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-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 19:49:27 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_led_controller_0_0_sim_netlist.vhdl
-- Design : ip_design_led_controller_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_led_controller_v1_0_S00_AXI is
port (
S_AXI_ARREADY : out STD_LOGIC;
S_AXI_AWREADY : out STD_LOGIC;
S_AXI_WREADY : out STD_LOGIC;
LEDs_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_bvalid : out STD_LOGIC;
s00_axi_arvalid : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_araddr : in STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_aresetn : in STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_rready : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_led_controller_v1_0_S00_AXI;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_led_controller_v1_0_S00_AXI is
signal \^leds_out\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_awready\ : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal aw_en_i_1_n_0 : STD_LOGIC;
signal aw_en_reg_n_0 : STD_LOGIC;
signal axi_araddr : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \axi_araddr[2]_i_1_n_0\ : STD_LOGIC;
signal \axi_araddr[3]_i_1_n_0\ : STD_LOGIC;
signal axi_arready_i_1_n_0 : STD_LOGIC;
signal \axi_awaddr[2]_i_1_n_0\ : STD_LOGIC;
signal \axi_awaddr[3]_i_1_n_0\ : STD_LOGIC;
signal axi_awready0 : STD_LOGIC;
signal axi_bvalid_i_1_n_0 : STD_LOGIC;
signal axi_rvalid_i_1_n_0 : STD_LOGIC;
signal axi_wready0 : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 1 downto 0 );
signal p_1_in : STD_LOGIC_VECTOR ( 31 downto 7 );
signal reg_data_out : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s00_axi_bvalid\ : STD_LOGIC;
signal \^s00_axi_rvalid\ : STD_LOGIC;
signal slv_reg0 : STD_LOGIC_VECTOR ( 31 downto 8 );
signal \slv_reg0[7]_i_1_n_0\ : STD_LOGIC;
signal slv_reg1 : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \slv_reg1[15]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg1[23]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg1[31]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg1[7]_i_1_n_0\ : STD_LOGIC;
signal slv_reg2 : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \slv_reg2[15]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg2[23]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg2[31]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg2[7]_i_1_n_0\ : STD_LOGIC;
signal slv_reg3 : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \slv_reg3[15]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg3[23]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg3[31]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg3[7]_i_1_n_0\ : STD_LOGIC;
signal \slv_reg_rden__0\ : STD_LOGIC;
signal \slv_reg_wren__0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axi_araddr[3]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of axi_arready_i_1 : label is "soft_lutpair1";
attribute SOFT_HLUTNM of axi_wready_i_1 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \slv_reg0[7]_i_3\ : label is "soft_lutpair0";
begin
LEDs_out(7 downto 0) <= \^leds_out\(7 downto 0);
S_AXI_ARREADY <= \^s_axi_arready\;
S_AXI_AWREADY <= \^s_axi_awready\;
S_AXI_WREADY <= \^s_axi_wready\;
s00_axi_bvalid <= \^s00_axi_bvalid\;
s00_axi_rvalid <= \^s00_axi_rvalid\;
aw_en_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"F7FFC4CCC4CCC4CC"
)
port map (
I0 => s00_axi_wvalid,
I1 => aw_en_reg_n_0,
I2 => \^s_axi_awready\,
I3 => s00_axi_awvalid,
I4 => s00_axi_bready,
I5 => \^s00_axi_bvalid\,
O => aw_en_i_1_n_0
);
aw_en_reg: unisim.vcomponents.FDSE
port map (
C => s00_axi_aclk,
CE => '1',
D => aw_en_i_1_n_0,
Q => aw_en_reg_n_0,
S => \slv_reg0[7]_i_1_n_0\
);
\axi_araddr[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s00_axi_araddr(0),
I1 => s00_axi_arvalid,
I2 => \^s_axi_arready\,
I3 => axi_araddr(2),
O => \axi_araddr[2]_i_1_n_0\
);
\axi_araddr[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => s00_axi_araddr(1),
I1 => s00_axi_arvalid,
I2 => \^s_axi_arready\,
I3 => axi_araddr(3),
O => \axi_araddr[3]_i_1_n_0\
);
\axi_araddr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => '1',
D => \axi_araddr[2]_i_1_n_0\,
Q => axi_araddr(2),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_araddr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => '1',
D => \axi_araddr[3]_i_1_n_0\,
Q => axi_araddr(3),
R => \slv_reg0[7]_i_1_n_0\
);
axi_arready_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s00_axi_arvalid,
I1 => \^s_axi_arready\,
O => axi_arready_i_1_n_0
);
axi_arready_reg: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => '1',
D => axi_arready_i_1_n_0,
Q => \^s_axi_arready\,
R => \slv_reg0[7]_i_1_n_0\
);
\axi_awaddr[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FBFFFFFF08000000"
)
port map (
I0 => s00_axi_awaddr(0),
I1 => s00_axi_awvalid,
I2 => \^s_axi_awready\,
I3 => aw_en_reg_n_0,
I4 => s00_axi_wvalid,
I5 => p_0_in(0),
O => \axi_awaddr[2]_i_1_n_0\
);
\axi_awaddr[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FBFFFFFF08000000"
)
port map (
I0 => s00_axi_awaddr(1),
I1 => s00_axi_awvalid,
I2 => \^s_axi_awready\,
I3 => aw_en_reg_n_0,
I4 => s00_axi_wvalid,
I5 => p_0_in(1),
O => \axi_awaddr[3]_i_1_n_0\
);
\axi_awaddr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => '1',
D => \axi_awaddr[2]_i_1_n_0\,
Q => p_0_in(0),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_awaddr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => '1',
D => \axi_awaddr[3]_i_1_n_0\,
Q => p_0_in(1),
R => \slv_reg0[7]_i_1_n_0\
);
axi_awready_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => s00_axi_awvalid,
I1 => \^s_axi_awready\,
I2 => aw_en_reg_n_0,
I3 => s00_axi_wvalid,
O => axi_awready0
);
axi_awready_reg: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => '1',
D => axi_awready0,
Q => \^s_axi_awready\,
R => \slv_reg0[7]_i_1_n_0\
);
axi_bvalid_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000FFFF80008000"
)
port map (
I0 => \^s_axi_wready\,
I1 => \^s_axi_awready\,
I2 => s00_axi_awvalid,
I3 => s00_axi_wvalid,
I4 => s00_axi_bready,
I5 => \^s00_axi_bvalid\,
O => axi_bvalid_i_1_n_0
);
axi_bvalid_reg: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => '1',
D => axi_bvalid_i_1_n_0,
Q => \^s00_axi_bvalid\,
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(0),
I1 => \^leds_out\(0),
I2 => slv_reg3(0),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(0),
O => reg_data_out(0)
);
\axi_rdata[10]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(10),
I1 => slv_reg0(10),
I2 => slv_reg3(10),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(10),
O => reg_data_out(10)
);
\axi_rdata[11]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(11),
I1 => slv_reg0(11),
I2 => slv_reg3(11),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(11),
O => reg_data_out(11)
);
\axi_rdata[12]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(12),
I1 => slv_reg0(12),
I2 => slv_reg3(12),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(12),
O => reg_data_out(12)
);
\axi_rdata[13]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(13),
I1 => slv_reg0(13),
I2 => slv_reg3(13),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(13),
O => reg_data_out(13)
);
\axi_rdata[14]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(14),
I1 => slv_reg0(14),
I2 => slv_reg3(14),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(14),
O => reg_data_out(14)
);
\axi_rdata[15]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(15),
I1 => slv_reg0(15),
I2 => slv_reg3(15),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(15),
O => reg_data_out(15)
);
\axi_rdata[16]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(16),
I1 => slv_reg0(16),
I2 => slv_reg3(16),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(16),
O => reg_data_out(16)
);
\axi_rdata[17]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(17),
I1 => slv_reg0(17),
I2 => slv_reg3(17),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(17),
O => reg_data_out(17)
);
\axi_rdata[18]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(18),
I1 => slv_reg0(18),
I2 => slv_reg3(18),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(18),
O => reg_data_out(18)
);
\axi_rdata[19]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(19),
I1 => slv_reg0(19),
I2 => slv_reg3(19),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(19),
O => reg_data_out(19)
);
\axi_rdata[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(1),
I1 => \^leds_out\(1),
I2 => slv_reg3(1),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(1),
O => reg_data_out(1)
);
\axi_rdata[20]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(20),
I1 => slv_reg0(20),
I2 => slv_reg3(20),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(20),
O => reg_data_out(20)
);
\axi_rdata[21]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(21),
I1 => slv_reg0(21),
I2 => slv_reg3(21),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(21),
O => reg_data_out(21)
);
\axi_rdata[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(22),
I1 => slv_reg0(22),
I2 => slv_reg3(22),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(22),
O => reg_data_out(22)
);
\axi_rdata[23]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(23),
I1 => slv_reg0(23),
I2 => slv_reg3(23),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(23),
O => reg_data_out(23)
);
\axi_rdata[24]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(24),
I1 => slv_reg0(24),
I2 => slv_reg3(24),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(24),
O => reg_data_out(24)
);
\axi_rdata[25]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(25),
I1 => slv_reg0(25),
I2 => slv_reg3(25),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(25),
O => reg_data_out(25)
);
\axi_rdata[26]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(26),
I1 => slv_reg0(26),
I2 => slv_reg3(26),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(26),
O => reg_data_out(26)
);
\axi_rdata[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(27),
I1 => slv_reg0(27),
I2 => slv_reg3(27),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(27),
O => reg_data_out(27)
);
\axi_rdata[28]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(28),
I1 => slv_reg0(28),
I2 => slv_reg3(28),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(28),
O => reg_data_out(28)
);
\axi_rdata[29]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(29),
I1 => slv_reg0(29),
I2 => slv_reg3(29),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(29),
O => reg_data_out(29)
);
\axi_rdata[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(2),
I1 => \^leds_out\(2),
I2 => slv_reg3(2),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(2),
O => reg_data_out(2)
);
\axi_rdata[30]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(30),
I1 => slv_reg0(30),
I2 => slv_reg3(30),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(30),
O => reg_data_out(30)
);
\axi_rdata[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(31),
I1 => slv_reg0(31),
I2 => slv_reg3(31),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(31),
O => reg_data_out(31)
);
\axi_rdata[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(3),
I1 => \^leds_out\(3),
I2 => slv_reg3(3),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(3),
O => reg_data_out(3)
);
\axi_rdata[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(4),
I1 => \^leds_out\(4),
I2 => slv_reg3(4),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(4),
O => reg_data_out(4)
);
\axi_rdata[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(5),
I1 => \^leds_out\(5),
I2 => slv_reg3(5),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(5),
O => reg_data_out(5)
);
\axi_rdata[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(6),
I1 => \^leds_out\(6),
I2 => slv_reg3(6),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(6),
O => reg_data_out(6)
);
\axi_rdata[7]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(7),
I1 => \^leds_out\(7),
I2 => slv_reg3(7),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(7),
O => reg_data_out(7)
);
\axi_rdata[8]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(8),
I1 => slv_reg0(8),
I2 => slv_reg3(8),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(8),
O => reg_data_out(8)
);
\axi_rdata[9]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0AAFFCCF0AA00CC"
)
port map (
I0 => slv_reg1(9),
I1 => slv_reg0(9),
I2 => slv_reg3(9),
I3 => axi_araddr(3),
I4 => axi_araddr(2),
I5 => slv_reg2(9),
O => reg_data_out(9)
);
\axi_rdata_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(0),
Q => s00_axi_rdata(0),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(10),
Q => s00_axi_rdata(10),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(11),
Q => s00_axi_rdata(11),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(12),
Q => s00_axi_rdata(12),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(13),
Q => s00_axi_rdata(13),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(14),
Q => s00_axi_rdata(14),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(15),
Q => s00_axi_rdata(15),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(16),
Q => s00_axi_rdata(16),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(17),
Q => s00_axi_rdata(17),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(18),
Q => s00_axi_rdata(18),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(19),
Q => s00_axi_rdata(19),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(1),
Q => s00_axi_rdata(1),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(20),
Q => s00_axi_rdata(20),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(21),
Q => s00_axi_rdata(21),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(22),
Q => s00_axi_rdata(22),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(23),
Q => s00_axi_rdata(23),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(24),
Q => s00_axi_rdata(24),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(25),
Q => s00_axi_rdata(25),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(26),
Q => s00_axi_rdata(26),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(27),
Q => s00_axi_rdata(27),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(28),
Q => s00_axi_rdata(28),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(29),
Q => s00_axi_rdata(29),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(2),
Q => s00_axi_rdata(2),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(30),
Q => s00_axi_rdata(30),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(31),
Q => s00_axi_rdata(31),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(3),
Q => s00_axi_rdata(3),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(4),
Q => s00_axi_rdata(4),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(5),
Q => s00_axi_rdata(5),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(6),
Q => s00_axi_rdata(6),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(7),
Q => s00_axi_rdata(7),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(8),
Q => s00_axi_rdata(8),
R => \slv_reg0[7]_i_1_n_0\
);
\axi_rdata_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg_rden__0\,
D => reg_data_out(9),
Q => s00_axi_rdata(9),
R => \slv_reg0[7]_i_1_n_0\
);
axi_rvalid_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"08F8"
)
port map (
I0 => \^s_axi_arready\,
I1 => s00_axi_arvalid,
I2 => \^s00_axi_rvalid\,
I3 => s00_axi_rready,
O => axi_rvalid_i_1_n_0
);
axi_rvalid_reg: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => '1',
D => axi_rvalid_i_1_n_0,
Q => \^s00_axi_rvalid\,
R => \slv_reg0[7]_i_1_n_0\
);
axi_wready_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"4000"
)
port map (
I0 => \^s_axi_wready\,
I1 => s00_axi_wvalid,
I2 => s00_axi_awvalid,
I3 => aw_en_reg_n_0,
O => axi_wready0
);
axi_wready_reg: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => '1',
D => axi_wready0,
Q => \^s_axi_wready\,
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0200"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => p_0_in(0),
I3 => s00_axi_wstrb(1),
O => p_1_in(15)
);
\slv_reg0[23]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0200"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => p_0_in(0),
I3 => s00_axi_wstrb(2),
O => p_1_in(23)
);
\slv_reg0[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0200"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => p_0_in(0),
I3 => s00_axi_wstrb(3),
O => p_1_in(31)
);
\slv_reg0[7]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s00_axi_aresetn,
O => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0[7]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0200"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => p_0_in(0),
I3 => s00_axi_wstrb(0),
O => p_1_in(7)
);
\slv_reg0[7]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \^s_axi_wready\,
I1 => \^s_axi_awready\,
I2 => s00_axi_awvalid,
I3 => s00_axi_wvalid,
O => \slv_reg_wren__0\
);
\slv_reg0_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(7),
D => s00_axi_wdata(0),
Q => \^leds_out\(0),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(15),
D => s00_axi_wdata(10),
Q => slv_reg0(10),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(15),
D => s00_axi_wdata(11),
Q => slv_reg0(11),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(15),
D => s00_axi_wdata(12),
Q => slv_reg0(12),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(15),
D => s00_axi_wdata(13),
Q => slv_reg0(13),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(15),
D => s00_axi_wdata(14),
Q => slv_reg0(14),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(15),
D => s00_axi_wdata(15),
Q => slv_reg0(15),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(23),
D => s00_axi_wdata(16),
Q => slv_reg0(16),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(23),
D => s00_axi_wdata(17),
Q => slv_reg0(17),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(23),
D => s00_axi_wdata(18),
Q => slv_reg0(18),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(23),
D => s00_axi_wdata(19),
Q => slv_reg0(19),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(7),
D => s00_axi_wdata(1),
Q => \^leds_out\(1),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(23),
D => s00_axi_wdata(20),
Q => slv_reg0(20),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(23),
D => s00_axi_wdata(21),
Q => slv_reg0(21),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(23),
D => s00_axi_wdata(22),
Q => slv_reg0(22),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(23),
D => s00_axi_wdata(23),
Q => slv_reg0(23),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(31),
D => s00_axi_wdata(24),
Q => slv_reg0(24),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(31),
D => s00_axi_wdata(25),
Q => slv_reg0(25),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(31),
D => s00_axi_wdata(26),
Q => slv_reg0(26),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(31),
D => s00_axi_wdata(27),
Q => slv_reg0(27),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(31),
D => s00_axi_wdata(28),
Q => slv_reg0(28),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(31),
D => s00_axi_wdata(29),
Q => slv_reg0(29),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(7),
D => s00_axi_wdata(2),
Q => \^leds_out\(2),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(31),
D => s00_axi_wdata(30),
Q => slv_reg0(30),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(31),
D => s00_axi_wdata(31),
Q => slv_reg0(31),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(7),
D => s00_axi_wdata(3),
Q => \^leds_out\(3),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(7),
D => s00_axi_wdata(4),
Q => \^leds_out\(4),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(7),
D => s00_axi_wdata(5),
Q => \^leds_out\(5),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(7),
D => s00_axi_wdata(6),
Q => \^leds_out\(6),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(7),
D => s00_axi_wdata(7),
Q => \^leds_out\(7),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(15),
D => s00_axi_wdata(8),
Q => slv_reg0(8),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg0_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => p_1_in(15),
D => s00_axi_wdata(9),
Q => slv_reg0(9),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => s00_axi_wstrb(1),
I3 => p_0_in(0),
O => \slv_reg1[15]_i_1_n_0\
);
\slv_reg1[23]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => s00_axi_wstrb(2),
I3 => p_0_in(0),
O => \slv_reg1[23]_i_1_n_0\
);
\slv_reg1[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => s00_axi_wstrb(3),
I3 => p_0_in(0),
O => \slv_reg1[31]_i_1_n_0\
);
\slv_reg1[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => s00_axi_wstrb(0),
I3 => p_0_in(0),
O => \slv_reg1[7]_i_1_n_0\
);
\slv_reg1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[7]_i_1_n_0\,
D => s00_axi_wdata(0),
Q => slv_reg1(0),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[15]_i_1_n_0\,
D => s00_axi_wdata(10),
Q => slv_reg1(10),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[15]_i_1_n_0\,
D => s00_axi_wdata(11),
Q => slv_reg1(11),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[15]_i_1_n_0\,
D => s00_axi_wdata(12),
Q => slv_reg1(12),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[15]_i_1_n_0\,
D => s00_axi_wdata(13),
Q => slv_reg1(13),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[15]_i_1_n_0\,
D => s00_axi_wdata(14),
Q => slv_reg1(14),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[15]_i_1_n_0\,
D => s00_axi_wdata(15),
Q => slv_reg1(15),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[23]_i_1_n_0\,
D => s00_axi_wdata(16),
Q => slv_reg1(16),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[23]_i_1_n_0\,
D => s00_axi_wdata(17),
Q => slv_reg1(17),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[23]_i_1_n_0\,
D => s00_axi_wdata(18),
Q => slv_reg1(18),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[23]_i_1_n_0\,
D => s00_axi_wdata(19),
Q => slv_reg1(19),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[7]_i_1_n_0\,
D => s00_axi_wdata(1),
Q => slv_reg1(1),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[23]_i_1_n_0\,
D => s00_axi_wdata(20),
Q => slv_reg1(20),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[23]_i_1_n_0\,
D => s00_axi_wdata(21),
Q => slv_reg1(21),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[23]_i_1_n_0\,
D => s00_axi_wdata(22),
Q => slv_reg1(22),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[23]_i_1_n_0\,
D => s00_axi_wdata(23),
Q => slv_reg1(23),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[31]_i_1_n_0\,
D => s00_axi_wdata(24),
Q => slv_reg1(24),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[31]_i_1_n_0\,
D => s00_axi_wdata(25),
Q => slv_reg1(25),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[31]_i_1_n_0\,
D => s00_axi_wdata(26),
Q => slv_reg1(26),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[31]_i_1_n_0\,
D => s00_axi_wdata(27),
Q => slv_reg1(27),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[31]_i_1_n_0\,
D => s00_axi_wdata(28),
Q => slv_reg1(28),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[31]_i_1_n_0\,
D => s00_axi_wdata(29),
Q => slv_reg1(29),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[7]_i_1_n_0\,
D => s00_axi_wdata(2),
Q => slv_reg1(2),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[31]_i_1_n_0\,
D => s00_axi_wdata(30),
Q => slv_reg1(30),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[31]_i_1_n_0\,
D => s00_axi_wdata(31),
Q => slv_reg1(31),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[7]_i_1_n_0\,
D => s00_axi_wdata(3),
Q => slv_reg1(3),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[7]_i_1_n_0\,
D => s00_axi_wdata(4),
Q => slv_reg1(4),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[7]_i_1_n_0\,
D => s00_axi_wdata(5),
Q => slv_reg1(5),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[7]_i_1_n_0\,
D => s00_axi_wdata(6),
Q => slv_reg1(6),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[7]_i_1_n_0\,
D => s00_axi_wdata(7),
Q => slv_reg1(7),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[15]_i_1_n_0\,
D => s00_axi_wdata(8),
Q => slv_reg1(8),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg1_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg1[15]_i_1_n_0\,
D => s00_axi_wdata(9),
Q => slv_reg1(9),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => s00_axi_wstrb(1),
I3 => p_0_in(0),
O => \slv_reg2[15]_i_1_n_0\
);
\slv_reg2[23]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => s00_axi_wstrb(2),
I3 => p_0_in(0),
O => \slv_reg2[23]_i_1_n_0\
);
\slv_reg2[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => s00_axi_wstrb(3),
I3 => p_0_in(0),
O => \slv_reg2[31]_i_1_n_0\
);
\slv_reg2[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => p_0_in(1),
I2 => s00_axi_wstrb(0),
I3 => p_0_in(0),
O => \slv_reg2[7]_i_1_n_0\
);
\slv_reg2_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[7]_i_1_n_0\,
D => s00_axi_wdata(0),
Q => slv_reg2(0),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[15]_i_1_n_0\,
D => s00_axi_wdata(10),
Q => slv_reg2(10),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[15]_i_1_n_0\,
D => s00_axi_wdata(11),
Q => slv_reg2(11),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[15]_i_1_n_0\,
D => s00_axi_wdata(12),
Q => slv_reg2(12),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[15]_i_1_n_0\,
D => s00_axi_wdata(13),
Q => slv_reg2(13),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[15]_i_1_n_0\,
D => s00_axi_wdata(14),
Q => slv_reg2(14),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[15]_i_1_n_0\,
D => s00_axi_wdata(15),
Q => slv_reg2(15),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[23]_i_1_n_0\,
D => s00_axi_wdata(16),
Q => slv_reg2(16),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[23]_i_1_n_0\,
D => s00_axi_wdata(17),
Q => slv_reg2(17),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[23]_i_1_n_0\,
D => s00_axi_wdata(18),
Q => slv_reg2(18),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[23]_i_1_n_0\,
D => s00_axi_wdata(19),
Q => slv_reg2(19),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[7]_i_1_n_0\,
D => s00_axi_wdata(1),
Q => slv_reg2(1),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[23]_i_1_n_0\,
D => s00_axi_wdata(20),
Q => slv_reg2(20),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[23]_i_1_n_0\,
D => s00_axi_wdata(21),
Q => slv_reg2(21),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[23]_i_1_n_0\,
D => s00_axi_wdata(22),
Q => slv_reg2(22),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[23]_i_1_n_0\,
D => s00_axi_wdata(23),
Q => slv_reg2(23),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[31]_i_1_n_0\,
D => s00_axi_wdata(24),
Q => slv_reg2(24),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[31]_i_1_n_0\,
D => s00_axi_wdata(25),
Q => slv_reg2(25),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[31]_i_1_n_0\,
D => s00_axi_wdata(26),
Q => slv_reg2(26),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[31]_i_1_n_0\,
D => s00_axi_wdata(27),
Q => slv_reg2(27),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[31]_i_1_n_0\,
D => s00_axi_wdata(28),
Q => slv_reg2(28),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[31]_i_1_n_0\,
D => s00_axi_wdata(29),
Q => slv_reg2(29),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[7]_i_1_n_0\,
D => s00_axi_wdata(2),
Q => slv_reg2(2),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[31]_i_1_n_0\,
D => s00_axi_wdata(30),
Q => slv_reg2(30),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[31]_i_1_n_0\,
D => s00_axi_wdata(31),
Q => slv_reg2(31),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[7]_i_1_n_0\,
D => s00_axi_wdata(3),
Q => slv_reg2(3),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[7]_i_1_n_0\,
D => s00_axi_wdata(4),
Q => slv_reg2(4),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[7]_i_1_n_0\,
D => s00_axi_wdata(5),
Q => slv_reg2(5),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[7]_i_1_n_0\,
D => s00_axi_wdata(6),
Q => slv_reg2(6),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[7]_i_1_n_0\,
D => s00_axi_wdata(7),
Q => slv_reg2(7),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[15]_i_1_n_0\,
D => s00_axi_wdata(8),
Q => slv_reg2(8),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg2_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg2[15]_i_1_n_0\,
D => s00_axi_wdata(9),
Q => slv_reg2(9),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3[15]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => s00_axi_wstrb(1),
I2 => p_0_in(0),
I3 => p_0_in(1),
O => \slv_reg3[15]_i_1_n_0\
);
\slv_reg3[23]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => s00_axi_wstrb(2),
I2 => p_0_in(0),
I3 => p_0_in(1),
O => \slv_reg3[23]_i_1_n_0\
);
\slv_reg3[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => s00_axi_wstrb(3),
I2 => p_0_in(0),
I3 => p_0_in(1),
O => \slv_reg3[31]_i_1_n_0\
);
\slv_reg3[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"8000"
)
port map (
I0 => \slv_reg_wren__0\,
I1 => s00_axi_wstrb(0),
I2 => p_0_in(0),
I3 => p_0_in(1),
O => \slv_reg3[7]_i_1_n_0\
);
\slv_reg3_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[7]_i_1_n_0\,
D => s00_axi_wdata(0),
Q => slv_reg3(0),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[15]_i_1_n_0\,
D => s00_axi_wdata(10),
Q => slv_reg3(10),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[15]_i_1_n_0\,
D => s00_axi_wdata(11),
Q => slv_reg3(11),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[12]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[15]_i_1_n_0\,
D => s00_axi_wdata(12),
Q => slv_reg3(12),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[13]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[15]_i_1_n_0\,
D => s00_axi_wdata(13),
Q => slv_reg3(13),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[14]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[15]_i_1_n_0\,
D => s00_axi_wdata(14),
Q => slv_reg3(14),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[15]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[15]_i_1_n_0\,
D => s00_axi_wdata(15),
Q => slv_reg3(15),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[16]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[23]_i_1_n_0\,
D => s00_axi_wdata(16),
Q => slv_reg3(16),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[17]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[23]_i_1_n_0\,
D => s00_axi_wdata(17),
Q => slv_reg3(17),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[18]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[23]_i_1_n_0\,
D => s00_axi_wdata(18),
Q => slv_reg3(18),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[19]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[23]_i_1_n_0\,
D => s00_axi_wdata(19),
Q => slv_reg3(19),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[7]_i_1_n_0\,
D => s00_axi_wdata(1),
Q => slv_reg3(1),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[23]_i_1_n_0\,
D => s00_axi_wdata(20),
Q => slv_reg3(20),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[23]_i_1_n_0\,
D => s00_axi_wdata(21),
Q => slv_reg3(21),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[23]_i_1_n_0\,
D => s00_axi_wdata(22),
Q => slv_reg3(22),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[23]_i_1_n_0\,
D => s00_axi_wdata(23),
Q => slv_reg3(23),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[31]_i_1_n_0\,
D => s00_axi_wdata(24),
Q => slv_reg3(24),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[31]_i_1_n_0\,
D => s00_axi_wdata(25),
Q => slv_reg3(25),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[31]_i_1_n_0\,
D => s00_axi_wdata(26),
Q => slv_reg3(26),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[31]_i_1_n_0\,
D => s00_axi_wdata(27),
Q => slv_reg3(27),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[31]_i_1_n_0\,
D => s00_axi_wdata(28),
Q => slv_reg3(28),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[31]_i_1_n_0\,
D => s00_axi_wdata(29),
Q => slv_reg3(29),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[7]_i_1_n_0\,
D => s00_axi_wdata(2),
Q => slv_reg3(2),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[31]_i_1_n_0\,
D => s00_axi_wdata(30),
Q => slv_reg3(30),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[31]_i_1_n_0\,
D => s00_axi_wdata(31),
Q => slv_reg3(31),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[7]_i_1_n_0\,
D => s00_axi_wdata(3),
Q => slv_reg3(3),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[7]_i_1_n_0\,
D => s00_axi_wdata(4),
Q => slv_reg3(4),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[7]_i_1_n_0\,
D => s00_axi_wdata(5),
Q => slv_reg3(5),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[7]_i_1_n_0\,
D => s00_axi_wdata(6),
Q => slv_reg3(6),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[7]_i_1_n_0\,
D => s00_axi_wdata(7),
Q => slv_reg3(7),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[15]_i_1_n_0\,
D => s00_axi_wdata(8),
Q => slv_reg3(8),
R => \slv_reg0[7]_i_1_n_0\
);
\slv_reg3_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s00_axi_aclk,
CE => \slv_reg3[15]_i_1_n_0\,
D => s00_axi_wdata(9),
Q => slv_reg3(9),
R => \slv_reg0[7]_i_1_n_0\
);
slv_reg_rden: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \^s00_axi_rvalid\,
I1 => s00_axi_arvalid,
I2 => \^s_axi_arready\,
O => \slv_reg_rden__0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_led_controller_v1_0 is
port (
S_AXI_ARREADY : out STD_LOGIC;
S_AXI_AWREADY : out STD_LOGIC;
S_AXI_WREADY : out STD_LOGIC;
LEDs_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_bvalid : out STD_LOGIC;
s00_axi_arvalid : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_araddr : in STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_aresetn : in STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_rready : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_led_controller_v1_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_led_controller_v1_0 is
begin
led_controller_v1_0_S00_AXI_inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_led_controller_v1_0_S00_AXI
port map (
LEDs_out(7 downto 0) => LEDs_out(7 downto 0),
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_AWREADY => S_AXI_AWREADY,
S_AXI_WREADY => S_AXI_WREADY,
s00_axi_aclk => s00_axi_aclk,
s00_axi_araddr(1 downto 0) => s00_axi_araddr(1 downto 0),
s00_axi_aresetn => s00_axi_aresetn,
s00_axi_arvalid => s00_axi_arvalid,
s00_axi_awaddr(1 downto 0) => s00_axi_awaddr(1 downto 0),
s00_axi_awvalid => s00_axi_awvalid,
s00_axi_bready => s00_axi_bready,
s00_axi_bvalid => s00_axi_bvalid,
s00_axi_rdata(31 downto 0) => s00_axi_rdata(31 downto 0),
s00_axi_rready => s00_axi_rready,
s00_axi_rvalid => s00_axi_rvalid,
s00_axi_wdata(31 downto 0) => s00_axi_wdata(31 downto 0),
s00_axi_wstrb(3 downto 0) => s00_axi_wstrb(3 downto 0),
s00_axi_wvalid => s00_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
LEDs_out : out STD_LOGIC_VECTOR ( 7 downto 0 );
s00_axi_awaddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_awvalid : in STD_LOGIC;
s00_axi_awready : out STD_LOGIC;
s00_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_wvalid : in STD_LOGIC;
s00_axi_wready : out STD_LOGIC;
s00_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_bvalid : out STD_LOGIC;
s00_axi_bready : in STD_LOGIC;
s00_axi_araddr : in STD_LOGIC_VECTOR ( 3 downto 0 );
s00_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s00_axi_arvalid : in STD_LOGIC;
s00_axi_arready : out STD_LOGIC;
s00_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s00_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s00_axi_rvalid : out STD_LOGIC;
s00_axi_rready : in STD_LOGIC;
s00_axi_aclk : in STD_LOGIC;
s00_axi_aresetn : in STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "ip_design_led_controller_0_0,led_controller_v1_0,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "led_controller_v1_0,Vivado 2017.3";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal \<const0>\ : STD_LOGIC;
attribute X_INTERFACE_INFO : string;
attribute X_INTERFACE_INFO of s00_axi_aclk : signal is "xilinx.com:signal:clock:1.0 S00_AXI_CLK CLK";
attribute X_INTERFACE_PARAMETER : string;
attribute X_INTERFACE_PARAMETER of s00_axi_aclk : signal is "XIL_INTERFACENAME S00_AXI_CLK, ASSOCIATED_BUSIF S00_AXI, ASSOCIATED_RESET s00_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0";
attribute X_INTERFACE_INFO of s00_axi_aresetn : signal is "xilinx.com:signal:reset:1.0 S00_AXI_RST RST";
attribute X_INTERFACE_PARAMETER of s00_axi_aresetn : signal is "XIL_INTERFACENAME S00_AXI_RST, POLARITY ACTIVE_LOW";
attribute X_INTERFACE_INFO of s00_axi_arready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY";
attribute X_INTERFACE_INFO of s00_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID";
attribute X_INTERFACE_INFO of s00_axi_awready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY";
attribute X_INTERFACE_INFO of s00_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID";
attribute X_INTERFACE_INFO of s00_axi_bready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI BREADY";
attribute X_INTERFACE_INFO of s00_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI BVALID";
attribute X_INTERFACE_INFO of s00_axi_rready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RREADY";
attribute X_INTERFACE_PARAMETER of s00_axi_rready : signal is "XIL_INTERFACENAME S00_AXI, WIZ_DATA_WIDTH 32, WIZ_NUM_REG 4, SUPPORTS_NARROW_BURST 0, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 4, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
attribute X_INTERFACE_INFO of s00_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RVALID";
attribute X_INTERFACE_INFO of s00_axi_wready : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WREADY";
attribute X_INTERFACE_INFO of s00_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WVALID";
attribute X_INTERFACE_INFO of s00_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR";
attribute X_INTERFACE_INFO of s00_axi_arprot : signal is "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT";
attribute X_INTERFACE_INFO of s00_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR";
attribute X_INTERFACE_INFO of s00_axi_awprot : signal is "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT";
attribute X_INTERFACE_INFO of s00_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 S00_AXI BRESP";
attribute X_INTERFACE_INFO of s00_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RDATA";
attribute X_INTERFACE_INFO of s00_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 S00_AXI RRESP";
attribute X_INTERFACE_INFO of s00_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WDATA";
attribute X_INTERFACE_INFO of s00_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB";
begin
s00_axi_bresp(1) <= \<const0>\;
s00_axi_bresp(0) <= \<const0>\;
s00_axi_rresp(1) <= \<const0>\;
s00_axi_rresp(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_led_controller_v1_0
port map (
LEDs_out(7 downto 0) => LEDs_out(7 downto 0),
S_AXI_ARREADY => s00_axi_arready,
S_AXI_AWREADY => s00_axi_awready,
S_AXI_WREADY => s00_axi_wready,
s00_axi_aclk => s00_axi_aclk,
s00_axi_araddr(1 downto 0) => s00_axi_araddr(3 downto 2),
s00_axi_aresetn => s00_axi_aresetn,
s00_axi_arvalid => s00_axi_arvalid,
s00_axi_awaddr(1 downto 0) => s00_axi_awaddr(3 downto 2),
s00_axi_awvalid => s00_axi_awvalid,
s00_axi_bready => s00_axi_bready,
s00_axi_bvalid => s00_axi_bvalid,
s00_axi_rdata(31 downto 0) => s00_axi_rdata(31 downto 0),
s00_axi_rready => s00_axi_rready,
s00_axi_rvalid => s00_axi_rvalid,
s00_axi_wdata(31 downto 0) => s00_axi_wdata(31 downto 0),
s00_axi_wstrb(3 downto 0) => s00_axi_wstrb(3 downto 0),
s00_axi_wvalid => s00_axi_wvalid
);
end STRUCTURE;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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NrL9kw+eKQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 26688)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 26688)
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|
`protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_block
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`protect end_protected
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
ARCHITECTURE rtl OF subunit0 IS
BEGIN
a_ready <= b_ready;
b_data <= a_data;
b_last <= a_last;
b_strb <= a_strb;
b_valid <= a_valid;
END ARCHITECTURE rtl; |
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_delay is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 0;
BITPATTERN : string := "00000001";
WIDTH : positive := 8
);
port (
input : in std_logic_vector(width-1 downto 0) := (others=>'0');
clock : in std_logic := '0';
sclr : in std_logic := '0';
aclr : in std_logic := '0';
output : out std_logic_vector(width-1 downto 0);
ena : in std_logic := '0'
);
end entity alt_dspbuilder_delay;
architecture rtl of alt_dspbuilder_delay is
component alt_dspbuilder_delay_GNUECIBFDH is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 1;
BITPATTERN : string := "0";
WIDTH : positive := 1
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
ena : in std_logic := '0';
input : in std_logic_vector(1-1 downto 0) := (others=>'0');
output : out std_logic_vector(1-1 downto 0);
sclr : in std_logic := '0'
);
end component alt_dspbuilder_delay_GNUECIBFDH;
component alt_dspbuilder_delay_GNVTJPHWYT is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 1;
BITPATTERN : string := "01111111";
WIDTH : positive := 8
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
ena : in std_logic := '0';
input : in std_logic_vector(8-1 downto 0) := (others=>'0');
output : out std_logic_vector(8-1 downto 0);
sclr : in std_logic := '0'
);
end component alt_dspbuilder_delay_GNVTJPHWYT;
component alt_dspbuilder_delay_GNHYCSAEGT is
generic (
CLOCKPHASE : string := "1";
DELAY : positive := 1;
USE_INIT : natural := 0;
BITPATTERN : string := "0";
WIDTH : positive := 1
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
ena : in std_logic := '0';
input : in std_logic_vector(1-1 downto 0) := (others=>'0');
output : out std_logic_vector(1-1 downto 0);
sclr : in std_logic := '0'
);
end component alt_dspbuilder_delay_GNHYCSAEGT;
begin
alt_dspbuilder_delay_GNUECIBFDH_0: if ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 1) and (BITPATTERN = "0") and (WIDTH = 1)) generate
inst_alt_dspbuilder_delay_GNUECIBFDH_0: alt_dspbuilder_delay_GNUECIBFDH
generic map(CLOCKPHASE => "1", DELAY => 1, USE_INIT => 1, BITPATTERN => "0", WIDTH => 1)
port map(aclr => aclr, clock => clock, ena => ena, input => input, output => output, sclr => sclr);
end generate;
alt_dspbuilder_delay_GNVTJPHWYT_1: if ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 1) and (BITPATTERN = "01111111") and (WIDTH = 8)) generate
inst_alt_dspbuilder_delay_GNVTJPHWYT_1: alt_dspbuilder_delay_GNVTJPHWYT
generic map(CLOCKPHASE => "1", DELAY => 1, USE_INIT => 1, BITPATTERN => "01111111", WIDTH => 8)
port map(aclr => aclr, clock => clock, ena => ena, input => input, output => output, sclr => sclr);
end generate;
alt_dspbuilder_delay_GNHYCSAEGT_2: if ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 0) and (BITPATTERN = "0") and (WIDTH = 1)) generate
inst_alt_dspbuilder_delay_GNHYCSAEGT_2: alt_dspbuilder_delay_GNHYCSAEGT
generic map(CLOCKPHASE => "1", DELAY => 1, USE_INIT => 0, BITPATTERN => "0", WIDTH => 1)
port map(aclr => aclr, clock => clock, ena => ena, input => input, output => output, sclr => sclr);
end generate;
assert not (((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 1) and (BITPATTERN = "0") and (WIDTH = 1)) or ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 1) and (BITPATTERN = "01111111") and (WIDTH = 8)) or ((CLOCKPHASE = "1") and (DELAY = 1) and (USE_INIT = 0) and (BITPATTERN = "0") and (WIDTH = 1)))
report "Please run generate again" severity error;
end architecture rtl;
|
entity real1 is
end entity;
architecture test of real1 is
begin
process is
variable r : real;
begin
assert r = real'left;
r := 1.0;
r := r + 1.4;
assert r > 2.0;
assert r < 3.0;
assert r >= real'low;
assert r <= real'high;
assert r /= 5.0;
r := 2.0;
r := r * 3.0;
assert r > 5.99999;
assert r < 6.00001;
assert integer(r) = 6;
r := real(5);
report real'image(r);
report real'image(-5.262e2);
report real'image(1.23456);
report real'image(2.0 ** (-1));
report real'image(real'low);
report real'image(real'high);
wait;
end process;
end architecture;
|
entity real1 is
end entity;
architecture test of real1 is
begin
process is
variable r : real;
begin
assert r = real'left;
r := 1.0;
r := r + 1.4;
assert r > 2.0;
assert r < 3.0;
assert r >= real'low;
assert r <= real'high;
assert r /= 5.0;
r := 2.0;
r := r * 3.0;
assert r > 5.99999;
assert r < 6.00001;
assert integer(r) = 6;
r := real(5);
report real'image(r);
report real'image(-5.262e2);
report real'image(1.23456);
report real'image(2.0 ** (-1));
report real'image(real'low);
report real'image(real'high);
wait;
end process;
end architecture;
|
entity real1 is
end entity;
architecture test of real1 is
begin
process is
variable r : real;
begin
assert r = real'left;
r := 1.0;
r := r + 1.4;
assert r > 2.0;
assert r < 3.0;
assert r >= real'low;
assert r <= real'high;
assert r /= 5.0;
r := 2.0;
r := r * 3.0;
assert r > 5.99999;
assert r < 6.00001;
assert integer(r) = 6;
r := real(5);
report real'image(r);
report real'image(-5.262e2);
report real'image(1.23456);
report real'image(2.0 ** (-1));
report real'image(real'low);
report real'image(real'high);
wait;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity fluxo_de_dados_transmissao is
port(dado_serial : in std_logic;
enable_transmissao : in std_logic;
TD : out std_logic);
end fluxo_de_dados_transmissao;
architecture fluxo_de_dados_transmissao_Arch of fluxo_de_dados_transmissao is
begin
process (dado_serial, enable_transmissao)
begin
TD <= dado_serial and enable_transmissao;
end process;
end fluxo_de_dados_transmissao_Arch; |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:43:12 12/18/2013
-- Design Name:
-- Module Name: /home/nakayama/Desktop/583final/BO_Tests/Raster_Test.vhd
-- Project Name: BO_Tests
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: BreakRaster
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Raster_Test IS
END Raster_Test;
ARCHITECTURE behavior OF Raster_Test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT BreakRaster
PORT(
x_pos : IN std_logic_vector(11 downto 0);
y_pos : IN std_logic_vector(11 downto 0);
paddle_x : IN std_logic_vector(11 downto 0);
ball_x : IN std_logic_vector(11 downto 0);
ball_y : IN std_logic_vector(11 downto 0);
bricks : IN std_logic_vector(127 downto 0);
score : IN std_logic_vector(11 downto 0);
lives : IN std_logic_vector(3 downto 0);
draw_mode : IN std_logic_vector(3 downto 0);
R : OUT std_logic_vector(3 downto 0);
G : OUT std_logic_vector(3 downto 0);
B : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal x_pos : std_logic_vector(11 downto 0) := (others => '0');
signal y_pos : std_logic_vector(11 downto 0) := (others => '0');
signal paddle_x : std_logic_vector(11 downto 0) := (others => '0');
signal ball_x : std_logic_vector(11 downto 0) := (others => '0');
signal ball_y : std_logic_vector(11 downto 0) := (others => '0');
signal bricks : std_logic_vector(127 downto 0) := (others => '0');
signal score : std_logic_vector(11 downto 0) := (others => '0');
signal lives : std_logic_vector(3 downto 0) := (others => '0');
signal draw_mode : std_logic_vector(3 downto 0) := (others => '0');
--Outputs
signal R : std_logic_vector(3 downto 0);
signal G : std_logic_vector(3 downto 0);
signal B : std_logic_vector(3 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
constant clk_period : time := 40 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: BreakRaster PORT MAP (
x_pos => x_pos,
y_pos => y_pos,
paddle_x => paddle_x,
ball_x => ball_x,
ball_y => ball_y,
bricks => bricks,
score => score,
lives => lives,
draw_mode => draw_mode,
R => R,
G => G,
B => B
);
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
x_pos <= x"000";
y_pos <= x"000";
paddle_x <= x"0FF";
ball_x <= x"07F";
ball_y <= x"0FF";
bricks <= x"00000FFFFFFFFFFFFFFFFFFFFFFFFF0F";
score <= x"000";
lives <= x"0";
draw_mode <= x"1";
wait for clk_period;
x_pos <= x"010";
y_pos <= x"000";
wait for clk_period;
x_pos <= x"020";
y_pos <= x"040";
wait for clk_period;
x_pos <= x"020";
y_pos <= x"060";
wait for clk_period;
x_pos <= x"020";
y_pos <= x"074";
wait for clk_period;
x_pos <= x"020";
y_pos <= x"07C";
wait for clk_period;
x_pos <= x"020";
y_pos <= x"084";
wait for clk_period;
x_pos <= x"020";
y_pos <= x"08C";
wait for clk_period;
x_pos <= x"020";
y_pos <= x"094";
wait for clk_period;
x_pos <= x"020";
y_pos <= x"09C";
wait for clk_period;
x_pos <= x"060";
y_pos <= x"074";
wait for clk_period;
x_pos <= x"102";
y_pos <= x"1C3";
wait for clk_period;
x_pos <= x"080";
y_pos <= x"101";
-- insert stimulus here
wait;
end process;
END;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity bug is
port(index : in integer range 0 to 1);
end bug;
architecture behav of bug is
type foobar is record
foo : std_logic;
bar : std_logic_vector(1 downto 0);
end record;
-- Changing the order works:
--type foobar is record
-- bar : std_logic_vector(1 downto 0);
-- foo : std_logic;
--end record;
type foobar_array is array (0 to 1) of foobar;
signal s_foobar : foobar_array;
begin
s_foobar(index).bar(0) <= '0';
end architecture;
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity keyb_nov is
port(
clock: in std_logic;
input: in std_logic_vector(6 downto 0);
output: out std_logic_vector(1 downto 0)
);
end keyb_nov;
architecture behaviour of keyb_nov is
constant st0: std_logic_vector(4 downto 0) := "00000";
constant st1: std_logic_vector(4 downto 0) := "00100";
constant st2: std_logic_vector(4 downto 0) := "01100";
constant st3: std_logic_vector(4 downto 0) := "00001";
constant st4: std_logic_vector(4 downto 0) := "00101";
constant st5: std_logic_vector(4 downto 0) := "01101";
constant st6: std_logic_vector(4 downto 0) := "00111";
constant st7: std_logic_vector(4 downto 0) := "00110";
constant st8: std_logic_vector(4 downto 0) := "01110";
constant st9: std_logic_vector(4 downto 0) := "00011";
constant st10: std_logic_vector(4 downto 0) := "00010";
constant st11: std_logic_vector(4 downto 0) := "01000";
constant st12: std_logic_vector(4 downto 0) := "01001";
constant st13: std_logic_vector(4 downto 0) := "01111";
constant st14: std_logic_vector(4 downto 0) := "01010";
constant st15: std_logic_vector(4 downto 0) := "10101";
constant st16: std_logic_vector(4 downto 0) := "01011";
constant st17: std_logic_vector(4 downto 0) := "11010";
constant st18: std_logic_vector(4 downto 0) := "10100";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "--";
case current_state is
when st0 =>
if std_match(input, "---0000") then next_state <= st1; output <= "1-";
elsif std_match(input, "---0100") then next_state <= st2; output <= "1-";
elsif std_match(input, "---0010") then next_state <= st2; output <= "1-";
elsif std_match(input, "---0001") then next_state <= st2; output <= "1-";
elsif std_match(input, "---1100") then next_state <= st3; output <= "1-";
elsif std_match(input, "---1000") then next_state <= st3; output <= "1-";
elsif std_match(input, "---011-") then next_state <= st0; output <= "-0";
elsif std_match(input, "---01-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "---101-") then next_state <= st0; output <= "-0";
elsif std_match(input, "---10-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "---111-") then next_state <= st0; output <= "-0";
elsif std_match(input, "---11-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st1 =>
if std_match(input, "0000000") then next_state <= st4; output <= "1-";
elsif std_match(input, "1000000") then next_state <= st5; output <= "0-";
elsif std_match(input, "0100000") then next_state <= st5; output <= "0-";
elsif std_match(input, "0010000") then next_state <= st5; output <= "0-";
elsif std_match(input, "0001000") then next_state <= st5; output <= "0-";
elsif std_match(input, "0000100") then next_state <= st5; output <= "0-";
elsif std_match(input, "0000010") then next_state <= st5; output <= "0-";
elsif std_match(input, "0000001") then next_state <= st5; output <= "0-";
elsif std_match(input, "11-----") then next_state <= st0; output <= "-0";
elsif std_match(input, "1-1----") then next_state <= st0; output <= "-0";
elsif std_match(input, "1--1---") then next_state <= st0; output <= "-0";
elsif std_match(input, "1---1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "1----1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "1-----1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-11----") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1-1---") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1--1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1---1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1----1") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1-1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1--1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1---1") then next_state <= st0; output <= "-0";
elsif std_match(input, "---11--") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1-1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1--1") then next_state <= st0; output <= "-0";
elsif std_match(input, "----11-") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st2 =>
if std_match(input, "0000000") then next_state <= st5; output <= "--";
elsif std_match(input, "1------") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1----") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1---") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "------1") then next_state <= st0; output <= "-0";
end if;
when st3 =>
if std_match(input, "0000000") then next_state <= st6; output <= "1-";
elsif std_match(input, "0011000") then next_state <= st5; output <= "0-";
elsif std_match(input, "0000100") then next_state <= st5; output <= "0-";
elsif std_match(input, "0000010") then next_state <= st5; output <= "0-";
elsif std_match(input, "0000001") then next_state <= st5; output <= "0-";
elsif std_match(input, "1------") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "-0";
elsif std_match(input, "--01---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--10---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--111--") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11-1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11--1") then next_state <= st0; output <= "-0";
elsif std_match(input, "----11-") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st4 =>
if std_match(input, "-000000") then next_state <= st7; output <= "1-";
elsif std_match(input, "-100000") then next_state <= st8; output <= "0-";
elsif std_match(input, "-010000") then next_state <= st8; output <= "0-";
elsif std_match(input, "-001000") then next_state <= st8; output <= "0-";
elsif std_match(input, "-000100") then next_state <= st8; output <= "0-";
elsif std_match(input, "-000010") then next_state <= st8; output <= "0-";
elsif std_match(input, "-000001") then next_state <= st8; output <= "0-";
elsif std_match(input, "-11----") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1-1---") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1--1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1---1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "-1----1") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1-1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1--1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1---1") then next_state <= st0; output <= "-0";
elsif std_match(input, "---11--") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1-1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1--1") then next_state <= st0; output <= "-0";
elsif std_match(input, "----11-") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st5 =>
if std_match(input, "-000000") then next_state <= st8; output <= "0-";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1----") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1---") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "------1") then next_state <= st0; output <= "-0";
end if;
when st6 =>
if std_match(input, "-011000") then next_state <= st8; output <= "0-";
elsif std_match(input, "-000100") then next_state <= st8; output <= "0-";
elsif std_match(input, "-000010") then next_state <= st8; output <= "0-";
elsif std_match(input, "-000001") then next_state <= st8; output <= "0-";
elsif std_match(input, "-000000") then next_state <= st9; output <= "1-";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "-0";
elsif std_match(input, "--01---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--10---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--111--") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11-1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11--1") then next_state <= st0; output <= "-0";
elsif std_match(input, "----11-") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st7 =>
if std_match(input, "--00000") then next_state <= st10; output <= "1-";
elsif std_match(input, "--10000") then next_state <= st11; output <= "0-";
elsif std_match(input, "--01000") then next_state <= st11; output <= "0-";
elsif std_match(input, "--00100") then next_state <= st11; output <= "0-";
elsif std_match(input, "--00010") then next_state <= st11; output <= "0-";
elsif std_match(input, "--00001") then next_state <= st11; output <= "0-";
elsif std_match(input, "--11---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1-1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1--1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "--1---1") then next_state <= st0; output <= "-0";
elsif std_match(input, "---11--") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1-1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1--1") then next_state <= st0; output <= "-0";
elsif std_match(input, "----11-") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st8 =>
if std_match(input, "--00000") then next_state <= st11; output <= "0-";
elsif std_match(input, "--1----") then next_state <= st0; output <= "-0";
elsif std_match(input, "---1---") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "------1") then next_state <= st0; output <= "-0";
end if;
when st9 =>
if std_match(input, "--00000") then next_state <= st12; output <= "--";
elsif std_match(input, "--11000") then next_state <= st11; output <= "0-";
elsif std_match(input, "--00100") then next_state <= st11; output <= "0-";
elsif std_match(input, "--00010") then next_state <= st11; output <= "0-";
elsif std_match(input, "--00001") then next_state <= st11; output <= "0-";
elsif std_match(input, "--01---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--10---") then next_state <= st0; output <= "-0";
elsif std_match(input, "--111--") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11-1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "--11--1") then next_state <= st0; output <= "-0";
elsif std_match(input, "----11-") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st10 =>
if std_match(input, "----000") then next_state <= st13; output <= "1-";
elsif std_match(input, "----100") then next_state <= st14; output <= "0-";
elsif std_match(input, "----010") then next_state <= st14; output <= "0-";
elsif std_match(input, "----001") then next_state <= st14; output <= "0-";
elsif std_match(input, "----11-") then next_state <= st0; output <= "-0";
elsif std_match(input, "----1-1") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st11 =>
if std_match(input, "----000") then next_state <= st14; output <= "0-";
elsif std_match(input, "----1--") then next_state <= st0; output <= "-0";
elsif std_match(input, "-----1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "------1") then next_state <= st0; output <= "-0";
end if;
when st12 =>
if std_match(input, "-----00") then next_state <= st14; output <= "--";
elsif std_match(input, "-----1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "------1") then next_state <= st0; output <= "-0";
end if;
when st13 =>
if std_match(input, "-----00") then next_state <= st15; output <= "1-";
elsif std_match(input, "-----10") then next_state <= st16; output <= "0-";
elsif std_match(input, "-----01") then next_state <= st16; output <= "0-";
elsif std_match(input, "-----11") then next_state <= st0; output <= "-0";
end if;
when st14 =>
if std_match(input, "-----00") then next_state <= st16; output <= "0-";
elsif std_match(input, "-----1-") then next_state <= st0; output <= "-0";
elsif std_match(input, "------1") then next_state <= st0; output <= "-0";
end if;
when st15 =>
if std_match(input, "------0") then next_state <= st17; output <= "--";
elsif std_match(input, "------1") then next_state <= st18; output <= "0-";
end if;
when st16 =>
if std_match(input, "------0") then next_state <= st18; output <= "0-";
elsif std_match(input, "------1") then next_state <= st0; output <= "-0";
end if;
when st17 =>
if std_match(input, "-------") then next_state <= st0; output <= "-0";
end if;
when st18 =>
if std_match(input, "-------") then next_state <= st0; output <= "-1";
end if;
when others => next_state <= "-----"; output <= "--";
end case;
end process;
end behaviour;
|
-------------------------------------------------------------------------------
--
-- MSX1 FPGA project
--
-- Copyright (c) 2016, Fabio Belavenuto ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity PIO is
port (
reset_i : in std_logic;
ipl_en_i : in std_logic;
addr_i : in std_logic_vector(1 downto 0);
data_i : in std_logic_vector(7 downto 0);
data_o : out std_logic_vector(7 downto 0);
has_data_o : out std_logic;
cs_i : in std_logic;
rd_i : in std_logic;
wr_i : in std_logic;
port_a_o : out std_logic_vector(7 downto 0);
port_b_i : in std_logic_vector(7 downto 0);
port_c_o : out std_logic_vector(7 downto 0)
);
end entity;
architecture Behavior of PIO is
signal porta_r : std_logic_vector(7 downto 0);
signal portc_r : std_logic_vector(7 downto 0);
signal rd_cs_s : std_logic;
signal wr_cs_s : std_logic;
begin
-- Sinais de selecao de escrita e leitura
rd_cs_s <= '1' when cs_i = '1' and rd_i = '1' else '0';
wr_cs_s <= '1' when cs_i = '1' and wr_i = '1' else '0';
-- Portas de saida
process(reset_i, ipl_en_i, wr_cs_s)
variable portc_addr_v : integer range 0 to 7;
begin
if reset_i = '1' then
porta_r <= (others => ipl_en_i);
portc_r <= (7 => '0', others => '1'); -- beep silent
elsif falling_edge(wr_cs_s) then
if addr_i = "00" then
porta_r <= data_i;
elsif addr_i = "10" then
portc_r <= data_i;
elsif addr_i = "11" and data_i(7) = '0' then
portc_addr_v := to_integer(unsigned(data_i(3 downto 1)));
portc_r(portc_addr_v) <= data_i(0);
else
-- Ignora resto
end if;
end if;
end process;
-- Leitura
data_o <= porta_r when rd_cs_s = '1' and addr_i = "00" else
port_b_i when rd_cs_s = '1' and addr_i = "01" else
portc_r when rd_cs_s = '1' and addr_i = "10" else
(others => '0');
has_data_o <= '1' when rd_cs_s = '1' and addr_i /= "11" else '0';
-- I/O
port_a_o <= porta_r;
port_c_o <= portc_r;
end; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2050.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n01i02050ent IS
END c07s02b04x00p01n01i02050ent;
ARCHITECTURE c07s02b04x00p01n01i02050arch OF c07s02b04x00p01n01i02050ent IS
BEGIN
TESTING: PROCESS
variable STRINGV : STRING( 1 to 8 );
BEGIN
STRINGV := STRINGV - "hello, world";
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n01i02050 - The adding operators + and - are predefined for any numeric type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n01i02050arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2050.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n01i02050ent IS
END c07s02b04x00p01n01i02050ent;
ARCHITECTURE c07s02b04x00p01n01i02050arch OF c07s02b04x00p01n01i02050ent IS
BEGIN
TESTING: PROCESS
variable STRINGV : STRING( 1 to 8 );
BEGIN
STRINGV := STRINGV - "hello, world";
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n01i02050 - The adding operators + and - are predefined for any numeric type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n01i02050arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2050.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n01i02050ent IS
END c07s02b04x00p01n01i02050ent;
ARCHITECTURE c07s02b04x00p01n01i02050arch OF c07s02b04x00p01n01i02050ent IS
BEGIN
TESTING: PROCESS
variable STRINGV : STRING( 1 to 8 );
BEGIN
STRINGV := STRINGV - "hello, world";
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n01i02050 - The adding operators + and - are predefined for any numeric type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n01i02050arch;
|
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library stratixiii;
use stratixiii.all;
entity adqsout is
port(
clk : in std_logic; -- clk90
dqs : in std_logic;
dqs_oe : in std_logic;
dqs_oct : in std_logic; -- gnd = disable
dqs_pad : out std_logic; -- DQS pad
dqsn_pad : out std_logic -- DQSN pad
);
end;
architecture rtl of adqsout is
component stratixiii_ddio_out
generic(
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
half_rate_mode : string := "false";
use_new_clocking_model : string := "false";
lpm_type : string := "stratixiii_ddio_out"
);
port (
datainlo : in std_logic := '0';
datainhi : in std_logic := '0';
clk : in std_logic := '0';
clkhi : in std_logic := '0';
clklo : in std_logic := '0';
muxsel : in std_logic := '0';
ena : in std_logic := '1';
areset : in std_logic := '0';
sreset : in std_logic := '0';
dataout : out std_logic--;
--dfflo : out std_logic;
--dffhi : out std_logic;
--devclrn : in std_logic := '1';
--devpor : in std_logic := '1'
);
end component;
component stratixiii_ddio_oe is
generic(
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "stratixiii_ddio_oe"
);
port (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic--;
--dfflo : OUT std_logic;
--dffhi : OUT std_logic;
--devclrn : IN std_logic := '1';
--devpor : IN std_logic := '1'
);
end component;
component stratixiii_pseudo_diff_out is
generic (
lpm_type : string := "stratixiii_pseudo_diff_out"
);
port (
i : in std_logic := '0';
o : out std_logic;
obar : out std_logic
);
end component;
component stratixiii_io_obuf
generic(
bus_hold : string := "false";
open_drain_output : string := "false";
shift_series_termination_control : string := "false";
lpm_type : string := "stratixiii_io_obuf"
);
port(
dynamicterminationcontrol : in std_logic := '0';
i : in std_logic := '0';
o : out std_logic;
obar : out std_logic;
oe : in std_logic := '1'--;
--parallelterminationcontrol : in std_logic_vector(13 downto 0) := (others => '0');
--seriesterminationcontrol : in std_logic_vector(13 downto 0) := (others => '0')
);
end component;
signal vcc : std_logic;
signal gnd : std_logic_vector(13 downto 0);
signal dqs_reg, dqs_buf, dqsn_buf : std_logic;
signal dqs_oe_reg, dqs_oe_reg_n, dqs_oct_reg : std_logic;
signal dqsn_oe_reg, dqsn_oe_reg_n, dqsn_oct_reg : std_logic;
begin
vcc <= '1'; gnd <= (others => '0');
-- DQS output register --------------------------------------------------------------
dqs_reg0 : stratixiii_ddio_out
generic map(
power_up => "high",
async_mode => "none",
sync_mode => "none",
half_rate_mode => "false",
use_new_clocking_model => "false",
lpm_type => "stratixiii_ddio_out"
)
port map(
datainlo => gnd(0),
datainhi => dqs,
clk => clk,
clkhi => clk,
clklo => clk,
muxsel => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => dqs_reg--,
--dfflo => open,
--dffhi => open,
--devclrn => vcc,
--devpor => vcc
);
pseudo_diff0 : stratixiii_pseudo_diff_out
port map(
i => dqs_reg,
o => dqs_buf,
obar => dqsn_buf
);
-- Outout enable and oct for DQS, DQSN ----------------------------------------------
dqs_oe_reg0 : stratixiii_ddio_oe
generic map(
power_up => "low",
async_mode => "none",
sync_mode => "none",
lpm_type => "stratixiii_ddio_oe"
)
port map(
oe => dqs_oe,
clk => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => dqs_oe_reg--,
--dfflo => open,
--dffhi => open,
--devclrn => vcc,
--devpor => vcc
);
dqs_oe_reg_n <= not dqs_oe_reg;
dqs_oct_reg0 : stratixiii_ddio_oe
generic map(
power_up => "low",
async_mode => "none",
sync_mode => "none",
lpm_type => "stratixiii_ddio_oe"
)
port map(
oe => dqs_oct,
clk => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => dqs_oct_reg--,
--dfflo => open,
--dffhi => open,
--devclrn => vcc,
--devpor => vcc
);
dqsn_oe_reg0 : stratixiii_ddio_oe
generic map(
power_up => "low",
async_mode => "none",
sync_mode => "none",
lpm_type => "stratixiii_ddio_oe"
)
port map(
oe => dqs_oe,
clk => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => dqsn_oe_reg--,
--dfflo => open,
--dffhi => open,
--devclrn => vcc,
--devpor => vcc
);
dqsn_oe_reg_n <= not dqsn_oe_reg;
dqsn_oct_reg0 : stratixiii_ddio_oe
generic map(
power_up => "low",
async_mode => "none",
sync_mode => "none",
lpm_type => "stratixiii_ddio_oe"
)
port map(
oe => dqs_oct,
clk => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => dqsn_oct_reg--,
--dfflo => open,
--dffhi => open,
--devclrn => vcc,
--devpor => vcc
);
-- Out buffer (DQS, DQSN) -----------------------------------------------------------
dqs_buf0 : stratixiii_io_obuf
generic map(
open_drain_output => "false",
shift_series_termination_control => "false",
bus_hold => "false",
lpm_type => "stratixiii_io_obuf"
)
port map(
i => dqs_buf,
oe => dqs_oe_reg_n,
--dynamicterminationcontrol => dqs_oct, --gnd(0),--dqs_oct_reg,
--seriesterminationcontrol => gnd,
--parallelterminationcontrol => gnd,
o => dqs_pad,
obar => open
);
dqsn_buf0 : stratixiii_io_obuf
generic map(
open_drain_output => "false",
shift_series_termination_control => "false",
bus_hold => "false",
lpm_type => "stratixiii_io_obuf"
)
port map(
i => dqsn_buf,
oe => dqsn_oe_reg_n,
--dynamicterminationcontrol => dqs_oct, --gnd(0),--dqsn_oct_reg,
--seriesterminationcontrol => gnd,
--parallelterminationcontrol => gnd,
o => dqsn_pad,
obar => open
);
end;
|
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library stratixiii;
use stratixiii.all;
entity adqsout is
port(
clk : in std_logic; -- clk90
dqs : in std_logic;
dqs_oe : in std_logic;
dqs_oct : in std_logic; -- gnd = disable
dqs_pad : out std_logic; -- DQS pad
dqsn_pad : out std_logic -- DQSN pad
);
end;
architecture rtl of adqsout is
component stratixiii_ddio_out
generic(
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
half_rate_mode : string := "false";
use_new_clocking_model : string := "false";
lpm_type : string := "stratixiii_ddio_out"
);
port (
datainlo : in std_logic := '0';
datainhi : in std_logic := '0';
clk : in std_logic := '0';
clkhi : in std_logic := '0';
clklo : in std_logic := '0';
muxsel : in std_logic := '0';
ena : in std_logic := '1';
areset : in std_logic := '0';
sreset : in std_logic := '0';
dataout : out std_logic--;
--dfflo : out std_logic;
--dffhi : out std_logic;
--devclrn : in std_logic := '1';
--devpor : in std_logic := '1'
);
end component;
component stratixiii_ddio_oe is
generic(
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "stratixiii_ddio_oe"
);
port (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic--;
--dfflo : OUT std_logic;
--dffhi : OUT std_logic;
--devclrn : IN std_logic := '1';
--devpor : IN std_logic := '1'
);
end component;
component stratixiii_pseudo_diff_out is
generic (
lpm_type : string := "stratixiii_pseudo_diff_out"
);
port (
i : in std_logic := '0';
o : out std_logic;
obar : out std_logic
);
end component;
component stratixiii_io_obuf
generic(
bus_hold : string := "false";
open_drain_output : string := "false";
shift_series_termination_control : string := "false";
lpm_type : string := "stratixiii_io_obuf"
);
port(
dynamicterminationcontrol : in std_logic := '0';
i : in std_logic := '0';
o : out std_logic;
obar : out std_logic;
oe : in std_logic := '1'--;
--parallelterminationcontrol : in std_logic_vector(13 downto 0) := (others => '0');
--seriesterminationcontrol : in std_logic_vector(13 downto 0) := (others => '0')
);
end component;
signal vcc : std_logic;
signal gnd : std_logic_vector(13 downto 0);
signal dqs_reg, dqs_buf, dqsn_buf : std_logic;
signal dqs_oe_reg, dqs_oe_reg_n, dqs_oct_reg : std_logic;
signal dqsn_oe_reg, dqsn_oe_reg_n, dqsn_oct_reg : std_logic;
begin
vcc <= '1'; gnd <= (others => '0');
-- DQS output register --------------------------------------------------------------
dqs_reg0 : stratixiii_ddio_out
generic map(
power_up => "high",
async_mode => "none",
sync_mode => "none",
half_rate_mode => "false",
use_new_clocking_model => "false",
lpm_type => "stratixiii_ddio_out"
)
port map(
datainlo => gnd(0),
datainhi => dqs,
clk => clk,
clkhi => clk,
clklo => clk,
muxsel => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => dqs_reg--,
--dfflo => open,
--dffhi => open,
--devclrn => vcc,
--devpor => vcc
);
pseudo_diff0 : stratixiii_pseudo_diff_out
port map(
i => dqs_reg,
o => dqs_buf,
obar => dqsn_buf
);
-- Outout enable and oct for DQS, DQSN ----------------------------------------------
dqs_oe_reg0 : stratixiii_ddio_oe
generic map(
power_up => "low",
async_mode => "none",
sync_mode => "none",
lpm_type => "stratixiii_ddio_oe"
)
port map(
oe => dqs_oe,
clk => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => dqs_oe_reg--,
--dfflo => open,
--dffhi => open,
--devclrn => vcc,
--devpor => vcc
);
dqs_oe_reg_n <= not dqs_oe_reg;
dqs_oct_reg0 : stratixiii_ddio_oe
generic map(
power_up => "low",
async_mode => "none",
sync_mode => "none",
lpm_type => "stratixiii_ddio_oe"
)
port map(
oe => dqs_oct,
clk => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => dqs_oct_reg--,
--dfflo => open,
--dffhi => open,
--devclrn => vcc,
--devpor => vcc
);
dqsn_oe_reg0 : stratixiii_ddio_oe
generic map(
power_up => "low",
async_mode => "none",
sync_mode => "none",
lpm_type => "stratixiii_ddio_oe"
)
port map(
oe => dqs_oe,
clk => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => dqsn_oe_reg--,
--dfflo => open,
--dffhi => open,
--devclrn => vcc,
--devpor => vcc
);
dqsn_oe_reg_n <= not dqsn_oe_reg;
dqsn_oct_reg0 : stratixiii_ddio_oe
generic map(
power_up => "low",
async_mode => "none",
sync_mode => "none",
lpm_type => "stratixiii_ddio_oe"
)
port map(
oe => dqs_oct,
clk => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => dqsn_oct_reg--,
--dfflo => open,
--dffhi => open,
--devclrn => vcc,
--devpor => vcc
);
-- Out buffer (DQS, DQSN) -----------------------------------------------------------
dqs_buf0 : stratixiii_io_obuf
generic map(
open_drain_output => "false",
shift_series_termination_control => "false",
bus_hold => "false",
lpm_type => "stratixiii_io_obuf"
)
port map(
i => dqs_buf,
oe => dqs_oe_reg_n,
--dynamicterminationcontrol => dqs_oct, --gnd(0),--dqs_oct_reg,
--seriesterminationcontrol => gnd,
--parallelterminationcontrol => gnd,
o => dqs_pad,
obar => open
);
dqsn_buf0 : stratixiii_io_obuf
generic map(
open_drain_output => "false",
shift_series_termination_control => "false",
bus_hold => "false",
lpm_type => "stratixiii_io_obuf"
)
port map(
i => dqsn_buf,
oe => dqsn_oe_reg_n,
--dynamicterminationcontrol => dqs_oct, --gnd(0),--dqsn_oct_reg,
--seriesterminationcontrol => gnd,
--parallelterminationcontrol => gnd,
o => dqsn_pad,
obar => open
);
end;
|
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library stratixiii;
use stratixiii.all;
entity adqsout is
port(
clk : in std_logic; -- clk90
dqs : in std_logic;
dqs_oe : in std_logic;
dqs_oct : in std_logic; -- gnd = disable
dqs_pad : out std_logic; -- DQS pad
dqsn_pad : out std_logic -- DQSN pad
);
end;
architecture rtl of adqsout is
component stratixiii_ddio_out
generic(
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
half_rate_mode : string := "false";
use_new_clocking_model : string := "false";
lpm_type : string := "stratixiii_ddio_out"
);
port (
datainlo : in std_logic := '0';
datainhi : in std_logic := '0';
clk : in std_logic := '0';
clkhi : in std_logic := '0';
clklo : in std_logic := '0';
muxsel : in std_logic := '0';
ena : in std_logic := '1';
areset : in std_logic := '0';
sreset : in std_logic := '0';
dataout : out std_logic--;
--dfflo : out std_logic;
--dffhi : out std_logic;
--devclrn : in std_logic := '1';
--devpor : in std_logic := '1'
);
end component;
component stratixiii_ddio_oe is
generic(
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "stratixiii_ddio_oe"
);
port (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic--;
--dfflo : OUT std_logic;
--dffhi : OUT std_logic;
--devclrn : IN std_logic := '1';
--devpor : IN std_logic := '1'
);
end component;
component stratixiii_pseudo_diff_out is
generic (
lpm_type : string := "stratixiii_pseudo_diff_out"
);
port (
i : in std_logic := '0';
o : out std_logic;
obar : out std_logic
);
end component;
component stratixiii_io_obuf
generic(
bus_hold : string := "false";
open_drain_output : string := "false";
shift_series_termination_control : string := "false";
lpm_type : string := "stratixiii_io_obuf"
);
port(
dynamicterminationcontrol : in std_logic := '0';
i : in std_logic := '0';
o : out std_logic;
obar : out std_logic;
oe : in std_logic := '1'--;
--parallelterminationcontrol : in std_logic_vector(13 downto 0) := (others => '0');
--seriesterminationcontrol : in std_logic_vector(13 downto 0) := (others => '0')
);
end component;
signal vcc : std_logic;
signal gnd : std_logic_vector(13 downto 0);
signal dqs_reg, dqs_buf, dqsn_buf : std_logic;
signal dqs_oe_reg, dqs_oe_reg_n, dqs_oct_reg : std_logic;
signal dqsn_oe_reg, dqsn_oe_reg_n, dqsn_oct_reg : std_logic;
begin
vcc <= '1'; gnd <= (others => '0');
-- DQS output register --------------------------------------------------------------
dqs_reg0 : stratixiii_ddio_out
generic map(
power_up => "high",
async_mode => "none",
sync_mode => "none",
half_rate_mode => "false",
use_new_clocking_model => "false",
lpm_type => "stratixiii_ddio_out"
)
port map(
datainlo => gnd(0),
datainhi => dqs,
clk => clk,
clkhi => clk,
clklo => clk,
muxsel => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => dqs_reg--,
--dfflo => open,
--dffhi => open,
--devclrn => vcc,
--devpor => vcc
);
pseudo_diff0 : stratixiii_pseudo_diff_out
port map(
i => dqs_reg,
o => dqs_buf,
obar => dqsn_buf
);
-- Outout enable and oct for DQS, DQSN ----------------------------------------------
dqs_oe_reg0 : stratixiii_ddio_oe
generic map(
power_up => "low",
async_mode => "none",
sync_mode => "none",
lpm_type => "stratixiii_ddio_oe"
)
port map(
oe => dqs_oe,
clk => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => dqs_oe_reg--,
--dfflo => open,
--dffhi => open,
--devclrn => vcc,
--devpor => vcc
);
dqs_oe_reg_n <= not dqs_oe_reg;
dqs_oct_reg0 : stratixiii_ddio_oe
generic map(
power_up => "low",
async_mode => "none",
sync_mode => "none",
lpm_type => "stratixiii_ddio_oe"
)
port map(
oe => dqs_oct,
clk => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => dqs_oct_reg--,
--dfflo => open,
--dffhi => open,
--devclrn => vcc,
--devpor => vcc
);
dqsn_oe_reg0 : stratixiii_ddio_oe
generic map(
power_up => "low",
async_mode => "none",
sync_mode => "none",
lpm_type => "stratixiii_ddio_oe"
)
port map(
oe => dqs_oe,
clk => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => dqsn_oe_reg--,
--dfflo => open,
--dffhi => open,
--devclrn => vcc,
--devpor => vcc
);
dqsn_oe_reg_n <= not dqsn_oe_reg;
dqsn_oct_reg0 : stratixiii_ddio_oe
generic map(
power_up => "low",
async_mode => "none",
sync_mode => "none",
lpm_type => "stratixiii_ddio_oe"
)
port map(
oe => dqs_oct,
clk => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => dqsn_oct_reg--,
--dfflo => open,
--dffhi => open,
--devclrn => vcc,
--devpor => vcc
);
-- Out buffer (DQS, DQSN) -----------------------------------------------------------
dqs_buf0 : stratixiii_io_obuf
generic map(
open_drain_output => "false",
shift_series_termination_control => "false",
bus_hold => "false",
lpm_type => "stratixiii_io_obuf"
)
port map(
i => dqs_buf,
oe => dqs_oe_reg_n,
--dynamicterminationcontrol => dqs_oct, --gnd(0),--dqs_oct_reg,
--seriesterminationcontrol => gnd,
--parallelterminationcontrol => gnd,
o => dqs_pad,
obar => open
);
dqsn_buf0 : stratixiii_io_obuf
generic map(
open_drain_output => "false",
shift_series_termination_control => "false",
bus_hold => "false",
lpm_type => "stratixiii_io_obuf"
)
port map(
i => dqsn_buf,
oe => dqsn_oe_reg_n,
--dynamicterminationcontrol => dqs_oct, --gnd(0),--dqsn_oct_reg,
--seriesterminationcontrol => gnd,
--parallelterminationcontrol => gnd,
o => dqsn_pad,
obar => open
);
end;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:22:35 11/21/2016
-- Design Name:
-- Module Name: PC_Adder - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx prAdderitives in this code.
--library UNISAdder;
--use UNISAdder.VComponents.all;
entity PC_Adder is
Port (
PC : in STD_LOGIC_VECTOR(15 downto 0);
NPC : out STD_LOGIC_VECTOR(15 downto 0));
end PC_Adder;
architecture Behavioral of PC_Adder is
begin
process(PC)
begin
NPC <= PC + '1';
end process;
end Behavioral;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun May 28 18:34:35 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top system_debounce_0_0 -prefix
-- system_debounce_0_0_ system_debounce_0_0_stub.vhdl
-- Design : system_debounce_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_debounce_0_0 is
Port (
clk : in STD_LOGIC;
signal_in : in STD_LOGIC;
signal_out : out STD_LOGIC
);
end system_debounce_0_0;
architecture stub of system_debounce_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,signal_in,signal_out";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "debounce,Vivado 2016.4";
begin
end;
|
entity bitvec is
end entity;
architecture test of bitvec is
function get_bitvec(x, y : integer) return bit_vector is
variable r : bit_vector(x to y) := "00";
begin
return r;
end function;
begin
process is
variable b : bit_vector(3 downto 0);
variable n : integer;
begin
b := "1101";
n := 2;
wait for 1 ns;
assert not b = "0010";
assert (b and "1010") = "1000";
assert (b or "0110") = "1111";
assert (b xor "0111") = "1010";
assert (b xnor "0111") = "0101";
assert (b nand "1010") = "0111";
assert (b nor "0110") = "0000";
assert get_bitvec(1, n) = "00";
wait;
end process;
end architecture;
|
entity bitvec is
end entity;
architecture test of bitvec is
function get_bitvec(x, y : integer) return bit_vector is
variable r : bit_vector(x to y) := "00";
begin
return r;
end function;
begin
process is
variable b : bit_vector(3 downto 0);
variable n : integer;
begin
b := "1101";
n := 2;
wait for 1 ns;
assert not b = "0010";
assert (b and "1010") = "1000";
assert (b or "0110") = "1111";
assert (b xor "0111") = "1010";
assert (b xnor "0111") = "0101";
assert (b nand "1010") = "0111";
assert (b nor "0110") = "0000";
assert get_bitvec(1, n) = "00";
wait;
end process;
end architecture;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 24 ns;
PRC_RD_EN <= prc_re_i AFTER 24 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 24 ns;
PRC_RD_EN <= prc_re_i AFTER 24 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 24 ns;
PRC_RD_EN <= prc_re_i AFTER 24 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 24 ns;
PRC_RD_EN <= prc_re_i AFTER 24 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 24 ns;
PRC_RD_EN <= prc_re_i AFTER 24 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 24 ns;
PRC_RD_EN <= prc_re_i AFTER 24 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 24 ns;
PRC_RD_EN <= prc_re_i AFTER 24 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 24 ns;
PRC_RD_EN <= prc_re_i AFTER 24 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 24 ns;
PRC_RD_EN <= prc_re_i AFTER 24 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 24 ns;
PRC_RD_EN <= prc_re_i AFTER 24 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 24 ns;
PRC_RD_EN <= prc_re_i AFTER 24 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 24 ns;
PRC_RD_EN <= prc_re_i AFTER 24 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 24 ns;
PRC_RD_EN <= prc_re_i AFTER 24 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 24 ns;
PRC_RD_EN <= prc_re_i AFTER 24 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 24 ns;
PRC_RD_EN <= prc_re_i AFTER 24 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 24 ns;
PRC_RD_EN <= prc_re_i AFTER 24 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 24 ns;
PRC_RD_EN <= prc_re_i AFTER 24 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 24 ns;
PRC_RD_EN <= prc_re_i AFTER 24 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 24 ns;
PRC_RD_EN <= prc_re_i AFTER 24 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_i & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_i = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0' AND state_d1 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_i = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_i = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 24 ns;
PRC_RD_EN <= prc_re_i AFTER 24 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
RESET_EN <= reset_en_i;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
state_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
state_d1 <= state;
END IF;
END PROCESS;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_i = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_i = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND EMPTY = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(EMPTY = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
-------------------------------------------------------------------------------
-- axi_dma_lite_if
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_dma_lite_if.vhd
-- Description: This entity is AXI Lite Interface Module for the AXI DMA
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
library lib_pkg_v1_0;
library lib_cdc_v1_0;
use lib_pkg_v1_0.lib_pkg.clog2;
-------------------------------------------------------------------------------
entity axi_dma_lite_if is
generic(
C_NUM_CE : integer := 8 ;
C_AXI_LITE_IS_ASYNC : integer range 0 to 1 := 0 ;
C_S_AXI_LITE_ADDR_WIDTH : integer range 2 to 32 := 32 ;
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32
);
port (
-- Async clock input
ip2axi_aclk : in std_logic ; --
ip2axi_aresetn : in std_logic ; --
-----------------------------------------------------------------------
-- AXI Lite Control Interface
-----------------------------------------------------------------------
s_axi_lite_aclk : in std_logic ; --
s_axi_lite_aresetn : in std_logic ; --
--
-- AXI Lite Write Address Channel --
s_axi_lite_awvalid : in std_logic ; --
s_axi_lite_awready : out std_logic ; --
s_axi_lite_awaddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
--
-- AXI Lite Write Data Channel --
s_axi_lite_wvalid : in std_logic ; --
s_axi_lite_wready : out std_logic ; --
s_axi_lite_wdata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
--
-- AXI Lite Write Response Channel --
s_axi_lite_bresp : out std_logic_vector(1 downto 0) ; --
s_axi_lite_bvalid : out std_logic ; --
s_axi_lite_bready : in std_logic ; --
--
-- AXI Lite Read Address Channel --
s_axi_lite_arvalid : in std_logic ; --
s_axi_lite_arready : out std_logic ; --
s_axi_lite_araddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
s_axi_lite_rvalid : out std_logic ; --
s_axi_lite_rready : in std_logic ; --
s_axi_lite_rdata : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s_axi_lite_rresp : out std_logic_vector(1 downto 0) ; --
--
-- User IP Interface --
axi2ip_wrce : out std_logic_vector --
(C_NUM_CE-1 downto 0) ; --
axi2ip_wrdata : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
--
axi2ip_rdce : out std_logic_vector --
(C_NUM_CE-1 downto 0) ; --
axi2ip_rdaddr : out std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
ip2axi_rddata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) --
);
end axi_dma_lite_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_lite_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Register I/F Address offset
constant ADDR_OFFSET : integer := clog2(C_S_AXI_LITE_DATA_WIDTH/8);
-- Register I/F CE number
constant CE_ADDR_SIZE : integer := clog2(C_NUM_CE);
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- AXI Lite slave interface signals
signal awvalid : std_logic := '0';
signal awaddr : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal wvalid : std_logic := '0';
signal wdata : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal arvalid : std_logic := '0';
signal araddr : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal awvalid_d1 : std_logic := '0';
signal awvalid_re : std_logic := '0';
signal awready_i : std_logic := '0';
signal wvalid_d1 : std_logic := '0';
signal wvalid_re : std_logic := '0';
signal wready_i : std_logic := '0';
signal bvalid_i : std_logic := '0';
signal wr_addr_cap : std_logic := '0';
signal wr_data_cap : std_logic := '0';
-- AXI to IP interface signals
signal axi2ip_wraddr_i : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal axi2ip_wrdata_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal axi2ip_wren : std_logic := '0';
signal wrce : std_logic_vector(C_NUM_CE-1 downto 0);
signal rdce : std_logic_vector(C_NUM_CE-1 downto 0) := (others => '0');
signal arvalid_d1 : std_logic := '0';
signal arvalid_re : std_logic := '0';
signal arvalid_re_d1 : std_logic := '0';
signal arvalid_i : std_logic := '0';
signal arready_i : std_logic := '0';
signal rvalid : std_logic := '0';
signal axi2ip_rdaddr_i : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s_axi_lite_rvalid_i : std_logic := '0';
signal read_in_progress : std_logic := '0'; -- CR607165
signal rst_rvalid_re : std_logic := '0'; -- CR576999
signal rst_wvalid_re : std_logic := '0'; -- CR576999
signal rdy : std_logic := '0';
signal rdy1 : std_logic := '0';
signal wr_in_progress : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
--*****************************************************************************
--** AXI LITE READ
--*****************************************************************************
s_axi_lite_wready <= wready_i;
s_axi_lite_awready <= awready_i;
s_axi_lite_arready <= arready_i;
s_axi_lite_bvalid <= bvalid_i;
-------------------------------------------------------------------------------
-- Register AXI Inputs
-------------------------------------------------------------------------------
REG_INPUTS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
awvalid <= '0' ;
awaddr <= (others => '0') ;
wvalid <= '0' ;
wdata <= (others => '0') ;
arvalid <= '0' ;
araddr <= (others => '0') ;
else
awvalid <= s_axi_lite_awvalid ;
awaddr <= s_axi_lite_awaddr ;
wvalid <= s_axi_lite_wvalid ;
wdata <= s_axi_lite_wdata ;
arvalid <= s_axi_lite_arvalid ;
araddr <= s_axi_lite_araddr ;
end if;
end if;
end process REG_INPUTS;
-- s_axi_lite_aclk is synchronous to ip clock
GEN_SYNC_WRITE : if C_AXI_LITE_IS_ASYNC = 0 generate
begin
-------------------------------------------------------------------------------
-- Assert Write Adddress Ready Handshake
-- Capture rising edge of valid and register out as ready. This creates
-- a 3 clock cycle address phase but also registers all inputs and outputs.
-- Note : Single clock cycle address phase can be accomplished using
-- combinatorial logic.
-------------------------------------------------------------------------------
REG_AWVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
awvalid_d1 <= '0';
-- awvalid_re <= '0'; -- CR605883
else
awvalid_d1 <= awvalid;
-- awvalid_re <= awvalid and not awvalid_d1; -- CR605883
end if;
end if;
end process REG_AWVALID;
awvalid_re <= awvalid and not awvalid_d1 and (not (wr_in_progress)); -- CR605883
-------------------------------------------------------------------------------
-- Capture assertion of awvalid to indicate that we have captured
-- a valid address
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Assert Write Data Ready Handshake
-- Capture rising edge of valid and register out as ready. This creates
-- a 3 clock cycle address phase but also registers all inputs and outputs.
-- Note : Single clock cycle address phase can be accomplished using
-- combinatorial logic.
-------------------------------------------------------------------------------
REG_WVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
wvalid_d1 <= '0';
-- wvalid_re <= '0';
else
wvalid_d1 <= wvalid;
-- wvalid_re <= wvalid and not wvalid_d1; -- CR605883
end if;
end if;
end process REG_WVALID;
wvalid_re <= wvalid and not wvalid_d1; -- CR605883
WRITE_IN_PROGRESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
wr_in_progress <= '0';
elsif(awvalid_re = '1')then
wr_in_progress <= '1';
end if;
end if;
end process WRITE_IN_PROGRESS;
-- CR605883 (CDC) provide pure register output to synchronizers
--wvalid_re <= wvalid and not wvalid_d1 and not rst_wvalid_re;
-------------------------------------------------------------------------------
-- Capture assertion of wvalid to indicate that we have captured
-- valid data
-------------------------------------------------------------------------------
WRDATA_CAP_FLAG : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rdy = '1')then
wr_data_cap <= '0';
elsif(wvalid_re = '1')then
wr_data_cap <= '1';
end if;
end if;
end process WRDATA_CAP_FLAG;
REG_WREADY : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rdy = '1') then
rdy <= '0';
elsif (wr_data_cap = '1' and wr_addr_cap = '1') then
rdy <= '1';
end if;
wready_i <= rdy;
awready_i <= rdy;
rdy1 <= rdy;
end if;
end process REG_WREADY;
WRADDR_CAP_FLAG : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rdy = '1')then
wr_addr_cap <= '0';
elsif(awvalid_re = '1')then
wr_addr_cap <= '1';
end if;
end if;
end process WRADDR_CAP_FLAG;
-------------------------------------------------------------------------------
-- Capture Write Address
-------------------------------------------------------------------------------
REG_WRITE_ADDRESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
-- axi2ip_wraddr_i <= (others => '0');
-- Register address on valid
elsif(awvalid_re = '1')then
-- axi2ip_wraddr_i <= awaddr;
end if;
end if;
end process REG_WRITE_ADDRESS;
-------------------------------------------------------------------------------
-- Capture Write Data
-------------------------------------------------------------------------------
REG_WRITE_DATA : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
axi2ip_wrdata_i <= (others => '0');
-- Register address and assert ready
elsif(wvalid_re = '1')then
axi2ip_wrdata_i <= wdata;
end if;
end if;
end process REG_WRITE_DATA;
-------------------------------------------------------------------------------
-- Must have both a valid address and valid data before updating
-- a register. Note in AXI write address can come before or
-- after AXI write data.
-- axi2ip_wren <= '1' when wr_data_cap = '1' and wr_addr_cap = '1'
-- else '0';
axi2ip_wren <= rdy; -- or rdy1;
-------------------------------------------------------------------------------
-- Decode and assert proper chip enable per captured axi lite write address
-------------------------------------------------------------------------------
WRCE_GEN: for j in 0 to C_NUM_CE - 1 generate
constant BAR : std_logic_vector(CE_ADDR_SIZE-1 downto 0) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
wrce(j) <= axi2ip_wren when s_axi_lite_awaddr
((CE_ADDR_SIZE + ADDR_OFFSET) - 1
downto ADDR_OFFSET)
= BAR(CE_ADDR_SIZE-1 downto 0)
else '0';
end generate WRCE_GEN;
-------------------------------------------------------------------------------
-- register write ce's and data out to axi dma register module
-------------------------------------------------------------------------------
REG_WR_OUT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
axi2ip_wrce <= (others => '0');
-- axi2ip_wrdata <= (others => '0');
else
axi2ip_wrce <= wrce;
-- axi2ip_wrdata <= axi2ip_wrdata_i;
end if;
end if;
end process REG_WR_OUT;
axi2ip_wrdata <= s_axi_lite_wdata;
-------------------------------------------------------------------------------
-- Write Response
-------------------------------------------------------------------------------
s_axi_lite_bresp <= OKAY_RESP;
WRESP_PROCESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
bvalid_i <= '0';
rst_wvalid_re <= '0'; -- CR576999
-- If response issued and target indicates ready then
-- clear response
elsif(bvalid_i = '1' and s_axi_lite_bready = '1')then
bvalid_i <= '0';
rst_wvalid_re <= '0'; -- CR576999
-- Issue a resonse on write
elsif(rdy1 = '1')then
bvalid_i <= '1';
rst_wvalid_re <= '1'; -- CR576999
end if;
end if;
end process WRESP_PROCESS;
end generate GEN_SYNC_WRITE;
-- s_axi_lite_aclk is asynchronous to ip clock
GEN_ASYNC_WRITE : if C_AXI_LITE_IS_ASYNC = 1 generate
-- Data support
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
signal ip_wvalid_d1_cdc_to : std_logic := '0';
signal ip_wvalid_d2 : std_logic := '0';
signal ip_wvalid_re : std_logic := '0';
signal wr_wvalid_re_cdc_from : std_logic := '0';
signal wr_data_cdc_from : std_logic_vector -- CR605883
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); -- CR605883
signal wdata_d1_cdc_to : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal wdata_d2 : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal axi2ip_wrdata_cdc_tig : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal ip_data_cap : std_logic := '0';
-- Address support
signal ip_awvalid_d1_cdc_to : std_logic := '0';
signal ip_awvalid_d2 : std_logic := '0';
signal ip_awvalid_re : std_logic := '0';
signal wr_awvalid_re_cdc_from : std_logic := '0';
signal wr_addr_cdc_from : std_logic_vector -- CR605883
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0'); -- CR605883
signal awaddr_d1_cdc_tig : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal awaddr_d2 : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ip_addr_cap : std_logic := '0';
-- Bvalid support
signal lite_data_cap_d1 : std_logic := '0';
signal lite_data_cap_d2 : std_logic := '0';
signal lite_addr_cap_d1 : std_logic := '0';
signal lite_addr_cap_d2 : std_logic := '0';
signal lite_axi2ip_wren : std_logic := '0';
signal awvalid_cdc_from : std_logic := '0';
signal awvalid_cdc_to : std_logic := '0';
signal awvalid_to : std_logic := '0';
signal awvalid_to2 : std_logic := '0';
--ATTRIBUTE async_reg OF awvalid_cdc_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF awvalid_to : SIGNAL IS "true";
signal wvalid_cdc_from : std_logic := '0';
signal wvalid_cdc_to : std_logic := '0';
signal wvalid_to : std_logic := '0';
signal wvalid_to2 : std_logic := '0';
--ATTRIBUTE async_reg OF wvalid_cdc_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF wvalid_to : SIGNAL IS "true";
signal rdy_cdc_to : std_logic := '0';
signal rdy_cdc_from : std_logic := '0';
signal rdy_to : std_logic := '0';
signal rdy_to2 : std_logic := '0';
signal rdy_to2_cdc_from : std_logic := '0';
signal rdy_out : std_logic := '0';
--ATTRIBUTE async_reg OF rdy_cdc_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF rdy_to : SIGNAL IS "true";
Attribute KEEP of rdy_to2_cdc_from : signal is "TRUE";
Attribute EQUIVALENT_REGISTER_REMOVAL of rdy_to2_cdc_from : signal is "no";
signal rdy_back_cdc_to : std_logic := '0';
signal rdy_back_to : std_logic :='0';
--ATTRIBUTE async_reg OF rdy_back_cdc_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF rdy_back_to : SIGNAL IS "true";
signal rdy_back : std_logic := '0';
signal rdy_shut : std_logic := '0';
begin
REG_AWVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
awvalid_d1 <= '0';
else
awvalid_d1 <= awvalid;
end if;
end if;
end process REG_AWVALID;
awvalid_re <= awvalid and not awvalid_d1 and (not (wr_in_progress)); -- CR605883
-------------------------------------------------------------------------------
-- Capture assertion of awvalid to indicate that we have captured
-- a valid address
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Assert Write Data Ready Handshake
-- Capture rising edge of valid and register out as ready. This creates
-- a 3 clock cycle address phase but also registers all inputs and outputs.
-- Note : Single clock cycle address phase can be accomplished using
-- combinatorial logic.
-------------------------------------------------------------------------------
REG_WVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
wvalid_d1 <= '0';
else
wvalid_d1 <= wvalid;
end if;
end if;
end process REG_WVALID;
wvalid_re <= wvalid and not wvalid_d1; -- CR605883
--*************************************************************************
--** Write Address Support
--*************************************************************************
AWVLD_CDC_FROM : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
awvalid_cdc_from <= '0';
elsif(awvalid_re = '1')then
awvalid_cdc_from <= '1';
end if;
end if;
end process AWVLD_CDC_FROM;
AWVLD_CDC_TO : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => awvalid_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => awvalid_to,
scndry_vect_out => open
);
-- AWVLD_CDC_TO : process(ip2axi_aclk)
-- begin
-- if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
-- awvalid_cdc_to <= awvalid_cdc_from;
-- awvalid_to <= awvalid_cdc_to;
-- end if;
-- end process AWVLD_CDC_TO;
AWVLD_CDC_TO2 : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
awvalid_to2 <= '0';
else
awvalid_to2 <= awvalid_to;
end if;
end if;
end process AWVLD_CDC_TO2;
ip_awvalid_re <= awvalid_to and (not awvalid_to2);
WVLD_CDC_FROM : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
wvalid_cdc_from <= '0';
elsif(wvalid_re = '1')then
wvalid_cdc_from <= '1';
end if;
end if;
end process WVLD_CDC_FROM;
WVLD_CDC_TO : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => wvalid_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => wvalid_to,
scndry_vect_out => open
);
-- WVLD_CDC_TO : process(ip2axi_aclk)
-- begin
-- if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
-- wvalid_cdc_to <= wvalid_cdc_from;
-- wvalid_to <= wvalid_cdc_to;
-- end if;
-- end process WVLD_CDC_TO;
WVLD_CDC_TO2 : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
wvalid_to2 <= '0';
else
wvalid_to2 <= wvalid_to;
end if;
end if;
end process WVLD_CDC_TO2;
ip_wvalid_re <= wvalid_to and (not wvalid_to2);
REG_WADDR_TO_IPCLK : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH,
C_MTBF_STAGES => 1
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => s_axi_lite_awaddr,
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => awaddr_d1_cdc_tig
);
REG_WADDR_TO_IPCLK1 : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_S_AXI_LITE_DATA_WIDTH,
C_MTBF_STAGES => 1
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => s_axi_lite_wdata,
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => axi2ip_wrdata_cdc_tig
);
-- Double register address in
-- REG_WADDR_TO_IPCLK : process(ip2axi_aclk)
-- begin
-- if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
-- if(ip2axi_aresetn = '0')then
-- awaddr_d1_cdc_tig <= (others => '0');
-- -- axi2ip_wraddr_i <= (others => '0');
-- axi2ip_wrdata_cdc_tig <= (others => '0');
-- else
-- awaddr_d1_cdc_tig <= s_axi_lite_awaddr;
-- axi2ip_wrdata_cdc_tig <= s_axi_lite_wdata;
-- -- axi2ip_wraddr_i <= awaddr_d1_cdc_tig; -- CR605883
-- end if;
-- end if;
-- end process REG_WADDR_TO_IPCLK;
-- Flag that address has been captured
REG_IP_ADDR_CAP : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0' or rdy_shut = '1')then
ip_addr_cap <= '0';
elsif(ip_awvalid_re = '1')then
ip_addr_cap <= '1';
end if;
end if;
end process REG_IP_ADDR_CAP;
REG_WREADY : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0' or rdy_shut = '1') then -- or rdy = '1') then
rdy <= '0';
elsif (ip_data_cap = '1' and ip_addr_cap = '1') then
rdy <= '1';
end if;
end if;
end process REG_WREADY;
REG3_WREADY : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => rdy_to2_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => rdy_back_to,
scndry_vect_out => open
);
-- REG3_WREADY : process(ip2axi_aclk)
-- begin
-- if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
-- rdy_back_cdc_to <= rdy_to2_cdc_from;
-- rdy_back_to <= rdy_back_cdc_to;
-- end if;
-- end process REG3_WREADY;
REG3_WREADY2 : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0') then
rdy_back <= '0';
else
rdy_back <= rdy_back_to;
end if;
end if;
end process REG3_WREADY2;
rdy_shut <= rdy_back_to and (not rdy_back);
REG1_WREADY : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0' or rdy_shut = '1') then
rdy_cdc_from <= '0';
elsif (rdy = '1') then
rdy_cdc_from <= '1';
end if;
end if;
end process REG1_WREADY;
REG2_WREADY : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => ip2axi_aclk,
prmry_resetn => '0',
prmry_in => rdy_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '0',
scndry_out => rdy_to,
scndry_vect_out => open
);
-- REG2_WREADY : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- rdy_cdc_to <= rdy_cdc_from;
-- rdy_to <= rdy_cdc_to;
-- end if;
-- end process REG2_WREADY;
REG2_WREADY2 : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0') then
rdy_to2 <= '0';
rdy_to2_cdc_from <= '0';
else
rdy_to2 <= rdy_to;
rdy_to2_cdc_from <= rdy_to;
end if;
end if;
end process REG2_WREADY2;
rdy_out <= not (rdy_to) and rdy_to2;
wready_i <= rdy_out;
awready_i <= rdy_out;
--*************************************************************************
--** Write Data Support
--*************************************************************************
-------------------------------------------------------------------------------
-- Capture write data
-------------------------------------------------------------------------------
-- WRDATA_S_H : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- if(s_axi_lite_aresetn = '0')then
-- wr_data_cdc_from <= (others => '0');
-- elsif(wvalid_re = '1')then
-- wr_data_cdc_from <= wdata;
-- end if;
-- end if;
-- end process WRDATA_S_H;
-- Flag that data has been captured
REG_IP_DATA_CAP : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0' or rdy_shut = '1')then
ip_data_cap <= '0';
elsif(ip_wvalid_re = '1')then
ip_data_cap <= '1';
end if;
end if;
end process REG_IP_DATA_CAP;
-- Must have both a valid address and valid data before updating
-- a register. Note in AXI write address can come before or
-- after AXI write data.
axi2ip_wren <= rdy;
-- axi2ip_wren <= '1' when ip_data_cap = '1' and ip_addr_cap = '1'
-- else '0';
-------------------------------------------------------------------------------
-- Decode and assert proper chip enable per captured axi lite write address
-------------------------------------------------------------------------------
WRCE_GEN: for j in 0 to C_NUM_CE - 1 generate
constant BAR : std_logic_vector(CE_ADDR_SIZE-1 downto 0) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
wrce(j) <= axi2ip_wren when awaddr_d1_cdc_tig
((CE_ADDR_SIZE + ADDR_OFFSET) - 1
downto ADDR_OFFSET)
= BAR(CE_ADDR_SIZE-1 downto 0)
else '0';
end generate WRCE_GEN;
-------------------------------------------------------------------------------
-- register write ce's and data out to axi dma register module
-------------------------------------------------------------------------------
REG_WR_OUT : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
axi2ip_wrce <= (others => '0');
else
axi2ip_wrce <= wrce;
end if;
end if;
end process REG_WR_OUT;
axi2ip_wrdata <= axi2ip_wrdata_cdc_tig; --s_axi_lite_wdata;
--*************************************************************************
--** Write Response Support
--*************************************************************************
-- Minimum of 2 IP clocks for addr and data capture, therefore delaying
-- Lite clock addr and data capture by 2 Lite clocks will guarenttee bvalid
-- responce occurs after write data acutally written.
-- REG_ALIGN_CAP : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- if(s_axi_lite_aresetn = '0')then
-- lite_data_cap_d1 <= '0';
-- lite_data_cap_d2 <= '0';
-- lite_addr_cap_d1 <= '0';
-- lite_addr_cap_d2 <= '0';
-- else
-- lite_data_cap_d1 <= rdy; --wr_data_cap;
-- lite_data_cap_d2 <= lite_data_cap_d1;
-- lite_addr_cap_d1 <= rdy; --wr_addr_cap;
-- lite_addr_cap_d2 <= lite_addr_cap_d1;
-- end if;
-- end if;
-- end process REG_ALIGN_CAP;
-- Pseudo write enable used simply to assert bvalid
-- lite_axi2ip_wren <= rdy; --'1' when wr_data_cap = '1' and wr_addr_cap = '1'
-- else '0';
WRESP_PROCESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
bvalid_i <= '0';
rst_wvalid_re <= '0'; -- CR576999
-- If response issued and target indicates ready then
-- clear response
elsif(bvalid_i = '1' and s_axi_lite_bready = '1')then
bvalid_i <= '0';
rst_wvalid_re <= '0'; -- CR576999
-- Issue a resonse on write
elsif(rdy_out = '1')then
-- elsif(lite_axi2ip_wren = '1')then
bvalid_i <= '1';
rst_wvalid_re <= '1'; -- CR576999
end if;
end if;
end process WRESP_PROCESS;
s_axi_lite_bresp <= OKAY_RESP;
end generate GEN_ASYNC_WRITE;
--*****************************************************************************
--** AXI LITE READ
--*****************************************************************************
-------------------------------------------------------------------------------
-- Assert Read Adddress Ready Handshake
-- Capture rising edge of valid and register out as ready. This creates
-- a 3 clock cycle address phase but also registers all inputs and outputs.
-- Note : Single clock cycle address phase can be accomplished using
-- combinatorial logic.
-------------------------------------------------------------------------------
REG_ARVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_rvalid_re = '1')then
arvalid_d1 <= '0';
else
arvalid_d1 <= arvalid;
end if;
end if;
end process REG_ARVALID;
arvalid_re <= arvalid and not arvalid_d1
and not rst_rvalid_re and not read_in_progress; -- CR607165
-- register for proper alignment
REG_ARREADY : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
arready_i <= '0';
else
arready_i <= arvalid_re;
end if;
end if;
end process REG_ARREADY;
-- Always respond 'okay' axi lite read
s_axi_lite_rresp <= OKAY_RESP;
s_axi_lite_rvalid <= s_axi_lite_rvalid_i;
-- s_axi_lite_aclk is synchronous to ip clock
GEN_SYNC_READ : if C_AXI_LITE_IS_ASYNC = 0 generate
begin
read_in_progress <= '0'; --Not used for sync mode (CR607165)
-------------------------------------------------------------------------------
-- Capture Read Address
-------------------------------------------------------------------------------
REG_READ_ADDRESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
axi2ip_rdaddr_i <= (others => '0');
-- Register address on valid
elsif(arvalid_re = '1')then
axi2ip_rdaddr_i <= araddr;
end if;
end if;
end process REG_READ_ADDRESS;
-------------------------------------------------------------------------------
-- Generate RdCE based on address match to address bar
-------------------------------------------------------------------------------
RDCE_GEN: for j in 0 to C_NUM_CE - 1 generate
constant BAR : std_logic_vector(CE_ADDR_SIZE-1 downto 0) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
rdce(j) <= arvalid_re_d1
when axi2ip_rdaddr_i((CE_ADDR_SIZE + ADDR_OFFSET) - 1
downto ADDR_OFFSET)
= BAR(CE_ADDR_SIZE-1 downto 0)
else '0';
end generate RDCE_GEN;
-------------------------------------------------------------------------------
-- Register out to IP
-------------------------------------------------------------------------------
REG_RDCNTRL_OUT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
--axi2ip_rdce <= (others => '0');
axi2ip_rdaddr <= (others => '0');
else
--axi2ip_rdce <= rdce;
axi2ip_rdaddr <= axi2ip_rdaddr_i;
end if;
end if;
end process REG_RDCNTRL_OUT;
-- Sample and hold rdce value until rvalid assertion
REG_RDCE_OUT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_rvalid_re = '1')then
axi2ip_rdce <= (others => '0');
elsif(arvalid_re_d1 = '1')then
axi2ip_rdce <= rdce;
end if;
end if;
end process REG_RDCE_OUT;
-- Register for proper alignment
REG_RVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
arvalid_re_d1 <= '0';
rvalid <= '0';
else
arvalid_re_d1 <= arvalid_re;
rvalid <= arvalid_re_d1;
end if;
end if;
end process REG_RVALID;
-------------------------------------------------------------------------------
-- Drive read data and read data valid out on capture of valid address.
-------------------------------------------------------------------------------
REG_RD_OUT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
s_axi_lite_rdata <= (others => '0');
s_axi_lite_rvalid_i <= '0';
rst_rvalid_re <= '0'; -- CR576999
-- If rvalid driving out to target and target indicates ready
-- then de-assert rvalid. (structure guarentees min 1 clock of rvalid)
elsif(s_axi_lite_rvalid_i = '1' and s_axi_lite_rready = '1')then
s_axi_lite_rdata <= (others => '0');
s_axi_lite_rvalid_i <= '0';
rst_rvalid_re <= '0'; -- CR576999
-- If read cycle then assert rvalid and rdata out to target
elsif(rvalid = '1')then
s_axi_lite_rdata <= ip2axi_rddata;
s_axi_lite_rvalid_i <= '1';
rst_rvalid_re <= '1'; -- CR576999
end if;
end if;
end process REG_RD_OUT;
end generate GEN_SYNC_READ;
-- s_axi_lite_aclk is asynchronous to ip clock
GEN_ASYNC_READ : if C_AXI_LITE_IS_ASYNC = 1 generate
ATTRIBUTE async_reg : STRING;
signal ip_arvalid_d1_cdc_tig : std_logic := '0';
signal ip_arvalid_d2 : std_logic := '0';
signal ip_arvalid_d3 : std_logic := '0';
signal ip_arvalid_re : std_logic := '0';
signal araddr_d1_cdc_tig : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) :=(others => '0');
signal araddr_d2 : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) :=(others => '0');
signal araddr_d3 : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) :=(others => '0');
signal lite_rdata_cdc_from : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) :=(others => '0');
signal lite_rdata_d1_cdc_to : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) :=(others => '0');
signal lite_rdata_d2 : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) :=(others => '0');
--ATTRIBUTE async_reg OF ip_arvalid_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF ip_arvalid_d2 : SIGNAL IS "true";
--ATTRIBUTE async_reg OF araddr_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF araddr_d2 : SIGNAL IS "true";
--ATTRIBUTE async_reg OF lite_rdata_d1_cdc_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF lite_rdata_d2 : SIGNAL IS "true";
signal p_pulse_s_h : std_logic := '0';
signal p_pulse_s_h_clr : std_logic := '0';
signal s_pulse_d1 : std_logic := '0';
signal s_pulse_d2 : std_logic := '0';
signal s_pulse_d3 : std_logic := '0';
signal s_pulse_re : std_logic := '0';
signal p_pulse_re_d1 : std_logic := '0';
signal p_pulse_re_d2 : std_logic := '0';
signal p_pulse_re_d3 : std_logic := '0';
signal arready_d1 : std_logic := '0'; -- CR605883
signal arready_d2 : std_logic := '0'; -- CR605883
signal arready_d3 : std_logic := '0'; -- CR605883
signal arready_d4 : std_logic := '0'; -- CR605883
signal arready_d5 : std_logic := '0'; -- CR605883
signal arready_d6 : std_logic := '0'; -- CR605883
signal arready_d7 : std_logic := '0'; -- CR605883
signal arready_d8 : std_logic := '0'; -- CR605883
signal arready_d9 : std_logic := '0'; -- CR605883
signal arready_d10 : std_logic := '0'; -- CR605883
signal arready_d11 : std_logic := '0'; -- CR605883
signal arready_d12 : std_logic := '0'; -- CR605883
begin
-- CR607165
-- Flag to prevent overlapping reads
RD_PROGRESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_rvalid_re = '1')then
read_in_progress <= '0';
elsif(arvalid_re = '1')then
read_in_progress <= '1';
end if;
end if;
end process RD_PROGRESS;
-- Double register address in
REG_RADDR_TO_IPCLK : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => s_axi_lite_araddr,
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => araddr_d3
);
-- REG_RADDR_TO_IPCLK : process(ip2axi_aclk)
-- begin
-- if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
-- if(ip2axi_aresetn = '0')then
-- araddr_d1_cdc_tig <= (others => '0');
-- araddr_d2 <= (others => '0');
-- araddr_d3 <= (others => '0');
-- else
-- araddr_d1_cdc_tig <= s_axi_lite_araddr;
-- araddr_d2 <= araddr_d1_cdc_tig;
-- araddr_d3 <= araddr_d2;
-- end if;
-- end if;
-- end process REG_RADDR_TO_IPCLK;
-- Latch and hold read address
REG_ARADDR_PROCESS : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
axi2ip_rdaddr_i <= (others => '0');
elsif(ip_arvalid_re = '1')then
axi2ip_rdaddr_i <= araddr_d3;
end if;
end if;
end process REG_ARADDR_PROCESS;
axi2ip_rdaddr <= axi2ip_rdaddr_i;
-- Register awready into IP clock domain. awready
-- is a 1 axi_lite clock delay of the rising edge of
-- arvalid. This provides a signal that asserts when
-- araddr is known to be stable.
REG_ARVALID_TO_IPCLK : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => arready_i,
prmry_vect_in => (others => '0'),
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => ip_arvalid_d2,
scndry_vect_out => open
);
REG_ARVALID_TO_IPCLK1 : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
-- ip_arvalid_d1_cdc_tig <= '0';
-- ip_arvalid_d2 <= '0';
ip_arvalid_d3 <= '0';
else
-- ip_arvalid_d1_cdc_tig <= arready_i;
-- ip_arvalid_d2 <= ip_arvalid_d1_cdc_tig;
ip_arvalid_d3 <= ip_arvalid_d2;
end if;
end if;
end process REG_ARVALID_TO_IPCLK1;
ip_arvalid_re <= ip_arvalid_d2 and not ip_arvalid_d3;
-------------------------------------------------------------------------------
-- Generate Read CE's
-------------------------------------------------------------------------------
RDCE_GEN: for j in 0 to C_NUM_CE - 1 generate
constant BAR : std_logic_vector(CE_ADDR_SIZE-1 downto 0) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
rdce(j) <= ip_arvalid_re
when araddr_d3((CE_ADDR_SIZE + ADDR_OFFSET) - 1
downto ADDR_OFFSET)
= BAR(CE_ADDR_SIZE-1 downto 0)
else '0';
end generate RDCE_GEN;
-------------------------------------------------------------------------------
-- Register RDCE and RD Data out to IP
-------------------------------------------------------------------------------
REG_RDCNTRL_OUT : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
axi2ip_rdce <= (others => '0');
elsif(ip_arvalid_re = '1')then
axi2ip_rdce <= rdce;
else
axi2ip_rdce <= (others => '0');
end if;
end if;
end process REG_RDCNTRL_OUT;
-- Generate sample and hold pulse to capture read data from IP
REG_RVALID : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
rvalid <= '0';
else
rvalid <= ip_arvalid_re;
end if;
end if;
end process REG_RVALID;
-------------------------------------------------------------------------------
-- Sample and hold read data from IP
-------------------------------------------------------------------------------
S_H_READ_DATA : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
lite_rdata_cdc_from <= (others => '0');
-- If read cycle then assert rvalid and rdata out to target
elsif(rvalid = '1')then
lite_rdata_cdc_from <= ip2axi_rddata;
end if;
end if;
end process S_H_READ_DATA;
-- Cross read data to axi_lite clock domain
REG_DATA2LITE_CLOCK : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => ip2axi_aclk,
prmry_resetn => '0',
prmry_in => '0', --lite_rdata_cdc_from,
prmry_vect_in => lite_rdata_cdc_from,
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '0',
scndry_out => open, --lite_rdata_d2,
scndry_vect_out => lite_rdata_d2
);
-- REG_DATA2LITE_CLOCK : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- if(s_axi_lite_aresetn = '0')then
-- lite_rdata_d1_cdc_to <= (others => '0');
-- lite_rdata_d2 <= (others => '0');
-- else
-- lite_rdata_d1_cdc_to <= lite_rdata_cdc_from;
-- lite_rdata_d2 <= lite_rdata_d1_cdc_to;
-- end if;
-- end if;
-- end process REG_DATA2LITE_CLOCK;
-- CR605883 (CDC) modified to remove
-- Because axi_lite_aclk must be less than or equal to ip2axi_aclk
-- then read data will appear a maximum 6 clocks from assertion
-- of arready.
REG_ALIGN_RDATA_LATCH : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
arready_d1 <= '0';
arready_d2 <= '0';
arready_d3 <= '0';
arready_d4 <= '0';
arready_d5 <= '0';
arready_d6 <= '0';
arready_d7 <= '0';
arready_d8 <= '0';
arready_d9 <= '0';
arready_d10 <= '0';
arready_d11 <= '0';
arready_d12 <= '0';
else
arready_d1 <= arready_i;
arready_d2 <= arready_d1;
arready_d3 <= arready_d2;
arready_d4 <= arready_d3;
arready_d5 <= arready_d4;
arready_d6 <= arready_d5;
arready_d7 <= arready_d6;
arready_d8 <= arready_d7;
arready_d9 <= arready_d8;
arready_d10 <= arready_d9;
arready_d11 <= arready_d10;
arready_d12 <= arready_d11;
end if;
end if;
end process REG_ALIGN_RDATA_LATCH;
-------------------------------------------------------------------------------
-- Drive read data and read data valid out on capture of valid address.
-------------------------------------------------------------------------------
REG_RD_OUT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
s_axi_lite_rdata <= (others => '0');
s_axi_lite_rvalid_i <= '0';
rst_rvalid_re <= '0'; -- CR576999
-- If rvalid driving out to target and target indicates ready
-- then de-assert rvalid. (structure guarentees min 1 clock of rvalid)
elsif(s_axi_lite_rvalid_i = '1' and s_axi_lite_rready = '1')then
s_axi_lite_rdata <= (others => '0');
s_axi_lite_rvalid_i <= '0';
rst_rvalid_re <= '0'; -- CR576999
-- If read cycle then assert rvalid and rdata out to target
-- CR605883
--elsif(s_pulse_re = '1')then
elsif(arready_d12 = '1')then
s_axi_lite_rdata <= lite_rdata_d2;
s_axi_lite_rvalid_i <= '1';
rst_rvalid_re <= '1'; -- CR576999
end if;
end if;
end process REG_RD_OUT;
end generate GEN_ASYNC_READ;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_dma_lite_if
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_dma_lite_if.vhd
-- Description: This entity is AXI Lite Interface Module for the AXI DMA
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
library lib_pkg_v1_0;
library lib_cdc_v1_0;
use lib_pkg_v1_0.lib_pkg.clog2;
-------------------------------------------------------------------------------
entity axi_dma_lite_if is
generic(
C_NUM_CE : integer := 8 ;
C_AXI_LITE_IS_ASYNC : integer range 0 to 1 := 0 ;
C_S_AXI_LITE_ADDR_WIDTH : integer range 2 to 32 := 32 ;
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32
);
port (
-- Async clock input
ip2axi_aclk : in std_logic ; --
ip2axi_aresetn : in std_logic ; --
-----------------------------------------------------------------------
-- AXI Lite Control Interface
-----------------------------------------------------------------------
s_axi_lite_aclk : in std_logic ; --
s_axi_lite_aresetn : in std_logic ; --
--
-- AXI Lite Write Address Channel --
s_axi_lite_awvalid : in std_logic ; --
s_axi_lite_awready : out std_logic ; --
s_axi_lite_awaddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
--
-- AXI Lite Write Data Channel --
s_axi_lite_wvalid : in std_logic ; --
s_axi_lite_wready : out std_logic ; --
s_axi_lite_wdata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
--
-- AXI Lite Write Response Channel --
s_axi_lite_bresp : out std_logic_vector(1 downto 0) ; --
s_axi_lite_bvalid : out std_logic ; --
s_axi_lite_bready : in std_logic ; --
--
-- AXI Lite Read Address Channel --
s_axi_lite_arvalid : in std_logic ; --
s_axi_lite_arready : out std_logic ; --
s_axi_lite_araddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
s_axi_lite_rvalid : out std_logic ; --
s_axi_lite_rready : in std_logic ; --
s_axi_lite_rdata : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s_axi_lite_rresp : out std_logic_vector(1 downto 0) ; --
--
-- User IP Interface --
axi2ip_wrce : out std_logic_vector --
(C_NUM_CE-1 downto 0) ; --
axi2ip_wrdata : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
--
axi2ip_rdce : out std_logic_vector --
(C_NUM_CE-1 downto 0) ; --
axi2ip_rdaddr : out std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
ip2axi_rddata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) --
);
end axi_dma_lite_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_lite_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Register I/F Address offset
constant ADDR_OFFSET : integer := clog2(C_S_AXI_LITE_DATA_WIDTH/8);
-- Register I/F CE number
constant CE_ADDR_SIZE : integer := clog2(C_NUM_CE);
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- AXI Lite slave interface signals
signal awvalid : std_logic := '0';
signal awaddr : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal wvalid : std_logic := '0';
signal wdata : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal arvalid : std_logic := '0';
signal araddr : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal awvalid_d1 : std_logic := '0';
signal awvalid_re : std_logic := '0';
signal awready_i : std_logic := '0';
signal wvalid_d1 : std_logic := '0';
signal wvalid_re : std_logic := '0';
signal wready_i : std_logic := '0';
signal bvalid_i : std_logic := '0';
signal wr_addr_cap : std_logic := '0';
signal wr_data_cap : std_logic := '0';
-- AXI to IP interface signals
signal axi2ip_wraddr_i : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal axi2ip_wrdata_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal axi2ip_wren : std_logic := '0';
signal wrce : std_logic_vector(C_NUM_CE-1 downto 0);
signal rdce : std_logic_vector(C_NUM_CE-1 downto 0) := (others => '0');
signal arvalid_d1 : std_logic := '0';
signal arvalid_re : std_logic := '0';
signal arvalid_re_d1 : std_logic := '0';
signal arvalid_i : std_logic := '0';
signal arready_i : std_logic := '0';
signal rvalid : std_logic := '0';
signal axi2ip_rdaddr_i : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s_axi_lite_rvalid_i : std_logic := '0';
signal read_in_progress : std_logic := '0'; -- CR607165
signal rst_rvalid_re : std_logic := '0'; -- CR576999
signal rst_wvalid_re : std_logic := '0'; -- CR576999
signal rdy : std_logic := '0';
signal rdy1 : std_logic := '0';
signal wr_in_progress : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
--*****************************************************************************
--** AXI LITE READ
--*****************************************************************************
s_axi_lite_wready <= wready_i;
s_axi_lite_awready <= awready_i;
s_axi_lite_arready <= arready_i;
s_axi_lite_bvalid <= bvalid_i;
-------------------------------------------------------------------------------
-- Register AXI Inputs
-------------------------------------------------------------------------------
REG_INPUTS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
awvalid <= '0' ;
awaddr <= (others => '0') ;
wvalid <= '0' ;
wdata <= (others => '0') ;
arvalid <= '0' ;
araddr <= (others => '0') ;
else
awvalid <= s_axi_lite_awvalid ;
awaddr <= s_axi_lite_awaddr ;
wvalid <= s_axi_lite_wvalid ;
wdata <= s_axi_lite_wdata ;
arvalid <= s_axi_lite_arvalid ;
araddr <= s_axi_lite_araddr ;
end if;
end if;
end process REG_INPUTS;
-- s_axi_lite_aclk is synchronous to ip clock
GEN_SYNC_WRITE : if C_AXI_LITE_IS_ASYNC = 0 generate
begin
-------------------------------------------------------------------------------
-- Assert Write Adddress Ready Handshake
-- Capture rising edge of valid and register out as ready. This creates
-- a 3 clock cycle address phase but also registers all inputs and outputs.
-- Note : Single clock cycle address phase can be accomplished using
-- combinatorial logic.
-------------------------------------------------------------------------------
REG_AWVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
awvalid_d1 <= '0';
-- awvalid_re <= '0'; -- CR605883
else
awvalid_d1 <= awvalid;
-- awvalid_re <= awvalid and not awvalid_d1; -- CR605883
end if;
end if;
end process REG_AWVALID;
awvalid_re <= awvalid and not awvalid_d1 and (not (wr_in_progress)); -- CR605883
-------------------------------------------------------------------------------
-- Capture assertion of awvalid to indicate that we have captured
-- a valid address
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Assert Write Data Ready Handshake
-- Capture rising edge of valid and register out as ready. This creates
-- a 3 clock cycle address phase but also registers all inputs and outputs.
-- Note : Single clock cycle address phase can be accomplished using
-- combinatorial logic.
-------------------------------------------------------------------------------
REG_WVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
wvalid_d1 <= '0';
-- wvalid_re <= '0';
else
wvalid_d1 <= wvalid;
-- wvalid_re <= wvalid and not wvalid_d1; -- CR605883
end if;
end if;
end process REG_WVALID;
wvalid_re <= wvalid and not wvalid_d1; -- CR605883
WRITE_IN_PROGRESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
wr_in_progress <= '0';
elsif(awvalid_re = '1')then
wr_in_progress <= '1';
end if;
end if;
end process WRITE_IN_PROGRESS;
-- CR605883 (CDC) provide pure register output to synchronizers
--wvalid_re <= wvalid and not wvalid_d1 and not rst_wvalid_re;
-------------------------------------------------------------------------------
-- Capture assertion of wvalid to indicate that we have captured
-- valid data
-------------------------------------------------------------------------------
WRDATA_CAP_FLAG : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rdy = '1')then
wr_data_cap <= '0';
elsif(wvalid_re = '1')then
wr_data_cap <= '1';
end if;
end if;
end process WRDATA_CAP_FLAG;
REG_WREADY : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rdy = '1') then
rdy <= '0';
elsif (wr_data_cap = '1' and wr_addr_cap = '1') then
rdy <= '1';
end if;
wready_i <= rdy;
awready_i <= rdy;
rdy1 <= rdy;
end if;
end process REG_WREADY;
WRADDR_CAP_FLAG : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rdy = '1')then
wr_addr_cap <= '0';
elsif(awvalid_re = '1')then
wr_addr_cap <= '1';
end if;
end if;
end process WRADDR_CAP_FLAG;
-------------------------------------------------------------------------------
-- Capture Write Address
-------------------------------------------------------------------------------
REG_WRITE_ADDRESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
-- axi2ip_wraddr_i <= (others => '0');
-- Register address on valid
elsif(awvalid_re = '1')then
-- axi2ip_wraddr_i <= awaddr;
end if;
end if;
end process REG_WRITE_ADDRESS;
-------------------------------------------------------------------------------
-- Capture Write Data
-------------------------------------------------------------------------------
REG_WRITE_DATA : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
axi2ip_wrdata_i <= (others => '0');
-- Register address and assert ready
elsif(wvalid_re = '1')then
axi2ip_wrdata_i <= wdata;
end if;
end if;
end process REG_WRITE_DATA;
-------------------------------------------------------------------------------
-- Must have both a valid address and valid data before updating
-- a register. Note in AXI write address can come before or
-- after AXI write data.
-- axi2ip_wren <= '1' when wr_data_cap = '1' and wr_addr_cap = '1'
-- else '0';
axi2ip_wren <= rdy; -- or rdy1;
-------------------------------------------------------------------------------
-- Decode and assert proper chip enable per captured axi lite write address
-------------------------------------------------------------------------------
WRCE_GEN: for j in 0 to C_NUM_CE - 1 generate
constant BAR : std_logic_vector(CE_ADDR_SIZE-1 downto 0) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
wrce(j) <= axi2ip_wren when s_axi_lite_awaddr
((CE_ADDR_SIZE + ADDR_OFFSET) - 1
downto ADDR_OFFSET)
= BAR(CE_ADDR_SIZE-1 downto 0)
else '0';
end generate WRCE_GEN;
-------------------------------------------------------------------------------
-- register write ce's and data out to axi dma register module
-------------------------------------------------------------------------------
REG_WR_OUT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
axi2ip_wrce <= (others => '0');
-- axi2ip_wrdata <= (others => '0');
else
axi2ip_wrce <= wrce;
-- axi2ip_wrdata <= axi2ip_wrdata_i;
end if;
end if;
end process REG_WR_OUT;
axi2ip_wrdata <= s_axi_lite_wdata;
-------------------------------------------------------------------------------
-- Write Response
-------------------------------------------------------------------------------
s_axi_lite_bresp <= OKAY_RESP;
WRESP_PROCESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
bvalid_i <= '0';
rst_wvalid_re <= '0'; -- CR576999
-- If response issued and target indicates ready then
-- clear response
elsif(bvalid_i = '1' and s_axi_lite_bready = '1')then
bvalid_i <= '0';
rst_wvalid_re <= '0'; -- CR576999
-- Issue a resonse on write
elsif(rdy1 = '1')then
bvalid_i <= '1';
rst_wvalid_re <= '1'; -- CR576999
end if;
end if;
end process WRESP_PROCESS;
end generate GEN_SYNC_WRITE;
-- s_axi_lite_aclk is asynchronous to ip clock
GEN_ASYNC_WRITE : if C_AXI_LITE_IS_ASYNC = 1 generate
-- Data support
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
signal ip_wvalid_d1_cdc_to : std_logic := '0';
signal ip_wvalid_d2 : std_logic := '0';
signal ip_wvalid_re : std_logic := '0';
signal wr_wvalid_re_cdc_from : std_logic := '0';
signal wr_data_cdc_from : std_logic_vector -- CR605883
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); -- CR605883
signal wdata_d1_cdc_to : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal wdata_d2 : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal axi2ip_wrdata_cdc_tig : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal ip_data_cap : std_logic := '0';
-- Address support
signal ip_awvalid_d1_cdc_to : std_logic := '0';
signal ip_awvalid_d2 : std_logic := '0';
signal ip_awvalid_re : std_logic := '0';
signal wr_awvalid_re_cdc_from : std_logic := '0';
signal wr_addr_cdc_from : std_logic_vector -- CR605883
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0'); -- CR605883
signal awaddr_d1_cdc_tig : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal awaddr_d2 : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ip_addr_cap : std_logic := '0';
-- Bvalid support
signal lite_data_cap_d1 : std_logic := '0';
signal lite_data_cap_d2 : std_logic := '0';
signal lite_addr_cap_d1 : std_logic := '0';
signal lite_addr_cap_d2 : std_logic := '0';
signal lite_axi2ip_wren : std_logic := '0';
signal awvalid_cdc_from : std_logic := '0';
signal awvalid_cdc_to : std_logic := '0';
signal awvalid_to : std_logic := '0';
signal awvalid_to2 : std_logic := '0';
--ATTRIBUTE async_reg OF awvalid_cdc_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF awvalid_to : SIGNAL IS "true";
signal wvalid_cdc_from : std_logic := '0';
signal wvalid_cdc_to : std_logic := '0';
signal wvalid_to : std_logic := '0';
signal wvalid_to2 : std_logic := '0';
--ATTRIBUTE async_reg OF wvalid_cdc_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF wvalid_to : SIGNAL IS "true";
signal rdy_cdc_to : std_logic := '0';
signal rdy_cdc_from : std_logic := '0';
signal rdy_to : std_logic := '0';
signal rdy_to2 : std_logic := '0';
signal rdy_to2_cdc_from : std_logic := '0';
signal rdy_out : std_logic := '0';
--ATTRIBUTE async_reg OF rdy_cdc_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF rdy_to : SIGNAL IS "true";
Attribute KEEP of rdy_to2_cdc_from : signal is "TRUE";
Attribute EQUIVALENT_REGISTER_REMOVAL of rdy_to2_cdc_from : signal is "no";
signal rdy_back_cdc_to : std_logic := '0';
signal rdy_back_to : std_logic :='0';
--ATTRIBUTE async_reg OF rdy_back_cdc_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF rdy_back_to : SIGNAL IS "true";
signal rdy_back : std_logic := '0';
signal rdy_shut : std_logic := '0';
begin
REG_AWVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
awvalid_d1 <= '0';
else
awvalid_d1 <= awvalid;
end if;
end if;
end process REG_AWVALID;
awvalid_re <= awvalid and not awvalid_d1 and (not (wr_in_progress)); -- CR605883
-------------------------------------------------------------------------------
-- Capture assertion of awvalid to indicate that we have captured
-- a valid address
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Assert Write Data Ready Handshake
-- Capture rising edge of valid and register out as ready. This creates
-- a 3 clock cycle address phase but also registers all inputs and outputs.
-- Note : Single clock cycle address phase can be accomplished using
-- combinatorial logic.
-------------------------------------------------------------------------------
REG_WVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
wvalid_d1 <= '0';
else
wvalid_d1 <= wvalid;
end if;
end if;
end process REG_WVALID;
wvalid_re <= wvalid and not wvalid_d1; -- CR605883
--*************************************************************************
--** Write Address Support
--*************************************************************************
AWVLD_CDC_FROM : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
awvalid_cdc_from <= '0';
elsif(awvalid_re = '1')then
awvalid_cdc_from <= '1';
end if;
end if;
end process AWVLD_CDC_FROM;
AWVLD_CDC_TO : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => awvalid_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => awvalid_to,
scndry_vect_out => open
);
-- AWVLD_CDC_TO : process(ip2axi_aclk)
-- begin
-- if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
-- awvalid_cdc_to <= awvalid_cdc_from;
-- awvalid_to <= awvalid_cdc_to;
-- end if;
-- end process AWVLD_CDC_TO;
AWVLD_CDC_TO2 : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
awvalid_to2 <= '0';
else
awvalid_to2 <= awvalid_to;
end if;
end if;
end process AWVLD_CDC_TO2;
ip_awvalid_re <= awvalid_to and (not awvalid_to2);
WVLD_CDC_FROM : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
wvalid_cdc_from <= '0';
elsif(wvalid_re = '1')then
wvalid_cdc_from <= '1';
end if;
end if;
end process WVLD_CDC_FROM;
WVLD_CDC_TO : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => wvalid_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => wvalid_to,
scndry_vect_out => open
);
-- WVLD_CDC_TO : process(ip2axi_aclk)
-- begin
-- if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
-- wvalid_cdc_to <= wvalid_cdc_from;
-- wvalid_to <= wvalid_cdc_to;
-- end if;
-- end process WVLD_CDC_TO;
WVLD_CDC_TO2 : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
wvalid_to2 <= '0';
else
wvalid_to2 <= wvalid_to;
end if;
end if;
end process WVLD_CDC_TO2;
ip_wvalid_re <= wvalid_to and (not wvalid_to2);
REG_WADDR_TO_IPCLK : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH,
C_MTBF_STAGES => 1
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => s_axi_lite_awaddr,
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => awaddr_d1_cdc_tig
);
REG_WADDR_TO_IPCLK1 : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_S_AXI_LITE_DATA_WIDTH,
C_MTBF_STAGES => 1
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => s_axi_lite_wdata,
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => axi2ip_wrdata_cdc_tig
);
-- Double register address in
-- REG_WADDR_TO_IPCLK : process(ip2axi_aclk)
-- begin
-- if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
-- if(ip2axi_aresetn = '0')then
-- awaddr_d1_cdc_tig <= (others => '0');
-- -- axi2ip_wraddr_i <= (others => '0');
-- axi2ip_wrdata_cdc_tig <= (others => '0');
-- else
-- awaddr_d1_cdc_tig <= s_axi_lite_awaddr;
-- axi2ip_wrdata_cdc_tig <= s_axi_lite_wdata;
-- -- axi2ip_wraddr_i <= awaddr_d1_cdc_tig; -- CR605883
-- end if;
-- end if;
-- end process REG_WADDR_TO_IPCLK;
-- Flag that address has been captured
REG_IP_ADDR_CAP : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0' or rdy_shut = '1')then
ip_addr_cap <= '0';
elsif(ip_awvalid_re = '1')then
ip_addr_cap <= '1';
end if;
end if;
end process REG_IP_ADDR_CAP;
REG_WREADY : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0' or rdy_shut = '1') then -- or rdy = '1') then
rdy <= '0';
elsif (ip_data_cap = '1' and ip_addr_cap = '1') then
rdy <= '1';
end if;
end if;
end process REG_WREADY;
REG3_WREADY : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => rdy_to2_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => rdy_back_to,
scndry_vect_out => open
);
-- REG3_WREADY : process(ip2axi_aclk)
-- begin
-- if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
-- rdy_back_cdc_to <= rdy_to2_cdc_from;
-- rdy_back_to <= rdy_back_cdc_to;
-- end if;
-- end process REG3_WREADY;
REG3_WREADY2 : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0') then
rdy_back <= '0';
else
rdy_back <= rdy_back_to;
end if;
end if;
end process REG3_WREADY2;
rdy_shut <= rdy_back_to and (not rdy_back);
REG1_WREADY : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0' or rdy_shut = '1') then
rdy_cdc_from <= '0';
elsif (rdy = '1') then
rdy_cdc_from <= '1';
end if;
end if;
end process REG1_WREADY;
REG2_WREADY : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => ip2axi_aclk,
prmry_resetn => '0',
prmry_in => rdy_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '0',
scndry_out => rdy_to,
scndry_vect_out => open
);
-- REG2_WREADY : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- rdy_cdc_to <= rdy_cdc_from;
-- rdy_to <= rdy_cdc_to;
-- end if;
-- end process REG2_WREADY;
REG2_WREADY2 : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0') then
rdy_to2 <= '0';
rdy_to2_cdc_from <= '0';
else
rdy_to2 <= rdy_to;
rdy_to2_cdc_from <= rdy_to;
end if;
end if;
end process REG2_WREADY2;
rdy_out <= not (rdy_to) and rdy_to2;
wready_i <= rdy_out;
awready_i <= rdy_out;
--*************************************************************************
--** Write Data Support
--*************************************************************************
-------------------------------------------------------------------------------
-- Capture write data
-------------------------------------------------------------------------------
-- WRDATA_S_H : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- if(s_axi_lite_aresetn = '0')then
-- wr_data_cdc_from <= (others => '0');
-- elsif(wvalid_re = '1')then
-- wr_data_cdc_from <= wdata;
-- end if;
-- end if;
-- end process WRDATA_S_H;
-- Flag that data has been captured
REG_IP_DATA_CAP : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0' or rdy_shut = '1')then
ip_data_cap <= '0';
elsif(ip_wvalid_re = '1')then
ip_data_cap <= '1';
end if;
end if;
end process REG_IP_DATA_CAP;
-- Must have both a valid address and valid data before updating
-- a register. Note in AXI write address can come before or
-- after AXI write data.
axi2ip_wren <= rdy;
-- axi2ip_wren <= '1' when ip_data_cap = '1' and ip_addr_cap = '1'
-- else '0';
-------------------------------------------------------------------------------
-- Decode and assert proper chip enable per captured axi lite write address
-------------------------------------------------------------------------------
WRCE_GEN: for j in 0 to C_NUM_CE - 1 generate
constant BAR : std_logic_vector(CE_ADDR_SIZE-1 downto 0) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
wrce(j) <= axi2ip_wren when awaddr_d1_cdc_tig
((CE_ADDR_SIZE + ADDR_OFFSET) - 1
downto ADDR_OFFSET)
= BAR(CE_ADDR_SIZE-1 downto 0)
else '0';
end generate WRCE_GEN;
-------------------------------------------------------------------------------
-- register write ce's and data out to axi dma register module
-------------------------------------------------------------------------------
REG_WR_OUT : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
axi2ip_wrce <= (others => '0');
else
axi2ip_wrce <= wrce;
end if;
end if;
end process REG_WR_OUT;
axi2ip_wrdata <= axi2ip_wrdata_cdc_tig; --s_axi_lite_wdata;
--*************************************************************************
--** Write Response Support
--*************************************************************************
-- Minimum of 2 IP clocks for addr and data capture, therefore delaying
-- Lite clock addr and data capture by 2 Lite clocks will guarenttee bvalid
-- responce occurs after write data acutally written.
-- REG_ALIGN_CAP : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- if(s_axi_lite_aresetn = '0')then
-- lite_data_cap_d1 <= '0';
-- lite_data_cap_d2 <= '0';
-- lite_addr_cap_d1 <= '0';
-- lite_addr_cap_d2 <= '0';
-- else
-- lite_data_cap_d1 <= rdy; --wr_data_cap;
-- lite_data_cap_d2 <= lite_data_cap_d1;
-- lite_addr_cap_d1 <= rdy; --wr_addr_cap;
-- lite_addr_cap_d2 <= lite_addr_cap_d1;
-- end if;
-- end if;
-- end process REG_ALIGN_CAP;
-- Pseudo write enable used simply to assert bvalid
-- lite_axi2ip_wren <= rdy; --'1' when wr_data_cap = '1' and wr_addr_cap = '1'
-- else '0';
WRESP_PROCESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
bvalid_i <= '0';
rst_wvalid_re <= '0'; -- CR576999
-- If response issued and target indicates ready then
-- clear response
elsif(bvalid_i = '1' and s_axi_lite_bready = '1')then
bvalid_i <= '0';
rst_wvalid_re <= '0'; -- CR576999
-- Issue a resonse on write
elsif(rdy_out = '1')then
-- elsif(lite_axi2ip_wren = '1')then
bvalid_i <= '1';
rst_wvalid_re <= '1'; -- CR576999
end if;
end if;
end process WRESP_PROCESS;
s_axi_lite_bresp <= OKAY_RESP;
end generate GEN_ASYNC_WRITE;
--*****************************************************************************
--** AXI LITE READ
--*****************************************************************************
-------------------------------------------------------------------------------
-- Assert Read Adddress Ready Handshake
-- Capture rising edge of valid and register out as ready. This creates
-- a 3 clock cycle address phase but also registers all inputs and outputs.
-- Note : Single clock cycle address phase can be accomplished using
-- combinatorial logic.
-------------------------------------------------------------------------------
REG_ARVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_rvalid_re = '1')then
arvalid_d1 <= '0';
else
arvalid_d1 <= arvalid;
end if;
end if;
end process REG_ARVALID;
arvalid_re <= arvalid and not arvalid_d1
and not rst_rvalid_re and not read_in_progress; -- CR607165
-- register for proper alignment
REG_ARREADY : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
arready_i <= '0';
else
arready_i <= arvalid_re;
end if;
end if;
end process REG_ARREADY;
-- Always respond 'okay' axi lite read
s_axi_lite_rresp <= OKAY_RESP;
s_axi_lite_rvalid <= s_axi_lite_rvalid_i;
-- s_axi_lite_aclk is synchronous to ip clock
GEN_SYNC_READ : if C_AXI_LITE_IS_ASYNC = 0 generate
begin
read_in_progress <= '0'; --Not used for sync mode (CR607165)
-------------------------------------------------------------------------------
-- Capture Read Address
-------------------------------------------------------------------------------
REG_READ_ADDRESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
axi2ip_rdaddr_i <= (others => '0');
-- Register address on valid
elsif(arvalid_re = '1')then
axi2ip_rdaddr_i <= araddr;
end if;
end if;
end process REG_READ_ADDRESS;
-------------------------------------------------------------------------------
-- Generate RdCE based on address match to address bar
-------------------------------------------------------------------------------
RDCE_GEN: for j in 0 to C_NUM_CE - 1 generate
constant BAR : std_logic_vector(CE_ADDR_SIZE-1 downto 0) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
rdce(j) <= arvalid_re_d1
when axi2ip_rdaddr_i((CE_ADDR_SIZE + ADDR_OFFSET) - 1
downto ADDR_OFFSET)
= BAR(CE_ADDR_SIZE-1 downto 0)
else '0';
end generate RDCE_GEN;
-------------------------------------------------------------------------------
-- Register out to IP
-------------------------------------------------------------------------------
REG_RDCNTRL_OUT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
--axi2ip_rdce <= (others => '0');
axi2ip_rdaddr <= (others => '0');
else
--axi2ip_rdce <= rdce;
axi2ip_rdaddr <= axi2ip_rdaddr_i;
end if;
end if;
end process REG_RDCNTRL_OUT;
-- Sample and hold rdce value until rvalid assertion
REG_RDCE_OUT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_rvalid_re = '1')then
axi2ip_rdce <= (others => '0');
elsif(arvalid_re_d1 = '1')then
axi2ip_rdce <= rdce;
end if;
end if;
end process REG_RDCE_OUT;
-- Register for proper alignment
REG_RVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
arvalid_re_d1 <= '0';
rvalid <= '0';
else
arvalid_re_d1 <= arvalid_re;
rvalid <= arvalid_re_d1;
end if;
end if;
end process REG_RVALID;
-------------------------------------------------------------------------------
-- Drive read data and read data valid out on capture of valid address.
-------------------------------------------------------------------------------
REG_RD_OUT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
s_axi_lite_rdata <= (others => '0');
s_axi_lite_rvalid_i <= '0';
rst_rvalid_re <= '0'; -- CR576999
-- If rvalid driving out to target and target indicates ready
-- then de-assert rvalid. (structure guarentees min 1 clock of rvalid)
elsif(s_axi_lite_rvalid_i = '1' and s_axi_lite_rready = '1')then
s_axi_lite_rdata <= (others => '0');
s_axi_lite_rvalid_i <= '0';
rst_rvalid_re <= '0'; -- CR576999
-- If read cycle then assert rvalid and rdata out to target
elsif(rvalid = '1')then
s_axi_lite_rdata <= ip2axi_rddata;
s_axi_lite_rvalid_i <= '1';
rst_rvalid_re <= '1'; -- CR576999
end if;
end if;
end process REG_RD_OUT;
end generate GEN_SYNC_READ;
-- s_axi_lite_aclk is asynchronous to ip clock
GEN_ASYNC_READ : if C_AXI_LITE_IS_ASYNC = 1 generate
ATTRIBUTE async_reg : STRING;
signal ip_arvalid_d1_cdc_tig : std_logic := '0';
signal ip_arvalid_d2 : std_logic := '0';
signal ip_arvalid_d3 : std_logic := '0';
signal ip_arvalid_re : std_logic := '0';
signal araddr_d1_cdc_tig : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) :=(others => '0');
signal araddr_d2 : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) :=(others => '0');
signal araddr_d3 : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) :=(others => '0');
signal lite_rdata_cdc_from : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) :=(others => '0');
signal lite_rdata_d1_cdc_to : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) :=(others => '0');
signal lite_rdata_d2 : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) :=(others => '0');
--ATTRIBUTE async_reg OF ip_arvalid_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF ip_arvalid_d2 : SIGNAL IS "true";
--ATTRIBUTE async_reg OF araddr_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF araddr_d2 : SIGNAL IS "true";
--ATTRIBUTE async_reg OF lite_rdata_d1_cdc_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF lite_rdata_d2 : SIGNAL IS "true";
signal p_pulse_s_h : std_logic := '0';
signal p_pulse_s_h_clr : std_logic := '0';
signal s_pulse_d1 : std_logic := '0';
signal s_pulse_d2 : std_logic := '0';
signal s_pulse_d3 : std_logic := '0';
signal s_pulse_re : std_logic := '0';
signal p_pulse_re_d1 : std_logic := '0';
signal p_pulse_re_d2 : std_logic := '0';
signal p_pulse_re_d3 : std_logic := '0';
signal arready_d1 : std_logic := '0'; -- CR605883
signal arready_d2 : std_logic := '0'; -- CR605883
signal arready_d3 : std_logic := '0'; -- CR605883
signal arready_d4 : std_logic := '0'; -- CR605883
signal arready_d5 : std_logic := '0'; -- CR605883
signal arready_d6 : std_logic := '0'; -- CR605883
signal arready_d7 : std_logic := '0'; -- CR605883
signal arready_d8 : std_logic := '0'; -- CR605883
signal arready_d9 : std_logic := '0'; -- CR605883
signal arready_d10 : std_logic := '0'; -- CR605883
signal arready_d11 : std_logic := '0'; -- CR605883
signal arready_d12 : std_logic := '0'; -- CR605883
begin
-- CR607165
-- Flag to prevent overlapping reads
RD_PROGRESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_rvalid_re = '1')then
read_in_progress <= '0';
elsif(arvalid_re = '1')then
read_in_progress <= '1';
end if;
end if;
end process RD_PROGRESS;
-- Double register address in
REG_RADDR_TO_IPCLK : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => s_axi_lite_araddr,
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => araddr_d3
);
-- REG_RADDR_TO_IPCLK : process(ip2axi_aclk)
-- begin
-- if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
-- if(ip2axi_aresetn = '0')then
-- araddr_d1_cdc_tig <= (others => '0');
-- araddr_d2 <= (others => '0');
-- araddr_d3 <= (others => '0');
-- else
-- araddr_d1_cdc_tig <= s_axi_lite_araddr;
-- araddr_d2 <= araddr_d1_cdc_tig;
-- araddr_d3 <= araddr_d2;
-- end if;
-- end if;
-- end process REG_RADDR_TO_IPCLK;
-- Latch and hold read address
REG_ARADDR_PROCESS : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
axi2ip_rdaddr_i <= (others => '0');
elsif(ip_arvalid_re = '1')then
axi2ip_rdaddr_i <= araddr_d3;
end if;
end if;
end process REG_ARADDR_PROCESS;
axi2ip_rdaddr <= axi2ip_rdaddr_i;
-- Register awready into IP clock domain. awready
-- is a 1 axi_lite clock delay of the rising edge of
-- arvalid. This provides a signal that asserts when
-- araddr is known to be stable.
REG_ARVALID_TO_IPCLK : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => arready_i,
prmry_vect_in => (others => '0'),
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => ip_arvalid_d2,
scndry_vect_out => open
);
REG_ARVALID_TO_IPCLK1 : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
-- ip_arvalid_d1_cdc_tig <= '0';
-- ip_arvalid_d2 <= '0';
ip_arvalid_d3 <= '0';
else
-- ip_arvalid_d1_cdc_tig <= arready_i;
-- ip_arvalid_d2 <= ip_arvalid_d1_cdc_tig;
ip_arvalid_d3 <= ip_arvalid_d2;
end if;
end if;
end process REG_ARVALID_TO_IPCLK1;
ip_arvalid_re <= ip_arvalid_d2 and not ip_arvalid_d3;
-------------------------------------------------------------------------------
-- Generate Read CE's
-------------------------------------------------------------------------------
RDCE_GEN: for j in 0 to C_NUM_CE - 1 generate
constant BAR : std_logic_vector(CE_ADDR_SIZE-1 downto 0) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
rdce(j) <= ip_arvalid_re
when araddr_d3((CE_ADDR_SIZE + ADDR_OFFSET) - 1
downto ADDR_OFFSET)
= BAR(CE_ADDR_SIZE-1 downto 0)
else '0';
end generate RDCE_GEN;
-------------------------------------------------------------------------------
-- Register RDCE and RD Data out to IP
-------------------------------------------------------------------------------
REG_RDCNTRL_OUT : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
axi2ip_rdce <= (others => '0');
elsif(ip_arvalid_re = '1')then
axi2ip_rdce <= rdce;
else
axi2ip_rdce <= (others => '0');
end if;
end if;
end process REG_RDCNTRL_OUT;
-- Generate sample and hold pulse to capture read data from IP
REG_RVALID : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
rvalid <= '0';
else
rvalid <= ip_arvalid_re;
end if;
end if;
end process REG_RVALID;
-------------------------------------------------------------------------------
-- Sample and hold read data from IP
-------------------------------------------------------------------------------
S_H_READ_DATA : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
lite_rdata_cdc_from <= (others => '0');
-- If read cycle then assert rvalid and rdata out to target
elsif(rvalid = '1')then
lite_rdata_cdc_from <= ip2axi_rddata;
end if;
end if;
end process S_H_READ_DATA;
-- Cross read data to axi_lite clock domain
REG_DATA2LITE_CLOCK : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => ip2axi_aclk,
prmry_resetn => '0',
prmry_in => '0', --lite_rdata_cdc_from,
prmry_vect_in => lite_rdata_cdc_from,
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '0',
scndry_out => open, --lite_rdata_d2,
scndry_vect_out => lite_rdata_d2
);
-- REG_DATA2LITE_CLOCK : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- if(s_axi_lite_aresetn = '0')then
-- lite_rdata_d1_cdc_to <= (others => '0');
-- lite_rdata_d2 <= (others => '0');
-- else
-- lite_rdata_d1_cdc_to <= lite_rdata_cdc_from;
-- lite_rdata_d2 <= lite_rdata_d1_cdc_to;
-- end if;
-- end if;
-- end process REG_DATA2LITE_CLOCK;
-- CR605883 (CDC) modified to remove
-- Because axi_lite_aclk must be less than or equal to ip2axi_aclk
-- then read data will appear a maximum 6 clocks from assertion
-- of arready.
REG_ALIGN_RDATA_LATCH : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
arready_d1 <= '0';
arready_d2 <= '0';
arready_d3 <= '0';
arready_d4 <= '0';
arready_d5 <= '0';
arready_d6 <= '0';
arready_d7 <= '0';
arready_d8 <= '0';
arready_d9 <= '0';
arready_d10 <= '0';
arready_d11 <= '0';
arready_d12 <= '0';
else
arready_d1 <= arready_i;
arready_d2 <= arready_d1;
arready_d3 <= arready_d2;
arready_d4 <= arready_d3;
arready_d5 <= arready_d4;
arready_d6 <= arready_d5;
arready_d7 <= arready_d6;
arready_d8 <= arready_d7;
arready_d9 <= arready_d8;
arready_d10 <= arready_d9;
arready_d11 <= arready_d10;
arready_d12 <= arready_d11;
end if;
end if;
end process REG_ALIGN_RDATA_LATCH;
-------------------------------------------------------------------------------
-- Drive read data and read data valid out on capture of valid address.
-------------------------------------------------------------------------------
REG_RD_OUT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
s_axi_lite_rdata <= (others => '0');
s_axi_lite_rvalid_i <= '0';
rst_rvalid_re <= '0'; -- CR576999
-- If rvalid driving out to target and target indicates ready
-- then de-assert rvalid. (structure guarentees min 1 clock of rvalid)
elsif(s_axi_lite_rvalid_i = '1' and s_axi_lite_rready = '1')then
s_axi_lite_rdata <= (others => '0');
s_axi_lite_rvalid_i <= '0';
rst_rvalid_re <= '0'; -- CR576999
-- If read cycle then assert rvalid and rdata out to target
-- CR605883
--elsif(s_pulse_re = '1')then
elsif(arready_d12 = '1')then
s_axi_lite_rdata <= lite_rdata_d2;
s_axi_lite_rvalid_i <= '1';
rst_rvalid_re <= '1'; -- CR576999
end if;
end if;
end process REG_RD_OUT;
end generate GEN_ASYNC_READ;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_dma_lite_if
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_dma_lite_if.vhd
-- Description: This entity is AXI Lite Interface Module for the AXI DMA
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
library lib_pkg_v1_0;
library lib_cdc_v1_0;
use lib_pkg_v1_0.lib_pkg.clog2;
-------------------------------------------------------------------------------
entity axi_dma_lite_if is
generic(
C_NUM_CE : integer := 8 ;
C_AXI_LITE_IS_ASYNC : integer range 0 to 1 := 0 ;
C_S_AXI_LITE_ADDR_WIDTH : integer range 2 to 32 := 32 ;
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32
);
port (
-- Async clock input
ip2axi_aclk : in std_logic ; --
ip2axi_aresetn : in std_logic ; --
-----------------------------------------------------------------------
-- AXI Lite Control Interface
-----------------------------------------------------------------------
s_axi_lite_aclk : in std_logic ; --
s_axi_lite_aresetn : in std_logic ; --
--
-- AXI Lite Write Address Channel --
s_axi_lite_awvalid : in std_logic ; --
s_axi_lite_awready : out std_logic ; --
s_axi_lite_awaddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
--
-- AXI Lite Write Data Channel --
s_axi_lite_wvalid : in std_logic ; --
s_axi_lite_wready : out std_logic ; --
s_axi_lite_wdata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
--
-- AXI Lite Write Response Channel --
s_axi_lite_bresp : out std_logic_vector(1 downto 0) ; --
s_axi_lite_bvalid : out std_logic ; --
s_axi_lite_bready : in std_logic ; --
--
-- AXI Lite Read Address Channel --
s_axi_lite_arvalid : in std_logic ; --
s_axi_lite_arready : out std_logic ; --
s_axi_lite_araddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
s_axi_lite_rvalid : out std_logic ; --
s_axi_lite_rready : in std_logic ; --
s_axi_lite_rdata : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
s_axi_lite_rresp : out std_logic_vector(1 downto 0) ; --
--
-- User IP Interface --
axi2ip_wrce : out std_logic_vector --
(C_NUM_CE-1 downto 0) ; --
axi2ip_wrdata : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0); --
--
axi2ip_rdce : out std_logic_vector --
(C_NUM_CE-1 downto 0) ; --
axi2ip_rdaddr : out std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0); --
ip2axi_rddata : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) --
);
end axi_dma_lite_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_lite_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Register I/F Address offset
constant ADDR_OFFSET : integer := clog2(C_S_AXI_LITE_DATA_WIDTH/8);
-- Register I/F CE number
constant CE_ADDR_SIZE : integer := clog2(C_NUM_CE);
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- AXI Lite slave interface signals
signal awvalid : std_logic := '0';
signal awaddr : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal wvalid : std_logic := '0';
signal wdata : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal arvalid : std_logic := '0';
signal araddr : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal awvalid_d1 : std_logic := '0';
signal awvalid_re : std_logic := '0';
signal awready_i : std_logic := '0';
signal wvalid_d1 : std_logic := '0';
signal wvalid_re : std_logic := '0';
signal wready_i : std_logic := '0';
signal bvalid_i : std_logic := '0';
signal wr_addr_cap : std_logic := '0';
signal wr_data_cap : std_logic := '0';
-- AXI to IP interface signals
signal axi2ip_wraddr_i : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal axi2ip_wrdata_i : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal axi2ip_wren : std_logic := '0';
signal wrce : std_logic_vector(C_NUM_CE-1 downto 0);
signal rdce : std_logic_vector(C_NUM_CE-1 downto 0) := (others => '0');
signal arvalid_d1 : std_logic := '0';
signal arvalid_re : std_logic := '0';
signal arvalid_re_d1 : std_logic := '0';
signal arvalid_i : std_logic := '0';
signal arready_i : std_logic := '0';
signal rvalid : std_logic := '0';
signal axi2ip_rdaddr_i : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal s_axi_lite_rvalid_i : std_logic := '0';
signal read_in_progress : std_logic := '0'; -- CR607165
signal rst_rvalid_re : std_logic := '0'; -- CR576999
signal rst_wvalid_re : std_logic := '0'; -- CR576999
signal rdy : std_logic := '0';
signal rdy1 : std_logic := '0';
signal wr_in_progress : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
--*****************************************************************************
--** AXI LITE READ
--*****************************************************************************
s_axi_lite_wready <= wready_i;
s_axi_lite_awready <= awready_i;
s_axi_lite_arready <= arready_i;
s_axi_lite_bvalid <= bvalid_i;
-------------------------------------------------------------------------------
-- Register AXI Inputs
-------------------------------------------------------------------------------
REG_INPUTS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
awvalid <= '0' ;
awaddr <= (others => '0') ;
wvalid <= '0' ;
wdata <= (others => '0') ;
arvalid <= '0' ;
araddr <= (others => '0') ;
else
awvalid <= s_axi_lite_awvalid ;
awaddr <= s_axi_lite_awaddr ;
wvalid <= s_axi_lite_wvalid ;
wdata <= s_axi_lite_wdata ;
arvalid <= s_axi_lite_arvalid ;
araddr <= s_axi_lite_araddr ;
end if;
end if;
end process REG_INPUTS;
-- s_axi_lite_aclk is synchronous to ip clock
GEN_SYNC_WRITE : if C_AXI_LITE_IS_ASYNC = 0 generate
begin
-------------------------------------------------------------------------------
-- Assert Write Adddress Ready Handshake
-- Capture rising edge of valid and register out as ready. This creates
-- a 3 clock cycle address phase but also registers all inputs and outputs.
-- Note : Single clock cycle address phase can be accomplished using
-- combinatorial logic.
-------------------------------------------------------------------------------
REG_AWVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
awvalid_d1 <= '0';
-- awvalid_re <= '0'; -- CR605883
else
awvalid_d1 <= awvalid;
-- awvalid_re <= awvalid and not awvalid_d1; -- CR605883
end if;
end if;
end process REG_AWVALID;
awvalid_re <= awvalid and not awvalid_d1 and (not (wr_in_progress)); -- CR605883
-------------------------------------------------------------------------------
-- Capture assertion of awvalid to indicate that we have captured
-- a valid address
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Assert Write Data Ready Handshake
-- Capture rising edge of valid and register out as ready. This creates
-- a 3 clock cycle address phase but also registers all inputs and outputs.
-- Note : Single clock cycle address phase can be accomplished using
-- combinatorial logic.
-------------------------------------------------------------------------------
REG_WVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
wvalid_d1 <= '0';
-- wvalid_re <= '0';
else
wvalid_d1 <= wvalid;
-- wvalid_re <= wvalid and not wvalid_d1; -- CR605883
end if;
end if;
end process REG_WVALID;
wvalid_re <= wvalid and not wvalid_d1; -- CR605883
WRITE_IN_PROGRESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
wr_in_progress <= '0';
elsif(awvalid_re = '1')then
wr_in_progress <= '1';
end if;
end if;
end process WRITE_IN_PROGRESS;
-- CR605883 (CDC) provide pure register output to synchronizers
--wvalid_re <= wvalid and not wvalid_d1 and not rst_wvalid_re;
-------------------------------------------------------------------------------
-- Capture assertion of wvalid to indicate that we have captured
-- valid data
-------------------------------------------------------------------------------
WRDATA_CAP_FLAG : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rdy = '1')then
wr_data_cap <= '0';
elsif(wvalid_re = '1')then
wr_data_cap <= '1';
end if;
end if;
end process WRDATA_CAP_FLAG;
REG_WREADY : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rdy = '1') then
rdy <= '0';
elsif (wr_data_cap = '1' and wr_addr_cap = '1') then
rdy <= '1';
end if;
wready_i <= rdy;
awready_i <= rdy;
rdy1 <= rdy;
end if;
end process REG_WREADY;
WRADDR_CAP_FLAG : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rdy = '1')then
wr_addr_cap <= '0';
elsif(awvalid_re = '1')then
wr_addr_cap <= '1';
end if;
end if;
end process WRADDR_CAP_FLAG;
-------------------------------------------------------------------------------
-- Capture Write Address
-------------------------------------------------------------------------------
REG_WRITE_ADDRESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
-- axi2ip_wraddr_i <= (others => '0');
-- Register address on valid
elsif(awvalid_re = '1')then
-- axi2ip_wraddr_i <= awaddr;
end if;
end if;
end process REG_WRITE_ADDRESS;
-------------------------------------------------------------------------------
-- Capture Write Data
-------------------------------------------------------------------------------
REG_WRITE_DATA : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
axi2ip_wrdata_i <= (others => '0');
-- Register address and assert ready
elsif(wvalid_re = '1')then
axi2ip_wrdata_i <= wdata;
end if;
end if;
end process REG_WRITE_DATA;
-------------------------------------------------------------------------------
-- Must have both a valid address and valid data before updating
-- a register. Note in AXI write address can come before or
-- after AXI write data.
-- axi2ip_wren <= '1' when wr_data_cap = '1' and wr_addr_cap = '1'
-- else '0';
axi2ip_wren <= rdy; -- or rdy1;
-------------------------------------------------------------------------------
-- Decode and assert proper chip enable per captured axi lite write address
-------------------------------------------------------------------------------
WRCE_GEN: for j in 0 to C_NUM_CE - 1 generate
constant BAR : std_logic_vector(CE_ADDR_SIZE-1 downto 0) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
wrce(j) <= axi2ip_wren when s_axi_lite_awaddr
((CE_ADDR_SIZE + ADDR_OFFSET) - 1
downto ADDR_OFFSET)
= BAR(CE_ADDR_SIZE-1 downto 0)
else '0';
end generate WRCE_GEN;
-------------------------------------------------------------------------------
-- register write ce's and data out to axi dma register module
-------------------------------------------------------------------------------
REG_WR_OUT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
axi2ip_wrce <= (others => '0');
-- axi2ip_wrdata <= (others => '0');
else
axi2ip_wrce <= wrce;
-- axi2ip_wrdata <= axi2ip_wrdata_i;
end if;
end if;
end process REG_WR_OUT;
axi2ip_wrdata <= s_axi_lite_wdata;
-------------------------------------------------------------------------------
-- Write Response
-------------------------------------------------------------------------------
s_axi_lite_bresp <= OKAY_RESP;
WRESP_PROCESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
bvalid_i <= '0';
rst_wvalid_re <= '0'; -- CR576999
-- If response issued and target indicates ready then
-- clear response
elsif(bvalid_i = '1' and s_axi_lite_bready = '1')then
bvalid_i <= '0';
rst_wvalid_re <= '0'; -- CR576999
-- Issue a resonse on write
elsif(rdy1 = '1')then
bvalid_i <= '1';
rst_wvalid_re <= '1'; -- CR576999
end if;
end if;
end process WRESP_PROCESS;
end generate GEN_SYNC_WRITE;
-- s_axi_lite_aclk is asynchronous to ip clock
GEN_ASYNC_WRITE : if C_AXI_LITE_IS_ASYNC = 1 generate
-- Data support
-----------------------------------------------------------------------------
-- ATTRIBUTE Declarations
-----------------------------------------------------------------------------
-- Prevent x-propagation on clock-domain crossing register
ATTRIBUTE async_reg : STRING;
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
signal ip_wvalid_d1_cdc_to : std_logic := '0';
signal ip_wvalid_d2 : std_logic := '0';
signal ip_wvalid_re : std_logic := '0';
signal wr_wvalid_re_cdc_from : std_logic := '0';
signal wr_data_cdc_from : std_logic_vector -- CR605883
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0'); -- CR605883
signal wdata_d1_cdc_to : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal wdata_d2 : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal axi2ip_wrdata_cdc_tig : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) := (others => '0');
signal ip_data_cap : std_logic := '0';
-- Address support
signal ip_awvalid_d1_cdc_to : std_logic := '0';
signal ip_awvalid_d2 : std_logic := '0';
signal ip_awvalid_re : std_logic := '0';
signal wr_awvalid_re_cdc_from : std_logic := '0';
signal wr_addr_cdc_from : std_logic_vector -- CR605883
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0'); -- CR605883
signal awaddr_d1_cdc_tig : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal awaddr_d2 : std_logic_vector
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) := (others => '0');
signal ip_addr_cap : std_logic := '0';
-- Bvalid support
signal lite_data_cap_d1 : std_logic := '0';
signal lite_data_cap_d2 : std_logic := '0';
signal lite_addr_cap_d1 : std_logic := '0';
signal lite_addr_cap_d2 : std_logic := '0';
signal lite_axi2ip_wren : std_logic := '0';
signal awvalid_cdc_from : std_logic := '0';
signal awvalid_cdc_to : std_logic := '0';
signal awvalid_to : std_logic := '0';
signal awvalid_to2 : std_logic := '0';
--ATTRIBUTE async_reg OF awvalid_cdc_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF awvalid_to : SIGNAL IS "true";
signal wvalid_cdc_from : std_logic := '0';
signal wvalid_cdc_to : std_logic := '0';
signal wvalid_to : std_logic := '0';
signal wvalid_to2 : std_logic := '0';
--ATTRIBUTE async_reg OF wvalid_cdc_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF wvalid_to : SIGNAL IS "true";
signal rdy_cdc_to : std_logic := '0';
signal rdy_cdc_from : std_logic := '0';
signal rdy_to : std_logic := '0';
signal rdy_to2 : std_logic := '0';
signal rdy_to2_cdc_from : std_logic := '0';
signal rdy_out : std_logic := '0';
--ATTRIBUTE async_reg OF rdy_cdc_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF rdy_to : SIGNAL IS "true";
Attribute KEEP of rdy_to2_cdc_from : signal is "TRUE";
Attribute EQUIVALENT_REGISTER_REMOVAL of rdy_to2_cdc_from : signal is "no";
signal rdy_back_cdc_to : std_logic := '0';
signal rdy_back_to : std_logic :='0';
--ATTRIBUTE async_reg OF rdy_back_cdc_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF rdy_back_to : SIGNAL IS "true";
signal rdy_back : std_logic := '0';
signal rdy_shut : std_logic := '0';
begin
REG_AWVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
awvalid_d1 <= '0';
else
awvalid_d1 <= awvalid;
end if;
end if;
end process REG_AWVALID;
awvalid_re <= awvalid and not awvalid_d1 and (not (wr_in_progress)); -- CR605883
-------------------------------------------------------------------------------
-- Capture assertion of awvalid to indicate that we have captured
-- a valid address
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Assert Write Data Ready Handshake
-- Capture rising edge of valid and register out as ready. This creates
-- a 3 clock cycle address phase but also registers all inputs and outputs.
-- Note : Single clock cycle address phase can be accomplished using
-- combinatorial logic.
-------------------------------------------------------------------------------
REG_WVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
wvalid_d1 <= '0';
else
wvalid_d1 <= wvalid;
end if;
end if;
end process REG_WVALID;
wvalid_re <= wvalid and not wvalid_d1; -- CR605883
--*************************************************************************
--** Write Address Support
--*************************************************************************
AWVLD_CDC_FROM : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
awvalid_cdc_from <= '0';
elsif(awvalid_re = '1')then
awvalid_cdc_from <= '1';
end if;
end if;
end process AWVLD_CDC_FROM;
AWVLD_CDC_TO : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => awvalid_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => awvalid_to,
scndry_vect_out => open
);
-- AWVLD_CDC_TO : process(ip2axi_aclk)
-- begin
-- if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
-- awvalid_cdc_to <= awvalid_cdc_from;
-- awvalid_to <= awvalid_cdc_to;
-- end if;
-- end process AWVLD_CDC_TO;
AWVLD_CDC_TO2 : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
awvalid_to2 <= '0';
else
awvalid_to2 <= awvalid_to;
end if;
end if;
end process AWVLD_CDC_TO2;
ip_awvalid_re <= awvalid_to and (not awvalid_to2);
WVLD_CDC_FROM : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_wvalid_re = '1')then
wvalid_cdc_from <= '0';
elsif(wvalid_re = '1')then
wvalid_cdc_from <= '1';
end if;
end if;
end process WVLD_CDC_FROM;
WVLD_CDC_TO : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => wvalid_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => wvalid_to,
scndry_vect_out => open
);
-- WVLD_CDC_TO : process(ip2axi_aclk)
-- begin
-- if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
-- wvalid_cdc_to <= wvalid_cdc_from;
-- wvalid_to <= wvalid_cdc_to;
-- end if;
-- end process WVLD_CDC_TO;
WVLD_CDC_TO2 : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
wvalid_to2 <= '0';
else
wvalid_to2 <= wvalid_to;
end if;
end if;
end process WVLD_CDC_TO2;
ip_wvalid_re <= wvalid_to and (not wvalid_to2);
REG_WADDR_TO_IPCLK : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH,
C_MTBF_STAGES => 1
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => s_axi_lite_awaddr,
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => awaddr_d1_cdc_tig
);
REG_WADDR_TO_IPCLK1 : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_S_AXI_LITE_DATA_WIDTH,
C_MTBF_STAGES => 1
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => s_axi_lite_wdata,
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => axi2ip_wrdata_cdc_tig
);
-- Double register address in
-- REG_WADDR_TO_IPCLK : process(ip2axi_aclk)
-- begin
-- if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
-- if(ip2axi_aresetn = '0')then
-- awaddr_d1_cdc_tig <= (others => '0');
-- -- axi2ip_wraddr_i <= (others => '0');
-- axi2ip_wrdata_cdc_tig <= (others => '0');
-- else
-- awaddr_d1_cdc_tig <= s_axi_lite_awaddr;
-- axi2ip_wrdata_cdc_tig <= s_axi_lite_wdata;
-- -- axi2ip_wraddr_i <= awaddr_d1_cdc_tig; -- CR605883
-- end if;
-- end if;
-- end process REG_WADDR_TO_IPCLK;
-- Flag that address has been captured
REG_IP_ADDR_CAP : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0' or rdy_shut = '1')then
ip_addr_cap <= '0';
elsif(ip_awvalid_re = '1')then
ip_addr_cap <= '1';
end if;
end if;
end process REG_IP_ADDR_CAP;
REG_WREADY : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0' or rdy_shut = '1') then -- or rdy = '1') then
rdy <= '0';
elsif (ip_data_cap = '1' and ip_addr_cap = '1') then
rdy <= '1';
end if;
end if;
end process REG_WREADY;
REG3_WREADY : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => rdy_to2_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => rdy_back_to,
scndry_vect_out => open
);
-- REG3_WREADY : process(ip2axi_aclk)
-- begin
-- if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
-- rdy_back_cdc_to <= rdy_to2_cdc_from;
-- rdy_back_to <= rdy_back_cdc_to;
-- end if;
-- end process REG3_WREADY;
REG3_WREADY2 : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0') then
rdy_back <= '0';
else
rdy_back <= rdy_back_to;
end if;
end if;
end process REG3_WREADY2;
rdy_shut <= rdy_back_to and (not rdy_back);
REG1_WREADY : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0' or rdy_shut = '1') then
rdy_cdc_from <= '0';
elsif (rdy = '1') then
rdy_cdc_from <= '1';
end if;
end if;
end process REG1_WREADY;
REG2_WREADY : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => ip2axi_aclk,
prmry_resetn => '0',
prmry_in => rdy_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '0',
scndry_out => rdy_to,
scndry_vect_out => open
);
-- REG2_WREADY : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- rdy_cdc_to <= rdy_cdc_from;
-- rdy_to <= rdy_cdc_to;
-- end if;
-- end process REG2_WREADY;
REG2_WREADY2 : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0') then
rdy_to2 <= '0';
rdy_to2_cdc_from <= '0';
else
rdy_to2 <= rdy_to;
rdy_to2_cdc_from <= rdy_to;
end if;
end if;
end process REG2_WREADY2;
rdy_out <= not (rdy_to) and rdy_to2;
wready_i <= rdy_out;
awready_i <= rdy_out;
--*************************************************************************
--** Write Data Support
--*************************************************************************
-------------------------------------------------------------------------------
-- Capture write data
-------------------------------------------------------------------------------
-- WRDATA_S_H : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- if(s_axi_lite_aresetn = '0')then
-- wr_data_cdc_from <= (others => '0');
-- elsif(wvalid_re = '1')then
-- wr_data_cdc_from <= wdata;
-- end if;
-- end if;
-- end process WRDATA_S_H;
-- Flag that data has been captured
REG_IP_DATA_CAP : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0' or rdy_shut = '1')then
ip_data_cap <= '0';
elsif(ip_wvalid_re = '1')then
ip_data_cap <= '1';
end if;
end if;
end process REG_IP_DATA_CAP;
-- Must have both a valid address and valid data before updating
-- a register. Note in AXI write address can come before or
-- after AXI write data.
axi2ip_wren <= rdy;
-- axi2ip_wren <= '1' when ip_data_cap = '1' and ip_addr_cap = '1'
-- else '0';
-------------------------------------------------------------------------------
-- Decode and assert proper chip enable per captured axi lite write address
-------------------------------------------------------------------------------
WRCE_GEN: for j in 0 to C_NUM_CE - 1 generate
constant BAR : std_logic_vector(CE_ADDR_SIZE-1 downto 0) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
wrce(j) <= axi2ip_wren when awaddr_d1_cdc_tig
((CE_ADDR_SIZE + ADDR_OFFSET) - 1
downto ADDR_OFFSET)
= BAR(CE_ADDR_SIZE-1 downto 0)
else '0';
end generate WRCE_GEN;
-------------------------------------------------------------------------------
-- register write ce's and data out to axi dma register module
-------------------------------------------------------------------------------
REG_WR_OUT : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
axi2ip_wrce <= (others => '0');
else
axi2ip_wrce <= wrce;
end if;
end if;
end process REG_WR_OUT;
axi2ip_wrdata <= axi2ip_wrdata_cdc_tig; --s_axi_lite_wdata;
--*************************************************************************
--** Write Response Support
--*************************************************************************
-- Minimum of 2 IP clocks for addr and data capture, therefore delaying
-- Lite clock addr and data capture by 2 Lite clocks will guarenttee bvalid
-- responce occurs after write data acutally written.
-- REG_ALIGN_CAP : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- if(s_axi_lite_aresetn = '0')then
-- lite_data_cap_d1 <= '0';
-- lite_data_cap_d2 <= '0';
-- lite_addr_cap_d1 <= '0';
-- lite_addr_cap_d2 <= '0';
-- else
-- lite_data_cap_d1 <= rdy; --wr_data_cap;
-- lite_data_cap_d2 <= lite_data_cap_d1;
-- lite_addr_cap_d1 <= rdy; --wr_addr_cap;
-- lite_addr_cap_d2 <= lite_addr_cap_d1;
-- end if;
-- end if;
-- end process REG_ALIGN_CAP;
-- Pseudo write enable used simply to assert bvalid
-- lite_axi2ip_wren <= rdy; --'1' when wr_data_cap = '1' and wr_addr_cap = '1'
-- else '0';
WRESP_PROCESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
bvalid_i <= '0';
rst_wvalid_re <= '0'; -- CR576999
-- If response issued and target indicates ready then
-- clear response
elsif(bvalid_i = '1' and s_axi_lite_bready = '1')then
bvalid_i <= '0';
rst_wvalid_re <= '0'; -- CR576999
-- Issue a resonse on write
elsif(rdy_out = '1')then
-- elsif(lite_axi2ip_wren = '1')then
bvalid_i <= '1';
rst_wvalid_re <= '1'; -- CR576999
end if;
end if;
end process WRESP_PROCESS;
s_axi_lite_bresp <= OKAY_RESP;
end generate GEN_ASYNC_WRITE;
--*****************************************************************************
--** AXI LITE READ
--*****************************************************************************
-------------------------------------------------------------------------------
-- Assert Read Adddress Ready Handshake
-- Capture rising edge of valid and register out as ready. This creates
-- a 3 clock cycle address phase but also registers all inputs and outputs.
-- Note : Single clock cycle address phase can be accomplished using
-- combinatorial logic.
-------------------------------------------------------------------------------
REG_ARVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_rvalid_re = '1')then
arvalid_d1 <= '0';
else
arvalid_d1 <= arvalid;
end if;
end if;
end process REG_ARVALID;
arvalid_re <= arvalid and not arvalid_d1
and not rst_rvalid_re and not read_in_progress; -- CR607165
-- register for proper alignment
REG_ARREADY : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
arready_i <= '0';
else
arready_i <= arvalid_re;
end if;
end if;
end process REG_ARREADY;
-- Always respond 'okay' axi lite read
s_axi_lite_rresp <= OKAY_RESP;
s_axi_lite_rvalid <= s_axi_lite_rvalid_i;
-- s_axi_lite_aclk is synchronous to ip clock
GEN_SYNC_READ : if C_AXI_LITE_IS_ASYNC = 0 generate
begin
read_in_progress <= '0'; --Not used for sync mode (CR607165)
-------------------------------------------------------------------------------
-- Capture Read Address
-------------------------------------------------------------------------------
REG_READ_ADDRESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
axi2ip_rdaddr_i <= (others => '0');
-- Register address on valid
elsif(arvalid_re = '1')then
axi2ip_rdaddr_i <= araddr;
end if;
end if;
end process REG_READ_ADDRESS;
-------------------------------------------------------------------------------
-- Generate RdCE based on address match to address bar
-------------------------------------------------------------------------------
RDCE_GEN: for j in 0 to C_NUM_CE - 1 generate
constant BAR : std_logic_vector(CE_ADDR_SIZE-1 downto 0) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
rdce(j) <= arvalid_re_d1
when axi2ip_rdaddr_i((CE_ADDR_SIZE + ADDR_OFFSET) - 1
downto ADDR_OFFSET)
= BAR(CE_ADDR_SIZE-1 downto 0)
else '0';
end generate RDCE_GEN;
-------------------------------------------------------------------------------
-- Register out to IP
-------------------------------------------------------------------------------
REG_RDCNTRL_OUT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
--axi2ip_rdce <= (others => '0');
axi2ip_rdaddr <= (others => '0');
else
--axi2ip_rdce <= rdce;
axi2ip_rdaddr <= axi2ip_rdaddr_i;
end if;
end if;
end process REG_RDCNTRL_OUT;
-- Sample and hold rdce value until rvalid assertion
REG_RDCE_OUT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_rvalid_re = '1')then
axi2ip_rdce <= (others => '0');
elsif(arvalid_re_d1 = '1')then
axi2ip_rdce <= rdce;
end if;
end if;
end process REG_RDCE_OUT;
-- Register for proper alignment
REG_RVALID : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
arvalid_re_d1 <= '0';
rvalid <= '0';
else
arvalid_re_d1 <= arvalid_re;
rvalid <= arvalid_re_d1;
end if;
end if;
end process REG_RVALID;
-------------------------------------------------------------------------------
-- Drive read data and read data valid out on capture of valid address.
-------------------------------------------------------------------------------
REG_RD_OUT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
s_axi_lite_rdata <= (others => '0');
s_axi_lite_rvalid_i <= '0';
rst_rvalid_re <= '0'; -- CR576999
-- If rvalid driving out to target and target indicates ready
-- then de-assert rvalid. (structure guarentees min 1 clock of rvalid)
elsif(s_axi_lite_rvalid_i = '1' and s_axi_lite_rready = '1')then
s_axi_lite_rdata <= (others => '0');
s_axi_lite_rvalid_i <= '0';
rst_rvalid_re <= '0'; -- CR576999
-- If read cycle then assert rvalid and rdata out to target
elsif(rvalid = '1')then
s_axi_lite_rdata <= ip2axi_rddata;
s_axi_lite_rvalid_i <= '1';
rst_rvalid_re <= '1'; -- CR576999
end if;
end if;
end process REG_RD_OUT;
end generate GEN_SYNC_READ;
-- s_axi_lite_aclk is asynchronous to ip clock
GEN_ASYNC_READ : if C_AXI_LITE_IS_ASYNC = 1 generate
ATTRIBUTE async_reg : STRING;
signal ip_arvalid_d1_cdc_tig : std_logic := '0';
signal ip_arvalid_d2 : std_logic := '0';
signal ip_arvalid_d3 : std_logic := '0';
signal ip_arvalid_re : std_logic := '0';
signal araddr_d1_cdc_tig : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) :=(others => '0');
signal araddr_d2 : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) :=(others => '0');
signal araddr_d3 : std_logic_vector(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) :=(others => '0');
signal lite_rdata_cdc_from : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) :=(others => '0');
signal lite_rdata_d1_cdc_to : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) :=(others => '0');
signal lite_rdata_d2 : std_logic_vector(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) :=(others => '0');
--ATTRIBUTE async_reg OF ip_arvalid_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF ip_arvalid_d2 : SIGNAL IS "true";
--ATTRIBUTE async_reg OF araddr_d1_cdc_tig : SIGNAL IS "true";
--ATTRIBUTE async_reg OF araddr_d2 : SIGNAL IS "true";
--ATTRIBUTE async_reg OF lite_rdata_d1_cdc_to : SIGNAL IS "true";
--ATTRIBUTE async_reg OF lite_rdata_d2 : SIGNAL IS "true";
signal p_pulse_s_h : std_logic := '0';
signal p_pulse_s_h_clr : std_logic := '0';
signal s_pulse_d1 : std_logic := '0';
signal s_pulse_d2 : std_logic := '0';
signal s_pulse_d3 : std_logic := '0';
signal s_pulse_re : std_logic := '0';
signal p_pulse_re_d1 : std_logic := '0';
signal p_pulse_re_d2 : std_logic := '0';
signal p_pulse_re_d3 : std_logic := '0';
signal arready_d1 : std_logic := '0'; -- CR605883
signal arready_d2 : std_logic := '0'; -- CR605883
signal arready_d3 : std_logic := '0'; -- CR605883
signal arready_d4 : std_logic := '0'; -- CR605883
signal arready_d5 : std_logic := '0'; -- CR605883
signal arready_d6 : std_logic := '0'; -- CR605883
signal arready_d7 : std_logic := '0'; -- CR605883
signal arready_d8 : std_logic := '0'; -- CR605883
signal arready_d9 : std_logic := '0'; -- CR605883
signal arready_d10 : std_logic := '0'; -- CR605883
signal arready_d11 : std_logic := '0'; -- CR605883
signal arready_d12 : std_logic := '0'; -- CR605883
begin
-- CR607165
-- Flag to prevent overlapping reads
RD_PROGRESS : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0' or rst_rvalid_re = '1')then
read_in_progress <= '0';
elsif(arvalid_re = '1')then
read_in_progress <= '1';
end if;
end if;
end process RD_PROGRESS;
-- Double register address in
REG_RADDR_TO_IPCLK : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => '0',
prmry_vect_in => s_axi_lite_araddr,
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => open,
scndry_vect_out => araddr_d3
);
-- REG_RADDR_TO_IPCLK : process(ip2axi_aclk)
-- begin
-- if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
-- if(ip2axi_aresetn = '0')then
-- araddr_d1_cdc_tig <= (others => '0');
-- araddr_d2 <= (others => '0');
-- araddr_d3 <= (others => '0');
-- else
-- araddr_d1_cdc_tig <= s_axi_lite_araddr;
-- araddr_d2 <= araddr_d1_cdc_tig;
-- araddr_d3 <= araddr_d2;
-- end if;
-- end if;
-- end process REG_RADDR_TO_IPCLK;
-- Latch and hold read address
REG_ARADDR_PROCESS : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
axi2ip_rdaddr_i <= (others => '0');
elsif(ip_arvalid_re = '1')then
axi2ip_rdaddr_i <= araddr_d3;
end if;
end if;
end process REG_ARADDR_PROCESS;
axi2ip_rdaddr <= axi2ip_rdaddr_i;
-- Register awready into IP clock domain. awready
-- is a 1 axi_lite clock delay of the rising edge of
-- arvalid. This provides a signal that asserts when
-- araddr is known to be stable.
REG_ARVALID_TO_IPCLK : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => C_S_AXI_LITE_ADDR_WIDTH,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axi_lite_aclk,
prmry_resetn => '0',
prmry_in => arready_i,
prmry_vect_in => (others => '0'),
scndry_aclk => ip2axi_aclk,
scndry_resetn => '0',
scndry_out => ip_arvalid_d2,
scndry_vect_out => open
);
REG_ARVALID_TO_IPCLK1 : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
-- ip_arvalid_d1_cdc_tig <= '0';
-- ip_arvalid_d2 <= '0';
ip_arvalid_d3 <= '0';
else
-- ip_arvalid_d1_cdc_tig <= arready_i;
-- ip_arvalid_d2 <= ip_arvalid_d1_cdc_tig;
ip_arvalid_d3 <= ip_arvalid_d2;
end if;
end if;
end process REG_ARVALID_TO_IPCLK1;
ip_arvalid_re <= ip_arvalid_d2 and not ip_arvalid_d3;
-------------------------------------------------------------------------------
-- Generate Read CE's
-------------------------------------------------------------------------------
RDCE_GEN: for j in 0 to C_NUM_CE - 1 generate
constant BAR : std_logic_vector(CE_ADDR_SIZE-1 downto 0) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
rdce(j) <= ip_arvalid_re
when araddr_d3((CE_ADDR_SIZE + ADDR_OFFSET) - 1
downto ADDR_OFFSET)
= BAR(CE_ADDR_SIZE-1 downto 0)
else '0';
end generate RDCE_GEN;
-------------------------------------------------------------------------------
-- Register RDCE and RD Data out to IP
-------------------------------------------------------------------------------
REG_RDCNTRL_OUT : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
axi2ip_rdce <= (others => '0');
elsif(ip_arvalid_re = '1')then
axi2ip_rdce <= rdce;
else
axi2ip_rdce <= (others => '0');
end if;
end if;
end process REG_RDCNTRL_OUT;
-- Generate sample and hold pulse to capture read data from IP
REG_RVALID : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
rvalid <= '0';
else
rvalid <= ip_arvalid_re;
end if;
end if;
end process REG_RVALID;
-------------------------------------------------------------------------------
-- Sample and hold read data from IP
-------------------------------------------------------------------------------
S_H_READ_DATA : process(ip2axi_aclk)
begin
if(ip2axi_aclk'EVENT and ip2axi_aclk = '1')then
if(ip2axi_aresetn = '0')then
lite_rdata_cdc_from <= (others => '0');
-- If read cycle then assert rvalid and rdata out to target
elsif(rvalid = '1')then
lite_rdata_cdc_from <= ip2axi_rddata;
end if;
end if;
end process S_H_READ_DATA;
-- Cross read data to axi_lite clock domain
REG_DATA2LITE_CLOCK : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 0,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => ip2axi_aclk,
prmry_resetn => '0',
prmry_in => '0', --lite_rdata_cdc_from,
prmry_vect_in => lite_rdata_cdc_from,
scndry_aclk => s_axi_lite_aclk,
scndry_resetn => '0',
scndry_out => open, --lite_rdata_d2,
scndry_vect_out => lite_rdata_d2
);
-- REG_DATA2LITE_CLOCK : process(s_axi_lite_aclk)
-- begin
-- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
-- if(s_axi_lite_aresetn = '0')then
-- lite_rdata_d1_cdc_to <= (others => '0');
-- lite_rdata_d2 <= (others => '0');
-- else
-- lite_rdata_d1_cdc_to <= lite_rdata_cdc_from;
-- lite_rdata_d2 <= lite_rdata_d1_cdc_to;
-- end if;
-- end if;
-- end process REG_DATA2LITE_CLOCK;
-- CR605883 (CDC) modified to remove
-- Because axi_lite_aclk must be less than or equal to ip2axi_aclk
-- then read data will appear a maximum 6 clocks from assertion
-- of arready.
REG_ALIGN_RDATA_LATCH : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
arready_d1 <= '0';
arready_d2 <= '0';
arready_d3 <= '0';
arready_d4 <= '0';
arready_d5 <= '0';
arready_d6 <= '0';
arready_d7 <= '0';
arready_d8 <= '0';
arready_d9 <= '0';
arready_d10 <= '0';
arready_d11 <= '0';
arready_d12 <= '0';
else
arready_d1 <= arready_i;
arready_d2 <= arready_d1;
arready_d3 <= arready_d2;
arready_d4 <= arready_d3;
arready_d5 <= arready_d4;
arready_d6 <= arready_d5;
arready_d7 <= arready_d6;
arready_d8 <= arready_d7;
arready_d9 <= arready_d8;
arready_d10 <= arready_d9;
arready_d11 <= arready_d10;
arready_d12 <= arready_d11;
end if;
end if;
end process REG_ALIGN_RDATA_LATCH;
-------------------------------------------------------------------------------
-- Drive read data and read data valid out on capture of valid address.
-------------------------------------------------------------------------------
REG_RD_OUT : process(s_axi_lite_aclk)
begin
if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then
if(s_axi_lite_aresetn = '0')then
s_axi_lite_rdata <= (others => '0');
s_axi_lite_rvalid_i <= '0';
rst_rvalid_re <= '0'; -- CR576999
-- If rvalid driving out to target and target indicates ready
-- then de-assert rvalid. (structure guarentees min 1 clock of rvalid)
elsif(s_axi_lite_rvalid_i = '1' and s_axi_lite_rready = '1')then
s_axi_lite_rdata <= (others => '0');
s_axi_lite_rvalid_i <= '0';
rst_rvalid_re <= '0'; -- CR576999
-- If read cycle then assert rvalid and rdata out to target
-- CR605883
--elsif(s_pulse_re = '1')then
elsif(arready_d12 = '1')then
s_axi_lite_rdata <= lite_rdata_d2;
s_axi_lite_rvalid_i <= '1';
rst_rvalid_re <= '1'; -- CR576999
end if;
end if;
end process REG_RD_OUT;
end generate GEN_ASYNC_READ;
end implementation;
|
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Wishbone DMA Streaming Interface
---------------------------------------------------------------------------------------
-- File : xdma_interface_registers_pkg.vhd
-- Author : auto-generated by wbgen2 from xdma_interface_wb.wb
-- Created : Thu Sep 27 15:39:56 2012
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE xdma_interface_wb.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wbgen2_pkg.all;
package dma_iface_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_dma_iface_in_registers is record
ctl_done_i : std_logic;
ctl_ovf_i : std_logic;
fifo_c2b_wr_req_i : std_logic;
fifo_c2b_data_i : std_logic_vector(31 downto 0);
fifo_c2b_last_i : std_logic;
fifo_b2c_rd_req_i : std_logic;
end record;
constant c_dma_iface_in_registers_init_value: t_dma_iface_in_registers := (
ctl_done_i => '0',
ctl_ovf_i => '0',
fifo_c2b_wr_req_i => '0',
fifo_c2b_data_i => (others => '0'),
fifo_c2b_last_i => '0',
fifo_b2c_rd_req_i => '0'
);
-- Output registers (WB slave -> user design)
type t_dma_iface_out_registers is record
ctl_start_o : std_logic;
tr_cntr_o : std_logic_vector(31 downto 0);
fifo_c2b_wr_full_o : std_logic;
fifo_c2b_wr_empty_o : std_logic;
fifo_c2b_wr_usedw_o : std_logic_vector(7 downto 0);
fifo_b2c_rd_full_o : std_logic;
fifo_b2c_rd_empty_o : std_logic;
fifo_b2c_rd_usedw_o : std_logic_vector(7 downto 0);
fifo_b2c_data_o : std_logic_vector(31 downto 0);
end record;
constant c_dma_iface_out_registers_init_value: t_dma_iface_out_registers := (
ctl_start_o => '0',
tr_cntr_o => (others => '0'),
fifo_c2b_wr_full_o => '0',
fifo_c2b_wr_empty_o => '0',
fifo_c2b_wr_usedw_o => (others => '0'),
fifo_b2c_rd_full_o => '0',
fifo_b2c_rd_empty_o => '0',
fifo_b2c_rd_usedw_o => (others => '0'),
fifo_b2c_data_o => (others => '0')
);
function "or" (left, right: t_dma_iface_in_registers) return t_dma_iface_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;
package body dma_iface_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if(x = 'X' or x = 'U') then
return '0';
else
return x;
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_dma_iface_in_registers) return t_dma_iface_in_registers is
variable tmp: t_dma_iface_in_registers;
begin
tmp.ctl_done_i := f_x_to_zero(left.ctl_done_i) or f_x_to_zero(right.ctl_done_i);
tmp.ctl_ovf_i := f_x_to_zero(left.ctl_ovf_i) or f_x_to_zero(right.ctl_ovf_i);
tmp.fifo_c2b_wr_req_i := f_x_to_zero(left.fifo_c2b_wr_req_i) or f_x_to_zero(right.fifo_c2b_wr_req_i);
tmp.fifo_c2b_data_i := f_x_to_zero(left.fifo_c2b_data_i) or f_x_to_zero(right.fifo_c2b_data_i);
tmp.fifo_c2b_last_i := f_x_to_zero(left.fifo_c2b_last_i) or f_x_to_zero(right.fifo_c2b_last_i);
tmp.fifo_b2c_rd_req_i := f_x_to_zero(left.fifo_b2c_rd_req_i) or f_x_to_zero(right.fifo_b2c_rd_req_i);
return tmp;
end function;
end package body;
|
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`protect end_protected
|
--
-- Copyright (C) 2012 Jared Boone, ShareBrained Technology, Inc.
--
-- This file is part of PortaPack.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; see the file COPYING. If not, write to
-- the Free Software Foundation, Inc., 51 Franklin Street,
-- Boston, MA 02110-1301, USA.
library ieee;
use ieee.std_logic_1164.all;
entity top is
port (
MCU_D : inout std_logic_vector(7 downto 0);
MCU_DIR : in std_logic;
MCU_IO_STBX : in std_logic;
MCU_LCD_WRX : in std_logic;
MCU_ADDR : in std_logic;
MCU_LCD_TE : out std_logic;
MCU_P2_8 : in std_logic;
MCU_LCD_RDX : in std_logic;
TP_U : out std_logic;
TP_D : out std_logic;
TP_L : out std_logic;
TP_R : out std_logic;
SW_SEL : in std_logic;
SW_ROT_A : in std_logic;
SW_ROT_B : in std_logic;
SW_U : in std_logic;
SW_D : in std_logic;
SW_L : in std_logic;
SW_R : in std_logic;
LCD_RESETX : out std_logic;
LCD_RS : out std_logic;
LCD_WRX : out std_logic;
LCD_RDX : out std_logic;
LCD_DB : inout std_logic_vector(15 downto 0);
LCD_TE : in std_logic;
LCD_BACKLIGHT : out std_logic;
AUDIO_RESETX : out std_logic;
REF_EN : out std_logic;
GPS_RESETX : out std_logic;
GPS_TX_READY : in std_logic;
GPS_TIMEPULSE : in std_logic
);
end top;
architecture rtl of top is
signal switches : std_logic_vector(7 downto 0);
type data_direction_t is (from_mcu, to_mcu);
signal data_dir : data_direction_t;
signal mcu_data_out_lcd : std_logic_vector(7 downto 0);
signal mcu_data_out_io : std_logic_vector(7 downto 0);
signal mcu_data_out : std_logic_vector(7 downto 0);
signal mcu_data_in : std_logic_vector(7 downto 0);
signal lcd_data_in : std_logic_vector(15 downto 0);
signal lcd_data_in_mux : std_logic_vector(7 downto 0);
signal lcd_data_out : std_logic_vector(15 downto 0);
signal lcd_data_in_q : std_logic_vector(7 downto 0) := (others => '0');
signal lcd_data_out_q : std_logic_vector(7 downto 0) := (others => '0');
signal tp_q : std_logic_vector(7 downto 0) := (others => '0');
signal lcd_reset_q : std_logic := '1';
signal lcd_backlight_q : std_logic := '0';
signal audio_reset_q : std_logic := '1';
signal ref_en_q : std_logic := '0';
signal dir_read : boolean;
signal dir_write : boolean;
signal lcd_read_strobe : boolean;
signal lcd_write_strobe : boolean;
signal lcd_write : boolean;
signal io_strobe : boolean;
signal io_read_strobe : boolean;
signal io_write_strobe : boolean;
begin
-- I/O data
switches <= LCD_TE & not SW_ROT_B & not SW_ROT_A & not SW_SEL & not SW_U & not SW_D & not SW_L & not SW_R;
TP_U <= tp_q(3) when tp_q(7) = '1' else 'Z';
TP_D <= tp_q(2) when tp_q(6) = '1' else 'Z';
TP_L <= tp_q(1) when tp_q(5) = '1' else 'Z';
TP_R <= tp_q(0) when tp_q(4) = '1' else 'Z';
LCD_BACKLIGHT <= lcd_backlight_q;
MCU_LCD_TE <= LCD_TE;
-- State management
data_dir <= to_mcu when MCU_DIR = '1' else from_mcu;
dir_read <= (data_dir = to_mcu);
dir_write <= (data_dir = from_mcu);
io_strobe <= (MCU_IO_STBX = '0');
io_read_strobe <= io_strobe and dir_read;
lcd_read_strobe <= (MCU_LCD_RDX = '0');
lcd_write <= not lcd_read_strobe;
-- LCD interface
LCD_RS <= MCU_ADDR;
LCD_RDX <= MCU_LCD_RDX;
LCD_WRX <= MCU_LCD_WRX;
lcd_data_out <= lcd_data_out_q & mcu_data_in;
lcd_data_in <= LCD_DB;
LCD_DB <= lcd_data_out when lcd_write else (others => 'Z');
-- Reference clock
REF_EN <= ref_en_q;
-- Peripheral reset control
LCD_RESETX <= not lcd_reset_q;
AUDIO_RESETX <= not audio_reset_q;
GPS_RESETX <= '1';
-- MCU interface
mcu_data_out_lcd <= lcd_data_in(15 downto 8) when lcd_read_strobe else lcd_data_in_q;
mcu_data_out_io <= switches;
mcu_data_out <= mcu_data_out_io when io_read_strobe else mcu_data_out_lcd;
mcu_data_in <= MCU_D;
MCU_D <= mcu_data_out when dir_read else (others => 'Z');
-- Synchronous behaviors:
-- LCD write: Capture LCD high byte on LCD_WRX falling edge.
process(MCU_LCD_WRX, mcu_data_in)
begin
if falling_edge(MCU_LCD_WRX) then
lcd_data_out_q <= mcu_data_in;
end if;
end process;
-- LCD read: Capture LCD low byte on LCD_RD falling edge.
process(MCU_LCD_RDX, lcd_data_in)
begin
if rising_edge(MCU_LCD_RDX) then
lcd_data_in_q <= lcd_data_in(7 downto 0);
end if;
end process;
-- I/O write (to resistive touch panel): Capture data from
-- MCU and hold on TP pins until further notice.
process(MCU_IO_STBX, dir_write, mcu_data_in, MCU_ADDR)
begin
if rising_edge(MCU_IO_STBX) and dir_write then
if MCU_ADDR = '0' then
tp_q <= mcu_data_in;
else
lcd_reset_q <= mcu_data_in(0);
audio_reset_q <= mcu_data_in(1);
ref_en_q <= mcu_data_in(6);
lcd_backlight_q <= mcu_data_in(7);
end if;
end if;
end process;
end rtl;
|
--
-- Copyright (C) 2012 Jared Boone, ShareBrained Technology, Inc.
--
-- This file is part of PortaPack.
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; see the file COPYING. If not, write to
-- the Free Software Foundation, Inc., 51 Franklin Street,
-- Boston, MA 02110-1301, USA.
library ieee;
use ieee.std_logic_1164.all;
entity top is
port (
MCU_D : inout std_logic_vector(7 downto 0);
MCU_DIR : in std_logic;
MCU_IO_STBX : in std_logic;
MCU_LCD_WRX : in std_logic;
MCU_ADDR : in std_logic;
MCU_LCD_TE : out std_logic;
MCU_P2_8 : in std_logic;
MCU_LCD_RDX : in std_logic;
TP_U : out std_logic;
TP_D : out std_logic;
TP_L : out std_logic;
TP_R : out std_logic;
SW_SEL : in std_logic;
SW_ROT_A : in std_logic;
SW_ROT_B : in std_logic;
SW_U : in std_logic;
SW_D : in std_logic;
SW_L : in std_logic;
SW_R : in std_logic;
LCD_RESETX : out std_logic;
LCD_RS : out std_logic;
LCD_WRX : out std_logic;
LCD_RDX : out std_logic;
LCD_DB : inout std_logic_vector(15 downto 0);
LCD_TE : in std_logic;
LCD_BACKLIGHT : out std_logic;
AUDIO_RESETX : out std_logic;
REF_EN : out std_logic;
GPS_RESETX : out std_logic;
GPS_TX_READY : in std_logic;
GPS_TIMEPULSE : in std_logic
);
end top;
architecture rtl of top is
signal switches : std_logic_vector(7 downto 0);
type data_direction_t is (from_mcu, to_mcu);
signal data_dir : data_direction_t;
signal mcu_data_out_lcd : std_logic_vector(7 downto 0);
signal mcu_data_out_io : std_logic_vector(7 downto 0);
signal mcu_data_out : std_logic_vector(7 downto 0);
signal mcu_data_in : std_logic_vector(7 downto 0);
signal lcd_data_in : std_logic_vector(15 downto 0);
signal lcd_data_in_mux : std_logic_vector(7 downto 0);
signal lcd_data_out : std_logic_vector(15 downto 0);
signal lcd_data_in_q : std_logic_vector(7 downto 0) := (others => '0');
signal lcd_data_out_q : std_logic_vector(7 downto 0) := (others => '0');
signal tp_q : std_logic_vector(7 downto 0) := (others => '0');
signal lcd_reset_q : std_logic := '1';
signal lcd_backlight_q : std_logic := '0';
signal audio_reset_q : std_logic := '1';
signal ref_en_q : std_logic := '0';
signal dir_read : boolean;
signal dir_write : boolean;
signal lcd_read_strobe : boolean;
signal lcd_write_strobe : boolean;
signal lcd_write : boolean;
signal io_strobe : boolean;
signal io_read_strobe : boolean;
signal io_write_strobe : boolean;
begin
-- I/O data
switches <= LCD_TE & not SW_ROT_B & not SW_ROT_A & not SW_SEL & not SW_U & not SW_D & not SW_L & not SW_R;
TP_U <= tp_q(3) when tp_q(7) = '1' else 'Z';
TP_D <= tp_q(2) when tp_q(6) = '1' else 'Z';
TP_L <= tp_q(1) when tp_q(5) = '1' else 'Z';
TP_R <= tp_q(0) when tp_q(4) = '1' else 'Z';
LCD_BACKLIGHT <= lcd_backlight_q;
MCU_LCD_TE <= LCD_TE;
-- State management
data_dir <= to_mcu when MCU_DIR = '1' else from_mcu;
dir_read <= (data_dir = to_mcu);
dir_write <= (data_dir = from_mcu);
io_strobe <= (MCU_IO_STBX = '0');
io_read_strobe <= io_strobe and dir_read;
lcd_read_strobe <= (MCU_LCD_RDX = '0');
lcd_write <= not lcd_read_strobe;
-- LCD interface
LCD_RS <= MCU_ADDR;
LCD_RDX <= MCU_LCD_RDX;
LCD_WRX <= MCU_LCD_WRX;
lcd_data_out <= lcd_data_out_q & mcu_data_in;
lcd_data_in <= LCD_DB;
LCD_DB <= lcd_data_out when lcd_write else (others => 'Z');
-- Reference clock
REF_EN <= ref_en_q;
-- Peripheral reset control
LCD_RESETX <= not lcd_reset_q;
AUDIO_RESETX <= not audio_reset_q;
GPS_RESETX <= '1';
-- MCU interface
mcu_data_out_lcd <= lcd_data_in(15 downto 8) when lcd_read_strobe else lcd_data_in_q;
mcu_data_out_io <= switches;
mcu_data_out <= mcu_data_out_io when io_read_strobe else mcu_data_out_lcd;
mcu_data_in <= MCU_D;
MCU_D <= mcu_data_out when dir_read else (others => 'Z');
-- Synchronous behaviors:
-- LCD write: Capture LCD high byte on LCD_WRX falling edge.
process(MCU_LCD_WRX, mcu_data_in)
begin
if falling_edge(MCU_LCD_WRX) then
lcd_data_out_q <= mcu_data_in;
end if;
end process;
-- LCD read: Capture LCD low byte on LCD_RD falling edge.
process(MCU_LCD_RDX, lcd_data_in)
begin
if rising_edge(MCU_LCD_RDX) then
lcd_data_in_q <= lcd_data_in(7 downto 0);
end if;
end process;
-- I/O write (to resistive touch panel): Capture data from
-- MCU and hold on TP pins until further notice.
process(MCU_IO_STBX, dir_write, mcu_data_in, MCU_ADDR)
begin
if rising_edge(MCU_IO_STBX) and dir_write then
if MCU_ADDR = '0' then
tp_q <= mcu_data_in;
else
lcd_reset_q <= mcu_data_in(0);
audio_reset_q <= mcu_data_in(1);
ref_en_q <= mcu_data_in(6);
lcd_backlight_q <= mcu_data_in(7);
end if;
end if;
end process;
end rtl;
|
------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library cypress;
use cypress.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 8; -- rom data width (8/32)
romdepth : integer := 23; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 20; -- ram address depth
srambanks : integer := 1 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal clkout, pllref : std_ulogic;
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(23 downto 0);
signal data : std_logic_vector(31 downto 0);
signal romsn : std_ulogic;
signal iosn : std_ulogic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal dsuen, dsutx, dsurx, dsubren, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal error : std_logic;
signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal ssram_ce1n : std_logic;
signal ssram_ce2 : std_logic;
signal ssram_ce3n : std_logic;
signal ssram_wen : std_logic;
signal ssram_bw : std_logic_vector (0 to 3);
signal ssram_oen : std_ulogic;
signal ssaddr : std_logic_vector(20 downto 2);
signal ssdata : std_logic_vector(31 downto 0);
signal ssram_clk : std_ulogic;
signal ssram_adscn : std_ulogic;
signal ssram_adsp_n : std_ulogic;
signal ssram_adv_n : std_ulogic;
signal datazz : std_logic_vector(3 downto 0);
-- ddr memory
signal ddr_clk : std_logic;
signal ddr_clkb : std_logic;
signal ddr_clkin : std_logic;
signal ddr_cke : std_logic;
signal ddr_csb : std_logic;
signal ddr_web : std_ulogic; -- ddr write enable
signal ddr_rasb : std_ulogic; -- ddr ras
signal ddr_casb : std_ulogic; -- ddr cas
signal ddr_dm : std_logic_vector (1 downto 0); -- ddr dm
signal ddr_dqs : std_logic_vector (1 downto 0); -- ddr dqs
signal ddr_dqs2 : std_logic_vector (1 downto 0); -- ddr dqs
signal ddr_ad : std_logic_vector (12 downto 0); -- ddr address
signal ddr_ba : std_logic_vector (1 downto 0); -- ddr bank address
signal ddr_dq, ddr_dq2 : std_logic_vector (15 downto 0); -- ddr data
signal plllock : std_ulogic;
signal txd1, rxd1 : std_ulogic;
--signal txd2, rxd2 : std_ulogic;
-- for smc lan chip
signal eth_aen : std_ulogic; -- for smsc eth
signal eth_readn : std_ulogic; -- for smsc eth
signal eth_writen : std_ulogic; -- for smsc eth
signal eth_nbe : std_logic_vector(3 downto 0); -- for smsc eth
signal eth_datacsn : std_ulogic;
constant lresp : boolean := false;
signal sa : std_logic_vector(14 downto 0);
signal sd : std_logic_vector(31 downto 0);
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
ddr_clkin <= not clk after ct * 1 ns;
rst <= dsurst;
dsubren <= '1'; rxd1 <= '1';
dqs2delay : delay_wire
generic map(data_width => ddr_dqs'length, delay_atob => 3.0, delay_btoa => 1.0)
port map(a => ddr_dqs, b => ddr_dqs2);
ddr2delay : delay_wire
generic map(data_width => ddr_dq'length, delay_atob => 3.0, delay_btoa => 1.0)
port map(a => ddr_dq, b => ddr_dq2);
-- ddr_dqs <= (others => 'L');
d3 : entity work.leon3mp generic map (fabtech, memtech, padtech, clktech,
ncpu, disas, dbguart, pclow )
port map (rst, clk, error,
address, data, romsn, oen, writen, open, open,
ssram_ce1n, ssram_ce2, ssram_ce3n, ssram_wen, ssram_bw, ssram_oen, ssaddr, ssdata,
ssram_clk, ssram_adscn, ssram_adsp_n, ssram_adv_n, iosn,
ddr_clkin, ddr_clk, ddr_clkb, ddr_cke, ddr_csb, ddr_web, ddr_rasb,
ddr_casb, ddr_dm, ddr_dqs2, ddr_ad, ddr_ba, ddr_dq2,
dsubren, dsuact, rxd1, txd1,
eth_aen, eth_readn, eth_writen, eth_nbe);
ddr2: ddrram
generic map (width => 16, abits => 13,
colbits => 9, rowbits => 12, implbanks => 1,
fname => sdramfile, igndqs => 1)
port map (
ck => ddr_clk, cke => ddr_cke, csn => ddr_csb,
rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web,
dm => ddr_dm, ba => ddr_ba, a => ddr_ad, dq => ddr_dq, dqs => ddr_dqs);
datazz <= "HHHH";
ssram0 : cy7c1380d generic map (fname => sramfile)
port map(
ioDq(35 downto 32) => datazz, ioDq(31 downto 0) => ssdata,
iAddr => ssaddr(20 downto 2), iMode => gnd,
inGW => vcc, inBWE => ssram_wen, inADV => ssram_adv_n,
inADSP => ssram_adsp_n, inADSC => ssram_adscn,
iClk => ssram_clk,
inBwa => ssram_bw(3), inBwb => ssram_bw(2),
inBwc => ssram_bw(1), inBwd => ssram_bw(0),
inOE => ssram_oen, inCE1 => ssram_ce1n,
iCE2 => ssram_ce2, inCE3 => ssram_ce3n, iZz => gnd);
-- 8 bit prom
prom0 : sram generic map (index => 6, abits => romdepth, fname => promfile)
port map (address(romdepth-1 downto 0), data(31 downto 24),
romsn, writen, oen);
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= buskeep(data), (others => 'H') after 250 ns;
sd <= buskeep(sd), (others => 'H') after 250 ns;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, oen, writen, open);
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library machxo2;
use machxo2.components.all;
entity FiRoE is
generic (
IMP : string := "HDL",
TOGGLE : boolean := true
);
port (
FiRo_o : out std_logic;
Run_i : in std_logic
);
end entity FiRoE;
architecture rtl of FiRoE is
--+ signal for inverter loop
signal s_ring : std_logic_vector(15 downto 0);
signal s_tff : std_logic;
--+ attributes for synthesis tool to preserve inverter loop
attribute syn_keep : boolean;
attribute syn_hier : string;
attribute syn_hier of rtl : architecture is "hard";
attribute syn_keep of s_ring : signal is true;
attribute syn_keep of s_tff : signal is true;
--+ Attributes for lattice map tool to not merging inverter loop
attribute nomerge : boolean;
attribute nomerge of s_ring : signal is true;
begin
FiroRingG : for index in 0 to 30 generate
HdlG : if IMP = "HDL" generate
s_ring(index) <= not(s_ring(index - 1));
end generate HdlG;
LutG : if IMP = "LUT" generate
lut : LUT4
generic map (
init => x"FFFF"
)
port map (
Z => s_ring(i-1),
A => s_ring(i),
B => '0',
C => '0',
D => '0'
);
end generate LutG;
end generate FiroRingG;
s_ring(0) <= (s_ring(15) xor s_ring(14) xor s_ring(7) xor s_ring(6) xor s_ring(5) xor s_ring(4) xor s_ring(2)) and Run_i;
WithToggleG : if TOGGLE generate
tffP : process(Run_i, s_ring(15)) is
begin
if(Run_i = '0') then
s_tff <= '0';
elsif(rising_edge(s_ring(15))) then
s_tff <= not s_tff;
end if;
end process tffP;
FiRo_o <= s_ring(15) xor s_tff;
end generate WithToggleG;
WithoutToggleG : if not(TOGGLE) generate
FiRo_o <= s_ring(15);
end generate WithoutToggleG;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
entity stb_gen is
generic (
period_g : in positive);
port (
rst_i : in std_ulogic := '0';
clk_i : in std_ulogic;
sync_rst_i : in std_ulogic := '0';
stb_i : in std_ulogic := '1';
stb_o : out std_ulogic);
end;
architecture rtl of stb_gen is
signal stb : std_ulogic := '0';
signal cnt : natural range 0 to period_g-1 := 0;
begin
process(rst_i, clk_i)
begin
if rst_i = '1' then
stb <= '0';
cnt <= 0;
elsif rising_edge(clk_i) then
stb <= '0';
if sync_rst_i = '1' then
cnt <= 0;
elsif stb_i = '1' then
if cnt = period_g-1 then
stb <= '1';
cnt <= 0;
else
cnt <= cnt + 1;
end if;
end if;
end if;
end process;
stb_o <= stb;
end;
|
package body my_pkg is
procedure some_proc (
a : integer;
b : integer
) is
constant some_const : integer_vector :=
some_proc(
arg1, arg2, arg3, arg4,
arg5, arg6, arg7
) ;
variable a, b, c, d, e, f, g : integer;
constant some_const : integer_vector :=
some_proc(
arg1, arg2, arg3, arg4,
arg5, arg6, arg7
) ;
begin
some_var := other_proc(a, b, c
d, e, f, g, h
i, j, k, l, m
);
some_other_var := other_other_proc(z);
end procedure some_proc;
end package body my_pkg;
architecture arch of ent is
begin
proc_label : process is
begin
var1 := 1;
sig1 <= 2 &
3 &
4;
sig2 <= 5;
sig3 <= 6;
end process proc_label;
PROC2_LABEL : process is
begin
if rising_edge(some_clk) then
a <= b;
end if;
end process PROC_LABEL;
end architecture arch;
|
-- modified 2006-05-13 (Line 404)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fifo_async_almost_full is
generic(
DEPTH : natural;
AWIDTH : natural;
DWIDTH : natural;
RAM_TYPE : string -- "BLOCK_RAM" or "DIS_RAM"
);
port(
reset : in std_logic;
clr : in std_logic;
clka : in std_logic;
wea : in std_logic;
dia : in std_logic_vector(DWIDTH - 1 downto 0);
clkb : in std_logic;
rdb : in std_logic;
dob : out std_logic_vector(DWIDTH - 1 downto 0); -- dob delay = 2 clk compared with rdb
empty : out std_logic;
full : out std_logic;
almost_full : out std_logic;
dn : out std_logic_vector(AWIDTH -1 downto 0)
);
end fifo_async_almost_full;
architecture fast_read of fifo_async_almost_full is
component blockdram
generic(
depth: integer;
Dwidth: integer;
Awidth: integer
);
port(
addra: IN std_logic_VECTOR(Awidth-1 downto 0);
clka: IN std_logic;
addrb: IN std_logic_VECTOR(Awidth-1 downto 0);
clkb: IN std_logic;
dia: IN std_logic_VECTOR(Dwidth-1 downto 0);
wea: IN std_logic;
dob: OUT std_logic_VECTOR(Dwidth-1 downto 0) := (others => '0')
);
end component;
component disdram
generic(
depth: integer;
Dwidth: integer;
Awidth: integer
);
port(
A: IN std_logic_VECTOR(Awidth-1 downto 0);
CLK: IN std_logic;
D: IN std_logic_VECTOR(Dwidth-1 downto 0);
WE: IN std_logic;
DPRA: IN std_logic_VECTOR(Awidth-1 downto 0);
DPO: OUT std_logic_VECTOR(Dwidth-1 downto 0);
QDPO: OUT std_logic_VECTOR(Dwidth-1 downto 0)
);
end component;
signal DPO : std_logic_vector(DWIDTH-1 downto 0) := (others => '0');
component ASYNCWRITE
port(
reset: in std_logic;
async_clk: in std_logic;
sync_clk: in std_logic;
async_wren: in std_logic;
trigger: in std_logic;
sync_wren: out std_logic;
over: out std_logic;
flag: out std_logic
);
end component;
signal wea_sync : std_logic := '0';
signal wp_sync : std_logic_vector(AWIDTH-1 downto 0) := (others => '0');
signal wp : std_logic_vector(AWIDTH - 1 downto 0) := (others => '0');
signal rp : std_logic_vector(AWIDTH - 1 downto 0) := (others => '0');
signal ram_we : std_logic := '0';
signal empty_flag : std_logic := '1';
signal full_flag : std_logic := '0';
begin
use_block_ram : if RAM_TYPE = "BLOCK_RAM" generate
ram : blockdram
generic map(
depth => DEPTH,
Dwidth => DWIDTH,
Awidth => AWIDTH
)
port map(
addra => wp,
clka => clka,
addrb => rp,
clkb => clkb,
dia => dia,
wea => ram_we,
dob => dob
);
end generate use_block_ram;
use_dis_ram : if RAM_TYPE = "DIS_RAM" generate
ram : disdram
generic map(
depth => DEPTH,
Dwidth => DWIDTH,
Awidth => AWIDTH
)
port map(
A => wp,
CLK => clka,
D => dia,
WE => ram_we,
DPRA => rp,
DPO => DPO,
QDPO => open
);
RegDout : process(reset,clkb)
begin
if reset = '1' then
dob <= (others => '0');
elsif rising_edge(clkb) then
dob <= DPO;
end if;
end process;
end generate use_dis_ram;
WritePointorCtrl : process(reset,clr,clka)
begin
if reset = '1' or clr = '1' then
wp <= (others => '0');
elsif rising_edge(clka) then
-- if clr = '1' then
-- wp <= (others => '0');
-- elsif full_flag = '0' and wea = '1' then
if full_flag = '0' and wea = '1' then
wp <= wp + 1;
end if;
end if;
end process;
ram_we <= wea when full_flag = '0' else '0';
ASYNCWRITE_wea_ins : ASYNCWRITE
port map(
reset => reset,
async_clk => clka,
sync_clk => clkb,
async_wren => wea,
trigger => '1',
sync_wren => wea_sync,
over => open,
flag => open
);
WritePointorCtrl_sync : process(reset,clr,clkb)
begin
if reset = '1' or clr = '1' then
wp_sync <= (others => '0');
elsif rising_edge(clkb) then
-- if clr = '1' then
-- wp_sync <= (others => '0');
-- elsif full_flag = '0' and wea_sync = '1' then
if full_flag = '0' and wea_sync = '1' then
wp_sync <= wp_sync + 1;
end if;
end if;
end process;
ReadPointorCtrl : process(reset,clr,clkb)
begin
if reset = '1' or clr = '1' then
rp <= (others => '0');
elsif rising_edge(clkb) then
-- if clr = '1' then
-- rp <= (others => '0');
-- elsif empty_flag = '0' and rdb = '1' then
if empty_flag = '0' and rdb = '1' then
rp <= rp + 1;
end if;
end if;
end process;
GetEmptyFlag : process(reset,clr,clkb)
begin
if reset = '1' or clr = '1' then
empty_flag <= '1';
elsif rising_edge(clkb) then
-- if clr = '1' then
-- empty_flag <= '1';
-- elsif (wp_sync = rp) and (wea_sync = '1') then
if (wp_sync = rp) and (wea_sync = '1') then
empty_flag <= '0';
elsif (wp_sync = rp + 1) and (rdb = '1'and wea_sync = '0') then
empty_flag <= '1';
end if;
end if;
end process;
empty <= empty_flag;
GetFullFlag : process(reset,clr,clkb)
begin
if reset = '1' or clr = '1' then
full_flag <= '0';
elsif rising_edge(clkb) then
-- if clr = '1' then
-- full_flag <= '0';
-- elsif (wp_sync = rp - 1) and (wea_sync = '1' and rdb = '0') then
if (wp_sync = rp - 1) and (wea_sync = '1' and rdb = '0') then
full_flag <= '1';
elsif (wp_sync = rp) and (rdb = '1') then
full_flag <= '0';
end if;
end if;
end process;
full <= full_flag;
dn <= wp_sync - rp;
end fast_read;
---------------------------------------------------------------------------------
architecture fast_write of fifo_async_almost_full is
component blockdram
generic(
depth: integer;
Dwidth: integer;
Awidth: integer
);
port(
addra: IN std_logic_VECTOR(Awidth-1 downto 0);
clka: IN std_logic;
addrb: IN std_logic_VECTOR(Awidth-1 downto 0);
clkb: IN std_logic;
dia: IN std_logic_VECTOR(Dwidth-1 downto 0);
wea: IN std_logic;
dob: OUT std_logic_VECTOR(Dwidth-1 downto 0) := (others => '0')
);
end component;
component disdram
generic(
depth: integer;
Dwidth: integer;
Awidth: integer
);
port(
A: IN std_logic_VECTOR(Awidth-1 downto 0);
CLK: IN std_logic;
D: IN std_logic_VECTOR(Dwidth-1 downto 0);
WE: IN std_logic;
DPRA: IN std_logic_VECTOR(Awidth-1 downto 0);
DPO: OUT std_logic_VECTOR(Dwidth-1 downto 0);
QDPO: OUT std_logic_VECTOR(Dwidth-1 downto 0)
);
end component;
signal DPO : std_logic_vector(DWIDTH-1 downto 0) := (others => '0');
component ASYNCWRITE
port(
reset: in std_logic;
async_clk: in std_logic;
sync_clk: in std_logic;
async_wren: in std_logic;
trigger: in std_logic;
sync_wren: out std_logic;
over: out std_logic;
flag: out std_logic
);
end component;
signal rdb_sync : std_logic := '0';
signal rp_sync : std_logic_vector(AWIDTH-1 downto 0) := (others => '0');
signal wp : std_logic_vector(AWIDTH - 1 downto 0) := (others => '0');
signal rp : std_logic_vector(AWIDTH - 1 downto 0) := (others => '0');
signal ram_we : std_logic := '0';
signal empty_flag : std_logic := '1';
signal full_flag : std_logic := '0';
begin
use_block_ram : if RAM_TYPE = "BLOCK_RAM" generate
ram : blockdram
generic map(
depth => DEPTH,
Dwidth => DWIDTH,
Awidth => AWIDTH
)
port map(
addra => wp,
clka => clka,
addrb => rp,
clkb => clkb,
dia => dia,
wea => ram_we,
dob => dob
);
end generate use_block_ram;
use_dis_ram : if RAM_TYPE = "DIS_RAM" generate
ram : disdram
generic map(
depth => DEPTH,
Dwidth => DWIDTH,
Awidth => AWIDTH
)
port map(
A => wp,
CLK => clka,
D => dia,
WE => ram_we,
DPRA => rp,
DPO => DPO,
QDPO => open
);
RegDout : process(reset,clkb)
begin
if reset = '1' then
dob <= (others => '0');
elsif rising_edge(clkb) then
dob <= DPO;
end if;
end process;
end generate use_dis_ram;
WritePointorCtrl : process(reset,clr,clka)
begin
if reset = '1' or clr = '1' then
wp <= (others => '0');
elsif rising_edge(clka) then
-- if clr = '1' then
-- wp <= (others => '0');
-- elsif full_flag = '0' and wea = '1' then
if full_flag = '0' and wea = '1' then
wp <= wp + 1;
end if;
end if;
end process;
ram_we <= wea when full_flag = '0' else '0';
ReadPointorCtrl : process(reset,clr,clkb)
begin
if reset = '1' or clr = '1' then
rp <= (others => '0');
elsif rising_edge(clkb) then
-- if clr = '1' then
-- rp <= (others => '0');
-- elsif empty_flag = '0' and rdb = '1' then
if empty_flag = '0' and rdb = '1' then
rp <= rp + 1;
end if;
end if;
end process;
ASYNCWRITE_rdb_ins : ASYNCWRITE
port map(
reset => reset,
async_clk => clkb,
sync_clk => clka,
async_wren => rdb,
trigger => '1',
sync_wren => rdb_sync,
over => open,
flag => open
);
ReadPointorCtrl_sync : process(reset,clr,clka)
begin
if reset = '1' or clr = '1' then
rp_sync <= (others => '0');
elsif rising_edge(clka) then
-- if clr = '1' then
-- rp_sync <= (others => '0');
-- elsif empty_flag = '0' and rdb_sync = '1' then
if empty_flag = '0' and rdb_sync = '1' then
rp_sync <= rp_sync + 1;
end if;
end if;
end process;
GetEmptyFlag : process(reset,clr,clka)
begin
if reset = '1' or clr = '1' then
empty_flag <= '1';
elsif rising_edge(clka) then
-- if clr = '1' then
-- empty_flag <= '1';
-- elsif (wp = rp_sync) and (wea = '1') then
if (wp = rp_sync) and (wea = '1') then
empty_flag <= '0';
elsif (wp = rp_sync + 1) and (rdb_sync = '1'and wea = '0') then
empty_flag <= '1';
end if;
end if;
end process;
empty <= empty_flag;
GetFullFlag : process(reset,clr,clka)
begin
if reset = '1' or clr = '1' then
full_flag <= '0'; -- modified 2006-05-13
elsif rising_edge(clka) then
-- if clr = '1' then
-- full_flag <= '0';
-- elsif (wp = rp_sync - 1) and (wea = '1' and rdb_sync = '0') then
if (wp = rp_sync - 1) and (wea = '1' and rdb_sync = '0') then
full_flag <= '1';
elsif (wp = rp_sync) and (rdb_sync = '1') then
full_flag <= '0';
end if;
end if;
end process;
full <= full_flag;
GetAlmostFull : process(reset,clr,clka)
begin
if reset = '1' or clr = '1' then
almost_full <= '0'; -- modified 2006-05-13
elsif rising_edge(clka) then
-- if clr = '1' then
-- almost_full <= '0';
-- elsif (wp = rp_sync - 2) and (wea = '1' and rdb_sync = '0') then
if (wp = rp_sync - 2) and (wea = '1' and rdb_sync = '0') then
almost_full <= '1';
elsif (wp = rp_sync - 1) and (wea = '0' and rdb_sync = '1') then
almost_full <= '0';
end if;
end if;
end process;
dn <= wp - rp_sync;
end fast_write;
|
---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.ALL;
use ieee.numeric_std.ALL;
use IEEE.STD_LOGIC_MISC.all;
library work;
use work.zpupkg.all;
ENTITY zpu_glue IS
PORT
(
CLK : in std_logic;
RESET : in std_logic;
PAUSE : in std_logic;
ZPU_DI : in std_logic_vector(31 downto 0); -- response from general memory - for areas that only support 8/16 bit set top bits to 0
ZPU_ROM_DI : in std_logic_vector(31 downto 0); -- response from own program memory
ZPU_RAM_DI : in std_logic_vector(31 downto 0); -- response from own stack
ZPU_CONFIG_DI : in std_logic_vector(31 downto 0); -- response from config registers
ZPU_DO : out std_logic_vector(31 downto 0);
ZPU_ADDR_ROM_RAM : out std_logic_vector(15 downto 0); -- direct from zpu, for short paths
ZPU_ADDR_FETCH : out std_logic_vector(23 downto 0); -- clk->q, for longer paths
-- request
MEMORY_FETCH : out std_logic;
ZPU_READ_ENABLE : out std_logic;
ZPU_32BIT_WRITE_ENABLE : out std_logic; -- common case
ZPU_16BIT_WRITE_ENABLE : out std_logic; -- for sram (never happens yet!)
ZPU_8BIT_WRITE_ENABLE : out std_logic; -- for hardware regs
-- config
ZPU_CONFIG_WRITE : out std_logic;
-- stack request
ZPU_STACK_WRITE : out std_logic_vector(3 downto 0);
-- write to ROM!!
ZPU_ROM_WREN : out std_logic;
-- response
MEMORY_READY : in std_logic
);
END zpu_glue;
architecture sticky of zpu_glue is
component ZPUMediumCore is
generic(
WORD_SIZE : integer:=32; -- 16/32 (2**wordPower)
ADDR_W : integer:=24; -- Total address space width (incl. I/O)
MEM_W : integer:=16; -- Memory (prog+data+stack) width - stack at end of memory - so end of sdram. 32K ROM, 32K RAM (MAX)
D_CARE_VAL : std_logic:='X'; -- Value used to fill the unsused bits
MULT_PIPE : boolean:=false; -- Pipeline multiplication
BINOP_PIPE : integer range 0 to 2:=0; -- Pipeline binary operations (-, =, < and <=)
ENA_LEVEL0 : boolean:=true; -- eq, loadb, neqbranch and pushspadd
ENA_LEVEL1 : boolean:=true; -- lessthan, ulessthan, mult, storeb, callpcrel and sub
ENA_LEVEL2 : boolean:=true; -- lessthanorequal, ulessthanorequal, call and poppcrel
ENA_LSHR : boolean:=true; -- lshiftright
ENA_IDLE : boolean:=false; -- Enable the enable_i input
FAST_FETCH : boolean:=true); -- Merge the st_fetch with the st_execute states
port(
clk_i : in std_logic; -- CPU Clock
reset_i : in std_logic; -- Sync Reset
enable_i : in std_logic; -- Hold the CPU (after reset)
break_o : out std_logic; -- Break instruction executed
dbg_o : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
-- Memory interface
mem_busy_i : in std_logic; -- Memory is busy
data_i : in unsigned(WORD_SIZE-1 downto 0); -- Data from mem
data_o : out unsigned(WORD_SIZE-1 downto 0); -- Data to mem
addr_o : out unsigned(ADDR_W-1 downto 0); -- Memory address
write_en_o : out std_logic; -- Memory write enable (32-bit)
read_en_o : out std_logic; -- Memory read enable (32-bit)
byte_read_o : out std_logic;
byte_write_o : out std_logic;
short_write_o: out std_logic); -- never happens
end component;
signal zpu_addr_unsigned : unsigned(23 downto 0);
signal zpu_do_unsigned : unsigned(31 downto 0);
signal ZPU_DI_unsigned : unsigned(31 downto 0);
signal zpu_break : std_logic;
signal zpu_debug : zpu_dbgo_t;
signal zpu_mem_busy : std_logic;
signal zpu_memory_fetch_pending_next : std_logic;
signal zpu_memory_fetch_pending_reg : std_logic;
signal ZPU_32bit_READ_ENABLE_temp : std_logic;
signal ZPU_8bit_READ_ENABLE_temp : std_logic;
signal ZPU_READ_temp : std_logic;
signal ZPU_32BIT_WRITE_ENABLE_temp : std_logic;
signal ZPU_16BIT_WRITE_ENABLE_temp : std_logic;
signal ZPU_8BIT_WRITE_ENABLE_temp : std_logic;
signal ZPU_WRITE_temp : std_logic;
signal ZPU_32BIT_WRITE_ENABLE_next : std_logic;
signal ZPU_16BIT_WRITE_ENABLE_next : std_logic;
signal ZPU_8BIT_WRITE_ENABLE_next : std_logic;
signal ZPU_READ_next : std_logic;
signal ZPU_32BIT_WRITE_ENABLE_reg : std_logic;
signal ZPU_16BIT_WRITE_ENABLE_reg : std_logic;
signal ZPU_8BIT_WRITE_ENABLE_reg : std_logic;
signal ZPU_READ_reg : std_logic;
signal block_mem : std_logic;
signal config_mem : std_logic;
signal special_mem : std_logic;
signal result_next : std_logic_vector(4 downto 0);
signal result_reg : std_logic_vector(4 downto 0);
constant result_external : std_logic_vector(4 downto 0) := "00000";
constant result_ram : std_logic_vector(4 downto 0) := "00001";
constant result_ram_8bit_0 : std_logic_vector(4 downto 0) := "00010";
constant result_ram_8bit_1 : std_logic_vector(4 downto 0) := "00011";
constant result_ram_8bit_2 : std_logic_vector(4 downto 0) := "00100";
constant result_ram_8bit_3 : std_logic_vector(4 downto 0) := "00101";
constant result_rom : std_logic_vector(4 downto 0) := "00110";
constant result_rom_8bit_0 : std_logic_vector(4 downto 0) := "00111";
constant result_rom_8bit_1 : std_logic_vector(4 downto 0) := "01000";
constant result_rom_8bit_2 : std_logic_vector(4 downto 0) := "01001";
constant result_rom_8bit_3 : std_logic_vector(4 downto 0) := "01010";
constant result_config : std_logic_vector(4 downto 0) := "01011";
constant result_external_special : std_logic_vector(4 downto 0) := "01100";
signal request_type : std_logic_vector(4 downto 0);
signal zpu_di_use : std_logic_vector(31 downto 0);
signal memORY_ACCESS : std_logic;
-- 1 cycle delay on memory read - needed to allow running at higher clock
signal zpu_di_next : std_logic_vector(31 downto 0);
signal zpu_di_reg : std_logic_vector(31 downto 0);
signal memory_ready_next : std_logic;
signal memory_ready_reg : std_logic;
signal zpu_enable : std_logic;
signal zpu_addr_next : std_logic_vector(23 downto 0);
signal zpu_addr_reg : std_logic_vector(23 downto 0);
signal ZPU_DO_next : std_logic_vector(31 downto 0);
signal ZPU_DO_reg : std_logic_vector(31 downto 0);
begin
-- register
process(clk,reset)
begin
if (reset='1') then
zpu_memory_fetch_pending_reg <= '0';
result_reg <= result_rom;
zpu_di_reg <= (others=>'0');
zpu_do_reg <= (others=>'0');
memory_ready_reg <= '0';
zpu_addr_reg <= (others=>'0');
ZPU_32BIT_WRITE_ENABLE_reg <= '0';
ZPU_16BIT_WRITE_ENABLE_reg <= '0';
ZPU_8BIT_WRITE_ENABLE_reg <= '0';
ZPU_READ_reg <= '0';
elsif (clk'event and clk='1') then
zpu_memory_fetch_pending_reg <= zpu_memory_fetch_pending_next;
result_reg <= result_next;
zpu_di_reg <= zpu_di_next;
zpu_do_reg <= zpu_do_next;
memory_ready_reg <= memORY_READY_next;
zpu_addr_reg <=zpu_addr_next;
ZPU_32BIT_WRITE_ENABLE_reg <= ZPU_32BIT_WRITE_ENABLE_next;
ZPU_16BIT_WRITE_ENABLE_reg <= ZPU_16BIT_WRITE_ENABLE_next;
ZPU_8BIT_WRITE_ENABLE_reg <= ZPU_8BIT_WRITE_ENABLE_next;
ZPU_READ_reg <= ZPU_READ_next;
end if;
end process;
-- a little glue
process(zpu_ADDR_unsigned)
begin
block_mem <= '0';
config_mem <= '0';
special_mem <= '0';
-- $00000-$0FFFF = Own ROM/RAM
-- $10000-$1FFFF = Atari
-- $20000-$2FFFF = Atari - savestate (gtia/antic/pokey have memory behind them)
-- $40000-$4FFFF = Config area
if (or_reduce(std_logic_vector(zpu_ADDR_unsigned(23 downto 21))) = '0') then -- special area
block_mem <= not(zpu_addr_unsigned(18) or zpu_addr_unsigned(17) or zpu_addr_unsigned(16));
config_mem <= zpu_addr_unsigned(18);
special_mem <= zpu_addr_unsigned(17);
end if;
end process;
ZPU_READ_TEMP <= zpu_32bit_read_enable_temp or zpu_8BIT_read_enable_temp;
ZPU_WRITE_TEMP<= zpu_32BIT_WRITE_ENABLE_temp or zpu_16BIT_WRITE_ENABLE_temp or zpu_8BIT_WRITE_ENABLE_temp;
process(zpu_addr_reg,pause,memory_ready,zpu_memory_fetch_pending_next,request_type, zpu_memory_fetch_pending_reg, memory_ready_reg, zpu_ADDR_unsigned, zpu_8bit_read_enable_temp, zpu_write_temp, result_reg, block_mem, config_mem, special_mem, memORY_ACCESS,
zpu_read_reg,zpu_8BIT_WRITE_ENABLE_reg, zpu_16BIT_WRITE_ENABLE_reg, zpu_32BIT_WRITE_ENABLE_reg,
zpu_read_temp,zpu_8BIT_WRITE_ENABLE_temp, zpu_16BIT_WRITE_ENABLE_temp, zpu_32BIT_WRITE_ENABLE_temp,
zpu_do_unsigned, zpu_do_reg
)
begin
zpu_memory_fetch_pending_next <= zpu_memory_fetch_pending_reg;
result_next <= result_reg;
memory_ready_next <= memory_ready;
zpu_stACK_WRITE <= (others=>'0');
ZPU_ROM_WREN <= '0';
ZPU_config_write <= '0';
zpu_addr_next <= zpu_addr_reg;
zpu_do_next <= zpu_do_reg;
ZPU_MEM_BUSY <= pause;
MEMORY_ACCESS <= zpu_READ_temp or ZPU_WRITE_temp;
if (memory_access = '1') then
zpu_do_next <= std_logic_vector(zpu_do_unsigned);
end if;
memory_fetch <= zpu_memory_fetch_pending_reg;
zpu_read_next <= zpu_read_reg;
zpu_8bit_write_enable_next <= zpu_8bit_write_enable_reg;
zpu_16bit_write_enable_next <= zpu_16bit_write_enable_reg;
zpu_32bit_write_enable_next <= zpu_32bit_write_enable_reg;
request_type <= config_mem&block_mem&zpu_addr_unsigned(15)&memORY_ACCESS&zpu_memory_fetch_pending_reg;
case request_type is
when "00010"|"00110" =>
zpu_memory_fetch_pending_next <= '1';
if (special_mem='0') then
result_next <= result_external;
else
result_next <= result_external_special;
end if;
ZPU_MEM_BUSY <= '1';
zpu_addr_next <= std_logic_vector(zpu_addr_unsigned);
zpu_read_next <= zpu_read_temp;
zpu_8bit_write_enable_next <= zpu_8bit_write_enable_temp;
zpu_16bit_write_enable_next <= zpu_16bit_write_enable_temp;
zpu_32bit_write_enable_next <= zpu_32bit_write_enable_temp;
when "01010" =>
if (zpu_8bit_read_enable_temp='1') then
case (zpu_addr_unsigned(1 downto 0)) is
when "00" =>
result_next <= result_rom_8bit_3;
when "01" =>
result_next <= result_rom_8bit_2;
when "10" =>
result_next <= result_rom_8bit_1;
when "11" =>
result_next <= result_rom_8bit_0;
when others =>
--nop
end case;
else
result_next <= result_rom;
end if;
ZPU_ROM_WREN <= ZPU_WRITE_TEMP;
ZPU_MEM_BUSY <= '1';
zpu_addr_next <= std_logic_vector(zpu_addr_unsigned);
when "01110" =>
if (zpu_8bit_read_enable_temp='1' or zpu_8BIT_WRITE_ENABLE_temp='1') then
case (zpu_addr_unsigned(1 downto 0)) is
when "00" =>
result_next <= result_ram_8bit_3;
ZPU_STACK_WRITE(3) <= zpu_8BIT_write_enable_temp;
when "01" =>
result_next <= result_ram_8bit_2;
ZPU_STACK_WRITE(2) <= zpu_8BIT_write_enable_temp;
when "10" =>
result_next <= result_ram_8bit_1;
ZPU_STACK_WRITE(1) <= zpu_8BIT_write_enable_temp;
when "11" =>
result_next <= result_ram_8bit_0;
ZPU_STACK_WRITE(0) <= zpu_8BIT_write_enable_temp;
when others =>
--nop
end case;
else
result_next <= result_ram;
ZPU_STACK_WRITE <= (others=>zpu_write_temp);
end if;
ZPU_MEM_BUSY <= '1';
zpu_addr_next <= std_logic_vector(zpu_addr_unsigned);
when "10110"|"10010" =>
result_next <= result_config;
ZPU_MEM_BUSY <= '1';
ZPU_config_write <= ZPU_WRITE_temp;
zpu_addr_next <= std_logic_vector(zpu_addr_unsigned);
when "00001"|"00011"|"00101"|"00111"|"01001"|"01011"|"01101"|"01111"|
"10001"|"10011"|"10101"|"10111"|"11001"|"11011"|"11101"|"11111"|"00X01" =>
ZPU_MEM_BUSY <= not(memORY_READY_reg) or pause;
zpu_memory_fetch_pending_next <= not(memORY_READY);
when others =>
-- nop
end case;
end process;
zpu_di_next <= zpu_di;
process(result_reg, zpu_di_reg, zpu_rom_di, zpu_ram_di, zpu_config_di)
begin
zpu_di_use <= (others=>'0');
case result_reg is
when result_external =>
zpu_di_use <= zpu_di_reg;
when result_external_special =>
zpu_di_use(7 downto 0) <= zpu_di_reg(15 downto 8);
when result_rom =>
zpu_di_use <= zpu_rom_DI;
when result_rom_8bit_0 =>
zpu_di_use(7 downto 0) <= zpu_rom_DI(7 downto 0);
when result_rom_8bit_1 =>
zpu_di_use(7 downto 0) <= zpu_rom_DI(15 downto 8);
when result_rom_8bit_2 =>
zpu_di_use(7 downto 0) <= zpu_rom_DI(23 downto 16);
when result_rom_8bit_3 =>
zpu_di_use(7 downto 0) <= zpu_rom_DI(31 downto 24);
when result_ram =>
zpu_di_use <= zpu_ram_DI;
when result_ram_8bit_0 =>
zpu_di_use(7 downto 0) <= zpu_ram_DI(7 downto 0);
when result_ram_8bit_1 =>
zpu_di_use(7 downto 0) <= zpu_ram_DI(15 downto 8);
when result_ram_8bit_2 =>
zpu_di_use(7 downto 0) <= zpu_ram_DI(23 downto 16);
when result_ram_8bit_3 =>
zpu_di_use(7 downto 0) <= zpu_ram_DI(31 downto 24);
when result_config =>
zpu_di_use <= zpu_config_di;
when others =>
-- nothing
end case;
end process;
-- zpu itself
--zpu_enable <= enable and not(pause);
zpu_enable <= '1'; -- does nothing useful...
myzpu: ZPUMediumCore
port map (clk_i=>clk, reset_i=>reset,enable_i=>zpu_enable,break_o=>zpu_break,dbg_o=>zpu_debug,mem_busy_i=>ZPU_MEM_BUSY,
data_i=>zpu_di_unsigned,data_o=>zpu_do_unsigned,addr_o=>zpu_addr_unsigned,write_en_o=>zpu_32bit_write_enable_temp,read_en_o=>zpu_32bit_read_enable_temp,
byte_read_o=>zpu_8bit_read_enable_temp, byte_write_o=>zpu_8bit_write_enable_temp,short_write_o=>zpu_16bit_write_enable_temp);
zpu_di_unsigned <= unsigned(zpu_di_use);
zpu_do <= zpu_do_next;
ZPU_ADDR_ROM_RAM <= zpu_addr_next(15 downto 0);
ZPU_ADDR_FETCH <= zpu_addr_reg;
zpu_read_enable <= zpu_read_reg;
zpu_8bit_write_enable <= zpu_8bit_write_enable_reg;
zpu_16bit_write_enable <= zpu_16bit_write_enable_reg;
zpu_32bit_write_enable <= zpu_32bit_write_enable_reg;
end sticky;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:33:47 2017
-- Host : KLight-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/bg_pole/bg_pole_sim_netlist.vhdl
-- Design : bg_pole
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_pole_blk_mem_gen_prim_wrapper_init is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 6 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_pole_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end bg_pole_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of bg_pole_blk_mem_gen_prim_wrapper_init is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_0\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_1\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_10\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_11\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_12\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_16\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_17\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_18\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_19\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_2\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_20\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_24\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_25\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_26\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_27\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_28\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_3\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_32\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_33\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_34\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_35\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_4\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_8\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_9\ : STD_LOGIC;
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 1,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000006050607040603010000000000000000030506070706010000000000",
INIT_01 => X"0000020007060100040603010000000000000000060506070706010000000000",
INIT_02 => X"0000000004060301070601000004000000000000060506070406030100000000",
INIT_03 => X"0000000006050607040603010000000000000000030506070706010000000000",
INIT_04 => X"0000000006050607070601000000000000000000050606060406030100040000",
INIT_05 => X"0000000004060301070601000004000000000000060506070406030100000000",
INIT_06 => X"0000000003050607070601000000000000000000060506070406030100040000",
INIT_07 => X"0000000006050607070601000000000000000000050606060406030100040000",
INIT_08 => X"0000000006050607040603010000000000000200070601000406030100000000",
INIT_09 => X"0000000003050607070601000000000000000000060506070406030100040000",
INIT_0A => X"0000000005060606040603010004000000000000060506070406030100000000",
INIT_0B => X"0000000006050607040603010000000000000200070601000406030100000000",
INIT_0C => X"0000000006050607040603010004000000000000040603010706010000040000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 18,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 18
)
port map (
ADDRARDADDR(13 downto 12) => B"00",
ADDRARDADDR(11 downto 5) => addra(6 downto 0),
ADDRARDADDR(4 downto 0) => B"00000",
ADDRBWRADDR(13 downto 12) => B"00",
ADDRBWRADDR(11 downto 5) => addra(6 downto 0),
ADDRBWRADDR(4 downto 0) => B"10000",
CLKARDCLK => clka,
CLKBWRCLK => clka,
DIADI(15 downto 11) => B"00000",
DIADI(10 downto 8) => dina(5 downto 3),
DIADI(7 downto 3) => B"00000",
DIADI(2 downto 0) => dina(2 downto 0),
DIBDI(15 downto 11) => B"00000",
DIBDI(10 downto 8) => dina(11 downto 9),
DIBDI(7 downto 3) => B"00000",
DIBDI(2 downto 0) => dina(8 downto 6),
DIPADIP(1 downto 0) => B"00",
DIPBDIP(1 downto 0) => B"00",
DOADO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_0\,
DOADO(14) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_1\,
DOADO(13) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_2\,
DOADO(12) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_3\,
DOADO(11) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_4\,
DOADO(10 downto 8) => douta(5 downto 3),
DOADO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_8\,
DOADO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_9\,
DOADO(5) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_10\,
DOADO(4) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_11\,
DOADO(3) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_12\,
DOADO(2 downto 0) => douta(2 downto 0),
DOBDO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_16\,
DOBDO(14) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_17\,
DOBDO(13) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_18\,
DOBDO(12) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_19\,
DOBDO(11) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_20\,
DOBDO(10 downto 8) => douta(11 downto 9),
DOBDO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_24\,
DOBDO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_25\,
DOBDO(5) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_26\,
DOBDO(4) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_27\,
DOBDO(3) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_28\,
DOBDO(2 downto 0) => douta(8 downto 6),
DOPADOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_32\,
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_33\,
DOPBDOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_34\,
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_35\,
ENARDEN => '1',
ENBWREN => '1',
REGCEAREGCE => '1',
REGCEB => '1',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(3 downto 2) => B"00",
WEBWE(1) => wea(0),
WEBWE(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_pole_blk_mem_gen_prim_width is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 6 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_pole_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end bg_pole_blk_mem_gen_prim_width;
architecture STRUCTURE of bg_pole_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.bg_pole_blk_mem_gen_prim_wrapper_init
port map (
addra(6 downto 0) => addra(6 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_pole_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 6 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_pole_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end bg_pole_blk_mem_gen_generic_cstr;
architecture STRUCTURE of bg_pole_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.bg_pole_blk_mem_gen_prim_width
port map (
addra(6 downto 0) => addra(6 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_pole_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 6 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_pole_blk_mem_gen_top : entity is "blk_mem_gen_top";
end bg_pole_blk_mem_gen_top;
architecture STRUCTURE of bg_pole_blk_mem_gen_top is
begin
\valid.cstr\: entity work.bg_pole_blk_mem_gen_generic_cstr
port map (
addra(6 downto 0) => addra(6 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_pole_blk_mem_gen_v8_3_5_synth is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 6 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_pole_blk_mem_gen_v8_3_5_synth : entity is "blk_mem_gen_v8_3_5_synth";
end bg_pole_blk_mem_gen_v8_3_5_synth;
architecture STRUCTURE of bg_pole_blk_mem_gen_v8_3_5_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.bg_pole_blk_mem_gen_top
port map (
addra(6 downto 0) => addra(6 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_pole_blk_mem_gen_v8_3_5 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 6 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 6 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 11 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 11 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 6 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 6 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of bg_pole_blk_mem_gen_v8_3_5 : entity is 7;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of bg_pole_blk_mem_gen_v8_3_5 : entity is 7;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of bg_pole_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of bg_pole_blk_mem_gen_v8_3_5 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of bg_pole_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of bg_pole_blk_mem_gen_v8_3_5 : entity is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of bg_pole_blk_mem_gen_v8_3_5 : entity is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of bg_pole_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of bg_pole_blk_mem_gen_v8_3_5 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of bg_pole_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of bg_pole_blk_mem_gen_v8_3_5 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of bg_pole_blk_mem_gen_v8_3_5 : entity is "Estimated Power for IP : 2.7064499999999998 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of bg_pole_blk_mem_gen_v8_3_5 : entity is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of bg_pole_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of bg_pole_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of bg_pole_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of bg_pole_blk_mem_gen_v8_3_5 : entity is "bg_pole.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of bg_pole_blk_mem_gen_v8_3_5 : entity is "bg_pole.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of bg_pole_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of bg_pole_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of bg_pole_blk_mem_gen_v8_3_5 : entity is 104;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of bg_pole_blk_mem_gen_v8_3_5 : entity is 104;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of bg_pole_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of bg_pole_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of bg_pole_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of bg_pole_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of bg_pole_blk_mem_gen_v8_3_5 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of bg_pole_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of bg_pole_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of bg_pole_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of bg_pole_blk_mem_gen_v8_3_5 : entity is 104;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of bg_pole_blk_mem_gen_v8_3_5 : entity is 104;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of bg_pole_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of bg_pole_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of bg_pole_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of bg_pole_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of bg_pole_blk_mem_gen_v8_3_5 : entity is "artix7";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_pole_blk_mem_gen_v8_3_5 : entity is "blk_mem_gen_v8_3_5";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of bg_pole_blk_mem_gen_v8_3_5 : entity is "yes";
end bg_pole_blk_mem_gen_v8_3_5;
architecture STRUCTURE of bg_pole_blk_mem_gen_v8_3_5 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
doutb(11) <= \<const0>\;
doutb(10) <= \<const0>\;
doutb(9) <= \<const0>\;
doutb(8) <= \<const0>\;
doutb(7) <= \<const0>\;
doutb(6) <= \<const0>\;
doutb(5) <= \<const0>\;
doutb(4) <= \<const0>\;
doutb(3) <= \<const0>\;
doutb(2) <= \<const0>\;
doutb(1) <= \<const0>\;
doutb(0) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.bg_pole_blk_mem_gen_v8_3_5_synth
port map (
addra(6 downto 0) => addra(6 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_pole is
port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 6 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of bg_pole : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of bg_pole : entity is "bg_pole,blk_mem_gen_v8_3_5,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of bg_pole : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of bg_pole : entity is "blk_mem_gen_v8_3_5,Vivado 2016.4";
end bg_pole;
architecture STRUCTURE of bg_pole is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 6 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 6 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 7;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 7;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "0";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 2.7064499999999998 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "bg_pole.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "bg_pole.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 104;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 104;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 12;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 12;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 104;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 104;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 12;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "artix7";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.bg_pole_blk_mem_gen_v8_3_5
port map (
addra(6 downto 0) => addra(6 downto 0),
addrb(6 downto 0) => B"0000000",
clka => clka,
clkb => '0',
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(11 downto 0) => dina(11 downto 0),
dinb(11 downto 0) => B"000000000000",
douta(11 downto 0) => douta(11 downto 0),
doutb(11 downto 0) => NLW_U0_doutb_UNCONNECTED(11 downto 0),
eccpipece => '0',
ena => '0',
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(6 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(6 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => '0',
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(6 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(6 downto 0),
s_axi_rdata(11 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(11 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(11 downto 0) => B"000000000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity pwl_load is
generic ( load_enable : boolean := true;
res_init : resistance;
res1 : resistance;
t1 : time;
res2 : resistance;
t2 : time );
port ( terminal p1, p2 : electrical );
end entity pwl_load;
----------------------------------------------------------------
architecture ideal of pwl_load is
quantity v across i through p1 to p2;
signal res_signal : resistance := res_init;
begin
load_present : if load_enable generate
if domain = quiescent_domain or domain = frequency_domain use
v == i * res_init;
else
v == i * res_signal'ramp(1.0e-6, 1.0e-6);
end use;
create_event : process is
begin
wait for t1;
res_signal <= res1;
wait for t2 - t1;
res_signal <= res2;
wait;
end process create_event;
end generate load_present;
load_absent : if not load_enable generate
i == 0.0;
end generate load_absent;
end architecture ideal;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity pwl_load is
generic ( load_enable : boolean := true;
res_init : resistance;
res1 : resistance;
t1 : time;
res2 : resistance;
t2 : time );
port ( terminal p1, p2 : electrical );
end entity pwl_load;
----------------------------------------------------------------
architecture ideal of pwl_load is
quantity v across i through p1 to p2;
signal res_signal : resistance := res_init;
begin
load_present : if load_enable generate
if domain = quiescent_domain or domain = frequency_domain use
v == i * res_init;
else
v == i * res_signal'ramp(1.0e-6, 1.0e-6);
end use;
create_event : process is
begin
wait for t1;
res_signal <= res1;
wait for t2 - t1;
res_signal <= res2;
wait;
end process create_event;
end generate load_present;
load_absent : if not load_enable generate
i == 0.0;
end generate load_absent;
end architecture ideal;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity pwl_load is
generic ( load_enable : boolean := true;
res_init : resistance;
res1 : resistance;
t1 : time;
res2 : resistance;
t2 : time );
port ( terminal p1, p2 : electrical );
end entity pwl_load;
----------------------------------------------------------------
architecture ideal of pwl_load is
quantity v across i through p1 to p2;
signal res_signal : resistance := res_init;
begin
load_present : if load_enable generate
if domain = quiescent_domain or domain = frequency_domain use
v == i * res_init;
else
v == i * res_signal'ramp(1.0e-6, 1.0e-6);
end use;
create_event : process is
begin
wait for t1;
res_signal <= res1;
wait for t2 - t1;
res_signal <= res2;
wait;
end process create_event;
end generate load_present;
load_absent : if not load_enable generate
i == 0.0;
end generate load_absent;
end architecture ideal;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity RS232 is
Port ( clk : in STD_LOGIC;
-- Trasmisor --
Entrada_8bits : in STD_LOGIC_VECTOR (7 downto 0);
Activador_Envio_Mensaje : in STD_LOGIC;
Salida_1bit : out STD_LOGIC := '1';
-- Receptor --
Entrada_1bit : in STD_LOGIC;
Mensaje_8bits : out STD_LOGIC_VECTOR (7 downto 0) := "00000000";
Activador_Entrega_Mensaje : out STD_LOGIC := '0');
end RS232;
architecture arq_RS232 of RS232 is
component Divisor_Frecuencia
Port(
clk : in STD_LOGIC;
Salida : out STD_LOGIC
);
end component;
component Reception_8bits
Port(
Divisor_Frecuencia : in STD_LOGIC;
Entrada : in STD_LOGIC;
Mensaje : out STD_LOGIC_VECTOR (7 downto 0);
Confirmado : out STD_LOGIC
);
end component;
component Transmission_8bits
Port(
Divisor_Frecuencia : in STD_LOGIC;
Entrada : in STD_LOGIC_VECTOR (7 downto 0);
Activo : in STD_LOGIC;
Salida : out STD_LOGIC
);
end component;
signal Divisor_FrecuenciaAUX : std_logic := '1';
begin
Divisor_Frecuencia1 : Divisor_Frecuencia
Port map(
clk => clk,
Salida => Divisor_FrecuenciaAUX
);
Reception_8bits1 : Reception_8bits
Port map(
Divisor_Frecuencia => Divisor_FrecuenciaAUX,
Entrada => Entrada_1bit,
Mensaje => Mensaje_8bits,
Confirmado => Activador_Entrega_Mensaje
);
Transmission_8bits1 : Transmission_8bits
Port map(
Divisor_Frecuencia => Divisor_FrecuenciaAUX,
Entrada => Entrada_8bits,
Activo => Activador_Envio_Mensaje,
Salida => Salida_1bit
);
end arq_RS232;
|
entity tb_subprg02 is
end tb_subprg02;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_subprg02 is
signal a, na : std_logic_vector (3 downto 0);
signal n : natural range 0 to 1;
signal clk : std_logic;
begin
dut: entity work.subprg02
port map (a, n, clk, na);
process
procedure pulse is
begin
wait for 1 ns;
clk <= '1';
wait for 1 ns;
clk <= '0';
end pulse;
begin
n <= 0;
clk <= '0';
a <= x"0";
pulse;
assert na = x"f" severity failure;
a <= x"5";
pulse;
assert na = x"a" severity failure;
wait;
end process;
end behav;
|
entity choice1 is
end entity;
architecture test of choice1 is
signal s : integer;
begin
p1: process is
variable x : integer;
begin
case s is
when 1 | 2 =>
x := 3;
when 3 | 4 | 5 =>
x := 4;
when integer'low to 0 =>
x := -1;
when others =>
x := 5;
end case;
wait;
end process;
end architecture;
|
-------------------------------------------------------------------------------
-- Bitmap VGA display with 640x480 pixel resolution
-------------------------------------------------------------------------------
-- V 1.1.2 (2015/11/29)
-- Bertrand Le Gal ([email protected])
-- Some little modifications to support data reading
-- from file for RAM initilization.
--
-- V 1.1.1 (2015/07/28)
-- Yannick Bornat ([email protected])
--
-- For more information on this module, refer to module page :
-- http://bornat.vvv.enseirb.fr/wiki/doku.php?id=en202:vga_bitmap
--
-- V1.1.1 :
-- - Comment additions
-- - Code cleanup
-- V1.1.0 :
-- - added capacity above 3bpp
-- - ability to display grayscale pictures
-- - Module works @ 100MHz clock frequency
-- V1.0.1 :
-- - Fixed : image not centered on screen
-- V1.0.0 :
-- - Initial release
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
use std.textio.ALL;
entity VGA_bitmap_640x480 is
port(clk : in std_logic;
clk_vga : in std_logic;
reset : in std_logic;
VGA_hs : out std_logic; -- horisontal vga syncr.
VGA_vs : out std_logic; -- vertical vga syncr.
iter : out std_logic_vector(11 downto 0); -- iter output
ADDR1 : in std_logic_vector(16 downto 0);
data_in1 : in std_logic_vector(11 downto 0);
data_write1 : in std_logic;
ADDR2 : in std_logic_vector(16 downto 0);
data_in2 : in std_logic_vector(11 downto 0);
data_write2 : in std_logic;
ADDR3 : in std_logic_vector(16 downto 0);
data_in3 : in std_logic_vector(11 downto 0);
data_write3 : in std_logic;
ADDR4 : in std_logic_vector(16 downto 0);
data_in4 : in std_logic_vector(11 downto 0);
data_write4 : in std_logic);
end VGA_bitmap_640x480;
architecture Behavioral of VGA_bitmap_640x480 is
component RAM_single_port
Port ( clk : in STD_LOGIC;
data_write : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR(11 downto 0);
ADDR : in STD_LOGIC_VECTOR (16 downto 0);
data_out : out STD_LOGIC_VECTOR (11 downto 0));
end component;
signal h_counter : integer range 0 to 3199:=0; -- counter for H sync. (size depends of frequ because of division)
signal v_counter : integer range 0 to 520 :=0; -- counter for V sync. (base on v_counter, so no frequ issue)
signal TOP_line : boolean := false; -- this signal is true when the current pixel column is visible on the screen
signal TOP_display : boolean := false; -- this signal is true when the current pixel line is visible on the screen
signal pix_read_addr : integer range 0 to 307199:=0; -- the address at which displayed data is read
signal pix_read_addr1, pix_read1 : integer range 0 to 76799:=0; -- the address at which displayed data is read
--signal next_pixel,next_pixel1,next_pixel2 : std_logic_vector(3 downto 0); -- the data coding the value of the pixel to be displayed
signal pix_read_addrb : integer range 0 to 76799 := 0; -- the address at which displayed data is read
signal next_pixel1, data_temp1, data_temp2 , data_outtemp1, data_outtemp2,data_temp3, data_temp4 , data_outtemp3, data_outtemp4 : std_logic_vector(11 downto 0); -- the data coding the value of the pixel to be displayed
signal next_pixel2 : std_logic_vector(11 downto 0); -- the data coding the value of the pixel to be displayed
signal next_pixel : std_logic_vector(11 downto 0); -- the data coding the value of the pixel to be displayed
--signal data_writetemp1, data_writetemp2 : std_logic;
signal ADDRtemp1, ADDRtemp2, ADDRtemp3, ADDRtemp4 : std_logic_vector(16 downto 0); -- the data coding the value of the pixel to be displayed
begin
--------------------------------------------------------------------------------
RAM1: RAM_single_port
port map (clk,
data_write1,
data_in1,
ADDRtemp1,
data_outtemp1);
RAM2: RAM_single_port
port map (clk,
data_write2,
data_in2,
ADDRtemp2,
data_outtemp2);
RAM3: RAM_single_port
port map (clk,
data_write3,
data_in3,
ADDRtemp3,
data_outtemp3);
RAM4: RAM_single_port
port map (clk,
data_write4,
data_in4,
ADDRtemp4,
data_outtemp4);
-- pix_read_addrb <= pix_read_addr when pix_read_addr < 153599 else pix_read_addr - 153599;
ADDRtemp1<= ADDR1 when (data_write1 = '1') else std_logic_vector(to_unsigned(pix_read1, 17)) ;
ADDRtemp2<= ADDR2 when (data_write2 = '1') else std_logic_vector(to_unsigned(pix_read1, 17)) ;
ADDRtemp3<= ADDR3 when (data_write3 = '1') else std_logic_vector(to_unsigned(pix_read1, 17)) ;
ADDRtemp4<= ADDR4 when (data_write4 = '1') else std_logic_vector(to_unsigned(pix_read1, 17)) ;
--data_writetemp1 <= clk_VGA when (data_write1 = '0') else '1' ;
--data_writetemp2 <= clk_VGA when (data_write2 = '0') else '1' ;
-- process (clk)
-- begin
-- if (clk'event and clk = '1') then
-- if (data_write1 = '1') then
-- screen1(to_integer(unsigned(ADDR1))) <= data_in1 ;
-- end if;
-- end if;
-- end process;
--
-- process (clk_vga)
-- begin
-- if (clk_vga'event and clk_vga = '1') then
-- next_pixel1 <= screen1(pix_read_addrb) ;
-- end if;
-- end process;
--
-- process (clk)
-- begin
-- if (clk'event and clk = '1') then
-- if (data_write2 = '1') then
-- screen2(to_integer(unsigned(ADDR2))) <= data_in2 ;
-- end if;
-- end if;
-- end process;
--
-- process (clk_vga)
-- begin
-- if (clk_vga'event and clk_vga = '1') then
-- next_pixel2 <= screen2(pix_read_addrb);
-- end if;
-- end process;
process (clk_vga)
begin
if (clk_vga'event and clk_vga = '1') then
IF pix_read_addr < 76799 THEN
next_pixel <= data_outtemp1;
ELSif pix_read_addr < 153599 THEN
next_pixel <= data_outtemp2;
ELSif pix_read_addr < 230399 THEN
next_pixel <= data_outtemp3;
else
next_pixel <= data_outtemp4;
END IF;
end if;
end process;
--process (clk_vga)
--begin
-- if (clk_vga'event and clk_vga = '1') then
-- if (data_write1 = '1') then
-- screen1(to_integer(unsigned(ADDR1))) <= data_in1;
-- next_pixel1 <= data_in1;
-- else
-- next_pixel1 <= screen1(to_integer(unsigned(ADDR1)));
-- end if;
-- end if;
--end process;
--
--process (clk_vga)
--begin
-- if (clk_vga'event and clk_vga = '1') then
-- if (data_write2 = '1') then
-- screen2(to_integer(unsigned(ADDR2))) <= data_in2;
-- next_pixel2 <= data_in2;
-- else
-- next_pixel2 <= screen2(to_integer(unsigned(ADDR2));
-- end if;
-- end if;
--end process;
--process (next_pixel)
--begin
-- if (clk_vga'event and clk_vga = '1') then
-- next_pixel <= To_StdLogicVector( ram_out(pix_read_addr) );
-- end if;
--end process;
--ram_out <= screen1 when to_unsigned(pix_read_addr,18)(17) = '0' else screen2;
--------------------------------------------------------------------------------
--proc<='0' when (pix_read_addr <153599) else '1';
pixel_read_addr : process(clk_vga, clk)
begin
if clk_vga'event and clk_vga='1' then
if reset = '1' or (not TOP_display) then
pix_read_addr <= 0;
elsif TOP_line and (h_counter mod 4)=0 then
pix_read_addr <= pix_read_addr + 1;
elsif (pix_read_addr = 307199) then
pix_read_addr <= 0;
end if;
end if;
end process;
pixel_read1 : process(clk_vga, clk)
begin
if clk_vga'event and clk_vga='1' then
if reset = '1' or (not TOP_display) then
pix_read1 <= 0;
elsif TOP_line and (h_counter mod 4)=0 then
pix_read1 <= pix_read1 + 1;
elsif (pix_read1 = 76799) then
pix_read1 <= 0;
end if;
end if;
end process;
--pixel_read_addrb : process(clk_vga, clk)
--begin
-- if clk_vga'event and clk_vga='1' then
-- if reset = '1' or (not TOP_display) then
-- pix_read_addrb <= 0;
-- elsif TOP_line and (h_counter mod 4)=0 then
-- pix_read_addrb <= pix_read_addrb + 1;
-- elsif (pix_read_addrb = 153599) then
-- pix_read_addrb <= 0;
-- end if;
-- end if;
--end process;
--process(pix_read_addr)
--begin
-- if pix_read_addr < 153599 then
-- ram_number <= '0';
-- elsif pix_read_addr <307199 then
-- ram_number <= '1';
-- else
-- ram_number <= '0';
-- end if;
--end process;
-- this process manages the horizontal synchro using the counters
process(clk_vga)
begin
if clk_vga'event and clk_vga='1' then
if reset = '1' then
VGA_vs <= '0';
TOP_display <= false;
else
case v_counter is
when 0 => VGA_vs <= '0'; -- start of Tpw ( 0 -> 0 + 1)
when 2 => VGA_vs <= '1'; -- start of Tbp ( 2 -> 2 + 28 = 30)
when 31 => TOP_display <= true; -- start of Tdisp ( 31 -> 31 + 479 = 510)
when 511 => TOP_display <= false; -- start of Tfp (511 -> 511 + 9 = 520)
when others => null;
end case;
-- if v_counter = 0 then VGA_vs <= '0'; -- start of Tpw ( 0 -> 0 + 1)
-- elsif v_counter = 2 then VGA_vs <= '1'; -- start of Tbp ( 2 -> 2 + 28 = 30)
-- elsif v_counter = 75 then TOP_display <= true; -- start of Tdisp ( 31 -> 31 + 479 = 510)
-- elsif v_counter = 475 then TOP_display <= false; -- start of Tfp (511 -> 511 + 9 = 520)
-- end if;
end if;
end if;
end process;
process(clk_vga)
begin
if clk_vga'event and clk_vga='1' then
if (not TOP_line) or (not TOP_display) then
iter <= (others=>'0');
else
iter<= next_pixel;
end if;
end if;
end process;
-- this process manages the horizontal synchro using the counters
process(clk_vga)
begin
if clk_vga'event and clk_vga='1' then
if reset = '1' then
VGA_hs <= '0';
TOP_line <= false;
else
case h_counter is
when 2 => VGA_hs <= '0'; -- start of Tpw ( 0 -> 0 + 95) -- +2 because of delay in RAM
when 386 => VGA_hs <= '1'; -- start of Tbp ( 96 -> 96 + 47 = 143) -- 384=96*4 -- -- +2 because of delay in RAM
when 576 => TOP_line <= true; -- start of Tdisp ( 144 -> 144 + 639 = 783) -- 576=144*4
when 3136 => TOP_line <= false; -- start of Tfp ( 784 -> 784 + 15 = 799) -- 3136 = 784*4
when others => null;
end case;
-- if h_counter=2 then VGA_hs <= '0'; -- start of Tpw ( 0 -> 0 + 95) -- +2 because of delay in RAM
-- elsif h_counter=386 then VGA_hs <= '1'; -- start of Tbp ( 96 -> 96 + 47 = 143) -- 384=96*4 -- -- +2 because of delay in RAM
-- elsif h_counter=576 then TOP_line <= true; -- start of Tdisp ( 144 -> 144 + 639 = 783) -- 576=144*4
-- elsif h_counter=3136 then TOP_line <= false; -- start of Tfp ( 784 -> 784 + 15 = 799) -- 3136 = 784*4
-- end if;
end if;
end if;
end process;
-- counter management for synchro
process(clk_vga)
begin
if clk_vga'event and clk_vga='1' then
if reset='1' then
h_counter <= 0;
v_counter <= 0;
else
if h_counter = 3199 then
h_counter <= 0;
if v_counter = 520 then
v_counter <= 0;
else
v_counter <= v_counter + 1;
end if;
else
h_counter <= h_counter +1;
end if;
end if;
end if;
end process;
end Behavioral; |
--
-------------------------------------------------------------------------------------------
-- Copyright © 2011-2014, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
--
-- KCPSM6 reference design using 'uart_tx6' and 'uart_rx6'macros.
--
-- Ken Chapman - Xilinx Ltd.
--
-- 20th June 2014 - Initial version for KC705 board using Vivado 2014.1
--
-- This reference design provides a simple UART communication example. Please see
-- 'UART6_User_Guide_and_Reference_Designs_30Sept14.pdf' (or later) for more detailed
-- descriptions.
--
-- The KC705 board provides a 200MHz clock to the Kintex-7 device which is used by all
-- circuits in this design including KCPSM6 and the UART macros. In this example, KCPSM6
-- computes a constant which is applied to a clock division circuit to define a UART
-- communication BAUD rate of 115200.
--
-- Whilst the design is presented as a working example for the XC7K325TFFG900-2 device on
-- the KC705 Evaluation Board (www.xilinx.com), it is a simple reference design that is
-- easily adapted or incorporated into a design for use with any hardware platform. Indeed,
-- the method presented to define the BAUD rate can make this code even easier to port as
-- it only requires one constant to be defined and KCPSM6 works out everything else.
--
--
-------------------------------------------------------------------------------------------
--
-- Library declarations
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library unisim;
use unisim.vcomponents.all;
--
-------------------------------------------------------------------------------------------
--
--
entity uart6_kc705 is
Port ( uart_rx : in std_logic;
uart_tx : out std_logic;
clk200_p : in std_logic;
clk200_n : in std_logic);
end uart6_kc705;
--
-------------------------------------------------------------------------------------------
--
-- Start of test architecture
--
architecture Behavioral of uart6_kc705 is
--
-------------------------------------------------------------------------------------------
--
-- Components
--
-------------------------------------------------------------------------------------------
--
--
-- declaration of KCPSM6
--
component kcpsm6
generic( hwbuild : std_logic_vector(7 downto 0) := X"00";
interrupt_vector : std_logic_vector(11 downto 0) := X"3FF";
scratch_pad_memory_size : integer := 64);
port ( address : out std_logic_vector(11 downto 0);
instruction : in std_logic_vector(17 downto 0);
bram_enable : out std_logic;
in_port : in std_logic_vector(7 downto 0);
out_port : out std_logic_vector(7 downto 0);
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
k_write_strobe : out std_logic;
read_strobe : out std_logic;
interrupt : in std_logic;
interrupt_ack : out std_logic;
sleep : in std_logic;
reset : in std_logic;
clk : in std_logic);
end component;
--
-- Development Program Memory
--
component auto_baud_rate_control
generic( C_FAMILY : string := "S6";
C_RAM_SIZE_KWORDS : integer := 1;
C_JTAG_LOADER_ENABLE : integer := 0);
Port ( address : in std_logic_vector(11 downto 0);
instruction : out std_logic_vector(17 downto 0);
enable : in std_logic;
rdl : out std_logic;
clk : in std_logic);
end component;
--
-- UART Transmitter with integral 16 byte FIFO buffer
--
component uart_tx6
Port ( data_in : in std_logic_vector(7 downto 0);
en_16_x_baud : in std_logic;
serial_out : out std_logic;
buffer_write : in std_logic;
buffer_data_present : out std_logic;
buffer_half_full : out std_logic;
buffer_full : out std_logic;
buffer_reset : in std_logic;
clk : in std_logic);
end component;
--
-- UART Receiver with integral 16 byte FIFO buffer
--
component uart_rx6
Port ( serial_in : in std_logic;
en_16_x_baud : in std_logic;
data_out : out std_logic_vector(7 downto 0);
buffer_read : in std_logic;
buffer_data_present : out std_logic;
buffer_half_full : out std_logic;
buffer_full : out std_logic;
buffer_reset : in std_logic;
clk : in std_logic);
end component;
--
--
-------------------------------------------------------------------------------------------
--
-- Signals
--
-------------------------------------------------------------------------------------------
--
--
-- Signals used to create internal 200MHz clock from 200MHz differential clock
--
signal clk200 : std_logic;
signal clk : std_logic;
--
-- Constant to specify the clock frequency in megahertz.
--
constant clock_frequency_in_MHz : integer range 0 to 255 := 200;
--
--
-- Signals used to connect KCPSM6
--
signal address : std_logic_vector(11 downto 0);
signal instruction : std_logic_vector(17 downto 0);
signal bram_enable : std_logic;
signal in_port : std_logic_vector(7 downto 0);
signal out_port : std_logic_vector(7 downto 0);
signal port_id : std_logic_vector(7 downto 0);
signal write_strobe : std_logic;
signal k_write_strobe : std_logic;
signal read_strobe : std_logic;
signal interrupt : std_logic;
signal interrupt_ack : std_logic;
signal kcpsm6_sleep : std_logic;
signal kcpsm6_reset : std_logic;
signal rdl : std_logic;
--
-- Signals used to connect UART_TX6
--
signal uart_tx_data_in : std_logic_vector(7 downto 0);
signal write_to_uart_tx : std_logic;
signal pipe_port_id0 : std_logic := '0';
signal uart_tx_data_present : std_logic;
signal uart_tx_half_full : std_logic;
signal uart_tx_full : std_logic;
signal uart_tx_reset : std_logic;
--
-- Signals used to connect UART_RX6
--
signal uart_rx_data_out : std_logic_vector(7 downto 0);
signal read_from_uart_rx : std_logic := '0';
signal uart_rx_data_present : std_logic;
signal uart_rx_half_full : std_logic;
signal uart_rx_full : std_logic;
signal uart_rx_reset : std_logic;
--
-- Signals used to define baud rate
--
signal set_baud_rate : std_logic_vector(7 downto 0) := "00000000";
signal baud_rate_counter : std_logic_vector(7 downto 0) := "00000000";
signal en_16_x_baud : std_logic := '0';
--
--
-------------------------------------------------------------------------------------------
--
-- Start of circuit description
--
-------------------------------------------------------------------------------------------
--
begin
--
-----------------------------------------------------------------------------------------
-- Create and distribute an internal 200MHz clock from 200MHz differential clock
-----------------------------------------------------------------------------------------
--
diff_clk_buffer: IBUFGDS
port map ( I => clk200_p,
IB => clk200_n,
O => clk200);
--
-- BUFG used to reach the entire device with 200MHz
--
buffer200: BUFG
port map ( I => clk200,
O => clk);
--
-----------------------------------------------------------------------------------------
-- Instantiate KCPSM6 and connect to program ROM
-----------------------------------------------------------------------------------------
--
-- The generics can be defined as required. In this case the 'hwbuild' value is used to
-- define a version using the ASCII code for the desired letter.
--
processor: kcpsm6
generic map ( hwbuild => X"41", -- 41 hex is ASCII Character "A"
interrupt_vector => X"7FF",
scratch_pad_memory_size => 64)
port map( address => address,
instruction => instruction,
bram_enable => bram_enable,
port_id => port_id,
write_strobe => write_strobe,
k_write_strobe => k_write_strobe,
out_port => out_port,
read_strobe => read_strobe,
in_port => in_port,
interrupt => interrupt,
interrupt_ack => interrupt_ack,
sleep => kcpsm6_sleep,
reset => kcpsm6_reset,
clk => clk);
--
-- Reset connected to JTAG Loader enabled Program Memory
--
kcpsm6_reset <= rdl;
--
-- Unused signals tied off until required.
-- Tying to other signals used to minimise warning messages.
--
kcpsm6_sleep <= write_strobe and k_write_strobe; -- Always '0'
interrupt <= interrupt_ack;
--
-- Development Program Memory
-- JTAG Loader enabled for rapid code development.
--
program_rom: auto_baud_rate_control
generic map( C_FAMILY => "7S",
C_RAM_SIZE_KWORDS => 2,
C_JTAG_LOADER_ENABLE => 1)
port map( address => address,
instruction => instruction,
enable => bram_enable,
rdl => rdl,
clk => clk);
--
-----------------------------------------------------------------------------------------
-- UART Transmitter with integral 16 byte FIFO buffer
-----------------------------------------------------------------------------------------
--
-- Write to buffer in UART Transmitter at port address 01 hex
--
tx: uart_tx6
port map ( data_in => uart_tx_data_in,
en_16_x_baud => en_16_x_baud,
serial_out => uart_tx,
buffer_write => write_to_uart_tx,
buffer_data_present => uart_tx_data_present,
buffer_half_full => uart_tx_half_full,
buffer_full => uart_tx_full,
buffer_reset => uart_tx_reset,
clk => clk);
--
-----------------------------------------------------------------------------------------
-- UART Receiver with integral 16 byte FIFO buffer
-----------------------------------------------------------------------------------------
--
-- Read from buffer in UART Receiver at port address 01 hex.
--
-- When KCPMS6 reads data from the receiver a pulse must be generated so that the
-- FIFO buffer presents the next character to be read and updates the buffer flags.
--
rx: uart_rx6
port map ( serial_in => uart_rx,
en_16_x_baud => en_16_x_baud,
data_out => uart_rx_data_out,
buffer_read => read_from_uart_rx,
buffer_data_present => uart_rx_data_present,
buffer_half_full => uart_rx_half_full,
buffer_full => uart_rx_full,
buffer_reset => uart_rx_reset,
clk => clk);
--
-----------------------------------------------------------------------------------------
-- UART baud rate
-----------------------------------------------------------------------------------------
--
-- The baud rate is defined by the frequency of 'en_16_x_baud' pulses. These should occur
-- at 16 times the desired baud rate. KCPSM6 computes and sets an 8-bit value into
-- 'set_baud_rate' which is used to divide the clock frequency appropriately.
--
-- For example, if the clock frequency is 200MHz and the desired serial communication
-- baud rate is 115200 then PicoBlaze will set 'set_baud_rate' to 6C hex (108 decimal).
-- This circuit will then generate an 'en_16_x_baud' pulse once every 109 clock cycles
-- (note that 'baud_rate_counter' will include state zero). This would actually result
-- in a baud rate of 114,679 baud but that is only 0.45% low and well within limits.
--
baud_rate: process(clk)
begin
if clk'event and clk = '1' then
if baud_rate_counter = set_baud_rate then
baud_rate_counter <= "00000000";
en_16_x_baud <= '1'; -- single cycle enable pulse
else
baud_rate_counter <= baud_rate_counter + 1;
en_16_x_baud <= '0';
end if;
end if;
end process baud_rate;
--
-----------------------------------------------------------------------------------------
-- General Purpose Input Ports.
-----------------------------------------------------------------------------------------
--
-- Three input ports are used with the UART macros.
--
-- The first is used to monitor the flags on both the transmitter and receiver.
-- The second is used to read the data from the receiver and generate a 'buffer_read'
-- pulse.
-- The third is used to read a user defined constant that enabled KCPSM6 to know the
-- clock frequency so that it can compute values which will define the BAUD rate
-- for UART communications (as well as values used to define software delays).
--
input_ports: process(clk)
begin
if clk'event and clk = '1' then
case port_id(1 downto 0) is
-- Read UART status at port address 00 hex
when "00" => in_port(0) <= uart_tx_data_present;
in_port(1) <= uart_tx_half_full;
in_port(2) <= uart_tx_full;
in_port(3) <= uart_rx_data_present;
in_port(4) <= uart_rx_half_full;
in_port(5) <= uart_rx_full;
-- Read UART_RX6 data at port address 01 hex
-- (see 'buffer_read' pulse generation below)
when "01" => in_port <= uart_rx_data_out;
-- Read clock frequency contant at port address 02 hex
when "10" => in_port <= conv_std_logic_vector(clock_frequency_in_MHz, 8);
-- Specify don't care for all other inputs to obtain optimum implementation
when others => in_port <= "XXXXXXXX";
end case;
-- Generate 'buffer_read' pulse following read from port address 01
if (read_strobe = '1') and (port_id(1 downto 0) = "01") then
read_from_uart_rx <= '1';
else
read_from_uart_rx <= '0';
end if;
end if;
end process input_ports;
--
-----------------------------------------------------------------------------------------
-- General Purpose Output Ports
-----------------------------------------------------------------------------------------
--
-- In this design there are two general purpose output ports.
--
-- A port used to write data directly to the FIFO buffer within 'uart_tx6' macro.
--
-- A port used to define the communication BAUD rate of the UART.
--
-- Note that the assignment and decoding of 'port_id' is a one-hot resulting
-- in the minimum number of signals actually being decoded for a fast and
-- optimum implementation.
--
output_ports: process(clk)
begin
if clk'event and clk = '1' then
-- 'write_strobe' is used to qualify all writes to general output ports.
if write_strobe = '1' then
-- Write to UART at port addresses 01 hex
-- See below this clocked process for the combinatorial decode required.
-- Write to 'set_baud_rate' at port addresses 02 hex
-- This value is set by KCPSM6 to define the BAUD rate of the UART.
-- See the 'UART baud rate' section for details.
if (port_id(1) = '1') then
set_baud_rate <= out_port;
end if;
end if;
--
-- *** To reliably achieve 200MHz performance when writing to the FIFO buffer
-- within the UART transmitter, 'port_id' is pipelined to exploit both of
-- the clock cycles that it is valid.
--
pipe_port_id0 <= port_id(0);
end if;
end process output_ports;
--
-- Write directly to the FIFO buffer within 'uart_tx6' macro at port address 01 hex.
-- Note the direct connection of 'out_port' to the UART transmitter macro and the
-- way that a single clock cycle write pulse is generated to capture the data.
--
uart_tx_data_in <= out_port;
-- See *** above for definition of 'pipe_port_id0'.
write_to_uart_tx <= '1' when (write_strobe = '1') and (pipe_port_id0 = '1')
else '0';
--
-----------------------------------------------------------------------------------------
-- Constant-Optimised Output Ports
-----------------------------------------------------------------------------------------
--
-- One constant-optimised output port is used to facilitate resetting of the UART macros.
--
constant_output_ports: process(clk)
begin
if clk'event and clk = '1' then
if k_write_strobe = '1' then
if port_id(0) = '1' then
uart_tx_reset <= out_port(0);
uart_rx_reset <= out_port(1);
end if;
end if;
end if;
end process constant_output_ports;
--
-----------------------------------------------------------------------------------------
--
end Behavioral;
-------------------------------------------------------------------------------------------
--
-- END OF FILE uart6_kc705.vhd
--
-------------------------------------------------------------------------------------------
|
-- ctl_bypass.vhd
-- Jan Viktorin <[email protected]>
-- Copyright (C) 2011, 2012 Jan Viktorin
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
---
-- Shift register delay. It is usually used to delay
-- control signals when processing data path in
-- a separate pipeline.
---
entity ctl_bypass is
generic (
DWIDTH : integer := 3;
DEPTH : integer := 9
);
port (
CLK : in std_logic;
CE : in std_logic;
DI : in std_logic_vector(DWIDTH - 1 downto 0);
DO : out std_logic_vector(DWIDTH - 1 downto 0)
);
end entity;
architecture full of ctl_bypass is
type shreg_t is array(0 to DEPTH - 1) of std_logic_vector(DWIDTH - 1 downto 0);
signal shreg : shreg_t;
begin
shregp : process(CLK, CE, DI)
begin
if rising_edge(CLK) then
if CE = '1' then
shreg(0) <= DI;
for i in 1 to DEPTH - 1 loop
shreg(i) <= shreg(i - 1);
end loop;
end if;
end if;
end process;
DO <= shreg(shreg'length - 1);
end architecture;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:47:07 10/06/2010
-- Design Name:
-- Module Name: RefreshDisplay - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity RefreshDisplay is
port (
Rst : in STD_LOGIC;
Clk : in STD_LOGIC;
ClkOut : out STD_LOGIC);
end RefreshDisplay;
architecture Behavioral of RefreshDisplay is
--Declaraciones de constantes
constant Fosc : integer := 100000000; --Frecuencia del oscilador de tabletas NEXYS 3
constant Fdiv : integer := 800; --Frecuencia deseada del divisor
constant CtaMax : integer := Fosc / Fdiv; --Cuenta maxima a la que hay que llegar
--Declaracion de signals
signal Cont : integer range 0 to CtaMax;
begin
--Proceso que Divide la Frecuencia de entrada para obtener una Frecuencia de Refresh
process (Rst, Clk)
begin
if Rst = '1' then
Cont <= 0;
elsif (rising_edge(Clk)) then
if Cont = CtaMax then
Cont <= 0;
ClkOut <= '1';
else
Cont <= Cont + 1;
ClkOut<= '0';
end if;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:47:07 10/06/2010
-- Design Name:
-- Module Name: RefreshDisplay - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity RefreshDisplay is
port (
Rst : in STD_LOGIC;
Clk : in STD_LOGIC;
ClkOut : out STD_LOGIC);
end RefreshDisplay;
architecture Behavioral of RefreshDisplay is
--Declaraciones de constantes
constant Fosc : integer := 100000000; --Frecuencia del oscilador de tabletas NEXYS 3
constant Fdiv : integer := 800; --Frecuencia deseada del divisor
constant CtaMax : integer := Fosc / Fdiv; --Cuenta maxima a la que hay que llegar
--Declaracion de signals
signal Cont : integer range 0 to CtaMax;
begin
--Proceso que Divide la Frecuencia de entrada para obtener una Frecuencia de Refresh
process (Rst, Clk)
begin
if Rst = '1' then
Cont <= 0;
elsif (rising_edge(Clk)) then
if Cont = CtaMax then
Cont <= 0;
ClkOut <= '1';
else
Cont <= Cont + 1;
ClkOut<= '0';
end if;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:47:07 10/06/2010
-- Design Name:
-- Module Name: RefreshDisplay - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity RefreshDisplay is
port (
Rst : in STD_LOGIC;
Clk : in STD_LOGIC;
ClkOut : out STD_LOGIC);
end RefreshDisplay;
architecture Behavioral of RefreshDisplay is
--Declaraciones de constantes
constant Fosc : integer := 100000000; --Frecuencia del oscilador de tabletas NEXYS 3
constant Fdiv : integer := 800; --Frecuencia deseada del divisor
constant CtaMax : integer := Fosc / Fdiv; --Cuenta maxima a la que hay que llegar
--Declaracion de signals
signal Cont : integer range 0 to CtaMax;
begin
--Proceso que Divide la Frecuencia de entrada para obtener una Frecuencia de Refresh
process (Rst, Clk)
begin
if Rst = '1' then
Cont <= 0;
elsif (rising_edge(Clk)) then
if Cont = CtaMax then
Cont <= 0;
ClkOut <= '1';
else
Cont <= Cont + 1;
ClkOut<= '0';
end if;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:47:07 10/06/2010
-- Design Name:
-- Module Name: RefreshDisplay - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity RefreshDisplay is
port (
Rst : in STD_LOGIC;
Clk : in STD_LOGIC;
ClkOut : out STD_LOGIC);
end RefreshDisplay;
architecture Behavioral of RefreshDisplay is
--Declaraciones de constantes
constant Fosc : integer := 100000000; --Frecuencia del oscilador de tabletas NEXYS 3
constant Fdiv : integer := 800; --Frecuencia deseada del divisor
constant CtaMax : integer := Fosc / Fdiv; --Cuenta maxima a la que hay que llegar
--Declaracion de signals
signal Cont : integer range 0 to CtaMax;
begin
--Proceso que Divide la Frecuencia de entrada para obtener una Frecuencia de Refresh
process (Rst, Clk)
begin
if Rst = '1' then
Cont <= 0;
elsif (rising_edge(Clk)) then
if Cont = CtaMax then
Cont <= 0;
ClkOut <= '1';
else
Cont <= Cont + 1;
ClkOut<= '0';
end if;
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
-- Company : HSLU
-- Engineer : Gai, Waj
--
-- Create Date: 19-May-11
-- Project : RT Video Lab 1: Exercise 2
-- Description: Testbench for 5-tap FIR filter with loadable coefficients
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std; use std.textio.all;
entity fir_1d_load_tb IS
end fir_1d_load_tb;
architecture behavior of fir_1d_load_tb is
-- Component Declaration for the Unit Under Test (UUT)
component fir_1d_trn_load is
generic
(IN_DW, OUT_DW, COEF_DW, TAPS, DELAY : integer);
port
(ce_1 : in std_logic; -- clock enable
clk_1 : in std_logic; -- clock
load : in std_logic; -- load coeff pulse
coef : in std_logic_vector; -- coefficients
din : in std_logic_vector; -- data input
out_data : out std_logic_vector -- filtered output data
);
end component;
-- clock frequency definition
constant clk_freq : real := 100.0; -- 100 MHz
constant t_clk : time := 1000.0/clk_freq * 1 ns; -- one clock period
-- define delays for timing-simulation
constant t_stim : time := 0.25*t_clk; -- delay time for stimuli application
constant t_prop : time := 0.25*t_clk; -- propagation delay for UUT mimic
-- design parameters
constant IN_DW : integer := 8;
constant OUT_DW : integer := 19;
constant COEF_DW: integer := 7;
constant TAPS : integer := 5;
constant DELAY : integer := 8; -- adapt to adjust filter latency!!!
-- inputs signals
signal clk : std_logic := '0';
signal load : std_logic := '0';
signal coef : std_logic_vector(COEF_DW-1 downto 0) := (others => '0');
signal din : std_logic_vector(IN_DW-1 downto 0) := (others => '0');
-- outputs signals
signal out_data : std_logic_vector(OUT_DW-1 downto 0) := (others => '0');
-- local testbench control signals
signal load_done : boolean := false;
signal err_cnt : natural := 0;
-- I/O files
-- Expeceted responses are generated for the middle row of the corresponding
-- filter mask, which correspnds to the following coefficients:
-- Filter : b0 b1 b2 b3 b4
------------------------------------------
-- 1_Identity : 0 0 1 0 0
-- 2_Edge : 0 -1 8 -1 0
-- 3_SobelX : 0 2 0 -2 0
-- 4_SobelY : 0 0 0 0 0
-- 5_SobelXY : 0 -1 0 1 0
-- 6_Blur : 1 0 0 0 1
-- 7_Smooth : 1 5 44 5 1
-- 8_Sharpen : 0 -2 32 -2 0
-- 9_Gaussian : 2 4 8 4 2
------------------------------------------
constant mask_type : string := "7_Smooth";
file f_stimuli_d : text is in "..\1x5_Filter\" & mask_type & "\FIR_IN.txt";
file f_stimuli_c : text is in "..\1x5_Filter\" & mask_type & "\COEF_SEQ.txt";
file f_exp_resp : text is in "..\1x5_Filter\" & mask_type & "\FIR_OUT.txt";
file f_act_resp : text is out "..\1x5_Filter\" & mask_type & "\FIR_VHDL_OUT.txt";
begin
-- Instantiate the Unit Under Test
uut : fir_1d_trn_load
generic map (
IN_DW => IN_DW,
OUT_DW => OUT_DW,
COEF_DW => COEF_DW,
TAPS => TAPS,
DELAY => DELAY
)
port map (
ce_1 => '1',
clk_1 => clk,
load => load,
coef => coef,
din => din,
out_data => out_data
);
-- Clock generation
p_clk :process
begin
wait for t_clk/2;
clk <= not clk;
end process;
-- apply coeff_load stimuli to UUT
p_stim_c:process(clk)
variable inline : line;
variable char : character;
variable cnt_load : natural := 0;
begin
if clk'event and clk = '1' then
cnt_load := cnt_load + 1;
-- generate load-pulse 5 cycles long
if cnt_load = 100 then
load <= '1' after t_stim;
elsif cnt_load = 105 then
load <= '0' after t_stim;
end if;
-- apply coefficients 1 cycle too early and one cycle too long in order
-- to check correct load sequence (see COEF_SEQ.txt)
if cnt_load >= 100 then
if not endfile(f_stimuli_c) then
readline(f_stimuli_c,inline);
for k in COEF_DW-1 downto 0 loop
read(inline,char);
if char = '0' then
coef(k) <= '0' after t_stim;
else
coef(k) <= '1' after t_stim;
end if;
end loop;
else
-- start data_in application
load_done <= true;
end if;
end if;
end if;
end process;
-- apply data_in stimuli to UUT
p_stim_d:process(clk)
variable inline : line;
variable char : character;
begin
if clk'event and clk = '1' then
if load_done and (not endfile(f_stimuli_d)) then
readline(f_stimuli_d,inline);
for k in IN_DW-1 downto 0 loop
read(inline,char);
if char = '0' then
din(k) <= '0' after t_stim;
else
din(k) <= '1' after t_stim;
end if;
end loop;
elsif endfile(f_stimuli_d) then
-- end of simulation
assert false report "******** End of simulation : " &
"Total Number of Mismatches detected = " &
integer'image(err_cnt) &
" ********"
severity failure;
end if;
end if;
end process;
-- compare expected with actual responses and write output file
p_check: process(clk)
variable line_exp, line_act : line;
variable str_exp, str_act : string(OUT_DW downto 1);
begin
if clk'event and clk = '1' then
if load_done then
-- read expected value from file
readline(f_exp_resp, line_exp);
for k in OUT_DW-1 downto 0 loop
-- get all bits in actual output
if out_data(k) = '0' then
str_act(k+1) := '0';
elsif out_data(k) = '1' then
str_act(k+1) := '1';
end if;
write(line_act, str_act(k+1));
-- get all bits in expected output
read(line_exp, str_exp(k+1));
end loop;
-- write actual value to file
writeline(f_act_resp, line_act);
-- compare actual and expected output vector
if not (str_exp = str_act) then
assert false
report "expected: " & str_exp & " actual: " & str_act severity note;
err_cnt <= err_cnt + 1;
end if;
end if;
end if;
end process;
end;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.types.all;
entity lt24 is
port
(
CLOCK_50 : in std_logic;
KEY : in std_logic_vector(1 downto 0);
GPIO_0 : inout std_logic_vector(33 downto 0);
LT24_LCD_ON : out std_logic;
LT24_CS_N : out std_logic;
LT24_RESET_N : out std_logic;
LT24_RS : out std_logic; -- D/CX
LT24_WR_N : out std_logic;
LT24_RD_N : out std_logic;
LT24_D : inout std_logic_vector(15 downto 0));
end lt24;
architecture rtl of lt24 is
component bidir16
port
(
bidir : inout std_logic_vector(15 downto 0);
oe : in std_logic;
clk : in std_logic;
i : in std_logic_vector(15 downto 0);
o : out std_logic_vector(15 downto 0));
end component;
component topEntity_0
port(eta_i1 : in std_logic_vector(17 downto 0);
clk1000 : in std_logic;
clk1000_rst : in std_logic;
topLet_o : out std_logic_vector(24 downto 0));
end component;
signal clashi : std_logic_vector(17 downto 0);
signal clasho : std_logic_vector(24 downto 0);
signal ltdin : std_logic_vector(15 downto 0);
signal ltdout : std_logic_vector(15 downto 0);
signal oe : std_logic;
signal rxd : std_logic;
signal txd : std_logic;
begin
clash : topEntity_0
port map(
eta_i1 => clashi,
clk1000 => CLOCK_50,
clk1000_rst => KEY(0),
topLet_o => clasho);
lt24d : bidir16
port map(
bidir => LT24_D,
oe => oe,
clk => CLOCK_50,
i => ltdout,
o => ltdin);
clashi(15 downto 0) <= ltdin;
clashi(16) <= rxd;
clashi(17) <= KEY(1);
rxd <= GPIO_0(2);
GPIO_0(1) <= clasho(24);
txd <= clasho(23);
GPIO_0(4) <= txd;
LT24_LCD_ON <= clasho(22);
LT24_CS_N <= clasho(21);
LT24_RESET_N <= clasho(20);
LT24_RS <= clasho(19); -- D/CX
LT24_WR_N <= clasho(18);
LT24_RD_N <= clasho(17);
ltdout <= clasho(16 downto 1);
oe <= clasho(0);
end rtl;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: user.org:user:router:1.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY sys_router_0_0 IS
PORT (
CLOCK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
L_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
L_VIN : IN STD_LOGIC;
L_RIN : OUT STD_LOGIC;
L_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
L_VOUT : OUT STD_LOGIC;
L_ROUT : IN STD_LOGIC;
N_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
N_VIN : IN STD_LOGIC;
N_RIN : OUT STD_LOGIC;
N_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
N_VOUT : OUT STD_LOGIC;
N_ROUT : IN STD_LOGIC;
E_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
E_VIN : IN STD_LOGIC;
E_RIN : OUT STD_LOGIC;
E_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
E_VOUT : OUT STD_LOGIC;
E_ROUT : IN STD_LOGIC
);
END sys_router_0_0;
ARCHITECTURE sys_router_0_0_arch OF sys_router_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF sys_router_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT router_struct IS
GENERIC (
ADDR_X : INTEGER;
ADDR_Y : INTEGER;
N_INST : BOOLEAN;
S_INST : BOOLEAN;
E_INST : BOOLEAN;
W_INST : BOOLEAN
);
PORT (
CLOCK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
L_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
L_VIN : IN STD_LOGIC;
L_RIN : OUT STD_LOGIC;
L_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
L_VOUT : OUT STD_LOGIC;
L_ROUT : IN STD_LOGIC;
N_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
N_VIN : IN STD_LOGIC;
N_RIN : OUT STD_LOGIC;
N_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
N_VOUT : OUT STD_LOGIC;
N_ROUT : IN STD_LOGIC;
S_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_VIN : IN STD_LOGIC;
S_RIN : OUT STD_LOGIC;
S_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_VOUT : OUT STD_LOGIC;
S_ROUT : IN STD_LOGIC;
E_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
E_VIN : IN STD_LOGIC;
E_RIN : OUT STD_LOGIC;
E_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
E_VOUT : OUT STD_LOGIC;
E_ROUT : IN STD_LOGIC;
W_DIN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
W_VIN : IN STD_LOGIC;
W_RIN : OUT STD_LOGIC;
W_DOUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
W_VOUT : OUT STD_LOGIC;
W_ROUT : IN STD_LOGIC
);
END COMPONENT router_struct;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF CLOCK: SIGNAL IS "xilinx.com:signal:clock:1.0 CLOCK CLK";
ATTRIBUTE X_INTERFACE_INFO OF RESET: SIGNAL IS "xilinx.com:signal:reset:1.0 RESET RST";
ATTRIBUTE X_INTERFACE_INFO OF L_DIN: SIGNAL IS "xilinx.com:interface:axis:1.0 L_IN TDATA";
ATTRIBUTE X_INTERFACE_INFO OF L_VIN: SIGNAL IS "xilinx.com:interface:axis:1.0 L_IN TVALID";
ATTRIBUTE X_INTERFACE_INFO OF L_RIN: SIGNAL IS "xilinx.com:interface:axis:1.0 L_IN TREADY";
ATTRIBUTE X_INTERFACE_INFO OF L_DOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 L_OUT TDATA";
ATTRIBUTE X_INTERFACE_INFO OF L_VOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 L_OUT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF L_ROUT: SIGNAL IS "xilinx.com:interface:axis:1.0 L_OUT TREADY";
ATTRIBUTE X_INTERFACE_INFO OF N_DIN: SIGNAL IS "xilinx.com:interface:axis:1.0 N_IN TDATA";
ATTRIBUTE X_INTERFACE_INFO OF N_VIN: SIGNAL IS "xilinx.com:interface:axis:1.0 N_IN TVALID";
ATTRIBUTE X_INTERFACE_INFO OF N_RIN: SIGNAL IS "xilinx.com:interface:axis:1.0 N_IN TREADY";
ATTRIBUTE X_INTERFACE_INFO OF N_DOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 N_OUT TDATA";
ATTRIBUTE X_INTERFACE_INFO OF N_VOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 N_OUT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF N_ROUT: SIGNAL IS "xilinx.com:interface:axis:1.0 N_OUT TREADY";
ATTRIBUTE X_INTERFACE_INFO OF E_DIN: SIGNAL IS "xilinx.com:interface:axis:1.0 E_IN TDATA";
ATTRIBUTE X_INTERFACE_INFO OF E_VIN: SIGNAL IS "xilinx.com:interface:axis:1.0 E_IN TVALID";
ATTRIBUTE X_INTERFACE_INFO OF E_RIN: SIGNAL IS "xilinx.com:interface:axis:1.0 E_IN TREADY";
ATTRIBUTE X_INTERFACE_INFO OF E_DOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 E_OUT TDATA";
ATTRIBUTE X_INTERFACE_INFO OF E_VOUT: SIGNAL IS "xilinx.com:interface:axis:1.0 E_OUT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF E_ROUT: SIGNAL IS "xilinx.com:interface:axis:1.0 E_OUT TREADY";
BEGIN
U0 : router_struct
GENERIC MAP (
ADDR_X => 0,
ADDR_Y => 0,
N_INST => true,
S_INST => false,
E_INST => true,
W_INST => false
)
PORT MAP (
CLOCK => CLOCK,
RESET => RESET,
L_DIN => L_DIN,
L_VIN => L_VIN,
L_RIN => L_RIN,
L_DOUT => L_DOUT,
L_VOUT => L_VOUT,
L_ROUT => L_ROUT,
N_DIN => N_DIN,
N_VIN => N_VIN,
N_RIN => N_RIN,
N_DOUT => N_DOUT,
N_VOUT => N_VOUT,
N_ROUT => N_ROUT,
S_DIN => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S_VIN => '0',
S_ROUT => '0',
E_DIN => E_DIN,
E_VIN => E_VIN,
E_RIN => E_RIN,
E_DOUT => E_DOUT,
E_VOUT => E_VOUT,
E_ROUT => E_ROUT,
W_DIN => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
W_VIN => '0',
W_ROUT => '0'
);
END sys_router_0_0_arch;
|
----------------------------------------------------------------------------------
-- Company: Grad School
-- Engineer: Andreas Schuh
--
-- Create Date: 20:14:04 02/07/2013
-- Design Name:
-- Module Name: Statemachine - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
--ENTITY
entity SystemID is
Port ( ADC1in : in STD_LOGIC_VECTOR (31 downto 0);
ADC2in : in STD_LOGIC_VECTOR (31 downto 0);
DAC1out : out STD_LOGIC_VECTOR (31 downto 0);
DAC2out : out STD_LOGIC_VECTOR (31 downto 0);
clock : in STD_LOGIC);
end SystemID;
-- ARCHITECTURE
architecture Behavioral of SystemID is
------------------------------------------------------------------------------
-- DECLARE Compensator Parameters HERE - From MATLAB generated file
------------------------------------------------------------------------------
constant a11 : std_logic_vector := "00111111011111101000001010110010";
constant a12 : std_logic_vector := "00111101110110001001011101011111";
constant a21 : std_logic_vector := "10111101110110001001011101011111";
constant a22 : std_logic_vector := "00111111011111101000001010110010";
constant a33 : std_logic_vector := "00111111010011110100100101011111";
constant a34 : std_logic_vector := "00111111000101011100110100100011";
constant a43 : std_logic_vector := "10111111000101011100110100100011";
constant a44 : std_logic_vector := "00111111010011110100100101011111";
constant b1 : std_logic_vector := "10111011100101011111001010000110";
constant b2 : std_logic_vector := "00111100010101100110011000100000";
constant b3 : std_logic_vector := "10111011011001000111010100110001";
constant b4 : std_logic_vector := "10111100110010111000011111101011";
constant c1 : std_logic_vector := "00111100010101100010100101100000";
constant c2 : std_logic_vector := "10111011100101010110010010000101";
constant c3 : std_logic_vector := "10111100110010110101101110110001";
constant c4 : std_logic_vector := "10111011011001111000101100010100";
constant k1 : std_logic_vector := "10111101010100011110001110111000";
constant k2 : std_logic_vector := "00111101111000111001100001101000";
constant k3 : std_logic_vector := "00111101101000010100111110001011";
constant k4 : std_logic_vector := "10111110000110110101100011110011";
constant l1 : std_logic_vector := "00111111101000100100001001100101";
constant l2 : std_logic_vector := "10111110100100111111011000000000";
constant l3 : std_logic_vector := "11000000000100100001111011010000";
constant l4 : std_logic_vector := "10111110111111101110100111111000";
-- COMPONENTS
COMPONENT AddFloat
PORT (
a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
operation_nd : IN STD_LOGIC;
operation_rfd : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
underflow : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
invalid_op : OUT STD_LOGIC;
rdy : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT MultFloat
PORT (
a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
operation_nd : IN STD_LOGIC;
operation_rfd : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
underflow : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
invalid_op : OUT STD_LOGIC;
rdy : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT SubFloat
PORT (
a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
operation_nd : IN STD_LOGIC;
operation_rfd : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
underflow : OUT STD_LOGIC;
overflow : OUT STD_LOGIC;
invalid_op : OUT STD_LOGIC;
rdy : OUT STD_LOGIC
);
END COMPONENT;
-- for non Trimming
attribute KEEP : string;
attribute S : string;
-- SIGNALS
signal mult1a : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal mult1b : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal result_mult1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal mult2a : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal mult2b : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal result_mult2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal mult3a : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal mult3b : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal result_mult3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal mult4a : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal mult4b : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal result_mult4 : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal add1a : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal add1b : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal result_add1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal add2a : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal add2b : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal result_add2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal add3a : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal add3b : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal result_add3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal add4a : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal add4b : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal result_add4 : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal sub1a : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal sub1b : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal result_sub1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal vresult: std_logic_vector(31 downto 0);
signal vX1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := (others => '0');
signal vX2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := (others => '0');
signal vX3 : STD_LOGIC_VECTOR(31 DOWNTO 0) := (others => '0');
signal vX4 : STD_LOGIC_VECTOR(31 DOWNTO 0) := (others => '0');
signal vKX : STD_LOGIC_VECTOR(31 DOWNTO 0) := (others => '0');
signal vCX : STD_LOGIC_VECTOR(31 DOWNTO 0) := (others => '0');
signal vRminusKX : STD_LOGIC_VECTOR(31 DOWNTO 0) := (others => '0');
signal vSensorMinusCX : STD_LOGIC_VECTOR(31 DOWNTO 0) := (others => '0');
signal vInter_add1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := (others => '0');
signal vInter_add2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := (others => '0');
signal vInter_add3 : STD_LOGIC_VECTOR(31 DOWNTO 0) := (others => '0');
signal vInter_add4 : STD_LOGIC_VECTOR(31 DOWNTO 0) := (others => '0');
signal vInter_misc1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := (others => '0');
signal vInter_misc2 : STD_LOGIC_VECTOR(31 DOWNTO 0) := (others => '0');
signal operation_nd1 : STD_LOGIC;
signal operation_nd2 : STD_LOGIC;
signal operation_nd3 : STD_LOGIC;
signal operation_nd4 : STD_LOGIC;
signal operation_nd5 : STD_LOGIC;
signal operation_nd6 : STD_LOGIC;
signal operation_nd7 : STD_LOGIC;
signal operation_nd8 : STD_LOGIC;
signal operation_nd9 : STD_LOGIC;
signal ADCbuff : STD_LOGIC_VECTOR(31 DOWNTO 0);
-- STATE DEFINITIONS
type state_type is (Zero,One,Two,Three,Four,Five,Six,Seven,Eight,Nine);
signal state : state_type;
-- BEGIN
begin
-- INSTANTIATION OF COMPONENTS
AddFloat1 : AddFloat
PORT MAP (
a => add1a,
b => add1b,
operation_nd => operation_nd1,
operation_rfd => open,
result => result_add1,
underflow => open,
overflow => open,
invalid_op => open,
rdy => open
);
AddFloat2 : AddFloat
PORT MAP (
a => add2a,
b => add2b,
operation_nd => operation_nd2,
operation_rfd => open,
result => result_add2,
underflow => open,
overflow => open,
invalid_op => open,
rdy => open
);
AddFloat3 : AddFloat
PORT MAP (
a => add3a,
b => add3b,
operation_nd => operation_nd3,
operation_rfd => open,
result => result_add3,
underflow => open,
overflow => open,
invalid_op => open,
rdy => open
);
AddFloat4 : AddFloat
PORT MAP (
a => add4a,
b => add4b,
operation_nd => operation_nd4,
operation_rfd => open,
result => result_add4,
underflow => open,
overflow => open,
invalid_op => open,
rdy => open
);
MultFloat1 : MultFloat
PORT MAP (
a => mult1a,
b => mult1b,
operation_nd => operation_nd5,
operation_rfd => open,
result => result_mult1,
underflow => open,
overflow => open,
invalid_op => open,
rdy => open
);
MultFloat2 : MultFloat
PORT MAP (
a => mult2a,
b => mult2b,
operation_nd => operation_nd6,
operation_rfd => open,
result => result_mult2,
underflow => open,
overflow => open,
invalid_op => open,
rdy => open
);
MultFloat3 : MultFloat
PORT MAP (
a => mult3a,
b => mult3b,
operation_nd => operation_nd7,
operation_rfd => open,
result => result_mult3,
underflow => open,
overflow => open,
invalid_op => open,
rdy => open
);
MultFloat4 : MultFloat
PORT MAP (
a => mult4a,
b => mult4b,
operation_nd => operation_nd8,
operation_rfd => open,
result => result_mult4,
underflow => open,
overflow => open,
invalid_op => open,
rdy =>open
);
SubFloat1: SubFloat
PORT MAP (
a => sub1a,
b => sub1b,
operation_nd => operation_nd9,
operation_rfd => open,
result => result_sub1,
underflow => open,
overflow => open,
invalid_op => open,
rdy => open
);
-- SERIAL, SYNCHRONOUS PROCESS
-- All of the state machine is synchronous, no asyn. (combinatorial) code
process (clock)
begin
if(clock'event and clock='1') then
-- Default values for signal, to enforce full assigment.
mult1a <= (others => '0');
mult1b <= (others => '0');
mult2a <= (others => '0');
mult2b <= (others => '0');
mult3a <= (others => '0');
mult3b <= (others => '0');
mult4a <= (others => '0');
mult4b <= (others => '0');
add1a <= (others => '0');
add1b <= (others => '0');
add2a <= (others => '0');
add2b <= (others => '0');
add3a <= (others => '0');
add3b <= (others => '0');
add4a <= (others => '0');
add4b <= (others => '0');
sub1a <= (others => '0');
sub1b <= (others => '0');
vresult <= vresult;
vX1 <= vX1;
vX2 <= vX2;
vX3 <= vX3;
vX4 <= vX4;
vKX <= vKX;
vCX <= vCX;
vRminusKX <= vRminusKX;
vSensorMinusCX <= vSensorMinusCX;
vInter_add1 <= vInter_add1;
vInter_add2 <= vInter_add2;
vInter_add3 <= vInter_add3;
vInter_add4 <= vInter_add4;
vInter_misc1 <= vInter_misc1;
vInter_misc2 <= vInter_misc2;
operation_nd1 <= '0';
operation_nd2 <= '0';
operation_nd3 <= '0';
operation_nd4 <= '0';
operation_nd5 <= '0';
operation_nd6 <= '0';
operation_nd7 <= '0';
operation_nd8 <= '0';
operation_nd9 <= '0';
DAC1out <= vRminusKX;
DAC2out <= vCX;
state <= state;
-- START STATE MACHINE
case state is
when Zero =>
mult1a <= (others => '0');
mult1b <= (others => '0');
mult2a <= (others => '0');
mult2b <= (others => '0');
mult3a <= (others => '0');
mult3b <= (others => '0');
mult4a <= (others => '0');
mult4b <= (others => '0');
add1a <= (others => '0');
add1b <= (others => '0');
add2a <= (others => '0');
add2b <= (others => '0');
add3a <= (others => '0');
add3b <= (others => '0');
add4a <= (others => '0');
add4b <= (others => '0');
sub1a <= (others => '0');
sub1b <= (others => '0');
vresult <= (others => '0');
vX1 <= (others => '0');
vX2 <= (others => '0');
vX3 <= (others => '0');
vX4 <= (others => '0');
vKX <= (others => '0');
vCX <= (others => '0');
vRminusKX <= (others => '0');
vSensorMinusCX <= (others => '0');
vInter_add1 <= (others => '0');
vInter_add2 <= (others => '0');
vInter_add3 <= (others => '0');
vInter_add4 <= (others => '0');
vInter_misc1 <= (others => '0');
vInter_misc2 <= (others => '0');
DAC1out <= (others => '0');
DAC2out <= (others => '0');
operation_nd1 <= '0';
operation_nd2 <= '0';
operation_nd3 <= '0';
operation_nd4 <= '0';
operation_nd5 <= '0';
operation_nd6 <= '0';
operation_nd7 <= '0';
operation_nd8 <= '0';
operation_nd9 <= '0';
state <= One;
when One =>
add1a <= (others=>'0');
add1b <= (others=>'0');
operation_nd1 <= '0';
--vInter_misc1 := result_add1;
add2a <= (others=>'0');
add2b <= (others=>'0');
operation_nd2 <= '0';
--vInter_misc2 := result_add2;
add3a <= (others=>'0');
add3b <= (others=>'0');
operation_nd3 <= '0';
add4a <= (others=>'0');
add4b <= (others=>'0');
operation_nd4 <= '0';
mult1a <= vX1;
mult1b <= c1;
operation_nd5 <= '1';
mult2a <= vX2;
mult2b <= c2;
operation_nd6 <= '1';
mult3a <= vX3;
mult3b <= c3;
operation_nd7 <= '1';
mult4a <= vX4;
mult4b <= c4;
operation_nd8 <= '1';
sub1a <= ADC1in;
sub1b <= result_add1;
vKX <= result_add1;
operation_nd9 <= '1';
state <= Two;
when Two =>
add1a <= result_mult1;
add1b <= result_mult2;
operation_nd1 <= '1';
add2a <= result_mult3;
add2b <= result_mult4;
operation_nd2 <= '1';
add3a <= (others=>'0');
add3b <= (others=>'0');
operation_nd3 <= '0';
add4a <= (others=>'0');
add4b <= (others=>'0');
operation_nd4 <= '0';
mult1a <= vX1;
mult1b <= a11;
operation_nd5 <= '1';
mult2a <= vX2;
mult2b <= a12;
operation_nd6 <= '1';
mult3a <= vX1;
mult3b <= a21;
operation_nd7 <= '1';
mult4a <= vX2;
mult4b <= a22;
operation_nd8 <= '1';
vRminusKX <= result_sub1;
sub1a <= (others => '0');
sub1b <= (others => '0');
operation_nd9 <= '0';
state <= Three;
when Three =>
add1a <= result_mult1;
add1b <= result_mult2;
operation_nd1 <= '1';
add2a <= result_mult3;
add2b <= result_mult4;
operation_nd2 <= '1';
add3a <= result_add1;
add3b <= result_add2;
operation_nd3 <= '1';
add4a <= (others=>'0');
add4b <= (others=>'0');
operation_nd4 <= '0';
mult1a <= vX3;
mult1b <= a33;
operation_nd5 <= '1';
mult2a <= vX4;
mult2b <= a34;
operation_nd6 <= '1';
mult3a <= vX3;
mult3b <= a43;
operation_nd7 <= '1';
mult4a <= vX4;
mult4b <= a44;
operation_nd8 <= '1';
sub1a <= (others => '0');
sub1b <= (others => '0');
operation_nd9 <= '0';
state <= Four;
when Four =>
add1a <= result_mult1;
add1b <= result_mult2;
operation_nd1 <= '1';
vX1 <= result_add1;
add2a <= result_mult3;
add2b <= result_mult4;
operation_nd2 <= '1';
vX2 <= result_add2;
add3a <= (others=>'0');
add3b <= (others=>'0');
operation_nd3 <= '0';
add4a <= (others=>'0');
add4b <= (others=>'0');
operation_nd4 <= '0';
mult1a <= vRminusKX;
mult1b <= b1;
operation_nd5 <= '1';
mult2a <= vRminusKX;
mult2b <= b2;
operation_nd6 <= '1';
mult3a <= vRminusKX;
mult3b <= b3;
operation_nd7 <= '1';
mult4a <= vRminusKX;
mult4b <= b4;
operation_nd8 <= '1';
sub1a <= ADC2in;
sub1b <= result_add3;
operation_nd9 <= '1';
vCX <= result_add3;
state <= Five;
when Five =>
add1a <= vX1;
add1b <= result_mult1;
operation_nd1 <= '1';
add2a <= vX2;
add2b <= result_mult2;
operation_nd2 <= '1';
add3a <= result_add1;
add3b <= result_mult3;
vX3 <= result_add1;
operation_nd3 <= '1';
add4a <= result_add2;
add4b <= result_mult4;
vX4 <= result_add2;
operation_nd4 <= '1';
vSensorMinusCX <= result_sub1;
mult1a <= result_sub1;
mult1b <= l1;
operation_nd5 <= '1';
mult2a <= result_sub1;
mult2b <= l2;
operation_nd6 <= '1';
mult3a <= result_sub1;
mult3b <= l3;
operation_nd7 <= '1';
mult4a <= result_sub1;
mult4b <= l4;
operation_nd8 <= '1';
sub1a <= (others => '0');
sub1b <= (others => '0');
operation_nd9 <= '0';
state <= Six;
when Six =>
add1a <= result_add1;
add1b <= result_mult1;
operation_nd1 <= '1';
vX1 <= result_add1;
add2a <= result_add2;
add2b <= result_mult2;
operation_nd2 <= '1';
vX2 <= result_add2;
add3a <= result_add3;
add3b <= result_mult3;
operation_nd3 <= '1';
vX3 <= result_add3;
add4a <= result_add4;
add4b <= result_mult4;
operation_nd4 <= '1';
vX4 <= result_add4;
mult1a <= (others => '0');
mult1b <= (others => '0');
operation_nd5 <= '0';
mult2a <= (others => '0');
mult2b <= (others => '0');
operation_nd6 <= '0';
mult3a <= (others => '0');
mult3b <= (others => '0');
operation_nd7 <= '0';
mult4a <= (others => '0');
mult4b <= (others => '0');
operation_nd8 <= '0';
sub1a <= (others => '0');
sub1b <= (others => '0');
operation_nd9 <= '0';
state <= Seven;
when Seven =>
vX1 <= result_add1;
vX2 <= result_add2;
vX3 <= result_add3;
vX4 <= result_add4;
add1a <= (others=>'0');
add1b <= (others=>'0');
operation_nd1 <= '0';
add2a <= (others=>'0');
add2b <= (others=>'0');
operation_nd2 <= '0';
add3a <= (others=>'0');
add3b <= (others=>'0');
operation_nd3 <= '0';
add4a <= (others=>'0');
add4b <= (others=>'0');
operation_nd4 <= '0';
mult1a <= result_add1;
mult1b <= k1;
operation_nd5 <= '1';
mult2a <= result_add2;
mult2b <= k2;
operation_nd6 <= '1';
mult3a <= result_add3;
mult3b <= k3;
operation_nd7 <= '1';
mult4a <= result_add4;
mult4b <= k4;
operation_nd8 <= '1';
sub1a <= (others => '0');
sub1b <= (others => '0');
operation_nd9 <= '0';
state <= Eight;
when Eight =>
add1a <= result_mult1;
add1b <= result_mult2;
operation_nd1 <= '1';
add2a <= result_mult3;
add2b <= result_mult4;
operation_nd2 <= '1';
add3a <= (others=>'0');
add3b <= (others=>'0');
operation_nd3 <= '0';
add4a <= (others=>'0');
add4b <= (others=>'0');
operation_nd4 <= '0';
mult1a <= (others => '0');
mult1b <= (others => '0');
operation_nd5 <= '0';
mult2a <= (others => '0');
mult2b <= (others => '0');
operation_nd6 <= '0';
mult3a <= (others => '0');
mult3b <= (others => '0');
operation_nd7 <= '0';
mult4a <= (others => '0');
mult4b <= (others => '0');
operation_nd8 <= '0';
sub1a <= (others => '0');
sub1b <= (others => '0');
operation_nd9 <= '0';
state <= Nine;
when Nine =>
add1a <= result_add1;
add1b <= result_add2;
operation_nd1 <= '1';
add2a <= (others=>'0');
add2b <= (others=>'0');
operation_nd2 <= '0';
add3a <= (others=>'0');
add3b <= (others=>'0');
operation_nd3 <= '0';
add4a <= (others=>'0');
add4b <= (others=>'0');
operation_nd4 <= '0';
mult1a <= (others => '0');
mult1b <= (others => '0');
operation_nd5 <= '0';
mult2a <= (others => '0');
mult2b <= (others => '0');
operation_nd6 <= '0';
mult3a <= (others => '0');
mult3b <= (others => '0');
operation_nd7 <= '0';
mult4a <= (others => '0');
mult4b <= (others => '0');
operation_nd8 <= '0';
sub1a <= (others => '0');
sub1b <= (others => '0');
operation_nd9 <= '0';
state <= One;
when others =>
mult1a <= (others => '0');
mult1b <= (others => '0');
mult2a <= (others => '0');
mult2b <= (others => '0');
mult3a <= (others => '0');
mult3b <= (others => '0');
mult4a <= (others => '0');
mult4b <= (others => '0');
add1a <= (others => '0');
add1b <= (others => '0');
add2a <= (others => '0');
add2b <= (others => '0');
add3a <= (others => '0');
add3b <= (others => '0');
add4a <= (others => '0');
add4b <= (others => '0');
sub1a <= (others => '0');
sub1b <= (others => '0');
vresult <= (others => '0');
vX1 <= (others => '0');
vX2 <= (others => '0');
vX3 <= (others => '0');
vX4 <= (others => '0');
vKX <= (others => '0');
vCX <= (others => '0');
vRminusKX <= (others => '0');
vSensorMinusCX <= (others => '0');
vInter_add1 <= (others => '0');
vInter_add2 <= (others => '0');
vInter_add3 <= (others => '0');
vInter_add4 <= (others => '0');
vInter_misc1 <= (others => '0');
vInter_misc2 <= (others => '0');
DAC1out <= (others => '0');
DAC2out <= (others => '0');
operation_nd1 <= '0';
operation_nd2 <= '0';
operation_nd3 <= '0';
operation_nd4 <= '0';
operation_nd5 <= '0';
operation_nd6 <= '0';
operation_nd7 <= '0';
operation_nd8 <= '0';
operation_nd9 <= '0';
state <= One;
end case;
end if;
end process;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
entity xnor104 is
port (
a_i : in std_logic_vector (103 downto 0);
b_i : in std_logic_vector (103 downto 0);
c_o : out std_logic_vector (103 downto 0)
);
end entity xnor104;
architecture rtl of xnor104 is
begin
c_o <= a_i xnor b_i;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
entity xnor104 is
port (
a_i : in std_logic_vector (103 downto 0);
b_i : in std_logic_vector (103 downto 0);
c_o : out std_logic_vector (103 downto 0)
);
end entity xnor104;
architecture rtl of xnor104 is
begin
c_o <= a_i xnor b_i;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
entity xnor104 is
port (
a_i : in std_logic_vector (103 downto 0);
b_i : in std_logic_vector (103 downto 0);
c_o : out std_logic_vector (103 downto 0)
);
end entity xnor104;
architecture rtl of xnor104 is
begin
c_o <= a_i xnor b_i;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
entity xnor104 is
port (
a_i : in std_logic_vector (103 downto 0);
b_i : in std_logic_vector (103 downto 0);
c_o : out std_logic_vector (103 downto 0)
);
end entity xnor104;
architecture rtl of xnor104 is
begin
c_o <= a_i xnor b_i;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
entity solver_tb is
end solver_tb;
architecture behavioral of solver_tb is
component solver
port (
clk: in std_logic;
reset: in std_logic;
sat: out std_logic;
unsat: out std_logic
);
end component;
for solver_0: solver use entity work.solver;
signal clk, reset, sat, unsat: std_logic := '0';
begin
-- Instantiate solver
solver_0: solver port map (
clk => clk,
reset => reset,
sat => sat,
unsat => unsat
);
-- 166Mhz clock ~= 5.74 ns full-period, 2.87 ns half-period
clk <= '0' when (sat='1' or unsat='1') else not clk after 2.87 ns;
reset <= '0', '1' after 2 ns, '0' after 7 ns;
end behavioral; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package approximationTable is
constant approximationVector : std_logic_vector(268-1 downto 0) := ('1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1',
'1');
end package approximationTable;
|
--
-------------------------------------------------------------------------------------------
-- Copyright © 2011, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
-- UART Transmitter with integral 16 byte FIFO buffer
--
-- 8 bit, no parity, 1 stop bit
--
-- This module was made for use with Spartan-6 Generation Devices and is also ideally
-- suited for use with Virtex-6 and 7-Series devices.
--
-- Version 1 - 31st March 2011.
--
-- Ken Chapman
-- Xilinx Ltd
-- Benchmark House
-- 203 Brooklands Road
-- Weybridge
-- Surrey KT13 ORH
-- United Kingdom
--
-- [email protected]
--
-------------------------------------------------------------------------------------------
--
-- Format of this file.
--
-- The module defines the implementation of the logic using Xilinx primitives.
-- These ensure predictable synthesis results and maximise the density of the
-- implementation. The Unisim Library is used to define Xilinx primitives. It is also
-- used during simulation.
-- The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
-------------------------------------------------------------------------------------------
--
-- Library declarations
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
-------------------------------------------------------------------------------------------
--
-- Main Entity for
--
entity uart_tx6 is
Port ( data_in : in std_logic_vector(7 downto 0);
en_16_x_baud : in std_logic;
serial_out : out std_logic;
buffer_write : in std_logic;
buffer_data_present : out std_logic;
buffer_half_full : out std_logic;
buffer_full : out std_logic;
buffer_reset : in std_logic;
clk : in std_logic);
end uart_tx6;
--
-------------------------------------------------------------------------------------------
--
-- Start of Main Architecture for uart_tx6 - constrained
--
architecture rtl of uart_tx6 is
--
-------------------------------------------------------------------------------------------
--
-- Signals used in uart_tx6
--
-------------------------------------------------------------------------------------------
--
signal store_data : std_logic_vector(7 downto 0);
signal data : std_logic_vector(7 downto 0);
signal pointer_value : std_logic_vector(3 downto 0);
signal pointer : std_logic_vector(3 downto 0);
signal en_pointer : std_logic;
signal zero : std_logic;
signal full_int : std_logic;
signal data_present_value : std_logic;
signal data_present_int : std_logic;
signal sm_value : std_logic_vector(3 downto 0);
signal sm : std_logic_vector(3 downto 0);
signal div_value : std_logic_vector(3 downto 0);
signal div : std_logic_vector(3 downto 0);
signal lsb_data : std_logic;
signal msb_data : std_logic;
signal last_bit : std_logic;
signal serial_data : std_logic;
signal next_value : std_logic;
signal next_bit : std_logic;
signal buffer_read_value : std_logic;
signal buffer_read : std_logic;
--
-------------------------------------------------------------------------------------------
--
-- Attributes to guide mapping of logic into Slices.
-------------------------------------------------------------------------------------------
--
--
attribute hblknm : string;
attribute hblknm of pointer3_lut : label is "uart_tx6_1";
attribute hblknm of pointer3_flop : label is "uart_tx6_1";
attribute hblknm of pointer2_lut : label is "uart_tx6_1";
attribute hblknm of pointer2_flop : label is "uart_tx6_1";
attribute hblknm of pointer01_lut : label is "uart_tx6_1";
attribute hblknm of pointer1_flop : label is "uart_tx6_1";
attribute hblknm of pointer0_flop : label is "uart_tx6_1";
attribute hblknm of data_present_lut : label is "uart_tx6_1";
attribute hblknm of data_present_flop : label is "uart_tx6_1";
--
attribute hblknm of sm0_lut : label is "uart_tx6_2";
attribute hblknm of sm0_flop : label is "uart_tx6_2";
attribute hblknm of sm1_lut : label is "uart_tx6_2";
attribute hblknm of sm1_flop : label is "uart_tx6_2";
attribute hblknm of sm2_lut : label is "uart_tx6_2";
attribute hblknm of sm2_flop : label is "uart_tx6_2";
attribute hblknm of sm3_lut : label is "uart_tx6_2";
attribute hblknm of sm3_flop : label is "uart_tx6_2";
--
attribute hblknm of div01_lut : label is "uart_tx6_3";
attribute hblknm of div23_lut : label is "uart_tx6_3";
attribute hblknm of div0_flop : label is "uart_tx6_3";
attribute hblknm of div1_flop : label is "uart_tx6_3";
attribute hblknm of div2_flop : label is "uart_tx6_3";
attribute hblknm of div3_flop : label is "uart_tx6_3";
attribute hblknm of next_lut : label is "uart_tx6_3";
attribute hblknm of next_flop : label is "uart_tx6_3";
attribute hblknm of read_flop : label is "uart_tx6_3";
--
attribute hblknm of lsb_data_lut : label is "uart_tx6_4";
attribute hblknm of msb_data_lut : label is "uart_tx6_4";
attribute hblknm of serial_lut : label is "uart_tx6_4";
attribute hblknm of serial_flop : label is "uart_tx6_4";
attribute hblknm of full_lut : label is "uart_tx6_4";
--
--
-------------------------------------------------------------------------------------------
--
-- Start of uart_tx6 circuit description
--
-------------------------------------------------------------------------------------------
--
begin
-- SRL16E data storage
data_width_loop: for i in 0 to 7 generate
attribute hblknm : string;
attribute hblknm of storage_srl : label is "uart_tx6_5";
attribute hblknm of storage_flop : label is "uart_tx6_5";
begin
storage_srl: SRL16E
generic map (INIT => X"0000")
port map( D => data_in(i),
CE => buffer_write,
CLK => clk,
A0 => pointer(0),
A1 => pointer(1),
A2 => pointer(2),
A3 => pointer(3),
Q => store_data(i) );
storage_flop: FD
port map ( D => store_data(i),
Q => data(i),
C => clk);
end generate data_width_loop;
pointer3_lut: LUT6
generic map (INIT => X"FF00FE00FF80FF00")
port map( I0 => pointer(0),
I1 => pointer(1),
I2 => pointer(2),
I3 => pointer(3),
I4 => buffer_write,
I5 => buffer_read,
O => pointer_value(3));
pointer3_flop: FDR
port map ( D => pointer_value(3),
Q => pointer(3),
R => buffer_reset,
C => clk);
pointer2_lut: LUT6
generic map (INIT => X"F0F0E1E0F878F0F0")
port map( I0 => pointer(0),
I1 => pointer(1),
I2 => pointer(2),
I3 => pointer(3),
I4 => buffer_write,
I5 => buffer_read,
O => pointer_value(2));
pointer2_flop: FDR
port map ( D => pointer_value(2),
Q => pointer(2),
R => buffer_reset,
C => clk);
pointer01_lut: LUT6_2
generic map (INIT => X"CC9060CCAA5050AA")
port map( I0 => pointer(0),
I1 => pointer(1),
I2 => en_pointer,
I3 => buffer_write,
I4 => buffer_read,
I5 => '1',
O5 => pointer_value(0),
O6 => pointer_value(1));
pointer1_flop: FDR
port map ( D => pointer_value(1),
Q => pointer(1),
R => buffer_reset,
C => clk);
pointer0_flop: FDR
port map ( D => pointer_value(0),
Q => pointer(0),
R => buffer_reset,
C => clk);
data_present_lut: LUT6_2
generic map (INIT => X"F4FCF4FC040004C0")
port map( I0 => zero,
I1 => data_present_int,
I2 => buffer_write,
I3 => buffer_read,
I4 => full_int,
I5 => '1',
O5 => en_pointer,
O6 => data_present_value);
data_present_flop: FDR
port map ( D => data_present_value,
Q => data_present_int,
R => buffer_reset,
C => clk);
full_lut: LUT6_2
generic map (INIT => X"0001000080000000")
port map( I0 => pointer(0),
I1 => pointer(1),
I2 => pointer(2),
I3 => pointer(3),
I4 => '1',
I5 => '1',
O5 => full_int,
O6 => zero);
lsb_data_lut: LUT6
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data(0),
I1 => data(1),
I2 => data(2),
I3 => data(3),
I4 => sm(0),
I5 => sm(1),
O => lsb_data);
msb_data_lut: LUT6
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data(4),
I1 => data(5),
I2 => data(6),
I3 => data(7),
I4 => sm(0),
I5 => sm(1),
O => msb_data);
serial_lut: LUT6_2
generic map (INIT => X"CFAACC0F0FFFFFFF")
port map( I0 => lsb_data,
I1 => msb_data,
I2 => sm(1),
I3 => sm(2),
I4 => sm(3),
I5 => '1',
O5 => last_bit,
O6 => serial_data);
serial_flop: FD
port map ( D => serial_data,
Q => serial_out,
C => clk);
sm0_lut: LUT6
generic map (INIT => X"85500000AAAAAAAA")
port map( I0 => sm(0),
I1 => sm(1),
I2 => sm(2),
I3 => sm(3),
I4 => data_present_int,
I5 => next_bit,
O => sm_value(0));
sm0_flop: FD
port map ( D => sm_value(0),
Q => sm(0),
C => clk);
sm1_lut: LUT6
generic map (INIT => X"26610000CCCCCCCC")
port map( I0 => sm(0),
I1 => sm(1),
I2 => sm(2),
I3 => sm(3),
I4 => data_present_int,
I5 => next_bit,
O => sm_value(1));
sm1_flop: FD
port map ( D => sm_value(1),
Q => sm(1),
C => clk);
sm2_lut: LUT6
generic map (INIT => X"88700000F0F0F0F0")
port map( I0 => sm(0),
I1 => sm(1),
I2 => sm(2),
I3 => sm(3),
I4 => data_present_int,
I5 => next_bit,
O => sm_value(2));
sm2_flop: FD
port map ( D => sm_value(2),
Q => sm(2),
C => clk);
sm3_lut: LUT6
generic map (INIT => X"87440000FF00FF00")
port map( I0 => sm(0),
I1 => sm(1),
I2 => sm(2),
I3 => sm(3),
I4 => data_present_int,
I5 => next_bit,
O => sm_value(3));
sm3_flop: FD
port map ( D => sm_value(3),
Q => sm(3),
C => clk);
div01_lut: LUT6_2
generic map (INIT => X"6C0000005A000000")
port map( I0 => div(0),
I1 => div(1),
I2 => en_16_x_baud,
I3 => '1',
I4 => '1',
I5 => '1',
O5 => div_value(0),
O6 => div_value(1));
div0_flop: FD
port map ( D => div_value(0),
Q => div(0),
C => clk);
div1_flop: FD
port map ( D => div_value(1),
Q => div(1),
C => clk);
div23_lut: LUT6_2
generic map (INIT => X"7F80FF007878F0F0")
port map( I0 => div(0),
I1 => div(1),
I2 => div(2),
I3 => div(3),
I4 => en_16_x_baud,
I5 => '1',
O5 => div_value(2),
O6 => div_value(3));
div2_flop: FD
port map ( D => div_value(2),
Q => div(2),
C => clk);
div3_flop: FD
port map ( D => div_value(3),
Q => div(3),
C => clk);
next_lut: LUT6_2
generic map (INIT => X"0000000080000000")
port map( I0 => div(0),
I1 => div(1),
I2 => div(2),
I3 => div(3),
I4 => en_16_x_baud,
I5 => last_bit,
O5 => next_value,
O6 => buffer_read_value);
next_flop: FD
port map ( D => next_value,
Q => next_bit,
C => clk);
read_flop: FD
port map ( D => buffer_read_value,
Q => buffer_read,
C => clk);
-- assign internal signals to outputs
buffer_full <= full_int;
buffer_half_full <= pointer(3);
buffer_data_present <= data_present_int;
end;
-------------------------------------------------------------------------------------------
--
-- END OF FILE uart_tx6.vhd
--
-------------------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------------
-- FILE NAME : fmc150_stellar_cmd.vhd
--
-- AUTHOR : Peter Kortekaas
--
-- COMPANY : 4DSP
--
-- ITEM : 1
--
-- UNITS : Entity - fmc150_stellar_cmd
-- architecture - fmc150_stellar_cmd_syn
--
-- LANGUAGE : VHDL
--
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
--
--
--
--
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
--------------------------------------------------------------------------------
-- Entity declaration
--------------------------------------------------------------------------------
entity fmc150_stellar_cmd is
generic (
START_ADDR : std_logic_vector(27 downto 0) := x"0000000";
STOP_ADDR : std_logic_vector(27 downto 0) := x"0000010"
);
port (
reset : in std_logic;
-- Command interface
clk_cmd : in std_logic; --cmd_in and cmd_out are synchronous to this clock;
out_cmd : out std_logic_vector(63 downto 0);
out_cmd_val : out std_logic;
in_cmd : in std_logic_vector(63 downto 0);
in_cmd_val : in std_logic;
-- Register interface
clk_reg : in std_logic; --register interface is synchronous to this clock
out_reg : out std_logic_vector(31 downto 0);--caries the out register data
out_reg_val : out std_logic; --the out_reg has valid data (pulse)
out_reg_addr : out std_logic_vector(27 downto 0);--out register address
in_reg : in std_logic_vector(31 downto 0);--requested register data is placed on this bus
in_reg_val : in std_logic; --pulse to indicate requested register is valid
in_reg_req : out std_logic; --pulse to request data
in_reg_addr : out std_logic_vector(27 downto 0);--requested address
-- Mailbox interface
mbx_in_reg : in std_logic_vector(31 downto 0);--value of the mailbox to send
mbx_in_val : in std_logic --pulse to indicate mailbox is valid
);
end entity fmc150_stellar_cmd;
--------------------------------------------------------------------------------
-- Architecture declaration
--------------------------------------------------------------------------------
architecture arch_fmc150_stellar_cmd of fmc150_stellar_cmd is
-----------------------------------------------------------------------------------
-- Constant declarations
-----------------------------------------------------------------------------------
constant CMD_WR : std_logic_vector(3 downto 0) := x"1";
constant CMD_RD : std_logic_vector(3 downto 0) := x"2";
constant CMD_RD_ACK : std_logic_vector(3 downto 0) := x"4";
-----------------------------------------------------------------------------------
-- Dignal declarations
-----------------------------------------------------------------------------------
signal register_wr : std_logic;
signal register_rd : std_logic;
signal out_cmd_val_sig : std_logic;
signal in_reg_addr_sig : std_logic_vector(27 downto 0);
signal mbx_in_val_sig : std_logic;
signal mbx_received : std_logic;
-----------------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------------
component pulse2pulse
port (
in_clk : in std_logic;
out_clk : in std_logic;
rst : in std_logic;
pulsein : in std_logic;
inbusy : out std_logic;
pulseout : out std_logic
);
end component;
-----------------------------------------------------------------------------------
-- Begin
-----------------------------------------------------------------------------------
begin
-----------------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------------
p2p0: pulse2pulse
port map (
in_clk => clk_cmd,
out_clk => clk_reg,
rst => reset,
pulsein => register_wr,
inbusy => open,
pulseout => out_reg_val
);
p2p1: pulse2pulse
port map (
in_clk => clk_cmd,
out_clk => clk_reg,
rst => reset,
pulsein => register_rd,
inbusy => open,
pulseout => in_reg_req
);
p2p2: pulse2pulse
port map (
in_clk => clk_reg,
out_clk => clk_cmd,
rst => reset,
pulsein => in_reg_val,
inbusy => open,
pulseout => out_cmd_val_sig
);
p2p3: pulse2pulse
port map (
in_clk => clk_reg,
out_clk => clk_cmd ,
rst => reset,
pulsein => mbx_in_val,
inbusy => open,
pulseout => mbx_in_val_sig
);
-----------------------------------------------------------------------------------
-- Synchronous processes
-----------------------------------------------------------------------------------
in_reg_proc: process (reset, clk_cmd)
begin
if (reset = '1') then
in_reg_addr_sig <= (others => '0');
register_rd <= '0';
mbx_received <= '0';
out_cmd <= (others => '0');
out_cmd_val <= '0';
elsif (clk_cmd'event and clk_cmd = '1') then
--register the requested address when the address is in the modules range
if (in_cmd_val = '1' and in_cmd(63 downto 60) = CMD_RD and in_cmd(59 downto 32) >= start_addr and in_cmd(59 downto 32) <= stop_addr) then
in_reg_addr_sig <= in_cmd(59 downto 32)-start_addr;
end if;
--generate the read req pulse when the address is in the modules range
if (in_cmd_val = '1' and in_cmd(63 downto 60) = CMD_RD and in_cmd(59 downto 32) >= start_addr and in_cmd(59 downto 32) <= stop_addr) then
register_rd <= '1';
else
register_rd <= '0';
end if;
--mailbox has less priority then command acknowledge
--create the output packet
if (out_cmd_val_sig = '1' and mbx_in_val_sig = '1') then
mbx_received <= '1';
elsif( mbx_received = '1' and out_cmd_val_sig = '0') then
mbx_received <= '0';
end if;
if (out_cmd_val_sig = '1') then
out_cmd(31 downto 0) <= in_reg;
out_cmd(59 downto 32) <= in_reg_addr_sig+start_addr;
out_cmd(63 downto 60) <= CMD_RD_ACK;
elsif (mbx_in_val_sig = '1' or mbx_received = '1') then
out_cmd(31 downto 0) <= mbx_in_reg;
out_cmd(59 downto 32) <= start_addr;
out_cmd(63 downto 60) <= (others=>'0');
else
out_cmd(63 downto 0) <= (others=>'0');
end if;
if (out_cmd_val_sig = '1') then
out_cmd_val <= '1';
elsif (mbx_in_val_sig = '1' or mbx_received = '1') then
out_cmd_val <= '1';
else
out_cmd_val <= '0';
end if;
end if;
end process;
out_reg_proc: process(reset, clk_cmd)
begin
if (reset = '1') then
out_reg_addr <= (others => '0');
out_reg <= (others => '0');
register_wr <= '0';
elsif(clk_cmd'event and clk_cmd = '1') then
--register the requested address when the address is in the modules range
if (in_cmd_val = '1' and in_cmd(63 downto 60) = CMD_WR and in_cmd(59 downto 32) >= start_addr and in_cmd(59 downto 32) <= stop_addr) then
out_reg_addr <= in_cmd(59 downto 32) - start_addr;
out_reg <= in_cmd(31 downto 0);
end if;
--generate the write req pulse when the address is in the modules range
if (in_cmd_val = '1' and in_cmd(63 downto 60) = CMD_WR and in_cmd(59 downto 32) >= start_addr and in_cmd(59 downto 32) <= stop_addr) then
register_wr <= '1';
else
register_wr <= '0';
end if;
end if;
end process;
-----------------------------------------------------------------------------------
-- Asynchronous mapping
-----------------------------------------------------------------------------------
in_reg_addr <= in_reg_addr_sig;
-----------------------------------------------------------------------------------
-- End
-----------------------------------------------------------------------------------
end architecture arch_fmc150_stellar_cmd; |
-- VHDL de um contador de modulo 16
-- OBS: Para esse experimento so eh utilizada a contagem ate 11
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity contador_16_recepcao is
port(
clock : in std_logic;
enable : in std_logic;
zera : in std_logic;
conta : in std_logic;
contagem : out std_logic_vector(3 downto 0);
fim : out std_logic
);
end contador_16_recepcao;
architecture exemplo of contador_16_recepcao is
signal IQ: unsigned(3 downto 0);
begin
process (clock, conta, IQ, zera)
begin
if zera = '1' then
IQ <= (others => '0');
elsif clock'event and clock = '1' then
if (conta = '1' and enable = '1') then
IQ <= IQ + 1;
end if;
end if;
if IQ = 11 then
fim <= '1';
else
fim <= '0';
end if;
contagem <= std_logic_vector(IQ);
end process;
end exemplo;
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_ofdm_tx/TWDLMULT_SDNF1_3_block4.vhd
-- Created: 2018-02-27 13:25:18
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: TWDLMULT_SDNF1_3_block4
-- Source Path: hdl_ofdm_tx/ifft/TWDLMULT_SDNF1_3
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY TWDLMULT_SDNF1_3_block4 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
dout_10_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18_En13
dout_10_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18_En13
dout_12_re : IN std_logic_vector(17 DOWNTO 0); -- sfix18_En13
dout_12_im : IN std_logic_vector(17 DOWNTO 0); -- sfix18_En13
dout_2_vld : IN std_logic;
twdl_3_11_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_11_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_12_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_12_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_12_vld : IN std_logic;
softReset : IN std_logic;
twdlXdin_11_re : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin_11_im : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin_12_re : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin_12_im : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin_11_vld : OUT std_logic
);
END TWDLMULT_SDNF1_3_block4;
ARCHITECTURE rtl OF TWDLMULT_SDNF1_3_block4 IS
-- Component Declarations
COMPONENT Complex3Multiply_block6
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
din1_re_dly3 : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
din1_im_dly3 : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
din1_vld_dly3 : IN std_logic;
twdl_3_11_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_11_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
softReset : IN std_logic;
twdlXdin_11_re : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin_11_im : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin1_vld : OUT std_logic
);
END COMPONENT;
COMPONENT Complex3Multiply_block7
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
din2_re_dly3 : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
din2_im_dly3 : IN std_logic_vector(18 DOWNTO 0); -- sfix19_En13
di2_vld_dly3 : IN std_logic;
twdl_3_12_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
twdl_3_12_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
softReset : IN std_logic;
twdlXdin_12_re : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin_12_im : OUT std_logic_vector(18 DOWNTO 0); -- sfix19_En13
twdlXdin2_vld : OUT std_logic
);
END COMPONENT;
-- Component Configuration Statements
FOR ALL : Complex3Multiply_block6
USE ENTITY work.Complex3Multiply_block6(rtl);
FOR ALL : Complex3Multiply_block7
USE ENTITY work.Complex3Multiply_block7(rtl);
-- Signals
SIGNAL dout_10_re_signed : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL din_re : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_re_dly1 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_re_dly2 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL dout_10_im_signed : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL din_im : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_im_dly1 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_im_dly2 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_re_dly3 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_im_dly3 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din1_vld_dly1 : std_logic;
SIGNAL din1_vld_dly2 : std_logic;
SIGNAL din1_vld_dly3 : std_logic;
SIGNAL twdlXdin_11_re_tmp : std_logic_vector(18 DOWNTO 0); -- ufix19
SIGNAL twdlXdin_11_im_tmp : std_logic_vector(18 DOWNTO 0); -- ufix19
SIGNAL twdlXdin1_vld : std_logic;
SIGNAL dout_12_re_signed : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL din_re_1 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din2_re_dly1 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din2_re_dly2 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL dout_12_im_signed : signed(17 DOWNTO 0); -- sfix18_En13
SIGNAL din_im_1 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din2_im_dly1 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din2_im_dly2 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din2_re_dly3 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL din2_im_dly3 : signed(18 DOWNTO 0); -- sfix19_En13
SIGNAL di2_vld_dly1 : std_logic;
SIGNAL di2_vld_dly2 : std_logic;
SIGNAL di2_vld_dly3 : std_logic;
SIGNAL twdlXdin_12_re_tmp : std_logic_vector(18 DOWNTO 0); -- ufix19
SIGNAL twdlXdin_12_im_tmp : std_logic_vector(18 DOWNTO 0); -- ufix19
BEGIN
u_MUL3_1 : Complex3Multiply_block6
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
din1_re_dly3 => std_logic_vector(din1_re_dly3), -- sfix19_En13
din1_im_dly3 => std_logic_vector(din1_im_dly3), -- sfix19_En13
din1_vld_dly3 => din1_vld_dly3,
twdl_3_11_re => twdl_3_11_re, -- sfix16_En14
twdl_3_11_im => twdl_3_11_im, -- sfix16_En14
softReset => softReset,
twdlXdin_11_re => twdlXdin_11_re_tmp, -- sfix19_En13
twdlXdin_11_im => twdlXdin_11_im_tmp, -- sfix19_En13
twdlXdin1_vld => twdlXdin1_vld
);
u_MUL3_2 : Complex3Multiply_block7
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
din2_re_dly3 => std_logic_vector(din2_re_dly3), -- sfix19_En13
din2_im_dly3 => std_logic_vector(din2_im_dly3), -- sfix19_En13
di2_vld_dly3 => di2_vld_dly3,
twdl_3_12_re => twdl_3_12_re, -- sfix16_En14
twdl_3_12_im => twdl_3_12_im, -- sfix16_En14
softReset => softReset,
twdlXdin_12_re => twdlXdin_12_re_tmp, -- sfix19_En13
twdlXdin_12_im => twdlXdin_12_im_tmp, -- sfix19_En13
twdlXdin2_vld => twdlXdin_11_vld
);
dout_10_re_signed <= signed(dout_10_re);
din_re <= resize(dout_10_re_signed, 19);
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly1 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_re_dly1 <= din_re;
END IF;
END IF;
END PROCESS intdelay_process;
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly2 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_re_dly2 <= din1_re_dly1;
END IF;
END IF;
END PROCESS intdelay_1_process;
dout_10_im_signed <= signed(dout_10_im);
din_im <= resize(dout_10_im_signed, 19);
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly1 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_im_dly1 <= din_im;
END IF;
END IF;
END PROCESS intdelay_2_process;
intdelay_3_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly2 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_im_dly2 <= din1_im_dly1;
END IF;
END IF;
END PROCESS intdelay_3_process;
intdelay_4_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_re_dly3 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_re_dly3 <= din1_re_dly2;
END IF;
END IF;
END PROCESS intdelay_4_process;
intdelay_5_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_im_dly3 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_im_dly3 <= din1_im_dly2;
END IF;
END IF;
END PROCESS intdelay_5_process;
intdelay_6_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_vld_dly1 <= dout_2_vld;
END IF;
END IF;
END PROCESS intdelay_6_process;
intdelay_7_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_vld_dly2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_vld_dly2 <= din1_vld_dly1;
END IF;
END IF;
END PROCESS intdelay_7_process;
intdelay_8_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din1_vld_dly3 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din1_vld_dly3 <= din1_vld_dly2;
END IF;
END IF;
END PROCESS intdelay_8_process;
dout_12_re_signed <= signed(dout_12_re);
din_re_1 <= resize(dout_12_re_signed, 19);
intdelay_9_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_re_dly1 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din2_re_dly1 <= din_re_1;
END IF;
END IF;
END PROCESS intdelay_9_process;
intdelay_10_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_re_dly2 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din2_re_dly2 <= din2_re_dly1;
END IF;
END IF;
END PROCESS intdelay_10_process;
dout_12_im_signed <= signed(dout_12_im);
din_im_1 <= resize(dout_12_im_signed, 19);
intdelay_11_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_im_dly1 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din2_im_dly1 <= din_im_1;
END IF;
END IF;
END PROCESS intdelay_11_process;
intdelay_12_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_im_dly2 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din2_im_dly2 <= din2_im_dly1;
END IF;
END IF;
END PROCESS intdelay_12_process;
intdelay_13_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_re_dly3 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din2_re_dly3 <= din2_re_dly2;
END IF;
END IF;
END PROCESS intdelay_13_process;
intdelay_14_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
din2_im_dly3 <= to_signed(16#00000#, 19);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
din2_im_dly3 <= din2_im_dly2;
END IF;
END IF;
END PROCESS intdelay_14_process;
intdelay_15_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
di2_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
di2_vld_dly1 <= dout_2_vld;
END IF;
END IF;
END PROCESS intdelay_15_process;
intdelay_16_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
di2_vld_dly2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
di2_vld_dly2 <= di2_vld_dly1;
END IF;
END IF;
END PROCESS intdelay_16_process;
intdelay_17_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
di2_vld_dly3 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
di2_vld_dly3 <= di2_vld_dly2;
END IF;
END IF;
END PROCESS intdelay_17_process;
twdlXdin_11_re <= twdlXdin_11_re_tmp;
twdlXdin_11_im <= twdlXdin_11_im_tmp;
twdlXdin_12_re <= twdlXdin_12_re_tmp;
twdlXdin_12_im <= twdlXdin_12_im_tmp;
END rtl;
|
entity bounds37 is
end entity;
architecture test of bounds37 is
signal x : integer_vector(4 downto 0);
signal y : integer_vector(1 downto 0);
signal z : integer_vector(2 downto 0);
signal i0, i1 : integer;
begin
main: process is
begin
x <= (1, 2, 3, 4, 5);
wait for 1 ns;
i1 <= 1;
wait for 1 ns;
(i1, y) <= x(4 downto i1); -- Error
wait;
end process;
end architecture;
|
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: ClocksPLL.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 16.0.0 Build 211 04/27/2016 SJ Lite Edition
-- ************************************************************
--Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, the Altera Quartus Prime License Agreement,
--the Altera MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Altera and sold by Altera or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY ClocksPLL IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END ClocksPLL;
ARCHITECTURE SYN OF clockspll IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire2_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC ;
SIGNAL sub_wire7 : STD_LOGIC ;
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
areset : IN STD_LOGIC ;
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
locked : OUT STD_LOGIC
);
END COMPONENT;
BEGIN
sub_wire2_bv(0 DOWNTO 0) <= "0";
sub_wire2 <= To_stdlogicvector(sub_wire2_bv);
sub_wire0 <= inclk0;
sub_wire1 <= sub_wire2(0 DOWNTO 0) & sub_wire0;
sub_wire6 <= sub_wire3(2);
sub_wire5 <= sub_wire3(1);
sub_wire4 <= sub_wire3(0);
c0 <= sub_wire4;
c1 <= sub_wire5;
c2 <= sub_wire6;
locked <= sub_wire7;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 10,
clk0_duty_cycle => 50,
clk0_multiply_by => 1,
clk0_phase_shift => "0",
clk1_divide_by => 1,
clk1_duty_cycle => 50,
clk1_multiply_by => 6,
clk1_phase_shift => "0",
clk2_divide_by => 3125,
clk2_duty_cycle => 50,
clk2_multiply_by => 8,
clk2_phase_shift => "1953125",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone IV E",
lpm_hint => "CBX_MODULE_PREFIX=ClocksPLL",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_USED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "ON",
width_clock => 5
)
PORT MAP (
areset => areset,
inclk => sub_wire1,
clk => sub_wire3,
locked => sub_wire7
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "50000"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "5.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "300.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "0.128000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "23"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "5.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "300.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "0.12800000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "90.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "ClocksPLL.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "10"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "6"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "3125"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "8"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "1953125"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL ClocksPLL.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ClocksPLL.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ClocksPLL.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ClocksPLL.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ClocksPLL.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL ClocksPLL_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mips_soc is
port (
-- CLOCK
CPU_CLK : in std_logic; -- 32.5 Mhz
VGA_CLK : in std_logic; -- VGA_CLK 25Mhz
CPU_RESET : in std_logic;
-- VGA
VGA_R : OUT STD_LOGIC_VECTOR(3 downto 0);
VGA_G : OUT STD_LOGIC_VECTOR(3 downto 0);
VGA_B : OUT STD_LOGIC_VECTOR(3 downto 0);
VGA_VSYNC : buffer std_logic;
VGA_HSYNC : out std_logic;
-- SRAM
MEM_A : out std_logic_vector(31 downto 2);
MEM_DI : out std_logic_vector(31 downto 0);
MEM_DO : in std_logic_vector(31 downto 0);
MEM_MASK : out std_logic_vector(3 downto 0);
MEM_WR : out std_logic;
MEM_REQ : out std_logic;
MEM_BUSY : in std_logic;
-- Keyboard
KEYB_DATA : in std_logic_vector(7 downto 0);
-- Sound
MIPS_BEEPER : out std_logic;
-- SD Card
SD_MOSI : out std_logic;
SD_MISO : in std_logic;
SD_SCK : out std_logic;
SD_CS : out std_logic;
-- FDC Ports
VG93_CLK : in std_logic;
VG93_nCLR : in std_logic;
VG93_IRQ : out std_logic;
VG93_DRQ : out std_logic;
VG93_A : in std_logic_vector(1 downto 0);
VG93_D_IN : in std_logic_vector(7 downto 0);
VG93_D_OUT : out std_logic_vector(7 downto 0);
VG93_nCS : in std_logic;
VG93_nRD : in std_logic;
VG93_nWR : in std_logic;
VG93_nDDEN : in std_logic;
VG93_HRDY : in std_logic;
FDC_DRIVE : in std_logic_vector(1 downto 0);
FDC_nSIDE : in std_logic;
TST : out std_logic
);
end mips_soc;
architecture mips_soc_arch of mips_soc is
signal CPU_A : std_logic_vector(31 downto 0);
signal CPU_DI : std_logic_vector(31 downto 0);
signal CPU_DO : std_logic_vector(31 downto 0);
signal CPU_SEL : std_logic_vector(3 downto 0);
signal CPU_WE : std_logic;
signal CPU_INT : std_logic;
signal CPU_A_L : std_logic_vector(31 downto 0);
-- VGA
signal POS_X : unsigned(6 downto 0);
signal POS_Y : unsigned(4 downto 0);
signal VA : std_logic_vector(11 downto 0);
signal VDI : std_logic_vector(7 downto 0);
signal VDO : std_logic_vector(15 downto 0);
signal VWR : std_logic;
signal VATTR : std_logic_vector(7 downto 0);
signal VRG : std_logic_vector(7 downto 0);
-- HW timer: Frame counter
signal VGA_FRAMES : std_logic_vector(31 downto 0);
signal FR_LOCK : std_logic;
-- HW timer: CPU CLK counter
signal CPU_CLK_COUNTER : std_logic_vector(31 downto 0);
type STATES is (ST_IDLE, ST_INC, ST_SET_FRAMES, ST_SET_CC_COUNTER);
signal STATE : STATES;
-- SD Card
signal counter : unsigned(4 downto 0);
-- Shift register has an extra bit because we write on the
-- falling edge and read on the rising edge
signal shift_reg : std_logic_vector(8 downto 0);
signal in_reg : std_logic_vector(7 downto 0);
signal SD_BUSY : std_logic;
-- VG93 Reg
signal VG93_STATUS : std_logic_vector(7 downto 0);
signal VG93_TRACK_R : std_logic_vector(7 downto 0);
signal VG93_SECTOR_R : std_logic_vector(7 downto 0);
signal VG93_DATA_R : std_logic_vector(7 downto 0);
signal VG93_CONTROL : std_logic_vector(7 downto 0);
signal VG93_TRACK : std_logic_vector(7 downto 0);
signal VG93_SECTOR : std_logic_vector(7 downto 0);
signal VG93_DATA : std_logic_vector(7 downto 0);
signal VG93_CONTROL_READY_M : std_logic;
signal VG93_DATA_READY_M : std_logic;
signal VG93_CONTROL_READY : std_logic;
signal VG93_DATA_READY : std_logic;
signal VG93_IRQ_B : std_logic := '0';
signal VG93_DRQ_B : std_logic := '0';
signal SET_IRQ_DRQ : std_logic := '0';
signal RES_VG93_IRQ : std_logic;
signal RES_VG93_DRQ : std_logic;
signal RES_CR : std_logic := '0';
signal RES_DR : std_logic := '0';
signal idx_cnt : std_logic_vector(22 downto 0);
signal FDC_IDX : std_logic;
signal VG93_TYPE_1_CMD_SET : std_logic;
signal VG93_TYPE_1_CMD : std_logic;
begin
cpu: entity work.mlite_cpu
port map (
clk => CPU_CLK,
reset_in => CPU_RESET,
intr_in => CPU_INT,
mem_address => CPU_A,
mem_data_w => CPU_DO,
mem_data_r => CPU_DI,
mem_byte_we => CPU_SEL,
mem_pause => MEM_BUSY or SD_BUSY
);
u_MIPS_VIDEO : entity work.mips_video
port map(
CLK => CPU_CLK,
VGA_CLK => VGA_CLK,
RESET => CPU_RESET,
VA => VA,
VDI => VDI,
VDO => VDO,
VWR => VWR,
VATTR => VATTR,
VGA_R => VGA_R,
VGA_G => VGA_G,
VGA_B => VGA_B,
VGA_HSYNC => VGA_HSYNC,
VGA_VSYNC => VGA_VSYNC );
CPU_WE <= CPU_SEL(0) or CPU_SEL(1) or CPU_SEL(2) or CPU_SEL(3);
CPU_DI <= x"000000" & VRG when CPU_A_L = x"80000000" else
x"000000" & VATTR when CPU_A_L = x"80000010" else
x"0000" & VDO when CPU_A_L = x"80000020" or CPU_A_L = x"80000030" else
x"000000" & '0' & std_logic_vector(POS_X) when CPU_A_L = x"80000040" else
x"000000" & "000" & std_logic_vector(POS_Y) when CPU_A_L = x"80000050" else
VGA_FRAMES when CPU_A_L = x"80000060" else
CPU_CLK_COUNTER when CPU_A_L = x"80000064" else
x"000000" & in_reg when CPU_A_L = x"80000070" else
x"000000" & KEYB_DATA when CPU_A_L = x"80000090" else
x"000000" & "1" & VG93_nDDEN & "1" & FDC_nSIDE & VG93_HRDY & VG93_nCLR & FDC_DRIVE
when CPU_A_L = x"80000E40" else
x"000000" & VG93_CONTROL when CPU_A_L = x"80000E00" else
x"000000" & VG93_TRACK when CPU_A_L = x"80000E10" else
x"000000" & VG93_SECTOR when CPU_A_L = x"80000E20" else
x"000000" & VG93_DATA when CPU_A_L = x"80000E30" else
x"0000000" & "00" & VG93_DATA_READY & VG93_CONTROL_READY
when CPU_A_L = x"80000E50" else
MEM_DO;
VA <= std_logic_vector(POS_Y) & std_logic_vector(POS_X);
SD_CS <= '1' when CPU_RESET = '1' else
CPU_DO(0) when rising_edge(CPU_CLK) and MEM_BUSY = '0' and CPU_RESET = '0' and CPU_WE = '1' and CPU_A = x"80000080";
MIPS_BEEPER <= CPU_DO(0) when rising_edge(CPU_CLK) and MEM_BUSY = '0' and CPU_RESET = '0' and CPU_WE = '1' and CPU_A = x"80000FE0";
-- Main State Machine
process(CPU_CLK)
begin
if rising_edge(CPU_CLK) then
if CPU_RESET = '1' then
MEM_REQ <= '0';
POS_X <= "0000000";
POS_Y <= "00000";
STATE <= ST_IDLE;
VWR <= '0';
VRG <= "00000001";
FR_LOCK <= '0';
CPU_INT <= '0';
else
MEM_REQ <= '0';
MEM_WR <= '0';
VWR <= '0';
if VGA_VSYNC = '0' then
FR_LOCK <= '0';
end if;
case STATE is
when ST_INC =>
POS_X <= POS_X + 1;
if POS_X = 79 then
POS_X <= "0000000";
POS_Y <= POS_Y + 1;
if POS_Y = 29 then
POS_Y <= "00000";
end if;
end if;
STATE <= ST_IDLE;
when ST_SET_FRAMES =>
STATE <= ST_IDLE;
when ST_SET_CC_COUNTER =>
STATE <= ST_IDLE;
when OTHERS =>
STATE <= ST_IDLE;
end case;
if FR_LOCK = '0' and VGA_VSYNC = '1' and STATE /= ST_SET_FRAMES then
FR_LOCK <= '1';
VGA_FRAMES <= VGA_FRAMES + 1;
CPU_INT <= '1';
STATE <= ST_IDLE;
end if;
if STATE /= ST_SET_CC_COUNTER then
CPU_CLK_COUNTER <= CPU_CLK_COUNTER +1;
end if;
if MEM_BUSY = '0' and CPU_RESET = '0' then
CPU_A_L <= CPU_A;
if (CPU_A = x"80000020" or CPU_A = x"80000030") and VRG(0) = '1' then
STATE <= ST_INC;
end if;
-- Plasma ISR Vector
if CPU_A = x"0000003C" then
CPU_INT <= '0';
end if;
if CPU_A(31) = '1' and CPU_WE = '1' then
case CPU_A is
when x"80000000" => -- Video Mode
VRG <= CPU_DO(7 downto 0);
when x"80000010" => -- Video Set Attr
VATTR <= CPU_DO(7 downto 0);
if VRG(2) = '1' then
STATE <= ST_INC;
end if;
when x"80000020" => -- Video Write Char
VDI <= CPU_DO(7 downto 0);
VWR <= '1';
when x"80000030" => -- Video Write Char & Attr
VATTR <= CPU_DO(15 downto 8);
VDI <= CPU_DO(7 downto 0);
VWR <= '1';
when x"80000040" => -- Video Set X Pos
POS_X <= unsigned(CPU_DO(6 downto 0));
when x"80000050" => -- Video Set Y Pos
POS_Y <= unsigned(CPU_DO(4 downto 0));
when x"80000060" =>
VGA_FRAMES <= CPU_DO;
STATE <= ST_SET_FRAMES;
when x"80000064" =>
CPU_CLK_COUNTER <= CPU_DO;
STATE <= ST_SET_CC_COUNTER;
when OTHERS =>
STATE <= ST_IDLE;
end case;
-- CPU Mem Access
elsif CPU_A(31) = '0' then
MEM_A <= '0' & CPU_A(30 downto 2);
MEM_DI <= CPU_DO;
MEM_WR <= CPU_WE;
MEM_MASK <= CPU_SEL;
MEM_REQ <= '1';
end if;
end if;
end if;
end if;
end process;
-- SD Card Serializer
-- SD CLK = CPU_CLK / 2
-- MMC/SDC can work at the clock frequency upto 20/25 MHz.
process(CPU_CLK)
begin
if rising_edge(CPU_CLK) then
if CPU_RESET = '1' then
shift_reg <= (others => '1');
in_reg <= (others => '1');
counter <= "10000"; -- Idle
else
case counter is
when "10000" =>
if MEM_BUSY = '0' and CPU_A = x"80000070" then
if CPU_WE = '0' then
shift_reg <= (others => '1');
else
shift_reg <= CPU_DO(7 downto 0) & '1';
end if;
counter <= "00000";
end if;
when "01111" =>
in_reg <= shift_reg(7 downto 0);
counter <= "10000";
when OTHERS =>
counter <= counter + 1;
if counter(0) = '0' then
shift_reg(0) <= SD_MISO;
else
shift_reg <= shift_reg(7 downto 0) & '1';
end if;
end case;
end if;
end if;
end process;
SD_BUSY <= not counter(4);
TST <= counter(0);
SD_SCK <= counter(0);
SD_MOSI <= shift_reg(8);
-- VG93 Reg Read
VG93_D_OUT <= VG93_STATUS(7 downto 2) & FDC_IDX & VG93_STATUS(0)
when VG93_nCS = '0' and VG93_nRD = '0' and VG93_A = "00" and VG93_TYPE_1_CMD = '1' else
VG93_STATUS when VG93_nCS = '0' and VG93_nRD = '0' and VG93_A = "00" else
VG93_TRACK_R when VG93_nCS = '0' and VG93_nRD = '0' and VG93_A = "01" else
VG93_SECTOR_R when VG93_nCS = '0' and VG93_nRD = '0' and VG93_A = "10" else
VG93_DATA_R when VG93_nCS = '0' and VG93_nRD = '0' and VG93_A = "11" else
"11111111";
-- VG93 Status set to BUSY when Command received
VG93_STATUS <= CPU_DO(7 downto 0) when rising_edge(CPU_CLK) and MEM_BUSY = '0' and CPU_RESET = '0' and CPU_WE = '1' and CPU_A = x"80000E00" else
"00000001" when VG93_CONTROL_READY_M = '1';
VG93_TRACK_R <= CPU_DO(7 downto 0) when rising_edge(CPU_CLK) and MEM_BUSY = '0' and CPU_RESET = '0' and CPU_WE = '1' and CPU_A = x"80000E10";
VG93_SECTOR_R <= CPU_DO(7 downto 0) when rising_edge(CPU_CLK) and MEM_BUSY = '0' and CPU_RESET = '0' and CPU_WE = '1' and CPU_A = x"80000E20";
VG93_DATA_R <= CPU_DO(7 downto 0) when rising_edge(CPU_CLK) and MEM_BUSY = '0' and CPU_RESET = '0' and CPU_WE = '1' and CPU_A = x"80000E30";
-- VG93 Reg Write
VG93_CONTROL <= VG93_D_IN when VG93_nCS = '0' and VG93_A = "00" and VG93_nWR = '0' and falling_edge(VG93_CLK);
VG93_TRACK <= VG93_D_IN when VG93_nCS = '0' and VG93_A = "01" and VG93_nWR = '0' and falling_edge(VG93_CLK);
VG93_SECTOR <= VG93_D_IN when VG93_nCS = '0' and VG93_A = "10" and VG93_nWR = '0' and falling_edge(VG93_CLK);
VG93_DATA <= VG93_D_IN when VG93_nCS = '0' and VG93_A = "11" and VG93_nWR = '0' and falling_edge(VG93_CLK);
-- Buffers. IRQ and DRQ are send on VG93 status write
VG93_IRQ_B <= CPU_DO(1) when rising_edge(CPU_CLK) and MEM_BUSY = '0' and CPU_RESET = '0' and CPU_WE = '1' and CPU_A = x"80000E40";
VG93_DRQ_B <= CPU_DO(0) when rising_edge(CPU_CLK) and MEM_BUSY = '0' and CPU_RESET = '0' and CPU_WE = '1' and CPU_A = x"80000E40";
-- One shoot
SET_IRQ_DRQ <= '1' when rising_edge(CPU_CLK) and MEM_BUSY = '0' and CPU_RESET = '0' and CPU_WE = '1' and CPU_A = x"80000E00" else '0';
-- One shoot
RES_VG93_IRQ <= '1' when VG93_nCS = '0' and VG93_A = "00" and rising_edge(CPU_CLK) else '0';
RES_VG93_DRQ <= '1' when VG93_nCS = '0' and VG93_A = "11" and rising_edge(CPU_CLK) else '0';
-- IRQ is cleard if VG93 Status Reg read or VG92 Control Reg written
IRQ_TR: entity work.D_Flip_Flop PORT MAP(
rst => RES_VG93_IRQ,
pre => '0',
ce => SET_IRQ_DRQ,
d => VG93_IRQ_B,
q => VG93_IRQ
);
-- DRQ is cleared if VG93 Data Reg accessed
DRQ_TR: entity work.D_Flip_Flop PORT MAP(
rst => RES_VG93_DRQ,
pre => '0',
ce => SET_IRQ_DRQ,
d => VG93_DRQ_B,
q => VG93_DRQ
);
CR_TR: entity work.D_Flip_Flop PORT MAP(
rst => CPU_RESET,
pre => VG93_CONTROL_READY_M,
ce => RES_CR,
d => '0',
q => VG93_CONTROL_READY
);
-- One Shoot
VG93_CONTROL_READY_M <= '1' when VG93_nCS = '0' and VG93_A = "00" and VG93_nWR = '0' and falling_edge(VG93_CLK) else '0';
RES_CR <= '1' when rising_edge(CPU_CLK) and MEM_BUSY = '0' and CPU_RESET = '0' and CPU_WE = '0' and CPU_A = x"80000E00" else '0';
DR_TR: entity work.D_Flip_Flop PORT MAP(
rst => CPU_RESET,
pre => VG93_DATA_READY_M,
ce => RES_DR,
d => '0',
q => VG93_DATA_READY
);
VG93_DATA_READY_M <= '1' when VG93_A = "11" and VG93_nCS = '0' and falling_edge(VG93_CLK) else '0';
RES_DR <= '1' when rising_edge(CPU_CLK) and MEM_BUSY = '0' and CPU_RESET = '0' and CPU_A = x"80000E30" else '0';
IDX_TR: entity work.D_Flip_Flop PORT MAP(
rst => CPU_RESET,
pre => VG93_TYPE_1_CMD_SET,
ce => VG93_CONTROL_READY_M,
d => '0',
q => VG93_TYPE_1_CMD
);
VG93_TYPE_1_CMD_SET <= '1' when rising_edge(CPU_CLK) and MEM_BUSY = '0' and CPU_RESET = '0' and CPU_WE = '1' and CPU_A = x"80000E10" else '0';
-- FDC Index pulse generator
-- 5 Hz for 300 RPM, Pulse width 8ms
process (CPU_CLK)
begin
if rising_edge(CPU_CLK) then
idx_cnt <= idx_cnt + 1;
if idx_cnt = 260000 then
FDC_IDX <= '0';
end if;
if idx_cnt = 6132076 then
idx_cnt <= (others => '0');
FDC_IDX <= '1';
end if;
end if;
end process;
end mips_soc_arch; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1894.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01894ent IS
END c07s01b00x00p08n01i01894ent;
ARCHITECTURE c07s01b00x00p08n01i01894arch OF c07s01b00x00p08n01i01894ent IS
type small_int is range 0 to 7;
type cmd_bus is array (small_int range <>) of small_int;
signal ibus : cmd_bus(small_int);
signal s_int : small_int;
BEGIN
blk : block(s_int = 0)
begin
end block blk;
TESTING : PROCESS
BEGIN
s_int <= ibus'right(small_int(blk)) after 5 ns;
-- block labels illegal here
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01894 - Block labels are not permitted as primaries in a type conversion expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01894arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1894.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01894ent IS
END c07s01b00x00p08n01i01894ent;
ARCHITECTURE c07s01b00x00p08n01i01894arch OF c07s01b00x00p08n01i01894ent IS
type small_int is range 0 to 7;
type cmd_bus is array (small_int range <>) of small_int;
signal ibus : cmd_bus(small_int);
signal s_int : small_int;
BEGIN
blk : block(s_int = 0)
begin
end block blk;
TESTING : PROCESS
BEGIN
s_int <= ibus'right(small_int(blk)) after 5 ns;
-- block labels illegal here
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01894 - Block labels are not permitted as primaries in a type conversion expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01894arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1894.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01894ent IS
END c07s01b00x00p08n01i01894ent;
ARCHITECTURE c07s01b00x00p08n01i01894arch OF c07s01b00x00p08n01i01894ent IS
type small_int is range 0 to 7;
type cmd_bus is array (small_int range <>) of small_int;
signal ibus : cmd_bus(small_int);
signal s_int : small_int;
BEGIN
blk : block(s_int = 0)
begin
end block blk;
TESTING : PROCESS
BEGIN
s_int <= ibus'right(small_int(blk)) after 5 ns;
-- block labels illegal here
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01894 - Block labels are not permitted as primaries in a type conversion expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01894arch;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: i2c
-- File: i2c.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: I2C interface package
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
package i2c is
type i2c_in_type is record
scl : std_ulogic;
sda : std_ulogic;
end record;
type i2c_out_type is record
scl : std_ulogic;
scloen : std_ulogic;
sda : std_ulogic;
sdaoen : std_ulogic;
enable : std_ulogic;
end record;
-- AMBA wrapper for OC I2C-master
component i2cmst
generic (
pindex : integer;
paddr : integer;
pmask : integer;
pirq : integer;
oepol : integer range 0 to 1 := 0;
filter : integer range 2 to 512 := 2;
dynfilt : integer range 0 to 1 := 0
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
i2ci : in i2c_in_type;
i2co : out i2c_out_type
);
end component;
component i2cmst_gen
generic (
oepol : integer range 0 to 1 := 0;
filter : integer range 2 to 512 := 2;
dynfilt : integer range 0 to 1 := 0
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
psel : in std_ulogic;
penable : in std_ulogic;
paddr : in std_logic_vector(31 downto 0);
pwrite : in std_ulogic;
pwdata : in std_logic_vector(31 downto 0);
prdata : out std_logic_vector(31 downto 0);
irq : out std_logic;
i2ci_scl : in std_ulogic;
i2ci_sda : in std_ulogic;
i2co_scl : out std_ulogic;
i2co_scloen : out std_ulogic;
i2co_sda : out std_ulogic;
i2co_sdaoen : out std_ulogic;
i2co_enable : out std_ulogic
);
end component;
-- I2C slave
component i2cslv
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
hardaddr : integer range 0 to 1 := 0;
tenbit : integer range 0 to 1 := 0;
i2caddr : integer range 0 to 1023 := 0;
oepol : integer range 0 to 1 := 0;
filter : integer range 2 to 512 := 2
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
i2ci : in i2c_in_type;
i2co : out i2c_out_type
);
end component;
-- I2C to AHB bridge
type i2c2ahb_in_type is record
haddr : std_logic_vector(31 downto 0);
hmask : std_logic_vector(31 downto 0);
slvaddr : std_logic_vector(6 downto 0);
cfgaddr : std_logic_vector(6 downto 0);
en : std_ulogic;
end record;
type i2c2ahb_out_type is record
dma : std_ulogic;
wr : std_ulogic;
prot : std_ulogic;
end record;
component i2c2ahb
generic (
-- AHB Configuration
hindex : integer := 0;
--
ahbaddrh : integer := 0;
ahbaddrl : integer := 0;
ahbmaskh : integer := 0;
ahbmaskl : integer := 0;
-- I2C configuration
i2cslvaddr : integer range 0 to 127 := 0;
i2ccfgaddr : integer range 0 to 127 := 0;
oepol : integer range 0 to 1 := 0;
--
filter : integer range 2 to 512 := 2
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
-- I2C signals
i2ci : in i2c_in_type;
i2co : out i2c_out_type
);
end component;
component i2c2ahb_apb
generic (
-- AHB Configuration
hindex : integer := 0;
--
ahbaddrh : integer := 0;
ahbaddrl : integer := 0;
ahbmaskh : integer := 0;
ahbmaskl : integer := 0;
resen : integer := 0;
-- APB configuration
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
-- I2C configuration
i2cslvaddr : integer range 0 to 127 := 0;
i2ccfgaddr : integer range 0 to 127 := 0;
oepol : integer range 0 to 1 := 0;
--
filter : integer range 2 to 512 := 2
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
--
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
-- I2C signals
i2ci : in i2c_in_type;
i2co : out i2c_out_type
);
end component;
component i2c2ahbx
generic (
-- AHB configuration
hindex : integer := 0;
oepol : integer range 0 to 1 := 0;
filter : integer range 2 to 512 := 2
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
-- I2C signals
i2ci : in i2c_in_type;
i2co : out i2c_out_type;
--
i2c2ahbi : in i2c2ahb_in_type;
i2c2ahbo : out i2c2ahb_out_type
);
end component;
component i2c2ahb_gen
generic (
ahbaddrh : integer := 0;
ahbaddrl : integer := 0;
ahbmaskh : integer := 0;
ahbmaskl : integer := 0;
-- I2C configuration
i2cslvaddr : integer range 0 to 127 := 0;
i2ccfgaddr : integer range 0 to 127 := 0;
oepol : integer range 0 to 1 := 0;
--
filter : integer range 2 to 512 := 2
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi_hgrant : in std_ulogic;
ahbi_hready : in std_ulogic;
ahbi_hresp : in std_logic_vector(1 downto 0);
ahbi_hrdata : in std_logic_vector(31 downto 0);
--ahbo : out ahb_mst_out_type;
ahbo_hbusreq : out std_ulogic;
ahbo_hlock : out std_ulogic;
ahbo_htrans : out std_logic_vector(1 downto 0);
ahbo_haddr : out std_logic_vector(31 downto 0);
ahbo_hwrite : out std_ulogic;
ahbo_hsize : out std_logic_vector(2 downto 0);
ahbo_hburst : out std_logic_vector(2 downto 0);
ahbo_hprot : out std_logic_vector(3 downto 0);
ahbo_hwdata : out std_logic_vector(31 downto 0);
-- I2C signals
--i2ci : in i2c_in_type;
i2ci_scl : in std_ulogic;
i2ci_sda : in std_ulogic;
--i2co : out i2c_out_type
i2co_scl : out std_ulogic;
i2co_scloen : out std_ulogic;
i2co_sda : out std_ulogic;
i2co_sdaoen : out std_ulogic;
i2co_enable : out std_ulogic
);
end component;
component i2c2ahb_apb_gen
generic (
ahbaddrh : integer := 0;
ahbaddrl : integer := 0;
ahbmaskh : integer := 0;
ahbmaskl : integer := 0;
resen : integer := 0;
-- APB configuration
pindex : integer := 0; -- slave bus index
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
-- I2C configuration
i2cslvaddr : integer range 0 to 127 := 0;
i2ccfgaddr : integer range 0 to 127 := 0;
oepol : integer range 0 to 1 := 0;
--
filter : integer range 2 to 512 := 2
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
--ahbi : in ahb_mst_in_type;
ahbi_hgrant : in std_ulogic;
ahbi_hready : in std_ulogic;
ahbi_hresp : in std_logic_vector(1 downto 0);
ahbi_hrdata : in std_logic_vector(31 downto 0);
--ahbo : out ahb_mst_out_type;
ahbo_hbusreq : out std_ulogic;
ahbo_hlock : out std_ulogic;
ahbo_htrans : out std_logic_vector(1 downto 0);
ahbo_haddr : out std_logic_vector(31 downto 0);
ahbo_hwrite : out std_ulogic;
ahbo_hsize : out std_logic_vector(2 downto 0);
ahbo_hburst : out std_logic_vector(2 downto 0);
ahbo_hprot : out std_logic_vector(3 downto 0);
ahbo_hwdata : out std_logic_vector(31 downto 0);
-- APB slave interface
apbi_psel : in std_ulogic;
apbi_penable : in std_ulogic;
apbi_paddr : in std_logic_vector(31 downto 0);
apbi_pwrite : in std_ulogic;
apbi_pwdata : in std_logic_vector(31 downto 0);
apbo_prdata : out std_logic_vector(31 downto 0);
apbo_irq : out std_logic;
-- I2C signals
--i2ci : in i2c_in_type;
i2ci_scl : in std_ulogic;
i2ci_sda : in std_ulogic;
--i2co : out i2c_out_type
i2co_scl : out std_ulogic;
i2co_scloen : out std_ulogic;
i2co_sda : out std_ulogic;
i2co_sdaoen : out std_ulogic;
i2co_enable : out std_ulogic
);
end component;
end;
|
--Practica4 de Diseño Automatico de Sistemas
--Cronometro.
--Fichero Principal.
--Desarrollada por Héctor Gutiérrez Palancarejo.
library ieee;
use ieee.std_logic_1164.all;
entity cronometer is
port(
clk : in std_logic;
rst : in std_logic;
sel : in std_logic;
puesta_zero : in std_logic;
start_stop : in std_logic;
left_segs : out std_logic_vector (6 downto 0);
right_segs : out std_logic_vector (6 downto 0);
decimal_segs : out std_logic_vector (6 downto 0);
point : out std_logic_vector (2 downto 0)
);
end cronometer;
architecture rtl of cronometer is
component contador is
port(
clk : in std_logic;
rst : in std_logic;
puesta_zero : in std_logic;
start_stop : in std_logic;
cmp : in std_logic_vector (3 downto 0);
display : out std_logic_vector (3 downto 0);
fin : out std_logic
);
end component;
component clk10hz is
port(
clk : in std_logic;
rst : in std_logic;
clk_out : out std_logic
);
end component;
component switch2display7seg is
port(
a : in std_logic_vector(3 downto 0);
b : out std_logic_vector(6 downto 0)
);
end component;
component synchronizer is
port(
x : in std_logic;
rst : in std_logic;
clk : in std_logic;
xsync : out std_logic
);
end component;
component debouncer is
port(
x : in std_logic;
rst : in std_logic;
clk : in std_logic;
xdeb : out std_logic
);
end component;
component edgedetector is
port(
rst : in std_logic;
x : in std_logic;
clk : in std_logic;
x_falling_edge : out std_logic;
x_rising_edge : out std_logic
);
end component;
signal clk10,rst1 : std_logic;
signal start_sync, start_deb, start_edge,start_state : std_logic;
signal zero_sync, zero_deb, zero_edge, zero_state : std_logic;
signal fin_decimas, fin_usecs, fin_dsecs, fin_umin, fin_dmin : std_logic;
signal decimas_7segs : std_logic_vector (3 downto 0);
signal unidades_sec_7segs, decenas_sec_7segs : std_logic_vector (3 downto 0);
signal unidades_min_7segs, decenas_min_7segs : std_logic_vector (3 downto 0);
signal left_display, right_display : std_logic_vector (3 downto 0);
signal left_display7, right_display7, third_display7 : std_logic_vector (6 downto 0);
--trimmed signals:
signal trim1,trim2 : std_logic;
begin
start_stop_signal : process(clk,rst,start_edge)
begin
if(rst = '0') then
start_state <= '0';
elsif(rising_edge(clk)) then
if(start_edge = '1')then
start_state <= not(start_state);
end if;
end if;
end process;
zero_signal : process(clk,rst,rst1,zero_edge)
begin
if(rst = '0' or rst1 = '1') then
zero_state <= '0';
elsif(rising_edge(clk)) then
if(zero_edge = '1')then
zero_state <= '1';
end if;
end if;
end process;
counter_to_zero : process(clk10,rst,zero_state)
begin
if(rst = '0') then
rst1 <= '0';
elsif(rising_edge(clk10))then
if(zero_state = '1') then
rst1 <= '1';
else
rst1 <= '0';
end if;
end if;
end process;
point(2) <= fin_decimas;
point(1) <= fin_usecs;
point(0) <= fin_dsecs;
u_sync_start : synchronizer port map (x=>start_stop,rst=>rst,
clk=>clk,xsync=>start_sync);
u_deb_start : debouncer port map (x=>start_sync,rst=>rst,
clk=>clk,xdeb=>start_deb);
u_edge_start : edgedetector port map (rst=>rst,x=>start_deb,
clk=>clk,x_falling_edge=>start_edge,x_rising_edge=>trim1);
u_sync_zero : synchronizer port map (x=>puesta_zero,rst=>rst,
clk=>clk,xsync=>zero_sync);
u_deb_zero : debouncer port map (x=>zero_sync,rst=>rst,
clk=>clk,xdeb=>zero_deb);
u_edge_zero : edgedetector port map (rst=>rst,x=>zero_deb,
clk=>clk,x_falling_edge=>zero_edge,x_rising_edge=>trim2);
u_clk10hz : clk10hz port map (clk=>clk, rst=>rst, clk_out=>clk10);
u_decimas : contador port map (clk=>clk10,rst=>rst,puesta_zero=>zero_state,
start_stop=>start_state,cmp=>"1001",display=>decimas_7segs,fin=>fin_decimas);
u_unidades_secs : contador port map (clk=>clk10,rst=>rst,puesta_zero=>zero_state,
start_stop=>fin_decimas,cmp=>"1001",display=>unidades_sec_7segs,fin=>fin_usecs);
u_decenas_secs : contador port map (clk=>clk10,rst=>rst,puesta_zero=>zero_state,
start_stop=>fin_usecs,cmp=>"0101",display=>decenas_sec_7segs,fin=>fin_dsecs);
u_unidades_min : contador port map (clk=>clk10,rst=>rst,puesta_zero=>zero_state,
start_stop=>fin_dsecs,cmp=>"1001",display=>unidades_min_7segs,fin=>fin_umin);
u_decenas_min : contador port map (clk=>clk10,rst=>rst,puesta_zero=>zero_state,
start_stop=>fin_umin,cmp=>"0101",display=>decenas_min_7segs,fin=>fin_dmin);
u_left7segs: switch2display7seg port map (a=>left_display,b=>left_display7);
u_right7segs: switch2display7seg port map (a=>right_display,b=>right_display7);
u_third7segs: switch2display7seg port map (a=>decimas_7segs,b=>third_display7);
left_display <= decenas_sec_7segs when sel = '1' else decenas_min_7segs;
right_display <= unidades_sec_7segs when sel = '1' else unidades_min_7segs;
left_segs <= left_display7;
right_segs <= right_display7;
decimal_segs <= third_display7;
end rtl;
|
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: RAM_multiple_access
-- Module Name: RAM_multiple_access
-- Project Name: Essentials
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Circuit to simulate the behavioral of multiple memory RAM that shares the same content.
-- It is useful when you want to access more than one location at the same time, and
-- the locations for each access can be anywhere in the memory, where in banks in most
-- time is one address after another.
-- It can be seen as one single with multiple I/O operating at the same time.
--
-- The circuits parameters
--
-- number_of_memories :
--
-- The total number of memories or the total number of I/O's applied.
--
-- ram_address_size :
--
-- Address size of the RAM used on the circuit.
--
-- ram_word_size :
--
-- The size of internal word of the RAM.
--
-- file_ram_word_size :
--
-- The size of the word used in the file to be loaded on the RAM.(ARCH: FILE_LOAD)
--
-- load_file_name :
--
-- The name of file to be loaded.(ARCH: FILE_LOAD)
--
-- dump_file_name :
--
-- The name of the file to be used to dump the memory.(ARCH: FILE_LOAD)
--
-- Dependencies:
-- VHDL-93
--
-- IEEE.NUMERIC_STD.ALL;
-- IEEE.STD_LOGIC_TEXTIO.ALL;
-- STD.TEXTIO.ALL;
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_TEXTIO.ALL;
library STD;
use STD.TEXTIO.ALL;
entity ram_multiple_access is
Generic (
number_of_memories : integer;
ram_address_size : integer;
ram_word_size : integer;
file_ram_word_size : integer;
load_file_name : string := "ram.dat";
dump_file_name : string := "ram.dat"
);
Port (
data_in : in STD_LOGIC_VECTOR(((ram_word_size)*(number_of_memories) - 1) downto 0);
rw : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
dump : in STD_LOGIC;
address : in STD_LOGIC_VECTOR(((ram_address_size)*(number_of_memories) - 1) downto 0);
rst_value : in STD_LOGIC_VECTOR((ram_word_size - 1) downto 0);
data_out : out STD_LOGIC_VECTOR(((ram_word_size)*(number_of_memories) - 1) downto 0)
);
end ram_multiple_access;
architecture simple of ram_multiple_access is
type ramtype is array(0 to (2**ram_address_size - 1)) of std_logic_vector((ram_word_size - 1) downto 0);
procedure dump_ram (ram_file_name : in string; memory_ram : in ramtype) is
FILE ram_file : text is out ram_file_name;
variable line_n : line;
begin
for I in ramtype'range loop
write (line_n, memory_ram(I));
writeline (ram_file, line_n);
end loop;
end procedure;
signal memory_ram : ramtype;
begin
process (clk)
begin
if clk'event and clk = '1' then
if rst = '1' then
for I in ramtype'range loop
memory_ram(I) <= rst_value;
end loop;
end if;
if dump = '1' then
dump_ram(dump_file_name, memory_ram);
end if;
if rw = '1' then
for index in 0 to (number_of_memories - 1) loop
memory_ram(to_integer(unsigned(address(((ram_address_size)*(index + 1) - 1) downto ((ram_address_size)*index))))) <= data_in(((ram_word_size)*(index + 1) - 1) downto ((ram_word_size)*index));
end loop;
end if;
for index in 0 to (number_of_memories - 1) loop
data_out(((ram_word_size)*(index + 1) - 1) downto ((ram_word_size)*index)) <= memory_ram(to_integer(unsigned(address(((ram_address_size)*(index + 1) - 1) downto ((ram_address_size)*index)))));
end loop;
end if;
end process;
end simple;
|
--==============================================================================
-- File: d_mem.vhd
-- Author: Pietro Lorefice
--==============================================================================
-- Description:
-- Data memory for the processor. Synchronous dual-port interface with two
-- unidirectional data buses and memory selection.
--
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity d_mem is
generic (
N : integer; -- # of addresses
B : integer -- Word size
);
port (
clk : in std_logic; -- Clock
rst : in std_logic; -- Synch reset
we_l : in std_logic; -- Write enable
sel_l : in std_logic; -- Select
r_addr : in std_logic_vector(N-1 downto 0); -- Read address
w_addr : in std_logic_vector(N-1 downto 0); -- Write address
w_data : in std_logic_vector(B-1 downto 0); -- Data input
r_data : out std_logic_vector(B-1 downto 0) -- Data output
);
end entity d_mem;
architecture RTL of d_mem is
type mem_t is array(2**N - 1 downto 0) of std_logic_vector(B-1 downto 0);
signal mem_i : mem_t; -- Storage element
signal r_data_q : std_logic_vector(B-1 downto 0); -- Data output register
begin
-- =================
-- | Storage logic |
-- =================
ram_reg : process(clk) is
begin
if rising_edge(clk) then
if rst = '1' then
mem_i <= (others => (others => '0'));
r_data_q <= (others => '0');
else
if (sel_l = '1') then
r_data_q <= (others => '0');
else
r_data_q <= mem_i(to_integer(unsigned(r_addr)));
if we_l = '0' then
mem_i(to_integer(unsigned(w_addr))) <= w_data;
end if;
end if;
end if;
end if;
end process ram_reg;
-- ================
-- | Output logic |
-- ================
r_data <= r_data_q;
end architecture RTL;
|
library verilog;
use verilog.vl_types.all;
entity Control_unit_vlg_vec_tst is
end Control_unit_vlg_vec_tst;
|
iafRefCell- |
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: lconf
-- File: lconf.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: LEON configuration register. Returns the configuration
-- of the processor.
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.target.all;
use work.config.all;
use work.iface.all;
use work.amba.all;
entity lconf is
port (
rst : rst_type;
apbo : out apb_slv_out_type
);
end;
architecture rtl of lconf is
begin
beh : process(rst)
variable regsd : std_logic_vector(31 downto 0);
begin
regsd := (others => '0');
if WPROTEN then regsd(1 downto 0) := "01"; end if;
case PCICORE is
when insilicon => regsd(3 downto 2) := "01";
when esa => regsd(3 downto 2) := "10";
when ahbtst => regsd(3 downto 2) := "11";
when others => regsd(3 downto 2) := "00";
end case;
if FPEN then regsd(5 downto 4) := "01"; end if;
if AHBSTATEN then regsd(6) := '1'; end if;
if WDOGEN then regsd(7) := '1'; end if;
if MULTIPLIER /= none then regsd(8) := '1'; end if;
if DIVIDER /= none then regsd(9) := '1'; end if;
regsd(11 downto 10) := std_logic_vector(conv_unsigned(DLINE_BITS, 2));
regsd(14 downto 12) := std_logic_vector(conv_unsigned(DLINE_BITS+DOFFSET_BITS-8, 3));
regsd(16 downto 15) := std_logic_vector(conv_unsigned(ILINE_BITS, 2));
regsd(19 downto 17) := std_logic_vector(conv_unsigned(ILINE_BITS+IOFFSET_BITS-8, 3));
regsd(24 downto 20) := std_logic_vector(conv_unsigned(NWINDOWS-1,5));
if MACEN then regsd(25) := '1'; end if;
apbo.prdata <= regsd;
end process;
end;
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: lconf
-- File: lconf.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: LEON configuration register. Returns the configuration
-- of the processor.
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.target.all;
use work.config.all;
use work.iface.all;
use work.amba.all;
entity lconf is
port (
rst : rst_type;
apbo : out apb_slv_out_type
);
end;
architecture rtl of lconf is
begin
beh : process(rst)
variable regsd : std_logic_vector(31 downto 0);
begin
regsd := (others => '0');
if WPROTEN then regsd(1 downto 0) := "01"; end if;
case PCICORE is
when insilicon => regsd(3 downto 2) := "01";
when esa => regsd(3 downto 2) := "10";
when ahbtst => regsd(3 downto 2) := "11";
when others => regsd(3 downto 2) := "00";
end case;
if FPEN then regsd(5 downto 4) := "01"; end if;
if AHBSTATEN then regsd(6) := '1'; end if;
if WDOGEN then regsd(7) := '1'; end if;
if MULTIPLIER /= none then regsd(8) := '1'; end if;
if DIVIDER /= none then regsd(9) := '1'; end if;
regsd(11 downto 10) := std_logic_vector(conv_unsigned(DLINE_BITS, 2));
regsd(14 downto 12) := std_logic_vector(conv_unsigned(DLINE_BITS+DOFFSET_BITS-8, 3));
regsd(16 downto 15) := std_logic_vector(conv_unsigned(ILINE_BITS, 2));
regsd(19 downto 17) := std_logic_vector(conv_unsigned(ILINE_BITS+IOFFSET_BITS-8, 3));
regsd(24 downto 20) := std_logic_vector(conv_unsigned(NWINDOWS-1,5));
if MACEN then regsd(25) := '1'; end if;
apbo.prdata <= regsd;
end process;
end;
|
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