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-- (c) Copyright 2012 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. ------------------------------------------------------------ ------------------------------------------------------------------------------- -- Filename: axi_dma_pkg.vhd -- Description: This package contains various constants and functions for -- AXI DMA operations. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library lib_pkg_v1_0_2; use lib_pkg_v1_0_2.lib_pkg.clog2; package axi_dma_pkg is ------------------------------------------------------------------------------- -- Function declarations ------------------------------------------------------------------------------- -- Find minimum required btt width function required_btt_width (dwidth : integer; burst_size : integer; btt_width : integer) return integer; -- Return correct hertz paramter value function hertz_prmtr_select(included : integer; lite_frequency : integer; sg_frequency : integer) return integer; -- Return SnF enable or disable function enable_snf (sf_enabled : integer; axi_data_width : integer; axis_tdata_width : integer) return integer; ------------------------------------------------------------------------------- -- Constant Declarations ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- AXI Responce Values ------------------------------------------------------------------------------- constant OKAY_RESP : std_logic_vector(1 downto 0) := "00"; constant EXOKAY_RESP : std_logic_vector(1 downto 0) := "01"; constant SLVERR_RESP : std_logic_vector(1 downto 0) := "10"; constant DECERR_RESP : std_logic_vector(1 downto 0) := "11"; constant MTBF_STAGES : integer := 4; constant C_FIFO_MTBF : integer := 4; ------------------------------------------------------------------------------- -- Misc Constants ------------------------------------------------------------------------------- --constant NUM_REG_TOTAL : integer := 18; --constant NUM_REG_TOTAL : integer := 23; constant NUM_REG_TOTAL : integer := 143; -- To accomodate S2MM registers --constant NUM_REG_PER_CHANNEL : integer := 6; constant NUM_REG_PER_CHANNEL : integer := 12; constant NUM_REG_PER_S2MM : integer := 120; --constant REG_MSB_ADDR_BIT : integer := clog2(NUM_REG_TOTAL)-1; constant CMD_BASE_WIDTH : integer := 40; constant BUFFER_LENGTH_WIDTH : integer := 23; -- Constants Used in Desc Updates constant DESC_STS_TYPE : std_logic := '1'; constant DESC_DATA_TYPE : std_logic := '0'; constant DESC_LAST : std_logic := '1'; constant DESC_NOT_LAST : std_logic := '0'; -- Interrupt Coalescing constant ZERO_THRESHOLD : std_logic_vector(7 downto 0) := (others => '0'); constant ONE_THRESHOLD : std_logic_vector(7 downto 0) := "00000001"; constant ZERO_DELAY : std_logic_vector(7 downto 0) := (others => '0'); ------------------------------------------------------------------------------- -- AXI Lite AXI DMA Register Offsets ------------------------------------------------------------------------------- constant MM2S_DMACR_INDEX : integer := 0; constant MM2S_DMASR_INDEX : integer := 1; constant MM2S_CURDESC_LSB_INDEX : integer := 2; constant MM2S_CURDESC_MSB_INDEX : integer := 3; constant MM2S_TAILDESC_LSB_INDEX : integer := 4; constant MM2S_TAILDESC_MSB_INDEX : integer := 5; constant MM2S_SA_INDEX : integer := 6; constant MM2S_SA2_INDEX : integer := 7; constant RESERVED_20_INDEX : integer := 8; constant RESERVED_24_INDEX : integer := 9; constant MM2S_LENGTH_INDEX : integer := 10; constant RESERVED_2C_INDEX : integer := 11; constant S2MM_DMACR_INDEX : integer := 12; constant S2MM_DMASR_INDEX : integer := 13; constant S2MM_CURDESC_LSB_INDEX : integer := 14; constant S2MM_CURDESC_MSB_INDEX : integer := 15; constant S2MM_TAILDESC_LSB_INDEX : integer := 16; constant S2MM_TAILDESC_MSB_INDEX : integer := 17; constant S2MM_DA_INDEX : integer := 18; constant S2MM_DA2_INDEX : integer := 19; constant RESERVED_50_INDEX : integer := 20; constant RESERVED_54_INDEX : integer := 21; --constant S2MM_LENGTH_INDEX : integer := 22; constant S2MM_LENGTH_INDEX : integer := 142; constant MM2S_DMACR_OFFSET : std_logic_vector(9 downto 0) := "0000000000"; -- 0x00 constant MM2S_DMASR_OFFSET : std_logic_vector(9 downto 0) := "0000000100"; -- 0x04 constant MM2S_CURDESC_LSB_OFFSET : std_logic_vector(9 downto 0) := "0000001000"; -- 0x08 constant MM2S_CURDESC_MSB_OFFSET : std_logic_vector(9 downto 0) := "0000001100"; -- 0x0C constant MM2S_TAILDESC_LSB_OFFSET : std_logic_vector(9 downto 0) := "0000010000"; -- 0x10 constant MM2S_TAILDESC_MSB_OFFSET : std_logic_vector(9 downto 0) := "0000010100"; -- 0x14 constant MM2S_SA_OFFSET : std_logic_vector(9 downto 0) := "0000011000"; -- 0x18 constant MM2S_SA2_OFFSET : std_logic_vector(9 downto 0) := "0000011100"; -- 0x1C constant RESERVED_20_OFFSET : std_logic_vector(9 downto 0) := "0000100000"; -- 0x20 constant RESERVED_24_OFFSET : std_logic_vector(9 downto 0) := "0000100100"; -- 0x24 constant MM2S_LENGTH_OFFSET : std_logic_vector(9 downto 0) := "0000101000"; -- 0x28 -- Following was reserved, now is used for SG xCache and xUser constant SGCTL_OFFSET : std_logic_vector(9 downto 0) := "0000101100"; -- 0x2C constant S2MM_DMACR_OFFSET : std_logic_vector(9 downto 0) := "0000110000"; -- 0x30 constant S2MM_DMASR_OFFSET : std_logic_vector(9 downto 0) := "0000110100"; -- 0x34 constant S2MM_CURDESC_LSB_OFFSET : std_logic_vector(9 downto 0) := "0000111000"; -- 0x38 constant S2MM_CURDESC_MSB_OFFSET : std_logic_vector(9 downto 0) := "0000111100"; -- 0x3C constant S2MM_TAILDESC_LSB_OFFSET : std_logic_vector(9 downto 0) := "0001000000"; -- 0x40 constant S2MM_TAILDESC_MSB_OFFSET : std_logic_vector(9 downto 0) := "0001000100"; -- 0x44 constant S2MM_DA_OFFSET : std_logic_vector(9 downto 0) := "0001001000"; -- 0x48 --CR603034 constant S2MM_DA2_OFFSET : std_logic_vector(9 downto 0) := "0001001100"; -- 0x4C constant RESERVED_50_OFFSET : std_logic_vector(9 downto 0) := "0001010000"; -- 0x50 constant RESERVED_54_OFFSET : std_logic_vector(9 downto 0) := "0001010100"; -- 0x54 constant S2MM_LENGTH_OFFSET : std_logic_vector(9 downto 0) := "0001011000"; -- 0x58 -- New registers for S2MM channels constant S2MM_CURDESC1_LSB_OFFSET : std_logic_vector(9 downto 0) := "0001110000"; -- 0x70 constant S2MM_CURDESC1_MSB_OFFSET : std_logic_vector(9 downto 0) := "0001110100"; -- 0x74 constant S2MM_TAILDESC1_LSB_OFFSET : std_logic_vector(9 downto 0) := "0001111000"; -- 0x78 constant S2MM_TAILDESC1_MSB_OFFSET : std_logic_vector(9 downto 0) := "0001111100"; -- 0x7C constant S2MM_CURDESC2_LSB_OFFSET : std_logic_vector(9 downto 0) := "0010010000"; -- 0x90 constant S2MM_CURDESC2_MSB_OFFSET : std_logic_vector(9 downto 0) := "0010010100"; -- 0x94 constant S2MM_TAILDESC2_LSB_OFFSET : std_logic_vector(9 downto 0) := "0010011000"; -- 0x98 constant S2MM_TAILDESC2_MSB_OFFSET : std_logic_vector(9 downto 0) := "0010011100"; -- 0x9C constant S2MM_CURDESC3_LSB_OFFSET : std_logic_vector(9 downto 0) := "0010110000"; -- 0xB0 constant S2MM_CURDESC3_MSB_OFFSET : std_logic_vector(9 downto 0) := "0010110100"; -- 0xB4 constant S2MM_TAILDESC3_LSB_OFFSET : std_logic_vector(9 downto 0) := "0010111000"; -- 0xB8 constant S2MM_TAILDESC3_MSB_OFFSET : std_logic_vector(9 downto 0) := "0010111100"; -- 0xBC constant S2MM_CURDESC4_LSB_OFFSET : std_logic_vector(9 downto 0) := "0011010000"; -- 0xD0 constant S2MM_CURDESC4_MSB_OFFSET : std_logic_vector(9 downto 0) := "0011010100"; -- 0xD4 constant S2MM_TAILDESC4_LSB_OFFSET : std_logic_vector(9 downto 0) := "0011011000"; -- 0xD8 constant S2MM_TAILDESC4_MSB_OFFSET : std_logic_vector(9 downto 0) := "0011011100"; -- 0xDC constant S2MM_CURDESC5_LSB_OFFSET : std_logic_vector(9 downto 0) := "0011110000"; -- 0xF0 constant S2MM_CURDESC5_MSB_OFFSET : std_logic_vector(9 downto 0) := "0011110100"; -- 0xF4 constant S2MM_TAILDESC5_LSB_OFFSET : std_logic_vector(9 downto 0) := "0011111000"; -- 0xF8 constant S2MM_TAILDESC5_MSB_OFFSET : std_logic_vector(9 downto 0) := "0011111100"; -- 0xFC constant S2MM_CURDESC6_LSB_OFFSET : std_logic_vector(9 downto 0) := "0100010000"; -- 0x110 constant S2MM_CURDESC6_MSB_OFFSET : std_logic_vector(9 downto 0) := "0100010100"; -- 0x114 constant S2MM_TAILDESC6_LSB_OFFSET : std_logic_vector(9 downto 0) := "0100011000"; -- 0x118 constant S2MM_TAILDESC6_MSB_OFFSET : std_logic_vector(9 downto 0) := "0100011100"; -- 0x11C constant S2MM_CURDESC7_LSB_OFFSET : std_logic_vector(9 downto 0) := "0100110000"; -- 0x130 constant S2MM_CURDESC7_MSB_OFFSET : std_logic_vector(9 downto 0) := "0100110100"; -- 0x134 constant S2MM_TAILDESC7_LSB_OFFSET : std_logic_vector(9 downto 0) := "0100111000"; -- 0x138 constant S2MM_TAILDESC7_MSB_OFFSET : std_logic_vector(9 downto 0) := "0100111100"; -- 0x13C constant S2MM_CURDESC8_LSB_OFFSET : std_logic_vector(9 downto 0) := "0101010000"; -- 0x150 constant S2MM_CURDESC8_MSB_OFFSET : std_logic_vector(9 downto 0) := "0101010100"; -- 0x154 constant S2MM_TAILDESC8_LSB_OFFSET : std_logic_vector(9 downto 0) := "0101011000"; -- 0x158 constant S2MM_TAILDESC8_MSB_OFFSET : std_logic_vector(9 downto 0) := "0101011100"; -- 0x15C constant S2MM_CURDESC9_LSB_OFFSET : std_logic_vector(9 downto 0) := "0101110000"; -- 0x170 constant S2MM_CURDESC9_MSB_OFFSET : std_logic_vector(9 downto 0) := "0101110100"; -- 0x174 constant S2MM_TAILDESC9_LSB_OFFSET : std_logic_vector(9 downto 0) := "0101111000"; -- 0x178 constant S2MM_TAILDESC9_MSB_OFFSET : std_logic_vector(9 downto 0) := "0101111100"; -- 0x17C constant S2MM_CURDESC10_LSB_OFFSET : std_logic_vector(9 downto 0) := "0110010000"; -- 0x190 constant S2MM_CURDESC10_MSB_OFFSET : std_logic_vector(9 downto 0) := "0110010100"; -- 0x194 constant S2MM_TAILDESC10_LSB_OFFSET : std_logic_vector(9 downto 0) := "0110011000"; -- 0x198 constant S2MM_TAILDESC10_MSB_OFFSET : std_logic_vector(9 downto 0) := "0110011100"; -- 0x19C constant S2MM_CURDESC11_LSB_OFFSET : std_logic_vector(9 downto 0) := "0110110000"; -- 0x1B0 constant S2MM_CURDESC11_MSB_OFFSET : std_logic_vector(9 downto 0) := "0110110100"; -- 0x1B4 constant S2MM_TAILDESC11_LSB_OFFSET : std_logic_vector(9 downto 0) := "0110111000"; -- 0x1B8 constant S2MM_TAILDESC11_MSB_OFFSET : std_logic_vector(9 downto 0) := "0110111100"; -- 0x1BC constant S2MM_CURDESC12_LSB_OFFSET : std_logic_vector(9 downto 0) := "0111010000"; -- 0x1D0 constant S2MM_CURDESC12_MSB_OFFSET : std_logic_vector(9 downto 0) := "0111010100"; -- 0x1D4 constant S2MM_TAILDESC12_LSB_OFFSET : std_logic_vector(9 downto 0) := "0111011000"; -- 0x1D8 constant S2MM_TAILDESC12_MSB_OFFSET : std_logic_vector(9 downto 0) := "0111011100"; -- 0x1DC constant S2MM_CURDESC13_LSB_OFFSET : std_logic_vector(9 downto 0) := "0111110000"; -- 0x1F0 constant S2MM_CURDESC13_MSB_OFFSET : std_logic_vector(9 downto 0) := "0111110100"; -- 0x1F4 constant S2MM_TAILDESC13_LSB_OFFSET : std_logic_vector(9 downto 0) := "0111111000"; -- 0x1F8 constant S2MM_TAILDESC13_MSB_OFFSET : std_logic_vector(9 downto 0) := "0111111100"; -- 0x1FC constant S2MM_CURDESC14_LSB_OFFSET : std_logic_vector(9 downto 0) := "1000010000"; -- 0x210 constant S2MM_CURDESC14_MSB_OFFSET : std_logic_vector(9 downto 0) := "1000010100"; -- 0x214 constant S2MM_TAILDESC14_LSB_OFFSET : std_logic_vector(9 downto 0) := "1000011000"; -- 0x218 constant S2MM_TAILDESC14_MSB_OFFSET : std_logic_vector(9 downto 0) := "1000011100"; -- 0x21C constant S2MM_CURDESC15_LSB_OFFSET : std_logic_vector(9 downto 0) := "1000110000"; -- 0x230 constant S2MM_CURDESC15_MSB_OFFSET : std_logic_vector(9 downto 0) := "1000110100"; -- 0x234 constant S2MM_TAILDESC15_LSB_OFFSET : std_logic_vector(9 downto 0) := "1000111000"; -- 0x238 constant S2MM_TAILDESC15_MSB_OFFSET : std_logic_vector(9 downto 0) := "1000111100"; -- 0x23C ------------------------------------------------------------------------------- -- Register Bit Constants ------------------------------------------------------------------------------- -- DMACR constant DMACR_RS_BIT : integer := 0; constant DMACR_TAILPEN_BIT : integer := 1; constant DMACR_RESET_BIT : integer := 2; constant DMACR_KH_BIT : integer := 3; constant CYCLIC_BIT : integer := 4; --constant DMACR_RESERVED3_BIT : integer := 3; --constant DMACR_RESERVED4_BIT : integer := 4; constant DMACR_RESERVED5_BIT : integer := 5; constant DMACR_RESERVED6_BIT : integer := 6; constant DMACR_RESERVED7_BIT : integer := 7; constant DMACR_RESERVED8_BIT : integer := 8; constant DMACR_RESERVED9_BIT : integer := 9; constant DMACR_RESERVED10_BIT : integer := 10; constant DMACR_RESERVED11_BIT : integer := 11; constant DMACR_IOC_IRQEN_BIT : integer := 12; constant DMACR_DLY_IRQEN_BIT : integer := 13; constant DMACR_ERR_IRQEN_BIT : integer := 14; constant DMACR_RESERVED15_BIT : integer := 15; constant DMACR_IRQTHRESH_LSB_BIT : integer := 16; constant DMACR_IRQTHRESH_MSB_BIT : integer := 23; constant DMACR_IRQDELAY_LSB_BIT : integer := 24; constant DMACR_IRQDELAY_MSB_BIT : integer := 31; -- DMASR constant DMASR_HALTED_BIT : integer := 0; constant DMASR_IDLE_BIT : integer := 1; constant DMASR_CMPLT_BIT : integer := 2; constant DMASR_ERROR_BIT : integer := 3; constant DMASR_DMAINTERR_BIT : integer := 4; constant DMASR_DMASLVERR_BIT : integer := 5; constant DMASR_DMADECERR_BIT : integer := 6; constant DMASR_RESERVED7_BIT : integer := 7; constant DMASR_SGINTERR_BIT : integer := 8; constant DMASR_SGSLVERR_BIT : integer := 9; constant DMASR_SGDECERR_BIT : integer := 10; constant DMASR_RESERVED11_BIT : integer := 11; constant DMASR_IOCIRQ_BIT : integer := 12; constant DMASR_DLYIRQ_BIT : integer := 13; constant DMASR_ERRIRQ_BIT : integer := 14; constant DMASR_RESERVED15_BIT : integer := 15; constant DMASR_IRQTHRESH_LSB_BIT : integer := 16; constant DMASR_IRQTHRESH_MSB_BIT : integer := 23; constant DMASR_IRQDELAY_LSB_BIT : integer := 24; constant DMASR_IRQDELAY_MSB_BIT : integer := 31; -- CURDESC constant CURDESC_LOWER_MSB_BIT : integer := 31; constant CURDESC_LOWER_LSB_BIT : integer := 6; constant CURDESC_RESERVED_BIT5 : integer := 5; constant CURDESC_RESERVED_BIT4 : integer := 4; constant CURDESC_RESERVED_BIT3 : integer := 3; constant CURDESC_RESERVED_BIT2 : integer := 2; constant CURDESC_RESERVED_BIT1 : integer := 1; constant CURDESC_RESERVED_BIT0 : integer := 0; -- TAILDESC constant TAILDESC_LOWER_MSB_BIT : integer := 31; constant TAILDESC_LOWER_LSB_BIT : integer := 6; constant TAILDESC_RESERVED_BIT5 : integer := 5; constant TAILDESC_RESERVED_BIT4 : integer := 4; constant TAILDESC_RESERVED_BIT3 : integer := 3; constant TAILDESC_RESERVED_BIT2 : integer := 2; constant TAILDESC_RESERVED_BIT1 : integer := 1; constant TAILDESC_RESERVED_BIT0 : integer := 0; -- DataMover Command / Status Constants constant DATAMOVER_CMDDONE_BIT : integer := 7; constant DATAMOVER_SLVERR_BIT : integer := 6; constant DATAMOVER_DECERR_BIT : integer := 5; constant DATAMOVER_INTERR_BIT : integer := 4; constant DATAMOVER_TAGMSB_BIT : integer := 3; constant DATAMOVER_TAGLSB_BIT : integer := 0; -- Descriptor Control Bits constant DESC_BLENGTH_LSB_BIT : integer := 0; constant DESC_BLENGTH_MSB_BIT : integer := 22; constant DESC_RSVD23_BIT : integer := 23; constant DESC_RSVD24_BIT : integer := 24; constant DESC_RSVD25_BIT : integer := 25; constant DESC_EOF_BIT : integer := 26; constant DESC_SOF_BIT : integer := 27; constant DESC_RSVD28_BIT : integer := 28; constant DESC_RSVD29_BIT : integer := 29; constant DESC_RSVD30_BIT : integer := 30; constant DESC_IOC_BIT : integer := 31; -- Descriptor Status Bits constant DESC_STS_CMPLTD_BIT : integer := 31; constant DESC_STS_DECERR_BIT : integer := 30; constant DESC_STS_SLVERR_BIT : integer := 29; constant DESC_STS_INTERR_BIT : integer := 28; constant DESC_STS_RXSOF_BIT : integer := 27; constant DESC_STS_RXEOF_BIT : integer := 26; constant DESC_STS_RSVD25_BIT : integer := 25; constant DESC_STS_RSVD24_BIT : integer := 24; constant DESC_STS_RSVD23_BIT : integer := 23; constant DESC_STS_XFRDBYTS_MSB_BIT : integer := 22; constant DESC_STS_XFRDBYTS_LSB_BIT : integer := 0; -- DataMover Command / Status Constants constant DATAMOVER_STS_CMDDONE_BIT : integer := 7; constant DATAMOVER_STS_SLVERR_BIT : integer := 6; constant DATAMOVER_STS_DECERR_BIT : integer := 5; constant DATAMOVER_STS_INTERR_BIT : integer := 4; constant DATAMOVER_STS_TAGMSB_BIT : integer := 3; constant DATAMOVER_STS_TAGLSB_BIT : integer := 0; constant DATAMOVER_STS_TAGEOF_BIT : integer := 1; constant DATAMOVER_STS_TLAST_BIT : integer := 31; constant DATAMOVER_CMD_BTTLSB_BIT : integer := 0; constant DATAMOVER_CMD_BTTMSB_BIT : integer := 22; constant DATAMOVER_CMD_TYPE_BIT : integer := 23; constant DATAMOVER_CMD_DSALSB_BIT : integer := 24; constant DATAMOVER_CMD_DSAMSB_BIT : integer := 29; constant DATAMOVER_CMD_EOF_BIT : integer := 30; constant DATAMOVER_CMD_DRR_BIT : integer := 31; constant DATAMOVER_CMD_ADDRLSB_BIT : integer := 32; -- Note: Bit offset require adding ADDR WIDTH to get to actual bit index constant DATAMOVER_CMD_ADDRMSB_BOFST: integer := 31; constant DATAMOVER_CMD_TAGLSB_BOFST : integer := 32; constant DATAMOVER_CMD_TAGMSB_BOFST : integer := 35; constant DATAMOVER_CMD_RSVLSB_BOFST : integer := 36; constant DATAMOVER_CMD_RSVMSB_BOFST : integer := 39; end axi_dma_pkg; ------------------------------------------------------------------------------- -- PACKAGE BODY ------------------------------------------------------------------------------- package body axi_dma_pkg is ------------------------------------------------------------------------------- -- Function to determine minimum bits required for BTT_SIZE field ------------------------------------------------------------------------------- function required_btt_width ( dwidth : integer; burst_size: integer; btt_width : integer) return integer is variable min_width : integer; begin min_width := clog2((dwidth/8)*burst_size)+1; if(min_width > btt_width)then return min_width; else return btt_width; end if; end function required_btt_width; ------------------------------------------------------------------------------- -- function to return Frequency Hertz parameter based on inclusion of sg engine ------------------------------------------------------------------------------- function hertz_prmtr_select(included : integer; lite_frequency : integer; sg_frequency : integer) return integer is begin -- 1 = Scatter Gather Included -- 0 = Scatter Gather Excluded if(included = 1)then return sg_frequency; else return lite_frequency; end if; end; ------------------------------------------------------------------------------- -- function to enable store and forward based on data width mismatch -- or directly enabled ------------------------------------------------------------------------------- function enable_snf (sf_enabled : integer; axi_data_width : integer; axis_tdata_width : integer) return integer is begin -- If store and forward enable or data widths do not -- match then return 1 to enable snf if( (sf_enabled = 1) or (axi_data_width /= axis_tdata_width))then return 1; else -- coverage off return 0; -- coverage on end if; end; end package body axi_dma_pkg;
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. ------------------------------------------------------------ ------------------------------------------------------------------------------- -- Filename: axi_dma_pkg.vhd -- Description: This package contains various constants and functions for -- AXI DMA operations. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library lib_pkg_v1_0_2; use lib_pkg_v1_0_2.lib_pkg.clog2; package axi_dma_pkg is ------------------------------------------------------------------------------- -- Function declarations ------------------------------------------------------------------------------- -- Find minimum required btt width function required_btt_width (dwidth : integer; burst_size : integer; btt_width : integer) return integer; -- Return correct hertz paramter value function hertz_prmtr_select(included : integer; lite_frequency : integer; sg_frequency : integer) return integer; -- Return SnF enable or disable function enable_snf (sf_enabled : integer; axi_data_width : integer; axis_tdata_width : integer) return integer; ------------------------------------------------------------------------------- -- Constant Declarations ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- AXI Responce Values ------------------------------------------------------------------------------- constant OKAY_RESP : std_logic_vector(1 downto 0) := "00"; constant EXOKAY_RESP : std_logic_vector(1 downto 0) := "01"; constant SLVERR_RESP : std_logic_vector(1 downto 0) := "10"; constant DECERR_RESP : std_logic_vector(1 downto 0) := "11"; constant MTBF_STAGES : integer := 4; constant C_FIFO_MTBF : integer := 4; ------------------------------------------------------------------------------- -- Misc Constants ------------------------------------------------------------------------------- --constant NUM_REG_TOTAL : integer := 18; --constant NUM_REG_TOTAL : integer := 23; constant NUM_REG_TOTAL : integer := 143; -- To accomodate S2MM registers --constant NUM_REG_PER_CHANNEL : integer := 6; constant NUM_REG_PER_CHANNEL : integer := 12; constant NUM_REG_PER_S2MM : integer := 120; --constant REG_MSB_ADDR_BIT : integer := clog2(NUM_REG_TOTAL)-1; constant CMD_BASE_WIDTH : integer := 40; constant BUFFER_LENGTH_WIDTH : integer := 23; -- Constants Used in Desc Updates constant DESC_STS_TYPE : std_logic := '1'; constant DESC_DATA_TYPE : std_logic := '0'; constant DESC_LAST : std_logic := '1'; constant DESC_NOT_LAST : std_logic := '0'; -- Interrupt Coalescing constant ZERO_THRESHOLD : std_logic_vector(7 downto 0) := (others => '0'); constant ONE_THRESHOLD : std_logic_vector(7 downto 0) := "00000001"; constant ZERO_DELAY : std_logic_vector(7 downto 0) := (others => '0'); ------------------------------------------------------------------------------- -- AXI Lite AXI DMA Register Offsets ------------------------------------------------------------------------------- constant MM2S_DMACR_INDEX : integer := 0; constant MM2S_DMASR_INDEX : integer := 1; constant MM2S_CURDESC_LSB_INDEX : integer := 2; constant MM2S_CURDESC_MSB_INDEX : integer := 3; constant MM2S_TAILDESC_LSB_INDEX : integer := 4; constant MM2S_TAILDESC_MSB_INDEX : integer := 5; constant MM2S_SA_INDEX : integer := 6; constant MM2S_SA2_INDEX : integer := 7; constant RESERVED_20_INDEX : integer := 8; constant RESERVED_24_INDEX : integer := 9; constant MM2S_LENGTH_INDEX : integer := 10; constant RESERVED_2C_INDEX : integer := 11; constant S2MM_DMACR_INDEX : integer := 12; constant S2MM_DMASR_INDEX : integer := 13; constant S2MM_CURDESC_LSB_INDEX : integer := 14; constant S2MM_CURDESC_MSB_INDEX : integer := 15; constant S2MM_TAILDESC_LSB_INDEX : integer := 16; constant S2MM_TAILDESC_MSB_INDEX : integer := 17; constant S2MM_DA_INDEX : integer := 18; constant S2MM_DA2_INDEX : integer := 19; constant RESERVED_50_INDEX : integer := 20; constant RESERVED_54_INDEX : integer := 21; --constant S2MM_LENGTH_INDEX : integer := 22; constant S2MM_LENGTH_INDEX : integer := 142; constant MM2S_DMACR_OFFSET : std_logic_vector(9 downto 0) := "0000000000"; -- 0x00 constant MM2S_DMASR_OFFSET : std_logic_vector(9 downto 0) := "0000000100"; -- 0x04 constant MM2S_CURDESC_LSB_OFFSET : std_logic_vector(9 downto 0) := "0000001000"; -- 0x08 constant MM2S_CURDESC_MSB_OFFSET : std_logic_vector(9 downto 0) := "0000001100"; -- 0x0C constant MM2S_TAILDESC_LSB_OFFSET : std_logic_vector(9 downto 0) := "0000010000"; -- 0x10 constant MM2S_TAILDESC_MSB_OFFSET : std_logic_vector(9 downto 0) := "0000010100"; -- 0x14 constant MM2S_SA_OFFSET : std_logic_vector(9 downto 0) := "0000011000"; -- 0x18 constant MM2S_SA2_OFFSET : std_logic_vector(9 downto 0) := "0000011100"; -- 0x1C constant RESERVED_20_OFFSET : std_logic_vector(9 downto 0) := "0000100000"; -- 0x20 constant RESERVED_24_OFFSET : std_logic_vector(9 downto 0) := "0000100100"; -- 0x24 constant MM2S_LENGTH_OFFSET : std_logic_vector(9 downto 0) := "0000101000"; -- 0x28 -- Following was reserved, now is used for SG xCache and xUser constant SGCTL_OFFSET : std_logic_vector(9 downto 0) := "0000101100"; -- 0x2C constant S2MM_DMACR_OFFSET : std_logic_vector(9 downto 0) := "0000110000"; -- 0x30 constant S2MM_DMASR_OFFSET : std_logic_vector(9 downto 0) := "0000110100"; -- 0x34 constant S2MM_CURDESC_LSB_OFFSET : std_logic_vector(9 downto 0) := "0000111000"; -- 0x38 constant S2MM_CURDESC_MSB_OFFSET : std_logic_vector(9 downto 0) := "0000111100"; -- 0x3C constant S2MM_TAILDESC_LSB_OFFSET : std_logic_vector(9 downto 0) := "0001000000"; -- 0x40 constant S2MM_TAILDESC_MSB_OFFSET : std_logic_vector(9 downto 0) := "0001000100"; -- 0x44 constant S2MM_DA_OFFSET : std_logic_vector(9 downto 0) := "0001001000"; -- 0x48 --CR603034 constant S2MM_DA2_OFFSET : std_logic_vector(9 downto 0) := "0001001100"; -- 0x4C constant RESERVED_50_OFFSET : std_logic_vector(9 downto 0) := "0001010000"; -- 0x50 constant RESERVED_54_OFFSET : std_logic_vector(9 downto 0) := "0001010100"; -- 0x54 constant S2MM_LENGTH_OFFSET : std_logic_vector(9 downto 0) := "0001011000"; -- 0x58 -- New registers for S2MM channels constant S2MM_CURDESC1_LSB_OFFSET : std_logic_vector(9 downto 0) := "0001110000"; -- 0x70 constant S2MM_CURDESC1_MSB_OFFSET : std_logic_vector(9 downto 0) := "0001110100"; -- 0x74 constant S2MM_TAILDESC1_LSB_OFFSET : std_logic_vector(9 downto 0) := "0001111000"; -- 0x78 constant S2MM_TAILDESC1_MSB_OFFSET : std_logic_vector(9 downto 0) := "0001111100"; -- 0x7C constant S2MM_CURDESC2_LSB_OFFSET : std_logic_vector(9 downto 0) := "0010010000"; -- 0x90 constant S2MM_CURDESC2_MSB_OFFSET : std_logic_vector(9 downto 0) := "0010010100"; -- 0x94 constant S2MM_TAILDESC2_LSB_OFFSET : std_logic_vector(9 downto 0) := "0010011000"; -- 0x98 constant S2MM_TAILDESC2_MSB_OFFSET : std_logic_vector(9 downto 0) := "0010011100"; -- 0x9C constant S2MM_CURDESC3_LSB_OFFSET : std_logic_vector(9 downto 0) := "0010110000"; -- 0xB0 constant S2MM_CURDESC3_MSB_OFFSET : std_logic_vector(9 downto 0) := "0010110100"; -- 0xB4 constant S2MM_TAILDESC3_LSB_OFFSET : std_logic_vector(9 downto 0) := "0010111000"; -- 0xB8 constant S2MM_TAILDESC3_MSB_OFFSET : std_logic_vector(9 downto 0) := "0010111100"; -- 0xBC constant S2MM_CURDESC4_LSB_OFFSET : std_logic_vector(9 downto 0) := "0011010000"; -- 0xD0 constant S2MM_CURDESC4_MSB_OFFSET : std_logic_vector(9 downto 0) := "0011010100"; -- 0xD4 constant S2MM_TAILDESC4_LSB_OFFSET : std_logic_vector(9 downto 0) := "0011011000"; -- 0xD8 constant S2MM_TAILDESC4_MSB_OFFSET : std_logic_vector(9 downto 0) := "0011011100"; -- 0xDC constant S2MM_CURDESC5_LSB_OFFSET : std_logic_vector(9 downto 0) := "0011110000"; -- 0xF0 constant S2MM_CURDESC5_MSB_OFFSET : std_logic_vector(9 downto 0) := "0011110100"; -- 0xF4 constant S2MM_TAILDESC5_LSB_OFFSET : std_logic_vector(9 downto 0) := "0011111000"; -- 0xF8 constant S2MM_TAILDESC5_MSB_OFFSET : std_logic_vector(9 downto 0) := "0011111100"; -- 0xFC constant S2MM_CURDESC6_LSB_OFFSET : std_logic_vector(9 downto 0) := "0100010000"; -- 0x110 constant S2MM_CURDESC6_MSB_OFFSET : std_logic_vector(9 downto 0) := "0100010100"; -- 0x114 constant S2MM_TAILDESC6_LSB_OFFSET : std_logic_vector(9 downto 0) := "0100011000"; -- 0x118 constant S2MM_TAILDESC6_MSB_OFFSET : std_logic_vector(9 downto 0) := "0100011100"; -- 0x11C constant S2MM_CURDESC7_LSB_OFFSET : std_logic_vector(9 downto 0) := "0100110000"; -- 0x130 constant S2MM_CURDESC7_MSB_OFFSET : std_logic_vector(9 downto 0) := "0100110100"; -- 0x134 constant S2MM_TAILDESC7_LSB_OFFSET : std_logic_vector(9 downto 0) := "0100111000"; -- 0x138 constant S2MM_TAILDESC7_MSB_OFFSET : std_logic_vector(9 downto 0) := "0100111100"; -- 0x13C constant S2MM_CURDESC8_LSB_OFFSET : std_logic_vector(9 downto 0) := "0101010000"; -- 0x150 constant S2MM_CURDESC8_MSB_OFFSET : std_logic_vector(9 downto 0) := "0101010100"; -- 0x154 constant S2MM_TAILDESC8_LSB_OFFSET : std_logic_vector(9 downto 0) := "0101011000"; -- 0x158 constant S2MM_TAILDESC8_MSB_OFFSET : std_logic_vector(9 downto 0) := "0101011100"; -- 0x15C constant S2MM_CURDESC9_LSB_OFFSET : std_logic_vector(9 downto 0) := "0101110000"; -- 0x170 constant S2MM_CURDESC9_MSB_OFFSET : std_logic_vector(9 downto 0) := "0101110100"; -- 0x174 constant S2MM_TAILDESC9_LSB_OFFSET : std_logic_vector(9 downto 0) := "0101111000"; -- 0x178 constant S2MM_TAILDESC9_MSB_OFFSET : std_logic_vector(9 downto 0) := "0101111100"; -- 0x17C constant S2MM_CURDESC10_LSB_OFFSET : std_logic_vector(9 downto 0) := "0110010000"; -- 0x190 constant S2MM_CURDESC10_MSB_OFFSET : std_logic_vector(9 downto 0) := "0110010100"; -- 0x194 constant S2MM_TAILDESC10_LSB_OFFSET : std_logic_vector(9 downto 0) := "0110011000"; -- 0x198 constant S2MM_TAILDESC10_MSB_OFFSET : std_logic_vector(9 downto 0) := "0110011100"; -- 0x19C constant S2MM_CURDESC11_LSB_OFFSET : std_logic_vector(9 downto 0) := "0110110000"; -- 0x1B0 constant S2MM_CURDESC11_MSB_OFFSET : std_logic_vector(9 downto 0) := "0110110100"; -- 0x1B4 constant S2MM_TAILDESC11_LSB_OFFSET : std_logic_vector(9 downto 0) := "0110111000"; -- 0x1B8 constant S2MM_TAILDESC11_MSB_OFFSET : std_logic_vector(9 downto 0) := "0110111100"; -- 0x1BC constant S2MM_CURDESC12_LSB_OFFSET : std_logic_vector(9 downto 0) := "0111010000"; -- 0x1D0 constant S2MM_CURDESC12_MSB_OFFSET : std_logic_vector(9 downto 0) := "0111010100"; -- 0x1D4 constant S2MM_TAILDESC12_LSB_OFFSET : std_logic_vector(9 downto 0) := "0111011000"; -- 0x1D8 constant S2MM_TAILDESC12_MSB_OFFSET : std_logic_vector(9 downto 0) := "0111011100"; -- 0x1DC constant S2MM_CURDESC13_LSB_OFFSET : std_logic_vector(9 downto 0) := "0111110000"; -- 0x1F0 constant S2MM_CURDESC13_MSB_OFFSET : std_logic_vector(9 downto 0) := "0111110100"; -- 0x1F4 constant S2MM_TAILDESC13_LSB_OFFSET : std_logic_vector(9 downto 0) := "0111111000"; -- 0x1F8 constant S2MM_TAILDESC13_MSB_OFFSET : std_logic_vector(9 downto 0) := "0111111100"; -- 0x1FC constant S2MM_CURDESC14_LSB_OFFSET : std_logic_vector(9 downto 0) := "1000010000"; -- 0x210 constant S2MM_CURDESC14_MSB_OFFSET : std_logic_vector(9 downto 0) := "1000010100"; -- 0x214 constant S2MM_TAILDESC14_LSB_OFFSET : std_logic_vector(9 downto 0) := "1000011000"; -- 0x218 constant S2MM_TAILDESC14_MSB_OFFSET : std_logic_vector(9 downto 0) := "1000011100"; -- 0x21C constant S2MM_CURDESC15_LSB_OFFSET : std_logic_vector(9 downto 0) := "1000110000"; -- 0x230 constant S2MM_CURDESC15_MSB_OFFSET : std_logic_vector(9 downto 0) := "1000110100"; -- 0x234 constant S2MM_TAILDESC15_LSB_OFFSET : std_logic_vector(9 downto 0) := "1000111000"; -- 0x238 constant S2MM_TAILDESC15_MSB_OFFSET : std_logic_vector(9 downto 0) := "1000111100"; -- 0x23C ------------------------------------------------------------------------------- -- Register Bit Constants ------------------------------------------------------------------------------- -- DMACR constant DMACR_RS_BIT : integer := 0; constant DMACR_TAILPEN_BIT : integer := 1; constant DMACR_RESET_BIT : integer := 2; constant DMACR_KH_BIT : integer := 3; constant CYCLIC_BIT : integer := 4; --constant DMACR_RESERVED3_BIT : integer := 3; --constant DMACR_RESERVED4_BIT : integer := 4; constant DMACR_RESERVED5_BIT : integer := 5; constant DMACR_RESERVED6_BIT : integer := 6; constant DMACR_RESERVED7_BIT : integer := 7; constant DMACR_RESERVED8_BIT : integer := 8; constant DMACR_RESERVED9_BIT : integer := 9; constant DMACR_RESERVED10_BIT : integer := 10; constant DMACR_RESERVED11_BIT : integer := 11; constant DMACR_IOC_IRQEN_BIT : integer := 12; constant DMACR_DLY_IRQEN_BIT : integer := 13; constant DMACR_ERR_IRQEN_BIT : integer := 14; constant DMACR_RESERVED15_BIT : integer := 15; constant DMACR_IRQTHRESH_LSB_BIT : integer := 16; constant DMACR_IRQTHRESH_MSB_BIT : integer := 23; constant DMACR_IRQDELAY_LSB_BIT : integer := 24; constant DMACR_IRQDELAY_MSB_BIT : integer := 31; -- DMASR constant DMASR_HALTED_BIT : integer := 0; constant DMASR_IDLE_BIT : integer := 1; constant DMASR_CMPLT_BIT : integer := 2; constant DMASR_ERROR_BIT : integer := 3; constant DMASR_DMAINTERR_BIT : integer := 4; constant DMASR_DMASLVERR_BIT : integer := 5; constant DMASR_DMADECERR_BIT : integer := 6; constant DMASR_RESERVED7_BIT : integer := 7; constant DMASR_SGINTERR_BIT : integer := 8; constant DMASR_SGSLVERR_BIT : integer := 9; constant DMASR_SGDECERR_BIT : integer := 10; constant DMASR_RESERVED11_BIT : integer := 11; constant DMASR_IOCIRQ_BIT : integer := 12; constant DMASR_DLYIRQ_BIT : integer := 13; constant DMASR_ERRIRQ_BIT : integer := 14; constant DMASR_RESERVED15_BIT : integer := 15; constant DMASR_IRQTHRESH_LSB_BIT : integer := 16; constant DMASR_IRQTHRESH_MSB_BIT : integer := 23; constant DMASR_IRQDELAY_LSB_BIT : integer := 24; constant DMASR_IRQDELAY_MSB_BIT : integer := 31; -- CURDESC constant CURDESC_LOWER_MSB_BIT : integer := 31; constant CURDESC_LOWER_LSB_BIT : integer := 6; constant CURDESC_RESERVED_BIT5 : integer := 5; constant CURDESC_RESERVED_BIT4 : integer := 4; constant CURDESC_RESERVED_BIT3 : integer := 3; constant CURDESC_RESERVED_BIT2 : integer := 2; constant CURDESC_RESERVED_BIT1 : integer := 1; constant CURDESC_RESERVED_BIT0 : integer := 0; -- TAILDESC constant TAILDESC_LOWER_MSB_BIT : integer := 31; constant TAILDESC_LOWER_LSB_BIT : integer := 6; constant TAILDESC_RESERVED_BIT5 : integer := 5; constant TAILDESC_RESERVED_BIT4 : integer := 4; constant TAILDESC_RESERVED_BIT3 : integer := 3; constant TAILDESC_RESERVED_BIT2 : integer := 2; constant TAILDESC_RESERVED_BIT1 : integer := 1; constant TAILDESC_RESERVED_BIT0 : integer := 0; -- DataMover Command / Status Constants constant DATAMOVER_CMDDONE_BIT : integer := 7; constant DATAMOVER_SLVERR_BIT : integer := 6; constant DATAMOVER_DECERR_BIT : integer := 5; constant DATAMOVER_INTERR_BIT : integer := 4; constant DATAMOVER_TAGMSB_BIT : integer := 3; constant DATAMOVER_TAGLSB_BIT : integer := 0; -- Descriptor Control Bits constant DESC_BLENGTH_LSB_BIT : integer := 0; constant DESC_BLENGTH_MSB_BIT : integer := 22; constant DESC_RSVD23_BIT : integer := 23; constant DESC_RSVD24_BIT : integer := 24; constant DESC_RSVD25_BIT : integer := 25; constant DESC_EOF_BIT : integer := 26; constant DESC_SOF_BIT : integer := 27; constant DESC_RSVD28_BIT : integer := 28; constant DESC_RSVD29_BIT : integer := 29; constant DESC_RSVD30_BIT : integer := 30; constant DESC_IOC_BIT : integer := 31; -- Descriptor Status Bits constant DESC_STS_CMPLTD_BIT : integer := 31; constant DESC_STS_DECERR_BIT : integer := 30; constant DESC_STS_SLVERR_BIT : integer := 29; constant DESC_STS_INTERR_BIT : integer := 28; constant DESC_STS_RXSOF_BIT : integer := 27; constant DESC_STS_RXEOF_BIT : integer := 26; constant DESC_STS_RSVD25_BIT : integer := 25; constant DESC_STS_RSVD24_BIT : integer := 24; constant DESC_STS_RSVD23_BIT : integer := 23; constant DESC_STS_XFRDBYTS_MSB_BIT : integer := 22; constant DESC_STS_XFRDBYTS_LSB_BIT : integer := 0; -- DataMover Command / Status Constants constant DATAMOVER_STS_CMDDONE_BIT : integer := 7; constant DATAMOVER_STS_SLVERR_BIT : integer := 6; constant DATAMOVER_STS_DECERR_BIT : integer := 5; constant DATAMOVER_STS_INTERR_BIT : integer := 4; constant DATAMOVER_STS_TAGMSB_BIT : integer := 3; constant DATAMOVER_STS_TAGLSB_BIT : integer := 0; constant DATAMOVER_STS_TAGEOF_BIT : integer := 1; constant DATAMOVER_STS_TLAST_BIT : integer := 31; constant DATAMOVER_CMD_BTTLSB_BIT : integer := 0; constant DATAMOVER_CMD_BTTMSB_BIT : integer := 22; constant DATAMOVER_CMD_TYPE_BIT : integer := 23; constant DATAMOVER_CMD_DSALSB_BIT : integer := 24; constant DATAMOVER_CMD_DSAMSB_BIT : integer := 29; constant DATAMOVER_CMD_EOF_BIT : integer := 30; constant DATAMOVER_CMD_DRR_BIT : integer := 31; constant DATAMOVER_CMD_ADDRLSB_BIT : integer := 32; -- Note: Bit offset require adding ADDR WIDTH to get to actual bit index constant DATAMOVER_CMD_ADDRMSB_BOFST: integer := 31; constant DATAMOVER_CMD_TAGLSB_BOFST : integer := 32; constant DATAMOVER_CMD_TAGMSB_BOFST : integer := 35; constant DATAMOVER_CMD_RSVLSB_BOFST : integer := 36; constant DATAMOVER_CMD_RSVMSB_BOFST : integer := 39; end axi_dma_pkg; ------------------------------------------------------------------------------- -- PACKAGE BODY ------------------------------------------------------------------------------- package body axi_dma_pkg is ------------------------------------------------------------------------------- -- Function to determine minimum bits required for BTT_SIZE field ------------------------------------------------------------------------------- function required_btt_width ( dwidth : integer; burst_size: integer; btt_width : integer) return integer is variable min_width : integer; begin min_width := clog2((dwidth/8)*burst_size)+1; if(min_width > btt_width)then return min_width; else return btt_width; end if; end function required_btt_width; ------------------------------------------------------------------------------- -- function to return Frequency Hertz parameter based on inclusion of sg engine ------------------------------------------------------------------------------- function hertz_prmtr_select(included : integer; lite_frequency : integer; sg_frequency : integer) return integer is begin -- 1 = Scatter Gather Included -- 0 = Scatter Gather Excluded if(included = 1)then return sg_frequency; else return lite_frequency; end if; end; ------------------------------------------------------------------------------- -- function to enable store and forward based on data width mismatch -- or directly enabled ------------------------------------------------------------------------------- function enable_snf (sf_enabled : integer; axi_data_width : integer; axis_tdata_width : integer) return integer is begin -- If store and forward enable or data widths do not -- match then return 1 to enable snf if( (sf_enabled = 1) or (axi_data_width /= axis_tdata_width))then return 1; else -- coverage off return 0; -- coverage on end if; end; end package body axi_dma_pkg;
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. ------------------------------------------------------------ ------------------------------------------------------------------------------- -- Filename: axi_dma_pkg.vhd -- Description: This package contains various constants and functions for -- AXI DMA operations. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library lib_pkg_v1_0_2; use lib_pkg_v1_0_2.lib_pkg.clog2; package axi_dma_pkg is ------------------------------------------------------------------------------- -- Function declarations ------------------------------------------------------------------------------- -- Find minimum required btt width function required_btt_width (dwidth : integer; burst_size : integer; btt_width : integer) return integer; -- Return correct hertz paramter value function hertz_prmtr_select(included : integer; lite_frequency : integer; sg_frequency : integer) return integer; -- Return SnF enable or disable function enable_snf (sf_enabled : integer; axi_data_width : integer; axis_tdata_width : integer) return integer; ------------------------------------------------------------------------------- -- Constant Declarations ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- AXI Responce Values ------------------------------------------------------------------------------- constant OKAY_RESP : std_logic_vector(1 downto 0) := "00"; constant EXOKAY_RESP : std_logic_vector(1 downto 0) := "01"; constant SLVERR_RESP : std_logic_vector(1 downto 0) := "10"; constant DECERR_RESP : std_logic_vector(1 downto 0) := "11"; constant MTBF_STAGES : integer := 4; constant C_FIFO_MTBF : integer := 4; ------------------------------------------------------------------------------- -- Misc Constants ------------------------------------------------------------------------------- --constant NUM_REG_TOTAL : integer := 18; --constant NUM_REG_TOTAL : integer := 23; constant NUM_REG_TOTAL : integer := 143; -- To accomodate S2MM registers --constant NUM_REG_PER_CHANNEL : integer := 6; constant NUM_REG_PER_CHANNEL : integer := 12; constant NUM_REG_PER_S2MM : integer := 120; --constant REG_MSB_ADDR_BIT : integer := clog2(NUM_REG_TOTAL)-1; constant CMD_BASE_WIDTH : integer := 40; constant BUFFER_LENGTH_WIDTH : integer := 23; -- Constants Used in Desc Updates constant DESC_STS_TYPE : std_logic := '1'; constant DESC_DATA_TYPE : std_logic := '0'; constant DESC_LAST : std_logic := '1'; constant DESC_NOT_LAST : std_logic := '0'; -- Interrupt Coalescing constant ZERO_THRESHOLD : std_logic_vector(7 downto 0) := (others => '0'); constant ONE_THRESHOLD : std_logic_vector(7 downto 0) := "00000001"; constant ZERO_DELAY : std_logic_vector(7 downto 0) := (others => '0'); ------------------------------------------------------------------------------- -- AXI Lite AXI DMA Register Offsets ------------------------------------------------------------------------------- constant MM2S_DMACR_INDEX : integer := 0; constant MM2S_DMASR_INDEX : integer := 1; constant MM2S_CURDESC_LSB_INDEX : integer := 2; constant MM2S_CURDESC_MSB_INDEX : integer := 3; constant MM2S_TAILDESC_LSB_INDEX : integer := 4; constant MM2S_TAILDESC_MSB_INDEX : integer := 5; constant MM2S_SA_INDEX : integer := 6; constant MM2S_SA2_INDEX : integer := 7; constant RESERVED_20_INDEX : integer := 8; constant RESERVED_24_INDEX : integer := 9; constant MM2S_LENGTH_INDEX : integer := 10; constant RESERVED_2C_INDEX : integer := 11; constant S2MM_DMACR_INDEX : integer := 12; constant S2MM_DMASR_INDEX : integer := 13; constant S2MM_CURDESC_LSB_INDEX : integer := 14; constant S2MM_CURDESC_MSB_INDEX : integer := 15; constant S2MM_TAILDESC_LSB_INDEX : integer := 16; constant S2MM_TAILDESC_MSB_INDEX : integer := 17; constant S2MM_DA_INDEX : integer := 18; constant S2MM_DA2_INDEX : integer := 19; constant RESERVED_50_INDEX : integer := 20; constant RESERVED_54_INDEX : integer := 21; --constant S2MM_LENGTH_INDEX : integer := 22; constant S2MM_LENGTH_INDEX : integer := 142; constant MM2S_DMACR_OFFSET : std_logic_vector(9 downto 0) := "0000000000"; -- 0x00 constant MM2S_DMASR_OFFSET : std_logic_vector(9 downto 0) := "0000000100"; -- 0x04 constant MM2S_CURDESC_LSB_OFFSET : std_logic_vector(9 downto 0) := "0000001000"; -- 0x08 constant MM2S_CURDESC_MSB_OFFSET : std_logic_vector(9 downto 0) := "0000001100"; -- 0x0C constant MM2S_TAILDESC_LSB_OFFSET : std_logic_vector(9 downto 0) := "0000010000"; -- 0x10 constant MM2S_TAILDESC_MSB_OFFSET : std_logic_vector(9 downto 0) := "0000010100"; -- 0x14 constant MM2S_SA_OFFSET : std_logic_vector(9 downto 0) := "0000011000"; -- 0x18 constant MM2S_SA2_OFFSET : std_logic_vector(9 downto 0) := "0000011100"; -- 0x1C constant RESERVED_20_OFFSET : std_logic_vector(9 downto 0) := "0000100000"; -- 0x20 constant RESERVED_24_OFFSET : std_logic_vector(9 downto 0) := "0000100100"; -- 0x24 constant MM2S_LENGTH_OFFSET : std_logic_vector(9 downto 0) := "0000101000"; -- 0x28 -- Following was reserved, now is used for SG xCache and xUser constant SGCTL_OFFSET : std_logic_vector(9 downto 0) := "0000101100"; -- 0x2C constant S2MM_DMACR_OFFSET : std_logic_vector(9 downto 0) := "0000110000"; -- 0x30 constant S2MM_DMASR_OFFSET : std_logic_vector(9 downto 0) := "0000110100"; -- 0x34 constant S2MM_CURDESC_LSB_OFFSET : std_logic_vector(9 downto 0) := "0000111000"; -- 0x38 constant S2MM_CURDESC_MSB_OFFSET : std_logic_vector(9 downto 0) := "0000111100"; -- 0x3C constant S2MM_TAILDESC_LSB_OFFSET : std_logic_vector(9 downto 0) := "0001000000"; -- 0x40 constant S2MM_TAILDESC_MSB_OFFSET : std_logic_vector(9 downto 0) := "0001000100"; -- 0x44 constant S2MM_DA_OFFSET : std_logic_vector(9 downto 0) := "0001001000"; -- 0x48 --CR603034 constant S2MM_DA2_OFFSET : std_logic_vector(9 downto 0) := "0001001100"; -- 0x4C constant RESERVED_50_OFFSET : std_logic_vector(9 downto 0) := "0001010000"; -- 0x50 constant RESERVED_54_OFFSET : std_logic_vector(9 downto 0) := "0001010100"; -- 0x54 constant S2MM_LENGTH_OFFSET : std_logic_vector(9 downto 0) := "0001011000"; -- 0x58 -- New registers for S2MM channels constant S2MM_CURDESC1_LSB_OFFSET : std_logic_vector(9 downto 0) := "0001110000"; -- 0x70 constant S2MM_CURDESC1_MSB_OFFSET : std_logic_vector(9 downto 0) := "0001110100"; -- 0x74 constant S2MM_TAILDESC1_LSB_OFFSET : std_logic_vector(9 downto 0) := "0001111000"; -- 0x78 constant S2MM_TAILDESC1_MSB_OFFSET : std_logic_vector(9 downto 0) := "0001111100"; -- 0x7C constant S2MM_CURDESC2_LSB_OFFSET : std_logic_vector(9 downto 0) := "0010010000"; -- 0x90 constant S2MM_CURDESC2_MSB_OFFSET : std_logic_vector(9 downto 0) := "0010010100"; -- 0x94 constant S2MM_TAILDESC2_LSB_OFFSET : std_logic_vector(9 downto 0) := "0010011000"; -- 0x98 constant S2MM_TAILDESC2_MSB_OFFSET : std_logic_vector(9 downto 0) := "0010011100"; -- 0x9C constant S2MM_CURDESC3_LSB_OFFSET : std_logic_vector(9 downto 0) := "0010110000"; -- 0xB0 constant S2MM_CURDESC3_MSB_OFFSET : std_logic_vector(9 downto 0) := "0010110100"; -- 0xB4 constant S2MM_TAILDESC3_LSB_OFFSET : std_logic_vector(9 downto 0) := "0010111000"; -- 0xB8 constant S2MM_TAILDESC3_MSB_OFFSET : std_logic_vector(9 downto 0) := "0010111100"; -- 0xBC constant S2MM_CURDESC4_LSB_OFFSET : std_logic_vector(9 downto 0) := "0011010000"; -- 0xD0 constant S2MM_CURDESC4_MSB_OFFSET : std_logic_vector(9 downto 0) := "0011010100"; -- 0xD4 constant S2MM_TAILDESC4_LSB_OFFSET : std_logic_vector(9 downto 0) := "0011011000"; -- 0xD8 constant S2MM_TAILDESC4_MSB_OFFSET : std_logic_vector(9 downto 0) := "0011011100"; -- 0xDC constant S2MM_CURDESC5_LSB_OFFSET : std_logic_vector(9 downto 0) := "0011110000"; -- 0xF0 constant S2MM_CURDESC5_MSB_OFFSET : std_logic_vector(9 downto 0) := "0011110100"; -- 0xF4 constant S2MM_TAILDESC5_LSB_OFFSET : std_logic_vector(9 downto 0) := "0011111000"; -- 0xF8 constant S2MM_TAILDESC5_MSB_OFFSET : std_logic_vector(9 downto 0) := "0011111100"; -- 0xFC constant S2MM_CURDESC6_LSB_OFFSET : std_logic_vector(9 downto 0) := "0100010000"; -- 0x110 constant S2MM_CURDESC6_MSB_OFFSET : std_logic_vector(9 downto 0) := "0100010100"; -- 0x114 constant S2MM_TAILDESC6_LSB_OFFSET : std_logic_vector(9 downto 0) := "0100011000"; -- 0x118 constant S2MM_TAILDESC6_MSB_OFFSET : std_logic_vector(9 downto 0) := "0100011100"; -- 0x11C constant S2MM_CURDESC7_LSB_OFFSET : std_logic_vector(9 downto 0) := "0100110000"; -- 0x130 constant S2MM_CURDESC7_MSB_OFFSET : std_logic_vector(9 downto 0) := "0100110100"; -- 0x134 constant S2MM_TAILDESC7_LSB_OFFSET : std_logic_vector(9 downto 0) := "0100111000"; -- 0x138 constant S2MM_TAILDESC7_MSB_OFFSET : std_logic_vector(9 downto 0) := "0100111100"; -- 0x13C constant S2MM_CURDESC8_LSB_OFFSET : std_logic_vector(9 downto 0) := "0101010000"; -- 0x150 constant S2MM_CURDESC8_MSB_OFFSET : std_logic_vector(9 downto 0) := "0101010100"; -- 0x154 constant S2MM_TAILDESC8_LSB_OFFSET : std_logic_vector(9 downto 0) := "0101011000"; -- 0x158 constant S2MM_TAILDESC8_MSB_OFFSET : std_logic_vector(9 downto 0) := "0101011100"; -- 0x15C constant S2MM_CURDESC9_LSB_OFFSET : std_logic_vector(9 downto 0) := "0101110000"; -- 0x170 constant S2MM_CURDESC9_MSB_OFFSET : std_logic_vector(9 downto 0) := "0101110100"; -- 0x174 constant S2MM_TAILDESC9_LSB_OFFSET : std_logic_vector(9 downto 0) := "0101111000"; -- 0x178 constant S2MM_TAILDESC9_MSB_OFFSET : std_logic_vector(9 downto 0) := "0101111100"; -- 0x17C constant S2MM_CURDESC10_LSB_OFFSET : std_logic_vector(9 downto 0) := "0110010000"; -- 0x190 constant S2MM_CURDESC10_MSB_OFFSET : std_logic_vector(9 downto 0) := "0110010100"; -- 0x194 constant S2MM_TAILDESC10_LSB_OFFSET : std_logic_vector(9 downto 0) := "0110011000"; -- 0x198 constant S2MM_TAILDESC10_MSB_OFFSET : std_logic_vector(9 downto 0) := "0110011100"; -- 0x19C constant S2MM_CURDESC11_LSB_OFFSET : std_logic_vector(9 downto 0) := "0110110000"; -- 0x1B0 constant S2MM_CURDESC11_MSB_OFFSET : std_logic_vector(9 downto 0) := "0110110100"; -- 0x1B4 constant S2MM_TAILDESC11_LSB_OFFSET : std_logic_vector(9 downto 0) := "0110111000"; -- 0x1B8 constant S2MM_TAILDESC11_MSB_OFFSET : std_logic_vector(9 downto 0) := "0110111100"; -- 0x1BC constant S2MM_CURDESC12_LSB_OFFSET : std_logic_vector(9 downto 0) := "0111010000"; -- 0x1D0 constant S2MM_CURDESC12_MSB_OFFSET : std_logic_vector(9 downto 0) := "0111010100"; -- 0x1D4 constant S2MM_TAILDESC12_LSB_OFFSET : std_logic_vector(9 downto 0) := "0111011000"; -- 0x1D8 constant S2MM_TAILDESC12_MSB_OFFSET : std_logic_vector(9 downto 0) := "0111011100"; -- 0x1DC constant S2MM_CURDESC13_LSB_OFFSET : std_logic_vector(9 downto 0) := "0111110000"; -- 0x1F0 constant S2MM_CURDESC13_MSB_OFFSET : std_logic_vector(9 downto 0) := "0111110100"; -- 0x1F4 constant S2MM_TAILDESC13_LSB_OFFSET : std_logic_vector(9 downto 0) := "0111111000"; -- 0x1F8 constant S2MM_TAILDESC13_MSB_OFFSET : std_logic_vector(9 downto 0) := "0111111100"; -- 0x1FC constant S2MM_CURDESC14_LSB_OFFSET : std_logic_vector(9 downto 0) := "1000010000"; -- 0x210 constant S2MM_CURDESC14_MSB_OFFSET : std_logic_vector(9 downto 0) := "1000010100"; -- 0x214 constant S2MM_TAILDESC14_LSB_OFFSET : std_logic_vector(9 downto 0) := "1000011000"; -- 0x218 constant S2MM_TAILDESC14_MSB_OFFSET : std_logic_vector(9 downto 0) := "1000011100"; -- 0x21C constant S2MM_CURDESC15_LSB_OFFSET : std_logic_vector(9 downto 0) := "1000110000"; -- 0x230 constant S2MM_CURDESC15_MSB_OFFSET : std_logic_vector(9 downto 0) := "1000110100"; -- 0x234 constant S2MM_TAILDESC15_LSB_OFFSET : std_logic_vector(9 downto 0) := "1000111000"; -- 0x238 constant S2MM_TAILDESC15_MSB_OFFSET : std_logic_vector(9 downto 0) := "1000111100"; -- 0x23C ------------------------------------------------------------------------------- -- Register Bit Constants ------------------------------------------------------------------------------- -- DMACR constant DMACR_RS_BIT : integer := 0; constant DMACR_TAILPEN_BIT : integer := 1; constant DMACR_RESET_BIT : integer := 2; constant DMACR_KH_BIT : integer := 3; constant CYCLIC_BIT : integer := 4; --constant DMACR_RESERVED3_BIT : integer := 3; --constant DMACR_RESERVED4_BIT : integer := 4; constant DMACR_RESERVED5_BIT : integer := 5; constant DMACR_RESERVED6_BIT : integer := 6; constant DMACR_RESERVED7_BIT : integer := 7; constant DMACR_RESERVED8_BIT : integer := 8; constant DMACR_RESERVED9_BIT : integer := 9; constant DMACR_RESERVED10_BIT : integer := 10; constant DMACR_RESERVED11_BIT : integer := 11; constant DMACR_IOC_IRQEN_BIT : integer := 12; constant DMACR_DLY_IRQEN_BIT : integer := 13; constant DMACR_ERR_IRQEN_BIT : integer := 14; constant DMACR_RESERVED15_BIT : integer := 15; constant DMACR_IRQTHRESH_LSB_BIT : integer := 16; constant DMACR_IRQTHRESH_MSB_BIT : integer := 23; constant DMACR_IRQDELAY_LSB_BIT : integer := 24; constant DMACR_IRQDELAY_MSB_BIT : integer := 31; -- DMASR constant DMASR_HALTED_BIT : integer := 0; constant DMASR_IDLE_BIT : integer := 1; constant DMASR_CMPLT_BIT : integer := 2; constant DMASR_ERROR_BIT : integer := 3; constant DMASR_DMAINTERR_BIT : integer := 4; constant DMASR_DMASLVERR_BIT : integer := 5; constant DMASR_DMADECERR_BIT : integer := 6; constant DMASR_RESERVED7_BIT : integer := 7; constant DMASR_SGINTERR_BIT : integer := 8; constant DMASR_SGSLVERR_BIT : integer := 9; constant DMASR_SGDECERR_BIT : integer := 10; constant DMASR_RESERVED11_BIT : integer := 11; constant DMASR_IOCIRQ_BIT : integer := 12; constant DMASR_DLYIRQ_BIT : integer := 13; constant DMASR_ERRIRQ_BIT : integer := 14; constant DMASR_RESERVED15_BIT : integer := 15; constant DMASR_IRQTHRESH_LSB_BIT : integer := 16; constant DMASR_IRQTHRESH_MSB_BIT : integer := 23; constant DMASR_IRQDELAY_LSB_BIT : integer := 24; constant DMASR_IRQDELAY_MSB_BIT : integer := 31; -- CURDESC constant CURDESC_LOWER_MSB_BIT : integer := 31; constant CURDESC_LOWER_LSB_BIT : integer := 6; constant CURDESC_RESERVED_BIT5 : integer := 5; constant CURDESC_RESERVED_BIT4 : integer := 4; constant CURDESC_RESERVED_BIT3 : integer := 3; constant CURDESC_RESERVED_BIT2 : integer := 2; constant CURDESC_RESERVED_BIT1 : integer := 1; constant CURDESC_RESERVED_BIT0 : integer := 0; -- TAILDESC constant TAILDESC_LOWER_MSB_BIT : integer := 31; constant TAILDESC_LOWER_LSB_BIT : integer := 6; constant TAILDESC_RESERVED_BIT5 : integer := 5; constant TAILDESC_RESERVED_BIT4 : integer := 4; constant TAILDESC_RESERVED_BIT3 : integer := 3; constant TAILDESC_RESERVED_BIT2 : integer := 2; constant TAILDESC_RESERVED_BIT1 : integer := 1; constant TAILDESC_RESERVED_BIT0 : integer := 0; -- DataMover Command / Status Constants constant DATAMOVER_CMDDONE_BIT : integer := 7; constant DATAMOVER_SLVERR_BIT : integer := 6; constant DATAMOVER_DECERR_BIT : integer := 5; constant DATAMOVER_INTERR_BIT : integer := 4; constant DATAMOVER_TAGMSB_BIT : integer := 3; constant DATAMOVER_TAGLSB_BIT : integer := 0; -- Descriptor Control Bits constant DESC_BLENGTH_LSB_BIT : integer := 0; constant DESC_BLENGTH_MSB_BIT : integer := 22; constant DESC_RSVD23_BIT : integer := 23; constant DESC_RSVD24_BIT : integer := 24; constant DESC_RSVD25_BIT : integer := 25; constant DESC_EOF_BIT : integer := 26; constant DESC_SOF_BIT : integer := 27; constant DESC_RSVD28_BIT : integer := 28; constant DESC_RSVD29_BIT : integer := 29; constant DESC_RSVD30_BIT : integer := 30; constant DESC_IOC_BIT : integer := 31; -- Descriptor Status Bits constant DESC_STS_CMPLTD_BIT : integer := 31; constant DESC_STS_DECERR_BIT : integer := 30; constant DESC_STS_SLVERR_BIT : integer := 29; constant DESC_STS_INTERR_BIT : integer := 28; constant DESC_STS_RXSOF_BIT : integer := 27; constant DESC_STS_RXEOF_BIT : integer := 26; constant DESC_STS_RSVD25_BIT : integer := 25; constant DESC_STS_RSVD24_BIT : integer := 24; constant DESC_STS_RSVD23_BIT : integer := 23; constant DESC_STS_XFRDBYTS_MSB_BIT : integer := 22; constant DESC_STS_XFRDBYTS_LSB_BIT : integer := 0; -- DataMover Command / Status Constants constant DATAMOVER_STS_CMDDONE_BIT : integer := 7; constant DATAMOVER_STS_SLVERR_BIT : integer := 6; constant DATAMOVER_STS_DECERR_BIT : integer := 5; constant DATAMOVER_STS_INTERR_BIT : integer := 4; constant DATAMOVER_STS_TAGMSB_BIT : integer := 3; constant DATAMOVER_STS_TAGLSB_BIT : integer := 0; constant DATAMOVER_STS_TAGEOF_BIT : integer := 1; constant DATAMOVER_STS_TLAST_BIT : integer := 31; constant DATAMOVER_CMD_BTTLSB_BIT : integer := 0; constant DATAMOVER_CMD_BTTMSB_BIT : integer := 22; constant DATAMOVER_CMD_TYPE_BIT : integer := 23; constant DATAMOVER_CMD_DSALSB_BIT : integer := 24; constant DATAMOVER_CMD_DSAMSB_BIT : integer := 29; constant DATAMOVER_CMD_EOF_BIT : integer := 30; constant DATAMOVER_CMD_DRR_BIT : integer := 31; constant DATAMOVER_CMD_ADDRLSB_BIT : integer := 32; -- Note: Bit offset require adding ADDR WIDTH to get to actual bit index constant DATAMOVER_CMD_ADDRMSB_BOFST: integer := 31; constant DATAMOVER_CMD_TAGLSB_BOFST : integer := 32; constant DATAMOVER_CMD_TAGMSB_BOFST : integer := 35; constant DATAMOVER_CMD_RSVLSB_BOFST : integer := 36; constant DATAMOVER_CMD_RSVMSB_BOFST : integer := 39; end axi_dma_pkg; ------------------------------------------------------------------------------- -- PACKAGE BODY ------------------------------------------------------------------------------- package body axi_dma_pkg is ------------------------------------------------------------------------------- -- Function to determine minimum bits required for BTT_SIZE field ------------------------------------------------------------------------------- function required_btt_width ( dwidth : integer; burst_size: integer; btt_width : integer) return integer is variable min_width : integer; begin min_width := clog2((dwidth/8)*burst_size)+1; if(min_width > btt_width)then return min_width; else return btt_width; end if; end function required_btt_width; ------------------------------------------------------------------------------- -- function to return Frequency Hertz parameter based on inclusion of sg engine ------------------------------------------------------------------------------- function hertz_prmtr_select(included : integer; lite_frequency : integer; sg_frequency : integer) return integer is begin -- 1 = Scatter Gather Included -- 0 = Scatter Gather Excluded if(included = 1)then return sg_frequency; else return lite_frequency; end if; end; ------------------------------------------------------------------------------- -- function to enable store and forward based on data width mismatch -- or directly enabled ------------------------------------------------------------------------------- function enable_snf (sf_enabled : integer; axi_data_width : integer; axis_tdata_width : integer) return integer is begin -- If store and forward enable or data widths do not -- match then return 1 to enable snf if( (sf_enabled = 1) or (axi_data_width /= axis_tdata_width))then return 1; else -- coverage off return 0; -- coverage on end if; end; end package body axi_dma_pkg;
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. ------------------------------------------------------------ ------------------------------------------------------------------------------- -- Filename: axi_dma_pkg.vhd -- Description: This package contains various constants and functions for -- AXI DMA operations. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library lib_pkg_v1_0_2; use lib_pkg_v1_0_2.lib_pkg.clog2; package axi_dma_pkg is ------------------------------------------------------------------------------- -- Function declarations ------------------------------------------------------------------------------- -- Find minimum required btt width function required_btt_width (dwidth : integer; burst_size : integer; btt_width : integer) return integer; -- Return correct hertz paramter value function hertz_prmtr_select(included : integer; lite_frequency : integer; sg_frequency : integer) return integer; -- Return SnF enable or disable function enable_snf (sf_enabled : integer; axi_data_width : integer; axis_tdata_width : integer) return integer; ------------------------------------------------------------------------------- -- Constant Declarations ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- AXI Responce Values ------------------------------------------------------------------------------- constant OKAY_RESP : std_logic_vector(1 downto 0) := "00"; constant EXOKAY_RESP : std_logic_vector(1 downto 0) := "01"; constant SLVERR_RESP : std_logic_vector(1 downto 0) := "10"; constant DECERR_RESP : std_logic_vector(1 downto 0) := "11"; constant MTBF_STAGES : integer := 4; constant C_FIFO_MTBF : integer := 4; ------------------------------------------------------------------------------- -- Misc Constants ------------------------------------------------------------------------------- --constant NUM_REG_TOTAL : integer := 18; --constant NUM_REG_TOTAL : integer := 23; constant NUM_REG_TOTAL : integer := 143; -- To accomodate S2MM registers --constant NUM_REG_PER_CHANNEL : integer := 6; constant NUM_REG_PER_CHANNEL : integer := 12; constant NUM_REG_PER_S2MM : integer := 120; --constant REG_MSB_ADDR_BIT : integer := clog2(NUM_REG_TOTAL)-1; constant CMD_BASE_WIDTH : integer := 40; constant BUFFER_LENGTH_WIDTH : integer := 23; -- Constants Used in Desc Updates constant DESC_STS_TYPE : std_logic := '1'; constant DESC_DATA_TYPE : std_logic := '0'; constant DESC_LAST : std_logic := '1'; constant DESC_NOT_LAST : std_logic := '0'; -- Interrupt Coalescing constant ZERO_THRESHOLD : std_logic_vector(7 downto 0) := (others => '0'); constant ONE_THRESHOLD : std_logic_vector(7 downto 0) := "00000001"; constant ZERO_DELAY : std_logic_vector(7 downto 0) := (others => '0'); ------------------------------------------------------------------------------- -- AXI Lite AXI DMA Register Offsets ------------------------------------------------------------------------------- constant MM2S_DMACR_INDEX : integer := 0; constant MM2S_DMASR_INDEX : integer := 1; constant MM2S_CURDESC_LSB_INDEX : integer := 2; constant MM2S_CURDESC_MSB_INDEX : integer := 3; constant MM2S_TAILDESC_LSB_INDEX : integer := 4; constant MM2S_TAILDESC_MSB_INDEX : integer := 5; constant MM2S_SA_INDEX : integer := 6; constant MM2S_SA2_INDEX : integer := 7; constant RESERVED_20_INDEX : integer := 8; constant RESERVED_24_INDEX : integer := 9; constant MM2S_LENGTH_INDEX : integer := 10; constant RESERVED_2C_INDEX : integer := 11; constant S2MM_DMACR_INDEX : integer := 12; constant S2MM_DMASR_INDEX : integer := 13; constant S2MM_CURDESC_LSB_INDEX : integer := 14; constant S2MM_CURDESC_MSB_INDEX : integer := 15; constant S2MM_TAILDESC_LSB_INDEX : integer := 16; constant S2MM_TAILDESC_MSB_INDEX : integer := 17; constant S2MM_DA_INDEX : integer := 18; constant S2MM_DA2_INDEX : integer := 19; constant RESERVED_50_INDEX : integer := 20; constant RESERVED_54_INDEX : integer := 21; --constant S2MM_LENGTH_INDEX : integer := 22; constant S2MM_LENGTH_INDEX : integer := 142; constant MM2S_DMACR_OFFSET : std_logic_vector(9 downto 0) := "0000000000"; -- 0x00 constant MM2S_DMASR_OFFSET : std_logic_vector(9 downto 0) := "0000000100"; -- 0x04 constant MM2S_CURDESC_LSB_OFFSET : std_logic_vector(9 downto 0) := "0000001000"; -- 0x08 constant MM2S_CURDESC_MSB_OFFSET : std_logic_vector(9 downto 0) := "0000001100"; -- 0x0C constant MM2S_TAILDESC_LSB_OFFSET : std_logic_vector(9 downto 0) := "0000010000"; -- 0x10 constant MM2S_TAILDESC_MSB_OFFSET : std_logic_vector(9 downto 0) := "0000010100"; -- 0x14 constant MM2S_SA_OFFSET : std_logic_vector(9 downto 0) := "0000011000"; -- 0x18 constant MM2S_SA2_OFFSET : std_logic_vector(9 downto 0) := "0000011100"; -- 0x1C constant RESERVED_20_OFFSET : std_logic_vector(9 downto 0) := "0000100000"; -- 0x20 constant RESERVED_24_OFFSET : std_logic_vector(9 downto 0) := "0000100100"; -- 0x24 constant MM2S_LENGTH_OFFSET : std_logic_vector(9 downto 0) := "0000101000"; -- 0x28 -- Following was reserved, now is used for SG xCache and xUser constant SGCTL_OFFSET : std_logic_vector(9 downto 0) := "0000101100"; -- 0x2C constant S2MM_DMACR_OFFSET : std_logic_vector(9 downto 0) := "0000110000"; -- 0x30 constant S2MM_DMASR_OFFSET : std_logic_vector(9 downto 0) := "0000110100"; -- 0x34 constant S2MM_CURDESC_LSB_OFFSET : std_logic_vector(9 downto 0) := "0000111000"; -- 0x38 constant S2MM_CURDESC_MSB_OFFSET : std_logic_vector(9 downto 0) := "0000111100"; -- 0x3C constant S2MM_TAILDESC_LSB_OFFSET : std_logic_vector(9 downto 0) := "0001000000"; -- 0x40 constant S2MM_TAILDESC_MSB_OFFSET : std_logic_vector(9 downto 0) := "0001000100"; -- 0x44 constant S2MM_DA_OFFSET : std_logic_vector(9 downto 0) := "0001001000"; -- 0x48 --CR603034 constant S2MM_DA2_OFFSET : std_logic_vector(9 downto 0) := "0001001100"; -- 0x4C constant RESERVED_50_OFFSET : std_logic_vector(9 downto 0) := "0001010000"; -- 0x50 constant RESERVED_54_OFFSET : std_logic_vector(9 downto 0) := "0001010100"; -- 0x54 constant S2MM_LENGTH_OFFSET : std_logic_vector(9 downto 0) := "0001011000"; -- 0x58 -- New registers for S2MM channels constant S2MM_CURDESC1_LSB_OFFSET : std_logic_vector(9 downto 0) := "0001110000"; -- 0x70 constant S2MM_CURDESC1_MSB_OFFSET : std_logic_vector(9 downto 0) := "0001110100"; -- 0x74 constant S2MM_TAILDESC1_LSB_OFFSET : std_logic_vector(9 downto 0) := "0001111000"; -- 0x78 constant S2MM_TAILDESC1_MSB_OFFSET : std_logic_vector(9 downto 0) := "0001111100"; -- 0x7C constant S2MM_CURDESC2_LSB_OFFSET : std_logic_vector(9 downto 0) := "0010010000"; -- 0x90 constant S2MM_CURDESC2_MSB_OFFSET : std_logic_vector(9 downto 0) := "0010010100"; -- 0x94 constant S2MM_TAILDESC2_LSB_OFFSET : std_logic_vector(9 downto 0) := "0010011000"; -- 0x98 constant S2MM_TAILDESC2_MSB_OFFSET : std_logic_vector(9 downto 0) := "0010011100"; -- 0x9C constant S2MM_CURDESC3_LSB_OFFSET : std_logic_vector(9 downto 0) := "0010110000"; -- 0xB0 constant S2MM_CURDESC3_MSB_OFFSET : std_logic_vector(9 downto 0) := "0010110100"; -- 0xB4 constant S2MM_TAILDESC3_LSB_OFFSET : std_logic_vector(9 downto 0) := "0010111000"; -- 0xB8 constant S2MM_TAILDESC3_MSB_OFFSET : std_logic_vector(9 downto 0) := "0010111100"; -- 0xBC constant S2MM_CURDESC4_LSB_OFFSET : std_logic_vector(9 downto 0) := "0011010000"; -- 0xD0 constant S2MM_CURDESC4_MSB_OFFSET : std_logic_vector(9 downto 0) := "0011010100"; -- 0xD4 constant S2MM_TAILDESC4_LSB_OFFSET : std_logic_vector(9 downto 0) := "0011011000"; -- 0xD8 constant S2MM_TAILDESC4_MSB_OFFSET : std_logic_vector(9 downto 0) := "0011011100"; -- 0xDC constant S2MM_CURDESC5_LSB_OFFSET : std_logic_vector(9 downto 0) := "0011110000"; -- 0xF0 constant S2MM_CURDESC5_MSB_OFFSET : std_logic_vector(9 downto 0) := "0011110100"; -- 0xF4 constant S2MM_TAILDESC5_LSB_OFFSET : std_logic_vector(9 downto 0) := "0011111000"; -- 0xF8 constant S2MM_TAILDESC5_MSB_OFFSET : std_logic_vector(9 downto 0) := "0011111100"; -- 0xFC constant S2MM_CURDESC6_LSB_OFFSET : std_logic_vector(9 downto 0) := "0100010000"; -- 0x110 constant S2MM_CURDESC6_MSB_OFFSET : std_logic_vector(9 downto 0) := "0100010100"; -- 0x114 constant S2MM_TAILDESC6_LSB_OFFSET : std_logic_vector(9 downto 0) := "0100011000"; -- 0x118 constant S2MM_TAILDESC6_MSB_OFFSET : std_logic_vector(9 downto 0) := "0100011100"; -- 0x11C constant S2MM_CURDESC7_LSB_OFFSET : std_logic_vector(9 downto 0) := "0100110000"; -- 0x130 constant S2MM_CURDESC7_MSB_OFFSET : std_logic_vector(9 downto 0) := "0100110100"; -- 0x134 constant S2MM_TAILDESC7_LSB_OFFSET : std_logic_vector(9 downto 0) := "0100111000"; -- 0x138 constant S2MM_TAILDESC7_MSB_OFFSET : std_logic_vector(9 downto 0) := "0100111100"; -- 0x13C constant S2MM_CURDESC8_LSB_OFFSET : std_logic_vector(9 downto 0) := "0101010000"; -- 0x150 constant S2MM_CURDESC8_MSB_OFFSET : std_logic_vector(9 downto 0) := "0101010100"; -- 0x154 constant S2MM_TAILDESC8_LSB_OFFSET : std_logic_vector(9 downto 0) := "0101011000"; -- 0x158 constant S2MM_TAILDESC8_MSB_OFFSET : std_logic_vector(9 downto 0) := "0101011100"; -- 0x15C constant S2MM_CURDESC9_LSB_OFFSET : std_logic_vector(9 downto 0) := "0101110000"; -- 0x170 constant S2MM_CURDESC9_MSB_OFFSET : std_logic_vector(9 downto 0) := "0101110100"; -- 0x174 constant S2MM_TAILDESC9_LSB_OFFSET : std_logic_vector(9 downto 0) := "0101111000"; -- 0x178 constant S2MM_TAILDESC9_MSB_OFFSET : std_logic_vector(9 downto 0) := "0101111100"; -- 0x17C constant S2MM_CURDESC10_LSB_OFFSET : std_logic_vector(9 downto 0) := "0110010000"; -- 0x190 constant S2MM_CURDESC10_MSB_OFFSET : std_logic_vector(9 downto 0) := "0110010100"; -- 0x194 constant S2MM_TAILDESC10_LSB_OFFSET : std_logic_vector(9 downto 0) := "0110011000"; -- 0x198 constant S2MM_TAILDESC10_MSB_OFFSET : std_logic_vector(9 downto 0) := "0110011100"; -- 0x19C constant S2MM_CURDESC11_LSB_OFFSET : std_logic_vector(9 downto 0) := "0110110000"; -- 0x1B0 constant S2MM_CURDESC11_MSB_OFFSET : std_logic_vector(9 downto 0) := "0110110100"; -- 0x1B4 constant S2MM_TAILDESC11_LSB_OFFSET : std_logic_vector(9 downto 0) := "0110111000"; -- 0x1B8 constant S2MM_TAILDESC11_MSB_OFFSET : std_logic_vector(9 downto 0) := "0110111100"; -- 0x1BC constant S2MM_CURDESC12_LSB_OFFSET : std_logic_vector(9 downto 0) := "0111010000"; -- 0x1D0 constant S2MM_CURDESC12_MSB_OFFSET : std_logic_vector(9 downto 0) := "0111010100"; -- 0x1D4 constant S2MM_TAILDESC12_LSB_OFFSET : std_logic_vector(9 downto 0) := "0111011000"; -- 0x1D8 constant S2MM_TAILDESC12_MSB_OFFSET : std_logic_vector(9 downto 0) := "0111011100"; -- 0x1DC constant S2MM_CURDESC13_LSB_OFFSET : std_logic_vector(9 downto 0) := "0111110000"; -- 0x1F0 constant S2MM_CURDESC13_MSB_OFFSET : std_logic_vector(9 downto 0) := "0111110100"; -- 0x1F4 constant S2MM_TAILDESC13_LSB_OFFSET : std_logic_vector(9 downto 0) := "0111111000"; -- 0x1F8 constant S2MM_TAILDESC13_MSB_OFFSET : std_logic_vector(9 downto 0) := "0111111100"; -- 0x1FC constant S2MM_CURDESC14_LSB_OFFSET : std_logic_vector(9 downto 0) := "1000010000"; -- 0x210 constant S2MM_CURDESC14_MSB_OFFSET : std_logic_vector(9 downto 0) := "1000010100"; -- 0x214 constant S2MM_TAILDESC14_LSB_OFFSET : std_logic_vector(9 downto 0) := "1000011000"; -- 0x218 constant S2MM_TAILDESC14_MSB_OFFSET : std_logic_vector(9 downto 0) := "1000011100"; -- 0x21C constant S2MM_CURDESC15_LSB_OFFSET : std_logic_vector(9 downto 0) := "1000110000"; -- 0x230 constant S2MM_CURDESC15_MSB_OFFSET : std_logic_vector(9 downto 0) := "1000110100"; -- 0x234 constant S2MM_TAILDESC15_LSB_OFFSET : std_logic_vector(9 downto 0) := "1000111000"; -- 0x238 constant S2MM_TAILDESC15_MSB_OFFSET : std_logic_vector(9 downto 0) := "1000111100"; -- 0x23C ------------------------------------------------------------------------------- -- Register Bit Constants ------------------------------------------------------------------------------- -- DMACR constant DMACR_RS_BIT : integer := 0; constant DMACR_TAILPEN_BIT : integer := 1; constant DMACR_RESET_BIT : integer := 2; constant DMACR_KH_BIT : integer := 3; constant CYCLIC_BIT : integer := 4; --constant DMACR_RESERVED3_BIT : integer := 3; --constant DMACR_RESERVED4_BIT : integer := 4; constant DMACR_RESERVED5_BIT : integer := 5; constant DMACR_RESERVED6_BIT : integer := 6; constant DMACR_RESERVED7_BIT : integer := 7; constant DMACR_RESERVED8_BIT : integer := 8; constant DMACR_RESERVED9_BIT : integer := 9; constant DMACR_RESERVED10_BIT : integer := 10; constant DMACR_RESERVED11_BIT : integer := 11; constant DMACR_IOC_IRQEN_BIT : integer := 12; constant DMACR_DLY_IRQEN_BIT : integer := 13; constant DMACR_ERR_IRQEN_BIT : integer := 14; constant DMACR_RESERVED15_BIT : integer := 15; constant DMACR_IRQTHRESH_LSB_BIT : integer := 16; constant DMACR_IRQTHRESH_MSB_BIT : integer := 23; constant DMACR_IRQDELAY_LSB_BIT : integer := 24; constant DMACR_IRQDELAY_MSB_BIT : integer := 31; -- DMASR constant DMASR_HALTED_BIT : integer := 0; constant DMASR_IDLE_BIT : integer := 1; constant DMASR_CMPLT_BIT : integer := 2; constant DMASR_ERROR_BIT : integer := 3; constant DMASR_DMAINTERR_BIT : integer := 4; constant DMASR_DMASLVERR_BIT : integer := 5; constant DMASR_DMADECERR_BIT : integer := 6; constant DMASR_RESERVED7_BIT : integer := 7; constant DMASR_SGINTERR_BIT : integer := 8; constant DMASR_SGSLVERR_BIT : integer := 9; constant DMASR_SGDECERR_BIT : integer := 10; constant DMASR_RESERVED11_BIT : integer := 11; constant DMASR_IOCIRQ_BIT : integer := 12; constant DMASR_DLYIRQ_BIT : integer := 13; constant DMASR_ERRIRQ_BIT : integer := 14; constant DMASR_RESERVED15_BIT : integer := 15; constant DMASR_IRQTHRESH_LSB_BIT : integer := 16; constant DMASR_IRQTHRESH_MSB_BIT : integer := 23; constant DMASR_IRQDELAY_LSB_BIT : integer := 24; constant DMASR_IRQDELAY_MSB_BIT : integer := 31; -- CURDESC constant CURDESC_LOWER_MSB_BIT : integer := 31; constant CURDESC_LOWER_LSB_BIT : integer := 6; constant CURDESC_RESERVED_BIT5 : integer := 5; constant CURDESC_RESERVED_BIT4 : integer := 4; constant CURDESC_RESERVED_BIT3 : integer := 3; constant CURDESC_RESERVED_BIT2 : integer := 2; constant CURDESC_RESERVED_BIT1 : integer := 1; constant CURDESC_RESERVED_BIT0 : integer := 0; -- TAILDESC constant TAILDESC_LOWER_MSB_BIT : integer := 31; constant TAILDESC_LOWER_LSB_BIT : integer := 6; constant TAILDESC_RESERVED_BIT5 : integer := 5; constant TAILDESC_RESERVED_BIT4 : integer := 4; constant TAILDESC_RESERVED_BIT3 : integer := 3; constant TAILDESC_RESERVED_BIT2 : integer := 2; constant TAILDESC_RESERVED_BIT1 : integer := 1; constant TAILDESC_RESERVED_BIT0 : integer := 0; -- DataMover Command / Status Constants constant DATAMOVER_CMDDONE_BIT : integer := 7; constant DATAMOVER_SLVERR_BIT : integer := 6; constant DATAMOVER_DECERR_BIT : integer := 5; constant DATAMOVER_INTERR_BIT : integer := 4; constant DATAMOVER_TAGMSB_BIT : integer := 3; constant DATAMOVER_TAGLSB_BIT : integer := 0; -- Descriptor Control Bits constant DESC_BLENGTH_LSB_BIT : integer := 0; constant DESC_BLENGTH_MSB_BIT : integer := 22; constant DESC_RSVD23_BIT : integer := 23; constant DESC_RSVD24_BIT : integer := 24; constant DESC_RSVD25_BIT : integer := 25; constant DESC_EOF_BIT : integer := 26; constant DESC_SOF_BIT : integer := 27; constant DESC_RSVD28_BIT : integer := 28; constant DESC_RSVD29_BIT : integer := 29; constant DESC_RSVD30_BIT : integer := 30; constant DESC_IOC_BIT : integer := 31; -- Descriptor Status Bits constant DESC_STS_CMPLTD_BIT : integer := 31; constant DESC_STS_DECERR_BIT : integer := 30; constant DESC_STS_SLVERR_BIT : integer := 29; constant DESC_STS_INTERR_BIT : integer := 28; constant DESC_STS_RXSOF_BIT : integer := 27; constant DESC_STS_RXEOF_BIT : integer := 26; constant DESC_STS_RSVD25_BIT : integer := 25; constant DESC_STS_RSVD24_BIT : integer := 24; constant DESC_STS_RSVD23_BIT : integer := 23; constant DESC_STS_XFRDBYTS_MSB_BIT : integer := 22; constant DESC_STS_XFRDBYTS_LSB_BIT : integer := 0; -- DataMover Command / Status Constants constant DATAMOVER_STS_CMDDONE_BIT : integer := 7; constant DATAMOVER_STS_SLVERR_BIT : integer := 6; constant DATAMOVER_STS_DECERR_BIT : integer := 5; constant DATAMOVER_STS_INTERR_BIT : integer := 4; constant DATAMOVER_STS_TAGMSB_BIT : integer := 3; constant DATAMOVER_STS_TAGLSB_BIT : integer := 0; constant DATAMOVER_STS_TAGEOF_BIT : integer := 1; constant DATAMOVER_STS_TLAST_BIT : integer := 31; constant DATAMOVER_CMD_BTTLSB_BIT : integer := 0; constant DATAMOVER_CMD_BTTMSB_BIT : integer := 22; constant DATAMOVER_CMD_TYPE_BIT : integer := 23; constant DATAMOVER_CMD_DSALSB_BIT : integer := 24; constant DATAMOVER_CMD_DSAMSB_BIT : integer := 29; constant DATAMOVER_CMD_EOF_BIT : integer := 30; constant DATAMOVER_CMD_DRR_BIT : integer := 31; constant DATAMOVER_CMD_ADDRLSB_BIT : integer := 32; -- Note: Bit offset require adding ADDR WIDTH to get to actual bit index constant DATAMOVER_CMD_ADDRMSB_BOFST: integer := 31; constant DATAMOVER_CMD_TAGLSB_BOFST : integer := 32; constant DATAMOVER_CMD_TAGMSB_BOFST : integer := 35; constant DATAMOVER_CMD_RSVLSB_BOFST : integer := 36; constant DATAMOVER_CMD_RSVMSB_BOFST : integer := 39; end axi_dma_pkg; ------------------------------------------------------------------------------- -- PACKAGE BODY ------------------------------------------------------------------------------- package body axi_dma_pkg is ------------------------------------------------------------------------------- -- Function to determine minimum bits required for BTT_SIZE field ------------------------------------------------------------------------------- function required_btt_width ( dwidth : integer; burst_size: integer; btt_width : integer) return integer is variable min_width : integer; begin min_width := clog2((dwidth/8)*burst_size)+1; if(min_width > btt_width)then return min_width; else return btt_width; end if; end function required_btt_width; ------------------------------------------------------------------------------- -- function to return Frequency Hertz parameter based on inclusion of sg engine ------------------------------------------------------------------------------- function hertz_prmtr_select(included : integer; lite_frequency : integer; sg_frequency : integer) return integer is begin -- 1 = Scatter Gather Included -- 0 = Scatter Gather Excluded if(included = 1)then return sg_frequency; else return lite_frequency; end if; end; ------------------------------------------------------------------------------- -- function to enable store and forward based on data width mismatch -- or directly enabled ------------------------------------------------------------------------------- function enable_snf (sf_enabled : integer; axi_data_width : integer; axis_tdata_width : integer) return integer is begin -- If store and forward enable or data widths do not -- match then return 1 to enable snf if( (sf_enabled = 1) or (axi_data_width /= axis_tdata_width))then return 1; else -- coverage off return 0; -- coverage on end if; end; end package body axi_dma_pkg;
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. ------------------------------------------------------------ ------------------------------------------------------------------------------- -- Filename: axi_dma_pkg.vhd -- Description: This package contains various constants and functions for -- AXI DMA operations. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library lib_pkg_v1_0_2; use lib_pkg_v1_0_2.lib_pkg.clog2; package axi_dma_pkg is ------------------------------------------------------------------------------- -- Function declarations ------------------------------------------------------------------------------- -- Find minimum required btt width function required_btt_width (dwidth : integer; burst_size : integer; btt_width : integer) return integer; -- Return correct hertz paramter value function hertz_prmtr_select(included : integer; lite_frequency : integer; sg_frequency : integer) return integer; -- Return SnF enable or disable function enable_snf (sf_enabled : integer; axi_data_width : integer; axis_tdata_width : integer) return integer; ------------------------------------------------------------------------------- -- Constant Declarations ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- AXI Responce Values ------------------------------------------------------------------------------- constant OKAY_RESP : std_logic_vector(1 downto 0) := "00"; constant EXOKAY_RESP : std_logic_vector(1 downto 0) := "01"; constant SLVERR_RESP : std_logic_vector(1 downto 0) := "10"; constant DECERR_RESP : std_logic_vector(1 downto 0) := "11"; constant MTBF_STAGES : integer := 4; constant C_FIFO_MTBF : integer := 4; ------------------------------------------------------------------------------- -- Misc Constants ------------------------------------------------------------------------------- --constant NUM_REG_TOTAL : integer := 18; --constant NUM_REG_TOTAL : integer := 23; constant NUM_REG_TOTAL : integer := 143; -- To accomodate S2MM registers --constant NUM_REG_PER_CHANNEL : integer := 6; constant NUM_REG_PER_CHANNEL : integer := 12; constant NUM_REG_PER_S2MM : integer := 120; --constant REG_MSB_ADDR_BIT : integer := clog2(NUM_REG_TOTAL)-1; constant CMD_BASE_WIDTH : integer := 40; constant BUFFER_LENGTH_WIDTH : integer := 23; -- Constants Used in Desc Updates constant DESC_STS_TYPE : std_logic := '1'; constant DESC_DATA_TYPE : std_logic := '0'; constant DESC_LAST : std_logic := '1'; constant DESC_NOT_LAST : std_logic := '0'; -- Interrupt Coalescing constant ZERO_THRESHOLD : std_logic_vector(7 downto 0) := (others => '0'); constant ONE_THRESHOLD : std_logic_vector(7 downto 0) := "00000001"; constant ZERO_DELAY : std_logic_vector(7 downto 0) := (others => '0'); ------------------------------------------------------------------------------- -- AXI Lite AXI DMA Register Offsets ------------------------------------------------------------------------------- constant MM2S_DMACR_INDEX : integer := 0; constant MM2S_DMASR_INDEX : integer := 1; constant MM2S_CURDESC_LSB_INDEX : integer := 2; constant MM2S_CURDESC_MSB_INDEX : integer := 3; constant MM2S_TAILDESC_LSB_INDEX : integer := 4; constant MM2S_TAILDESC_MSB_INDEX : integer := 5; constant MM2S_SA_INDEX : integer := 6; constant MM2S_SA2_INDEX : integer := 7; constant RESERVED_20_INDEX : integer := 8; constant RESERVED_24_INDEX : integer := 9; constant MM2S_LENGTH_INDEX : integer := 10; constant RESERVED_2C_INDEX : integer := 11; constant S2MM_DMACR_INDEX : integer := 12; constant S2MM_DMASR_INDEX : integer := 13; constant S2MM_CURDESC_LSB_INDEX : integer := 14; constant S2MM_CURDESC_MSB_INDEX : integer := 15; constant S2MM_TAILDESC_LSB_INDEX : integer := 16; constant S2MM_TAILDESC_MSB_INDEX : integer := 17; constant S2MM_DA_INDEX : integer := 18; constant S2MM_DA2_INDEX : integer := 19; constant RESERVED_50_INDEX : integer := 20; constant RESERVED_54_INDEX : integer := 21; --constant S2MM_LENGTH_INDEX : integer := 22; constant S2MM_LENGTH_INDEX : integer := 142; constant MM2S_DMACR_OFFSET : std_logic_vector(9 downto 0) := "0000000000"; -- 0x00 constant MM2S_DMASR_OFFSET : std_logic_vector(9 downto 0) := "0000000100"; -- 0x04 constant MM2S_CURDESC_LSB_OFFSET : std_logic_vector(9 downto 0) := "0000001000"; -- 0x08 constant MM2S_CURDESC_MSB_OFFSET : std_logic_vector(9 downto 0) := "0000001100"; -- 0x0C constant MM2S_TAILDESC_LSB_OFFSET : std_logic_vector(9 downto 0) := "0000010000"; -- 0x10 constant MM2S_TAILDESC_MSB_OFFSET : std_logic_vector(9 downto 0) := "0000010100"; -- 0x14 constant MM2S_SA_OFFSET : std_logic_vector(9 downto 0) := "0000011000"; -- 0x18 constant MM2S_SA2_OFFSET : std_logic_vector(9 downto 0) := "0000011100"; -- 0x1C constant RESERVED_20_OFFSET : std_logic_vector(9 downto 0) := "0000100000"; -- 0x20 constant RESERVED_24_OFFSET : std_logic_vector(9 downto 0) := "0000100100"; -- 0x24 constant MM2S_LENGTH_OFFSET : std_logic_vector(9 downto 0) := "0000101000"; -- 0x28 -- Following was reserved, now is used for SG xCache and xUser constant SGCTL_OFFSET : std_logic_vector(9 downto 0) := "0000101100"; -- 0x2C constant S2MM_DMACR_OFFSET : std_logic_vector(9 downto 0) := "0000110000"; -- 0x30 constant S2MM_DMASR_OFFSET : std_logic_vector(9 downto 0) := "0000110100"; -- 0x34 constant S2MM_CURDESC_LSB_OFFSET : std_logic_vector(9 downto 0) := "0000111000"; -- 0x38 constant S2MM_CURDESC_MSB_OFFSET : std_logic_vector(9 downto 0) := "0000111100"; -- 0x3C constant S2MM_TAILDESC_LSB_OFFSET : std_logic_vector(9 downto 0) := "0001000000"; -- 0x40 constant S2MM_TAILDESC_MSB_OFFSET : std_logic_vector(9 downto 0) := "0001000100"; -- 0x44 constant S2MM_DA_OFFSET : std_logic_vector(9 downto 0) := "0001001000"; -- 0x48 --CR603034 constant S2MM_DA2_OFFSET : std_logic_vector(9 downto 0) := "0001001100"; -- 0x4C constant RESERVED_50_OFFSET : std_logic_vector(9 downto 0) := "0001010000"; -- 0x50 constant RESERVED_54_OFFSET : std_logic_vector(9 downto 0) := "0001010100"; -- 0x54 constant S2MM_LENGTH_OFFSET : std_logic_vector(9 downto 0) := "0001011000"; -- 0x58 -- New registers for S2MM channels constant S2MM_CURDESC1_LSB_OFFSET : std_logic_vector(9 downto 0) := "0001110000"; -- 0x70 constant S2MM_CURDESC1_MSB_OFFSET : std_logic_vector(9 downto 0) := "0001110100"; -- 0x74 constant S2MM_TAILDESC1_LSB_OFFSET : std_logic_vector(9 downto 0) := "0001111000"; -- 0x78 constant S2MM_TAILDESC1_MSB_OFFSET : std_logic_vector(9 downto 0) := "0001111100"; -- 0x7C constant S2MM_CURDESC2_LSB_OFFSET : std_logic_vector(9 downto 0) := "0010010000"; -- 0x90 constant S2MM_CURDESC2_MSB_OFFSET : std_logic_vector(9 downto 0) := "0010010100"; -- 0x94 constant S2MM_TAILDESC2_LSB_OFFSET : std_logic_vector(9 downto 0) := "0010011000"; -- 0x98 constant S2MM_TAILDESC2_MSB_OFFSET : std_logic_vector(9 downto 0) := "0010011100"; -- 0x9C constant S2MM_CURDESC3_LSB_OFFSET : std_logic_vector(9 downto 0) := "0010110000"; -- 0xB0 constant S2MM_CURDESC3_MSB_OFFSET : std_logic_vector(9 downto 0) := "0010110100"; -- 0xB4 constant S2MM_TAILDESC3_LSB_OFFSET : std_logic_vector(9 downto 0) := "0010111000"; -- 0xB8 constant S2MM_TAILDESC3_MSB_OFFSET : std_logic_vector(9 downto 0) := "0010111100"; -- 0xBC constant S2MM_CURDESC4_LSB_OFFSET : std_logic_vector(9 downto 0) := "0011010000"; -- 0xD0 constant S2MM_CURDESC4_MSB_OFFSET : std_logic_vector(9 downto 0) := "0011010100"; -- 0xD4 constant S2MM_TAILDESC4_LSB_OFFSET : std_logic_vector(9 downto 0) := "0011011000"; -- 0xD8 constant S2MM_TAILDESC4_MSB_OFFSET : std_logic_vector(9 downto 0) := "0011011100"; -- 0xDC constant S2MM_CURDESC5_LSB_OFFSET : std_logic_vector(9 downto 0) := "0011110000"; -- 0xF0 constant S2MM_CURDESC5_MSB_OFFSET : std_logic_vector(9 downto 0) := "0011110100"; -- 0xF4 constant S2MM_TAILDESC5_LSB_OFFSET : std_logic_vector(9 downto 0) := "0011111000"; -- 0xF8 constant S2MM_TAILDESC5_MSB_OFFSET : std_logic_vector(9 downto 0) := "0011111100"; -- 0xFC constant S2MM_CURDESC6_LSB_OFFSET : std_logic_vector(9 downto 0) := "0100010000"; -- 0x110 constant S2MM_CURDESC6_MSB_OFFSET : std_logic_vector(9 downto 0) := "0100010100"; -- 0x114 constant S2MM_TAILDESC6_LSB_OFFSET : std_logic_vector(9 downto 0) := "0100011000"; -- 0x118 constant S2MM_TAILDESC6_MSB_OFFSET : std_logic_vector(9 downto 0) := "0100011100"; -- 0x11C constant S2MM_CURDESC7_LSB_OFFSET : std_logic_vector(9 downto 0) := "0100110000"; -- 0x130 constant S2MM_CURDESC7_MSB_OFFSET : std_logic_vector(9 downto 0) := "0100110100"; -- 0x134 constant S2MM_TAILDESC7_LSB_OFFSET : std_logic_vector(9 downto 0) := "0100111000"; -- 0x138 constant S2MM_TAILDESC7_MSB_OFFSET : std_logic_vector(9 downto 0) := "0100111100"; -- 0x13C constant S2MM_CURDESC8_LSB_OFFSET : std_logic_vector(9 downto 0) := "0101010000"; -- 0x150 constant S2MM_CURDESC8_MSB_OFFSET : std_logic_vector(9 downto 0) := "0101010100"; -- 0x154 constant S2MM_TAILDESC8_LSB_OFFSET : std_logic_vector(9 downto 0) := "0101011000"; -- 0x158 constant S2MM_TAILDESC8_MSB_OFFSET : std_logic_vector(9 downto 0) := "0101011100"; -- 0x15C constant S2MM_CURDESC9_LSB_OFFSET : std_logic_vector(9 downto 0) := "0101110000"; -- 0x170 constant S2MM_CURDESC9_MSB_OFFSET : std_logic_vector(9 downto 0) := "0101110100"; -- 0x174 constant S2MM_TAILDESC9_LSB_OFFSET : std_logic_vector(9 downto 0) := "0101111000"; -- 0x178 constant S2MM_TAILDESC9_MSB_OFFSET : std_logic_vector(9 downto 0) := "0101111100"; -- 0x17C constant S2MM_CURDESC10_LSB_OFFSET : std_logic_vector(9 downto 0) := "0110010000"; -- 0x190 constant S2MM_CURDESC10_MSB_OFFSET : std_logic_vector(9 downto 0) := "0110010100"; -- 0x194 constant S2MM_TAILDESC10_LSB_OFFSET : std_logic_vector(9 downto 0) := "0110011000"; -- 0x198 constant S2MM_TAILDESC10_MSB_OFFSET : std_logic_vector(9 downto 0) := "0110011100"; -- 0x19C constant S2MM_CURDESC11_LSB_OFFSET : std_logic_vector(9 downto 0) := "0110110000"; -- 0x1B0 constant S2MM_CURDESC11_MSB_OFFSET : std_logic_vector(9 downto 0) := "0110110100"; -- 0x1B4 constant S2MM_TAILDESC11_LSB_OFFSET : std_logic_vector(9 downto 0) := "0110111000"; -- 0x1B8 constant S2MM_TAILDESC11_MSB_OFFSET : std_logic_vector(9 downto 0) := "0110111100"; -- 0x1BC constant S2MM_CURDESC12_LSB_OFFSET : std_logic_vector(9 downto 0) := "0111010000"; -- 0x1D0 constant S2MM_CURDESC12_MSB_OFFSET : std_logic_vector(9 downto 0) := "0111010100"; -- 0x1D4 constant S2MM_TAILDESC12_LSB_OFFSET : std_logic_vector(9 downto 0) := "0111011000"; -- 0x1D8 constant S2MM_TAILDESC12_MSB_OFFSET : std_logic_vector(9 downto 0) := "0111011100"; -- 0x1DC constant S2MM_CURDESC13_LSB_OFFSET : std_logic_vector(9 downto 0) := "0111110000"; -- 0x1F0 constant S2MM_CURDESC13_MSB_OFFSET : std_logic_vector(9 downto 0) := "0111110100"; -- 0x1F4 constant S2MM_TAILDESC13_LSB_OFFSET : std_logic_vector(9 downto 0) := "0111111000"; -- 0x1F8 constant S2MM_TAILDESC13_MSB_OFFSET : std_logic_vector(9 downto 0) := "0111111100"; -- 0x1FC constant S2MM_CURDESC14_LSB_OFFSET : std_logic_vector(9 downto 0) := "1000010000"; -- 0x210 constant S2MM_CURDESC14_MSB_OFFSET : std_logic_vector(9 downto 0) := "1000010100"; -- 0x214 constant S2MM_TAILDESC14_LSB_OFFSET : std_logic_vector(9 downto 0) := "1000011000"; -- 0x218 constant S2MM_TAILDESC14_MSB_OFFSET : std_logic_vector(9 downto 0) := "1000011100"; -- 0x21C constant S2MM_CURDESC15_LSB_OFFSET : std_logic_vector(9 downto 0) := "1000110000"; -- 0x230 constant S2MM_CURDESC15_MSB_OFFSET : std_logic_vector(9 downto 0) := "1000110100"; -- 0x234 constant S2MM_TAILDESC15_LSB_OFFSET : std_logic_vector(9 downto 0) := "1000111000"; -- 0x238 constant S2MM_TAILDESC15_MSB_OFFSET : std_logic_vector(9 downto 0) := "1000111100"; -- 0x23C ------------------------------------------------------------------------------- -- Register Bit Constants ------------------------------------------------------------------------------- -- DMACR constant DMACR_RS_BIT : integer := 0; constant DMACR_TAILPEN_BIT : integer := 1; constant DMACR_RESET_BIT : integer := 2; constant DMACR_KH_BIT : integer := 3; constant CYCLIC_BIT : integer := 4; --constant DMACR_RESERVED3_BIT : integer := 3; --constant DMACR_RESERVED4_BIT : integer := 4; constant DMACR_RESERVED5_BIT : integer := 5; constant DMACR_RESERVED6_BIT : integer := 6; constant DMACR_RESERVED7_BIT : integer := 7; constant DMACR_RESERVED8_BIT : integer := 8; constant DMACR_RESERVED9_BIT : integer := 9; constant DMACR_RESERVED10_BIT : integer := 10; constant DMACR_RESERVED11_BIT : integer := 11; constant DMACR_IOC_IRQEN_BIT : integer := 12; constant DMACR_DLY_IRQEN_BIT : integer := 13; constant DMACR_ERR_IRQEN_BIT : integer := 14; constant DMACR_RESERVED15_BIT : integer := 15; constant DMACR_IRQTHRESH_LSB_BIT : integer := 16; constant DMACR_IRQTHRESH_MSB_BIT : integer := 23; constant DMACR_IRQDELAY_LSB_BIT : integer := 24; constant DMACR_IRQDELAY_MSB_BIT : integer := 31; -- DMASR constant DMASR_HALTED_BIT : integer := 0; constant DMASR_IDLE_BIT : integer := 1; constant DMASR_CMPLT_BIT : integer := 2; constant DMASR_ERROR_BIT : integer := 3; constant DMASR_DMAINTERR_BIT : integer := 4; constant DMASR_DMASLVERR_BIT : integer := 5; constant DMASR_DMADECERR_BIT : integer := 6; constant DMASR_RESERVED7_BIT : integer := 7; constant DMASR_SGINTERR_BIT : integer := 8; constant DMASR_SGSLVERR_BIT : integer := 9; constant DMASR_SGDECERR_BIT : integer := 10; constant DMASR_RESERVED11_BIT : integer := 11; constant DMASR_IOCIRQ_BIT : integer := 12; constant DMASR_DLYIRQ_BIT : integer := 13; constant DMASR_ERRIRQ_BIT : integer := 14; constant DMASR_RESERVED15_BIT : integer := 15; constant DMASR_IRQTHRESH_LSB_BIT : integer := 16; constant DMASR_IRQTHRESH_MSB_BIT : integer := 23; constant DMASR_IRQDELAY_LSB_BIT : integer := 24; constant DMASR_IRQDELAY_MSB_BIT : integer := 31; -- CURDESC constant CURDESC_LOWER_MSB_BIT : integer := 31; constant CURDESC_LOWER_LSB_BIT : integer := 6; constant CURDESC_RESERVED_BIT5 : integer := 5; constant CURDESC_RESERVED_BIT4 : integer := 4; constant CURDESC_RESERVED_BIT3 : integer := 3; constant CURDESC_RESERVED_BIT2 : integer := 2; constant CURDESC_RESERVED_BIT1 : integer := 1; constant CURDESC_RESERVED_BIT0 : integer := 0; -- TAILDESC constant TAILDESC_LOWER_MSB_BIT : integer := 31; constant TAILDESC_LOWER_LSB_BIT : integer := 6; constant TAILDESC_RESERVED_BIT5 : integer := 5; constant TAILDESC_RESERVED_BIT4 : integer := 4; constant TAILDESC_RESERVED_BIT3 : integer := 3; constant TAILDESC_RESERVED_BIT2 : integer := 2; constant TAILDESC_RESERVED_BIT1 : integer := 1; constant TAILDESC_RESERVED_BIT0 : integer := 0; -- DataMover Command / Status Constants constant DATAMOVER_CMDDONE_BIT : integer := 7; constant DATAMOVER_SLVERR_BIT : integer := 6; constant DATAMOVER_DECERR_BIT : integer := 5; constant DATAMOVER_INTERR_BIT : integer := 4; constant DATAMOVER_TAGMSB_BIT : integer := 3; constant DATAMOVER_TAGLSB_BIT : integer := 0; -- Descriptor Control Bits constant DESC_BLENGTH_LSB_BIT : integer := 0; constant DESC_BLENGTH_MSB_BIT : integer := 22; constant DESC_RSVD23_BIT : integer := 23; constant DESC_RSVD24_BIT : integer := 24; constant DESC_RSVD25_BIT : integer := 25; constant DESC_EOF_BIT : integer := 26; constant DESC_SOF_BIT : integer := 27; constant DESC_RSVD28_BIT : integer := 28; constant DESC_RSVD29_BIT : integer := 29; constant DESC_RSVD30_BIT : integer := 30; constant DESC_IOC_BIT : integer := 31; -- Descriptor Status Bits constant DESC_STS_CMPLTD_BIT : integer := 31; constant DESC_STS_DECERR_BIT : integer := 30; constant DESC_STS_SLVERR_BIT : integer := 29; constant DESC_STS_INTERR_BIT : integer := 28; constant DESC_STS_RXSOF_BIT : integer := 27; constant DESC_STS_RXEOF_BIT : integer := 26; constant DESC_STS_RSVD25_BIT : integer := 25; constant DESC_STS_RSVD24_BIT : integer := 24; constant DESC_STS_RSVD23_BIT : integer := 23; constant DESC_STS_XFRDBYTS_MSB_BIT : integer := 22; constant DESC_STS_XFRDBYTS_LSB_BIT : integer := 0; -- DataMover Command / Status Constants constant DATAMOVER_STS_CMDDONE_BIT : integer := 7; constant DATAMOVER_STS_SLVERR_BIT : integer := 6; constant DATAMOVER_STS_DECERR_BIT : integer := 5; constant DATAMOVER_STS_INTERR_BIT : integer := 4; constant DATAMOVER_STS_TAGMSB_BIT : integer := 3; constant DATAMOVER_STS_TAGLSB_BIT : integer := 0; constant DATAMOVER_STS_TAGEOF_BIT : integer := 1; constant DATAMOVER_STS_TLAST_BIT : integer := 31; constant DATAMOVER_CMD_BTTLSB_BIT : integer := 0; constant DATAMOVER_CMD_BTTMSB_BIT : integer := 22; constant DATAMOVER_CMD_TYPE_BIT : integer := 23; constant DATAMOVER_CMD_DSALSB_BIT : integer := 24; constant DATAMOVER_CMD_DSAMSB_BIT : integer := 29; constant DATAMOVER_CMD_EOF_BIT : integer := 30; constant DATAMOVER_CMD_DRR_BIT : integer := 31; constant DATAMOVER_CMD_ADDRLSB_BIT : integer := 32; -- Note: Bit offset require adding ADDR WIDTH to get to actual bit index constant DATAMOVER_CMD_ADDRMSB_BOFST: integer := 31; constant DATAMOVER_CMD_TAGLSB_BOFST : integer := 32; constant DATAMOVER_CMD_TAGMSB_BOFST : integer := 35; constant DATAMOVER_CMD_RSVLSB_BOFST : integer := 36; constant DATAMOVER_CMD_RSVMSB_BOFST : integer := 39; end axi_dma_pkg; ------------------------------------------------------------------------------- -- PACKAGE BODY ------------------------------------------------------------------------------- package body axi_dma_pkg is ------------------------------------------------------------------------------- -- Function to determine minimum bits required for BTT_SIZE field ------------------------------------------------------------------------------- function required_btt_width ( dwidth : integer; burst_size: integer; btt_width : integer) return integer is variable min_width : integer; begin min_width := clog2((dwidth/8)*burst_size)+1; if(min_width > btt_width)then return min_width; else return btt_width; end if; end function required_btt_width; ------------------------------------------------------------------------------- -- function to return Frequency Hertz parameter based on inclusion of sg engine ------------------------------------------------------------------------------- function hertz_prmtr_select(included : integer; lite_frequency : integer; sg_frequency : integer) return integer is begin -- 1 = Scatter Gather Included -- 0 = Scatter Gather Excluded if(included = 1)then return sg_frequency; else return lite_frequency; end if; end; ------------------------------------------------------------------------------- -- function to enable store and forward based on data width mismatch -- or directly enabled ------------------------------------------------------------------------------- function enable_snf (sf_enabled : integer; axi_data_width : integer; axis_tdata_width : integer) return integer is begin -- If store and forward enable or data widths do not -- match then return 1 to enable snf if( (sf_enabled = 1) or (axi_data_width /= axis_tdata_width))then return 1; else -- coverage off return 0; -- coverage on end if; end; end package body axi_dma_pkg;
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. ------------------------------------------------------------ ------------------------------------------------------------------------------- -- Filename: axi_dma_pkg.vhd -- Description: This package contains various constants and functions for -- AXI DMA operations. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library lib_pkg_v1_0_2; use lib_pkg_v1_0_2.lib_pkg.clog2; package axi_dma_pkg is ------------------------------------------------------------------------------- -- Function declarations ------------------------------------------------------------------------------- -- Find minimum required btt width function required_btt_width (dwidth : integer; burst_size : integer; btt_width : integer) return integer; -- Return correct hertz paramter value function hertz_prmtr_select(included : integer; lite_frequency : integer; sg_frequency : integer) return integer; -- Return SnF enable or disable function enable_snf (sf_enabled : integer; axi_data_width : integer; axis_tdata_width : integer) return integer; ------------------------------------------------------------------------------- -- Constant Declarations ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- AXI Responce Values ------------------------------------------------------------------------------- constant OKAY_RESP : std_logic_vector(1 downto 0) := "00"; constant EXOKAY_RESP : std_logic_vector(1 downto 0) := "01"; constant SLVERR_RESP : std_logic_vector(1 downto 0) := "10"; constant DECERR_RESP : std_logic_vector(1 downto 0) := "11"; constant MTBF_STAGES : integer := 4; constant C_FIFO_MTBF : integer := 4; ------------------------------------------------------------------------------- -- Misc Constants ------------------------------------------------------------------------------- --constant NUM_REG_TOTAL : integer := 18; --constant NUM_REG_TOTAL : integer := 23; constant NUM_REG_TOTAL : integer := 143; -- To accomodate S2MM registers --constant NUM_REG_PER_CHANNEL : integer := 6; constant NUM_REG_PER_CHANNEL : integer := 12; constant NUM_REG_PER_S2MM : integer := 120; --constant REG_MSB_ADDR_BIT : integer := clog2(NUM_REG_TOTAL)-1; constant CMD_BASE_WIDTH : integer := 40; constant BUFFER_LENGTH_WIDTH : integer := 23; -- Constants Used in Desc Updates constant DESC_STS_TYPE : std_logic := '1'; constant DESC_DATA_TYPE : std_logic := '0'; constant DESC_LAST : std_logic := '1'; constant DESC_NOT_LAST : std_logic := '0'; -- Interrupt Coalescing constant ZERO_THRESHOLD : std_logic_vector(7 downto 0) := (others => '0'); constant ONE_THRESHOLD : std_logic_vector(7 downto 0) := "00000001"; constant ZERO_DELAY : std_logic_vector(7 downto 0) := (others => '0'); ------------------------------------------------------------------------------- -- AXI Lite AXI DMA Register Offsets ------------------------------------------------------------------------------- constant MM2S_DMACR_INDEX : integer := 0; constant MM2S_DMASR_INDEX : integer := 1; constant MM2S_CURDESC_LSB_INDEX : integer := 2; constant MM2S_CURDESC_MSB_INDEX : integer := 3; constant MM2S_TAILDESC_LSB_INDEX : integer := 4; constant MM2S_TAILDESC_MSB_INDEX : integer := 5; constant MM2S_SA_INDEX : integer := 6; constant MM2S_SA2_INDEX : integer := 7; constant RESERVED_20_INDEX : integer := 8; constant RESERVED_24_INDEX : integer := 9; constant MM2S_LENGTH_INDEX : integer := 10; constant RESERVED_2C_INDEX : integer := 11; constant S2MM_DMACR_INDEX : integer := 12; constant S2MM_DMASR_INDEX : integer := 13; constant S2MM_CURDESC_LSB_INDEX : integer := 14; constant S2MM_CURDESC_MSB_INDEX : integer := 15; constant S2MM_TAILDESC_LSB_INDEX : integer := 16; constant S2MM_TAILDESC_MSB_INDEX : integer := 17; constant S2MM_DA_INDEX : integer := 18; constant S2MM_DA2_INDEX : integer := 19; constant RESERVED_50_INDEX : integer := 20; constant RESERVED_54_INDEX : integer := 21; --constant S2MM_LENGTH_INDEX : integer := 22; constant S2MM_LENGTH_INDEX : integer := 142; constant MM2S_DMACR_OFFSET : std_logic_vector(9 downto 0) := "0000000000"; -- 0x00 constant MM2S_DMASR_OFFSET : std_logic_vector(9 downto 0) := "0000000100"; -- 0x04 constant MM2S_CURDESC_LSB_OFFSET : std_logic_vector(9 downto 0) := "0000001000"; -- 0x08 constant MM2S_CURDESC_MSB_OFFSET : std_logic_vector(9 downto 0) := "0000001100"; -- 0x0C constant MM2S_TAILDESC_LSB_OFFSET : std_logic_vector(9 downto 0) := "0000010000"; -- 0x10 constant MM2S_TAILDESC_MSB_OFFSET : std_logic_vector(9 downto 0) := "0000010100"; -- 0x14 constant MM2S_SA_OFFSET : std_logic_vector(9 downto 0) := "0000011000"; -- 0x18 constant MM2S_SA2_OFFSET : std_logic_vector(9 downto 0) := "0000011100"; -- 0x1C constant RESERVED_20_OFFSET : std_logic_vector(9 downto 0) := "0000100000"; -- 0x20 constant RESERVED_24_OFFSET : std_logic_vector(9 downto 0) := "0000100100"; -- 0x24 constant MM2S_LENGTH_OFFSET : std_logic_vector(9 downto 0) := "0000101000"; -- 0x28 -- Following was reserved, now is used for SG xCache and xUser constant SGCTL_OFFSET : std_logic_vector(9 downto 0) := "0000101100"; -- 0x2C constant S2MM_DMACR_OFFSET : std_logic_vector(9 downto 0) := "0000110000"; -- 0x30 constant S2MM_DMASR_OFFSET : std_logic_vector(9 downto 0) := "0000110100"; -- 0x34 constant S2MM_CURDESC_LSB_OFFSET : std_logic_vector(9 downto 0) := "0000111000"; -- 0x38 constant S2MM_CURDESC_MSB_OFFSET : std_logic_vector(9 downto 0) := "0000111100"; -- 0x3C constant S2MM_TAILDESC_LSB_OFFSET : std_logic_vector(9 downto 0) := "0001000000"; -- 0x40 constant S2MM_TAILDESC_MSB_OFFSET : std_logic_vector(9 downto 0) := "0001000100"; -- 0x44 constant S2MM_DA_OFFSET : std_logic_vector(9 downto 0) := "0001001000"; -- 0x48 --CR603034 constant S2MM_DA2_OFFSET : std_logic_vector(9 downto 0) := "0001001100"; -- 0x4C constant RESERVED_50_OFFSET : std_logic_vector(9 downto 0) := "0001010000"; -- 0x50 constant RESERVED_54_OFFSET : std_logic_vector(9 downto 0) := "0001010100"; -- 0x54 constant S2MM_LENGTH_OFFSET : std_logic_vector(9 downto 0) := "0001011000"; -- 0x58 -- New registers for S2MM channels constant S2MM_CURDESC1_LSB_OFFSET : std_logic_vector(9 downto 0) := "0001110000"; -- 0x70 constant S2MM_CURDESC1_MSB_OFFSET : std_logic_vector(9 downto 0) := "0001110100"; -- 0x74 constant S2MM_TAILDESC1_LSB_OFFSET : std_logic_vector(9 downto 0) := "0001111000"; -- 0x78 constant S2MM_TAILDESC1_MSB_OFFSET : std_logic_vector(9 downto 0) := "0001111100"; -- 0x7C constant S2MM_CURDESC2_LSB_OFFSET : std_logic_vector(9 downto 0) := "0010010000"; -- 0x90 constant S2MM_CURDESC2_MSB_OFFSET : std_logic_vector(9 downto 0) := "0010010100"; -- 0x94 constant S2MM_TAILDESC2_LSB_OFFSET : std_logic_vector(9 downto 0) := "0010011000"; -- 0x98 constant S2MM_TAILDESC2_MSB_OFFSET : std_logic_vector(9 downto 0) := "0010011100"; -- 0x9C constant S2MM_CURDESC3_LSB_OFFSET : std_logic_vector(9 downto 0) := "0010110000"; -- 0xB0 constant S2MM_CURDESC3_MSB_OFFSET : std_logic_vector(9 downto 0) := "0010110100"; -- 0xB4 constant S2MM_TAILDESC3_LSB_OFFSET : std_logic_vector(9 downto 0) := "0010111000"; -- 0xB8 constant S2MM_TAILDESC3_MSB_OFFSET : std_logic_vector(9 downto 0) := "0010111100"; -- 0xBC constant S2MM_CURDESC4_LSB_OFFSET : std_logic_vector(9 downto 0) := "0011010000"; -- 0xD0 constant S2MM_CURDESC4_MSB_OFFSET : std_logic_vector(9 downto 0) := "0011010100"; -- 0xD4 constant S2MM_TAILDESC4_LSB_OFFSET : std_logic_vector(9 downto 0) := "0011011000"; -- 0xD8 constant S2MM_TAILDESC4_MSB_OFFSET : std_logic_vector(9 downto 0) := "0011011100"; -- 0xDC constant S2MM_CURDESC5_LSB_OFFSET : std_logic_vector(9 downto 0) := "0011110000"; -- 0xF0 constant S2MM_CURDESC5_MSB_OFFSET : std_logic_vector(9 downto 0) := "0011110100"; -- 0xF4 constant S2MM_TAILDESC5_LSB_OFFSET : std_logic_vector(9 downto 0) := "0011111000"; -- 0xF8 constant S2MM_TAILDESC5_MSB_OFFSET : std_logic_vector(9 downto 0) := "0011111100"; -- 0xFC constant S2MM_CURDESC6_LSB_OFFSET : std_logic_vector(9 downto 0) := "0100010000"; -- 0x110 constant S2MM_CURDESC6_MSB_OFFSET : std_logic_vector(9 downto 0) := "0100010100"; -- 0x114 constant S2MM_TAILDESC6_LSB_OFFSET : std_logic_vector(9 downto 0) := "0100011000"; -- 0x118 constant S2MM_TAILDESC6_MSB_OFFSET : std_logic_vector(9 downto 0) := "0100011100"; -- 0x11C constant S2MM_CURDESC7_LSB_OFFSET : std_logic_vector(9 downto 0) := "0100110000"; -- 0x130 constant S2MM_CURDESC7_MSB_OFFSET : std_logic_vector(9 downto 0) := "0100110100"; -- 0x134 constant S2MM_TAILDESC7_LSB_OFFSET : std_logic_vector(9 downto 0) := "0100111000"; -- 0x138 constant S2MM_TAILDESC7_MSB_OFFSET : std_logic_vector(9 downto 0) := "0100111100"; -- 0x13C constant S2MM_CURDESC8_LSB_OFFSET : std_logic_vector(9 downto 0) := "0101010000"; -- 0x150 constant S2MM_CURDESC8_MSB_OFFSET : std_logic_vector(9 downto 0) := "0101010100"; -- 0x154 constant S2MM_TAILDESC8_LSB_OFFSET : std_logic_vector(9 downto 0) := "0101011000"; -- 0x158 constant S2MM_TAILDESC8_MSB_OFFSET : std_logic_vector(9 downto 0) := "0101011100"; -- 0x15C constant S2MM_CURDESC9_LSB_OFFSET : std_logic_vector(9 downto 0) := "0101110000"; -- 0x170 constant S2MM_CURDESC9_MSB_OFFSET : std_logic_vector(9 downto 0) := "0101110100"; -- 0x174 constant S2MM_TAILDESC9_LSB_OFFSET : std_logic_vector(9 downto 0) := "0101111000"; -- 0x178 constant S2MM_TAILDESC9_MSB_OFFSET : std_logic_vector(9 downto 0) := "0101111100"; -- 0x17C constant S2MM_CURDESC10_LSB_OFFSET : std_logic_vector(9 downto 0) := "0110010000"; -- 0x190 constant S2MM_CURDESC10_MSB_OFFSET : std_logic_vector(9 downto 0) := "0110010100"; -- 0x194 constant S2MM_TAILDESC10_LSB_OFFSET : std_logic_vector(9 downto 0) := "0110011000"; -- 0x198 constant S2MM_TAILDESC10_MSB_OFFSET : std_logic_vector(9 downto 0) := "0110011100"; -- 0x19C constant S2MM_CURDESC11_LSB_OFFSET : std_logic_vector(9 downto 0) := "0110110000"; -- 0x1B0 constant S2MM_CURDESC11_MSB_OFFSET : std_logic_vector(9 downto 0) := "0110110100"; -- 0x1B4 constant S2MM_TAILDESC11_LSB_OFFSET : std_logic_vector(9 downto 0) := "0110111000"; -- 0x1B8 constant S2MM_TAILDESC11_MSB_OFFSET : std_logic_vector(9 downto 0) := "0110111100"; -- 0x1BC constant S2MM_CURDESC12_LSB_OFFSET : std_logic_vector(9 downto 0) := "0111010000"; -- 0x1D0 constant S2MM_CURDESC12_MSB_OFFSET : std_logic_vector(9 downto 0) := "0111010100"; -- 0x1D4 constant S2MM_TAILDESC12_LSB_OFFSET : std_logic_vector(9 downto 0) := "0111011000"; -- 0x1D8 constant S2MM_TAILDESC12_MSB_OFFSET : std_logic_vector(9 downto 0) := "0111011100"; -- 0x1DC constant S2MM_CURDESC13_LSB_OFFSET : std_logic_vector(9 downto 0) := "0111110000"; -- 0x1F0 constant S2MM_CURDESC13_MSB_OFFSET : std_logic_vector(9 downto 0) := "0111110100"; -- 0x1F4 constant S2MM_TAILDESC13_LSB_OFFSET : std_logic_vector(9 downto 0) := "0111111000"; -- 0x1F8 constant S2MM_TAILDESC13_MSB_OFFSET : std_logic_vector(9 downto 0) := "0111111100"; -- 0x1FC constant S2MM_CURDESC14_LSB_OFFSET : std_logic_vector(9 downto 0) := "1000010000"; -- 0x210 constant S2MM_CURDESC14_MSB_OFFSET : std_logic_vector(9 downto 0) := "1000010100"; -- 0x214 constant S2MM_TAILDESC14_LSB_OFFSET : std_logic_vector(9 downto 0) := "1000011000"; -- 0x218 constant S2MM_TAILDESC14_MSB_OFFSET : std_logic_vector(9 downto 0) := "1000011100"; -- 0x21C constant S2MM_CURDESC15_LSB_OFFSET : std_logic_vector(9 downto 0) := "1000110000"; -- 0x230 constant S2MM_CURDESC15_MSB_OFFSET : std_logic_vector(9 downto 0) := "1000110100"; -- 0x234 constant S2MM_TAILDESC15_LSB_OFFSET : std_logic_vector(9 downto 0) := "1000111000"; -- 0x238 constant S2MM_TAILDESC15_MSB_OFFSET : std_logic_vector(9 downto 0) := "1000111100"; -- 0x23C ------------------------------------------------------------------------------- -- Register Bit Constants ------------------------------------------------------------------------------- -- DMACR constant DMACR_RS_BIT : integer := 0; constant DMACR_TAILPEN_BIT : integer := 1; constant DMACR_RESET_BIT : integer := 2; constant DMACR_KH_BIT : integer := 3; constant CYCLIC_BIT : integer := 4; --constant DMACR_RESERVED3_BIT : integer := 3; --constant DMACR_RESERVED4_BIT : integer := 4; constant DMACR_RESERVED5_BIT : integer := 5; constant DMACR_RESERVED6_BIT : integer := 6; constant DMACR_RESERVED7_BIT : integer := 7; constant DMACR_RESERVED8_BIT : integer := 8; constant DMACR_RESERVED9_BIT : integer := 9; constant DMACR_RESERVED10_BIT : integer := 10; constant DMACR_RESERVED11_BIT : integer := 11; constant DMACR_IOC_IRQEN_BIT : integer := 12; constant DMACR_DLY_IRQEN_BIT : integer := 13; constant DMACR_ERR_IRQEN_BIT : integer := 14; constant DMACR_RESERVED15_BIT : integer := 15; constant DMACR_IRQTHRESH_LSB_BIT : integer := 16; constant DMACR_IRQTHRESH_MSB_BIT : integer := 23; constant DMACR_IRQDELAY_LSB_BIT : integer := 24; constant DMACR_IRQDELAY_MSB_BIT : integer := 31; -- DMASR constant DMASR_HALTED_BIT : integer := 0; constant DMASR_IDLE_BIT : integer := 1; constant DMASR_CMPLT_BIT : integer := 2; constant DMASR_ERROR_BIT : integer := 3; constant DMASR_DMAINTERR_BIT : integer := 4; constant DMASR_DMASLVERR_BIT : integer := 5; constant DMASR_DMADECERR_BIT : integer := 6; constant DMASR_RESERVED7_BIT : integer := 7; constant DMASR_SGINTERR_BIT : integer := 8; constant DMASR_SGSLVERR_BIT : integer := 9; constant DMASR_SGDECERR_BIT : integer := 10; constant DMASR_RESERVED11_BIT : integer := 11; constant DMASR_IOCIRQ_BIT : integer := 12; constant DMASR_DLYIRQ_BIT : integer := 13; constant DMASR_ERRIRQ_BIT : integer := 14; constant DMASR_RESERVED15_BIT : integer := 15; constant DMASR_IRQTHRESH_LSB_BIT : integer := 16; constant DMASR_IRQTHRESH_MSB_BIT : integer := 23; constant DMASR_IRQDELAY_LSB_BIT : integer := 24; constant DMASR_IRQDELAY_MSB_BIT : integer := 31; -- CURDESC constant CURDESC_LOWER_MSB_BIT : integer := 31; constant CURDESC_LOWER_LSB_BIT : integer := 6; constant CURDESC_RESERVED_BIT5 : integer := 5; constant CURDESC_RESERVED_BIT4 : integer := 4; constant CURDESC_RESERVED_BIT3 : integer := 3; constant CURDESC_RESERVED_BIT2 : integer := 2; constant CURDESC_RESERVED_BIT1 : integer := 1; constant CURDESC_RESERVED_BIT0 : integer := 0; -- TAILDESC constant TAILDESC_LOWER_MSB_BIT : integer := 31; constant TAILDESC_LOWER_LSB_BIT : integer := 6; constant TAILDESC_RESERVED_BIT5 : integer := 5; constant TAILDESC_RESERVED_BIT4 : integer := 4; constant TAILDESC_RESERVED_BIT3 : integer := 3; constant TAILDESC_RESERVED_BIT2 : integer := 2; constant TAILDESC_RESERVED_BIT1 : integer := 1; constant TAILDESC_RESERVED_BIT0 : integer := 0; -- DataMover Command / Status Constants constant DATAMOVER_CMDDONE_BIT : integer := 7; constant DATAMOVER_SLVERR_BIT : integer := 6; constant DATAMOVER_DECERR_BIT : integer := 5; constant DATAMOVER_INTERR_BIT : integer := 4; constant DATAMOVER_TAGMSB_BIT : integer := 3; constant DATAMOVER_TAGLSB_BIT : integer := 0; -- Descriptor Control Bits constant DESC_BLENGTH_LSB_BIT : integer := 0; constant DESC_BLENGTH_MSB_BIT : integer := 22; constant DESC_RSVD23_BIT : integer := 23; constant DESC_RSVD24_BIT : integer := 24; constant DESC_RSVD25_BIT : integer := 25; constant DESC_EOF_BIT : integer := 26; constant DESC_SOF_BIT : integer := 27; constant DESC_RSVD28_BIT : integer := 28; constant DESC_RSVD29_BIT : integer := 29; constant DESC_RSVD30_BIT : integer := 30; constant DESC_IOC_BIT : integer := 31; -- Descriptor Status Bits constant DESC_STS_CMPLTD_BIT : integer := 31; constant DESC_STS_DECERR_BIT : integer := 30; constant DESC_STS_SLVERR_BIT : integer := 29; constant DESC_STS_INTERR_BIT : integer := 28; constant DESC_STS_RXSOF_BIT : integer := 27; constant DESC_STS_RXEOF_BIT : integer := 26; constant DESC_STS_RSVD25_BIT : integer := 25; constant DESC_STS_RSVD24_BIT : integer := 24; constant DESC_STS_RSVD23_BIT : integer := 23; constant DESC_STS_XFRDBYTS_MSB_BIT : integer := 22; constant DESC_STS_XFRDBYTS_LSB_BIT : integer := 0; -- DataMover Command / Status Constants constant DATAMOVER_STS_CMDDONE_BIT : integer := 7; constant DATAMOVER_STS_SLVERR_BIT : integer := 6; constant DATAMOVER_STS_DECERR_BIT : integer := 5; constant DATAMOVER_STS_INTERR_BIT : integer := 4; constant DATAMOVER_STS_TAGMSB_BIT : integer := 3; constant DATAMOVER_STS_TAGLSB_BIT : integer := 0; constant DATAMOVER_STS_TAGEOF_BIT : integer := 1; constant DATAMOVER_STS_TLAST_BIT : integer := 31; constant DATAMOVER_CMD_BTTLSB_BIT : integer := 0; constant DATAMOVER_CMD_BTTMSB_BIT : integer := 22; constant DATAMOVER_CMD_TYPE_BIT : integer := 23; constant DATAMOVER_CMD_DSALSB_BIT : integer := 24; constant DATAMOVER_CMD_DSAMSB_BIT : integer := 29; constant DATAMOVER_CMD_EOF_BIT : integer := 30; constant DATAMOVER_CMD_DRR_BIT : integer := 31; constant DATAMOVER_CMD_ADDRLSB_BIT : integer := 32; -- Note: Bit offset require adding ADDR WIDTH to get to actual bit index constant DATAMOVER_CMD_ADDRMSB_BOFST: integer := 31; constant DATAMOVER_CMD_TAGLSB_BOFST : integer := 32; constant DATAMOVER_CMD_TAGMSB_BOFST : integer := 35; constant DATAMOVER_CMD_RSVLSB_BOFST : integer := 36; constant DATAMOVER_CMD_RSVMSB_BOFST : integer := 39; end axi_dma_pkg; ------------------------------------------------------------------------------- -- PACKAGE BODY ------------------------------------------------------------------------------- package body axi_dma_pkg is ------------------------------------------------------------------------------- -- Function to determine minimum bits required for BTT_SIZE field ------------------------------------------------------------------------------- function required_btt_width ( dwidth : integer; burst_size: integer; btt_width : integer) return integer is variable min_width : integer; begin min_width := clog2((dwidth/8)*burst_size)+1; if(min_width > btt_width)then return min_width; else return btt_width; end if; end function required_btt_width; ------------------------------------------------------------------------------- -- function to return Frequency Hertz parameter based on inclusion of sg engine ------------------------------------------------------------------------------- function hertz_prmtr_select(included : integer; lite_frequency : integer; sg_frequency : integer) return integer is begin -- 1 = Scatter Gather Included -- 0 = Scatter Gather Excluded if(included = 1)then return sg_frequency; else return lite_frequency; end if; end; ------------------------------------------------------------------------------- -- function to enable store and forward based on data width mismatch -- or directly enabled ------------------------------------------------------------------------------- function enable_snf (sf_enabled : integer; axi_data_width : integer; axis_tdata_width : integer) return integer is begin -- If store and forward enable or data widths do not -- match then return 1 to enable snf if( (sf_enabled = 1) or (axi_data_width /= axis_tdata_width))then return 1; else -- coverage off return 0; -- coverage on end if; end; end package body axi_dma_pkg;
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. ------------------------------------------------------------ ------------------------------------------------------------------------------- -- Filename: axi_dma_pkg.vhd -- Description: This package contains various constants and functions for -- AXI DMA operations. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library lib_pkg_v1_0_2; use lib_pkg_v1_0_2.lib_pkg.clog2; package axi_dma_pkg is ------------------------------------------------------------------------------- -- Function declarations ------------------------------------------------------------------------------- -- Find minimum required btt width function required_btt_width (dwidth : integer; burst_size : integer; btt_width : integer) return integer; -- Return correct hertz paramter value function hertz_prmtr_select(included : integer; lite_frequency : integer; sg_frequency : integer) return integer; -- Return SnF enable or disable function enable_snf (sf_enabled : integer; axi_data_width : integer; axis_tdata_width : integer) return integer; ------------------------------------------------------------------------------- -- Constant Declarations ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- AXI Responce Values ------------------------------------------------------------------------------- constant OKAY_RESP : std_logic_vector(1 downto 0) := "00"; constant EXOKAY_RESP : std_logic_vector(1 downto 0) := "01"; constant SLVERR_RESP : std_logic_vector(1 downto 0) := "10"; constant DECERR_RESP : std_logic_vector(1 downto 0) := "11"; constant MTBF_STAGES : integer := 4; constant C_FIFO_MTBF : integer := 4; ------------------------------------------------------------------------------- -- Misc Constants ------------------------------------------------------------------------------- --constant NUM_REG_TOTAL : integer := 18; --constant NUM_REG_TOTAL : integer := 23; constant NUM_REG_TOTAL : integer := 143; -- To accomodate S2MM registers --constant NUM_REG_PER_CHANNEL : integer := 6; constant NUM_REG_PER_CHANNEL : integer := 12; constant NUM_REG_PER_S2MM : integer := 120; --constant REG_MSB_ADDR_BIT : integer := clog2(NUM_REG_TOTAL)-1; constant CMD_BASE_WIDTH : integer := 40; constant BUFFER_LENGTH_WIDTH : integer := 23; -- Constants Used in Desc Updates constant DESC_STS_TYPE : std_logic := '1'; constant DESC_DATA_TYPE : std_logic := '0'; constant DESC_LAST : std_logic := '1'; constant DESC_NOT_LAST : std_logic := '0'; -- Interrupt Coalescing constant ZERO_THRESHOLD : std_logic_vector(7 downto 0) := (others => '0'); constant ONE_THRESHOLD : std_logic_vector(7 downto 0) := "00000001"; constant ZERO_DELAY : std_logic_vector(7 downto 0) := (others => '0'); ------------------------------------------------------------------------------- -- AXI Lite AXI DMA Register Offsets ------------------------------------------------------------------------------- constant MM2S_DMACR_INDEX : integer := 0; constant MM2S_DMASR_INDEX : integer := 1; constant MM2S_CURDESC_LSB_INDEX : integer := 2; constant MM2S_CURDESC_MSB_INDEX : integer := 3; constant MM2S_TAILDESC_LSB_INDEX : integer := 4; constant MM2S_TAILDESC_MSB_INDEX : integer := 5; constant MM2S_SA_INDEX : integer := 6; constant MM2S_SA2_INDEX : integer := 7; constant RESERVED_20_INDEX : integer := 8; constant RESERVED_24_INDEX : integer := 9; constant MM2S_LENGTH_INDEX : integer := 10; constant RESERVED_2C_INDEX : integer := 11; constant S2MM_DMACR_INDEX : integer := 12; constant S2MM_DMASR_INDEX : integer := 13; constant S2MM_CURDESC_LSB_INDEX : integer := 14; constant S2MM_CURDESC_MSB_INDEX : integer := 15; constant S2MM_TAILDESC_LSB_INDEX : integer := 16; constant S2MM_TAILDESC_MSB_INDEX : integer := 17; constant S2MM_DA_INDEX : integer := 18; constant S2MM_DA2_INDEX : integer := 19; constant RESERVED_50_INDEX : integer := 20; constant RESERVED_54_INDEX : integer := 21; --constant S2MM_LENGTH_INDEX : integer := 22; constant S2MM_LENGTH_INDEX : integer := 142; constant MM2S_DMACR_OFFSET : std_logic_vector(9 downto 0) := "0000000000"; -- 0x00 constant MM2S_DMASR_OFFSET : std_logic_vector(9 downto 0) := "0000000100"; -- 0x04 constant MM2S_CURDESC_LSB_OFFSET : std_logic_vector(9 downto 0) := "0000001000"; -- 0x08 constant MM2S_CURDESC_MSB_OFFSET : std_logic_vector(9 downto 0) := "0000001100"; -- 0x0C constant MM2S_TAILDESC_LSB_OFFSET : std_logic_vector(9 downto 0) := "0000010000"; -- 0x10 constant MM2S_TAILDESC_MSB_OFFSET : std_logic_vector(9 downto 0) := "0000010100"; -- 0x14 constant MM2S_SA_OFFSET : std_logic_vector(9 downto 0) := "0000011000"; -- 0x18 constant MM2S_SA2_OFFSET : std_logic_vector(9 downto 0) := "0000011100"; -- 0x1C constant RESERVED_20_OFFSET : std_logic_vector(9 downto 0) := "0000100000"; -- 0x20 constant RESERVED_24_OFFSET : std_logic_vector(9 downto 0) := "0000100100"; -- 0x24 constant MM2S_LENGTH_OFFSET : std_logic_vector(9 downto 0) := "0000101000"; -- 0x28 -- Following was reserved, now is used for SG xCache and xUser constant SGCTL_OFFSET : std_logic_vector(9 downto 0) := "0000101100"; -- 0x2C constant S2MM_DMACR_OFFSET : std_logic_vector(9 downto 0) := "0000110000"; -- 0x30 constant S2MM_DMASR_OFFSET : std_logic_vector(9 downto 0) := "0000110100"; -- 0x34 constant S2MM_CURDESC_LSB_OFFSET : std_logic_vector(9 downto 0) := "0000111000"; -- 0x38 constant S2MM_CURDESC_MSB_OFFSET : std_logic_vector(9 downto 0) := "0000111100"; -- 0x3C constant S2MM_TAILDESC_LSB_OFFSET : std_logic_vector(9 downto 0) := "0001000000"; -- 0x40 constant S2MM_TAILDESC_MSB_OFFSET : std_logic_vector(9 downto 0) := "0001000100"; -- 0x44 constant S2MM_DA_OFFSET : std_logic_vector(9 downto 0) := "0001001000"; -- 0x48 --CR603034 constant S2MM_DA2_OFFSET : std_logic_vector(9 downto 0) := "0001001100"; -- 0x4C constant RESERVED_50_OFFSET : std_logic_vector(9 downto 0) := "0001010000"; -- 0x50 constant RESERVED_54_OFFSET : std_logic_vector(9 downto 0) := "0001010100"; -- 0x54 constant S2MM_LENGTH_OFFSET : std_logic_vector(9 downto 0) := "0001011000"; -- 0x58 -- New registers for S2MM channels constant S2MM_CURDESC1_LSB_OFFSET : std_logic_vector(9 downto 0) := "0001110000"; -- 0x70 constant S2MM_CURDESC1_MSB_OFFSET : std_logic_vector(9 downto 0) := "0001110100"; -- 0x74 constant S2MM_TAILDESC1_LSB_OFFSET : std_logic_vector(9 downto 0) := "0001111000"; -- 0x78 constant S2MM_TAILDESC1_MSB_OFFSET : std_logic_vector(9 downto 0) := "0001111100"; -- 0x7C constant S2MM_CURDESC2_LSB_OFFSET : std_logic_vector(9 downto 0) := "0010010000"; -- 0x90 constant S2MM_CURDESC2_MSB_OFFSET : std_logic_vector(9 downto 0) := "0010010100"; -- 0x94 constant S2MM_TAILDESC2_LSB_OFFSET : std_logic_vector(9 downto 0) := "0010011000"; -- 0x98 constant S2MM_TAILDESC2_MSB_OFFSET : std_logic_vector(9 downto 0) := "0010011100"; -- 0x9C constant S2MM_CURDESC3_LSB_OFFSET : std_logic_vector(9 downto 0) := "0010110000"; -- 0xB0 constant S2MM_CURDESC3_MSB_OFFSET : std_logic_vector(9 downto 0) := "0010110100"; -- 0xB4 constant S2MM_TAILDESC3_LSB_OFFSET : std_logic_vector(9 downto 0) := "0010111000"; -- 0xB8 constant S2MM_TAILDESC3_MSB_OFFSET : std_logic_vector(9 downto 0) := "0010111100"; -- 0xBC constant S2MM_CURDESC4_LSB_OFFSET : std_logic_vector(9 downto 0) := "0011010000"; -- 0xD0 constant S2MM_CURDESC4_MSB_OFFSET : std_logic_vector(9 downto 0) := "0011010100"; -- 0xD4 constant S2MM_TAILDESC4_LSB_OFFSET : std_logic_vector(9 downto 0) := "0011011000"; -- 0xD8 constant S2MM_TAILDESC4_MSB_OFFSET : std_logic_vector(9 downto 0) := "0011011100"; -- 0xDC constant S2MM_CURDESC5_LSB_OFFSET : std_logic_vector(9 downto 0) := "0011110000"; -- 0xF0 constant S2MM_CURDESC5_MSB_OFFSET : std_logic_vector(9 downto 0) := "0011110100"; -- 0xF4 constant S2MM_TAILDESC5_LSB_OFFSET : std_logic_vector(9 downto 0) := "0011111000"; -- 0xF8 constant S2MM_TAILDESC5_MSB_OFFSET : std_logic_vector(9 downto 0) := "0011111100"; -- 0xFC constant S2MM_CURDESC6_LSB_OFFSET : std_logic_vector(9 downto 0) := "0100010000"; -- 0x110 constant S2MM_CURDESC6_MSB_OFFSET : std_logic_vector(9 downto 0) := "0100010100"; -- 0x114 constant S2MM_TAILDESC6_LSB_OFFSET : std_logic_vector(9 downto 0) := "0100011000"; -- 0x118 constant S2MM_TAILDESC6_MSB_OFFSET : std_logic_vector(9 downto 0) := "0100011100"; -- 0x11C constant S2MM_CURDESC7_LSB_OFFSET : std_logic_vector(9 downto 0) := "0100110000"; -- 0x130 constant S2MM_CURDESC7_MSB_OFFSET : std_logic_vector(9 downto 0) := "0100110100"; -- 0x134 constant S2MM_TAILDESC7_LSB_OFFSET : std_logic_vector(9 downto 0) := "0100111000"; -- 0x138 constant S2MM_TAILDESC7_MSB_OFFSET : std_logic_vector(9 downto 0) := "0100111100"; -- 0x13C constant S2MM_CURDESC8_LSB_OFFSET : std_logic_vector(9 downto 0) := "0101010000"; -- 0x150 constant S2MM_CURDESC8_MSB_OFFSET : std_logic_vector(9 downto 0) := "0101010100"; -- 0x154 constant S2MM_TAILDESC8_LSB_OFFSET : std_logic_vector(9 downto 0) := "0101011000"; -- 0x158 constant S2MM_TAILDESC8_MSB_OFFSET : std_logic_vector(9 downto 0) := "0101011100"; -- 0x15C constant S2MM_CURDESC9_LSB_OFFSET : std_logic_vector(9 downto 0) := "0101110000"; -- 0x170 constant S2MM_CURDESC9_MSB_OFFSET : std_logic_vector(9 downto 0) := "0101110100"; -- 0x174 constant S2MM_TAILDESC9_LSB_OFFSET : std_logic_vector(9 downto 0) := "0101111000"; -- 0x178 constant S2MM_TAILDESC9_MSB_OFFSET : std_logic_vector(9 downto 0) := "0101111100"; -- 0x17C constant S2MM_CURDESC10_LSB_OFFSET : std_logic_vector(9 downto 0) := "0110010000"; -- 0x190 constant S2MM_CURDESC10_MSB_OFFSET : std_logic_vector(9 downto 0) := "0110010100"; -- 0x194 constant S2MM_TAILDESC10_LSB_OFFSET : std_logic_vector(9 downto 0) := "0110011000"; -- 0x198 constant S2MM_TAILDESC10_MSB_OFFSET : std_logic_vector(9 downto 0) := "0110011100"; -- 0x19C constant S2MM_CURDESC11_LSB_OFFSET : std_logic_vector(9 downto 0) := "0110110000"; -- 0x1B0 constant S2MM_CURDESC11_MSB_OFFSET : std_logic_vector(9 downto 0) := "0110110100"; -- 0x1B4 constant S2MM_TAILDESC11_LSB_OFFSET : std_logic_vector(9 downto 0) := "0110111000"; -- 0x1B8 constant S2MM_TAILDESC11_MSB_OFFSET : std_logic_vector(9 downto 0) := "0110111100"; -- 0x1BC constant S2MM_CURDESC12_LSB_OFFSET : std_logic_vector(9 downto 0) := "0111010000"; -- 0x1D0 constant S2MM_CURDESC12_MSB_OFFSET : std_logic_vector(9 downto 0) := "0111010100"; -- 0x1D4 constant S2MM_TAILDESC12_LSB_OFFSET : std_logic_vector(9 downto 0) := "0111011000"; -- 0x1D8 constant S2MM_TAILDESC12_MSB_OFFSET : std_logic_vector(9 downto 0) := "0111011100"; -- 0x1DC constant S2MM_CURDESC13_LSB_OFFSET : std_logic_vector(9 downto 0) := "0111110000"; -- 0x1F0 constant S2MM_CURDESC13_MSB_OFFSET : std_logic_vector(9 downto 0) := "0111110100"; -- 0x1F4 constant S2MM_TAILDESC13_LSB_OFFSET : std_logic_vector(9 downto 0) := "0111111000"; -- 0x1F8 constant S2MM_TAILDESC13_MSB_OFFSET : std_logic_vector(9 downto 0) := "0111111100"; -- 0x1FC constant S2MM_CURDESC14_LSB_OFFSET : std_logic_vector(9 downto 0) := "1000010000"; -- 0x210 constant S2MM_CURDESC14_MSB_OFFSET : std_logic_vector(9 downto 0) := "1000010100"; -- 0x214 constant S2MM_TAILDESC14_LSB_OFFSET : std_logic_vector(9 downto 0) := "1000011000"; -- 0x218 constant S2MM_TAILDESC14_MSB_OFFSET : std_logic_vector(9 downto 0) := "1000011100"; -- 0x21C constant S2MM_CURDESC15_LSB_OFFSET : std_logic_vector(9 downto 0) := "1000110000"; -- 0x230 constant S2MM_CURDESC15_MSB_OFFSET : std_logic_vector(9 downto 0) := "1000110100"; -- 0x234 constant S2MM_TAILDESC15_LSB_OFFSET : std_logic_vector(9 downto 0) := "1000111000"; -- 0x238 constant S2MM_TAILDESC15_MSB_OFFSET : std_logic_vector(9 downto 0) := "1000111100"; -- 0x23C ------------------------------------------------------------------------------- -- Register Bit Constants ------------------------------------------------------------------------------- -- DMACR constant DMACR_RS_BIT : integer := 0; constant DMACR_TAILPEN_BIT : integer := 1; constant DMACR_RESET_BIT : integer := 2; constant DMACR_KH_BIT : integer := 3; constant CYCLIC_BIT : integer := 4; --constant DMACR_RESERVED3_BIT : integer := 3; --constant DMACR_RESERVED4_BIT : integer := 4; constant DMACR_RESERVED5_BIT : integer := 5; constant DMACR_RESERVED6_BIT : integer := 6; constant DMACR_RESERVED7_BIT : integer := 7; constant DMACR_RESERVED8_BIT : integer := 8; constant DMACR_RESERVED9_BIT : integer := 9; constant DMACR_RESERVED10_BIT : integer := 10; constant DMACR_RESERVED11_BIT : integer := 11; constant DMACR_IOC_IRQEN_BIT : integer := 12; constant DMACR_DLY_IRQEN_BIT : integer := 13; constant DMACR_ERR_IRQEN_BIT : integer := 14; constant DMACR_RESERVED15_BIT : integer := 15; constant DMACR_IRQTHRESH_LSB_BIT : integer := 16; constant DMACR_IRQTHRESH_MSB_BIT : integer := 23; constant DMACR_IRQDELAY_LSB_BIT : integer := 24; constant DMACR_IRQDELAY_MSB_BIT : integer := 31; -- DMASR constant DMASR_HALTED_BIT : integer := 0; constant DMASR_IDLE_BIT : integer := 1; constant DMASR_CMPLT_BIT : integer := 2; constant DMASR_ERROR_BIT : integer := 3; constant DMASR_DMAINTERR_BIT : integer := 4; constant DMASR_DMASLVERR_BIT : integer := 5; constant DMASR_DMADECERR_BIT : integer := 6; constant DMASR_RESERVED7_BIT : integer := 7; constant DMASR_SGINTERR_BIT : integer := 8; constant DMASR_SGSLVERR_BIT : integer := 9; constant DMASR_SGDECERR_BIT : integer := 10; constant DMASR_RESERVED11_BIT : integer := 11; constant DMASR_IOCIRQ_BIT : integer := 12; constant DMASR_DLYIRQ_BIT : integer := 13; constant DMASR_ERRIRQ_BIT : integer := 14; constant DMASR_RESERVED15_BIT : integer := 15; constant DMASR_IRQTHRESH_LSB_BIT : integer := 16; constant DMASR_IRQTHRESH_MSB_BIT : integer := 23; constant DMASR_IRQDELAY_LSB_BIT : integer := 24; constant DMASR_IRQDELAY_MSB_BIT : integer := 31; -- CURDESC constant CURDESC_LOWER_MSB_BIT : integer := 31; constant CURDESC_LOWER_LSB_BIT : integer := 6; constant CURDESC_RESERVED_BIT5 : integer := 5; constant CURDESC_RESERVED_BIT4 : integer := 4; constant CURDESC_RESERVED_BIT3 : integer := 3; constant CURDESC_RESERVED_BIT2 : integer := 2; constant CURDESC_RESERVED_BIT1 : integer := 1; constant CURDESC_RESERVED_BIT0 : integer := 0; -- TAILDESC constant TAILDESC_LOWER_MSB_BIT : integer := 31; constant TAILDESC_LOWER_LSB_BIT : integer := 6; constant TAILDESC_RESERVED_BIT5 : integer := 5; constant TAILDESC_RESERVED_BIT4 : integer := 4; constant TAILDESC_RESERVED_BIT3 : integer := 3; constant TAILDESC_RESERVED_BIT2 : integer := 2; constant TAILDESC_RESERVED_BIT1 : integer := 1; constant TAILDESC_RESERVED_BIT0 : integer := 0; -- DataMover Command / Status Constants constant DATAMOVER_CMDDONE_BIT : integer := 7; constant DATAMOVER_SLVERR_BIT : integer := 6; constant DATAMOVER_DECERR_BIT : integer := 5; constant DATAMOVER_INTERR_BIT : integer := 4; constant DATAMOVER_TAGMSB_BIT : integer := 3; constant DATAMOVER_TAGLSB_BIT : integer := 0; -- Descriptor Control Bits constant DESC_BLENGTH_LSB_BIT : integer := 0; constant DESC_BLENGTH_MSB_BIT : integer := 22; constant DESC_RSVD23_BIT : integer := 23; constant DESC_RSVD24_BIT : integer := 24; constant DESC_RSVD25_BIT : integer := 25; constant DESC_EOF_BIT : integer := 26; constant DESC_SOF_BIT : integer := 27; constant DESC_RSVD28_BIT : integer := 28; constant DESC_RSVD29_BIT : integer := 29; constant DESC_RSVD30_BIT : integer := 30; constant DESC_IOC_BIT : integer := 31; -- Descriptor Status Bits constant DESC_STS_CMPLTD_BIT : integer := 31; constant DESC_STS_DECERR_BIT : integer := 30; constant DESC_STS_SLVERR_BIT : integer := 29; constant DESC_STS_INTERR_BIT : integer := 28; constant DESC_STS_RXSOF_BIT : integer := 27; constant DESC_STS_RXEOF_BIT : integer := 26; constant DESC_STS_RSVD25_BIT : integer := 25; constant DESC_STS_RSVD24_BIT : integer := 24; constant DESC_STS_RSVD23_BIT : integer := 23; constant DESC_STS_XFRDBYTS_MSB_BIT : integer := 22; constant DESC_STS_XFRDBYTS_LSB_BIT : integer := 0; -- DataMover Command / Status Constants constant DATAMOVER_STS_CMDDONE_BIT : integer := 7; constant DATAMOVER_STS_SLVERR_BIT : integer := 6; constant DATAMOVER_STS_DECERR_BIT : integer := 5; constant DATAMOVER_STS_INTERR_BIT : integer := 4; constant DATAMOVER_STS_TAGMSB_BIT : integer := 3; constant DATAMOVER_STS_TAGLSB_BIT : integer := 0; constant DATAMOVER_STS_TAGEOF_BIT : integer := 1; constant DATAMOVER_STS_TLAST_BIT : integer := 31; constant DATAMOVER_CMD_BTTLSB_BIT : integer := 0; constant DATAMOVER_CMD_BTTMSB_BIT : integer := 22; constant DATAMOVER_CMD_TYPE_BIT : integer := 23; constant DATAMOVER_CMD_DSALSB_BIT : integer := 24; constant DATAMOVER_CMD_DSAMSB_BIT : integer := 29; constant DATAMOVER_CMD_EOF_BIT : integer := 30; constant DATAMOVER_CMD_DRR_BIT : integer := 31; constant DATAMOVER_CMD_ADDRLSB_BIT : integer := 32; -- Note: Bit offset require adding ADDR WIDTH to get to actual bit index constant DATAMOVER_CMD_ADDRMSB_BOFST: integer := 31; constant DATAMOVER_CMD_TAGLSB_BOFST : integer := 32; constant DATAMOVER_CMD_TAGMSB_BOFST : integer := 35; constant DATAMOVER_CMD_RSVLSB_BOFST : integer := 36; constant DATAMOVER_CMD_RSVMSB_BOFST : integer := 39; end axi_dma_pkg; ------------------------------------------------------------------------------- -- PACKAGE BODY ------------------------------------------------------------------------------- package body axi_dma_pkg is ------------------------------------------------------------------------------- -- Function to determine minimum bits required for BTT_SIZE field ------------------------------------------------------------------------------- function required_btt_width ( dwidth : integer; burst_size: integer; btt_width : integer) return integer is variable min_width : integer; begin min_width := clog2((dwidth/8)*burst_size)+1; if(min_width > btt_width)then return min_width; else return btt_width; end if; end function required_btt_width; ------------------------------------------------------------------------------- -- function to return Frequency Hertz parameter based on inclusion of sg engine ------------------------------------------------------------------------------- function hertz_prmtr_select(included : integer; lite_frequency : integer; sg_frequency : integer) return integer is begin -- 1 = Scatter Gather Included -- 0 = Scatter Gather Excluded if(included = 1)then return sg_frequency; else return lite_frequency; end if; end; ------------------------------------------------------------------------------- -- function to enable store and forward based on data width mismatch -- or directly enabled ------------------------------------------------------------------------------- function enable_snf (sf_enabled : integer; axi_data_width : integer; axis_tdata_width : integer) return integer is begin -- If store and forward enable or data widths do not -- match then return 1 to enable snf if( (sf_enabled = 1) or (axi_data_width /= axis_tdata_width))then return 1; else -- coverage off return 0; -- coverage on end if; end; end package body axi_dma_pkg;
------------------------------------------------------------------------------- -- Title : gig_eth -- Project : K7UGbE ------------------------------------------------------------------------------- -- File : gig_eth.vhd -- Author : Yuan Mei -- Company : LBNL -- Created : 2016-11-20 -- Last update: 2016-11-20 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- -- Description: gig_eth with sgmii interface to external PHY ------------------------------------------------------------------------------- -- Copyright (c) 2016 ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2016-11-20 1.0 ymei Created ------------------------------------------------------------------------------- library unisim; use unisim.vcomponents.all; library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.com5402pkg.all; -------------------------------------------------------------------------------- -- The entity declaration for the example_design level wrapper. -------------------------------------------------------------------------------- ENTITY gig_eth IS PORT ( -- asynchronous reset glbl_rst : IN std_logic; -- clocks SYS_CLK : IN std_logic; sgmii125_clk : OUT std_logic; -- routed back out, single-ended -- PHY interface phy_resetn : OUT std_logic; -- SGMII interface ------------------ sgmii_clk_p : IN std_logic; sgmii_clk_n : IN std_logic; sgmii_rx_p : IN std_logic; sgmii_rx_n : IN std_logic; sgmii_tx_p : OUT std_logic; sgmii_tx_n : OUT std_logic; -- MDIO interface ----------------- mdio : INOUT std_logic; mdc : OUT std_logic; -- status status : OUT std_logic_vector(31 DOWNTO 0); -- TCP MAC_ADDR : IN std_logic_vector(47 DOWNTO 0); IPv4_ADDR : IN std_logic_vector(31 DOWNTO 0); IPv6_ADDR : IN std_logic_vector(127 DOWNTO 0); SUBNET_MASK : IN std_logic_vector(31 DOWNTO 0); GATEWAY_IP_ADDR : IN std_logic_vector(31 DOWNTO 0); TCP_CONNECTION_RESET : IN std_logic; TX_TDATA : IN std_logic_vector(7 DOWNTO 0); TX_TVALID : IN std_logic; TX_TREADY : OUT std_logic; RX_TDATA : OUT std_logic_vector(7 DOWNTO 0); RX_TVALID : OUT std_logic; RX_TREADY : IN std_logic; -- FIFO TCP_USE_FIFO : IN std_logic; TX_FIFO_WRCLK : IN std_logic; TX_FIFO_Q : IN std_logic_vector(31 DOWNTO 0); TX_FIFO_WREN : IN std_logic; TX_FIFO_FULL : OUT std_logic; RX_FIFO_RDCLK : IN std_logic; RX_FIFO_Q : OUT std_logic_vector(31 DOWNTO 0); RX_FIFO_RDEN : IN std_logic; RX_FIFO_EMPTY : OUT std_logic ); END gig_eth; ARCHITECTURE wrapper OF gig_eth IS ATTRIBUTE DowngradeIPIdentifiedWarnings : string; ATTRIBUTE DowngradeIPIdentifiedWarnings OF wrapper : ARCHITECTURE IS "yes"; COMPONENT GlobalResetter GENERIC ( CLK_RESET_DELAY_CNT : integer := 10000; GBL_RESET_DELAY_CNT : integer := 100; CNT_RANGE_HIGH : integer := 16383 ); PORT ( FORCE_RST : IN std_logic; CLK : IN std_logic; -- system clock DCM_LOCKED : IN std_logic; CLK_RST : OUT std_logic; GLOBAL_RST : OUT std_logic ); END COMPONENT; COMPONENT COM5402 IS GENERIC ( CLK_FREQUENCY : integer := 125; -- CLK frequency in MHz. Needed to compute actual delays. TX_IDLE_TIMEOUT : integer RANGE 0 TO 50 := 50; -- inactive input timeout, expressed in 4us units. -- 50*4us = 200us -- Controls the transmit stream segmentation: data in the elastic buffer will be transmitted if -- no input is received within TX_IDLE_TIMEOUT, without waiting for the transmit frame to be filled with MSS data bytes. SIMULATION : std_logic := '0' -- 1 during simulation with Wireshark .cap file, '0' otherwise -- Wireshark many not be able to collect offloaded checksum computations. -- when SIMULATION = '1': (a) IP header checksum is valid if 0000, -- (b) TCP checksum computation is forced to a valid 00001 irrespective of the 16-bit checksum -- captured by Wireshark. ); PORT ( --//-- CLK, RESET CLK : IN std_logic; -- All signals are synchronous with CLK -- CLK must be a global clock 125 MHz or faster to match the Gbps MAC speed. ASYNC_RESET : IN std_logic; -- to be phased out. replace with SYNC_RESET SYNC_RESET : IN std_logic; --//-- CONFIGURATION -- configuration signals are synchonous with CLK -- Synchronous with CLK clock. MAC_ADDR : IN std_logic_vector(47 DOWNTO 0); IPv4_ADDR : IN std_logic_vector(31 DOWNTO 0); IPv6_ADDR : IN std_logic_vector(127 DOWNTO 0); SUBNET_MASK : IN std_logic_vector(31 DOWNTO 0); GATEWAY_IP_ADDR : IN std_logic_vector(31 DOWNTO 0); -- local IP address. 4 bytes for IPv4, 16 bytes for IPv6 -- Natural order (MSB) 172.16.1.128 (LSB) as transmitted in the IP frame. --// User-initiated connection reset for stream I CONNECTION_RESET : IN std_logic_vector((NTCPSTREAMS-1) DOWNTO 0); --//-- Protocol -> Transmit MAC Interface -- 32-bit CRC is automatically appended by the MAC layer. User should not supply it. -- Synchonous with the user-side CLK MAC_TX_DATA : OUT std_logic_vector(7 DOWNTO 0); -- MAC reads the data at the rising edge of CLK when MAC_TX_DATA_VALID = '1' MAC_TX_DATA_VALID : OUT std_logic; -- data valid MAC_TX_SOF : out std_logic; -- start of frame: '1' when sending the first byte. MAC_TX_EOF : OUT std_logic; -- '1' when sending the last byte in a packet to be transmitted. -- Aligned with MAC_TX_DATA_VALID MAC_TX_CTS : IN std_logic; -- MAC-generated Clear To Send flow control signal, indicating room in the -- MAC tx elastic buffer for a complete maximum size frame 1518B. -- The user should check that this signal is high before deciding to send -- sending the next frame. -- Note: MAC_TX_CTS may go low while the frame is transfered in. Ignore it as space is guaranteed -- at the start of frame. --//-- Receive MAC -> Protocol -- Valid rx packets only: packets with bad CRC or invalid address are discarded. -- The 32-bit CRC is always removed by the MAC layer. -- Synchonous with the user-side CLK MAC_RX_DATA : IN std_logic_vector(7 DOWNTO 0); -- USER reads the data at the rising edge of CLK when MAC_RX_DATA_VALID = '1' MAC_RX_DATA_VALID : IN std_logic; -- data valid MAC_RX_SOF : IN std_logic; -- '1' when sending the first byte in a received packet. -- Aligned with MAC_RX_DATA_VALID MAC_RX_EOF : IN std_logic; -- '1' when sending the last byte in a received packet. -- Aligned with MAC_RX_DATA_VALID --//-- Application <- UDP rx UDP_RX_DATA : OUT std_logic_vector(7 DOWNTO 0); UDP_RX_DATA_VALID : OUT std_logic; UDP_RX_SOF : OUT std_logic; UDP_RX_EOF : OUT std_logic; -- 1 CLK pulse indicating that UDP_RX_DATA is the last byte in the UDP data field. -- ALWAYS CHECK UDP_RX_DATA_VALID at the end of packet (UDP_RX_EOF = '1') to confirm -- that the UDP packet is valid. External buffer may have to backtrack to the the last -- valid pointer to discard an invalid UDP packet. -- Reason: we only knows about bad UDP packets at the end. UDP_RX_DEST_PORT_NO : IN std_logic_vector(15 DOWNTO 0); --//-- Application -> UDP tx UDP_TX_DATA : IN std_logic_vector(7 DOWNTO 0); UDP_TX_DATA_VALID : IN std_logic; UDP_TX_SOF : IN std_logic; -- 1 CLK-wide pulse to mark the first byte in the tx UDP frame UDP_TX_EOF : IN std_logic; -- 1 CLK-wide pulse to mark the last byte in the tx UDP frame UDP_TX_CTS : OUT std_logic; UDP_TX_ACK : OUT std_logic; -- 1 CLK-wide pulse indicating that the previous UDP frame is being sent UDP_TX_NAK : OUT std_logic; -- 1 CLK-wide pulse indicating that the previous UDP frame could not be sent UDP_TX_DEST_IP_ADDR : IN std_logic_vector(127 DOWNTO 0); UDP_TX_DEST_PORT_NO : IN std_logic_vector(15 DOWNTO 0); UDP_TX_SOURCE_PORT_NO : IN std_logic_vector(15 DOWNTO 0); --//-- Application <- TCP rx -- NTCPSTREAMS can operate independently. Only one stream active at any given time. -- Data is pushed out. Limited flow-control here. Receipient must be able to accept data -- at any time (in other words, it is the receipient's responsibility to have elastic -- buffer if needed). TCP_RX_DATA : OUT SLV8xNTCPSTREAMStype; TCP_RX_DATA_VALID : OUT std_logic_vector((NTCPSTREAMS-1) DOWNTO 0); TCP_RX_RTS : OUT std_logic; TCP_RX_CTS : IN std_logic; -- Optional Clear-To-Send. pull to '1' when output flow control is unused. -- WARNING: pulling CTS down will stop the flow for ALL streams. --//-- Application -> TCP tx -- NTCPSTREAMS can operate independently and concurrently. No scheduling arbitration needed here. TCP_TX_DATA : IN SLV8xNTCPSTREAMStype; TCP_TX_DATA_VALID : IN std_logic_vector((NTCPSTREAMS-1) DOWNTO 0); TCP_TX_CTS : OUT std_logic_vector((NTCPSTREAMS-1) DOWNTO 0); -- Clear To Send = transmit flow control. -- App is responsible for checking the CTS signal before sending APP_DATA --//-- TEST POINTS, COMSCOPE TRACES CS1 : OUT std_logic_vector(7 DOWNTO 0); CS1_CLK : OUT std_logic; CS2 : OUT std_logic_vector(7 DOWNTO 0); CS2_CLK : OUT std_logic; TP : OUT std_logic_vector(10 DOWNTO 1) ); END COMPONENT; -- Must have programmable full with single-threshold of 61 -- out of total write-depth 64 COMPONENT fifo8to32 PORT ( rst : IN std_logic; wr_clk : IN std_logic; rd_clk : IN std_logic; din : IN std_logic_vector(7 DOWNTO 0); wr_en : IN std_logic; rd_en : IN std_logic; dout : OUT std_logic_vector(31 DOWNTO 0); full : OUT std_logic; prog_full : OUT std_logic; empty : OUT std_logic ); END COMPONENT; COMPONENT fifo32to8 PORT ( rst : IN std_logic; wr_clk : IN std_logic; rd_clk : IN std_logic; din : IN std_logic_vector(31 DOWNTO 0); wr_en : IN std_logic; rd_en : IN std_logic; dout : OUT std_logic_vector(7 DOWNTO 0); full : OUT std_logic; empty : OUT std_logic ); END COMPONENT; ------------------------------------------------------------------------------ -- Component Declaration for the Tri-Mode EMAC core FIFO Block wrapper ------------------------------------------------------------------------------ component tri_mode_ethernet_mac_0_fifo_block port( gtx_clk : in std_logic; -- asynchronous reset glbl_rstn : in std_logic; rx_axi_rstn : in std_logic; tx_axi_rstn : in std_logic; -- Receiver Statistics Interface ------------------------------------------ rx_mac_aclk : out std_logic; rx_reset : out std_logic; rx_statistics_vector : out std_logic_vector(27 downto 0); rx_statistics_valid : out std_logic; -- Receiver (AXI-S) Interface ------------------------------------------ rx_fifo_clock : in std_logic; rx_fifo_resetn : in std_logic; rx_axis_fifo_tready : in std_logic; rx_axis_fifo_tvalid : out std_logic; rx_axis_fifo_tdata : out std_logic_vector(7 downto 0); rx_axis_fifo_tlast : out std_logic; -- Transmitter Statistics Interface ------------------------------------------- tx_mac_aclk : out std_logic; tx_reset : out std_logic; tx_ifg_delay : in std_logic_vector(7 downto 0); tx_statistics_vector : out std_logic_vector(31 downto 0); tx_statistics_valid : out std_logic; -- Transmitter (AXI-S) Interface ------------------------------------------- tx_fifo_clock : in std_logic; tx_fifo_resetn : in std_logic; tx_axis_fifo_tready : out std_logic; tx_axis_fifo_tvalid : in std_logic; tx_axis_fifo_tdata : in std_logic_vector(7 downto 0); tx_axis_fifo_tlast : in std_logic; -- MAC Control Interface -------------------------- pause_req : in std_logic; pause_val : in std_logic_vector(15 downto 0); -- GMII Interface ------------------- gmii_txd : out std_logic_vector(7 downto 0); gmii_tx_en : out std_logic; gmii_tx_er : out std_logic; gmii_rxd : in std_logic_vector(7 downto 0); gmii_rx_dv : in std_logic; gmii_rx_er : in std_logic; speedis100 : out std_logic; speedis10100 : out std_logic; -- MDIO Interface ----------------- mdio : inout std_logic; mdc : out std_logic; -- AXI-Lite Interface ----------------- s_axi_aclk : in std_logic; s_axi_resetn : in std_logic; -- s_axi_awaddr : in std_logic_vector(11 downto 0); s_axi_awvalid : in std_logic; s_axi_awready : out std_logic; -- s_axi_wdata : in std_logic_vector(31 downto 0); s_axi_wvalid : in std_logic; s_axi_wready : out std_logic; -- s_axi_bresp : out std_logic_vector(1 downto 0); s_axi_bvalid : out std_logic; s_axi_bready : in std_logic; -- s_axi_araddr : in std_logic_vector(11 downto 0); s_axi_arvalid : in std_logic; s_axi_arready : out std_logic; -- s_axi_rdata : out std_logic_vector(31 downto 0); s_axi_rresp : out std_logic_vector(1 downto 0); s_axi_rvalid : out std_logic; s_axi_rready : in std_logic ); end component; ------------------------------------------------------------------------------ -- Component Declaration for the AXI-Lite State machine ------------------------------------------------------------------------------ component tri_mode_ethernet_mac_0_axi_lite_sm port ( s_axi_aclk : in std_logic; s_axi_resetn : in std_logic; mac_speed : in std_logic_vector(1 downto 0); update_speed : in std_logic; serial_command : in std_logic; serial_response : out std_logic; phy_loopback : in std_logic; s_axi_awaddr : out std_logic_vector(11 downto 0); s_axi_awvalid : out std_logic; s_axi_awready : in std_logic; s_axi_wdata : out std_logic_vector(31 downto 0); s_axi_wvalid : out std_logic; s_axi_wready : in std_logic; s_axi_bresp : in std_logic_vector(1 downto 0); s_axi_bvalid : in std_logic; s_axi_bready : out std_logic; s_axi_araddr : out std_logic_vector(11 downto 0); s_axi_arvalid : out std_logic; s_axi_arready : in std_logic; s_axi_rdata : in std_logic_vector(31 downto 0); s_axi_rresp : in std_logic_vector(1 downto 0); s_axi_rvalid : in std_logic; s_axi_rready : out std_logic ); end component; ------------------------------------------------------------------------------ -- Component declaration for the synchroniser ------------------------------------------------------------------------------ component tri_mode_ethernet_mac_0_sync_block port ( clk : in std_logic; data_in : in std_logic; data_out : out std_logic ); end component; ------------------------------------------------------------------------------ -- Component declaration for the reset logic ------------------------------------------------------------------------------ component tri_mode_ethernet_mac_0_example_design_resets is port ( -- clocks s_axi_aclk : in std_logic; gtx_clk : in std_logic; -- asynchronous resets glbl_rst : in std_logic; reset_error : in std_logic; rx_reset : in std_logic; tx_reset : in std_logic; dcm_locked : in std_logic; -- synchronous reset outputs glbl_rst_intn : out std_logic; gtx_resetn : out std_logic := '0'; s_axi_resetn : out std_logic := '0'; phy_resetn : out std_logic; chk_resetn : out std_logic := '0' ); end component; ------------------------------------------------------------------------------ -- Component declaration for SGMII PCS/PMA core ------------------------------------------------------------------------------ COMPONENT gig_ethernet_pcs_pma_0 PORT ( -- LVDS transceiver Interface ----------------------------- txp : OUT std_logic; -- Differential +ve of serial transmission from PMA to PMD. txn : OUT std_logic; -- Differential -ve of serial transmission from PMA to PMD. rxp : IN std_logic; -- Differential +ve for serial reception from PMD to PMA. rxn : IN std_logic; -- Differential -ve for serial reception from PMD to PMA. refclk625_p : IN std_logic; refclk625_n : IN std_logic; -- GMII Interface ----------------- sgmii_clk_r : OUT std_logic; -- Clock for client MAC (125Mhz, 12.5MHz or 1.25MHz). sgmii_clk_f : OUT std_logic; -- Clock for client MAC (125Mhz, 12.5MHz or 1.25MHz). sgmii_clk_en : OUT std_logic; -- Clock enable for client MAC clk125_out : OUT std_logic; clk312_out : OUT std_logic; idelay_rdy_out : OUT std_logic; clk625_out : OUT std_logic; rst_125_out : OUT std_logic; mmcm_locked_out : OUT std_logic; -- Speed Control speed_is_10_100 : IN std_logic; -- Core should operate at either 10Mbps or 100Mbps speeds speed_is_100 : IN std_logic; -- Core should operate at 100Mbps speed -- GMII Interface ----------------- gmii_txd : IN std_logic_vector(7 DOWNTO 0); -- Transmit data from client MAC. gmii_tx_en : IN std_logic; -- Transmit control signal from client MAC. gmii_tx_er : IN std_logic; -- Transmit control signal from client MAC. gmii_rxd : OUT std_logic_vector(7 DOWNTO 0); -- Received Data to client MAC. gmii_rx_dv : OUT std_logic; -- Received control signal to client MAC. gmii_rx_er : OUT std_logic; -- Received control signal to client MAC. gmii_isolate : OUT std_logic; -- Tristate control to electrically isolate GMII. configuration_vector : IN std_logic_vector(4 DOWNTO 0); -- Alternative to MDIO interface. an_interrupt : OUT std_logic; -- Interrupt to processor to signal that Auto-Negotiation has completed an_adv_config_vector : IN std_logic_vector(15 DOWNTO 0); -- Alternate interface to program REG4 (AN ADV) an_restart_config : IN std_logic; -- Alternate signal to modify AN restart bit in REG0 -- General IO's --------------- status_vector : OUT std_logic_vector(15 DOWNTO 0); -- Core status. reset : IN std_logic; -- Asynchronous reset for entire core. signal_detect : IN std_logic -- Input from PMD to indicate presence of optical input. ); END COMPONENT; ------------------------------------------------------------------------------ -- internal signals used in this top level wrapper. ------------------------------------------------------------------------------ -- example design clocks signal gtx_clk : std_logic; signal gtx_clk_bufg : std_logic; signal dcm_locked : std_logic; signal s_axi_aclk : std_logic; signal rx_mac_aclk : std_logic; signal tx_mac_aclk : std_logic; signal sgmii_clk_r : std_logic; signal sgmii_clk_f : std_logic; -- resets (and reset generation) signal grst : std_logic; signal gclk_rst : std_logic; signal reset_error : std_logic; signal s_axi_resetn : std_logic; signal chk_resetn : std_logic; signal gtx_resetn : std_logic; signal rx_reset : std_logic; signal tx_reset : std_logic; -- signal glbl_rst_int : std_logic; signal phy_reset_count : unsigned(5 downto 0) := (others => '0'); signal glbl_rst_intn : std_logic; signal dcm_status_locked : std_logic; signal pcs_pma_status_rst : std_logic; -- signal gmii_txd_int : std_logic_vector(7 downto 0); signal gmii_tx_en_int : std_logic; signal gmii_tx_er_int : std_logic; signal gmii_rxd_int : std_logic_vector(7 downto 0); signal gmii_rx_dv_int : std_logic; signal gmii_rx_er_int : std_logic; -- PCS PMA signal configuration_vector : std_logic_vector(4 downto 0); signal an_interrupt : std_logic; signal an_adv_config_vector : std_logic_vector(15 downto 0); signal an_restart_config : std_logic; signal speed_is_10_100 : std_logic; signal speed_is_100 : std_logic; signal status_vector : std_logic_vector(15 downto 0); signal signal_detect : std_logic; -- MAC signal mac_speed : std_logic_vector(1 downto 0); signal serial_response : std_logic; signal frame_error : std_logic; signal frame_errorn : std_logic; signal activity_flash : std_logic; signal activity_flashn : std_logic; -- signal update_speed : std_logic := '0'; signal config_board : std_logic := '0'; -- USER side RX AXI-S interface signal rx_fifo_clock : std_logic; signal rx_fifo_resetn : std_logic; signal rx_axis_fifo_tdata : std_logic_vector(7 downto 0); signal rx_axis_fifo_tvalid : std_logic; signal rx_axis_fifo_tlast : std_logic; signal rx_axis_fifo_tready : std_logic; -- USER side TX AXI-S interface signal tx_fifo_clock : std_logic; signal tx_fifo_resetn : std_logic; signal tx_axis_fifo_tdata : std_logic_vector(7 downto 0); signal tx_axis_fifo_tvalid : std_logic; signal tx_axis_fifo_tlast : std_logic; signal tx_axis_fifo_tready : std_logic; -- RX Statistics serialisation signals signal rx_statistics_s : std_logic := '0'; signal rx_statistics_valid : std_logic; signal rx_statistics_valid_reg : std_logic; signal rx_statistics_vector : std_logic_vector(27 downto 0); signal rx_stats : std_logic_vector(27 downto 0); signal rx_stats_shift : std_logic_vector(29 downto 0); signal rx_stats_toggle : std_logic := '0'; signal rx_stats_toggle_sync : std_logic; signal rx_stats_toggle_sync_reg : std_logic := '0'; -- TX Statistics serialisation signals signal tx_statistics_s : std_logic := '0'; signal tx_statistics_valid : std_logic; signal tx_statistics_valid_reg : std_logic; signal tx_statistics_vector : std_logic_vector(31 downto 0); signal tx_stats : std_logic_vector(31 downto 0); signal tx_stats_shift : std_logic_vector(33 downto 0); signal tx_stats_toggle : std_logic := '0'; signal tx_stats_toggle_sync : std_logic; signal tx_stats_toggle_sync_reg : std_logic := '0'; -- Pause interface DESerialisation signal pause_req_s : std_logic := '0'; signal pause_shift : std_logic_vector(18 downto 0); signal pause_req : std_logic; signal pause_val : std_logic_vector(15 downto 0); -- AXI-Lite interface signal s_axi_awaddr : std_logic_vector(11 downto 0); signal s_axi_awvalid : std_logic; signal s_axi_awready : std_logic; signal s_axi_wdata : std_logic_vector(31 downto 0); signal s_axi_wvalid : std_logic; signal s_axi_wready : std_logic; signal s_axi_bresp : std_logic_vector(1 downto 0); signal s_axi_bvalid : std_logic; signal s_axi_bready : std_logic; signal s_axi_araddr : std_logic_vector(11 downto 0); signal s_axi_arvalid : std_logic; signal s_axi_arready : std_logic; signal s_axi_rdata : std_logic_vector(31 downto 0); signal s_axi_rresp : std_logic_vector(1 downto 0); signal s_axi_rvalid : std_logic; signal s_axi_rready : std_logic; -- signal tie offs signal tx_ifg_delay : std_logic_vector(7 downto 0) := (others => '0'); -- not used in this example signal inband_link_status : std_logic; signal inband_clock_speed : std_logic_vector(1 downto 0); signal inband_duplex_status : std_logic; signal int_frame_error : std_logic; signal int_activity_flash : std_logic; -- set board defaults - only updated when reprogrammed signal enable_phy_loopback : std_logic := '0'; -- tcp SIGNAL tcp_mac_addr : std_logic_vector(47 DOWNTO 0); SIGNAL tcp_ipv4_addr : std_logic_vector(31 DOWNTO 0); SIGNAL tcp_ipv6_addr : std_logic_vector(127 DOWNTO 0); SIGNAL tcp_subnet_mask : std_logic_vector(31 DOWNTO 0); SIGNAL tcp_gateway_ip_addr : std_logic_vector(31 DOWNTO 0); -- SIGNAL mac_rx_sof : std_logic; SIGNAL tcp_rx_data : std_logic_vector(7 DOWNTO 0); SIGNAL tcp_rx_data_valid : std_logic; SIGNAL tcp_rx_rts : std_logic; SIGNAL tcp_rx_cts : std_logic; SIGNAL tcp_tx_data : std_logic_vector(7 DOWNTO 0); SIGNAL tcp_tx_data_valid : std_logic; SIGNAL tcp_tx_cts : std_logic; -- SIGNAL tcp_rx_data_slv8x : SLV8xNTCPSTREAMStype; SIGNAL tcp_tx_data_slv8x : SLV8xNTCPSTREAMStype; SIGNAL tcp_rx_data_valid_vector : std_logic_vector((NTCPSTREAMS-1) DOWNTO 0); SIGNAL tcp_tx_cts_vector : std_logic_vector((NTCPSTREAMS-1) DOWNTO 0); -- SIGNAL rx_fifo_full : std_logic; SIGNAL rx_fifo_fullm3 : std_logic; SIGNAL tx_fifo_dout : std_logic_vector(7 DOWNTO 0); SIGNAL tx_fifo_rden : std_logic; SIGNAL tx_fifo_empty : std_logic; -- SIGNAL connection_reset_v : std_logic_vector((NTCPSTREAMS-1) DOWNTO 0); SIGNAL tcp_tx_data_valid_v : std_logic_vector((NTCPSTREAMS-1) DOWNTO 0); ------------------------------------------------------------------------------ -- Begin architecture ------------------------------------------------------------------------------ BEGIN frame_error <= int_frame_error; frame_errorn <= NOT int_frame_error; activity_flash <= int_activity_flash; activity_flashn <= NOT int_activity_flash; mac_speed <= "11"; -- gtx_clk_bufg <= gtx_clk; s_axi_aclk <= gtx_clk; sgmii125_clk <= gtx_clk; -- generate the user side clocks for the axi fifos tx_fifo_clock <= gtx_clk_bufg; rx_fifo_clock <= gtx_clk_bufg; g_resets : GlobalResetter PORT MAP ( FORCE_RST => glbl_rst, CLK => SYS_CLK, DCM_LOCKED => dcm_status_locked, CLK_RST => gclk_rst, GLOBAL_RST => grst ); phy_resetn <= NOT gclk_rst; -- check pcs_pma status once every 10 seconds and reset if necessary. -- assuming sys_clk is 300MHz dcm_status_locked <= dcm_locked AND (NOT pcs_pma_status_rst); pcs_pma_status_reset_proc : PROCESS (SYS_CLK, glbl_rst) IS VARIABLE cnt : unsigned(31 DOWNTO 0); BEGIN -- PROCESS pcs_pma_status_reset_proc IF glbl_rst = '1' THEN -- asynchronous reset cnt := to_unsigned(0, cnt'length); pcs_pma_status_rst <= '0'; ELSIF rising_edge(SYS_CLK) THEN -- rising clock edge pcs_pma_status_rst <= '0'; IF cnt = x"b2d05e00" THEN pcs_pma_status_rst <= NOT status_vector(7); cnt := to_unsigned(0, cnt'length); ELSE cnt := cnt + 1; END IF; END IF; END PROCESS pcs_pma_status_reset_proc; ------------------------------------------------------------------------------ -- Generate resets required for the fifo side signals etc ------------------------------------------------------------------------------ example_resets : tri_mode_ethernet_mac_0_example_design_resets port map ( -- clocks s_axi_aclk => s_axi_aclk, gtx_clk => gtx_clk_bufg, -- asynchronous resets glbl_rst => grst, reset_error => reset_error, rx_reset => rx_reset, tx_reset => tx_reset, dcm_locked => dcm_locked, -- synchronous reset outputs glbl_rst_intn => glbl_rst_intn, gtx_resetn => gtx_resetn, s_axi_resetn => s_axi_resetn, phy_resetn => OPEN, -- phy_resetn, chk_resetn => chk_resetn ); glbl_rst_int <= NOT glbl_rst_intn; reset_error <= '0'; -- generate the user side resets for the axi fifos tx_fifo_resetn <= gtx_resetn; rx_fifo_resetn <= gtx_resetn; ---------------------------------------------------------------------------- -- Instantiate the AXI-LITE Controller ---------------------------------------------------------------------------- axi_lite_controller : tri_mode_ethernet_mac_0_axi_lite_sm port map ( s_axi_aclk => s_axi_aclk, s_axi_resetn => s_axi_resetn, mac_speed => mac_speed, update_speed => update_speed, serial_command => pause_req_s, serial_response => serial_response, phy_loopback => enable_phy_loopback, s_axi_awaddr => s_axi_awaddr, s_axi_awvalid => s_axi_awvalid, s_axi_awready => s_axi_awready, s_axi_wdata => s_axi_wdata, s_axi_wvalid => s_axi_wvalid, s_axi_wready => s_axi_wready, s_axi_bresp => s_axi_bresp, s_axi_bvalid => s_axi_bvalid, s_axi_bready => s_axi_bready, s_axi_araddr => s_axi_araddr, s_axi_arvalid => s_axi_arvalid, s_axi_arready => s_axi_arready, s_axi_rdata => s_axi_rdata, s_axi_rresp => s_axi_rresp, s_axi_rvalid => s_axi_rvalid, s_axi_rready => s_axi_rready ); ------------------------------------------------------------------------------ -- Instantiate the TRIMAC core FIFO Block wrapper ------------------------------------------------------------------------------ trimac_fifo_block : tri_mode_ethernet_mac_0_fifo_block port map ( gtx_clk => gtx_clk_bufg, -- asynchronous reset glbl_rstn => glbl_rst_intn, rx_axi_rstn => '1', tx_axi_rstn => '1', -- Receiver Statistics Interface ----------------------------------------- rx_mac_aclk => rx_mac_aclk, rx_reset => rx_reset, rx_statistics_vector => rx_statistics_vector, rx_statistics_valid => rx_statistics_valid, -- Receiver => AXI-S Interface ------------------------------------------ rx_fifo_clock => rx_fifo_clock, rx_fifo_resetn => rx_fifo_resetn, rx_axis_fifo_tready => rx_axis_fifo_tready, rx_axis_fifo_tvalid => rx_axis_fifo_tvalid, rx_axis_fifo_tdata => rx_axis_fifo_tdata, rx_axis_fifo_tlast => rx_axis_fifo_tlast, -- Transmitter Statistics Interface -------------------------------------------- tx_mac_aclk => tx_mac_aclk, tx_reset => tx_reset, tx_ifg_delay => tx_ifg_delay, tx_statistics_vector => tx_statistics_vector, tx_statistics_valid => tx_statistics_valid, -- Transmitter => AXI-S Interface --------------------------------------------- tx_fifo_clock => tx_fifo_clock, tx_fifo_resetn => tx_fifo_resetn, tx_axis_fifo_tready => tx_axis_fifo_tready, tx_axis_fifo_tvalid => tx_axis_fifo_tvalid, tx_axis_fifo_tdata => tx_axis_fifo_tdata, tx_axis_fifo_tlast => tx_axis_fifo_tlast, -- MAC Control Interface -------------------------- pause_req => pause_req, pause_val => pause_val, -- GMII Interface ------------------- gmii_txd => gmii_txd_int, gmii_tx_en => gmii_tx_en_int, gmii_tx_er => gmii_tx_er_int, gmii_rxd => gmii_rxd_int, gmii_rx_dv => gmii_rx_dv_int, gmii_rx_er => gmii_rx_er_int, speedis100 => speed_is_100, speedis10100 => speed_is_10_100, -- MDIO Interface ----------------- mdio => mdio, mdc => mdc, -- AXI-Lite Interface ----------------- s_axi_aclk => s_axi_aclk, s_axi_resetn => s_axi_resetn, -- s_axi_awaddr => s_axi_awaddr, s_axi_awvalid => s_axi_awvalid, s_axi_awready => s_axi_awready, -- s_axi_wdata => s_axi_wdata, s_axi_wvalid => s_axi_wvalid, s_axi_wready => s_axi_wready, -- s_axi_bresp => s_axi_bresp, s_axi_bvalid => s_axi_bvalid, s_axi_bready => s_axi_bready, -- s_axi_araddr => s_axi_araddr, s_axi_arvalid => s_axi_arvalid, s_axi_arready => s_axi_arready, -- s_axi_rdata => s_axi_rdata, s_axi_rresp => s_axi_rresp, s_axi_rvalid => s_axi_rvalid, s_axi_rready => s_axi_rready ); ------------------------------------------------------------------------------ -- Instantiate the SGMII PCS/PMA core. ------------------------------------------------------------------------------ gig_pcs_pma : gig_ethernet_pcs_pma_0 PORT MAP ( -- LVDS transceiver Interface ----------------------------- txp => sgmii_tx_p, -- Differential +ve of serial transmission from PMA to PMD. txn => sgmii_tx_n, -- Differential -ve of serial transmission from PMA to PMD. rxp => sgmii_rx_p, -- Differential +ve for serial reception from PMD to PMA. rxn => sgmii_rx_n, -- Differential -ve for serial reception from PMD to PMA. -- refclk625_p => sgmii_clk_p, refclk625_n => sgmii_clk_n, mmcm_locked_out => dcm_locked, rst_125_out => OPEN, clk125_out => gtx_clk, clk312_out => OPEN, clk625_out => OPEN, idelay_rdy_out => OPEN, sgmii_clk_r => sgmii_clk_r, sgmii_clk_f => sgmii_clk_f, sgmii_clk_en => OPEN, gmii_txd => gmii_txd_int, gmii_tx_en => gmii_tx_en_int, gmii_tx_er => gmii_tx_er_int, gmii_rxd => gmii_rxd_int, gmii_rx_dv => gmii_rx_dv_int, gmii_rx_er => gmii_rx_er_int, gmii_isolate => OPEN, -- Management ----------------------------- configuration_vector => configuration_vector, -- Alternative to MDIO interface. an_interrupt => an_interrupt, -- Interrupt to processor to signal that Auto-Negotiation has completed an_adv_config_vector => an_adv_config_vector, -- Alternate interface to program REG4 (AN ADV) an_restart_config => an_restart_config, -- Alternate signal to modify AN restart bit in REG0 -- General IO's speed_is_10_100 => speed_is_10_100, speed_is_100 => speed_is_100, --------------- status_vector => status_vector, -- Core status. reset => gclk_rst, -- Asynchronous reset for entire core. signal_detect => signal_detect -- Input from PMD to indicate presence of optical input. ); signal_detect <= '1'; configuration_vector <= "10000"; -- [4]AN enable, [3]Isolate disabled, [2]Powerdowndisabled, -- [1]loopback disabled, [0]Unidirectional disabled an_adv_config_vector <= "0000000000100001"; an_restart_config <= '1'; status <= "000000000000000" & dcm_locked & status_vector; ---------------------------------------------< tcp_server PROCESS (gtx_clk_bufg) IS BEGIN -- Make configurations synchronous to CLK125 of the TCP module IF rising_edge(gtx_clk_bufg) THEN tcp_mac_addr <= MAC_ADDR; tcp_ipv4_addr <= IPv4_ADDR; tcp_ipv6_addr <= IPv6_ADDR; tcp_subnet_mask <= SUBNET_MASK; tcp_gateway_ip_addr <= GATEWAY_IP_ADDR; END IF; END PROCESS; -- generate a 1-clk wide pulse SOF (start of frame) mac_rx_sof_gen : PROCESS (gtx_clk_bufg, glbl_rst_int) IS VARIABLE state : std_logic; VARIABLE tvalid_prev : std_logic; BEGIN IF glbl_rst_int = '1' THEN state := '0'; tvalid_prev := '0'; mac_rx_sof <= '0'; ELSIF falling_edge(gtx_clk_bufg) THEN mac_rx_sof <= '0'; IF state = '0' THEN IF tvalid_prev = '0' AND rx_axis_fifo_tvalid = '1' THEN mac_rx_sof <= '1'; state := '1'; END IF; ELSE -- state = '1' IF rx_axis_fifo_tlast = '1' THEN state := '0'; END IF; END IF; tvalid_prev := rx_axis_fifo_tvalid; END IF; END PROCESS; rx_axis_fifo_tready <= '1'; tcp_rx_data <= tcp_rx_data_slv8x(0); tcp_tx_data_slv8x(0) <= tcp_tx_data; tcp_tx_cts <= tcp_tx_cts_vector(0); tcp_rx_data_valid <= tcp_rx_data_valid_vector(0); connection_reset_v <= (OTHERS => tcp_connection_reset); tcp_tx_data_valid_v <= (OTHERS => tcp_tx_data_valid); tcp_server_inst : COM5402 GENERIC MAP ( CLK_FREQUENCY => 125, -- CLK frequency in MHz. Needed to compute actual delays. TX_IDLE_TIMEOUT => 50, -- inactive input timeout, expressed in 4us units. -- 50*4us = 200us -- Controls the transmit stream segmentation: data in the elastic buffer will be transmitted if -- no input is received within TX_IDLE_TIMEOUT, without waiting for the transmit frame to be filled with MSS data bytes. SIMULATION => '0' -- 1 during simulation with Wireshark .cap file, '0' otherwise -- Wireshark many not be able to collect offloaded checksum computations. -- when SIMULATION = '1': (a) IP header checksum is valid if 0000, -- (b) TCP checksum computation is forced to a valid 00001 irrespective of the 16-bit checksum -- captured by Wireshark. ) PORT MAP ( --//-- CLK, RESET CLK => gtx_clk_bufg, -- All signals are synchronous with CLK -- CLK must be a global clock 125 MHz or faster to match the Gbps MAC speed. ASYNC_RESET => glbl_rst_int, -- to be phased out. replace with SYNC_RESET SYNC_RESET => glbl_rst_int, --//-- CONFIGURATION -- configuration signals are synchonous with CLK -- Synchronous with CLK clock. MAC_ADDR => tcp_mac_addr, IPv4_ADDR => tcp_ipv4_addr, IPv6_ADDR => tcp_ipv6_addr, SUBNET_MASK => tcp_subnet_mask, GATEWAY_IP_ADDR => tcp_gateway_ip_addr, -- local IP address. 4 bytes for IPv4, 16 bytes for IPv6 -- Natural order (MSB) 172.16.1.128 (LSB) as transmitted in the IP frame. --// User-initiated connection reset for stream I CONNECTION_RESET => connection_reset_v, --//-- Protocol -> Transmit MAC Interface -- 32-bit CRC is automatically appended by the MAC layer. User should not supply it. -- Synchonous with the user-side CLK MAC_TX_DATA => tx_axis_fifo_tdata, -- MAC reads the data at the rising edge of CLK when MAC_TX_DATA_VALID = '1' MAC_TX_DATA_VALID => tx_axis_fifo_tvalid, -- data valid MAC_TX_SOF => OPEN, -- start of frame: '1' when sending the first byte. MAC_TX_EOF => tx_axis_fifo_tlast, -- '1' when sending the last byte in a packet to be transmitted. -- Aligned with MAC_TX_DATA_VALID MAC_TX_CTS => tx_axis_fifo_tready, -- MAC-generated Clear To Send flow control signal, indicating room in the -- MAC tx elastic buffer for a complete maximum size frame 1518B. -- The user should check that this signal is high before deciding to send -- sending the next frame. -- Note: MAC_TX_CTS may go low while the frame is transfered in. Ignore it as space is guaranteed -- at the start of frame. --//-- Receive MAC -> Protocol -- Valid rx packets only: packets with bad CRC or invalid address are discarded. -- The 32-bit CRC is always removed by the MAC layer. -- Synchonous with the user-side CLK MAC_RX_DATA => rx_axis_fifo_tdata, -- USER reads the data at the rising edge of CLK when MAC_RX_DATA_VALID = '1' MAC_RX_DATA_VALID => rx_axis_fifo_tvalid, -- data valid MAC_RX_SOF => mac_rx_sof, -- '1' when sending the first byte in a received packet. -- Aligned with MAC_RX_DATA_VALID MAC_RX_EOF => rx_axis_fifo_tlast, -- '1' when sending the last byte in a received packet. -- Aligned with MAC_RX_DATA_VALID --//-- Application <- UDP rx UDP_RX_DATA => OPEN, UDP_RX_DATA_VALID => OPEN, UDP_RX_SOF => OPEN, UDP_RX_EOF => OPEN, -- 1 CLK pulse indicating that UDP_RX_DATA is the last byte in the UDP data field. -- ALWAYS CHECK UDP_RX_DATA_VALID at the end of packet (UDP_RX_EOF = '1') to confirm -- that the UDP packet is valid. External buffer may have to backtrack to the the last -- valid pointer to discard an invalid UDP packet. -- Reason: we only knows about bad UDP packets at the end. UDP_RX_DEST_PORT_NO => (OTHERS => '0'), --//-- Application -> UDP tx UDP_TX_DATA => (OTHERS => '0'), UDP_TX_DATA_VALID => '0', UDP_TX_SOF => '0', -- 1 CLK-wide pulse to mark the first byte in the tx UDP frame UDP_TX_EOF => '0', -- 1 CLK-wide pulse to mark the last byte in the tx UDP frame UDP_TX_CTS => OPEN, UDP_TX_ACK => OPEN, -- 1 CLK-wide pulse indicating that the previous UDP frame is being sent UDP_TX_NAK => OPEN, -- 1 CLK-wide pulse indicating that the previous UDP frame could not be sent UDP_TX_DEST_IP_ADDR => (OTHERS => '0'), UDP_TX_DEST_PORT_NO => (OTHERS => '0'), UDP_TX_SOURCE_PORT_NO => (OTHERS => '0'), --//-- Application <- TCP rx -- NTCPSTREAMS can operate independently. Only one stream active at any given time. -- Data is pushed out. Limited flow-control here. Receipient must be able to accept data -- at any time (in other words, it is the receipient's responsibility to have elastic -- buffer if needed). TCP_RX_DATA => tcp_rx_data_slv8x, TCP_RX_DATA_VALID => tcp_rx_data_valid_vector, TCP_RX_RTS => tcp_rx_rts, TCP_RX_CTS => tcp_rx_cts, -- Optional Clear-To-Send. pull to '1' when output flow control is unused. -- WARNING: pulling CTS down will stop the flow for ALL streams. --//-- Application -> TCP tx -- NTCPSTREAMS can operate independently and concurrently. No scheduling arbitration needed here. TCP_TX_DATA => tcp_tx_data_slv8x, TCP_TX_DATA_VALID => tcp_tx_data_valid_v, TCP_TX_CTS => tcp_tx_cts_vector, -- Clear To Send = transmit flow control. -- App is responsible for checking the CTS signal before sending APP_DATA --//-- TEST POINTS, COMSCOPE TRACES CS1 => OPEN, CS1_CLK => OPEN, CS2 => OPEN, CS2_CLK => OPEN, TP => OPEN ); -- Must have programmable full with single-threshold of 61 -- out of total write-depth 64. -- When RX_CTS is low, the Server continues to drive out 3 more bytes of data -- (observed with ILA). The fifo must be able to accept them, hence the use -- of prog_full. rx_fifo_inst : fifo8to32 PORT MAP ( rst => glbl_rst_int, wr_clk => gtx_clk_bufg, rd_clk => RX_FIFO_RDCLK, din => tcp_rx_data, wr_en => tcp_rx_data_valid, rd_en => RX_FIFO_RDEN, dout => RX_FIFO_Q, full => rx_fifo_full, prog_full => rx_fifo_fullm3, -- asserted at (full-3) writes empty => RX_FIFO_EMPTY ); tcp_rx_cts <= (NOT rx_fifo_fullm3) WHEN TCP_USE_FIFO = '1' ELSE RX_TREADY; RX_TDATA <= tcp_rx_data; RX_TVALID <= tcp_rx_data_valid; tx_fifo_inst : fifo32to8 PORT MAP ( rst => glbl_rst_int, wr_clk => TX_FIFO_WRCLK, rd_clk => gtx_clk_bufg, din => TX_FIFO_Q, wr_en => TX_FIFO_WREN, rd_en => tx_fifo_rden, dout => tx_fifo_dout, full => TX_FIFO_FULL, empty => tx_fifo_empty ); tcp_tx_data_valid <= ((NOT tx_fifo_empty) AND tcp_tx_cts) WHEN TCP_USE_FIFO = '1' ELSE TX_TVALID; tx_fifo_rden <= tcp_tx_data_valid; tcp_tx_data <= tx_fifo_dout WHEN TCP_USE_FIFO = '1' ELSE TX_TDATA; TX_TREADY <= tcp_tx_cts; END wrapper;
-------------------------------------------------------------------------------- -- Designer: Paolo Fulgoni <[email protected]> -- -- Create Date: 02/01/2008 -- Last Update: 03/28/2008 -- Project Name: camellia-vhdl -- Description: Looping version of Camellia -- -- Copyright (C) 2008 Paolo Fulgoni -- This file is part of camellia-vhdl. -- camellia-vhdl is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 3 of the License, or -- (at your option) any later version. -- camellia-vhdl is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- You should have received a copy of the GNU General Public License -- along with this program. If not, see <http://www.gnu.org/licenses/>. -- -- The Camellia cipher algorithm is 128 bit cipher developed by NTT and -- Mitsubishi Electric researchers. -- http://info.isl.ntt.co.jp/crypt/eng/camellia/ -------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; entity camellia is port ( clk : in STD_LOGIC; reset : in STD_LOGIC; data_in : in STD_LOGIC_VECTOR (0 to 127); enc_dec : in STD_LOGIC; data_rdy : in STD_LOGIC; data_acq : out STD_LOGIC; key : in STD_LOGIC_VECTOR (0 to 255); k_len : in STD_LOGIC_VECTOR (0 to 1); key_rdy : in STD_LOGIC; key_acq : out STD_LOGIC; data_out : out STD_LOGIC_VECTOR (0 to 127); output_rdy : out STD_LOGIC -- post-synthesis debug ); end camellia; architecture RTL of camellia is signal s_clk : STD_LOGIC; signal s_reset : STD_LOGIC; signal s_data_in : STD_LOGIC_VECTOR (0 to 127); signal s_enc_dec : STD_LOGIC; signal s_data_rdy : STD_LOGIC; signal s_data_acq : STD_LOGIC; signal s_key_in : STD_LOGIC_VECTOR (0 to 255); signal s_k_len : STD_LOGIC_VECTOR (0 to 1); signal s_key_rdy : STD_LOGIC; signal s_key_acq : STD_LOGIC; signal s_data_to : STD_LOGIC_VECTOR (0 to 127); signal s_output_rdy : STD_LOGIC; signal s_k1 : STD_LOGIC_VECTOR (0 to 63); signal s_k2 : STD_LOGIC_VECTOR (0 to 63); signal s_newdata : STD_LOGIC; signal s_sel : STD_LOGIC; signal s_pre_xor : STD_LOGIC_VECTOR (0 to 127); signal s_post_xor : STD_LOGIC_VECTOR (0 to 127); signal s_data_from : STD_LOGIC_VECTOR (0 to 127); component datapath is port ( clk : in STD_LOGIC; reset : in STD_LOGIC; data_in : in STD_LOGIC_VECTOR (0 to 127); k1 : in STD_LOGIC_VECTOR (0 to 63); k2 : in STD_LOGIC_VECTOR (0 to 63); newdata : in STD_LOGIC; sel : in STD_LOGIC; pre_xor : in STD_LOGIC_VECTOR (0 to 127); post_xor : in STD_LOGIC_VECTOR (0 to 127); data_out : out STD_LOGIC_VECTOR (0 to 127) ); end component; component control is port ( clk : in STD_LOGIC; reset : in STD_LOGIC; data_in : in STD_LOGIC_VECTOR (0 to 127); enc_dec : in STD_LOGIC; data_rdy : in STD_LOGIC; data_acq : out STD_LOGIC; key_in : in STD_LOGIC_VECTOR (0 to 255); k_len : in STD_LOGIC_VECTOR (0 to 1); key_rdy : in STD_LOGIC; key_acq : out STD_LOGIC; data_to : out STD_LOGIC_VECTOR (0 to 127); output_rdy : out STD_LOGIC; k1 : out STD_LOGIC_VECTOR (0 to 63); k2 : out STD_LOGIC_VECTOR (0 to 63); newdata : out STD_LOGIC; sel : out STD_LOGIC; pre_xor : out STD_LOGIC_VECTOR (0 to 127); post_xor : out STD_LOGIC_VECTOR (0 to 127); data_from : in STD_LOGIC_VECTOR (0 to 127) ); end component; begin DP : datapath port map( clk => s_clk, reset => s_reset, data_in => s_data_to, k1 => s_k1, k2 => s_k2, newdata => s_newdata, sel => s_sel, pre_xor => s_pre_xor, post_xor => s_post_xor, data_out => s_data_from ); CTRL : control port map( clk => s_clk, reset => s_reset, data_in => s_data_in, enc_dec => s_enc_dec, data_rdy => s_data_rdy, data_acq => s_data_acq, key_in => s_key_in, k_len => s_k_len, key_rdy => s_key_rdy, key_acq => s_key_acq, data_to => s_data_to, output_rdy => s_output_rdy, k1 => s_k1, k2 => s_k2, newdata => s_newdata, sel => s_sel, pre_xor => s_pre_xor, post_xor => s_post_xor, data_from => s_data_from ); s_clk <= clk; s_reset <= reset; s_data_in <= data_in; s_enc_dec <= enc_dec; s_data_rdy <= data_rdy; s_key_in <= key; s_k_len <= k_len; s_key_rdy <= key_rdy; data_acq <= s_data_acq; key_acq <= s_key_acq; data_out <= s_data_from(64 to 127) & s_data_from(0 to 63); output_rdy <= s_output_rdy; end RTL;
-------------------------------------------------------------------------------- -- Company: -- Engineer: LJW -- -- Create Date: 22:26:31 04/18/05 -- Design Name: -- Module Name: Clock+MpxInd - Behavioral -- Project Name: IBM2030 -- Target Device: XC3S1000 -- Tool versions: ISE V7.1 -- Description: Four-phase clock generation and Multiplexor channel indicators -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ClockMpxInd is Port ( -- Clock stuff CLOCK_IN : in std_logic; T1,T2,T3,T4 : out std_logic; P1,P2,P3,P4 : out std_logic; OSC_T_LINE : out std_logic; -- 12A M_CONV_OSC : out std_logic; -- 03C P_CONV_OSC : out std_logic; -- 03D,03C M_CONV_OSC_2 : out std_logic; -- 03C CLOCK_ON : out std_logic; -- 03D,04A,03C,13B,12A,11B CLOCK_OFF : out std_logic; -- 04B,06C,09B,03D CLOCK_START : in std_logic; -- 03C MACH_RST_3 : in std_logic; -- 03D -- Mpx Indicator stuff TEST_LAMP : in std_Logic; -- 04A OPNL_IN,ADDR_IN,STATUS_IN,SERVICE_IN, SELECT_OUT,ADDR_OUT,COMMAND_OUT,SERVICE_OUT, SUPPRESS_OUT : in std_logic; -- 08D FO_P : in std_logic; -- 08C FO : in std_logic_vector(0 to 7); -- 08C IND_OPNL_IN, IND_ADDR_IN,IND_STATUS_IN,IND_SERV_IN, IND_SEL_OUT,IND_ADDR_OUT,IND_CMMD_OUT,IND_SERV_OUT, IND_SUPPR_OUT,IND_FO_P : out std_logic; IND_FO : out std_logic_vector(0 to 7) ); end ClockMpxInd; architecture slt of ClockMpxInd is -- subtype DividerSize is STD_LOGIC_VECTOR(5 downto 0); -- constant RATIO : DividerSize := "001111"; -- 16 gives 3.125MHz -- subtype DividerSize is STD_LOGIC_VECTOR(25 downto 0); -- constant RATIO : DividerSize := "00111100000000000000000000"; -- 16M gives 3.125Hz subtype DividerSize is STD_LOGIC_VECTOR(25 downto 0); constant RATIO : DividerSize := "00010011000100101101000000"; -- 5M gives 10Hz constant ZERO : DividerSize := (others=>'0'); constant ONE : DividerSize := (0=>'1',others=>'0'); signal DIVIDER : DividerSize; signal OSC2,OSC,DLYD_OSC : STD_LOGIC; -- signal SETS,RSTS : STD_LOGIC_VECTOR(1 to 4); signal CLK : STD_LOGIC_VECTOR(1 to 4); begin -- Divide the 50MHz FPGA clock down -- 1.5us storage cycle means T1-4 takes 750ns, or 3MHz -- OSC2 is actually double the original oscillator as only one edge is used process (CLOCK_IN) begin if CLOCK_IN'event and CLOCK_IN='1' then if DIVIDER=RATIO then DIVIDER <= ZERO; OSC2 <= not OSC2; else DIVIDER <= DIVIDER + ONE; end if; end if; end process; -- AC1K6,AC1C6 Probably have to re-do this lot to get it work --SETS(1) <= not DLYD_OSC and CLOCK_START and not CLK(3) and CLK(4); --SETS(2) <= DLYD_OSC not CLK(4) and CLK(1); --SETS(3) <= not DLYD_OSC and not CLK(1) and CLK(2); --SETS(4) <= (DLYD_OSC and not CLK(2) and CLK(3)) or MACH_RST_3='1'; --RSTS(1) <= (not DLYD_OSC and CLK(2)) or MACH_RST_3='1'; --RSTS(2) <= (OSC and CLK(3)) or MACH_RST_3='1'; --RSTS(3) <= (not DLYD_OSC and CLK(4)) or MACH_RST_3='1'; --RSTS(4) <= OSC and CLK(1); --FLV(SETS,RSTS,CLK); -- AC1C6 -- The following process forms a ring counter -- MACH_RST_3 forces the counter to 0001 -- If CLOCK_START is false, the counter stays at 0001 -- When CLOCK_START goes true, the counter cycles through -- 0001 0001 0001 1001 1100 0110 0011 1001 1100 .... -- When CLOCK_START subsequently goes false, the sequence continues -- until reaching 0011, after which it stays at 0001 -- ... 1001 1100 0110 0011 0001 0001 0001 ... -- The original counter used a level-triggered implementation, driven by -- both levels of the OSC signal. Here it is easier to make it edge triggered -- which requires a clock of twice the frequency, hence OSC2 process (OSC2, MACH_RST_3) begin if OSC2'event and OSC2='1' then if OSC='0' then -- Rising edge OSC <= '1'; if CLK(2)='1' or MACH_RST_3='1' then CLK(1) <= '0'; elsif CLOCK_START='1' and CLK(4)='1' then CLK(1) <= '1'; end if; if CLK(4)='1' or MACH_RST_3='1' then CLK(3) <= '0'; elsif CLK(2)='1' then CLK(3) <= '1'; end if; else -- Falling edge OSC <= '0'; if CLK(3)='1' or MACH_RST_3='1' then CLK(2) <= '0'; elsif CLK(1)='1' then CLK(2) <= '1'; end if; if CLK(3)='1' or MACH_RST_3='1' then CLK(4) <= '1'; elsif CLK(1)='1' then CLK(4) <= '0'; end if; end if; end if; end process; OSC_T_LINE <= not OSC; M_CONV_OSC <= OSC; DLYD_OSC <= OSC; -- AC1C6 P1 <= CLK(1); P2 <= CLK(2); P3 <= CLK(3); P4 <= CLK(4); T1 <= CLK(4) and CLK(1); T2 <= CLK(1) and CLK(2); T3 <= CLK(2) and CLK(3); T4 <= CLK(3) and CLK(4); CLOCK_ON <= CLK(1) or CLK(2) or CLK(3); CLOCK_OFF <= not (CLK(1) or CLK(2) or CLK(3)); P_CONV_OSC <= OSC and not (CLK(1) or CLK(2) or CLK(3)); M_CONV_OSC_2 <= OSC and not (CLK(1) or CLK(2) or CLK(3)); -- Note: Not inverted, despite the name -- The indicator drivers for the Multiplexor channel are here IND_OPNL_IN <= OPNL_IN or TEST_LAMP; IND_ADDR_IN <= ADDR_IN or TEST_LAMP; IND_STATUS_IN <= STATUS_IN or TEST_LAMP; IND_SERV_IN <= SERVICE_IN or TEST_LAMP; IND_SEL_OUT <= SELECT_OUT or TEST_LAMP; IND_ADDR_OUT <= ADDR_OUT or TEST_LAMP; IND_CMMD_OUT <= COMMAND_OUT or TEST_LAMP; IND_SERV_OUT <= SERVICE_OUT or TEST_LAMP; IND_SUPPR_OUT <= SUPPRESS_OUT or TEST_LAMP; IND_FO_P <= FO_P or TEST_LAMP; IND_FO <= FO or (FO'range => TEST_LAMP); end slt;
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0 -- IP Revision: 7 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY proc_sys_reset_v5_0; USE proc_sys_reset_v5_0.proc_sys_reset; ENTITY triangle_intersect_rst_processing_system7_0_100M_0 IS PORT ( slowest_sync_clk : IN STD_LOGIC; ext_reset_in : IN STD_LOGIC; aux_reset_in : IN STD_LOGIC; mb_debug_sys_rst : IN STD_LOGIC; dcm_locked : IN STD_LOGIC; mb_reset : OUT STD_LOGIC; bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) ); END triangle_intersect_rst_processing_system7_0_100M_0; ARCHITECTURE triangle_intersect_rst_processing_system7_0_100M_0_arch OF triangle_intersect_rst_processing_system7_0_100M_0 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : string; ATTRIBUTE DowngradeIPIdentifiedWarnings OF triangle_intersect_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "yes"; COMPONENT proc_sys_reset IS GENERIC ( C_FAMILY : STRING; C_EXT_RST_WIDTH : INTEGER; C_AUX_RST_WIDTH : INTEGER; C_EXT_RESET_HIGH : STD_LOGIC; C_AUX_RESET_HIGH : STD_LOGIC; C_NUM_BUS_RST : INTEGER; C_NUM_PERP_RST : INTEGER; C_NUM_INTERCONNECT_ARESETN : INTEGER; C_NUM_PERP_ARESETN : INTEGER ); PORT ( slowest_sync_clk : IN STD_LOGIC; ext_reset_in : IN STD_LOGIC; aux_reset_in : IN STD_LOGIC; mb_debug_sys_rst : IN STD_LOGIC; dcm_locked : IN STD_LOGIC; mb_reset : OUT STD_LOGIC; bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0) ); END COMPONENT proc_sys_reset; ATTRIBUTE X_CORE_INFO : STRING; ATTRIBUTE X_CORE_INFO OF triangle_intersect_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2015.1"; ATTRIBUTE CHECK_LICENSE_TYPE : STRING; ATTRIBUTE CHECK_LICENSE_TYPE OF triangle_intersect_rst_processing_system7_0_100M_0_arch : ARCHITECTURE IS "triangle_intersect_rst_processing_system7_0_100M_0,proc_sys_reset,{}"; ATTRIBUTE CORE_GENERATION_INFO : STRING; ATTRIBUTE CORE_GENERATION_INFO OF triangle_intersect_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "triangle_intersect_rst_processing_system7_0_100M_0,proc_sys_reset,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=7,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}"; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK"; ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST"; ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST"; ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST"; ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST"; ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST"; ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST"; ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST"; ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST"; BEGIN U0 : proc_sys_reset GENERIC MAP ( C_FAMILY => "zynq", C_EXT_RST_WIDTH => 4, C_AUX_RST_WIDTH => 4, C_EXT_RESET_HIGH => '0', C_AUX_RESET_HIGH => '0', C_NUM_BUS_RST => 1, C_NUM_PERP_RST => 1, C_NUM_INTERCONNECT_ARESETN => 1, C_NUM_PERP_ARESETN => 1 ) PORT MAP ( slowest_sync_clk => slowest_sync_clk, ext_reset_in => ext_reset_in, aux_reset_in => aux_reset_in, mb_debug_sys_rst => mb_debug_sys_rst, dcm_locked => dcm_locked, mb_reset => mb_reset, bus_struct_reset => bus_struct_reset, peripheral_reset => peripheral_reset, interconnect_aresetn => interconnect_aresetn, peripheral_aresetn => peripheral_aresetn ); END triangle_intersect_rst_processing_system7_0_100M_0_arch;
-- niosII_system.vhd -- Generated using ACDS version 13.0sp1 232 at 2016.04.06.21:13:30 library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity niosII_system is port ( clk_clk : in std_logic := '0'; -- clk.clk reset_reset_n : in std_logic := '0'; -- reset.reset_n green_leds_external_connection_export : out std_logic_vector(7 downto 0); -- green_leds_external_connection.export switches_external_connection_export : in std_logic_vector(7 downto 0) := (others => '0'); -- switches_external_connection.export sdram_0_wire_addr : out std_logic_vector(11 downto 0); -- sdram_0_wire.addr sdram_0_wire_ba : out std_logic_vector(1 downto 0); -- .ba sdram_0_wire_cas_n : out std_logic; -- .cas_n sdram_0_wire_cke : out std_logic; -- .cke sdram_0_wire_cs_n : out std_logic; -- .cs_n sdram_0_wire_dq : inout std_logic_vector(15 downto 0) := (others => '0'); -- .dq sdram_0_wire_dqm : out std_logic_vector(1 downto 0); -- .dqm sdram_0_wire_ras_n : out std_logic; -- .ras_n sdram_0_wire_we_n : out std_logic; -- .we_n sram_0_external_interface_DQ : inout std_logic_vector(15 downto 0) := (others => '0'); -- sram_0_external_interface.DQ sram_0_external_interface_ADDR : out std_logic_vector(17 downto 0); -- .ADDR sram_0_external_interface_LB_N : out std_logic; -- .LB_N sram_0_external_interface_UB_N : out std_logic; -- .UB_N sram_0_external_interface_CE_N : out std_logic; -- .CE_N sram_0_external_interface_OE_N : out std_logic; -- .OE_N sram_0_external_interface_WE_N : out std_logic; -- .WE_N altpll_0_c0_clk : out std_logic; -- altpll_0_c0.clk usb_0_external_interface_INT1 : in std_logic := '0'; -- usb_0_external_interface.INT1 usb_0_external_interface_DATA : inout std_logic_vector(15 downto 0) := (others => '0'); -- .DATA usb_0_external_interface_RST_N : out std_logic; -- .RST_N usb_0_external_interface_ADDR : out std_logic_vector(1 downto 0); -- .ADDR usb_0_external_interface_CS_N : out std_logic; -- .CS_N usb_0_external_interface_RD_N : out std_logic; -- .RD_N usb_0_external_interface_WR_N : out std_logic; -- .WR_N usb_0_external_interface_INT0 : in std_logic := '0'; -- .INT0 rs232_0_external_interface_RXD : in std_logic := '0'; -- rs232_0_external_interface.RXD rs232_0_external_interface_TXD : out std_logic; -- .TXD tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_read_n_out : out std_logic_vector(0 downto 0); -- tristate_conduit_bridge_0_out.generic_tristate_controller_0_tcm_read_n_out tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_data_out : inout std_logic_vector(7 downto 0) := (others => '0'); -- .generic_tristate_controller_0_tcm_data_out tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_chipselect_n_out : out std_logic_vector(0 downto 0); -- .generic_tristate_controller_0_tcm_chipselect_n_out tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_write_n_out : out std_logic_vector(0 downto 0); -- .generic_tristate_controller_0_tcm_write_n_out tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_byteenable_out : out std_logic_vector(0 downto 0); -- .generic_tristate_controller_0_tcm_byteenable_out tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_begintransfer_out : out std_logic_vector(0 downto 0); -- .generic_tristate_controller_0_tcm_begintransfer_out tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_address_out : out std_logic_vector(21 downto 0) -- .generic_tristate_controller_0_tcm_address_out ); end entity niosII_system; architecture rtl of niosII_system is component niosII_system_nios2_qsys_0 is port ( clk : in std_logic := 'X'; -- clk reset_n : in std_logic := 'X'; -- reset_n d_address : out std_logic_vector(24 downto 0); -- address d_byteenable : out std_logic_vector(3 downto 0); -- byteenable d_read : out std_logic; -- read d_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata d_waitrequest : in std_logic := 'X'; -- waitrequest d_write : out std_logic; -- write d_writedata : out std_logic_vector(31 downto 0); -- writedata jtag_debug_module_debugaccess_to_roms : out std_logic; -- debugaccess i_address : out std_logic_vector(24 downto 0); -- address i_read : out std_logic; -- read i_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata i_waitrequest : in std_logic := 'X'; -- waitrequest d_irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq jtag_debug_module_resetrequest : out std_logic; -- reset jtag_debug_module_address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address jtag_debug_module_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable jtag_debug_module_debugaccess : in std_logic := 'X'; -- debugaccess jtag_debug_module_read : in std_logic := 'X'; -- read jtag_debug_module_readdata : out std_logic_vector(31 downto 0); -- readdata jtag_debug_module_waitrequest : out std_logic; -- waitrequest jtag_debug_module_write : in std_logic := 'X'; -- write jtag_debug_module_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata no_ci_readra : out std_logic -- readra ); end component niosII_system_nios2_qsys_0; component niosII_system_onchip_memory2_0 is port ( clk : in std_logic := 'X'; -- clk address : in std_logic_vector(11 downto 0) := (others => 'X'); -- address clken : in std_logic := 'X'; -- clken chipselect : in std_logic := 'X'; -- chipselect write : in std_logic := 'X'; -- write readdata : out std_logic_vector(31 downto 0); -- readdata writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable reset : in std_logic := 'X'; -- reset reset_req : in std_logic := 'X' -- reset_req ); end component niosII_system_onchip_memory2_0; component niosII_system_sysid_qsys_0 is port ( clock : in std_logic := 'X'; -- clk reset_n : in std_logic := 'X'; -- reset_n readdata : out std_logic_vector(31 downto 0); -- readdata address : in std_logic := 'X' -- address ); end component niosII_system_sysid_qsys_0; component niosII_system_jtag_uart_0 is port ( clk : in std_logic := 'X'; -- clk rst_n : in std_logic := 'X'; -- reset_n av_chipselect : in std_logic := 'X'; -- chipselect av_address : in std_logic := 'X'; -- address av_read_n : in std_logic := 'X'; -- read_n av_readdata : out std_logic_vector(31 downto 0); -- readdata av_write_n : in std_logic := 'X'; -- write_n av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata av_waitrequest : out std_logic; -- waitrequest av_irq : out std_logic -- irq ); end component niosII_system_jtag_uart_0; component niosII_system_green_leds is port ( clk : in std_logic := 'X'; -- clk reset_n : in std_logic := 'X'; -- reset_n address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address write_n : in std_logic := 'X'; -- write_n writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata chipselect : in std_logic := 'X'; -- chipselect readdata : out std_logic_vector(31 downto 0); -- readdata out_port : out std_logic_vector(7 downto 0) -- export ); end component niosII_system_green_leds; component niosII_system_switches is port ( clk : in std_logic := 'X'; -- clk reset_n : in std_logic := 'X'; -- reset_n address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address readdata : out std_logic_vector(31 downto 0); -- readdata in_port : in std_logic_vector(7 downto 0) := (others => 'X') -- export ); end component niosII_system_switches; component niosII_system_altpll_0 is port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset read : in std_logic := 'X'; -- read write : in std_logic := 'X'; -- write address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address readdata : out std_logic_vector(31 downto 0); -- readdata writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata c0 : out std_logic; -- clk c1 : out std_logic; -- clk areset : in std_logic := 'X'; -- export locked : out std_logic; -- export phasedone : out std_logic -- export ); end component niosII_system_altpll_0; component niosII_system_sdram_0 is port ( clk : in std_logic := 'X'; -- clk reset_n : in std_logic := 'X'; -- reset_n az_addr : in std_logic_vector(21 downto 0) := (others => 'X'); -- address az_be_n : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable_n az_cs : in std_logic := 'X'; -- chipselect az_data : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata az_rd_n : in std_logic := 'X'; -- read_n az_wr_n : in std_logic := 'X'; -- write_n za_data : out std_logic_vector(15 downto 0); -- readdata za_valid : out std_logic; -- readdatavalid za_waitrequest : out std_logic; -- waitrequest zs_addr : out std_logic_vector(11 downto 0); -- export zs_ba : out std_logic_vector(1 downto 0); -- export zs_cas_n : out std_logic; -- export zs_cke : out std_logic; -- export zs_cs_n : out std_logic; -- export zs_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- export zs_dqm : out std_logic_vector(1 downto 0); -- export zs_ras_n : out std_logic; -- export zs_we_n : out std_logic -- export ); end component niosII_system_sdram_0; component niosII_system_sram_0 is port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset SRAM_DQ : inout std_logic_vector(15 downto 0) := (others => 'X'); -- export SRAM_ADDR : out std_logic_vector(17 downto 0); -- export SRAM_LB_N : out std_logic; -- export SRAM_UB_N : out std_logic; -- export SRAM_CE_N : out std_logic; -- export SRAM_OE_N : out std_logic; -- export SRAM_WE_N : out std_logic; -- export address : in std_logic_vector(17 downto 0) := (others => 'X'); -- address byteenable : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable read : in std_logic := 'X'; -- read write : in std_logic := 'X'; -- write writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata readdata : out std_logic_vector(15 downto 0); -- readdata readdatavalid : out std_logic -- readdatavalid ); end component niosII_system_sram_0; component niosII_system_timer_0 is port ( clk : in std_logic := 'X'; -- clk reset_n : in std_logic := 'X'; -- reset_n address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata readdata : out std_logic_vector(15 downto 0); -- readdata chipselect : in std_logic := 'X'; -- chipselect write_n : in std_logic := 'X'; -- write_n irq : out std_logic -- irq ); end component niosII_system_timer_0; component niosII_system_usb_0 is port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address chipselect : in std_logic := 'X'; -- chipselect read : in std_logic := 'X'; -- read write : in std_logic := 'X'; -- write writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata readdata : out std_logic_vector(15 downto 0); -- readdata irq : out std_logic; -- irq OTG_INT1 : in std_logic := 'X'; -- export OTG_DATA : inout std_logic_vector(15 downto 0) := (others => 'X'); -- export OTG_RST_N : out std_logic; -- export OTG_ADDR : out std_logic_vector(1 downto 0); -- export OTG_CS_N : out std_logic; -- export OTG_RD_N : out std_logic; -- export OTG_WR_N : out std_logic; -- export OTG_INT0 : in std_logic := 'X' -- export ); end component niosII_system_usb_0; component niosII_system_rs232_0 is port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset address : in std_logic := 'X'; -- address chipselect : in std_logic := 'X'; -- chipselect byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable read : in std_logic := 'X'; -- read write : in std_logic := 'X'; -- write writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata readdata : out std_logic_vector(31 downto 0); -- readdata irq : out std_logic; -- irq UART_RXD : in std_logic := 'X'; -- export UART_TXD : out std_logic -- export ); end component niosII_system_rs232_0; component niosII_system_generic_tristate_controller_0 is generic ( TCM_ADDRESS_W : integer := 30; TCM_DATA_W : integer := 32; TCM_BYTEENABLE_W : integer := 4; TCM_READ_WAIT : integer := 1; TCM_WRITE_WAIT : integer := 0; TCM_SETUP_WAIT : integer := 0; TCM_DATA_HOLD : integer := 0; TCM_TURNAROUND_TIME : integer := 2; TCM_TIMING_UNITS : integer := 1; TCM_READLATENCY : integer := 2; TCM_SYMBOLS_PER_WORD : integer := 4; USE_READDATA : integer := 1; USE_WRITEDATA : integer := 1; USE_READ : integer := 1; USE_WRITE : integer := 1; USE_BYTEENABLE : integer := 1; USE_CHIPSELECT : integer := 0; USE_LOCK : integer := 0; USE_ADDRESS : integer := 1; USE_WAITREQUEST : integer := 0; USE_WRITEBYTEENABLE : integer := 0; USE_OUTPUTENABLE : integer := 0; USE_RESETREQUEST : integer := 0; USE_IRQ : integer := 0; USE_RESET_OUTPUT : integer := 0; ACTIVE_LOW_READ : integer := 0; ACTIVE_LOW_LOCK : integer := 0; ACTIVE_LOW_WRITE : integer := 0; ACTIVE_LOW_CHIPSELECT : integer := 0; ACTIVE_LOW_BYTEENABLE : integer := 0; ACTIVE_LOW_OUTPUTENABLE : integer := 0; ACTIVE_LOW_WRITEBYTEENABLE : integer := 0; ACTIVE_LOW_WAITREQUEST : integer := 0; ACTIVE_LOW_BEGINTRANSFER : integer := 0; CHIPSELECT_THROUGH_READLATENCY : integer := 0 ); port ( clk_clk : in std_logic := 'X'; -- clk reset_reset : in std_logic := 'X'; -- reset uas_address : in std_logic_vector(21 downto 0) := (others => 'X'); -- address uas_burstcount : in std_logic_vector(0 downto 0) := (others => 'X'); -- burstcount uas_read : in std_logic := 'X'; -- read uas_write : in std_logic := 'X'; -- write uas_waitrequest : out std_logic; -- waitrequest uas_readdatavalid : out std_logic; -- readdatavalid uas_byteenable : in std_logic_vector(0 downto 0) := (others => 'X'); -- byteenable uas_readdata : out std_logic_vector(7 downto 0); -- readdata uas_writedata : in std_logic_vector(7 downto 0) := (others => 'X'); -- writedata uas_lock : in std_logic := 'X'; -- lock uas_debugaccess : in std_logic := 'X'; -- debugaccess tcm_write_n_out : out std_logic; -- write_n_out tcm_read_n_out : out std_logic; -- read_n_out tcm_begintransfer_out : out std_logic; -- begintransfer_out tcm_chipselect_n_out : out std_logic; -- chipselect_n_out tcm_request : out std_logic; -- request tcm_grant : in std_logic := 'X'; -- grant tcm_address_out : out std_logic_vector(21 downto 0); -- address_out tcm_byteenable_out : out std_logic; -- byteenable_out tcm_data_out : out std_logic_vector(7 downto 0); -- data_out tcm_data_outen : out std_logic; -- data_outen tcm_data_in : in std_logic_vector(7 downto 0) := (others => 'X') -- data_in ); end component niosII_system_generic_tristate_controller_0; component niosII_system_tristate_conduit_bridge_0 is port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset request : in std_logic := 'X'; -- request grant : out std_logic; -- grant tcs_generic_tristate_controller_0_tcm_read_n_out : in std_logic_vector(0 downto 0) := (others => 'X'); -- generic_tristate_controller_0_tcm_read_n_out_out tcs_generic_tristate_controller_0_tcm_data_out : in std_logic_vector(7 downto 0) := (others => 'X'); -- generic_tristate_controller_0_tcm_data_out_out tcs_generic_tristate_controller_0_tcm_data_outen : in std_logic := 'X'; -- generic_tristate_controller_0_tcm_data_out_outen tcs_generic_tristate_controller_0_tcm_data_in : out std_logic_vector(7 downto 0); -- generic_tristate_controller_0_tcm_data_out_in tcs_generic_tristate_controller_0_tcm_chipselect_n_out : in std_logic_vector(0 downto 0) := (others => 'X'); -- generic_tristate_controller_0_tcm_chipselect_n_out_out tcs_generic_tristate_controller_0_tcm_write_n_out : in std_logic_vector(0 downto 0) := (others => 'X'); -- generic_tristate_controller_0_tcm_write_n_out_out tcs_generic_tristate_controller_0_tcm_byteenable_out : in std_logic_vector(0 downto 0) := (others => 'X'); -- generic_tristate_controller_0_tcm_byteenable_out_out tcs_generic_tristate_controller_0_tcm_begintransfer_out : in std_logic_vector(0 downto 0) := (others => 'X'); -- generic_tristate_controller_0_tcm_begintransfer_out_out tcs_generic_tristate_controller_0_tcm_address_out : in std_logic_vector(21 downto 0) := (others => 'X'); -- generic_tristate_controller_0_tcm_address_out_out generic_tristate_controller_0_tcm_read_n_out : out std_logic_vector(0 downto 0); -- generic_tristate_controller_0_tcm_read_n_out generic_tristate_controller_0_tcm_data_out : inout std_logic_vector(7 downto 0) := (others => 'X'); -- generic_tristate_controller_0_tcm_data_out generic_tristate_controller_0_tcm_chipselect_n_out : out std_logic_vector(0 downto 0); -- generic_tristate_controller_0_tcm_chipselect_n_out generic_tristate_controller_0_tcm_write_n_out : out std_logic_vector(0 downto 0); -- generic_tristate_controller_0_tcm_write_n_out generic_tristate_controller_0_tcm_byteenable_out : out std_logic_vector(0 downto 0); -- generic_tristate_controller_0_tcm_byteenable_out generic_tristate_controller_0_tcm_begintransfer_out : out std_logic_vector(0 downto 0); -- generic_tristate_controller_0_tcm_begintransfer_out generic_tristate_controller_0_tcm_address_out : out std_logic_vector(21 downto 0) -- generic_tristate_controller_0_tcm_address_out ); end component niosII_system_tristate_conduit_bridge_0; component niosII_system_tristate_conduit_pin_sharer_0 is port ( clk_clk : in std_logic := 'X'; -- clk reset_reset : in std_logic := 'X'; -- reset request : out std_logic; -- request grant : in std_logic := 'X'; -- grant generic_tristate_controller_0_tcm_byteenable_out : out std_logic_vector(0 downto 0); -- generic_tristate_controller_0_tcm_byteenable_out_out generic_tristate_controller_0_tcm_address_out : out std_logic_vector(21 downto 0); -- generic_tristate_controller_0_tcm_address_out_out generic_tristate_controller_0_tcm_read_n_out : out std_logic_vector(0 downto 0); -- generic_tristate_controller_0_tcm_read_n_out_out generic_tristate_controller_0_tcm_write_n_out : out std_logic_vector(0 downto 0); -- generic_tristate_controller_0_tcm_write_n_out_out generic_tristate_controller_0_tcm_data_out : out std_logic_vector(7 downto 0); -- generic_tristate_controller_0_tcm_data_out_out generic_tristate_controller_0_tcm_data_in : in std_logic_vector(7 downto 0) := (others => 'X'); -- generic_tristate_controller_0_tcm_data_out_in generic_tristate_controller_0_tcm_data_outen : out std_logic; -- generic_tristate_controller_0_tcm_data_out_outen generic_tristate_controller_0_tcm_chipselect_n_out : out std_logic_vector(0 downto 0); -- generic_tristate_controller_0_tcm_chipselect_n_out_out generic_tristate_controller_0_tcm_begintransfer_out : out std_logic_vector(0 downto 0); -- generic_tristate_controller_0_tcm_begintransfer_out_out tcs0_request : in std_logic := 'X'; -- request tcs0_grant : out std_logic; -- grant tcs0_byteenable_out : in std_logic_vector(0 downto 0) := (others => 'X'); -- byteenable_out tcs0_address_out : in std_logic_vector(21 downto 0) := (others => 'X'); -- address_out tcs0_read_n_out : in std_logic_vector(0 downto 0) := (others => 'X'); -- read_n_out tcs0_write_n_out : in std_logic_vector(0 downto 0) := (others => 'X'); -- write_n_out tcs0_data_out : in std_logic_vector(7 downto 0) := (others => 'X'); -- data_out tcs0_data_in : out std_logic_vector(7 downto 0); -- data_in tcs0_data_outen : in std_logic := 'X'; -- data_outen tcs0_chipselect_n_out : in std_logic_vector(0 downto 0) := (others => 'X'); -- chipselect_n_out tcs0_begintransfer_out : in std_logic_vector(0 downto 0) := (others => 'X') -- begintransfer_out ); end component niosII_system_tristate_conduit_pin_sharer_0; component altera_merlin_master_agent is generic ( PKT_PROTECTION_H : integer := 80; PKT_PROTECTION_L : integer := 80; PKT_BEGIN_BURST : integer := 81; PKT_BURSTWRAP_H : integer := 79; PKT_BURSTWRAP_L : integer := 77; PKT_BURST_SIZE_H : integer := 86; PKT_BURST_SIZE_L : integer := 84; PKT_BURST_TYPE_H : integer := 94; PKT_BURST_TYPE_L : integer := 93; PKT_BYTE_CNT_H : integer := 76; PKT_BYTE_CNT_L : integer := 74; PKT_ADDR_H : integer := 73; PKT_ADDR_L : integer := 42; PKT_TRANS_COMPRESSED_READ : integer := 41; PKT_TRANS_POSTED : integer := 40; PKT_TRANS_WRITE : integer := 39; PKT_TRANS_READ : integer := 38; PKT_TRANS_LOCK : integer := 82; PKT_TRANS_EXCLUSIVE : integer := 83; PKT_DATA_H : integer := 37; PKT_DATA_L : integer := 6; PKT_BYTEEN_H : integer := 5; PKT_BYTEEN_L : integer := 2; PKT_SRC_ID_H : integer := 1; PKT_SRC_ID_L : integer := 1; PKT_DEST_ID_H : integer := 0; PKT_DEST_ID_L : integer := 0; PKT_THREAD_ID_H : integer := 88; PKT_THREAD_ID_L : integer := 87; PKT_CACHE_H : integer := 92; PKT_CACHE_L : integer := 89; PKT_DATA_SIDEBAND_H : integer := 105; PKT_DATA_SIDEBAND_L : integer := 98; PKT_QOS_H : integer := 109; PKT_QOS_L : integer := 106; PKT_ADDR_SIDEBAND_H : integer := 97; PKT_ADDR_SIDEBAND_L : integer := 93; PKT_RESPONSE_STATUS_H : integer := 111; PKT_RESPONSE_STATUS_L : integer := 110; ST_DATA_W : integer := 112; ST_CHANNEL_W : integer := 1; AV_BURSTCOUNT_W : integer := 3; SUPPRESS_0_BYTEEN_RSP : integer := 1; ID : integer := 1; BURSTWRAP_VALUE : integer := 4; CACHE_VALUE : integer := 0; SECURE_ACCESS_BIT : integer := 1; USE_READRESPONSE : integer := 0; USE_WRITERESPONSE : integer := 0 ); port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset av_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address av_write : in std_logic := 'X'; -- write av_read : in std_logic := 'X'; -- read av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata av_readdata : out std_logic_vector(31 downto 0); -- readdata av_waitrequest : out std_logic; -- waitrequest av_readdatavalid : out std_logic; -- readdatavalid av_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable av_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount av_debugaccess : in std_logic := 'X'; -- debugaccess av_lock : in std_logic := 'X'; -- lock cp_valid : out std_logic; -- valid cp_data : out std_logic_vector(99 downto 0); -- data cp_startofpacket : out std_logic; -- startofpacket cp_endofpacket : out std_logic; -- endofpacket cp_ready : in std_logic := 'X'; -- ready rp_valid : in std_logic := 'X'; -- valid rp_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data rp_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel rp_startofpacket : in std_logic := 'X'; -- startofpacket rp_endofpacket : in std_logic := 'X'; -- endofpacket rp_ready : out std_logic; -- ready av_response : out std_logic_vector(1 downto 0); -- response av_writeresponserequest : in std_logic := 'X'; -- writeresponserequest av_writeresponsevalid : out std_logic -- writeresponsevalid ); end component altera_merlin_master_agent; component niosII_system_addr_router is port ( sink_ready : out std_logic; -- ready sink_valid : in std_logic := 'X'; -- valid sink_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data sink_startofpacket : in std_logic := 'X'; -- startofpacket sink_endofpacket : in std_logic := 'X'; -- endofpacket clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset src_ready : in std_logic := 'X'; -- ready src_valid : out std_logic; -- valid src_data : out std_logic_vector(99 downto 0); -- data src_channel : out std_logic_vector(12 downto 0); -- channel src_startofpacket : out std_logic; -- startofpacket src_endofpacket : out std_logic -- endofpacket ); end component niosII_system_addr_router; component niosII_system_addr_router_001 is port ( sink_ready : out std_logic; -- ready sink_valid : in std_logic := 'X'; -- valid sink_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data sink_startofpacket : in std_logic := 'X'; -- startofpacket sink_endofpacket : in std_logic := 'X'; -- endofpacket clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset src_ready : in std_logic := 'X'; -- ready src_valid : out std_logic; -- valid src_data : out std_logic_vector(99 downto 0); -- data src_channel : out std_logic_vector(12 downto 0); -- channel src_startofpacket : out std_logic; -- startofpacket src_endofpacket : out std_logic -- endofpacket ); end component niosII_system_addr_router_001; component niosII_system_id_router is port ( sink_ready : out std_logic; -- ready sink_valid : in std_logic := 'X'; -- valid sink_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data sink_startofpacket : in std_logic := 'X'; -- startofpacket sink_endofpacket : in std_logic := 'X'; -- endofpacket clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset src_ready : in std_logic := 'X'; -- ready src_valid : out std_logic; -- valid src_data : out std_logic_vector(99 downto 0); -- data src_channel : out std_logic_vector(12 downto 0); -- channel src_startofpacket : out std_logic; -- startofpacket src_endofpacket : out std_logic -- endofpacket ); end component niosII_system_id_router; component niosII_system_id_router_001 is port ( sink_ready : out std_logic; -- ready sink_valid : in std_logic := 'X'; -- valid sink_data : in std_logic_vector(81 downto 0) := (others => 'X'); -- data sink_startofpacket : in std_logic := 'X'; -- startofpacket sink_endofpacket : in std_logic := 'X'; -- endofpacket clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset src_ready : in std_logic := 'X'; -- ready src_valid : out std_logic; -- valid src_data : out std_logic_vector(81 downto 0); -- data src_channel : out std_logic_vector(12 downto 0); -- channel src_startofpacket : out std_logic; -- startofpacket src_endofpacket : out std_logic -- endofpacket ); end component niosII_system_id_router_001; component niosII_system_id_router_004 is port ( sink_ready : out std_logic; -- ready sink_valid : in std_logic := 'X'; -- valid sink_data : in std_logic_vector(72 downto 0) := (others => 'X'); -- data sink_startofpacket : in std_logic := 'X'; -- startofpacket sink_endofpacket : in std_logic := 'X'; -- endofpacket clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset src_ready : in std_logic := 'X'; -- ready src_valid : out std_logic; -- valid src_data : out std_logic_vector(72 downto 0); -- data src_channel : out std_logic_vector(12 downto 0); -- channel src_startofpacket : out std_logic; -- startofpacket src_endofpacket : out std_logic -- endofpacket ); end component niosII_system_id_router_004; component niosII_system_id_router_005 is port ( sink_ready : out std_logic; -- ready sink_valid : in std_logic := 'X'; -- valid sink_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data sink_startofpacket : in std_logic := 'X'; -- startofpacket sink_endofpacket : in std_logic := 'X'; -- endofpacket clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset src_ready : in std_logic := 'X'; -- ready src_valid : out std_logic; -- valid src_data : out std_logic_vector(99 downto 0); -- data src_channel : out std_logic_vector(12 downto 0); -- channel src_startofpacket : out std_logic; -- startofpacket src_endofpacket : out std_logic -- endofpacket ); end component niosII_system_id_router_005; component niosII_system_cmd_xbar_demux is port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset sink_ready : out std_logic; -- ready sink_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel sink_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data sink_startofpacket : in std_logic := 'X'; -- startofpacket sink_endofpacket : in std_logic := 'X'; -- endofpacket sink_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- valid src0_ready : in std_logic := 'X'; -- ready src0_valid : out std_logic; -- valid src0_data : out std_logic_vector(99 downto 0); -- data src0_channel : out std_logic_vector(12 downto 0); -- channel src0_startofpacket : out std_logic; -- startofpacket src0_endofpacket : out std_logic; -- endofpacket src1_ready : in std_logic := 'X'; -- ready src1_valid : out std_logic; -- valid src1_data : out std_logic_vector(99 downto 0); -- data src1_channel : out std_logic_vector(12 downto 0); -- channel src1_startofpacket : out std_logic; -- startofpacket src1_endofpacket : out std_logic; -- endofpacket src2_ready : in std_logic := 'X'; -- ready src2_valid : out std_logic; -- valid src2_data : out std_logic_vector(99 downto 0); -- data src2_channel : out std_logic_vector(12 downto 0); -- channel src2_startofpacket : out std_logic; -- startofpacket src2_endofpacket : out std_logic; -- endofpacket src3_ready : in std_logic := 'X'; -- ready src3_valid : out std_logic; -- valid src3_data : out std_logic_vector(99 downto 0); -- data src3_channel : out std_logic_vector(12 downto 0); -- channel src3_startofpacket : out std_logic; -- startofpacket src3_endofpacket : out std_logic; -- endofpacket src4_ready : in std_logic := 'X'; -- ready src4_valid : out std_logic; -- valid src4_data : out std_logic_vector(99 downto 0); -- data src4_channel : out std_logic_vector(12 downto 0); -- channel src4_startofpacket : out std_logic; -- startofpacket src4_endofpacket : out std_logic -- endofpacket ); end component niosII_system_cmd_xbar_demux; component niosII_system_cmd_xbar_demux_001 is port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset sink_ready : out std_logic; -- ready sink_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel sink_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data sink_startofpacket : in std_logic := 'X'; -- startofpacket sink_endofpacket : in std_logic := 'X'; -- endofpacket sink_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- valid src0_ready : in std_logic := 'X'; -- ready src0_valid : out std_logic; -- valid src0_data : out std_logic_vector(99 downto 0); -- data src0_channel : out std_logic_vector(12 downto 0); -- channel src0_startofpacket : out std_logic; -- startofpacket src0_endofpacket : out std_logic; -- endofpacket src1_ready : in std_logic := 'X'; -- ready src1_valid : out std_logic; -- valid src1_data : out std_logic_vector(99 downto 0); -- data src1_channel : out std_logic_vector(12 downto 0); -- channel src1_startofpacket : out std_logic; -- startofpacket src1_endofpacket : out std_logic; -- endofpacket src2_ready : in std_logic := 'X'; -- ready src2_valid : out std_logic; -- valid src2_data : out std_logic_vector(99 downto 0); -- data src2_channel : out std_logic_vector(12 downto 0); -- channel src2_startofpacket : out std_logic; -- startofpacket src2_endofpacket : out std_logic; -- endofpacket src3_ready : in std_logic := 'X'; -- ready src3_valid : out std_logic; -- valid src3_data : out std_logic_vector(99 downto 0); -- data src3_channel : out std_logic_vector(12 downto 0); -- channel src3_startofpacket : out std_logic; -- startofpacket src3_endofpacket : out std_logic; -- endofpacket src4_ready : in std_logic := 'X'; -- ready src4_valid : out std_logic; -- valid src4_data : out std_logic_vector(99 downto 0); -- data src4_channel : out std_logic_vector(12 downto 0); -- channel src4_startofpacket : out std_logic; -- startofpacket src4_endofpacket : out std_logic; -- endofpacket src5_ready : in std_logic := 'X'; -- ready src5_valid : out std_logic; -- valid src5_data : out std_logic_vector(99 downto 0); -- data src5_channel : out std_logic_vector(12 downto 0); -- channel src5_startofpacket : out std_logic; -- startofpacket src5_endofpacket : out std_logic; -- endofpacket src6_ready : in std_logic := 'X'; -- ready src6_valid : out std_logic; -- valid src6_data : out std_logic_vector(99 downto 0); -- data src6_channel : out std_logic_vector(12 downto 0); -- channel src6_startofpacket : out std_logic; -- startofpacket src6_endofpacket : out std_logic; -- endofpacket src7_ready : in std_logic := 'X'; -- ready src7_valid : out std_logic; -- valid src7_data : out std_logic_vector(99 downto 0); -- data src7_channel : out std_logic_vector(12 downto 0); -- channel src7_startofpacket : out std_logic; -- startofpacket src7_endofpacket : out std_logic; -- endofpacket src8_ready : in std_logic := 'X'; -- ready src8_valid : out std_logic; -- valid src8_data : out std_logic_vector(99 downto 0); -- data src8_channel : out std_logic_vector(12 downto 0); -- channel src8_startofpacket : out std_logic; -- startofpacket src8_endofpacket : out std_logic; -- endofpacket src9_ready : in std_logic := 'X'; -- ready src9_valid : out std_logic; -- valid src9_data : out std_logic_vector(99 downto 0); -- data src9_channel : out std_logic_vector(12 downto 0); -- channel src9_startofpacket : out std_logic; -- startofpacket src9_endofpacket : out std_logic; -- endofpacket src10_ready : in std_logic := 'X'; -- ready src10_valid : out std_logic; -- valid src10_data : out std_logic_vector(99 downto 0); -- data src10_channel : out std_logic_vector(12 downto 0); -- channel src10_startofpacket : out std_logic; -- startofpacket src10_endofpacket : out std_logic; -- endofpacket src11_ready : in std_logic := 'X'; -- ready src11_valid : out std_logic; -- valid src11_data : out std_logic_vector(99 downto 0); -- data src11_channel : out std_logic_vector(12 downto 0); -- channel src11_startofpacket : out std_logic; -- startofpacket src11_endofpacket : out std_logic; -- endofpacket src12_ready : in std_logic := 'X'; -- ready src12_valid : out std_logic; -- valid src12_data : out std_logic_vector(99 downto 0); -- data src12_channel : out std_logic_vector(12 downto 0); -- channel src12_startofpacket : out std_logic; -- startofpacket src12_endofpacket : out std_logic -- endofpacket ); end component niosII_system_cmd_xbar_demux_001; component niosII_system_cmd_xbar_mux is port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset src_ready : in std_logic := 'X'; -- ready src_valid : out std_logic; -- valid src_data : out std_logic_vector(99 downto 0); -- data src_channel : out std_logic_vector(12 downto 0); -- channel src_startofpacket : out std_logic; -- startofpacket src_endofpacket : out std_logic; -- endofpacket sink0_ready : out std_logic; -- ready sink0_valid : in std_logic := 'X'; -- valid sink0_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel sink0_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data sink0_startofpacket : in std_logic := 'X'; -- startofpacket sink0_endofpacket : in std_logic := 'X'; -- endofpacket sink1_ready : out std_logic; -- ready sink1_valid : in std_logic := 'X'; -- valid sink1_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel sink1_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data sink1_startofpacket : in std_logic := 'X'; -- startofpacket sink1_endofpacket : in std_logic := 'X' -- endofpacket ); end component niosII_system_cmd_xbar_mux; component niosII_system_rsp_xbar_demux is port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset sink_ready : out std_logic; -- ready sink_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel sink_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data sink_startofpacket : in std_logic := 'X'; -- startofpacket sink_endofpacket : in std_logic := 'X'; -- endofpacket sink_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- valid src0_ready : in std_logic := 'X'; -- ready src0_valid : out std_logic; -- valid src0_data : out std_logic_vector(99 downto 0); -- data src0_channel : out std_logic_vector(12 downto 0); -- channel src0_startofpacket : out std_logic; -- startofpacket src0_endofpacket : out std_logic; -- endofpacket src1_ready : in std_logic := 'X'; -- ready src1_valid : out std_logic; -- valid src1_data : out std_logic_vector(99 downto 0); -- data src1_channel : out std_logic_vector(12 downto 0); -- channel src1_startofpacket : out std_logic; -- startofpacket src1_endofpacket : out std_logic -- endofpacket ); end component niosII_system_rsp_xbar_demux; component niosII_system_rsp_xbar_demux_005 is port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset sink_ready : out std_logic; -- ready sink_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel sink_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data sink_startofpacket : in std_logic := 'X'; -- startofpacket sink_endofpacket : in std_logic := 'X'; -- endofpacket sink_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- valid src0_ready : in std_logic := 'X'; -- ready src0_valid : out std_logic; -- valid src0_data : out std_logic_vector(99 downto 0); -- data src0_channel : out std_logic_vector(12 downto 0); -- channel src0_startofpacket : out std_logic; -- startofpacket src0_endofpacket : out std_logic -- endofpacket ); end component niosII_system_rsp_xbar_demux_005; component niosII_system_rsp_xbar_mux is port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset src_ready : in std_logic := 'X'; -- ready src_valid : out std_logic; -- valid src_data : out std_logic_vector(99 downto 0); -- data src_channel : out std_logic_vector(12 downto 0); -- channel src_startofpacket : out std_logic; -- startofpacket src_endofpacket : out std_logic; -- endofpacket sink0_ready : out std_logic; -- ready sink0_valid : in std_logic := 'X'; -- valid sink0_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel sink0_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data sink0_startofpacket : in std_logic := 'X'; -- startofpacket sink0_endofpacket : in std_logic := 'X'; -- endofpacket sink1_ready : out std_logic; -- ready sink1_valid : in std_logic := 'X'; -- valid sink1_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel sink1_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data sink1_startofpacket : in std_logic := 'X'; -- startofpacket sink1_endofpacket : in std_logic := 'X'; -- endofpacket sink2_ready : out std_logic; -- ready sink2_valid : in std_logic := 'X'; -- valid sink2_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel sink2_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data sink2_startofpacket : in std_logic := 'X'; -- startofpacket sink2_endofpacket : in std_logic := 'X'; -- endofpacket sink3_ready : out std_logic; -- ready sink3_valid : in std_logic := 'X'; -- valid sink3_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel sink3_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data sink3_startofpacket : in std_logic := 'X'; -- startofpacket sink3_endofpacket : in std_logic := 'X'; -- endofpacket sink4_ready : out std_logic; -- ready sink4_valid : in std_logic := 'X'; -- valid sink4_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel sink4_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data sink4_startofpacket : in std_logic := 'X'; -- startofpacket sink4_endofpacket : in std_logic := 'X' -- endofpacket ); end component niosII_system_rsp_xbar_mux; component niosII_system_rsp_xbar_mux_001 is port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset src_ready : in std_logic := 'X'; -- ready src_valid : out std_logic; -- valid src_data : out std_logic_vector(99 downto 0); -- data src_channel : out std_logic_vector(12 downto 0); -- channel src_startofpacket : out std_logic; -- startofpacket src_endofpacket : out std_logic; -- endofpacket sink0_ready : out std_logic; -- ready sink0_valid : in std_logic := 'X'; -- valid sink0_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel sink0_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data sink0_startofpacket : in std_logic := 'X'; -- startofpacket sink0_endofpacket : in std_logic := 'X'; -- endofpacket sink1_ready : out std_logic; -- ready sink1_valid : in std_logic := 'X'; -- valid sink1_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel sink1_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data sink1_startofpacket : in std_logic := 'X'; -- startofpacket sink1_endofpacket : in std_logic := 'X'; -- endofpacket sink2_ready : out std_logic; -- ready sink2_valid : in std_logic := 'X'; -- valid sink2_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel sink2_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data sink2_startofpacket : in std_logic := 'X'; -- startofpacket sink2_endofpacket : in std_logic := 'X'; -- endofpacket sink3_ready : out std_logic; -- ready sink3_valid : in std_logic := 'X'; -- valid sink3_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel sink3_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data sink3_startofpacket : in std_logic := 'X'; -- startofpacket sink3_endofpacket : in std_logic := 'X'; -- endofpacket sink4_ready : out std_logic; -- ready sink4_valid : in std_logic := 'X'; -- valid sink4_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel sink4_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data sink4_startofpacket : in std_logic := 'X'; -- startofpacket sink4_endofpacket : in std_logic := 'X'; -- endofpacket sink5_ready : out std_logic; -- ready sink5_valid : in std_logic := 'X'; -- valid sink5_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel sink5_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data sink5_startofpacket : in std_logic := 'X'; -- startofpacket sink5_endofpacket : in std_logic := 'X'; -- endofpacket sink6_ready : out std_logic; -- ready sink6_valid : in std_logic := 'X'; -- valid sink6_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel sink6_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data sink6_startofpacket : in std_logic := 'X'; -- startofpacket sink6_endofpacket : in std_logic := 'X'; -- endofpacket sink7_ready : out std_logic; -- ready sink7_valid : in std_logic := 'X'; -- valid sink7_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel sink7_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data sink7_startofpacket : in std_logic := 'X'; -- startofpacket sink7_endofpacket : in std_logic := 'X'; -- endofpacket sink8_ready : out std_logic; -- ready sink8_valid : in std_logic := 'X'; -- valid sink8_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel sink8_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data sink8_startofpacket : in std_logic := 'X'; -- startofpacket sink8_endofpacket : in std_logic := 'X'; -- endofpacket sink9_ready : out std_logic; -- ready sink9_valid : in std_logic := 'X'; -- valid sink9_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel sink9_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data sink9_startofpacket : in std_logic := 'X'; -- startofpacket sink9_endofpacket : in std_logic := 'X'; -- endofpacket sink10_ready : out std_logic; -- ready sink10_valid : in std_logic := 'X'; -- valid sink10_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel sink10_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data sink10_startofpacket : in std_logic := 'X'; -- startofpacket sink10_endofpacket : in std_logic := 'X'; -- endofpacket sink11_ready : out std_logic; -- ready sink11_valid : in std_logic := 'X'; -- valid sink11_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel sink11_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data sink11_startofpacket : in std_logic := 'X'; -- startofpacket sink11_endofpacket : in std_logic := 'X'; -- endofpacket sink12_ready : out std_logic; -- ready sink12_valid : in std_logic := 'X'; -- valid sink12_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel sink12_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data sink12_startofpacket : in std_logic := 'X'; -- startofpacket sink12_endofpacket : in std_logic := 'X' -- endofpacket ); end component niosII_system_rsp_xbar_mux_001; component altera_avalon_st_handshake_clock_crosser is generic ( DATA_WIDTH : integer := 8; BITS_PER_SYMBOL : integer := 8; USE_PACKETS : integer := 0; USE_CHANNEL : integer := 0; CHANNEL_WIDTH : integer := 1; USE_ERROR : integer := 0; ERROR_WIDTH : integer := 1; VALID_SYNC_DEPTH : integer := 2; READY_SYNC_DEPTH : integer := 2; USE_OUTPUT_PIPELINE : integer := 1 ); port ( in_clk : in std_logic := 'X'; -- clk in_reset : in std_logic := 'X'; -- reset out_clk : in std_logic := 'X'; -- clk out_reset : in std_logic := 'X'; -- reset in_ready : out std_logic; -- ready in_valid : in std_logic := 'X'; -- valid in_startofpacket : in std_logic := 'X'; -- startofpacket in_endofpacket : in std_logic := 'X'; -- endofpacket in_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel in_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data out_ready : in std_logic := 'X'; -- ready out_valid : out std_logic; -- valid out_startofpacket : out std_logic; -- startofpacket out_endofpacket : out std_logic; -- endofpacket out_channel : out std_logic_vector(12 downto 0); -- channel out_data : out std_logic_vector(99 downto 0); -- data in_empty : in std_logic := 'X'; -- empty in_error : in std_logic := 'X'; -- error out_empty : out std_logic; -- empty out_error : out std_logic -- error ); end component altera_avalon_st_handshake_clock_crosser; component niosII_system_irq_mapper is port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset receiver0_irq : in std_logic := 'X'; -- irq receiver1_irq : in std_logic := 'X'; -- irq receiver2_irq : in std_logic := 'X'; -- irq receiver3_irq : in std_logic := 'X'; -- irq sender_irq : out std_logic_vector(31 downto 0) -- irq ); end component niosII_system_irq_mapper; component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo is generic ( SYMBOLS_PER_BEAT : integer := 1; BITS_PER_SYMBOL : integer := 8; FIFO_DEPTH : integer := 16; CHANNEL_WIDTH : integer := 0; ERROR_WIDTH : integer := 0; USE_PACKETS : integer := 0; USE_FILL_LEVEL : integer := 0; EMPTY_LATENCY : integer := 3; USE_MEMORY_BLOCKS : integer := 1; USE_STORE_FORWARD : integer := 0; USE_ALMOST_FULL_IF : integer := 0; USE_ALMOST_EMPTY_IF : integer := 0 ); port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset in_data : in std_logic_vector(100 downto 0) := (others => 'X'); -- data in_valid : in std_logic := 'X'; -- valid in_ready : out std_logic; -- ready in_startofpacket : in std_logic := 'X'; -- startofpacket in_endofpacket : in std_logic := 'X'; -- endofpacket out_data : out std_logic_vector(100 downto 0); -- data out_valid : out std_logic; -- valid out_ready : in std_logic := 'X'; -- ready out_startofpacket : out std_logic; -- startofpacket out_endofpacket : out std_logic; -- endofpacket csr_address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address csr_read : in std_logic := 'X'; -- read csr_write : in std_logic := 'X'; -- write csr_readdata : out std_logic_vector(31 downto 0); -- readdata csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata almost_full_data : out std_logic; -- data almost_empty_data : out std_logic; -- data in_empty : in std_logic := 'X'; -- empty out_empty : out std_logic; -- empty in_error : in std_logic := 'X'; -- error out_error : out std_logic; -- error in_channel : in std_logic := 'X'; -- channel out_channel : out std_logic -- channel ); end component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo; component niosii_system_sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo is generic ( SYMBOLS_PER_BEAT : integer := 1; BITS_PER_SYMBOL : integer := 8; FIFO_DEPTH : integer := 16; CHANNEL_WIDTH : integer := 0; ERROR_WIDTH : integer := 0; USE_PACKETS : integer := 0; USE_FILL_LEVEL : integer := 0; EMPTY_LATENCY : integer := 3; USE_MEMORY_BLOCKS : integer := 1; USE_STORE_FORWARD : integer := 0; USE_ALMOST_FULL_IF : integer := 0; USE_ALMOST_EMPTY_IF : integer := 0 ); port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset in_data : in std_logic_vector(82 downto 0) := (others => 'X'); -- data in_valid : in std_logic := 'X'; -- valid in_ready : out std_logic; -- ready in_startofpacket : in std_logic := 'X'; -- startofpacket in_endofpacket : in std_logic := 'X'; -- endofpacket out_data : out std_logic_vector(82 downto 0); -- data out_valid : out std_logic; -- valid out_ready : in std_logic := 'X'; -- ready out_startofpacket : out std_logic; -- startofpacket out_endofpacket : out std_logic; -- endofpacket csr_address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address csr_read : in std_logic := 'X'; -- read csr_write : in std_logic := 'X'; -- write csr_readdata : out std_logic_vector(31 downto 0); -- readdata csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata almost_full_data : out std_logic; -- data almost_empty_data : out std_logic; -- data in_empty : in std_logic := 'X'; -- empty out_empty : out std_logic; -- empty in_error : in std_logic := 'X'; -- error out_error : out std_logic; -- error in_channel : in std_logic := 'X'; -- channel out_channel : out std_logic -- channel ); end component niosii_system_sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo; component niosii_system_sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo is generic ( SYMBOLS_PER_BEAT : integer := 1; BITS_PER_SYMBOL : integer := 8; FIFO_DEPTH : integer := 16; CHANNEL_WIDTH : integer := 0; ERROR_WIDTH : integer := 0; USE_PACKETS : integer := 0; USE_FILL_LEVEL : integer := 0; EMPTY_LATENCY : integer := 3; USE_MEMORY_BLOCKS : integer := 1; USE_STORE_FORWARD : integer := 0; USE_ALMOST_FULL_IF : integer := 0; USE_ALMOST_EMPTY_IF : integer := 0 ); port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset in_data : in std_logic_vector(17 downto 0) := (others => 'X'); -- data in_valid : in std_logic := 'X'; -- valid in_ready : out std_logic; -- ready out_data : out std_logic_vector(17 downto 0); -- data out_valid : out std_logic; -- valid out_ready : in std_logic := 'X'; -- ready csr_address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address csr_read : in std_logic := 'X'; -- read csr_write : in std_logic := 'X'; -- write csr_readdata : out std_logic_vector(31 downto 0); -- readdata csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata almost_full_data : out std_logic; -- data almost_empty_data : out std_logic; -- data in_startofpacket : in std_logic := 'X'; -- startofpacket in_endofpacket : in std_logic := 'X'; -- endofpacket out_startofpacket : out std_logic; -- startofpacket out_endofpacket : out std_logic; -- endofpacket in_empty : in std_logic := 'X'; -- empty out_empty : out std_logic; -- empty in_error : in std_logic := 'X'; -- error out_error : out std_logic; -- error in_channel : in std_logic := 'X'; -- channel out_channel : out std_logic -- channel ); end component niosii_system_sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo; component niosii_system_generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo is generic ( SYMBOLS_PER_BEAT : integer := 1; BITS_PER_SYMBOL : integer := 8; FIFO_DEPTH : integer := 16; CHANNEL_WIDTH : integer := 0; ERROR_WIDTH : integer := 0; USE_PACKETS : integer := 0; USE_FILL_LEVEL : integer := 0; EMPTY_LATENCY : integer := 3; USE_MEMORY_BLOCKS : integer := 1; USE_STORE_FORWARD : integer := 0; USE_ALMOST_FULL_IF : integer := 0; USE_ALMOST_EMPTY_IF : integer := 0 ); port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset in_data : in std_logic_vector(73 downto 0) := (others => 'X'); -- data in_valid : in std_logic := 'X'; -- valid in_ready : out std_logic; -- ready in_startofpacket : in std_logic := 'X'; -- startofpacket in_endofpacket : in std_logic := 'X'; -- endofpacket out_data : out std_logic_vector(73 downto 0); -- data out_valid : out std_logic; -- valid out_ready : in std_logic := 'X'; -- ready out_startofpacket : out std_logic; -- startofpacket out_endofpacket : out std_logic; -- endofpacket csr_address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address csr_read : in std_logic := 'X'; -- read csr_write : in std_logic := 'X'; -- write csr_readdata : out std_logic_vector(31 downto 0); -- readdata csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata almost_full_data : out std_logic; -- data almost_empty_data : out std_logic; -- data in_empty : in std_logic := 'X'; -- empty out_empty : out std_logic; -- empty in_error : in std_logic := 'X'; -- error out_error : out std_logic; -- error in_channel : in std_logic := 'X'; -- channel out_channel : out std_logic -- channel ); end component niosii_system_generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo; component niosii_system_generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo is generic ( SYMBOLS_PER_BEAT : integer := 1; BITS_PER_SYMBOL : integer := 8; FIFO_DEPTH : integer := 16; CHANNEL_WIDTH : integer := 0; ERROR_WIDTH : integer := 0; USE_PACKETS : integer := 0; USE_FILL_LEVEL : integer := 0; EMPTY_LATENCY : integer := 3; USE_MEMORY_BLOCKS : integer := 1; USE_STORE_FORWARD : integer := 0; USE_ALMOST_FULL_IF : integer := 0; USE_ALMOST_EMPTY_IF : integer := 0 ); port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset in_data : in std_logic_vector(9 downto 0) := (others => 'X'); -- data in_valid : in std_logic := 'X'; -- valid in_ready : out std_logic; -- ready out_data : out std_logic_vector(9 downto 0); -- data out_valid : out std_logic; -- valid out_ready : in std_logic := 'X'; -- ready csr_address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address csr_read : in std_logic := 'X'; -- read csr_write : in std_logic := 'X'; -- write csr_readdata : out std_logic_vector(31 downto 0); -- readdata csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata almost_full_data : out std_logic; -- data almost_empty_data : out std_logic; -- data in_startofpacket : in std_logic := 'X'; -- startofpacket in_endofpacket : in std_logic := 'X'; -- endofpacket out_startofpacket : out std_logic; -- startofpacket out_endofpacket : out std_logic; -- endofpacket in_empty : in std_logic := 'X'; -- empty out_empty : out std_logic; -- empty in_error : in std_logic := 'X'; -- error out_error : out std_logic; -- error in_channel : in std_logic := 'X'; -- channel out_channel : out std_logic -- channel ); end component niosii_system_generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo; component niosii_system_altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo is generic ( SYMBOLS_PER_BEAT : integer := 1; BITS_PER_SYMBOL : integer := 8; FIFO_DEPTH : integer := 16; CHANNEL_WIDTH : integer := 0; ERROR_WIDTH : integer := 0; USE_PACKETS : integer := 0; USE_FILL_LEVEL : integer := 0; EMPTY_LATENCY : integer := 3; USE_MEMORY_BLOCKS : integer := 1; USE_STORE_FORWARD : integer := 0; USE_ALMOST_FULL_IF : integer := 0; USE_ALMOST_EMPTY_IF : integer := 0 ); port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset in_data : in std_logic_vector(33 downto 0) := (others => 'X'); -- data in_valid : in std_logic := 'X'; -- valid in_ready : out std_logic; -- ready out_data : out std_logic_vector(33 downto 0); -- data out_valid : out std_logic; -- valid out_ready : in std_logic := 'X'; -- ready csr_address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address csr_read : in std_logic := 'X'; -- read csr_write : in std_logic := 'X'; -- write csr_readdata : out std_logic_vector(31 downto 0); -- readdata csr_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata almost_full_data : out std_logic; -- data almost_empty_data : out std_logic; -- data in_startofpacket : in std_logic := 'X'; -- startofpacket in_endofpacket : in std_logic := 'X'; -- endofpacket out_startofpacket : out std_logic; -- startofpacket out_endofpacket : out std_logic; -- endofpacket in_empty : in std_logic := 'X'; -- empty out_empty : out std_logic; -- empty in_error : in std_logic := 'X'; -- error out_error : out std_logic; -- error in_channel : in std_logic := 'X'; -- channel out_channel : out std_logic -- channel ); end component niosii_system_altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo; component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent is generic ( PKT_DATA_H : integer := 31; PKT_DATA_L : integer := 0; PKT_BEGIN_BURST : integer := 81; PKT_SYMBOL_W : integer := 8; PKT_BYTEEN_H : integer := 71; PKT_BYTEEN_L : integer := 68; PKT_ADDR_H : integer := 63; PKT_ADDR_L : integer := 32; PKT_TRANS_COMPRESSED_READ : integer := 67; PKT_TRANS_POSTED : integer := 66; PKT_TRANS_WRITE : integer := 65; PKT_TRANS_READ : integer := 64; PKT_TRANS_LOCK : integer := 87; PKT_SRC_ID_H : integer := 74; PKT_SRC_ID_L : integer := 72; PKT_DEST_ID_H : integer := 77; PKT_DEST_ID_L : integer := 75; PKT_BURSTWRAP_H : integer := 85; PKT_BURSTWRAP_L : integer := 82; PKT_BYTE_CNT_H : integer := 81; PKT_BYTE_CNT_L : integer := 78; PKT_PROTECTION_H : integer := 86; PKT_PROTECTION_L : integer := 86; PKT_RESPONSE_STATUS_H : integer := 89; PKT_RESPONSE_STATUS_L : integer := 88; PKT_BURST_SIZE_H : integer := 92; PKT_BURST_SIZE_L : integer := 90; ST_CHANNEL_W : integer := 8; ST_DATA_W : integer := 93; AVS_BURSTCOUNT_W : integer := 4; SUPPRESS_0_BYTEEN_CMD : integer := 1; PREVENT_FIFO_OVERFLOW : integer := 0; USE_READRESPONSE : integer := 0; USE_WRITERESPONSE : integer := 0 ); port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset m0_address : out std_logic_vector(24 downto 0); -- address m0_burstcount : out std_logic_vector(2 downto 0); -- burstcount m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable m0_debugaccess : out std_logic; -- debugaccess m0_lock : out std_logic; -- lock m0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata m0_readdatavalid : in std_logic := 'X'; -- readdatavalid m0_read : out std_logic; -- read m0_waitrequest : in std_logic := 'X'; -- waitrequest m0_writedata : out std_logic_vector(31 downto 0); -- writedata m0_write : out std_logic; -- write rp_endofpacket : out std_logic; -- endofpacket rp_ready : in std_logic := 'X'; -- ready rp_valid : out std_logic; -- valid rp_data : out std_logic_vector(99 downto 0); -- data rp_startofpacket : out std_logic; -- startofpacket cp_ready : out std_logic; -- ready cp_valid : in std_logic := 'X'; -- valid cp_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data cp_startofpacket : in std_logic := 'X'; -- startofpacket cp_endofpacket : in std_logic := 'X'; -- endofpacket cp_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel rf_sink_ready : out std_logic; -- ready rf_sink_valid : in std_logic := 'X'; -- valid rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket rf_sink_data : in std_logic_vector(100 downto 0) := (others => 'X'); -- data rf_source_ready : in std_logic := 'X'; -- ready rf_source_valid : out std_logic; -- valid rf_source_startofpacket : out std_logic; -- startofpacket rf_source_endofpacket : out std_logic; -- endofpacket rf_source_data : out std_logic_vector(100 downto 0); -- data rdata_fifo_sink_ready : out std_logic; -- ready rdata_fifo_sink_valid : in std_logic := 'X'; -- valid rdata_fifo_sink_data : in std_logic_vector(33 downto 0) := (others => 'X'); -- data rdata_fifo_src_ready : in std_logic := 'X'; -- ready rdata_fifo_src_valid : out std_logic; -- valid rdata_fifo_src_data : out std_logic_vector(33 downto 0); -- data m0_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response m0_writeresponserequest : out std_logic; -- writeresponserequest m0_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid ); end component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent; component niosii_system_sdram_0_s1_translator_avalon_universal_slave_0_agent is generic ( PKT_DATA_H : integer := 31; PKT_DATA_L : integer := 0; PKT_BEGIN_BURST : integer := 81; PKT_SYMBOL_W : integer := 8; PKT_BYTEEN_H : integer := 71; PKT_BYTEEN_L : integer := 68; PKT_ADDR_H : integer := 63; PKT_ADDR_L : integer := 32; PKT_TRANS_COMPRESSED_READ : integer := 67; PKT_TRANS_POSTED : integer := 66; PKT_TRANS_WRITE : integer := 65; PKT_TRANS_READ : integer := 64; PKT_TRANS_LOCK : integer := 87; PKT_SRC_ID_H : integer := 74; PKT_SRC_ID_L : integer := 72; PKT_DEST_ID_H : integer := 77; PKT_DEST_ID_L : integer := 75; PKT_BURSTWRAP_H : integer := 85; PKT_BURSTWRAP_L : integer := 82; PKT_BYTE_CNT_H : integer := 81; PKT_BYTE_CNT_L : integer := 78; PKT_PROTECTION_H : integer := 86; PKT_PROTECTION_L : integer := 86; PKT_RESPONSE_STATUS_H : integer := 89; PKT_RESPONSE_STATUS_L : integer := 88; PKT_BURST_SIZE_H : integer := 92; PKT_BURST_SIZE_L : integer := 90; ST_CHANNEL_W : integer := 8; ST_DATA_W : integer := 93; AVS_BURSTCOUNT_W : integer := 4; SUPPRESS_0_BYTEEN_CMD : integer := 1; PREVENT_FIFO_OVERFLOW : integer := 0; USE_READRESPONSE : integer := 0; USE_WRITERESPONSE : integer := 0 ); port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset m0_address : out std_logic_vector(24 downto 0); -- address m0_burstcount : out std_logic_vector(1 downto 0); -- burstcount m0_byteenable : out std_logic_vector(1 downto 0); -- byteenable m0_debugaccess : out std_logic; -- debugaccess m0_lock : out std_logic; -- lock m0_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata m0_readdatavalid : in std_logic := 'X'; -- readdatavalid m0_read : out std_logic; -- read m0_waitrequest : in std_logic := 'X'; -- waitrequest m0_writedata : out std_logic_vector(15 downto 0); -- writedata m0_write : out std_logic; -- write rp_endofpacket : out std_logic; -- endofpacket rp_ready : in std_logic := 'X'; -- ready rp_valid : out std_logic; -- valid rp_data : out std_logic_vector(81 downto 0); -- data rp_startofpacket : out std_logic; -- startofpacket cp_ready : out std_logic; -- ready cp_valid : in std_logic := 'X'; -- valid cp_data : in std_logic_vector(81 downto 0) := (others => 'X'); -- data cp_startofpacket : in std_logic := 'X'; -- startofpacket cp_endofpacket : in std_logic := 'X'; -- endofpacket cp_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel rf_sink_ready : out std_logic; -- ready rf_sink_valid : in std_logic := 'X'; -- valid rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket rf_sink_data : in std_logic_vector(82 downto 0) := (others => 'X'); -- data rf_source_ready : in std_logic := 'X'; -- ready rf_source_valid : out std_logic; -- valid rf_source_startofpacket : out std_logic; -- startofpacket rf_source_endofpacket : out std_logic; -- endofpacket rf_source_data : out std_logic_vector(82 downto 0); -- data rdata_fifo_sink_ready : out std_logic; -- ready rdata_fifo_sink_valid : in std_logic := 'X'; -- valid rdata_fifo_sink_data : in std_logic_vector(17 downto 0) := (others => 'X'); -- data rdata_fifo_src_ready : in std_logic := 'X'; -- ready rdata_fifo_src_valid : out std_logic; -- valid rdata_fifo_src_data : out std_logic_vector(17 downto 0); -- data m0_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response m0_writeresponserequest : out std_logic; -- writeresponserequest m0_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid ); end component niosii_system_sdram_0_s1_translator_avalon_universal_slave_0_agent; component niosii_system_generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent is generic ( PKT_DATA_H : integer := 31; PKT_DATA_L : integer := 0; PKT_BEGIN_BURST : integer := 81; PKT_SYMBOL_W : integer := 8; PKT_BYTEEN_H : integer := 71; PKT_BYTEEN_L : integer := 68; PKT_ADDR_H : integer := 63; PKT_ADDR_L : integer := 32; PKT_TRANS_COMPRESSED_READ : integer := 67; PKT_TRANS_POSTED : integer := 66; PKT_TRANS_WRITE : integer := 65; PKT_TRANS_READ : integer := 64; PKT_TRANS_LOCK : integer := 87; PKT_SRC_ID_H : integer := 74; PKT_SRC_ID_L : integer := 72; PKT_DEST_ID_H : integer := 77; PKT_DEST_ID_L : integer := 75; PKT_BURSTWRAP_H : integer := 85; PKT_BURSTWRAP_L : integer := 82; PKT_BYTE_CNT_H : integer := 81; PKT_BYTE_CNT_L : integer := 78; PKT_PROTECTION_H : integer := 86; PKT_PROTECTION_L : integer := 86; PKT_RESPONSE_STATUS_H : integer := 89; PKT_RESPONSE_STATUS_L : integer := 88; PKT_BURST_SIZE_H : integer := 92; PKT_BURST_SIZE_L : integer := 90; ST_CHANNEL_W : integer := 8; ST_DATA_W : integer := 93; AVS_BURSTCOUNT_W : integer := 4; SUPPRESS_0_BYTEEN_CMD : integer := 1; PREVENT_FIFO_OVERFLOW : integer := 0; USE_READRESPONSE : integer := 0; USE_WRITERESPONSE : integer := 0 ); port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset m0_address : out std_logic_vector(24 downto 0); -- address m0_burstcount : out std_logic_vector(0 downto 0); -- burstcount m0_byteenable : out std_logic_vector(0 downto 0); -- byteenable m0_debugaccess : out std_logic; -- debugaccess m0_lock : out std_logic; -- lock m0_readdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- readdata m0_readdatavalid : in std_logic := 'X'; -- readdatavalid m0_read : out std_logic; -- read m0_waitrequest : in std_logic := 'X'; -- waitrequest m0_writedata : out std_logic_vector(7 downto 0); -- writedata m0_write : out std_logic; -- write rp_endofpacket : out std_logic; -- endofpacket rp_ready : in std_logic := 'X'; -- ready rp_valid : out std_logic; -- valid rp_data : out std_logic_vector(72 downto 0); -- data rp_startofpacket : out std_logic; -- startofpacket cp_ready : out std_logic; -- ready cp_valid : in std_logic := 'X'; -- valid cp_data : in std_logic_vector(72 downto 0) := (others => 'X'); -- data cp_startofpacket : in std_logic := 'X'; -- startofpacket cp_endofpacket : in std_logic := 'X'; -- endofpacket cp_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel rf_sink_ready : out std_logic; -- ready rf_sink_valid : in std_logic := 'X'; -- valid rf_sink_startofpacket : in std_logic := 'X'; -- startofpacket rf_sink_endofpacket : in std_logic := 'X'; -- endofpacket rf_sink_data : in std_logic_vector(73 downto 0) := (others => 'X'); -- data rf_source_ready : in std_logic := 'X'; -- ready rf_source_valid : out std_logic; -- valid rf_source_startofpacket : out std_logic; -- startofpacket rf_source_endofpacket : out std_logic; -- endofpacket rf_source_data : out std_logic_vector(73 downto 0); -- data rdata_fifo_sink_ready : out std_logic; -- ready rdata_fifo_sink_valid : in std_logic := 'X'; -- valid rdata_fifo_sink_data : in std_logic_vector(9 downto 0) := (others => 'X'); -- data rdata_fifo_src_ready : in std_logic := 'X'; -- ready rdata_fifo_src_valid : out std_logic; -- valid rdata_fifo_src_data : out std_logic_vector(9 downto 0); -- data m0_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response m0_writeresponserequest : out std_logic; -- writeresponserequest m0_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid ); end component niosii_system_generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent; component niosii_system_width_adapter is generic ( IN_PKT_ADDR_H : integer := 60; IN_PKT_ADDR_L : integer := 36; IN_PKT_DATA_H : integer := 31; IN_PKT_DATA_L : integer := 0; IN_PKT_BYTEEN_H : integer := 35; IN_PKT_BYTEEN_L : integer := 32; IN_PKT_BYTE_CNT_H : integer := 63; IN_PKT_BYTE_CNT_L : integer := 61; IN_PKT_TRANS_COMPRESSED_READ : integer := 65; IN_PKT_BURSTWRAP_H : integer := 67; IN_PKT_BURSTWRAP_L : integer := 66; IN_PKT_BURST_SIZE_H : integer := 70; IN_PKT_BURST_SIZE_L : integer := 68; IN_PKT_RESPONSE_STATUS_H : integer := 72; IN_PKT_RESPONSE_STATUS_L : integer := 71; IN_PKT_TRANS_EXCLUSIVE : integer := 73; IN_PKT_BURST_TYPE_H : integer := 75; IN_PKT_BURST_TYPE_L : integer := 74; IN_ST_DATA_W : integer := 76; OUT_PKT_ADDR_H : integer := 60; OUT_PKT_ADDR_L : integer := 36; OUT_PKT_DATA_H : integer := 31; OUT_PKT_DATA_L : integer := 0; OUT_PKT_BYTEEN_H : integer := 35; OUT_PKT_BYTEEN_L : integer := 32; OUT_PKT_BYTE_CNT_H : integer := 63; OUT_PKT_BYTE_CNT_L : integer := 61; OUT_PKT_TRANS_COMPRESSED_READ : integer := 65; OUT_PKT_BURST_SIZE_H : integer := 68; OUT_PKT_BURST_SIZE_L : integer := 66; OUT_PKT_RESPONSE_STATUS_H : integer := 70; OUT_PKT_RESPONSE_STATUS_L : integer := 69; OUT_PKT_TRANS_EXCLUSIVE : integer := 71; OUT_PKT_BURST_TYPE_H : integer := 73; OUT_PKT_BURST_TYPE_L : integer := 72; OUT_ST_DATA_W : integer := 74; ST_CHANNEL_W : integer := 32; OPTIMIZE_FOR_RSP : integer := 0; RESPONSE_PATH : integer := 0 ); port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset in_valid : in std_logic := 'X'; -- valid in_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel in_startofpacket : in std_logic := 'X'; -- startofpacket in_endofpacket : in std_logic := 'X'; -- endofpacket in_ready : out std_logic; -- ready in_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data out_endofpacket : out std_logic; -- endofpacket out_data : out std_logic_vector(81 downto 0); -- data out_channel : out std_logic_vector(12 downto 0); -- channel out_valid : out std_logic; -- valid out_ready : in std_logic := 'X'; -- ready out_startofpacket : out std_logic; -- startofpacket in_command_size_data : in std_logic_vector(2 downto 0) := (others => 'X') -- data ); end component niosii_system_width_adapter; component niosii_system_width_adapter_001 is generic ( IN_PKT_ADDR_H : integer := 60; IN_PKT_ADDR_L : integer := 36; IN_PKT_DATA_H : integer := 31; IN_PKT_DATA_L : integer := 0; IN_PKT_BYTEEN_H : integer := 35; IN_PKT_BYTEEN_L : integer := 32; IN_PKT_BYTE_CNT_H : integer := 63; IN_PKT_BYTE_CNT_L : integer := 61; IN_PKT_TRANS_COMPRESSED_READ : integer := 65; IN_PKT_BURSTWRAP_H : integer := 67; IN_PKT_BURSTWRAP_L : integer := 66; IN_PKT_BURST_SIZE_H : integer := 70; IN_PKT_BURST_SIZE_L : integer := 68; IN_PKT_RESPONSE_STATUS_H : integer := 72; IN_PKT_RESPONSE_STATUS_L : integer := 71; IN_PKT_TRANS_EXCLUSIVE : integer := 73; IN_PKT_BURST_TYPE_H : integer := 75; IN_PKT_BURST_TYPE_L : integer := 74; IN_ST_DATA_W : integer := 76; OUT_PKT_ADDR_H : integer := 60; OUT_PKT_ADDR_L : integer := 36; OUT_PKT_DATA_H : integer := 31; OUT_PKT_DATA_L : integer := 0; OUT_PKT_BYTEEN_H : integer := 35; OUT_PKT_BYTEEN_L : integer := 32; OUT_PKT_BYTE_CNT_H : integer := 63; OUT_PKT_BYTE_CNT_L : integer := 61; OUT_PKT_TRANS_COMPRESSED_READ : integer := 65; OUT_PKT_BURST_SIZE_H : integer := 68; OUT_PKT_BURST_SIZE_L : integer := 66; OUT_PKT_RESPONSE_STATUS_H : integer := 70; OUT_PKT_RESPONSE_STATUS_L : integer := 69; OUT_PKT_TRANS_EXCLUSIVE : integer := 71; OUT_PKT_BURST_TYPE_H : integer := 73; OUT_PKT_BURST_TYPE_L : integer := 72; OUT_ST_DATA_W : integer := 74; ST_CHANNEL_W : integer := 32; OPTIMIZE_FOR_RSP : integer := 0; RESPONSE_PATH : integer := 0 ); port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset in_valid : in std_logic := 'X'; -- valid in_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel in_startofpacket : in std_logic := 'X'; -- startofpacket in_endofpacket : in std_logic := 'X'; -- endofpacket in_ready : out std_logic; -- ready in_data : in std_logic_vector(81 downto 0) := (others => 'X'); -- data out_endofpacket : out std_logic; -- endofpacket out_data : out std_logic_vector(99 downto 0); -- data out_channel : out std_logic_vector(12 downto 0); -- channel out_valid : out std_logic; -- valid out_ready : in std_logic := 'X'; -- ready out_startofpacket : out std_logic; -- startofpacket in_command_size_data : in std_logic_vector(2 downto 0) := (others => 'X') -- data ); end component niosii_system_width_adapter_001; component niosii_system_width_adapter_004 is generic ( IN_PKT_ADDR_H : integer := 60; IN_PKT_ADDR_L : integer := 36; IN_PKT_DATA_H : integer := 31; IN_PKT_DATA_L : integer := 0; IN_PKT_BYTEEN_H : integer := 35; IN_PKT_BYTEEN_L : integer := 32; IN_PKT_BYTE_CNT_H : integer := 63; IN_PKT_BYTE_CNT_L : integer := 61; IN_PKT_TRANS_COMPRESSED_READ : integer := 65; IN_PKT_BURSTWRAP_H : integer := 67; IN_PKT_BURSTWRAP_L : integer := 66; IN_PKT_BURST_SIZE_H : integer := 70; IN_PKT_BURST_SIZE_L : integer := 68; IN_PKT_RESPONSE_STATUS_H : integer := 72; IN_PKT_RESPONSE_STATUS_L : integer := 71; IN_PKT_TRANS_EXCLUSIVE : integer := 73; IN_PKT_BURST_TYPE_H : integer := 75; IN_PKT_BURST_TYPE_L : integer := 74; IN_ST_DATA_W : integer := 76; OUT_PKT_ADDR_H : integer := 60; OUT_PKT_ADDR_L : integer := 36; OUT_PKT_DATA_H : integer := 31; OUT_PKT_DATA_L : integer := 0; OUT_PKT_BYTEEN_H : integer := 35; OUT_PKT_BYTEEN_L : integer := 32; OUT_PKT_BYTE_CNT_H : integer := 63; OUT_PKT_BYTE_CNT_L : integer := 61; OUT_PKT_TRANS_COMPRESSED_READ : integer := 65; OUT_PKT_BURST_SIZE_H : integer := 68; OUT_PKT_BURST_SIZE_L : integer := 66; OUT_PKT_RESPONSE_STATUS_H : integer := 70; OUT_PKT_RESPONSE_STATUS_L : integer := 69; OUT_PKT_TRANS_EXCLUSIVE : integer := 71; OUT_PKT_BURST_TYPE_H : integer := 73; OUT_PKT_BURST_TYPE_L : integer := 72; OUT_ST_DATA_W : integer := 74; ST_CHANNEL_W : integer := 32; OPTIMIZE_FOR_RSP : integer := 0; RESPONSE_PATH : integer := 0 ); port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset in_valid : in std_logic := 'X'; -- valid in_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel in_startofpacket : in std_logic := 'X'; -- startofpacket in_endofpacket : in std_logic := 'X'; -- endofpacket in_ready : out std_logic; -- ready in_data : in std_logic_vector(99 downto 0) := (others => 'X'); -- data out_endofpacket : out std_logic; -- endofpacket out_data : out std_logic_vector(72 downto 0); -- data out_channel : out std_logic_vector(12 downto 0); -- channel out_valid : out std_logic; -- valid out_ready : in std_logic := 'X'; -- ready out_startofpacket : out std_logic; -- startofpacket in_command_size_data : in std_logic_vector(2 downto 0) := (others => 'X') -- data ); end component niosii_system_width_adapter_004; component niosii_system_width_adapter_005 is generic ( IN_PKT_ADDR_H : integer := 60; IN_PKT_ADDR_L : integer := 36; IN_PKT_DATA_H : integer := 31; IN_PKT_DATA_L : integer := 0; IN_PKT_BYTEEN_H : integer := 35; IN_PKT_BYTEEN_L : integer := 32; IN_PKT_BYTE_CNT_H : integer := 63; IN_PKT_BYTE_CNT_L : integer := 61; IN_PKT_TRANS_COMPRESSED_READ : integer := 65; IN_PKT_BURSTWRAP_H : integer := 67; IN_PKT_BURSTWRAP_L : integer := 66; IN_PKT_BURST_SIZE_H : integer := 70; IN_PKT_BURST_SIZE_L : integer := 68; IN_PKT_RESPONSE_STATUS_H : integer := 72; IN_PKT_RESPONSE_STATUS_L : integer := 71; IN_PKT_TRANS_EXCLUSIVE : integer := 73; IN_PKT_BURST_TYPE_H : integer := 75; IN_PKT_BURST_TYPE_L : integer := 74; IN_ST_DATA_W : integer := 76; OUT_PKT_ADDR_H : integer := 60; OUT_PKT_ADDR_L : integer := 36; OUT_PKT_DATA_H : integer := 31; OUT_PKT_DATA_L : integer := 0; OUT_PKT_BYTEEN_H : integer := 35; OUT_PKT_BYTEEN_L : integer := 32; OUT_PKT_BYTE_CNT_H : integer := 63; OUT_PKT_BYTE_CNT_L : integer := 61; OUT_PKT_TRANS_COMPRESSED_READ : integer := 65; OUT_PKT_BURST_SIZE_H : integer := 68; OUT_PKT_BURST_SIZE_L : integer := 66; OUT_PKT_RESPONSE_STATUS_H : integer := 70; OUT_PKT_RESPONSE_STATUS_L : integer := 69; OUT_PKT_TRANS_EXCLUSIVE : integer := 71; OUT_PKT_BURST_TYPE_H : integer := 73; OUT_PKT_BURST_TYPE_L : integer := 72; OUT_ST_DATA_W : integer := 74; ST_CHANNEL_W : integer := 32; OPTIMIZE_FOR_RSP : integer := 0; RESPONSE_PATH : integer := 0 ); port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset in_valid : in std_logic := 'X'; -- valid in_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel in_startofpacket : in std_logic := 'X'; -- startofpacket in_endofpacket : in std_logic := 'X'; -- endofpacket in_ready : out std_logic; -- ready in_data : in std_logic_vector(72 downto 0) := (others => 'X'); -- data out_endofpacket : out std_logic; -- endofpacket out_data : out std_logic_vector(99 downto 0); -- data out_channel : out std_logic_vector(12 downto 0); -- channel out_valid : out std_logic; -- valid out_ready : in std_logic := 'X'; -- ready out_startofpacket : out std_logic; -- startofpacket in_command_size_data : in std_logic_vector(2 downto 0) := (others => 'X') -- data ); end component niosii_system_width_adapter_005; component niosii_system_nios2_qsys_0_instruction_master_translator is generic ( AV_ADDRESS_W : integer := 32; AV_DATA_W : integer := 32; AV_BURSTCOUNT_W : integer := 4; AV_BYTEENABLE_W : integer := 4; UAV_ADDRESS_W : integer := 38; UAV_BURSTCOUNT_W : integer := 10; USE_READ : integer := 1; USE_WRITE : integer := 1; USE_BEGINBURSTTRANSFER : integer := 0; USE_BEGINTRANSFER : integer := 0; USE_CHIPSELECT : integer := 0; USE_BURSTCOUNT : integer := 1; USE_READDATAVALID : integer := 1; USE_WAITREQUEST : integer := 1; USE_READRESPONSE : integer := 0; USE_WRITERESPONSE : integer := 0; AV_SYMBOLS_PER_WORD : integer := 4; AV_ADDRESS_SYMBOLS : integer := 0; AV_BURSTCOUNT_SYMBOLS : integer := 0; AV_CONSTANT_BURST_BEHAVIOR : integer := 0; UAV_CONSTANT_BURST_BEHAVIOR : integer := 0; AV_LINEWRAPBURSTS : integer := 0; AV_REGISTERINCOMINGSIGNALS : integer := 0 ); port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset uav_address : out std_logic_vector(24 downto 0); -- address uav_burstcount : out std_logic_vector(2 downto 0); -- burstcount uav_read : out std_logic; -- read uav_write : out std_logic; -- write uav_waitrequest : in std_logic := 'X'; -- waitrequest uav_readdatavalid : in std_logic := 'X'; -- readdatavalid uav_byteenable : out std_logic_vector(3 downto 0); -- byteenable uav_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata uav_writedata : out std_logic_vector(31 downto 0); -- writedata uav_lock : out std_logic; -- lock uav_debugaccess : out std_logic; -- debugaccess av_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address av_waitrequest : out std_logic; -- waitrequest av_read : in std_logic := 'X'; -- read av_readdata : out std_logic_vector(31 downto 0); -- readdata av_burstcount : in std_logic_vector(0 downto 0) := (others => 'X'); -- burstcount av_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable av_beginbursttransfer : in std_logic := 'X'; -- beginbursttransfer av_begintransfer : in std_logic := 'X'; -- begintransfer av_chipselect : in std_logic := 'X'; -- chipselect av_readdatavalid : out std_logic; -- readdatavalid av_write : in std_logic := 'X'; -- write av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata av_lock : in std_logic := 'X'; -- lock av_debugaccess : in std_logic := 'X'; -- debugaccess uav_clken : out std_logic; -- clken av_clken : in std_logic := 'X'; -- clken uav_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response av_response : out std_logic_vector(1 downto 0); -- response uav_writeresponserequest : out std_logic; -- writeresponserequest uav_writeresponsevalid : in std_logic := 'X'; -- writeresponsevalid av_writeresponserequest : in std_logic := 'X'; -- writeresponserequest av_writeresponsevalid : out std_logic -- writeresponsevalid ); end component niosii_system_nios2_qsys_0_instruction_master_translator; component niosii_system_nios2_qsys_0_data_master_translator is generic ( AV_ADDRESS_W : integer := 32; AV_DATA_W : integer := 32; AV_BURSTCOUNT_W : integer := 4; AV_BYTEENABLE_W : integer := 4; UAV_ADDRESS_W : integer := 38; UAV_BURSTCOUNT_W : integer := 10; USE_READ : integer := 1; USE_WRITE : integer := 1; USE_BEGINBURSTTRANSFER : integer := 0; USE_BEGINTRANSFER : integer := 0; USE_CHIPSELECT : integer := 0; USE_BURSTCOUNT : integer := 1; USE_READDATAVALID : integer := 1; USE_WAITREQUEST : integer := 1; USE_READRESPONSE : integer := 0; USE_WRITERESPONSE : integer := 0; AV_SYMBOLS_PER_WORD : integer := 4; AV_ADDRESS_SYMBOLS : integer := 0; AV_BURSTCOUNT_SYMBOLS : integer := 0; AV_CONSTANT_BURST_BEHAVIOR : integer := 0; UAV_CONSTANT_BURST_BEHAVIOR : integer := 0; AV_LINEWRAPBURSTS : integer := 0; AV_REGISTERINCOMINGSIGNALS : integer := 0 ); port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset uav_address : out std_logic_vector(24 downto 0); -- address uav_burstcount : out std_logic_vector(2 downto 0); -- burstcount uav_read : out std_logic; -- read uav_write : out std_logic; -- write uav_waitrequest : in std_logic := 'X'; -- waitrequest uav_readdatavalid : in std_logic := 'X'; -- readdatavalid uav_byteenable : out std_logic_vector(3 downto 0); -- byteenable uav_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata uav_writedata : out std_logic_vector(31 downto 0); -- writedata uav_lock : out std_logic; -- lock uav_debugaccess : out std_logic; -- debugaccess av_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address av_waitrequest : out std_logic; -- waitrequest av_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable av_read : in std_logic := 'X'; -- read av_readdata : out std_logic_vector(31 downto 0); -- readdata av_write : in std_logic := 'X'; -- write av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata av_debugaccess : in std_logic := 'X'; -- debugaccess av_burstcount : in std_logic_vector(0 downto 0) := (others => 'X'); -- burstcount av_beginbursttransfer : in std_logic := 'X'; -- beginbursttransfer av_begintransfer : in std_logic := 'X'; -- begintransfer av_chipselect : in std_logic := 'X'; -- chipselect av_readdatavalid : out std_logic; -- readdatavalid av_lock : in std_logic := 'X'; -- lock uav_clken : out std_logic; -- clken av_clken : in std_logic := 'X'; -- clken uav_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response av_response : out std_logic_vector(1 downto 0); -- response uav_writeresponserequest : out std_logic; -- writeresponserequest uav_writeresponsevalid : in std_logic := 'X'; -- writeresponsevalid av_writeresponserequest : in std_logic := 'X'; -- writeresponserequest av_writeresponsevalid : out std_logic -- writeresponsevalid ); end component niosii_system_nios2_qsys_0_data_master_translator; component niosii_system_burst_adapter is generic ( PKT_ADDR_H : integer := 79; PKT_ADDR_L : integer := 48; PKT_BEGIN_BURST : integer := 81; PKT_BYTE_CNT_H : integer := 5; PKT_BYTE_CNT_L : integer := 0; PKT_BYTEEN_H : integer := 83; PKT_BYTEEN_L : integer := 80; PKT_BURST_SIZE_H : integer := 86; PKT_BURST_SIZE_L : integer := 84; PKT_BURST_TYPE_H : integer := 88; PKT_BURST_TYPE_L : integer := 87; PKT_BURSTWRAP_H : integer := 11; PKT_BURSTWRAP_L : integer := 6; PKT_TRANS_COMPRESSED_READ : integer := 14; PKT_TRANS_WRITE : integer := 13; PKT_TRANS_READ : integer := 12; OUT_NARROW_SIZE : integer := 0; IN_NARROW_SIZE : integer := 0; OUT_FIXED : integer := 0; OUT_COMPLETE_WRAP : integer := 0; ST_DATA_W : integer := 89; ST_CHANNEL_W : integer := 8; OUT_BYTE_CNT_H : integer := 5; OUT_BURSTWRAP_H : integer := 11; COMPRESSED_READ_SUPPORT : integer := 1; BYTEENABLE_SYNTHESIS : integer := 0; PIPE_INPUTS : integer := 0; NO_WRAP_SUPPORT : integer := 0; BURSTWRAP_CONST_MASK : integer := 0; BURSTWRAP_CONST_VALUE : integer := -1 ); port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset sink0_valid : in std_logic := 'X'; -- valid sink0_data : in std_logic_vector(81 downto 0) := (others => 'X'); -- data sink0_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel sink0_startofpacket : in std_logic := 'X'; -- startofpacket sink0_endofpacket : in std_logic := 'X'; -- endofpacket sink0_ready : out std_logic; -- ready source0_valid : out std_logic; -- valid source0_data : out std_logic_vector(81 downto 0); -- data source0_channel : out std_logic_vector(12 downto 0); -- channel source0_startofpacket : out std_logic; -- startofpacket source0_endofpacket : out std_logic; -- endofpacket source0_ready : in std_logic := 'X' -- ready ); end component niosii_system_burst_adapter; component niosii_system_burst_adapter_002 is generic ( PKT_ADDR_H : integer := 79; PKT_ADDR_L : integer := 48; PKT_BEGIN_BURST : integer := 81; PKT_BYTE_CNT_H : integer := 5; PKT_BYTE_CNT_L : integer := 0; PKT_BYTEEN_H : integer := 83; PKT_BYTEEN_L : integer := 80; PKT_BURST_SIZE_H : integer := 86; PKT_BURST_SIZE_L : integer := 84; PKT_BURST_TYPE_H : integer := 88; PKT_BURST_TYPE_L : integer := 87; PKT_BURSTWRAP_H : integer := 11; PKT_BURSTWRAP_L : integer := 6; PKT_TRANS_COMPRESSED_READ : integer := 14; PKT_TRANS_WRITE : integer := 13; PKT_TRANS_READ : integer := 12; OUT_NARROW_SIZE : integer := 0; IN_NARROW_SIZE : integer := 0; OUT_FIXED : integer := 0; OUT_COMPLETE_WRAP : integer := 0; ST_DATA_W : integer := 89; ST_CHANNEL_W : integer := 8; OUT_BYTE_CNT_H : integer := 5; OUT_BURSTWRAP_H : integer := 11; COMPRESSED_READ_SUPPORT : integer := 1; BYTEENABLE_SYNTHESIS : integer := 0; PIPE_INPUTS : integer := 0; NO_WRAP_SUPPORT : integer := 0; BURSTWRAP_CONST_MASK : integer := 0; BURSTWRAP_CONST_VALUE : integer := -1 ); port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset sink0_valid : in std_logic := 'X'; -- valid sink0_data : in std_logic_vector(72 downto 0) := (others => 'X'); -- data sink0_channel : in std_logic_vector(12 downto 0) := (others => 'X'); -- channel sink0_startofpacket : in std_logic := 'X'; -- startofpacket sink0_endofpacket : in std_logic := 'X'; -- endofpacket sink0_ready : out std_logic; -- ready source0_valid : out std_logic; -- valid source0_data : out std_logic_vector(72 downto 0); -- data source0_channel : out std_logic_vector(12 downto 0); -- channel source0_startofpacket : out std_logic; -- startofpacket source0_endofpacket : out std_logic; -- endofpacket source0_ready : in std_logic := 'X' -- ready ); end component niosii_system_burst_adapter_002; component niosii_system_nios2_qsys_0_jtag_debug_module_translator is generic ( AV_ADDRESS_W : integer := 30; AV_DATA_W : integer := 32; UAV_DATA_W : integer := 32; AV_BURSTCOUNT_W : integer := 4; AV_BYTEENABLE_W : integer := 4; UAV_BYTEENABLE_W : integer := 4; UAV_ADDRESS_W : integer := 32; UAV_BURSTCOUNT_W : integer := 4; AV_READLATENCY : integer := 0; USE_READDATAVALID : integer := 1; USE_WAITREQUEST : integer := 1; USE_UAV_CLKEN : integer := 0; USE_READRESPONSE : integer := 0; USE_WRITERESPONSE : integer := 0; AV_SYMBOLS_PER_WORD : integer := 4; AV_ADDRESS_SYMBOLS : integer := 0; AV_BURSTCOUNT_SYMBOLS : integer := 0; AV_CONSTANT_BURST_BEHAVIOR : integer := 0; UAV_CONSTANT_BURST_BEHAVIOR : integer := 0; AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0; CHIPSELECT_THROUGH_READLATENCY : integer := 0; AV_READ_WAIT_CYCLES : integer := 0; AV_WRITE_WAIT_CYCLES : integer := 0; AV_SETUP_WAIT_CYCLES : integer := 0; AV_DATA_HOLD_CYCLES : integer := 0 ); port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount uav_read : in std_logic := 'X'; -- read uav_write : in std_logic := 'X'; -- write uav_waitrequest : out std_logic; -- waitrequest uav_readdatavalid : out std_logic; -- readdatavalid uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable uav_readdata : out std_logic_vector(31 downto 0); -- readdata uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata uav_lock : in std_logic := 'X'; -- lock uav_debugaccess : in std_logic := 'X'; -- debugaccess av_address : out std_logic_vector(8 downto 0); -- address av_write : out std_logic; -- write av_read : out std_logic; -- read av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata av_writedata : out std_logic_vector(31 downto 0); -- writedata av_byteenable : out std_logic_vector(3 downto 0); -- byteenable av_waitrequest : in std_logic := 'X'; -- waitrequest av_debugaccess : out std_logic; -- debugaccess av_begintransfer : out std_logic; -- begintransfer av_beginbursttransfer : out std_logic; -- beginbursttransfer av_burstcount : out std_logic_vector(0 downto 0); -- burstcount av_readdatavalid : in std_logic := 'X'; -- readdatavalid av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable av_lock : out std_logic; -- lock av_chipselect : out std_logic; -- chipselect av_clken : out std_logic; -- clken uav_clken : in std_logic := 'X'; -- clken av_outputenable : out std_logic; -- outputenable uav_response : out std_logic_vector(1 downto 0); -- response av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest uav_writeresponsevalid : out std_logic; -- writeresponsevalid av_writeresponserequest : out std_logic; -- writeresponserequest av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid ); end component niosii_system_nios2_qsys_0_jtag_debug_module_translator; component niosii_system_sdram_0_s1_translator is generic ( AV_ADDRESS_W : integer := 30; AV_DATA_W : integer := 32; UAV_DATA_W : integer := 32; AV_BURSTCOUNT_W : integer := 4; AV_BYTEENABLE_W : integer := 4; UAV_BYTEENABLE_W : integer := 4; UAV_ADDRESS_W : integer := 32; UAV_BURSTCOUNT_W : integer := 4; AV_READLATENCY : integer := 0; USE_READDATAVALID : integer := 1; USE_WAITREQUEST : integer := 1; USE_UAV_CLKEN : integer := 0; USE_READRESPONSE : integer := 0; USE_WRITERESPONSE : integer := 0; AV_SYMBOLS_PER_WORD : integer := 4; AV_ADDRESS_SYMBOLS : integer := 0; AV_BURSTCOUNT_SYMBOLS : integer := 0; AV_CONSTANT_BURST_BEHAVIOR : integer := 0; UAV_CONSTANT_BURST_BEHAVIOR : integer := 0; AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0; CHIPSELECT_THROUGH_READLATENCY : integer := 0; AV_READ_WAIT_CYCLES : integer := 0; AV_WRITE_WAIT_CYCLES : integer := 0; AV_SETUP_WAIT_CYCLES : integer := 0; AV_DATA_HOLD_CYCLES : integer := 0 ); port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address uav_burstcount : in std_logic_vector(1 downto 0) := (others => 'X'); -- burstcount uav_read : in std_logic := 'X'; -- read uav_write : in std_logic := 'X'; -- write uav_waitrequest : out std_logic; -- waitrequest uav_readdatavalid : out std_logic; -- readdatavalid uav_byteenable : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable uav_readdata : out std_logic_vector(15 downto 0); -- readdata uav_writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata uav_lock : in std_logic := 'X'; -- lock uav_debugaccess : in std_logic := 'X'; -- debugaccess av_address : out std_logic_vector(21 downto 0); -- address av_write : out std_logic; -- write av_read : out std_logic; -- read av_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata av_writedata : out std_logic_vector(15 downto 0); -- writedata av_byteenable : out std_logic_vector(1 downto 0); -- byteenable av_readdatavalid : in std_logic := 'X'; -- readdatavalid av_waitrequest : in std_logic := 'X'; -- waitrequest av_chipselect : out std_logic; -- chipselect av_begintransfer : out std_logic; -- begintransfer av_beginbursttransfer : out std_logic; -- beginbursttransfer av_burstcount : out std_logic_vector(0 downto 0); -- burstcount av_writebyteenable : out std_logic_vector(1 downto 0); -- writebyteenable av_lock : out std_logic; -- lock av_clken : out std_logic; -- clken uav_clken : in std_logic := 'X'; -- clken av_debugaccess : out std_logic; -- debugaccess av_outputenable : out std_logic; -- outputenable uav_response : out std_logic_vector(1 downto 0); -- response av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest uav_writeresponsevalid : out std_logic; -- writeresponsevalid av_writeresponserequest : out std_logic; -- writeresponserequest av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid ); end component niosii_system_sdram_0_s1_translator; component niosii_system_onchip_memory2_0_s1_translator is generic ( AV_ADDRESS_W : integer := 30; AV_DATA_W : integer := 32; UAV_DATA_W : integer := 32; AV_BURSTCOUNT_W : integer := 4; AV_BYTEENABLE_W : integer := 4; UAV_BYTEENABLE_W : integer := 4; UAV_ADDRESS_W : integer := 32; UAV_BURSTCOUNT_W : integer := 4; AV_READLATENCY : integer := 0; USE_READDATAVALID : integer := 1; USE_WAITREQUEST : integer := 1; USE_UAV_CLKEN : integer := 0; USE_READRESPONSE : integer := 0; USE_WRITERESPONSE : integer := 0; AV_SYMBOLS_PER_WORD : integer := 4; AV_ADDRESS_SYMBOLS : integer := 0; AV_BURSTCOUNT_SYMBOLS : integer := 0; AV_CONSTANT_BURST_BEHAVIOR : integer := 0; UAV_CONSTANT_BURST_BEHAVIOR : integer := 0; AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0; CHIPSELECT_THROUGH_READLATENCY : integer := 0; AV_READ_WAIT_CYCLES : integer := 0; AV_WRITE_WAIT_CYCLES : integer := 0; AV_SETUP_WAIT_CYCLES : integer := 0; AV_DATA_HOLD_CYCLES : integer := 0 ); port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount uav_read : in std_logic := 'X'; -- read uav_write : in std_logic := 'X'; -- write uav_waitrequest : out std_logic; -- waitrequest uav_readdatavalid : out std_logic; -- readdatavalid uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable uav_readdata : out std_logic_vector(31 downto 0); -- readdata uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata uav_lock : in std_logic := 'X'; -- lock uav_debugaccess : in std_logic := 'X'; -- debugaccess av_address : out std_logic_vector(11 downto 0); -- address av_write : out std_logic; -- write av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata av_writedata : out std_logic_vector(31 downto 0); -- writedata av_byteenable : out std_logic_vector(3 downto 0); -- byteenable av_chipselect : out std_logic; -- chipselect av_clken : out std_logic; -- clken av_read : out std_logic; -- read av_begintransfer : out std_logic; -- begintransfer av_beginbursttransfer : out std_logic; -- beginbursttransfer av_burstcount : out std_logic_vector(0 downto 0); -- burstcount av_readdatavalid : in std_logic := 'X'; -- readdatavalid av_waitrequest : in std_logic := 'X'; -- waitrequest av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable av_lock : out std_logic; -- lock uav_clken : in std_logic := 'X'; -- clken av_debugaccess : out std_logic; -- debugaccess av_outputenable : out std_logic; -- outputenable uav_response : out std_logic_vector(1 downto 0); -- response av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest uav_writeresponsevalid : out std_logic; -- writeresponsevalid av_writeresponserequest : out std_logic; -- writeresponserequest av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid ); end component niosii_system_onchip_memory2_0_s1_translator; component niosii_system_sram_0_avalon_sram_slave_translator is generic ( AV_ADDRESS_W : integer := 30; AV_DATA_W : integer := 32; UAV_DATA_W : integer := 32; AV_BURSTCOUNT_W : integer := 4; AV_BYTEENABLE_W : integer := 4; UAV_BYTEENABLE_W : integer := 4; UAV_ADDRESS_W : integer := 32; UAV_BURSTCOUNT_W : integer := 4; AV_READLATENCY : integer := 0; USE_READDATAVALID : integer := 1; USE_WAITREQUEST : integer := 1; USE_UAV_CLKEN : integer := 0; USE_READRESPONSE : integer := 0; USE_WRITERESPONSE : integer := 0; AV_SYMBOLS_PER_WORD : integer := 4; AV_ADDRESS_SYMBOLS : integer := 0; AV_BURSTCOUNT_SYMBOLS : integer := 0; AV_CONSTANT_BURST_BEHAVIOR : integer := 0; UAV_CONSTANT_BURST_BEHAVIOR : integer := 0; AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0; CHIPSELECT_THROUGH_READLATENCY : integer := 0; AV_READ_WAIT_CYCLES : integer := 0; AV_WRITE_WAIT_CYCLES : integer := 0; AV_SETUP_WAIT_CYCLES : integer := 0; AV_DATA_HOLD_CYCLES : integer := 0 ); port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address uav_burstcount : in std_logic_vector(1 downto 0) := (others => 'X'); -- burstcount uav_read : in std_logic := 'X'; -- read uav_write : in std_logic := 'X'; -- write uav_waitrequest : out std_logic; -- waitrequest uav_readdatavalid : out std_logic; -- readdatavalid uav_byteenable : in std_logic_vector(1 downto 0) := (others => 'X'); -- byteenable uav_readdata : out std_logic_vector(15 downto 0); -- readdata uav_writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata uav_lock : in std_logic := 'X'; -- lock uav_debugaccess : in std_logic := 'X'; -- debugaccess av_address : out std_logic_vector(17 downto 0); -- address av_write : out std_logic; -- write av_read : out std_logic; -- read av_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata av_writedata : out std_logic_vector(15 downto 0); -- writedata av_byteenable : out std_logic_vector(1 downto 0); -- byteenable av_readdatavalid : in std_logic := 'X'; -- readdatavalid av_begintransfer : out std_logic; -- begintransfer av_beginbursttransfer : out std_logic; -- beginbursttransfer av_burstcount : out std_logic_vector(0 downto 0); -- burstcount av_waitrequest : in std_logic := 'X'; -- waitrequest av_writebyteenable : out std_logic_vector(1 downto 0); -- writebyteenable av_lock : out std_logic; -- lock av_chipselect : out std_logic; -- chipselect av_clken : out std_logic; -- clken uav_clken : in std_logic := 'X'; -- clken av_debugaccess : out std_logic; -- debugaccess av_outputenable : out std_logic; -- outputenable uav_response : out std_logic_vector(1 downto 0); -- response av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest uav_writeresponsevalid : out std_logic; -- writeresponsevalid av_writeresponserequest : out std_logic; -- writeresponserequest av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid ); end component niosii_system_sram_0_avalon_sram_slave_translator; component niosii_system_generic_tristate_controller_0_uas_translator is generic ( AV_ADDRESS_W : integer := 30; AV_DATA_W : integer := 32; UAV_DATA_W : integer := 32; AV_BURSTCOUNT_W : integer := 4; AV_BYTEENABLE_W : integer := 4; UAV_BYTEENABLE_W : integer := 4; UAV_ADDRESS_W : integer := 32; UAV_BURSTCOUNT_W : integer := 4; AV_READLATENCY : integer := 0; USE_READDATAVALID : integer := 1; USE_WAITREQUEST : integer := 1; USE_UAV_CLKEN : integer := 0; USE_READRESPONSE : integer := 0; USE_WRITERESPONSE : integer := 0; AV_SYMBOLS_PER_WORD : integer := 4; AV_ADDRESS_SYMBOLS : integer := 0; AV_BURSTCOUNT_SYMBOLS : integer := 0; AV_CONSTANT_BURST_BEHAVIOR : integer := 0; UAV_CONSTANT_BURST_BEHAVIOR : integer := 0; AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0; CHIPSELECT_THROUGH_READLATENCY : integer := 0; AV_READ_WAIT_CYCLES : integer := 0; AV_WRITE_WAIT_CYCLES : integer := 0; AV_SETUP_WAIT_CYCLES : integer := 0; AV_DATA_HOLD_CYCLES : integer := 0 ); port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address uav_burstcount : in std_logic_vector(0 downto 0) := (others => 'X'); -- burstcount uav_read : in std_logic := 'X'; -- read uav_write : in std_logic := 'X'; -- write uav_waitrequest : out std_logic; -- waitrequest uav_readdatavalid : out std_logic; -- readdatavalid uav_byteenable : in std_logic_vector(0 downto 0) := (others => 'X'); -- byteenable uav_readdata : out std_logic_vector(7 downto 0); -- readdata uav_writedata : in std_logic_vector(7 downto 0) := (others => 'X'); -- writedata uav_lock : in std_logic := 'X'; -- lock uav_debugaccess : in std_logic := 'X'; -- debugaccess av_address : out std_logic_vector(21 downto 0); -- address av_write : out std_logic; -- write av_read : out std_logic; -- read av_readdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- readdata av_writedata : out std_logic_vector(7 downto 0); -- writedata av_burstcount : out std_logic_vector(0 downto 0); -- burstcount av_byteenable : out std_logic_vector(0 downto 0); -- byteenable av_readdatavalid : in std_logic := 'X'; -- readdatavalid av_waitrequest : in std_logic := 'X'; -- waitrequest av_lock : out std_logic; -- lock av_debugaccess : out std_logic; -- debugaccess av_begintransfer : out std_logic; -- begintransfer av_beginbursttransfer : out std_logic; -- beginbursttransfer av_writebyteenable : out std_logic_vector(0 downto 0); -- writebyteenable av_chipselect : out std_logic; -- chipselect av_clken : out std_logic; -- clken uav_clken : in std_logic := 'X'; -- clken av_outputenable : out std_logic; -- outputenable uav_response : out std_logic_vector(1 downto 0); -- response av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest uav_writeresponsevalid : out std_logic; -- writeresponsevalid av_writeresponserequest : out std_logic; -- writeresponserequest av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid ); end component niosii_system_generic_tristate_controller_0_uas_translator; component niosii_system_jtag_uart_0_avalon_jtag_slave_translator is generic ( AV_ADDRESS_W : integer := 30; AV_DATA_W : integer := 32; UAV_DATA_W : integer := 32; AV_BURSTCOUNT_W : integer := 4; AV_BYTEENABLE_W : integer := 4; UAV_BYTEENABLE_W : integer := 4; UAV_ADDRESS_W : integer := 32; UAV_BURSTCOUNT_W : integer := 4; AV_READLATENCY : integer := 0; USE_READDATAVALID : integer := 1; USE_WAITREQUEST : integer := 1; USE_UAV_CLKEN : integer := 0; USE_READRESPONSE : integer := 0; USE_WRITERESPONSE : integer := 0; AV_SYMBOLS_PER_WORD : integer := 4; AV_ADDRESS_SYMBOLS : integer := 0; AV_BURSTCOUNT_SYMBOLS : integer := 0; AV_CONSTANT_BURST_BEHAVIOR : integer := 0; UAV_CONSTANT_BURST_BEHAVIOR : integer := 0; AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0; CHIPSELECT_THROUGH_READLATENCY : integer := 0; AV_READ_WAIT_CYCLES : integer := 0; AV_WRITE_WAIT_CYCLES : integer := 0; AV_SETUP_WAIT_CYCLES : integer := 0; AV_DATA_HOLD_CYCLES : integer := 0 ); port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount uav_read : in std_logic := 'X'; -- read uav_write : in std_logic := 'X'; -- write uav_waitrequest : out std_logic; -- waitrequest uav_readdatavalid : out std_logic; -- readdatavalid uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable uav_readdata : out std_logic_vector(31 downto 0); -- readdata uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata uav_lock : in std_logic := 'X'; -- lock uav_debugaccess : in std_logic := 'X'; -- debugaccess av_address : out std_logic_vector(0 downto 0); -- address av_write : out std_logic; -- write av_read : out std_logic; -- read av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata av_writedata : out std_logic_vector(31 downto 0); -- writedata av_waitrequest : in std_logic := 'X'; -- waitrequest av_chipselect : out std_logic; -- chipselect av_begintransfer : out std_logic; -- begintransfer av_beginbursttransfer : out std_logic; -- beginbursttransfer av_burstcount : out std_logic_vector(0 downto 0); -- burstcount av_byteenable : out std_logic_vector(0 downto 0); -- byteenable av_readdatavalid : in std_logic := 'X'; -- readdatavalid av_writebyteenable : out std_logic_vector(0 downto 0); -- writebyteenable av_lock : out std_logic; -- lock av_clken : out std_logic; -- clken uav_clken : in std_logic := 'X'; -- clken av_debugaccess : out std_logic; -- debugaccess av_outputenable : out std_logic; -- outputenable uav_response : out std_logic_vector(1 downto 0); -- response av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest uav_writeresponsevalid : out std_logic; -- writeresponsevalid av_writeresponserequest : out std_logic; -- writeresponserequest av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid ); end component niosii_system_jtag_uart_0_avalon_jtag_slave_translator; component niosii_system_sysid_qsys_0_control_slave_translator is generic ( AV_ADDRESS_W : integer := 30; AV_DATA_W : integer := 32; UAV_DATA_W : integer := 32; AV_BURSTCOUNT_W : integer := 4; AV_BYTEENABLE_W : integer := 4; UAV_BYTEENABLE_W : integer := 4; UAV_ADDRESS_W : integer := 32; UAV_BURSTCOUNT_W : integer := 4; AV_READLATENCY : integer := 0; USE_READDATAVALID : integer := 1; USE_WAITREQUEST : integer := 1; USE_UAV_CLKEN : integer := 0; USE_READRESPONSE : integer := 0; USE_WRITERESPONSE : integer := 0; AV_SYMBOLS_PER_WORD : integer := 4; AV_ADDRESS_SYMBOLS : integer := 0; AV_BURSTCOUNT_SYMBOLS : integer := 0; AV_CONSTANT_BURST_BEHAVIOR : integer := 0; UAV_CONSTANT_BURST_BEHAVIOR : integer := 0; AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0; CHIPSELECT_THROUGH_READLATENCY : integer := 0; AV_READ_WAIT_CYCLES : integer := 0; AV_WRITE_WAIT_CYCLES : integer := 0; AV_SETUP_WAIT_CYCLES : integer := 0; AV_DATA_HOLD_CYCLES : integer := 0 ); port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount uav_read : in std_logic := 'X'; -- read uav_write : in std_logic := 'X'; -- write uav_waitrequest : out std_logic; -- waitrequest uav_readdatavalid : out std_logic; -- readdatavalid uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable uav_readdata : out std_logic_vector(31 downto 0); -- readdata uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata uav_lock : in std_logic := 'X'; -- lock uav_debugaccess : in std_logic := 'X'; -- debugaccess av_address : out std_logic_vector(0 downto 0); -- address av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata av_write : out std_logic; -- write av_read : out std_logic; -- read av_writedata : out std_logic_vector(31 downto 0); -- writedata av_begintransfer : out std_logic; -- begintransfer av_beginbursttransfer : out std_logic; -- beginbursttransfer av_burstcount : out std_logic_vector(0 downto 0); -- burstcount av_byteenable : out std_logic_vector(3 downto 0); -- byteenable av_readdatavalid : in std_logic := 'X'; -- readdatavalid av_waitrequest : in std_logic := 'X'; -- waitrequest av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable av_lock : out std_logic; -- lock av_chipselect : out std_logic; -- chipselect av_clken : out std_logic; -- clken uav_clken : in std_logic := 'X'; -- clken av_debugaccess : out std_logic; -- debugaccess av_outputenable : out std_logic; -- outputenable uav_response : out std_logic_vector(1 downto 0); -- response av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest uav_writeresponsevalid : out std_logic; -- writeresponsevalid av_writeresponserequest : out std_logic; -- writeresponserequest av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid ); end component niosii_system_sysid_qsys_0_control_slave_translator; component niosii_system_green_leds_s1_translator is generic ( AV_ADDRESS_W : integer := 30; AV_DATA_W : integer := 32; UAV_DATA_W : integer := 32; AV_BURSTCOUNT_W : integer := 4; AV_BYTEENABLE_W : integer := 4; UAV_BYTEENABLE_W : integer := 4; UAV_ADDRESS_W : integer := 32; UAV_BURSTCOUNT_W : integer := 4; AV_READLATENCY : integer := 0; USE_READDATAVALID : integer := 1; USE_WAITREQUEST : integer := 1; USE_UAV_CLKEN : integer := 0; USE_READRESPONSE : integer := 0; USE_WRITERESPONSE : integer := 0; AV_SYMBOLS_PER_WORD : integer := 4; AV_ADDRESS_SYMBOLS : integer := 0; AV_BURSTCOUNT_SYMBOLS : integer := 0; AV_CONSTANT_BURST_BEHAVIOR : integer := 0; UAV_CONSTANT_BURST_BEHAVIOR : integer := 0; AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0; CHIPSELECT_THROUGH_READLATENCY : integer := 0; AV_READ_WAIT_CYCLES : integer := 0; AV_WRITE_WAIT_CYCLES : integer := 0; AV_SETUP_WAIT_CYCLES : integer := 0; AV_DATA_HOLD_CYCLES : integer := 0 ); port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount uav_read : in std_logic := 'X'; -- read uav_write : in std_logic := 'X'; -- write uav_waitrequest : out std_logic; -- waitrequest uav_readdatavalid : out std_logic; -- readdatavalid uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable uav_readdata : out std_logic_vector(31 downto 0); -- readdata uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata uav_lock : in std_logic := 'X'; -- lock uav_debugaccess : in std_logic := 'X'; -- debugaccess av_address : out std_logic_vector(1 downto 0); -- address av_write : out std_logic; -- write av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata av_writedata : out std_logic_vector(31 downto 0); -- writedata av_chipselect : out std_logic; -- chipselect av_read : out std_logic; -- read av_begintransfer : out std_logic; -- begintransfer av_beginbursttransfer : out std_logic; -- beginbursttransfer av_burstcount : out std_logic_vector(0 downto 0); -- burstcount av_byteenable : out std_logic_vector(0 downto 0); -- byteenable av_readdatavalid : in std_logic := 'X'; -- readdatavalid av_waitrequest : in std_logic := 'X'; -- waitrequest av_writebyteenable : out std_logic_vector(0 downto 0); -- writebyteenable av_lock : out std_logic; -- lock av_clken : out std_logic; -- clken uav_clken : in std_logic := 'X'; -- clken av_debugaccess : out std_logic; -- debugaccess av_outputenable : out std_logic; -- outputenable uav_response : out std_logic_vector(1 downto 0); -- response av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest uav_writeresponsevalid : out std_logic; -- writeresponsevalid av_writeresponserequest : out std_logic; -- writeresponserequest av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid ); end component niosii_system_green_leds_s1_translator; component niosii_system_switches_s1_translator is generic ( AV_ADDRESS_W : integer := 30; AV_DATA_W : integer := 32; UAV_DATA_W : integer := 32; AV_BURSTCOUNT_W : integer := 4; AV_BYTEENABLE_W : integer := 4; UAV_BYTEENABLE_W : integer := 4; UAV_ADDRESS_W : integer := 32; UAV_BURSTCOUNT_W : integer := 4; AV_READLATENCY : integer := 0; USE_READDATAVALID : integer := 1; USE_WAITREQUEST : integer := 1; USE_UAV_CLKEN : integer := 0; USE_READRESPONSE : integer := 0; USE_WRITERESPONSE : integer := 0; AV_SYMBOLS_PER_WORD : integer := 4; AV_ADDRESS_SYMBOLS : integer := 0; AV_BURSTCOUNT_SYMBOLS : integer := 0; AV_CONSTANT_BURST_BEHAVIOR : integer := 0; UAV_CONSTANT_BURST_BEHAVIOR : integer := 0; AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0; CHIPSELECT_THROUGH_READLATENCY : integer := 0; AV_READ_WAIT_CYCLES : integer := 0; AV_WRITE_WAIT_CYCLES : integer := 0; AV_SETUP_WAIT_CYCLES : integer := 0; AV_DATA_HOLD_CYCLES : integer := 0 ); port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount uav_read : in std_logic := 'X'; -- read uav_write : in std_logic := 'X'; -- write uav_waitrequest : out std_logic; -- waitrequest uav_readdatavalid : out std_logic; -- readdatavalid uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable uav_readdata : out std_logic_vector(31 downto 0); -- readdata uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata uav_lock : in std_logic := 'X'; -- lock uav_debugaccess : in std_logic := 'X'; -- debugaccess av_address : out std_logic_vector(1 downto 0); -- address av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata av_write : out std_logic; -- write av_read : out std_logic; -- read av_writedata : out std_logic_vector(31 downto 0); -- writedata av_begintransfer : out std_logic; -- begintransfer av_beginbursttransfer : out std_logic; -- beginbursttransfer av_burstcount : out std_logic_vector(0 downto 0); -- burstcount av_byteenable : out std_logic_vector(0 downto 0); -- byteenable av_readdatavalid : in std_logic := 'X'; -- readdatavalid av_waitrequest : in std_logic := 'X'; -- waitrequest av_writebyteenable : out std_logic_vector(0 downto 0); -- writebyteenable av_lock : out std_logic; -- lock av_chipselect : out std_logic; -- chipselect av_clken : out std_logic; -- clken uav_clken : in std_logic := 'X'; -- clken av_debugaccess : out std_logic; -- debugaccess av_outputenable : out std_logic; -- outputenable uav_response : out std_logic_vector(1 downto 0); -- response av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest uav_writeresponsevalid : out std_logic; -- writeresponsevalid av_writeresponserequest : out std_logic; -- writeresponserequest av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid ); end component niosii_system_switches_s1_translator; component niosii_system_altpll_0_pll_slave_translator is generic ( AV_ADDRESS_W : integer := 30; AV_DATA_W : integer := 32; UAV_DATA_W : integer := 32; AV_BURSTCOUNT_W : integer := 4; AV_BYTEENABLE_W : integer := 4; UAV_BYTEENABLE_W : integer := 4; UAV_ADDRESS_W : integer := 32; UAV_BURSTCOUNT_W : integer := 4; AV_READLATENCY : integer := 0; USE_READDATAVALID : integer := 1; USE_WAITREQUEST : integer := 1; USE_UAV_CLKEN : integer := 0; USE_READRESPONSE : integer := 0; USE_WRITERESPONSE : integer := 0; AV_SYMBOLS_PER_WORD : integer := 4; AV_ADDRESS_SYMBOLS : integer := 0; AV_BURSTCOUNT_SYMBOLS : integer := 0; AV_CONSTANT_BURST_BEHAVIOR : integer := 0; UAV_CONSTANT_BURST_BEHAVIOR : integer := 0; AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0; CHIPSELECT_THROUGH_READLATENCY : integer := 0; AV_READ_WAIT_CYCLES : integer := 0; AV_WRITE_WAIT_CYCLES : integer := 0; AV_SETUP_WAIT_CYCLES : integer := 0; AV_DATA_HOLD_CYCLES : integer := 0 ); port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount uav_read : in std_logic := 'X'; -- read uav_write : in std_logic := 'X'; -- write uav_waitrequest : out std_logic; -- waitrequest uav_readdatavalid : out std_logic; -- readdatavalid uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable uav_readdata : out std_logic_vector(31 downto 0); -- readdata uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata uav_lock : in std_logic := 'X'; -- lock uav_debugaccess : in std_logic := 'X'; -- debugaccess av_address : out std_logic_vector(1 downto 0); -- address av_write : out std_logic; -- write av_read : out std_logic; -- read av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata av_writedata : out std_logic_vector(31 downto 0); -- writedata av_begintransfer : out std_logic; -- begintransfer av_beginbursttransfer : out std_logic; -- beginbursttransfer av_burstcount : out std_logic_vector(0 downto 0); -- burstcount av_byteenable : out std_logic_vector(3 downto 0); -- byteenable av_readdatavalid : in std_logic := 'X'; -- readdatavalid av_waitrequest : in std_logic := 'X'; -- waitrequest av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable av_lock : out std_logic; -- lock av_chipselect : out std_logic; -- chipselect av_clken : out std_logic; -- clken uav_clken : in std_logic := 'X'; -- clken av_debugaccess : out std_logic; -- debugaccess av_outputenable : out std_logic; -- outputenable uav_response : out std_logic_vector(1 downto 0); -- response av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest uav_writeresponsevalid : out std_logic; -- writeresponsevalid av_writeresponserequest : out std_logic; -- writeresponserequest av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid ); end component niosii_system_altpll_0_pll_slave_translator; component niosii_system_timer_0_s1_translator is generic ( AV_ADDRESS_W : integer := 30; AV_DATA_W : integer := 32; UAV_DATA_W : integer := 32; AV_BURSTCOUNT_W : integer := 4; AV_BYTEENABLE_W : integer := 4; UAV_BYTEENABLE_W : integer := 4; UAV_ADDRESS_W : integer := 32; UAV_BURSTCOUNT_W : integer := 4; AV_READLATENCY : integer := 0; USE_READDATAVALID : integer := 1; USE_WAITREQUEST : integer := 1; USE_UAV_CLKEN : integer := 0; USE_READRESPONSE : integer := 0; USE_WRITERESPONSE : integer := 0; AV_SYMBOLS_PER_WORD : integer := 4; AV_ADDRESS_SYMBOLS : integer := 0; AV_BURSTCOUNT_SYMBOLS : integer := 0; AV_CONSTANT_BURST_BEHAVIOR : integer := 0; UAV_CONSTANT_BURST_BEHAVIOR : integer := 0; AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0; CHIPSELECT_THROUGH_READLATENCY : integer := 0; AV_READ_WAIT_CYCLES : integer := 0; AV_WRITE_WAIT_CYCLES : integer := 0; AV_SETUP_WAIT_CYCLES : integer := 0; AV_DATA_HOLD_CYCLES : integer := 0 ); port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount uav_read : in std_logic := 'X'; -- read uav_write : in std_logic := 'X'; -- write uav_waitrequest : out std_logic; -- waitrequest uav_readdatavalid : out std_logic; -- readdatavalid uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable uav_readdata : out std_logic_vector(31 downto 0); -- readdata uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata uav_lock : in std_logic := 'X'; -- lock uav_debugaccess : in std_logic := 'X'; -- debugaccess av_address : out std_logic_vector(2 downto 0); -- address av_write : out std_logic; -- write av_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata av_writedata : out std_logic_vector(15 downto 0); -- writedata av_chipselect : out std_logic; -- chipselect av_read : out std_logic; -- read av_begintransfer : out std_logic; -- begintransfer av_beginbursttransfer : out std_logic; -- beginbursttransfer av_burstcount : out std_logic_vector(0 downto 0); -- burstcount av_byteenable : out std_logic_vector(0 downto 0); -- byteenable av_readdatavalid : in std_logic := 'X'; -- readdatavalid av_waitrequest : in std_logic := 'X'; -- waitrequest av_writebyteenable : out std_logic_vector(0 downto 0); -- writebyteenable av_lock : out std_logic; -- lock av_clken : out std_logic; -- clken uav_clken : in std_logic := 'X'; -- clken av_debugaccess : out std_logic; -- debugaccess av_outputenable : out std_logic; -- outputenable uav_response : out std_logic_vector(1 downto 0); -- response av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest uav_writeresponsevalid : out std_logic; -- writeresponsevalid av_writeresponserequest : out std_logic; -- writeresponserequest av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid ); end component niosii_system_timer_0_s1_translator; component niosii_system_usb_0_avalon_usb_slave_translator is generic ( AV_ADDRESS_W : integer := 30; AV_DATA_W : integer := 32; UAV_DATA_W : integer := 32; AV_BURSTCOUNT_W : integer := 4; AV_BYTEENABLE_W : integer := 4; UAV_BYTEENABLE_W : integer := 4; UAV_ADDRESS_W : integer := 32; UAV_BURSTCOUNT_W : integer := 4; AV_READLATENCY : integer := 0; USE_READDATAVALID : integer := 1; USE_WAITREQUEST : integer := 1; USE_UAV_CLKEN : integer := 0; USE_READRESPONSE : integer := 0; USE_WRITERESPONSE : integer := 0; AV_SYMBOLS_PER_WORD : integer := 4; AV_ADDRESS_SYMBOLS : integer := 0; AV_BURSTCOUNT_SYMBOLS : integer := 0; AV_CONSTANT_BURST_BEHAVIOR : integer := 0; UAV_CONSTANT_BURST_BEHAVIOR : integer := 0; AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0; CHIPSELECT_THROUGH_READLATENCY : integer := 0; AV_READ_WAIT_CYCLES : integer := 0; AV_WRITE_WAIT_CYCLES : integer := 0; AV_SETUP_WAIT_CYCLES : integer := 0; AV_DATA_HOLD_CYCLES : integer := 0 ); port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount uav_read : in std_logic := 'X'; -- read uav_write : in std_logic := 'X'; -- write uav_waitrequest : out std_logic; -- waitrequest uav_readdatavalid : out std_logic; -- readdatavalid uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable uav_readdata : out std_logic_vector(31 downto 0); -- readdata uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata uav_lock : in std_logic := 'X'; -- lock uav_debugaccess : in std_logic := 'X'; -- debugaccess av_address : out std_logic_vector(1 downto 0); -- address av_write : out std_logic; -- write av_read : out std_logic; -- read av_readdata : in std_logic_vector(15 downto 0) := (others => 'X'); -- readdata av_writedata : out std_logic_vector(15 downto 0); -- writedata av_chipselect : out std_logic; -- chipselect av_begintransfer : out std_logic; -- begintransfer av_beginbursttransfer : out std_logic; -- beginbursttransfer av_burstcount : out std_logic_vector(0 downto 0); -- burstcount av_byteenable : out std_logic_vector(0 downto 0); -- byteenable av_readdatavalid : in std_logic := 'X'; -- readdatavalid av_waitrequest : in std_logic := 'X'; -- waitrequest av_writebyteenable : out std_logic_vector(0 downto 0); -- writebyteenable av_lock : out std_logic; -- lock av_clken : out std_logic; -- clken uav_clken : in std_logic := 'X'; -- clken av_debugaccess : out std_logic; -- debugaccess av_outputenable : out std_logic; -- outputenable uav_response : out std_logic_vector(1 downto 0); -- response av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest uav_writeresponsevalid : out std_logic; -- writeresponsevalid av_writeresponserequest : out std_logic; -- writeresponserequest av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid ); end component niosii_system_usb_0_avalon_usb_slave_translator; component niosii_system_rs232_0_avalon_rs232_slave_translator is generic ( AV_ADDRESS_W : integer := 30; AV_DATA_W : integer := 32; UAV_DATA_W : integer := 32; AV_BURSTCOUNT_W : integer := 4; AV_BYTEENABLE_W : integer := 4; UAV_BYTEENABLE_W : integer := 4; UAV_ADDRESS_W : integer := 32; UAV_BURSTCOUNT_W : integer := 4; AV_READLATENCY : integer := 0; USE_READDATAVALID : integer := 1; USE_WAITREQUEST : integer := 1; USE_UAV_CLKEN : integer := 0; USE_READRESPONSE : integer := 0; USE_WRITERESPONSE : integer := 0; AV_SYMBOLS_PER_WORD : integer := 4; AV_ADDRESS_SYMBOLS : integer := 0; AV_BURSTCOUNT_SYMBOLS : integer := 0; AV_CONSTANT_BURST_BEHAVIOR : integer := 0; UAV_CONSTANT_BURST_BEHAVIOR : integer := 0; AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0; CHIPSELECT_THROUGH_READLATENCY : integer := 0; AV_READ_WAIT_CYCLES : integer := 0; AV_WRITE_WAIT_CYCLES : integer := 0; AV_SETUP_WAIT_CYCLES : integer := 0; AV_DATA_HOLD_CYCLES : integer := 0 ); port ( clk : in std_logic := 'X'; -- clk reset : in std_logic := 'X'; -- reset uav_address : in std_logic_vector(24 downto 0) := (others => 'X'); -- address uav_burstcount : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount uav_read : in std_logic := 'X'; -- read uav_write : in std_logic := 'X'; -- write uav_waitrequest : out std_logic; -- waitrequest uav_readdatavalid : out std_logic; -- readdatavalid uav_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable uav_readdata : out std_logic_vector(31 downto 0); -- readdata uav_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata uav_lock : in std_logic := 'X'; -- lock uav_debugaccess : in std_logic := 'X'; -- debugaccess av_address : out std_logic_vector(0 downto 0); -- address av_write : out std_logic; -- write av_read : out std_logic; -- read av_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata av_writedata : out std_logic_vector(31 downto 0); -- writedata av_byteenable : out std_logic_vector(3 downto 0); -- byteenable av_chipselect : out std_logic; -- chipselect av_begintransfer : out std_logic; -- begintransfer av_beginbursttransfer : out std_logic; -- beginbursttransfer av_burstcount : out std_logic_vector(0 downto 0); -- burstcount av_readdatavalid : in std_logic := 'X'; -- readdatavalid av_waitrequest : in std_logic := 'X'; -- waitrequest av_writebyteenable : out std_logic_vector(3 downto 0); -- writebyteenable av_lock : out std_logic; -- lock av_clken : out std_logic; -- clken uav_clken : in std_logic := 'X'; -- clken av_debugaccess : out std_logic; -- debugaccess av_outputenable : out std_logic; -- outputenable uav_response : out std_logic_vector(1 downto 0); -- response av_response : in std_logic_vector(1 downto 0) := (others => 'X'); -- response uav_writeresponserequest : in std_logic := 'X'; -- writeresponserequest uav_writeresponsevalid : out std_logic; -- writeresponsevalid av_writeresponserequest : out std_logic; -- writeresponserequest av_writeresponsevalid : in std_logic := 'X' -- writeresponsevalid ); end component niosii_system_rs232_0_avalon_rs232_slave_translator; component niosii_system_rst_controller is generic ( NUM_RESET_INPUTS : integer := 6; OUTPUT_RESET_SYNC_EDGES : string := "deassert"; SYNC_DEPTH : integer := 2; RESET_REQUEST_PRESENT : integer := 0 ); port ( reset_in0 : in std_logic := 'X'; -- reset reset_in1 : in std_logic := 'X'; -- reset clk : in std_logic := 'X'; -- clk reset_out : out std_logic; -- reset reset_req : out std_logic; -- reset_req reset_in2 : in std_logic := 'X'; -- reset reset_in3 : in std_logic := 'X'; -- reset reset_in4 : in std_logic := 'X'; -- reset reset_in5 : in std_logic := 'X'; -- reset reset_in6 : in std_logic := 'X'; -- reset reset_in7 : in std_logic := 'X'; -- reset reset_in8 : in std_logic := 'X'; -- reset reset_in9 : in std_logic := 'X'; -- reset reset_in10 : in std_logic := 'X'; -- reset reset_in11 : in std_logic := 'X'; -- reset reset_in12 : in std_logic := 'X'; -- reset reset_in13 : in std_logic := 'X'; -- reset reset_in14 : in std_logic := 'X'; -- reset reset_in15 : in std_logic := 'X' -- reset ); end component niosii_system_rst_controller; component niosii_system_rst_controller_001 is generic ( NUM_RESET_INPUTS : integer := 6; OUTPUT_RESET_SYNC_EDGES : string := "deassert"; SYNC_DEPTH : integer := 2; RESET_REQUEST_PRESENT : integer := 0 ); port ( reset_in0 : in std_logic := 'X'; -- reset reset_in1 : in std_logic := 'X'; -- reset clk : in std_logic := 'X'; -- clk reset_out : out std_logic; -- reset reset_req : out std_logic; -- reset_req reset_in2 : in std_logic := 'X'; -- reset reset_in3 : in std_logic := 'X'; -- reset reset_in4 : in std_logic := 'X'; -- reset reset_in5 : in std_logic := 'X'; -- reset reset_in6 : in std_logic := 'X'; -- reset reset_in7 : in std_logic := 'X'; -- reset reset_in8 : in std_logic := 'X'; -- reset reset_in9 : in std_logic := 'X'; -- reset reset_in10 : in std_logic := 'X'; -- reset reset_in11 : in std_logic := 'X'; -- reset reset_in12 : in std_logic := 'X'; -- reset reset_in13 : in std_logic := 'X'; -- reset reset_in14 : in std_logic := 'X'; -- reset reset_in15 : in std_logic := 'X' -- reset ); end component niosii_system_rst_controller_001; signal altpll_0_c1_clk : std_logic; -- altpll_0:c1 -> [addr_router:clk, addr_router_001:clk, burst_adapter:clk, burst_adapter_001:clk, burst_adapter_002:clk, cmd_xbar_demux:clk, cmd_xbar_demux_001:clk, cmd_xbar_mux:clk, cmd_xbar_mux_001:clk, cmd_xbar_mux_002:clk, cmd_xbar_mux_003:clk, cmd_xbar_mux_004:clk, crosser:in_clk, crosser_001:out_clk, generic_tristate_controller_0:clk_clk, generic_tristate_controller_0_uas_translator:clk, generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:clk, generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo:clk, generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, green_leds:clk, green_leds_s1_translator:clk, green_leds_s1_translator_avalon_universal_slave_0_agent:clk, green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, id_router:clk, id_router_001:clk, id_router_002:clk, id_router_003:clk, id_router_004:clk, id_router_005:clk, id_router_006:clk, id_router_007:clk, id_router_008:clk, id_router_010:clk, id_router_011:clk, id_router_012:clk, irq_mapper:clk, jtag_uart_0:clk, jtag_uart_0_avalon_jtag_slave_translator:clk, jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:clk, jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, nios2_qsys_0:clk, nios2_qsys_0_data_master_translator:clk, nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:clk, nios2_qsys_0_instruction_master_translator:clk, nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:clk, nios2_qsys_0_jtag_debug_module_translator:clk, nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:clk, nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, onchip_memory2_0:clk, onchip_memory2_0_s1_translator:clk, onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:clk, onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, rs232_0:clk, rs232_0_avalon_rs232_slave_translator:clk, rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:clk, rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, rsp_xbar_demux:clk, rsp_xbar_demux_001:clk, rsp_xbar_demux_002:clk, rsp_xbar_demux_003:clk, rsp_xbar_demux_004:clk, rsp_xbar_demux_005:clk, rsp_xbar_demux_006:clk, rsp_xbar_demux_007:clk, rsp_xbar_demux_008:clk, rsp_xbar_demux_010:clk, rsp_xbar_demux_011:clk, rsp_xbar_demux_012:clk, rsp_xbar_mux:clk, rsp_xbar_mux_001:clk, rst_controller:clk, sdram_0:clk, sdram_0_s1_translator:clk, sdram_0_s1_translator_avalon_universal_slave_0_agent:clk, sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:clk, sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, sram_0:clk, sram_0_avalon_sram_slave_translator:clk, sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:clk, sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:clk, sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, switches:clk, switches_s1_translator:clk, switches_s1_translator_avalon_universal_slave_0_agent:clk, switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, sysid_qsys_0:clock, sysid_qsys_0_control_slave_translator:clk, sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:clk, sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, timer_0:clk, timer_0_s1_translator:clk, timer_0_s1_translator_avalon_universal_slave_0_agent:clk, timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, tristate_conduit_bridge_0:clk, tristate_conduit_pin_sharer_0:clk_clk, usb_0:clk, usb_0_avalon_usb_slave_translator:clk, usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:clk, usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:clk, width_adapter:clk, width_adapter_001:clk, width_adapter_002:clk, width_adapter_003:clk, width_adapter_004:clk, width_adapter_005:clk] signal generic_tristate_controller_0_tcm_chipselect_n_out : std_logic; -- generic_tristate_controller_0:tcm_chipselect_n_out -> tristate_conduit_pin_sharer_0:tcs0_chipselect_n_out signal generic_tristate_controller_0_tcm_grant : std_logic; -- tristate_conduit_pin_sharer_0:tcs0_grant -> generic_tristate_controller_0:tcm_grant signal generic_tristate_controller_0_tcm_data_outen : std_logic; -- generic_tristate_controller_0:tcm_data_outen -> tristate_conduit_pin_sharer_0:tcs0_data_outen signal generic_tristate_controller_0_tcm_byteenable_out : std_logic; -- generic_tristate_controller_0:tcm_byteenable_out -> tristate_conduit_pin_sharer_0:tcs0_byteenable_out signal generic_tristate_controller_0_tcm_request : std_logic; -- generic_tristate_controller_0:tcm_request -> tristate_conduit_pin_sharer_0:tcs0_request signal generic_tristate_controller_0_tcm_begintransfer_out : std_logic; -- generic_tristate_controller_0:tcm_begintransfer_out -> tristate_conduit_pin_sharer_0:tcs0_begintransfer_out signal generic_tristate_controller_0_tcm_data_out : std_logic_vector(7 downto 0); -- generic_tristate_controller_0:tcm_data_out -> tristate_conduit_pin_sharer_0:tcs0_data_out signal generic_tristate_controller_0_tcm_write_n_out : std_logic; -- generic_tristate_controller_0:tcm_write_n_out -> tristate_conduit_pin_sharer_0:tcs0_write_n_out signal generic_tristate_controller_0_tcm_address_out : std_logic_vector(21 downto 0); -- generic_tristate_controller_0:tcm_address_out -> tristate_conduit_pin_sharer_0:tcs0_address_out signal generic_tristate_controller_0_tcm_data_in : std_logic_vector(7 downto 0); -- tristate_conduit_pin_sharer_0:tcs0_data_in -> generic_tristate_controller_0:tcm_data_in signal generic_tristate_controller_0_tcm_read_n_out : std_logic; -- generic_tristate_controller_0:tcm_read_n_out -> tristate_conduit_pin_sharer_0:tcs0_read_n_out signal tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_read_n_out_out : std_logic_vector(0 downto 0); -- tristate_conduit_pin_sharer_0:generic_tristate_controller_0_tcm_read_n_out -> tristate_conduit_bridge_0:tcs_generic_tristate_controller_0_tcm_read_n_out signal tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_byteenable_out_out : std_logic_vector(0 downto 0); -- tristate_conduit_pin_sharer_0:generic_tristate_controller_0_tcm_byteenable_out -> tristate_conduit_bridge_0:tcs_generic_tristate_controller_0_tcm_byteenable_out signal tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_begintransfer_out_out : std_logic_vector(0 downto 0); -- tristate_conduit_pin_sharer_0:generic_tristate_controller_0_tcm_begintransfer_out -> tristate_conduit_bridge_0:tcs_generic_tristate_controller_0_tcm_begintransfer_out signal tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_write_n_out_out : std_logic_vector(0 downto 0); -- tristate_conduit_pin_sharer_0:generic_tristate_controller_0_tcm_write_n_out -> tristate_conduit_bridge_0:tcs_generic_tristate_controller_0_tcm_write_n_out signal tristate_conduit_pin_sharer_0_tcm_grant : std_logic; -- tristate_conduit_bridge_0:grant -> tristate_conduit_pin_sharer_0:grant signal tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_data_out_in : std_logic_vector(7 downto 0); -- tristate_conduit_bridge_0:tcs_generic_tristate_controller_0_tcm_data_in -> tristate_conduit_pin_sharer_0:generic_tristate_controller_0_tcm_data_in signal tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_data_out_out : std_logic_vector(7 downto 0); -- tristate_conduit_pin_sharer_0:generic_tristate_controller_0_tcm_data_out -> tristate_conduit_bridge_0:tcs_generic_tristate_controller_0_tcm_data_out signal tristate_conduit_pin_sharer_0_tcm_request : std_logic; -- tristate_conduit_pin_sharer_0:request -> tristate_conduit_bridge_0:request signal tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_chipselect_n_out_out : std_logic_vector(0 downto 0); -- tristate_conduit_pin_sharer_0:generic_tristate_controller_0_tcm_chipselect_n_out -> tristate_conduit_bridge_0:tcs_generic_tristate_controller_0_tcm_chipselect_n_out signal tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_data_out_outen : std_logic; -- tristate_conduit_pin_sharer_0:generic_tristate_controller_0_tcm_data_outen -> tristate_conduit_bridge_0:tcs_generic_tristate_controller_0_tcm_data_outen signal tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_address_out_out : std_logic_vector(21 downto 0); -- tristate_conduit_pin_sharer_0:generic_tristate_controller_0_tcm_address_out -> tristate_conduit_bridge_0:tcs_generic_tristate_controller_0_tcm_address_out signal nios2_qsys_0_instruction_master_waitrequest : std_logic; -- nios2_qsys_0_instruction_master_translator:av_waitrequest -> nios2_qsys_0:i_waitrequest signal nios2_qsys_0_instruction_master_address : std_logic_vector(24 downto 0); -- nios2_qsys_0:i_address -> nios2_qsys_0_instruction_master_translator:av_address signal nios2_qsys_0_instruction_master_read : std_logic; -- nios2_qsys_0:i_read -> nios2_qsys_0_instruction_master_translator:av_read signal nios2_qsys_0_instruction_master_readdata : std_logic_vector(31 downto 0); -- nios2_qsys_0_instruction_master_translator:av_readdata -> nios2_qsys_0:i_readdata signal nios2_qsys_0_data_master_waitrequest : std_logic; -- nios2_qsys_0_data_master_translator:av_waitrequest -> nios2_qsys_0:d_waitrequest signal nios2_qsys_0_data_master_writedata : std_logic_vector(31 downto 0); -- nios2_qsys_0:d_writedata -> nios2_qsys_0_data_master_translator:av_writedata signal nios2_qsys_0_data_master_address : std_logic_vector(24 downto 0); -- nios2_qsys_0:d_address -> nios2_qsys_0_data_master_translator:av_address signal nios2_qsys_0_data_master_write : std_logic; -- nios2_qsys_0:d_write -> nios2_qsys_0_data_master_translator:av_write signal nios2_qsys_0_data_master_read : std_logic; -- nios2_qsys_0:d_read -> nios2_qsys_0_data_master_translator:av_read signal nios2_qsys_0_data_master_readdata : std_logic_vector(31 downto 0); -- nios2_qsys_0_data_master_translator:av_readdata -> nios2_qsys_0:d_readdata signal nios2_qsys_0_data_master_debugaccess : std_logic; -- nios2_qsys_0:jtag_debug_module_debugaccess_to_roms -> nios2_qsys_0_data_master_translator:av_debugaccess signal nios2_qsys_0_data_master_byteenable : std_logic_vector(3 downto 0); -- nios2_qsys_0:d_byteenable -> nios2_qsys_0_data_master_translator:av_byteenable signal nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_waitrequest : std_logic; -- nios2_qsys_0:jtag_debug_module_waitrequest -> nios2_qsys_0_jtag_debug_module_translator:av_waitrequest signal nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- nios2_qsys_0_jtag_debug_module_translator:av_writedata -> nios2_qsys_0:jtag_debug_module_writedata signal nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_address : std_logic_vector(8 downto 0); -- nios2_qsys_0_jtag_debug_module_translator:av_address -> nios2_qsys_0:jtag_debug_module_address signal nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_write : std_logic; -- nios2_qsys_0_jtag_debug_module_translator:av_write -> nios2_qsys_0:jtag_debug_module_write signal nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_read : std_logic; -- nios2_qsys_0_jtag_debug_module_translator:av_read -> nios2_qsys_0:jtag_debug_module_read signal nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- nios2_qsys_0:jtag_debug_module_readdata -> nios2_qsys_0_jtag_debug_module_translator:av_readdata signal nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess : std_logic; -- nios2_qsys_0_jtag_debug_module_translator:av_debugaccess -> nios2_qsys_0:jtag_debug_module_debugaccess signal nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_byteenable : std_logic_vector(3 downto 0); -- nios2_qsys_0_jtag_debug_module_translator:av_byteenable -> nios2_qsys_0:jtag_debug_module_byteenable signal sdram_0_s1_translator_avalon_anti_slave_0_waitrequest : std_logic; -- sdram_0:za_waitrequest -> sdram_0_s1_translator:av_waitrequest signal sdram_0_s1_translator_avalon_anti_slave_0_writedata : std_logic_vector(15 downto 0); -- sdram_0_s1_translator:av_writedata -> sdram_0:az_data signal sdram_0_s1_translator_avalon_anti_slave_0_address : std_logic_vector(21 downto 0); -- sdram_0_s1_translator:av_address -> sdram_0:az_addr signal sdram_0_s1_translator_avalon_anti_slave_0_chipselect : std_logic; -- sdram_0_s1_translator:av_chipselect -> sdram_0:az_cs signal sdram_0_s1_translator_avalon_anti_slave_0_write : std_logic; -- sdram_0_s1_translator:av_write -> sdram_0_s1_translator_avalon_anti_slave_0_write:in signal sdram_0_s1_translator_avalon_anti_slave_0_read : std_logic; -- sdram_0_s1_translator:av_read -> sdram_0_s1_translator_avalon_anti_slave_0_read:in signal sdram_0_s1_translator_avalon_anti_slave_0_readdata : std_logic_vector(15 downto 0); -- sdram_0:za_data -> sdram_0_s1_translator:av_readdata signal sdram_0_s1_translator_avalon_anti_slave_0_readdatavalid : std_logic; -- sdram_0:za_valid -> sdram_0_s1_translator:av_readdatavalid signal sdram_0_s1_translator_avalon_anti_slave_0_byteenable : std_logic_vector(1 downto 0); -- sdram_0_s1_translator:av_byteenable -> sdram_0_s1_translator_avalon_anti_slave_0_byteenable:in signal onchip_memory2_0_s1_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- onchip_memory2_0_s1_translator:av_writedata -> onchip_memory2_0:writedata signal onchip_memory2_0_s1_translator_avalon_anti_slave_0_address : std_logic_vector(11 downto 0); -- onchip_memory2_0_s1_translator:av_address -> onchip_memory2_0:address signal onchip_memory2_0_s1_translator_avalon_anti_slave_0_chipselect : std_logic; -- onchip_memory2_0_s1_translator:av_chipselect -> onchip_memory2_0:chipselect signal onchip_memory2_0_s1_translator_avalon_anti_slave_0_clken : std_logic; -- onchip_memory2_0_s1_translator:av_clken -> onchip_memory2_0:clken signal onchip_memory2_0_s1_translator_avalon_anti_slave_0_write : std_logic; -- onchip_memory2_0_s1_translator:av_write -> onchip_memory2_0:write signal onchip_memory2_0_s1_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- onchip_memory2_0:readdata -> onchip_memory2_0_s1_translator:av_readdata signal onchip_memory2_0_s1_translator_avalon_anti_slave_0_byteenable : std_logic_vector(3 downto 0); -- onchip_memory2_0_s1_translator:av_byteenable -> onchip_memory2_0:byteenable signal sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_writedata : std_logic_vector(15 downto 0); -- sram_0_avalon_sram_slave_translator:av_writedata -> sram_0:writedata signal sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_address : std_logic_vector(17 downto 0); -- sram_0_avalon_sram_slave_translator:av_address -> sram_0:address signal sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_write : std_logic; -- sram_0_avalon_sram_slave_translator:av_write -> sram_0:write signal sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_read : std_logic; -- sram_0_avalon_sram_slave_translator:av_read -> sram_0:read signal sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_readdata : std_logic_vector(15 downto 0); -- sram_0:readdata -> sram_0_avalon_sram_slave_translator:av_readdata signal sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_readdatavalid : std_logic; -- sram_0:readdatavalid -> sram_0_avalon_sram_slave_translator:av_readdatavalid signal sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_byteenable : std_logic_vector(1 downto 0); -- sram_0_avalon_sram_slave_translator:av_byteenable -> sram_0:byteenable signal generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_waitrequest : std_logic; -- generic_tristate_controller_0:uas_waitrequest -> generic_tristate_controller_0_uas_translator:av_waitrequest signal generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_burstcount : std_logic_vector(0 downto 0); -- generic_tristate_controller_0_uas_translator:av_burstcount -> generic_tristate_controller_0:uas_burstcount signal generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_writedata : std_logic_vector(7 downto 0); -- generic_tristate_controller_0_uas_translator:av_writedata -> generic_tristate_controller_0:uas_writedata signal generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_address : std_logic_vector(21 downto 0); -- generic_tristate_controller_0_uas_translator:av_address -> generic_tristate_controller_0:uas_address signal generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_lock : std_logic; -- generic_tristate_controller_0_uas_translator:av_lock -> generic_tristate_controller_0:uas_lock signal generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_write : std_logic; -- generic_tristate_controller_0_uas_translator:av_write -> generic_tristate_controller_0:uas_write signal generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_read : std_logic; -- generic_tristate_controller_0_uas_translator:av_read -> generic_tristate_controller_0:uas_read signal generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_readdata : std_logic_vector(7 downto 0); -- generic_tristate_controller_0:uas_readdata -> generic_tristate_controller_0_uas_translator:av_readdata signal generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_debugaccess : std_logic; -- generic_tristate_controller_0_uas_translator:av_debugaccess -> generic_tristate_controller_0:uas_debugaccess signal generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_readdatavalid : std_logic; -- generic_tristate_controller_0:uas_readdatavalid -> generic_tristate_controller_0_uas_translator:av_readdatavalid signal generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_byteenable : std_logic_vector(0 downto 0); -- generic_tristate_controller_0_uas_translator:av_byteenable -> generic_tristate_controller_0:uas_byteenable signal jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest : std_logic; -- jtag_uart_0:av_waitrequest -> jtag_uart_0_avalon_jtag_slave_translator:av_waitrequest signal jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- jtag_uart_0_avalon_jtag_slave_translator:av_writedata -> jtag_uart_0:av_writedata signal jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_address : std_logic_vector(0 downto 0); -- jtag_uart_0_avalon_jtag_slave_translator:av_address -> jtag_uart_0:av_address signal jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator:av_chipselect -> jtag_uart_0:av_chipselect signal jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator:av_write -> jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write:in signal jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator:av_read -> jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read:in signal jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- jtag_uart_0:av_readdata -> jtag_uart_0_avalon_jtag_slave_translator:av_readdata signal sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_address : std_logic_vector(0 downto 0); -- sysid_qsys_0_control_slave_translator:av_address -> sysid_qsys_0:address signal sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- sysid_qsys_0:readdata -> sysid_qsys_0_control_slave_translator:av_readdata signal green_leds_s1_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- green_leds_s1_translator:av_writedata -> green_leds:writedata signal green_leds_s1_translator_avalon_anti_slave_0_address : std_logic_vector(1 downto 0); -- green_leds_s1_translator:av_address -> green_leds:address signal green_leds_s1_translator_avalon_anti_slave_0_chipselect : std_logic; -- green_leds_s1_translator:av_chipselect -> green_leds:chipselect signal green_leds_s1_translator_avalon_anti_slave_0_write : std_logic; -- green_leds_s1_translator:av_write -> green_leds_s1_translator_avalon_anti_slave_0_write:in signal green_leds_s1_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- green_leds:readdata -> green_leds_s1_translator:av_readdata signal switches_s1_translator_avalon_anti_slave_0_address : std_logic_vector(1 downto 0); -- switches_s1_translator:av_address -> switches:address signal switches_s1_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- switches:readdata -> switches_s1_translator:av_readdata signal altpll_0_pll_slave_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- altpll_0_pll_slave_translator:av_writedata -> altpll_0:writedata signal altpll_0_pll_slave_translator_avalon_anti_slave_0_address : std_logic_vector(1 downto 0); -- altpll_0_pll_slave_translator:av_address -> altpll_0:address signal altpll_0_pll_slave_translator_avalon_anti_slave_0_write : std_logic; -- altpll_0_pll_slave_translator:av_write -> altpll_0:write signal altpll_0_pll_slave_translator_avalon_anti_slave_0_read : std_logic; -- altpll_0_pll_slave_translator:av_read -> altpll_0:read signal altpll_0_pll_slave_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- altpll_0:readdata -> altpll_0_pll_slave_translator:av_readdata signal timer_0_s1_translator_avalon_anti_slave_0_writedata : std_logic_vector(15 downto 0); -- timer_0_s1_translator:av_writedata -> timer_0:writedata signal timer_0_s1_translator_avalon_anti_slave_0_address : std_logic_vector(2 downto 0); -- timer_0_s1_translator:av_address -> timer_0:address signal timer_0_s1_translator_avalon_anti_slave_0_chipselect : std_logic; -- timer_0_s1_translator:av_chipselect -> timer_0:chipselect signal timer_0_s1_translator_avalon_anti_slave_0_write : std_logic; -- timer_0_s1_translator:av_write -> timer_0_s1_translator_avalon_anti_slave_0_write:in signal timer_0_s1_translator_avalon_anti_slave_0_readdata : std_logic_vector(15 downto 0); -- timer_0:readdata -> timer_0_s1_translator:av_readdata signal usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_writedata : std_logic_vector(15 downto 0); -- usb_0_avalon_usb_slave_translator:av_writedata -> usb_0:writedata signal usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_address : std_logic_vector(1 downto 0); -- usb_0_avalon_usb_slave_translator:av_address -> usb_0:address signal usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_chipselect : std_logic; -- usb_0_avalon_usb_slave_translator:av_chipselect -> usb_0:chipselect signal usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_write : std_logic; -- usb_0_avalon_usb_slave_translator:av_write -> usb_0:write signal usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_read : std_logic; -- usb_0_avalon_usb_slave_translator:av_read -> usb_0:read signal usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_readdata : std_logic_vector(15 downto 0); -- usb_0:readdata -> usb_0_avalon_usb_slave_translator:av_readdata signal rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_writedata : std_logic_vector(31 downto 0); -- rs232_0_avalon_rs232_slave_translator:av_writedata -> rs232_0:writedata signal rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_address : std_logic_vector(0 downto 0); -- rs232_0_avalon_rs232_slave_translator:av_address -> rs232_0:address signal rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_chipselect : std_logic; -- rs232_0_avalon_rs232_slave_translator:av_chipselect -> rs232_0:chipselect signal rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_write : std_logic; -- rs232_0_avalon_rs232_slave_translator:av_write -> rs232_0:write signal rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_read : std_logic; -- rs232_0_avalon_rs232_slave_translator:av_read -> rs232_0:read signal rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_readdata : std_logic_vector(31 downto 0); -- rs232_0:readdata -> rs232_0_avalon_rs232_slave_translator:av_readdata signal rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_byteenable : std_logic_vector(3 downto 0); -- rs232_0_avalon_rs232_slave_translator:av_byteenable -> rs232_0:byteenable signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_waitrequest : std_logic; -- nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_waitrequest -> nios2_qsys_0_instruction_master_translator:uav_waitrequest signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_burstcount : std_logic_vector(2 downto 0); -- nios2_qsys_0_instruction_master_translator:uav_burstcount -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_burstcount signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_writedata : std_logic_vector(31 downto 0); -- nios2_qsys_0_instruction_master_translator:uav_writedata -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_writedata signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_address : std_logic_vector(24 downto 0); -- nios2_qsys_0_instruction_master_translator:uav_address -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_address signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_lock : std_logic; -- nios2_qsys_0_instruction_master_translator:uav_lock -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_lock signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_write : std_logic; -- nios2_qsys_0_instruction_master_translator:uav_write -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_write signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_read : std_logic; -- nios2_qsys_0_instruction_master_translator:uav_read -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_read signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdata : std_logic_vector(31 downto 0); -- nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_readdata -> nios2_qsys_0_instruction_master_translator:uav_readdata signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_debugaccess : std_logic; -- nios2_qsys_0_instruction_master_translator:uav_debugaccess -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_debugaccess signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_byteenable : std_logic_vector(3 downto 0); -- nios2_qsys_0_instruction_master_translator:uav_byteenable -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_byteenable signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdatavalid : std_logic; -- nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> nios2_qsys_0_instruction_master_translator:uav_readdatavalid signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_waitrequest : std_logic; -- nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_waitrequest -> nios2_qsys_0_data_master_translator:uav_waitrequest signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_burstcount : std_logic_vector(2 downto 0); -- nios2_qsys_0_data_master_translator:uav_burstcount -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_burstcount signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_writedata : std_logic_vector(31 downto 0); -- nios2_qsys_0_data_master_translator:uav_writedata -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_writedata signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_address : std_logic_vector(24 downto 0); -- nios2_qsys_0_data_master_translator:uav_address -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_address signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_lock : std_logic; -- nios2_qsys_0_data_master_translator:uav_lock -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_lock signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_write : std_logic; -- nios2_qsys_0_data_master_translator:uav_write -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_write signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_read : std_logic; -- nios2_qsys_0_data_master_translator:uav_read -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_read signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdata : std_logic_vector(31 downto 0); -- nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_readdata -> nios2_qsys_0_data_master_translator:uav_readdata signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_debugaccess : std_logic; -- nios2_qsys_0_data_master_translator:uav_debugaccess -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_debugaccess signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_byteenable : std_logic_vector(3 downto 0); -- nios2_qsys_0_data_master_translator:uav_byteenable -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_byteenable signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdatavalid : std_logic; -- nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:av_readdatavalid -> nios2_qsys_0_data_master_translator:uav_readdatavalid signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- nios2_qsys_0_jtag_debug_module_translator:uav_waitrequest -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_waitrequest signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_burstcount -> nios2_qsys_0_jtag_debug_module_translator:uav_burstcount signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_writedata -> nios2_qsys_0_jtag_debug_module_translator:uav_writedata signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_address -> nios2_qsys_0_jtag_debug_module_translator:uav_address signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_write -> nios2_qsys_0_jtag_debug_module_translator:uav_write signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_lock -> nios2_qsys_0_jtag_debug_module_translator:uav_lock signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_read -> nios2_qsys_0_jtag_debug_module_translator:uav_read signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- nios2_qsys_0_jtag_debug_module_translator:uav_readdata -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdata signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- nios2_qsys_0_jtag_debug_module_translator:uav_readdatavalid -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_readdatavalid signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_debugaccess -> nios2_qsys_0_jtag_debug_module_translator:uav_debugaccess signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:m0_byteenable -> nios2_qsys_0_jtag_debug_module_translator:uav_byteenable signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_valid -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(100 downto 0); -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_data -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_source_ready signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_valid signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(100 downto 0); -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_data signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rf_sink_ready -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(33 downto 0); -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready signal sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- sdram_0_s1_translator:uav_waitrequest -> sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest signal sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(1 downto 0); -- sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> sdram_0_s1_translator:uav_burstcount signal sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(15 downto 0); -- sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> sdram_0_s1_translator:uav_writedata signal sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_address -> sdram_0_s1_translator:uav_address signal sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_write -> sdram_0_s1_translator:uav_write signal sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_lock -> sdram_0_s1_translator:uav_lock signal sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_read -> sdram_0_s1_translator:uav_read signal sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(15 downto 0); -- sdram_0_s1_translator:uav_readdata -> sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_readdata signal sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- sdram_0_s1_translator:uav_readdatavalid -> sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid signal sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sdram_0_s1_translator:uav_debugaccess signal sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(1 downto 0); -- sdram_0_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> sdram_0_s1_translator:uav_byteenable signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(82 downto 0); -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_source_ready signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(82 downto 0); -- sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_data signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:in_valid signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(17 downto 0); -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:in_data signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:in_ready -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:out_valid -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data : std_logic_vector(17 downto 0); -- sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:out_data -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:out_ready signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- onchip_memory2_0_s1_translator:uav_waitrequest -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> onchip_memory2_0_s1_translator:uav_burstcount signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> onchip_memory2_0_s1_translator:uav_writedata signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_address -> onchip_memory2_0_s1_translator:uav_address signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_write -> onchip_memory2_0_s1_translator:uav_write signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_lock -> onchip_memory2_0_s1_translator:uav_lock signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_read -> onchip_memory2_0_s1_translator:uav_read signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- onchip_memory2_0_s1_translator:uav_readdata -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_readdata signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- onchip_memory2_0_s1_translator:uav_readdatavalid -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> onchip_memory2_0_s1_translator:uav_debugaccess signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> onchip_memory2_0_s1_translator:uav_byteenable signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(100 downto 0); -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_source_ready signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(100 downto 0); -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_data signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(33 downto 0); -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- sram_0_avalon_sram_slave_translator:uav_waitrequest -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(1 downto 0); -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> sram_0_avalon_sram_slave_translator:uav_burstcount signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(15 downto 0); -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> sram_0_avalon_sram_slave_translator:uav_writedata signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_address -> sram_0_avalon_sram_slave_translator:uav_address signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_write -> sram_0_avalon_sram_slave_translator:uav_write signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_lock -> sram_0_avalon_sram_slave_translator:uav_lock signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_read -> sram_0_avalon_sram_slave_translator:uav_read signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(15 downto 0); -- sram_0_avalon_sram_slave_translator:uav_readdata -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_readdata signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- sram_0_avalon_sram_slave_translator:uav_readdatavalid -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sram_0_avalon_sram_slave_translator:uav_debugaccess signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(1 downto 0); -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> sram_0_avalon_sram_slave_translator:uav_byteenable signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(82 downto 0); -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_source_ready signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(82 downto 0); -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_data signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:in_valid signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(17 downto 0); -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:in_data signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:in_ready -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:out_valid -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data : std_logic_vector(17 downto 0); -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:out_data -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:out_ready signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- generic_tristate_controller_0_uas_translator:uav_waitrequest -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:m0_waitrequest signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(0 downto 0); -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:m0_burstcount -> generic_tristate_controller_0_uas_translator:uav_burstcount signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(7 downto 0); -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:m0_writedata -> generic_tristate_controller_0_uas_translator:uav_writedata signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:m0_address -> generic_tristate_controller_0_uas_translator:uav_address signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:m0_write -> generic_tristate_controller_0_uas_translator:uav_write signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:m0_lock -> generic_tristate_controller_0_uas_translator:uav_lock signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:m0_read -> generic_tristate_controller_0_uas_translator:uav_read signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(7 downto 0); -- generic_tristate_controller_0_uas_translator:uav_readdata -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:m0_readdata signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- generic_tristate_controller_0_uas_translator:uav_readdatavalid -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:m0_readdatavalid signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:m0_debugaccess -> generic_tristate_controller_0_uas_translator:uav_debugaccess signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(0 downto 0); -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:m0_byteenable -> generic_tristate_controller_0_uas_translator:uav_byteenable signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rf_source_valid -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(73 downto 0); -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rf_source_data -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rf_source_ready signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rf_sink_valid signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(73 downto 0); -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rf_sink_data signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rf_sink_ready -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo:in_valid signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(9 downto 0); -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo:in_data signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo:in_ready -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo:out_valid -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data : std_logic_vector(9 downto 0); -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo:out_data -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo:out_ready signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator:uav_waitrequest -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> jtag_uart_0_avalon_jtag_slave_translator:uav_burstcount signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> jtag_uart_0_avalon_jtag_slave_translator:uav_writedata signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_address -> jtag_uart_0_avalon_jtag_slave_translator:uav_address signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_write -> jtag_uart_0_avalon_jtag_slave_translator:uav_write signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_lock -> jtag_uart_0_avalon_jtag_slave_translator:uav_lock signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_read -> jtag_uart_0_avalon_jtag_slave_translator:uav_read signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- jtag_uart_0_avalon_jtag_slave_translator:uav_readdata -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_readdata signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator:uav_readdatavalid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> jtag_uart_0_avalon_jtag_slave_translator:uav_debugaccess signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> jtag_uart_0_avalon_jtag_slave_translator:uav_byteenable signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(100 downto 0); -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_source_ready signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(100 downto 0); -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_data signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(33 downto 0); -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- sysid_qsys_0_control_slave_translator:uav_waitrequest -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> sysid_qsys_0_control_slave_translator:uav_burstcount signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> sysid_qsys_0_control_slave_translator:uav_writedata signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_address -> sysid_qsys_0_control_slave_translator:uav_address signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_write -> sysid_qsys_0_control_slave_translator:uav_write signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_lock -> sysid_qsys_0_control_slave_translator:uav_lock signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_read -> sysid_qsys_0_control_slave_translator:uav_read signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- sysid_qsys_0_control_slave_translator:uav_readdata -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_readdata signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- sysid_qsys_0_control_slave_translator:uav_readdatavalid -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> sysid_qsys_0_control_slave_translator:uav_debugaccess signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> sysid_qsys_0_control_slave_translator:uav_byteenable signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(100 downto 0); -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_source_ready signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(100 downto 0); -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_data signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(33 downto 0); -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready signal green_leds_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- green_leds_s1_translator:uav_waitrequest -> green_leds_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest signal green_leds_s1_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- green_leds_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> green_leds_s1_translator:uav_burstcount signal green_leds_s1_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- green_leds_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> green_leds_s1_translator:uav_writedata signal green_leds_s1_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- green_leds_s1_translator_avalon_universal_slave_0_agent:m0_address -> green_leds_s1_translator:uav_address signal green_leds_s1_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:m0_write -> green_leds_s1_translator:uav_write signal green_leds_s1_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:m0_lock -> green_leds_s1_translator:uav_lock signal green_leds_s1_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:m0_read -> green_leds_s1_translator:uav_read signal green_leds_s1_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- green_leds_s1_translator:uav_readdata -> green_leds_s1_translator_avalon_universal_slave_0_agent:m0_readdata signal green_leds_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- green_leds_s1_translator:uav_readdatavalid -> green_leds_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid signal green_leds_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> green_leds_s1_translator:uav_debugaccess signal green_leds_s1_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- green_leds_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> green_leds_s1_translator:uav_byteenable signal green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket signal green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid signal green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket signal green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(100 downto 0); -- green_leds_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data signal green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> green_leds_s1_translator_avalon_universal_slave_0_agent:rf_source_ready signal green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> green_leds_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket signal green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> green_leds_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid signal green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> green_leds_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket signal green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(100 downto 0); -- green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> green_leds_s1_translator_avalon_universal_slave_0_agent:rf_sink_data signal green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready signal green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> green_leds_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid signal green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(33 downto 0); -- green_leds_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> green_leds_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data signal green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> green_leds_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready signal switches_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- switches_s1_translator:uav_waitrequest -> switches_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest signal switches_s1_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- switches_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> switches_s1_translator:uav_burstcount signal switches_s1_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- switches_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> switches_s1_translator:uav_writedata signal switches_s1_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- switches_s1_translator_avalon_universal_slave_0_agent:m0_address -> switches_s1_translator:uav_address signal switches_s1_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- switches_s1_translator_avalon_universal_slave_0_agent:m0_write -> switches_s1_translator:uav_write signal switches_s1_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- switches_s1_translator_avalon_universal_slave_0_agent:m0_lock -> switches_s1_translator:uav_lock signal switches_s1_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- switches_s1_translator_avalon_universal_slave_0_agent:m0_read -> switches_s1_translator:uav_read signal switches_s1_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- switches_s1_translator:uav_readdata -> switches_s1_translator_avalon_universal_slave_0_agent:m0_readdata signal switches_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- switches_s1_translator:uav_readdatavalid -> switches_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid signal switches_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- switches_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> switches_s1_translator:uav_debugaccess signal switches_s1_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- switches_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> switches_s1_translator:uav_byteenable signal switches_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- switches_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket signal switches_s1_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- switches_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid signal switches_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- switches_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket signal switches_s1_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(100 downto 0); -- switches_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data signal switches_s1_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> switches_s1_translator_avalon_universal_slave_0_agent:rf_source_ready signal switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket signal switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid signal switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket signal switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(100 downto 0); -- switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_data signal switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- switches_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready signal switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid signal switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(33 downto 0); -- switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data signal switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> switches_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- altpll_0_pll_slave_translator:uav_waitrequest -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> altpll_0_pll_slave_translator:uav_burstcount signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> altpll_0_pll_slave_translator:uav_writedata signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_address -> altpll_0_pll_slave_translator:uav_address signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_write -> altpll_0_pll_slave_translator:uav_write signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_lock -> altpll_0_pll_slave_translator:uav_lock signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_read -> altpll_0_pll_slave_translator:uav_read signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- altpll_0_pll_slave_translator:uav_readdata -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_readdata signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- altpll_0_pll_slave_translator:uav_readdatavalid -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> altpll_0_pll_slave_translator:uav_debugaccess signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> altpll_0_pll_slave_translator:uav_byteenable signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(100 downto 0); -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_source_ready signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(100 downto 0); -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_sink_data signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:in_valid signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(33 downto 0); -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:in_data signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:in_ready -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:out_valid -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data : std_logic_vector(33 downto 0); -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:out_data -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:out_ready signal timer_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- timer_0_s1_translator:uav_waitrequest -> timer_0_s1_translator_avalon_universal_slave_0_agent:m0_waitrequest signal timer_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- timer_0_s1_translator_avalon_universal_slave_0_agent:m0_burstcount -> timer_0_s1_translator:uav_burstcount signal timer_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- timer_0_s1_translator_avalon_universal_slave_0_agent:m0_writedata -> timer_0_s1_translator:uav_writedata signal timer_0_s1_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- timer_0_s1_translator_avalon_universal_slave_0_agent:m0_address -> timer_0_s1_translator:uav_address signal timer_0_s1_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:m0_write -> timer_0_s1_translator:uav_write signal timer_0_s1_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:m0_lock -> timer_0_s1_translator:uav_lock signal timer_0_s1_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:m0_read -> timer_0_s1_translator:uav_read signal timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- timer_0_s1_translator:uav_readdata -> timer_0_s1_translator_avalon_universal_slave_0_agent:m0_readdata signal timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- timer_0_s1_translator:uav_readdatavalid -> timer_0_s1_translator_avalon_universal_slave_0_agent:m0_readdatavalid signal timer_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:m0_debugaccess -> timer_0_s1_translator:uav_debugaccess signal timer_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- timer_0_s1_translator_avalon_universal_slave_0_agent:m0_byteenable -> timer_0_s1_translator:uav_byteenable signal timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket signal timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_valid -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid signal timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket signal timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(100 downto 0); -- timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_data -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data signal timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_source_ready signal timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket signal timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_valid signal timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket signal timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(100 downto 0); -- timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_data signal timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:rf_sink_ready -> timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready signal timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid signal timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(33 downto 0); -- timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data signal timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> timer_0_s1_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- usb_0_avalon_usb_slave_translator:uav_waitrequest -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> usb_0_avalon_usb_slave_translator:uav_burstcount signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> usb_0_avalon_usb_slave_translator:uav_writedata signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:m0_address -> usb_0_avalon_usb_slave_translator:uav_address signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:m0_write -> usb_0_avalon_usb_slave_translator:uav_write signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:m0_lock -> usb_0_avalon_usb_slave_translator:uav_lock signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:m0_read -> usb_0_avalon_usb_slave_translator:uav_read signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- usb_0_avalon_usb_slave_translator:uav_readdata -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:m0_readdata signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- usb_0_avalon_usb_slave_translator:uav_readdatavalid -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> usb_0_avalon_usb_slave_translator:uav_debugaccess signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> usb_0_avalon_usb_slave_translator:uav_byteenable signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(100 downto 0); -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rf_source_ready signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(100 downto 0); -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rf_sink_data signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(33 downto 0); -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest : std_logic; -- rs232_0_avalon_rs232_slave_translator:uav_waitrequest -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:m0_waitrequest signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_burstcount : std_logic_vector(2 downto 0); -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:m0_burstcount -> rs232_0_avalon_rs232_slave_translator:uav_burstcount signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_writedata : std_logic_vector(31 downto 0); -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:m0_writedata -> rs232_0_avalon_rs232_slave_translator:uav_writedata signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_address : std_logic_vector(24 downto 0); -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:m0_address -> rs232_0_avalon_rs232_slave_translator:uav_address signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_write : std_logic; -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:m0_write -> rs232_0_avalon_rs232_slave_translator:uav_write signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_lock : std_logic; -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:m0_lock -> rs232_0_avalon_rs232_slave_translator:uav_lock signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_read : std_logic; -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:m0_read -> rs232_0_avalon_rs232_slave_translator:uav_read signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_readdata : std_logic_vector(31 downto 0); -- rs232_0_avalon_rs232_slave_translator:uav_readdata -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:m0_readdata signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid : std_logic; -- rs232_0_avalon_rs232_slave_translator:uav_readdatavalid -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:m0_readdatavalid signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess : std_logic; -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:m0_debugaccess -> rs232_0_avalon_rs232_slave_translator:uav_debugaccess signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_byteenable : std_logic_vector(3 downto 0); -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:m0_byteenable -> rs232_0_avalon_rs232_slave_translator:uav_byteenable signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket : std_logic; -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rf_source_endofpacket -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_endofpacket signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_valid : std_logic; -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rf_source_valid -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_valid signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket : std_logic; -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rf_source_startofpacket -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_startofpacket signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_data : std_logic_vector(100 downto 0); -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rf_source_data -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_data signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_ready : std_logic; -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:in_ready -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rf_source_ready signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket : std_logic; -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_endofpacket -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rf_sink_endofpacket signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid : std_logic; -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_valid -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rf_sink_valid signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket : std_logic; -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_startofpacket -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rf_sink_startofpacket signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data : std_logic_vector(100 downto 0); -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_data -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rf_sink_data signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready : std_logic; -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rf_sink_ready -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:out_ready signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid : std_logic; -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_valid -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_valid signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data : std_logic_vector(33 downto 0); -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_data -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_data signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready : std_logic; -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_sink_ready -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rdata_fifo_src_ready signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket : std_logic; -- nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router:sink_endofpacket signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_valid : std_logic; -- nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router:sink_valid signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket : std_logic; -- nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router:sink_startofpacket signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_data : std_logic_vector(99 downto 0); -- nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router:sink_data signal nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_ready : std_logic; -- addr_router:sink_ready -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:cp_ready signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket : std_logic; -- nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:cp_endofpacket -> addr_router_001:sink_endofpacket signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_valid : std_logic; -- nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:cp_valid -> addr_router_001:sink_valid signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket : std_logic; -- nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:cp_startofpacket -> addr_router_001:sink_startofpacket signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_data : std_logic_vector(99 downto 0); -- nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:cp_data -> addr_router_001:sink_data signal nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_ready : std_logic; -- addr_router_001:sink_ready -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:cp_ready signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router:sink_endofpacket signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_valid -> id_router:sink_valid signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router:sink_startofpacket signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(99 downto 0); -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_data -> id_router:sink_data signal nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router:sink_ready -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:rp_ready signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_001:sink_endofpacket signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_001:sink_valid signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_001:sink_startofpacket signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(81 downto 0); -- sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_001:sink_data signal sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_001:sink_ready -> sdram_0_s1_translator_avalon_universal_slave_0_agent:rp_ready signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_002:sink_endofpacket signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_002:sink_valid signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_002:sink_startofpacket signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(99 downto 0); -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_002:sink_data signal onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_002:sink_ready -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:rp_ready signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_003:sink_endofpacket signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_003:sink_valid signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_003:sink_startofpacket signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(81 downto 0); -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_003:sink_data signal sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_003:sink_ready -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:rp_ready signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_004:sink_endofpacket signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_004:sink_valid signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_004:sink_startofpacket signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(72 downto 0); -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rp_data -> id_router_004:sink_data signal generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_004:sink_ready -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:rp_ready signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_005:sink_endofpacket signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_005:sink_valid signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_005:sink_startofpacket signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(99 downto 0); -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_005:sink_data signal jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_005:sink_ready -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:rp_ready signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_006:sink_endofpacket signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_006:sink_valid signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_006:sink_startofpacket signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(99 downto 0); -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_006:sink_data signal sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_006:sink_ready -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:rp_ready signal green_leds_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_007:sink_endofpacket signal green_leds_s1_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_007:sink_valid signal green_leds_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_007:sink_startofpacket signal green_leds_s1_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(99 downto 0); -- green_leds_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_007:sink_data signal green_leds_s1_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_007:sink_ready -> green_leds_s1_translator_avalon_universal_slave_0_agent:rp_ready signal switches_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- switches_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_008:sink_endofpacket signal switches_s1_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- switches_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_008:sink_valid signal switches_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- switches_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_008:sink_startofpacket signal switches_s1_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(99 downto 0); -- switches_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_008:sink_data signal switches_s1_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_008:sink_ready -> switches_s1_translator_avalon_universal_slave_0_agent:rp_ready signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_009:sink_endofpacket signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_009:sink_valid signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_009:sink_startofpacket signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(99 downto 0); -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_009:sink_data signal altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_009:sink_ready -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:rp_ready signal timer_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_010:sink_endofpacket signal timer_0_s1_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_010:sink_valid signal timer_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_010:sink_startofpacket signal timer_0_s1_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(99 downto 0); -- timer_0_s1_translator_avalon_universal_slave_0_agent:rp_data -> id_router_010:sink_data signal timer_0_s1_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_010:sink_ready -> timer_0_s1_translator_avalon_universal_slave_0_agent:rp_ready signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_011:sink_endofpacket signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_011:sink_valid signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_011:sink_startofpacket signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(99 downto 0); -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_011:sink_data signal usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_011:sink_ready -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:rp_ready signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket : std_logic; -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rp_endofpacket -> id_router_012:sink_endofpacket signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_valid : std_logic; -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rp_valid -> id_router_012:sink_valid signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket : std_logic; -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rp_startofpacket -> id_router_012:sink_startofpacket signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_data : std_logic_vector(99 downto 0); -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rp_data -> id_router_012:sink_data signal rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_ready : std_logic; -- id_router_012:sink_ready -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:rp_ready signal burst_adapter_source0_endofpacket : std_logic; -- burst_adapter:source0_endofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket signal burst_adapter_source0_valid : std_logic; -- burst_adapter:source0_valid -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_valid signal burst_adapter_source0_startofpacket : std_logic; -- burst_adapter:source0_startofpacket -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket signal burst_adapter_source0_data : std_logic_vector(81 downto 0); -- burst_adapter:source0_data -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_data signal burst_adapter_source0_ready : std_logic; -- sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_ready -> burst_adapter:source0_ready signal burst_adapter_source0_channel : std_logic_vector(12 downto 0); -- burst_adapter:source0_channel -> sdram_0_s1_translator_avalon_universal_slave_0_agent:cp_channel signal burst_adapter_001_source0_endofpacket : std_logic; -- burst_adapter_001:source0_endofpacket -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket signal burst_adapter_001_source0_valid : std_logic; -- burst_adapter_001:source0_valid -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_valid signal burst_adapter_001_source0_startofpacket : std_logic; -- burst_adapter_001:source0_startofpacket -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket signal burst_adapter_001_source0_data : std_logic_vector(81 downto 0); -- burst_adapter_001:source0_data -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_data signal burst_adapter_001_source0_ready : std_logic; -- sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_ready -> burst_adapter_001:source0_ready signal burst_adapter_001_source0_channel : std_logic_vector(12 downto 0); -- burst_adapter_001:source0_channel -> sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:cp_channel signal burst_adapter_002_source0_endofpacket : std_logic; -- burst_adapter_002:source0_endofpacket -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:cp_endofpacket signal burst_adapter_002_source0_valid : std_logic; -- burst_adapter_002:source0_valid -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:cp_valid signal burst_adapter_002_source0_startofpacket : std_logic; -- burst_adapter_002:source0_startofpacket -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:cp_startofpacket signal burst_adapter_002_source0_data : std_logic_vector(72 downto 0); -- burst_adapter_002:source0_data -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:cp_data signal burst_adapter_002_source0_ready : std_logic; -- generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:cp_ready -> burst_adapter_002:source0_ready signal burst_adapter_002_source0_channel : std_logic_vector(12 downto 0); -- burst_adapter_002:source0_channel -> generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:cp_channel signal rst_controller_reset_out_reset : std_logic; -- rst_controller:reset_out -> [addr_router:reset, addr_router_001:reset, burst_adapter:reset, burst_adapter_001:reset, burst_adapter_002:reset, cmd_xbar_demux:reset, cmd_xbar_demux_001:reset, cmd_xbar_mux:reset, cmd_xbar_mux_001:reset, cmd_xbar_mux_002:reset, cmd_xbar_mux_003:reset, cmd_xbar_mux_004:reset, crosser:in_reset, crosser_001:out_reset, generic_tristate_controller_0:reset_reset, generic_tristate_controller_0_uas_translator:reset, generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent:reset, generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo:reset, generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, green_leds_s1_translator:reset, green_leds_s1_translator_avalon_universal_slave_0_agent:reset, green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, id_router:reset, id_router_001:reset, id_router_002:reset, id_router_003:reset, id_router_004:reset, id_router_005:reset, id_router_006:reset, id_router_007:reset, id_router_008:reset, id_router_010:reset, id_router_011:reset, id_router_012:reset, irq_mapper:reset, jtag_uart_0_avalon_jtag_slave_translator:reset, jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:reset, jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, nios2_qsys_0_data_master_translator:reset, nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:reset, nios2_qsys_0_instruction_master_translator:reset, nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:reset, nios2_qsys_0_jtag_debug_module_translator:reset, nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:reset, nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, onchip_memory2_0:reset, onchip_memory2_0_s1_translator:reset, onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:reset, onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, rs232_0:reset, rs232_0_avalon_rs232_slave_translator:reset, rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:reset, rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, rsp_xbar_demux:reset, rsp_xbar_demux_001:reset, rsp_xbar_demux_002:reset, rsp_xbar_demux_003:reset, rsp_xbar_demux_004:reset, rsp_xbar_demux_005:reset, rsp_xbar_demux_006:reset, rsp_xbar_demux_007:reset, rsp_xbar_demux_008:reset, rsp_xbar_demux_010:reset, rsp_xbar_demux_011:reset, rsp_xbar_demux_012:reset, rsp_xbar_mux:reset, rsp_xbar_mux_001:reset, rst_controller_reset_out_reset:in, sdram_0_s1_translator:reset, sdram_0_s1_translator_avalon_universal_slave_0_agent:reset, sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo:reset, sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, sram_0:reset, sram_0_avalon_sram_slave_translator:reset, sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent:reset, sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:reset, sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, switches_s1_translator:reset, switches_s1_translator_avalon_universal_slave_0_agent:reset, switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, sysid_qsys_0_control_slave_translator:reset, sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:reset, sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, timer_0_s1_translator:reset, timer_0_s1_translator_avalon_universal_slave_0_agent:reset, timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, tristate_conduit_bridge_0:reset, tristate_conduit_pin_sharer_0:reset_reset, usb_0:reset, usb_0_avalon_usb_slave_translator:reset, usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:reset, usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, width_adapter:reset, width_adapter_001:reset, width_adapter_002:reset, width_adapter_003:reset, width_adapter_004:reset, width_adapter_005:reset] signal rst_controller_reset_out_reset_req : std_logic; -- rst_controller:reset_req -> onchip_memory2_0:reset_req signal nios2_qsys_0_jtag_debug_module_reset_reset : std_logic; -- nios2_qsys_0:jtag_debug_module_resetrequest -> [rst_controller:reset_in1, rst_controller_001:reset_in1] signal rst_controller_001_reset_out_reset : std_logic; -- rst_controller_001:reset_out -> [altpll_0:reset, altpll_0_pll_slave_translator:reset, altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:reset, altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo:reset, altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo:reset, crosser:out_reset, crosser_001:in_reset, id_router_009:reset, rsp_xbar_demux_009:reset] signal cmd_xbar_demux_src0_endofpacket : std_logic; -- cmd_xbar_demux:src0_endofpacket -> cmd_xbar_mux:sink0_endofpacket signal cmd_xbar_demux_src0_valid : std_logic; -- cmd_xbar_demux:src0_valid -> cmd_xbar_mux:sink0_valid signal cmd_xbar_demux_src0_startofpacket : std_logic; -- cmd_xbar_demux:src0_startofpacket -> cmd_xbar_mux:sink0_startofpacket signal cmd_xbar_demux_src0_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux:src0_data -> cmd_xbar_mux:sink0_data signal cmd_xbar_demux_src0_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux:src0_channel -> cmd_xbar_mux:sink0_channel signal cmd_xbar_demux_src0_ready : std_logic; -- cmd_xbar_mux:sink0_ready -> cmd_xbar_demux:src0_ready signal cmd_xbar_demux_src1_endofpacket : std_logic; -- cmd_xbar_demux:src1_endofpacket -> cmd_xbar_mux_001:sink0_endofpacket signal cmd_xbar_demux_src1_valid : std_logic; -- cmd_xbar_demux:src1_valid -> cmd_xbar_mux_001:sink0_valid signal cmd_xbar_demux_src1_startofpacket : std_logic; -- cmd_xbar_demux:src1_startofpacket -> cmd_xbar_mux_001:sink0_startofpacket signal cmd_xbar_demux_src1_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux:src1_data -> cmd_xbar_mux_001:sink0_data signal cmd_xbar_demux_src1_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux:src1_channel -> cmd_xbar_mux_001:sink0_channel signal cmd_xbar_demux_src1_ready : std_logic; -- cmd_xbar_mux_001:sink0_ready -> cmd_xbar_demux:src1_ready signal cmd_xbar_demux_src2_endofpacket : std_logic; -- cmd_xbar_demux:src2_endofpacket -> cmd_xbar_mux_002:sink0_endofpacket signal cmd_xbar_demux_src2_valid : std_logic; -- cmd_xbar_demux:src2_valid -> cmd_xbar_mux_002:sink0_valid signal cmd_xbar_demux_src2_startofpacket : std_logic; -- cmd_xbar_demux:src2_startofpacket -> cmd_xbar_mux_002:sink0_startofpacket signal cmd_xbar_demux_src2_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux:src2_data -> cmd_xbar_mux_002:sink0_data signal cmd_xbar_demux_src2_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux:src2_channel -> cmd_xbar_mux_002:sink0_channel signal cmd_xbar_demux_src2_ready : std_logic; -- cmd_xbar_mux_002:sink0_ready -> cmd_xbar_demux:src2_ready signal cmd_xbar_demux_src3_endofpacket : std_logic; -- cmd_xbar_demux:src3_endofpacket -> cmd_xbar_mux_003:sink0_endofpacket signal cmd_xbar_demux_src3_valid : std_logic; -- cmd_xbar_demux:src3_valid -> cmd_xbar_mux_003:sink0_valid signal cmd_xbar_demux_src3_startofpacket : std_logic; -- cmd_xbar_demux:src3_startofpacket -> cmd_xbar_mux_003:sink0_startofpacket signal cmd_xbar_demux_src3_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux:src3_data -> cmd_xbar_mux_003:sink0_data signal cmd_xbar_demux_src3_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux:src3_channel -> cmd_xbar_mux_003:sink0_channel signal cmd_xbar_demux_src3_ready : std_logic; -- cmd_xbar_mux_003:sink0_ready -> cmd_xbar_demux:src3_ready signal cmd_xbar_demux_src4_endofpacket : std_logic; -- cmd_xbar_demux:src4_endofpacket -> cmd_xbar_mux_004:sink0_endofpacket signal cmd_xbar_demux_src4_valid : std_logic; -- cmd_xbar_demux:src4_valid -> cmd_xbar_mux_004:sink0_valid signal cmd_xbar_demux_src4_startofpacket : std_logic; -- cmd_xbar_demux:src4_startofpacket -> cmd_xbar_mux_004:sink0_startofpacket signal cmd_xbar_demux_src4_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux:src4_data -> cmd_xbar_mux_004:sink0_data signal cmd_xbar_demux_src4_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux:src4_channel -> cmd_xbar_mux_004:sink0_channel signal cmd_xbar_demux_src4_ready : std_logic; -- cmd_xbar_mux_004:sink0_ready -> cmd_xbar_demux:src4_ready signal cmd_xbar_demux_001_src0_endofpacket : std_logic; -- cmd_xbar_demux_001:src0_endofpacket -> cmd_xbar_mux:sink1_endofpacket signal cmd_xbar_demux_001_src0_valid : std_logic; -- cmd_xbar_demux_001:src0_valid -> cmd_xbar_mux:sink1_valid signal cmd_xbar_demux_001_src0_startofpacket : std_logic; -- cmd_xbar_demux_001:src0_startofpacket -> cmd_xbar_mux:sink1_startofpacket signal cmd_xbar_demux_001_src0_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src0_data -> cmd_xbar_mux:sink1_data signal cmd_xbar_demux_001_src0_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src0_channel -> cmd_xbar_mux:sink1_channel signal cmd_xbar_demux_001_src0_ready : std_logic; -- cmd_xbar_mux:sink1_ready -> cmd_xbar_demux_001:src0_ready signal cmd_xbar_demux_001_src1_endofpacket : std_logic; -- cmd_xbar_demux_001:src1_endofpacket -> cmd_xbar_mux_001:sink1_endofpacket signal cmd_xbar_demux_001_src1_valid : std_logic; -- cmd_xbar_demux_001:src1_valid -> cmd_xbar_mux_001:sink1_valid signal cmd_xbar_demux_001_src1_startofpacket : std_logic; -- cmd_xbar_demux_001:src1_startofpacket -> cmd_xbar_mux_001:sink1_startofpacket signal cmd_xbar_demux_001_src1_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src1_data -> cmd_xbar_mux_001:sink1_data signal cmd_xbar_demux_001_src1_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src1_channel -> cmd_xbar_mux_001:sink1_channel signal cmd_xbar_demux_001_src1_ready : std_logic; -- cmd_xbar_mux_001:sink1_ready -> cmd_xbar_demux_001:src1_ready signal cmd_xbar_demux_001_src2_endofpacket : std_logic; -- cmd_xbar_demux_001:src2_endofpacket -> cmd_xbar_mux_002:sink1_endofpacket signal cmd_xbar_demux_001_src2_valid : std_logic; -- cmd_xbar_demux_001:src2_valid -> cmd_xbar_mux_002:sink1_valid signal cmd_xbar_demux_001_src2_startofpacket : std_logic; -- cmd_xbar_demux_001:src2_startofpacket -> cmd_xbar_mux_002:sink1_startofpacket signal cmd_xbar_demux_001_src2_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src2_data -> cmd_xbar_mux_002:sink1_data signal cmd_xbar_demux_001_src2_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src2_channel -> cmd_xbar_mux_002:sink1_channel signal cmd_xbar_demux_001_src2_ready : std_logic; -- cmd_xbar_mux_002:sink1_ready -> cmd_xbar_demux_001:src2_ready signal cmd_xbar_demux_001_src3_endofpacket : std_logic; -- cmd_xbar_demux_001:src3_endofpacket -> cmd_xbar_mux_003:sink1_endofpacket signal cmd_xbar_demux_001_src3_valid : std_logic; -- cmd_xbar_demux_001:src3_valid -> cmd_xbar_mux_003:sink1_valid signal cmd_xbar_demux_001_src3_startofpacket : std_logic; -- cmd_xbar_demux_001:src3_startofpacket -> cmd_xbar_mux_003:sink1_startofpacket signal cmd_xbar_demux_001_src3_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src3_data -> cmd_xbar_mux_003:sink1_data signal cmd_xbar_demux_001_src3_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src3_channel -> cmd_xbar_mux_003:sink1_channel signal cmd_xbar_demux_001_src3_ready : std_logic; -- cmd_xbar_mux_003:sink1_ready -> cmd_xbar_demux_001:src3_ready signal cmd_xbar_demux_001_src4_endofpacket : std_logic; -- cmd_xbar_demux_001:src4_endofpacket -> cmd_xbar_mux_004:sink1_endofpacket signal cmd_xbar_demux_001_src4_valid : std_logic; -- cmd_xbar_demux_001:src4_valid -> cmd_xbar_mux_004:sink1_valid signal cmd_xbar_demux_001_src4_startofpacket : std_logic; -- cmd_xbar_demux_001:src4_startofpacket -> cmd_xbar_mux_004:sink1_startofpacket signal cmd_xbar_demux_001_src4_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src4_data -> cmd_xbar_mux_004:sink1_data signal cmd_xbar_demux_001_src4_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src4_channel -> cmd_xbar_mux_004:sink1_channel signal cmd_xbar_demux_001_src4_ready : std_logic; -- cmd_xbar_mux_004:sink1_ready -> cmd_xbar_demux_001:src4_ready signal cmd_xbar_demux_001_src5_endofpacket : std_logic; -- cmd_xbar_demux_001:src5_endofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket signal cmd_xbar_demux_001_src5_valid : std_logic; -- cmd_xbar_demux_001:src5_valid -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_valid signal cmd_xbar_demux_001_src5_startofpacket : std_logic; -- cmd_xbar_demux_001:src5_startofpacket -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket signal cmd_xbar_demux_001_src5_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src5_data -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_data signal cmd_xbar_demux_001_src5_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src5_channel -> jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_channel signal cmd_xbar_demux_001_src6_endofpacket : std_logic; -- cmd_xbar_demux_001:src6_endofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket signal cmd_xbar_demux_001_src6_valid : std_logic; -- cmd_xbar_demux_001:src6_valid -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_valid signal cmd_xbar_demux_001_src6_startofpacket : std_logic; -- cmd_xbar_demux_001:src6_startofpacket -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket signal cmd_xbar_demux_001_src6_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src6_data -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_data signal cmd_xbar_demux_001_src6_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src6_channel -> sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_channel signal cmd_xbar_demux_001_src7_endofpacket : std_logic; -- cmd_xbar_demux_001:src7_endofpacket -> green_leds_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket signal cmd_xbar_demux_001_src7_valid : std_logic; -- cmd_xbar_demux_001:src7_valid -> green_leds_s1_translator_avalon_universal_slave_0_agent:cp_valid signal cmd_xbar_demux_001_src7_startofpacket : std_logic; -- cmd_xbar_demux_001:src7_startofpacket -> green_leds_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket signal cmd_xbar_demux_001_src7_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src7_data -> green_leds_s1_translator_avalon_universal_slave_0_agent:cp_data signal cmd_xbar_demux_001_src7_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src7_channel -> green_leds_s1_translator_avalon_universal_slave_0_agent:cp_channel signal cmd_xbar_demux_001_src8_endofpacket : std_logic; -- cmd_xbar_demux_001:src8_endofpacket -> switches_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket signal cmd_xbar_demux_001_src8_valid : std_logic; -- cmd_xbar_demux_001:src8_valid -> switches_s1_translator_avalon_universal_slave_0_agent:cp_valid signal cmd_xbar_demux_001_src8_startofpacket : std_logic; -- cmd_xbar_demux_001:src8_startofpacket -> switches_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket signal cmd_xbar_demux_001_src8_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src8_data -> switches_s1_translator_avalon_universal_slave_0_agent:cp_data signal cmd_xbar_demux_001_src8_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src8_channel -> switches_s1_translator_avalon_universal_slave_0_agent:cp_channel signal cmd_xbar_demux_001_src10_endofpacket : std_logic; -- cmd_xbar_demux_001:src10_endofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket signal cmd_xbar_demux_001_src10_valid : std_logic; -- cmd_xbar_demux_001:src10_valid -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_valid signal cmd_xbar_demux_001_src10_startofpacket : std_logic; -- cmd_xbar_demux_001:src10_startofpacket -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket signal cmd_xbar_demux_001_src10_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src10_data -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_data signal cmd_xbar_demux_001_src10_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src10_channel -> timer_0_s1_translator_avalon_universal_slave_0_agent:cp_channel signal cmd_xbar_demux_001_src11_endofpacket : std_logic; -- cmd_xbar_demux_001:src11_endofpacket -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket signal cmd_xbar_demux_001_src11_valid : std_logic; -- cmd_xbar_demux_001:src11_valid -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:cp_valid signal cmd_xbar_demux_001_src11_startofpacket : std_logic; -- cmd_xbar_demux_001:src11_startofpacket -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket signal cmd_xbar_demux_001_src11_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src11_data -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:cp_data signal cmd_xbar_demux_001_src11_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src11_channel -> usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:cp_channel signal cmd_xbar_demux_001_src12_endofpacket : std_logic; -- cmd_xbar_demux_001:src12_endofpacket -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket signal cmd_xbar_demux_001_src12_valid : std_logic; -- cmd_xbar_demux_001:src12_valid -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:cp_valid signal cmd_xbar_demux_001_src12_startofpacket : std_logic; -- cmd_xbar_demux_001:src12_startofpacket -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket signal cmd_xbar_demux_001_src12_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src12_data -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:cp_data signal cmd_xbar_demux_001_src12_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src12_channel -> rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:cp_channel signal rsp_xbar_demux_src0_endofpacket : std_logic; -- rsp_xbar_demux:src0_endofpacket -> rsp_xbar_mux:sink0_endofpacket signal rsp_xbar_demux_src0_valid : std_logic; -- rsp_xbar_demux:src0_valid -> rsp_xbar_mux:sink0_valid signal rsp_xbar_demux_src0_startofpacket : std_logic; -- rsp_xbar_demux:src0_startofpacket -> rsp_xbar_mux:sink0_startofpacket signal rsp_xbar_demux_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux:src0_data -> rsp_xbar_mux:sink0_data signal rsp_xbar_demux_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux:src0_channel -> rsp_xbar_mux:sink0_channel signal rsp_xbar_demux_src0_ready : std_logic; -- rsp_xbar_mux:sink0_ready -> rsp_xbar_demux:src0_ready signal rsp_xbar_demux_src1_endofpacket : std_logic; -- rsp_xbar_demux:src1_endofpacket -> rsp_xbar_mux_001:sink0_endofpacket signal rsp_xbar_demux_src1_valid : std_logic; -- rsp_xbar_demux:src1_valid -> rsp_xbar_mux_001:sink0_valid signal rsp_xbar_demux_src1_startofpacket : std_logic; -- rsp_xbar_demux:src1_startofpacket -> rsp_xbar_mux_001:sink0_startofpacket signal rsp_xbar_demux_src1_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux:src1_data -> rsp_xbar_mux_001:sink0_data signal rsp_xbar_demux_src1_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux:src1_channel -> rsp_xbar_mux_001:sink0_channel signal rsp_xbar_demux_src1_ready : std_logic; -- rsp_xbar_mux_001:sink0_ready -> rsp_xbar_demux:src1_ready signal rsp_xbar_demux_001_src0_endofpacket : std_logic; -- rsp_xbar_demux_001:src0_endofpacket -> rsp_xbar_mux:sink1_endofpacket signal rsp_xbar_demux_001_src0_valid : std_logic; -- rsp_xbar_demux_001:src0_valid -> rsp_xbar_mux:sink1_valid signal rsp_xbar_demux_001_src0_startofpacket : std_logic; -- rsp_xbar_demux_001:src0_startofpacket -> rsp_xbar_mux:sink1_startofpacket signal rsp_xbar_demux_001_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_001:src0_data -> rsp_xbar_mux:sink1_data signal rsp_xbar_demux_001_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_001:src0_channel -> rsp_xbar_mux:sink1_channel signal rsp_xbar_demux_001_src0_ready : std_logic; -- rsp_xbar_mux:sink1_ready -> rsp_xbar_demux_001:src0_ready signal rsp_xbar_demux_001_src1_endofpacket : std_logic; -- rsp_xbar_demux_001:src1_endofpacket -> rsp_xbar_mux_001:sink1_endofpacket signal rsp_xbar_demux_001_src1_valid : std_logic; -- rsp_xbar_demux_001:src1_valid -> rsp_xbar_mux_001:sink1_valid signal rsp_xbar_demux_001_src1_startofpacket : std_logic; -- rsp_xbar_demux_001:src1_startofpacket -> rsp_xbar_mux_001:sink1_startofpacket signal rsp_xbar_demux_001_src1_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_001:src1_data -> rsp_xbar_mux_001:sink1_data signal rsp_xbar_demux_001_src1_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_001:src1_channel -> rsp_xbar_mux_001:sink1_channel signal rsp_xbar_demux_001_src1_ready : std_logic; -- rsp_xbar_mux_001:sink1_ready -> rsp_xbar_demux_001:src1_ready signal rsp_xbar_demux_002_src0_endofpacket : std_logic; -- rsp_xbar_demux_002:src0_endofpacket -> rsp_xbar_mux:sink2_endofpacket signal rsp_xbar_demux_002_src0_valid : std_logic; -- rsp_xbar_demux_002:src0_valid -> rsp_xbar_mux:sink2_valid signal rsp_xbar_demux_002_src0_startofpacket : std_logic; -- rsp_xbar_demux_002:src0_startofpacket -> rsp_xbar_mux:sink2_startofpacket signal rsp_xbar_demux_002_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_002:src0_data -> rsp_xbar_mux:sink2_data signal rsp_xbar_demux_002_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_002:src0_channel -> rsp_xbar_mux:sink2_channel signal rsp_xbar_demux_002_src0_ready : std_logic; -- rsp_xbar_mux:sink2_ready -> rsp_xbar_demux_002:src0_ready signal rsp_xbar_demux_002_src1_endofpacket : std_logic; -- rsp_xbar_demux_002:src1_endofpacket -> rsp_xbar_mux_001:sink2_endofpacket signal rsp_xbar_demux_002_src1_valid : std_logic; -- rsp_xbar_demux_002:src1_valid -> rsp_xbar_mux_001:sink2_valid signal rsp_xbar_demux_002_src1_startofpacket : std_logic; -- rsp_xbar_demux_002:src1_startofpacket -> rsp_xbar_mux_001:sink2_startofpacket signal rsp_xbar_demux_002_src1_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_002:src1_data -> rsp_xbar_mux_001:sink2_data signal rsp_xbar_demux_002_src1_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_002:src1_channel -> rsp_xbar_mux_001:sink2_channel signal rsp_xbar_demux_002_src1_ready : std_logic; -- rsp_xbar_mux_001:sink2_ready -> rsp_xbar_demux_002:src1_ready signal rsp_xbar_demux_003_src0_endofpacket : std_logic; -- rsp_xbar_demux_003:src0_endofpacket -> rsp_xbar_mux:sink3_endofpacket signal rsp_xbar_demux_003_src0_valid : std_logic; -- rsp_xbar_demux_003:src0_valid -> rsp_xbar_mux:sink3_valid signal rsp_xbar_demux_003_src0_startofpacket : std_logic; -- rsp_xbar_demux_003:src0_startofpacket -> rsp_xbar_mux:sink3_startofpacket signal rsp_xbar_demux_003_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_003:src0_data -> rsp_xbar_mux:sink3_data signal rsp_xbar_demux_003_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_003:src0_channel -> rsp_xbar_mux:sink3_channel signal rsp_xbar_demux_003_src0_ready : std_logic; -- rsp_xbar_mux:sink3_ready -> rsp_xbar_demux_003:src0_ready signal rsp_xbar_demux_003_src1_endofpacket : std_logic; -- rsp_xbar_demux_003:src1_endofpacket -> rsp_xbar_mux_001:sink3_endofpacket signal rsp_xbar_demux_003_src1_valid : std_logic; -- rsp_xbar_demux_003:src1_valid -> rsp_xbar_mux_001:sink3_valid signal rsp_xbar_demux_003_src1_startofpacket : std_logic; -- rsp_xbar_demux_003:src1_startofpacket -> rsp_xbar_mux_001:sink3_startofpacket signal rsp_xbar_demux_003_src1_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_003:src1_data -> rsp_xbar_mux_001:sink3_data signal rsp_xbar_demux_003_src1_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_003:src1_channel -> rsp_xbar_mux_001:sink3_channel signal rsp_xbar_demux_003_src1_ready : std_logic; -- rsp_xbar_mux_001:sink3_ready -> rsp_xbar_demux_003:src1_ready signal rsp_xbar_demux_004_src0_endofpacket : std_logic; -- rsp_xbar_demux_004:src0_endofpacket -> rsp_xbar_mux:sink4_endofpacket signal rsp_xbar_demux_004_src0_valid : std_logic; -- rsp_xbar_demux_004:src0_valid -> rsp_xbar_mux:sink4_valid signal rsp_xbar_demux_004_src0_startofpacket : std_logic; -- rsp_xbar_demux_004:src0_startofpacket -> rsp_xbar_mux:sink4_startofpacket signal rsp_xbar_demux_004_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_004:src0_data -> rsp_xbar_mux:sink4_data signal rsp_xbar_demux_004_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_004:src0_channel -> rsp_xbar_mux:sink4_channel signal rsp_xbar_demux_004_src0_ready : std_logic; -- rsp_xbar_mux:sink4_ready -> rsp_xbar_demux_004:src0_ready signal rsp_xbar_demux_004_src1_endofpacket : std_logic; -- rsp_xbar_demux_004:src1_endofpacket -> rsp_xbar_mux_001:sink4_endofpacket signal rsp_xbar_demux_004_src1_valid : std_logic; -- rsp_xbar_demux_004:src1_valid -> rsp_xbar_mux_001:sink4_valid signal rsp_xbar_demux_004_src1_startofpacket : std_logic; -- rsp_xbar_demux_004:src1_startofpacket -> rsp_xbar_mux_001:sink4_startofpacket signal rsp_xbar_demux_004_src1_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_004:src1_data -> rsp_xbar_mux_001:sink4_data signal rsp_xbar_demux_004_src1_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_004:src1_channel -> rsp_xbar_mux_001:sink4_channel signal rsp_xbar_demux_004_src1_ready : std_logic; -- rsp_xbar_mux_001:sink4_ready -> rsp_xbar_demux_004:src1_ready signal rsp_xbar_demux_005_src0_endofpacket : std_logic; -- rsp_xbar_demux_005:src0_endofpacket -> rsp_xbar_mux_001:sink5_endofpacket signal rsp_xbar_demux_005_src0_valid : std_logic; -- rsp_xbar_demux_005:src0_valid -> rsp_xbar_mux_001:sink5_valid signal rsp_xbar_demux_005_src0_startofpacket : std_logic; -- rsp_xbar_demux_005:src0_startofpacket -> rsp_xbar_mux_001:sink5_startofpacket signal rsp_xbar_demux_005_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_005:src0_data -> rsp_xbar_mux_001:sink5_data signal rsp_xbar_demux_005_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_005:src0_channel -> rsp_xbar_mux_001:sink5_channel signal rsp_xbar_demux_005_src0_ready : std_logic; -- rsp_xbar_mux_001:sink5_ready -> rsp_xbar_demux_005:src0_ready signal rsp_xbar_demux_006_src0_endofpacket : std_logic; -- rsp_xbar_demux_006:src0_endofpacket -> rsp_xbar_mux_001:sink6_endofpacket signal rsp_xbar_demux_006_src0_valid : std_logic; -- rsp_xbar_demux_006:src0_valid -> rsp_xbar_mux_001:sink6_valid signal rsp_xbar_demux_006_src0_startofpacket : std_logic; -- rsp_xbar_demux_006:src0_startofpacket -> rsp_xbar_mux_001:sink6_startofpacket signal rsp_xbar_demux_006_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_006:src0_data -> rsp_xbar_mux_001:sink6_data signal rsp_xbar_demux_006_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_006:src0_channel -> rsp_xbar_mux_001:sink6_channel signal rsp_xbar_demux_006_src0_ready : std_logic; -- rsp_xbar_mux_001:sink6_ready -> rsp_xbar_demux_006:src0_ready signal rsp_xbar_demux_007_src0_endofpacket : std_logic; -- rsp_xbar_demux_007:src0_endofpacket -> rsp_xbar_mux_001:sink7_endofpacket signal rsp_xbar_demux_007_src0_valid : std_logic; -- rsp_xbar_demux_007:src0_valid -> rsp_xbar_mux_001:sink7_valid signal rsp_xbar_demux_007_src0_startofpacket : std_logic; -- rsp_xbar_demux_007:src0_startofpacket -> rsp_xbar_mux_001:sink7_startofpacket signal rsp_xbar_demux_007_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_007:src0_data -> rsp_xbar_mux_001:sink7_data signal rsp_xbar_demux_007_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_007:src0_channel -> rsp_xbar_mux_001:sink7_channel signal rsp_xbar_demux_007_src0_ready : std_logic; -- rsp_xbar_mux_001:sink7_ready -> rsp_xbar_demux_007:src0_ready signal rsp_xbar_demux_008_src0_endofpacket : std_logic; -- rsp_xbar_demux_008:src0_endofpacket -> rsp_xbar_mux_001:sink8_endofpacket signal rsp_xbar_demux_008_src0_valid : std_logic; -- rsp_xbar_demux_008:src0_valid -> rsp_xbar_mux_001:sink8_valid signal rsp_xbar_demux_008_src0_startofpacket : std_logic; -- rsp_xbar_demux_008:src0_startofpacket -> rsp_xbar_mux_001:sink8_startofpacket signal rsp_xbar_demux_008_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_008:src0_data -> rsp_xbar_mux_001:sink8_data signal rsp_xbar_demux_008_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_008:src0_channel -> rsp_xbar_mux_001:sink8_channel signal rsp_xbar_demux_008_src0_ready : std_logic; -- rsp_xbar_mux_001:sink8_ready -> rsp_xbar_demux_008:src0_ready signal rsp_xbar_demux_010_src0_endofpacket : std_logic; -- rsp_xbar_demux_010:src0_endofpacket -> rsp_xbar_mux_001:sink10_endofpacket signal rsp_xbar_demux_010_src0_valid : std_logic; -- rsp_xbar_demux_010:src0_valid -> rsp_xbar_mux_001:sink10_valid signal rsp_xbar_demux_010_src0_startofpacket : std_logic; -- rsp_xbar_demux_010:src0_startofpacket -> rsp_xbar_mux_001:sink10_startofpacket signal rsp_xbar_demux_010_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_010:src0_data -> rsp_xbar_mux_001:sink10_data signal rsp_xbar_demux_010_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_010:src0_channel -> rsp_xbar_mux_001:sink10_channel signal rsp_xbar_demux_010_src0_ready : std_logic; -- rsp_xbar_mux_001:sink10_ready -> rsp_xbar_demux_010:src0_ready signal rsp_xbar_demux_011_src0_endofpacket : std_logic; -- rsp_xbar_demux_011:src0_endofpacket -> rsp_xbar_mux_001:sink11_endofpacket signal rsp_xbar_demux_011_src0_valid : std_logic; -- rsp_xbar_demux_011:src0_valid -> rsp_xbar_mux_001:sink11_valid signal rsp_xbar_demux_011_src0_startofpacket : std_logic; -- rsp_xbar_demux_011:src0_startofpacket -> rsp_xbar_mux_001:sink11_startofpacket signal rsp_xbar_demux_011_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_011:src0_data -> rsp_xbar_mux_001:sink11_data signal rsp_xbar_demux_011_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_011:src0_channel -> rsp_xbar_mux_001:sink11_channel signal rsp_xbar_demux_011_src0_ready : std_logic; -- rsp_xbar_mux_001:sink11_ready -> rsp_xbar_demux_011:src0_ready signal rsp_xbar_demux_012_src0_endofpacket : std_logic; -- rsp_xbar_demux_012:src0_endofpacket -> rsp_xbar_mux_001:sink12_endofpacket signal rsp_xbar_demux_012_src0_valid : std_logic; -- rsp_xbar_demux_012:src0_valid -> rsp_xbar_mux_001:sink12_valid signal rsp_xbar_demux_012_src0_startofpacket : std_logic; -- rsp_xbar_demux_012:src0_startofpacket -> rsp_xbar_mux_001:sink12_startofpacket signal rsp_xbar_demux_012_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_012:src0_data -> rsp_xbar_mux_001:sink12_data signal rsp_xbar_demux_012_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_012:src0_channel -> rsp_xbar_mux_001:sink12_channel signal rsp_xbar_demux_012_src0_ready : std_logic; -- rsp_xbar_mux_001:sink12_ready -> rsp_xbar_demux_012:src0_ready signal addr_router_src_endofpacket : std_logic; -- addr_router:src_endofpacket -> cmd_xbar_demux:sink_endofpacket signal addr_router_src_valid : std_logic; -- addr_router:src_valid -> cmd_xbar_demux:sink_valid signal addr_router_src_startofpacket : std_logic; -- addr_router:src_startofpacket -> cmd_xbar_demux:sink_startofpacket signal addr_router_src_data : std_logic_vector(99 downto 0); -- addr_router:src_data -> cmd_xbar_demux:sink_data signal addr_router_src_channel : std_logic_vector(12 downto 0); -- addr_router:src_channel -> cmd_xbar_demux:sink_channel signal addr_router_src_ready : std_logic; -- cmd_xbar_demux:sink_ready -> addr_router:src_ready signal rsp_xbar_mux_src_endofpacket : std_logic; -- rsp_xbar_mux:src_endofpacket -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:rp_endofpacket signal rsp_xbar_mux_src_valid : std_logic; -- rsp_xbar_mux:src_valid -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:rp_valid signal rsp_xbar_mux_src_startofpacket : std_logic; -- rsp_xbar_mux:src_startofpacket -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:rp_startofpacket signal rsp_xbar_mux_src_data : std_logic_vector(99 downto 0); -- rsp_xbar_mux:src_data -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:rp_data signal rsp_xbar_mux_src_channel : std_logic_vector(12 downto 0); -- rsp_xbar_mux:src_channel -> nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:rp_channel signal rsp_xbar_mux_src_ready : std_logic; -- nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_mux:src_ready signal addr_router_001_src_endofpacket : std_logic; -- addr_router_001:src_endofpacket -> cmd_xbar_demux_001:sink_endofpacket signal addr_router_001_src_valid : std_logic; -- addr_router_001:src_valid -> cmd_xbar_demux_001:sink_valid signal addr_router_001_src_startofpacket : std_logic; -- addr_router_001:src_startofpacket -> cmd_xbar_demux_001:sink_startofpacket signal addr_router_001_src_data : std_logic_vector(99 downto 0); -- addr_router_001:src_data -> cmd_xbar_demux_001:sink_data signal addr_router_001_src_channel : std_logic_vector(12 downto 0); -- addr_router_001:src_channel -> cmd_xbar_demux_001:sink_channel signal addr_router_001_src_ready : std_logic; -- cmd_xbar_demux_001:sink_ready -> addr_router_001:src_ready signal rsp_xbar_mux_001_src_endofpacket : std_logic; -- rsp_xbar_mux_001:src_endofpacket -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:rp_endofpacket signal rsp_xbar_mux_001_src_valid : std_logic; -- rsp_xbar_mux_001:src_valid -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:rp_valid signal rsp_xbar_mux_001_src_startofpacket : std_logic; -- rsp_xbar_mux_001:src_startofpacket -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:rp_startofpacket signal rsp_xbar_mux_001_src_data : std_logic_vector(99 downto 0); -- rsp_xbar_mux_001:src_data -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:rp_data signal rsp_xbar_mux_001_src_channel : std_logic_vector(12 downto 0); -- rsp_xbar_mux_001:src_channel -> nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:rp_channel signal rsp_xbar_mux_001_src_ready : std_logic; -- nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent:rp_ready -> rsp_xbar_mux_001:src_ready signal cmd_xbar_mux_src_endofpacket : std_logic; -- cmd_xbar_mux:src_endofpacket -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_endofpacket signal cmd_xbar_mux_src_valid : std_logic; -- cmd_xbar_mux:src_valid -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_valid signal cmd_xbar_mux_src_startofpacket : std_logic; -- cmd_xbar_mux:src_startofpacket -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_startofpacket signal cmd_xbar_mux_src_data : std_logic_vector(99 downto 0); -- cmd_xbar_mux:src_data -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_data signal cmd_xbar_mux_src_channel : std_logic_vector(12 downto 0); -- cmd_xbar_mux:src_channel -> nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_channel signal cmd_xbar_mux_src_ready : std_logic; -- nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux:src_ready signal id_router_src_endofpacket : std_logic; -- id_router:src_endofpacket -> rsp_xbar_demux:sink_endofpacket signal id_router_src_valid : std_logic; -- id_router:src_valid -> rsp_xbar_demux:sink_valid signal id_router_src_startofpacket : std_logic; -- id_router:src_startofpacket -> rsp_xbar_demux:sink_startofpacket signal id_router_src_data : std_logic_vector(99 downto 0); -- id_router:src_data -> rsp_xbar_demux:sink_data signal id_router_src_channel : std_logic_vector(12 downto 0); -- id_router:src_channel -> rsp_xbar_demux:sink_channel signal id_router_src_ready : std_logic; -- rsp_xbar_demux:sink_ready -> id_router:src_ready signal cmd_xbar_mux_002_src_endofpacket : std_logic; -- cmd_xbar_mux_002:src_endofpacket -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:cp_endofpacket signal cmd_xbar_mux_002_src_valid : std_logic; -- cmd_xbar_mux_002:src_valid -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:cp_valid signal cmd_xbar_mux_002_src_startofpacket : std_logic; -- cmd_xbar_mux_002:src_startofpacket -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:cp_startofpacket signal cmd_xbar_mux_002_src_data : std_logic_vector(99 downto 0); -- cmd_xbar_mux_002:src_data -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:cp_data signal cmd_xbar_mux_002_src_channel : std_logic_vector(12 downto 0); -- cmd_xbar_mux_002:src_channel -> onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:cp_channel signal cmd_xbar_mux_002_src_ready : std_logic; -- onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_mux_002:src_ready signal id_router_002_src_endofpacket : std_logic; -- id_router_002:src_endofpacket -> rsp_xbar_demux_002:sink_endofpacket signal id_router_002_src_valid : std_logic; -- id_router_002:src_valid -> rsp_xbar_demux_002:sink_valid signal id_router_002_src_startofpacket : std_logic; -- id_router_002:src_startofpacket -> rsp_xbar_demux_002:sink_startofpacket signal id_router_002_src_data : std_logic_vector(99 downto 0); -- id_router_002:src_data -> rsp_xbar_demux_002:sink_data signal id_router_002_src_channel : std_logic_vector(12 downto 0); -- id_router_002:src_channel -> rsp_xbar_demux_002:sink_channel signal id_router_002_src_ready : std_logic; -- rsp_xbar_demux_002:sink_ready -> id_router_002:src_ready signal cmd_xbar_demux_001_src5_ready : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src5_ready signal id_router_005_src_endofpacket : std_logic; -- id_router_005:src_endofpacket -> rsp_xbar_demux_005:sink_endofpacket signal id_router_005_src_valid : std_logic; -- id_router_005:src_valid -> rsp_xbar_demux_005:sink_valid signal id_router_005_src_startofpacket : std_logic; -- id_router_005:src_startofpacket -> rsp_xbar_demux_005:sink_startofpacket signal id_router_005_src_data : std_logic_vector(99 downto 0); -- id_router_005:src_data -> rsp_xbar_demux_005:sink_data signal id_router_005_src_channel : std_logic_vector(12 downto 0); -- id_router_005:src_channel -> rsp_xbar_demux_005:sink_channel signal id_router_005_src_ready : std_logic; -- rsp_xbar_demux_005:sink_ready -> id_router_005:src_ready signal cmd_xbar_demux_001_src6_ready : std_logic; -- sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src6_ready signal id_router_006_src_endofpacket : std_logic; -- id_router_006:src_endofpacket -> rsp_xbar_demux_006:sink_endofpacket signal id_router_006_src_valid : std_logic; -- id_router_006:src_valid -> rsp_xbar_demux_006:sink_valid signal id_router_006_src_startofpacket : std_logic; -- id_router_006:src_startofpacket -> rsp_xbar_demux_006:sink_startofpacket signal id_router_006_src_data : std_logic_vector(99 downto 0); -- id_router_006:src_data -> rsp_xbar_demux_006:sink_data signal id_router_006_src_channel : std_logic_vector(12 downto 0); -- id_router_006:src_channel -> rsp_xbar_demux_006:sink_channel signal id_router_006_src_ready : std_logic; -- rsp_xbar_demux_006:sink_ready -> id_router_006:src_ready signal cmd_xbar_demux_001_src7_ready : std_logic; -- green_leds_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src7_ready signal id_router_007_src_endofpacket : std_logic; -- id_router_007:src_endofpacket -> rsp_xbar_demux_007:sink_endofpacket signal id_router_007_src_valid : std_logic; -- id_router_007:src_valid -> rsp_xbar_demux_007:sink_valid signal id_router_007_src_startofpacket : std_logic; -- id_router_007:src_startofpacket -> rsp_xbar_demux_007:sink_startofpacket signal id_router_007_src_data : std_logic_vector(99 downto 0); -- id_router_007:src_data -> rsp_xbar_demux_007:sink_data signal id_router_007_src_channel : std_logic_vector(12 downto 0); -- id_router_007:src_channel -> rsp_xbar_demux_007:sink_channel signal id_router_007_src_ready : std_logic; -- rsp_xbar_demux_007:sink_ready -> id_router_007:src_ready signal cmd_xbar_demux_001_src8_ready : std_logic; -- switches_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src8_ready signal id_router_008_src_endofpacket : std_logic; -- id_router_008:src_endofpacket -> rsp_xbar_demux_008:sink_endofpacket signal id_router_008_src_valid : std_logic; -- id_router_008:src_valid -> rsp_xbar_demux_008:sink_valid signal id_router_008_src_startofpacket : std_logic; -- id_router_008:src_startofpacket -> rsp_xbar_demux_008:sink_startofpacket signal id_router_008_src_data : std_logic_vector(99 downto 0); -- id_router_008:src_data -> rsp_xbar_demux_008:sink_data signal id_router_008_src_channel : std_logic_vector(12 downto 0); -- id_router_008:src_channel -> rsp_xbar_demux_008:sink_channel signal id_router_008_src_ready : std_logic; -- rsp_xbar_demux_008:sink_ready -> id_router_008:src_ready signal crosser_out_ready : std_logic; -- altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:cp_ready -> crosser:out_ready signal id_router_009_src_endofpacket : std_logic; -- id_router_009:src_endofpacket -> rsp_xbar_demux_009:sink_endofpacket signal id_router_009_src_valid : std_logic; -- id_router_009:src_valid -> rsp_xbar_demux_009:sink_valid signal id_router_009_src_startofpacket : std_logic; -- id_router_009:src_startofpacket -> rsp_xbar_demux_009:sink_startofpacket signal id_router_009_src_data : std_logic_vector(99 downto 0); -- id_router_009:src_data -> rsp_xbar_demux_009:sink_data signal id_router_009_src_channel : std_logic_vector(12 downto 0); -- id_router_009:src_channel -> rsp_xbar_demux_009:sink_channel signal id_router_009_src_ready : std_logic; -- rsp_xbar_demux_009:sink_ready -> id_router_009:src_ready signal cmd_xbar_demux_001_src10_ready : std_logic; -- timer_0_s1_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src10_ready signal id_router_010_src_endofpacket : std_logic; -- id_router_010:src_endofpacket -> rsp_xbar_demux_010:sink_endofpacket signal id_router_010_src_valid : std_logic; -- id_router_010:src_valid -> rsp_xbar_demux_010:sink_valid signal id_router_010_src_startofpacket : std_logic; -- id_router_010:src_startofpacket -> rsp_xbar_demux_010:sink_startofpacket signal id_router_010_src_data : std_logic_vector(99 downto 0); -- id_router_010:src_data -> rsp_xbar_demux_010:sink_data signal id_router_010_src_channel : std_logic_vector(12 downto 0); -- id_router_010:src_channel -> rsp_xbar_demux_010:sink_channel signal id_router_010_src_ready : std_logic; -- rsp_xbar_demux_010:sink_ready -> id_router_010:src_ready signal cmd_xbar_demux_001_src11_ready : std_logic; -- usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src11_ready signal id_router_011_src_endofpacket : std_logic; -- id_router_011:src_endofpacket -> rsp_xbar_demux_011:sink_endofpacket signal id_router_011_src_valid : std_logic; -- id_router_011:src_valid -> rsp_xbar_demux_011:sink_valid signal id_router_011_src_startofpacket : std_logic; -- id_router_011:src_startofpacket -> rsp_xbar_demux_011:sink_startofpacket signal id_router_011_src_data : std_logic_vector(99 downto 0); -- id_router_011:src_data -> rsp_xbar_demux_011:sink_data signal id_router_011_src_channel : std_logic_vector(12 downto 0); -- id_router_011:src_channel -> rsp_xbar_demux_011:sink_channel signal id_router_011_src_ready : std_logic; -- rsp_xbar_demux_011:sink_ready -> id_router_011:src_ready signal cmd_xbar_demux_001_src12_ready : std_logic; -- rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent:cp_ready -> cmd_xbar_demux_001:src12_ready signal id_router_012_src_endofpacket : std_logic; -- id_router_012:src_endofpacket -> rsp_xbar_demux_012:sink_endofpacket signal id_router_012_src_valid : std_logic; -- id_router_012:src_valid -> rsp_xbar_demux_012:sink_valid signal id_router_012_src_startofpacket : std_logic; -- id_router_012:src_startofpacket -> rsp_xbar_demux_012:sink_startofpacket signal id_router_012_src_data : std_logic_vector(99 downto 0); -- id_router_012:src_data -> rsp_xbar_demux_012:sink_data signal id_router_012_src_channel : std_logic_vector(12 downto 0); -- id_router_012:src_channel -> rsp_xbar_demux_012:sink_channel signal id_router_012_src_ready : std_logic; -- rsp_xbar_demux_012:sink_ready -> id_router_012:src_ready signal cmd_xbar_mux_001_src_endofpacket : std_logic; -- cmd_xbar_mux_001:src_endofpacket -> width_adapter:in_endofpacket signal cmd_xbar_mux_001_src_valid : std_logic; -- cmd_xbar_mux_001:src_valid -> width_adapter:in_valid signal cmd_xbar_mux_001_src_startofpacket : std_logic; -- cmd_xbar_mux_001:src_startofpacket -> width_adapter:in_startofpacket signal cmd_xbar_mux_001_src_data : std_logic_vector(99 downto 0); -- cmd_xbar_mux_001:src_data -> width_adapter:in_data signal cmd_xbar_mux_001_src_channel : std_logic_vector(12 downto 0); -- cmd_xbar_mux_001:src_channel -> width_adapter:in_channel signal cmd_xbar_mux_001_src_ready : std_logic; -- width_adapter:in_ready -> cmd_xbar_mux_001:src_ready signal width_adapter_src_endofpacket : std_logic; -- width_adapter:out_endofpacket -> burst_adapter:sink0_endofpacket signal width_adapter_src_valid : std_logic; -- width_adapter:out_valid -> burst_adapter:sink0_valid signal width_adapter_src_startofpacket : std_logic; -- width_adapter:out_startofpacket -> burst_adapter:sink0_startofpacket signal width_adapter_src_data : std_logic_vector(81 downto 0); -- width_adapter:out_data -> burst_adapter:sink0_data signal width_adapter_src_ready : std_logic; -- burst_adapter:sink0_ready -> width_adapter:out_ready signal width_adapter_src_channel : std_logic_vector(12 downto 0); -- width_adapter:out_channel -> burst_adapter:sink0_channel signal id_router_001_src_endofpacket : std_logic; -- id_router_001:src_endofpacket -> width_adapter_001:in_endofpacket signal id_router_001_src_valid : std_logic; -- id_router_001:src_valid -> width_adapter_001:in_valid signal id_router_001_src_startofpacket : std_logic; -- id_router_001:src_startofpacket -> width_adapter_001:in_startofpacket signal id_router_001_src_data : std_logic_vector(81 downto 0); -- id_router_001:src_data -> width_adapter_001:in_data signal id_router_001_src_channel : std_logic_vector(12 downto 0); -- id_router_001:src_channel -> width_adapter_001:in_channel signal id_router_001_src_ready : std_logic; -- width_adapter_001:in_ready -> id_router_001:src_ready signal width_adapter_001_src_endofpacket : std_logic; -- width_adapter_001:out_endofpacket -> rsp_xbar_demux_001:sink_endofpacket signal width_adapter_001_src_valid : std_logic; -- width_adapter_001:out_valid -> rsp_xbar_demux_001:sink_valid signal width_adapter_001_src_startofpacket : std_logic; -- width_adapter_001:out_startofpacket -> rsp_xbar_demux_001:sink_startofpacket signal width_adapter_001_src_data : std_logic_vector(99 downto 0); -- width_adapter_001:out_data -> rsp_xbar_demux_001:sink_data signal width_adapter_001_src_ready : std_logic; -- rsp_xbar_demux_001:sink_ready -> width_adapter_001:out_ready signal width_adapter_001_src_channel : std_logic_vector(12 downto 0); -- width_adapter_001:out_channel -> rsp_xbar_demux_001:sink_channel signal cmd_xbar_mux_003_src_endofpacket : std_logic; -- cmd_xbar_mux_003:src_endofpacket -> width_adapter_002:in_endofpacket signal cmd_xbar_mux_003_src_valid : std_logic; -- cmd_xbar_mux_003:src_valid -> width_adapter_002:in_valid signal cmd_xbar_mux_003_src_startofpacket : std_logic; -- cmd_xbar_mux_003:src_startofpacket -> width_adapter_002:in_startofpacket signal cmd_xbar_mux_003_src_data : std_logic_vector(99 downto 0); -- cmd_xbar_mux_003:src_data -> width_adapter_002:in_data signal cmd_xbar_mux_003_src_channel : std_logic_vector(12 downto 0); -- cmd_xbar_mux_003:src_channel -> width_adapter_002:in_channel signal cmd_xbar_mux_003_src_ready : std_logic; -- width_adapter_002:in_ready -> cmd_xbar_mux_003:src_ready signal width_adapter_002_src_endofpacket : std_logic; -- width_adapter_002:out_endofpacket -> burst_adapter_001:sink0_endofpacket signal width_adapter_002_src_valid : std_logic; -- width_adapter_002:out_valid -> burst_adapter_001:sink0_valid signal width_adapter_002_src_startofpacket : std_logic; -- width_adapter_002:out_startofpacket -> burst_adapter_001:sink0_startofpacket signal width_adapter_002_src_data : std_logic_vector(81 downto 0); -- width_adapter_002:out_data -> burst_adapter_001:sink0_data signal width_adapter_002_src_ready : std_logic; -- burst_adapter_001:sink0_ready -> width_adapter_002:out_ready signal width_adapter_002_src_channel : std_logic_vector(12 downto 0); -- width_adapter_002:out_channel -> burst_adapter_001:sink0_channel signal id_router_003_src_endofpacket : std_logic; -- id_router_003:src_endofpacket -> width_adapter_003:in_endofpacket signal id_router_003_src_valid : std_logic; -- id_router_003:src_valid -> width_adapter_003:in_valid signal id_router_003_src_startofpacket : std_logic; -- id_router_003:src_startofpacket -> width_adapter_003:in_startofpacket signal id_router_003_src_data : std_logic_vector(81 downto 0); -- id_router_003:src_data -> width_adapter_003:in_data signal id_router_003_src_channel : std_logic_vector(12 downto 0); -- id_router_003:src_channel -> width_adapter_003:in_channel signal id_router_003_src_ready : std_logic; -- width_adapter_003:in_ready -> id_router_003:src_ready signal width_adapter_003_src_endofpacket : std_logic; -- width_adapter_003:out_endofpacket -> rsp_xbar_demux_003:sink_endofpacket signal width_adapter_003_src_valid : std_logic; -- width_adapter_003:out_valid -> rsp_xbar_demux_003:sink_valid signal width_adapter_003_src_startofpacket : std_logic; -- width_adapter_003:out_startofpacket -> rsp_xbar_demux_003:sink_startofpacket signal width_adapter_003_src_data : std_logic_vector(99 downto 0); -- width_adapter_003:out_data -> rsp_xbar_demux_003:sink_data signal width_adapter_003_src_ready : std_logic; -- rsp_xbar_demux_003:sink_ready -> width_adapter_003:out_ready signal width_adapter_003_src_channel : std_logic_vector(12 downto 0); -- width_adapter_003:out_channel -> rsp_xbar_demux_003:sink_channel signal cmd_xbar_mux_004_src_endofpacket : std_logic; -- cmd_xbar_mux_004:src_endofpacket -> width_adapter_004:in_endofpacket signal cmd_xbar_mux_004_src_valid : std_logic; -- cmd_xbar_mux_004:src_valid -> width_adapter_004:in_valid signal cmd_xbar_mux_004_src_startofpacket : std_logic; -- cmd_xbar_mux_004:src_startofpacket -> width_adapter_004:in_startofpacket signal cmd_xbar_mux_004_src_data : std_logic_vector(99 downto 0); -- cmd_xbar_mux_004:src_data -> width_adapter_004:in_data signal cmd_xbar_mux_004_src_channel : std_logic_vector(12 downto 0); -- cmd_xbar_mux_004:src_channel -> width_adapter_004:in_channel signal cmd_xbar_mux_004_src_ready : std_logic; -- width_adapter_004:in_ready -> cmd_xbar_mux_004:src_ready signal width_adapter_004_src_endofpacket : std_logic; -- width_adapter_004:out_endofpacket -> burst_adapter_002:sink0_endofpacket signal width_adapter_004_src_valid : std_logic; -- width_adapter_004:out_valid -> burst_adapter_002:sink0_valid signal width_adapter_004_src_startofpacket : std_logic; -- width_adapter_004:out_startofpacket -> burst_adapter_002:sink0_startofpacket signal width_adapter_004_src_data : std_logic_vector(72 downto 0); -- width_adapter_004:out_data -> burst_adapter_002:sink0_data signal width_adapter_004_src_ready : std_logic; -- burst_adapter_002:sink0_ready -> width_adapter_004:out_ready signal width_adapter_004_src_channel : std_logic_vector(12 downto 0); -- width_adapter_004:out_channel -> burst_adapter_002:sink0_channel signal id_router_004_src_endofpacket : std_logic; -- id_router_004:src_endofpacket -> width_adapter_005:in_endofpacket signal id_router_004_src_valid : std_logic; -- id_router_004:src_valid -> width_adapter_005:in_valid signal id_router_004_src_startofpacket : std_logic; -- id_router_004:src_startofpacket -> width_adapter_005:in_startofpacket signal id_router_004_src_data : std_logic_vector(72 downto 0); -- id_router_004:src_data -> width_adapter_005:in_data signal id_router_004_src_channel : std_logic_vector(12 downto 0); -- id_router_004:src_channel -> width_adapter_005:in_channel signal id_router_004_src_ready : std_logic; -- width_adapter_005:in_ready -> id_router_004:src_ready signal width_adapter_005_src_endofpacket : std_logic; -- width_adapter_005:out_endofpacket -> rsp_xbar_demux_004:sink_endofpacket signal width_adapter_005_src_valid : std_logic; -- width_adapter_005:out_valid -> rsp_xbar_demux_004:sink_valid signal width_adapter_005_src_startofpacket : std_logic; -- width_adapter_005:out_startofpacket -> rsp_xbar_demux_004:sink_startofpacket signal width_adapter_005_src_data : std_logic_vector(99 downto 0); -- width_adapter_005:out_data -> rsp_xbar_demux_004:sink_data signal width_adapter_005_src_ready : std_logic; -- rsp_xbar_demux_004:sink_ready -> width_adapter_005:out_ready signal width_adapter_005_src_channel : std_logic_vector(12 downto 0); -- width_adapter_005:out_channel -> rsp_xbar_demux_004:sink_channel signal crosser_out_endofpacket : std_logic; -- crosser:out_endofpacket -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:cp_endofpacket signal crosser_out_valid : std_logic; -- crosser:out_valid -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:cp_valid signal crosser_out_startofpacket : std_logic; -- crosser:out_startofpacket -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:cp_startofpacket signal crosser_out_data : std_logic_vector(99 downto 0); -- crosser:out_data -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:cp_data signal crosser_out_channel : std_logic_vector(12 downto 0); -- crosser:out_channel -> altpll_0_pll_slave_translator_avalon_universal_slave_0_agent:cp_channel signal cmd_xbar_demux_001_src9_endofpacket : std_logic; -- cmd_xbar_demux_001:src9_endofpacket -> crosser:in_endofpacket signal cmd_xbar_demux_001_src9_valid : std_logic; -- cmd_xbar_demux_001:src9_valid -> crosser:in_valid signal cmd_xbar_demux_001_src9_startofpacket : std_logic; -- cmd_xbar_demux_001:src9_startofpacket -> crosser:in_startofpacket signal cmd_xbar_demux_001_src9_data : std_logic_vector(99 downto 0); -- cmd_xbar_demux_001:src9_data -> crosser:in_data signal cmd_xbar_demux_001_src9_channel : std_logic_vector(12 downto 0); -- cmd_xbar_demux_001:src9_channel -> crosser:in_channel signal cmd_xbar_demux_001_src9_ready : std_logic; -- crosser:in_ready -> cmd_xbar_demux_001:src9_ready signal crosser_001_out_endofpacket : std_logic; -- crosser_001:out_endofpacket -> rsp_xbar_mux_001:sink9_endofpacket signal crosser_001_out_valid : std_logic; -- crosser_001:out_valid -> rsp_xbar_mux_001:sink9_valid signal crosser_001_out_startofpacket : std_logic; -- crosser_001:out_startofpacket -> rsp_xbar_mux_001:sink9_startofpacket signal crosser_001_out_data : std_logic_vector(99 downto 0); -- crosser_001:out_data -> rsp_xbar_mux_001:sink9_data signal crosser_001_out_channel : std_logic_vector(12 downto 0); -- crosser_001:out_channel -> rsp_xbar_mux_001:sink9_channel signal crosser_001_out_ready : std_logic; -- rsp_xbar_mux_001:sink9_ready -> crosser_001:out_ready signal rsp_xbar_demux_009_src0_endofpacket : std_logic; -- rsp_xbar_demux_009:src0_endofpacket -> crosser_001:in_endofpacket signal rsp_xbar_demux_009_src0_valid : std_logic; -- rsp_xbar_demux_009:src0_valid -> crosser_001:in_valid signal rsp_xbar_demux_009_src0_startofpacket : std_logic; -- rsp_xbar_demux_009:src0_startofpacket -> crosser_001:in_startofpacket signal rsp_xbar_demux_009_src0_data : std_logic_vector(99 downto 0); -- rsp_xbar_demux_009:src0_data -> crosser_001:in_data signal rsp_xbar_demux_009_src0_channel : std_logic_vector(12 downto 0); -- rsp_xbar_demux_009:src0_channel -> crosser_001:in_channel signal rsp_xbar_demux_009_src0_ready : std_logic; -- crosser_001:in_ready -> rsp_xbar_demux_009:src0_ready signal irq_mapper_receiver0_irq : std_logic; -- timer_0:irq -> irq_mapper:receiver0_irq signal irq_mapper_receiver1_irq : std_logic; -- jtag_uart_0:av_irq -> irq_mapper:receiver1_irq signal irq_mapper_receiver2_irq : std_logic; -- usb_0:irq -> irq_mapper:receiver2_irq signal irq_mapper_receiver3_irq : std_logic; -- rs232_0:irq -> irq_mapper:receiver3_irq signal nios2_qsys_0_d_irq_irq : std_logic_vector(31 downto 0); -- irq_mapper:sender_irq -> nios2_qsys_0:d_irq signal reset_reset_n_ports_inv : std_logic; -- reset_reset_n:inv -> [rst_controller:reset_in0, rst_controller_001:reset_in0] signal sdram_0_s1_translator_avalon_anti_slave_0_write_ports_inv : std_logic; -- sdram_0_s1_translator_avalon_anti_slave_0_write:inv -> sdram_0:az_wr_n signal sdram_0_s1_translator_avalon_anti_slave_0_read_ports_inv : std_logic; -- sdram_0_s1_translator_avalon_anti_slave_0_read:inv -> sdram_0:az_rd_n signal sdram_0_s1_translator_avalon_anti_slave_0_byteenable_ports_inv : std_logic_vector(1 downto 0); -- sdram_0_s1_translator_avalon_anti_slave_0_byteenable:inv -> sdram_0:az_be_n signal jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write_ports_inv : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write:inv -> jtag_uart_0:av_write_n signal jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read_ports_inv : std_logic; -- jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read:inv -> jtag_uart_0:av_read_n signal green_leds_s1_translator_avalon_anti_slave_0_write_ports_inv : std_logic; -- green_leds_s1_translator_avalon_anti_slave_0_write:inv -> green_leds:write_n signal timer_0_s1_translator_avalon_anti_slave_0_write_ports_inv : std_logic; -- timer_0_s1_translator_avalon_anti_slave_0_write:inv -> timer_0:write_n signal rst_controller_reset_out_reset_ports_inv : std_logic; -- rst_controller_reset_out_reset:inv -> [green_leds:reset_n, jtag_uart_0:rst_n, nios2_qsys_0:reset_n, sdram_0:reset_n, switches:reset_n, sysid_qsys_0:reset_n, timer_0:reset_n] begin nios2_qsys_0 : component niosII_system_nios2_qsys_0 port map ( clk => altpll_0_c1_clk, -- clk.clk reset_n => rst_controller_reset_out_reset_ports_inv, -- reset_n.reset_n d_address => nios2_qsys_0_data_master_address, -- data_master.address d_byteenable => nios2_qsys_0_data_master_byteenable, -- .byteenable d_read => nios2_qsys_0_data_master_read, -- .read d_readdata => nios2_qsys_0_data_master_readdata, -- .readdata d_waitrequest => nios2_qsys_0_data_master_waitrequest, -- .waitrequest d_write => nios2_qsys_0_data_master_write, -- .write d_writedata => nios2_qsys_0_data_master_writedata, -- .writedata jtag_debug_module_debugaccess_to_roms => nios2_qsys_0_data_master_debugaccess, -- .debugaccess i_address => nios2_qsys_0_instruction_master_address, -- instruction_master.address i_read => nios2_qsys_0_instruction_master_read, -- .read i_readdata => nios2_qsys_0_instruction_master_readdata, -- .readdata i_waitrequest => nios2_qsys_0_instruction_master_waitrequest, -- .waitrequest d_irq => nios2_qsys_0_d_irq_irq, -- d_irq.irq jtag_debug_module_resetrequest => nios2_qsys_0_jtag_debug_module_reset_reset, -- jtag_debug_module_reset.reset jtag_debug_module_address => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_address, -- jtag_debug_module.address jtag_debug_module_byteenable => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_byteenable, -- .byteenable jtag_debug_module_debugaccess => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess, -- .debugaccess jtag_debug_module_read => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_read, -- .read jtag_debug_module_readdata => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_readdata, -- .readdata jtag_debug_module_waitrequest => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest jtag_debug_module_write => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_write, -- .write jtag_debug_module_writedata => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_writedata, -- .writedata no_ci_readra => open -- custom_instruction_master.readra ); onchip_memory2_0 : component niosII_system_onchip_memory2_0 port map ( clk => altpll_0_c1_clk, -- clk1.clk address => onchip_memory2_0_s1_translator_avalon_anti_slave_0_address, -- s1.address clken => onchip_memory2_0_s1_translator_avalon_anti_slave_0_clken, -- .clken chipselect => onchip_memory2_0_s1_translator_avalon_anti_slave_0_chipselect, -- .chipselect write => onchip_memory2_0_s1_translator_avalon_anti_slave_0_write, -- .write readdata => onchip_memory2_0_s1_translator_avalon_anti_slave_0_readdata, -- .readdata writedata => onchip_memory2_0_s1_translator_avalon_anti_slave_0_writedata, -- .writedata byteenable => onchip_memory2_0_s1_translator_avalon_anti_slave_0_byteenable, -- .byteenable reset => rst_controller_reset_out_reset, -- reset1.reset reset_req => rst_controller_reset_out_reset_req -- .reset_req ); sysid_qsys_0 : component niosII_system_sysid_qsys_0 port map ( clock => altpll_0_c1_clk, -- clk.clk reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n readdata => sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_readdata, -- control_slave.readdata address => sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_address(0) -- .address ); jtag_uart_0 : component niosII_system_jtag_uart_0 port map ( clk => altpll_0_c1_clk, -- clk.clk rst_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n av_chipselect => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect, -- avalon_jtag_slave.chipselect av_address => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_address(0), -- .address av_read_n => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read_ports_inv, -- .read_n av_readdata => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata, -- .readdata av_write_n => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write_ports_inv, -- .write_n av_writedata => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata, -- .writedata av_waitrequest => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest av_irq => irq_mapper_receiver1_irq -- irq.irq ); green_leds : component niosII_system_green_leds port map ( clk => altpll_0_c1_clk, -- clk.clk reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n address => green_leds_s1_translator_avalon_anti_slave_0_address, -- s1.address write_n => green_leds_s1_translator_avalon_anti_slave_0_write_ports_inv, -- .write_n writedata => green_leds_s1_translator_avalon_anti_slave_0_writedata, -- .writedata chipselect => green_leds_s1_translator_avalon_anti_slave_0_chipselect, -- .chipselect readdata => green_leds_s1_translator_avalon_anti_slave_0_readdata, -- .readdata out_port => green_leds_external_connection_export -- external_connection.export ); switches : component niosII_system_switches port map ( clk => altpll_0_c1_clk, -- clk.clk reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n address => switches_s1_translator_avalon_anti_slave_0_address, -- s1.address readdata => switches_s1_translator_avalon_anti_slave_0_readdata, -- .readdata in_port => switches_external_connection_export -- external_connection.export ); altpll_0 : component niosII_system_altpll_0 port map ( clk => clk_clk, -- inclk_interface.clk reset => rst_controller_001_reset_out_reset, -- inclk_interface_reset.reset read => altpll_0_pll_slave_translator_avalon_anti_slave_0_read, -- pll_slave.read write => altpll_0_pll_slave_translator_avalon_anti_slave_0_write, -- .write address => altpll_0_pll_slave_translator_avalon_anti_slave_0_address, -- .address readdata => altpll_0_pll_slave_translator_avalon_anti_slave_0_readdata, -- .readdata writedata => altpll_0_pll_slave_translator_avalon_anti_slave_0_writedata, -- .writedata c0 => altpll_0_c0_clk, -- c0.clk c1 => altpll_0_c1_clk, -- c1.clk areset => open, -- areset_conduit.export locked => open, -- locked_conduit.export phasedone => open -- phasedone_conduit.export ); sdram_0 : component niosII_system_sdram_0 port map ( clk => altpll_0_c1_clk, -- clk.clk reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n az_addr => sdram_0_s1_translator_avalon_anti_slave_0_address, -- s1.address az_be_n => sdram_0_s1_translator_avalon_anti_slave_0_byteenable_ports_inv, -- .byteenable_n az_cs => sdram_0_s1_translator_avalon_anti_slave_0_chipselect, -- .chipselect az_data => sdram_0_s1_translator_avalon_anti_slave_0_writedata, -- .writedata az_rd_n => sdram_0_s1_translator_avalon_anti_slave_0_read_ports_inv, -- .read_n az_wr_n => sdram_0_s1_translator_avalon_anti_slave_0_write_ports_inv, -- .write_n za_data => sdram_0_s1_translator_avalon_anti_slave_0_readdata, -- .readdata za_valid => sdram_0_s1_translator_avalon_anti_slave_0_readdatavalid, -- .readdatavalid za_waitrequest => sdram_0_s1_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest zs_addr => sdram_0_wire_addr, -- wire.export zs_ba => sdram_0_wire_ba, -- .export zs_cas_n => sdram_0_wire_cas_n, -- .export zs_cke => sdram_0_wire_cke, -- .export zs_cs_n => sdram_0_wire_cs_n, -- .export zs_dq => sdram_0_wire_dq, -- .export zs_dqm => sdram_0_wire_dqm, -- .export zs_ras_n => sdram_0_wire_ras_n, -- .export zs_we_n => sdram_0_wire_we_n -- .export ); sram_0 : component niosII_system_sram_0 port map ( clk => altpll_0_c1_clk, -- clock_reset.clk reset => rst_controller_reset_out_reset, -- clock_reset_reset.reset SRAM_DQ => sram_0_external_interface_DQ, -- external_interface.export SRAM_ADDR => sram_0_external_interface_ADDR, -- .export SRAM_LB_N => sram_0_external_interface_LB_N, -- .export SRAM_UB_N => sram_0_external_interface_UB_N, -- .export SRAM_CE_N => sram_0_external_interface_CE_N, -- .export SRAM_OE_N => sram_0_external_interface_OE_N, -- .export SRAM_WE_N => sram_0_external_interface_WE_N, -- .export address => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_address, -- avalon_sram_slave.address byteenable => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_byteenable, -- .byteenable read => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_read, -- .read write => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_write, -- .write writedata => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_writedata, -- .writedata readdata => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_readdata, -- .readdata readdatavalid => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_readdatavalid -- .readdatavalid ); timer_0 : component niosII_system_timer_0 port map ( clk => altpll_0_c1_clk, -- clk.clk reset_n => rst_controller_reset_out_reset_ports_inv, -- reset.reset_n address => timer_0_s1_translator_avalon_anti_slave_0_address, -- s1.address writedata => timer_0_s1_translator_avalon_anti_slave_0_writedata, -- .writedata readdata => timer_0_s1_translator_avalon_anti_slave_0_readdata, -- .readdata chipselect => timer_0_s1_translator_avalon_anti_slave_0_chipselect, -- .chipselect write_n => timer_0_s1_translator_avalon_anti_slave_0_write_ports_inv, -- .write_n irq => irq_mapper_receiver0_irq -- irq.irq ); usb_0 : component niosII_system_usb_0 port map ( clk => altpll_0_c1_clk, -- clock_reset.clk reset => rst_controller_reset_out_reset, -- clock_reset_reset.reset address => usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_address, -- avalon_usb_slave.address chipselect => usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_chipselect, -- .chipselect read => usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_read, -- .read write => usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_write, -- .write writedata => usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_writedata, -- .writedata readdata => usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_readdata, -- .readdata irq => irq_mapper_receiver2_irq, -- interrupt.irq OTG_INT1 => usb_0_external_interface_INT1, -- external_interface.export OTG_DATA => usb_0_external_interface_DATA, -- .export OTG_RST_N => usb_0_external_interface_RST_N, -- .export OTG_ADDR => usb_0_external_interface_ADDR, -- .export OTG_CS_N => usb_0_external_interface_CS_N, -- .export OTG_RD_N => usb_0_external_interface_RD_N, -- .export OTG_WR_N => usb_0_external_interface_WR_N, -- .export OTG_INT0 => usb_0_external_interface_INT0 -- .export ); rs232_0 : component niosII_system_rs232_0 port map ( clk => altpll_0_c1_clk, -- clock_reset.clk reset => rst_controller_reset_out_reset, -- clock_reset_reset.reset address => rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_address(0), -- avalon_rs232_slave.address chipselect => rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_chipselect, -- .chipselect byteenable => rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_byteenable, -- .byteenable read => rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_read, -- .read write => rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_write, -- .write writedata => rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_writedata, -- .writedata readdata => rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_readdata, -- .readdata irq => irq_mapper_receiver3_irq, -- interrupt.irq UART_RXD => rs232_0_external_interface_RXD, -- external_interface.export UART_TXD => rs232_0_external_interface_TXD -- .export ); generic_tristate_controller_0 : component niosII_system_generic_tristate_controller_0 generic map ( TCM_ADDRESS_W => 22, TCM_DATA_W => 8, TCM_BYTEENABLE_W => 1, TCM_READ_WAIT => 160, TCM_WRITE_WAIT => 160, TCM_SETUP_WAIT => 40, TCM_DATA_HOLD => 40, TCM_TURNAROUND_TIME => 2, TCM_TIMING_UNITS => 0, TCM_READLATENCY => 2, TCM_SYMBOLS_PER_WORD => 1, USE_READDATA => 1, USE_WRITEDATA => 1, USE_READ => 1, USE_WRITE => 1, USE_BYTEENABLE => 1, USE_CHIPSELECT => 1, USE_LOCK => 0, USE_ADDRESS => 1, USE_WAITREQUEST => 0, USE_WRITEBYTEENABLE => 0, USE_OUTPUTENABLE => 0, USE_RESETREQUEST => 0, USE_IRQ => 0, USE_RESET_OUTPUT => 0, ACTIVE_LOW_READ => 1, ACTIVE_LOW_LOCK => 0, ACTIVE_LOW_WRITE => 1, ACTIVE_LOW_CHIPSELECT => 1, ACTIVE_LOW_BYTEENABLE => 0, ACTIVE_LOW_OUTPUTENABLE => 0, ACTIVE_LOW_WRITEBYTEENABLE => 0, ACTIVE_LOW_WAITREQUEST => 0, ACTIVE_LOW_BEGINTRANSFER => 0, CHIPSELECT_THROUGH_READLATENCY => 0 ) port map ( clk_clk => altpll_0_c1_clk, -- clk.clk reset_reset => rst_controller_reset_out_reset, -- reset.reset uas_address => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_address, -- uas.address uas_burstcount => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_burstcount, -- .burstcount uas_read => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_read, -- .read uas_write => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_write, -- .write uas_waitrequest => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest uas_readdatavalid => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_readdatavalid, -- .readdatavalid uas_byteenable => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_byteenable, -- .byteenable uas_readdata => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_readdata, -- .readdata uas_writedata => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_writedata, -- .writedata uas_lock => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_lock, -- .lock uas_debugaccess => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_debugaccess, -- .debugaccess tcm_write_n_out => generic_tristate_controller_0_tcm_write_n_out, -- tcm.write_n_out tcm_read_n_out => generic_tristate_controller_0_tcm_read_n_out, -- .read_n_out tcm_begintransfer_out => generic_tristate_controller_0_tcm_begintransfer_out, -- .begintransfer_out tcm_chipselect_n_out => generic_tristate_controller_0_tcm_chipselect_n_out, -- .chipselect_n_out tcm_request => generic_tristate_controller_0_tcm_request, -- .request tcm_grant => generic_tristate_controller_0_tcm_grant, -- .grant tcm_address_out => generic_tristate_controller_0_tcm_address_out, -- .address_out tcm_byteenable_out => generic_tristate_controller_0_tcm_byteenable_out, -- .byteenable_out tcm_data_out => generic_tristate_controller_0_tcm_data_out, -- .data_out tcm_data_outen => generic_tristate_controller_0_tcm_data_outen, -- .data_outen tcm_data_in => generic_tristate_controller_0_tcm_data_in -- .data_in ); tristate_conduit_bridge_0 : component niosII_system_tristate_conduit_bridge_0 port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- reset.reset request => tristate_conduit_pin_sharer_0_tcm_request, -- tcs.request grant => tristate_conduit_pin_sharer_0_tcm_grant, -- .grant tcs_generic_tristate_controller_0_tcm_read_n_out => tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_read_n_out_out, -- .generic_tristate_controller_0_tcm_read_n_out_out tcs_generic_tristate_controller_0_tcm_data_out => tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_data_out_out, -- .generic_tristate_controller_0_tcm_data_out_out tcs_generic_tristate_controller_0_tcm_data_outen => tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_data_out_outen, -- .generic_tristate_controller_0_tcm_data_out_outen tcs_generic_tristate_controller_0_tcm_data_in => tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_data_out_in, -- .generic_tristate_controller_0_tcm_data_out_in tcs_generic_tristate_controller_0_tcm_chipselect_n_out => tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_chipselect_n_out_out, -- .generic_tristate_controller_0_tcm_chipselect_n_out_out tcs_generic_tristate_controller_0_tcm_write_n_out => tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_write_n_out_out, -- .generic_tristate_controller_0_tcm_write_n_out_out tcs_generic_tristate_controller_0_tcm_byteenable_out => tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_byteenable_out_out, -- .generic_tristate_controller_0_tcm_byteenable_out_out tcs_generic_tristate_controller_0_tcm_begintransfer_out => tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_begintransfer_out_out, -- .generic_tristate_controller_0_tcm_begintransfer_out_out tcs_generic_tristate_controller_0_tcm_address_out => tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_address_out_out, -- .generic_tristate_controller_0_tcm_address_out_out generic_tristate_controller_0_tcm_read_n_out => tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_read_n_out, -- out.generic_tristate_controller_0_tcm_read_n_out generic_tristate_controller_0_tcm_data_out => tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_data_out, -- .generic_tristate_controller_0_tcm_data_out generic_tristate_controller_0_tcm_chipselect_n_out => tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_chipselect_n_out, -- .generic_tristate_controller_0_tcm_chipselect_n_out generic_tristate_controller_0_tcm_write_n_out => tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_write_n_out, -- .generic_tristate_controller_0_tcm_write_n_out generic_tristate_controller_0_tcm_byteenable_out => tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_byteenable_out, -- .generic_tristate_controller_0_tcm_byteenable_out generic_tristate_controller_0_tcm_begintransfer_out => tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_begintransfer_out, -- .generic_tristate_controller_0_tcm_begintransfer_out generic_tristate_controller_0_tcm_address_out => tristate_conduit_bridge_0_out_generic_tristate_controller_0_tcm_address_out -- .generic_tristate_controller_0_tcm_address_out ); tristate_conduit_pin_sharer_0 : component niosII_system_tristate_conduit_pin_sharer_0 port map ( clk_clk => altpll_0_c1_clk, -- clk.clk reset_reset => rst_controller_reset_out_reset, -- reset.reset request => tristate_conduit_pin_sharer_0_tcm_request, -- tcm.request grant => tristate_conduit_pin_sharer_0_tcm_grant, -- .grant generic_tristate_controller_0_tcm_byteenable_out => tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_byteenable_out_out, -- .generic_tristate_controller_0_tcm_byteenable_out_out generic_tristate_controller_0_tcm_address_out => tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_address_out_out, -- .generic_tristate_controller_0_tcm_address_out_out generic_tristate_controller_0_tcm_read_n_out => tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_read_n_out_out, -- .generic_tristate_controller_0_tcm_read_n_out_out generic_tristate_controller_0_tcm_write_n_out => tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_write_n_out_out, -- .generic_tristate_controller_0_tcm_write_n_out_out generic_tristate_controller_0_tcm_data_out => tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_data_out_out, -- .generic_tristate_controller_0_tcm_data_out_out generic_tristate_controller_0_tcm_data_in => tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_data_out_in, -- .generic_tristate_controller_0_tcm_data_out_in generic_tristate_controller_0_tcm_data_outen => tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_data_out_outen, -- .generic_tristate_controller_0_tcm_data_out_outen generic_tristate_controller_0_tcm_chipselect_n_out => tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_chipselect_n_out_out, -- .generic_tristate_controller_0_tcm_chipselect_n_out_out generic_tristate_controller_0_tcm_begintransfer_out => tristate_conduit_pin_sharer_0_tcm_generic_tristate_controller_0_tcm_begintransfer_out_out, -- .generic_tristate_controller_0_tcm_begintransfer_out_out tcs0_request => generic_tristate_controller_0_tcm_request, -- tcs0.request tcs0_grant => generic_tristate_controller_0_tcm_grant, -- .grant tcs0_byteenable_out(0) => generic_tristate_controller_0_tcm_byteenable_out, -- .byteenable_out tcs0_address_out => generic_tristate_controller_0_tcm_address_out, -- .address_out tcs0_read_n_out(0) => generic_tristate_controller_0_tcm_read_n_out, -- .read_n_out tcs0_write_n_out(0) => generic_tristate_controller_0_tcm_write_n_out, -- .write_n_out tcs0_data_out => generic_tristate_controller_0_tcm_data_out, -- .data_out tcs0_data_in => generic_tristate_controller_0_tcm_data_in, -- .data_in tcs0_data_outen => generic_tristate_controller_0_tcm_data_outen, -- .data_outen tcs0_chipselect_n_out(0) => generic_tristate_controller_0_tcm_chipselect_n_out, -- .chipselect_n_out tcs0_begintransfer_out(0) => generic_tristate_controller_0_tcm_begintransfer_out -- .begintransfer_out ); nios2_qsys_0_instruction_master_translator : component niosii_system_nios2_qsys_0_instruction_master_translator generic map ( AV_ADDRESS_W => 25, AV_DATA_W => 32, AV_BURSTCOUNT_W => 1, AV_BYTEENABLE_W => 4, UAV_ADDRESS_W => 25, UAV_BURSTCOUNT_W => 3, USE_READ => 1, USE_WRITE => 0, USE_BEGINBURSTTRANSFER => 0, USE_BEGINTRANSFER => 0, USE_CHIPSELECT => 0, USE_BURSTCOUNT => 0, USE_READDATAVALID => 0, USE_WAITREQUEST => 1, USE_READRESPONSE => 0, USE_WRITERESPONSE => 0, AV_SYMBOLS_PER_WORD => 4, AV_ADDRESS_SYMBOLS => 1, AV_BURSTCOUNT_SYMBOLS => 0, AV_CONSTANT_BURST_BEHAVIOR => 0, UAV_CONSTANT_BURST_BEHAVIOR => 0, AV_LINEWRAPBURSTS => 1, AV_REGISTERINCOMINGSIGNALS => 0 ) port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- reset.reset uav_address => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_address, -- avalon_universal_master_0.address uav_burstcount => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_burstcount, -- .burstcount uav_read => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_read, -- .read uav_write => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_write, -- .write uav_waitrequest => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_waitrequest, -- .waitrequest uav_readdatavalid => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdatavalid, -- .readdatavalid uav_byteenable => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_byteenable, -- .byteenable uav_readdata => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdata, -- .readdata uav_writedata => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_writedata, -- .writedata uav_lock => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_lock, -- .lock uav_debugaccess => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_debugaccess, -- .debugaccess av_address => nios2_qsys_0_instruction_master_address, -- avalon_anti_master_0.address av_waitrequest => nios2_qsys_0_instruction_master_waitrequest, -- .waitrequest av_read => nios2_qsys_0_instruction_master_read, -- .read av_readdata => nios2_qsys_0_instruction_master_readdata, -- .readdata av_burstcount => "1", -- (terminated) av_byteenable => "1111", -- (terminated) av_beginbursttransfer => '0', -- (terminated) av_begintransfer => '0', -- (terminated) av_chipselect => '0', -- (terminated) av_readdatavalid => open, -- (terminated) av_write => '0', -- (terminated) av_writedata => "00000000000000000000000000000000", -- (terminated) av_lock => '0', -- (terminated) av_debugaccess => '0', -- (terminated) uav_clken => open, -- (terminated) av_clken => '1', -- (terminated) uav_response => "00", -- (terminated) av_response => open, -- (terminated) uav_writeresponserequest => open, -- (terminated) uav_writeresponsevalid => '0', -- (terminated) av_writeresponserequest => '0', -- (terminated) av_writeresponsevalid => open -- (terminated) ); nios2_qsys_0_data_master_translator : component niosii_system_nios2_qsys_0_data_master_translator generic map ( AV_ADDRESS_W => 25, AV_DATA_W => 32, AV_BURSTCOUNT_W => 1, AV_BYTEENABLE_W => 4, UAV_ADDRESS_W => 25, UAV_BURSTCOUNT_W => 3, USE_READ => 1, USE_WRITE => 1, USE_BEGINBURSTTRANSFER => 0, USE_BEGINTRANSFER => 0, USE_CHIPSELECT => 0, USE_BURSTCOUNT => 0, USE_READDATAVALID => 0, USE_WAITREQUEST => 1, USE_READRESPONSE => 0, USE_WRITERESPONSE => 0, AV_SYMBOLS_PER_WORD => 4, AV_ADDRESS_SYMBOLS => 1, AV_BURSTCOUNT_SYMBOLS => 0, AV_CONSTANT_BURST_BEHAVIOR => 0, UAV_CONSTANT_BURST_BEHAVIOR => 0, AV_LINEWRAPBURSTS => 0, AV_REGISTERINCOMINGSIGNALS => 1 ) port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- reset.reset uav_address => nios2_qsys_0_data_master_translator_avalon_universal_master_0_address, -- avalon_universal_master_0.address uav_burstcount => nios2_qsys_0_data_master_translator_avalon_universal_master_0_burstcount, -- .burstcount uav_read => nios2_qsys_0_data_master_translator_avalon_universal_master_0_read, -- .read uav_write => nios2_qsys_0_data_master_translator_avalon_universal_master_0_write, -- .write uav_waitrequest => nios2_qsys_0_data_master_translator_avalon_universal_master_0_waitrequest, -- .waitrequest uav_readdatavalid => nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdatavalid, -- .readdatavalid uav_byteenable => nios2_qsys_0_data_master_translator_avalon_universal_master_0_byteenable, -- .byteenable uav_readdata => nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdata, -- .readdata uav_writedata => nios2_qsys_0_data_master_translator_avalon_universal_master_0_writedata, -- .writedata uav_lock => nios2_qsys_0_data_master_translator_avalon_universal_master_0_lock, -- .lock uav_debugaccess => nios2_qsys_0_data_master_translator_avalon_universal_master_0_debugaccess, -- .debugaccess av_address => nios2_qsys_0_data_master_address, -- avalon_anti_master_0.address av_waitrequest => nios2_qsys_0_data_master_waitrequest, -- .waitrequest av_byteenable => nios2_qsys_0_data_master_byteenable, -- .byteenable av_read => nios2_qsys_0_data_master_read, -- .read av_readdata => nios2_qsys_0_data_master_readdata, -- .readdata av_write => nios2_qsys_0_data_master_write, -- .write av_writedata => nios2_qsys_0_data_master_writedata, -- .writedata av_debugaccess => nios2_qsys_0_data_master_debugaccess, -- .debugaccess av_burstcount => "1", -- (terminated) av_beginbursttransfer => '0', -- (terminated) av_begintransfer => '0', -- (terminated) av_chipselect => '0', -- (terminated) av_readdatavalid => open, -- (terminated) av_lock => '0', -- (terminated) uav_clken => open, -- (terminated) av_clken => '1', -- (terminated) uav_response => "00", -- (terminated) av_response => open, -- (terminated) uav_writeresponserequest => open, -- (terminated) uav_writeresponsevalid => '0', -- (terminated) av_writeresponserequest => '0', -- (terminated) av_writeresponsevalid => open -- (terminated) ); nios2_qsys_0_jtag_debug_module_translator : component niosii_system_nios2_qsys_0_jtag_debug_module_translator generic map ( AV_ADDRESS_W => 9, AV_DATA_W => 32, UAV_DATA_W => 32, AV_BURSTCOUNT_W => 1, AV_BYTEENABLE_W => 4, UAV_BYTEENABLE_W => 4, UAV_ADDRESS_W => 25, UAV_BURSTCOUNT_W => 3, AV_READLATENCY => 0, USE_READDATAVALID => 0, USE_WAITREQUEST => 1, USE_UAV_CLKEN => 0, USE_READRESPONSE => 0, USE_WRITERESPONSE => 0, AV_SYMBOLS_PER_WORD => 4, AV_ADDRESS_SYMBOLS => 0, AV_BURSTCOUNT_SYMBOLS => 0, AV_CONSTANT_BURST_BEHAVIOR => 0, UAV_CONSTANT_BURST_BEHAVIOR => 0, AV_REQUIRE_UNALIGNED_ADDRESSES => 0, CHIPSELECT_THROUGH_READLATENCY => 0, AV_READ_WAIT_CYCLES => 1, AV_WRITE_WAIT_CYCLES => 0, AV_SETUP_WAIT_CYCLES => 0, AV_DATA_HOLD_CYCLES => 0 ) port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- reset.reset uav_address => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address uav_burstcount => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount uav_read => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read, -- .read uav_write => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write, -- .write uav_waitrequest => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest uav_readdatavalid => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid uav_byteenable => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable uav_readdata => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata uav_writedata => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata uav_lock => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock uav_debugaccess => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess av_address => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address av_write => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_write, -- .write av_read => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_read, -- .read av_readdata => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_readdata, -- .readdata av_writedata => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_writedata, -- .writedata av_byteenable => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_byteenable, -- .byteenable av_waitrequest => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest av_debugaccess => nios2_qsys_0_jtag_debug_module_translator_avalon_anti_slave_0_debugaccess, -- .debugaccess av_begintransfer => open, -- (terminated) av_beginbursttransfer => open, -- (terminated) av_burstcount => open, -- (terminated) av_readdatavalid => '0', -- (terminated) av_writebyteenable => open, -- (terminated) av_lock => open, -- (terminated) av_chipselect => open, -- (terminated) av_clken => open, -- (terminated) uav_clken => '0', -- (terminated) av_outputenable => open, -- (terminated) uav_response => open, -- (terminated) av_response => "00", -- (terminated) uav_writeresponserequest => '0', -- (terminated) uav_writeresponsevalid => open, -- (terminated) av_writeresponserequest => open, -- (terminated) av_writeresponsevalid => '0' -- (terminated) ); sdram_0_s1_translator : component niosii_system_sdram_0_s1_translator generic map ( AV_ADDRESS_W => 22, AV_DATA_W => 16, UAV_DATA_W => 16, AV_BURSTCOUNT_W => 1, AV_BYTEENABLE_W => 2, UAV_BYTEENABLE_W => 2, UAV_ADDRESS_W => 25, UAV_BURSTCOUNT_W => 2, AV_READLATENCY => 0, USE_READDATAVALID => 1, USE_WAITREQUEST => 1, USE_UAV_CLKEN => 0, USE_READRESPONSE => 0, USE_WRITERESPONSE => 0, AV_SYMBOLS_PER_WORD => 2, AV_ADDRESS_SYMBOLS => 0, AV_BURSTCOUNT_SYMBOLS => 0, AV_CONSTANT_BURST_BEHAVIOR => 0, UAV_CONSTANT_BURST_BEHAVIOR => 0, AV_REQUIRE_UNALIGNED_ADDRESSES => 0, CHIPSELECT_THROUGH_READLATENCY => 0, AV_READ_WAIT_CYCLES => 1, AV_WRITE_WAIT_CYCLES => 0, AV_SETUP_WAIT_CYCLES => 0, AV_DATA_HOLD_CYCLES => 0 ) port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- reset.reset uav_address => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address uav_burstcount => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount uav_read => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_read, -- .read uav_write => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_write, -- .write uav_waitrequest => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest uav_readdatavalid => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid uav_byteenable => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable uav_readdata => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata uav_writedata => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata uav_lock => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock uav_debugaccess => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess av_address => sdram_0_s1_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address av_write => sdram_0_s1_translator_avalon_anti_slave_0_write, -- .write av_read => sdram_0_s1_translator_avalon_anti_slave_0_read, -- .read av_readdata => sdram_0_s1_translator_avalon_anti_slave_0_readdata, -- .readdata av_writedata => sdram_0_s1_translator_avalon_anti_slave_0_writedata, -- .writedata av_byteenable => sdram_0_s1_translator_avalon_anti_slave_0_byteenable, -- .byteenable av_readdatavalid => sdram_0_s1_translator_avalon_anti_slave_0_readdatavalid, -- .readdatavalid av_waitrequest => sdram_0_s1_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest av_chipselect => sdram_0_s1_translator_avalon_anti_slave_0_chipselect, -- .chipselect av_begintransfer => open, -- (terminated) av_beginbursttransfer => open, -- (terminated) av_burstcount => open, -- (terminated) av_writebyteenable => open, -- (terminated) av_lock => open, -- (terminated) av_clken => open, -- (terminated) uav_clken => '0', -- (terminated) av_debugaccess => open, -- (terminated) av_outputenable => open, -- (terminated) uav_response => open, -- (terminated) av_response => "00", -- (terminated) uav_writeresponserequest => '0', -- (terminated) uav_writeresponsevalid => open, -- (terminated) av_writeresponserequest => open, -- (terminated) av_writeresponsevalid => '0' -- (terminated) ); onchip_memory2_0_s1_translator : component niosii_system_onchip_memory2_0_s1_translator generic map ( AV_ADDRESS_W => 12, AV_DATA_W => 32, UAV_DATA_W => 32, AV_BURSTCOUNT_W => 1, AV_BYTEENABLE_W => 4, UAV_BYTEENABLE_W => 4, UAV_ADDRESS_W => 25, UAV_BURSTCOUNT_W => 3, AV_READLATENCY => 1, USE_READDATAVALID => 0, USE_WAITREQUEST => 0, USE_UAV_CLKEN => 0, USE_READRESPONSE => 0, USE_WRITERESPONSE => 0, AV_SYMBOLS_PER_WORD => 4, AV_ADDRESS_SYMBOLS => 0, AV_BURSTCOUNT_SYMBOLS => 0, AV_CONSTANT_BURST_BEHAVIOR => 0, UAV_CONSTANT_BURST_BEHAVIOR => 0, AV_REQUIRE_UNALIGNED_ADDRESSES => 0, CHIPSELECT_THROUGH_READLATENCY => 0, AV_READ_WAIT_CYCLES => 0, AV_WRITE_WAIT_CYCLES => 0, AV_SETUP_WAIT_CYCLES => 0, AV_DATA_HOLD_CYCLES => 0 ) port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- reset.reset uav_address => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address uav_burstcount => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount uav_read => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_read, -- .read uav_write => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_write, -- .write uav_waitrequest => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest uav_readdatavalid => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid uav_byteenable => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable uav_readdata => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata uav_writedata => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata uav_lock => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock uav_debugaccess => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess av_address => onchip_memory2_0_s1_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address av_write => onchip_memory2_0_s1_translator_avalon_anti_slave_0_write, -- .write av_readdata => onchip_memory2_0_s1_translator_avalon_anti_slave_0_readdata, -- .readdata av_writedata => onchip_memory2_0_s1_translator_avalon_anti_slave_0_writedata, -- .writedata av_byteenable => onchip_memory2_0_s1_translator_avalon_anti_slave_0_byteenable, -- .byteenable av_chipselect => onchip_memory2_0_s1_translator_avalon_anti_slave_0_chipselect, -- .chipselect av_clken => onchip_memory2_0_s1_translator_avalon_anti_slave_0_clken, -- .clken av_read => open, -- (terminated) av_begintransfer => open, -- (terminated) av_beginbursttransfer => open, -- (terminated) av_burstcount => open, -- (terminated) av_readdatavalid => '0', -- (terminated) av_waitrequest => '0', -- (terminated) av_writebyteenable => open, -- (terminated) av_lock => open, -- (terminated) uav_clken => '0', -- (terminated) av_debugaccess => open, -- (terminated) av_outputenable => open, -- (terminated) uav_response => open, -- (terminated) av_response => "00", -- (terminated) uav_writeresponserequest => '0', -- (terminated) uav_writeresponsevalid => open, -- (terminated) av_writeresponserequest => open, -- (terminated) av_writeresponsevalid => '0' -- (terminated) ); sram_0_avalon_sram_slave_translator : component niosii_system_sram_0_avalon_sram_slave_translator generic map ( AV_ADDRESS_W => 18, AV_DATA_W => 16, UAV_DATA_W => 16, AV_BURSTCOUNT_W => 1, AV_BYTEENABLE_W => 2, UAV_BYTEENABLE_W => 2, UAV_ADDRESS_W => 25, UAV_BURSTCOUNT_W => 2, AV_READLATENCY => 0, USE_READDATAVALID => 1, USE_WAITREQUEST => 0, USE_UAV_CLKEN => 0, USE_READRESPONSE => 0, USE_WRITERESPONSE => 0, AV_SYMBOLS_PER_WORD => 2, AV_ADDRESS_SYMBOLS => 0, AV_BURSTCOUNT_SYMBOLS => 0, AV_CONSTANT_BURST_BEHAVIOR => 0, UAV_CONSTANT_BURST_BEHAVIOR => 0, AV_REQUIRE_UNALIGNED_ADDRESSES => 0, CHIPSELECT_THROUGH_READLATENCY => 0, AV_READ_WAIT_CYCLES => 0, AV_WRITE_WAIT_CYCLES => 0, AV_SETUP_WAIT_CYCLES => 0, AV_DATA_HOLD_CYCLES => 0 ) port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- reset.reset uav_address => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address uav_burstcount => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount uav_read => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read uav_write => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write uav_waitrequest => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest uav_readdatavalid => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid uav_byteenable => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable uav_readdata => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata uav_writedata => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata uav_lock => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock uav_debugaccess => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess av_address => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address av_write => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_write, -- .write av_read => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_read, -- .read av_readdata => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_readdata, -- .readdata av_writedata => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_writedata, -- .writedata av_byteenable => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_byteenable, -- .byteenable av_readdatavalid => sram_0_avalon_sram_slave_translator_avalon_anti_slave_0_readdatavalid, -- .readdatavalid av_begintransfer => open, -- (terminated) av_beginbursttransfer => open, -- (terminated) av_burstcount => open, -- (terminated) av_waitrequest => '0', -- (terminated) av_writebyteenable => open, -- (terminated) av_lock => open, -- (terminated) av_chipselect => open, -- (terminated) av_clken => open, -- (terminated) uav_clken => '0', -- (terminated) av_debugaccess => open, -- (terminated) av_outputenable => open, -- (terminated) uav_response => open, -- (terminated) av_response => "00", -- (terminated) uav_writeresponserequest => '0', -- (terminated) uav_writeresponsevalid => open, -- (terminated) av_writeresponserequest => open, -- (terminated) av_writeresponsevalid => '0' -- (terminated) ); generic_tristate_controller_0_uas_translator : component niosii_system_generic_tristate_controller_0_uas_translator generic map ( AV_ADDRESS_W => 22, AV_DATA_W => 8, UAV_DATA_W => 8, AV_BURSTCOUNT_W => 1, AV_BYTEENABLE_W => 1, UAV_BYTEENABLE_W => 1, UAV_ADDRESS_W => 25, UAV_BURSTCOUNT_W => 1, AV_READLATENCY => 0, USE_READDATAVALID => 1, USE_WAITREQUEST => 1, USE_UAV_CLKEN => 0, USE_READRESPONSE => 0, USE_WRITERESPONSE => 0, AV_SYMBOLS_PER_WORD => 1, AV_ADDRESS_SYMBOLS => 1, AV_BURSTCOUNT_SYMBOLS => 1, AV_CONSTANT_BURST_BEHAVIOR => 0, UAV_CONSTANT_BURST_BEHAVIOR => 0, AV_REQUIRE_UNALIGNED_ADDRESSES => 0, CHIPSELECT_THROUGH_READLATENCY => 0, AV_READ_WAIT_CYCLES => 0, AV_WRITE_WAIT_CYCLES => 0, AV_SETUP_WAIT_CYCLES => 0, AV_DATA_HOLD_CYCLES => 0 ) port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- reset.reset uav_address => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address uav_burstcount => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount uav_read => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_read, -- .read uav_write => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_write, -- .write uav_waitrequest => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest uav_readdatavalid => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid uav_byteenable => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable uav_readdata => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata uav_writedata => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata uav_lock => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock uav_debugaccess => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess av_address => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address av_write => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_write, -- .write av_read => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_read, -- .read av_readdata => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_readdata, -- .readdata av_writedata => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_writedata, -- .writedata av_burstcount => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_burstcount, -- .burstcount av_byteenable => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_byteenable, -- .byteenable av_readdatavalid => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_readdatavalid, -- .readdatavalid av_waitrequest => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest av_lock => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_lock, -- .lock av_debugaccess => generic_tristate_controller_0_uas_translator_avalon_anti_slave_0_debugaccess, -- .debugaccess av_begintransfer => open, -- (terminated) av_beginbursttransfer => open, -- (terminated) av_writebyteenable => open, -- (terminated) av_chipselect => open, -- (terminated) av_clken => open, -- (terminated) uav_clken => '0', -- (terminated) av_outputenable => open, -- (terminated) uav_response => open, -- (terminated) av_response => "00", -- (terminated) uav_writeresponserequest => '0', -- (terminated) uav_writeresponsevalid => open, -- (terminated) av_writeresponserequest => open, -- (terminated) av_writeresponsevalid => '0' -- (terminated) ); jtag_uart_0_avalon_jtag_slave_translator : component niosii_system_jtag_uart_0_avalon_jtag_slave_translator generic map ( AV_ADDRESS_W => 1, AV_DATA_W => 32, UAV_DATA_W => 32, AV_BURSTCOUNT_W => 1, AV_BYTEENABLE_W => 1, UAV_BYTEENABLE_W => 4, UAV_ADDRESS_W => 25, UAV_BURSTCOUNT_W => 3, AV_READLATENCY => 0, USE_READDATAVALID => 0, USE_WAITREQUEST => 1, USE_UAV_CLKEN => 0, USE_READRESPONSE => 0, USE_WRITERESPONSE => 0, AV_SYMBOLS_PER_WORD => 4, AV_ADDRESS_SYMBOLS => 0, AV_BURSTCOUNT_SYMBOLS => 0, AV_CONSTANT_BURST_BEHAVIOR => 0, UAV_CONSTANT_BURST_BEHAVIOR => 0, AV_REQUIRE_UNALIGNED_ADDRESSES => 0, CHIPSELECT_THROUGH_READLATENCY => 0, AV_READ_WAIT_CYCLES => 1, AV_WRITE_WAIT_CYCLES => 0, AV_SETUP_WAIT_CYCLES => 0, AV_DATA_HOLD_CYCLES => 0 ) port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- reset.reset uav_address => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address uav_burstcount => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount uav_read => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read uav_write => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write uav_waitrequest => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest uav_readdatavalid => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid uav_byteenable => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable uav_readdata => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata uav_writedata => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata uav_lock => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock uav_debugaccess => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess av_address => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address av_write => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write, -- .write av_read => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read, -- .read av_readdata => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_readdata, -- .readdata av_writedata => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_writedata, -- .writedata av_waitrequest => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_waitrequest, -- .waitrequest av_chipselect => jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_chipselect, -- .chipselect av_begintransfer => open, -- (terminated) av_beginbursttransfer => open, -- (terminated) av_burstcount => open, -- (terminated) av_byteenable => open, -- (terminated) av_readdatavalid => '0', -- (terminated) av_writebyteenable => open, -- (terminated) av_lock => open, -- (terminated) av_clken => open, -- (terminated) uav_clken => '0', -- (terminated) av_debugaccess => open, -- (terminated) av_outputenable => open, -- (terminated) uav_response => open, -- (terminated) av_response => "00", -- (terminated) uav_writeresponserequest => '0', -- (terminated) uav_writeresponsevalid => open, -- (terminated) av_writeresponserequest => open, -- (terminated) av_writeresponsevalid => '0' -- (terminated) ); sysid_qsys_0_control_slave_translator : component niosii_system_sysid_qsys_0_control_slave_translator generic map ( AV_ADDRESS_W => 1, AV_DATA_W => 32, UAV_DATA_W => 32, AV_BURSTCOUNT_W => 1, AV_BYTEENABLE_W => 4, UAV_BYTEENABLE_W => 4, UAV_ADDRESS_W => 25, UAV_BURSTCOUNT_W => 3, AV_READLATENCY => 0, USE_READDATAVALID => 0, USE_WAITREQUEST => 0, USE_UAV_CLKEN => 0, USE_READRESPONSE => 0, USE_WRITERESPONSE => 0, AV_SYMBOLS_PER_WORD => 4, AV_ADDRESS_SYMBOLS => 0, AV_BURSTCOUNT_SYMBOLS => 0, AV_CONSTANT_BURST_BEHAVIOR => 0, UAV_CONSTANT_BURST_BEHAVIOR => 0, AV_REQUIRE_UNALIGNED_ADDRESSES => 0, CHIPSELECT_THROUGH_READLATENCY => 0, AV_READ_WAIT_CYCLES => 1, AV_WRITE_WAIT_CYCLES => 0, AV_SETUP_WAIT_CYCLES => 0, AV_DATA_HOLD_CYCLES => 0 ) port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- reset.reset uav_address => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address uav_burstcount => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount uav_read => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read uav_write => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write uav_waitrequest => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest uav_readdatavalid => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid uav_byteenable => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable uav_readdata => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata uav_writedata => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata uav_lock => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock uav_debugaccess => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess av_address => sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address av_readdata => sysid_qsys_0_control_slave_translator_avalon_anti_slave_0_readdata, -- .readdata av_write => open, -- (terminated) av_read => open, -- (terminated) av_writedata => open, -- (terminated) av_begintransfer => open, -- (terminated) av_beginbursttransfer => open, -- (terminated) av_burstcount => open, -- (terminated) av_byteenable => open, -- (terminated) av_readdatavalid => '0', -- (terminated) av_waitrequest => '0', -- (terminated) av_writebyteenable => open, -- (terminated) av_lock => open, -- (terminated) av_chipselect => open, -- (terminated) av_clken => open, -- (terminated) uav_clken => '0', -- (terminated) av_debugaccess => open, -- (terminated) av_outputenable => open, -- (terminated) uav_response => open, -- (terminated) av_response => "00", -- (terminated) uav_writeresponserequest => '0', -- (terminated) uav_writeresponsevalid => open, -- (terminated) av_writeresponserequest => open, -- (terminated) av_writeresponsevalid => '0' -- (terminated) ); green_leds_s1_translator : component niosii_system_green_leds_s1_translator generic map ( AV_ADDRESS_W => 2, AV_DATA_W => 32, UAV_DATA_W => 32, AV_BURSTCOUNT_W => 1, AV_BYTEENABLE_W => 1, UAV_BYTEENABLE_W => 4, UAV_ADDRESS_W => 25, UAV_BURSTCOUNT_W => 3, AV_READLATENCY => 0, USE_READDATAVALID => 0, USE_WAITREQUEST => 0, USE_UAV_CLKEN => 0, USE_READRESPONSE => 0, USE_WRITERESPONSE => 0, AV_SYMBOLS_PER_WORD => 4, AV_ADDRESS_SYMBOLS => 0, AV_BURSTCOUNT_SYMBOLS => 0, AV_CONSTANT_BURST_BEHAVIOR => 0, UAV_CONSTANT_BURST_BEHAVIOR => 0, AV_REQUIRE_UNALIGNED_ADDRESSES => 0, CHIPSELECT_THROUGH_READLATENCY => 0, AV_READ_WAIT_CYCLES => 1, AV_WRITE_WAIT_CYCLES => 0, AV_SETUP_WAIT_CYCLES => 0, AV_DATA_HOLD_CYCLES => 0 ) port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- reset.reset uav_address => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address uav_burstcount => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount uav_read => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_read, -- .read uav_write => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_write, -- .write uav_waitrequest => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest uav_readdatavalid => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid uav_byteenable => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable uav_readdata => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata uav_writedata => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata uav_lock => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock uav_debugaccess => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess av_address => green_leds_s1_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address av_write => green_leds_s1_translator_avalon_anti_slave_0_write, -- .write av_readdata => green_leds_s1_translator_avalon_anti_slave_0_readdata, -- .readdata av_writedata => green_leds_s1_translator_avalon_anti_slave_0_writedata, -- .writedata av_chipselect => green_leds_s1_translator_avalon_anti_slave_0_chipselect, -- .chipselect av_read => open, -- (terminated) av_begintransfer => open, -- (terminated) av_beginbursttransfer => open, -- (terminated) av_burstcount => open, -- (terminated) av_byteenable => open, -- (terminated) av_readdatavalid => '0', -- (terminated) av_waitrequest => '0', -- (terminated) av_writebyteenable => open, -- (terminated) av_lock => open, -- (terminated) av_clken => open, -- (terminated) uav_clken => '0', -- (terminated) av_debugaccess => open, -- (terminated) av_outputenable => open, -- (terminated) uav_response => open, -- (terminated) av_response => "00", -- (terminated) uav_writeresponserequest => '0', -- (terminated) uav_writeresponsevalid => open, -- (terminated) av_writeresponserequest => open, -- (terminated) av_writeresponsevalid => '0' -- (terminated) ); switches_s1_translator : component niosii_system_switches_s1_translator generic map ( AV_ADDRESS_W => 2, AV_DATA_W => 32, UAV_DATA_W => 32, AV_BURSTCOUNT_W => 1, AV_BYTEENABLE_W => 1, UAV_BYTEENABLE_W => 4, UAV_ADDRESS_W => 25, UAV_BURSTCOUNT_W => 3, AV_READLATENCY => 0, USE_READDATAVALID => 0, USE_WAITREQUEST => 0, USE_UAV_CLKEN => 0, USE_READRESPONSE => 0, USE_WRITERESPONSE => 0, AV_SYMBOLS_PER_WORD => 4, AV_ADDRESS_SYMBOLS => 0, AV_BURSTCOUNT_SYMBOLS => 0, AV_CONSTANT_BURST_BEHAVIOR => 0, UAV_CONSTANT_BURST_BEHAVIOR => 0, AV_REQUIRE_UNALIGNED_ADDRESSES => 0, CHIPSELECT_THROUGH_READLATENCY => 0, AV_READ_WAIT_CYCLES => 1, AV_WRITE_WAIT_CYCLES => 0, AV_SETUP_WAIT_CYCLES => 0, AV_DATA_HOLD_CYCLES => 0 ) port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- reset.reset uav_address => switches_s1_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address uav_burstcount => switches_s1_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount uav_read => switches_s1_translator_avalon_universal_slave_0_agent_m0_read, -- .read uav_write => switches_s1_translator_avalon_universal_slave_0_agent_m0_write, -- .write uav_waitrequest => switches_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest uav_readdatavalid => switches_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid uav_byteenable => switches_s1_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable uav_readdata => switches_s1_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata uav_writedata => switches_s1_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata uav_lock => switches_s1_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock uav_debugaccess => switches_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess av_address => switches_s1_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address av_readdata => switches_s1_translator_avalon_anti_slave_0_readdata, -- .readdata av_write => open, -- (terminated) av_read => open, -- (terminated) av_writedata => open, -- (terminated) av_begintransfer => open, -- (terminated) av_beginbursttransfer => open, -- (terminated) av_burstcount => open, -- (terminated) av_byteenable => open, -- (terminated) av_readdatavalid => '0', -- (terminated) av_waitrequest => '0', -- (terminated) av_writebyteenable => open, -- (terminated) av_lock => open, -- (terminated) av_chipselect => open, -- (terminated) av_clken => open, -- (terminated) uav_clken => '0', -- (terminated) av_debugaccess => open, -- (terminated) av_outputenable => open, -- (terminated) uav_response => open, -- (terminated) av_response => "00", -- (terminated) uav_writeresponserequest => '0', -- (terminated) uav_writeresponsevalid => open, -- (terminated) av_writeresponserequest => open, -- (terminated) av_writeresponsevalid => '0' -- (terminated) ); altpll_0_pll_slave_translator : component niosii_system_altpll_0_pll_slave_translator generic map ( AV_ADDRESS_W => 2, AV_DATA_W => 32, UAV_DATA_W => 32, AV_BURSTCOUNT_W => 1, AV_BYTEENABLE_W => 4, UAV_BYTEENABLE_W => 4, UAV_ADDRESS_W => 25, UAV_BURSTCOUNT_W => 3, AV_READLATENCY => 0, USE_READDATAVALID => 0, USE_WAITREQUEST => 0, USE_UAV_CLKEN => 0, USE_READRESPONSE => 0, USE_WRITERESPONSE => 0, AV_SYMBOLS_PER_WORD => 4, AV_ADDRESS_SYMBOLS => 0, AV_BURSTCOUNT_SYMBOLS => 0, AV_CONSTANT_BURST_BEHAVIOR => 0, UAV_CONSTANT_BURST_BEHAVIOR => 0, AV_REQUIRE_UNALIGNED_ADDRESSES => 0, CHIPSELECT_THROUGH_READLATENCY => 0, AV_READ_WAIT_CYCLES => 0, AV_WRITE_WAIT_CYCLES => 0, AV_SETUP_WAIT_CYCLES => 0, AV_DATA_HOLD_CYCLES => 0 ) port map ( clk => clk_clk, -- clk.clk reset => rst_controller_001_reset_out_reset, -- reset.reset uav_address => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address uav_burstcount => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount uav_read => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read uav_write => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write uav_waitrequest => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest uav_readdatavalid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid uav_byteenable => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable uav_readdata => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata uav_writedata => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata uav_lock => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock uav_debugaccess => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess av_address => altpll_0_pll_slave_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address av_write => altpll_0_pll_slave_translator_avalon_anti_slave_0_write, -- .write av_read => altpll_0_pll_slave_translator_avalon_anti_slave_0_read, -- .read av_readdata => altpll_0_pll_slave_translator_avalon_anti_slave_0_readdata, -- .readdata av_writedata => altpll_0_pll_slave_translator_avalon_anti_slave_0_writedata, -- .writedata av_begintransfer => open, -- (terminated) av_beginbursttransfer => open, -- (terminated) av_burstcount => open, -- (terminated) av_byteenable => open, -- (terminated) av_readdatavalid => '0', -- (terminated) av_waitrequest => '0', -- (terminated) av_writebyteenable => open, -- (terminated) av_lock => open, -- (terminated) av_chipselect => open, -- (terminated) av_clken => open, -- (terminated) uav_clken => '0', -- (terminated) av_debugaccess => open, -- (terminated) av_outputenable => open, -- (terminated) uav_response => open, -- (terminated) av_response => "00", -- (terminated) uav_writeresponserequest => '0', -- (terminated) uav_writeresponsevalid => open, -- (terminated) av_writeresponserequest => open, -- (terminated) av_writeresponsevalid => '0' -- (terminated) ); timer_0_s1_translator : component niosii_system_timer_0_s1_translator generic map ( AV_ADDRESS_W => 3, AV_DATA_W => 16, UAV_DATA_W => 32, AV_BURSTCOUNT_W => 1, AV_BYTEENABLE_W => 1, UAV_BYTEENABLE_W => 4, UAV_ADDRESS_W => 25, UAV_BURSTCOUNT_W => 3, AV_READLATENCY => 0, USE_READDATAVALID => 0, USE_WAITREQUEST => 0, USE_UAV_CLKEN => 0, USE_READRESPONSE => 0, USE_WRITERESPONSE => 0, AV_SYMBOLS_PER_WORD => 4, AV_ADDRESS_SYMBOLS => 0, AV_BURSTCOUNT_SYMBOLS => 0, AV_CONSTANT_BURST_BEHAVIOR => 0, UAV_CONSTANT_BURST_BEHAVIOR => 0, AV_REQUIRE_UNALIGNED_ADDRESSES => 0, CHIPSELECT_THROUGH_READLATENCY => 0, AV_READ_WAIT_CYCLES => 1, AV_WRITE_WAIT_CYCLES => 0, AV_SETUP_WAIT_CYCLES => 0, AV_DATA_HOLD_CYCLES => 0 ) port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- reset.reset uav_address => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address uav_burstcount => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount uav_read => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_read, -- .read uav_write => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_write, -- .write uav_waitrequest => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest uav_readdatavalid => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid uav_byteenable => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable uav_readdata => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata uav_writedata => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata uav_lock => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock uav_debugaccess => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess av_address => timer_0_s1_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address av_write => timer_0_s1_translator_avalon_anti_slave_0_write, -- .write av_readdata => timer_0_s1_translator_avalon_anti_slave_0_readdata, -- .readdata av_writedata => timer_0_s1_translator_avalon_anti_slave_0_writedata, -- .writedata av_chipselect => timer_0_s1_translator_avalon_anti_slave_0_chipselect, -- .chipselect av_read => open, -- (terminated) av_begintransfer => open, -- (terminated) av_beginbursttransfer => open, -- (terminated) av_burstcount => open, -- (terminated) av_byteenable => open, -- (terminated) av_readdatavalid => '0', -- (terminated) av_waitrequest => '0', -- (terminated) av_writebyteenable => open, -- (terminated) av_lock => open, -- (terminated) av_clken => open, -- (terminated) uav_clken => '0', -- (terminated) av_debugaccess => open, -- (terminated) av_outputenable => open, -- (terminated) uav_response => open, -- (terminated) av_response => "00", -- (terminated) uav_writeresponserequest => '0', -- (terminated) uav_writeresponsevalid => open, -- (terminated) av_writeresponserequest => open, -- (terminated) av_writeresponsevalid => '0' -- (terminated) ); usb_0_avalon_usb_slave_translator : component niosii_system_usb_0_avalon_usb_slave_translator generic map ( AV_ADDRESS_W => 2, AV_DATA_W => 16, UAV_DATA_W => 32, AV_BURSTCOUNT_W => 1, AV_BYTEENABLE_W => 1, UAV_BYTEENABLE_W => 4, UAV_ADDRESS_W => 25, UAV_BURSTCOUNT_W => 3, AV_READLATENCY => 0, USE_READDATAVALID => 0, USE_WAITREQUEST => 0, USE_UAV_CLKEN => 0, USE_READRESPONSE => 0, USE_WRITERESPONSE => 0, AV_SYMBOLS_PER_WORD => 4, AV_ADDRESS_SYMBOLS => 0, AV_BURSTCOUNT_SYMBOLS => 0, AV_CONSTANT_BURST_BEHAVIOR => 0, UAV_CONSTANT_BURST_BEHAVIOR => 0, AV_REQUIRE_UNALIGNED_ADDRESSES => 0, CHIPSELECT_THROUGH_READLATENCY => 0, AV_READ_WAIT_CYCLES => 5, AV_WRITE_WAIT_CYCLES => 5, AV_SETUP_WAIT_CYCLES => 5, AV_DATA_HOLD_CYCLES => 5 ) port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- reset.reset uav_address => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address uav_burstcount => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount uav_read => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read uav_write => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write uav_waitrequest => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest uav_readdatavalid => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid uav_byteenable => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable uav_readdata => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata uav_writedata => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata uav_lock => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock uav_debugaccess => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess av_address => usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address av_write => usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_write, -- .write av_read => usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_read, -- .read av_readdata => usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_readdata, -- .readdata av_writedata => usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_writedata, -- .writedata av_chipselect => usb_0_avalon_usb_slave_translator_avalon_anti_slave_0_chipselect, -- .chipselect av_begintransfer => open, -- (terminated) av_beginbursttransfer => open, -- (terminated) av_burstcount => open, -- (terminated) av_byteenable => open, -- (terminated) av_readdatavalid => '0', -- (terminated) av_waitrequest => '0', -- (terminated) av_writebyteenable => open, -- (terminated) av_lock => open, -- (terminated) av_clken => open, -- (terminated) uav_clken => '0', -- (terminated) av_debugaccess => open, -- (terminated) av_outputenable => open, -- (terminated) uav_response => open, -- (terminated) av_response => "00", -- (terminated) uav_writeresponserequest => '0', -- (terminated) uav_writeresponsevalid => open, -- (terminated) av_writeresponserequest => open, -- (terminated) av_writeresponsevalid => '0' -- (terminated) ); rs232_0_avalon_rs232_slave_translator : component niosii_system_rs232_0_avalon_rs232_slave_translator generic map ( AV_ADDRESS_W => 1, AV_DATA_W => 32, UAV_DATA_W => 32, AV_BURSTCOUNT_W => 1, AV_BYTEENABLE_W => 4, UAV_BYTEENABLE_W => 4, UAV_ADDRESS_W => 25, UAV_BURSTCOUNT_W => 3, AV_READLATENCY => 1, USE_READDATAVALID => 0, USE_WAITREQUEST => 0, USE_UAV_CLKEN => 0, USE_READRESPONSE => 0, USE_WRITERESPONSE => 0, AV_SYMBOLS_PER_WORD => 4, AV_ADDRESS_SYMBOLS => 0, AV_BURSTCOUNT_SYMBOLS => 0, AV_CONSTANT_BURST_BEHAVIOR => 0, UAV_CONSTANT_BURST_BEHAVIOR => 0, AV_REQUIRE_UNALIGNED_ADDRESSES => 0, CHIPSELECT_THROUGH_READLATENCY => 0, AV_READ_WAIT_CYCLES => 0, AV_WRITE_WAIT_CYCLES => 0, AV_SETUP_WAIT_CYCLES => 0, AV_DATA_HOLD_CYCLES => 0 ) port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- reset.reset uav_address => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_address, -- avalon_universal_slave_0.address uav_burstcount => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount uav_read => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read uav_write => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write uav_waitrequest => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest uav_readdatavalid => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid uav_byteenable => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable uav_readdata => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata uav_writedata => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata uav_lock => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock uav_debugaccess => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess av_address => rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_address, -- avalon_anti_slave_0.address av_write => rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_write, -- .write av_read => rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_read, -- .read av_readdata => rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_readdata, -- .readdata av_writedata => rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_writedata, -- .writedata av_byteenable => rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_byteenable, -- .byteenable av_chipselect => rs232_0_avalon_rs232_slave_translator_avalon_anti_slave_0_chipselect, -- .chipselect av_begintransfer => open, -- (terminated) av_beginbursttransfer => open, -- (terminated) av_burstcount => open, -- (terminated) av_readdatavalid => '0', -- (terminated) av_waitrequest => '0', -- (terminated) av_writebyteenable => open, -- (terminated) av_lock => open, -- (terminated) av_clken => open, -- (terminated) uav_clken => '0', -- (terminated) av_debugaccess => open, -- (terminated) av_outputenable => open, -- (terminated) uav_response => open, -- (terminated) av_response => "00", -- (terminated) uav_writeresponserequest => '0', -- (terminated) uav_writeresponsevalid => open, -- (terminated) av_writeresponserequest => open, -- (terminated) av_writeresponsevalid => '0' -- (terminated) ); nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent : component altera_merlin_master_agent generic map ( PKT_PROTECTION_H => 93, PKT_PROTECTION_L => 91, PKT_BEGIN_BURST => 80, PKT_BURSTWRAP_H => 72, PKT_BURSTWRAP_L => 70, PKT_BURST_SIZE_H => 75, PKT_BURST_SIZE_L => 73, PKT_BURST_TYPE_H => 77, PKT_BURST_TYPE_L => 76, PKT_BYTE_CNT_H => 69, PKT_BYTE_CNT_L => 67, PKT_ADDR_H => 60, PKT_ADDR_L => 36, PKT_TRANS_COMPRESSED_READ => 61, PKT_TRANS_POSTED => 62, PKT_TRANS_WRITE => 63, PKT_TRANS_READ => 64, PKT_TRANS_LOCK => 65, PKT_TRANS_EXCLUSIVE => 66, PKT_DATA_H => 31, PKT_DATA_L => 0, PKT_BYTEEN_H => 35, PKT_BYTEEN_L => 32, PKT_SRC_ID_H => 85, PKT_SRC_ID_L => 82, PKT_DEST_ID_H => 89, PKT_DEST_ID_L => 86, PKT_THREAD_ID_H => 90, PKT_THREAD_ID_L => 90, PKT_CACHE_H => 97, PKT_CACHE_L => 94, PKT_DATA_SIDEBAND_H => 79, PKT_DATA_SIDEBAND_L => 79, PKT_QOS_H => 81, PKT_QOS_L => 81, PKT_ADDR_SIDEBAND_H => 78, PKT_ADDR_SIDEBAND_L => 78, PKT_RESPONSE_STATUS_H => 99, PKT_RESPONSE_STATUS_L => 98, ST_DATA_W => 100, ST_CHANNEL_W => 13, AV_BURSTCOUNT_W => 3, SUPPRESS_0_BYTEEN_RSP => 0, ID => 1, BURSTWRAP_VALUE => 3, CACHE_VALUE => 0, SECURE_ACCESS_BIT => 1, USE_READRESPONSE => 0, USE_WRITERESPONSE => 0 ) port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset av_address => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_address, -- av.address av_write => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_write, -- .write av_read => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_read, -- .read av_writedata => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_writedata, -- .writedata av_readdata => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdata, -- .readdata av_waitrequest => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_waitrequest, -- .waitrequest av_readdatavalid => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_readdatavalid, -- .readdatavalid av_byteenable => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_byteenable, -- .byteenable av_burstcount => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_burstcount, -- .burstcount av_debugaccess => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_debugaccess, -- .debugaccess av_lock => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_lock, -- .lock cp_valid => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_valid, -- cp.valid cp_data => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_data, -- .data cp_startofpacket => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket, -- .startofpacket cp_endofpacket => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket, -- .endofpacket cp_ready => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_ready, -- .ready rp_valid => rsp_xbar_mux_src_valid, -- rp.valid rp_data => rsp_xbar_mux_src_data, -- .data rp_channel => rsp_xbar_mux_src_channel, -- .channel rp_startofpacket => rsp_xbar_mux_src_startofpacket, -- .startofpacket rp_endofpacket => rsp_xbar_mux_src_endofpacket, -- .endofpacket rp_ready => rsp_xbar_mux_src_ready, -- .ready av_response => open, -- (terminated) av_writeresponserequest => '0', -- (terminated) av_writeresponsevalid => open -- (terminated) ); nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent : component altera_merlin_master_agent generic map ( PKT_PROTECTION_H => 93, PKT_PROTECTION_L => 91, PKT_BEGIN_BURST => 80, PKT_BURSTWRAP_H => 72, PKT_BURSTWRAP_L => 70, PKT_BURST_SIZE_H => 75, PKT_BURST_SIZE_L => 73, PKT_BURST_TYPE_H => 77, PKT_BURST_TYPE_L => 76, PKT_BYTE_CNT_H => 69, PKT_BYTE_CNT_L => 67, PKT_ADDR_H => 60, PKT_ADDR_L => 36, PKT_TRANS_COMPRESSED_READ => 61, PKT_TRANS_POSTED => 62, PKT_TRANS_WRITE => 63, PKT_TRANS_READ => 64, PKT_TRANS_LOCK => 65, PKT_TRANS_EXCLUSIVE => 66, PKT_DATA_H => 31, PKT_DATA_L => 0, PKT_BYTEEN_H => 35, PKT_BYTEEN_L => 32, PKT_SRC_ID_H => 85, PKT_SRC_ID_L => 82, PKT_DEST_ID_H => 89, PKT_DEST_ID_L => 86, PKT_THREAD_ID_H => 90, PKT_THREAD_ID_L => 90, PKT_CACHE_H => 97, PKT_CACHE_L => 94, PKT_DATA_SIDEBAND_H => 79, PKT_DATA_SIDEBAND_L => 79, PKT_QOS_H => 81, PKT_QOS_L => 81, PKT_ADDR_SIDEBAND_H => 78, PKT_ADDR_SIDEBAND_L => 78, PKT_RESPONSE_STATUS_H => 99, PKT_RESPONSE_STATUS_L => 98, ST_DATA_W => 100, ST_CHANNEL_W => 13, AV_BURSTCOUNT_W => 3, SUPPRESS_0_BYTEEN_RSP => 0, ID => 0, BURSTWRAP_VALUE => 7, CACHE_VALUE => 0, SECURE_ACCESS_BIT => 1, USE_READRESPONSE => 0, USE_WRITERESPONSE => 0 ) port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset av_address => nios2_qsys_0_data_master_translator_avalon_universal_master_0_address, -- av.address av_write => nios2_qsys_0_data_master_translator_avalon_universal_master_0_write, -- .write av_read => nios2_qsys_0_data_master_translator_avalon_universal_master_0_read, -- .read av_writedata => nios2_qsys_0_data_master_translator_avalon_universal_master_0_writedata, -- .writedata av_readdata => nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdata, -- .readdata av_waitrequest => nios2_qsys_0_data_master_translator_avalon_universal_master_0_waitrequest, -- .waitrequest av_readdatavalid => nios2_qsys_0_data_master_translator_avalon_universal_master_0_readdatavalid, -- .readdatavalid av_byteenable => nios2_qsys_0_data_master_translator_avalon_universal_master_0_byteenable, -- .byteenable av_burstcount => nios2_qsys_0_data_master_translator_avalon_universal_master_0_burstcount, -- .burstcount av_debugaccess => nios2_qsys_0_data_master_translator_avalon_universal_master_0_debugaccess, -- .debugaccess av_lock => nios2_qsys_0_data_master_translator_avalon_universal_master_0_lock, -- .lock cp_valid => nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_valid, -- cp.valid cp_data => nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_data, -- .data cp_startofpacket => nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket, -- .startofpacket cp_endofpacket => nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket, -- .endofpacket cp_ready => nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_ready, -- .ready rp_valid => rsp_xbar_mux_001_src_valid, -- rp.valid rp_data => rsp_xbar_mux_001_src_data, -- .data rp_channel => rsp_xbar_mux_001_src_channel, -- .channel rp_startofpacket => rsp_xbar_mux_001_src_startofpacket, -- .startofpacket rp_endofpacket => rsp_xbar_mux_001_src_endofpacket, -- .endofpacket rp_ready => rsp_xbar_mux_001_src_ready, -- .ready av_response => open, -- (terminated) av_writeresponserequest => '0', -- (terminated) av_writeresponsevalid => open -- (terminated) ); nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent generic map ( PKT_DATA_H => 31, PKT_DATA_L => 0, PKT_BEGIN_BURST => 80, PKT_SYMBOL_W => 8, PKT_BYTEEN_H => 35, PKT_BYTEEN_L => 32, PKT_ADDR_H => 60, PKT_ADDR_L => 36, PKT_TRANS_COMPRESSED_READ => 61, PKT_TRANS_POSTED => 62, PKT_TRANS_WRITE => 63, PKT_TRANS_READ => 64, PKT_TRANS_LOCK => 65, PKT_SRC_ID_H => 85, PKT_SRC_ID_L => 82, PKT_DEST_ID_H => 89, PKT_DEST_ID_L => 86, PKT_BURSTWRAP_H => 72, PKT_BURSTWRAP_L => 70, PKT_BYTE_CNT_H => 69, PKT_BYTE_CNT_L => 67, PKT_PROTECTION_H => 93, PKT_PROTECTION_L => 91, PKT_RESPONSE_STATUS_H => 99, PKT_RESPONSE_STATUS_L => 98, PKT_BURST_SIZE_H => 75, PKT_BURST_SIZE_L => 73, ST_CHANNEL_W => 13, ST_DATA_W => 100, AVS_BURSTCOUNT_W => 3, SUPPRESS_0_BYTEEN_CMD => 0, PREVENT_FIFO_OVERFLOW => 1, USE_READRESPONSE => 0, USE_WRITERESPONSE => 0 ) port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset m0_address => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address m0_burstcount => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount m0_byteenable => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable m0_debugaccess => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess m0_lock => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock m0_readdata => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata m0_readdatavalid => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid m0_read => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_read, -- .read m0_waitrequest => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest m0_writedata => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata m0_write => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_m0_write, -- .write rp_endofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket rp_ready => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready rp_valid => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid rp_data => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data, -- .data rp_startofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket cp_ready => cmd_xbar_mux_src_ready, -- cp.ready cp_valid => cmd_xbar_mux_src_valid, -- .valid cp_data => cmd_xbar_mux_src_data, -- .data cp_startofpacket => cmd_xbar_mux_src_startofpacket, -- .startofpacket cp_endofpacket => cmd_xbar_mux_src_endofpacket, -- .endofpacket cp_channel => cmd_xbar_mux_src_channel, -- .channel rf_sink_ready => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready rf_sink_valid => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid rf_sink_startofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket rf_sink_endofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket rf_sink_data => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data rf_source_ready => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready rf_source_valid => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid rf_source_startofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket rf_source_endofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket rf_source_data => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data rdata_fifo_sink_ready => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready rdata_fifo_sink_valid => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid rdata_fifo_sink_data => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data rdata_fifo_src_ready => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready rdata_fifo_src_valid => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid rdata_fifo_src_data => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data m0_response => "00", -- (terminated) m0_writeresponserequest => open, -- (terminated) m0_writeresponsevalid => '0' -- (terminated) ); nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo generic map ( SYMBOLS_PER_BEAT => 1, BITS_PER_SYMBOL => 101, FIFO_DEPTH => 2, CHANNEL_WIDTH => 0, ERROR_WIDTH => 0, USE_PACKETS => 1, USE_FILL_LEVEL => 0, EMPTY_LATENCY => 1, USE_MEMORY_BLOCKS => 0, USE_STORE_FORWARD => 0, USE_ALMOST_FULL_IF => 0, USE_ALMOST_EMPTY_IF => 0 ) port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset in_data => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data in_valid => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid in_ready => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready in_startofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket in_endofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket out_data => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data out_valid => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid out_ready => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready out_startofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket out_endofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket csr_address => "00", -- (terminated) csr_read => '0', -- (terminated) csr_write => '0', -- (terminated) csr_readdata => open, -- (terminated) csr_writedata => "00000000000000000000000000000000", -- (terminated) almost_full_data => open, -- (terminated) almost_empty_data => open, -- (terminated) in_empty => '0', -- (terminated) out_empty => open, -- (terminated) in_error => '0', -- (terminated) out_error => open, -- (terminated) in_channel => '0', -- (terminated) out_channel => open -- (terminated) ); sdram_0_s1_translator_avalon_universal_slave_0_agent : component niosii_system_sdram_0_s1_translator_avalon_universal_slave_0_agent generic map ( PKT_DATA_H => 15, PKT_DATA_L => 0, PKT_BEGIN_BURST => 62, PKT_SYMBOL_W => 8, PKT_BYTEEN_H => 17, PKT_BYTEEN_L => 16, PKT_ADDR_H => 42, PKT_ADDR_L => 18, PKT_TRANS_COMPRESSED_READ => 43, PKT_TRANS_POSTED => 44, PKT_TRANS_WRITE => 45, PKT_TRANS_READ => 46, PKT_TRANS_LOCK => 47, PKT_SRC_ID_H => 67, PKT_SRC_ID_L => 64, PKT_DEST_ID_H => 71, PKT_DEST_ID_L => 68, PKT_BURSTWRAP_H => 54, PKT_BURSTWRAP_L => 52, PKT_BYTE_CNT_H => 51, PKT_BYTE_CNT_L => 49, PKT_PROTECTION_H => 75, PKT_PROTECTION_L => 73, PKT_RESPONSE_STATUS_H => 81, PKT_RESPONSE_STATUS_L => 80, PKT_BURST_SIZE_H => 57, PKT_BURST_SIZE_L => 55, ST_CHANNEL_W => 13, ST_DATA_W => 82, AVS_BURSTCOUNT_W => 2, SUPPRESS_0_BYTEEN_CMD => 1, PREVENT_FIFO_OVERFLOW => 1, USE_READRESPONSE => 0, USE_WRITERESPONSE => 0 ) port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset m0_address => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address m0_burstcount => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount m0_byteenable => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable m0_debugaccess => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess m0_lock => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock m0_readdata => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata m0_readdatavalid => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid m0_read => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_read, -- .read m0_waitrequest => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest m0_writedata => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata m0_write => sdram_0_s1_translator_avalon_universal_slave_0_agent_m0_write, -- .write rp_endofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket rp_ready => sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready rp_valid => sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid rp_data => sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_data, -- .data rp_startofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket cp_ready => burst_adapter_source0_ready, -- cp.ready cp_valid => burst_adapter_source0_valid, -- .valid cp_data => burst_adapter_source0_data, -- .data cp_startofpacket => burst_adapter_source0_startofpacket, -- .startofpacket cp_endofpacket => burst_adapter_source0_endofpacket, -- .endofpacket cp_channel => burst_adapter_source0_channel, -- .channel rf_sink_ready => sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready rf_sink_valid => sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid rf_sink_startofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket rf_sink_endofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket rf_sink_data => sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data rf_source_ready => sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready rf_source_valid => sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid rf_source_startofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket rf_source_endofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket rf_source_data => sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data rdata_fifo_sink_ready => sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready, -- rdata_fifo_sink.ready rdata_fifo_sink_valid => sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid, -- .valid rdata_fifo_sink_data => sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data, -- .data rdata_fifo_src_ready => sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready rdata_fifo_src_valid => sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid rdata_fifo_src_data => sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data m0_response => "00", -- (terminated) m0_writeresponserequest => open, -- (terminated) m0_writeresponsevalid => '0' -- (terminated) ); sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo : component niosii_system_sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo generic map ( SYMBOLS_PER_BEAT => 1, BITS_PER_SYMBOL => 83, FIFO_DEPTH => 8, CHANNEL_WIDTH => 0, ERROR_WIDTH => 0, USE_PACKETS => 1, USE_FILL_LEVEL => 0, EMPTY_LATENCY => 1, USE_MEMORY_BLOCKS => 0, USE_STORE_FORWARD => 0, USE_ALMOST_FULL_IF => 0, USE_ALMOST_EMPTY_IF => 0 ) port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset in_data => sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data in_valid => sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid in_ready => sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready in_startofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket in_endofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket out_data => sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data out_valid => sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid out_ready => sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready out_startofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket out_endofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket csr_address => "00", -- (terminated) csr_read => '0', -- (terminated) csr_write => '0', -- (terminated) csr_readdata => open, -- (terminated) csr_writedata => "00000000000000000000000000000000", -- (terminated) almost_full_data => open, -- (terminated) almost_empty_data => open, -- (terminated) in_empty => '0', -- (terminated) out_empty => open, -- (terminated) in_error => '0', -- (terminated) out_error => open, -- (terminated) in_channel => '0', -- (terminated) out_channel => open -- (terminated) ); sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo : component niosii_system_sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo generic map ( SYMBOLS_PER_BEAT => 1, BITS_PER_SYMBOL => 18, FIFO_DEPTH => 8, CHANNEL_WIDTH => 0, ERROR_WIDTH => 0, USE_PACKETS => 0, USE_FILL_LEVEL => 0, EMPTY_LATENCY => 3, USE_MEMORY_BLOCKS => 1, USE_STORE_FORWARD => 0, USE_ALMOST_FULL_IF => 0, USE_ALMOST_EMPTY_IF => 0 ) port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset in_data => sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- in.data in_valid => sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid in_ready => sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- .ready out_data => sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data, -- out.data out_valid => sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid, -- .valid out_ready => sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready, -- .ready csr_address => "00", -- (terminated) csr_read => '0', -- (terminated) csr_write => '0', -- (terminated) csr_readdata => open, -- (terminated) csr_writedata => "00000000000000000000000000000000", -- (terminated) almost_full_data => open, -- (terminated) almost_empty_data => open, -- (terminated) in_startofpacket => '0', -- (terminated) in_endofpacket => '0', -- (terminated) out_startofpacket => open, -- (terminated) out_endofpacket => open, -- (terminated) in_empty => '0', -- (terminated) out_empty => open, -- (terminated) in_error => '0', -- (terminated) out_error => open, -- (terminated) in_channel => '0', -- (terminated) out_channel => open -- (terminated) ); onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent generic map ( PKT_DATA_H => 31, PKT_DATA_L => 0, PKT_BEGIN_BURST => 80, PKT_SYMBOL_W => 8, PKT_BYTEEN_H => 35, PKT_BYTEEN_L => 32, PKT_ADDR_H => 60, PKT_ADDR_L => 36, PKT_TRANS_COMPRESSED_READ => 61, PKT_TRANS_POSTED => 62, PKT_TRANS_WRITE => 63, PKT_TRANS_READ => 64, PKT_TRANS_LOCK => 65, PKT_SRC_ID_H => 85, PKT_SRC_ID_L => 82, PKT_DEST_ID_H => 89, PKT_DEST_ID_L => 86, PKT_BURSTWRAP_H => 72, PKT_BURSTWRAP_L => 70, PKT_BYTE_CNT_H => 69, PKT_BYTE_CNT_L => 67, PKT_PROTECTION_H => 93, PKT_PROTECTION_L => 91, PKT_RESPONSE_STATUS_H => 99, PKT_RESPONSE_STATUS_L => 98, PKT_BURST_SIZE_H => 75, PKT_BURST_SIZE_L => 73, ST_CHANNEL_W => 13, ST_DATA_W => 100, AVS_BURSTCOUNT_W => 3, SUPPRESS_0_BYTEEN_CMD => 0, PREVENT_FIFO_OVERFLOW => 1, USE_READRESPONSE => 0, USE_WRITERESPONSE => 0 ) port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset m0_address => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address m0_burstcount => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount m0_byteenable => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable m0_debugaccess => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess m0_lock => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock m0_readdata => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata m0_readdatavalid => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid m0_read => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_read, -- .read m0_waitrequest => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest m0_writedata => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata m0_write => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_m0_write, -- .write rp_endofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket rp_ready => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready rp_valid => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid rp_data => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_data, -- .data rp_startofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket cp_ready => cmd_xbar_mux_002_src_ready, -- cp.ready cp_valid => cmd_xbar_mux_002_src_valid, -- .valid cp_data => cmd_xbar_mux_002_src_data, -- .data cp_startofpacket => cmd_xbar_mux_002_src_startofpacket, -- .startofpacket cp_endofpacket => cmd_xbar_mux_002_src_endofpacket, -- .endofpacket cp_channel => cmd_xbar_mux_002_src_channel, -- .channel rf_sink_ready => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready rf_sink_valid => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid rf_sink_startofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket rf_sink_endofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket rf_sink_data => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data rf_source_ready => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready rf_source_valid => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid rf_source_startofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket rf_source_endofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket rf_source_data => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data rdata_fifo_sink_ready => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready rdata_fifo_sink_valid => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid rdata_fifo_sink_data => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data rdata_fifo_src_ready => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready rdata_fifo_src_valid => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid rdata_fifo_src_data => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data m0_response => "00", -- (terminated) m0_writeresponserequest => open, -- (terminated) m0_writeresponsevalid => '0' -- (terminated) ); onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo generic map ( SYMBOLS_PER_BEAT => 1, BITS_PER_SYMBOL => 101, FIFO_DEPTH => 2, CHANNEL_WIDTH => 0, ERROR_WIDTH => 0, USE_PACKETS => 1, USE_FILL_LEVEL => 0, EMPTY_LATENCY => 1, USE_MEMORY_BLOCKS => 0, USE_STORE_FORWARD => 0, USE_ALMOST_FULL_IF => 0, USE_ALMOST_EMPTY_IF => 0 ) port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset in_data => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data in_valid => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid in_ready => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready in_startofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket in_endofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket out_data => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data out_valid => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid out_ready => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready out_startofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket out_endofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket csr_address => "00", -- (terminated) csr_read => '0', -- (terminated) csr_write => '0', -- (terminated) csr_readdata => open, -- (terminated) csr_writedata => "00000000000000000000000000000000", -- (terminated) almost_full_data => open, -- (terminated) almost_empty_data => open, -- (terminated) in_empty => '0', -- (terminated) out_empty => open, -- (terminated) in_error => '0', -- (terminated) out_error => open, -- (terminated) in_channel => '0', -- (terminated) out_channel => open -- (terminated) ); sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent : component niosii_system_sdram_0_s1_translator_avalon_universal_slave_0_agent generic map ( PKT_DATA_H => 15, PKT_DATA_L => 0, PKT_BEGIN_BURST => 62, PKT_SYMBOL_W => 8, PKT_BYTEEN_H => 17, PKT_BYTEEN_L => 16, PKT_ADDR_H => 42, PKT_ADDR_L => 18, PKT_TRANS_COMPRESSED_READ => 43, PKT_TRANS_POSTED => 44, PKT_TRANS_WRITE => 45, PKT_TRANS_READ => 46, PKT_TRANS_LOCK => 47, PKT_SRC_ID_H => 67, PKT_SRC_ID_L => 64, PKT_DEST_ID_H => 71, PKT_DEST_ID_L => 68, PKT_BURSTWRAP_H => 54, PKT_BURSTWRAP_L => 52, PKT_BYTE_CNT_H => 51, PKT_BYTE_CNT_L => 49, PKT_PROTECTION_H => 75, PKT_PROTECTION_L => 73, PKT_RESPONSE_STATUS_H => 81, PKT_RESPONSE_STATUS_L => 80, PKT_BURST_SIZE_H => 57, PKT_BURST_SIZE_L => 55, ST_CHANNEL_W => 13, ST_DATA_W => 82, AVS_BURSTCOUNT_W => 2, SUPPRESS_0_BYTEEN_CMD => 1, PREVENT_FIFO_OVERFLOW => 1, USE_READRESPONSE => 0, USE_WRITERESPONSE => 0 ) port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset m0_address => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address m0_burstcount => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount m0_byteenable => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable m0_debugaccess => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess m0_lock => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock m0_readdata => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata m0_readdatavalid => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid m0_read => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read m0_waitrequest => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest m0_writedata => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata m0_write => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write rp_endofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket rp_ready => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready rp_valid => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid rp_data => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data rp_startofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket cp_ready => burst_adapter_001_source0_ready, -- cp.ready cp_valid => burst_adapter_001_source0_valid, -- .valid cp_data => burst_adapter_001_source0_data, -- .data cp_startofpacket => burst_adapter_001_source0_startofpacket, -- .startofpacket cp_endofpacket => burst_adapter_001_source0_endofpacket, -- .endofpacket cp_channel => burst_adapter_001_source0_channel, -- .channel rf_sink_ready => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready rf_sink_valid => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid rf_sink_startofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket rf_sink_endofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket rf_sink_data => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data rf_source_ready => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready rf_source_valid => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid rf_source_startofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket rf_source_endofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket rf_source_data => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data rdata_fifo_sink_ready => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready, -- rdata_fifo_sink.ready rdata_fifo_sink_valid => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid, -- .valid rdata_fifo_sink_data => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data, -- .data rdata_fifo_src_ready => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready rdata_fifo_src_valid => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid rdata_fifo_src_data => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data m0_response => "00", -- (terminated) m0_writeresponserequest => open, -- (terminated) m0_writeresponsevalid => '0' -- (terminated) ); sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo : component niosii_system_sdram_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo generic map ( SYMBOLS_PER_BEAT => 1, BITS_PER_SYMBOL => 83, FIFO_DEPTH => 3, CHANNEL_WIDTH => 0, ERROR_WIDTH => 0, USE_PACKETS => 1, USE_FILL_LEVEL => 0, EMPTY_LATENCY => 1, USE_MEMORY_BLOCKS => 0, USE_STORE_FORWARD => 0, USE_ALMOST_FULL_IF => 0, USE_ALMOST_EMPTY_IF => 0 ) port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset in_data => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data in_valid => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid in_ready => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready in_startofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket in_endofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket out_data => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data out_valid => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid out_ready => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready out_startofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket out_endofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket csr_address => "00", -- (terminated) csr_read => '0', -- (terminated) csr_write => '0', -- (terminated) csr_readdata => open, -- (terminated) csr_writedata => "00000000000000000000000000000000", -- (terminated) almost_full_data => open, -- (terminated) almost_empty_data => open, -- (terminated) in_empty => '0', -- (terminated) out_empty => open, -- (terminated) in_error => '0', -- (terminated) out_error => open, -- (terminated) in_channel => '0', -- (terminated) out_channel => open -- (terminated) ); sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo : component niosii_system_sdram_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo generic map ( SYMBOLS_PER_BEAT => 1, BITS_PER_SYMBOL => 18, FIFO_DEPTH => 3, CHANNEL_WIDTH => 0, ERROR_WIDTH => 0, USE_PACKETS => 0, USE_FILL_LEVEL => 0, EMPTY_LATENCY => 0, USE_MEMORY_BLOCKS => 0, USE_STORE_FORWARD => 0, USE_ALMOST_FULL_IF => 0, USE_ALMOST_EMPTY_IF => 0 ) port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset in_data => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- in.data in_valid => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid in_ready => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- .ready out_data => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data, -- out.data out_valid => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid, -- .valid out_ready => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready, -- .ready csr_address => "00", -- (terminated) csr_read => '0', -- (terminated) csr_write => '0', -- (terminated) csr_readdata => open, -- (terminated) csr_writedata => "00000000000000000000000000000000", -- (terminated) almost_full_data => open, -- (terminated) almost_empty_data => open, -- (terminated) in_startofpacket => '0', -- (terminated) in_endofpacket => '0', -- (terminated) out_startofpacket => open, -- (terminated) out_endofpacket => open, -- (terminated) in_empty => '0', -- (terminated) out_empty => open, -- (terminated) in_error => '0', -- (terminated) out_error => open, -- (terminated) in_channel => '0', -- (terminated) out_channel => open -- (terminated) ); generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent : component niosii_system_generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent generic map ( PKT_DATA_H => 7, PKT_DATA_L => 0, PKT_BEGIN_BURST => 53, PKT_SYMBOL_W => 8, PKT_BYTEEN_H => 8, PKT_BYTEEN_L => 8, PKT_ADDR_H => 33, PKT_ADDR_L => 9, PKT_TRANS_COMPRESSED_READ => 34, PKT_TRANS_POSTED => 35, PKT_TRANS_WRITE => 36, PKT_TRANS_READ => 37, PKT_TRANS_LOCK => 38, PKT_SRC_ID_H => 58, PKT_SRC_ID_L => 55, PKT_DEST_ID_H => 62, PKT_DEST_ID_L => 59, PKT_BURSTWRAP_H => 45, PKT_BURSTWRAP_L => 43, PKT_BYTE_CNT_H => 42, PKT_BYTE_CNT_L => 40, PKT_PROTECTION_H => 66, PKT_PROTECTION_L => 64, PKT_RESPONSE_STATUS_H => 72, PKT_RESPONSE_STATUS_L => 71, PKT_BURST_SIZE_H => 48, PKT_BURST_SIZE_L => 46, ST_CHANNEL_W => 13, ST_DATA_W => 73, AVS_BURSTCOUNT_W => 1, SUPPRESS_0_BYTEEN_CMD => 1, PREVENT_FIFO_OVERFLOW => 1, USE_READRESPONSE => 0, USE_WRITERESPONSE => 0 ) port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset m0_address => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address m0_burstcount => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount m0_byteenable => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable m0_debugaccess => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess m0_lock => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock m0_readdata => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata m0_readdatavalid => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid m0_read => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_read, -- .read m0_waitrequest => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest m0_writedata => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata m0_write => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_m0_write, -- .write rp_endofpacket => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket rp_ready => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready rp_valid => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid rp_data => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rp_data, -- .data rp_startofpacket => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket cp_ready => burst_adapter_002_source0_ready, -- cp.ready cp_valid => burst_adapter_002_source0_valid, -- .valid cp_data => burst_adapter_002_source0_data, -- .data cp_startofpacket => burst_adapter_002_source0_startofpacket, -- .startofpacket cp_endofpacket => burst_adapter_002_source0_endofpacket, -- .endofpacket cp_channel => burst_adapter_002_source0_channel, -- .channel rf_sink_ready => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready rf_sink_valid => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid rf_sink_startofpacket => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket rf_sink_endofpacket => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket rf_sink_data => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data rf_source_ready => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready rf_source_valid => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid rf_source_startofpacket => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket rf_source_endofpacket => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket rf_source_data => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data rdata_fifo_sink_ready => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready, -- rdata_fifo_sink.ready rdata_fifo_sink_valid => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid, -- .valid rdata_fifo_sink_data => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data, -- .data rdata_fifo_src_ready => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready rdata_fifo_src_valid => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid rdata_fifo_src_data => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data m0_response => "00", -- (terminated) m0_writeresponserequest => open, -- (terminated) m0_writeresponsevalid => '0' -- (terminated) ); generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo : component niosii_system_generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo generic map ( SYMBOLS_PER_BEAT => 1, BITS_PER_SYMBOL => 74, FIFO_DEPTH => 4, CHANNEL_WIDTH => 0, ERROR_WIDTH => 0, USE_PACKETS => 1, USE_FILL_LEVEL => 0, EMPTY_LATENCY => 1, USE_MEMORY_BLOCKS => 0, USE_STORE_FORWARD => 0, USE_ALMOST_FULL_IF => 0, USE_ALMOST_EMPTY_IF => 0 ) port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset in_data => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data in_valid => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid in_ready => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready in_startofpacket => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket in_endofpacket => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket out_data => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data out_valid => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid out_ready => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready out_startofpacket => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket out_endofpacket => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket csr_address => "00", -- (terminated) csr_read => '0', -- (terminated) csr_write => '0', -- (terminated) csr_readdata => open, -- (terminated) csr_writedata => "00000000000000000000000000000000", -- (terminated) almost_full_data => open, -- (terminated) almost_empty_data => open, -- (terminated) in_empty => '0', -- (terminated) out_empty => open, -- (terminated) in_error => '0', -- (terminated) out_error => open, -- (terminated) in_channel => '0', -- (terminated) out_channel => open -- (terminated) ); generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo : component niosii_system_generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo generic map ( SYMBOLS_PER_BEAT => 1, BITS_PER_SYMBOL => 10, FIFO_DEPTH => 4, CHANNEL_WIDTH => 0, ERROR_WIDTH => 0, USE_PACKETS => 0, USE_FILL_LEVEL => 0, EMPTY_LATENCY => 0, USE_MEMORY_BLOCKS => 0, USE_STORE_FORWARD => 0, USE_ALMOST_FULL_IF => 0, USE_ALMOST_EMPTY_IF => 0 ) port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset in_data => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- in.data in_valid => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid in_ready => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- .ready out_data => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data, -- out.data out_valid => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid, -- .valid out_ready => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready, -- .ready csr_address => "00", -- (terminated) csr_read => '0', -- (terminated) csr_write => '0', -- (terminated) csr_readdata => open, -- (terminated) csr_writedata => "00000000000000000000000000000000", -- (terminated) almost_full_data => open, -- (terminated) almost_empty_data => open, -- (terminated) in_startofpacket => '0', -- (terminated) in_endofpacket => '0', -- (terminated) out_startofpacket => open, -- (terminated) out_endofpacket => open, -- (terminated) in_empty => '0', -- (terminated) out_empty => open, -- (terminated) in_error => '0', -- (terminated) out_error => open, -- (terminated) in_channel => '0', -- (terminated) out_channel => open -- (terminated) ); jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent generic map ( PKT_DATA_H => 31, PKT_DATA_L => 0, PKT_BEGIN_BURST => 80, PKT_SYMBOL_W => 8, PKT_BYTEEN_H => 35, PKT_BYTEEN_L => 32, PKT_ADDR_H => 60, PKT_ADDR_L => 36, PKT_TRANS_COMPRESSED_READ => 61, PKT_TRANS_POSTED => 62, PKT_TRANS_WRITE => 63, PKT_TRANS_READ => 64, PKT_TRANS_LOCK => 65, PKT_SRC_ID_H => 85, PKT_SRC_ID_L => 82, PKT_DEST_ID_H => 89, PKT_DEST_ID_L => 86, PKT_BURSTWRAP_H => 72, PKT_BURSTWRAP_L => 70, PKT_BYTE_CNT_H => 69, PKT_BYTE_CNT_L => 67, PKT_PROTECTION_H => 93, PKT_PROTECTION_L => 91, PKT_RESPONSE_STATUS_H => 99, PKT_RESPONSE_STATUS_L => 98, PKT_BURST_SIZE_H => 75, PKT_BURST_SIZE_L => 73, ST_CHANNEL_W => 13, ST_DATA_W => 100, AVS_BURSTCOUNT_W => 3, SUPPRESS_0_BYTEEN_CMD => 0, PREVENT_FIFO_OVERFLOW => 1, USE_READRESPONSE => 0, USE_WRITERESPONSE => 0 ) port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset m0_address => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address m0_burstcount => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount m0_byteenable => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable m0_debugaccess => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess m0_lock => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock m0_readdata => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata m0_readdatavalid => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid m0_read => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read m0_waitrequest => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest m0_writedata => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata m0_write => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write rp_endofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket rp_ready => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready rp_valid => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid rp_data => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data rp_startofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket cp_ready => cmd_xbar_demux_001_src5_ready, -- cp.ready cp_valid => cmd_xbar_demux_001_src5_valid, -- .valid cp_data => cmd_xbar_demux_001_src5_data, -- .data cp_startofpacket => cmd_xbar_demux_001_src5_startofpacket, -- .startofpacket cp_endofpacket => cmd_xbar_demux_001_src5_endofpacket, -- .endofpacket cp_channel => cmd_xbar_demux_001_src5_channel, -- .channel rf_sink_ready => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready rf_sink_valid => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid rf_sink_startofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket rf_sink_endofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket rf_sink_data => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data rf_source_ready => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready rf_source_valid => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid rf_source_startofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket rf_source_endofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket rf_source_data => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data rdata_fifo_sink_ready => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready rdata_fifo_sink_valid => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid rdata_fifo_sink_data => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data rdata_fifo_src_ready => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready rdata_fifo_src_valid => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid rdata_fifo_src_data => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data m0_response => "00", -- (terminated) m0_writeresponserequest => open, -- (terminated) m0_writeresponsevalid => '0' -- (terminated) ); jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo generic map ( SYMBOLS_PER_BEAT => 1, BITS_PER_SYMBOL => 101, FIFO_DEPTH => 2, CHANNEL_WIDTH => 0, ERROR_WIDTH => 0, USE_PACKETS => 1, USE_FILL_LEVEL => 0, EMPTY_LATENCY => 1, USE_MEMORY_BLOCKS => 0, USE_STORE_FORWARD => 0, USE_ALMOST_FULL_IF => 0, USE_ALMOST_EMPTY_IF => 0 ) port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset in_data => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data in_valid => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid in_ready => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready in_startofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket in_endofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket out_data => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data out_valid => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid out_ready => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready out_startofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket out_endofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket csr_address => "00", -- (terminated) csr_read => '0', -- (terminated) csr_write => '0', -- (terminated) csr_readdata => open, -- (terminated) csr_writedata => "00000000000000000000000000000000", -- (terminated) almost_full_data => open, -- (terminated) almost_empty_data => open, -- (terminated) in_empty => '0', -- (terminated) out_empty => open, -- (terminated) in_error => '0', -- (terminated) out_error => open, -- (terminated) in_channel => '0', -- (terminated) out_channel => open -- (terminated) ); sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent generic map ( PKT_DATA_H => 31, PKT_DATA_L => 0, PKT_BEGIN_BURST => 80, PKT_SYMBOL_W => 8, PKT_BYTEEN_H => 35, PKT_BYTEEN_L => 32, PKT_ADDR_H => 60, PKT_ADDR_L => 36, PKT_TRANS_COMPRESSED_READ => 61, PKT_TRANS_POSTED => 62, PKT_TRANS_WRITE => 63, PKT_TRANS_READ => 64, PKT_TRANS_LOCK => 65, PKT_SRC_ID_H => 85, PKT_SRC_ID_L => 82, PKT_DEST_ID_H => 89, PKT_DEST_ID_L => 86, PKT_BURSTWRAP_H => 72, PKT_BURSTWRAP_L => 70, PKT_BYTE_CNT_H => 69, PKT_BYTE_CNT_L => 67, PKT_PROTECTION_H => 93, PKT_PROTECTION_L => 91, PKT_RESPONSE_STATUS_H => 99, PKT_RESPONSE_STATUS_L => 98, PKT_BURST_SIZE_H => 75, PKT_BURST_SIZE_L => 73, ST_CHANNEL_W => 13, ST_DATA_W => 100, AVS_BURSTCOUNT_W => 3, SUPPRESS_0_BYTEEN_CMD => 0, PREVENT_FIFO_OVERFLOW => 1, USE_READRESPONSE => 0, USE_WRITERESPONSE => 0 ) port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset m0_address => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address m0_burstcount => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount m0_byteenable => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable m0_debugaccess => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess m0_lock => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock m0_readdata => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata m0_readdatavalid => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid m0_read => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read m0_waitrequest => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest m0_writedata => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata m0_write => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write rp_endofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket rp_ready => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready rp_valid => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid rp_data => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data rp_startofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket cp_ready => cmd_xbar_demux_001_src6_ready, -- cp.ready cp_valid => cmd_xbar_demux_001_src6_valid, -- .valid cp_data => cmd_xbar_demux_001_src6_data, -- .data cp_startofpacket => cmd_xbar_demux_001_src6_startofpacket, -- .startofpacket cp_endofpacket => cmd_xbar_demux_001_src6_endofpacket, -- .endofpacket cp_channel => cmd_xbar_demux_001_src6_channel, -- .channel rf_sink_ready => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready rf_sink_valid => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid rf_sink_startofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket rf_sink_endofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket rf_sink_data => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data rf_source_ready => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready rf_source_valid => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid rf_source_startofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket rf_source_endofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket rf_source_data => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data rdata_fifo_sink_ready => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready rdata_fifo_sink_valid => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid rdata_fifo_sink_data => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data rdata_fifo_src_ready => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready rdata_fifo_src_valid => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid rdata_fifo_src_data => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data m0_response => "00", -- (terminated) m0_writeresponserequest => open, -- (terminated) m0_writeresponsevalid => '0' -- (terminated) ); sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo generic map ( SYMBOLS_PER_BEAT => 1, BITS_PER_SYMBOL => 101, FIFO_DEPTH => 2, CHANNEL_WIDTH => 0, ERROR_WIDTH => 0, USE_PACKETS => 1, USE_FILL_LEVEL => 0, EMPTY_LATENCY => 1, USE_MEMORY_BLOCKS => 0, USE_STORE_FORWARD => 0, USE_ALMOST_FULL_IF => 0, USE_ALMOST_EMPTY_IF => 0 ) port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset in_data => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data in_valid => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid in_ready => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready in_startofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket in_endofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket out_data => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data out_valid => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid out_ready => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready out_startofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket out_endofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket csr_address => "00", -- (terminated) csr_read => '0', -- (terminated) csr_write => '0', -- (terminated) csr_readdata => open, -- (terminated) csr_writedata => "00000000000000000000000000000000", -- (terminated) almost_full_data => open, -- (terminated) almost_empty_data => open, -- (terminated) in_empty => '0', -- (terminated) out_empty => open, -- (terminated) in_error => '0', -- (terminated) out_error => open, -- (terminated) in_channel => '0', -- (terminated) out_channel => open -- (terminated) ); green_leds_s1_translator_avalon_universal_slave_0_agent : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent generic map ( PKT_DATA_H => 31, PKT_DATA_L => 0, PKT_BEGIN_BURST => 80, PKT_SYMBOL_W => 8, PKT_BYTEEN_H => 35, PKT_BYTEEN_L => 32, PKT_ADDR_H => 60, PKT_ADDR_L => 36, PKT_TRANS_COMPRESSED_READ => 61, PKT_TRANS_POSTED => 62, PKT_TRANS_WRITE => 63, PKT_TRANS_READ => 64, PKT_TRANS_LOCK => 65, PKT_SRC_ID_H => 85, PKT_SRC_ID_L => 82, PKT_DEST_ID_H => 89, PKT_DEST_ID_L => 86, PKT_BURSTWRAP_H => 72, PKT_BURSTWRAP_L => 70, PKT_BYTE_CNT_H => 69, PKT_BYTE_CNT_L => 67, PKT_PROTECTION_H => 93, PKT_PROTECTION_L => 91, PKT_RESPONSE_STATUS_H => 99, PKT_RESPONSE_STATUS_L => 98, PKT_BURST_SIZE_H => 75, PKT_BURST_SIZE_L => 73, ST_CHANNEL_W => 13, ST_DATA_W => 100, AVS_BURSTCOUNT_W => 3, SUPPRESS_0_BYTEEN_CMD => 0, PREVENT_FIFO_OVERFLOW => 1, USE_READRESPONSE => 0, USE_WRITERESPONSE => 0 ) port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset m0_address => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address m0_burstcount => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount m0_byteenable => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable m0_debugaccess => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess m0_lock => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock m0_readdata => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata m0_readdatavalid => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid m0_read => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_read, -- .read m0_waitrequest => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest m0_writedata => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata m0_write => green_leds_s1_translator_avalon_universal_slave_0_agent_m0_write, -- .write rp_endofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket rp_ready => green_leds_s1_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready rp_valid => green_leds_s1_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid rp_data => green_leds_s1_translator_avalon_universal_slave_0_agent_rp_data, -- .data rp_startofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket cp_ready => cmd_xbar_demux_001_src7_ready, -- cp.ready cp_valid => cmd_xbar_demux_001_src7_valid, -- .valid cp_data => cmd_xbar_demux_001_src7_data, -- .data cp_startofpacket => cmd_xbar_demux_001_src7_startofpacket, -- .startofpacket cp_endofpacket => cmd_xbar_demux_001_src7_endofpacket, -- .endofpacket cp_channel => cmd_xbar_demux_001_src7_channel, -- .channel rf_sink_ready => green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready rf_sink_valid => green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid rf_sink_startofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket rf_sink_endofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket rf_sink_data => green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data rf_source_ready => green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready rf_source_valid => green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid rf_source_startofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket rf_source_endofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket rf_source_data => green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data rdata_fifo_sink_ready => green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready rdata_fifo_sink_valid => green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid rdata_fifo_sink_data => green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data rdata_fifo_src_ready => green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready rdata_fifo_src_valid => green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid rdata_fifo_src_data => green_leds_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data m0_response => "00", -- (terminated) m0_writeresponserequest => open, -- (terminated) m0_writeresponsevalid => '0' -- (terminated) ); green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo generic map ( SYMBOLS_PER_BEAT => 1, BITS_PER_SYMBOL => 101, FIFO_DEPTH => 2, CHANNEL_WIDTH => 0, ERROR_WIDTH => 0, USE_PACKETS => 1, USE_FILL_LEVEL => 0, EMPTY_LATENCY => 1, USE_MEMORY_BLOCKS => 0, USE_STORE_FORWARD => 0, USE_ALMOST_FULL_IF => 0, USE_ALMOST_EMPTY_IF => 0 ) port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset in_data => green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data in_valid => green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid in_ready => green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready in_startofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket in_endofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket out_data => green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data out_valid => green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid out_ready => green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready out_startofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket out_endofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket csr_address => "00", -- (terminated) csr_read => '0', -- (terminated) csr_write => '0', -- (terminated) csr_readdata => open, -- (terminated) csr_writedata => "00000000000000000000000000000000", -- (terminated) almost_full_data => open, -- (terminated) almost_empty_data => open, -- (terminated) in_empty => '0', -- (terminated) out_empty => open, -- (terminated) in_error => '0', -- (terminated) out_error => open, -- (terminated) in_channel => '0', -- (terminated) out_channel => open -- (terminated) ); switches_s1_translator_avalon_universal_slave_0_agent : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent generic map ( PKT_DATA_H => 31, PKT_DATA_L => 0, PKT_BEGIN_BURST => 80, PKT_SYMBOL_W => 8, PKT_BYTEEN_H => 35, PKT_BYTEEN_L => 32, PKT_ADDR_H => 60, PKT_ADDR_L => 36, PKT_TRANS_COMPRESSED_READ => 61, PKT_TRANS_POSTED => 62, PKT_TRANS_WRITE => 63, PKT_TRANS_READ => 64, PKT_TRANS_LOCK => 65, PKT_SRC_ID_H => 85, PKT_SRC_ID_L => 82, PKT_DEST_ID_H => 89, PKT_DEST_ID_L => 86, PKT_BURSTWRAP_H => 72, PKT_BURSTWRAP_L => 70, PKT_BYTE_CNT_H => 69, PKT_BYTE_CNT_L => 67, PKT_PROTECTION_H => 93, PKT_PROTECTION_L => 91, PKT_RESPONSE_STATUS_H => 99, PKT_RESPONSE_STATUS_L => 98, PKT_BURST_SIZE_H => 75, PKT_BURST_SIZE_L => 73, ST_CHANNEL_W => 13, ST_DATA_W => 100, AVS_BURSTCOUNT_W => 3, SUPPRESS_0_BYTEEN_CMD => 0, PREVENT_FIFO_OVERFLOW => 1, USE_READRESPONSE => 0, USE_WRITERESPONSE => 0 ) port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset m0_address => switches_s1_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address m0_burstcount => switches_s1_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount m0_byteenable => switches_s1_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable m0_debugaccess => switches_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess m0_lock => switches_s1_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock m0_readdata => switches_s1_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata m0_readdatavalid => switches_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid m0_read => switches_s1_translator_avalon_universal_slave_0_agent_m0_read, -- .read m0_waitrequest => switches_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest m0_writedata => switches_s1_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata m0_write => switches_s1_translator_avalon_universal_slave_0_agent_m0_write, -- .write rp_endofpacket => switches_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket rp_ready => switches_s1_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready rp_valid => switches_s1_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid rp_data => switches_s1_translator_avalon_universal_slave_0_agent_rp_data, -- .data rp_startofpacket => switches_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket cp_ready => cmd_xbar_demux_001_src8_ready, -- cp.ready cp_valid => cmd_xbar_demux_001_src8_valid, -- .valid cp_data => cmd_xbar_demux_001_src8_data, -- .data cp_startofpacket => cmd_xbar_demux_001_src8_startofpacket, -- .startofpacket cp_endofpacket => cmd_xbar_demux_001_src8_endofpacket, -- .endofpacket cp_channel => cmd_xbar_demux_001_src8_channel, -- .channel rf_sink_ready => switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready rf_sink_valid => switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid rf_sink_startofpacket => switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket rf_sink_endofpacket => switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket rf_sink_data => switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data rf_source_ready => switches_s1_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready rf_source_valid => switches_s1_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid rf_source_startofpacket => switches_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket rf_source_endofpacket => switches_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket rf_source_data => switches_s1_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data rdata_fifo_sink_ready => switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready rdata_fifo_sink_valid => switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid rdata_fifo_sink_data => switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data rdata_fifo_src_ready => switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready rdata_fifo_src_valid => switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid rdata_fifo_src_data => switches_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data m0_response => "00", -- (terminated) m0_writeresponserequest => open, -- (terminated) m0_writeresponsevalid => '0' -- (terminated) ); switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo generic map ( SYMBOLS_PER_BEAT => 1, BITS_PER_SYMBOL => 101, FIFO_DEPTH => 2, CHANNEL_WIDTH => 0, ERROR_WIDTH => 0, USE_PACKETS => 1, USE_FILL_LEVEL => 0, EMPTY_LATENCY => 1, USE_MEMORY_BLOCKS => 0, USE_STORE_FORWARD => 0, USE_ALMOST_FULL_IF => 0, USE_ALMOST_EMPTY_IF => 0 ) port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset in_data => switches_s1_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data in_valid => switches_s1_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid in_ready => switches_s1_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready in_startofpacket => switches_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket in_endofpacket => switches_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket out_data => switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data out_valid => switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid out_ready => switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready out_startofpacket => switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket out_endofpacket => switches_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket csr_address => "00", -- (terminated) csr_read => '0', -- (terminated) csr_write => '0', -- (terminated) csr_readdata => open, -- (terminated) csr_writedata => "00000000000000000000000000000000", -- (terminated) almost_full_data => open, -- (terminated) almost_empty_data => open, -- (terminated) in_empty => '0', -- (terminated) out_empty => open, -- (terminated) in_error => '0', -- (terminated) out_error => open, -- (terminated) in_channel => '0', -- (terminated) out_channel => open -- (terminated) ); altpll_0_pll_slave_translator_avalon_universal_slave_0_agent : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent generic map ( PKT_DATA_H => 31, PKT_DATA_L => 0, PKT_BEGIN_BURST => 80, PKT_SYMBOL_W => 8, PKT_BYTEEN_H => 35, PKT_BYTEEN_L => 32, PKT_ADDR_H => 60, PKT_ADDR_L => 36, PKT_TRANS_COMPRESSED_READ => 61, PKT_TRANS_POSTED => 62, PKT_TRANS_WRITE => 63, PKT_TRANS_READ => 64, PKT_TRANS_LOCK => 65, PKT_SRC_ID_H => 85, PKT_SRC_ID_L => 82, PKT_DEST_ID_H => 89, PKT_DEST_ID_L => 86, PKT_BURSTWRAP_H => 72, PKT_BURSTWRAP_L => 70, PKT_BYTE_CNT_H => 69, PKT_BYTE_CNT_L => 67, PKT_PROTECTION_H => 93, PKT_PROTECTION_L => 91, PKT_RESPONSE_STATUS_H => 99, PKT_RESPONSE_STATUS_L => 98, PKT_BURST_SIZE_H => 75, PKT_BURST_SIZE_L => 73, ST_CHANNEL_W => 13, ST_DATA_W => 100, AVS_BURSTCOUNT_W => 3, SUPPRESS_0_BYTEEN_CMD => 0, PREVENT_FIFO_OVERFLOW => 1, USE_READRESPONSE => 0, USE_WRITERESPONSE => 0 ) port map ( clk => clk_clk, -- clk.clk reset => rst_controller_001_reset_out_reset, -- clk_reset.reset m0_address => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address m0_burstcount => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount m0_byteenable => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable m0_debugaccess => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess m0_lock => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock m0_readdata => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata m0_readdatavalid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid m0_read => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read m0_waitrequest => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest m0_writedata => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata m0_write => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write rp_endofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket rp_ready => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready rp_valid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid rp_data => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data rp_startofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket cp_ready => crosser_out_ready, -- cp.ready cp_valid => crosser_out_valid, -- .valid cp_data => crosser_out_data, -- .data cp_startofpacket => crosser_out_startofpacket, -- .startofpacket cp_endofpacket => crosser_out_endofpacket, -- .endofpacket cp_channel => crosser_out_channel, -- .channel rf_sink_ready => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready rf_sink_valid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid rf_sink_startofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket rf_sink_endofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket rf_sink_data => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data rf_source_ready => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready rf_source_valid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid rf_source_startofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket rf_source_endofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket rf_source_data => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data rdata_fifo_sink_ready => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready, -- rdata_fifo_sink.ready rdata_fifo_sink_valid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid, -- .valid rdata_fifo_sink_data => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data, -- .data rdata_fifo_src_ready => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready rdata_fifo_src_valid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid rdata_fifo_src_data => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data m0_response => "00", -- (terminated) m0_writeresponserequest => open, -- (terminated) m0_writeresponsevalid => '0' -- (terminated) ); altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo generic map ( SYMBOLS_PER_BEAT => 1, BITS_PER_SYMBOL => 101, FIFO_DEPTH => 2, CHANNEL_WIDTH => 0, ERROR_WIDTH => 0, USE_PACKETS => 1, USE_FILL_LEVEL => 0, EMPTY_LATENCY => 1, USE_MEMORY_BLOCKS => 0, USE_STORE_FORWARD => 0, USE_ALMOST_FULL_IF => 0, USE_ALMOST_EMPTY_IF => 0 ) port map ( clk => clk_clk, -- clk.clk reset => rst_controller_001_reset_out_reset, -- clk_reset.reset in_data => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data in_valid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid in_ready => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready in_startofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket in_endofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket out_data => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data out_valid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid out_ready => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready out_startofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket out_endofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket csr_address => "00", -- (terminated) csr_read => '0', -- (terminated) csr_write => '0', -- (terminated) csr_readdata => open, -- (terminated) csr_writedata => "00000000000000000000000000000000", -- (terminated) almost_full_data => open, -- (terminated) almost_empty_data => open, -- (terminated) in_empty => '0', -- (terminated) out_empty => open, -- (terminated) in_error => '0', -- (terminated) out_error => open, -- (terminated) in_channel => '0', -- (terminated) out_channel => open -- (terminated) ); altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo : component niosii_system_altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo generic map ( SYMBOLS_PER_BEAT => 1, BITS_PER_SYMBOL => 34, FIFO_DEPTH => 2, CHANNEL_WIDTH => 0, ERROR_WIDTH => 0, USE_PACKETS => 0, USE_FILL_LEVEL => 0, EMPTY_LATENCY => 0, USE_MEMORY_BLOCKS => 0, USE_STORE_FORWARD => 0, USE_ALMOST_FULL_IF => 0, USE_ALMOST_EMPTY_IF => 0 ) port map ( clk => clk_clk, -- clk.clk reset => rst_controller_001_reset_out_reset, -- clk_reset.reset in_data => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- in.data in_valid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid in_ready => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- .ready out_data => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_data, -- out.data out_valid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_valid, -- .valid out_ready => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_out_ready, -- .ready csr_address => "00", -- (terminated) csr_read => '0', -- (terminated) csr_write => '0', -- (terminated) csr_readdata => open, -- (terminated) csr_writedata => "00000000000000000000000000000000", -- (terminated) almost_full_data => open, -- (terminated) almost_empty_data => open, -- (terminated) in_startofpacket => '0', -- (terminated) in_endofpacket => '0', -- (terminated) out_startofpacket => open, -- (terminated) out_endofpacket => open, -- (terminated) in_empty => '0', -- (terminated) out_empty => open, -- (terminated) in_error => '0', -- (terminated) out_error => open, -- (terminated) in_channel => '0', -- (terminated) out_channel => open -- (terminated) ); timer_0_s1_translator_avalon_universal_slave_0_agent : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent generic map ( PKT_DATA_H => 31, PKT_DATA_L => 0, PKT_BEGIN_BURST => 80, PKT_SYMBOL_W => 8, PKT_BYTEEN_H => 35, PKT_BYTEEN_L => 32, PKT_ADDR_H => 60, PKT_ADDR_L => 36, PKT_TRANS_COMPRESSED_READ => 61, PKT_TRANS_POSTED => 62, PKT_TRANS_WRITE => 63, PKT_TRANS_READ => 64, PKT_TRANS_LOCK => 65, PKT_SRC_ID_H => 85, PKT_SRC_ID_L => 82, PKT_DEST_ID_H => 89, PKT_DEST_ID_L => 86, PKT_BURSTWRAP_H => 72, PKT_BURSTWRAP_L => 70, PKT_BYTE_CNT_H => 69, PKT_BYTE_CNT_L => 67, PKT_PROTECTION_H => 93, PKT_PROTECTION_L => 91, PKT_RESPONSE_STATUS_H => 99, PKT_RESPONSE_STATUS_L => 98, PKT_BURST_SIZE_H => 75, PKT_BURST_SIZE_L => 73, ST_CHANNEL_W => 13, ST_DATA_W => 100, AVS_BURSTCOUNT_W => 3, SUPPRESS_0_BYTEEN_CMD => 0, PREVENT_FIFO_OVERFLOW => 1, USE_READRESPONSE => 0, USE_WRITERESPONSE => 0 ) port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset m0_address => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address m0_burstcount => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount m0_byteenable => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable m0_debugaccess => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess m0_lock => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock m0_readdata => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata m0_readdatavalid => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid m0_read => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_read, -- .read m0_waitrequest => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest m0_writedata => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata m0_write => timer_0_s1_translator_avalon_universal_slave_0_agent_m0_write, -- .write rp_endofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket rp_ready => timer_0_s1_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready rp_valid => timer_0_s1_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid rp_data => timer_0_s1_translator_avalon_universal_slave_0_agent_rp_data, -- .data rp_startofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket cp_ready => cmd_xbar_demux_001_src10_ready, -- cp.ready cp_valid => cmd_xbar_demux_001_src10_valid, -- .valid cp_data => cmd_xbar_demux_001_src10_data, -- .data cp_startofpacket => cmd_xbar_demux_001_src10_startofpacket, -- .startofpacket cp_endofpacket => cmd_xbar_demux_001_src10_endofpacket, -- .endofpacket cp_channel => cmd_xbar_demux_001_src10_channel, -- .channel rf_sink_ready => timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready rf_sink_valid => timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid rf_sink_startofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket rf_sink_endofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket rf_sink_data => timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data rf_source_ready => timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready rf_source_valid => timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid rf_source_startofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket rf_source_endofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket rf_source_data => timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data rdata_fifo_sink_ready => timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready rdata_fifo_sink_valid => timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid rdata_fifo_sink_data => timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data rdata_fifo_src_ready => timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready rdata_fifo_src_valid => timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid rdata_fifo_src_data => timer_0_s1_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data m0_response => "00", -- (terminated) m0_writeresponserequest => open, -- (terminated) m0_writeresponsevalid => '0' -- (terminated) ); timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo generic map ( SYMBOLS_PER_BEAT => 1, BITS_PER_SYMBOL => 101, FIFO_DEPTH => 2, CHANNEL_WIDTH => 0, ERROR_WIDTH => 0, USE_PACKETS => 1, USE_FILL_LEVEL => 0, EMPTY_LATENCY => 1, USE_MEMORY_BLOCKS => 0, USE_STORE_FORWARD => 0, USE_ALMOST_FULL_IF => 0, USE_ALMOST_EMPTY_IF => 0 ) port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset in_data => timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data in_valid => timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid in_ready => timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready in_startofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket in_endofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket out_data => timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data out_valid => timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid out_ready => timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready out_startofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket out_endofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket csr_address => "00", -- (terminated) csr_read => '0', -- (terminated) csr_write => '0', -- (terminated) csr_readdata => open, -- (terminated) csr_writedata => "00000000000000000000000000000000", -- (terminated) almost_full_data => open, -- (terminated) almost_empty_data => open, -- (terminated) in_empty => '0', -- (terminated) out_empty => open, -- (terminated) in_error => '0', -- (terminated) out_error => open, -- (terminated) in_channel => '0', -- (terminated) out_channel => open -- (terminated) ); usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent generic map ( PKT_DATA_H => 31, PKT_DATA_L => 0, PKT_BEGIN_BURST => 80, PKT_SYMBOL_W => 8, PKT_BYTEEN_H => 35, PKT_BYTEEN_L => 32, PKT_ADDR_H => 60, PKT_ADDR_L => 36, PKT_TRANS_COMPRESSED_READ => 61, PKT_TRANS_POSTED => 62, PKT_TRANS_WRITE => 63, PKT_TRANS_READ => 64, PKT_TRANS_LOCK => 65, PKT_SRC_ID_H => 85, PKT_SRC_ID_L => 82, PKT_DEST_ID_H => 89, PKT_DEST_ID_L => 86, PKT_BURSTWRAP_H => 72, PKT_BURSTWRAP_L => 70, PKT_BYTE_CNT_H => 69, PKT_BYTE_CNT_L => 67, PKT_PROTECTION_H => 93, PKT_PROTECTION_L => 91, PKT_RESPONSE_STATUS_H => 99, PKT_RESPONSE_STATUS_L => 98, PKT_BURST_SIZE_H => 75, PKT_BURST_SIZE_L => 73, ST_CHANNEL_W => 13, ST_DATA_W => 100, AVS_BURSTCOUNT_W => 3, SUPPRESS_0_BYTEEN_CMD => 0, PREVENT_FIFO_OVERFLOW => 1, USE_READRESPONSE => 0, USE_WRITERESPONSE => 0 ) port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset m0_address => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address m0_burstcount => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount m0_byteenable => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable m0_debugaccess => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess m0_lock => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock m0_readdata => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata m0_readdatavalid => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid m0_read => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read m0_waitrequest => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest m0_writedata => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata m0_write => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write rp_endofpacket => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket rp_ready => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready rp_valid => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid rp_data => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data rp_startofpacket => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket cp_ready => cmd_xbar_demux_001_src11_ready, -- cp.ready cp_valid => cmd_xbar_demux_001_src11_valid, -- .valid cp_data => cmd_xbar_demux_001_src11_data, -- .data cp_startofpacket => cmd_xbar_demux_001_src11_startofpacket, -- .startofpacket cp_endofpacket => cmd_xbar_demux_001_src11_endofpacket, -- .endofpacket cp_channel => cmd_xbar_demux_001_src11_channel, -- .channel rf_sink_ready => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready rf_sink_valid => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid rf_sink_startofpacket => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket rf_sink_endofpacket => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket rf_sink_data => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data rf_source_ready => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready rf_source_valid => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid rf_source_startofpacket => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket rf_source_endofpacket => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket rf_source_data => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data rdata_fifo_sink_ready => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready rdata_fifo_sink_valid => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid rdata_fifo_sink_data => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data rdata_fifo_src_ready => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready rdata_fifo_src_valid => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid rdata_fifo_src_data => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data m0_response => "00", -- (terminated) m0_writeresponserequest => open, -- (terminated) m0_writeresponsevalid => '0' -- (terminated) ); usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo generic map ( SYMBOLS_PER_BEAT => 1, BITS_PER_SYMBOL => 101, FIFO_DEPTH => 2, CHANNEL_WIDTH => 0, ERROR_WIDTH => 0, USE_PACKETS => 1, USE_FILL_LEVEL => 0, EMPTY_LATENCY => 1, USE_MEMORY_BLOCKS => 0, USE_STORE_FORWARD => 0, USE_ALMOST_FULL_IF => 0, USE_ALMOST_EMPTY_IF => 0 ) port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset in_data => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data in_valid => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid in_ready => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready in_startofpacket => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket in_endofpacket => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket out_data => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data out_valid => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid out_ready => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready out_startofpacket => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket out_endofpacket => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket csr_address => "00", -- (terminated) csr_read => '0', -- (terminated) csr_write => '0', -- (terminated) csr_readdata => open, -- (terminated) csr_writedata => "00000000000000000000000000000000", -- (terminated) almost_full_data => open, -- (terminated) almost_empty_data => open, -- (terminated) in_empty => '0', -- (terminated) out_empty => open, -- (terminated) in_error => '0', -- (terminated) out_error => open, -- (terminated) in_channel => '0', -- (terminated) out_channel => open -- (terminated) ); rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent generic map ( PKT_DATA_H => 31, PKT_DATA_L => 0, PKT_BEGIN_BURST => 80, PKT_SYMBOL_W => 8, PKT_BYTEEN_H => 35, PKT_BYTEEN_L => 32, PKT_ADDR_H => 60, PKT_ADDR_L => 36, PKT_TRANS_COMPRESSED_READ => 61, PKT_TRANS_POSTED => 62, PKT_TRANS_WRITE => 63, PKT_TRANS_READ => 64, PKT_TRANS_LOCK => 65, PKT_SRC_ID_H => 85, PKT_SRC_ID_L => 82, PKT_DEST_ID_H => 89, PKT_DEST_ID_L => 86, PKT_BURSTWRAP_H => 72, PKT_BURSTWRAP_L => 70, PKT_BYTE_CNT_H => 69, PKT_BYTE_CNT_L => 67, PKT_PROTECTION_H => 93, PKT_PROTECTION_L => 91, PKT_RESPONSE_STATUS_H => 99, PKT_RESPONSE_STATUS_L => 98, PKT_BURST_SIZE_H => 75, PKT_BURST_SIZE_L => 73, ST_CHANNEL_W => 13, ST_DATA_W => 100, AVS_BURSTCOUNT_W => 3, SUPPRESS_0_BYTEEN_CMD => 0, PREVENT_FIFO_OVERFLOW => 1, USE_READRESPONSE => 0, USE_WRITERESPONSE => 0 ) port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset m0_address => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_address, -- m0.address m0_burstcount => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_burstcount, -- .burstcount m0_byteenable => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_byteenable, -- .byteenable m0_debugaccess => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_debugaccess, -- .debugaccess m0_lock => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_lock, -- .lock m0_readdata => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_readdata, -- .readdata m0_readdatavalid => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_readdatavalid, -- .readdatavalid m0_read => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_read, -- .read m0_waitrequest => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_waitrequest, -- .waitrequest m0_writedata => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_writedata, -- .writedata m0_write => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_m0_write, -- .write rp_endofpacket => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- rp.endofpacket rp_ready => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- .ready rp_valid => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid rp_data => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data rp_startofpacket => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket cp_ready => cmd_xbar_demux_001_src12_ready, -- cp.ready cp_valid => cmd_xbar_demux_001_src12_valid, -- .valid cp_data => cmd_xbar_demux_001_src12_data, -- .data cp_startofpacket => cmd_xbar_demux_001_src12_startofpacket, -- .startofpacket cp_endofpacket => cmd_xbar_demux_001_src12_endofpacket, -- .endofpacket cp_channel => cmd_xbar_demux_001_src12_channel, -- .channel rf_sink_ready => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- rf_sink.ready rf_sink_valid => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid rf_sink_startofpacket => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket rf_sink_endofpacket => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket rf_sink_data => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- .data rf_source_ready => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- rf_source.ready rf_source_valid => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid rf_source_startofpacket => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket rf_source_endofpacket => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket rf_source_data => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- .data rdata_fifo_sink_ready => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_sink.ready rdata_fifo_sink_valid => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid rdata_fifo_sink_data => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data rdata_fifo_src_ready => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_ready, -- rdata_fifo_src.ready rdata_fifo_src_valid => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_valid, -- .valid rdata_fifo_src_data => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rdata_fifo_src_data, -- .data m0_response => "00", -- (terminated) m0_writeresponserequest => open, -- (terminated) m0_writeresponsevalid => '0' -- (terminated) ); rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo : component niosii_system_nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo generic map ( SYMBOLS_PER_BEAT => 1, BITS_PER_SYMBOL => 101, FIFO_DEPTH => 2, CHANNEL_WIDTH => 0, ERROR_WIDTH => 0, USE_PACKETS => 1, USE_FILL_LEVEL => 0, EMPTY_LATENCY => 1, USE_MEMORY_BLOCKS => 0, USE_STORE_FORWARD => 0, USE_ALMOST_FULL_IF => 0, USE_ALMOST_EMPTY_IF => 0 ) port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset in_data => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_data, -- in.data in_valid => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_valid, -- .valid in_ready => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_ready, -- .ready in_startofpacket => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_startofpacket, -- .startofpacket in_endofpacket => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rf_source_endofpacket, -- .endofpacket out_data => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_data, -- out.data out_valid => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_valid, -- .valid out_ready => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_ready, -- .ready out_startofpacket => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_startofpacket, -- .startofpacket out_endofpacket => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rsp_fifo_out_endofpacket, -- .endofpacket csr_address => "00", -- (terminated) csr_read => '0', -- (terminated) csr_write => '0', -- (terminated) csr_readdata => open, -- (terminated) csr_writedata => "00000000000000000000000000000000", -- (terminated) almost_full_data => open, -- (terminated) almost_empty_data => open, -- (terminated) in_empty => '0', -- (terminated) out_empty => open, -- (terminated) in_error => '0', -- (terminated) out_error => open, -- (terminated) in_channel => '0', -- (terminated) out_channel => open -- (terminated) ); addr_router : component niosII_system_addr_router port map ( sink_ready => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_ready, -- sink.ready sink_valid => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_valid, -- .valid sink_data => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_data, -- .data sink_startofpacket => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_startofpacket, -- .startofpacket sink_endofpacket => nios2_qsys_0_instruction_master_translator_avalon_universal_master_0_agent_cp_endofpacket, -- .endofpacket clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset src_ready => addr_router_src_ready, -- src.ready src_valid => addr_router_src_valid, -- .valid src_data => addr_router_src_data, -- .data src_channel => addr_router_src_channel, -- .channel src_startofpacket => addr_router_src_startofpacket, -- .startofpacket src_endofpacket => addr_router_src_endofpacket -- .endofpacket ); addr_router_001 : component niosII_system_addr_router_001 port map ( sink_ready => nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_ready, -- sink.ready sink_valid => nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_valid, -- .valid sink_data => nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_data, -- .data sink_startofpacket => nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_startofpacket, -- .startofpacket sink_endofpacket => nios2_qsys_0_data_master_translator_avalon_universal_master_0_agent_cp_endofpacket, -- .endofpacket clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset src_ready => addr_router_001_src_ready, -- src.ready src_valid => addr_router_001_src_valid, -- .valid src_data => addr_router_001_src_data, -- .data src_channel => addr_router_001_src_channel, -- .channel src_startofpacket => addr_router_001_src_startofpacket, -- .startofpacket src_endofpacket => addr_router_001_src_endofpacket -- .endofpacket ); id_router : component niosII_system_id_router port map ( sink_ready => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready sink_valid => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid sink_data => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_data, -- .data sink_startofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket sink_endofpacket => nios2_qsys_0_jtag_debug_module_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset src_ready => id_router_src_ready, -- src.ready src_valid => id_router_src_valid, -- .valid src_data => id_router_src_data, -- .data src_channel => id_router_src_channel, -- .channel src_startofpacket => id_router_src_startofpacket, -- .startofpacket src_endofpacket => id_router_src_endofpacket -- .endofpacket ); id_router_001 : component niosII_system_id_router_001 port map ( sink_ready => sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready sink_valid => sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid sink_data => sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_data, -- .data sink_startofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket sink_endofpacket => sdram_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset src_ready => id_router_001_src_ready, -- src.ready src_valid => id_router_001_src_valid, -- .valid src_data => id_router_001_src_data, -- .data src_channel => id_router_001_src_channel, -- .channel src_startofpacket => id_router_001_src_startofpacket, -- .startofpacket src_endofpacket => id_router_001_src_endofpacket -- .endofpacket ); id_router_002 : component niosII_system_id_router port map ( sink_ready => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready sink_valid => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid sink_data => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_data, -- .data sink_startofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket sink_endofpacket => onchip_memory2_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset src_ready => id_router_002_src_ready, -- src.ready src_valid => id_router_002_src_valid, -- .valid src_data => id_router_002_src_data, -- .data src_channel => id_router_002_src_channel, -- .channel src_startofpacket => id_router_002_src_startofpacket, -- .startofpacket src_endofpacket => id_router_002_src_endofpacket -- .endofpacket ); id_router_003 : component niosII_system_id_router_001 port map ( sink_ready => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready sink_valid => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid sink_data => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data sink_startofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket sink_endofpacket => sram_0_avalon_sram_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset src_ready => id_router_003_src_ready, -- src.ready src_valid => id_router_003_src_valid, -- .valid src_data => id_router_003_src_data, -- .data src_channel => id_router_003_src_channel, -- .channel src_startofpacket => id_router_003_src_startofpacket, -- .startofpacket src_endofpacket => id_router_003_src_endofpacket -- .endofpacket ); id_router_004 : component niosII_system_id_router_004 port map ( sink_ready => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready sink_valid => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid sink_data => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rp_data, -- .data sink_startofpacket => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket sink_endofpacket => generic_tristate_controller_0_uas_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset src_ready => id_router_004_src_ready, -- src.ready src_valid => id_router_004_src_valid, -- .valid src_data => id_router_004_src_data, -- .data src_channel => id_router_004_src_channel, -- .channel src_startofpacket => id_router_004_src_startofpacket, -- .startofpacket src_endofpacket => id_router_004_src_endofpacket -- .endofpacket ); id_router_005 : component niosII_system_id_router_005 port map ( sink_ready => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready sink_valid => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid sink_data => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data sink_startofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket sink_endofpacket => jtag_uart_0_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset src_ready => id_router_005_src_ready, -- src.ready src_valid => id_router_005_src_valid, -- .valid src_data => id_router_005_src_data, -- .data src_channel => id_router_005_src_channel, -- .channel src_startofpacket => id_router_005_src_startofpacket, -- .startofpacket src_endofpacket => id_router_005_src_endofpacket -- .endofpacket ); id_router_006 : component niosII_system_id_router_005 port map ( sink_ready => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready sink_valid => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid sink_data => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data sink_startofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket sink_endofpacket => sysid_qsys_0_control_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset src_ready => id_router_006_src_ready, -- src.ready src_valid => id_router_006_src_valid, -- .valid src_data => id_router_006_src_data, -- .data src_channel => id_router_006_src_channel, -- .channel src_startofpacket => id_router_006_src_startofpacket, -- .startofpacket src_endofpacket => id_router_006_src_endofpacket -- .endofpacket ); id_router_007 : component niosII_system_id_router_005 port map ( sink_ready => green_leds_s1_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready sink_valid => green_leds_s1_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid sink_data => green_leds_s1_translator_avalon_universal_slave_0_agent_rp_data, -- .data sink_startofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket sink_endofpacket => green_leds_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset src_ready => id_router_007_src_ready, -- src.ready src_valid => id_router_007_src_valid, -- .valid src_data => id_router_007_src_data, -- .data src_channel => id_router_007_src_channel, -- .channel src_startofpacket => id_router_007_src_startofpacket, -- .startofpacket src_endofpacket => id_router_007_src_endofpacket -- .endofpacket ); id_router_008 : component niosII_system_id_router_005 port map ( sink_ready => switches_s1_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready sink_valid => switches_s1_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid sink_data => switches_s1_translator_avalon_universal_slave_0_agent_rp_data, -- .data sink_startofpacket => switches_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket sink_endofpacket => switches_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset src_ready => id_router_008_src_ready, -- src.ready src_valid => id_router_008_src_valid, -- .valid src_data => id_router_008_src_data, -- .data src_channel => id_router_008_src_channel, -- .channel src_startofpacket => id_router_008_src_startofpacket, -- .startofpacket src_endofpacket => id_router_008_src_endofpacket -- .endofpacket ); id_router_009 : component niosII_system_id_router_005 port map ( sink_ready => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready sink_valid => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid sink_data => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data sink_startofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket sink_endofpacket => altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket clk => clk_clk, -- clk.clk reset => rst_controller_001_reset_out_reset, -- clk_reset.reset src_ready => id_router_009_src_ready, -- src.ready src_valid => id_router_009_src_valid, -- .valid src_data => id_router_009_src_data, -- .data src_channel => id_router_009_src_channel, -- .channel src_startofpacket => id_router_009_src_startofpacket, -- .startofpacket src_endofpacket => id_router_009_src_endofpacket -- .endofpacket ); id_router_010 : component niosII_system_id_router_005 port map ( sink_ready => timer_0_s1_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready sink_valid => timer_0_s1_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid sink_data => timer_0_s1_translator_avalon_universal_slave_0_agent_rp_data, -- .data sink_startofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket sink_endofpacket => timer_0_s1_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset src_ready => id_router_010_src_ready, -- src.ready src_valid => id_router_010_src_valid, -- .valid src_data => id_router_010_src_data, -- .data src_channel => id_router_010_src_channel, -- .channel src_startofpacket => id_router_010_src_startofpacket, -- .startofpacket src_endofpacket => id_router_010_src_endofpacket -- .endofpacket ); id_router_011 : component niosII_system_id_router_005 port map ( sink_ready => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready sink_valid => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid sink_data => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data sink_startofpacket => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket sink_endofpacket => usb_0_avalon_usb_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset src_ready => id_router_011_src_ready, -- src.ready src_valid => id_router_011_src_valid, -- .valid src_data => id_router_011_src_data, -- .data src_channel => id_router_011_src_channel, -- .channel src_startofpacket => id_router_011_src_startofpacket, -- .startofpacket src_endofpacket => id_router_011_src_endofpacket -- .endofpacket ); id_router_012 : component niosII_system_id_router_005 port map ( sink_ready => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_ready, -- sink.ready sink_valid => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_valid, -- .valid sink_data => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_data, -- .data sink_startofpacket => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_startofpacket, -- .startofpacket sink_endofpacket => rs232_0_avalon_rs232_slave_translator_avalon_universal_slave_0_agent_rp_endofpacket, -- .endofpacket clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset src_ready => id_router_012_src_ready, -- src.ready src_valid => id_router_012_src_valid, -- .valid src_data => id_router_012_src_data, -- .data src_channel => id_router_012_src_channel, -- .channel src_startofpacket => id_router_012_src_startofpacket, -- .startofpacket src_endofpacket => id_router_012_src_endofpacket -- .endofpacket ); burst_adapter : component niosii_system_burst_adapter generic map ( PKT_ADDR_H => 42, PKT_ADDR_L => 18, PKT_BEGIN_BURST => 62, PKT_BYTE_CNT_H => 51, PKT_BYTE_CNT_L => 49, PKT_BYTEEN_H => 17, PKT_BYTEEN_L => 16, PKT_BURST_SIZE_H => 57, PKT_BURST_SIZE_L => 55, PKT_BURST_TYPE_H => 59, PKT_BURST_TYPE_L => 58, PKT_BURSTWRAP_H => 54, PKT_BURSTWRAP_L => 52, PKT_TRANS_COMPRESSED_READ => 43, PKT_TRANS_WRITE => 45, PKT_TRANS_READ => 46, OUT_NARROW_SIZE => 0, IN_NARROW_SIZE => 0, OUT_FIXED => 0, OUT_COMPLETE_WRAP => 0, ST_DATA_W => 82, ST_CHANNEL_W => 13, OUT_BYTE_CNT_H => 50, OUT_BURSTWRAP_H => 54, COMPRESSED_READ_SUPPORT => 0, BYTEENABLE_SYNTHESIS => 1, PIPE_INPUTS => 0, NO_WRAP_SUPPORT => 0, BURSTWRAP_CONST_MASK => 3, BURSTWRAP_CONST_VALUE => 3 ) port map ( clk => altpll_0_c1_clk, -- cr0.clk reset => rst_controller_reset_out_reset, -- cr0_reset.reset sink0_valid => width_adapter_src_valid, -- sink0.valid sink0_data => width_adapter_src_data, -- .data sink0_channel => width_adapter_src_channel, -- .channel sink0_startofpacket => width_adapter_src_startofpacket, -- .startofpacket sink0_endofpacket => width_adapter_src_endofpacket, -- .endofpacket sink0_ready => width_adapter_src_ready, -- .ready source0_valid => burst_adapter_source0_valid, -- source0.valid source0_data => burst_adapter_source0_data, -- .data source0_channel => burst_adapter_source0_channel, -- .channel source0_startofpacket => burst_adapter_source0_startofpacket, -- .startofpacket source0_endofpacket => burst_adapter_source0_endofpacket, -- .endofpacket source0_ready => burst_adapter_source0_ready -- .ready ); burst_adapter_001 : component niosii_system_burst_adapter generic map ( PKT_ADDR_H => 42, PKT_ADDR_L => 18, PKT_BEGIN_BURST => 62, PKT_BYTE_CNT_H => 51, PKT_BYTE_CNT_L => 49, PKT_BYTEEN_H => 17, PKT_BYTEEN_L => 16, PKT_BURST_SIZE_H => 57, PKT_BURST_SIZE_L => 55, PKT_BURST_TYPE_H => 59, PKT_BURST_TYPE_L => 58, PKT_BURSTWRAP_H => 54, PKT_BURSTWRAP_L => 52, PKT_TRANS_COMPRESSED_READ => 43, PKT_TRANS_WRITE => 45, PKT_TRANS_READ => 46, OUT_NARROW_SIZE => 0, IN_NARROW_SIZE => 0, OUT_FIXED => 0, OUT_COMPLETE_WRAP => 0, ST_DATA_W => 82, ST_CHANNEL_W => 13, OUT_BYTE_CNT_H => 50, OUT_BURSTWRAP_H => 54, COMPRESSED_READ_SUPPORT => 0, BYTEENABLE_SYNTHESIS => 1, PIPE_INPUTS => 0, NO_WRAP_SUPPORT => 0, BURSTWRAP_CONST_MASK => 3, BURSTWRAP_CONST_VALUE => 3 ) port map ( clk => altpll_0_c1_clk, -- cr0.clk reset => rst_controller_reset_out_reset, -- cr0_reset.reset sink0_valid => width_adapter_002_src_valid, -- sink0.valid sink0_data => width_adapter_002_src_data, -- .data sink0_channel => width_adapter_002_src_channel, -- .channel sink0_startofpacket => width_adapter_002_src_startofpacket, -- .startofpacket sink0_endofpacket => width_adapter_002_src_endofpacket, -- .endofpacket sink0_ready => width_adapter_002_src_ready, -- .ready source0_valid => burst_adapter_001_source0_valid, -- source0.valid source0_data => burst_adapter_001_source0_data, -- .data source0_channel => burst_adapter_001_source0_channel, -- .channel source0_startofpacket => burst_adapter_001_source0_startofpacket, -- .startofpacket source0_endofpacket => burst_adapter_001_source0_endofpacket, -- .endofpacket source0_ready => burst_adapter_001_source0_ready -- .ready ); burst_adapter_002 : component niosii_system_burst_adapter_002 generic map ( PKT_ADDR_H => 33, PKT_ADDR_L => 9, PKT_BEGIN_BURST => 53, PKT_BYTE_CNT_H => 42, PKT_BYTE_CNT_L => 40, PKT_BYTEEN_H => 8, PKT_BYTEEN_L => 8, PKT_BURST_SIZE_H => 48, PKT_BURST_SIZE_L => 46, PKT_BURST_TYPE_H => 50, PKT_BURST_TYPE_L => 49, PKT_BURSTWRAP_H => 45, PKT_BURSTWRAP_L => 43, PKT_TRANS_COMPRESSED_READ => 34, PKT_TRANS_WRITE => 36, PKT_TRANS_READ => 37, OUT_NARROW_SIZE => 0, IN_NARROW_SIZE => 0, OUT_FIXED => 0, OUT_COMPLETE_WRAP => 0, ST_DATA_W => 73, ST_CHANNEL_W => 13, OUT_BYTE_CNT_H => 40, OUT_BURSTWRAP_H => 45, COMPRESSED_READ_SUPPORT => 0, BYTEENABLE_SYNTHESIS => 1, PIPE_INPUTS => 0, NO_WRAP_SUPPORT => 0, BURSTWRAP_CONST_MASK => 3, BURSTWRAP_CONST_VALUE => 3 ) port map ( clk => altpll_0_c1_clk, -- cr0.clk reset => rst_controller_reset_out_reset, -- cr0_reset.reset sink0_valid => width_adapter_004_src_valid, -- sink0.valid sink0_data => width_adapter_004_src_data, -- .data sink0_channel => width_adapter_004_src_channel, -- .channel sink0_startofpacket => width_adapter_004_src_startofpacket, -- .startofpacket sink0_endofpacket => width_adapter_004_src_endofpacket, -- .endofpacket sink0_ready => width_adapter_004_src_ready, -- .ready source0_valid => burst_adapter_002_source0_valid, -- source0.valid source0_data => burst_adapter_002_source0_data, -- .data source0_channel => burst_adapter_002_source0_channel, -- .channel source0_startofpacket => burst_adapter_002_source0_startofpacket, -- .startofpacket source0_endofpacket => burst_adapter_002_source0_endofpacket, -- .endofpacket source0_ready => burst_adapter_002_source0_ready -- .ready ); rst_controller : component niosii_system_rst_controller generic map ( NUM_RESET_INPUTS => 2, OUTPUT_RESET_SYNC_EDGES => "deassert", SYNC_DEPTH => 2, RESET_REQUEST_PRESENT => 1 ) port map ( reset_in0 => reset_reset_n_ports_inv, -- reset_in0.reset reset_in1 => nios2_qsys_0_jtag_debug_module_reset_reset, -- reset_in1.reset clk => altpll_0_c1_clk, -- clk.clk reset_out => rst_controller_reset_out_reset, -- reset_out.reset reset_req => rst_controller_reset_out_reset_req, -- .reset_req reset_in2 => '0', -- (terminated) reset_in3 => '0', -- (terminated) reset_in4 => '0', -- (terminated) reset_in5 => '0', -- (terminated) reset_in6 => '0', -- (terminated) reset_in7 => '0', -- (terminated) reset_in8 => '0', -- (terminated) reset_in9 => '0', -- (terminated) reset_in10 => '0', -- (terminated) reset_in11 => '0', -- (terminated) reset_in12 => '0', -- (terminated) reset_in13 => '0', -- (terminated) reset_in14 => '0', -- (terminated) reset_in15 => '0' -- (terminated) ); rst_controller_001 : component niosii_system_rst_controller_001 generic map ( NUM_RESET_INPUTS => 2, OUTPUT_RESET_SYNC_EDGES => "deassert", SYNC_DEPTH => 2, RESET_REQUEST_PRESENT => 0 ) port map ( reset_in0 => reset_reset_n_ports_inv, -- reset_in0.reset reset_in1 => nios2_qsys_0_jtag_debug_module_reset_reset, -- reset_in1.reset clk => clk_clk, -- clk.clk reset_out => rst_controller_001_reset_out_reset, -- reset_out.reset reset_req => open, -- (terminated) reset_in2 => '0', -- (terminated) reset_in3 => '0', -- (terminated) reset_in4 => '0', -- (terminated) reset_in5 => '0', -- (terminated) reset_in6 => '0', -- (terminated) reset_in7 => '0', -- (terminated) reset_in8 => '0', -- (terminated) reset_in9 => '0', -- (terminated) reset_in10 => '0', -- (terminated) reset_in11 => '0', -- (terminated) reset_in12 => '0', -- (terminated) reset_in13 => '0', -- (terminated) reset_in14 => '0', -- (terminated) reset_in15 => '0' -- (terminated) ); cmd_xbar_demux : component niosII_system_cmd_xbar_demux port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset sink_ready => addr_router_src_ready, -- sink.ready sink_channel => addr_router_src_channel, -- .channel sink_data => addr_router_src_data, -- .data sink_startofpacket => addr_router_src_startofpacket, -- .startofpacket sink_endofpacket => addr_router_src_endofpacket, -- .endofpacket sink_valid(0) => addr_router_src_valid, -- .valid src0_ready => cmd_xbar_demux_src0_ready, -- src0.ready src0_valid => cmd_xbar_demux_src0_valid, -- .valid src0_data => cmd_xbar_demux_src0_data, -- .data src0_channel => cmd_xbar_demux_src0_channel, -- .channel src0_startofpacket => cmd_xbar_demux_src0_startofpacket, -- .startofpacket src0_endofpacket => cmd_xbar_demux_src0_endofpacket, -- .endofpacket src1_ready => cmd_xbar_demux_src1_ready, -- src1.ready src1_valid => cmd_xbar_demux_src1_valid, -- .valid src1_data => cmd_xbar_demux_src1_data, -- .data src1_channel => cmd_xbar_demux_src1_channel, -- .channel src1_startofpacket => cmd_xbar_demux_src1_startofpacket, -- .startofpacket src1_endofpacket => cmd_xbar_demux_src1_endofpacket, -- .endofpacket src2_ready => cmd_xbar_demux_src2_ready, -- src2.ready src2_valid => cmd_xbar_demux_src2_valid, -- .valid src2_data => cmd_xbar_demux_src2_data, -- .data src2_channel => cmd_xbar_demux_src2_channel, -- .channel src2_startofpacket => cmd_xbar_demux_src2_startofpacket, -- .startofpacket src2_endofpacket => cmd_xbar_demux_src2_endofpacket, -- .endofpacket src3_ready => cmd_xbar_demux_src3_ready, -- src3.ready src3_valid => cmd_xbar_demux_src3_valid, -- .valid src3_data => cmd_xbar_demux_src3_data, -- .data src3_channel => cmd_xbar_demux_src3_channel, -- .channel src3_startofpacket => cmd_xbar_demux_src3_startofpacket, -- .startofpacket src3_endofpacket => cmd_xbar_demux_src3_endofpacket, -- .endofpacket src4_ready => cmd_xbar_demux_src4_ready, -- src4.ready src4_valid => cmd_xbar_demux_src4_valid, -- .valid src4_data => cmd_xbar_demux_src4_data, -- .data src4_channel => cmd_xbar_demux_src4_channel, -- .channel src4_startofpacket => cmd_xbar_demux_src4_startofpacket, -- .startofpacket src4_endofpacket => cmd_xbar_demux_src4_endofpacket -- .endofpacket ); cmd_xbar_demux_001 : component niosII_system_cmd_xbar_demux_001 port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset sink_ready => addr_router_001_src_ready, -- sink.ready sink_channel => addr_router_001_src_channel, -- .channel sink_data => addr_router_001_src_data, -- .data sink_startofpacket => addr_router_001_src_startofpacket, -- .startofpacket sink_endofpacket => addr_router_001_src_endofpacket, -- .endofpacket sink_valid(0) => addr_router_001_src_valid, -- .valid src0_ready => cmd_xbar_demux_001_src0_ready, -- src0.ready src0_valid => cmd_xbar_demux_001_src0_valid, -- .valid src0_data => cmd_xbar_demux_001_src0_data, -- .data src0_channel => cmd_xbar_demux_001_src0_channel, -- .channel src0_startofpacket => cmd_xbar_demux_001_src0_startofpacket, -- .startofpacket src0_endofpacket => cmd_xbar_demux_001_src0_endofpacket, -- .endofpacket src1_ready => cmd_xbar_demux_001_src1_ready, -- src1.ready src1_valid => cmd_xbar_demux_001_src1_valid, -- .valid src1_data => cmd_xbar_demux_001_src1_data, -- .data src1_channel => cmd_xbar_demux_001_src1_channel, -- .channel src1_startofpacket => cmd_xbar_demux_001_src1_startofpacket, -- .startofpacket src1_endofpacket => cmd_xbar_demux_001_src1_endofpacket, -- .endofpacket src2_ready => cmd_xbar_demux_001_src2_ready, -- src2.ready src2_valid => cmd_xbar_demux_001_src2_valid, -- .valid src2_data => cmd_xbar_demux_001_src2_data, -- .data src2_channel => cmd_xbar_demux_001_src2_channel, -- .channel src2_startofpacket => cmd_xbar_demux_001_src2_startofpacket, -- .startofpacket src2_endofpacket => cmd_xbar_demux_001_src2_endofpacket, -- .endofpacket src3_ready => cmd_xbar_demux_001_src3_ready, -- src3.ready src3_valid => cmd_xbar_demux_001_src3_valid, -- .valid src3_data => cmd_xbar_demux_001_src3_data, -- .data src3_channel => cmd_xbar_demux_001_src3_channel, -- .channel src3_startofpacket => cmd_xbar_demux_001_src3_startofpacket, -- .startofpacket src3_endofpacket => cmd_xbar_demux_001_src3_endofpacket, -- .endofpacket src4_ready => cmd_xbar_demux_001_src4_ready, -- src4.ready src4_valid => cmd_xbar_demux_001_src4_valid, -- .valid src4_data => cmd_xbar_demux_001_src4_data, -- .data src4_channel => cmd_xbar_demux_001_src4_channel, -- .channel src4_startofpacket => cmd_xbar_demux_001_src4_startofpacket, -- .startofpacket src4_endofpacket => cmd_xbar_demux_001_src4_endofpacket, -- .endofpacket src5_ready => cmd_xbar_demux_001_src5_ready, -- src5.ready src5_valid => cmd_xbar_demux_001_src5_valid, -- .valid src5_data => cmd_xbar_demux_001_src5_data, -- .data src5_channel => cmd_xbar_demux_001_src5_channel, -- .channel src5_startofpacket => cmd_xbar_demux_001_src5_startofpacket, -- .startofpacket src5_endofpacket => cmd_xbar_demux_001_src5_endofpacket, -- .endofpacket src6_ready => cmd_xbar_demux_001_src6_ready, -- src6.ready src6_valid => cmd_xbar_demux_001_src6_valid, -- .valid src6_data => cmd_xbar_demux_001_src6_data, -- .data src6_channel => cmd_xbar_demux_001_src6_channel, -- .channel src6_startofpacket => cmd_xbar_demux_001_src6_startofpacket, -- .startofpacket src6_endofpacket => cmd_xbar_demux_001_src6_endofpacket, -- .endofpacket src7_ready => cmd_xbar_demux_001_src7_ready, -- src7.ready src7_valid => cmd_xbar_demux_001_src7_valid, -- .valid src7_data => cmd_xbar_demux_001_src7_data, -- .data src7_channel => cmd_xbar_demux_001_src7_channel, -- .channel src7_startofpacket => cmd_xbar_demux_001_src7_startofpacket, -- .startofpacket src7_endofpacket => cmd_xbar_demux_001_src7_endofpacket, -- .endofpacket src8_ready => cmd_xbar_demux_001_src8_ready, -- src8.ready src8_valid => cmd_xbar_demux_001_src8_valid, -- .valid src8_data => cmd_xbar_demux_001_src8_data, -- .data src8_channel => cmd_xbar_demux_001_src8_channel, -- .channel src8_startofpacket => cmd_xbar_demux_001_src8_startofpacket, -- .startofpacket src8_endofpacket => cmd_xbar_demux_001_src8_endofpacket, -- .endofpacket src9_ready => cmd_xbar_demux_001_src9_ready, -- src9.ready src9_valid => cmd_xbar_demux_001_src9_valid, -- .valid src9_data => cmd_xbar_demux_001_src9_data, -- .data src9_channel => cmd_xbar_demux_001_src9_channel, -- .channel src9_startofpacket => cmd_xbar_demux_001_src9_startofpacket, -- .startofpacket src9_endofpacket => cmd_xbar_demux_001_src9_endofpacket, -- .endofpacket src10_ready => cmd_xbar_demux_001_src10_ready, -- src10.ready src10_valid => cmd_xbar_demux_001_src10_valid, -- .valid src10_data => cmd_xbar_demux_001_src10_data, -- .data src10_channel => cmd_xbar_demux_001_src10_channel, -- .channel src10_startofpacket => cmd_xbar_demux_001_src10_startofpacket, -- .startofpacket src10_endofpacket => cmd_xbar_demux_001_src10_endofpacket, -- .endofpacket src11_ready => cmd_xbar_demux_001_src11_ready, -- src11.ready src11_valid => cmd_xbar_demux_001_src11_valid, -- .valid src11_data => cmd_xbar_demux_001_src11_data, -- .data src11_channel => cmd_xbar_demux_001_src11_channel, -- .channel src11_startofpacket => cmd_xbar_demux_001_src11_startofpacket, -- .startofpacket src11_endofpacket => cmd_xbar_demux_001_src11_endofpacket, -- .endofpacket src12_ready => cmd_xbar_demux_001_src12_ready, -- src12.ready src12_valid => cmd_xbar_demux_001_src12_valid, -- .valid src12_data => cmd_xbar_demux_001_src12_data, -- .data src12_channel => cmd_xbar_demux_001_src12_channel, -- .channel src12_startofpacket => cmd_xbar_demux_001_src12_startofpacket, -- .startofpacket src12_endofpacket => cmd_xbar_demux_001_src12_endofpacket -- .endofpacket ); cmd_xbar_mux : component niosII_system_cmd_xbar_mux port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset src_ready => cmd_xbar_mux_src_ready, -- src.ready src_valid => cmd_xbar_mux_src_valid, -- .valid src_data => cmd_xbar_mux_src_data, -- .data src_channel => cmd_xbar_mux_src_channel, -- .channel src_startofpacket => cmd_xbar_mux_src_startofpacket, -- .startofpacket src_endofpacket => cmd_xbar_mux_src_endofpacket, -- .endofpacket sink0_ready => cmd_xbar_demux_src0_ready, -- sink0.ready sink0_valid => cmd_xbar_demux_src0_valid, -- .valid sink0_channel => cmd_xbar_demux_src0_channel, -- .channel sink0_data => cmd_xbar_demux_src0_data, -- .data sink0_startofpacket => cmd_xbar_demux_src0_startofpacket, -- .startofpacket sink0_endofpacket => cmd_xbar_demux_src0_endofpacket, -- .endofpacket sink1_ready => cmd_xbar_demux_001_src0_ready, -- sink1.ready sink1_valid => cmd_xbar_demux_001_src0_valid, -- .valid sink1_channel => cmd_xbar_demux_001_src0_channel, -- .channel sink1_data => cmd_xbar_demux_001_src0_data, -- .data sink1_startofpacket => cmd_xbar_demux_001_src0_startofpacket, -- .startofpacket sink1_endofpacket => cmd_xbar_demux_001_src0_endofpacket -- .endofpacket ); cmd_xbar_mux_001 : component niosII_system_cmd_xbar_mux port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset src_ready => cmd_xbar_mux_001_src_ready, -- src.ready src_valid => cmd_xbar_mux_001_src_valid, -- .valid src_data => cmd_xbar_mux_001_src_data, -- .data src_channel => cmd_xbar_mux_001_src_channel, -- .channel src_startofpacket => cmd_xbar_mux_001_src_startofpacket, -- .startofpacket src_endofpacket => cmd_xbar_mux_001_src_endofpacket, -- .endofpacket sink0_ready => cmd_xbar_demux_src1_ready, -- sink0.ready sink0_valid => cmd_xbar_demux_src1_valid, -- .valid sink0_channel => cmd_xbar_demux_src1_channel, -- .channel sink0_data => cmd_xbar_demux_src1_data, -- .data sink0_startofpacket => cmd_xbar_demux_src1_startofpacket, -- .startofpacket sink0_endofpacket => cmd_xbar_demux_src1_endofpacket, -- .endofpacket sink1_ready => cmd_xbar_demux_001_src1_ready, -- sink1.ready sink1_valid => cmd_xbar_demux_001_src1_valid, -- .valid sink1_channel => cmd_xbar_demux_001_src1_channel, -- .channel sink1_data => cmd_xbar_demux_001_src1_data, -- .data sink1_startofpacket => cmd_xbar_demux_001_src1_startofpacket, -- .startofpacket sink1_endofpacket => cmd_xbar_demux_001_src1_endofpacket -- .endofpacket ); cmd_xbar_mux_002 : component niosII_system_cmd_xbar_mux port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset src_ready => cmd_xbar_mux_002_src_ready, -- src.ready src_valid => cmd_xbar_mux_002_src_valid, -- .valid src_data => cmd_xbar_mux_002_src_data, -- .data src_channel => cmd_xbar_mux_002_src_channel, -- .channel src_startofpacket => cmd_xbar_mux_002_src_startofpacket, -- .startofpacket src_endofpacket => cmd_xbar_mux_002_src_endofpacket, -- .endofpacket sink0_ready => cmd_xbar_demux_src2_ready, -- sink0.ready sink0_valid => cmd_xbar_demux_src2_valid, -- .valid sink0_channel => cmd_xbar_demux_src2_channel, -- .channel sink0_data => cmd_xbar_demux_src2_data, -- .data sink0_startofpacket => cmd_xbar_demux_src2_startofpacket, -- .startofpacket sink0_endofpacket => cmd_xbar_demux_src2_endofpacket, -- .endofpacket sink1_ready => cmd_xbar_demux_001_src2_ready, -- sink1.ready sink1_valid => cmd_xbar_demux_001_src2_valid, -- .valid sink1_channel => cmd_xbar_demux_001_src2_channel, -- .channel sink1_data => cmd_xbar_demux_001_src2_data, -- .data sink1_startofpacket => cmd_xbar_demux_001_src2_startofpacket, -- .startofpacket sink1_endofpacket => cmd_xbar_demux_001_src2_endofpacket -- .endofpacket ); cmd_xbar_mux_003 : component niosII_system_cmd_xbar_mux port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset src_ready => cmd_xbar_mux_003_src_ready, -- src.ready src_valid => cmd_xbar_mux_003_src_valid, -- .valid src_data => cmd_xbar_mux_003_src_data, -- .data src_channel => cmd_xbar_mux_003_src_channel, -- .channel src_startofpacket => cmd_xbar_mux_003_src_startofpacket, -- .startofpacket src_endofpacket => cmd_xbar_mux_003_src_endofpacket, -- .endofpacket sink0_ready => cmd_xbar_demux_src3_ready, -- sink0.ready sink0_valid => cmd_xbar_demux_src3_valid, -- .valid sink0_channel => cmd_xbar_demux_src3_channel, -- .channel sink0_data => cmd_xbar_demux_src3_data, -- .data sink0_startofpacket => cmd_xbar_demux_src3_startofpacket, -- .startofpacket sink0_endofpacket => cmd_xbar_demux_src3_endofpacket, -- .endofpacket sink1_ready => cmd_xbar_demux_001_src3_ready, -- sink1.ready sink1_valid => cmd_xbar_demux_001_src3_valid, -- .valid sink1_channel => cmd_xbar_demux_001_src3_channel, -- .channel sink1_data => cmd_xbar_demux_001_src3_data, -- .data sink1_startofpacket => cmd_xbar_demux_001_src3_startofpacket, -- .startofpacket sink1_endofpacket => cmd_xbar_demux_001_src3_endofpacket -- .endofpacket ); cmd_xbar_mux_004 : component niosII_system_cmd_xbar_mux port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset src_ready => cmd_xbar_mux_004_src_ready, -- src.ready src_valid => cmd_xbar_mux_004_src_valid, -- .valid src_data => cmd_xbar_mux_004_src_data, -- .data src_channel => cmd_xbar_mux_004_src_channel, -- .channel src_startofpacket => cmd_xbar_mux_004_src_startofpacket, -- .startofpacket src_endofpacket => cmd_xbar_mux_004_src_endofpacket, -- .endofpacket sink0_ready => cmd_xbar_demux_src4_ready, -- sink0.ready sink0_valid => cmd_xbar_demux_src4_valid, -- .valid sink0_channel => cmd_xbar_demux_src4_channel, -- .channel sink0_data => cmd_xbar_demux_src4_data, -- .data sink0_startofpacket => cmd_xbar_demux_src4_startofpacket, -- .startofpacket sink0_endofpacket => cmd_xbar_demux_src4_endofpacket, -- .endofpacket sink1_ready => cmd_xbar_demux_001_src4_ready, -- sink1.ready sink1_valid => cmd_xbar_demux_001_src4_valid, -- .valid sink1_channel => cmd_xbar_demux_001_src4_channel, -- .channel sink1_data => cmd_xbar_demux_001_src4_data, -- .data sink1_startofpacket => cmd_xbar_demux_001_src4_startofpacket, -- .startofpacket sink1_endofpacket => cmd_xbar_demux_001_src4_endofpacket -- .endofpacket ); rsp_xbar_demux : component niosII_system_rsp_xbar_demux port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset sink_ready => id_router_src_ready, -- sink.ready sink_channel => id_router_src_channel, -- .channel sink_data => id_router_src_data, -- .data sink_startofpacket => id_router_src_startofpacket, -- .startofpacket sink_endofpacket => id_router_src_endofpacket, -- .endofpacket sink_valid(0) => id_router_src_valid, -- .valid src0_ready => rsp_xbar_demux_src0_ready, -- src0.ready src0_valid => rsp_xbar_demux_src0_valid, -- .valid src0_data => rsp_xbar_demux_src0_data, -- .data src0_channel => rsp_xbar_demux_src0_channel, -- .channel src0_startofpacket => rsp_xbar_demux_src0_startofpacket, -- .startofpacket src0_endofpacket => rsp_xbar_demux_src0_endofpacket, -- .endofpacket src1_ready => rsp_xbar_demux_src1_ready, -- src1.ready src1_valid => rsp_xbar_demux_src1_valid, -- .valid src1_data => rsp_xbar_demux_src1_data, -- .data src1_channel => rsp_xbar_demux_src1_channel, -- .channel src1_startofpacket => rsp_xbar_demux_src1_startofpacket, -- .startofpacket src1_endofpacket => rsp_xbar_demux_src1_endofpacket -- .endofpacket ); rsp_xbar_demux_001 : component niosII_system_rsp_xbar_demux port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset sink_ready => width_adapter_001_src_ready, -- sink.ready sink_channel => width_adapter_001_src_channel, -- .channel sink_data => width_adapter_001_src_data, -- .data sink_startofpacket => width_adapter_001_src_startofpacket, -- .startofpacket sink_endofpacket => width_adapter_001_src_endofpacket, -- .endofpacket sink_valid(0) => width_adapter_001_src_valid, -- .valid src0_ready => rsp_xbar_demux_001_src0_ready, -- src0.ready src0_valid => rsp_xbar_demux_001_src0_valid, -- .valid src0_data => rsp_xbar_demux_001_src0_data, -- .data src0_channel => rsp_xbar_demux_001_src0_channel, -- .channel src0_startofpacket => rsp_xbar_demux_001_src0_startofpacket, -- .startofpacket src0_endofpacket => rsp_xbar_demux_001_src0_endofpacket, -- .endofpacket src1_ready => rsp_xbar_demux_001_src1_ready, -- src1.ready src1_valid => rsp_xbar_demux_001_src1_valid, -- .valid src1_data => rsp_xbar_demux_001_src1_data, -- .data src1_channel => rsp_xbar_demux_001_src1_channel, -- .channel src1_startofpacket => rsp_xbar_demux_001_src1_startofpacket, -- .startofpacket src1_endofpacket => rsp_xbar_demux_001_src1_endofpacket -- .endofpacket ); rsp_xbar_demux_002 : component niosII_system_rsp_xbar_demux port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset sink_ready => id_router_002_src_ready, -- sink.ready sink_channel => id_router_002_src_channel, -- .channel sink_data => id_router_002_src_data, -- .data sink_startofpacket => id_router_002_src_startofpacket, -- .startofpacket sink_endofpacket => id_router_002_src_endofpacket, -- .endofpacket sink_valid(0) => id_router_002_src_valid, -- .valid src0_ready => rsp_xbar_demux_002_src0_ready, -- src0.ready src0_valid => rsp_xbar_demux_002_src0_valid, -- .valid src0_data => rsp_xbar_demux_002_src0_data, -- .data src0_channel => rsp_xbar_demux_002_src0_channel, -- .channel src0_startofpacket => rsp_xbar_demux_002_src0_startofpacket, -- .startofpacket src0_endofpacket => rsp_xbar_demux_002_src0_endofpacket, -- .endofpacket src1_ready => rsp_xbar_demux_002_src1_ready, -- src1.ready src1_valid => rsp_xbar_demux_002_src1_valid, -- .valid src1_data => rsp_xbar_demux_002_src1_data, -- .data src1_channel => rsp_xbar_demux_002_src1_channel, -- .channel src1_startofpacket => rsp_xbar_demux_002_src1_startofpacket, -- .startofpacket src1_endofpacket => rsp_xbar_demux_002_src1_endofpacket -- .endofpacket ); rsp_xbar_demux_003 : component niosII_system_rsp_xbar_demux port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset sink_ready => width_adapter_003_src_ready, -- sink.ready sink_channel => width_adapter_003_src_channel, -- .channel sink_data => width_adapter_003_src_data, -- .data sink_startofpacket => width_adapter_003_src_startofpacket, -- .startofpacket sink_endofpacket => width_adapter_003_src_endofpacket, -- .endofpacket sink_valid(0) => width_adapter_003_src_valid, -- .valid src0_ready => rsp_xbar_demux_003_src0_ready, -- src0.ready src0_valid => rsp_xbar_demux_003_src0_valid, -- .valid src0_data => rsp_xbar_demux_003_src0_data, -- .data src0_channel => rsp_xbar_demux_003_src0_channel, -- .channel src0_startofpacket => rsp_xbar_demux_003_src0_startofpacket, -- .startofpacket src0_endofpacket => rsp_xbar_demux_003_src0_endofpacket, -- .endofpacket src1_ready => rsp_xbar_demux_003_src1_ready, -- src1.ready src1_valid => rsp_xbar_demux_003_src1_valid, -- .valid src1_data => rsp_xbar_demux_003_src1_data, -- .data src1_channel => rsp_xbar_demux_003_src1_channel, -- .channel src1_startofpacket => rsp_xbar_demux_003_src1_startofpacket, -- .startofpacket src1_endofpacket => rsp_xbar_demux_003_src1_endofpacket -- .endofpacket ); rsp_xbar_demux_004 : component niosII_system_rsp_xbar_demux port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset sink_ready => width_adapter_005_src_ready, -- sink.ready sink_channel => width_adapter_005_src_channel, -- .channel sink_data => width_adapter_005_src_data, -- .data sink_startofpacket => width_adapter_005_src_startofpacket, -- .startofpacket sink_endofpacket => width_adapter_005_src_endofpacket, -- .endofpacket sink_valid(0) => width_adapter_005_src_valid, -- .valid src0_ready => rsp_xbar_demux_004_src0_ready, -- src0.ready src0_valid => rsp_xbar_demux_004_src0_valid, -- .valid src0_data => rsp_xbar_demux_004_src0_data, -- .data src0_channel => rsp_xbar_demux_004_src0_channel, -- .channel src0_startofpacket => rsp_xbar_demux_004_src0_startofpacket, -- .startofpacket src0_endofpacket => rsp_xbar_demux_004_src0_endofpacket, -- .endofpacket src1_ready => rsp_xbar_demux_004_src1_ready, -- src1.ready src1_valid => rsp_xbar_demux_004_src1_valid, -- .valid src1_data => rsp_xbar_demux_004_src1_data, -- .data src1_channel => rsp_xbar_demux_004_src1_channel, -- .channel src1_startofpacket => rsp_xbar_demux_004_src1_startofpacket, -- .startofpacket src1_endofpacket => rsp_xbar_demux_004_src1_endofpacket -- .endofpacket ); rsp_xbar_demux_005 : component niosII_system_rsp_xbar_demux_005 port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset sink_ready => id_router_005_src_ready, -- sink.ready sink_channel => id_router_005_src_channel, -- .channel sink_data => id_router_005_src_data, -- .data sink_startofpacket => id_router_005_src_startofpacket, -- .startofpacket sink_endofpacket => id_router_005_src_endofpacket, -- .endofpacket sink_valid(0) => id_router_005_src_valid, -- .valid src0_ready => rsp_xbar_demux_005_src0_ready, -- src0.ready src0_valid => rsp_xbar_demux_005_src0_valid, -- .valid src0_data => rsp_xbar_demux_005_src0_data, -- .data src0_channel => rsp_xbar_demux_005_src0_channel, -- .channel src0_startofpacket => rsp_xbar_demux_005_src0_startofpacket, -- .startofpacket src0_endofpacket => rsp_xbar_demux_005_src0_endofpacket -- .endofpacket ); rsp_xbar_demux_006 : component niosII_system_rsp_xbar_demux_005 port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset sink_ready => id_router_006_src_ready, -- sink.ready sink_channel => id_router_006_src_channel, -- .channel sink_data => id_router_006_src_data, -- .data sink_startofpacket => id_router_006_src_startofpacket, -- .startofpacket sink_endofpacket => id_router_006_src_endofpacket, -- .endofpacket sink_valid(0) => id_router_006_src_valid, -- .valid src0_ready => rsp_xbar_demux_006_src0_ready, -- src0.ready src0_valid => rsp_xbar_demux_006_src0_valid, -- .valid src0_data => rsp_xbar_demux_006_src0_data, -- .data src0_channel => rsp_xbar_demux_006_src0_channel, -- .channel src0_startofpacket => rsp_xbar_demux_006_src0_startofpacket, -- .startofpacket src0_endofpacket => rsp_xbar_demux_006_src0_endofpacket -- .endofpacket ); rsp_xbar_demux_007 : component niosII_system_rsp_xbar_demux_005 port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset sink_ready => id_router_007_src_ready, -- sink.ready sink_channel => id_router_007_src_channel, -- .channel sink_data => id_router_007_src_data, -- .data sink_startofpacket => id_router_007_src_startofpacket, -- .startofpacket sink_endofpacket => id_router_007_src_endofpacket, -- .endofpacket sink_valid(0) => id_router_007_src_valid, -- .valid src0_ready => rsp_xbar_demux_007_src0_ready, -- src0.ready src0_valid => rsp_xbar_demux_007_src0_valid, -- .valid src0_data => rsp_xbar_demux_007_src0_data, -- .data src0_channel => rsp_xbar_demux_007_src0_channel, -- .channel src0_startofpacket => rsp_xbar_demux_007_src0_startofpacket, -- .startofpacket src0_endofpacket => rsp_xbar_demux_007_src0_endofpacket -- .endofpacket ); rsp_xbar_demux_008 : component niosII_system_rsp_xbar_demux_005 port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset sink_ready => id_router_008_src_ready, -- sink.ready sink_channel => id_router_008_src_channel, -- .channel sink_data => id_router_008_src_data, -- .data sink_startofpacket => id_router_008_src_startofpacket, -- .startofpacket sink_endofpacket => id_router_008_src_endofpacket, -- .endofpacket sink_valid(0) => id_router_008_src_valid, -- .valid src0_ready => rsp_xbar_demux_008_src0_ready, -- src0.ready src0_valid => rsp_xbar_demux_008_src0_valid, -- .valid src0_data => rsp_xbar_demux_008_src0_data, -- .data src0_channel => rsp_xbar_demux_008_src0_channel, -- .channel src0_startofpacket => rsp_xbar_demux_008_src0_startofpacket, -- .startofpacket src0_endofpacket => rsp_xbar_demux_008_src0_endofpacket -- .endofpacket ); rsp_xbar_demux_009 : component niosII_system_rsp_xbar_demux_005 port map ( clk => clk_clk, -- clk.clk reset => rst_controller_001_reset_out_reset, -- clk_reset.reset sink_ready => id_router_009_src_ready, -- sink.ready sink_channel => id_router_009_src_channel, -- .channel sink_data => id_router_009_src_data, -- .data sink_startofpacket => id_router_009_src_startofpacket, -- .startofpacket sink_endofpacket => id_router_009_src_endofpacket, -- .endofpacket sink_valid(0) => id_router_009_src_valid, -- .valid src0_ready => rsp_xbar_demux_009_src0_ready, -- src0.ready src0_valid => rsp_xbar_demux_009_src0_valid, -- .valid src0_data => rsp_xbar_demux_009_src0_data, -- .data src0_channel => rsp_xbar_demux_009_src0_channel, -- .channel src0_startofpacket => rsp_xbar_demux_009_src0_startofpacket, -- .startofpacket src0_endofpacket => rsp_xbar_demux_009_src0_endofpacket -- .endofpacket ); rsp_xbar_demux_010 : component niosII_system_rsp_xbar_demux_005 port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset sink_ready => id_router_010_src_ready, -- sink.ready sink_channel => id_router_010_src_channel, -- .channel sink_data => id_router_010_src_data, -- .data sink_startofpacket => id_router_010_src_startofpacket, -- .startofpacket sink_endofpacket => id_router_010_src_endofpacket, -- .endofpacket sink_valid(0) => id_router_010_src_valid, -- .valid src0_ready => rsp_xbar_demux_010_src0_ready, -- src0.ready src0_valid => rsp_xbar_demux_010_src0_valid, -- .valid src0_data => rsp_xbar_demux_010_src0_data, -- .data src0_channel => rsp_xbar_demux_010_src0_channel, -- .channel src0_startofpacket => rsp_xbar_demux_010_src0_startofpacket, -- .startofpacket src0_endofpacket => rsp_xbar_demux_010_src0_endofpacket -- .endofpacket ); rsp_xbar_demux_011 : component niosII_system_rsp_xbar_demux_005 port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset sink_ready => id_router_011_src_ready, -- sink.ready sink_channel => id_router_011_src_channel, -- .channel sink_data => id_router_011_src_data, -- .data sink_startofpacket => id_router_011_src_startofpacket, -- .startofpacket sink_endofpacket => id_router_011_src_endofpacket, -- .endofpacket sink_valid(0) => id_router_011_src_valid, -- .valid src0_ready => rsp_xbar_demux_011_src0_ready, -- src0.ready src0_valid => rsp_xbar_demux_011_src0_valid, -- .valid src0_data => rsp_xbar_demux_011_src0_data, -- .data src0_channel => rsp_xbar_demux_011_src0_channel, -- .channel src0_startofpacket => rsp_xbar_demux_011_src0_startofpacket, -- .startofpacket src0_endofpacket => rsp_xbar_demux_011_src0_endofpacket -- .endofpacket ); rsp_xbar_demux_012 : component niosII_system_rsp_xbar_demux_005 port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset sink_ready => id_router_012_src_ready, -- sink.ready sink_channel => id_router_012_src_channel, -- .channel sink_data => id_router_012_src_data, -- .data sink_startofpacket => id_router_012_src_startofpacket, -- .startofpacket sink_endofpacket => id_router_012_src_endofpacket, -- .endofpacket sink_valid(0) => id_router_012_src_valid, -- .valid src0_ready => rsp_xbar_demux_012_src0_ready, -- src0.ready src0_valid => rsp_xbar_demux_012_src0_valid, -- .valid src0_data => rsp_xbar_demux_012_src0_data, -- .data src0_channel => rsp_xbar_demux_012_src0_channel, -- .channel src0_startofpacket => rsp_xbar_demux_012_src0_startofpacket, -- .startofpacket src0_endofpacket => rsp_xbar_demux_012_src0_endofpacket -- .endofpacket ); rsp_xbar_mux : component niosII_system_rsp_xbar_mux port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset src_ready => rsp_xbar_mux_src_ready, -- src.ready src_valid => rsp_xbar_mux_src_valid, -- .valid src_data => rsp_xbar_mux_src_data, -- .data src_channel => rsp_xbar_mux_src_channel, -- .channel src_startofpacket => rsp_xbar_mux_src_startofpacket, -- .startofpacket src_endofpacket => rsp_xbar_mux_src_endofpacket, -- .endofpacket sink0_ready => rsp_xbar_demux_src0_ready, -- sink0.ready sink0_valid => rsp_xbar_demux_src0_valid, -- .valid sink0_channel => rsp_xbar_demux_src0_channel, -- .channel sink0_data => rsp_xbar_demux_src0_data, -- .data sink0_startofpacket => rsp_xbar_demux_src0_startofpacket, -- .startofpacket sink0_endofpacket => rsp_xbar_demux_src0_endofpacket, -- .endofpacket sink1_ready => rsp_xbar_demux_001_src0_ready, -- sink1.ready sink1_valid => rsp_xbar_demux_001_src0_valid, -- .valid sink1_channel => rsp_xbar_demux_001_src0_channel, -- .channel sink1_data => rsp_xbar_demux_001_src0_data, -- .data sink1_startofpacket => rsp_xbar_demux_001_src0_startofpacket, -- .startofpacket sink1_endofpacket => rsp_xbar_demux_001_src0_endofpacket, -- .endofpacket sink2_ready => rsp_xbar_demux_002_src0_ready, -- sink2.ready sink2_valid => rsp_xbar_demux_002_src0_valid, -- .valid sink2_channel => rsp_xbar_demux_002_src0_channel, -- .channel sink2_data => rsp_xbar_demux_002_src0_data, -- .data sink2_startofpacket => rsp_xbar_demux_002_src0_startofpacket, -- .startofpacket sink2_endofpacket => rsp_xbar_demux_002_src0_endofpacket, -- .endofpacket sink3_ready => rsp_xbar_demux_003_src0_ready, -- sink3.ready sink3_valid => rsp_xbar_demux_003_src0_valid, -- .valid sink3_channel => rsp_xbar_demux_003_src0_channel, -- .channel sink3_data => rsp_xbar_demux_003_src0_data, -- .data sink3_startofpacket => rsp_xbar_demux_003_src0_startofpacket, -- .startofpacket sink3_endofpacket => rsp_xbar_demux_003_src0_endofpacket, -- .endofpacket sink4_ready => rsp_xbar_demux_004_src0_ready, -- sink4.ready sink4_valid => rsp_xbar_demux_004_src0_valid, -- .valid sink4_channel => rsp_xbar_demux_004_src0_channel, -- .channel sink4_data => rsp_xbar_demux_004_src0_data, -- .data sink4_startofpacket => rsp_xbar_demux_004_src0_startofpacket, -- .startofpacket sink4_endofpacket => rsp_xbar_demux_004_src0_endofpacket -- .endofpacket ); rsp_xbar_mux_001 : component niosII_system_rsp_xbar_mux_001 port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset src_ready => rsp_xbar_mux_001_src_ready, -- src.ready src_valid => rsp_xbar_mux_001_src_valid, -- .valid src_data => rsp_xbar_mux_001_src_data, -- .data src_channel => rsp_xbar_mux_001_src_channel, -- .channel src_startofpacket => rsp_xbar_mux_001_src_startofpacket, -- .startofpacket src_endofpacket => rsp_xbar_mux_001_src_endofpacket, -- .endofpacket sink0_ready => rsp_xbar_demux_src1_ready, -- sink0.ready sink0_valid => rsp_xbar_demux_src1_valid, -- .valid sink0_channel => rsp_xbar_demux_src1_channel, -- .channel sink0_data => rsp_xbar_demux_src1_data, -- .data sink0_startofpacket => rsp_xbar_demux_src1_startofpacket, -- .startofpacket sink0_endofpacket => rsp_xbar_demux_src1_endofpacket, -- .endofpacket sink1_ready => rsp_xbar_demux_001_src1_ready, -- sink1.ready sink1_valid => rsp_xbar_demux_001_src1_valid, -- .valid sink1_channel => rsp_xbar_demux_001_src1_channel, -- .channel sink1_data => rsp_xbar_demux_001_src1_data, -- .data sink1_startofpacket => rsp_xbar_demux_001_src1_startofpacket, -- .startofpacket sink1_endofpacket => rsp_xbar_demux_001_src1_endofpacket, -- .endofpacket sink2_ready => rsp_xbar_demux_002_src1_ready, -- sink2.ready sink2_valid => rsp_xbar_demux_002_src1_valid, -- .valid sink2_channel => rsp_xbar_demux_002_src1_channel, -- .channel sink2_data => rsp_xbar_demux_002_src1_data, -- .data sink2_startofpacket => rsp_xbar_demux_002_src1_startofpacket, -- .startofpacket sink2_endofpacket => rsp_xbar_demux_002_src1_endofpacket, -- .endofpacket sink3_ready => rsp_xbar_demux_003_src1_ready, -- sink3.ready sink3_valid => rsp_xbar_demux_003_src1_valid, -- .valid sink3_channel => rsp_xbar_demux_003_src1_channel, -- .channel sink3_data => rsp_xbar_demux_003_src1_data, -- .data sink3_startofpacket => rsp_xbar_demux_003_src1_startofpacket, -- .startofpacket sink3_endofpacket => rsp_xbar_demux_003_src1_endofpacket, -- .endofpacket sink4_ready => rsp_xbar_demux_004_src1_ready, -- sink4.ready sink4_valid => rsp_xbar_demux_004_src1_valid, -- .valid sink4_channel => rsp_xbar_demux_004_src1_channel, -- .channel sink4_data => rsp_xbar_demux_004_src1_data, -- .data sink4_startofpacket => rsp_xbar_demux_004_src1_startofpacket, -- .startofpacket sink4_endofpacket => rsp_xbar_demux_004_src1_endofpacket, -- .endofpacket sink5_ready => rsp_xbar_demux_005_src0_ready, -- sink5.ready sink5_valid => rsp_xbar_demux_005_src0_valid, -- .valid sink5_channel => rsp_xbar_demux_005_src0_channel, -- .channel sink5_data => rsp_xbar_demux_005_src0_data, -- .data sink5_startofpacket => rsp_xbar_demux_005_src0_startofpacket, -- .startofpacket sink5_endofpacket => rsp_xbar_demux_005_src0_endofpacket, -- .endofpacket sink6_ready => rsp_xbar_demux_006_src0_ready, -- sink6.ready sink6_valid => rsp_xbar_demux_006_src0_valid, -- .valid sink6_channel => rsp_xbar_demux_006_src0_channel, -- .channel sink6_data => rsp_xbar_demux_006_src0_data, -- .data sink6_startofpacket => rsp_xbar_demux_006_src0_startofpacket, -- .startofpacket sink6_endofpacket => rsp_xbar_demux_006_src0_endofpacket, -- .endofpacket sink7_ready => rsp_xbar_demux_007_src0_ready, -- sink7.ready sink7_valid => rsp_xbar_demux_007_src0_valid, -- .valid sink7_channel => rsp_xbar_demux_007_src0_channel, -- .channel sink7_data => rsp_xbar_demux_007_src0_data, -- .data sink7_startofpacket => rsp_xbar_demux_007_src0_startofpacket, -- .startofpacket sink7_endofpacket => rsp_xbar_demux_007_src0_endofpacket, -- .endofpacket sink8_ready => rsp_xbar_demux_008_src0_ready, -- sink8.ready sink8_valid => rsp_xbar_demux_008_src0_valid, -- .valid sink8_channel => rsp_xbar_demux_008_src0_channel, -- .channel sink8_data => rsp_xbar_demux_008_src0_data, -- .data sink8_startofpacket => rsp_xbar_demux_008_src0_startofpacket, -- .startofpacket sink8_endofpacket => rsp_xbar_demux_008_src0_endofpacket, -- .endofpacket sink9_ready => crosser_001_out_ready, -- sink9.ready sink9_valid => crosser_001_out_valid, -- .valid sink9_channel => crosser_001_out_channel, -- .channel sink9_data => crosser_001_out_data, -- .data sink9_startofpacket => crosser_001_out_startofpacket, -- .startofpacket sink9_endofpacket => crosser_001_out_endofpacket, -- .endofpacket sink10_ready => rsp_xbar_demux_010_src0_ready, -- sink10.ready sink10_valid => rsp_xbar_demux_010_src0_valid, -- .valid sink10_channel => rsp_xbar_demux_010_src0_channel, -- .channel sink10_data => rsp_xbar_demux_010_src0_data, -- .data sink10_startofpacket => rsp_xbar_demux_010_src0_startofpacket, -- .startofpacket sink10_endofpacket => rsp_xbar_demux_010_src0_endofpacket, -- .endofpacket sink11_ready => rsp_xbar_demux_011_src0_ready, -- sink11.ready sink11_valid => rsp_xbar_demux_011_src0_valid, -- .valid sink11_channel => rsp_xbar_demux_011_src0_channel, -- .channel sink11_data => rsp_xbar_demux_011_src0_data, -- .data sink11_startofpacket => rsp_xbar_demux_011_src0_startofpacket, -- .startofpacket sink11_endofpacket => rsp_xbar_demux_011_src0_endofpacket, -- .endofpacket sink12_ready => rsp_xbar_demux_012_src0_ready, -- sink12.ready sink12_valid => rsp_xbar_demux_012_src0_valid, -- .valid sink12_channel => rsp_xbar_demux_012_src0_channel, -- .channel sink12_data => rsp_xbar_demux_012_src0_data, -- .data sink12_startofpacket => rsp_xbar_demux_012_src0_startofpacket, -- .startofpacket sink12_endofpacket => rsp_xbar_demux_012_src0_endofpacket -- .endofpacket ); width_adapter : component niosii_system_width_adapter generic map ( IN_PKT_ADDR_H => 60, IN_PKT_ADDR_L => 36, IN_PKT_DATA_H => 31, IN_PKT_DATA_L => 0, IN_PKT_BYTEEN_H => 35, IN_PKT_BYTEEN_L => 32, IN_PKT_BYTE_CNT_H => 69, IN_PKT_BYTE_CNT_L => 67, IN_PKT_TRANS_COMPRESSED_READ => 61, IN_PKT_BURSTWRAP_H => 72, IN_PKT_BURSTWRAP_L => 70, IN_PKT_BURST_SIZE_H => 75, IN_PKT_BURST_SIZE_L => 73, IN_PKT_RESPONSE_STATUS_H => 99, IN_PKT_RESPONSE_STATUS_L => 98, IN_PKT_TRANS_EXCLUSIVE => 66, IN_PKT_BURST_TYPE_H => 77, IN_PKT_BURST_TYPE_L => 76, IN_ST_DATA_W => 100, OUT_PKT_ADDR_H => 42, OUT_PKT_ADDR_L => 18, OUT_PKT_DATA_H => 15, OUT_PKT_DATA_L => 0, OUT_PKT_BYTEEN_H => 17, OUT_PKT_BYTEEN_L => 16, OUT_PKT_BYTE_CNT_H => 51, OUT_PKT_BYTE_CNT_L => 49, OUT_PKT_TRANS_COMPRESSED_READ => 43, OUT_PKT_BURST_SIZE_H => 57, OUT_PKT_BURST_SIZE_L => 55, OUT_PKT_RESPONSE_STATUS_H => 81, OUT_PKT_RESPONSE_STATUS_L => 80, OUT_PKT_TRANS_EXCLUSIVE => 48, OUT_PKT_BURST_TYPE_H => 59, OUT_PKT_BURST_TYPE_L => 58, OUT_ST_DATA_W => 82, ST_CHANNEL_W => 13, OPTIMIZE_FOR_RSP => 0, RESPONSE_PATH => 0 ) port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset in_valid => cmd_xbar_mux_001_src_valid, -- sink.valid in_channel => cmd_xbar_mux_001_src_channel, -- .channel in_startofpacket => cmd_xbar_mux_001_src_startofpacket, -- .startofpacket in_endofpacket => cmd_xbar_mux_001_src_endofpacket, -- .endofpacket in_ready => cmd_xbar_mux_001_src_ready, -- .ready in_data => cmd_xbar_mux_001_src_data, -- .data out_endofpacket => width_adapter_src_endofpacket, -- src.endofpacket out_data => width_adapter_src_data, -- .data out_channel => width_adapter_src_channel, -- .channel out_valid => width_adapter_src_valid, -- .valid out_ready => width_adapter_src_ready, -- .ready out_startofpacket => width_adapter_src_startofpacket, -- .startofpacket in_command_size_data => "000" -- (terminated) ); width_adapter_001 : component niosii_system_width_adapter_001 generic map ( IN_PKT_ADDR_H => 42, IN_PKT_ADDR_L => 18, IN_PKT_DATA_H => 15, IN_PKT_DATA_L => 0, IN_PKT_BYTEEN_H => 17, IN_PKT_BYTEEN_L => 16, IN_PKT_BYTE_CNT_H => 51, IN_PKT_BYTE_CNT_L => 49, IN_PKT_TRANS_COMPRESSED_READ => 43, IN_PKT_BURSTWRAP_H => 54, IN_PKT_BURSTWRAP_L => 52, IN_PKT_BURST_SIZE_H => 57, IN_PKT_BURST_SIZE_L => 55, IN_PKT_RESPONSE_STATUS_H => 81, IN_PKT_RESPONSE_STATUS_L => 80, IN_PKT_TRANS_EXCLUSIVE => 48, IN_PKT_BURST_TYPE_H => 59, IN_PKT_BURST_TYPE_L => 58, IN_ST_DATA_W => 82, OUT_PKT_ADDR_H => 60, OUT_PKT_ADDR_L => 36, OUT_PKT_DATA_H => 31, OUT_PKT_DATA_L => 0, OUT_PKT_BYTEEN_H => 35, OUT_PKT_BYTEEN_L => 32, OUT_PKT_BYTE_CNT_H => 69, OUT_PKT_BYTE_CNT_L => 67, OUT_PKT_TRANS_COMPRESSED_READ => 61, OUT_PKT_BURST_SIZE_H => 75, OUT_PKT_BURST_SIZE_L => 73, OUT_PKT_RESPONSE_STATUS_H => 99, OUT_PKT_RESPONSE_STATUS_L => 98, OUT_PKT_TRANS_EXCLUSIVE => 66, OUT_PKT_BURST_TYPE_H => 77, OUT_PKT_BURST_TYPE_L => 76, OUT_ST_DATA_W => 100, ST_CHANNEL_W => 13, OPTIMIZE_FOR_RSP => 1, RESPONSE_PATH => 1 ) port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset in_valid => id_router_001_src_valid, -- sink.valid in_channel => id_router_001_src_channel, -- .channel in_startofpacket => id_router_001_src_startofpacket, -- .startofpacket in_endofpacket => id_router_001_src_endofpacket, -- .endofpacket in_ready => id_router_001_src_ready, -- .ready in_data => id_router_001_src_data, -- .data out_endofpacket => width_adapter_001_src_endofpacket, -- src.endofpacket out_data => width_adapter_001_src_data, -- .data out_channel => width_adapter_001_src_channel, -- .channel out_valid => width_adapter_001_src_valid, -- .valid out_ready => width_adapter_001_src_ready, -- .ready out_startofpacket => width_adapter_001_src_startofpacket, -- .startofpacket in_command_size_data => "000" -- (terminated) ); width_adapter_002 : component niosii_system_width_adapter generic map ( IN_PKT_ADDR_H => 60, IN_PKT_ADDR_L => 36, IN_PKT_DATA_H => 31, IN_PKT_DATA_L => 0, IN_PKT_BYTEEN_H => 35, IN_PKT_BYTEEN_L => 32, IN_PKT_BYTE_CNT_H => 69, IN_PKT_BYTE_CNT_L => 67, IN_PKT_TRANS_COMPRESSED_READ => 61, IN_PKT_BURSTWRAP_H => 72, IN_PKT_BURSTWRAP_L => 70, IN_PKT_BURST_SIZE_H => 75, IN_PKT_BURST_SIZE_L => 73, IN_PKT_RESPONSE_STATUS_H => 99, IN_PKT_RESPONSE_STATUS_L => 98, IN_PKT_TRANS_EXCLUSIVE => 66, IN_PKT_BURST_TYPE_H => 77, IN_PKT_BURST_TYPE_L => 76, IN_ST_DATA_W => 100, OUT_PKT_ADDR_H => 42, OUT_PKT_ADDR_L => 18, OUT_PKT_DATA_H => 15, OUT_PKT_DATA_L => 0, OUT_PKT_BYTEEN_H => 17, OUT_PKT_BYTEEN_L => 16, OUT_PKT_BYTE_CNT_H => 51, OUT_PKT_BYTE_CNT_L => 49, OUT_PKT_TRANS_COMPRESSED_READ => 43, OUT_PKT_BURST_SIZE_H => 57, OUT_PKT_BURST_SIZE_L => 55, OUT_PKT_RESPONSE_STATUS_H => 81, OUT_PKT_RESPONSE_STATUS_L => 80, OUT_PKT_TRANS_EXCLUSIVE => 48, OUT_PKT_BURST_TYPE_H => 59, OUT_PKT_BURST_TYPE_L => 58, OUT_ST_DATA_W => 82, ST_CHANNEL_W => 13, OPTIMIZE_FOR_RSP => 0, RESPONSE_PATH => 0 ) port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset in_valid => cmd_xbar_mux_003_src_valid, -- sink.valid in_channel => cmd_xbar_mux_003_src_channel, -- .channel in_startofpacket => cmd_xbar_mux_003_src_startofpacket, -- .startofpacket in_endofpacket => cmd_xbar_mux_003_src_endofpacket, -- .endofpacket in_ready => cmd_xbar_mux_003_src_ready, -- .ready in_data => cmd_xbar_mux_003_src_data, -- .data out_endofpacket => width_adapter_002_src_endofpacket, -- src.endofpacket out_data => width_adapter_002_src_data, -- .data out_channel => width_adapter_002_src_channel, -- .channel out_valid => width_adapter_002_src_valid, -- .valid out_ready => width_adapter_002_src_ready, -- .ready out_startofpacket => width_adapter_002_src_startofpacket, -- .startofpacket in_command_size_data => "000" -- (terminated) ); width_adapter_003 : component niosii_system_width_adapter_001 generic map ( IN_PKT_ADDR_H => 42, IN_PKT_ADDR_L => 18, IN_PKT_DATA_H => 15, IN_PKT_DATA_L => 0, IN_PKT_BYTEEN_H => 17, IN_PKT_BYTEEN_L => 16, IN_PKT_BYTE_CNT_H => 51, IN_PKT_BYTE_CNT_L => 49, IN_PKT_TRANS_COMPRESSED_READ => 43, IN_PKT_BURSTWRAP_H => 54, IN_PKT_BURSTWRAP_L => 52, IN_PKT_BURST_SIZE_H => 57, IN_PKT_BURST_SIZE_L => 55, IN_PKT_RESPONSE_STATUS_H => 81, IN_PKT_RESPONSE_STATUS_L => 80, IN_PKT_TRANS_EXCLUSIVE => 48, IN_PKT_BURST_TYPE_H => 59, IN_PKT_BURST_TYPE_L => 58, IN_ST_DATA_W => 82, OUT_PKT_ADDR_H => 60, OUT_PKT_ADDR_L => 36, OUT_PKT_DATA_H => 31, OUT_PKT_DATA_L => 0, OUT_PKT_BYTEEN_H => 35, OUT_PKT_BYTEEN_L => 32, OUT_PKT_BYTE_CNT_H => 69, OUT_PKT_BYTE_CNT_L => 67, OUT_PKT_TRANS_COMPRESSED_READ => 61, OUT_PKT_BURST_SIZE_H => 75, OUT_PKT_BURST_SIZE_L => 73, OUT_PKT_RESPONSE_STATUS_H => 99, OUT_PKT_RESPONSE_STATUS_L => 98, OUT_PKT_TRANS_EXCLUSIVE => 66, OUT_PKT_BURST_TYPE_H => 77, OUT_PKT_BURST_TYPE_L => 76, OUT_ST_DATA_W => 100, ST_CHANNEL_W => 13, OPTIMIZE_FOR_RSP => 1, RESPONSE_PATH => 1 ) port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset in_valid => id_router_003_src_valid, -- sink.valid in_channel => id_router_003_src_channel, -- .channel in_startofpacket => id_router_003_src_startofpacket, -- .startofpacket in_endofpacket => id_router_003_src_endofpacket, -- .endofpacket in_ready => id_router_003_src_ready, -- .ready in_data => id_router_003_src_data, -- .data out_endofpacket => width_adapter_003_src_endofpacket, -- src.endofpacket out_data => width_adapter_003_src_data, -- .data out_channel => width_adapter_003_src_channel, -- .channel out_valid => width_adapter_003_src_valid, -- .valid out_ready => width_adapter_003_src_ready, -- .ready out_startofpacket => width_adapter_003_src_startofpacket, -- .startofpacket in_command_size_data => "000" -- (terminated) ); width_adapter_004 : component niosii_system_width_adapter_004 generic map ( IN_PKT_ADDR_H => 60, IN_PKT_ADDR_L => 36, IN_PKT_DATA_H => 31, IN_PKT_DATA_L => 0, IN_PKT_BYTEEN_H => 35, IN_PKT_BYTEEN_L => 32, IN_PKT_BYTE_CNT_H => 69, IN_PKT_BYTE_CNT_L => 67, IN_PKT_TRANS_COMPRESSED_READ => 61, IN_PKT_BURSTWRAP_H => 72, IN_PKT_BURSTWRAP_L => 70, IN_PKT_BURST_SIZE_H => 75, IN_PKT_BURST_SIZE_L => 73, IN_PKT_RESPONSE_STATUS_H => 99, IN_PKT_RESPONSE_STATUS_L => 98, IN_PKT_TRANS_EXCLUSIVE => 66, IN_PKT_BURST_TYPE_H => 77, IN_PKT_BURST_TYPE_L => 76, IN_ST_DATA_W => 100, OUT_PKT_ADDR_H => 33, OUT_PKT_ADDR_L => 9, OUT_PKT_DATA_H => 7, OUT_PKT_DATA_L => 0, OUT_PKT_BYTEEN_H => 8, OUT_PKT_BYTEEN_L => 8, OUT_PKT_BYTE_CNT_H => 42, OUT_PKT_BYTE_CNT_L => 40, OUT_PKT_TRANS_COMPRESSED_READ => 34, OUT_PKT_BURST_SIZE_H => 48, OUT_PKT_BURST_SIZE_L => 46, OUT_PKT_RESPONSE_STATUS_H => 72, OUT_PKT_RESPONSE_STATUS_L => 71, OUT_PKT_TRANS_EXCLUSIVE => 39, OUT_PKT_BURST_TYPE_H => 50, OUT_PKT_BURST_TYPE_L => 49, OUT_ST_DATA_W => 73, ST_CHANNEL_W => 13, OPTIMIZE_FOR_RSP => 0, RESPONSE_PATH => 0 ) port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset in_valid => cmd_xbar_mux_004_src_valid, -- sink.valid in_channel => cmd_xbar_mux_004_src_channel, -- .channel in_startofpacket => cmd_xbar_mux_004_src_startofpacket, -- .startofpacket in_endofpacket => cmd_xbar_mux_004_src_endofpacket, -- .endofpacket in_ready => cmd_xbar_mux_004_src_ready, -- .ready in_data => cmd_xbar_mux_004_src_data, -- .data out_endofpacket => width_adapter_004_src_endofpacket, -- src.endofpacket out_data => width_adapter_004_src_data, -- .data out_channel => width_adapter_004_src_channel, -- .channel out_valid => width_adapter_004_src_valid, -- .valid out_ready => width_adapter_004_src_ready, -- .ready out_startofpacket => width_adapter_004_src_startofpacket, -- .startofpacket in_command_size_data => "000" -- (terminated) ); width_adapter_005 : component niosii_system_width_adapter_005 generic map ( IN_PKT_ADDR_H => 33, IN_PKT_ADDR_L => 9, IN_PKT_DATA_H => 7, IN_PKT_DATA_L => 0, IN_PKT_BYTEEN_H => 8, IN_PKT_BYTEEN_L => 8, IN_PKT_BYTE_CNT_H => 42, IN_PKT_BYTE_CNT_L => 40, IN_PKT_TRANS_COMPRESSED_READ => 34, IN_PKT_BURSTWRAP_H => 45, IN_PKT_BURSTWRAP_L => 43, IN_PKT_BURST_SIZE_H => 48, IN_PKT_BURST_SIZE_L => 46, IN_PKT_RESPONSE_STATUS_H => 72, IN_PKT_RESPONSE_STATUS_L => 71, IN_PKT_TRANS_EXCLUSIVE => 39, IN_PKT_BURST_TYPE_H => 50, IN_PKT_BURST_TYPE_L => 49, IN_ST_DATA_W => 73, OUT_PKT_ADDR_H => 60, OUT_PKT_ADDR_L => 36, OUT_PKT_DATA_H => 31, OUT_PKT_DATA_L => 0, OUT_PKT_BYTEEN_H => 35, OUT_PKT_BYTEEN_L => 32, OUT_PKT_BYTE_CNT_H => 69, OUT_PKT_BYTE_CNT_L => 67, OUT_PKT_TRANS_COMPRESSED_READ => 61, OUT_PKT_BURST_SIZE_H => 75, OUT_PKT_BURST_SIZE_L => 73, OUT_PKT_RESPONSE_STATUS_H => 99, OUT_PKT_RESPONSE_STATUS_L => 98, OUT_PKT_TRANS_EXCLUSIVE => 66, OUT_PKT_BURST_TYPE_H => 77, OUT_PKT_BURST_TYPE_L => 76, OUT_ST_DATA_W => 100, ST_CHANNEL_W => 13, OPTIMIZE_FOR_RSP => 1, RESPONSE_PATH => 1 ) port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset in_valid => id_router_004_src_valid, -- sink.valid in_channel => id_router_004_src_channel, -- .channel in_startofpacket => id_router_004_src_startofpacket, -- .startofpacket in_endofpacket => id_router_004_src_endofpacket, -- .endofpacket in_ready => id_router_004_src_ready, -- .ready in_data => id_router_004_src_data, -- .data out_endofpacket => width_adapter_005_src_endofpacket, -- src.endofpacket out_data => width_adapter_005_src_data, -- .data out_channel => width_adapter_005_src_channel, -- .channel out_valid => width_adapter_005_src_valid, -- .valid out_ready => width_adapter_005_src_ready, -- .ready out_startofpacket => width_adapter_005_src_startofpacket, -- .startofpacket in_command_size_data => "000" -- (terminated) ); crosser : component altera_avalon_st_handshake_clock_crosser generic map ( DATA_WIDTH => 100, BITS_PER_SYMBOL => 100, USE_PACKETS => 1, USE_CHANNEL => 1, CHANNEL_WIDTH => 13, USE_ERROR => 0, ERROR_WIDTH => 1, VALID_SYNC_DEPTH => 2, READY_SYNC_DEPTH => 2, USE_OUTPUT_PIPELINE => 0 ) port map ( in_clk => altpll_0_c1_clk, -- in_clk.clk in_reset => rst_controller_reset_out_reset, -- in_clk_reset.reset out_clk => clk_clk, -- out_clk.clk out_reset => rst_controller_001_reset_out_reset, -- out_clk_reset.reset in_ready => cmd_xbar_demux_001_src9_ready, -- in.ready in_valid => cmd_xbar_demux_001_src9_valid, -- .valid in_startofpacket => cmd_xbar_demux_001_src9_startofpacket, -- .startofpacket in_endofpacket => cmd_xbar_demux_001_src9_endofpacket, -- .endofpacket in_channel => cmd_xbar_demux_001_src9_channel, -- .channel in_data => cmd_xbar_demux_001_src9_data, -- .data out_ready => crosser_out_ready, -- out.ready out_valid => crosser_out_valid, -- .valid out_startofpacket => crosser_out_startofpacket, -- .startofpacket out_endofpacket => crosser_out_endofpacket, -- .endofpacket out_channel => crosser_out_channel, -- .channel out_data => crosser_out_data, -- .data in_empty => '0', -- (terminated) in_error => '0', -- (terminated) out_empty => open, -- (terminated) out_error => open -- (terminated) ); crosser_001 : component altera_avalon_st_handshake_clock_crosser generic map ( DATA_WIDTH => 100, BITS_PER_SYMBOL => 100, USE_PACKETS => 1, USE_CHANNEL => 1, CHANNEL_WIDTH => 13, USE_ERROR => 0, ERROR_WIDTH => 1, VALID_SYNC_DEPTH => 2, READY_SYNC_DEPTH => 2, USE_OUTPUT_PIPELINE => 0 ) port map ( in_clk => clk_clk, -- in_clk.clk in_reset => rst_controller_001_reset_out_reset, -- in_clk_reset.reset out_clk => altpll_0_c1_clk, -- out_clk.clk out_reset => rst_controller_reset_out_reset, -- out_clk_reset.reset in_ready => rsp_xbar_demux_009_src0_ready, -- in.ready in_valid => rsp_xbar_demux_009_src0_valid, -- .valid in_startofpacket => rsp_xbar_demux_009_src0_startofpacket, -- .startofpacket in_endofpacket => rsp_xbar_demux_009_src0_endofpacket, -- .endofpacket in_channel => rsp_xbar_demux_009_src0_channel, -- .channel in_data => rsp_xbar_demux_009_src0_data, -- .data out_ready => crosser_001_out_ready, -- out.ready out_valid => crosser_001_out_valid, -- .valid out_startofpacket => crosser_001_out_startofpacket, -- .startofpacket out_endofpacket => crosser_001_out_endofpacket, -- .endofpacket out_channel => crosser_001_out_channel, -- .channel out_data => crosser_001_out_data, -- .data in_empty => '0', -- (terminated) in_error => '0', -- (terminated) out_empty => open, -- (terminated) out_error => open -- (terminated) ); irq_mapper : component niosII_system_irq_mapper port map ( clk => altpll_0_c1_clk, -- clk.clk reset => rst_controller_reset_out_reset, -- clk_reset.reset receiver0_irq => irq_mapper_receiver0_irq, -- receiver0.irq receiver1_irq => irq_mapper_receiver1_irq, -- receiver1.irq receiver2_irq => irq_mapper_receiver2_irq, -- receiver2.irq receiver3_irq => irq_mapper_receiver3_irq, -- receiver3.irq sender_irq => nios2_qsys_0_d_irq_irq -- sender.irq ); reset_reset_n_ports_inv <= not reset_reset_n; sdram_0_s1_translator_avalon_anti_slave_0_write_ports_inv <= not sdram_0_s1_translator_avalon_anti_slave_0_write; sdram_0_s1_translator_avalon_anti_slave_0_read_ports_inv <= not sdram_0_s1_translator_avalon_anti_slave_0_read; sdram_0_s1_translator_avalon_anti_slave_0_byteenable_ports_inv <= not sdram_0_s1_translator_avalon_anti_slave_0_byteenable; jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write_ports_inv <= not jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_write; jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read_ports_inv <= not jtag_uart_0_avalon_jtag_slave_translator_avalon_anti_slave_0_read; green_leds_s1_translator_avalon_anti_slave_0_write_ports_inv <= not green_leds_s1_translator_avalon_anti_slave_0_write; timer_0_s1_translator_avalon_anti_slave_0_write_ports_inv <= not timer_0_s1_translator_avalon_anti_slave_0_write; rst_controller_reset_out_reset_ports_inv <= not rst_controller_reset_out_reset; end architecture rtl; -- of niosII_system
------------------------------------------------------------------------------- -- axi_sg_updt_noqueue ------------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_sg_updt_noqueue.vhd -- Description: This entity provides the descriptor update for the No Queue mode -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- axi_sg.vhd -- axi_sg_pkg.vhd -- |- axi_sg_ftch_mngr.vhd -- | |- axi_sg_ftch_sm.vhd -- | |- axi_sg_ftch_pntr.vhd -- | |- axi_sg_ftch_cmdsts_if.vhd -- |- axi_sg_updt_mngr.vhd -- | |- axi_sg_updt_sm.vhd -- | |- axi_sg_updt_cmdsts_if.vhd -- |- axi_sg_ftch_q_mngr.vhd -- | |- axi_sg_ftch_queue.vhd -- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd -- | | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd -- | |- axi_sg_ftch_noqueue.vhd -- |- axi_sg_updt_q_mngr.vhd -- | |- axi_sg_updt_queue.vhd -- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd -- | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd -- | |- axi_sg_updt_noqueue.vhd -- |- axi_sg_intrpt.vhd -- |- axi_datamover_v5_0.axi_datamover.vhd -- ------------------------------------------------------------------------------- -- Author: Gary Burch -- History: -- GAB 3/19/10 v1_00_a -- ^^^^^^ -- - Initial Release -- ~~~~~~ -- GAB 8/26/10 v2_00_a -- ^^^^^^ -- Seperated update queues into two seperate files, no queue and queue to -- simplify maintainance. -- ~~~~~~ -- GAB 10/21/10 v4_03 -- ^^^^^^ -- Rolled version to v4_03 -- ~~~~~~ -- GAB 11/15/10 v2_01_a -- ^^^^^^ -- CR582800 -- Converted all stream paraters ***_DATA_WIDTH to ***_TDATA_WIDTH -- ~~~~~~ -- GAB 6/13/11 v4_03 -- ^^^^^^ -- Update to AXI Datamover v4_03 -- Added aynchronous operation -- ~~~~~~ ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library axi_vdma_v6_2_8; use axi_vdma_v6_2_8.axi_sg_pkg.all; library lib_pkg_v1_0_2; library lib_fifo_v1_0_5; use lib_fifo_v1_0_5.sync_fifo_fg; use lib_pkg_v1_0_2.lib_pkg.all; ------------------------------------------------------------------------------- entity axi_sg_updt_noqueue is generic ( C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32; -- Master AXI Memory Map Address Width for Scatter Gather R/W Port C_M_AXIS_UPDT_DATA_WIDTH : integer range 32 to 32 := 32; -- Master AXI Memory Map Data Width for Scatter Gather R/W Port C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32; -- 32 Update Status Bits C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33 -- 1 IOC bit + 32 Update Status Bits ); port ( ----------------------------------------------------------------------- -- AXI Scatter Gather Interface ----------------------------------------------------------------------- m_axi_sg_aclk : in std_logic ; -- m_axi_sg_aresetn : in std_logic ; -- -- -- Channel 1 Control -- updt_curdesc_wren : out std_logic ; -- updt_curdesc : out std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- updt_active : in std_logic ; -- updt_queue_empty : out std_logic ; -- updt_ioc : out std_logic ; -- updt_ioc_irq_set : in std_logic ; -- -- dma_interr : out std_logic ; -- dma_slverr : out std_logic ; -- dma_decerr : out std_logic ; -- dma_interr_set : in std_logic ; -- dma_slverr_set : in std_logic ; -- dma_decerr_set : in std_logic ; -- -- --*********************************-- -- --** Channel Update Interface In **-- -- --*********************************-- -- -- Update Pointer Stream -- s_axis_updtptr_tdata : in std_logic_vector -- (C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) ; -- s_axis_updtptr_tvalid : in std_logic ; -- s_axis_updtptr_tready : out std_logic ; -- s_axis_updtptr_tlast : in std_logic ; -- -- -- Update Status Stream -- s_axis_updtsts_tdata : in std_logic_vector -- (C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); -- s_axis_updtsts_tvalid : in std_logic ; -- s_axis_updtsts_tready : out std_logic ; -- s_axis_updtsts_tlast : in std_logic ; -- -- --*********************************-- -- --** Channel Update Interface Out**-- -- --*********************************-- -- -- S2MM Stream Out To DataMover -- m_axis_updt_tdata : out std_logic_vector -- (C_M_AXIS_UPDT_DATA_WIDTH-1 downto 0); -- m_axis_updt_tlast : out std_logic ; -- m_axis_updt_tvalid : out std_logic ; -- m_axis_updt_tready : in std_logic -- ); end axi_sg_updt_noqueue; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_sg_updt_noqueue is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- No Contstants Declared ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- -- Channel signals signal writing_curdesc : std_logic := '0'; signal write_curdesc_lsb : std_logic := '0'; signal write_curdesc_msb : std_logic := '0'; signal updt_active_d1 : std_logic := '0'; signal updt_active_re : std_logic := '0'; type PNTR_STATE_TYPE is (IDLE, READ_CURDESC_LSB, READ_CURDESC_MSB, WRITE_STATUS ); signal pntr_cs : PNTR_STATE_TYPE; signal pntr_ns : PNTR_STATE_TYPE; signal writing_status : std_logic := '0'; signal curdesc_tready : std_logic := '0'; signal writing_status_d1 : std_logic := '0'; signal writing_status_re : std_logic := '0'; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin -- Asset active strobe on rising edge of update active -- asertion. This kicks off the update process for -- the channel REG_ACTIVE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then updt_active_d1 <= '0'; else updt_active_d1 <= updt_active; end if; end if; end process REG_ACTIVE; updt_active_re <= updt_active and not updt_active_d1; -- Current Descriptor Pointer Fetch. This state machine controls -- reading out the current pointer from the Queue or channel port -- and writing it to the update manager for use in command -- generation to the DataMover for Descriptor update. CURDESC_PNTR_STATE : process(pntr_cs, updt_active, s_axis_updtptr_tvalid, s_axis_updtsts_tvalid, s_axis_updtsts_tlast, m_axis_updt_tready) begin write_curdesc_lsb <= '0'; write_curdesc_msb <= '0'; writing_status <= '0'; writing_curdesc <= '0'; curdesc_tready <= '0'; pntr_ns <= pntr_cs; case pntr_cs is when IDLE => if(s_axis_updtptr_tvalid = '1' and updt_active = '1')then writing_curdesc <= '1'; pntr_ns <= READ_CURDESC_LSB; else pntr_ns <= IDLE; end if; --------------------------------------------------------------- -- Get lower current descriptor when READ_CURDESC_LSB => curdesc_tready <= '1'; writing_curdesc <= '1'; -- on tvalid from Queue or channel port then register -- lsb curdesc and setup to register msb curdesc if(s_axis_updtptr_tvalid = '1' and updt_active = '1')then write_curdesc_lsb <= '1'; pntr_ns <= READ_CURDESC_MSB; else pntr_ns <= READ_CURDESC_LSB; end if; --------------------------------------------------------------- -- Get upper current descriptor when READ_CURDESC_MSB => curdesc_tready <= '1'; writing_curdesc <= '1'; -- On tvalid from Queue or channel port then register -- msb. This will also write curdesc out to update -- manager. if(s_axis_updtptr_tvalid = '1')then write_curdesc_msb <= '1'; pntr_ns <= WRITE_STATUS; else pntr_ns <= READ_CURDESC_MSB; end if; --------------------------------------------------------------- -- Hold in this state until remainder of descriptor is -- written out. when WRITE_STATUS => writing_status <= s_axis_updtsts_tvalid; if(s_axis_updtsts_tvalid = '1' and m_axis_updt_tready = '1' and s_axis_updtsts_tlast = '1')then pntr_ns <= IDLE; else pntr_ns <= WRITE_STATUS; end if; when others => pntr_ns <= IDLE; end case; end process CURDESC_PNTR_STATE; --------------------------------------------------------------------------- -- Register for CURDESC Pointer state machine --------------------------------------------------------------------------- REG_PNTR_STATES : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then pntr_cs <= IDLE; else pntr_cs <= pntr_ns; end if; end if; end process REG_PNTR_STATES; -- Status stream signals m_axis_updt_tdata <= s_axis_updtsts_tdata(C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0); m_axis_updt_tvalid <= s_axis_updtsts_tvalid and writing_status; m_axis_updt_tlast <= s_axis_updtsts_tlast and writing_status; s_axis_updtsts_tready <= m_axis_updt_tready and writing_status; -- Pointer stream signals s_axis_updtptr_tready <= curdesc_tready; -- Indicate need for channel service for update state machine updt_queue_empty <= not s_axis_updtsts_tvalid; --********************************************************************* --** POINTER CAPTURE LOGIC --********************************************************************* --------------------------------------------------------------------------- -- Write lower order Next Descriptor Pointer out to pntr_mngr --------------------------------------------------------------------------- REG_LSB_CURPNTR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then updt_curdesc(31 downto 0) <= (others => '0'); -- Capture lower pointer from FIFO or channel port elsif(write_curdesc_lsb = '1')then updt_curdesc(31 downto 0) <= s_axis_updtptr_tdata(C_S_AXIS_UPDPTR_TDATA_WIDTH - 1 downto 0); end if; end if; end process REG_LSB_CURPNTR; --------------------------------------------------------------------------- -- 64 Bit Scatter Gather addresses enabled --------------------------------------------------------------------------- GEN_UPPER_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate begin --------------------------------------------------------------------------- -- Write upper order Next Descriptor Pointer out to pntr_mngr --------------------------------------------------------------------------- REG_MSB_CURPNTR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then updt_curdesc(63 downto 32) <= (others => '0'); updt_curdesc_wren <= '0'; -- Capture upper pointer from FIFO or channel port -- and also write curdesc out elsif(write_curdesc_msb = '1')then updt_curdesc(63 downto 32) <= s_axis_updtptr_tdata(C_S_AXIS_UPDPTR_TDATA_WIDTH - 1 downto 0); updt_curdesc_wren <= '1'; -- Assert tready/wren for only 1 clock else updt_curdesc_wren <= '0'; end if; end if; end process REG_MSB_CURPNTR; end generate GEN_UPPER_MSB_CURDESC; --------------------------------------------------------------------------- -- 32 Bit Scatter Gather addresses enabled --------------------------------------------------------------------------- GEN_NO_UPR_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate begin ----------------------------------------------------------------------- -- No upper order therefore dump fetched word and write pntr lower next -- pointer to pntr mngr ----------------------------------------------------------------------- REG_MSB_CURPNTR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then updt_curdesc_wren <= '0'; -- Throw away second word, only write curdesc out with msb -- set to zero elsif(write_curdesc_msb = '1')then updt_curdesc_wren <= '1'; -- Assert for only 1 clock else updt_curdesc_wren <= '0'; end if; end if; end process REG_MSB_CURPNTR; end generate GEN_NO_UPR_MSB_CURDESC; --********************************************************************* --** ERROR CAPTURE LOGIC --********************************************************************* ----------------------------------------------------------------------- -- Generate rising edge pulse on writing status signal. This will -- assert at the beginning of the status write. Coupled with status -- fifo set to first word fall through status will be on dout -- regardless of target ready. ----------------------------------------------------------------------- REG_WRITE_STATUS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then writing_status_d1 <= '0'; else writing_status_d1 <= writing_status; end if; end if; end process REG_WRITE_STATUS; writing_status_re <= writing_status and not writing_status_d1; --------------------------------------------------------------------------- -- Caputure IOC begin set --------------------------------------------------------------------------- REG_IOC_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or updt_ioc_irq_set = '1')then updt_ioc <= '0'; elsif(writing_status_re = '1')then updt_ioc <= s_axis_updtsts_tdata(DESC_IOC_TAG_BIT); end if; end if; end process REG_IOC_PROCESS; ----------------------------------------------------------------------- -- Capture DMA Internal Errors ----------------------------------------------------------------------- CAPTURE_DMAINT_ERROR: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dma_interr_set = '1')then dma_interr <= '0'; elsif(writing_status_re = '1')then dma_interr <= s_axis_updtsts_tdata(DESC_STS_INTERR_BIT); end if; end if; end process CAPTURE_DMAINT_ERROR; ----------------------------------------------------------------------- -- Capture DMA Slave Errors ----------------------------------------------------------------------- CAPTURE_DMASLV_ERROR: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dma_slverr_set = '1')then dma_slverr <= '0'; elsif(writing_status_re = '1')then dma_slverr <= s_axis_updtsts_tdata(DESC_STS_SLVERR_BIT); end if; end if; end process CAPTURE_DMASLV_ERROR; ----------------------------------------------------------------------- -- Capture DMA Decode Errors ----------------------------------------------------------------------- CAPTURE_DMADEC_ERROR: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dma_decerr_set = '1')then dma_decerr <= '0'; elsif(writing_status_re = '1')then dma_decerr <= s_axis_updtsts_tdata(DESC_STS_DECERR_BIT); end if; end if; end process CAPTURE_DMADEC_ERROR; end implementation;
------------------------------------------------------------------------------- -- axi_sg_updt_noqueue ------------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_sg_updt_noqueue.vhd -- Description: This entity provides the descriptor update for the No Queue mode -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- axi_sg.vhd -- axi_sg_pkg.vhd -- |- axi_sg_ftch_mngr.vhd -- | |- axi_sg_ftch_sm.vhd -- | |- axi_sg_ftch_pntr.vhd -- | |- axi_sg_ftch_cmdsts_if.vhd -- |- axi_sg_updt_mngr.vhd -- | |- axi_sg_updt_sm.vhd -- | |- axi_sg_updt_cmdsts_if.vhd -- |- axi_sg_ftch_q_mngr.vhd -- | |- axi_sg_ftch_queue.vhd -- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd -- | | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd -- | |- axi_sg_ftch_noqueue.vhd -- |- axi_sg_updt_q_mngr.vhd -- | |- axi_sg_updt_queue.vhd -- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd -- | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd -- | |- axi_sg_updt_noqueue.vhd -- |- axi_sg_intrpt.vhd -- |- axi_datamover_v5_0.axi_datamover.vhd -- ------------------------------------------------------------------------------- -- Author: Gary Burch -- History: -- GAB 3/19/10 v1_00_a -- ^^^^^^ -- - Initial Release -- ~~~~~~ -- GAB 8/26/10 v2_00_a -- ^^^^^^ -- Seperated update queues into two seperate files, no queue and queue to -- simplify maintainance. -- ~~~~~~ -- GAB 10/21/10 v4_03 -- ^^^^^^ -- Rolled version to v4_03 -- ~~~~~~ -- GAB 11/15/10 v2_01_a -- ^^^^^^ -- CR582800 -- Converted all stream paraters ***_DATA_WIDTH to ***_TDATA_WIDTH -- ~~~~~~ -- GAB 6/13/11 v4_03 -- ^^^^^^ -- Update to AXI Datamover v4_03 -- Added aynchronous operation -- ~~~~~~ ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library axi_vdma_v6_2_8; use axi_vdma_v6_2_8.axi_sg_pkg.all; library lib_pkg_v1_0_2; library lib_fifo_v1_0_5; use lib_fifo_v1_0_5.sync_fifo_fg; use lib_pkg_v1_0_2.lib_pkg.all; ------------------------------------------------------------------------------- entity axi_sg_updt_noqueue is generic ( C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32; -- Master AXI Memory Map Address Width for Scatter Gather R/W Port C_M_AXIS_UPDT_DATA_WIDTH : integer range 32 to 32 := 32; -- Master AXI Memory Map Data Width for Scatter Gather R/W Port C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32; -- 32 Update Status Bits C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33 -- 1 IOC bit + 32 Update Status Bits ); port ( ----------------------------------------------------------------------- -- AXI Scatter Gather Interface ----------------------------------------------------------------------- m_axi_sg_aclk : in std_logic ; -- m_axi_sg_aresetn : in std_logic ; -- -- -- Channel 1 Control -- updt_curdesc_wren : out std_logic ; -- updt_curdesc : out std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- updt_active : in std_logic ; -- updt_queue_empty : out std_logic ; -- updt_ioc : out std_logic ; -- updt_ioc_irq_set : in std_logic ; -- -- dma_interr : out std_logic ; -- dma_slverr : out std_logic ; -- dma_decerr : out std_logic ; -- dma_interr_set : in std_logic ; -- dma_slverr_set : in std_logic ; -- dma_decerr_set : in std_logic ; -- -- --*********************************-- -- --** Channel Update Interface In **-- -- --*********************************-- -- -- Update Pointer Stream -- s_axis_updtptr_tdata : in std_logic_vector -- (C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) ; -- s_axis_updtptr_tvalid : in std_logic ; -- s_axis_updtptr_tready : out std_logic ; -- s_axis_updtptr_tlast : in std_logic ; -- -- -- Update Status Stream -- s_axis_updtsts_tdata : in std_logic_vector -- (C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); -- s_axis_updtsts_tvalid : in std_logic ; -- s_axis_updtsts_tready : out std_logic ; -- s_axis_updtsts_tlast : in std_logic ; -- -- --*********************************-- -- --** Channel Update Interface Out**-- -- --*********************************-- -- -- S2MM Stream Out To DataMover -- m_axis_updt_tdata : out std_logic_vector -- (C_M_AXIS_UPDT_DATA_WIDTH-1 downto 0); -- m_axis_updt_tlast : out std_logic ; -- m_axis_updt_tvalid : out std_logic ; -- m_axis_updt_tready : in std_logic -- ); end axi_sg_updt_noqueue; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_sg_updt_noqueue is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- No Contstants Declared ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- -- Channel signals signal writing_curdesc : std_logic := '0'; signal write_curdesc_lsb : std_logic := '0'; signal write_curdesc_msb : std_logic := '0'; signal updt_active_d1 : std_logic := '0'; signal updt_active_re : std_logic := '0'; type PNTR_STATE_TYPE is (IDLE, READ_CURDESC_LSB, READ_CURDESC_MSB, WRITE_STATUS ); signal pntr_cs : PNTR_STATE_TYPE; signal pntr_ns : PNTR_STATE_TYPE; signal writing_status : std_logic := '0'; signal curdesc_tready : std_logic := '0'; signal writing_status_d1 : std_logic := '0'; signal writing_status_re : std_logic := '0'; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin -- Asset active strobe on rising edge of update active -- asertion. This kicks off the update process for -- the channel REG_ACTIVE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then updt_active_d1 <= '0'; else updt_active_d1 <= updt_active; end if; end if; end process REG_ACTIVE; updt_active_re <= updt_active and not updt_active_d1; -- Current Descriptor Pointer Fetch. This state machine controls -- reading out the current pointer from the Queue or channel port -- and writing it to the update manager for use in command -- generation to the DataMover for Descriptor update. CURDESC_PNTR_STATE : process(pntr_cs, updt_active, s_axis_updtptr_tvalid, s_axis_updtsts_tvalid, s_axis_updtsts_tlast, m_axis_updt_tready) begin write_curdesc_lsb <= '0'; write_curdesc_msb <= '0'; writing_status <= '0'; writing_curdesc <= '0'; curdesc_tready <= '0'; pntr_ns <= pntr_cs; case pntr_cs is when IDLE => if(s_axis_updtptr_tvalid = '1' and updt_active = '1')then writing_curdesc <= '1'; pntr_ns <= READ_CURDESC_LSB; else pntr_ns <= IDLE; end if; --------------------------------------------------------------- -- Get lower current descriptor when READ_CURDESC_LSB => curdesc_tready <= '1'; writing_curdesc <= '1'; -- on tvalid from Queue or channel port then register -- lsb curdesc and setup to register msb curdesc if(s_axis_updtptr_tvalid = '1' and updt_active = '1')then write_curdesc_lsb <= '1'; pntr_ns <= READ_CURDESC_MSB; else pntr_ns <= READ_CURDESC_LSB; end if; --------------------------------------------------------------- -- Get upper current descriptor when READ_CURDESC_MSB => curdesc_tready <= '1'; writing_curdesc <= '1'; -- On tvalid from Queue or channel port then register -- msb. This will also write curdesc out to update -- manager. if(s_axis_updtptr_tvalid = '1')then write_curdesc_msb <= '1'; pntr_ns <= WRITE_STATUS; else pntr_ns <= READ_CURDESC_MSB; end if; --------------------------------------------------------------- -- Hold in this state until remainder of descriptor is -- written out. when WRITE_STATUS => writing_status <= s_axis_updtsts_tvalid; if(s_axis_updtsts_tvalid = '1' and m_axis_updt_tready = '1' and s_axis_updtsts_tlast = '1')then pntr_ns <= IDLE; else pntr_ns <= WRITE_STATUS; end if; when others => pntr_ns <= IDLE; end case; end process CURDESC_PNTR_STATE; --------------------------------------------------------------------------- -- Register for CURDESC Pointer state machine --------------------------------------------------------------------------- REG_PNTR_STATES : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then pntr_cs <= IDLE; else pntr_cs <= pntr_ns; end if; end if; end process REG_PNTR_STATES; -- Status stream signals m_axis_updt_tdata <= s_axis_updtsts_tdata(C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0); m_axis_updt_tvalid <= s_axis_updtsts_tvalid and writing_status; m_axis_updt_tlast <= s_axis_updtsts_tlast and writing_status; s_axis_updtsts_tready <= m_axis_updt_tready and writing_status; -- Pointer stream signals s_axis_updtptr_tready <= curdesc_tready; -- Indicate need for channel service for update state machine updt_queue_empty <= not s_axis_updtsts_tvalid; --********************************************************************* --** POINTER CAPTURE LOGIC --********************************************************************* --------------------------------------------------------------------------- -- Write lower order Next Descriptor Pointer out to pntr_mngr --------------------------------------------------------------------------- REG_LSB_CURPNTR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then updt_curdesc(31 downto 0) <= (others => '0'); -- Capture lower pointer from FIFO or channel port elsif(write_curdesc_lsb = '1')then updt_curdesc(31 downto 0) <= s_axis_updtptr_tdata(C_S_AXIS_UPDPTR_TDATA_WIDTH - 1 downto 0); end if; end if; end process REG_LSB_CURPNTR; --------------------------------------------------------------------------- -- 64 Bit Scatter Gather addresses enabled --------------------------------------------------------------------------- GEN_UPPER_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate begin --------------------------------------------------------------------------- -- Write upper order Next Descriptor Pointer out to pntr_mngr --------------------------------------------------------------------------- REG_MSB_CURPNTR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then updt_curdesc(63 downto 32) <= (others => '0'); updt_curdesc_wren <= '0'; -- Capture upper pointer from FIFO or channel port -- and also write curdesc out elsif(write_curdesc_msb = '1')then updt_curdesc(63 downto 32) <= s_axis_updtptr_tdata(C_S_AXIS_UPDPTR_TDATA_WIDTH - 1 downto 0); updt_curdesc_wren <= '1'; -- Assert tready/wren for only 1 clock else updt_curdesc_wren <= '0'; end if; end if; end process REG_MSB_CURPNTR; end generate GEN_UPPER_MSB_CURDESC; --------------------------------------------------------------------------- -- 32 Bit Scatter Gather addresses enabled --------------------------------------------------------------------------- GEN_NO_UPR_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate begin ----------------------------------------------------------------------- -- No upper order therefore dump fetched word and write pntr lower next -- pointer to pntr mngr ----------------------------------------------------------------------- REG_MSB_CURPNTR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then updt_curdesc_wren <= '0'; -- Throw away second word, only write curdesc out with msb -- set to zero elsif(write_curdesc_msb = '1')then updt_curdesc_wren <= '1'; -- Assert for only 1 clock else updt_curdesc_wren <= '0'; end if; end if; end process REG_MSB_CURPNTR; end generate GEN_NO_UPR_MSB_CURDESC; --********************************************************************* --** ERROR CAPTURE LOGIC --********************************************************************* ----------------------------------------------------------------------- -- Generate rising edge pulse on writing status signal. This will -- assert at the beginning of the status write. Coupled with status -- fifo set to first word fall through status will be on dout -- regardless of target ready. ----------------------------------------------------------------------- REG_WRITE_STATUS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then writing_status_d1 <= '0'; else writing_status_d1 <= writing_status; end if; end if; end process REG_WRITE_STATUS; writing_status_re <= writing_status and not writing_status_d1; --------------------------------------------------------------------------- -- Caputure IOC begin set --------------------------------------------------------------------------- REG_IOC_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or updt_ioc_irq_set = '1')then updt_ioc <= '0'; elsif(writing_status_re = '1')then updt_ioc <= s_axis_updtsts_tdata(DESC_IOC_TAG_BIT); end if; end if; end process REG_IOC_PROCESS; ----------------------------------------------------------------------- -- Capture DMA Internal Errors ----------------------------------------------------------------------- CAPTURE_DMAINT_ERROR: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dma_interr_set = '1')then dma_interr <= '0'; elsif(writing_status_re = '1')then dma_interr <= s_axis_updtsts_tdata(DESC_STS_INTERR_BIT); end if; end if; end process CAPTURE_DMAINT_ERROR; ----------------------------------------------------------------------- -- Capture DMA Slave Errors ----------------------------------------------------------------------- CAPTURE_DMASLV_ERROR: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dma_slverr_set = '1')then dma_slverr <= '0'; elsif(writing_status_re = '1')then dma_slverr <= s_axis_updtsts_tdata(DESC_STS_SLVERR_BIT); end if; end if; end process CAPTURE_DMASLV_ERROR; ----------------------------------------------------------------------- -- Capture DMA Decode Errors ----------------------------------------------------------------------- CAPTURE_DMADEC_ERROR: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dma_decerr_set = '1')then dma_decerr <= '0'; elsif(writing_status_re = '1')then dma_decerr <= s_axis_updtsts_tdata(DESC_STS_DECERR_BIT); end if; end if; end process CAPTURE_DMADEC_ERROR; end implementation;
------------------------------------------------------------------------------- -- axi_sg_updt_noqueue ------------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_sg_updt_noqueue.vhd -- Description: This entity provides the descriptor update for the No Queue mode -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- axi_sg.vhd -- axi_sg_pkg.vhd -- |- axi_sg_ftch_mngr.vhd -- | |- axi_sg_ftch_sm.vhd -- | |- axi_sg_ftch_pntr.vhd -- | |- axi_sg_ftch_cmdsts_if.vhd -- |- axi_sg_updt_mngr.vhd -- | |- axi_sg_updt_sm.vhd -- | |- axi_sg_updt_cmdsts_if.vhd -- |- axi_sg_ftch_q_mngr.vhd -- | |- axi_sg_ftch_queue.vhd -- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd -- | | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd -- | |- axi_sg_ftch_noqueue.vhd -- |- axi_sg_updt_q_mngr.vhd -- | |- axi_sg_updt_queue.vhd -- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd -- | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd -- | |- axi_sg_updt_noqueue.vhd -- |- axi_sg_intrpt.vhd -- |- axi_datamover_v5_0.axi_datamover.vhd -- ------------------------------------------------------------------------------- -- Author: Gary Burch -- History: -- GAB 3/19/10 v1_00_a -- ^^^^^^ -- - Initial Release -- ~~~~~~ -- GAB 8/26/10 v2_00_a -- ^^^^^^ -- Seperated update queues into two seperate files, no queue and queue to -- simplify maintainance. -- ~~~~~~ -- GAB 10/21/10 v4_03 -- ^^^^^^ -- Rolled version to v4_03 -- ~~~~~~ -- GAB 11/15/10 v2_01_a -- ^^^^^^ -- CR582800 -- Converted all stream paraters ***_DATA_WIDTH to ***_TDATA_WIDTH -- ~~~~~~ -- GAB 6/13/11 v4_03 -- ^^^^^^ -- Update to AXI Datamover v4_03 -- Added aynchronous operation -- ~~~~~~ ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library axi_vdma_v6_2_8; use axi_vdma_v6_2_8.axi_sg_pkg.all; library lib_pkg_v1_0_2; library lib_fifo_v1_0_5; use lib_fifo_v1_0_5.sync_fifo_fg; use lib_pkg_v1_0_2.lib_pkg.all; ------------------------------------------------------------------------------- entity axi_sg_updt_noqueue is generic ( C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32; -- Master AXI Memory Map Address Width for Scatter Gather R/W Port C_M_AXIS_UPDT_DATA_WIDTH : integer range 32 to 32 := 32; -- Master AXI Memory Map Data Width for Scatter Gather R/W Port C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32; -- 32 Update Status Bits C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33 -- 1 IOC bit + 32 Update Status Bits ); port ( ----------------------------------------------------------------------- -- AXI Scatter Gather Interface ----------------------------------------------------------------------- m_axi_sg_aclk : in std_logic ; -- m_axi_sg_aresetn : in std_logic ; -- -- -- Channel 1 Control -- updt_curdesc_wren : out std_logic ; -- updt_curdesc : out std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- updt_active : in std_logic ; -- updt_queue_empty : out std_logic ; -- updt_ioc : out std_logic ; -- updt_ioc_irq_set : in std_logic ; -- -- dma_interr : out std_logic ; -- dma_slverr : out std_logic ; -- dma_decerr : out std_logic ; -- dma_interr_set : in std_logic ; -- dma_slverr_set : in std_logic ; -- dma_decerr_set : in std_logic ; -- -- --*********************************-- -- --** Channel Update Interface In **-- -- --*********************************-- -- -- Update Pointer Stream -- s_axis_updtptr_tdata : in std_logic_vector -- (C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) ; -- s_axis_updtptr_tvalid : in std_logic ; -- s_axis_updtptr_tready : out std_logic ; -- s_axis_updtptr_tlast : in std_logic ; -- -- -- Update Status Stream -- s_axis_updtsts_tdata : in std_logic_vector -- (C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); -- s_axis_updtsts_tvalid : in std_logic ; -- s_axis_updtsts_tready : out std_logic ; -- s_axis_updtsts_tlast : in std_logic ; -- -- --*********************************-- -- --** Channel Update Interface Out**-- -- --*********************************-- -- -- S2MM Stream Out To DataMover -- m_axis_updt_tdata : out std_logic_vector -- (C_M_AXIS_UPDT_DATA_WIDTH-1 downto 0); -- m_axis_updt_tlast : out std_logic ; -- m_axis_updt_tvalid : out std_logic ; -- m_axis_updt_tready : in std_logic -- ); end axi_sg_updt_noqueue; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_sg_updt_noqueue is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- No Contstants Declared ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- -- Channel signals signal writing_curdesc : std_logic := '0'; signal write_curdesc_lsb : std_logic := '0'; signal write_curdesc_msb : std_logic := '0'; signal updt_active_d1 : std_logic := '0'; signal updt_active_re : std_logic := '0'; type PNTR_STATE_TYPE is (IDLE, READ_CURDESC_LSB, READ_CURDESC_MSB, WRITE_STATUS ); signal pntr_cs : PNTR_STATE_TYPE; signal pntr_ns : PNTR_STATE_TYPE; signal writing_status : std_logic := '0'; signal curdesc_tready : std_logic := '0'; signal writing_status_d1 : std_logic := '0'; signal writing_status_re : std_logic := '0'; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin -- Asset active strobe on rising edge of update active -- asertion. This kicks off the update process for -- the channel REG_ACTIVE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then updt_active_d1 <= '0'; else updt_active_d1 <= updt_active; end if; end if; end process REG_ACTIVE; updt_active_re <= updt_active and not updt_active_d1; -- Current Descriptor Pointer Fetch. This state machine controls -- reading out the current pointer from the Queue or channel port -- and writing it to the update manager for use in command -- generation to the DataMover for Descriptor update. CURDESC_PNTR_STATE : process(pntr_cs, updt_active, s_axis_updtptr_tvalid, s_axis_updtsts_tvalid, s_axis_updtsts_tlast, m_axis_updt_tready) begin write_curdesc_lsb <= '0'; write_curdesc_msb <= '0'; writing_status <= '0'; writing_curdesc <= '0'; curdesc_tready <= '0'; pntr_ns <= pntr_cs; case pntr_cs is when IDLE => if(s_axis_updtptr_tvalid = '1' and updt_active = '1')then writing_curdesc <= '1'; pntr_ns <= READ_CURDESC_LSB; else pntr_ns <= IDLE; end if; --------------------------------------------------------------- -- Get lower current descriptor when READ_CURDESC_LSB => curdesc_tready <= '1'; writing_curdesc <= '1'; -- on tvalid from Queue or channel port then register -- lsb curdesc and setup to register msb curdesc if(s_axis_updtptr_tvalid = '1' and updt_active = '1')then write_curdesc_lsb <= '1'; pntr_ns <= READ_CURDESC_MSB; else pntr_ns <= READ_CURDESC_LSB; end if; --------------------------------------------------------------- -- Get upper current descriptor when READ_CURDESC_MSB => curdesc_tready <= '1'; writing_curdesc <= '1'; -- On tvalid from Queue or channel port then register -- msb. This will also write curdesc out to update -- manager. if(s_axis_updtptr_tvalid = '1')then write_curdesc_msb <= '1'; pntr_ns <= WRITE_STATUS; else pntr_ns <= READ_CURDESC_MSB; end if; --------------------------------------------------------------- -- Hold in this state until remainder of descriptor is -- written out. when WRITE_STATUS => writing_status <= s_axis_updtsts_tvalid; if(s_axis_updtsts_tvalid = '1' and m_axis_updt_tready = '1' and s_axis_updtsts_tlast = '1')then pntr_ns <= IDLE; else pntr_ns <= WRITE_STATUS; end if; when others => pntr_ns <= IDLE; end case; end process CURDESC_PNTR_STATE; --------------------------------------------------------------------------- -- Register for CURDESC Pointer state machine --------------------------------------------------------------------------- REG_PNTR_STATES : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then pntr_cs <= IDLE; else pntr_cs <= pntr_ns; end if; end if; end process REG_PNTR_STATES; -- Status stream signals m_axis_updt_tdata <= s_axis_updtsts_tdata(C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0); m_axis_updt_tvalid <= s_axis_updtsts_tvalid and writing_status; m_axis_updt_tlast <= s_axis_updtsts_tlast and writing_status; s_axis_updtsts_tready <= m_axis_updt_tready and writing_status; -- Pointer stream signals s_axis_updtptr_tready <= curdesc_tready; -- Indicate need for channel service for update state machine updt_queue_empty <= not s_axis_updtsts_tvalid; --********************************************************************* --** POINTER CAPTURE LOGIC --********************************************************************* --------------------------------------------------------------------------- -- Write lower order Next Descriptor Pointer out to pntr_mngr --------------------------------------------------------------------------- REG_LSB_CURPNTR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then updt_curdesc(31 downto 0) <= (others => '0'); -- Capture lower pointer from FIFO or channel port elsif(write_curdesc_lsb = '1')then updt_curdesc(31 downto 0) <= s_axis_updtptr_tdata(C_S_AXIS_UPDPTR_TDATA_WIDTH - 1 downto 0); end if; end if; end process REG_LSB_CURPNTR; --------------------------------------------------------------------------- -- 64 Bit Scatter Gather addresses enabled --------------------------------------------------------------------------- GEN_UPPER_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate begin --------------------------------------------------------------------------- -- Write upper order Next Descriptor Pointer out to pntr_mngr --------------------------------------------------------------------------- REG_MSB_CURPNTR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then updt_curdesc(63 downto 32) <= (others => '0'); updt_curdesc_wren <= '0'; -- Capture upper pointer from FIFO or channel port -- and also write curdesc out elsif(write_curdesc_msb = '1')then updt_curdesc(63 downto 32) <= s_axis_updtptr_tdata(C_S_AXIS_UPDPTR_TDATA_WIDTH - 1 downto 0); updt_curdesc_wren <= '1'; -- Assert tready/wren for only 1 clock else updt_curdesc_wren <= '0'; end if; end if; end process REG_MSB_CURPNTR; end generate GEN_UPPER_MSB_CURDESC; --------------------------------------------------------------------------- -- 32 Bit Scatter Gather addresses enabled --------------------------------------------------------------------------- GEN_NO_UPR_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate begin ----------------------------------------------------------------------- -- No upper order therefore dump fetched word and write pntr lower next -- pointer to pntr mngr ----------------------------------------------------------------------- REG_MSB_CURPNTR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then updt_curdesc_wren <= '0'; -- Throw away second word, only write curdesc out with msb -- set to zero elsif(write_curdesc_msb = '1')then updt_curdesc_wren <= '1'; -- Assert for only 1 clock else updt_curdesc_wren <= '0'; end if; end if; end process REG_MSB_CURPNTR; end generate GEN_NO_UPR_MSB_CURDESC; --********************************************************************* --** ERROR CAPTURE LOGIC --********************************************************************* ----------------------------------------------------------------------- -- Generate rising edge pulse on writing status signal. This will -- assert at the beginning of the status write. Coupled with status -- fifo set to first word fall through status will be on dout -- regardless of target ready. ----------------------------------------------------------------------- REG_WRITE_STATUS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then writing_status_d1 <= '0'; else writing_status_d1 <= writing_status; end if; end if; end process REG_WRITE_STATUS; writing_status_re <= writing_status and not writing_status_d1; --------------------------------------------------------------------------- -- Caputure IOC begin set --------------------------------------------------------------------------- REG_IOC_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or updt_ioc_irq_set = '1')then updt_ioc <= '0'; elsif(writing_status_re = '1')then updt_ioc <= s_axis_updtsts_tdata(DESC_IOC_TAG_BIT); end if; end if; end process REG_IOC_PROCESS; ----------------------------------------------------------------------- -- Capture DMA Internal Errors ----------------------------------------------------------------------- CAPTURE_DMAINT_ERROR: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dma_interr_set = '1')then dma_interr <= '0'; elsif(writing_status_re = '1')then dma_interr <= s_axis_updtsts_tdata(DESC_STS_INTERR_BIT); end if; end if; end process CAPTURE_DMAINT_ERROR; ----------------------------------------------------------------------- -- Capture DMA Slave Errors ----------------------------------------------------------------------- CAPTURE_DMASLV_ERROR: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dma_slverr_set = '1')then dma_slverr <= '0'; elsif(writing_status_re = '1')then dma_slverr <= s_axis_updtsts_tdata(DESC_STS_SLVERR_BIT); end if; end if; end process CAPTURE_DMASLV_ERROR; ----------------------------------------------------------------------- -- Capture DMA Decode Errors ----------------------------------------------------------------------- CAPTURE_DMADEC_ERROR: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dma_decerr_set = '1')then dma_decerr <= '0'; elsif(writing_status_re = '1')then dma_decerr <= s_axis_updtsts_tdata(DESC_STS_DECERR_BIT); end if; end if; end process CAPTURE_DMADEC_ERROR; end implementation;
------------------------------------------------------------------------------- -- axi_sg_updt_noqueue ------------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_sg_updt_noqueue.vhd -- Description: This entity provides the descriptor update for the No Queue mode -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- -- Structure: -- axi_sg.vhd -- axi_sg_pkg.vhd -- |- axi_sg_ftch_mngr.vhd -- | |- axi_sg_ftch_sm.vhd -- | |- axi_sg_ftch_pntr.vhd -- | |- axi_sg_ftch_cmdsts_if.vhd -- |- axi_sg_updt_mngr.vhd -- | |- axi_sg_updt_sm.vhd -- | |- axi_sg_updt_cmdsts_if.vhd -- |- axi_sg_ftch_q_mngr.vhd -- | |- axi_sg_ftch_queue.vhd -- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd -- | | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd -- | |- axi_sg_ftch_noqueue.vhd -- |- axi_sg_updt_q_mngr.vhd -- | |- axi_sg_updt_queue.vhd -- | | |- proc_common_v4_0_2.sync_fifo_fg.vhd -- | |- proc_common_v4_0_2.axi_sg_afifo_autord.vhd -- | |- axi_sg_updt_noqueue.vhd -- |- axi_sg_intrpt.vhd -- |- axi_datamover_v5_0.axi_datamover.vhd -- ------------------------------------------------------------------------------- -- Author: Gary Burch -- History: -- GAB 3/19/10 v1_00_a -- ^^^^^^ -- - Initial Release -- ~~~~~~ -- GAB 8/26/10 v2_00_a -- ^^^^^^ -- Seperated update queues into two seperate files, no queue and queue to -- simplify maintainance. -- ~~~~~~ -- GAB 10/21/10 v4_03 -- ^^^^^^ -- Rolled version to v4_03 -- ~~~~~~ -- GAB 11/15/10 v2_01_a -- ^^^^^^ -- CR582800 -- Converted all stream paraters ***_DATA_WIDTH to ***_TDATA_WIDTH -- ~~~~~~ -- GAB 6/13/11 v4_03 -- ^^^^^^ -- Update to AXI Datamover v4_03 -- Added aynchronous operation -- ~~~~~~ ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library axi_vdma_v6_2_8; use axi_vdma_v6_2_8.axi_sg_pkg.all; library lib_pkg_v1_0_2; library lib_fifo_v1_0_5; use lib_fifo_v1_0_5.sync_fifo_fg; use lib_pkg_v1_0_2.lib_pkg.all; ------------------------------------------------------------------------------- entity axi_sg_updt_noqueue is generic ( C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32; -- Master AXI Memory Map Address Width for Scatter Gather R/W Port C_M_AXIS_UPDT_DATA_WIDTH : integer range 32 to 32 := 32; -- Master AXI Memory Map Data Width for Scatter Gather R/W Port C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32; -- 32 Update Status Bits C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33 -- 1 IOC bit + 32 Update Status Bits ); port ( ----------------------------------------------------------------------- -- AXI Scatter Gather Interface ----------------------------------------------------------------------- m_axi_sg_aclk : in std_logic ; -- m_axi_sg_aresetn : in std_logic ; -- -- -- Channel 1 Control -- updt_curdesc_wren : out std_logic ; -- updt_curdesc : out std_logic_vector -- (C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; -- updt_active : in std_logic ; -- updt_queue_empty : out std_logic ; -- updt_ioc : out std_logic ; -- updt_ioc_irq_set : in std_logic ; -- -- dma_interr : out std_logic ; -- dma_slverr : out std_logic ; -- dma_decerr : out std_logic ; -- dma_interr_set : in std_logic ; -- dma_slverr_set : in std_logic ; -- dma_decerr_set : in std_logic ; -- -- --*********************************-- -- --** Channel Update Interface In **-- -- --*********************************-- -- -- Update Pointer Stream -- s_axis_updtptr_tdata : in std_logic_vector -- (C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) ; -- s_axis_updtptr_tvalid : in std_logic ; -- s_axis_updtptr_tready : out std_logic ; -- s_axis_updtptr_tlast : in std_logic ; -- -- -- Update Status Stream -- s_axis_updtsts_tdata : in std_logic_vector -- (C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); -- s_axis_updtsts_tvalid : in std_logic ; -- s_axis_updtsts_tready : out std_logic ; -- s_axis_updtsts_tlast : in std_logic ; -- -- --*********************************-- -- --** Channel Update Interface Out**-- -- --*********************************-- -- -- S2MM Stream Out To DataMover -- m_axis_updt_tdata : out std_logic_vector -- (C_M_AXIS_UPDT_DATA_WIDTH-1 downto 0); -- m_axis_updt_tlast : out std_logic ; -- m_axis_updt_tvalid : out std_logic ; -- m_axis_updt_tready : in std_logic -- ); end axi_sg_updt_noqueue; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_sg_updt_noqueue is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- No Contstants Declared ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- -- Channel signals signal writing_curdesc : std_logic := '0'; signal write_curdesc_lsb : std_logic := '0'; signal write_curdesc_msb : std_logic := '0'; signal updt_active_d1 : std_logic := '0'; signal updt_active_re : std_logic := '0'; type PNTR_STATE_TYPE is (IDLE, READ_CURDESC_LSB, READ_CURDESC_MSB, WRITE_STATUS ); signal pntr_cs : PNTR_STATE_TYPE; signal pntr_ns : PNTR_STATE_TYPE; signal writing_status : std_logic := '0'; signal curdesc_tready : std_logic := '0'; signal writing_status_d1 : std_logic := '0'; signal writing_status_re : std_logic := '0'; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin -- Asset active strobe on rising edge of update active -- asertion. This kicks off the update process for -- the channel REG_ACTIVE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then updt_active_d1 <= '0'; else updt_active_d1 <= updt_active; end if; end if; end process REG_ACTIVE; updt_active_re <= updt_active and not updt_active_d1; -- Current Descriptor Pointer Fetch. This state machine controls -- reading out the current pointer from the Queue or channel port -- and writing it to the update manager for use in command -- generation to the DataMover for Descriptor update. CURDESC_PNTR_STATE : process(pntr_cs, updt_active, s_axis_updtptr_tvalid, s_axis_updtsts_tvalid, s_axis_updtsts_tlast, m_axis_updt_tready) begin write_curdesc_lsb <= '0'; write_curdesc_msb <= '0'; writing_status <= '0'; writing_curdesc <= '0'; curdesc_tready <= '0'; pntr_ns <= pntr_cs; case pntr_cs is when IDLE => if(s_axis_updtptr_tvalid = '1' and updt_active = '1')then writing_curdesc <= '1'; pntr_ns <= READ_CURDESC_LSB; else pntr_ns <= IDLE; end if; --------------------------------------------------------------- -- Get lower current descriptor when READ_CURDESC_LSB => curdesc_tready <= '1'; writing_curdesc <= '1'; -- on tvalid from Queue or channel port then register -- lsb curdesc and setup to register msb curdesc if(s_axis_updtptr_tvalid = '1' and updt_active = '1')then write_curdesc_lsb <= '1'; pntr_ns <= READ_CURDESC_MSB; else pntr_ns <= READ_CURDESC_LSB; end if; --------------------------------------------------------------- -- Get upper current descriptor when READ_CURDESC_MSB => curdesc_tready <= '1'; writing_curdesc <= '1'; -- On tvalid from Queue or channel port then register -- msb. This will also write curdesc out to update -- manager. if(s_axis_updtptr_tvalid = '1')then write_curdesc_msb <= '1'; pntr_ns <= WRITE_STATUS; else pntr_ns <= READ_CURDESC_MSB; end if; --------------------------------------------------------------- -- Hold in this state until remainder of descriptor is -- written out. when WRITE_STATUS => writing_status <= s_axis_updtsts_tvalid; if(s_axis_updtsts_tvalid = '1' and m_axis_updt_tready = '1' and s_axis_updtsts_tlast = '1')then pntr_ns <= IDLE; else pntr_ns <= WRITE_STATUS; end if; when others => pntr_ns <= IDLE; end case; end process CURDESC_PNTR_STATE; --------------------------------------------------------------------------- -- Register for CURDESC Pointer state machine --------------------------------------------------------------------------- REG_PNTR_STATES : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then pntr_cs <= IDLE; else pntr_cs <= pntr_ns; end if; end if; end process REG_PNTR_STATES; -- Status stream signals m_axis_updt_tdata <= s_axis_updtsts_tdata(C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0); m_axis_updt_tvalid <= s_axis_updtsts_tvalid and writing_status; m_axis_updt_tlast <= s_axis_updtsts_tlast and writing_status; s_axis_updtsts_tready <= m_axis_updt_tready and writing_status; -- Pointer stream signals s_axis_updtptr_tready <= curdesc_tready; -- Indicate need for channel service for update state machine updt_queue_empty <= not s_axis_updtsts_tvalid; --********************************************************************* --** POINTER CAPTURE LOGIC --********************************************************************* --------------------------------------------------------------------------- -- Write lower order Next Descriptor Pointer out to pntr_mngr --------------------------------------------------------------------------- REG_LSB_CURPNTR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then updt_curdesc(31 downto 0) <= (others => '0'); -- Capture lower pointer from FIFO or channel port elsif(write_curdesc_lsb = '1')then updt_curdesc(31 downto 0) <= s_axis_updtptr_tdata(C_S_AXIS_UPDPTR_TDATA_WIDTH - 1 downto 0); end if; end if; end process REG_LSB_CURPNTR; --------------------------------------------------------------------------- -- 64 Bit Scatter Gather addresses enabled --------------------------------------------------------------------------- GEN_UPPER_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate begin --------------------------------------------------------------------------- -- Write upper order Next Descriptor Pointer out to pntr_mngr --------------------------------------------------------------------------- REG_MSB_CURPNTR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then updt_curdesc(63 downto 32) <= (others => '0'); updt_curdesc_wren <= '0'; -- Capture upper pointer from FIFO or channel port -- and also write curdesc out elsif(write_curdesc_msb = '1')then updt_curdesc(63 downto 32) <= s_axis_updtptr_tdata(C_S_AXIS_UPDPTR_TDATA_WIDTH - 1 downto 0); updt_curdesc_wren <= '1'; -- Assert tready/wren for only 1 clock else updt_curdesc_wren <= '0'; end if; end if; end process REG_MSB_CURPNTR; end generate GEN_UPPER_MSB_CURDESC; --------------------------------------------------------------------------- -- 32 Bit Scatter Gather addresses enabled --------------------------------------------------------------------------- GEN_NO_UPR_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate begin ----------------------------------------------------------------------- -- No upper order therefore dump fetched word and write pntr lower next -- pointer to pntr mngr ----------------------------------------------------------------------- REG_MSB_CURPNTR : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' )then updt_curdesc_wren <= '0'; -- Throw away second word, only write curdesc out with msb -- set to zero elsif(write_curdesc_msb = '1')then updt_curdesc_wren <= '1'; -- Assert for only 1 clock else updt_curdesc_wren <= '0'; end if; end if; end process REG_MSB_CURPNTR; end generate GEN_NO_UPR_MSB_CURDESC; --********************************************************************* --** ERROR CAPTURE LOGIC --********************************************************************* ----------------------------------------------------------------------- -- Generate rising edge pulse on writing status signal. This will -- assert at the beginning of the status write. Coupled with status -- fifo set to first word fall through status will be on dout -- regardless of target ready. ----------------------------------------------------------------------- REG_WRITE_STATUS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0')then writing_status_d1 <= '0'; else writing_status_d1 <= writing_status; end if; end if; end process REG_WRITE_STATUS; writing_status_re <= writing_status and not writing_status_d1; --------------------------------------------------------------------------- -- Caputure IOC begin set --------------------------------------------------------------------------- REG_IOC_PROCESS : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or updt_ioc_irq_set = '1')then updt_ioc <= '0'; elsif(writing_status_re = '1')then updt_ioc <= s_axis_updtsts_tdata(DESC_IOC_TAG_BIT); end if; end if; end process REG_IOC_PROCESS; ----------------------------------------------------------------------- -- Capture DMA Internal Errors ----------------------------------------------------------------------- CAPTURE_DMAINT_ERROR: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dma_interr_set = '1')then dma_interr <= '0'; elsif(writing_status_re = '1')then dma_interr <= s_axis_updtsts_tdata(DESC_STS_INTERR_BIT); end if; end if; end process CAPTURE_DMAINT_ERROR; ----------------------------------------------------------------------- -- Capture DMA Slave Errors ----------------------------------------------------------------------- CAPTURE_DMASLV_ERROR: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dma_slverr_set = '1')then dma_slverr <= '0'; elsif(writing_status_re = '1')then dma_slverr <= s_axis_updtsts_tdata(DESC_STS_SLVERR_BIT); end if; end if; end process CAPTURE_DMASLV_ERROR; ----------------------------------------------------------------------- -- Capture DMA Decode Errors ----------------------------------------------------------------------- CAPTURE_DMADEC_ERROR: process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(m_axi_sg_aresetn = '0' or dma_decerr_set = '1')then dma_decerr <= '0'; elsif(writing_status_re = '1')then dma_decerr <= s_axis_updtsts_tdata(DESC_STS_DECERR_BIT); end if; end if; end process CAPTURE_DMADEC_ERROR; end implementation;
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity d_flip_flop is Port ( clk : in std_logic; reset : in std_logic; din : in std_logic; dout : out std_logic ); end d_flip_flop; architecture Behavioral of d_flip_flop is begin process (CLK, RESET) begin if RESET='1' then --asynchronous RESET active High DOUT <= '0'; elsif (CLK'event and CLK='1') then --CLK rising edge DOUT <= DIN; end if; end process; end Behavioral;
-- control module (implements MIPS control unit) LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_SIGNED.ALL; ENTITY control IS PORT( SIGNAL Opcode : IN STD_LOGIC_VECTOR( 5 DOWNTO 0 ); SIGNAL RegDst : OUT STD_LOGIC; SIGNAL ALUSrc : OUT STD_LOGIC; SIGNAL MemtoReg : OUT STD_LOGIC; SIGNAL RegWrite : OUT STD_LOGIC; SIGNAL D_RegWrite_out : OUT STD_LOGIC; SIGNAL DD_RegWrite_out : OUT STD_LOGIC; SIGNAL MemRead : OUT STD_LOGIC; SIGNAL MemWrite : OUT STD_LOGIC; SIGNAL Branch : OUT STD_LOGIC; SIGNAL ALUop : OUT STD_LOGIC_VECTOR( 1 DOWNTO 0 ); SIGNAL clock, reset : IN STD_LOGIC ); END control; ARCHITECTURE behavior OF control IS SIGNAL R_format, Lw, Sw, Beq : STD_LOGIC; SIGNAL D_ALUSrc : STD_LOGIC; SIGNAL D_ALUOp : STD_LOGIC_VECTOR( 1 DOWNTO 0 ); SIGNAL D_Branch, DD_Branch : STD_LOGIC; SIGNAL D_MemRead, DD_MemRead : STD_LOGIC; SIGNAL D_MemWrite, DD_MemWrite : STD_LOGIC; SIGNAL D_MemtoReg, DD_MemtoReg, DDD_MemtoReg : STD_LOGIC; SIGNAL D_RegWrite, DD_RegWrite, DDD_RegWrite : STD_LOGIC; BEGIN -- Code to generate control signals using opcode bits R_format <= '1' WHEN Opcode = "000000" ELSE '0'; Lw <= '1' WHEN Opcode = "100011" ELSE '0'; Sw <= '1' WHEN Opcode = "101011" ELSE '0'; Beq <= '1' WHEN Opcode = "000100" ELSE '0'; RegDst <= R_format; D_ALUSrc <= Lw OR Sw; D_ALUOp( 1 ) <= R_format; D_ALUOp( 0 ) <= Beq; DD_MemRead <= Lw; DD_MemWrite <= Sw; Branch <= Beq; DDD_MemtoReg <= Lw; DDD_RegWrite <= R_format OR Lw; D_RegWrite_out <= D_RegWrite; DD_RegWrite_out <= DD_RegWrite; PROCESS BEGIN WAIT UNTIL clock'EVENT AND clock='1'; IF reset = '1' THEN ALUop <= "00"; ALUSrc <= '0'; MemRead <= '0'; D_MemRead <= '0'; MemWrite <= '0'; D_MemWrite <= '0'; D_Branch <= '0'; MemtoReg <= '0'; D_MemtoReg <= '0'; DD_MemtoReg <= '0'; RegWrite <= '0'; D_RegWrite <= '0'; DD_RegWrite <= '0'; ELSE ALUSrc <= D_ALUsrc; ALUOp <= D_ALUOp; MemRead <= D_MemRead; D_MemRead <= DD_MemRead; MemWrite <= D_MemWrite; D_MemWrite <= DD_MemWrite; MemtoReg <= D_MemtoReg; D_MemtoReg <= DD_MemtoReg; DD_MemtoReg <= DDD_MemtoReg; RegWrite <= D_RegWrite; D_RegWrite <= DD_RegWrite; DD_RegWrite <= DDD_RegWrite; END IF; END PROCESS; END behavior;
package STRSYN is attribute SigDir : string; attribute SigType : string; attribute SigBias : string; end STRSYN; entity op is port ( terminal in1: electrical; terminal in2: electrical; terminal out1: electrical; terminal vbias4: electrical; terminal gnd: electrical; terminal vdd: electrical; terminal vbias2: electrical; terminal vbias1: electrical; terminal vbias3: electrical); end op; architecture simple of op is -- Attributes for Ports attribute SigDir of in1:terminal is "input"; attribute SigType of in1:terminal is "voltage"; attribute SigDir of in2:terminal is "input"; attribute SigType of in2:terminal is "voltage"; attribute SigDir of out1:terminal is "output"; attribute SigType of out1:terminal is "voltage"; attribute SigDir of vbias4:terminal is "reference"; attribute SigType of vbias4:terminal is "voltage"; attribute SigDir of gnd:terminal is "reference"; attribute SigType of gnd:terminal is "current"; attribute SigBias of gnd:terminal is "negative"; attribute SigDir of vdd:terminal is "reference"; attribute SigType of vdd:terminal is "current"; attribute SigBias of vdd:terminal is "positive"; attribute SigDir of vbias2:terminal is "reference"; attribute SigType of vbias2:terminal is "voltage"; attribute SigDir of vbias1:terminal is "reference"; attribute SigType of vbias1:terminal is "voltage"; attribute SigDir of vbias3:terminal is "reference"; attribute SigType of vbias3:terminal is "voltage"; terminal net1: electrical; terminal net2: electrical; terminal net3: electrical; terminal net4: electrical; terminal net5: electrical; terminal net6: electrical; terminal net7: electrical; terminal net8: electrical; terminal net9: electrical; terminal net10: electrical; terminal net11: electrical; terminal net12: electrical; begin subnet0_subnet0_m1 : entity nmos(behave) generic map( L => Ldiff_0, W => Wdiff_0, scope => private ) port map( D => net1, G => in1, S => net6 ); subnet0_subnet0_m2 : entity nmos(behave) generic map( L => Ldiff_0, W => Wdiff_0, scope => private ) port map( D => net2, G => in2, S => net6 ); subnet0_subnet0_m3 : entity nmos(behave) generic map( L => LBias, W => W_0 ) port map( D => net6, G => vbias4, S => gnd ); subnet0_subnet0_m4 : entity nmos(behave) generic map( L => Ldiff_0, W => Wdiff_0, scope => private ) port map( D => net7, G => in1, S => net6 ); subnet0_subnet0_m5 : entity nmos(behave) generic map( L => Ldiff_0, W => Wdiff_0, scope => private ) port map( D => net7, G => in2, S => net6 ); subnet0_subnet0_m6 : entity pmos(behave) generic map( L => Lcmdiffp_0, W => Wcmdiffp_0, scope => private ) port map( D => net7, G => net7, S => vdd ); subnet0_subnet0_m7 : entity pmos(behave) generic map( L => Lcmdiffp_0, W => Wcmdiffp_0, scope => private ) port map( D => net7, G => net7, S => vdd ); subnet0_subnet0_m8 : entity pmos(behave) generic map( L => Lcmdiffp_0, W => Wcmdiffp_0, scope => private ) port map( D => net1, G => net7, S => vdd ); subnet0_subnet0_m9 : entity pmos(behave) generic map( L => Lcmdiffp_0, W => Wcmdiffp_0, scope => private ) port map( D => net2, G => net7, S => vdd ); subnet0_subnet1_m1 : entity nmos(behave) generic map( L => Lsrc, W => Wsrc_2, scope => Wprivate, symmetry_scope => sym_7 ) port map( D => net3, G => net1, S => gnd ); subnet0_subnet2_m1 : entity nmos(behave) generic map( L => Lsrc, W => Wsrc_2, scope => Wprivate, symmetry_scope => sym_7 ) port map( D => net4, G => net2, S => gnd ); subnet0_subnet3_m1 : entity pmos(behave) generic map( L => LBias, W => Wcmcasc_3, scope => Wprivate, symmetry_scope => sym_8 ) port map( D => net3, G => vbias2, S => net8 ); subnet0_subnet3_m2 : entity pmos(behave) generic map( L => Lcm_3, W => Wcm_3, scope => private, symmetry_scope => sym_8 ) port map( D => net8, G => net3, S => vdd ); subnet0_subnet3_m3 : entity pmos(behave) generic map( L => Lcm_3, W => Wcmout_3, scope => private, symmetry_scope => sym_8 ) port map( D => net9, G => net3, S => vdd ); subnet0_subnet3_m4 : entity pmos(behave) generic map( L => LBias, W => Wcmcasc_3, scope => Wprivate, symmetry_scope => sym_8 ) port map( D => net5, G => vbias2, S => net9 ); subnet0_subnet4_m1 : entity pmos(behave) generic map( L => LBias, W => Wcmcasc_3, scope => Wprivate, symmetry_scope => sym_8 ) port map( D => net4, G => vbias2, S => net10 ); subnet0_subnet4_m2 : entity pmos(behave) generic map( L => Lcm_3, W => Wcm_3, scope => private, symmetry_scope => sym_8 ) port map( D => net10, G => net4, S => vdd ); subnet0_subnet4_m3 : entity pmos(behave) generic map( L => Lcm_3, W => Wcmout_3, scope => private, symmetry_scope => sym_8 ) port map( D => net11, G => net4, S => vdd ); subnet0_subnet4_m4 : entity pmos(behave) generic map( L => LBias, W => Wcmcasc_3, scope => Wprivate, symmetry_scope => sym_8 ) port map( D => out1, G => vbias2, S => net11 ); subnet0_subnet5_m1 : entity nmos(behave) generic map( L => Lcm_1, W => Wcm_1, scope => private ) port map( D => net5, G => net5, S => gnd ); subnet0_subnet5_m2 : entity nmos(behave) generic map( L => Lcm_1, W => Wcmcout_1, scope => private ) port map( D => out1, G => net5, S => gnd ); subnet1_subnet0_m1 : entity pmos(behave) generic map( L => LBias, W => (pfak)*(WBias) ) port map( D => vbias1, G => vbias1, S => vdd ); subnet1_subnet0_m2 : entity pmos(behave) generic map( L => (pfak)*(LBias), W => (pfak)*(WBias) ) port map( D => vbias2, G => vbias2, S => vbias1 ); subnet1_subnet0_i1 : entity idc(behave) generic map( dc => 1.145e-05 ) port map( P => vdd, N => vbias3 ); subnet1_subnet0_m3 : entity nmos(behave) generic map( L => (pfak)*(LBias), W => WBias ) port map( D => vbias3, G => vbias3, S => vbias4 ); subnet1_subnet0_m4 : entity nmos(behave) generic map( L => LBias, W => WBias ) port map( D => vbias2, G => vbias3, S => net12 ); subnet1_subnet0_m5 : entity nmos(behave) generic map( L => LBias, W => WBias ) port map( D => vbias4, G => vbias4, S => gnd ); subnet1_subnet0_m6 : entity nmos(behave) generic map( L => LBias, W => WBias ) port map( D => net12, G => vbias4, S => gnd ); end simple;
-- ====================================================================== -- CBC-MAC-DES -- Copyright (C) 2015 Torsten Meissner ------------------------------------------------------------------------- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -- ====================================================================== library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.des_pkg.all; entity cbcmac_des is port ( reset_i : in std_logic; -- low active async reset clk_i : in std_logic; -- clock start_i : in std_logic; -- start cbc key_i : in std_logic_vector(0 to 63); -- key input data_i : in std_logic_vector(0 to 63); -- data input valid_i : in std_logic; -- input key/data valid flag accept_o : out std_logic; -- input accept data_o : out std_logic_vector(0 tO 63); -- data output valid_o : out std_logic; -- output data valid flag accept_i : in std_logic -- output accept ); end entity cbcmac_des; architecture rtl of cbcmac_des is component des is generic ( design_type : string := "ITER" ); port ( reset_i : in std_logic; clk_i : in std_logic; mode_i : in std_logic; key_i : in std_logic_vector(0 to 63); data_i : in std_logic_vector(0 to 63); valid_i : in std_logic; accept_o : out std_logic; data_o : out std_logic_vector(0 to 63); valid_o : out std_logic; accept_i : in std_logic ); end component des; -- CBCMAC must have fix IV for security reasons constant C_IV : std_logic_vector(0 to 63) := (others => '0'); signal s_des_datain : std_logic_vector(0 to 63); signal s_des_dataout : std_logic_vector(0 to 63); signal s_des_dataout_d : std_logic_vector(0 to 63); signal s_des_key : std_logic_vector(0 to 63); signal s_key : std_logic_vector(0 to 63); signal s_des_accept : std_logic; signal s_des_validout : std_logic; begin s_des_datain <= C_IV xor data_i when start_i = '1' else s_des_dataout_d xor data_i; data_o <= s_des_dataout; s_des_key <= key_i when start_i = '1' else s_key; accept_o <= s_des_accept; valid_o <= s_des_validout; inputregister : process(clk_i, reset_i) is begin if(reset_i = '0') then s_key <= (others => '0'); elsif(rising_edge(clk_i)) then if(valid_i = '1' and s_des_accept = '1' and start_i = '1') then s_key <= key_i; end if; end if; end process inputregister; outputregister : process(clk_i, reset_i) is begin if(reset_i = '0') then s_des_dataout_d <= (others => '0'); elsif(rising_edge(clk_i)) then if(s_des_validout = '1') then s_des_dataout_d <= s_des_dataout; end if; end if; end process outputregister; i_des : des generic map ( design_type => "ITER" ) port map ( reset_i => reset_i, clk_i => clk_i, mode_i => '0', key_i => s_des_key, data_i => s_des_datain, valid_i => valid_i, accept_o => s_des_accept, data_o => s_des_dataout, valid_o => s_des_validout, accept_i => accept_i ); end architecture rtl;
---------------------------------------------------------------------------------- -- Company: TU Vienna -- Engineer: Georg Blemenschitz -- -- Create Date: 17:41:00 12/02/2009 -- Design Name: FIFO -- Module Name: tb_FIFOSync -- Description: VHDL Test Bench for module: FIFOSyncTop -- -- Revision: -- Revision 0.01 - File Created ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity tb_FIFOSync is end tb_FIFOSync;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1969.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c07s02b01x00p02n02i01969ent IS END c07s02b01x00p02n02i01969ent; ARCHITECTURE c07s02b01x00p02n02i01969arch OF c07s02b01x00p02n02i01969ent IS BEGIN TESTING: PROCESS variable a : boolean := TRUE; variable b : boolean := FALSE; variable c : boolean; BEGIN c := a nor b; assert NOT(c=FALSE) report "***PASSED TEST: c07s02b01x00p02n02i01969" severity NOTE; assert ( c=FALSE ) report "***FAILED TEST: c07s02b01x00p02n02i01969 - Logical operation of 'NOR'." severity ERROR; wait; END PROCESS TESTING; END c07s02b01x00p02n02i01969arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1969.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c07s02b01x00p02n02i01969ent IS END c07s02b01x00p02n02i01969ent; ARCHITECTURE c07s02b01x00p02n02i01969arch OF c07s02b01x00p02n02i01969ent IS BEGIN TESTING: PROCESS variable a : boolean := TRUE; variable b : boolean := FALSE; variable c : boolean; BEGIN c := a nor b; assert NOT(c=FALSE) report "***PASSED TEST: c07s02b01x00p02n02i01969" severity NOTE; assert ( c=FALSE ) report "***FAILED TEST: c07s02b01x00p02n02i01969 - Logical operation of 'NOR'." severity ERROR; wait; END PROCESS TESTING; END c07s02b01x00p02n02i01969arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1969.vhd,v 1.2 2001-10-26 16:29:44 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c07s02b01x00p02n02i01969ent IS END c07s02b01x00p02n02i01969ent; ARCHITECTURE c07s02b01x00p02n02i01969arch OF c07s02b01x00p02n02i01969ent IS BEGIN TESTING: PROCESS variable a : boolean := TRUE; variable b : boolean := FALSE; variable c : boolean; BEGIN c := a nor b; assert NOT(c=FALSE) report "***PASSED TEST: c07s02b01x00p02n02i01969" severity NOTE; assert ( c=FALSE ) report "***FAILED TEST: c07s02b01x00p02n02i01969 - Logical operation of 'NOR'." severity ERROR; wait; END PROCESS TESTING; END c07s02b01x00p02n02i01969arch;
---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 11/11/2016 01:36:23 PM -- Design Name: -- Module Name: Top_Level_TB - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Top_Level_TB is -- Port ( ); end Top_Level_TB; architecture Behavioral of Top_Level_TB is component Top_Level is Port ( iClk : in std_logic; iRst : in std_logic; iCommand32 : in std_logic_vector(31 downto 0); oResult1 : out std_logic_vector(31 downto 0); oResult2 : out std_logic_vector(31 downto 0) ); end component; signal s_Clk : std_logic := '1'; signal s_Rst : std_logic; signal s_Command32 : std_logic_vector(31 downto 0); signal s_Result1 : std_logic_vector(31 downto 0); signal s_Result2 : std_logic_vector(31 downto 0); begin s_Clk <= not s_Clk after 10 ns; DUT: Top_Level port map( iClk => s_Clk, iRst => s_Rst, iCommand32 => s_Command32, oResult1 => s_Result1, oResult2 => s_Result2 ); Test: process begin s_Rst <= '1'; wait for 10 ns; s_Rst <= '0'; s_Command32 <= "00000010001100100100000000100000"; wait for 10 ns; wait; end process; end Behavioral;
`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block DYkUg37UnVRJ+X5v5iFDmCWObMw/mUCrJuxa/Cr9wGl4FgcJi6OQesLI1M+aH7+emQJssoNWrh+N iL9trwbpEg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Vb74X6mc2H0e6MLiEAhBKZ84QSTgHhg3aAfwLeb5H8AGScZ7UqNDKDmI5IhuJ/LPpdHQCtOent5+ I1p5tELHTH0LzN6BILTKGZBdaGJ2AKKoofyljqaR51srCF/ZJLUOrn1XUZMkdlutYXGikghh+zK5 6+/HFEYyz6zhpfFGpAE= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block DUY8u9eRLqeXCDG4E2/8OtDIacK06AysbSio1XfMMKnofNQFNkb8eAjngrn4u/YZ6G16ZNMG7YoY jk2Rx2Q3M5GrNkHLNcW1r1FM93KBIPYna3s3UsOdPXI8u/gdrTwtTwv/xpFT5pO5KUummozg1ol2 CfVK4phP0ptL6RF00qSF6IA3NotRdVSf39i8Abyti2fNqAeVQtQbe8y1/1WV9RrHHqEjarv5sqIY 6GslwJ8wdJjPL0QS11gBEh6rDpndqUhWIIFTUrFMd1tEU2WzUCNSxtbBPYlWfpU8e4/l9e5xSsF6 weW3wzZvwjgR473vdWcupdpbpXFjQjfOA39+/w== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block p0GGQgjzPW+6PIUsMdZXTQnjW6BUopNyvt7ApHmGMwjrt0lKkYFdeq6NnHPNeKi9xrrloGAO2Tha FhPoK1WSUQvFoRR4uKVUk0OywXYhciTgYL90XL5T7z6pvP+T2xdoDnAiUPoqzH/Ubhhi84EoGyo2 +zIDCCcTvvnznOBjfpk= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block m1/kaqW4ETEcDTOeEJMS5yQHRelnhe+7sXgpcKiP6lTf8NZHj87LtgfMx1Oh7TGMtL3OsgLwXKl5 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block DYkUg37UnVRJ+X5v5iFDmCWObMw/mUCrJuxa/Cr9wGl4FgcJi6OQesLI1M+aH7+emQJssoNWrh+N iL9trwbpEg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Vb74X6mc2H0e6MLiEAhBKZ84QSTgHhg3aAfwLeb5H8AGScZ7UqNDKDmI5IhuJ/LPpdHQCtOent5+ I1p5tELHTH0LzN6BILTKGZBdaGJ2AKKoofyljqaR51srCF/ZJLUOrn1XUZMkdlutYXGikghh+zK5 6+/HFEYyz6zhpfFGpAE= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block DUY8u9eRLqeXCDG4E2/8OtDIacK06AysbSio1XfMMKnofNQFNkb8eAjngrn4u/YZ6G16ZNMG7YoY jk2Rx2Q3M5GrNkHLNcW1r1FM93KBIPYna3s3UsOdPXI8u/gdrTwtTwv/xpFT5pO5KUummozg1ol2 CfVK4phP0ptL6RF00qSF6IA3NotRdVSf39i8Abyti2fNqAeVQtQbe8y1/1WV9RrHHqEjarv5sqIY 6GslwJ8wdJjPL0QS11gBEh6rDpndqUhWIIFTUrFMd1tEU2WzUCNSxtbBPYlWfpU8e4/l9e5xSsF6 weW3wzZvwjgR473vdWcupdpbpXFjQjfOA39+/w== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block p0GGQgjzPW+6PIUsMdZXTQnjW6BUopNyvt7ApHmGMwjrt0lKkYFdeq6NnHPNeKi9xrrloGAO2Tha FhPoK1WSUQvFoRR4uKVUk0OywXYhciTgYL90XL5T7z6pvP+T2xdoDnAiUPoqzH/Ubhhi84EoGyo2 +zIDCCcTvvnznOBjfpk= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block m1/kaqW4ETEcDTOeEJMS5yQHRelnhe+7sXgpcKiP6lTf8NZHj87LtgfMx1Oh7TGMtL3OsgLwXKl5 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block DYkUg37UnVRJ+X5v5iFDmCWObMw/mUCrJuxa/Cr9wGl4FgcJi6OQesLI1M+aH7+emQJssoNWrh+N iL9trwbpEg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Vb74X6mc2H0e6MLiEAhBKZ84QSTgHhg3aAfwLeb5H8AGScZ7UqNDKDmI5IhuJ/LPpdHQCtOent5+ I1p5tELHTH0LzN6BILTKGZBdaGJ2AKKoofyljqaR51srCF/ZJLUOrn1XUZMkdlutYXGikghh+zK5 6+/HFEYyz6zhpfFGpAE= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block DYkUg37UnVRJ+X5v5iFDmCWObMw/mUCrJuxa/Cr9wGl4FgcJi6OQesLI1M+aH7+emQJssoNWrh+N iL9trwbpEg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Vb74X6mc2H0e6MLiEAhBKZ84QSTgHhg3aAfwLeb5H8AGScZ7UqNDKDmI5IhuJ/LPpdHQCtOent5+ I1p5tELHTH0LzN6BILTKGZBdaGJ2AKKoofyljqaR51srCF/ZJLUOrn1XUZMkdlutYXGikghh+zK5 6+/HFEYyz6zhpfFGpAE= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block DYkUg37UnVRJ+X5v5iFDmCWObMw/mUCrJuxa/Cr9wGl4FgcJi6OQesLI1M+aH7+emQJssoNWrh+N iL9trwbpEg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Vb74X6mc2H0e6MLiEAhBKZ84QSTgHhg3aAfwLeb5H8AGScZ7UqNDKDmI5IhuJ/LPpdHQCtOent5+ I1p5tELHTH0LzN6BILTKGZBdaGJ2AKKoofyljqaR51srCF/ZJLUOrn1XUZMkdlutYXGikghh+zK5 6+/HFEYyz6zhpfFGpAE= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block DYkUg37UnVRJ+X5v5iFDmCWObMw/mUCrJuxa/Cr9wGl4FgcJi6OQesLI1M+aH7+emQJssoNWrh+N iL9trwbpEg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Vb74X6mc2H0e6MLiEAhBKZ84QSTgHhg3aAfwLeb5H8AGScZ7UqNDKDmI5IhuJ/LPpdHQCtOent5+ I1p5tELHTH0LzN6BILTKGZBdaGJ2AKKoofyljqaR51srCF/ZJLUOrn1XUZMkdlutYXGikghh+zK5 6+/HFEYyz6zhpfFGpAE= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block DYkUg37UnVRJ+X5v5iFDmCWObMw/mUCrJuxa/Cr9wGl4FgcJi6OQesLI1M+aH7+emQJssoNWrh+N iL9trwbpEg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Vb74X6mc2H0e6MLiEAhBKZ84QSTgHhg3aAfwLeb5H8AGScZ7UqNDKDmI5IhuJ/LPpdHQCtOent5+ I1p5tELHTH0LzN6BILTKGZBdaGJ2AKKoofyljqaR51srCF/ZJLUOrn1XUZMkdlutYXGikghh+zK5 6+/HFEYyz6zhpfFGpAE= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block DYkUg37UnVRJ+X5v5iFDmCWObMw/mUCrJuxa/Cr9wGl4FgcJi6OQesLI1M+aH7+emQJssoNWrh+N iL9trwbpEg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Vb74X6mc2H0e6MLiEAhBKZ84QSTgHhg3aAfwLeb5H8AGScZ7UqNDKDmI5IhuJ/LPpdHQCtOent5+ I1p5tELHTH0LzN6BILTKGZBdaGJ2AKKoofyljqaR51srCF/ZJLUOrn1XUZMkdlutYXGikghh+zK5 6+/HFEYyz6zhpfFGpAE= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block DUY8u9eRLqeXCDG4E2/8OtDIacK06AysbSio1XfMMKnofNQFNkb8eAjngrn4u/YZ6G16ZNMG7YoY jk2Rx2Q3M5GrNkHLNcW1r1FM93KBIPYna3s3UsOdPXI8u/gdrTwtTwv/xpFT5pO5KUummozg1ol2 CfVK4phP0ptL6RF00qSF6IA3NotRdVSf39i8Abyti2fNqAeVQtQbe8y1/1WV9RrHHqEjarv5sqIY 6GslwJ8wdJjPL0QS11gBEh6rDpndqUhWIIFTUrFMd1tEU2WzUCNSxtbBPYlWfpU8e4/l9e5xSsF6 weW3wzZvwjgR473vdWcupdpbpXFjQjfOA39+/w== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block p0GGQgjzPW+6PIUsMdZXTQnjW6BUopNyvt7ApHmGMwjrt0lKkYFdeq6NnHPNeKi9xrrloGAO2Tha FhPoK1WSUQvFoRR4uKVUk0OywXYhciTgYL90XL5T7z6pvP+T2xdoDnAiUPoqzH/Ubhhi84EoGyo2 +zIDCCcTvvnznOBjfpk= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block m1/kaqW4ETEcDTOeEJMS5yQHRelnhe+7sXgpcKiP6lTf8NZHj87LtgfMx1Oh7TGMtL3OsgLwXKl5 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block DYkUg37UnVRJ+X5v5iFDmCWObMw/mUCrJuxa/Cr9wGl4FgcJi6OQesLI1M+aH7+emQJssoNWrh+N iL9trwbpEg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Vb74X6mc2H0e6MLiEAhBKZ84QSTgHhg3aAfwLeb5H8AGScZ7UqNDKDmI5IhuJ/LPpdHQCtOent5+ I1p5tELHTH0LzN6BILTKGZBdaGJ2AKKoofyljqaR51srCF/ZJLUOrn1XUZMkdlutYXGikghh+zK5 6+/HFEYyz6zhpfFGpAE= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block DYkUg37UnVRJ+X5v5iFDmCWObMw/mUCrJuxa/Cr9wGl4FgcJi6OQesLI1M+aH7+emQJssoNWrh+N iL9trwbpEg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Vb74X6mc2H0e6MLiEAhBKZ84QSTgHhg3aAfwLeb5H8AGScZ7UqNDKDmI5IhuJ/LPpdHQCtOent5+ I1p5tELHTH0LzN6BILTKGZBdaGJ2AKKoofyljqaR51srCF/ZJLUOrn1XUZMkdlutYXGikghh+zK5 6+/HFEYyz6zhpfFGpAE= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block DYkUg37UnVRJ+X5v5iFDmCWObMw/mUCrJuxa/Cr9wGl4FgcJi6OQesLI1M+aH7+emQJssoNWrh+N iL9trwbpEg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Vb74X6mc2H0e6MLiEAhBKZ84QSTgHhg3aAfwLeb5H8AGScZ7UqNDKDmI5IhuJ/LPpdHQCtOent5+ I1p5tELHTH0LzN6BILTKGZBdaGJ2AKKoofyljqaR51srCF/ZJLUOrn1XUZMkdlutYXGikghh+zK5 6+/HFEYyz6zhpfFGpAE= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block DYkUg37UnVRJ+X5v5iFDmCWObMw/mUCrJuxa/Cr9wGl4FgcJi6OQesLI1M+aH7+emQJssoNWrh+N iL9trwbpEg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Vb74X6mc2H0e6MLiEAhBKZ84QSTgHhg3aAfwLeb5H8AGScZ7UqNDKDmI5IhuJ/LPpdHQCtOent5+ I1p5tELHTH0LzN6BILTKGZBdaGJ2AKKoofyljqaR51srCF/ZJLUOrn1XUZMkdlutYXGikghh+zK5 6+/HFEYyz6zhpfFGpAE= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block DYkUg37UnVRJ+X5v5iFDmCWObMw/mUCrJuxa/Cr9wGl4FgcJi6OQesLI1M+aH7+emQJssoNWrh+N iL9trwbpEg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Vb74X6mc2H0e6MLiEAhBKZ84QSTgHhg3aAfwLeb5H8AGScZ7UqNDKDmI5IhuJ/LPpdHQCtOent5+ I1p5tELHTH0LzN6BILTKGZBdaGJ2AKKoofyljqaR51srCF/ZJLUOrn1XUZMkdlutYXGikghh+zK5 6+/HFEYyz6zhpfFGpAE= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block DYkUg37UnVRJ+X5v5iFDmCWObMw/mUCrJuxa/Cr9wGl4FgcJi6OQesLI1M+aH7+emQJssoNWrh+N iL9trwbpEg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Vb74X6mc2H0e6MLiEAhBKZ84QSTgHhg3aAfwLeb5H8AGScZ7UqNDKDmI5IhuJ/LPpdHQCtOent5+ I1p5tELHTH0LzN6BILTKGZBdaGJ2AKKoofyljqaR51srCF/ZJLUOrn1XUZMkdlutYXGikghh+zK5 6+/HFEYyz6zhpfFGpAE= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block DUY8u9eRLqeXCDG4E2/8OtDIacK06AysbSio1XfMMKnofNQFNkb8eAjngrn4u/YZ6G16ZNMG7YoY jk2Rx2Q3M5GrNkHLNcW1r1FM93KBIPYna3s3UsOdPXI8u/gdrTwtTwv/xpFT5pO5KUummozg1ol2 CfVK4phP0ptL6RF00qSF6IA3NotRdVSf39i8Abyti2fNqAeVQtQbe8y1/1WV9RrHHqEjarv5sqIY 6GslwJ8wdJjPL0QS11gBEh6rDpndqUhWIIFTUrFMd1tEU2WzUCNSxtbBPYlWfpU8e4/l9e5xSsF6 weW3wzZvwjgR473vdWcupdpbpXFjQjfOA39+/w== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block p0GGQgjzPW+6PIUsMdZXTQnjW6BUopNyvt7ApHmGMwjrt0lKkYFdeq6NnHPNeKi9xrrloGAO2Tha FhPoK1WSUQvFoRR4uKVUk0OywXYhciTgYL90XL5T7z6pvP+T2xdoDnAiUPoqzH/Ubhhi84EoGyo2 +zIDCCcTvvnznOBjfpk= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block m1/kaqW4ETEcDTOeEJMS5yQHRelnhe+7sXgpcKiP6lTf8NZHj87LtgfMx1Oh7TGMtL3OsgLwXKl5 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block DYkUg37UnVRJ+X5v5iFDmCWObMw/mUCrJuxa/Cr9wGl4FgcJi6OQesLI1M+aH7+emQJssoNWrh+N iL9trwbpEg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Vb74X6mc2H0e6MLiEAhBKZ84QSTgHhg3aAfwLeb5H8AGScZ7UqNDKDmI5IhuJ/LPpdHQCtOent5+ I1p5tELHTH0LzN6BILTKGZBdaGJ2AKKoofyljqaR51srCF/ZJLUOrn1XUZMkdlutYXGikghh+zK5 6+/HFEYyz6zhpfFGpAE= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block DYkUg37UnVRJ+X5v5iFDmCWObMw/mUCrJuxa/Cr9wGl4FgcJi6OQesLI1M+aH7+emQJssoNWrh+N iL9trwbpEg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Vb74X6mc2H0e6MLiEAhBKZ84QSTgHhg3aAfwLeb5H8AGScZ7UqNDKDmI5IhuJ/LPpdHQCtOent5+ I1p5tELHTH0LzN6BILTKGZBdaGJ2AKKoofyljqaR51srCF/ZJLUOrn1XUZMkdlutYXGikghh+zK5 6+/HFEYyz6zhpfFGpAE= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block DYkUg37UnVRJ+X5v5iFDmCWObMw/mUCrJuxa/Cr9wGl4FgcJi6OQesLI1M+aH7+emQJssoNWrh+N iL9trwbpEg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Vb74X6mc2H0e6MLiEAhBKZ84QSTgHhg3aAfwLeb5H8AGScZ7UqNDKDmI5IhuJ/LPpdHQCtOent5+ I1p5tELHTH0LzN6BILTKGZBdaGJ2AKKoofyljqaR51srCF/ZJLUOrn1XUZMkdlutYXGikghh+zK5 6+/HFEYyz6zhpfFGpAE= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block DYkUg37UnVRJ+X5v5iFDmCWObMw/mUCrJuxa/Cr9wGl4FgcJi6OQesLI1M+aH7+emQJssoNWrh+N iL9trwbpEg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Vb74X6mc2H0e6MLiEAhBKZ84QSTgHhg3aAfwLeb5H8AGScZ7UqNDKDmI5IhuJ/LPpdHQCtOent5+ I1p5tELHTH0LzN6BILTKGZBdaGJ2AKKoofyljqaR51srCF/ZJLUOrn1XUZMkdlutYXGikghh+zK5 6+/HFEYyz6zhpfFGpAE= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2013" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block DYkUg37UnVRJ+X5v5iFDmCWObMw/mUCrJuxa/Cr9wGl4FgcJi6OQesLI1M+aH7+emQJssoNWrh+N iL9trwbpEg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block Vb74X6mc2H0e6MLiEAhBKZ84QSTgHhg3aAfwLeb5H8AGScZ7UqNDKDmI5IhuJ/LPpdHQCtOent5+ I1p5tELHTH0LzN6BILTKGZBdaGJ2AKKoofyljqaR51srCF/ZJLUOrn1XUZMkdlutYXGikghh+zK5 6+/HFEYyz6zhpfFGpAE= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 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-- The MIT License (MIT) -- -- Copyright (c) 2013 Michael Lancaster -- -- Permission is hereby granted, free of charge, to any person obtaining a copy -- of this software and associated documentation files (the "Software"), to -- deal in the Software without restriction, including without limitation the -- rights to use, copy, modify, merge, publish, distribute, sublicense, and/or -- sell copies of the Software, and to permit persons to whom the Software is -- furnished to do so, subject to the following conditions: -- -- The above copyright notice and this permission notice shall be included in -- all copies or substantial portions of the Software. -- -- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS -- IN THE SOFTWARE. -- SMT full adder -- Michael Lancaster <[email protected]> -- 4 October 2013 library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity smt_full_adder is Port ( A : in STD_LOGIC; B : in STD_LOGIC; Cin : in STD_LOGIC; Cout : out STD_LOGIC; S : out STD_LOGIC); end smt_full_adder; architecture Behavioral of smt_full_adder is begin S <= A or B or Cin; Cout <= (A and B) or (Cin and (A or B)); end Behavioral;
----------------------------------------------------------------------------- -- LEON3 Demonstration design test bench -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research ------------------------------------------------------------------------------ -- This file is a part of the GRLIB VHDL IP LIBRARY -- Copyright (C) 2003 - 2008, Gaisler Research -- Copyright (C) 2008 - 2013, Aeroflex Gaisler -- -- This program is free software; you can redistribute it and/or modify -- it under the terms of the GNU General Public License as published by -- the Free Software Foundation; either version 2 of the License, or -- (at your option) any later version. -- -- This program is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program; if not, write to the Free Software -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; library gaisler; use gaisler.libdcom.all; use gaisler.sim.all; library techmap; use techmap.gencomp.all; library micron; use micron.components.all; library hynix; use hynix.components.all; use work.debug.all; use work.config.all; library hynix; use hynix.components.all; entity testbench is generic ( fabtech : integer := CFG_FABTECH; memtech : integer := CFG_MEMTECH; padtech : integer := CFG_PADTECH; clktech : integer := CFG_CLKTECH; clkperiod : integer := 10 -- system clock period ); end; architecture behav of testbench is constant promfile : string := "prom.srec"; -- rom contents constant sdramfile : string := "ram.srec"; -- sdram contents constant ct : integer := clkperiod/2; signal clk : std_logic := '0'; signal rst : std_logic := '0'; signal rstn : std_logic; signal error : std_logic; -- PROM flash signal address : std_logic_vector(26 downto 0):=(others =>'0'); signal data : std_logic_vector(31 downto 0); signal RamCE : std_logic; signal oen : std_ulogic; signal writen : std_ulogic; -- Debug support unit signal dsubre : std_ulogic; -- AHB Uart signal dsurx : std_ulogic; signal dsutx : std_ulogic; -- APB Uart signal urxd : std_ulogic; signal utxd : std_ulogic; -- Output signals for LEDs signal led : std_logic_vector(15 downto 0); begin -- clock and reset clk <= not clk after ct * 1 ns; rst <= '1', '0' after 100 ns; rstn <= not rst; dsubre <= '0'; urxd <= 'H'; d3 : entity work.leon3mp generic map (fabtech, memtech, padtech, clktech) port map ( clk => clk, btnCpuResetn => rstn, -- PROM address => address(22 downto 0), data => data(31 downto 16), RamOE => oen, RamWE => writen, RamCE => RamCE, -- AHB Uart RsRx => dsurx, RsTx => dsutx, -- Output signals for LEDs led => led ); sram0 : sram generic map (index => 4, abits => 24, fname => sdramfile) port map (address(23 downto 0), data(31 downto 24), RamCE, writen, oen); sram1 : sram generic map (index => 5, abits => 24, fname => sdramfile) port map (address(23 downto 0), data(23 downto 16), RamCE, writen, oen); led(3) <= 'L'; -- ERROR pull-down error <= not led(3); iuerr : process begin wait for 5 us; assert (to_X01(error) = '1') report "*** IU in error mode, simulation halted ***" severity failure; end process; data <= buskeep(data) after 5 ns; end;
-------------------------------------------------------------------------------- -- -- BLK MEM GEN v7_3 Core - Stimulus Generator For TDP -- -------------------------------------------------------------------------------- -- -- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -------------------------------------------------------------------------------- -- -- Filename: bmg_stim_gen.vhd -- -- Description: -- Stimulus Generation For TDP -- 100 Writes and 100 Reads will be performed in a repeatitive loop till the -- simulation ends -- -------------------------------------------------------------------------------- -- Author: IP Solutions Division -- -- History: Sep 12, 2011 - First Release -------------------------------------------------------------------------------- -- -------------------------------------------------------------------------------- -- Library Declarations -------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_MISC.ALL; LIBRARY work; USE work.ALL; USE work.BMG_TB_PKG.ALL; ENTITY REGISTER_LOGIC_TDP IS PORT( Q : OUT STD_LOGIC; CLK : IN STD_LOGIC; RST : IN STD_LOGIC; D : IN STD_LOGIC ); END REGISTER_LOGIC_TDP; ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_TDP IS SIGNAL Q_O : STD_LOGIC :='0'; BEGIN Q <= Q_O; FF_BEH: PROCESS(CLK) BEGIN IF(RISING_EDGE(CLK)) THEN IF(RST ='1') THEN Q_O <= '0'; ELSE Q_O <= D; END IF; END IF; END PROCESS; END REGISTER_ARCH; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; --USE IEEE.NUMERIC_STD.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_MISC.ALL; LIBRARY work; USE work.ALL; USE work.BMG_TB_PKG.ALL; ENTITY BMG_STIM_GEN IS PORT ( CLKA : IN STD_LOGIC; CLKB : IN STD_LOGIC; TB_RST : IN STD_LOGIC; ADDRA : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); DINA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); ENA : OUT STD_LOGIC :='0'; WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0'); WEB : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0'); ADDRB : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); DINB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); ENB : OUT STD_LOGIC :='0'; CHECK_DATA: OUT STD_LOGIC_VECTOR(1 DOWNTO 0):=(OTHERS => '0') ); END BMG_STIM_GEN; ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); CONSTANT ADDR_ZERO : STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); CONSTANT DATA_PART_CNT_A : INTEGER:= DIVROUNDUP(8,8); CONSTANT DATA_PART_CNT_B : INTEGER:= DIVROUNDUP(8,8); SIGNAL WRITE_ADDR_A : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); SIGNAL WRITE_ADDR_B : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); SIGNAL WRITE_ADDR_INT_A : STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); SIGNAL READ_ADDR_INT_A : STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); SIGNAL WRITE_ADDR_INT_B : STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); SIGNAL READ_ADDR_INT_B : STD_LOGIC_VECTOR(2 DOWNTO 0) := (OTHERS => '0'); SIGNAL READ_ADDR_A : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); SIGNAL READ_ADDR_B : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); SIGNAL DINA_INT : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); SIGNAL DINB_INT : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); SIGNAL MAX_COUNT : STD_LOGIC_VECTOR(10 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(8,11); SIGNAL DO_WRITE_A : STD_LOGIC := '0'; SIGNAL DO_READ_A : STD_LOGIC := '0'; SIGNAL DO_WRITE_B : STD_LOGIC := '0'; SIGNAL DO_READ_B : STD_LOGIC := '0'; SIGNAL COUNT_NO : STD_LOGIC_VECTOR (10 DOWNTO 0):=(OTHERS => '0'); SIGNAL DO_READ_RA : STD_LOGIC := '0'; SIGNAL DO_READ_RB : STD_LOGIC := '0'; SIGNAL DO_READ_REG_A: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0'); SIGNAL DO_READ_REG_B: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0'); SIGNAL COUNT : integer := 0; SIGNAL COUNT_B : integer := 0; CONSTANT WRITE_CNT_A : integer := 6; CONSTANT READ_CNT_A : integer := 6; CONSTANT WRITE_CNT_B : integer := 4; CONSTANT READ_CNT_B : integer := 4; signal porta_wr_rd : std_logic:='0'; signal portb_wr_rd : std_logic:='0'; signal porta_wr_rd_complete: std_logic:='0'; signal portb_wr_rd_complete: std_logic:='0'; signal incr_cnt : std_logic :='0'; signal incr_cnt_b : std_logic :='0'; SIGNAL PORTB_WR_RD_HAPPENED: STD_LOGIC :='0'; SIGNAL LATCH_PORTA_WR_RD_COMPLETE : STD_LOGIC :='0'; SIGNAL PORTA_WR_RD_L1 :STD_LOGIC :='0'; SIGNAL PORTA_WR_RD_L2 :STD_LOGIC :='0'; SIGNAL PORTB_WR_RD_R1 :STD_LOGIC :='0'; SIGNAL PORTB_WR_RD_R2 :STD_LOGIC :='0'; SIGNAL PORTA_WR_RD_HAPPENED: STD_LOGIC :='0'; SIGNAL LATCH_PORTB_WR_RD_COMPLETE : STD_LOGIC :='0'; SIGNAL PORTB_WR_RD_L1 :STD_LOGIC :='0'; SIGNAL PORTB_WR_RD_L2 :STD_LOGIC :='0'; SIGNAL PORTA_WR_RD_R1 :STD_LOGIC :='0'; SIGNAL PORTA_WR_RD_R2 :STD_LOGIC :='0'; BEGIN WRITE_ADDR_INT_A(2 DOWNTO 0) <= WRITE_ADDR_A(2 DOWNTO 0); READ_ADDR_INT_A(2 DOWNTO 0) <= READ_ADDR_A(2 DOWNTO 0); ADDRA <= IF_THEN_ELSE(DO_WRITE_A='1',WRITE_ADDR_INT_A,READ_ADDR_INT_A) ; WRITE_ADDR_INT_B(2 DOWNTO 0) <= WRITE_ADDR_B(2 DOWNTO 0); --To avoid collision during idle period, negating the read_addr of port A READ_ADDR_INT_B(2 DOWNTO 0) <= IF_THEN_ELSE( (DO_WRITE_B='0' AND DO_READ_B='0'),ADDR_ZERO,READ_ADDR_B(2 DOWNTO 0)); ADDRB <= IF_THEN_ELSE(DO_WRITE_B='1',WRITE_ADDR_INT_B,READ_ADDR_INT_B) ; DINA <= DINA_INT ; DINB <= DINB_INT ; CHECK_DATA(0) <= DO_READ_A; CHECK_DATA(1) <= DO_READ_B; RD_ADDR_GEN_INST_A:ENTITY work.ADDR_GEN GENERIC MAP( C_MAX_DEPTH => 8, RST_INC => 1 ) PORT MAP( CLK => CLKA, RST => TB_RST, EN => DO_READ_A, LOAD => '0', LOAD_VALUE => ZERO, ADDR_OUT => READ_ADDR_A ); WR_ADDR_GEN_INST_A:ENTITY work.ADDR_GEN GENERIC MAP( C_MAX_DEPTH =>8 , RST_INC => 1 ) PORT MAP( CLK => CLKA, RST => TB_RST, EN => DO_WRITE_A, LOAD => '0', LOAD_VALUE => ZERO, ADDR_OUT => WRITE_ADDR_A ); RD_ADDR_GEN_INST_B:ENTITY work.ADDR_GEN GENERIC MAP( C_MAX_DEPTH => 8 , RST_INC => 1 ) PORT MAP( CLK => CLKB, RST => TB_RST, EN => DO_READ_B, LOAD => '0', LOAD_VALUE => ZERO, ADDR_OUT => READ_ADDR_B ); WR_ADDR_GEN_INST_B:ENTITY work.ADDR_GEN GENERIC MAP( C_MAX_DEPTH => 8 , RST_INC => 1 ) PORT MAP( CLK => CLKB, RST => TB_RST, EN => DO_WRITE_B, LOAD => '0', LOAD_VALUE => ZERO, ADDR_OUT => WRITE_ADDR_B ); WR_DATA_GEN_INST_A:ENTITY work.DATA_GEN GENERIC MAP ( DATA_GEN_WIDTH =>8, DOUT_WIDTH => 8, DATA_PART_CNT => 1, SEED => 2) PORT MAP ( CLK =>CLKA, RST => TB_RST, EN => DO_WRITE_A, DATA_OUT => DINA_INT ); WR_DATA_GEN_INST_B:ENTITY work.DATA_GEN GENERIC MAP ( DATA_GEN_WIDTH =>8, DOUT_WIDTH =>8 , DATA_PART_CNT =>1, SEED => 2) PORT MAP ( CLK =>CLKB, RST => TB_RST, EN => DO_WRITE_B, DATA_OUT => DINB_INT ); PROCESS(CLKB) BEGIN IF(RISING_EDGE(CLKB)) THEN IF(TB_RST='1') THEN LATCH_PORTB_WR_RD_COMPLETE<='0'; ELSIF(PORTB_WR_RD_COMPLETE='1') THEN LATCH_PORTB_WR_RD_COMPLETE <='1'; ELSIF(PORTA_WR_RD_HAPPENED='1') THEN LATCH_PORTB_WR_RD_COMPLETE<='0'; END IF; END IF; END PROCESS; PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(TB_RST='1') THEN PORTB_WR_RD_L1 <='0'; PORTB_WR_RD_L2 <='0'; ELSE PORTB_WR_RD_L1 <= LATCH_PORTB_WR_RD_COMPLETE; PORTB_WR_RD_L2 <= PORTB_WR_RD_L1; END IF; END IF; END PROCESS; PORTA_WR_RD_EN: PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(TB_RST='1') THEN PORTA_WR_RD <='1'; ELSE PORTA_WR_RD <= PORTB_WR_RD_L2; END IF; END IF; END PROCESS; PROCESS(CLKB) BEGIN IF(RISING_EDGE(CLKB)) THEN IF(TB_RST='1') THEN PORTA_WR_RD_R1 <='0'; PORTA_WR_RD_R2 <='0'; ELSE PORTA_WR_RD_R1 <=PORTA_WR_RD; PORTA_WR_RD_R2 <=PORTA_WR_RD_R1; END IF; END IF; END PROCESS; PORTA_WR_RD_HAPPENED <= PORTA_WR_RD_R2; PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(TB_RST='1') THEN LATCH_PORTA_WR_RD_COMPLETE<='0'; ELSIF(PORTA_WR_RD_COMPLETE='1') THEN LATCH_PORTA_WR_RD_COMPLETE <='1'; ELSIF(PORTB_WR_RD_HAPPENED='1') THEN LATCH_PORTA_WR_RD_COMPLETE<='0'; END IF; END IF; END PROCESS; PROCESS(CLKB) BEGIN IF(RISING_EDGE(CLKB)) THEN IF(TB_RST='1') THEN PORTA_WR_RD_L1 <='0'; PORTA_WR_RD_L2 <='0'; ELSE PORTA_WR_RD_L1 <= LATCH_PORTA_WR_RD_COMPLETE; PORTA_WR_RD_L2 <= PORTA_WR_RD_L1; END IF; END IF; END PROCESS; PORTB_EN: PROCESS(CLKB) BEGIN IF(RISING_EDGE(CLKB)) THEN IF(TB_RST='1') THEN PORTB_WR_RD <='0'; ELSE PORTB_WR_RD <= PORTA_WR_RD_L2; END IF; END IF; END PROCESS; PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(TB_RST='1') THEN PORTB_WR_RD_R1 <='0'; PORTB_WR_RD_R2 <='0'; ELSE PORTB_WR_RD_R1 <=PORTB_WR_RD; PORTB_WR_RD_R2 <=PORTB_WR_RD_R1; END IF; END IF; END PROCESS; ---double registered of porta complete on portb clk PORTB_WR_RD_HAPPENED <= PORTB_WR_RD_R2; PORTA_WR_RD_COMPLETE <= '1' when count=(WRITE_CNT_A+READ_CNT_A) else '0'; start_counter: process(clka) begin if(rising_edge(clka)) then if(TB_RST='1') then incr_cnt <= '0'; elsif(porta_wr_rd ='1') then incr_cnt <='1'; elsif(porta_wr_rd_complete='1') then incr_cnt <='0'; end if; end if; end process; COUNTER: process(clka) begin if(rising_edge(clka)) then if(TB_RST='1') then count <= 0; elsif(incr_cnt='1') then count<=count+1; end if; if(count=(WRITE_CNT_A+READ_CNT_A)) then count<=0; end if; end if; end process; DO_WRITE_A<='1' when (count <WRITE_CNT_A and incr_cnt='1') else '0'; DO_READ_A <='1' when (count >WRITE_CNT_A and incr_cnt='1') else '0'; PORTB_WR_RD_COMPLETE <= '1' when count_b=(WRITE_CNT_B+READ_CNT_B) else '0'; startb_counter: process(clkb) begin if(rising_edge(clkb)) then if(TB_RST='1') then incr_cnt_b <= '0'; elsif(portb_wr_rd ='1') then incr_cnt_b <='1'; elsif(portb_wr_rd_complete='1') then incr_cnt_b <='0'; end if; end if; end process; COUNTER_B: process(clkb) begin if(rising_edge(clkb)) then if(TB_RST='1') then count_b <= 0; elsif(incr_cnt_b='1') then count_b<=count_b+1; end if; if(count_b=WRITE_CNT_B+READ_CNT_B) then count_b<=0; end if; end if; end process; DO_WRITE_B<='1' when (count_b <WRITE_CNT_B and incr_cnt_b='1') else '0'; DO_READ_B <='1' when (count_b >WRITE_CNT_B and incr_cnt_b='1') else '0'; BEGIN_SHIFT_REG_A: FOR I IN 0 TO 4 GENERATE BEGIN DFF_RIGHT: IF I=0 GENERATE BEGIN SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_TDP PORT MAP( Q => DO_READ_REG_A(0), CLK =>CLKA, RST=>TB_RST, D =>DO_READ_A ); END GENERATE DFF_RIGHT; DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE BEGIN SHIFT_INST: ENTITY work.REGISTER_LOGIC_TDP PORT MAP( Q => DO_READ_REG_A(I), CLK =>CLKA, RST=>TB_RST, D =>DO_READ_REG_A(I-1) ); END GENERATE DFF_OTHERS; END GENERATE BEGIN_SHIFT_REG_A; BEGIN_SHIFT_REG_B: FOR I IN 0 TO 4 GENERATE BEGIN DFF_RIGHT: IF I=0 GENERATE BEGIN SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_TDP PORT MAP( Q => DO_READ_REG_B(0), CLK =>CLKB, RST=>TB_RST, D =>DO_READ_B ); END GENERATE DFF_RIGHT; DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE BEGIN SHIFT_INST: ENTITY work.REGISTER_LOGIC_TDP PORT MAP( Q => DO_READ_REG_B(I), CLK =>CLKB, RST=>TB_RST, D =>DO_READ_REG_B(I-1) ); END GENERATE DFF_OTHERS; END GENERATE BEGIN_SHIFT_REG_B; REGCEA_PROCESS: PROCESS(CLKA) BEGIN IF(RISING_EDGE(CLKA)) THEN IF(TB_RST='1') THEN DO_READ_RA <= '0'; ELSE DO_READ_RA <= DO_READ_A; END IF; END IF; END PROCESS; REGCEB_PROCESS: PROCESS(CLKB) BEGIN IF(RISING_EDGE(CLKB)) THEN IF(TB_RST='1') THEN DO_READ_RB <= '0'; ELSE DO_READ_RB <= DO_READ_B; END IF; END IF; END PROCESS; ---REGCEB SHOULD BE SET AT THE CORE OUTPUT REGISTER/EMBEEDED OUTPUT REGISTER --- WHEN CORE OUTPUT REGISTER IS SET REGCE SHOUD BE SET TO '1' WHEN THE READ DATA IS AVAILABLE AT THE CORE OUTPUT REGISTER --WHEN CORE OUTPUT REGISTER IS '0' AND OUTPUT_PRIMITIVE_REG ='1', REGCE SHOULD BE SET WHEN THE DATA IS AVAILABLE AT THE PRIMITIVE OUTPUT REGISTER. -- HERE, TO GENERAILIZE REGCE IS ASSERTED ENA <= DO_READ_A OR DO_WRITE_A ; ENB <= DO_READ_B OR DO_WRITE_B ; WEA(0) <= IF_THEN_ELSE(DO_WRITE_A='1','1','0') ; WEB(0) <= IF_THEN_ELSE(DO_WRITE_B='1','1','0') ; END ARCHITECTURE;
---------------------------------------------------------------------------------- -- Company: UNIVERSITY OF MASSACHUSETTS - DARTMOUTH -- Engineer: CHRISTOPHER PARKS ([email protected]) -- -- Create Date: 15:33:22 03/11/2016 -- Module Name: PipelineRegisters - Behavioral -- Target Devices: SPARTAN XC3S500E -- Description: REGISTERS TO BE USED AS A PIPELINE REGISTER -- -- Dependencies: IEEE.STD_LOGIC_1164 -- -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity PipelineRegisters is Port ( Clk : in STD_LOGIC; -- Clock Ena : in STD_LOGIC; -- Enable Rst : in STD_LOGIC; -- Reset line Din : in STD_LOGIC_VECTOR (15 downto 0); -- Data in Dout : out STD_LOGIC_VECTOR (15 downto 0)); -- Data out end PipelineRegisters; architecture Behavioral of PipelineRegisters is signal DataOutSignal : STD_LOGIC_VECTOR(15 DOWNTO 0) := (others=>'0'); -- Use a signal that always begins at 0 to ensure safe states begin BehavioralProcess: process(Clk, Rst) begin if(rising_edge(Clk) and Ena = '1') then DataOutSignal <= Din; Dout <= DataOutSignal; -- Update data out end if; if(Rst = '1' and Ena = '1') then -- If the reset line has been driven high, reset the data out. Dout <= (others=>'0'); -- Set data out to all zeroes end if; end process; end Behavioral;
---------------------------------------------------------------------------------- -- Company: UNIVERSITY OF MASSACHUSETTS - DARTMOUTH -- Engineer: CHRISTOPHER PARKS ([email protected]) -- -- Create Date: 15:33:22 03/11/2016 -- Module Name: PipelineRegisters - Behavioral -- Target Devices: SPARTAN XC3S500E -- Description: REGISTERS TO BE USED AS A PIPELINE REGISTER -- -- Dependencies: IEEE.STD_LOGIC_1164 -- -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity PipelineRegisters is Port ( Clk : in STD_LOGIC; -- Clock Ena : in STD_LOGIC; -- Enable Rst : in STD_LOGIC; -- Reset line Din : in STD_LOGIC_VECTOR (15 downto 0); -- Data in Dout : out STD_LOGIC_VECTOR (15 downto 0)); -- Data out end PipelineRegisters; architecture Behavioral of PipelineRegisters is signal DataOutSignal : STD_LOGIC_VECTOR(15 DOWNTO 0) := (others=>'0'); -- Use a signal that always begins at 0 to ensure safe states begin BehavioralProcess: process(Clk, Rst) begin if(rising_edge(Clk) and Ena = '1') then DataOutSignal <= Din; Dout <= DataOutSignal; -- Update data out end if; if(Rst = '1' and Ena = '1') then -- If the reset line has been driven high, reset the data out. Dout <= (others=>'0'); -- Set data out to all zeroes end if; end process; end Behavioral;
---------------------------------------------------------------------------------- -- Company: UNIVERSITY OF MASSACHUSETTS - DARTMOUTH -- Engineer: CHRISTOPHER PARKS ([email protected]) -- -- Create Date: 15:33:22 03/11/2016 -- Module Name: PipelineRegisters - Behavioral -- Target Devices: SPARTAN XC3S500E -- Description: REGISTERS TO BE USED AS A PIPELINE REGISTER -- -- Dependencies: IEEE.STD_LOGIC_1164 -- -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity PipelineRegisters is Port ( Clk : in STD_LOGIC; -- Clock Ena : in STD_LOGIC; -- Enable Rst : in STD_LOGIC; -- Reset line Din : in STD_LOGIC_VECTOR (15 downto 0); -- Data in Dout : out STD_LOGIC_VECTOR (15 downto 0)); -- Data out end PipelineRegisters; architecture Behavioral of PipelineRegisters is signal DataOutSignal : STD_LOGIC_VECTOR(15 DOWNTO 0) := (others=>'0'); -- Use a signal that always begins at 0 to ensure safe states begin BehavioralProcess: process(Clk, Rst) begin if(rising_edge(Clk) and Ena = '1') then DataOutSignal <= Din; Dout <= DataOutSignal; -- Update data out end if; if(Rst = '1' and Ena = '1') then -- If the reset line has been driven high, reset the data out. Dout <= (others=>'0'); -- Set data out to all zeroes end if; end process; end Behavioral;
---------------------------------------------------------------------------------- -- Company: UNIVERSITY OF MASSACHUSETTS - DARTMOUTH -- Engineer: CHRISTOPHER PARKS ([email protected]) -- -- Create Date: 15:33:22 03/11/2016 -- Module Name: PipelineRegisters - Behavioral -- Target Devices: SPARTAN XC3S500E -- Description: REGISTERS TO BE USED AS A PIPELINE REGISTER -- -- Dependencies: IEEE.STD_LOGIC_1164 -- -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity PipelineRegisters is Port ( Clk : in STD_LOGIC; -- Clock Ena : in STD_LOGIC; -- Enable Rst : in STD_LOGIC; -- Reset line Din : in STD_LOGIC_VECTOR (15 downto 0); -- Data in Dout : out STD_LOGIC_VECTOR (15 downto 0)); -- Data out end PipelineRegisters; architecture Behavioral of PipelineRegisters is signal DataOutSignal : STD_LOGIC_VECTOR(15 DOWNTO 0) := (others=>'0'); -- Use a signal that always begins at 0 to ensure safe states begin BehavioralProcess: process(Clk, Rst) begin if(rising_edge(Clk) and Ena = '1') then DataOutSignal <= Din; Dout <= DataOutSignal; -- Update data out end if; if(Rst = '1' and Ena = '1') then -- If the reset line has been driven high, reset the data out. Dout <= (others=>'0'); -- Set data out to all zeroes end if; end process; end Behavioral;
---------------------------------------------------------------------------------- -- Company: UNIVERSITY OF MASSACHUSETTS - DARTMOUTH -- Engineer: CHRISTOPHER PARKS ([email protected]) -- -- Create Date: 15:33:22 03/11/2016 -- Module Name: PipelineRegisters - Behavioral -- Target Devices: SPARTAN XC3S500E -- Description: REGISTERS TO BE USED AS A PIPELINE REGISTER -- -- Dependencies: IEEE.STD_LOGIC_1164 -- -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity PipelineRegisters is Port ( Clk : in STD_LOGIC; -- Clock Ena : in STD_LOGIC; -- Enable Rst : in STD_LOGIC; -- Reset line Din : in STD_LOGIC_VECTOR (15 downto 0); -- Data in Dout : out STD_LOGIC_VECTOR (15 downto 0)); -- Data out end PipelineRegisters; architecture Behavioral of PipelineRegisters is signal DataOutSignal : STD_LOGIC_VECTOR(15 DOWNTO 0) := (others=>'0'); -- Use a signal that always begins at 0 to ensure safe states begin BehavioralProcess: process(Clk, Rst) begin if(rising_edge(Clk) and Ena = '1') then DataOutSignal <= Din; Dout <= DataOutSignal; -- Update data out end if; if(Rst = '1' and Ena = '1') then -- If the reset line has been driven high, reset the data out. Dout <= (others=>'0'); -- Set data out to all zeroes end if; end process; end Behavioral;
-- Revision history: -- 2015-08-12 Lukas Jaeger created library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library WORK; use WORK.all; entity control_pipeline is port( clk : in std_logic; rst : in std_logic; rd_mask : out std_logic_vector(3 downto 0); wr_mask : out std_logic_vector(3 downto 0); instr_stall : in std_logic; data_stall : in std_logic; instr_in : in std_logic_vector(31 downto 0); alu_op : out std_logic_vector(5 downto 0); exc_mux1 : out std_logic_vector(1 downto 0); exc_mux2 : out std_logic_vector(1 downto 0); exc_alu_zero : in std_logic_vector(0 downto 0); memstg_mux : out std_logic; id_regdest_mux : out std_logic_vector (1 downto 0); id_regshift_mux : out std_logic_vector (1 downto 0); id_enable_regs : out std_logic; in_mux_pc : out std_logic; stage_control : out std_logic_vector (4 downto 0) ); end entity control_pipeline; architecture behavioural of control_pipeline is signal instr_1, instr_2, instr_3, instr_4: std_logic_vector (31 downto 0); begin pipeline: process(clk, rst) is begin if (rst = '1') then instr_1 <= x"00000000"; instr_2 <= x"00000000"; instr_3 <= x"00000000"; instr_4 <= x"00000000"; stage_control <= "11111"; elsif (rising_edge(clk)) then instr_1 <= instr_in; instr_2 <= instr_1; instr_3 <= instr_2; instr_4 <= instr_3; end if; end process; id: process (instr_1) is begin if (instr_1(31 downto 26) = "000000") then -- R-type instructions id_regdest_mux <= "00"; id_regshift_mux <= "00"; if (instr_1(20 downto 0) = "000000000000000001000") then -- JR-instruction in_mux_pc <= '1'; else in_mux_pc <= '0'; end if; else -- I-Type- and J-Type instructions. They can go together, because nobody cares about -- the alu-result of a J-Type, so it does not matter, which value is yielded to ex id_regdest_mux <= "10"; if (instr_1(31 downto 26) = "001111") then -- LUI needs a shift id_regshift_mux <= "01"; in_mux_pc <= '0'; elsif ((instr_1(31 downto 26) = "000010") -- J or (instr_1 (31 downto 26) = "000011") -- JAL or (instr_1 (31 downto 26) = "011101") -- JALX or (instr_1 (31 downto 26) = "000100") -- BEQ or (instr_1 (31 downto 26) = "000001") -- BGEZ or (instr_1 (31 downto 26) = "000111") -- BGTZ or (instr_1 (31 downto 26) = "000110") -- BLEZ or (instr_1 (31 downto 26) = "000101") -- BEQZ ) then id_regshift_mux <= "00"; in_mux_pc <= '1'; else id_regshift_mux <= "00"; in_mux_pc <= '0'; end if; end if; end process; ex: process (instr_2) is begin if (instr_2 (31 downto 26) = "001111") then --LUI exc_mux1 <= "00"; exc_mux2 <= "01"; alu_op <="000100"; elsif ((instr_2 (31 downto 26) = "001001") --ADDIU or (instr_2 (31 downto 26) = "100011") --LW or (instr_2 (31 downto 26) = "101011") --SW or (instr_2 (31 downto 26) = "101000") --SB or (instr_2 (31 downto 26) = "100100") --LBU )then exc_mux1 <="10"; exc_mux2 <="01"; alu_op <="100000"; elsif (instr_2 (31 downto 26) = "001010") then --SLTI exc_mux1 <="10"; exc_mux2 <="01"; alu_op <="001000"; elsif (instr_2 (31 downto 26) = "001100") then --ANDI exc_mux1 <="10"; exc_mux2 <="01"; alu_op <="100100"; else --if (instr_2 (31 downto 26) = "000000") then -- NOP and other R-types and Ops, where the result does not matter exc_mux1 <= "10"; exc_mux2 <= "00"; alu_op <= "000100"; end if; end process; mem: process (instr_3) is begin if (instr_3 (31 downto 26) = "100011") then --LW memstg_mux <= '1'; rd_mask <= "1111"; wr_mask <= "0000"; elsif (instr_3 (31 downto 26) = "100100") then --LBU memstg_mux <= '1'; rd_mask <= "0001"; wr_mask <= "0000"; elsif (instr_3 (31 downto 26) = "101011") then --SW memstg_mux <= '0'; rd_mask <= "0000"; wr_mask <= "1111"; elsif (instr_3 (31 downto 26) = "101000") then --SB memstg_mux <= '0'; rd_mask <= "0000"; wr_mask <= "0001"; else memstg_mux <= '0'; rd_mask <= "0000"; wr_mask <= "0000"; end if; end process; wb: process (instr_4) is begin if ((instr_4 (31 downto 26) = "001111") or --LUI (instr_4 (31 downto 26) = "001001") or --ADDIU (instr_4 (31 downto 26) = "100011") or --LW (instr_4 (31 downto 26) = "100100") or --LBU (instr_4 (31 downto 26) = "001010") or --SLTI (instr_4 (31 downto 26) = "001100") --ANDI ) then id_enable_regs <= '1'; else id_enable_regs <= '0'; end if; end process; stall: process (data_stall, instr_stall) is begin if (data_stall = '1' or instr_stall = '1') then stage_control <= "00000"; else stage_control <= "11111"; end if; end process; end architecture;
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** ALTERA FLOATING POINT DATAPATH COMPILER *** --*** *** --*** HCC_CASTFTOX.VHD *** --*** *** --*** Function: Cast IEEE754 Single to Internal *** --*** Single *** --*** *** --*** 14/07/07 ML *** --*** *** --*** (c) 2007 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** 06/02/08 - divider mantissa aa to aaff *** --*** 13/07/09 - if zip, then zero '1' in frac *** --*** *** --*** *** --*************************************************** ENTITY hcc_castftox IS GENERIC ( target : integer := 1; -- 0 (internal), 1 (multiplier), 2 (divider) roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1' mantissa : positive := 32; outputpipe : integer := 1 -- 0 no pipe, 1 output always registered ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1); cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); ccsat, cczip : OUT STD_LOGIC ); END hcc_castftox; ARCHITECTURE rtl OF hcc_castftox IS signal zerovec : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1); signal aaff : STD_LOGIC_VECTOR (32 DOWNTO 1); signal ccff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); signal fracnode, fractional : STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal expnode, exponent : STD_LOGIC_VECTOR (10 DOWNTO 1); signal satnode, zipnode : STD_LOGIC; signal satff, zipff : STD_LOGIC; BEGIN -- ieee754: sign (32), 8 exponent (31:24), 23 mantissa (23:1) -- x format: (signx5,!sign,mantissa XOR sign, sign(xx.xx)), exponent(10:1) -- multiplier : (SIGN)('1')(23:1)sign(xx.xx), exponent(10:1) -- divider : "01"(23:1) (00..00),exponent(10:1) (lower mantissa bits ignored by fpdiv1x) gza: IF (roundconvert = 1) GENERATE gza: FOR k IN 1 TO mantissa-1 GENERATE zerovec(k) <= '0'; END GENERATE; END GENERATE; pca: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO 32 LOOP aaff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN aaff <= aa; END IF; END IF; END PROCESS; gro: IF ((target = 0 AND outputpipe = 1) OR (target = 1 AND outputpipe = 1)) GENERATE pca: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO mantissa+10 LOOP ccff(k) <= '0'; END LOOP; satff <= '0'; zipff <= '0'; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN ccff <= fractional & exponent; satff <= satnode; zipff <= zipnode; END IF; END IF; END PROCESS; END GENERATE; -- if exponent = 255 => saturate, if 0 => 0 satnode <= aaff(31) AND aaff(30) AND aaff(29) AND aaff(28) AND aaff(27) AND aaff(26) AND aaff(25) AND aaff(24); zipnode <= NOT(aaff(31) OR aaff(30) OR aaff(29) OR aaff(28) OR aaff(27) OR aaff(26) OR aaff(25) OR aaff(24)); gexpa: FOR k IN 1 TO 8 GENERATE expnode(k) <= (aaff(k+23) OR satnode) AND NOT(zipnode); END GENERATE; expnode(9) <= satnode; expnode(10) <= '0'; --*** internal format *** gxa: IF (target = 0) GENERATE fracnode(mantissa) <= aaff(32); fracnode(mantissa-1) <= aaff(32); fracnode(mantissa-2) <= aaff(32); fracnode(mantissa-3) <= aaff(32); fracnode(mantissa-4) <= aaff(32); --fracnode(mantissa-5) <= NOT(aaff(32)); -- '1' XOR sign -- 13/07/09 fracnode(mantissa-5) <= aaff(32) XOR NOT(zipnode); -- '1' XOR sign gxb: FOR k IN 1 TO 23 GENERATE fracnode(mantissa-29+k)<= (aaff(k) XOR aaff(32)); END GENERATE; gxc: FOR k IN 1 TO mantissa-29 GENERATE fracnode(k)<= aaff(32); -- '0' XOR sign END GENERATE; gxd: IF (roundconvert = 0) GENERATE fractional <= fracnode; END GENERATE; gxe: IF (roundconvert = 1) GENERATE fractional <= fracnode + (zerovec(mantissa-1) & aaff(32)); END GENERATE; exponent <= expnode; END GENERATE; --*** direct to multiplier *** gma: IF (target = 1) GENERATE fracnode(mantissa) <= aaff(32); --fracnode(mantissa-1) <= NOT(aaff(32)); -- '1' XOR sign -- 13/07/09 fracnode(mantissa-1) <= aaff(32) XOR NOT(zipnode); gmb: FOR k IN 1 TO 23 GENERATE fracnode(mantissa-25+k)<= (aaff(k) XOR aaff(32)); END GENERATE; gmc: FOR k IN 1 TO mantissa-25 GENERATE fracnode(k)<= aaff(32); -- '0' XOR sign END GENERATE; gmd: IF (roundconvert = 0) GENERATE fractional <= fracnode; END GENERATE; gme: IF (roundconvert = 1) GENERATE fractional <= fracnode + (zerovec(mantissa-1) & aaff(32)); END GENERATE; --***??? adjust ??? exponent <= expnode; END GENERATE; -- never register output --*** direct to divider *** gda: IF (target = 2) GENERATE fracnode(mantissa) <= aaff(32); -- 13/07/09 fracnode(mantissa-1) <= '1' AND NOT(zipnode); fracnode(mantissa-2 DOWNTO mantissa-24)<= aaff(23 DOWNTO 1); gfb: FOR k IN 1 TO mantissa-25 GENERATE fracnode(k)<= '0'; END GENERATE; fractional <= fracnode; --***??? adjust ??? exponent <= expnode; END GENERATE; --*** OUTPUTS *** goa: IF ((target = 0 AND outputpipe = 1) OR (target = 1 AND outputpipe = 1)) GENERATE cc <= ccff; ccsat <= satff; cczip <= zipff; END GENERATE; gob: IF ((target = 0 AND outputpipe = 0) OR (target = 1 AND outputpipe = 0) OR (target = 2)) GENERATE cc <= fractional & exponent; ccsat <= satnode; cczip <= zipnode; END GENERATE; END rtl;
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** ALTERA FLOATING POINT DATAPATH COMPILER *** --*** *** --*** HCC_CASTFTOX.VHD *** --*** *** --*** Function: Cast IEEE754 Single to Internal *** --*** Single *** --*** *** --*** 14/07/07 ML *** --*** *** --*** (c) 2007 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** 06/02/08 - divider mantissa aa to aaff *** --*** 13/07/09 - if zip, then zero '1' in frac *** --*** *** --*** *** --*************************************************** ENTITY hcc_castftox IS GENERIC ( target : integer := 1; -- 0 (internal), 1 (multiplier), 2 (divider) roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1' mantissa : positive := 32; outputpipe : integer := 1 -- 0 no pipe, 1 output always registered ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1); cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); ccsat, cczip : OUT STD_LOGIC ); END hcc_castftox; ARCHITECTURE rtl OF hcc_castftox IS signal zerovec : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1); signal aaff : STD_LOGIC_VECTOR (32 DOWNTO 1); signal ccff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); signal fracnode, fractional : STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal expnode, exponent : STD_LOGIC_VECTOR (10 DOWNTO 1); signal satnode, zipnode : STD_LOGIC; signal satff, zipff : STD_LOGIC; BEGIN -- ieee754: sign (32), 8 exponent (31:24), 23 mantissa (23:1) -- x format: (signx5,!sign,mantissa XOR sign, sign(xx.xx)), exponent(10:1) -- multiplier : (SIGN)('1')(23:1)sign(xx.xx), exponent(10:1) -- divider : "01"(23:1) (00..00),exponent(10:1) (lower mantissa bits ignored by fpdiv1x) gza: IF (roundconvert = 1) GENERATE gza: FOR k IN 1 TO mantissa-1 GENERATE zerovec(k) <= '0'; END GENERATE; END GENERATE; pca: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO 32 LOOP aaff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN aaff <= aa; END IF; END IF; END PROCESS; gro: IF ((target = 0 AND outputpipe = 1) OR (target = 1 AND outputpipe = 1)) GENERATE pca: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO mantissa+10 LOOP ccff(k) <= '0'; END LOOP; satff <= '0'; zipff <= '0'; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN ccff <= fractional & exponent; satff <= satnode; zipff <= zipnode; END IF; END IF; END PROCESS; END GENERATE; -- if exponent = 255 => saturate, if 0 => 0 satnode <= aaff(31) AND aaff(30) AND aaff(29) AND aaff(28) AND aaff(27) AND aaff(26) AND aaff(25) AND aaff(24); zipnode <= NOT(aaff(31) OR aaff(30) OR aaff(29) OR aaff(28) OR aaff(27) OR aaff(26) OR aaff(25) OR aaff(24)); gexpa: FOR k IN 1 TO 8 GENERATE expnode(k) <= (aaff(k+23) OR satnode) AND NOT(zipnode); END GENERATE; expnode(9) <= satnode; expnode(10) <= '0'; --*** internal format *** gxa: IF (target = 0) GENERATE fracnode(mantissa) <= aaff(32); fracnode(mantissa-1) <= aaff(32); fracnode(mantissa-2) <= aaff(32); fracnode(mantissa-3) <= aaff(32); fracnode(mantissa-4) <= aaff(32); --fracnode(mantissa-5) <= NOT(aaff(32)); -- '1' XOR sign -- 13/07/09 fracnode(mantissa-5) <= aaff(32) XOR NOT(zipnode); -- '1' XOR sign gxb: FOR k IN 1 TO 23 GENERATE fracnode(mantissa-29+k)<= (aaff(k) XOR aaff(32)); END GENERATE; gxc: FOR k IN 1 TO mantissa-29 GENERATE fracnode(k)<= aaff(32); -- '0' XOR sign END GENERATE; gxd: IF (roundconvert = 0) GENERATE fractional <= fracnode; END GENERATE; gxe: IF (roundconvert = 1) GENERATE fractional <= fracnode + (zerovec(mantissa-1) & aaff(32)); END GENERATE; exponent <= expnode; END GENERATE; --*** direct to multiplier *** gma: IF (target = 1) GENERATE fracnode(mantissa) <= aaff(32); --fracnode(mantissa-1) <= NOT(aaff(32)); -- '1' XOR sign -- 13/07/09 fracnode(mantissa-1) <= aaff(32) XOR NOT(zipnode); gmb: FOR k IN 1 TO 23 GENERATE fracnode(mantissa-25+k)<= (aaff(k) XOR aaff(32)); END GENERATE; gmc: FOR k IN 1 TO mantissa-25 GENERATE fracnode(k)<= aaff(32); -- '0' XOR sign END GENERATE; gmd: IF (roundconvert = 0) GENERATE fractional <= fracnode; END GENERATE; gme: IF (roundconvert = 1) GENERATE fractional <= fracnode + (zerovec(mantissa-1) & aaff(32)); END GENERATE; --***??? adjust ??? exponent <= expnode; END GENERATE; -- never register output --*** direct to divider *** gda: IF (target = 2) GENERATE fracnode(mantissa) <= aaff(32); -- 13/07/09 fracnode(mantissa-1) <= '1' AND NOT(zipnode); fracnode(mantissa-2 DOWNTO mantissa-24)<= aaff(23 DOWNTO 1); gfb: FOR k IN 1 TO mantissa-25 GENERATE fracnode(k)<= '0'; END GENERATE; fractional <= fracnode; --***??? adjust ??? exponent <= expnode; END GENERATE; --*** OUTPUTS *** goa: IF ((target = 0 AND outputpipe = 1) OR (target = 1 AND outputpipe = 1)) GENERATE cc <= ccff; ccsat <= satff; cczip <= zipff; END GENERATE; gob: IF ((target = 0 AND outputpipe = 0) OR (target = 1 AND outputpipe = 0) OR (target = 2)) GENERATE cc <= fractional & exponent; ccsat <= satnode; cczip <= zipnode; END GENERATE; END rtl;
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** ALTERA FLOATING POINT DATAPATH COMPILER *** --*** *** --*** HCC_CASTFTOX.VHD *** --*** *** --*** Function: Cast IEEE754 Single to Internal *** --*** Single *** --*** *** --*** 14/07/07 ML *** --*** *** --*** (c) 2007 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** 06/02/08 - divider mantissa aa to aaff *** --*** 13/07/09 - if zip, then zero '1' in frac *** --*** *** --*** *** --*************************************************** ENTITY hcc_castftox IS GENERIC ( target : integer := 1; -- 0 (internal), 1 (multiplier), 2 (divider) roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1' mantissa : positive := 32; outputpipe : integer := 1 -- 0 no pipe, 1 output always registered ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1); cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); ccsat, cczip : OUT STD_LOGIC ); END hcc_castftox; ARCHITECTURE rtl OF hcc_castftox IS signal zerovec : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1); signal aaff : STD_LOGIC_VECTOR (32 DOWNTO 1); signal ccff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); signal fracnode, fractional : STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal expnode, exponent : STD_LOGIC_VECTOR (10 DOWNTO 1); signal satnode, zipnode : STD_LOGIC; signal satff, zipff : STD_LOGIC; BEGIN -- ieee754: sign (32), 8 exponent (31:24), 23 mantissa (23:1) -- x format: (signx5,!sign,mantissa XOR sign, sign(xx.xx)), exponent(10:1) -- multiplier : (SIGN)('1')(23:1)sign(xx.xx), exponent(10:1) -- divider : "01"(23:1) (00..00),exponent(10:1) (lower mantissa bits ignored by fpdiv1x) gza: IF (roundconvert = 1) GENERATE gza: FOR k IN 1 TO mantissa-1 GENERATE zerovec(k) <= '0'; END GENERATE; END GENERATE; pca: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO 32 LOOP aaff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN aaff <= aa; END IF; END IF; END PROCESS; gro: IF ((target = 0 AND outputpipe = 1) OR (target = 1 AND outputpipe = 1)) GENERATE pca: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO mantissa+10 LOOP ccff(k) <= '0'; END LOOP; satff <= '0'; zipff <= '0'; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN ccff <= fractional & exponent; satff <= satnode; zipff <= zipnode; END IF; END IF; END PROCESS; END GENERATE; -- if exponent = 255 => saturate, if 0 => 0 satnode <= aaff(31) AND aaff(30) AND aaff(29) AND aaff(28) AND aaff(27) AND aaff(26) AND aaff(25) AND aaff(24); zipnode <= NOT(aaff(31) OR aaff(30) OR aaff(29) OR aaff(28) OR aaff(27) OR aaff(26) OR aaff(25) OR aaff(24)); gexpa: FOR k IN 1 TO 8 GENERATE expnode(k) <= (aaff(k+23) OR satnode) AND NOT(zipnode); END GENERATE; expnode(9) <= satnode; expnode(10) <= '0'; --*** internal format *** gxa: IF (target = 0) GENERATE fracnode(mantissa) <= aaff(32); fracnode(mantissa-1) <= aaff(32); fracnode(mantissa-2) <= aaff(32); fracnode(mantissa-3) <= aaff(32); fracnode(mantissa-4) <= aaff(32); --fracnode(mantissa-5) <= NOT(aaff(32)); -- '1' XOR sign -- 13/07/09 fracnode(mantissa-5) <= aaff(32) XOR NOT(zipnode); -- '1' XOR sign gxb: FOR k IN 1 TO 23 GENERATE fracnode(mantissa-29+k)<= (aaff(k) XOR aaff(32)); END GENERATE; gxc: FOR k IN 1 TO mantissa-29 GENERATE fracnode(k)<= aaff(32); -- '0' XOR sign END GENERATE; gxd: IF (roundconvert = 0) GENERATE fractional <= fracnode; END GENERATE; gxe: IF (roundconvert = 1) GENERATE fractional <= fracnode + (zerovec(mantissa-1) & aaff(32)); END GENERATE; exponent <= expnode; END GENERATE; --*** direct to multiplier *** gma: IF (target = 1) GENERATE fracnode(mantissa) <= aaff(32); --fracnode(mantissa-1) <= NOT(aaff(32)); -- '1' XOR sign -- 13/07/09 fracnode(mantissa-1) <= aaff(32) XOR NOT(zipnode); gmb: FOR k IN 1 TO 23 GENERATE fracnode(mantissa-25+k)<= (aaff(k) XOR aaff(32)); END GENERATE; gmc: FOR k IN 1 TO mantissa-25 GENERATE fracnode(k)<= aaff(32); -- '0' XOR sign END GENERATE; gmd: IF (roundconvert = 0) GENERATE fractional <= fracnode; END GENERATE; gme: IF (roundconvert = 1) GENERATE fractional <= fracnode + (zerovec(mantissa-1) & aaff(32)); END GENERATE; --***??? adjust ??? exponent <= expnode; END GENERATE; -- never register output --*** direct to divider *** gda: IF (target = 2) GENERATE fracnode(mantissa) <= aaff(32); -- 13/07/09 fracnode(mantissa-1) <= '1' AND NOT(zipnode); fracnode(mantissa-2 DOWNTO mantissa-24)<= aaff(23 DOWNTO 1); gfb: FOR k IN 1 TO mantissa-25 GENERATE fracnode(k)<= '0'; END GENERATE; fractional <= fracnode; --***??? adjust ??? exponent <= expnode; END GENERATE; --*** OUTPUTS *** goa: IF ((target = 0 AND outputpipe = 1) OR (target = 1 AND outputpipe = 1)) GENERATE cc <= ccff; ccsat <= satff; cczip <= zipff; END GENERATE; gob: IF ((target = 0 AND outputpipe = 0) OR (target = 1 AND outputpipe = 0) OR (target = 2)) GENERATE cc <= fractional & exponent; ccsat <= satnode; cczip <= zipnode; END GENERATE; END rtl;
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** ALTERA FLOATING POINT DATAPATH COMPILER *** --*** *** --*** HCC_CASTFTOX.VHD *** --*** *** --*** Function: Cast IEEE754 Single to Internal *** --*** Single *** --*** *** --*** 14/07/07 ML *** --*** *** --*** (c) 2007 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** 06/02/08 - divider mantissa aa to aaff *** --*** 13/07/09 - if zip, then zero '1' in frac *** --*** *** --*** *** --*************************************************** ENTITY hcc_castftox IS GENERIC ( target : integer := 1; -- 0 (internal), 1 (multiplier), 2 (divider) roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1' mantissa : positive := 32; outputpipe : integer := 1 -- 0 no pipe, 1 output always registered ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1); cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); ccsat, cczip : OUT STD_LOGIC ); END hcc_castftox; ARCHITECTURE rtl OF hcc_castftox IS signal zerovec : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1); signal aaff : STD_LOGIC_VECTOR (32 DOWNTO 1); signal ccff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); signal fracnode, fractional : STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal expnode, exponent : STD_LOGIC_VECTOR (10 DOWNTO 1); signal satnode, zipnode : STD_LOGIC; signal satff, zipff : STD_LOGIC; BEGIN -- ieee754: sign (32), 8 exponent (31:24), 23 mantissa (23:1) -- x format: (signx5,!sign,mantissa XOR sign, sign(xx.xx)), exponent(10:1) -- multiplier : (SIGN)('1')(23:1)sign(xx.xx), exponent(10:1) -- divider : "01"(23:1) (00..00),exponent(10:1) (lower mantissa bits ignored by fpdiv1x) gza: IF (roundconvert = 1) GENERATE gza: FOR k IN 1 TO mantissa-1 GENERATE zerovec(k) <= '0'; END GENERATE; END GENERATE; pca: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO 32 LOOP aaff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN aaff <= aa; END IF; END IF; END PROCESS; gro: IF ((target = 0 AND outputpipe = 1) OR (target = 1 AND outputpipe = 1)) GENERATE pca: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO mantissa+10 LOOP ccff(k) <= '0'; END LOOP; satff <= '0'; zipff <= '0'; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN ccff <= fractional & exponent; satff <= satnode; zipff <= zipnode; END IF; END IF; END PROCESS; END GENERATE; -- if exponent = 255 => saturate, if 0 => 0 satnode <= aaff(31) AND aaff(30) AND aaff(29) AND aaff(28) AND aaff(27) AND aaff(26) AND aaff(25) AND aaff(24); zipnode <= NOT(aaff(31) OR aaff(30) OR aaff(29) OR aaff(28) OR aaff(27) OR aaff(26) OR aaff(25) OR aaff(24)); gexpa: FOR k IN 1 TO 8 GENERATE expnode(k) <= (aaff(k+23) OR satnode) AND NOT(zipnode); END GENERATE; expnode(9) <= satnode; expnode(10) <= '0'; --*** internal format *** gxa: IF (target = 0) GENERATE fracnode(mantissa) <= aaff(32); fracnode(mantissa-1) <= aaff(32); fracnode(mantissa-2) <= aaff(32); fracnode(mantissa-3) <= aaff(32); fracnode(mantissa-4) <= aaff(32); --fracnode(mantissa-5) <= NOT(aaff(32)); -- '1' XOR sign -- 13/07/09 fracnode(mantissa-5) <= aaff(32) XOR NOT(zipnode); -- '1' XOR sign gxb: FOR k IN 1 TO 23 GENERATE fracnode(mantissa-29+k)<= (aaff(k) XOR aaff(32)); END GENERATE; gxc: FOR k IN 1 TO mantissa-29 GENERATE fracnode(k)<= aaff(32); -- '0' XOR sign END GENERATE; gxd: IF (roundconvert = 0) GENERATE fractional <= fracnode; END GENERATE; gxe: IF (roundconvert = 1) GENERATE fractional <= fracnode + (zerovec(mantissa-1) & aaff(32)); END GENERATE; exponent <= expnode; END GENERATE; --*** direct to multiplier *** gma: IF (target = 1) GENERATE fracnode(mantissa) <= aaff(32); --fracnode(mantissa-1) <= NOT(aaff(32)); -- '1' XOR sign -- 13/07/09 fracnode(mantissa-1) <= aaff(32) XOR NOT(zipnode); gmb: FOR k IN 1 TO 23 GENERATE fracnode(mantissa-25+k)<= (aaff(k) XOR aaff(32)); END GENERATE; gmc: FOR k IN 1 TO mantissa-25 GENERATE fracnode(k)<= aaff(32); -- '0' XOR sign END GENERATE; gmd: IF (roundconvert = 0) GENERATE fractional <= fracnode; END GENERATE; gme: IF (roundconvert = 1) GENERATE fractional <= fracnode + (zerovec(mantissa-1) & aaff(32)); END GENERATE; --***??? adjust ??? exponent <= expnode; END GENERATE; -- never register output --*** direct to divider *** gda: IF (target = 2) GENERATE fracnode(mantissa) <= aaff(32); -- 13/07/09 fracnode(mantissa-1) <= '1' AND NOT(zipnode); fracnode(mantissa-2 DOWNTO mantissa-24)<= aaff(23 DOWNTO 1); gfb: FOR k IN 1 TO mantissa-25 GENERATE fracnode(k)<= '0'; END GENERATE; fractional <= fracnode; --***??? adjust ??? exponent <= expnode; END GENERATE; --*** OUTPUTS *** goa: IF ((target = 0 AND outputpipe = 1) OR (target = 1 AND outputpipe = 1)) GENERATE cc <= ccff; ccsat <= satff; cczip <= zipff; END GENERATE; gob: IF ((target = 0 AND outputpipe = 0) OR (target = 1 AND outputpipe = 0) OR (target = 2)) GENERATE cc <= fractional & exponent; ccsat <= satnode; cczip <= zipnode; END GENERATE; END rtl;
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** ALTERA FLOATING POINT DATAPATH COMPILER *** --*** *** --*** HCC_CASTFTOX.VHD *** --*** *** --*** Function: Cast IEEE754 Single to Internal *** --*** Single *** --*** *** --*** 14/07/07 ML *** --*** *** --*** (c) 2007 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** 06/02/08 - divider mantissa aa to aaff *** --*** 13/07/09 - if zip, then zero '1' in frac *** --*** *** --*** *** --*************************************************** ENTITY hcc_castftox IS GENERIC ( target : integer := 1; -- 0 (internal), 1 (multiplier), 2 (divider) roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1' mantissa : positive := 32; outputpipe : integer := 1 -- 0 no pipe, 1 output always registered ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1); cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); ccsat, cczip : OUT STD_LOGIC ); END hcc_castftox; ARCHITECTURE rtl OF hcc_castftox IS signal zerovec : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1); signal aaff : STD_LOGIC_VECTOR (32 DOWNTO 1); signal ccff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); signal fracnode, fractional : STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal expnode, exponent : STD_LOGIC_VECTOR (10 DOWNTO 1); signal satnode, zipnode : STD_LOGIC; signal satff, zipff : STD_LOGIC; BEGIN -- ieee754: sign (32), 8 exponent (31:24), 23 mantissa (23:1) -- x format: (signx5,!sign,mantissa XOR sign, sign(xx.xx)), exponent(10:1) -- multiplier : (SIGN)('1')(23:1)sign(xx.xx), exponent(10:1) -- divider : "01"(23:1) (00..00),exponent(10:1) (lower mantissa bits ignored by fpdiv1x) gza: IF (roundconvert = 1) GENERATE gza: FOR k IN 1 TO mantissa-1 GENERATE zerovec(k) <= '0'; END GENERATE; END GENERATE; pca: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO 32 LOOP aaff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN aaff <= aa; END IF; END IF; END PROCESS; gro: IF ((target = 0 AND outputpipe = 1) OR (target = 1 AND outputpipe = 1)) GENERATE pca: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO mantissa+10 LOOP ccff(k) <= '0'; END LOOP; satff <= '0'; zipff <= '0'; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN ccff <= fractional & exponent; satff <= satnode; zipff <= zipnode; END IF; END IF; END PROCESS; END GENERATE; -- if exponent = 255 => saturate, if 0 => 0 satnode <= aaff(31) AND aaff(30) AND aaff(29) AND aaff(28) AND aaff(27) AND aaff(26) AND aaff(25) AND aaff(24); zipnode <= NOT(aaff(31) OR aaff(30) OR aaff(29) OR aaff(28) OR aaff(27) OR aaff(26) OR aaff(25) OR aaff(24)); gexpa: FOR k IN 1 TO 8 GENERATE expnode(k) <= (aaff(k+23) OR satnode) AND NOT(zipnode); END GENERATE; expnode(9) <= satnode; expnode(10) <= '0'; --*** internal format *** gxa: IF (target = 0) GENERATE fracnode(mantissa) <= aaff(32); fracnode(mantissa-1) <= aaff(32); fracnode(mantissa-2) <= aaff(32); fracnode(mantissa-3) <= aaff(32); fracnode(mantissa-4) <= aaff(32); --fracnode(mantissa-5) <= NOT(aaff(32)); -- '1' XOR sign -- 13/07/09 fracnode(mantissa-5) <= aaff(32) XOR NOT(zipnode); -- '1' XOR sign gxb: FOR k IN 1 TO 23 GENERATE fracnode(mantissa-29+k)<= (aaff(k) XOR aaff(32)); END GENERATE; gxc: FOR k IN 1 TO mantissa-29 GENERATE fracnode(k)<= aaff(32); -- '0' XOR sign END GENERATE; gxd: IF (roundconvert = 0) GENERATE fractional <= fracnode; END GENERATE; gxe: IF (roundconvert = 1) GENERATE fractional <= fracnode + (zerovec(mantissa-1) & aaff(32)); END GENERATE; exponent <= expnode; END GENERATE; --*** direct to multiplier *** gma: IF (target = 1) GENERATE fracnode(mantissa) <= aaff(32); --fracnode(mantissa-1) <= NOT(aaff(32)); -- '1' XOR sign -- 13/07/09 fracnode(mantissa-1) <= aaff(32) XOR NOT(zipnode); gmb: FOR k IN 1 TO 23 GENERATE fracnode(mantissa-25+k)<= (aaff(k) XOR aaff(32)); END GENERATE; gmc: FOR k IN 1 TO mantissa-25 GENERATE fracnode(k)<= aaff(32); -- '0' XOR sign END GENERATE; gmd: IF (roundconvert = 0) GENERATE fractional <= fracnode; END GENERATE; gme: IF (roundconvert = 1) GENERATE fractional <= fracnode + (zerovec(mantissa-1) & aaff(32)); END GENERATE; --***??? adjust ??? exponent <= expnode; END GENERATE; -- never register output --*** direct to divider *** gda: IF (target = 2) GENERATE fracnode(mantissa) <= aaff(32); -- 13/07/09 fracnode(mantissa-1) <= '1' AND NOT(zipnode); fracnode(mantissa-2 DOWNTO mantissa-24)<= aaff(23 DOWNTO 1); gfb: FOR k IN 1 TO mantissa-25 GENERATE fracnode(k)<= '0'; END GENERATE; fractional <= fracnode; --***??? adjust ??? exponent <= expnode; END GENERATE; --*** OUTPUTS *** goa: IF ((target = 0 AND outputpipe = 1) OR (target = 1 AND outputpipe = 1)) GENERATE cc <= ccff; ccsat <= satff; cczip <= zipff; END GENERATE; gob: IF ((target = 0 AND outputpipe = 0) OR (target = 1 AND outputpipe = 0) OR (target = 2)) GENERATE cc <= fractional & exponent; ccsat <= satnode; cczip <= zipnode; END GENERATE; END rtl;
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** ALTERA FLOATING POINT DATAPATH COMPILER *** --*** *** --*** HCC_CASTFTOX.VHD *** --*** *** --*** Function: Cast IEEE754 Single to Internal *** --*** Single *** --*** *** --*** 14/07/07 ML *** --*** *** --*** (c) 2007 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** 06/02/08 - divider mantissa aa to aaff *** --*** 13/07/09 - if zip, then zero '1' in frac *** --*** *** --*** *** --*************************************************** ENTITY hcc_castftox IS GENERIC ( target : integer := 1; -- 0 (internal), 1 (multiplier), 2 (divider) roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1' mantissa : positive := 32; outputpipe : integer := 1 -- 0 no pipe, 1 output always registered ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1); cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); ccsat, cczip : OUT STD_LOGIC ); END hcc_castftox; ARCHITECTURE rtl OF hcc_castftox IS signal zerovec : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1); signal aaff : STD_LOGIC_VECTOR (32 DOWNTO 1); signal ccff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); signal fracnode, fractional : STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal expnode, exponent : STD_LOGIC_VECTOR (10 DOWNTO 1); signal satnode, zipnode : STD_LOGIC; signal satff, zipff : STD_LOGIC; BEGIN -- ieee754: sign (32), 8 exponent (31:24), 23 mantissa (23:1) -- x format: (signx5,!sign,mantissa XOR sign, sign(xx.xx)), exponent(10:1) -- multiplier : (SIGN)('1')(23:1)sign(xx.xx), exponent(10:1) -- divider : "01"(23:1) (00..00),exponent(10:1) (lower mantissa bits ignored by fpdiv1x) gza: IF (roundconvert = 1) GENERATE gza: FOR k IN 1 TO mantissa-1 GENERATE zerovec(k) <= '0'; END GENERATE; END GENERATE; pca: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO 32 LOOP aaff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN aaff <= aa; END IF; END IF; END PROCESS; gro: IF ((target = 0 AND outputpipe = 1) OR (target = 1 AND outputpipe = 1)) GENERATE pca: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO mantissa+10 LOOP ccff(k) <= '0'; END LOOP; satff <= '0'; zipff <= '0'; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN ccff <= fractional & exponent; satff <= satnode; zipff <= zipnode; END IF; END IF; END PROCESS; END GENERATE; -- if exponent = 255 => saturate, if 0 => 0 satnode <= aaff(31) AND aaff(30) AND aaff(29) AND aaff(28) AND aaff(27) AND aaff(26) AND aaff(25) AND aaff(24); zipnode <= NOT(aaff(31) OR aaff(30) OR aaff(29) OR aaff(28) OR aaff(27) OR aaff(26) OR aaff(25) OR aaff(24)); gexpa: FOR k IN 1 TO 8 GENERATE expnode(k) <= (aaff(k+23) OR satnode) AND NOT(zipnode); END GENERATE; expnode(9) <= satnode; expnode(10) <= '0'; --*** internal format *** gxa: IF (target = 0) GENERATE fracnode(mantissa) <= aaff(32); fracnode(mantissa-1) <= aaff(32); fracnode(mantissa-2) <= aaff(32); fracnode(mantissa-3) <= aaff(32); fracnode(mantissa-4) <= aaff(32); --fracnode(mantissa-5) <= NOT(aaff(32)); -- '1' XOR sign -- 13/07/09 fracnode(mantissa-5) <= aaff(32) XOR NOT(zipnode); -- '1' XOR sign gxb: FOR k IN 1 TO 23 GENERATE fracnode(mantissa-29+k)<= (aaff(k) XOR aaff(32)); END GENERATE; gxc: FOR k IN 1 TO mantissa-29 GENERATE fracnode(k)<= aaff(32); -- '0' XOR sign END GENERATE; gxd: IF (roundconvert = 0) GENERATE fractional <= fracnode; END GENERATE; gxe: IF (roundconvert = 1) GENERATE fractional <= fracnode + (zerovec(mantissa-1) & aaff(32)); END GENERATE; exponent <= expnode; END GENERATE; --*** direct to multiplier *** gma: IF (target = 1) GENERATE fracnode(mantissa) <= aaff(32); --fracnode(mantissa-1) <= NOT(aaff(32)); -- '1' XOR sign -- 13/07/09 fracnode(mantissa-1) <= aaff(32) XOR NOT(zipnode); gmb: FOR k IN 1 TO 23 GENERATE fracnode(mantissa-25+k)<= (aaff(k) XOR aaff(32)); END GENERATE; gmc: FOR k IN 1 TO mantissa-25 GENERATE fracnode(k)<= aaff(32); -- '0' XOR sign END GENERATE; gmd: IF (roundconvert = 0) GENERATE fractional <= fracnode; END GENERATE; gme: IF (roundconvert = 1) GENERATE fractional <= fracnode + (zerovec(mantissa-1) & aaff(32)); END GENERATE; --***??? adjust ??? exponent <= expnode; END GENERATE; -- never register output --*** direct to divider *** gda: IF (target = 2) GENERATE fracnode(mantissa) <= aaff(32); -- 13/07/09 fracnode(mantissa-1) <= '1' AND NOT(zipnode); fracnode(mantissa-2 DOWNTO mantissa-24)<= aaff(23 DOWNTO 1); gfb: FOR k IN 1 TO mantissa-25 GENERATE fracnode(k)<= '0'; END GENERATE; fractional <= fracnode; --***??? adjust ??? exponent <= expnode; END GENERATE; --*** OUTPUTS *** goa: IF ((target = 0 AND outputpipe = 1) OR (target = 1 AND outputpipe = 1)) GENERATE cc <= ccff; ccsat <= satff; cczip <= zipff; END GENERATE; gob: IF ((target = 0 AND outputpipe = 0) OR (target = 1 AND outputpipe = 0) OR (target = 2)) GENERATE cc <= fractional & exponent; ccsat <= satnode; cczip <= zipnode; END GENERATE; END rtl;
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** ALTERA FLOATING POINT DATAPATH COMPILER *** --*** *** --*** HCC_CASTFTOX.VHD *** --*** *** --*** Function: Cast IEEE754 Single to Internal *** --*** Single *** --*** *** --*** 14/07/07 ML *** --*** *** --*** (c) 2007 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** 06/02/08 - divider mantissa aa to aaff *** --*** 13/07/09 - if zip, then zero '1' in frac *** --*** *** --*** *** --*************************************************** ENTITY hcc_castftox IS GENERIC ( target : integer := 1; -- 0 (internal), 1 (multiplier), 2 (divider) roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1' mantissa : positive := 32; outputpipe : integer := 1 -- 0 no pipe, 1 output always registered ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1); cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); ccsat, cczip : OUT STD_LOGIC ); END hcc_castftox; ARCHITECTURE rtl OF hcc_castftox IS signal zerovec : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1); signal aaff : STD_LOGIC_VECTOR (32 DOWNTO 1); signal ccff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); signal fracnode, fractional : STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal expnode, exponent : STD_LOGIC_VECTOR (10 DOWNTO 1); signal satnode, zipnode : STD_LOGIC; signal satff, zipff : STD_LOGIC; BEGIN -- ieee754: sign (32), 8 exponent (31:24), 23 mantissa (23:1) -- x format: (signx5,!sign,mantissa XOR sign, sign(xx.xx)), exponent(10:1) -- multiplier : (SIGN)('1')(23:1)sign(xx.xx), exponent(10:1) -- divider : "01"(23:1) (00..00),exponent(10:1) (lower mantissa bits ignored by fpdiv1x) gza: IF (roundconvert = 1) GENERATE gza: FOR k IN 1 TO mantissa-1 GENERATE zerovec(k) <= '0'; END GENERATE; END GENERATE; pca: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO 32 LOOP aaff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN aaff <= aa; END IF; END IF; END PROCESS; gro: IF ((target = 0 AND outputpipe = 1) OR (target = 1 AND outputpipe = 1)) GENERATE pca: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO mantissa+10 LOOP ccff(k) <= '0'; END LOOP; satff <= '0'; zipff <= '0'; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN ccff <= fractional & exponent; satff <= satnode; zipff <= zipnode; END IF; END IF; END PROCESS; END GENERATE; -- if exponent = 255 => saturate, if 0 => 0 satnode <= aaff(31) AND aaff(30) AND aaff(29) AND aaff(28) AND aaff(27) AND aaff(26) AND aaff(25) AND aaff(24); zipnode <= NOT(aaff(31) OR aaff(30) OR aaff(29) OR aaff(28) OR aaff(27) OR aaff(26) OR aaff(25) OR aaff(24)); gexpa: FOR k IN 1 TO 8 GENERATE expnode(k) <= (aaff(k+23) OR satnode) AND NOT(zipnode); END GENERATE; expnode(9) <= satnode; expnode(10) <= '0'; --*** internal format *** gxa: IF (target = 0) GENERATE fracnode(mantissa) <= aaff(32); fracnode(mantissa-1) <= aaff(32); fracnode(mantissa-2) <= aaff(32); fracnode(mantissa-3) <= aaff(32); fracnode(mantissa-4) <= aaff(32); --fracnode(mantissa-5) <= NOT(aaff(32)); -- '1' XOR sign -- 13/07/09 fracnode(mantissa-5) <= aaff(32) XOR NOT(zipnode); -- '1' XOR sign gxb: FOR k IN 1 TO 23 GENERATE fracnode(mantissa-29+k)<= (aaff(k) XOR aaff(32)); END GENERATE; gxc: FOR k IN 1 TO mantissa-29 GENERATE fracnode(k)<= aaff(32); -- '0' XOR sign END GENERATE; gxd: IF (roundconvert = 0) GENERATE fractional <= fracnode; END GENERATE; gxe: IF (roundconvert = 1) GENERATE fractional <= fracnode + (zerovec(mantissa-1) & aaff(32)); END GENERATE; exponent <= expnode; END GENERATE; --*** direct to multiplier *** gma: IF (target = 1) GENERATE fracnode(mantissa) <= aaff(32); --fracnode(mantissa-1) <= NOT(aaff(32)); -- '1' XOR sign -- 13/07/09 fracnode(mantissa-1) <= aaff(32) XOR NOT(zipnode); gmb: FOR k IN 1 TO 23 GENERATE fracnode(mantissa-25+k)<= (aaff(k) XOR aaff(32)); END GENERATE; gmc: FOR k IN 1 TO mantissa-25 GENERATE fracnode(k)<= aaff(32); -- '0' XOR sign END GENERATE; gmd: IF (roundconvert = 0) GENERATE fractional <= fracnode; END GENERATE; gme: IF (roundconvert = 1) GENERATE fractional <= fracnode + (zerovec(mantissa-1) & aaff(32)); END GENERATE; --***??? adjust ??? exponent <= expnode; END GENERATE; -- never register output --*** direct to divider *** gda: IF (target = 2) GENERATE fracnode(mantissa) <= aaff(32); -- 13/07/09 fracnode(mantissa-1) <= '1' AND NOT(zipnode); fracnode(mantissa-2 DOWNTO mantissa-24)<= aaff(23 DOWNTO 1); gfb: FOR k IN 1 TO mantissa-25 GENERATE fracnode(k)<= '0'; END GENERATE; fractional <= fracnode; --***??? adjust ??? exponent <= expnode; END GENERATE; --*** OUTPUTS *** goa: IF ((target = 0 AND outputpipe = 1) OR (target = 1 AND outputpipe = 1)) GENERATE cc <= ccff; ccsat <= satff; cczip <= zipff; END GENERATE; gob: IF ((target = 0 AND outputpipe = 0) OR (target = 1 AND outputpipe = 0) OR (target = 2)) GENERATE cc <= fractional & exponent; ccsat <= satnode; cczip <= zipnode; END GENERATE; END rtl;
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** ALTERA FLOATING POINT DATAPATH COMPILER *** --*** *** --*** HCC_CASTFTOX.VHD *** --*** *** --*** Function: Cast IEEE754 Single to Internal *** --*** Single *** --*** *** --*** 14/07/07 ML *** --*** *** --*** (c) 2007 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** 06/02/08 - divider mantissa aa to aaff *** --*** 13/07/09 - if zip, then zero '1' in frac *** --*** *** --*** *** --*************************************************** ENTITY hcc_castftox IS GENERIC ( target : integer := 1; -- 0 (internal), 1 (multiplier), 2 (divider) roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1' mantissa : positive := 32; outputpipe : integer := 1 -- 0 no pipe, 1 output always registered ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1); cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); ccsat, cczip : OUT STD_LOGIC ); END hcc_castftox; ARCHITECTURE rtl OF hcc_castftox IS signal zerovec : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1); signal aaff : STD_LOGIC_VECTOR (32 DOWNTO 1); signal ccff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); signal fracnode, fractional : STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal expnode, exponent : STD_LOGIC_VECTOR (10 DOWNTO 1); signal satnode, zipnode : STD_LOGIC; signal satff, zipff : STD_LOGIC; BEGIN -- ieee754: sign (32), 8 exponent (31:24), 23 mantissa (23:1) -- x format: (signx5,!sign,mantissa XOR sign, sign(xx.xx)), exponent(10:1) -- multiplier : (SIGN)('1')(23:1)sign(xx.xx), exponent(10:1) -- divider : "01"(23:1) (00..00),exponent(10:1) (lower mantissa bits ignored by fpdiv1x) gza: IF (roundconvert = 1) GENERATE gza: FOR k IN 1 TO mantissa-1 GENERATE zerovec(k) <= '0'; END GENERATE; END GENERATE; pca: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO 32 LOOP aaff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN aaff <= aa; END IF; END IF; END PROCESS; gro: IF ((target = 0 AND outputpipe = 1) OR (target = 1 AND outputpipe = 1)) GENERATE pca: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO mantissa+10 LOOP ccff(k) <= '0'; END LOOP; satff <= '0'; zipff <= '0'; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN ccff <= fractional & exponent; satff <= satnode; zipff <= zipnode; END IF; END IF; END PROCESS; END GENERATE; -- if exponent = 255 => saturate, if 0 => 0 satnode <= aaff(31) AND aaff(30) AND aaff(29) AND aaff(28) AND aaff(27) AND aaff(26) AND aaff(25) AND aaff(24); zipnode <= NOT(aaff(31) OR aaff(30) OR aaff(29) OR aaff(28) OR aaff(27) OR aaff(26) OR aaff(25) OR aaff(24)); gexpa: FOR k IN 1 TO 8 GENERATE expnode(k) <= (aaff(k+23) OR satnode) AND NOT(zipnode); END GENERATE; expnode(9) <= satnode; expnode(10) <= '0'; --*** internal format *** gxa: IF (target = 0) GENERATE fracnode(mantissa) <= aaff(32); fracnode(mantissa-1) <= aaff(32); fracnode(mantissa-2) <= aaff(32); fracnode(mantissa-3) <= aaff(32); fracnode(mantissa-4) <= aaff(32); --fracnode(mantissa-5) <= NOT(aaff(32)); -- '1' XOR sign -- 13/07/09 fracnode(mantissa-5) <= aaff(32) XOR NOT(zipnode); -- '1' XOR sign gxb: FOR k IN 1 TO 23 GENERATE fracnode(mantissa-29+k)<= (aaff(k) XOR aaff(32)); END GENERATE; gxc: FOR k IN 1 TO mantissa-29 GENERATE fracnode(k)<= aaff(32); -- '0' XOR sign END GENERATE; gxd: IF (roundconvert = 0) GENERATE fractional <= fracnode; END GENERATE; gxe: IF (roundconvert = 1) GENERATE fractional <= fracnode + (zerovec(mantissa-1) & aaff(32)); END GENERATE; exponent <= expnode; END GENERATE; --*** direct to multiplier *** gma: IF (target = 1) GENERATE fracnode(mantissa) <= aaff(32); --fracnode(mantissa-1) <= NOT(aaff(32)); -- '1' XOR sign -- 13/07/09 fracnode(mantissa-1) <= aaff(32) XOR NOT(zipnode); gmb: FOR k IN 1 TO 23 GENERATE fracnode(mantissa-25+k)<= (aaff(k) XOR aaff(32)); END GENERATE; gmc: FOR k IN 1 TO mantissa-25 GENERATE fracnode(k)<= aaff(32); -- '0' XOR sign END GENERATE; gmd: IF (roundconvert = 0) GENERATE fractional <= fracnode; END GENERATE; gme: IF (roundconvert = 1) GENERATE fractional <= fracnode + (zerovec(mantissa-1) & aaff(32)); END GENERATE; --***??? adjust ??? exponent <= expnode; END GENERATE; -- never register output --*** direct to divider *** gda: IF (target = 2) GENERATE fracnode(mantissa) <= aaff(32); -- 13/07/09 fracnode(mantissa-1) <= '1' AND NOT(zipnode); fracnode(mantissa-2 DOWNTO mantissa-24)<= aaff(23 DOWNTO 1); gfb: FOR k IN 1 TO mantissa-25 GENERATE fracnode(k)<= '0'; END GENERATE; fractional <= fracnode; --***??? adjust ??? exponent <= expnode; END GENERATE; --*** OUTPUTS *** goa: IF ((target = 0 AND outputpipe = 1) OR (target = 1 AND outputpipe = 1)) GENERATE cc <= ccff; ccsat <= satff; cczip <= zipff; END GENERATE; gob: IF ((target = 0 AND outputpipe = 0) OR (target = 1 AND outputpipe = 0) OR (target = 2)) GENERATE cc <= fractional & exponent; ccsat <= satnode; cczip <= zipnode; END GENERATE; END rtl;
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** ALTERA FLOATING POINT DATAPATH COMPILER *** --*** *** --*** HCC_CASTFTOX.VHD *** --*** *** --*** Function: Cast IEEE754 Single to Internal *** --*** Single *** --*** *** --*** 14/07/07 ML *** --*** *** --*** (c) 2007 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** 06/02/08 - divider mantissa aa to aaff *** --*** 13/07/09 - if zip, then zero '1' in frac *** --*** *** --*** *** --*************************************************** ENTITY hcc_castftox IS GENERIC ( target : integer := 1; -- 0 (internal), 1 (multiplier), 2 (divider) roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1' mantissa : positive := 32; outputpipe : integer := 1 -- 0 no pipe, 1 output always registered ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1); cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); ccsat, cczip : OUT STD_LOGIC ); END hcc_castftox; ARCHITECTURE rtl OF hcc_castftox IS signal zerovec : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1); signal aaff : STD_LOGIC_VECTOR (32 DOWNTO 1); signal ccff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); signal fracnode, fractional : STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal expnode, exponent : STD_LOGIC_VECTOR (10 DOWNTO 1); signal satnode, zipnode : STD_LOGIC; signal satff, zipff : STD_LOGIC; BEGIN -- ieee754: sign (32), 8 exponent (31:24), 23 mantissa (23:1) -- x format: (signx5,!sign,mantissa XOR sign, sign(xx.xx)), exponent(10:1) -- multiplier : (SIGN)('1')(23:1)sign(xx.xx), exponent(10:1) -- divider : "01"(23:1) (00..00),exponent(10:1) (lower mantissa bits ignored by fpdiv1x) gza: IF (roundconvert = 1) GENERATE gza: FOR k IN 1 TO mantissa-1 GENERATE zerovec(k) <= '0'; END GENERATE; END GENERATE; pca: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO 32 LOOP aaff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN aaff <= aa; END IF; END IF; END PROCESS; gro: IF ((target = 0 AND outputpipe = 1) OR (target = 1 AND outputpipe = 1)) GENERATE pca: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO mantissa+10 LOOP ccff(k) <= '0'; END LOOP; satff <= '0'; zipff <= '0'; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN ccff <= fractional & exponent; satff <= satnode; zipff <= zipnode; END IF; END IF; END PROCESS; END GENERATE; -- if exponent = 255 => saturate, if 0 => 0 satnode <= aaff(31) AND aaff(30) AND aaff(29) AND aaff(28) AND aaff(27) AND aaff(26) AND aaff(25) AND aaff(24); zipnode <= NOT(aaff(31) OR aaff(30) OR aaff(29) OR aaff(28) OR aaff(27) OR aaff(26) OR aaff(25) OR aaff(24)); gexpa: FOR k IN 1 TO 8 GENERATE expnode(k) <= (aaff(k+23) OR satnode) AND NOT(zipnode); END GENERATE; expnode(9) <= satnode; expnode(10) <= '0'; --*** internal format *** gxa: IF (target = 0) GENERATE fracnode(mantissa) <= aaff(32); fracnode(mantissa-1) <= aaff(32); fracnode(mantissa-2) <= aaff(32); fracnode(mantissa-3) <= aaff(32); fracnode(mantissa-4) <= aaff(32); --fracnode(mantissa-5) <= NOT(aaff(32)); -- '1' XOR sign -- 13/07/09 fracnode(mantissa-5) <= aaff(32) XOR NOT(zipnode); -- '1' XOR sign gxb: FOR k IN 1 TO 23 GENERATE fracnode(mantissa-29+k)<= (aaff(k) XOR aaff(32)); END GENERATE; gxc: FOR k IN 1 TO mantissa-29 GENERATE fracnode(k)<= aaff(32); -- '0' XOR sign END GENERATE; gxd: IF (roundconvert = 0) GENERATE fractional <= fracnode; END GENERATE; gxe: IF (roundconvert = 1) GENERATE fractional <= fracnode + (zerovec(mantissa-1) & aaff(32)); END GENERATE; exponent <= expnode; END GENERATE; --*** direct to multiplier *** gma: IF (target = 1) GENERATE fracnode(mantissa) <= aaff(32); --fracnode(mantissa-1) <= NOT(aaff(32)); -- '1' XOR sign -- 13/07/09 fracnode(mantissa-1) <= aaff(32) XOR NOT(zipnode); gmb: FOR k IN 1 TO 23 GENERATE fracnode(mantissa-25+k)<= (aaff(k) XOR aaff(32)); END GENERATE; gmc: FOR k IN 1 TO mantissa-25 GENERATE fracnode(k)<= aaff(32); -- '0' XOR sign END GENERATE; gmd: IF (roundconvert = 0) GENERATE fractional <= fracnode; END GENERATE; gme: IF (roundconvert = 1) GENERATE fractional <= fracnode + (zerovec(mantissa-1) & aaff(32)); END GENERATE; --***??? adjust ??? exponent <= expnode; END GENERATE; -- never register output --*** direct to divider *** gda: IF (target = 2) GENERATE fracnode(mantissa) <= aaff(32); -- 13/07/09 fracnode(mantissa-1) <= '1' AND NOT(zipnode); fracnode(mantissa-2 DOWNTO mantissa-24)<= aaff(23 DOWNTO 1); gfb: FOR k IN 1 TO mantissa-25 GENERATE fracnode(k)<= '0'; END GENERATE; fractional <= fracnode; --***??? adjust ??? exponent <= expnode; END GENERATE; --*** OUTPUTS *** goa: IF ((target = 0 AND outputpipe = 1) OR (target = 1 AND outputpipe = 1)) GENERATE cc <= ccff; ccsat <= satff; cczip <= zipff; END GENERATE; gob: IF ((target = 0 AND outputpipe = 0) OR (target = 1 AND outputpipe = 0) OR (target = 2)) GENERATE cc <= fractional & exponent; ccsat <= satnode; cczip <= zipnode; END GENERATE; END rtl;
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** ALTERA FLOATING POINT DATAPATH COMPILER *** --*** *** --*** HCC_CASTFTOX.VHD *** --*** *** --*** Function: Cast IEEE754 Single to Internal *** --*** Single *** --*** *** --*** 14/07/07 ML *** --*** *** --*** (c) 2007 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** 06/02/08 - divider mantissa aa to aaff *** --*** 13/07/09 - if zip, then zero '1' in frac *** --*** *** --*** *** --*************************************************** ENTITY hcc_castftox IS GENERIC ( target : integer := 1; -- 0 (internal), 1 (multiplier), 2 (divider) roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1' mantissa : positive := 32; outputpipe : integer := 1 -- 0 no pipe, 1 output always registered ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1); cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); ccsat, cczip : OUT STD_LOGIC ); END hcc_castftox; ARCHITECTURE rtl OF hcc_castftox IS signal zerovec : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1); signal aaff : STD_LOGIC_VECTOR (32 DOWNTO 1); signal ccff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); signal fracnode, fractional : STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal expnode, exponent : STD_LOGIC_VECTOR (10 DOWNTO 1); signal satnode, zipnode : STD_LOGIC; signal satff, zipff : STD_LOGIC; BEGIN -- ieee754: sign (32), 8 exponent (31:24), 23 mantissa (23:1) -- x format: (signx5,!sign,mantissa XOR sign, sign(xx.xx)), exponent(10:1) -- multiplier : (SIGN)('1')(23:1)sign(xx.xx), exponent(10:1) -- divider : "01"(23:1) (00..00),exponent(10:1) (lower mantissa bits ignored by fpdiv1x) gza: IF (roundconvert = 1) GENERATE gza: FOR k IN 1 TO mantissa-1 GENERATE zerovec(k) <= '0'; END GENERATE; END GENERATE; pca: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO 32 LOOP aaff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN aaff <= aa; END IF; END IF; END PROCESS; gro: IF ((target = 0 AND outputpipe = 1) OR (target = 1 AND outputpipe = 1)) GENERATE pca: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO mantissa+10 LOOP ccff(k) <= '0'; END LOOP; satff <= '0'; zipff <= '0'; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN ccff <= fractional & exponent; satff <= satnode; zipff <= zipnode; END IF; END IF; END PROCESS; END GENERATE; -- if exponent = 255 => saturate, if 0 => 0 satnode <= aaff(31) AND aaff(30) AND aaff(29) AND aaff(28) AND aaff(27) AND aaff(26) AND aaff(25) AND aaff(24); zipnode <= NOT(aaff(31) OR aaff(30) OR aaff(29) OR aaff(28) OR aaff(27) OR aaff(26) OR aaff(25) OR aaff(24)); gexpa: FOR k IN 1 TO 8 GENERATE expnode(k) <= (aaff(k+23) OR satnode) AND NOT(zipnode); END GENERATE; expnode(9) <= satnode; expnode(10) <= '0'; --*** internal format *** gxa: IF (target = 0) GENERATE fracnode(mantissa) <= aaff(32); fracnode(mantissa-1) <= aaff(32); fracnode(mantissa-2) <= aaff(32); fracnode(mantissa-3) <= aaff(32); fracnode(mantissa-4) <= aaff(32); --fracnode(mantissa-5) <= NOT(aaff(32)); -- '1' XOR sign -- 13/07/09 fracnode(mantissa-5) <= aaff(32) XOR NOT(zipnode); -- '1' XOR sign gxb: FOR k IN 1 TO 23 GENERATE fracnode(mantissa-29+k)<= (aaff(k) XOR aaff(32)); END GENERATE; gxc: FOR k IN 1 TO mantissa-29 GENERATE fracnode(k)<= aaff(32); -- '0' XOR sign END GENERATE; gxd: IF (roundconvert = 0) GENERATE fractional <= fracnode; END GENERATE; gxe: IF (roundconvert = 1) GENERATE fractional <= fracnode + (zerovec(mantissa-1) & aaff(32)); END GENERATE; exponent <= expnode; END GENERATE; --*** direct to multiplier *** gma: IF (target = 1) GENERATE fracnode(mantissa) <= aaff(32); --fracnode(mantissa-1) <= NOT(aaff(32)); -- '1' XOR sign -- 13/07/09 fracnode(mantissa-1) <= aaff(32) XOR NOT(zipnode); gmb: FOR k IN 1 TO 23 GENERATE fracnode(mantissa-25+k)<= (aaff(k) XOR aaff(32)); END GENERATE; gmc: FOR k IN 1 TO mantissa-25 GENERATE fracnode(k)<= aaff(32); -- '0' XOR sign END GENERATE; gmd: IF (roundconvert = 0) GENERATE fractional <= fracnode; END GENERATE; gme: IF (roundconvert = 1) GENERATE fractional <= fracnode + (zerovec(mantissa-1) & aaff(32)); END GENERATE; --***??? adjust ??? exponent <= expnode; END GENERATE; -- never register output --*** direct to divider *** gda: IF (target = 2) GENERATE fracnode(mantissa) <= aaff(32); -- 13/07/09 fracnode(mantissa-1) <= '1' AND NOT(zipnode); fracnode(mantissa-2 DOWNTO mantissa-24)<= aaff(23 DOWNTO 1); gfb: FOR k IN 1 TO mantissa-25 GENERATE fracnode(k)<= '0'; END GENERATE; fractional <= fracnode; --***??? adjust ??? exponent <= expnode; END GENERATE; --*** OUTPUTS *** goa: IF ((target = 0 AND outputpipe = 1) OR (target = 1 AND outputpipe = 1)) GENERATE cc <= ccff; ccsat <= satff; cczip <= zipff; END GENERATE; gob: IF ((target = 0 AND outputpipe = 0) OR (target = 1 AND outputpipe = 0) OR (target = 2)) GENERATE cc <= fractional & exponent; ccsat <= satnode; cczip <= zipnode; END GENERATE; END rtl;
library IEEE; use IEEE.Std_Logic_1164.all; entity decod is port (C: in std_logic_vector(3 downto 0); S: out std_logic_vector(6 downto 0) ); end decod; architecture circuito of decod is begin -- decodifica binario para 7 segmentos S <= "1000000" when C = "0000" else "1111001" when C = "0001" else "0100100" when C = "0010" else "0110000" when C = "0011" else "0011001" when C = "0100" else "0010010" when C = "0101" else "0000010" when C = "0110" else "1111000" when C = "0111" else "0000000" when C = "1000" else "0011000" when C = "1001" else "0001000" when C = "1010" else "0000011" when C = "1011" else "1000110" when C = "1100" else "0100001" when C = "1101" else "0000110" when C = "1110" else "0001110" when C = "1111" else "1111111"; end circuito;
-- -*- vhdl -*- ------------------------------------------------------------------------------- -- Copyright (c) 2012, The CARPE Project, All rights reserved. -- -- See the AUTHORS file for individual contributors. -- -- -- -- Copyright and related rights are licensed under the Solderpad -- -- Hardware License, Version 0.51 (the "License"); you may not use this -- -- file except in compliance with the License. You may obtain a copy of -- -- the License at http://solderpad.org/licenses/SHL-0.51. -- -- -- -- Unless required by applicable law or agreed to in writing, software, -- -- hardware and materials distributed under this License is distributed -- -- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -- -- either express or implied. See the License for the specific language -- -- governing permissions and limitations under the License. -- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; library util; use util.types_pkg.all; use work.cpu_btb_cache_config_pkg.all; package cpu_btb_cache_replace_none_pkg is constant cpu_btb_cache_replace_none_state_bits : natural := 0; subtype cpu_btb_cache_replace_none_state_type is std_ulogic_vector(cpu_btb_cache_replace_none_state_bits-1 downto 0); type cpu_btb_cache_replace_none_ctrl_in_type is record flush : std_ulogic; re : std_ulogic; we : std_ulogic; end record; type cpu_btb_cache_replace_none_dp_in_type is record rindex : std_ulogic_vector(cpu_btb_cache_index_bits-1 downto 0); windex : std_ulogic_vector(cpu_btb_cache_index_bits-1 downto 0); wway : std_ulogic_vector(2**cpu_btb_cache_log2_assoc-1 downto 0); wstate : cpu_btb_cache_replace_none_state_type; end record; type cpu_btb_cache_replace_none_dp_out_type is record rway : std_ulogic_vector(2**cpu_btb_cache_assoc-1 downto 0); rstate : cpu_btb_cache_replace_none_state_type; end record; end package;
------------------------------------------------------------------------------- -- Title : Accelerator Adapter -- Project : ------------------------------------------------------------------------------- -- File : xd_m2s_converter.vhd -- Author : rmg/jn -- Company : Xilinx, Inc. -- Created : 2012-09-05 -- Last update: 2012-11-04 -- Platform : -- Standard : VHDL'93 ------------------------------------------------------------------------------- -- Description: ------------------------------------------------------------------------------- -- (c) Copyright 2012 Xilinx, Inc. All rights reserved. ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2012-09-05 1.0 rmg/jn Created -- 2013-07-31 2.0 pvk Updated Tvalid generattion logic to remove stream -- protocol error where tvalid was deasserting -- tlast ------------------------------------------------------------------------------- -- **************************************************************************** -- -- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- **************************************************************************** ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library axis_accelerator_adapter_v2_1_6; use axis_accelerator_adapter_v2_1_6.xd_adapter_pkg.all; entity xd_m2s_converter is generic ( -- System generics: C_FAMILY : string; -- Xilinx FPGA family SIZE_WIDTH : integer; AXI_DATA_WIDTH : integer; AXI_ADDR_WIDTH : integer; AXI_USER_WIDTH : integer; AXI_ID_WIDTH : integer; AXI_DEST_WIDTH : integer); port ( axi_clk : in std_logic; axi_rst : in std_logic; axis_vld : out std_logic; axis_rdy : in std_logic; axis_data : out std_logic_vector(AXI_DATA_WIDTH-1 downto 0); axis_keep : out std_logic_vector((AXI_DATA_WIDTH/8)-1 downto 0); axis_strb : out std_logic_vector((AXI_DATA_WIDTH/8)-1 downto 0); axis_last : out std_logic; axis_id : out std_logic_vector(AXI_ID_WIDTH-1 downto 0); axis_dest : out std_logic_vector(AXI_DEST_WIDTH-1 downto 0); axis_user : out std_logic_vector(AXI_USER_WIDTH-1 downto 0); conv_size : in std_logic_vector(SIZE_WIDTH-1 downto 0); conv_addr : out std_logic_vector(AXI_ADDR_WIDTH-1 downto 0); conv_ce : out std_logic; conv_we : out std_logic; conv_last : out std_logic; conv_rdy : in std_logic; conv_data : in std_logic_vector(AXI_DATA_WIDTH-1 downto 0); host_oarg_tdest : in std_logic_vector(AXI_DEST_WIDTH-1 downto 0)); end entity; architecture rtl of xd_m2s_converter is constant STRB_WIDTH : integer := AXI_DATA_WIDTH/8; type state_type is ( idle, running, wait_last); signal state : state_type; constant SUBWORD_WIDTH : integer := log2(AXI_DATA_WIDTH/8); constant WORD_CNT_WIDTH : integer := SIZE_WIDTH - SUBWORD_WIDTH; constant WORD_CNT_LSB : integer := SUBWORD_WIDTH; constant WORD_CNT_MSB : integer := SIZE_WIDTH-1; signal word_cnt : unsigned(WORD_CNT_WIDTH-1 downto 0); signal init_cnt : std_logic; signal word_cnt_0 : std_logic; signal word_cnt_1 : std_logic; signal full_last_word : std_logic; signal last_word : std_logic; signal last_strb : std_logic_vector(STRB_WIDTH-1 downto 0); -- signal conv_addr_i : unsigned(AXI_ADDR_WIDTH-1 downto 0); signal conv_ce_i : std_logic; signal conv_data_vld : std_logic; signal conv_data_last : std_logic; signal conv_data_strb : std_logic_vector(STRB_WIDTH-1 downto 0); signal fill_pipe : std_logic; -- signal dout_vld : std_logic; signal dout_last : std_logic; signal dout_rdy : std_logic; signal dout : std_logic_vector(AXI_DATA_WIDTH-1 downto 0); signal dout_strb : std_logic_vector(STRB_WIDTH-1 downto 0); begin -- Each time we send a stream out, we initialize to zero its buffer conv_we <= '0'; -- count the words to read: process(axi_clk) variable aux : unsigned(WORD_CNT_WIDTH-1 downto 0); begin if(axi_clk'event and axi_clk = '1') then if(init_cnt = '1') then aux := unsigned(conv_size(WORD_CNT_MSB downto WORD_CNT_LSB)); word_cnt <= aux; word_cnt_0 <= '0'; word_cnt_1 <= '0'; if(aux(WORD_CNT_WIDTH-1 downto 1) = 0) then word_cnt_1 <= aux(0); word_cnt_0 <= not(aux(0)); end if; elsif(conv_ce_i = '1') then word_cnt <= word_cnt - 1; if(word_cnt = 2) then word_cnt_1 <= '1'; else word_cnt_1 <= '0'; end if; word_cnt_0 <= word_cnt_1; end if; end if; end process; -- Address to access: process(axi_clk) variable aux : unsigned(WORD_CNT_WIDTH-1 downto 0); begin if(axi_clk'event and axi_clk = '1') then if(init_cnt = '1') then conv_addr_i <= (others => '0'); elsif(conv_ce_i = '1') then conv_addr_i <= conv_addr_i + 1; end if; end if; end process; conv_addr <= std_logic_vector(conv_addr_i); -- Last read; although last_strb seems complex, each bit generated should be -- a simple LUT with 3 inputs (SUBWORD_WIDTH = 3) process(axi_clk) constant zeros : std_logic_vector(SUBWORD_WIDTH-1 downto 0) := (others => '0'); variable aux : integer range 0 to (2**SUBWORD_WIDTH)-1; begin if(axi_clk'event and axi_clk = '1') then if(init_cnt = '1') then aux := to_integer(unsigned(conv_size(SUBWORD_WIDTH-1 downto 0))); if(aux = 0) then full_last_word <= '1'; last_strb <= (others => '1'); else full_last_word <= '0'; last_strb <= std_logic_vector(to_unsigned(2**aux-1, STRB_WIDTH)); end if; end if; end if; end process; last_word <= word_cnt_1 when (full_last_word = '1') else word_cnt_0; -- This module behaves like a two-stage pipeline -- first stage is BRAM outputs (from multibuffer) -- second stage is te registered output of the module -- TAP 1: BRAM output process(axi_clk) begin if (axi_clk'event and axi_clk = '1') then if (axi_rst = '1') then conv_data_vld <= '0'; conv_data_last <= '0'; conv_data_strb <= (others => '0'); elsif(conv_data_vld = '0' or dout_vld = '0' or (dout_vld and dout_rdy) = '1') then -- this tage happens if any of the following conditions: -- 1.- stage is empty => refresh continous of the input values to the stage -- 2.- next stage is empty => data in this stage move to next stage -- 3.- pipeline moves => consumed data in last stage conv_data_vld <= conv_ce_i; conv_data_last <= last_word; if(last_word = '1') then conv_data_strb <= last_strb; else conv_data_strb <= (others => '1'); end if; end if; end if; end process; -- TAP 2: Output register. process(axi_clk) begin if (axi_clk'event and axi_clk = '1') then if (axi_rst = '1') then dout_vld <= '0'; elsif(dout_vld = '0' or (dout_vld and dout_rdy) = '1') then dout_vld <= conv_data_vld; end if; end if; end process; process(axi_clk) begin if (axi_clk'event and axi_clk = '1') then if(dout_vld = '0' or (dout_vld and dout_rdy) = '1') then dout <= conv_data; dout_last <= conv_data_last; dout_strb <= conv_data_strb; end if; end if; end process; -- Control of reads during filling the pipe: process(axi_clk) begin if (axi_clk'event and axi_clk = '1') then if (axi_rst = '1') then fill_pipe <= '0'; else if(dout_vld = '1') then -- last stage is busy -- Stop if first stage is full or about to be filled (new data coming) fill_pipe <= not(conv_data_vld or conv_ce_i); elsif(conv_data_vld = '1') then -- second to last stage busy -- if new data coming, stop reads fill_pipe <= not(conv_ce_i); else -- pipe is empty fill_pipe <= '1'; end if; end if; end if; end process; -- FSM: process(axi_clk, axi_rst) begin if(axi_rst = '1') then state <= idle; elsif(axi_clk'event and axi_clk = '1') then case state is when idle => if(conv_rdy = '1') then state <= running; end if; when running => if(last_word = '1' and conv_ce_i = '1') then --state <= idle; state <= wait_last; end if; when wait_last => if(dout_last = '1' and axis_rdy = '1') then state <= idle; end if; when others => end case; end if; end process; process(state, conv_rdy, last_word, dout_vld, dout_rdy, fill_pipe) begin init_cnt <= '0'; conv_last <= '0'; conv_ce_i <= '0'; case state is when idle => -- init_cnt <= conv_rdy; init_cnt <= '1'; when running => conv_ce_i <= (dout_vld and dout_rdy) or fill_pipe; conv_last <= last_word and ((dout_vld and dout_rdy) or fill_pipe); when others => end case; end process; conv_ce <= conv_ce_i; axis_vld <= dout_vld; dout_rdy <= axis_rdy; axis_data <= dout; axis_keep <= dout_strb; axis_strb <= dout_strb; axis_last <= dout_last; axis_id <= (others => '0'); axis_dest <= host_oarg_tdest; axis_user <= (others => '0'); end rtl;
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_19_tkfifo.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $ -- $Revision: 1.3 $ -- -- --------------------------------------------------------------------- library qsim; package token_fifo_adt is alias element_type is qsim.qsim_types.token_type; type fifo_record; type fifo_type is access fifo_record; function new_fifo return fifo_type; procedure test_empty ( variable fifo : in fifo_type; variable is_empty : out boolean ); procedure insert ( fifo : inout fifo_type; element : in element_type ); procedure remove ( fifo : inout fifo_type; element : out element_type ); -- private types type fifo_entry_record; type fifo_entry is access fifo_entry_record; type fifo_entry_record is record next_entry : fifo_entry; element : element_type; end record; type fifo_record is record head_entry, tail_entry : fifo_entry; end record; end package token_fifo_adt;
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_19_tkfifo.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $ -- $Revision: 1.3 $ -- -- --------------------------------------------------------------------- library qsim; package token_fifo_adt is alias element_type is qsim.qsim_types.token_type; type fifo_record; type fifo_type is access fifo_record; function new_fifo return fifo_type; procedure test_empty ( variable fifo : in fifo_type; variable is_empty : out boolean ); procedure insert ( fifo : inout fifo_type; element : in element_type ); procedure remove ( fifo : inout fifo_type; element : out element_type ); -- private types type fifo_entry_record; type fifo_entry is access fifo_entry_record; type fifo_entry_record is record next_entry : fifo_entry; element : element_type; end record; type fifo_record is record head_entry, tail_entry : fifo_entry; end record; end package token_fifo_adt;
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: ch_19_tkfifo.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $ -- $Revision: 1.3 $ -- -- --------------------------------------------------------------------- library qsim; package token_fifo_adt is alias element_type is qsim.qsim_types.token_type; type fifo_record; type fifo_type is access fifo_record; function new_fifo return fifo_type; procedure test_empty ( variable fifo : in fifo_type; variable is_empty : out boolean ); procedure insert ( fifo : inout fifo_type; element : in element_type ); procedure remove ( fifo : inout fifo_type; element : out element_type ); -- private types type fifo_entry_record; type fifo_entry is access fifo_entry_record; type fifo_entry_record is record next_entry : fifo_entry; element : element_type; end record; type fifo_record is record head_entry, tail_entry : fifo_entry; end record; end package token_fifo_adt;
-------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 14:02:57 07/14/2014 -- Design Name: -- Module Name: /home/qfi/Documents/aeshw/aes-core/aes-core/key_expansion_tb.vhd -- Project Name: aes-core -- Target Device: -- Tool versions: -- Description: -- -- VHDL Test Bench Created by ISE for module: key_expansion -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector for the ports of the unit under test. Xilinx recommends -- that these types always be used for the top-level I/O of a design in order -- to guarantee that the testbench will bind correctly to the post-implementation -- simulation model. -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --USE ieee.numeric_std.ALL; ENTITY key_expansion_tb IS END key_expansion_tb; ARCHITECTURE behavior OF key_expansion_tb IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT key_expansion PORT( clk : IN std_logic; reset : IN std_logic; exp_start : IN std_logic; exp_end : OUT std_logic; address_in : IN std_logic_vector(3 downto 0); key_in : IN std_logic_vector(127 downto 0); key_out : OUT std_logic_vector(127 downto 0) ); END COMPONENT; --Inputs signal clk : std_logic := '0'; signal reset : std_logic := '0'; signal exp_start : std_logic := '0'; signal address_in : std_logic_vector(3 downto 0) := (others => '0'); signal key_in : std_logic_vector(127 downto 0) := (others => '0'); --Outputs signal exp_end : std_logic; signal key_out : std_logic_vector(127 downto 0); -- Clock period definitions constant clk_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: key_expansion PORT MAP ( clk => clk, reset => reset, exp_start => exp_start, exp_end => exp_end, address_in => address_in, key_in => key_in, key_out => key_out ); -- Clock process definitions clk_process :process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; -- Stimulus process stim_proc: process begin wait for clk_period; exp_start <= '1'; key_in <= x"2b7e151628aed2a6abf7158809cf4f3c"; wait for clk_period; assert exp_end = '0' report "key expansion module: failure" severity failure; -- expander and counter now initialized exp_start <= '0'; -- wait until expansion is finished for i in 1 to 10 loop wait for clk_period; assert exp_end = '0' report "key expansion module: failure" severity failure; end loop; wait for clk_period; -- expansion should now be finished assert exp_end = '1' report "key expansion module: failure" severity failure; wait for clk_period; -- expansion is ready again assert exp_end = '0' report "key expansion module: failure" severity failure; wait for clk_period*10; -- lookup ram values address_in <= x"0"; wait for clk_period; assert key_out = x"2b7e151628aed2a6abf7158809cf4f3c" report "ram module : lookup failure (address 0)" severity failure; address_in <= x"1"; wait for clk_period; assert key_out = x"a0fafe1788542cb123a339392a6c7605" report "ram module : lookup failure (address 1)" severity failure; address_in <= x"2"; wait for clk_period; assert key_out = x"f2c295f27a96b9435935807a7359f67f" report "ram module : lookup failure (address 2)" severity failure; address_in <= x"3"; wait for clk_period; assert key_out = x"3d80477d4716fe3e1e237e446d7a883b" report "ram module : lookup failure (address 3)" severity failure; address_in <= x"4"; wait for clk_period; assert key_out = x"ef44a541a8525b7fb671253bdb0bad00" report "ram module : lookup failure (address 4)" severity failure; address_in <= x"5"; wait for clk_period; assert key_out = x"d4d1c6f87c839d87caf2b8bc11f915bc" report "ram module : lookup failure (address 5)" severity failure; address_in <= x"6"; wait for clk_period; assert key_out = x"6d88a37a110b3efddbf98641ca0093fd" report "ram module : lookup failure (address 6)" severity failure; address_in <= x"7"; wait for clk_period; assert key_out = x"4e54f70e5f5fc9f384a64fb24ea6dc4f" report "ram module : lookup failure (address 7)" severity failure; address_in <= x"8"; wait for clk_period; assert key_out = x"ead27321b58dbad2312bf5607f8d292f" report "ram module : lookup failure (address 8)" severity failure; address_in <= x"9"; wait for clk_period; assert key_out = x"ac7766f319fadc2128d12941575c006e" report "ram module : lookup failure (address 9)" severity failure; address_in <= x"A"; wait for clk_period; assert key_out = x"d014f9a8c9ee2589e13f0cc8b6630ca6" report "ram module : lookup failure (address A)" severity failure; wait; end process; END;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1561.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c08s10b00x00p03n01i01561ent IS END c08s10b00x00p03n01i01561ent; ARCHITECTURE c08s10b00x00p03n01i01561arch OF c08s10b00x00p03n01i01561ent IS BEGIN TESTING: PROCESS variable s : integer := 0; BEGIN L : for i in 1 to 10 loop next K when i = 3; s := s + 1; end loop L; assert FALSE report "***FAILED TEST: c08s10b00x00p03n01i01561 - A next statement with a label loop must be inside that loop" severity ERROR; wait; END PROCESS TESTING; END c08s10b00x00p03n01i01561arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1561.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c08s10b00x00p03n01i01561ent IS END c08s10b00x00p03n01i01561ent; ARCHITECTURE c08s10b00x00p03n01i01561arch OF c08s10b00x00p03n01i01561ent IS BEGIN TESTING: PROCESS variable s : integer := 0; BEGIN L : for i in 1 to 10 loop next K when i = 3; s := s + 1; end loop L; assert FALSE report "***FAILED TEST: c08s10b00x00p03n01i01561 - A next statement with a label loop must be inside that loop" severity ERROR; wait; END PROCESS TESTING; END c08s10b00x00p03n01i01561arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc1561.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $ -- $Revision: 1.2 $ -- -- --------------------------------------------------------------------- ENTITY c08s10b00x00p03n01i01561ent IS END c08s10b00x00p03n01i01561ent; ARCHITECTURE c08s10b00x00p03n01i01561arch OF c08s10b00x00p03n01i01561ent IS BEGIN TESTING: PROCESS variable s : integer := 0; BEGIN L : for i in 1 to 10 loop next K when i = 3; s := s + 1; end loop L; assert FALSE report "***FAILED TEST: c08s10b00x00p03n01i01561 - A next statement with a label loop must be inside that loop" severity ERROR; wait; END PROCESS TESTING; END c08s10b00x00p03n01i01561arch;
architecture test of test2 is constant foo : bar; begin end;
LIBRARY ieee; LIBRARY work; LIBRARY lpm; USE lpm.all; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** ALTERA FLOATING POINT DATAPATH COMPILER *** --*** *** --*** HCC_ADDPIPES.VHD *** --*** *** --*** Function: Synthesizable Pipelined Adder *** --*** *** --*** 14/07/07 ML *** --*** *** --*** (c) 2007 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY hcc_addpipes IS GENERIC ( width : positive := 64; pipes : positive := 1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1); carryin : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); END hcc_addpipes; ARCHITECTURE syn of hcc_addpipes IS component lpm_add_sub GENERIC ( lpm_direction : STRING; lpm_hint : STRING; lpm_pipeline : NATURAL; lpm_type : STRING; lpm_width : NATURAL ); PORT ( dataa : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0); datab : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0); cin : IN STD_LOGIC ; clken : IN STD_LOGIC ; aclr : IN STD_LOGIC ; clock : IN STD_LOGIC ; result : OUT STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0) ); end component; BEGIN addtwo: lpm_add_sub GENERIC MAP ( lpm_direction => "ADD", lpm_hint => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=YES", lpm_pipeline => pipes, lpm_type => "LPM_ADD_SUB", lpm_width => width ) PORT MAP ( dataa => aa, datab => bb, cin => carryin, clken => enable, aclr => reset, clock => sysclk, result => cc ); END syn;
LIBRARY ieee; LIBRARY work; LIBRARY lpm; USE lpm.all; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** ALTERA FLOATING POINT DATAPATH COMPILER *** --*** *** --*** HCC_ADDPIPES.VHD *** --*** *** --*** Function: Synthesizable Pipelined Adder *** --*** *** --*** 14/07/07 ML *** --*** *** --*** (c) 2007 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY hcc_addpipes IS GENERIC ( width : positive := 64; pipes : positive := 1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1); carryin : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); END hcc_addpipes; ARCHITECTURE syn of hcc_addpipes IS component lpm_add_sub GENERIC ( lpm_direction : STRING; lpm_hint : STRING; lpm_pipeline : NATURAL; lpm_type : STRING; lpm_width : NATURAL ); PORT ( dataa : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0); datab : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0); cin : IN STD_LOGIC ; clken : IN STD_LOGIC ; aclr : IN STD_LOGIC ; clock : IN STD_LOGIC ; result : OUT STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0) ); end component; BEGIN addtwo: lpm_add_sub GENERIC MAP ( lpm_direction => "ADD", lpm_hint => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=YES", lpm_pipeline => pipes, lpm_type => "LPM_ADD_SUB", lpm_width => width ) PORT MAP ( dataa => aa, datab => bb, cin => carryin, clken => enable, aclr => reset, clock => sysclk, result => cc ); END syn;
LIBRARY ieee; LIBRARY work; LIBRARY lpm; USE lpm.all; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** ALTERA FLOATING POINT DATAPATH COMPILER *** --*** *** --*** HCC_ADDPIPES.VHD *** --*** *** --*** Function: Synthesizable Pipelined Adder *** --*** *** --*** 14/07/07 ML *** --*** *** --*** (c) 2007 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY hcc_addpipes IS GENERIC ( width : positive := 64; pipes : positive := 1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1); carryin : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); END hcc_addpipes; ARCHITECTURE syn of hcc_addpipes IS component lpm_add_sub GENERIC ( lpm_direction : STRING; lpm_hint : STRING; lpm_pipeline : NATURAL; lpm_type : STRING; lpm_width : NATURAL ); PORT ( dataa : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0); datab : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0); cin : IN STD_LOGIC ; clken : IN STD_LOGIC ; aclr : IN STD_LOGIC ; clock : IN STD_LOGIC ; result : OUT STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0) ); end component; BEGIN addtwo: lpm_add_sub GENERIC MAP ( lpm_direction => "ADD", lpm_hint => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=YES", lpm_pipeline => pipes, lpm_type => "LPM_ADD_SUB", lpm_width => width ) PORT MAP ( dataa => aa, datab => bb, cin => carryin, clken => enable, aclr => reset, clock => sysclk, result => cc ); END syn;
LIBRARY ieee; LIBRARY work; LIBRARY lpm; USE lpm.all; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** ALTERA FLOATING POINT DATAPATH COMPILER *** --*** *** --*** HCC_ADDPIPES.VHD *** --*** *** --*** Function: Synthesizable Pipelined Adder *** --*** *** --*** 14/07/07 ML *** --*** *** --*** (c) 2007 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY hcc_addpipes IS GENERIC ( width : positive := 64; pipes : positive := 1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1); carryin : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); END hcc_addpipes; ARCHITECTURE syn of hcc_addpipes IS component lpm_add_sub GENERIC ( lpm_direction : STRING; lpm_hint : STRING; lpm_pipeline : NATURAL; lpm_type : STRING; lpm_width : NATURAL ); PORT ( dataa : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0); datab : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0); cin : IN STD_LOGIC ; clken : IN STD_LOGIC ; aclr : IN STD_LOGIC ; clock : IN STD_LOGIC ; result : OUT STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0) ); end component; BEGIN addtwo: lpm_add_sub GENERIC MAP ( lpm_direction => "ADD", lpm_hint => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=YES", lpm_pipeline => pipes, lpm_type => "LPM_ADD_SUB", lpm_width => width ) PORT MAP ( dataa => aa, datab => bb, cin => carryin, clken => enable, aclr => reset, clock => sysclk, result => cc ); END syn;
LIBRARY ieee; LIBRARY work; LIBRARY lpm; USE lpm.all; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** ALTERA FLOATING POINT DATAPATH COMPILER *** --*** *** --*** HCC_ADDPIPES.VHD *** --*** *** --*** Function: Synthesizable Pipelined Adder *** --*** *** --*** 14/07/07 ML *** --*** *** --*** (c) 2007 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY hcc_addpipes IS GENERIC ( width : positive := 64; pipes : positive := 1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1); carryin : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); END hcc_addpipes; ARCHITECTURE syn of hcc_addpipes IS component lpm_add_sub GENERIC ( lpm_direction : STRING; lpm_hint : STRING; lpm_pipeline : NATURAL; lpm_type : STRING; lpm_width : NATURAL ); PORT ( dataa : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0); datab : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0); cin : IN STD_LOGIC ; clken : IN STD_LOGIC ; aclr : IN STD_LOGIC ; clock : IN STD_LOGIC ; result : OUT STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0) ); end component; BEGIN addtwo: lpm_add_sub GENERIC MAP ( lpm_direction => "ADD", lpm_hint => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=YES", lpm_pipeline => pipes, lpm_type => "LPM_ADD_SUB", lpm_width => width ) PORT MAP ( dataa => aa, datab => bb, cin => carryin, clken => enable, aclr => reset, clock => sysclk, result => cc ); END syn;
LIBRARY ieee; LIBRARY work; LIBRARY lpm; USE lpm.all; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** ALTERA FLOATING POINT DATAPATH COMPILER *** --*** *** --*** HCC_ADDPIPES.VHD *** --*** *** --*** Function: Synthesizable Pipelined Adder *** --*** *** --*** 14/07/07 ML *** --*** *** --*** (c) 2007 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY hcc_addpipes IS GENERIC ( width : positive := 64; pipes : positive := 1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1); carryin : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); END hcc_addpipes; ARCHITECTURE syn of hcc_addpipes IS component lpm_add_sub GENERIC ( lpm_direction : STRING; lpm_hint : STRING; lpm_pipeline : NATURAL; lpm_type : STRING; lpm_width : NATURAL ); PORT ( dataa : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0); datab : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0); cin : IN STD_LOGIC ; clken : IN STD_LOGIC ; aclr : IN STD_LOGIC ; clock : IN STD_LOGIC ; result : OUT STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0) ); end component; BEGIN addtwo: lpm_add_sub GENERIC MAP ( lpm_direction => "ADD", lpm_hint => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=YES", lpm_pipeline => pipes, lpm_type => "LPM_ADD_SUB", lpm_width => width ) PORT MAP ( dataa => aa, datab => bb, cin => carryin, clken => enable, aclr => reset, clock => sysclk, result => cc ); END syn;
LIBRARY ieee; LIBRARY work; LIBRARY lpm; USE lpm.all; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** ALTERA FLOATING POINT DATAPATH COMPILER *** --*** *** --*** HCC_ADDPIPES.VHD *** --*** *** --*** Function: Synthesizable Pipelined Adder *** --*** *** --*** 14/07/07 ML *** --*** *** --*** (c) 2007 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY hcc_addpipes IS GENERIC ( width : positive := 64; pipes : positive := 1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1); carryin : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); END hcc_addpipes; ARCHITECTURE syn of hcc_addpipes IS component lpm_add_sub GENERIC ( lpm_direction : STRING; lpm_hint : STRING; lpm_pipeline : NATURAL; lpm_type : STRING; lpm_width : NATURAL ); PORT ( dataa : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0); datab : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0); cin : IN STD_LOGIC ; clken : IN STD_LOGIC ; aclr : IN STD_LOGIC ; clock : IN STD_LOGIC ; result : OUT STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0) ); end component; BEGIN addtwo: lpm_add_sub GENERIC MAP ( lpm_direction => "ADD", lpm_hint => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=YES", lpm_pipeline => pipes, lpm_type => "LPM_ADD_SUB", lpm_width => width ) PORT MAP ( dataa => aa, datab => bb, cin => carryin, clken => enable, aclr => reset, clock => sysclk, result => cc ); END syn;
LIBRARY ieee; LIBRARY work; LIBRARY lpm; USE lpm.all; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** ALTERA FLOATING POINT DATAPATH COMPILER *** --*** *** --*** HCC_ADDPIPES.VHD *** --*** *** --*** Function: Synthesizable Pipelined Adder *** --*** *** --*** 14/07/07 ML *** --*** *** --*** (c) 2007 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY hcc_addpipes IS GENERIC ( width : positive := 64; pipes : positive := 1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1); carryin : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); END hcc_addpipes; ARCHITECTURE syn of hcc_addpipes IS component lpm_add_sub GENERIC ( lpm_direction : STRING; lpm_hint : STRING; lpm_pipeline : NATURAL; lpm_type : STRING; lpm_width : NATURAL ); PORT ( dataa : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0); datab : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0); cin : IN STD_LOGIC ; clken : IN STD_LOGIC ; aclr : IN STD_LOGIC ; clock : IN STD_LOGIC ; result : OUT STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0) ); end component; BEGIN addtwo: lpm_add_sub GENERIC MAP ( lpm_direction => "ADD", lpm_hint => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=YES", lpm_pipeline => pipes, lpm_type => "LPM_ADD_SUB", lpm_width => width ) PORT MAP ( dataa => aa, datab => bb, cin => carryin, clken => enable, aclr => reset, clock => sysclk, result => cc ); END syn;
LIBRARY ieee; LIBRARY work; LIBRARY lpm; USE lpm.all; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** ALTERA FLOATING POINT DATAPATH COMPILER *** --*** *** --*** HCC_ADDPIPES.VHD *** --*** *** --*** Function: Synthesizable Pipelined Adder *** --*** *** --*** 14/07/07 ML *** --*** *** --*** (c) 2007 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY hcc_addpipes IS GENERIC ( width : positive := 64; pipes : positive := 1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1); carryin : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); END hcc_addpipes; ARCHITECTURE syn of hcc_addpipes IS component lpm_add_sub GENERIC ( lpm_direction : STRING; lpm_hint : STRING; lpm_pipeline : NATURAL; lpm_type : STRING; lpm_width : NATURAL ); PORT ( dataa : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0); datab : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0); cin : IN STD_LOGIC ; clken : IN STD_LOGIC ; aclr : IN STD_LOGIC ; clock : IN STD_LOGIC ; result : OUT STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0) ); end component; BEGIN addtwo: lpm_add_sub GENERIC MAP ( lpm_direction => "ADD", lpm_hint => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=YES", lpm_pipeline => pipes, lpm_type => "LPM_ADD_SUB", lpm_width => width ) PORT MAP ( dataa => aa, datab => bb, cin => carryin, clken => enable, aclr => reset, clock => sysclk, result => cc ); END syn;
LIBRARY ieee; LIBRARY work; LIBRARY lpm; USE lpm.all; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** ALTERA FLOATING POINT DATAPATH COMPILER *** --*** *** --*** HCC_ADDPIPES.VHD *** --*** *** --*** Function: Synthesizable Pipelined Adder *** --*** *** --*** 14/07/07 ML *** --*** *** --*** (c) 2007 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY hcc_addpipes IS GENERIC ( width : positive := 64; pipes : positive := 1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1); carryin : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); END hcc_addpipes; ARCHITECTURE syn of hcc_addpipes IS component lpm_add_sub GENERIC ( lpm_direction : STRING; lpm_hint : STRING; lpm_pipeline : NATURAL; lpm_type : STRING; lpm_width : NATURAL ); PORT ( dataa : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0); datab : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0); cin : IN STD_LOGIC ; clken : IN STD_LOGIC ; aclr : IN STD_LOGIC ; clock : IN STD_LOGIC ; result : OUT STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0) ); end component; BEGIN addtwo: lpm_add_sub GENERIC MAP ( lpm_direction => "ADD", lpm_hint => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=YES", lpm_pipeline => pipes, lpm_type => "LPM_ADD_SUB", lpm_width => width ) PORT MAP ( dataa => aa, datab => bb, cin => carryin, clken => enable, aclr => reset, clock => sysclk, result => cc ); END syn;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc695.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $ -- $Revision: 1.3 $ -- -- --------------------------------------------------------------------- -- **************************** -- -- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:05 1996 -- -- **************************** -- -- **************************** -- -- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:39 1996 -- -- **************************** -- -- **************************** -- -- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:43 1996 -- -- **************************** -- ENTITY c03s04b01x00p23n01i00695ent IS END c03s04b01x00p23n01i00695ent; ARCHITECTURE c03s04b01x00p23n01i00695arch OF c03s04b01x00p23n01i00695ent IS BEGIN TESTING: PROCESS -- Declare the type and the file. type FT is file of BOOLEAN; -- Declare the actual file to read. file FILEV : FT open read_mode is "iofile.10"; -- Declare a variable into which we will read. constant CON : BOOLEAN := TRUE; variable VAR : BOOLEAN; variable k : integer := 0; BEGIN -- Read in the file. for I in 1 to 100 loop if (ENDFILE( FILEV ) /= FALSE) then k := 1; end if; assert( (ENDFILE( FILEV ) = FALSE) ) report "Hit the end of file too soon."; READ( FILEV,VAR ); if (VAR /= CON) then k := 1; end if; end loop; -- Verify that we are at the end. if (ENDFILE( FILEV ) /= TRUE) then k := 1; end if; assert( ENDFILE( FILEV ) = TRUE ) report "Have not reached end of file yet." severity ERROR; assert NOT( k = 0 ) report "***PASSED TEST: c03s04b01x00p23n01i00695" severity NOTE; assert( k = 0 ) report "***FAILED TEST: c03s04b01x00p23n01i00695 - The variables don't equal the constants." severity ERROR; wait; END PROCESS TESTING; END c03s04b01x00p23n01i00695arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc695.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $ -- $Revision: 1.3 $ -- -- --------------------------------------------------------------------- -- **************************** -- -- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:05 1996 -- -- **************************** -- -- **************************** -- -- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:39 1996 -- -- **************************** -- -- **************************** -- -- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:43 1996 -- -- **************************** -- ENTITY c03s04b01x00p23n01i00695ent IS END c03s04b01x00p23n01i00695ent; ARCHITECTURE c03s04b01x00p23n01i00695arch OF c03s04b01x00p23n01i00695ent IS BEGIN TESTING: PROCESS -- Declare the type and the file. type FT is file of BOOLEAN; -- Declare the actual file to read. file FILEV : FT open read_mode is "iofile.10"; -- Declare a variable into which we will read. constant CON : BOOLEAN := TRUE; variable VAR : BOOLEAN; variable k : integer := 0; BEGIN -- Read in the file. for I in 1 to 100 loop if (ENDFILE( FILEV ) /= FALSE) then k := 1; end if; assert( (ENDFILE( FILEV ) = FALSE) ) report "Hit the end of file too soon."; READ( FILEV,VAR ); if (VAR /= CON) then k := 1; end if; end loop; -- Verify that we are at the end. if (ENDFILE( FILEV ) /= TRUE) then k := 1; end if; assert( ENDFILE( FILEV ) = TRUE ) report "Have not reached end of file yet." severity ERROR; assert NOT( k = 0 ) report "***PASSED TEST: c03s04b01x00p23n01i00695" severity NOTE; assert( k = 0 ) report "***FAILED TEST: c03s04b01x00p23n01i00695 - The variables don't equal the constants." severity ERROR; wait; END PROCESS TESTING; END c03s04b01x00p23n01i00695arch;
-- Copyright (C) 2001 Bill Billowitch. -- Some of the work to develop this test suite was done with Air Force -- support. The Air Force and Bill Billowitch assume no -- responsibilities for this software. -- This file is part of VESTs (Vhdl tESTs). -- VESTs is free software; you can redistribute it and/or modify it -- under the terms of the GNU General Public License as published by the -- Free Software Foundation; either version 2 of the License, or (at -- your option) any later version. -- VESTs is distributed in the hope that it will be useful, but WITHOUT -- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -- for more details. -- You should have received a copy of the GNU General Public License -- along with VESTs; if not, write to the Free Software Foundation, -- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- --------------------------------------------------------------------- -- -- $Id: tc695.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $ -- $Revision: 1.3 $ -- -- --------------------------------------------------------------------- -- **************************** -- -- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:05 1996 -- -- **************************** -- -- **************************** -- -- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:39 1996 -- -- **************************** -- -- **************************** -- -- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:43 1996 -- -- **************************** -- ENTITY c03s04b01x00p23n01i00695ent IS END c03s04b01x00p23n01i00695ent; ARCHITECTURE c03s04b01x00p23n01i00695arch OF c03s04b01x00p23n01i00695ent IS BEGIN TESTING: PROCESS -- Declare the type and the file. type FT is file of BOOLEAN; -- Declare the actual file to read. file FILEV : FT open read_mode is "iofile.10"; -- Declare a variable into which we will read. constant CON : BOOLEAN := TRUE; variable VAR : BOOLEAN; variable k : integer := 0; BEGIN -- Read in the file. for I in 1 to 100 loop if (ENDFILE( FILEV ) /= FALSE) then k := 1; end if; assert( (ENDFILE( FILEV ) = FALSE) ) report "Hit the end of file too soon."; READ( FILEV,VAR ); if (VAR /= CON) then k := 1; end if; end loop; -- Verify that we are at the end. if (ENDFILE( FILEV ) /= TRUE) then k := 1; end if; assert( ENDFILE( FILEV ) = TRUE ) report "Have not reached end of file yet." severity ERROR; assert NOT( k = 0 ) report "***PASSED TEST: c03s04b01x00p23n01i00695" severity NOTE; assert( k = 0 ) report "***FAILED TEST: c03s04b01x00p23n01i00695 - The variables don't equal the constants." severity ERROR; wait; END PROCESS TESTING; END c03s04b01x00p23n01i00695arch;
library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.ALL; entity FIFO_data_path is generic ( DATA_WIDTH: integer := 32 ); port ( reset: in std_logic; clk: in std_logic; RX: in std_logic_vector(DATA_WIDTH-1 downto 0); read_pointer, write_pointer: in std_logic_vector(3 downto 0); write_en : in std_logic; Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0) ); end FIFO_data_path; architecture behavior of FIFO_data_path is signal FIFO_MEM_1 , FIFO_MEM_1_in : std_logic_vector(DATA_WIDTH-1 downto 0); signal FIFO_MEM_2 , FIFO_MEM_2_in : std_logic_vector(DATA_WIDTH-1 downto 0); signal FIFO_MEM_3 , FIFO_MEM_3_in : std_logic_vector(DATA_WIDTH-1 downto 0); signal FIFO_MEM_4 , FIFO_MEM_4_in : std_logic_vector(DATA_WIDTH-1 downto 0); begin process (clk, reset)begin if reset = '0' then FIFO_MEM_1 <= (others=>'0'); FIFO_MEM_2 <= (others=>'0'); FIFO_MEM_3 <= (others=>'0'); FIFO_MEM_4 <= (others=>'0'); elsif clk'event and clk = '1' then if write_en = '1' then --write into the memory FIFO_MEM_1 <= FIFO_MEM_1_in; FIFO_MEM_2 <= FIFO_MEM_2_in; FIFO_MEM_3 <= FIFO_MEM_3_in; FIFO_MEM_4 <= FIFO_MEM_4_in; end if; end if; end process; process(RX, write_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4)begin case( write_pointer ) is when "0001" => FIFO_MEM_1_in <= RX; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4; when "0010" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= RX; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4; when "0100" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= RX; FIFO_MEM_4_in <= FIFO_MEM_4; when "1000" => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= RX; when others => FIFO_MEM_1_in <= FIFO_MEM_1; FIFO_MEM_2_in <= FIFO_MEM_2; FIFO_MEM_3_in <= FIFO_MEM_3; FIFO_MEM_4_in <= FIFO_MEM_4; end case ; end process; process(read_pointer, FIFO_MEM_1, FIFO_MEM_2, FIFO_MEM_3, FIFO_MEM_4)begin case( read_pointer ) is when "0001" => Data_out <= FIFO_MEM_1; when "0010" => Data_out <= FIFO_MEM_2; when "0100" => Data_out <= FIFO_MEM_3; when "1000" => Data_out <= FIFO_MEM_4; when others => Data_out <= FIFO_MEM_1; end case ; end process; end behavior;
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*- -- vim: tabstop=2:shiftwidth=2:noexpandtab -- kate: tab-width 2; replace-tabs off; indent-width 2; -- ============================================================================= -- Authors: Patrick Lehmann -- -- Package: Project specific configuration. -- -- Description: -- ------------------------------------ -- Configuration file for a Xilinx KCU105 board. -- -- -- License: -- ============================================================================= -- Copyright 2017-2020 Patrick Lehmann - Boetzingen, Germany -- -- Licensed under the Apache License, Version 2.0 (the "License"); -- you may not use this file except in compliance with the License. -- You may obtain a copy of the License at -- -- http://www.apache.org/licenses/LICENSE-2.0 -- -- Unless required by applicable law or agreed to in writing, software -- distributed under the License is distributed on an "AS IS" BASIS, -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -- See the License for the specific language governing permissions and -- limitations under the License. -- ============================================================================= -- -- package my_config is -- Change these lines to setup configuration. constant MY_BOARD : string := "KCU105"; -- KCU105 - Xilinx Kintex UltraScale reference design board: XCKU040 constant MY_DEVICE : string := "None"; -- infer from MY_BOARD -- constant MY_VERBOSE : boolean := FALSE; -- activate detailed report statements in functions and procedures end package;
--------------------------------------------------------------------------- -- -- Title: Hardware Thread User Logic Quicksort -- Thread implements the quicksort algorithm -- Passed in argument is a pointer to following struct -- struct sortData { -- int * startData; //pointer to start of array -- int * endData; //pointer to end of array -- int cacheOption // 1 operate on data where it is, 0 copy into HWTI first -- There is not return argument, the HWT just sorts the data. -- --------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; use IEEE.std_logic_misc.all; library Unisim; use Unisim.all; --------------------------------------------------------------------------- -- Port declarations --------------------------------------------------------------------------- -- Definition of Ports: -- -- Misc. Signals -- clock -- -- HWTI to HWTUL interconnect -- intrfc2thrd_address 32 bits memory -- intrfc2thrd_value 32 bits memory function -- intrfc2thrd_function 16 bits control -- intrfc2thrd_goWait 1 bits control -- -- HWTUL to HWTI interconnect -- thrd2intrfc_address 32 bits memory -- thrd2intrfc_value 32 bits memory function -- thrd2intrfc_function 16 bits function -- thrd2intrfc_opcode 6 bits memory function -- --------------------------------------------------------------------------- -- Thread Manager Entity section --------------------------------------------------------------------------- entity user_logic_hwtul is port ( clock : in std_logic; intrfc2thrd_address : in std_logic_vector(0 to 31); intrfc2thrd_value : in std_logic_vector(0 to 31); intrfc2thrd_function : in std_logic_vector(0 to 15); intrfc2thrd_goWait : in std_logic; thrd2intrfc_address : out std_logic_vector(0 to 31); thrd2intrfc_value : out std_logic_vector(0 to 31); thrd2intrfc_function : out std_logic_vector(0 to 15); thrd2intrfc_opcode : out std_logic_vector(0 to 5) ); end entity user_logic_hwtul; --------------------------------------------------------------------------- -- Architecture section --------------------------------------------------------------------------- architecture IMP of user_logic_hwtul is --------------------------------------------------------------------------- -- Signal declarations --------------------------------------------------------------------------- type state_machine is ( FUNCTION_RESET, FUNCTION_USER_SELECT, FUNCTION_START, READ_SORTDATA_1, READ_SORTDATA_2, READ_SORTDATA_3, READ_SORTDATA_4, READ_SORTDATA_5, READ_SORTDATA_6, READ_SORTDATA_7, READ_SORTDATA_8, COPY_DATA_1, COPY_DATA_2, COPY_DATA_3, COPY_DATA_4, COPY_DATA_5, COPY_DATA_6, COPY_DATA_7, RECOPY_DATA_1, RECOPY_DATA_2, RECOPY_DATA_3, RECOPY_DATA_4, FREE_1, FREE_2, CALL_QSORT_1, CALL_QSORT_2, CALL_QSORT_3, READ_ARRAY_1, READ_ARRAY_2, READ_ARRAY_3, READ_ARRAY_4, READ_ARRAY_5, READ_ARRAY_6, EXIT_THREAD_1, EXIT_THREAD_2, QUICKSORT_1, QUICKSORT_2, QUICKSORT_3, QUICKSORT_4, QUICKSORT_5, QUICKSORT_6, QUICKSORT_7, QUICKSORT_8, QUICKSORT_9, QUICKSORT_A, QUICKSORT_B, QUICKSORT_DO, QUICKSORT_WHILE_LEFT_0, QUICKSORT_WHILE_LEFT_1, QUICKSORT_WHILE_LEFT_2, QUICKSORT_WHILE_LEFT_3, QUICKSORT_BREAK, QUICKSORT_WHILE_RIGHT_1, QUICKSORT_WHILE_RIGHT_2, QUICKSORT_WHILE_RIGHT_3, QUICKSORT_SWAP_1, QUICKSORT_SWAP_2, QUICKSORT_SWAP_3, QUICKSORT_SWAP_4, QUICKSORT_SWAP_5, QUICKSORT_WHILE, QUICKSORT_CALL_QS_0, QUICKSORT_CALL_QS_1, QUICKSORT_CALL_QS_2, QUICKSORT_CALL_QS_3, QUICKSORT_CALL_QS_4, QUICKSORT_CALL_QS_5, QUICKSORT_CALL_QS_6, QUICKSORT_CALL_QS_7, QUICKSORT_CALL_QS_8, QUICKSORT_CALL_QS_9, QUICKSORT_CALL_QS_A, QUICKSORT_RETURN, WAIT_STATE, ERROR_STATE); -- Function definitions constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000"; constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001"; constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002"; constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003"; constant U_READ_SORTDATA_5 : std_logic_vector(0 to 15) := x"0007"; constant U_COPY_DATA_3 : std_logic_vector(0 to 15) := x"0053"; constant U_READ_ARRAY_1 : std_logic_vector(0 to 15) := x"0031"; constant U_EXIT_THREAD_1 : std_logic_vector(0 to 15) := x"0021"; constant U_FREE_1 : std_logic_vector(0 to 15) := x"0041"; constant U_QUICKSORT_1 : std_logic_vector(0 to 15) := x"0101"; constant U_QUICKSORT_CALL_QS_6 : std_logic_vector(0 to 15) := x"0171"; constant U_QUICKSORT_RETURN : std_logic_vector(0 to 15) := x"0181"; -- Range 0003 to 7999 reserved for user logic's state machine -- Range 8000 to 9999 reserved for system calls -- constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000"; -- constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001"; -- constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010"; -- constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011"; constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012"; constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013"; constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014"; constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015"; constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016"; -- constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020"; -- constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021"; -- constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022"; -- constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023"; -- constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030"; -- constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031"; -- constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032"; -- constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033"; -- constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034"; -- constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040"; -- constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041"; -- constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042"; -- constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043"; -- constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050"; -- constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051"; -- constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052"; -- constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053"; -- constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054"; -- Ranged A000 to FFFF reserved for supported library calls constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000"; constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001"; constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002"; constant FUNCTION_MEMCPY : std_logic_vector(0 to 15) := x"A100"; -- user_opcode Constants constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000"; -- Memory sub-interface specific opcodes constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001"; constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010"; constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011"; constant OPCODE_READ : std_logic_vector(0 to 5) := "000100"; constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101"; constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110"; -- Function sub-interface specific opcodes constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000"; constant OPCODE_POP : std_logic_vector(0 to 5) := "010001"; constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010"; constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011"; constant Z32 : std_logic_vector(0 to 31) := (others => '0'); signal current_state, next_state : state_machine := FUNCTION_RESET; signal return_state, return_state_next : state_machine := FUNCTION_RESET; signal startPtr, startPtr_next : std_logic_vector(0 to 31); signal endPtr, endPtr_next : std_logic_vector(0 to 31); signal leftPtr, leftPtr_next : std_logic_vector(0 to 31); signal rightPtr, rightPtr_next : std_logic_vector(0 to 31); signal left, left_next : std_logic_vector(0 to 31); signal right, right_next : std_logic_vector(0 to 31); signal pivot, pivot_next : std_logic_vector(0 to 31); signal cache, cache_next : std_logic; signal toUser_address : std_logic_vector(0 to 31); signal toUser_value : std_logic_vector(0 to 31); signal toUser_function : std_logic_vector(0 to 15); signal toUser_goWait : std_logic; --------------------------------------------------------------------------- -- Begin architecture --------------------------------------------------------------------------- begin -- architecture IMP HWTUL_STATE_PROCESS : process (clock) is begin if (clock'event and (clock = '1')) then toUser_address <= intrfc2thrd_address; toUser_value <= intrfc2thrd_value; toUser_function <= intrfc2thrd_function; toUser_goWait <= intrfc2thrd_goWait; startPtr <= startPtr_next; endPtr <= endPtr_next; leftPtr <= leftPtr_next; rightPtr <= rightPtr_next; left <= left_next; right <= right_next; pivot <= pivot_next; cache <= cache_next; return_state <= return_state_next; -- Find out if the HWTI is tell us what to do if (intrfc2thrd_goWait = '1') then case intrfc2thrd_function is -- Typically the HWTI will tell us to control our own destiny when U_FUNCTION_USER_SELECT => current_state <= next_state; -- List all the functions the HWTI could tell us to run when U_FUNCTION_RESET => current_state <= FUNCTION_RESET; when U_FUNCTION_START => current_state <= FUNCTION_START; when U_READ_SORTDATA_5 => current_state <= READ_SORTDATA_5; when U_COPY_DATA_3 => current_state <= COPY_DATA_3; when U_READ_ARRAY_1 => current_state <= READ_ARRAY_1; when U_FREE_1 => current_state <= FREE_1; when U_EXIT_THREAD_1 => current_state <= EXIT_THREAD_1; when U_QUICKSORT_1 => current_state <= QUICKSORT_1; when U_QUICKSORT_CALL_QS_6 => current_state <= QUICKSORT_CALL_QS_6; when U_QUICKSORT_RETURN => current_state <= QUICKSORT_RETURN; -- If the HWTI tells us to do something we don't know, error when OTHERS => current_state <= ERROR_STATE; end case; else current_state <= WAIT_STATE; end if; end if; end process HWTUL_STATE_PROCESS; HWTUL_STATE_MACHINE : process (current_state) is begin -- Default register assignments thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse thrd2intrfc_address <= Z32; thrd2intrfc_value <= Z32; thrd2intrfc_function <= U_FUNCTION_USER_SELECT; next_state <= current_state; return_state_next <= return_state; startPtr_next <= startPtr; endPtr_next <= endPtr; leftPtr_next <= leftPtr; rightPtr_next <= rightPtr; left_next <= left; right_next <= right; pivot_next <= pivot; cache_next <= cache; -- The state machine case current_state is when FUNCTION_RESET => --Set default values thrd2intrfc_opcode <= OPCODE_NOOP; thrd2intrfc_address <= Z32; thrd2intrfc_value <= Z32; thrd2intrfc_function <= U_FUNCTION_START; startPtr_next <= Z32; endPtr_next <= Z32; leftPtr_next <= Z32; rightPtr_next <= Z32; left_next <= Z32; right_next <= Z32; pivot_next <= Z32; cache_next <= '1'; when FUNCTION_START => -- 0002 -- read the passed in argument thrd2intrfc_opcode <= OPCODE_POP; thrd2intrfc_address <= Z32; return_state_next <= READ_SORTDATA_1; next_state <= WAIT_STATE; when READ_SORTDATA_1 => -- 0003 -- The passed in argument is address of struct sortdata -- For the time being, store value in startPtr startPtr_next <= toUser_value; -- Read the endPtr address thrd2intrfc_opcode <= OPCODE_LOAD; thrd2intrfc_address <= toUser_value + 4; return_state_next <= READ_SORTDATA_2; next_state <= WAIT_STATE; when READ_SORTDATA_2 => -- 0004 endPtr_next <= toUser_value; -- Read the cache option thrd2intrfc_opcode <= OPCODE_LOAD; thrd2intrfc_address <= startPtr + 8; return_state_next <= READ_SORTDATA_3; next_state <= WAIT_STATE; when READ_SORTDATA_3 => -- 0005 cache_next <= toUser_value(31); -- Now read the address of startPtr thrd2intrfc_opcode <= OPCODE_LOAD; thrd2intrfc_address <= startPtr; return_state_next <= READ_SORTDATA_4; next_state <= WAIT_STATE; when READ_SORTDATA_4 => -- 0006 startPtr_next <= toUser_value; leftPtr_next <= toUser_value; rightPtr_next <= endPtr; -- Declare four local variables to hold start, end, left, right pointers thrd2intrfc_opcode <= OPCODE_DECLARE; thrd2intrfc_value <= x"00000004"; if ( cache = '1' ) then -- copy the global data locally return_state_next <= COPY_DATA_1; next_state <= WAIT_STATE; else -- work on data where it is return_state_next <= READ_SORTDATA_5; next_state <= WAIT_STATE; end if; when READ_SORTDATA_5 => -- 0007 -- Save the start pointer thrd2intrfc_opcode <= OPCODE_WRITE; thrd2intrfc_address <= Z32; thrd2intrfc_value <= startPtr; return_state_next <= READ_SORTDATA_6; next_state <= WAIT_STATE; when READ_SORTDATA_6 => -- 0008 -- Save the end pointer thrd2intrfc_opcode <= OPCODE_WRITE; thrd2intrfc_address <= x"00000001"; thrd2intrfc_value <= endPtr; return_state_next <= READ_SORTDATA_7; next_state <= WAIT_STATE; when READ_SORTDATA_7 => -- 0009 -- Save the left pointer thrd2intrfc_opcode <= OPCODE_WRITE; thrd2intrfc_address <= x"00000002"; thrd2intrfc_value <= leftPtr; return_state_next <= READ_SORTDATA_8; next_state <= WAIT_STATE; when READ_SORTDATA_8 => -- 000A -- Save the right pointer thrd2intrfc_opcode <= OPCODE_WRITE; thrd2intrfc_address <= x"00000003"; thrd2intrfc_value <= rightPtr; -- Sort the data! return_state_next <= CALL_QSORT_1; next_state <= WAIT_STATE; when CALL_QSORT_1 => -- 0011 -- Push the second argument, endPtr; thrd2intrfc_opcode <= OPCODE_PUSH; thrd2intrfc_value <= rightPtr; return_state_next <= CALL_QSORT_2; next_state <= WAIT_STATE; when CALL_QSORT_2 => -- 0012 -- Push the first argument, startPtr; thrd2intrfc_opcode <= OPCODE_PUSH; thrd2intrfc_value <= leftPtr; return_state_next <= CALL_QSORT_3; next_state <= WAIT_STATE; when CALL_QSORT_3 => -- 0013 -- Call quicksort thrd2intrfc_opcode <= OPCODE_CALL; thrd2intrfc_function <= U_QUICKSORT_1; thrd2intrfc_value <= Z32(0 to 15) & U_READ_ARRAY_1; return_state_next <= WAIT_STATE; next_state <= WAIT_STATE; when READ_ARRAY_1 => -- 0031 -- Read the startPtr from memory thrd2intrfc_opcode <= OPCODE_READ; thrd2intrfc_address <= Z32; return_state_next <= READ_ARRAY_2; next_state <= WAIT_STATE; when READ_ARRAY_2 => -- 0032 startPtr_next <= toUser_value; -- Read the endPtr from memory thrd2intrfc_opcode <= OPCODE_READ; thrd2intrfc_address <= x"00000001"; return_state_next <= READ_ARRAY_3; next_state <= WAIT_STATE; when READ_ARRAY_3 => -- 0033 endPtr_next <= toUser_value; -- Read the leftPtr from memory thrd2intrfc_opcode <= OPCODE_READ; thrd2intrfc_address <= x"00000002"; return_state_next <= READ_ARRAY_4; next_state <= WAIT_STATE; when READ_ARRAY_4 => -- 0034 leftPtr_next <= toUser_value; -- Read the rightPtr from memory thrd2intrfc_opcode <= OPCODE_READ; thrd2intrfc_address <= x"00000003"; return_state_next <= READ_ARRAY_5; next_state <= WAIT_STATE; when READ_ARRAY_5 => -- 0035 rightPtr_next <= toUser_value; next_state <= READ_ARRAY_6; when READ_ARRAY_6 => -- 0037 if ( cache = '1' ) then -- Recopy data next_state <= RECOPY_DATA_1; else next_state <= EXIT_THREAD_1; end if; when RECOPY_DATA_1 => -- 0061 -- Push the number of bytes to allocate to stack thrd2intrfc_opcode <= OPCODE_PUSH; thrd2intrfc_value <= (rightPtr - leftPtr + 4); return_state_next <= RECOPY_DATA_2; next_state <= WAIT_STATE; when RECOPY_DATA_2 => -- 0062 -- Push the address to start cpying from thrd2intrfc_opcode <= OPCODE_PUSH; thrd2intrfc_value <= leftPtr; return_state_next <= RECOPY_DATA_3; next_state <= WAIT_STATE; when RECOPY_DATA_3 => -- 0063 -- Push the address to copy to thrd2intrfc_opcode <= OPCODE_PUSH; thrd2intrfc_value <= startPtr; return_state_next <= RECOPY_DATA_4; next_state <= WAIT_STATE; when RECOPY_DATA_4 => -- 0064 -- Call mempy thrd2intrfc_opcode <= OPCODE_CALL; thrd2intrfc_function <= FUNCTION_MEMCPY; thrd2intrfc_value <= Z32(0 to 15) & U_FREE_1; return_state_next <= WAIT_STATE; next_state <= WAIT_STATE; when FREE_1 => -- Push the address to free thrd2intrfc_opcode <= OPCODE_PUSH; thrd2intrfc_value <= leftPtr; return_state_next <= FREE_2; next_state <= WAIT_STATE; when FREE_2 => -- Call free thrd2intrfc_opcode <= OPCODE_CALL; thrd2intrfc_function <= FUNCTION_FREE; thrd2intrfc_value <= Z32(0 to 15) & U_EXIT_THREAD_1; return_state_next <= WAIT_STATE; next_state <= WAIT_STATE; when COPY_DATA_1 => -- 0051 -- Push the number of bytes to allocate to stack thrd2intrfc_opcode <= OPCODE_PUSH; thrd2intrfc_value <= (endPtr - startPtr + 4); return_state_next <= COPY_DATA_2; next_state <= WAIT_STATE; when COPY_DATA_2 => -- 0052 -- Call the malloc function thrd2intrfc_opcode <= OPCODE_CALL; thrd2intrfc_function <= FUNCTION_MALLOC; thrd2intrfc_value <= Z32(0 to 15) & U_COPY_DATA_3; return_state_next <= WAIT_STATE; next_state <= WAIT_STATE; when COPY_DATA_3 => -- 0053 -- Record the starting address of allocated data leftPtr_next <= toUser_value; -- Calculate the ending address of allocated dta rightPtr_next <= toUser_value + (endPtr - startPtr); -- Copy the data next_state <= COPY_DATA_4; when COPY_DATA_4 => -- 0054 -- Push the number of bytes to copy thrd2intrfc_opcode <= OPCODE_PUSH; thrd2intrfc_value <= (endPtr - startPtr + 4); return_state_next <= COPY_DATA_5; next_state <= WAIT_STATE; when COPY_DATA_5 => -- 0055 -- Push the address to start copying from thrd2intrfc_opcode <= OPCODE_PUSH; thrd2intrfc_value <= startPtr; return_state_next <= COPY_DATA_6; next_state <= WAIT_STATE; when COPY_DATA_6 => -- 0056 -- Push the address to copy data to thrd2intrfc_opcode <= OPCODE_PUSH; thrd2intrfc_value <= leftPtr; return_state_next <= COPY_DATA_7; next_state <= WAIT_STATE; when COPY_DATA_7 => -- 0057 -- Call memcopy thrd2intrfc_opcode <= OPCODE_CALL; thrd2intrfc_function <= FUNCTION_MEMCPY; thrd2intrfc_value <= Z32(0 to 15) & U_READ_SORTDATA_5; return_state_next <= WAIT_STATE; next_state <= WAIT_STATE; when EXIT_THREAD_1 => -- 0021 -- Push a null argument onto stack, as required by hthread_exit; thrd2intrfc_opcode <= OPCODE_PUSH; thrd2intrfc_value <= Z32; return_state_next <= EXIT_THREAD_2; next_state <= WAIT_STATE; when EXIT_THREAD_2 => -- 0022 -- Call exit thread thrd2intrfc_opcode <= OPCODE_CALL; thrd2intrfc_function <= FUNCTION_HTHREAD_EXIT; thrd2intrfc_value <= Z32(0 to 15) & U_FUNCTION_RESET; return_state_next <= WAIT_STATE; next_state <= WAIT_STATE; when ERROR_STATE => -- 7999 next_state <= ERROR_STATE; ----------------------------------------------------------------------- -- Quicksort function -- argument 1 - start pointer -- argument 2 - end pointer ----------------------------------------------------------------------- when QUICKSORT_1 => -- 0101 -- Read the first argument thrd2intrfc_opcode <= OPCODE_POP; thrd2intrfc_value <= Z32; return_state_next <= QUICKSORT_2; next_state <= WAIT_STATE; when QUICKSORT_2 => -- 0102 startPtr_next <= toUser_value; -- Read the second argument thrd2intrfc_opcode <= OPCODE_POP; thrd2intrfc_value <= x"00000001"; return_state_next <= QUICKSORT_3; next_state <= WAIT_STATE; when QUICKSORT_3 => -- 0103 endPtr_next <= toUser_value; next_state <= QUICKSORT_4; when QUICKSORT_4 => -- 0104 -- Declare 5 variables thrd2intrfc_opcode <= OPCODE_DECLARE; thrd2intrfc_value <= x"00000002"; return_state_next <= QUICKSORT_5; next_state <= WAIT_STATE; when QUICKSORT_5 => -- 0105 -- Copy the start and end pointers leftPtr_next <= startPtr; rightPtr_next <= endPtr; next_state <= QUICKSORT_6; when QUICKSORT_6 => -- 0106 -- check to see if left and right pointers are equal if ( leftPtr >= rightPtr ) then -- Nothing to sort, return next_state <= QUICKSORT_RETURN; else next_state <= QUICKSORT_7; end if; when QUICKSORT_7 => -- 0107 -- Read the value of the leftPtr thrd2intrfc_opcode <= OPCODE_LOAD; thrd2intrfc_address <= leftPtr; return_state_next <= QUICKSORT_8; next_state <= WAIT_STATE; when QUICKSORT_8 => -- 0108 left_next <= toUser_value; -- Read the value of the rightPtr thrd2intrfc_opcode <= OPCODE_LOAD; thrd2intrfc_address <= rightPtr; return_state_next <= QUICKSORT_9; next_state <= WAIT_STATE; when QUICKSORT_9 => -- 0109 right_next <= toUser_value; next_state <= QUICKSORT_A; when QUICKSORT_A => -- 010A -- determine the pivot value by first taking sum of left and right pivot_next <= left + right; next_state <= QUICKSORT_B; when QUICKSORT_B => -- 010B -- next divide the sum of left and right by two (or shift) pivot_next <= '0' & pivot(0 to 30); next_state <= QUICKSORT_DO; when QUICKSORT_DO => -- 0111 -- This is a placeholder for my own sanity next_state <= QUICKSORT_WHILE_LEFT_0; when QUICKSORT_WHILE_LEFT_0 => -- 0121 -- check to see if leftPtr moved past rightPtr if ( leftPtr < rightPtr ) then next_state <= QUICKSORT_WHILE_LEFT_1; else leftPtr_next <= rightPtr; next_state <= QUICKSORT_BREAK; end if; when QUICKSORT_WHILE_LEFT_1 => -- 0121 -- check to see if left < pivot if ( left <= pivot ) then -- left does not have to be swapped, increment leftPtr leftPtr_next <= leftPtr + 4; next_state <= QUICKSORT_WHILE_LEFT_2; else -- left needs to be swapped, end the while loop next_state <= QUICKSORT_BREAK; end if; when QUICKSORT_WHILE_LEFT_2 => -- 0122 -- read value of leftPtr thrd2intrfc_opcode <= OPCODE_LOAD; thrd2intrfc_address <= leftPtr; return_state_next <= QUICKSORT_WHILE_LEFT_3; next_state <= WAIT_STATE; when QUICKSORT_WHILE_LEFT_3 => -- 0123 left_next <= toUser_value; next_state <= QUICKSORT_WHILE_LEFT_0; when QUICKSORT_BREAK => -- 0131 -- Check that we did not move past right ptr if ( leftPtr >= rightPtr ) then -- we are done swapping next_state <= QUICKSORT_CALL_QS_0; else next_state <= QUICKSORT_WHILE_RIGHT_1; end if; when QUICKSORT_WHILE_RIGHT_1 => -- 0141 -- check to see if right < pivot if ( right > pivot ) then -- right does not have to be swapped, decrement rightPtr rightPtr_next <= rightPtr - 4; next_state <= QUICKSORT_WHILE_RIGHT_2; else -- right needs to be swapped, end the while loop next_state <= QUICKSORT_SWAP_1; end if; when QUICKSORT_WHILE_RIGHT_2 => -- 0142 -- read value of rightPtr thrd2intrfc_opcode <= OPCODE_LOAD; thrd2intrfc_address <= rightPtr; return_state_next <= QUICKSORT_WHILE_RIGHT_3; next_state <= WAIT_STATE; when QUICKSORT_WHILE_RIGHT_3 => -- 0143 right_next <= toUser_value; next_state <= QUICKSORT_BREAK; when QUICKSORT_SWAP_1 => -- 0151 -- write the value of rightPtr with left thrd2intrfc_opcode <= OPCODE_STORE; thrd2intrfc_address <= rightPtr; thrd2intrfc_value <= left; return_state_next <= QUICKSORT_SWAP_2; next_state <= WAIT_STATE; when QUICKSORT_SWAP_2 => -- 0152 -- write the value of leftPtr with right thrd2intrfc_opcode <= OPCODE_STORE; thrd2intrfc_address <= leftPtr; thrd2intrfc_value <= right; return_state_next <= QUICKSORT_SWAP_3; next_state <= WAIT_STATE; when QUICKSORT_SWAP_3 => -- 0153 -- increment/decrement pointers leftPtr_next <= leftPtr + 4; rightPtr_next <= rightPtr - 4; next_state <= QUICKSORT_SWAP_4; when QUICKSORT_SWAP_4 => -- 0154 -- read new value of left thrd2intrfc_opcode <= OPCODE_LOAD; thrd2intrfc_address <= leftPtr; return_state_next <= QUICKSORT_SWAP_5; next_state <= WAIT_STATE; when QUICKSORT_SWAP_5 => -- 0155 left_next <= toUser_value; -- read new value of right thrd2intrfc_opcode <= OPCODE_LOAD; thrd2intrfc_address <= rightPtr; return_state_next <= QUICKSORT_WHILE; next_state <= WAIT_STATE; when QUICKSORT_WHILE => -- 0161 right_next <= toUser_value; -- check to make sure leftPtr < rightPtr if ( leftPtr < rightPtr ) then next_state <= QUICKSORT_DO; else next_state <= QUICKSORT_CALL_QS_0; end if; when QUICKSORT_CALL_QS_0 => -- 0170 -- Check to see if leftPtr == rightPtr if ( leftPtr = rightPtr ) then -- Check to see if right > pivot if ( right >= pivot ) then leftPtr_next <= rightPtr - 4; else rightPtr_next <= rightPtr + 4; end if; else if ( right > pivot ) then leftPtr_next <= rightPtr - 4; else leftPtr_next <= rightPtr; rightPtr_next <= leftPtr; end if; end if; next_state <= QUICKSORT_CALL_QS_1; when QUICKSORT_CALL_QS_1 => -- 0171 -- Before calling quicksort need to save rightPtr and endPtr -- Save the rightPtr thrd2intrfc_opcode <= OPCODE_WRITE; thrd2intrfc_address <= x"00000000"; thrd2intrfc_value <= rightPtr; return_state_next <= QUICKSORT_CALL_QS_2; next_state <= WAIT_STATE; when QUICKSORT_CALL_QS_2 => -- 0172 -- Save the endPtr thrd2intrfc_opcode <= OPCODE_WRITE; thrd2intrfc_address <= x"00000001"; thrd2intrfc_value <= endPtr; return_state_next <= QUICKSORT_CALL_QS_3; next_state <= WAIT_STATE; when QUICKSORT_CALL_QS_3 => -- 0173 -- Push the leftPtr thrd2intrfc_opcode <= OPCODE_PUSH; thrd2intrfc_value <= leftPtr; return_state_next <= QUICKSORT_CALL_QS_4; next_state <= WAIT_STATE; when QUICKSORT_CALL_QS_4 => -- 0174 -- Push the startPtr thrd2intrfc_opcode <= OPCODE_PUSH; thrd2intrfc_value <= startPtr; return_state_next <= QUICKSORT_CALL_QS_5; next_state <= WAIT_STATE; when QUICKSORT_CALL_QS_5 => -- 0175 -- Call quicksort thrd2intrfc_opcode <= OPCODE_CALL; thrd2intrfc_function <= U_QUICKSORT_1; thrd2intrfc_value <= Z32(0 to 15) & U_QUICKSORT_CALL_QS_6; return_state_next <= WAIT_STATE; next_state <= WAIT_STATE; when QUICKSORT_CALL_QS_6 => -- 0176 -- read the value of endPtr thrd2intrfc_opcode <= OPCODE_READ; thrd2intrfc_address <= x"00000001"; return_state_next <= QUICKSORT_CALL_QS_7; next_state <= WAIT_STATE; when QUICKSORT_CALL_QS_7 => -- 0177 endPtr_next <= toUser_value; -- read the value of rightPtr thrd2intrfc_opcode <= OPCODE_READ; thrd2intrfc_address <= x"00000000"; return_state_next <= QUICKSORT_CALL_QS_8; next_state <= WAIT_STATE; when QUICKSORT_CALL_QS_8 => -- 0178 rightPtr_next <= toUser_value; -- Push the rightPtr thrd2intrfc_opcode <= OPCODE_PUSH; thrd2intrfc_value <= endPtr; return_state_next <= QUICKSORT_CALL_QS_9; next_state <= WAIT_STATE; when QUICKSORT_CALL_QS_9 => -- 0179 -- push the endPtr thrd2intrfc_opcode <= OPCODE_PUSH; thrd2intrfc_value <= rightPtr; return_state_next <= QUICKSORT_CALL_QS_A; next_state <= WAIT_STATE; when QUICKSORT_CALL_QS_A => -- 017A -- Call quicksort thrd2intrfc_opcode <= OPCODE_CALL; thrd2intrfc_function <= U_QUICKSORT_1; thrd2intrfc_value <= Z32(0 to 15) & U_QUICKSORT_RETURN; return_state_next <= WAIT_STATE; next_state <= WAIT_STATE; when QUICKSORT_RETURN => -- 0181 -- Return thrd2intrfc_opcode <= OPCODE_RETURN; thrd2intrfc_value <= Z32; return_state_next <= ERROR_STATE; next_state <= WAIT_STATE; when WAIT_STATE => case toUser_goWait is when '1' => --Here because HWTUL chose to be here for one clock cycle next_state <= return_state; when OTHERS => --ie '0', Here because HWTI is telling us to wait next_state <= return_state; end case; when others => next_state <= ERROR_STATE; end case; end process HWTUL_STATE_MACHINE; end architecture IMP;
-- ----------------------------------------------------------------------- -- -- Turbo Chameleon -- -- Multi purpose FPGA expansion for the Commodore 64 computer -- -- ----------------------------------------------------------------------- -- Copyright 2005-2021 by Peter Wendrich ([email protected]) -- http://www.syntiac.com/chameleon.html -- -- This source file is free software: you can redistribute it and/or modify -- it under the terms of the GNU Lesser General Public License as published -- by the Free Software Foundation, either version 3 of the License, or -- (at your option) any later version. -- -- This source file is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- GNU General Public License for more details. -- -- You should have received a copy of the GNU General Public License -- along with this program. If not, see <http://www.gnu.org/licenses/>. -- -- ----------------------------------------------------------------------- -- -- Part of the Gigatron emulator. -- A SDRAM controller to emulate the 16-bit wide code ROM. -- -- ----------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -- ----------------------------------------------------------------------- entity gigatron_sdram_ctrl is generic ( clk_ticks_per_usec : integer; refresh_period_us : integer := 64000; colbits : integer := 9; rowbits : integer := 13; setup_cycles : integer := 2 ); port ( clk : in std_logic; reset : in std_logic; -- Parameters cas_latency : in unsigned(1 downto 0) := "10"; ras_nops : in unsigned(3 downto 0) := "0001"; write_nops : in unsigned(3 downto 0) := "0000"; precharge_nops : in unsigned(3 downto 0) := "0001"; refresh_nops : in unsigned(3 downto 0) := "0110"; -- Initial ROM image load from spi-flash romload_req : in std_logic; romload_ack : out std_logic; romload_a : in unsigned((rowbits+colbits+2) downto 0); romload_d : in unsigned(7 downto 0); -- Reading of 16-bit ROM data from emulation rom_req : in std_logic; rom_ack : out std_logic; rom_a : in unsigned(15 downto 0); rom_q : out unsigned(15 downto 0); -- SDRAM interface ram_data : inout unsigned(15 downto 0); ram_addr : out unsigned((rowbits-1) downto 0); ram_ba : out unsigned(1 downto 0); ram_we : out std_logic; ram_ras : out std_logic; ram_cas : out std_logic; ram_ldqm : out std_logic; ram_udqm : out std_logic ); end entity; architecture rtl of gigatron_sdram_ctrl is constant refresh_interval : integer := (refresh_period_us * clk_ticks_per_usec) / (2**rowbits); constant refresh_timer_range : integer := refresh_interval*3; type state_t is ( ST_RESET, ST_INIT_PRECHARGE, ST_SETMODE, ST_IDLE, ST_LOADROM_CAS, ST_ROM_CAS, ST_ROM_DATA, ST_REFRESH); signal state_reg : state_t := ST_RESET; signal refresh_timer_reg : integer range 0 to refresh_timer_range := 0; signal timer_reg : unsigned(3 downto 0) := (others => '0'); signal ram_oe_reg : std_logic := '0'; signal ram_ras_reg : std_logic := '1'; signal ram_cas_reg : std_logic := '1'; signal ram_we_reg : std_logic := '1'; signal ram_ba_reg : unsigned(ram_ba'range) := (others => '0'); signal ram_data_reg : unsigned(ram_data'range) := (others => '0'); signal ram_addr_reg : unsigned(ram_addr'range) := (others => '0'); signal ram_ldqm_reg : std_logic := '1'; signal ram_udqm_reg : std_logic := '1'; signal romload_req_reg : std_logic := '0'; signal romload_ack_reg : std_logic := '0'; signal romload_bank : unsigned(ram_ba'range); signal romload_row : unsigned(ram_addr'range); signal romload_col : unsigned(colbits-1 downto 0); signal rom_req_reg : std_logic := '0'; signal rom_ack_reg : std_logic := '0'; signal rom_q_reg : unsigned(rom_q'range) := (others => '0'); signal rom_bank : unsigned(ram_ba'range); signal rom_row : unsigned(ram_addr'range); signal rom_col : unsigned(colbits-1 downto 0); begin romload_ack <= romload_ack_reg; rom_ack <= rom_ack_reg; rom_q <= rom_q_reg; ram_ras <= ram_ras_reg; ram_cas <= ram_cas_reg; ram_we <= ram_we_reg; ram_ba <= ram_ba_reg; ram_data <= ram_data_reg when ram_oe_reg = '1' else (others => 'Z'); ram_addr <= ram_addr_reg; ram_ldqm <= ram_ldqm_reg; ram_udqm <= ram_udqm_reg; romload_bank <= romload_a(rowbits+colbits+2 downto rowbits+colbits+1); romload_row <= romload_a(rowbits+colbits downto colbits+1); romload_col <= romload_a(colbits downto 1); rom_bank <= "00"; rom_row <= "000000" & rom_a(15 downto 9); rom_col <= rom_a(8 downto 0); process(clk) begin if rising_edge(clk) then ram_addr_reg <= (others => '0'); ram_data_reg <= (others => '0'); ram_oe_reg <= '0'; ram_ras_reg <= '1'; ram_cas_reg <= '1'; ram_we_reg <= '1'; ram_ldqm_reg <= '0'; ram_udqm_reg <= '0'; refresh_timer_reg <= refresh_timer_reg + 1; if timer_reg /= 0 then timer_reg <= timer_reg - 1; else case state_reg is when ST_RESET => state_reg <= ST_INIT_PRECHARGE; timer_reg <= (others => '1'); when ST_INIT_PRECHARGE => ram_ras_reg <= '0'; ram_we_reg <= '0'; -- Precharge all banks ram_addr_reg(10) <= '1'; timer_reg <= precharge_nops; state_reg <= ST_SETMODE; when ST_SETMODE => ram_ras_reg <= '0'; ram_cas_reg <= '0'; ram_we_reg <= '0'; ram_ba_reg <= "00"; -- A2-A0=111 burst length, A3=0 sequential, A6-A4 cas-latency, rest reserved or default 0 ram_addr_reg <= "0000000" & cas_latency & "0000"; timer_reg <= to_unsigned(setup_cycles - 1, timer_reg'length); state_reg <= ST_IDLE; when ST_IDLE => if romload_req /= romload_req_reg then romload_req_reg <= romload_req; ram_ras_reg <= '0'; ram_ba_reg <= romload_bank; ram_addr_reg <= romload_row; timer_reg <= ras_nops; state_reg <= ST_LOADROM_CAS; elsif rom_req /= rom_req_reg then rom_req_reg <= rom_req; ram_ras_reg <= '0'; ram_ba_reg <= rom_bank; ram_addr_reg <= rom_row; timer_reg <= ras_nops; state_reg <= ST_ROM_CAS; elsif refresh_timer_reg > refresh_interval then state_reg <= ST_REFRESH; end if; when ST_LOADROM_CAS => ram_cas_reg <= '0'; ram_we_reg <= '0'; ram_ba_reg <= romload_bank; ram_addr_reg(romload_col'range) <= romload_col; ram_addr_reg(10) <= '1'; ram_data_reg <= romload_d & romload_d; ram_oe_reg <= '1'; ram_ldqm_reg <= romload_a(0); ram_udqm_reg <= not romload_a(0); timer_reg <= precharge_nops; romload_ack_reg <= romload_req_reg; state_reg <= ST_IDLE; when ST_ROM_CAS => ram_cas_reg <= '0'; ram_ba_reg <= rom_bank; ram_addr_reg(romload_col'range) <= rom_col; ram_addr_reg(10) <= '1'; timer_reg <= "0010"; if cas_latency = 3 then timer_reg <= "0011"; end if; state_reg <= ST_ROM_DATA; when ST_ROM_DATA => rom_q_reg <= ram_data; rom_ack_reg <= rom_req_reg; state_reg <= ST_IDLE; when ST_REFRESH => refresh_timer_reg <= refresh_timer_reg - refresh_interval; timer_reg <= refresh_nops; ram_ras_reg <= '0'; ram_cas_reg <= '0'; state_reg <= ST_IDLE; end case; end if; if reset = '1' then state_reg <= ST_RESET; romload_req_reg <= romload_req; romload_ack_reg <= romload_req; rom_req_reg <= rom_req; rom_ack_reg <= rom_req; end if; end if; end process; end architecture;
--Copyright (C) 2016 Siavoosh Payandeh Azad and Behrad Niazmand library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.ALL; entity FIFO_credit_based_control_part_checkers is port ( valid_in: in std_logic; read_en_N : in std_logic; read_en_E : in std_logic; read_en_W : in std_logic; read_en_S : in std_logic; read_en_L : in std_logic; read_pointer: in std_logic_vector(3 downto 0); read_pointer_in: in std_logic_vector(3 downto 0); write_pointer: in std_logic_vector(3 downto 0); write_pointer_in: in std_logic_vector(3 downto 0); credit_out: in std_logic; empty_out: in std_logic; full_out: in std_logic; read_en_out: in std_logic; write_en_out: in std_logic; fake_credit: in std_logic; fake_credit_counter: in std_logic_vector(1 downto 0); fake_credit_counter_in: in std_logic_vector(1 downto 0); state_out: in std_logic_vector(4 downto 0); state_in: in std_logic_vector(4 downto 0); fault_info: in std_logic; fault_info_out: in std_logic; fault_info_in: in std_logic; health_info: in std_logic; faulty_packet_out: in std_logic; faulty_packet_in: in std_logic; flit_type: in std_logic_vector(2 downto 0); fault_out: in std_logic; write_fake_flit: in std_logic; -- Functional checkers err_empty_full, err_empty_read_en, err_full_write_en, err_state_in_onehot, err_read_pointer_in_onehot, err_write_pointer_in_onehot, -- Structural checkers err_write_en_write_pointer, err_not_write_en_write_pointer, err_read_pointer_write_pointer_not_empty, err_read_pointer_write_pointer_empty, err_read_pointer_write_pointer_not_full, err_read_pointer_write_pointer_full, err_read_pointer_increment, err_read_pointer_not_increment, err_write_en, err_not_write_en, err_not_write_en1, err_not_write_en2, err_read_en_mismatch, err_read_en_mismatch1, -- Newly added checkers for FIFO with packet drop and fault classifier support! err_fake_credit_read_en_fake_credit_counter_in_increment, err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement, err_not_fake_credit_read_en_fake_credit_counter_in_not_change, err_fake_credit_not_read_en_fake_credit_counter_in_not_change, err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change, err_fake_credit_read_en_credit_out, err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out, err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out, -- Checkers for Packet Dropping FSM of FIFO err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit, err_state_out_Idle_not_fault_out_valid_in_state_in_not_change, err_state_out_Idle_not_fault_out_not_fake_credit, err_state_out_Idle_not_fault_out_not_fault_info_in, err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal, err_state_out_Idle_fault_out_fake_credit, err_state_out_Idle_fault_out_state_in_Packet_drop, err_state_out_Idle_fault_out_fault_info_in, err_state_out_Idle_fault_out_faulty_packet_in, err_state_out_Idle_not_health_info, err_state_out_Idle_not_write_fake_flit, err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit, err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit, err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit, err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in, err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Header_flit_valid_in_fault_out_write_fake_flit, err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Header_flit_valid_in_fault_out_fault_info_in, err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change, err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Header_flit_not_valid_in_not_fault_info_in, err_state_out_Header_flit_not_valid_in_not_write_fake_flit, err_state_out_Header_flit_or_Body_flit_not_fake_credit, err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change, err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit, err_state_out_Body_flit_valid_in_not_fault_out_health_info, err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit, err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in, err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Body_flit_valid_in_fault_out_write_fake_flit, err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Body_flit_valid_in_fault_out_fault_info_in, err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change, err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Body_flit_not_valid_in_not_fault_info_in, err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info, err_state_out_Body_flit_valid_in_fault_out_not_health_info, err_state_out_Body_flit_valid_in_not_health_info, err_state_out_Body_flit_not_fake_credit, err_state_out_Body_flit_not_valid_in_not_write_fake_flit, err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit, err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit, err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in, err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Tail_flit_valid_in_fault_out_fake_credit, err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Tail_flit_valid_in_fault_out_fault_info_in, err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Tail_flit_not_valid_in_state_in_Idle, err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change, err_state_out_Tail_flit_not_valid_in_not_fault_info_in, err_state_out_Tail_flit_not_valid_in_not_fake_credit, err_state_out_Tail_flit_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit, err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change, err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Packet_drop_not_fault_info_in, err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit, err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change, err_fault_info_fault_info_out_equal, err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal, err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in : out std_logic ); end FIFO_credit_based_control_part_checkers; architecture behavior of FIFO_credit_based_control_part_checkers is CONSTANT Idle: std_logic_vector (4 downto 0) := "00001"; CONSTANT Header_flit: std_logic_vector (4 downto 0) := "00010"; CONSTANT Body_flit: std_logic_vector (4 downto 0) := "00100"; CONSTANT Tail_flit: std_logic_vector (4 downto 0) := "01000"; CONSTANT Packet_drop: std_logic_vector (4 downto 0) := "10000"; begin -- Functional Checkers (Might cover or be covered by some of the structural checkers) -- Empty and full cannot be high at the same time! process (empty_out, full_out) begin if (empty_out = '1' and full_out = '1') then err_empty_full <= '1'; else err_empty_full <= '0'; end if; end process; -- Reading from an empty FIFO is not possible! process (empty_out, read_en_out) begin if (empty_out = '1' and read_en_out = '1') then err_empty_read_en <= '1'; else err_empty_read_en <= '0'; end if; end process; -- Writing to a full FIFO is not possible! process (full_out, write_en_out) begin if (full_out = '1' and write_en_out = '1') then err_full_write_en <= '1'; else err_full_write_en <= '0'; end if; end process; -- The states of the packet dropping FSM of FIFO must always be one-hot (state_in)! process (state_in) begin if (state_in /= Idle and state_in /= Header_flit and state_in /= Body_flit and state_in /= Tail_flit and state_in /= Packet_drop) then err_state_in_onehot <= '1'; else err_state_in_onehot <= '0'; end if; end process; -- Read pointer must always be one-hot! process (read_pointer_in) begin if (read_pointer_in /= "0001" and read_pointer_in /= "0010" and read_pointer_in /= "0100" and read_pointer_in /= "1000") then err_read_pointer_in_onehot <= '1'; else err_read_pointer_in_onehot <= '0'; end if; end process; -- Write pointer must always be one-hot! process (write_pointer_in) begin if (write_pointer_in /= "0001" and write_pointer_in /= "0010" and write_pointer_in /= "0100" and write_pointer_in /= "1000") then err_write_pointer_in_onehot <= '1'; else err_write_pointer_in_onehot <= '0'; end if; end process; --------------------------------------------------------------------------------------------------------- -- Structural Checkers -- Write pointer and Read pointer checkers process (write_en_out, write_pointer_in, write_pointer) begin if (write_en_out = '1' and write_pointer_in /= (write_pointer(2 downto 0) & write_pointer(3)) ) then err_write_en_write_pointer <= '1'; else err_write_en_write_pointer <= '0'; end if; end process; -- Checked ! process (write_en_out, write_pointer_in, write_pointer) begin if (write_en_out = '0' and write_pointer_in /= write_pointer ) then err_not_write_en_write_pointer <= '1'; else err_not_write_en_write_pointer <= '0'; end if; end process; -- Checked ! process (read_pointer, write_pointer, empty_out) begin if (read_pointer = write_pointer and empty_out = '0' ) then err_read_pointer_write_pointer_not_empty <= '1'; else err_read_pointer_write_pointer_not_empty <= '0'; end if; end process; -- Checked ! process (read_pointer, write_pointer, empty_out) begin if (read_pointer /= write_pointer and empty_out = '1' ) then err_read_pointer_write_pointer_empty <= '1'; else err_read_pointer_write_pointer_empty <= '0'; end if; end process; -- Checked ! process (write_pointer, read_pointer, full_out) begin if (write_pointer = (read_pointer(0)&read_pointer(3 downto 1)) and full_out = '0' ) then err_read_pointer_write_pointer_not_full <= '1'; else err_read_pointer_write_pointer_not_full <= '0'; end if; end process; -- Checked ! process (write_pointer, read_pointer, full_out) begin if (write_pointer /= (read_pointer(0)&read_pointer(3 downto 1)) and full_out = '1' ) then err_read_pointer_write_pointer_full <= '1'; else err_read_pointer_write_pointer_full <= '0'; end if; end process; -- Checked ! process (read_en_out, empty_out, read_pointer_in, read_pointer) begin if (read_en_out = '1' and empty_out = '0' and read_pointer_in /= (read_pointer(2 downto 0)&read_pointer(3)) ) then err_read_pointer_increment <= '1'; else err_read_pointer_increment <= '0'; end if; end process; -- Checked ! process (read_en_out, empty_out, read_pointer_in, read_pointer) begin if ( (read_en_out = '0' or empty_out = '1') and read_pointer_in /= read_pointer ) then err_read_pointer_not_increment <= '1'; else err_read_pointer_not_increment <= '0'; end if; end process; -- Checked ! process (valid_in, faulty_packet_out, fault_out, write_fake_flit, full_out, write_en_out) begin if (valid_in = '1' and ((faulty_packet_out = '0' and fault_out = '0') or write_fake_flit = '1') and full_out ='0' and write_en_out = '0') then err_write_en <= '1'; else err_write_en <= '0'; end if; end process; -- Updated ! process (valid_in, faulty_packet_out, fault_out, write_fake_flit, full_out, write_en_out) begin if ( (valid_in = '0' or (((faulty_packet_out = '1' or fault_out = '1') and write_fake_flit = '0')) or full_out = '1') and write_en_out = '1') then err_not_write_en <= '1'; else err_not_write_en <= '0'; end if; end process; process (valid_in, faulty_packet_out, fault_out, write_fake_flit, full_out, write_en_out) begin if ( valid_in = '1' and ((faulty_packet_out = '1' or fault_out = '1') and write_fake_flit = '0') and write_en_out = '1') then err_not_write_en1 <= '1'; else err_not_write_en1 <= '0'; end if; end process; process (valid_in, faulty_packet_out, fault_out, write_fake_flit, full_out, write_en_out) begin if ( valid_in = '1' and ((faulty_packet_out = '0' and fault_out = '0') or write_fake_flit = '1') and full_out = '1' and write_en_out = '1') then err_not_write_en2 <= '1'; else err_not_write_en2 <= '0'; end if; end process; -- Updated ! process (read_en_N, read_en_E, read_en_W, read_en_S, read_en_L, empty_out, read_en_out) begin if ( (read_en_N = '1' or read_en_E = '1' or read_en_W = '1' or read_en_S = '1' or read_en_L = '1') and empty_out = '0' and read_en_out = '0' ) then err_read_en_mismatch <= '1'; else err_read_en_mismatch <= '0'; end if; end process; process (read_en_N, read_en_E, read_en_W, read_en_S, read_en_L, empty_out, read_en_out) begin if ( ((read_en_N = '0' and read_en_E = '0' and read_en_W = '0' and read_en_S = '0' and read_en_L = '0') or empty_out = '1') and read_en_out = '1' ) then err_read_en_mismatch1 <= '1'; else err_read_en_mismatch1 <= '0'; end if; end process; -- Newly added checkers for FIFO with packet drop and fault classifier support! process (fake_credit, read_en_out, fake_credit_counter_in, fake_credit_counter) begin if (fake_credit = '1' and read_en_out = '1' and fake_credit_counter_in /= fake_credit_counter + 1) then err_fake_credit_read_en_fake_credit_counter_in_increment <= '1'; else err_fake_credit_read_en_fake_credit_counter_in_increment <= '0'; end if; end process; process (fake_credit, read_en_out, fake_credit_counter, fake_credit_counter_in) begin if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter > 0 and fake_credit_counter_in /= fake_credit_counter - 1 ) then err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement <= '1'; else err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement <= '0'; end if; end process; process (fake_credit, read_en_out, fake_credit_counter_in, fake_credit_counter) begin if (fake_credit = '0' and read_en_out = '1' and fake_credit_counter_in /= fake_credit_counter) then err_not_fake_credit_read_en_fake_credit_counter_in_not_change <= '1'; else err_not_fake_credit_read_en_fake_credit_counter_in_not_change <= '0'; end if; end process; process (fake_credit, read_en_out, fake_credit_counter_in, fake_credit_counter) begin if (fake_credit = '1' and read_en_out = '0' and fake_credit_counter_in /= fake_credit_counter) then err_fake_credit_not_read_en_fake_credit_counter_in_not_change <= '1'; else err_fake_credit_not_read_en_fake_credit_counter_in_not_change <= '0'; end if; end process; process (fake_credit, read_en_out, fake_credit_counter, fake_credit_counter_in) begin if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter <= 0 and fake_credit_counter_in /= fake_credit_counter) then err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change <= '1'; else err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change <= '0'; end if; end process; process (fake_credit, read_en_out, credit_out) begin if ((fake_credit = '1' or read_en_out ='1') and credit_out = '0') then err_fake_credit_read_en_credit_out <= '1'; else err_fake_credit_read_en_credit_out <= '0'; end if; end process; process (fake_credit, read_en_out, fake_credit_counter, credit_out) begin if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter > 0 and credit_out = '0') then err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out <= '1'; else err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out <= '0'; end if; end process; process (fake_credit, read_en_out, fake_credit_counter, credit_out) begin if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter <= 0 and credit_out = '1') then err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out <= '1'; else err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out <= '0'; end if; end process; -------------------------------------------------------------------------------------------------- -- Idle state -- fault_out = '0' -------------------------------------------------------------------------------------------------- process (state_out, fault_out, valid_in, state_in) begin if (state_out = Idle and fault_out = '0' and valid_in = '1' and state_in /= Header_flit) then err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit <= '1'; else err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit <= '0'; end if; end process; process (state_out, fault_out, valid_in, state_in, state_out) begin if (state_out = Idle and fault_out = '0' and valid_in = '0' and state_in /= state_out) then err_state_out_Idle_not_fault_out_valid_in_state_in_not_change <= '1'; else err_state_out_Idle_not_fault_out_valid_in_state_in_not_change <= '0'; end if; end process; process (state_out, fault_out, fake_credit) begin if (state_out = Idle and fault_out = '0' and fake_credit = '1') then err_state_out_Idle_not_fault_out_not_fake_credit <= '1'; else err_state_out_Idle_not_fault_out_not_fake_credit <= '0'; end if; end process; process (state_out, fault_out, fault_info_in) begin if (state_out = Idle and fault_out = '0' and fault_info_in = '1') then err_state_out_Idle_not_fault_out_not_fault_info_in <= '1'; else err_state_out_Idle_not_fault_out_not_fault_info_in <= '0'; end if; end process; process (state_out, fault_out, faulty_packet_in, faulty_packet_out) begin if (state_out = Idle and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal <= '1'; else err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal <= '0'; end if; end process; -- fault_out = '1' -------------------------------------------------------------------------------------------------- process (state_out, fault_out, fake_credit) begin if (state_out = Idle and fault_out = '1' and fake_credit = '0') then err_state_out_Idle_fault_out_fake_credit <= '1'; else err_state_out_Idle_fault_out_fake_credit <= '0'; end if; end process; process (state_out, fault_out, state_in) begin if (state_out = Idle and fault_out = '1' and state_in /= Packet_drop) then err_state_out_Idle_fault_out_state_in_Packet_drop <= '1'; else err_state_out_Idle_fault_out_state_in_Packet_drop <= '0'; end if; end process; process (state_out, fault_out, fault_info_in) begin if (state_out = Idle and fault_out = '1' and fault_info_in = '0') then err_state_out_Idle_fault_out_fault_info_in <= '1'; else err_state_out_Idle_fault_out_fault_info_in <= '0'; end if; end process; process (state_out, fault_out, faulty_packet_in) begin if (state_out = Idle and fault_out = '1' and faulty_packet_in /= '1') then err_state_out_Idle_fault_out_faulty_packet_in <= '1'; else err_state_out_Idle_fault_out_faulty_packet_in <= '0'; end if; end process; process (state_out, write_fake_flit) begin if (state_out = Idle and write_fake_flit = '1') then err_state_out_Idle_not_write_fake_flit <= '1'; else err_state_out_Idle_not_write_fake_flit <= '0'; end if; end process; -- Other properties for Idle state -------------------------------------------------------------------------------------------------- process (state_out, health_info) begin if ( (state_out = Idle or state_out = Header_flit or state_out = Tail_flit or state_out = Packet_drop) and health_info = '1') then err_state_out_Idle_not_health_info <= '1'; else err_state_out_Idle_not_health_info <= '0'; end if; end process; -------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------- -- Header_flit state -- fault_out = '0' -------------------------------------------------------------------------------------------------- process (state_out, valid_in, fault_out, flit_type, state_in) begin if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and flit_type = "010" and state_in /= Body_flit) then err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit <= '1'; else err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit <= '0'; end if; end process; process (state_out, valid_in, fault_out, flit_type, state_in) begin if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and flit_type = "100" and state_in /= Tail_flit) then err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit <= '1'; else err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit <= '0'; end if; end process; process (state_out, valid_in, fault_out, write_fake_flit) begin if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and write_fake_flit = '1') then err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit <= '1'; else err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit <= '0'; end if; end process; process (state_out, valid_in, fault_out, fault_info_in) begin if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and fault_info_in = '1') then err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in <= '1'; else err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in <= '0'; end if; end process; process (state_out, valid_in, fault_out, faulty_packet_in, faulty_packet_out) begin if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1'; else err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0'; end if; end process; -- fault_out = '1' -------------------------------------------------------------------------------------------------- process (state_out, valid_in, fault_out, write_fake_flit) begin if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and write_fake_flit = '0') then err_state_out_Header_flit_valid_in_fault_out_write_fake_flit <= '1'; else err_state_out_Header_flit_valid_in_fault_out_write_fake_flit <= '0'; end if; end process; process (state_out, valid_in, fault_out, state_in) begin if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and state_in /= Packet_drop) then err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop <= '1'; else err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop <= '0'; end if; end process; process (state_out, valid_in, fault_out, fault_info_in) begin if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and fault_info_in = '0') then err_state_out_Header_flit_valid_in_fault_out_fault_info_in <= '1'; else err_state_out_Header_flit_valid_in_fault_out_fault_info_in <= '0'; end if; end process; process (state_out, valid_in, fault_out, faulty_packet_in) begin if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and faulty_packet_in /= '1') then err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in <= '1'; else err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in <= '0'; end if; end process; process (state_out, valid_in, state_in, state_out) begin if (state_out = Header_flit and valid_in = '0' and state_in /= state_out) then err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change <= '1'; else err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change <= '0'; end if; end process; process (state_out, valid_in, faulty_packet_in, faulty_packet_out) begin if (state_out = Header_flit and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '1'; else err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '0'; end if; end process; process (state_out, valid_in, fault_info_in) begin if (state_out = Header_flit and valid_in = '0' and fault_info_in = '1') then err_state_out_Header_flit_not_valid_in_not_fault_info_in <= '1'; else err_state_out_Header_flit_not_valid_in_not_fault_info_in <= '0'; end if; end process; process (state_out, valid_in, write_fake_flit) begin if (state_out = Header_flit and valid_in = '0' and write_fake_flit = '1') then err_state_out_Header_flit_not_valid_in_not_write_fake_flit <= '1'; else err_state_out_Header_flit_not_valid_in_not_write_fake_flit <= '0'; end if; end process; process (state_out, fake_credit) begin if ( (state_out = Header_flit or state_out = Body_flit) and fake_credit /= '0') then err_state_out_Header_flit_or_Body_flit_not_fake_credit <= '1'; else err_state_out_Header_flit_or_Body_flit_not_fake_credit <= '0'; end if; end process; -------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------- -- Body_flit state -- fault_out = '0' -------------------------------------------------------------------------------------------------- process (state_out, valid_in, fault_out, flit_type, state_in, state_out) begin if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type = "010" and state_in /= state_out) then err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change <= '1'; else err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change <= '0'; end if; end process; process (state_out, valid_in, fault_out, flit_type, state_in) begin if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type = "100" and state_in /= Tail_flit) then err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit <= '1'; else err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit <= '0'; end if; end process; process (state_out, valid_in, fault_out, flit_type, health_info) begin if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type = "100" and health_info = '0') then err_state_out_Body_flit_valid_in_not_fault_out_health_info <= '1'; else err_state_out_Body_flit_valid_in_not_fault_out_health_info <= '0'; end if; end process; process (state_out, valid_in, fault_out, flit_type, health_info) begin if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type /= "100" and health_info = '1') then err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info <= '1'; else err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info <= '0'; end if; end process; process (state_out, valid_in, fault_out, health_info) begin if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and health_info = '1') then err_state_out_Body_flit_valid_in_fault_out_not_health_info <= '1'; else err_state_out_Body_flit_valid_in_fault_out_not_health_info <= '0'; end if; end process; process (state_out, valid_in, health_info) begin if (state_out = Body_flit and valid_in = '0' and health_info = '1') then err_state_out_Body_flit_valid_in_not_health_info <= '1'; else err_state_out_Body_flit_valid_in_not_health_info <= '0'; end if; end process; process (state_out, valid_in, fault_out, write_fake_flit) begin if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and write_fake_flit = '1') then err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit <= '1'; else err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit <= '0'; end if; end process; process (state_out, valid_in, fault_out, fault_info_in) begin if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and fault_info_in = '1') then err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in <= '1'; else err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in <= '0'; end if; end process; process (state_out, valid_in, fault_out, faulty_packet_in, faulty_packet_out) begin if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1'; else err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0'; end if; end process; -- fault_out = '1' -------------------------------------------------------------------------------------------------- process (state_out, valid_in, fault_out, write_fake_flit) begin if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and write_fake_flit = '0') then err_state_out_Body_flit_valid_in_fault_out_write_fake_flit <= '1'; else err_state_out_Body_flit_valid_in_fault_out_write_fake_flit <= '0'; end if; end process; process (state_out, valid_in, fault_out, state_in) begin if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and state_in /= Packet_drop) then err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop <= '1'; else err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop <= '0'; end if; end process; process (state_out, valid_in, fault_out, fault_info_in) begin if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and fault_info_in = '0') then err_state_out_Body_flit_valid_in_fault_out_fault_info_in <= '1'; else err_state_out_Body_flit_valid_in_fault_out_fault_info_in <= '0'; end if; end process; process (state_out, valid_in, fault_out, faulty_packet_in) begin if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and faulty_packet_in /= '1') then err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in <= '1'; else err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in <= '0'; end if; end process; process (state_out, valid_in, state_in) begin if (state_out = Body_flit and valid_in = '0' and state_in /= state_out) then err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change <= '1'; else err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change <= '0'; end if; end process; process (state_out, valid_in, faulty_packet_in, faulty_packet_out) begin if (state_out = Body_flit and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '1'; else err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '0'; end if; end process; process (state_out, valid_in, fault_info_in) begin if (state_out = Body_flit and valid_in = '0' and fault_info_in = '1') then err_state_out_Body_flit_not_valid_in_not_fault_info_in <= '1'; else err_state_out_Body_flit_not_valid_in_not_fault_info_in <= '0'; end if; end process; process (state_out, fake_credit) begin if (state_out = Body_flit and fake_credit = '1') then err_state_out_Body_flit_not_fake_credit <= '1'; else err_state_out_Body_flit_not_fake_credit <= '0'; end if; end process; process (state_out, valid_in, write_fake_flit) begin if (state_out = Body_flit and valid_in = '0' and write_fake_flit = '1') then err_state_out_Body_flit_not_valid_in_not_write_fake_flit <= '1'; else err_state_out_Body_flit_not_valid_in_not_write_fake_flit <= '0'; end if; end process; -------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------- -- Tail_flit state -- fault_out = '0' -------------------------------------------------------------------------------------------------- process (state_out, valid_in, fault_out, flit_type, state_in) begin if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and flit_type = "001" and state_in /= Header_flit) then err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit <= '1'; else err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit <= '0'; end if; end process; process (state_out, valid_in, fault_out, fake_credit) begin if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and fake_credit = '1') then err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit <= '1'; else err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit <= '0'; end if; end process; process (state_out, valid_in, fault_out, fault_info_in) begin if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and fault_info_in = '1') then err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in <= '1'; else err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in <= '0'; end if; end process; process (state_out, valid_in, fault_out, faulty_packet_in, faulty_packet_out) begin if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1'; else err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0'; end if; end process; -- fault_out = '1' -------------------------------------------------------------------------------------------------- process (state_out, valid_in, fault_out, fake_credit) begin if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and fake_credit /= '1') then err_state_out_Tail_flit_valid_in_fault_out_fake_credit <= '1'; else err_state_out_Tail_flit_valid_in_fault_out_fake_credit <= '0'; end if; end process; process (state_out, valid_in, fault_out, state_in) begin if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and state_in /= Packet_drop) then err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop <= '1'; else err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop <= '0'; end if; end process; process (state_out, valid_in, fault_out, fault_info_in) begin if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and fault_info_in = '0') then err_state_out_Tail_flit_valid_in_fault_out_fault_info_in <= '1'; else err_state_out_Tail_flit_valid_in_fault_out_fault_info_in <= '0'; end if; end process; process (state_out, valid_in, fault_out, faulty_packet_in) begin if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and faulty_packet_in /= '1') then err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in <= '1'; else err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in <= '0'; end if; end process; process (state_out, valid_in, state_in) begin if (state_out = Tail_flit and valid_in = '0' and state_in /= Idle) then err_state_out_Tail_flit_not_valid_in_state_in_Idle <= '1'; else err_state_out_Tail_flit_not_valid_in_state_in_Idle <= '0'; end if; end process; process (state_out, valid_in, faulty_packet_in, faulty_packet_out) begin if (state_out = Tail_flit and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change <= '1'; else err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change <= '0'; end if; end process; process (state_out, valid_in, fault_info_in) begin if (state_out = Tail_flit and valid_in = '0' and fault_info_in = '1') then err_state_out_Tail_flit_not_valid_in_not_fault_info_in <= '1'; else err_state_out_Tail_flit_not_valid_in_not_fault_info_in <= '0'; end if; end process; process (state_out, valid_in, fake_credit) begin if (state_out = Tail_flit and valid_in = '0' and fake_credit /= '0') then err_state_out_Tail_flit_not_valid_in_not_fake_credit <= '1'; else err_state_out_Tail_flit_not_valid_in_not_fake_credit <= '0'; end if; end process; process (state_out, write_fake_flit) begin if (state_out = Tail_flit and write_fake_flit = '1') then err_state_out_Tail_flit_not_write_fake_flit <= '1'; else err_state_out_Tail_flit_not_write_fake_flit <= '0'; end if; end process; -------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------- -- Packet_drop state -- faulty_packet_out = '1' -------------------------------------------------------------------------------------------------- process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, fake_credit) begin if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and fake_credit /= '0') then err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit <= '1'; else err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, faulty_packet_in) begin if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and faulty_packet_in /= '0') then err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in <= '1'; else err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in) begin if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and state_in /= Header_flit) then err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit <= '1'; else err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, write_fake_flit) begin if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and write_fake_flit = '0') then err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit <= '1'; else err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in, state_out) begin if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '1' and state_in /= state_out) then err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change <= '1'; else err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, faulty_packet_in) begin if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '0' and faulty_packet_in /= '0') then err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in <= '1'; else err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in, state_out) begin if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '1' and state_in /= state_out) then err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change <= '1'; else err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in) begin if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '0' and state_in /= Idle) then err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle <= '1'; else err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, fake_credit) begin if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '0' and fake_credit = '0') then err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit <= '1'; else err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, fake_credit) begin if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and ((flit_type /= "001" and flit_type /= "100") or fault_out = '1') and fake_credit = '0') then err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit <= '1'; else err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, faulty_packet_in, faulty_packet_out) begin if (state_out = Packet_drop and faulty_packet_out = '1' and ( valid_in = '0' or (flit_type /= "001" and flit_type /= "100") or fault_out = '1' ) and faulty_packet_in /= faulty_packet_out) then err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1'; else err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in, state_out) begin if (state_out = Packet_drop and faulty_packet_out = '1' and ((flit_type /= "001" and flit_type /= "100") or fault_out = '1') and state_in /= state_out) then err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change <= '1'; else err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, faulty_packet_in, faulty_packet_out) begin if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal <= '1'; else err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, state_in, state_out) begin if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and state_in /= state_out) then err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change <= '1'; else err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, write_fake_flit) begin if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and write_fake_flit = '1') then err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit <= '1'; else err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, fake_credit) begin if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and fake_credit = '1') then err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit <= '1'; else err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit <= '0'; end if; end process; -- faulty_packet_out = '0' -------------------------------------------------------------------------------------------------- process (state_out, faulty_packet_out, state_in, state_out) begin if (state_out = Packet_drop and faulty_packet_out = '0' and state_in /= state_out) then err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change <= '1'; else err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change <= '0'; end if; end process; process (state_out, faulty_packet_out, faulty_packet_in, faulty_packet_out) begin if (state_out = Packet_drop and faulty_packet_out = '0' and faulty_packet_in /= faulty_packet_out) then err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change <= '1'; else err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change <= '0'; end if; end process; process (state_out, fault_info_in) begin if (state_out = Packet_drop and fault_info_in = '1') then err_state_out_Packet_drop_not_fault_info_in <= '1'; else err_state_out_Packet_drop_not_fault_info_in <= '0'; end if; end process; process (state_out, faulty_packet_out, fake_credit) begin if (state_out = Packet_drop and faulty_packet_out = '0' and fake_credit = '1') then err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit <= '1'; else err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, write_fake_flit) begin if (state_out = Packet_drop and faulty_packet_out = '1' and (valid_in = '0' or flit_type /= "001" or fault_out = '1') and write_fake_flit = '1') then err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit <= '1'; else err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit <= '0'; end if; end process; process (state_out, faulty_packet_out, write_fake_flit) begin if (state_out = Packet_drop and faulty_packet_out = '0' and write_fake_flit = '1') then err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit <= '1'; else err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit <= '0'; end if; end process; process (fault_info, fault_info_out) begin if (fault_info /= fault_info_out) then err_fault_info_fault_info_out_equal <= '1'; else err_fault_info_fault_info_out_equal <= '0'; end if; end process; process (state_out, valid_in, state_in, state_out) begin if (state_out = Packet_drop and valid_in = '0' and state_in /= state_out) then err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal <= '1'; else err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal <= '0'; end if; end process; process (state_out, valid_in, fault_out, flit_type, state_in, state_out) begin if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and flit_type /= "001" and state_in /= state_out) then err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal <= '1'; else err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal <= '0'; end if; end process; -- Added after change of design ! process (state_out, faulty_packet_out, valid_in, flit_type, fault_info_in) begin if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_info_in /= '1') then err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in <= '1'; else err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, fault_info_in) begin if (state_out = Packet_drop and faulty_packet_out = '1' and (valid_in = '0' or flit_type /= "001") and fault_info_in /= '0') then err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in <= '1'; else err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in <= '0'; end if; end process; end behavior;
--Copyright (C) 2016 Siavoosh Payandeh Azad and Behrad Niazmand library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.ALL; entity FIFO_credit_based_control_part_checkers is port ( valid_in: in std_logic; read_en_N : in std_logic; read_en_E : in std_logic; read_en_W : in std_logic; read_en_S : in std_logic; read_en_L : in std_logic; read_pointer: in std_logic_vector(3 downto 0); read_pointer_in: in std_logic_vector(3 downto 0); write_pointer: in std_logic_vector(3 downto 0); write_pointer_in: in std_logic_vector(3 downto 0); credit_out: in std_logic; empty_out: in std_logic; full_out: in std_logic; read_en_out: in std_logic; write_en_out: in std_logic; fake_credit: in std_logic; fake_credit_counter: in std_logic_vector(1 downto 0); fake_credit_counter_in: in std_logic_vector(1 downto 0); state_out: in std_logic_vector(4 downto 0); state_in: in std_logic_vector(4 downto 0); fault_info: in std_logic; fault_info_out: in std_logic; fault_info_in: in std_logic; health_info: in std_logic; faulty_packet_out: in std_logic; faulty_packet_in: in std_logic; flit_type: in std_logic_vector(2 downto 0); fault_out: in std_logic; write_fake_flit: in std_logic; -- Functional checkers err_empty_full, err_empty_read_en, err_full_write_en, err_state_in_onehot, err_read_pointer_in_onehot, err_write_pointer_in_onehot, -- Structural checkers err_write_en_write_pointer, err_not_write_en_write_pointer, err_read_pointer_write_pointer_not_empty, err_read_pointer_write_pointer_empty, err_read_pointer_write_pointer_not_full, err_read_pointer_write_pointer_full, err_read_pointer_increment, err_read_pointer_not_increment, err_write_en, err_not_write_en, err_not_write_en1, err_not_write_en2, err_read_en_mismatch, err_read_en_mismatch1, -- Newly added checkers for FIFO with packet drop and fault classifier support! err_fake_credit_read_en_fake_credit_counter_in_increment, err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement, err_not_fake_credit_read_en_fake_credit_counter_in_not_change, err_fake_credit_not_read_en_fake_credit_counter_in_not_change, err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change, err_fake_credit_read_en_credit_out, err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out, err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out, -- Checkers for Packet Dropping FSM of FIFO err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit, err_state_out_Idle_not_fault_out_valid_in_state_in_not_change, err_state_out_Idle_not_fault_out_not_fake_credit, err_state_out_Idle_not_fault_out_not_fault_info_in, err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal, err_state_out_Idle_fault_out_fake_credit, err_state_out_Idle_fault_out_state_in_Packet_drop, err_state_out_Idle_fault_out_fault_info_in, err_state_out_Idle_fault_out_faulty_packet_in, err_state_out_Idle_not_health_info, err_state_out_Idle_not_write_fake_flit, err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit, err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit, err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit, err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in, err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Header_flit_valid_in_fault_out_write_fake_flit, err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Header_flit_valid_in_fault_out_fault_info_in, err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change, err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Header_flit_not_valid_in_not_fault_info_in, err_state_out_Header_flit_not_valid_in_not_write_fake_flit, err_state_out_Header_flit_or_Body_flit_not_fake_credit, err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change, err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit, err_state_out_Body_flit_valid_in_not_fault_out_health_info, err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit, err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in, err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Body_flit_valid_in_fault_out_write_fake_flit, err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Body_flit_valid_in_fault_out_fault_info_in, err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change, err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Body_flit_not_valid_in_not_fault_info_in, err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info, err_state_out_Body_flit_valid_in_fault_out_not_health_info, err_state_out_Body_flit_valid_in_not_health_info, err_state_out_Body_flit_not_fake_credit, err_state_out_Body_flit_not_valid_in_not_write_fake_flit, err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit, err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit, err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in, err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Tail_flit_valid_in_fault_out_fake_credit, err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Tail_flit_valid_in_fault_out_fault_info_in, err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Tail_flit_not_valid_in_state_in_Idle, err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change, err_state_out_Tail_flit_not_valid_in_not_fault_info_in, err_state_out_Tail_flit_not_valid_in_not_fake_credit, err_state_out_Tail_flit_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit, err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change, err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Packet_drop_not_fault_info_in, err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit, err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change, err_fault_info_fault_info_out_equal, err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal, err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in : out std_logic ); end FIFO_credit_based_control_part_checkers; architecture behavior of FIFO_credit_based_control_part_checkers is CONSTANT Idle: std_logic_vector (4 downto 0) := "00001"; CONSTANT Header_flit: std_logic_vector (4 downto 0) := "00010"; CONSTANT Body_flit: std_logic_vector (4 downto 0) := "00100"; CONSTANT Tail_flit: std_logic_vector (4 downto 0) := "01000"; CONSTANT Packet_drop: std_logic_vector (4 downto 0) := "10000"; begin -- Functional Checkers (Might cover or be covered by some of the structural checkers) -- Empty and full cannot be high at the same time! process (empty_out, full_out) begin if (empty_out = '1' and full_out = '1') then err_empty_full <= '1'; else err_empty_full <= '0'; end if; end process; -- Reading from an empty FIFO is not possible! process (empty_out, read_en_out) begin if (empty_out = '1' and read_en_out = '1') then err_empty_read_en <= '1'; else err_empty_read_en <= '0'; end if; end process; -- Writing to a full FIFO is not possible! process (full_out, write_en_out) begin if (full_out = '1' and write_en_out = '1') then err_full_write_en <= '1'; else err_full_write_en <= '0'; end if; end process; -- The states of the packet dropping FSM of FIFO must always be one-hot (state_in)! process (state_in) begin if (state_in /= Idle and state_in /= Header_flit and state_in /= Body_flit and state_in /= Tail_flit and state_in /= Packet_drop) then err_state_in_onehot <= '1'; else err_state_in_onehot <= '0'; end if; end process; -- Read pointer must always be one-hot! process (read_pointer_in) begin if (read_pointer_in /= "0001" and read_pointer_in /= "0010" and read_pointer_in /= "0100" and read_pointer_in /= "1000") then err_read_pointer_in_onehot <= '1'; else err_read_pointer_in_onehot <= '0'; end if; end process; -- Write pointer must always be one-hot! process (write_pointer_in) begin if (write_pointer_in /= "0001" and write_pointer_in /= "0010" and write_pointer_in /= "0100" and write_pointer_in /= "1000") then err_write_pointer_in_onehot <= '1'; else err_write_pointer_in_onehot <= '0'; end if; end process; --------------------------------------------------------------------------------------------------------- -- Structural Checkers -- Write pointer and Read pointer checkers process (write_en_out, write_pointer_in, write_pointer) begin if (write_en_out = '1' and write_pointer_in /= (write_pointer(2 downto 0) & write_pointer(3)) ) then err_write_en_write_pointer <= '1'; else err_write_en_write_pointer <= '0'; end if; end process; -- Checked ! process (write_en_out, write_pointer_in, write_pointer) begin if (write_en_out = '0' and write_pointer_in /= write_pointer ) then err_not_write_en_write_pointer <= '1'; else err_not_write_en_write_pointer <= '0'; end if; end process; -- Checked ! process (read_pointer, write_pointer, empty_out) begin if (read_pointer = write_pointer and empty_out = '0' ) then err_read_pointer_write_pointer_not_empty <= '1'; else err_read_pointer_write_pointer_not_empty <= '0'; end if; end process; -- Checked ! process (read_pointer, write_pointer, empty_out) begin if (read_pointer /= write_pointer and empty_out = '1' ) then err_read_pointer_write_pointer_empty <= '1'; else err_read_pointer_write_pointer_empty <= '0'; end if; end process; -- Checked ! process (write_pointer, read_pointer, full_out) begin if (write_pointer = (read_pointer(0)&read_pointer(3 downto 1)) and full_out = '0' ) then err_read_pointer_write_pointer_not_full <= '1'; else err_read_pointer_write_pointer_not_full <= '0'; end if; end process; -- Checked ! process (write_pointer, read_pointer, full_out) begin if (write_pointer /= (read_pointer(0)&read_pointer(3 downto 1)) and full_out = '1' ) then err_read_pointer_write_pointer_full <= '1'; else err_read_pointer_write_pointer_full <= '0'; end if; end process; -- Checked ! process (read_en_out, empty_out, read_pointer_in, read_pointer) begin if (read_en_out = '1' and empty_out = '0' and read_pointer_in /= (read_pointer(2 downto 0)&read_pointer(3)) ) then err_read_pointer_increment <= '1'; else err_read_pointer_increment <= '0'; end if; end process; -- Checked ! process (read_en_out, empty_out, read_pointer_in, read_pointer) begin if ( (read_en_out = '0' or empty_out = '1') and read_pointer_in /= read_pointer ) then err_read_pointer_not_increment <= '1'; else err_read_pointer_not_increment <= '0'; end if; end process; -- Checked ! process (valid_in, faulty_packet_out, fault_out, write_fake_flit, full_out, write_en_out) begin if (valid_in = '1' and ((faulty_packet_out = '0' and fault_out = '0') or write_fake_flit = '1') and full_out ='0' and write_en_out = '0') then err_write_en <= '1'; else err_write_en <= '0'; end if; end process; -- Updated ! process (valid_in, faulty_packet_out, fault_out, write_fake_flit, full_out, write_en_out) begin if ( (valid_in = '0' or (((faulty_packet_out = '1' or fault_out = '1') and write_fake_flit = '0')) or full_out = '1') and write_en_out = '1') then err_not_write_en <= '1'; else err_not_write_en <= '0'; end if; end process; process (valid_in, faulty_packet_out, fault_out, write_fake_flit, full_out, write_en_out) begin if ( valid_in = '1' and ((faulty_packet_out = '1' or fault_out = '1') and write_fake_flit = '0') and write_en_out = '1') then err_not_write_en1 <= '1'; else err_not_write_en1 <= '0'; end if; end process; process (valid_in, faulty_packet_out, fault_out, write_fake_flit, full_out, write_en_out) begin if ( valid_in = '1' and ((faulty_packet_out = '0' and fault_out = '0') or write_fake_flit = '1') and full_out = '1' and write_en_out = '1') then err_not_write_en2 <= '1'; else err_not_write_en2 <= '0'; end if; end process; -- Updated ! process (read_en_N, read_en_E, read_en_W, read_en_S, read_en_L, empty_out, read_en_out) begin if ( (read_en_N = '1' or read_en_E = '1' or read_en_W = '1' or read_en_S = '1' or read_en_L = '1') and empty_out = '0' and read_en_out = '0' ) then err_read_en_mismatch <= '1'; else err_read_en_mismatch <= '0'; end if; end process; process (read_en_N, read_en_E, read_en_W, read_en_S, read_en_L, empty_out, read_en_out) begin if ( ((read_en_N = '0' and read_en_E = '0' and read_en_W = '0' and read_en_S = '0' and read_en_L = '0') or empty_out = '1') and read_en_out = '1' ) then err_read_en_mismatch1 <= '1'; else err_read_en_mismatch1 <= '0'; end if; end process; -- Newly added checkers for FIFO with packet drop and fault classifier support! process (fake_credit, read_en_out, fake_credit_counter_in, fake_credit_counter) begin if (fake_credit = '1' and read_en_out = '1' and fake_credit_counter_in /= fake_credit_counter + 1) then err_fake_credit_read_en_fake_credit_counter_in_increment <= '1'; else err_fake_credit_read_en_fake_credit_counter_in_increment <= '0'; end if; end process; process (fake_credit, read_en_out, fake_credit_counter, fake_credit_counter_in) begin if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter > 0 and fake_credit_counter_in /= fake_credit_counter - 1 ) then err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement <= '1'; else err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement <= '0'; end if; end process; process (fake_credit, read_en_out, fake_credit_counter_in, fake_credit_counter) begin if (fake_credit = '0' and read_en_out = '1' and fake_credit_counter_in /= fake_credit_counter) then err_not_fake_credit_read_en_fake_credit_counter_in_not_change <= '1'; else err_not_fake_credit_read_en_fake_credit_counter_in_not_change <= '0'; end if; end process; process (fake_credit, read_en_out, fake_credit_counter_in, fake_credit_counter) begin if (fake_credit = '1' and read_en_out = '0' and fake_credit_counter_in /= fake_credit_counter) then err_fake_credit_not_read_en_fake_credit_counter_in_not_change <= '1'; else err_fake_credit_not_read_en_fake_credit_counter_in_not_change <= '0'; end if; end process; process (fake_credit, read_en_out, fake_credit_counter, fake_credit_counter_in) begin if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter <= 0 and fake_credit_counter_in /= fake_credit_counter) then err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change <= '1'; else err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change <= '0'; end if; end process; process (fake_credit, read_en_out, credit_out) begin if ((fake_credit = '1' or read_en_out ='1') and credit_out = '0') then err_fake_credit_read_en_credit_out <= '1'; else err_fake_credit_read_en_credit_out <= '0'; end if; end process; process (fake_credit, read_en_out, fake_credit_counter, credit_out) begin if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter > 0 and credit_out = '0') then err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out <= '1'; else err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out <= '0'; end if; end process; process (fake_credit, read_en_out, fake_credit_counter, credit_out) begin if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter <= 0 and credit_out = '1') then err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out <= '1'; else err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out <= '0'; end if; end process; -------------------------------------------------------------------------------------------------- -- Idle state -- fault_out = '0' -------------------------------------------------------------------------------------------------- process (state_out, fault_out, valid_in, state_in) begin if (state_out = Idle and fault_out = '0' and valid_in = '1' and state_in /= Header_flit) then err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit <= '1'; else err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit <= '0'; end if; end process; process (state_out, fault_out, valid_in, state_in, state_out) begin if (state_out = Idle and fault_out = '0' and valid_in = '0' and state_in /= state_out) then err_state_out_Idle_not_fault_out_valid_in_state_in_not_change <= '1'; else err_state_out_Idle_not_fault_out_valid_in_state_in_not_change <= '0'; end if; end process; process (state_out, fault_out, fake_credit) begin if (state_out = Idle and fault_out = '0' and fake_credit = '1') then err_state_out_Idle_not_fault_out_not_fake_credit <= '1'; else err_state_out_Idle_not_fault_out_not_fake_credit <= '0'; end if; end process; process (state_out, fault_out, fault_info_in) begin if (state_out = Idle and fault_out = '0' and fault_info_in = '1') then err_state_out_Idle_not_fault_out_not_fault_info_in <= '1'; else err_state_out_Idle_not_fault_out_not_fault_info_in <= '0'; end if; end process; process (state_out, fault_out, faulty_packet_in, faulty_packet_out) begin if (state_out = Idle and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal <= '1'; else err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal <= '0'; end if; end process; -- fault_out = '1' -------------------------------------------------------------------------------------------------- process (state_out, fault_out, fake_credit) begin if (state_out = Idle and fault_out = '1' and fake_credit = '0') then err_state_out_Idle_fault_out_fake_credit <= '1'; else err_state_out_Idle_fault_out_fake_credit <= '0'; end if; end process; process (state_out, fault_out, state_in) begin if (state_out = Idle and fault_out = '1' and state_in /= Packet_drop) then err_state_out_Idle_fault_out_state_in_Packet_drop <= '1'; else err_state_out_Idle_fault_out_state_in_Packet_drop <= '0'; end if; end process; process (state_out, fault_out, fault_info_in) begin if (state_out = Idle and fault_out = '1' and fault_info_in = '0') then err_state_out_Idle_fault_out_fault_info_in <= '1'; else err_state_out_Idle_fault_out_fault_info_in <= '0'; end if; end process; process (state_out, fault_out, faulty_packet_in) begin if (state_out = Idle and fault_out = '1' and faulty_packet_in /= '1') then err_state_out_Idle_fault_out_faulty_packet_in <= '1'; else err_state_out_Idle_fault_out_faulty_packet_in <= '0'; end if; end process; process (state_out, write_fake_flit) begin if (state_out = Idle and write_fake_flit = '1') then err_state_out_Idle_not_write_fake_flit <= '1'; else err_state_out_Idle_not_write_fake_flit <= '0'; end if; end process; -- Other properties for Idle state -------------------------------------------------------------------------------------------------- process (state_out, health_info) begin if ( (state_out = Idle or state_out = Header_flit or state_out = Tail_flit or state_out = Packet_drop) and health_info = '1') then err_state_out_Idle_not_health_info <= '1'; else err_state_out_Idle_not_health_info <= '0'; end if; end process; -------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------- -- Header_flit state -- fault_out = '0' -------------------------------------------------------------------------------------------------- process (state_out, valid_in, fault_out, flit_type, state_in) begin if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and flit_type = "010" and state_in /= Body_flit) then err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit <= '1'; else err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit <= '0'; end if; end process; process (state_out, valid_in, fault_out, flit_type, state_in) begin if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and flit_type = "100" and state_in /= Tail_flit) then err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit <= '1'; else err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit <= '0'; end if; end process; process (state_out, valid_in, fault_out, write_fake_flit) begin if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and write_fake_flit = '1') then err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit <= '1'; else err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit <= '0'; end if; end process; process (state_out, valid_in, fault_out, fault_info_in) begin if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and fault_info_in = '1') then err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in <= '1'; else err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in <= '0'; end if; end process; process (state_out, valid_in, fault_out, faulty_packet_in, faulty_packet_out) begin if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1'; else err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0'; end if; end process; -- fault_out = '1' -------------------------------------------------------------------------------------------------- process (state_out, valid_in, fault_out, write_fake_flit) begin if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and write_fake_flit = '0') then err_state_out_Header_flit_valid_in_fault_out_write_fake_flit <= '1'; else err_state_out_Header_flit_valid_in_fault_out_write_fake_flit <= '0'; end if; end process; process (state_out, valid_in, fault_out, state_in) begin if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and state_in /= Packet_drop) then err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop <= '1'; else err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop <= '0'; end if; end process; process (state_out, valid_in, fault_out, fault_info_in) begin if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and fault_info_in = '0') then err_state_out_Header_flit_valid_in_fault_out_fault_info_in <= '1'; else err_state_out_Header_flit_valid_in_fault_out_fault_info_in <= '0'; end if; end process; process (state_out, valid_in, fault_out, faulty_packet_in) begin if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and faulty_packet_in /= '1') then err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in <= '1'; else err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in <= '0'; end if; end process; process (state_out, valid_in, state_in, state_out) begin if (state_out = Header_flit and valid_in = '0' and state_in /= state_out) then err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change <= '1'; else err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change <= '0'; end if; end process; process (state_out, valid_in, faulty_packet_in, faulty_packet_out) begin if (state_out = Header_flit and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '1'; else err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '0'; end if; end process; process (state_out, valid_in, fault_info_in) begin if (state_out = Header_flit and valid_in = '0' and fault_info_in = '1') then err_state_out_Header_flit_not_valid_in_not_fault_info_in <= '1'; else err_state_out_Header_flit_not_valid_in_not_fault_info_in <= '0'; end if; end process; process (state_out, valid_in, write_fake_flit) begin if (state_out = Header_flit and valid_in = '0' and write_fake_flit = '1') then err_state_out_Header_flit_not_valid_in_not_write_fake_flit <= '1'; else err_state_out_Header_flit_not_valid_in_not_write_fake_flit <= '0'; end if; end process; process (state_out, fake_credit) begin if ( (state_out = Header_flit or state_out = Body_flit) and fake_credit /= '0') then err_state_out_Header_flit_or_Body_flit_not_fake_credit <= '1'; else err_state_out_Header_flit_or_Body_flit_not_fake_credit <= '0'; end if; end process; -------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------- -- Body_flit state -- fault_out = '0' -------------------------------------------------------------------------------------------------- process (state_out, valid_in, fault_out, flit_type, state_in, state_out) begin if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type = "010" and state_in /= state_out) then err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change <= '1'; else err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change <= '0'; end if; end process; process (state_out, valid_in, fault_out, flit_type, state_in) begin if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type = "100" and state_in /= Tail_flit) then err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit <= '1'; else err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit <= '0'; end if; end process; process (state_out, valid_in, fault_out, flit_type, health_info) begin if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type = "100" and health_info = '0') then err_state_out_Body_flit_valid_in_not_fault_out_health_info <= '1'; else err_state_out_Body_flit_valid_in_not_fault_out_health_info <= '0'; end if; end process; process (state_out, valid_in, fault_out, flit_type, health_info) begin if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type /= "100" and health_info = '1') then err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info <= '1'; else err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info <= '0'; end if; end process; process (state_out, valid_in, fault_out, health_info) begin if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and health_info = '1') then err_state_out_Body_flit_valid_in_fault_out_not_health_info <= '1'; else err_state_out_Body_flit_valid_in_fault_out_not_health_info <= '0'; end if; end process; process (state_out, valid_in, health_info) begin if (state_out = Body_flit and valid_in = '0' and health_info = '1') then err_state_out_Body_flit_valid_in_not_health_info <= '1'; else err_state_out_Body_flit_valid_in_not_health_info <= '0'; end if; end process; process (state_out, valid_in, fault_out, write_fake_flit) begin if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and write_fake_flit = '1') then err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit <= '1'; else err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit <= '0'; end if; end process; process (state_out, valid_in, fault_out, fault_info_in) begin if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and fault_info_in = '1') then err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in <= '1'; else err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in <= '0'; end if; end process; process (state_out, valid_in, fault_out, faulty_packet_in, faulty_packet_out) begin if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1'; else err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0'; end if; end process; -- fault_out = '1' -------------------------------------------------------------------------------------------------- process (state_out, valid_in, fault_out, write_fake_flit) begin if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and write_fake_flit = '0') then err_state_out_Body_flit_valid_in_fault_out_write_fake_flit <= '1'; else err_state_out_Body_flit_valid_in_fault_out_write_fake_flit <= '0'; end if; end process; process (state_out, valid_in, fault_out, state_in) begin if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and state_in /= Packet_drop) then err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop <= '1'; else err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop <= '0'; end if; end process; process (state_out, valid_in, fault_out, fault_info_in) begin if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and fault_info_in = '0') then err_state_out_Body_flit_valid_in_fault_out_fault_info_in <= '1'; else err_state_out_Body_flit_valid_in_fault_out_fault_info_in <= '0'; end if; end process; process (state_out, valid_in, fault_out, faulty_packet_in) begin if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and faulty_packet_in /= '1') then err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in <= '1'; else err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in <= '0'; end if; end process; process (state_out, valid_in, state_in) begin if (state_out = Body_flit and valid_in = '0' and state_in /= state_out) then err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change <= '1'; else err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change <= '0'; end if; end process; process (state_out, valid_in, faulty_packet_in, faulty_packet_out) begin if (state_out = Body_flit and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '1'; else err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '0'; end if; end process; process (state_out, valid_in, fault_info_in) begin if (state_out = Body_flit and valid_in = '0' and fault_info_in = '1') then err_state_out_Body_flit_not_valid_in_not_fault_info_in <= '1'; else err_state_out_Body_flit_not_valid_in_not_fault_info_in <= '0'; end if; end process; process (state_out, fake_credit) begin if (state_out = Body_flit and fake_credit = '1') then err_state_out_Body_flit_not_fake_credit <= '1'; else err_state_out_Body_flit_not_fake_credit <= '0'; end if; end process; process (state_out, valid_in, write_fake_flit) begin if (state_out = Body_flit and valid_in = '0' and write_fake_flit = '1') then err_state_out_Body_flit_not_valid_in_not_write_fake_flit <= '1'; else err_state_out_Body_flit_not_valid_in_not_write_fake_flit <= '0'; end if; end process; -------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------- -- Tail_flit state -- fault_out = '0' -------------------------------------------------------------------------------------------------- process (state_out, valid_in, fault_out, flit_type, state_in) begin if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and flit_type = "001" and state_in /= Header_flit) then err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit <= '1'; else err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit <= '0'; end if; end process; process (state_out, valid_in, fault_out, fake_credit) begin if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and fake_credit = '1') then err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit <= '1'; else err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit <= '0'; end if; end process; process (state_out, valid_in, fault_out, fault_info_in) begin if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and fault_info_in = '1') then err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in <= '1'; else err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in <= '0'; end if; end process; process (state_out, valid_in, fault_out, faulty_packet_in, faulty_packet_out) begin if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1'; else err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0'; end if; end process; -- fault_out = '1' -------------------------------------------------------------------------------------------------- process (state_out, valid_in, fault_out, fake_credit) begin if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and fake_credit /= '1') then err_state_out_Tail_flit_valid_in_fault_out_fake_credit <= '1'; else err_state_out_Tail_flit_valid_in_fault_out_fake_credit <= '0'; end if; end process; process (state_out, valid_in, fault_out, state_in) begin if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and state_in /= Packet_drop) then err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop <= '1'; else err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop <= '0'; end if; end process; process (state_out, valid_in, fault_out, fault_info_in) begin if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and fault_info_in = '0') then err_state_out_Tail_flit_valid_in_fault_out_fault_info_in <= '1'; else err_state_out_Tail_flit_valid_in_fault_out_fault_info_in <= '0'; end if; end process; process (state_out, valid_in, fault_out, faulty_packet_in) begin if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and faulty_packet_in /= '1') then err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in <= '1'; else err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in <= '0'; end if; end process; process (state_out, valid_in, state_in) begin if (state_out = Tail_flit and valid_in = '0' and state_in /= Idle) then err_state_out_Tail_flit_not_valid_in_state_in_Idle <= '1'; else err_state_out_Tail_flit_not_valid_in_state_in_Idle <= '0'; end if; end process; process (state_out, valid_in, faulty_packet_in, faulty_packet_out) begin if (state_out = Tail_flit and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change <= '1'; else err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change <= '0'; end if; end process; process (state_out, valid_in, fault_info_in) begin if (state_out = Tail_flit and valid_in = '0' and fault_info_in = '1') then err_state_out_Tail_flit_not_valid_in_not_fault_info_in <= '1'; else err_state_out_Tail_flit_not_valid_in_not_fault_info_in <= '0'; end if; end process; process (state_out, valid_in, fake_credit) begin if (state_out = Tail_flit and valid_in = '0' and fake_credit /= '0') then err_state_out_Tail_flit_not_valid_in_not_fake_credit <= '1'; else err_state_out_Tail_flit_not_valid_in_not_fake_credit <= '0'; end if; end process; process (state_out, write_fake_flit) begin if (state_out = Tail_flit and write_fake_flit = '1') then err_state_out_Tail_flit_not_write_fake_flit <= '1'; else err_state_out_Tail_flit_not_write_fake_flit <= '0'; end if; end process; -------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------- -- Packet_drop state -- faulty_packet_out = '1' -------------------------------------------------------------------------------------------------- process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, fake_credit) begin if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and fake_credit /= '0') then err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit <= '1'; else err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, faulty_packet_in) begin if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and faulty_packet_in /= '0') then err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in <= '1'; else err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in) begin if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and state_in /= Header_flit) then err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit <= '1'; else err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, write_fake_flit) begin if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and write_fake_flit = '0') then err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit <= '1'; else err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in, state_out) begin if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '1' and state_in /= state_out) then err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change <= '1'; else err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, faulty_packet_in) begin if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '0' and faulty_packet_in /= '0') then err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in <= '1'; else err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in, state_out) begin if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '1' and state_in /= state_out) then err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change <= '1'; else err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in) begin if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '0' and state_in /= Idle) then err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle <= '1'; else err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, fake_credit) begin if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '0' and fake_credit = '0') then err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit <= '1'; else err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, fake_credit) begin if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and ((flit_type /= "001" and flit_type /= "100") or fault_out = '1') and fake_credit = '0') then err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit <= '1'; else err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, faulty_packet_in, faulty_packet_out) begin if (state_out = Packet_drop and faulty_packet_out = '1' and ( valid_in = '0' or (flit_type /= "001" and flit_type /= "100") or fault_out = '1' ) and faulty_packet_in /= faulty_packet_out) then err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1'; else err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in, state_out) begin if (state_out = Packet_drop and faulty_packet_out = '1' and ((flit_type /= "001" and flit_type /= "100") or fault_out = '1') and state_in /= state_out) then err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change <= '1'; else err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, faulty_packet_in, faulty_packet_out) begin if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal <= '1'; else err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, state_in, state_out) begin if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and state_in /= state_out) then err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change <= '1'; else err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, write_fake_flit) begin if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and write_fake_flit = '1') then err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit <= '1'; else err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, fake_credit) begin if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and fake_credit = '1') then err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit <= '1'; else err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit <= '0'; end if; end process; -- faulty_packet_out = '0' -------------------------------------------------------------------------------------------------- process (state_out, faulty_packet_out, state_in, state_out) begin if (state_out = Packet_drop and faulty_packet_out = '0' and state_in /= state_out) then err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change <= '1'; else err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change <= '0'; end if; end process; process (state_out, faulty_packet_out, faulty_packet_in, faulty_packet_out) begin if (state_out = Packet_drop and faulty_packet_out = '0' and faulty_packet_in /= faulty_packet_out) then err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change <= '1'; else err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change <= '0'; end if; end process; process (state_out, fault_info_in) begin if (state_out = Packet_drop and fault_info_in = '1') then err_state_out_Packet_drop_not_fault_info_in <= '1'; else err_state_out_Packet_drop_not_fault_info_in <= '0'; end if; end process; process (state_out, faulty_packet_out, fake_credit) begin if (state_out = Packet_drop and faulty_packet_out = '0' and fake_credit = '1') then err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit <= '1'; else err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, write_fake_flit) begin if (state_out = Packet_drop and faulty_packet_out = '1' and (valid_in = '0' or flit_type /= "001" or fault_out = '1') and write_fake_flit = '1') then err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit <= '1'; else err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit <= '0'; end if; end process; process (state_out, faulty_packet_out, write_fake_flit) begin if (state_out = Packet_drop and faulty_packet_out = '0' and write_fake_flit = '1') then err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit <= '1'; else err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit <= '0'; end if; end process; process (fault_info, fault_info_out) begin if (fault_info /= fault_info_out) then err_fault_info_fault_info_out_equal <= '1'; else err_fault_info_fault_info_out_equal <= '0'; end if; end process; process (state_out, valid_in, state_in, state_out) begin if (state_out = Packet_drop and valid_in = '0' and state_in /= state_out) then err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal <= '1'; else err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal <= '0'; end if; end process; process (state_out, valid_in, fault_out, flit_type, state_in, state_out) begin if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and flit_type /= "001" and state_in /= state_out) then err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal <= '1'; else err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal <= '0'; end if; end process; -- Added after change of design ! process (state_out, faulty_packet_out, valid_in, flit_type, fault_info_in) begin if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_info_in /= '1') then err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in <= '1'; else err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, fault_info_in) begin if (state_out = Packet_drop and faulty_packet_out = '1' and (valid_in = '0' or flit_type /= "001") and fault_info_in /= '0') then err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in <= '1'; else err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in <= '0'; end if; end process; end behavior;
--Copyright (C) 2016 Siavoosh Payandeh Azad and Behrad Niazmand library ieee; use ieee.std_logic_1164.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.ALL; entity FIFO_credit_based_control_part_checkers is port ( valid_in: in std_logic; read_en_N : in std_logic; read_en_E : in std_logic; read_en_W : in std_logic; read_en_S : in std_logic; read_en_L : in std_logic; read_pointer: in std_logic_vector(3 downto 0); read_pointer_in: in std_logic_vector(3 downto 0); write_pointer: in std_logic_vector(3 downto 0); write_pointer_in: in std_logic_vector(3 downto 0); credit_out: in std_logic; empty_out: in std_logic; full_out: in std_logic; read_en_out: in std_logic; write_en_out: in std_logic; fake_credit: in std_logic; fake_credit_counter: in std_logic_vector(1 downto 0); fake_credit_counter_in: in std_logic_vector(1 downto 0); state_out: in std_logic_vector(4 downto 0); state_in: in std_logic_vector(4 downto 0); fault_info: in std_logic; fault_info_out: in std_logic; fault_info_in: in std_logic; health_info: in std_logic; faulty_packet_out: in std_logic; faulty_packet_in: in std_logic; flit_type: in std_logic_vector(2 downto 0); fault_out: in std_logic; write_fake_flit: in std_logic; -- Functional checkers err_empty_full, err_empty_read_en, err_full_write_en, err_state_in_onehot, err_read_pointer_in_onehot, err_write_pointer_in_onehot, -- Structural checkers err_write_en_write_pointer, err_not_write_en_write_pointer, err_read_pointer_write_pointer_not_empty, err_read_pointer_write_pointer_empty, err_read_pointer_write_pointer_not_full, err_read_pointer_write_pointer_full, err_read_pointer_increment, err_read_pointer_not_increment, err_write_en, err_not_write_en, err_not_write_en1, err_not_write_en2, err_read_en_mismatch, err_read_en_mismatch1, -- Newly added checkers for FIFO with packet drop and fault classifier support! err_fake_credit_read_en_fake_credit_counter_in_increment, err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement, err_not_fake_credit_read_en_fake_credit_counter_in_not_change, err_fake_credit_not_read_en_fake_credit_counter_in_not_change, err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change, err_fake_credit_read_en_credit_out, err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out, err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out, -- Checkers for Packet Dropping FSM of FIFO err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit, err_state_out_Idle_not_fault_out_valid_in_state_in_not_change, err_state_out_Idle_not_fault_out_not_fake_credit, err_state_out_Idle_not_fault_out_not_fault_info_in, err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal, err_state_out_Idle_fault_out_fake_credit, err_state_out_Idle_fault_out_state_in_Packet_drop, err_state_out_Idle_fault_out_fault_info_in, err_state_out_Idle_fault_out_faulty_packet_in, err_state_out_Idle_not_health_info, err_state_out_Idle_not_write_fake_flit, err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit, err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit, err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit, err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in, err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Header_flit_valid_in_fault_out_write_fake_flit, err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Header_flit_valid_in_fault_out_fault_info_in, err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change, err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Header_flit_not_valid_in_not_fault_info_in, err_state_out_Header_flit_not_valid_in_not_write_fake_flit, err_state_out_Header_flit_or_Body_flit_not_fake_credit, err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change, err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit, err_state_out_Body_flit_valid_in_not_fault_out_health_info, err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit, err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in, err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Body_flit_valid_in_fault_out_write_fake_flit, err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Body_flit_valid_in_fault_out_fault_info_in, err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change, err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Body_flit_not_valid_in_not_fault_info_in, err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info, err_state_out_Body_flit_valid_in_fault_out_not_health_info, err_state_out_Body_flit_valid_in_not_health_info, err_state_out_Body_flit_not_fake_credit, err_state_out_Body_flit_not_valid_in_not_write_fake_flit, err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit, err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit, err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in, err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Tail_flit_valid_in_fault_out_fake_credit, err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop, err_state_out_Tail_flit_valid_in_fault_out_fault_info_in, err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in, err_state_out_Tail_flit_not_valid_in_state_in_Idle, err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change, err_state_out_Tail_flit_not_valid_in_not_fault_info_in, err_state_out_Tail_flit_not_valid_in_not_fake_credit, err_state_out_Tail_flit_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit, err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change, err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change, err_state_out_Packet_drop_not_fault_info_in, err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit, err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change, err_fault_info_fault_info_out_equal, err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal, err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal, err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in, err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in : out std_logic ); end FIFO_credit_based_control_part_checkers; architecture behavior of FIFO_credit_based_control_part_checkers is CONSTANT Idle: std_logic_vector (4 downto 0) := "00001"; CONSTANT Header_flit: std_logic_vector (4 downto 0) := "00010"; CONSTANT Body_flit: std_logic_vector (4 downto 0) := "00100"; CONSTANT Tail_flit: std_logic_vector (4 downto 0) := "01000"; CONSTANT Packet_drop: std_logic_vector (4 downto 0) := "10000"; begin -- Functional Checkers (Might cover or be covered by some of the structural checkers) -- Empty and full cannot be high at the same time! process (empty_out, full_out) begin if (empty_out = '1' and full_out = '1') then err_empty_full <= '1'; else err_empty_full <= '0'; end if; end process; -- Reading from an empty FIFO is not possible! process (empty_out, read_en_out) begin if (empty_out = '1' and read_en_out = '1') then err_empty_read_en <= '1'; else err_empty_read_en <= '0'; end if; end process; -- Writing to a full FIFO is not possible! process (full_out, write_en_out) begin if (full_out = '1' and write_en_out = '1') then err_full_write_en <= '1'; else err_full_write_en <= '0'; end if; end process; -- The states of the packet dropping FSM of FIFO must always be one-hot (state_in)! process (state_in) begin if (state_in /= Idle and state_in /= Header_flit and state_in /= Body_flit and state_in /= Tail_flit and state_in /= Packet_drop) then err_state_in_onehot <= '1'; else err_state_in_onehot <= '0'; end if; end process; -- Read pointer must always be one-hot! process (read_pointer_in) begin if (read_pointer_in /= "0001" and read_pointer_in /= "0010" and read_pointer_in /= "0100" and read_pointer_in /= "1000") then err_read_pointer_in_onehot <= '1'; else err_read_pointer_in_onehot <= '0'; end if; end process; -- Write pointer must always be one-hot! process (write_pointer_in) begin if (write_pointer_in /= "0001" and write_pointer_in /= "0010" and write_pointer_in /= "0100" and write_pointer_in /= "1000") then err_write_pointer_in_onehot <= '1'; else err_write_pointer_in_onehot <= '0'; end if; end process; --------------------------------------------------------------------------------------------------------- -- Structural Checkers -- Write pointer and Read pointer checkers process (write_en_out, write_pointer_in, write_pointer) begin if (write_en_out = '1' and write_pointer_in /= (write_pointer(2 downto 0) & write_pointer(3)) ) then err_write_en_write_pointer <= '1'; else err_write_en_write_pointer <= '0'; end if; end process; -- Checked ! process (write_en_out, write_pointer_in, write_pointer) begin if (write_en_out = '0' and write_pointer_in /= write_pointer ) then err_not_write_en_write_pointer <= '1'; else err_not_write_en_write_pointer <= '0'; end if; end process; -- Checked ! process (read_pointer, write_pointer, empty_out) begin if (read_pointer = write_pointer and empty_out = '0' ) then err_read_pointer_write_pointer_not_empty <= '1'; else err_read_pointer_write_pointer_not_empty <= '0'; end if; end process; -- Checked ! process (read_pointer, write_pointer, empty_out) begin if (read_pointer /= write_pointer and empty_out = '1' ) then err_read_pointer_write_pointer_empty <= '1'; else err_read_pointer_write_pointer_empty <= '0'; end if; end process; -- Checked ! process (write_pointer, read_pointer, full_out) begin if (write_pointer = (read_pointer(0)&read_pointer(3 downto 1)) and full_out = '0' ) then err_read_pointer_write_pointer_not_full <= '1'; else err_read_pointer_write_pointer_not_full <= '0'; end if; end process; -- Checked ! process (write_pointer, read_pointer, full_out) begin if (write_pointer /= (read_pointer(0)&read_pointer(3 downto 1)) and full_out = '1' ) then err_read_pointer_write_pointer_full <= '1'; else err_read_pointer_write_pointer_full <= '0'; end if; end process; -- Checked ! process (read_en_out, empty_out, read_pointer_in, read_pointer) begin if (read_en_out = '1' and empty_out = '0' and read_pointer_in /= (read_pointer(2 downto 0)&read_pointer(3)) ) then err_read_pointer_increment <= '1'; else err_read_pointer_increment <= '0'; end if; end process; -- Checked ! process (read_en_out, empty_out, read_pointer_in, read_pointer) begin if ( (read_en_out = '0' or empty_out = '1') and read_pointer_in /= read_pointer ) then err_read_pointer_not_increment <= '1'; else err_read_pointer_not_increment <= '0'; end if; end process; -- Checked ! process (valid_in, faulty_packet_out, fault_out, write_fake_flit, full_out, write_en_out) begin if (valid_in = '1' and ((faulty_packet_out = '0' and fault_out = '0') or write_fake_flit = '1') and full_out ='0' and write_en_out = '0') then err_write_en <= '1'; else err_write_en <= '0'; end if; end process; -- Updated ! process (valid_in, faulty_packet_out, fault_out, write_fake_flit, full_out, write_en_out) begin if ( (valid_in = '0' or (((faulty_packet_out = '1' or fault_out = '1') and write_fake_flit = '0')) or full_out = '1') and write_en_out = '1') then err_not_write_en <= '1'; else err_not_write_en <= '0'; end if; end process; process (valid_in, faulty_packet_out, fault_out, write_fake_flit, full_out, write_en_out) begin if ( valid_in = '1' and ((faulty_packet_out = '1' or fault_out = '1') and write_fake_flit = '0') and write_en_out = '1') then err_not_write_en1 <= '1'; else err_not_write_en1 <= '0'; end if; end process; process (valid_in, faulty_packet_out, fault_out, write_fake_flit, full_out, write_en_out) begin if ( valid_in = '1' and ((faulty_packet_out = '0' and fault_out = '0') or write_fake_flit = '1') and full_out = '1' and write_en_out = '1') then err_not_write_en2 <= '1'; else err_not_write_en2 <= '0'; end if; end process; -- Updated ! process (read_en_N, read_en_E, read_en_W, read_en_S, read_en_L, empty_out, read_en_out) begin if ( (read_en_N = '1' or read_en_E = '1' or read_en_W = '1' or read_en_S = '1' or read_en_L = '1') and empty_out = '0' and read_en_out = '0' ) then err_read_en_mismatch <= '1'; else err_read_en_mismatch <= '0'; end if; end process; process (read_en_N, read_en_E, read_en_W, read_en_S, read_en_L, empty_out, read_en_out) begin if ( ((read_en_N = '0' and read_en_E = '0' and read_en_W = '0' and read_en_S = '0' and read_en_L = '0') or empty_out = '1') and read_en_out = '1' ) then err_read_en_mismatch1 <= '1'; else err_read_en_mismatch1 <= '0'; end if; end process; -- Newly added checkers for FIFO with packet drop and fault classifier support! process (fake_credit, read_en_out, fake_credit_counter_in, fake_credit_counter) begin if (fake_credit = '1' and read_en_out = '1' and fake_credit_counter_in /= fake_credit_counter + 1) then err_fake_credit_read_en_fake_credit_counter_in_increment <= '1'; else err_fake_credit_read_en_fake_credit_counter_in_increment <= '0'; end if; end process; process (fake_credit, read_en_out, fake_credit_counter, fake_credit_counter_in) begin if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter > 0 and fake_credit_counter_in /= fake_credit_counter - 1 ) then err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement <= '1'; else err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_fake_credit_counter_in_decrement <= '0'; end if; end process; process (fake_credit, read_en_out, fake_credit_counter_in, fake_credit_counter) begin if (fake_credit = '0' and read_en_out = '1' and fake_credit_counter_in /= fake_credit_counter) then err_not_fake_credit_read_en_fake_credit_counter_in_not_change <= '1'; else err_not_fake_credit_read_en_fake_credit_counter_in_not_change <= '0'; end if; end process; process (fake_credit, read_en_out, fake_credit_counter_in, fake_credit_counter) begin if (fake_credit = '1' and read_en_out = '0' and fake_credit_counter_in /= fake_credit_counter) then err_fake_credit_not_read_en_fake_credit_counter_in_not_change <= '1'; else err_fake_credit_not_read_en_fake_credit_counter_in_not_change <= '0'; end if; end process; process (fake_credit, read_en_out, fake_credit_counter, fake_credit_counter_in) begin if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter <= 0 and fake_credit_counter_in /= fake_credit_counter) then err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change <= '1'; else err_not_fake_credit_not_read_en_fake_credit_counter_zero_fake_credit_counter_in_not_change <= '0'; end if; end process; process (fake_credit, read_en_out, credit_out) begin if ((fake_credit = '1' or read_en_out ='1') and credit_out = '0') then err_fake_credit_read_en_credit_out <= '1'; else err_fake_credit_read_en_credit_out <= '0'; end if; end process; process (fake_credit, read_en_out, fake_credit_counter, credit_out) begin if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter > 0 and credit_out = '0') then err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out <= '1'; else err_not_fake_credit_not_read_en_fake_credit_counter_not_zero_credit_out <= '0'; end if; end process; process (fake_credit, read_en_out, fake_credit_counter, credit_out) begin if (fake_credit = '0' and read_en_out = '0' and fake_credit_counter <= 0 and credit_out = '1') then err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out <= '1'; else err_not_fake_credit_not_read_en_fake_credit_counter_zero_not_credit_out <= '0'; end if; end process; -------------------------------------------------------------------------------------------------- -- Idle state -- fault_out = '0' -------------------------------------------------------------------------------------------------- process (state_out, fault_out, valid_in, state_in) begin if (state_out = Idle and fault_out = '0' and valid_in = '1' and state_in /= Header_flit) then err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit <= '1'; else err_state_out_Idle_not_fault_out_valid_in_state_in_Header_flit <= '0'; end if; end process; process (state_out, fault_out, valid_in, state_in, state_out) begin if (state_out = Idle and fault_out = '0' and valid_in = '0' and state_in /= state_out) then err_state_out_Idle_not_fault_out_valid_in_state_in_not_change <= '1'; else err_state_out_Idle_not_fault_out_valid_in_state_in_not_change <= '0'; end if; end process; process (state_out, fault_out, fake_credit) begin if (state_out = Idle and fault_out = '0' and fake_credit = '1') then err_state_out_Idle_not_fault_out_not_fake_credit <= '1'; else err_state_out_Idle_not_fault_out_not_fake_credit <= '0'; end if; end process; process (state_out, fault_out, fault_info_in) begin if (state_out = Idle and fault_out = '0' and fault_info_in = '1') then err_state_out_Idle_not_fault_out_not_fault_info_in <= '1'; else err_state_out_Idle_not_fault_out_not_fault_info_in <= '0'; end if; end process; process (state_out, fault_out, faulty_packet_in, faulty_packet_out) begin if (state_out = Idle and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal <= '1'; else err_state_out_Idle_not_fault_out_faulty_packet_in_faulty_packet_out_equal <= '0'; end if; end process; -- fault_out = '1' -------------------------------------------------------------------------------------------------- process (state_out, fault_out, fake_credit) begin if (state_out = Idle and fault_out = '1' and fake_credit = '0') then err_state_out_Idle_fault_out_fake_credit <= '1'; else err_state_out_Idle_fault_out_fake_credit <= '0'; end if; end process; process (state_out, fault_out, state_in) begin if (state_out = Idle and fault_out = '1' and state_in /= Packet_drop) then err_state_out_Idle_fault_out_state_in_Packet_drop <= '1'; else err_state_out_Idle_fault_out_state_in_Packet_drop <= '0'; end if; end process; process (state_out, fault_out, fault_info_in) begin if (state_out = Idle and fault_out = '1' and fault_info_in = '0') then err_state_out_Idle_fault_out_fault_info_in <= '1'; else err_state_out_Idle_fault_out_fault_info_in <= '0'; end if; end process; process (state_out, fault_out, faulty_packet_in) begin if (state_out = Idle and fault_out = '1' and faulty_packet_in /= '1') then err_state_out_Idle_fault_out_faulty_packet_in <= '1'; else err_state_out_Idle_fault_out_faulty_packet_in <= '0'; end if; end process; process (state_out, write_fake_flit) begin if (state_out = Idle and write_fake_flit = '1') then err_state_out_Idle_not_write_fake_flit <= '1'; else err_state_out_Idle_not_write_fake_flit <= '0'; end if; end process; -- Other properties for Idle state -------------------------------------------------------------------------------------------------- process (state_out, health_info) begin if ( (state_out = Idle or state_out = Header_flit or state_out = Tail_flit or state_out = Packet_drop) and health_info = '1') then err_state_out_Idle_not_health_info <= '1'; else err_state_out_Idle_not_health_info <= '0'; end if; end process; -------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------- -- Header_flit state -- fault_out = '0' -------------------------------------------------------------------------------------------------- process (state_out, valid_in, fault_out, flit_type, state_in) begin if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and flit_type = "010" and state_in /= Body_flit) then err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit <= '1'; else err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Body_state_in_Body_flit <= '0'; end if; end process; process (state_out, valid_in, fault_out, flit_type, state_in) begin if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and flit_type = "100" and state_in /= Tail_flit) then err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit <= '1'; else err_state_out_Header_flit_valid_in_not_fault_out_flit_type_Tail_state_in_Tail_flit <= '0'; end if; end process; process (state_out, valid_in, fault_out, write_fake_flit) begin if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and write_fake_flit = '1') then err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit <= '1'; else err_state_out_Header_flit_valid_in_not_fault_out_not_write_fake_flit <= '0'; end if; end process; process (state_out, valid_in, fault_out, fault_info_in) begin if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and fault_info_in = '1') then err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in <= '1'; else err_state_out_Header_flit_valid_in_not_fault_out_not_fault_info_in <= '0'; end if; end process; process (state_out, valid_in, fault_out, faulty_packet_in, faulty_packet_out) begin if (state_out = Header_flit and valid_in = '1' and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1'; else err_state_out_Header_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0'; end if; end process; -- fault_out = '1' -------------------------------------------------------------------------------------------------- process (state_out, valid_in, fault_out, write_fake_flit) begin if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and write_fake_flit = '0') then err_state_out_Header_flit_valid_in_fault_out_write_fake_flit <= '1'; else err_state_out_Header_flit_valid_in_fault_out_write_fake_flit <= '0'; end if; end process; process (state_out, valid_in, fault_out, state_in) begin if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and state_in /= Packet_drop) then err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop <= '1'; else err_state_out_Header_flit_valid_in_fault_out_state_in_Packet_drop <= '0'; end if; end process; process (state_out, valid_in, fault_out, fault_info_in) begin if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and fault_info_in = '0') then err_state_out_Header_flit_valid_in_fault_out_fault_info_in <= '1'; else err_state_out_Header_flit_valid_in_fault_out_fault_info_in <= '0'; end if; end process; process (state_out, valid_in, fault_out, faulty_packet_in) begin if (state_out = Header_flit and valid_in = '1' and fault_out = '1' and faulty_packet_in /= '1') then err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in <= '1'; else err_state_out_Header_flit_valid_in_fault_out_faulty_packet_in <= '0'; end if; end process; process (state_out, valid_in, state_in, state_out) begin if (state_out = Header_flit and valid_in = '0' and state_in /= state_out) then err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change <= '1'; else err_state_out_Header_flit_not_valid_in_state_in_state_out_not_change <= '0'; end if; end process; process (state_out, valid_in, faulty_packet_in, faulty_packet_out) begin if (state_out = Header_flit and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '1'; else err_state_out_Header_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '0'; end if; end process; process (state_out, valid_in, fault_info_in) begin if (state_out = Header_flit and valid_in = '0' and fault_info_in = '1') then err_state_out_Header_flit_not_valid_in_not_fault_info_in <= '1'; else err_state_out_Header_flit_not_valid_in_not_fault_info_in <= '0'; end if; end process; process (state_out, valid_in, write_fake_flit) begin if (state_out = Header_flit and valid_in = '0' and write_fake_flit = '1') then err_state_out_Header_flit_not_valid_in_not_write_fake_flit <= '1'; else err_state_out_Header_flit_not_valid_in_not_write_fake_flit <= '0'; end if; end process; process (state_out, fake_credit) begin if ( (state_out = Header_flit or state_out = Body_flit) and fake_credit /= '0') then err_state_out_Header_flit_or_Body_flit_not_fake_credit <= '1'; else err_state_out_Header_flit_or_Body_flit_not_fake_credit <= '0'; end if; end process; -------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------- -- Body_flit state -- fault_out = '0' -------------------------------------------------------------------------------------------------- process (state_out, valid_in, fault_out, flit_type, state_in, state_out) begin if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type = "010" and state_in /= state_out) then err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change <= '1'; else err_state_out_Body_flit_valid_in_not_fault_out_state_in_state_out_not_change <= '0'; end if; end process; process (state_out, valid_in, fault_out, flit_type, state_in) begin if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type = "100" and state_in /= Tail_flit) then err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit <= '1'; else err_state_out_Body_flit_valid_in_not_fault_out_state_in_Tail_flit <= '0'; end if; end process; process (state_out, valid_in, fault_out, flit_type, health_info) begin if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type = "100" and health_info = '0') then err_state_out_Body_flit_valid_in_not_fault_out_health_info <= '1'; else err_state_out_Body_flit_valid_in_not_fault_out_health_info <= '0'; end if; end process; process (state_out, valid_in, fault_out, flit_type, health_info) begin if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and flit_type /= "100" and health_info = '1') then err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info <= '1'; else err_state_out_Body_flit_valid_in_not_fault_out_flit_type_not_tail_not_health_info <= '0'; end if; end process; process (state_out, valid_in, fault_out, health_info) begin if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and health_info = '1') then err_state_out_Body_flit_valid_in_fault_out_not_health_info <= '1'; else err_state_out_Body_flit_valid_in_fault_out_not_health_info <= '0'; end if; end process; process (state_out, valid_in, health_info) begin if (state_out = Body_flit and valid_in = '0' and health_info = '1') then err_state_out_Body_flit_valid_in_not_health_info <= '1'; else err_state_out_Body_flit_valid_in_not_health_info <= '0'; end if; end process; process (state_out, valid_in, fault_out, write_fake_flit) begin if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and write_fake_flit = '1') then err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit <= '1'; else err_state_out_Body_flit_valid_in_not_fault_out_not_write_fake_flit <= '0'; end if; end process; process (state_out, valid_in, fault_out, fault_info_in) begin if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and fault_info_in = '1') then err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in <= '1'; else err_state_out_Body_flit_valid_in_not_fault_out_fault_info_in <= '0'; end if; end process; process (state_out, valid_in, fault_out, faulty_packet_in, faulty_packet_out) begin if (state_out = Body_flit and valid_in = '1' and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1'; else err_state_out_Body_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0'; end if; end process; -- fault_out = '1' -------------------------------------------------------------------------------------------------- process (state_out, valid_in, fault_out, write_fake_flit) begin if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and write_fake_flit = '0') then err_state_out_Body_flit_valid_in_fault_out_write_fake_flit <= '1'; else err_state_out_Body_flit_valid_in_fault_out_write_fake_flit <= '0'; end if; end process; process (state_out, valid_in, fault_out, state_in) begin if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and state_in /= Packet_drop) then err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop <= '1'; else err_state_out_Body_flit_valid_in_fault_out_state_in_Packet_drop <= '0'; end if; end process; process (state_out, valid_in, fault_out, fault_info_in) begin if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and fault_info_in = '0') then err_state_out_Body_flit_valid_in_fault_out_fault_info_in <= '1'; else err_state_out_Body_flit_valid_in_fault_out_fault_info_in <= '0'; end if; end process; process (state_out, valid_in, fault_out, faulty_packet_in) begin if (state_out = Body_flit and valid_in = '1' and fault_out = '1' and faulty_packet_in /= '1') then err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in <= '1'; else err_state_out_Body_flit_valid_in_fault_out_faulty_packet_in <= '0'; end if; end process; process (state_out, valid_in, state_in) begin if (state_out = Body_flit and valid_in = '0' and state_in /= state_out) then err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change <= '1'; else err_state_out_Body_flit_not_valid_in_state_in_state_out_not_change <= '0'; end if; end process; process (state_out, valid_in, faulty_packet_in, faulty_packet_out) begin if (state_out = Body_flit and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '1'; else err_state_out_Body_flit_not_valid_in_faulty_packet_in_faulty_packet_out_not_change <= '0'; end if; end process; process (state_out, valid_in, fault_info_in) begin if (state_out = Body_flit and valid_in = '0' and fault_info_in = '1') then err_state_out_Body_flit_not_valid_in_not_fault_info_in <= '1'; else err_state_out_Body_flit_not_valid_in_not_fault_info_in <= '0'; end if; end process; process (state_out, fake_credit) begin if (state_out = Body_flit and fake_credit = '1') then err_state_out_Body_flit_not_fake_credit <= '1'; else err_state_out_Body_flit_not_fake_credit <= '0'; end if; end process; process (state_out, valid_in, write_fake_flit) begin if (state_out = Body_flit and valid_in = '0' and write_fake_flit = '1') then err_state_out_Body_flit_not_valid_in_not_write_fake_flit <= '1'; else err_state_out_Body_flit_not_valid_in_not_write_fake_flit <= '0'; end if; end process; -------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------- -- Tail_flit state -- fault_out = '0' -------------------------------------------------------------------------------------------------- process (state_out, valid_in, fault_out, flit_type, state_in) begin if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and flit_type = "001" and state_in /= Header_flit) then err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit <= '1'; else err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_Header_state_in_Header_flit <= '0'; end if; end process; process (state_out, valid_in, fault_out, fake_credit) begin if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and fake_credit = '1') then err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit <= '1'; else err_state_out_Tail_flit_valid_in_not_fault_out_not_fake_credit <= '0'; end if; end process; process (state_out, valid_in, fault_out, fault_info_in) begin if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and fault_info_in = '1') then err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in <= '1'; else err_state_out_Tail_flit_valid_in_not_fault_out_not_fault_info_in <= '0'; end if; end process; process (state_out, valid_in, fault_out, faulty_packet_in, faulty_packet_out) begin if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and faulty_packet_in /= faulty_packet_out) then err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1'; else err_state_out_Tail_flit_valid_in_not_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0'; end if; end process; -- fault_out = '1' -------------------------------------------------------------------------------------------------- process (state_out, valid_in, fault_out, fake_credit) begin if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and fake_credit /= '1') then err_state_out_Tail_flit_valid_in_fault_out_fake_credit <= '1'; else err_state_out_Tail_flit_valid_in_fault_out_fake_credit <= '0'; end if; end process; process (state_out, valid_in, fault_out, state_in) begin if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and state_in /= Packet_drop) then err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop <= '1'; else err_state_out_Tail_flit_valid_in_fault_out_state_in_Packet_drop <= '0'; end if; end process; process (state_out, valid_in, fault_out, fault_info_in) begin if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and fault_info_in = '0') then err_state_out_Tail_flit_valid_in_fault_out_fault_info_in <= '1'; else err_state_out_Tail_flit_valid_in_fault_out_fault_info_in <= '0'; end if; end process; process (state_out, valid_in, fault_out, faulty_packet_in) begin if (state_out = Tail_flit and valid_in = '1' and fault_out = '1' and faulty_packet_in /= '1') then err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in <= '1'; else err_state_out_Tail_flit_valid_in_fault_out_faulty_packet_in <= '0'; end if; end process; process (state_out, valid_in, state_in) begin if (state_out = Tail_flit and valid_in = '0' and state_in /= Idle) then err_state_out_Tail_flit_not_valid_in_state_in_Idle <= '1'; else err_state_out_Tail_flit_not_valid_in_state_in_Idle <= '0'; end if; end process; process (state_out, valid_in, faulty_packet_in, faulty_packet_out) begin if (state_out = Tail_flit and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change <= '1'; else err_state_out_Tail_flit_not_valid_in_faulty_packet_in_faulty_packet_in_not_change <= '0'; end if; end process; process (state_out, valid_in, fault_info_in) begin if (state_out = Tail_flit and valid_in = '0' and fault_info_in = '1') then err_state_out_Tail_flit_not_valid_in_not_fault_info_in <= '1'; else err_state_out_Tail_flit_not_valid_in_not_fault_info_in <= '0'; end if; end process; process (state_out, valid_in, fake_credit) begin if (state_out = Tail_flit and valid_in = '0' and fake_credit /= '0') then err_state_out_Tail_flit_not_valid_in_not_fake_credit <= '1'; else err_state_out_Tail_flit_not_valid_in_not_fake_credit <= '0'; end if; end process; process (state_out, write_fake_flit) begin if (state_out = Tail_flit and write_fake_flit = '1') then err_state_out_Tail_flit_not_write_fake_flit <= '1'; else err_state_out_Tail_flit_not_write_fake_flit <= '0'; end if; end process; -------------------------------------------------------------------------------------------------- -------------------------------------------------------------------------------------------------- -- Packet_drop state -- faulty_packet_out = '1' -------------------------------------------------------------------------------------------------- process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, fake_credit) begin if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and fake_credit /= '0') then err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit <= '1'; else err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_fake_credit <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, faulty_packet_in) begin if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and faulty_packet_in /= '0') then err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in <= '1'; else err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_not_faulty_packet_in <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in) begin if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and state_in /= Header_flit) then err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit <= '1'; else err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_state_in_Header_flit <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, write_fake_flit) begin if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '0' and write_fake_flit = '0') then err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit <= '1'; else err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_out_write_fake_flit <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in, state_out) begin if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_out = '1' and state_in /= state_out) then err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change <= '1'; else err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_fault_out_state_in_state_out_not_change <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, faulty_packet_in) begin if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '0' and faulty_packet_in /= '0') then err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in <= '1'; else err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_faulty_packet_in <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in, state_out) begin if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '1' and state_in /= state_out) then err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change <= '1'; else err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_fault_out_state_in_state_out_not_change <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in) begin if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '0' and state_in /= Idle) then err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle <= '1'; else err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_not_state_in_Idle <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, fake_credit) begin if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "100" and fault_out = '0' and fake_credit = '0') then err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit <= '1'; else err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Tail_not_fault_out_fake_credit <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, fake_credit) begin if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and ((flit_type /= "001" and flit_type /= "100") or fault_out = '1') and fake_credit = '0') then err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit <= '1'; else err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_invalid_fault_out_fake_credit <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, faulty_packet_in, faulty_packet_out) begin if (state_out = Packet_drop and faulty_packet_out = '1' and ( valid_in = '0' or (flit_type /= "001" and flit_type /= "100") or fault_out = '1' ) and faulty_packet_in /= faulty_packet_out) then err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '1'; else err_state_out_Packet_drop_faulty_packet_out_not_valid_in_flit_type_body_or_invalid_fault_out_faulty_packet_in_faulty_packet_out_not_change <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, state_in, state_out) begin if (state_out = Packet_drop and faulty_packet_out = '1' and ((flit_type /= "001" and flit_type /= "100") or fault_out = '1') and state_in /= state_out) then err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change <= '1'; else err_state_out_Packet_drop_faulty_packet_out_flit_type_invalid_fault_out_state_in_state_out_not_change <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, faulty_packet_in, faulty_packet_out) begin if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and faulty_packet_in /= faulty_packet_out) then err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal <= '1'; else err_state_out_Packet_drop_faulty_packet_out_not_valid_in_faulty_packet_in_faulty_packet_out_equal <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, state_in, state_out) begin if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and state_in /= state_out) then err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change <= '1'; else err_state_out_Packet_drop_faulty_packet_out_not_valid_in_state_in_state_out_not_change <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, write_fake_flit) begin if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and write_fake_flit = '1') then err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit <= '1'; else err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_write_fake_flit <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, fake_credit) begin if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '0' and fake_credit = '1') then err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit <= '1'; else err_state_out_Packet_drop_faulty_packet_out_not_valid_in_not_fake_credit <= '0'; end if; end process; -- faulty_packet_out = '0' -------------------------------------------------------------------------------------------------- process (state_out, faulty_packet_out, state_in, state_out) begin if (state_out = Packet_drop and faulty_packet_out = '0' and state_in /= state_out) then err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change <= '1'; else err_state_out_Packet_drop_not_faulty_packet_out_state_in_state_out_not_change <= '0'; end if; end process; process (state_out, faulty_packet_out, faulty_packet_in, faulty_packet_out) begin if (state_out = Packet_drop and faulty_packet_out = '0' and faulty_packet_in /= faulty_packet_out) then err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change <= '1'; else err_state_out_Packet_drop_not_faulty_packet_out_faulty_packet_in_faulty_packet_out_not_change <= '0'; end if; end process; process (state_out, fault_info_in) begin if (state_out = Packet_drop and fault_info_in = '1') then err_state_out_Packet_drop_not_fault_info_in <= '1'; else err_state_out_Packet_drop_not_fault_info_in <= '0'; end if; end process; process (state_out, faulty_packet_out, fake_credit) begin if (state_out = Packet_drop and faulty_packet_out = '0' and fake_credit = '1') then err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit <= '1'; else err_state_out_Packet_drop_not_faulty_packet_out_not_fake_credit <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, write_fake_flit) begin if (state_out = Packet_drop and faulty_packet_out = '1' and (valid_in = '0' or flit_type /= "001" or fault_out = '1') and write_fake_flit = '1') then err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit <= '1'; else err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_header_or_fault_out_not_write_fake_flit <= '0'; end if; end process; process (state_out, faulty_packet_out, write_fake_flit) begin if (state_out = Packet_drop and faulty_packet_out = '0' and write_fake_flit = '1') then err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit <= '1'; else err_state_out_Packet_drop_not_faulty_packet_out_not_write_fake_flit <= '0'; end if; end process; process (fault_info, fault_info_out) begin if (fault_info /= fault_info_out) then err_fault_info_fault_info_out_equal <= '1'; else err_fault_info_fault_info_out_equal <= '0'; end if; end process; process (state_out, valid_in, state_in, state_out) begin if (state_out = Packet_drop and valid_in = '0' and state_in /= state_out) then err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal <= '1'; else err_state_out_Packet_drop_not_valid_in_state_in_state_out_equal <= '0'; end if; end process; process (state_out, valid_in, fault_out, flit_type, state_in, state_out) begin if (state_out = Tail_flit and valid_in = '1' and fault_out = '0' and flit_type /= "001" and state_in /= state_out) then err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal <= '1'; else err_state_out_Tail_flit_valid_in_not_fault_out_flit_type_not_Header_state_in_state_out_equal <= '0'; end if; end process; -- Added after change of design ! process (state_out, faulty_packet_out, valid_in, flit_type, fault_info_in) begin if (state_out = Packet_drop and faulty_packet_out = '1' and valid_in = '1' and flit_type = "001" and fault_info_in /= '1') then err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in <= '1'; else err_state_out_Packet_drop_faulty_packet_out_valid_in_flit_type_Header_not_fault_info_in <= '0'; end if; end process; process (state_out, faulty_packet_out, valid_in, flit_type, fault_out, fault_info_in) begin if (state_out = Packet_drop and faulty_packet_out = '1' and (valid_in = '0' or flit_type /= "001") and fault_info_in /= '0') then err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in <= '1'; else err_state_out_Packet_drop_faulty_packet_out_not_valid_in_or_flit_type_not_Header_not_not_fault_info_in <= '0'; end if; end process; end behavior;
-------------------------------------------------------------------------------- -- This file is owned and controlled by Xilinx and must be used solely -- -- for design, simulation, implementation and creation of design files -- -- limited to Xilinx devices or technologies. Use with non-Xilinx -- -- devices or technologies is expressly prohibited and immediately -- -- terminates your license. -- -- -- -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- -- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- -- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- -- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- -- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- -- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- -- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- -- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- -- PARTICULAR PURPOSE. -- -- -- -- Xilinx products are not intended for use in life support appliances, -- -- devices, or systems. Use in such applications are expressly -- -- prohibited. -- -- -- -- (c) Copyright 1995-2012 Xilinx, Inc. -- -- All rights reserved. -- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- You must compile the wrapper file pulse_regen_v6.vhd when simulating -- the core, pulse_regen_v6. When compiling the wrapper file, be sure to -- reference the XilinxCoreLib VHDL simulation library. For detailed -- instructions, please refer to the "CORE Generator Help". -- The synthesis directives "translate_off/translate_on" specified -- below are supported by Xilinx, Mentor Graphics and Synplicity -- synthesis tools. Ensure they are correct for your synthesis tool(s). LIBRARY ieee; USE ieee.std_logic_1164.ALL; -- synthesis translate_off LIBRARY XilinxCoreLib; -- synthesis translate_on ENTITY pulse_regen_v6 IS PORT ( rst : IN STD_LOGIC; wr_clk : IN STD_LOGIC; rd_clk : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(0 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); full : OUT STD_LOGIC; empty : OUT STD_LOGIC; valid : OUT STD_LOGIC ); END pulse_regen_v6; ARCHITECTURE pulse_regen_v6_a OF pulse_regen_v6 IS -- synthesis translate_off COMPONENT wrapped_pulse_regen_v6 PORT ( rst : IN STD_LOGIC; wr_clk : IN STD_LOGIC; rd_clk : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(0 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); full : OUT STD_LOGIC; empty : OUT STD_LOGIC; valid : OUT STD_LOGIC ); END COMPONENT; -- Configuration specification FOR ALL : wrapped_pulse_regen_v6 USE ENTITY XilinxCoreLib.fifo_generator_v8_4(behavioral) GENERIC MAP ( c_add_ngc_constraint => 0, c_application_type_axis => 0, c_application_type_rach => 0, c_application_type_rdch => 0, c_application_type_wach => 0, c_application_type_wdch => 0, c_application_type_wrch => 0, c_axi_addr_width => 32, c_axi_aruser_width => 1, c_axi_awuser_width => 1, c_axi_buser_width => 1, c_axi_data_width => 64, c_axi_id_width => 4, c_axi_ruser_width => 1, c_axi_type => 0, c_axi_wuser_width => 1, c_axis_tdata_width => 64, c_axis_tdest_width => 4, c_axis_tid_width => 8, c_axis_tkeep_width => 4, c_axis_tstrb_width => 4, c_axis_tuser_width => 4, c_axis_type => 0, c_common_clock => 0, c_count_type => 0, c_data_count_width => 4, c_default_value => "BlankString", c_din_width => 1, c_din_width_axis => 1, c_din_width_rach => 32, c_din_width_rdch => 64, c_din_width_wach => 32, c_din_width_wdch => 64, c_din_width_wrch => 2, c_dout_rst_val => "0", c_dout_width => 1, c_enable_rlocs => 0, c_enable_rst_sync => 1, c_error_injection_type => 0, c_error_injection_type_axis => 0, c_error_injection_type_rach => 0, c_error_injection_type_rdch => 0, c_error_injection_type_wach => 0, c_error_injection_type_wdch => 0, c_error_injection_type_wrch => 0, c_family => "spartan6", c_full_flags_rst_val => 1, c_has_almost_empty => 0, c_has_almost_full => 0, c_has_axi_aruser => 0, c_has_axi_awuser => 0, c_has_axi_buser => 0, c_has_axi_rd_channel => 0, c_has_axi_ruser => 0, c_has_axi_wr_channel => 0, c_has_axi_wuser => 0, c_has_axis_tdata => 0, c_has_axis_tdest => 0, c_has_axis_tid => 0, c_has_axis_tkeep => 0, c_has_axis_tlast => 0, c_has_axis_tready => 1, c_has_axis_tstrb => 0, c_has_axis_tuser => 0, c_has_backup => 0, c_has_data_count => 0, c_has_data_counts_axis => 0, c_has_data_counts_rach => 0, c_has_data_counts_rdch => 0, c_has_data_counts_wach => 0, c_has_data_counts_wdch => 0, c_has_data_counts_wrch => 0, c_has_int_clk => 0, c_has_master_ce => 0, c_has_meminit_file => 0, c_has_overflow => 0, c_has_prog_flags_axis => 0, c_has_prog_flags_rach => 0, c_has_prog_flags_rdch => 0, c_has_prog_flags_wach => 0, c_has_prog_flags_wdch => 0, c_has_prog_flags_wrch => 0, c_has_rd_data_count => 0, c_has_rd_rst => 0, c_has_rst => 1, c_has_slave_ce => 0, c_has_srst => 0, c_has_underflow => 0, c_has_valid => 1, c_has_wr_ack => 0, c_has_wr_data_count => 0, c_has_wr_rst => 0, c_implementation_type => 2, c_implementation_type_axis => 1, c_implementation_type_rach => 1, c_implementation_type_rdch => 1, c_implementation_type_wach => 1, c_implementation_type_wdch => 1, c_implementation_type_wrch => 1, c_init_wr_pntr_val => 0, c_interface_type => 0, c_memory_type => 2, c_mif_file_name => "BlankString", c_msgon_val => 1, c_optimization_mode => 0, c_overflow_low => 0, c_preload_latency => 0, c_preload_regs => 1, c_prim_fifo_type => "512x36", c_prog_empty_thresh_assert_val => 4, c_prog_empty_thresh_assert_val_axis => 1022, c_prog_empty_thresh_assert_val_rach => 1022, c_prog_empty_thresh_assert_val_rdch => 1022, c_prog_empty_thresh_assert_val_wach => 1022, c_prog_empty_thresh_assert_val_wdch => 1022, c_prog_empty_thresh_assert_val_wrch => 1022, c_prog_empty_thresh_negate_val => 5, c_prog_empty_type => 0, c_prog_empty_type_axis => 5, c_prog_empty_type_rach => 5, c_prog_empty_type_rdch => 5, c_prog_empty_type_wach => 5, c_prog_empty_type_wdch => 5, c_prog_empty_type_wrch => 5, c_prog_full_thresh_assert_val => 15, c_prog_full_thresh_assert_val_axis => 1023, c_prog_full_thresh_assert_val_rach => 1023, c_prog_full_thresh_assert_val_rdch => 1023, c_prog_full_thresh_assert_val_wach => 1023, c_prog_full_thresh_assert_val_wdch => 1023, c_prog_full_thresh_assert_val_wrch => 1023, c_prog_full_thresh_negate_val => 14, c_prog_full_type => 0, c_prog_full_type_axis => 5, c_prog_full_type_rach => 5, c_prog_full_type_rdch => 5, c_prog_full_type_wach => 5, c_prog_full_type_wdch => 5, c_prog_full_type_wrch => 5, c_rach_type => 0, c_rd_data_count_width => 4, c_rd_depth => 16, c_rd_freq => 1, c_rd_pntr_width => 4, c_rdch_type => 0, c_reg_slice_mode_axis => 0, c_reg_slice_mode_rach => 0, c_reg_slice_mode_rdch => 0, c_reg_slice_mode_wach => 0, c_reg_slice_mode_wdch => 0, c_reg_slice_mode_wrch => 0, c_synchronizer_stage => 2, c_underflow_low => 0, c_use_common_overflow => 0, c_use_common_underflow => 0, c_use_default_settings => 0, c_use_dout_rst => 1, c_use_ecc => 0, c_use_ecc_axis => 0, c_use_ecc_rach => 0, c_use_ecc_rdch => 0, c_use_ecc_wach => 0, c_use_ecc_wdch => 0, c_use_ecc_wrch => 0, c_use_embedded_reg => 0, c_use_fifo16_flags => 0, c_use_fwft_data_count => 0, c_valid_low => 0, c_wach_type => 0, c_wdch_type => 0, c_wr_ack_low => 0, c_wr_data_count_width => 4, c_wr_depth => 16, c_wr_depth_axis => 1024, c_wr_depth_rach => 16, c_wr_depth_rdch => 1024, c_wr_depth_wach => 16, c_wr_depth_wdch => 1024, c_wr_depth_wrch => 16, c_wr_freq => 1, c_wr_pntr_width => 4, c_wr_pntr_width_axis => 10, c_wr_pntr_width_rach => 4, c_wr_pntr_width_rdch => 10, c_wr_pntr_width_wach => 4, c_wr_pntr_width_wdch => 10, c_wr_pntr_width_wrch => 4, c_wr_response_latency => 1, c_wrch_type => 0 ); -- synthesis translate_on BEGIN -- synthesis translate_off U0 : wrapped_pulse_regen_v6 PORT MAP ( rst => rst, wr_clk => wr_clk, rd_clk => rd_clk, din => din, wr_en => wr_en, rd_en => rd_en, dout => dout, full => full, empty => empty, valid => valid ); -- synthesis translate_on END pulse_regen_v6_a;
library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.all; library std; entity leds is generic ( CLK_PROC_FREQ : integer := 48000000; LEDCOUNT : integer := 1 ); port ( clk_proc : in std_logic; reset_n : in std_logic; --------------------- external ports -------------------- o : out std_logic_vector(LEDCOUNT-1 downto 0); --======================= Slaves ======================== ------------------------- bus_sl ------------------------ addr_rel_i : in std_logic_vector(1 downto 0); wr_i : in std_logic; rd_i : in std_logic; datawr_i : in std_logic_vector(31 downto 0); datard_o : out std_logic_vector(31 downto 0) ); end leds; architecture rtl of leds is constant ENABLE_REG_ADDR : natural := 0; signal led_reg : std_logic_vector(LEDCOUNT-1 downto 0); begin process (clk_proc, reset_n) begin if (reset_n='0') then led_reg <= (others => '0'); elsif (clk_proc'event and clk_proc='1') then if(wr_i='1') then case addr_rel_i is when std_logic_vector(to_unsigned(ENABLE_REG_ADDR, 2))=> led_reg <= datawr_i(LEDCOUNT-1 downto 0); when others=> end case; end if; end if; end process; o <= led_reg; end rtl;
------------------------------------------------------------------------------- --! @project Unrolled (2) hardware implementation of Asconv1286 --! @author Michael Fivez --! @license This project is released under the GNU Public License. --! The license and distribution terms for this file may be --! found in the file LICENSE in this distribution or at --! http://www.gnu.org/licenses/gpl-3.0.txt --! @note This is an hardware implementation made for my graduation thesis --! at the KULeuven, in the COSIC department (year 2015-2016) --! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions', --! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications) ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity Ascon_StateUpdate is port( Clk : in std_logic; -- Clock Reset : in std_logic; -- Reset (synchronous) -- ExtInputs Start : in std_logic; Mode : in std_logic_vector(3 downto 0); Size : in std_logic_vector(2 downto 0); -- only matters for last block decryption IV : in std_logic_vector(127 downto 0); Key : in std_logic_vector(127 downto 0); DataIn : in std_logic_vector(63 downto 0); Busy : out std_logic; DataOut : out std_logic_vector(127 downto 0)); end entity Ascon_StateUpdate; architecture structural of Ascon_StateUpdate is -- Control signals signal RoundNr : std_logic_vector(2 downto 0); -- biggest round is 12 signal sel1,sel2,sel3,sel4 : std_logic_vector(1 downto 0); signal sel0 : std_logic_vector(2 downto 0); signal selout : std_logic; signal Reg0En,Reg1En,Reg2En,Reg3En,Reg4En,RegOutEn : std_logic; signal ActivateGen : std_logic; signal GenSize : std_logic_vector(2 downto 0); begin control: entity work.Ascon_StateUpdate_control port map (Clk, Reset, RoundNr, sel1, sel2, sel3, sel4, sel0, selout, Reg0En, Reg1En, Reg2En, Reg3En, Reg4En, RegOutEn, ActivateGen, GenSize, Start, Mode, Size, Busy); datapath: entity work.Ascon_StateUpdate_datapath port map (Clk, Reset, RoundNr, sel1, sel2, sel3, sel4, sel0, selout, Reg0En, Reg1En, Reg2En, Reg3En, Reg4En, RegOutEn, ActivateGen, GenSize, IV, Key, DataIn, DataOut); end architecture structural;
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- DO NOT MODIFY THIS FILE. -- IP VLNV: xilinx.com:ip:floating_point:7.0 -- IP Revision: 8 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; LIBRARY floating_point_v7_0; USE floating_point_v7_0.floating_point_v7_0; ENTITY tri_intersect_ap_fadd_7_full_dsp_32 IS PORT ( aclk : IN STD_LOGIC; aclken : IN STD_LOGIC; s_axis_a_tvalid : IN STD_LOGIC; s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_b_tvalid : IN STD_LOGIC; s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); m_axis_result_tvalid : OUT STD_LOGIC; m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END tri_intersect_ap_fadd_7_full_dsp_32; ARCHITECTURE tri_intersect_ap_fadd_7_full_dsp_32_arch OF tri_intersect_ap_fadd_7_full_dsp_32 IS ATTRIBUTE DowngradeIPIdentifiedWarnings : string; ATTRIBUTE DowngradeIPIdentifiedWarnings OF tri_intersect_ap_fadd_7_full_dsp_32_arch: ARCHITECTURE IS "yes"; COMPONENT floating_point_v7_0 IS GENERIC ( C_XDEVICEFAMILY : STRING; C_HAS_ADD : INTEGER; C_HAS_SUBTRACT : INTEGER; C_HAS_MULTIPLY : INTEGER; C_HAS_DIVIDE : INTEGER; C_HAS_SQRT : INTEGER; C_HAS_COMPARE : INTEGER; C_HAS_FIX_TO_FLT : INTEGER; C_HAS_FLT_TO_FIX : INTEGER; C_HAS_FLT_TO_FLT : INTEGER; C_HAS_RECIP : INTEGER; C_HAS_RECIP_SQRT : INTEGER; C_HAS_ABSOLUTE : INTEGER; C_HAS_LOGARITHM : INTEGER; C_HAS_EXPONENTIAL : INTEGER; C_HAS_FMA : INTEGER; C_HAS_FMS : INTEGER; C_HAS_ACCUMULATOR_A : INTEGER; C_HAS_ACCUMULATOR_S : INTEGER; C_A_WIDTH : INTEGER; C_A_FRACTION_WIDTH : INTEGER; C_B_WIDTH : INTEGER; C_B_FRACTION_WIDTH : INTEGER; C_C_WIDTH : INTEGER; C_C_FRACTION_WIDTH : INTEGER; C_RESULT_WIDTH : INTEGER; C_RESULT_FRACTION_WIDTH : INTEGER; C_COMPARE_OPERATION : INTEGER; C_LATENCY : INTEGER; C_OPTIMIZATION : INTEGER; C_MULT_USAGE : INTEGER; C_BRAM_USAGE : INTEGER; C_RATE : INTEGER; C_ACCUM_INPUT_MSB : INTEGER; C_ACCUM_MSB : INTEGER; C_ACCUM_LSB : INTEGER; C_HAS_UNDERFLOW : INTEGER; C_HAS_OVERFLOW : INTEGER; C_HAS_INVALID_OP : INTEGER; C_HAS_DIVIDE_BY_ZERO : INTEGER; C_HAS_ACCUM_OVERFLOW : INTEGER; C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER; C_HAS_ACLKEN : INTEGER; C_HAS_ARESETN : INTEGER; C_THROTTLE_SCHEME : INTEGER; C_HAS_A_TUSER : INTEGER; C_HAS_A_TLAST : INTEGER; C_HAS_B : INTEGER; C_HAS_B_TUSER : INTEGER; C_HAS_B_TLAST : INTEGER; C_HAS_C : INTEGER; C_HAS_C_TUSER : INTEGER; C_HAS_C_TLAST : INTEGER; C_HAS_OPERATION : INTEGER; C_HAS_OPERATION_TUSER : INTEGER; C_HAS_OPERATION_TLAST : INTEGER; C_HAS_RESULT_TUSER : INTEGER; C_HAS_RESULT_TLAST : INTEGER; C_TLAST_RESOLUTION : INTEGER; C_A_TDATA_WIDTH : INTEGER; C_A_TUSER_WIDTH : INTEGER; C_B_TDATA_WIDTH : INTEGER; C_B_TUSER_WIDTH : INTEGER; C_C_TDATA_WIDTH : INTEGER; C_C_TUSER_WIDTH : INTEGER; C_OPERATION_TDATA_WIDTH : INTEGER; C_OPERATION_TUSER_WIDTH : INTEGER; C_RESULT_TDATA_WIDTH : INTEGER; C_RESULT_TUSER_WIDTH : INTEGER ); PORT ( aclk : IN STD_LOGIC; aclken : IN STD_LOGIC; aresetn : IN STD_LOGIC; s_axis_a_tvalid : IN STD_LOGIC; s_axis_a_tready : OUT STD_LOGIC; s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_a_tlast : IN STD_LOGIC; s_axis_b_tvalid : IN STD_LOGIC; s_axis_b_tready : OUT STD_LOGIC; s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_b_tlast : IN STD_LOGIC; s_axis_c_tvalid : IN STD_LOGIC; s_axis_c_tready : OUT STD_LOGIC; s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0); s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_c_tlast : IN STD_LOGIC; s_axis_operation_tvalid : IN STD_LOGIC; s_axis_operation_tready : OUT STD_LOGIC; s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0); s_axis_operation_tlast : IN STD_LOGIC; m_axis_result_tvalid : OUT STD_LOGIC; m_axis_result_tready : IN STD_LOGIC; m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0); m_axis_result_tlast : OUT STD_LOGIC ); END COMPONENT floating_point_v7_0; ATTRIBUTE X_INTERFACE_INFO : STRING; ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK"; ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID"; ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID"; ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA"; BEGIN U0 : floating_point_v7_0 GENERIC MAP ( C_XDEVICEFAMILY => "zynq", C_HAS_ADD => 1, C_HAS_SUBTRACT => 0, C_HAS_MULTIPLY => 0, C_HAS_DIVIDE => 0, C_HAS_SQRT => 0, C_HAS_COMPARE => 0, C_HAS_FIX_TO_FLT => 0, C_HAS_FLT_TO_FIX => 0, C_HAS_FLT_TO_FLT => 0, C_HAS_RECIP => 0, C_HAS_RECIP_SQRT => 0, C_HAS_ABSOLUTE => 0, C_HAS_LOGARITHM => 0, C_HAS_EXPONENTIAL => 0, C_HAS_FMA => 0, C_HAS_FMS => 0, C_HAS_ACCUMULATOR_A => 0, C_HAS_ACCUMULATOR_S => 0, C_A_WIDTH => 32, C_A_FRACTION_WIDTH => 24, C_B_WIDTH => 32, C_B_FRACTION_WIDTH => 24, C_C_WIDTH => 32, C_C_FRACTION_WIDTH => 24, C_RESULT_WIDTH => 32, C_RESULT_FRACTION_WIDTH => 24, C_COMPARE_OPERATION => 8, C_LATENCY => 7, C_OPTIMIZATION => 1, C_MULT_USAGE => 2, C_BRAM_USAGE => 0, C_RATE => 1, C_ACCUM_INPUT_MSB => 32, C_ACCUM_MSB => 32, C_ACCUM_LSB => -31, C_HAS_UNDERFLOW => 0, C_HAS_OVERFLOW => 0, C_HAS_INVALID_OP => 0, C_HAS_DIVIDE_BY_ZERO => 0, C_HAS_ACCUM_OVERFLOW => 0, C_HAS_ACCUM_INPUT_OVERFLOW => 0, C_HAS_ACLKEN => 1, C_HAS_ARESETN => 0, C_THROTTLE_SCHEME => 3, C_HAS_A_TUSER => 0, C_HAS_A_TLAST => 0, C_HAS_B => 1, C_HAS_B_TUSER => 0, C_HAS_B_TLAST => 0, C_HAS_C => 0, C_HAS_C_TUSER => 0, C_HAS_C_TLAST => 0, C_HAS_OPERATION => 0, C_HAS_OPERATION_TUSER => 0, C_HAS_OPERATION_TLAST => 0, C_HAS_RESULT_TUSER => 0, C_HAS_RESULT_TLAST => 0, C_TLAST_RESOLUTION => 0, C_A_TDATA_WIDTH => 32, C_A_TUSER_WIDTH => 1, C_B_TDATA_WIDTH => 32, C_B_TUSER_WIDTH => 1, C_C_TDATA_WIDTH => 32, C_C_TUSER_WIDTH => 1, C_OPERATION_TDATA_WIDTH => 8, C_OPERATION_TUSER_WIDTH => 1, C_RESULT_TDATA_WIDTH => 32, C_RESULT_TUSER_WIDTH => 1 ) PORT MAP ( aclk => aclk, aclken => aclken, aresetn => '1', s_axis_a_tvalid => s_axis_a_tvalid, s_axis_a_tdata => s_axis_a_tdata, s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_a_tlast => '0', s_axis_b_tvalid => s_axis_b_tvalid, s_axis_b_tdata => s_axis_b_tdata, s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_b_tlast => '0', s_axis_c_tvalid => '0', s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)), s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_c_tlast => '0', s_axis_operation_tvalid => '0', s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)), s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)), s_axis_operation_tlast => '0', m_axis_result_tvalid => m_axis_result_tvalid, m_axis_result_tready => '0', m_axis_result_tdata => m_axis_result_tdata ); END tri_intersect_ap_fadd_7_full_dsp_32_arch;
library IEEE; use IEEE.Std_Logic_1164.all; entity C2 is port (A: in std_logic_vector(3 downto 0); B: in std_logic_vector(3 downto 0); F: out std_logic_vector(3 downto 0) ); end C2; architecture circuito of C2 is begin F <= A or B; end circuito;
library IEEE; use IEEE.Std_Logic_1164.all; entity C2 is port (A: in std_logic_vector(3 downto 0); B: in std_logic_vector(3 downto 0); F: out std_logic_vector(3 downto 0) ); end C2; architecture circuito of C2 is begin F <= A or B; end circuito;