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--
-- This file is part of IP_register
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity delay_register is
generic (
width : positive ;
delay : natural := 1); -- delay
port (
clk : in std_logic; -- clock
rst : in std_logic; --rst
input : in std_logic_vector(width - 1 downto 0); -- input
output : out std_logic_vector(width - 1 downto 0)); -- output
end delay_register;
architecture behavourial of delay_register is
-- signal delayed_output : std_logic_vector(delay downto 0) := (others => '0'); -- delayed output
type buffer_t is array (0 to delay) of std_logic_vector(width - 1 downto 0);
signal delayed_output : buffer_t := (others => (others => '0')); -- delayed output
begin -- behavourial
delayed_output(0) <= input;
delay_non_zero : if delay > 0 generate
delay_loop: for i in 0 to delay -1 generate
inst: entity work.my_register
generic map (
size => width
)
port map (
clk => clk,
rst => rst,
input => delayed_output(i),
output => delayed_output(i+1));
end generate delay_loop;
output <= delayed_output(delay);
end generate delay_non_zero;
delay_zero: if delay = 0 generate
output <= input;
end generate delay_zero;
end behavourial;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := spartan6;
constant CFG_MEMTECH : integer := spartan6;
constant CFG_PADTECH : integer := spartan6;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := spartan6;
constant CFG_CLKMUL : integer := (2);
constant CFG_CLKDIV : integer := (4);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 1;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 4 + 64*0;
constant CFG_ATBSZ : integer := 4;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020765#;
constant CFG_ETH_ENL : integer := 16#003456#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 0;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDR2SP : integer := 1;
constant CFG_DDR2SP_INIT : integer := 1;
constant CFG_DDR2SP_FREQ : integer := 100;
constant CFG_DDR2SP_TRFC : integer := (130);
constant CFG_DDR2SP_DATAWIDTH : integer := (16);
constant CFG_DDR2SP_FTEN : integer := 0;
constant CFG_DDR2SP_FTWIDTH : integer := 0;
constant CFG_DDR2SP_COL : integer := (10);
constant CFG_DDR2SP_SIZE : integer := (128);
constant CFG_DDR2SP_DELAY0 : integer := (0);
constant CFG_DDR2SP_DELAY1 : integer := (0);
constant CFG_DDR2SP_DELAY2 : integer := (0);
constant CFG_DDR2SP_DELAY3 : integer := (0);
constant CFG_DDR2SP_DELAY4 : integer := (0);
constant CFG_DDR2SP_DELAY5 : integer := (0);
constant CFG_DDR2SP_DELAY6 : integer := (0);
constant CFG_DDR2SP_DELAY7 : integer := (0);
constant CFG_DDR2SP_NOSYNC : integer := 1;
-- AHB status register
constant CFG_AHBSTAT : integer := 1;
constant CFG_AHBSTATN : integer := (1);
-- AHB ROM
constant CFG_AHBROMEN : integer := 1;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#100#;
constant CFG_ROMMASK : integer := 16#E00# + 16#100#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 1;
constant CFG_AHBRSZ : integer := 16;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (32);
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 1;
constant CFG_VGA_ENABLE : integer := 1;
constant CFG_SVGA_ENABLE : integer := 0;
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 1;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#03#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 0;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := (1);
constant CFG_SPIMCTRL_ASCALER : integer := (8);
constant CFG_SPIMCTRL_PWRUPCNT : integer := (30000);
constant CFG_SPIMCTRL_OFFSET : integer := 16#0#;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for struct of pads_eastnord
--
-- Generated
-- by: wig
-- on: Mon Mar 5 15:01:50 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl ../padio2.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: pads_eastnord-struct-a.vhd,v 1.6 2007/03/05 15:29:26 wig Exp $
-- $Date: 2007/03/05 15:29:26 $
-- $Log: pads_eastnord-struct-a.vhd,v $
-- Revision 1.6 2007/03/05 15:29:26 wig
-- Updated testcase.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.104 2007/03/03 17:24:06 wig Exp
--
-- Generator: mix_0.pl Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture struct of pads_eastnord
--
architecture struct of pads_eastnord is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component ioc
-- No Generated Generics
port (
-- Generated Port for Entity ioc
bypass : in std_ulogic_vector(1 downto 0);
clk : in std_ulogic_vector(1 downto 0);
clockdr_i : in std_ulogic;
di : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
do : in std_ulogic_vector(1 downto 0);
en : in std_ulogic_vector(1 downto 0);
enq : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
iddq : in std_ulogic_vector(1 downto 0);
mode_1_i : in std_ulogic;
mode_2_i : in std_ulogic;
mode_3_i : in std_ulogic;
mux_sel_p : in std_ulogic_vector(1 downto 0);
oe : in std_ulogic_vector(1 downto 0);
pad : inout std_ulogic;
pd : in std_ulogic_vector(1 downto 0);
res_n : in std_ulogic;
scan_en_i : in std_ulogic;
scan_i : in std_ulogic;
scan_o : out std_ulogic;
serial_input_i : in std_ulogic;
serial_output_o : out std_ulogic;
shiftdr_i : in std_ulogic;
tck_i : in std_ulogic;
tenq : in std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
updatedr_i : in std_ulogic
-- End of Generated Port for Entity ioc
);
end component;
-- ---------
--
-- Generated Signal List
--
signal mix_logic1_0 : std_ulogic;
signal mix_logic1_1 : std_ulogic;
signal mix_logic1_10 : std_ulogic;
signal mix_logic1_11 : std_ulogic;
signal mix_logic1_12 : std_ulogic;
signal mix_logic1_13 : std_ulogic;
signal mix_logic1_14 : std_ulogic;
signal mix_logic1_15 : std_ulogic;
signal mix_logic1_16 : std_ulogic;
signal mix_logic1_17 : std_ulogic;
signal mix_logic1_2 : std_ulogic;
signal mix_logic1_3 : std_ulogic;
signal mix_logic1_4 : std_ulogic;
signal mix_logic1_48 : std_ulogic;
signal mix_logic1_49 : std_ulogic;
signal mix_logic1_5 : std_ulogic;
signal mix_logic1_50 : std_ulogic;
signal mix_logic1_51 : std_ulogic;
signal mix_logic1_52 : std_ulogic;
signal mix_logic1_53 : std_ulogic;
signal mix_logic1_54 : std_ulogic;
signal mix_logic1_55 : std_ulogic;
signal mix_logic1_56 : std_ulogic;
signal mix_logic1_57 : std_ulogic;
signal mix_logic1_58 : std_ulogic;
signal mix_logic1_59 : std_ulogic;
signal mix_logic1_6 : std_ulogic;
signal mix_logic1_60 : std_ulogic;
signal mix_logic1_61 : std_ulogic;
signal mix_logic1_62 : std_ulogic;
signal mix_logic1_63 : std_ulogic;
signal mix_logic1_64 : std_ulogic;
signal mix_logic1_65 : std_ulogic;
signal mix_logic1_7 : std_ulogic;
signal mix_logic1_8 : std_ulogic;
signal mix_logic1_9 : std_ulogic;
signal mix_logic0_0 : std_ulogic;
signal mix_logic0_1 : std_ulogic;
signal mix_logic0_16 : std_ulogic;
signal mix_logic0_17 : std_ulogic;
signal mix_logic0_18 : std_ulogic;
signal mix_logic0_19 : std_ulogic;
signal mix_logic0_2 : std_ulogic;
signal mix_logic0_20 : std_ulogic;
signal mix_logic0_21 : std_ulogic;
signal mix_logic0_3 : std_ulogic;
signal mix_logic0_34 : std_ulogic;
signal mix_logic0_37 : std_ulogic;
signal mix_logic0_39 : std_ulogic;
signal mix_logic0_4 : std_ulogic;
signal mix_logic0_41 : std_ulogic;
signal mix_logic0_43 : std_ulogic;
signal mix_logic0_45 : std_ulogic;
signal mix_logic0_5 : std_ulogic;
signal mix_logic0_50 : std_ulogic;
signal mix_logic0_53 : std_ulogic;
signal mix_logic0_55 : std_ulogic;
signal mix_logic0_56 : std_ulogic;
signal mix_logic0_61 : std_ulogic;
signal mix_logic0_63 : std_ulogic;
signal clkf81 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal clockdr_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal dbo_o : std_ulogic_vector(15 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal default : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal mode_1_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal mode_2_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal mode_3_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pmux_sel_por : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal res_f81_n : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal rgbout_byp_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal rgbout_iddq_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal rgbout_sio_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_in_db2o_10 : std_ulogic;
signal s_in_db2o_11 : std_ulogic;
signal s_in_db2o_12 : std_ulogic;
signal s_in_db2o_13 : std_ulogic;
signal s_in_db2o_14 : std_ulogic;
signal s_in_db2o_15 : std_ulogic;
signal s_in_dbo_10 : std_ulogic;
signal s_in_dbo_11 : std_ulogic;
signal s_in_dbo_12 : std_ulogic;
signal s_in_dbo_13 : std_ulogic;
signal s_in_dbo_14 : std_ulogic;
signal s_in_dbo_15 : std_ulogic;
-- __I_OUT_OPEN signal s_out_db2o_10 : std_ulogic;
-- __I_OUT_OPEN signal s_out_db2o_11 : std_ulogic;
-- __I_OUT_OPEN signal s_out_db2o_12 : std_ulogic;
-- __I_OUT_OPEN signal s_out_db2o_13 : std_ulogic;
-- __I_OUT_OPEN signal s_out_db2o_14 : std_ulogic;
-- __I_OUT_OPEN signal s_out_db2o_15 : std_ulogic;
-- __I_OUT_OPEN signal s_out_dbo_10 : std_ulogic;
-- __I_OUT_OPEN signal s_out_dbo_11 : std_ulogic;
-- __I_OUT_OPEN signal s_out_dbo_12 : std_ulogic;
-- __I_OUT_OPEN signal s_out_dbo_13 : std_ulogic;
-- __I_OUT_OPEN signal s_out_dbo_14 : std_ulogic;
-- __I_OUT_OPEN signal s_out_dbo_15 : std_ulogic;
signal scan_en_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal shiftdr_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal tck_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal updatedr_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal varclk_i : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
mix_logic1_0 <= '1';
mix_logic1_1 <= '1';
mix_logic1_10 <= '1';
mix_logic1_11 <= '1';
mix_logic1_12 <= '1';
mix_logic1_13 <= '1';
mix_logic1_14 <= '1';
mix_logic1_15 <= '1';
mix_logic1_16 <= '1';
mix_logic1_17 <= '1';
mix_logic1_2 <= '1';
mix_logic1_3 <= '1';
mix_logic1_4 <= '1';
mix_logic1_48 <= '1';
mix_logic1_49 <= '1';
mix_logic1_5 <= '1';
mix_logic1_50 <= '1';
mix_logic1_51 <= '1';
mix_logic1_52 <= '1';
mix_logic1_53 <= '1';
mix_logic1_54 <= '1';
mix_logic1_55 <= '1';
mix_logic1_56 <= '1';
mix_logic1_57 <= '1';
mix_logic1_58 <= '1';
mix_logic1_59 <= '1';
mix_logic1_6 <= '1';
mix_logic1_60 <= '1';
mix_logic1_61 <= '1';
mix_logic1_62 <= '1';
mix_logic1_63 <= '1';
mix_logic1_64 <= '1';
mix_logic1_65 <= '1';
mix_logic1_7 <= '1';
mix_logic1_8 <= '1';
mix_logic1_9 <= '1';
mix_logic0_0 <= '0';
mix_logic0_1 <= '0';
mix_logic0_16 <= '0';
mix_logic0_17 <= '0';
mix_logic0_18 <= '0';
mix_logic0_19 <= '0';
mix_logic0_2 <= '0';
mix_logic0_20 <= '0';
mix_logic0_21 <= '0';
mix_logic0_3 <= '0';
mix_logic0_34 <= '0';
mix_logic0_37 <= '0';
mix_logic0_39 <= '0';
mix_logic0_4 <= '0';
mix_logic0_41 <= '0';
mix_logic0_43 <= '0';
mix_logic0_45 <= '0';
mix_logic0_5 <= '0';
mix_logic0_50 <= '0';
mix_logic0_53 <= '0';
mix_logic0_55 <= '0';
mix_logic0_56 <= '0';
mix_logic0_61 <= '0';
mix_logic0_63 <= '0';
clkf81 <= clkf81_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
clockdr_i <= clockdr_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
dbo_o_15_10_go(5 downto 0) <= dbo_o(15 downto 10); -- __I_O_SLICE_PORT
default <= default_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
mode_1_i <= mode_1_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
mode_2_i <= mode_2_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
mode_3_i <= mode_3_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
pmux_sel_por <= pmux_sel_por_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
res_f81_n <= res_f81_n_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
rgbout_byp_i <= rgbout_byp_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
rgbout_iddq_i <= rgbout_iddq_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
rgbout_sio_i <= rgbout_sio_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
scan_en_i <= scan_en_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
shiftdr_i <= shiftdr_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
tck_i <= tck_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
updatedr_i <= updatedr_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
varclk_i <= varclk_i_gi; -- __I_I_SLICE_PORT -- __I_SINGLE_BIT (0)
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for ioc_db2o_10
ioc_db2o_10: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_50, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => db2o_o(10), -- padout (X2)
do(0) => db2o_i(10), -- padin (X2)
do(1) => mix_logic1_48, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_16, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_49, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => db2o_10, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_34,
scan_o => open,
serial_input_i => s_in_db2o_10,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_db2o_10
-- Generated Instance Port Map for ioc_db2o_11
ioc_db2o_11: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_53, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => db2o_o(11), -- padout (X2)
do(0) => db2o_i(11), -- padin (X2)
do(1) => mix_logic1_51, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_17, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_52, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => db2o_11, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_39,
scan_o => open,
serial_input_i => s_in_db2o_11,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_db2o_11
-- Generated Instance Port Map for ioc_db2o_12
ioc_db2o_12: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_56, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => db2o_o(12), -- padout (X2)
do(0) => db2o_i(12), -- padin (X2)
do(1) => mix_logic1_54, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_18, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_55, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => db2o_12, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_55,
scan_o => open,
serial_input_i => s_in_db2o_12,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_db2o_12
-- Generated Instance Port Map for ioc_db2o_13
ioc_db2o_13: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_59, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => db2o_o(13), -- padout (X2)
do(0) => db2o_i(13), -- padin (X2)
do(1) => mix_logic1_57, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_19, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_58, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => db2o_13, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_37,
scan_o => open,
serial_input_i => s_in_db2o_13,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_db2o_13
-- Generated Instance Port Map for ioc_db2o_14
ioc_db2o_14: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_62, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => db2o_o(14), -- padout (X2)
do(0) => db2o_i(14), -- padin (X2)
do(1) => mix_logic1_60, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_20, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_61, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => db2o_14, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_45,
scan_o => open,
serial_input_i => s_in_db2o_14,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_db2o_14
-- Generated Instance Port Map for ioc_db2o_15
ioc_db2o_15: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_65, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => db2o_o(15), -- padout (X2)
do(0) => db2o_i(15), -- padin (X2)
do(1) => mix_logic1_63, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_21, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_64, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => db2o_15, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_41,
scan_o => open,
serial_input_i => s_in_db2o_15,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_db2o_15
-- Generated Instance Port Map for ioc_dbo_10
ioc_dbo_10: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_2, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => dbo_o(10), -- padout
do(0) => dbo_i(10), -- padin (X2)
do(1) => mix_logic1_0, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_0, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_1, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => dbo_10, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_50,
scan_o => open,
serial_input_i => s_in_dbo_10,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_dbo_10
-- Generated Instance Port Map for ioc_dbo_11
ioc_dbo_11: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_5, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => dbo_o(11), -- padout
do(0) => dbo_i(11), -- padin (X2)
do(1) => mix_logic1_3, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_1, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_4, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => dbo_11, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_61,
scan_o => open,
serial_input_i => s_in_dbo_11,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_dbo_11
-- Generated Instance Port Map for ioc_dbo_12
ioc_dbo_12: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_8, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => dbo_o(12), -- padout
do(0) => dbo_i(12), -- padin (X2)
do(1) => mix_logic1_6, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_2, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_7, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => dbo_12, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_53,
scan_o => open,
serial_input_i => s_in_dbo_12,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_dbo_12
-- Generated Instance Port Map for ioc_dbo_13
ioc_dbo_13: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_11, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => dbo_o(13), -- padout
do(0) => dbo_i(13), -- padin (X2)
do(1) => mix_logic1_9, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_3, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_10, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => dbo_13, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_43,
scan_o => open,
serial_input_i => s_in_dbo_13,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_dbo_13
-- Generated Instance Port Map for ioc_dbo_14
ioc_dbo_14: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_14, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => dbo_o(14), -- padout
do(0) => dbo_i(14), -- padin (X2)
do(1) => mix_logic1_12, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_4, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_13, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => dbo_14, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_56,
scan_o => open,
serial_input_i => s_in_dbo_14,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_dbo_14
-- Generated Instance Port Map for ioc_dbo_15
ioc_dbo_15: ioc
port map (
bypass(0) => rgbout_byp_i, -- __I_BIT_TO_BUSPORT
bypass(1) => mix_logic1_17, -- __I_BIT_TO_BUSPORT
clk(0) => varclk_i, -- __I_BIT_TO_BUSPORT
clk(1) => clkf81, -- __I_BIT_TO_BUSPORT
clockdr_i => clockdr_i,
di => dbo_o(15), -- padout
do(0) => dbo_i(15), -- padin (X2)
do(1) => mix_logic1_15, -- __I_BIT_TO_BUSPORT
en(0) => rgbout_sio_i, -- __I_BIT_TO_BUSPORT
en(1) => mix_logic0_5, -- __I_BIT_TO_BUSPORT
iddq(0) => rgbout_iddq_i, -- __I_BIT_TO_BUSPORT
iddq(1) => mix_logic1_16, -- __I_BIT_TO_BUSPORT
mode_1_i => mode_1_i,
mode_2_i => mode_2_i,
mode_3_i => mode_3_i,
mux_sel_p(0) => default, -- __I_BIT_TO_BUSPORT
mux_sel_p(1) => pmux_sel_por, -- __I_BIT_TO_BUSPORT
pad => dbo_15, -- Flat Panel
res_n => res_f81_n,
scan_en_i => scan_en_i,
scan_i => mix_logic0_63,
scan_o => open,
serial_input_i => s_in_dbo_15,
serial_output_o => open, -- __I_OUT_OPEN
shiftdr_i => shiftdr_i,
tck_i => tck_i,
updatedr_i => updatedr_i
);
-- End of Generated Instance Port Map for ioc_dbo_15
end struct;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
entity tb_dff08 is
end tb_dff08;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_dff08 is
signal clk : std_logic;
signal din : std_logic;
signal dout : std_logic;
begin
dut: entity work.dff08
port map (
q => dout,
d => din,
clk => clk);
process
procedure pulse is
begin
clk <= '1';
wait for 1 ns;
clk <= '0';
wait for 1 ns;
end pulse;
begin
din <= '0';
pulse;
assert dout = '0' severity failure;
din <= '1';
clk <= '1';
wait for 1 ns;
assert dout = '0' severity failure;
clk <= '0';
wait for 1 ns;
assert dout = '1' severity failure;
pulse;
assert dout = '1' severity failure;
din <= '0';
pulse;
assert dout = '0' severity failure;
wait;
end process;
end behav;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_08_fg_08_07.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- not in book
entity cpu is
end entity cpu;
-- end not in book
architecture behavioral of cpu is
begin
interpreter : process is
variable instr_reg : work.cpu_types.word;
variable instr_opcode : work.cpu_types.opcode;
begin
-- . . . -- initialize
loop
-- . . . -- fetch instruction
instr_opcode := work.cpu_types.extract_opcode ( instr_reg );
case instr_opcode is
when work.cpu_types.op_nop => null;
when work.cpu_types.op_breq => -- . . .
-- . . .
-- not in book
when others => null;
-- end not in book
end case;
end loop;
end process interpreter;
end architecture behavioral;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_08_fg_08_07.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- not in book
entity cpu is
end entity cpu;
-- end not in book
architecture behavioral of cpu is
begin
interpreter : process is
variable instr_reg : work.cpu_types.word;
variable instr_opcode : work.cpu_types.opcode;
begin
-- . . . -- initialize
loop
-- . . . -- fetch instruction
instr_opcode := work.cpu_types.extract_opcode ( instr_reg );
case instr_opcode is
when work.cpu_types.op_nop => null;
when work.cpu_types.op_breq => -- . . .
-- . . .
-- not in book
when others => null;
-- end not in book
end case;
end loop;
end process interpreter;
end architecture behavioral;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_08_fg_08_07.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
-- not in book
entity cpu is
end entity cpu;
-- end not in book
architecture behavioral of cpu is
begin
interpreter : process is
variable instr_reg : work.cpu_types.word;
variable instr_opcode : work.cpu_types.opcode;
begin
-- . . . -- initialize
loop
-- . . . -- fetch instruction
instr_opcode := work.cpu_types.extract_opcode ( instr_reg );
case instr_opcode is
when work.cpu_types.op_nop => null;
when work.cpu_types.op_breq => -- . . .
-- . . .
-- not in book
when others => null;
-- end not in book
end case;
end loop;
end process interpreter;
end architecture behavioral;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: blk_mem_gen_v7_3_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan3e
-- C_XDEVICEFAMILY : spartan3e
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 0
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : blk_mem_gen_v7_3.mif
-- C_USE_DEFAULT_DATA : 1
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 16
-- C_READ_WIDTH_A : 16
-- C_WRITE_DEPTH_A : 32
-- C_READ_DEPTH_A : 32
-- C_ADDRA_WIDTH : 5
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 16
-- C_READ_WIDTH_B : 16
-- C_WRITE_DEPTH_B : 32
-- C_READ_DEPTH_B : 32
-- C_ADDRB_WIDTH : 5
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY blk_mem_gen_v7_3_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END blk_mem_gen_v7_3_prod;
ARCHITECTURE xilinx OF blk_mem_gen_v7_3_prod IS
COMPONENT blk_mem_gen_v7_3_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : blk_mem_gen_v7_3_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: blk_mem_gen_v7_3_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan3e
-- C_XDEVICEFAMILY : spartan3e
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 0
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : blk_mem_gen_v7_3.mif
-- C_USE_DEFAULT_DATA : 1
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 16
-- C_READ_WIDTH_A : 16
-- C_WRITE_DEPTH_A : 32
-- C_READ_DEPTH_A : 32
-- C_ADDRA_WIDTH : 5
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 16
-- C_READ_WIDTH_B : 16
-- C_WRITE_DEPTH_B : 32
-- C_READ_DEPTH_B : 32
-- C_ADDRB_WIDTH : 5
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY blk_mem_gen_v7_3_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END blk_mem_gen_v7_3_prod;
ARCHITECTURE xilinx OF blk_mem_gen_v7_3_prod IS
COMPONENT blk_mem_gen_v7_3_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : blk_mem_gen_v7_3_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: blk_mem_gen_v7_3_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan3e
-- C_XDEVICEFAMILY : spartan3e
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 0
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : blk_mem_gen_v7_3.mif
-- C_USE_DEFAULT_DATA : 1
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 16
-- C_READ_WIDTH_A : 16
-- C_WRITE_DEPTH_A : 32
-- C_READ_DEPTH_A : 32
-- C_ADDRA_WIDTH : 5
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 16
-- C_READ_WIDTH_B : 16
-- C_WRITE_DEPTH_B : 32
-- C_READ_DEPTH_B : 32
-- C_ADDRB_WIDTH : 5
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY blk_mem_gen_v7_3_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END blk_mem_gen_v7_3_prod;
ARCHITECTURE xilinx OF blk_mem_gen_v7_3_prod IS
COMPONENT blk_mem_gen_v7_3_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : blk_mem_gen_v7_3_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: blk_mem_gen_v7_3_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan3e
-- C_XDEVICEFAMILY : spartan3e
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 0
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : blk_mem_gen_v7_3.mif
-- C_USE_DEFAULT_DATA : 1
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 16
-- C_READ_WIDTH_A : 16
-- C_WRITE_DEPTH_A : 32
-- C_READ_DEPTH_A : 32
-- C_ADDRA_WIDTH : 5
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 16
-- C_READ_WIDTH_B : 16
-- C_WRITE_DEPTH_B : 32
-- C_READ_DEPTH_B : 32
-- C_ADDRB_WIDTH : 5
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY blk_mem_gen_v7_3_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END blk_mem_gen_v7_3_prod;
ARCHITECTURE xilinx OF blk_mem_gen_v7_3_prod IS
COMPONENT blk_mem_gen_v7_3_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : blk_mem_gen_v7_3_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: blk_mem_gen_v7_3_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan3e
-- C_XDEVICEFAMILY : spartan3e
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 0
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 1
-- C_INIT_FILE_NAME : blk_mem_gen_v7_3.mif
-- C_USE_DEFAULT_DATA : 1
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 16
-- C_READ_WIDTH_A : 16
-- C_WRITE_DEPTH_A : 32
-- C_READ_DEPTH_A : 32
-- C_ADDRA_WIDTH : 5
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 16
-- C_READ_WIDTH_B : 16
-- C_WRITE_DEPTH_B : 32
-- C_READ_DEPTH_B : 32
-- C_ADDRB_WIDTH : 5
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY blk_mem_gen_v7_3_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END blk_mem_gen_v7_3_prod;
ARCHITECTURE xilinx OF blk_mem_gen_v7_3_prod IS
COMPONENT blk_mem_gen_v7_3_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : blk_mem_gen_v7_3_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
|
architecture rtl of fifo is
signal sig8 : record_type_3(
element1(7 downto 0),
element2(4 downto 0)(7 downto 0)
(
elementA(7 downto 0),
elementB(3 downto 0)
),
element3(3 downto 0)(
elementC(4 downto 1),
elementD(1 downto 0)),
element5(
elementE(3 downto 0)(6 downto 0),
elementF(7 downto 0)
),
element6(4 downto 0),
element7(7 downto 0)
);
begin
end architecture rtl;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity adc is
port ( quantity gain : in voltage;
terminal a : electrical;
signal clk : in bit;
signal d_out : out bit );
end entity adc;
architecture ideal of adc is
constant ref : real := 5.0;
quantity v_in across a;
quantity v_amplified : voltage;
begin
v_amplified == v_in * gain;
adc_behavior: process is
variable stored_d : bit;
begin
if clk = '1' then
if v_amplified > ref / 2.0 then
stored_d := '1';
else
stored_d := '0';
end if;
end if;
d_out <= stored_d after 5 ns;
wait on clk;
end process adc_behavior;
end architecture ideal;
architecture struct of adc is
terminal a_amplified, ref, half_ref: electrical;
quantity v_ref across i_ref through ref;
signal d : bit;
begin
res1 : entity work.resistor(ideal)
port map ( ref, half_ref);
res2 : entity work.resistor(ideal)
port map ( half_ref, electrical_ref );
amp : entity work.vc_amp(ideal)
port map ( gain, a, a_amplified );
comp : entity work.comparator(ideal)
port map ( a_amplified, half_ref, d);
ff : entity work.d_ff(basic)
port map ( d, clk, d_out );
v_ref == 5.0;
end architecture struct;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity adc is
port ( quantity gain : in voltage;
terminal a : electrical;
signal clk : in bit;
signal d_out : out bit );
end entity adc;
architecture ideal of adc is
constant ref : real := 5.0;
quantity v_in across a;
quantity v_amplified : voltage;
begin
v_amplified == v_in * gain;
adc_behavior: process is
variable stored_d : bit;
begin
if clk = '1' then
if v_amplified > ref / 2.0 then
stored_d := '1';
else
stored_d := '0';
end if;
end if;
d_out <= stored_d after 5 ns;
wait on clk;
end process adc_behavior;
end architecture ideal;
architecture struct of adc is
terminal a_amplified, ref, half_ref: electrical;
quantity v_ref across i_ref through ref;
signal d : bit;
begin
res1 : entity work.resistor(ideal)
port map ( ref, half_ref);
res2 : entity work.resistor(ideal)
port map ( half_ref, electrical_ref );
amp : entity work.vc_amp(ideal)
port map ( gain, a, a_amplified );
comp : entity work.comparator(ideal)
port map ( a_amplified, half_ref, d);
ff : entity work.d_ff(basic)
port map ( d, clk, d_out );
v_ref == 5.0;
end architecture struct;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity adc is
port ( quantity gain : in voltage;
terminal a : electrical;
signal clk : in bit;
signal d_out : out bit );
end entity adc;
architecture ideal of adc is
constant ref : real := 5.0;
quantity v_in across a;
quantity v_amplified : voltage;
begin
v_amplified == v_in * gain;
adc_behavior: process is
variable stored_d : bit;
begin
if clk = '1' then
if v_amplified > ref / 2.0 then
stored_d := '1';
else
stored_d := '0';
end if;
end if;
d_out <= stored_d after 5 ns;
wait on clk;
end process adc_behavior;
end architecture ideal;
architecture struct of adc is
terminal a_amplified, ref, half_ref: electrical;
quantity v_ref across i_ref through ref;
signal d : bit;
begin
res1 : entity work.resistor(ideal)
port map ( ref, half_ref);
res2 : entity work.resistor(ideal)
port map ( half_ref, electrical_ref );
amp : entity work.vc_amp(ideal)
port map ( gain, a, a_amplified );
comp : entity work.comparator(ideal)
port map ( a_amplified, half_ref, d);
ff : entity work.d_ff(basic)
port map ( d, clk, d_out );
v_ref == 5.0;
end architecture struct;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:uint_to_ieee754_fp:1.0
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY affine_block_uint_to_ieee754_fp_0_1 IS
PORT (
x : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END affine_block_uint_to_ieee754_fp_0_1;
ARCHITECTURE affine_block_uint_to_ieee754_fp_0_1_arch OF affine_block_uint_to_ieee754_fp_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF affine_block_uint_to_ieee754_fp_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT uint_to_ieee754_fp IS
GENERIC (
WIDTH : INTEGER
);
PORT (
x : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT uint_to_ieee754_fp;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF affine_block_uint_to_ieee754_fp_0_1_arch: ARCHITECTURE IS "uint_to_ieee754_fp,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF affine_block_uint_to_ieee754_fp_0_1_arch : ARCHITECTURE IS "affine_block_uint_to_ieee754_fp_0_1,uint_to_ieee754_fp,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF affine_block_uint_to_ieee754_fp_0_1_arch: ARCHITECTURE IS "affine_block_uint_to_ieee754_fp_0_1,uint_to_ieee754_fp,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=uint_to_ieee754_fp,x_ipVersion=1.0,x_ipCoreRevision=4,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,WIDTH=10}";
BEGIN
U0 : uint_to_ieee754_fp
GENERIC MAP (
WIDTH => 10
)
PORT MAP (
x => x,
y => y
);
END affine_block_uint_to_ieee754_fp_0_1_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:uint_to_ieee754_fp:1.0
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY affine_block_uint_to_ieee754_fp_0_1 IS
PORT (
x : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END affine_block_uint_to_ieee754_fp_0_1;
ARCHITECTURE affine_block_uint_to_ieee754_fp_0_1_arch OF affine_block_uint_to_ieee754_fp_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF affine_block_uint_to_ieee754_fp_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT uint_to_ieee754_fp IS
GENERIC (
WIDTH : INTEGER
);
PORT (
x : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
y : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT uint_to_ieee754_fp;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF affine_block_uint_to_ieee754_fp_0_1_arch: ARCHITECTURE IS "uint_to_ieee754_fp,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF affine_block_uint_to_ieee754_fp_0_1_arch : ARCHITECTURE IS "affine_block_uint_to_ieee754_fp_0_1,uint_to_ieee754_fp,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF affine_block_uint_to_ieee754_fp_0_1_arch: ARCHITECTURE IS "affine_block_uint_to_ieee754_fp_0_1,uint_to_ieee754_fp,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=uint_to_ieee754_fp,x_ipVersion=1.0,x_ipCoreRevision=4,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,WIDTH=10}";
BEGIN
U0 : uint_to_ieee754_fp
GENERIC MAP (
WIDTH => 10
)
PORT MAP (
x => x,
y => y
);
END affine_block_uint_to_ieee754_fp_0_1_arch;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_a
--
-- Generated
-- by: wig
-- on: Fri Jul 15 16:37:20 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../sigport.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_a-rtl-a.vhd,v 1.3 2005/07/15 16:20:04 wig Exp $
-- $Date: 2005/07/15 16:20:04 $
-- $Log: ent_a-rtl-a.vhd,v $
-- Revision 1.3 2005/07/15 16:20:04 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ent_a
--
architecture rtl of ent_a is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component ent_aa --
-- No Generated Generics
port (
-- Generated Port for Entity ent_aa
port_aa_1 : out std_ulogic;
port_aa_2 : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
port_aa_3 : out std_ulogic;
port_aa_4 : in std_ulogic;
port_aa_5 : out std_ulogic_vector(3 downto 0);
port_aa_6 : out std_ulogic_vector(3 downto 0);
sig_07 : out std_ulogic_vector(5 downto 0);
sig_08 : out std_ulogic_vector(8 downto 2);
sig_13 : out std_ulogic_vector(4 downto 0)
-- End of Generated Port for Entity ent_aa
);
end component;
-- ---------
component ent_ab --
-- No Generated Generics
port (
-- Generated Port for Entity ent_ab
port_ab_1 : in std_ulogic;
port_ab_2 : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
sig_13 : in std_ulogic_vector(4 downto 0)
-- End of Generated Port for Entity ent_ab
);
end component;
-- ---------
component ent_ac --
-- No Generated Generics
port (
-- Generated Port for Entity ent_ac
port_ac_2 : out std_ulogic -- __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity ent_ac
);
end component;
-- ---------
component ent_ad --
-- No Generated Generics
port (
-- Generated Port for Entity ent_ad
port_ad_2 : out std_ulogic -- __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity ent_ad
);
end component;
-- ---------
component ent_ae --
-- No Generated Generics
port (
-- Generated Port for Entity ent_ae
port_ae_2 : in std_ulogic_vector(4 downto 0);
port_ae_5 : in std_ulogic_vector(3 downto 0);
port_ae_6 : in std_ulogic_vector(3 downto 0);
sig_07 : in std_ulogic_vector(5 downto 0);
sig_08 : in std_ulogic_vector(8 downto 2);
sig_i_ae : in std_ulogic_vector(6 downto 0);
sig_o_ae : out std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity ent_ae
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal sig_01 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal sig_02 : std_ulogic_vector(4 downto 0);
signal sig_03 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal sig_04 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal sig_05 : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal sig_06 : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_sig_07 : std_ulogic_vector(5 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_sig_08 : std_ulogic_vector(8 downto 2); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_sig_13 : std_ulogic_vector(4 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal sig_i_ae : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal sig_o_ae : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
p_mix_sig_01_go <= sig_01; -- __I_O_BIT_PORT
p_mix_sig_03_go <= sig_03; -- __I_O_BIT_PORT
sig_04 <= p_mix_sig_04_gi; -- __I_I_BIT_PORT
p_mix_sig_05_2_1_go(1 downto 0) <= sig_05(2 downto 1); -- __I_O_SLICE_PORT
sig_06 <= p_mix_sig_06_gi; -- __I_I_BUS_PORT
s_int_sig_07 <= sig_07; -- __I_I_BUS_PORT
sig_08 <= s_int_sig_08; -- __I_O_BUS_PORT
sig_13 <= s_int_sig_13; -- __I_O_BUS_PORT
sig_i_ae <= p_mix_sig_i_ae_gi; -- __I_I_BUS_PORT
p_mix_sig_o_ae_go <= sig_o_ae; -- __I_O_BUS_PORT
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_aa
inst_aa: ent_aa
port map (
port_aa_1 => sig_01, -- Use internally test1Will create p_mix_sig_1_go port
port_aa_2 => sig_02(0), -- Use internally test2, no port generated
port_aa_3 => sig_03, -- Interhierachy link, will create p_mix_sig_3_go
port_aa_4 => sig_04, -- Interhierachy link, will create p_mix_sig_4_gi
port_aa_5 => sig_05, -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBus,...
port_aa_6 => sig_06, -- Conflicting definition (X2)
sig_07 => s_int_sig_07, -- Conflicting definition, IN false!
sig_08 => s_int_sig_08, -- VHDL intermediate needed (port name)
sig_13 => s_int_sig_13 -- Create internal signal name
);
-- End of Generated Instance Port Map for inst_aa
-- Generated Instance Port Map for inst_ab
inst_ab: ent_ab
port map (
port_ab_1 => sig_01, -- Use internally test1Will create p_mix_sig_1_go port
port_ab_2 => sig_02(1), -- Use internally test2, no port generated
sig_13 => s_int_sig_13 -- Create internal signal name
);
-- End of Generated Instance Port Map for inst_ab
-- Generated Instance Port Map for inst_ac
inst_ac: ent_ac
port map (
port_ac_2 => sig_02(3) -- Use internally test2, no port generated
);
-- End of Generated Instance Port Map for inst_ac
-- Generated Instance Port Map for inst_ad
inst_ad: ent_ad
port map (
port_ad_2 => sig_02(4) -- Use internally test2, no port generated
);
-- End of Generated Instance Port Map for inst_ad
-- Generated Instance Port Map for inst_ae
inst_ae: ent_ae
port map (
port_ae_2(1 downto 0) => sig_02(1 downto 0), -- Use internally test2, no port generated
port_ae_2(4 downto 3) => sig_02(4 downto 3), -- Use internally test2, no port generated
port_ae_5 => sig_05, -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBus,...
port_ae_6 => sig_06, -- Conflicting definition (X2)
sig_07 => s_int_sig_07, -- Conflicting definition, IN false!
sig_08 => s_int_sig_08, -- VHDL intermediate needed (port name)
sig_i_ae => sig_i_ae, -- Input Bus
sig_o_ae => sig_o_ae -- Output Bus
);
-- End of Generated Instance Port Map for inst_ae
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
-- TIMER.VHD (a peripheral module for SCOMP)
-- 2003.04.24
--
-- Timer returns a 16 bit counter value with a resolution of the CLOCK period.
-- Writing any value to timer resets to 0x0000, but the timer continues to run.
-- The counter value rolls over to 0x0000 after a clock tick at 0xFFFF.
LIBRARY IEEE;
LIBRARY LPM;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE LPM.LPM_COMPONENTS.ALL;
ENTITY TIMER IS
PORT(CLOCK,
RESETN,
CS,
IO_WRITE : IN STD_LOGIC;
IO_DATA : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0) );
END TIMER;
ARCHITECTURE a OF TIMER IS
SIGNAL COUNT : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL IO_OUT : STD_LOGIC;
BEGIN
-- Use LPM function to create bidirection I/O data bus
IO_BUS: lpm_bustri
GENERIC MAP (
lpm_width => 16
)
PORT MAP (
data => COUNT,
enabledt => IO_OUT,
tridata => IO_DATA
);
IO_OUT <= (CS AND NOT(IO_WRITE));
PROCESS (CLOCK, RESETN, CS, IO_WRITE)
BEGIN
IF (RESETN = '0' OR (CS AND IO_WRITE) = '1') THEN
COUNT <= x"0000";
ELSIF (FALLING_EDGE(CLOCK)) THEN
COUNT <= COUNT + 1;
END IF;
END PROCESS;
END a;
|
-- $Id: rlink_mon.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2014 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: rlink_mon - sim
-- Description: rlink monitor (for tb's)
--
-- Dependencies: -
-- Test bench: -
-- Tool versions: xst 8.2-17.7; ghdl 0.18-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2014-11-08 602 4.0.2 annotate clobber commas
-- 2014-10-25 599 4.0.1 use writeoptint()
-- 2014-10-12 596 4.0 adopt to new escaping, better 8 bit output
-- 2011-12-23 444 3.1 CLK_CYCLE now integer
-- 2011-11-19 427 3.0.2 now numeric_std clean
-- 2010-12-24 347 3.0.1 rename: CP_*->RL->*
-- 2010-12-22 346 3.0 renamed rritb_cpmon -> rlink_mon
-- 2010-06-11 303 2.5.1 fix data9 assignment, always proper width now
-- 2010-06-07 302 2.5 use sop/eop framing instead of soc+chaining
-- 2008-03-24 129 1.0.1 CLK_CYCLE now 31 bits
-- 2007-09-09 81 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
use work.rlinklib.all;
use work.comlib.all;
entity rlink_mon is -- rlink monitor
generic (
DWIDTH : positive := 9); -- data port width (8 or 9)
port (
CLK : in slbit; -- clock
CLK_CYCLE : in integer := 0; -- clock cycle number
ENA : in slbit := '1'; -- enable monitor output
RL_DI : in slv(DWIDTH-1 downto 0); -- rlink: data in
RL_ENA : in slbit; -- rlink: data enable
RL_BUSY : in slbit; -- rlink: data busy
RL_DO : in slv(DWIDTH-1 downto 0); -- rlink: data out
RL_VAL : in slbit; -- rlink: data valid
RL_HOLD : in slbit -- rlink: data hold
);
end rlink_mon;
architecture sim of rlink_mon is
begin
assert DWIDTH=8 or DWIDTH=9
report "assert(DWIDTH=8 or DWIDTH=9)" severity failure;
proc_moni: process
variable oline : line;
variable nbusy : integer := 0;
variable nhold : integer := 0;
variable edatarx : boolean := false;
variable edatatx : boolean := false;
procedure write_val(L: inout line;
data: in slv(DWIDTH-1 downto 0);
nwait: in integer;
txt1: in string(1 to 2);
txt2: in string;
edata: in boolean) is
variable data9 : slv9 := (others=>'0');
variable optxt : string(1 to 8) := ": ??rx ";
begin
if DWIDTH = 9 then
optxt(3 to 4) := "rl";
else
optxt(3 to 4) := "r8";
end if;
optxt(5 to 6) := txt1;
writetimestamp(L, CLK_CYCLE, optxt);
if DWIDTH = 9 then
write(L, data(data'left), right, 1);
else
write(L, string'(" "));
end if;
write(L, data(7 downto 0), right, 9);
writeoptint(L, txt2, nwait);
if DWIDTH=9 and data(data'left)='1' then
-- a copy to data9 needed to allow following case construct
-- using data directly gives a 'subtype is not locally static' error
data9 := (others=>'0');
data9(data'range) := data;
write(L, string'(" comma"));
case data9 is
when c_rlink_dat_sop => write(L, string'(" sop"));
when c_rlink_dat_eop => write(L, string'(" eop"));
when c_rlink_dat_nak => write(L, string'(" nak"));
when c_rlink_dat_attn => write(L, string'(" attn"));
when others => write(L, string'(" clobber|oob"));
end case;
end if;
if DWIDTH = 8 then
if edata then
write(L, string'(" edata"));
if data(c_cdata_edf_pref) /= c_cdata_ed_pref or
(not data(c_cdata_edf_eci)) /= data(c_cdata_edf_ec) then
write(L, string'(" FAIL: bad format"));
else
write(L, string'(" ec="));
write(L, data(c_cdata_edf_ec));
data9 := (others=>'0');
data9(8) := '1';
data9(c_cdata_edf_ec) := data(c_cdata_edf_ec);
case data9 is
when c_rlink_dat_sop => write(L, string'(" (sop)"));
when c_rlink_dat_eop => write(L, string'(" (eop)"));
when c_rlink_dat_nak => write(L, string'(" (nak)"));
when c_rlink_dat_attn => write(L, string'(" (attn)"));
when "100000" & c_cdata_ec_xon => write(L, string'(" (xon)"));
when "100000" & c_cdata_ec_xoff => write(L, string'(" (xoff)"));
when "100000" & c_cdata_ec_fill => write(L, string'(" (fill)"));
when "100000" & c_cdata_ec_esc => write(L, string'(" (esc)"));
when others =>
write(L, string'(" FAIL: bad ec"));
end case;
end if;
end if;
if data = c_cdata_escape then
write(L, string'(" escape"));
end if;
end if;
writeline(output, L);
end procedure write_val;
begin
loop
if ENA='0' then -- if disabled
wait until ENA='1'; -- stall process till enabled
end if;
wait until rising_edge(CLK); -- check at end of clock cycle
if RL_ENA = '1' then
if RL_BUSY = '1' then
nbusy := nbusy + 1;
else
write_val(oline, RL_DI, nbusy, "rx", " nbusy=", edatarx);
edatarx := RL_DI=c_cdata_escape;
nbusy := 0;
end if;
else
nbusy := 0;
end if;
if RL_VAL = '1' then
if RL_HOLD = '1' then
nhold := nhold + 1;
else
write_val(oline, RL_DO, nhold, "tx", " nhold=", edatatx);
edatatx := RL_DO=c_cdata_escape;
nhold := 0;
end if;
else
nhold := 0;
end if;
end loop;
end process proc_moni;
end sim;
|
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
-- Binary wrap-around counter with enable
entity counter_en is
port (Clk : in std_logic;
Rst : in std_logic;
Enable : in std_logic;
Cnt : out std_logic_vector (1 downto 0));
end counter_en;
-- Operation:
-- Count number of cycles @Enable is up.
-- Increase input from 0 to 2^N_BITS - 1 then start from zero again.
architecture Behavioral of counter_en is
signal count : std_logic_vector (N_BITS - 1 downto 0);
begin
Cnt <= count;
inc : process (Clk)
begin
if RISING_EDGE(Clk) then
if Enable = '1' then
count <= count + 1;
end if;
if Rst = '1' then
count <= (others => '0');
end if;
end if;
end process;
end Behavioral;
|
Library IEEE;
Use IEEE.std_logic_1164.All;
Use IEEE.std_logic_unsigned.All;
Entity testbench Is End testbench;
Architecture tb_upDownCounter Of testbench Is
Signal clk : STD_LOGIC := '1';
Signal inputSwitch : STD_LOGIC := '0';
Signal led0 : STD_LOGIC;
Signal led1 : STD_LOGIC;
Signal led2 : STD_LOGIC;
Signal led3 : STD_LOGIC;
Signal counter : integer range 0 to 4;
Signal clockCounter : integer range 0 to 50000000;
Constant twenty_five_nsec : time := 25 ns;
Component upDownCounter Port (
clk: in STD_LOGIC;
inputSwitch : in STD_LOGIC;
led0 : out STD_LOGIC;
led1 : out STD_LOGIC;
led2 : out STD_LOGIC;
led3 : out STD_LOGIC;
counter : inout integer range 0 to 4;
clockCounter : inout integer range 0 to 5);
End Component upDownCounter;
Begin
upDownCounter1 : upDownCounter
Port Map (
inputSwitch => inputSwitch,
clk => clk,
led0 => led0,
led1 => led1,
led2 => led2,
led3 => led3,
counter => counter,
clockCounter => clockCounter);
create_twenty_Mhz: Process
Begin
Wait For twenty_five_nsec;
clk <= NOT clk;
End Process;
inputSwitch <= '1' After 500 ns,
'0' After 1500 ns;
End tb_upDownCounter; |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: misc
-- File: mul_dware.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Dware multipliers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library Dware;
use DWARE.DWpackages.all;
use DWARE.DW_Foundation_comp_arith.all;
entity mul_dw is
generic (
a_width : positive := 2; -- multiplier word width
b_width : positive := 2; -- multiplicand word width
num_stages : positive := 2; -- number of pipeline stages
stall_mode : natural range 0 to 1 := 1 -- '0': non-stallable; '1': stallable
);
port(a : in std_logic_vector(a_width-1 downto 0);
b : in std_logic_vector(b_width-1 downto 0);
clk : in std_logic;
en : in std_logic;
sign : in std_logic;
product : out std_logic_vector(a_width+b_width-1 downto 0));
end;
architecture rtl of mul_dw is
component DW02_mult
generic( A_width: NATURAL; -- multiplier wordlength
B_width: NATURAL); -- multiplicand wordlength
port(A : in std_logic_vector(A_width-1 downto 0);
B : in std_logic_vector(B_width-1 downto 0);
TC : in std_logic; -- signed -> '1', unsigned -> '0'
PRODUCT : out std_logic_vector(A_width+B_width-1 downto 0));
end component;
signal gnd : std_ulogic;
begin
gnd <= '0';
np : if num_stages = 1 generate
u0 : DW02_mult
generic map ( a_width => a_width, b_width => b_width)
port map (a => a, b => b, TC => sign, product => product);
end generate;
pipe : if num_stages > 1 generate
u0 : DW_mult_pipe
generic map ( a_width => a_width, b_width => b_width,
num_stages => num_stages, stall_mode => stall_mode, rst_mode => 0)
port map (a => a, b => b, TC => sign, clk => clk, product => product,
rst_n => gnd, en => en);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library Dware;
use DWARE.DWpackages.all;
use DWARE.DW_Foundation_comp_arith.all;
entity dw_mul_61x61 is
port(A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end;
architecture rtl of dw_mul_61x61 is
signal gnd : std_ulogic;
signal pin, p : std_logic_vector(121 downto 0);
begin
gnd <= '0';
-- u0 : DW02_mult_2_stage
-- generic map ( A_width => A'length, B_width => B'length )
-- port map ( A => A, B => B, TC => gnd, CLK => CLK, PRODUCT => pin );
u0 : DW_mult_pipe
generic map ( a_width => 61, b_width => 61,
num_stages => 2, stall_mode => 0, rst_mode => 0)
port map (a => a, b => b, TC => gnd, clk => clk, product => pin,
rst_n => gnd, en => gnd);
reg0 : process(CLK)
begin
if rising_edge(CLK) then
p <= pin;
end if;
end process;
PRODUCT <= p;
end;
|
--------------------------------------------------------------------------------
--Copyright (c) 2014, Benjamin Bässler <[email protected]>
--All rights reserved.
--
--Redistribution and use in source and binary forms, with or without
--modification, are permitted provided that the following conditions are met:
--
--* Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
--
--* Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
--
--THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
--IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
--FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
--DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
--SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
--CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
--OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
--OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
--! @file camif.vhd
--! @brief Simulates the interface of the camera to the PCCL
--! @author Benjamin Bässler
--! @email [email protected]
--! @date 2014-04-11
--! @details This is the top module for the verification of a interface with vsync and
--! hsync used by the camera to send data to the PCCL
--! For automatic exhaustive testing of the PCCL use the verificator.vhd
--------------------------------------------------------------------------------
library ieee;
--! Use numeric std
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
use IEEE.math_real.all;
use work.types.all;
use work.utils.all;
library pccl_lib;
use pccl_lib.all;
use pccl_lib.common.all;
entity camif is
generic(
--! Image width
-- value from ccl_dut common.vhd
G_IMG_WIDTH : NATURAL := C_IMAGE_WIDTH;
--! Image height
-- value from ccl_dut common.vhd
G_IMG_HEIGHT : NATURAL := C_IMAGE_HEIGHT;
--! Number of parallel pixels
G_NO_PX : NATURAL := no_pixels;
--! Input width in bits
G_IN_WIDTH : NATURAL := 1024;
G_FIFO_SIZE : NATURAL := 64
);
port(
--! Clock input
clk_in : in STD_LOGIC;
clk_cam_in : in STD_LOGIC;
--! Reset input
rst_in : in STD_LOGIC;
min_fll_lvl_in : in UNSIGNED(15 downto 0);
-- input of image data
-- 16 MSB bits are used to save the number of valid pixels
-- only the last package of pixels can be smaller than 1024
data_in : in UNSIGNED(G_IN_WIDTH+16 - 1 downto 0);
data_vl_in : in STD_LOGIC;
data_in_rdy_out : out STD_LOGIC;
--! output data out
data_out : out UNSIGNED(63 downto 0);
data_rdy_in : in STD_LOGIC;
data_vl_out : out STD_LOGIC;
--! error value
error_out : out UNSIGNED(0 to 5);
--! high if image processing is completed
done_out : out STD_LOGIC;
--vsync error injection
vsync_err_in : in T_CAM_ERR;
--hsync error injection
hsync_err_in : in T_CAM_ERR;
--px active error injection
-- if value = 1 inserts a additional pixel before the given coordinate
-- if value = 0 forces the active signal to zero for the given coordinate
active_err_in : in T_CAM_ERR
);
end entity camif;
architecture camif_arc of camif is
--! pccl_dut signals
signal dut_fo_rdy_s : STD_LOGIC;
signal dut_hsync_s : STD_LOGIC;
signal dut_px_active_s : STD_LOGIC;
signal dut_px_s : UNSIGNED (0 to G_NO_PX-1);
signal dut_rst_s : STD_LOGIC;
signal dut_vsync_s : STD_LOGIC;
signal dut_error_s : STD_LOGIC_VECTOR (error_out'range);
signal dut_out_s : STD_LOGIC_VECTOR (gdt_data_range);
signal dut_out_vl_s : STD_LOGIC;
signal done_wait_s : UNSIGNED(log2_ceil(C_DUT_EXTRA_CLKS+1)-1 downto 0);
signal px_active_s : STD_LOGIC;
--! OUT FIFO signals
signal fifo_out_in_s : STD_LOGIC_VECTOR(63 downto 0) := (others => '0');
signal fifo_out_in_vl_s: STD_LOGIC;
signal fifo_out_full_s : STD_LOGIC;
signal fifo_out_rd_s : STD_LOGIC_VECTOR(63 downto 0);
signal fifo_out_rd_nx_s: STD_LOGIC;
signal fifo_out_empty_s: STD_LOGIC;
--! FIFO signals
signal fifo_rst_s : STD_LOGIC;
signal fifo_in_s : UNSIGNED(G_IN_WIDTH - 1 downto 0);
signal fifo_in_vl_s : STD_LOGIC;
signal fifo_full_s : STD_LOGIC;
signal fifo_rd_s : UNSIGNED(G_NO_PX - 1 downto 0);
signal fifo_rd_nxt_s : STD_LOGIC;
signal fifo_empty_s : STD_LOGIC;
--signal fifo_lvl_s : UNSIGNED(log2_ceil(G_FIFO_SIZE) downto 0);
signal fifo_as_rd_nxt_s: STD_LOGIC;
signal fifo_as_full_s : STD_LOGIC;
signal fifo_as_empty_s : STD_LOGIC;
signal fifo_as_pempty_s: STD_LOGIC;
signal fifo_as_rd_s : STD_LOGIC_VECTOR(15 downto 0);
signal fifo_as_pthresh_s : STD_LOGIC_VECTOR(6 downto 0);
signal fifo_as_wr_en_s : STD_LOGIC;
signal fifo_as_rst_s : STD_LOGIC;
signal vl_pixel_s : UNSIGNED(log2_ceil(C_IMAGE_HEIGHT * C_IMAGE_HEIGHT*2) downto 0);
signal row_cnt_s : UNSIGNED(log2_ceil(G_IMG_HEIGHT) downto 0);
signal col_cnt_s : UNSIGNED(log2_ceil(G_IMG_WIDTH) downto 0);
signal int_err_s : UNSIGNED(dut_error_s'range);
type T_STATE is (WAITING_DATA, PROCESSING, DONE, DONE_WAIT, RESET);
signal state_s : T_STATE;
signal state_dl1_s : T_STATE;
signal state_dl2_s : T_STATE;
signal active_err_d1_s : T_CAM_ERR;
signal hsync_err_d1_s : T_CAM_ERR;
signal vsync_err_d1_s : T_CAM_ERR;
signal active_err_d2_s : T_CAM_ERR;
signal hsync_err_d2_s : T_CAM_ERR;
signal vsync_err_d2_s : T_CAM_ERR;
signal active_err_s : T_CAM_ERR;
signal active_err_exe_s: unsigned(T_CAM_ERR'range);
signal hsync_err_s : T_CAM_ERR;
signal vsync_err_s : T_CAM_ERR;
signal min_fll_lvl_d1_s : STD_LOGIC_VECTOR(fifo_as_pthresh_s'range);
signal min_fll_lvl_d2_s : STD_LOGIC_VECTOR(fifo_as_pthresh_s'range);
begin
-- store active, hsync, vsync error injection values on reset
-- prevent metastable signals
p_err_store : process (clk_in, clk_cam_in)
begin
if rising_edge(clk_in) then
active_err_d1_s <= active_err_in;
hsync_err_d1_s <= hsync_err_in;
vsync_err_d1_s <= vsync_err_in;
end if;
if rising_edge(clk_cam_in) then
active_err_d2_s <= active_err_d1_s;
hsync_err_d2_s <= hsync_err_d1_s;
vsync_err_d2_s <= vsync_err_d1_s;
active_err_s <= active_err_d2_s;
hsync_err_s <= hsync_err_d2_s;
vsync_err_s <= vsync_err_d2_s;
end if;
end process;
-- prevent metastable signal for fifo fill level threshold before start with processing pixels
p_min_stable : process (clk_cam_in, clk_in)
begin
if rising_edge(clk_in) then
min_fll_lvl_d1_s <= STD_LOGIC_VECTOR(min_fll_lvl_in(min_fll_lvl_d1_s'range));
end if;
if rising_edge(clk_cam_in) then
min_fll_lvl_d2_s <= min_fll_lvl_d1_s;
fifo_as_pthresh_s <= min_fll_lvl_d2_s;
end if;
end process p_min_stable;
--! state machine generating the internal state
--! states: WAITING_DATA -> the buffer has not reached the min_fll_lvl_in
--! waiting for more data
--! PROCESSING -> enough data in the fifo writing data to camera
--! interface
--! RESET -> start new image
--! DONE_WAIT -> All pixels are send to the DUT waiting for all
--! output data
--! DONE -> All output data should be read
p_state : process (rst_in, clk_cam_in)
begin
if rst_in = '0' then
if rising_edge(clk_cam_in) then
dut_rst_s <= '0';
px_active_s <= '0';
dut_vsync_s <= '0';
dut_hsync_s <= '0';
fifo_as_rst_s <= '0';
fifo_as_rd_nxt_s <= '0';
int_err_s <= int_err_s or unsigned(dut_error_s);
case state_s is
when WAITING_DATA =>
if fifo_as_pempty_s = '0' then --fifo_lvl_s >= min_fll_lvl_in then
state_s <= PROCESSING;
fifo_as_rd_nxt_s <= '1';
end if;
when PROCESSING =>
if fifo_as_empty_s = '1' then --if vl_pixel_s < G_NO_PX then --fifo_lvl_s = 0 then
state_s <= WAITING_DATA;
if row_cnt_s = G_IMG_HEIGHT then
state_s <= DONE_WAIT;
end if;
else
px_active_s <= '1';
fifo_as_rd_nxt_s <= '1';
if col_cnt_s = 0 then
dut_hsync_s <= '1';
if row_cnt_s = 0 then
dut_vsync_s <= '1';
end if;
end if;
col_cnt_s <= col_cnt_s + G_NO_PX;
if col_cnt_s = G_IMG_WIDTH-G_NO_PX then
row_cnt_s <= row_cnt_s + 1;
col_cnt_s <= (others => '0');
end if;
-- active overwrite
for i in active_err_s'range loop
if active_err_s(i).row = row_cnt_s and
active_err_s(i).col = col_cnt_s
then
if active_err_s(i).val = '1' and active_err_exe_s(i) = '0' then
row_cnt_s <= row_cnt_s;
col_cnt_s <= col_cnt_s;
dut_hsync_s <= '0';
dut_vsync_s <= '0';
fifo_as_rd_nxt_s <= '0';
active_err_exe_s(i) <= '1';
elsif active_err_s(i).val = '0' then
px_active_s <= '0';
end if;
end if;
end loop;
-- hsync overwrite
for i in hsync_err_s'range loop
if hsync_err_s(i).row = row_cnt_s and
hsync_err_s(i).col = col_cnt_s
then
dut_hsync_s <= hsync_err_s(i).val;
end if;
end loop;
-- vsync overwrite
for i in hsync_err_s'range loop
if vsync_err_s(i).row = row_cnt_s and
vsync_err_s(i).col = col_cnt_s
then
dut_vsync_s <= vsync_err_s(i).val;
end if;
end loop;
end if;
when DONE_WAIT =>
if done_wait_s = 1 then
state_s <= DONE;
end if;
done_wait_s <= done_wait_s - 1;
fifo_as_rst_s <= '1';
when DONE =>
if done_wait_s = 0 then
state_s <= WAITING_DATA;
end if;
done_wait_s <= to_unsigned(C_DUT_EXTRA_CLKS+1, done_wait_s'length);
done_wait_s <= done_wait_s - 1;
row_cnt_s <= (others => '0');
col_cnt_s <= (others => '0');
dut_hsync_s <= '0';
fifo_as_rst_s <= '1';
active_err_exe_s <= (others => '0');
when RESET =>
state_s <= WAITING_DATA;
done_wait_s <= to_unsigned(C_DUT_EXTRA_CLKS+1, done_wait_s'length);
row_cnt_s <= (others => '0');
col_cnt_s <= (others => '0');
dut_hsync_s <= '0';
dut_rst_s <= '1';
fifo_as_rst_s <= '1';
int_err_s <= (others => '0');
active_err_exe_s <= (others => '0');
end case;
end if;
else
state_s <= RESET;
done_wait_s <= to_unsigned(C_DUT_EXTRA_CLKS+1, done_wait_s'length);
row_cnt_s <= (others => '0');
col_cnt_s <= (others => '0');
dut_hsync_s <= '0';
dut_rst_s <= '1';
fifo_as_rst_s <= '1';
int_err_s <= (others => '0');
active_err_exe_s <= (others => '0');
end if;
end process p_state;
p_rst_fifo : process (state_s)
begin
case state_s is
when RESET =>
fifo_rst_s <= '1';
when DONE_WAIT =>
fifo_rst_s <= '1';
when others =>
fifo_rst_s <= '0';
end case;
end process p_rst_fifo;
--! process for generating delay state signal
p_state_dl : process (clk_cam_in, clk_in)
begin
if rising_edge(clk_cam_in) then
state_dl1_s <= state_s;
end if;
if rising_edge(clk_in) then
state_dl2_s <= state_dl1_s;
end if;
end process p_state_dl;
fifo_rd_nxt_s <= not fifo_empty_s;
fifo_as_wr_en_s <= '1' when fifo_empty_s = '0' and vl_pixel_s > 0 else '0';
--! counts the valid pixels int the buffer
p_vl_px_cnt : process (clk_in, rst_in)
begin
if rst_in = '1' then
vl_pixel_s <= (others => '0');
else
if rising_edge(clk_in) then
if fifo_rd_nxt_s = '1' and vl_pixel_s >= G_NO_PX then --state_s = PROCESSING then
vl_pixel_s <= vl_pixel_s - G_NO_PX;
end if;
if data_vl_in = '1' then
if fifo_rd_nxt_s = '1' and vl_pixel_s >= G_NO_PX then --state_s = PROCESSING then
vl_pixel_s <= resize(vl_pixel_s + 8*data_in(data_in'high downto
data_in'high-16+1) - G_NO_PX, vl_pixel_s'length);
else
vl_pixel_s <= resize(vl_pixel_s + 8*data_in(data_in'high downto
data_in'high-16+1), vl_pixel_s'length);
end if;
end if;
end if;--clk
end if;--rst
end process p_vl_px_cnt;
error_out <= int_err_s;
done_out <= '1' when state_dl2_s = DONE and state_dl2_s /= DONE and rst_in = '0' else '0';
dut_px_s <= unsigned(fifo_as_rd_s);
-- convert to unsigned
dut_fo_rdy_s <= not fifo_out_full_s;
data_vl_out <= not fifo_out_empty_s;
fifo_out_in_s(dut_out_s'range) <= dut_out_s;
data_out <= unsigned(fifo_out_rd_s);
fifo_out : entity work.out_fifo
port map (
rst => rst_in,
wr_clk => clk_cam_in,
rd_clk => clk_in,
din => fifo_out_in_s,
wr_en => dut_out_vl_s,
rd_en => data_rdy_in,
dout => fifo_out_rd_s,
full => fifo_out_full_s,
empty => fifo_out_empty_s
);
dut_px_active_s <= px_active_s;-- and not fifo_as_empty_s;
pccl_dut : entity pccl_lib.pccl_top
generic map(
add_cu => False
)
port map (
clk => clk_cam_in,
fo_rdy => dut_fo_rdy_s,
hsync => dut_hsync_s,
pixel_active => dut_px_active_s,
pixel_clk => clk_cam_in,
pixel_data => std_logic_vector(dut_px_s),
res => dut_rst_s,
vsync => dut_vsync_s,
error_code => dut_error_s,
fo => dut_out_s,
fo_valid => dut_out_vl_s
);
-- the first 16 bits are used to indicate the number of valid bytes in data_in
fifo_in_s <= data_in(data_in'high-16 downto 0);
fifo_in_vl_s <= data_vl_in;
data_in_rdy_out <= not fifo_full_s;
in_async_fifo : entity work.in_fifo
port map (
rst => fifo_as_rst_s,
wr_clk => clk_in,
rd_clk => clk_cam_in,
din => std_logic_vector(fifo_rd_s),
wr_en => fifo_as_wr_en_s,
rd_en => fifo_as_rd_nxt_s,
dout => fifo_as_rd_s,
full => fifo_as_full_s,
empty => fifo_as_empty_s,
prog_empty_thresh => fifo_as_pthresh_s,
prog_empty => fifo_as_pempty_s
);
in_fifo : entity work.fifo_asym
generic map(
G_SIZE => G_FIFO_SIZE,
G_OUT_WORD_WIDTH=> G_NO_PX,
G_IN_MUL_WIDTH => G_IN_WIDTH/G_NO_PX,
G_ALMOST_EMPTY => 1,
G_ALMOST_FULL => G_FIFO_SIZE - 1,
G_FWFT => true
)
port map(
rst_in => fifo_rst_s,
clk_in => clk_in,
--! Data input
wr_d_in => fifo_in_s,
wr_valid_in => fifo_in_vl_s,
almost_full_out => open,
full_out => fifo_full_s,
--! Data output
rd_d_out => fifo_rd_s,
rd_next_in => fifo_rd_nxt_s,
almost_empty_out=> open,
empty_out => fifo_empty_s,
--! Fill level of fifo
fill_lvl_out => open --fifo_lvl_s
);
end architecture camif_arc;
|
-- Type qualified expressions
entity bar is end entity;
architecture foo of bar is
type foo is (a, b, 'c');
type bar is (a, b, c);
signal x : foo;
begin
process is
begin
x <= foo'(b);
--x <= foo'('c');
x <= foo'( 'c' );
end process;
end architecture;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: atmel_components
-- File: atmel_components.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: ATMEL ATC18 component declarations
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package atc18_components is
-- input pad
component pc33d00 port (pad : in std_logic; cin : out std_logic); end component;
-- input pad with pull-up
component pc33d00u port (pad : in std_logic; cin : out std_logic); end component;
-- schmitt input pad
component pc33d20 port (pad : in std_logic; cin : out std_logic); end component;
-- schmitt input pad with pull-up
component pt33d20u port (pad : inout std_logic; cin : out std_logic); end component;
-- output pads
component pt33o01 port (i : in std_logic; pad : out std_logic); end component;
component pt33o02 port (i : in std_logic; pad : out std_logic); end component;
component pt33o03 port (i : in std_logic; pad : out std_logic); end component;
component pt33o04 port (i : in std_logic; pad : out std_logic); end component;
-- tri-state output pads
component pt33t01 port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t02 port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t03 port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t04 port (i, oen : in std_logic; pad : out std_logic); end component;
-- tri-state output pads with pull-up
component pt33t01u port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t02u port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t03u port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t04u port (i, oen : in std_logic; pad : out std_logic); end component;
-- bidirectional pads
component pt33b01
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b02
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b03
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b04
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
-- bidirectional pads with pull-up
component pt33b01u
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b02u
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b03u
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b04u
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
--PCI pads
component pp33o01
port (i : in std_logic; pad : out std_logic);
end component;
component pp33b015vt
port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pp33t015vt
port (i, oen : in std_logic; pad : out std_logic);
end component;
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: atmel_components
-- File: atmel_components.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: ATMEL ATC18 component declarations
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package atc18_components is
-- input pad
component pc33d00 port (pad : in std_logic; cin : out std_logic); end component;
-- input pad with pull-up
component pc33d00u port (pad : in std_logic; cin : out std_logic); end component;
-- schmitt input pad
component pc33d20 port (pad : in std_logic; cin : out std_logic); end component;
-- schmitt input pad with pull-up
component pt33d20u port (pad : inout std_logic; cin : out std_logic); end component;
-- output pads
component pt33o01 port (i : in std_logic; pad : out std_logic); end component;
component pt33o02 port (i : in std_logic; pad : out std_logic); end component;
component pt33o03 port (i : in std_logic; pad : out std_logic); end component;
component pt33o04 port (i : in std_logic; pad : out std_logic); end component;
-- tri-state output pads
component pt33t01 port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t02 port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t03 port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t04 port (i, oen : in std_logic; pad : out std_logic); end component;
-- tri-state output pads with pull-up
component pt33t01u port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t02u port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t03u port (i, oen : in std_logic; pad : out std_logic); end component;
component pt33t04u port (i, oen : in std_logic; pad : out std_logic); end component;
-- bidirectional pads
component pt33b01
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b02
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b03
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b04
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
-- bidirectional pads with pull-up
component pt33b01u
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b02u
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b03u
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pt33b04u
port (i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
--PCI pads
component pp33o01
port (i : in std_logic; pad : out std_logic);
end component;
component pp33b015vt
port ( i, oen : in std_logic; cin : out std_logic; pad : inout std_logic);
end component;
component pp33t015vt
port (i, oen : in std_logic; pad : out std_logic);
end component;
end;
|
library verilog;
use verilog.vl_types.all;
entity Multiple_Cycles_CPU_vlg_tst is
end Multiple_Cycles_CPU_vlg_tst;
|
library verilog;
use verilog.vl_types.all;
entity Multiple_Cycles_CPU_vlg_tst is
end Multiple_Cycles_CPU_vlg_tst;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Cx_Reconf_pseudo_checkers is
port ( reconfig_cx: in std_logic; -- *
flit_type: in std_logic_vector(2 downto 0); -- *
empty: in std_logic; -- *
grants: in std_logic; -- *
Cx_in: in std_logic_vector(3 downto 0); -- *
Temp_Cx: in std_logic_vector(3 downto 0); -- *
reconfig_cx_in: in std_logic; -- *
Cx: in std_logic_vector(3 downto 0); -- *
Faulty_C_N: in std_logic; -- *
Faulty_C_E: in std_logic; -- *
Faulty_C_W: in std_logic; -- *
Faulty_C_S: in std_logic; -- *
Temp_Cx_in: in std_logic_vector(3 downto 0); -- *
-- Checker Outputs
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_reconfig_cx_in_reconfig_cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Temp_Cx_equal : out std_logic
);
end Cx_Reconf_pseudo_checkers;
architecture behavior of Cx_Reconf_pseudo_checkers is
signal Faulty_C_signals: std_logic_vector(3 downto 0);
begin
Faulty_C_signals <= not (Faulty_C_S & Faulty_C_W & Faulty_C_E & Faulty_C_N);
process(reconfig_cx, flit_type, empty, grants, Cx_in, Temp_Cx)
begin
if (reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' and Cx_in /= Temp_Cx) then
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal <= '1';
else
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal <= '0';
end if;
end process;
process(reconfig_cx, flit_type, empty, grants, reconfig_cx_in)
begin
if (reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' and reconfig_cx_in = '1') then
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in <= '1';
else
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in <= '0';
end if;
end process;
process(reconfig_cx, flit_type, empty, grants, Cx_in, Cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and Cx_in /= Cx) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal <= '0';
end if;
end process;
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, reconfig_cx_in)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '1') and (reconfig_cx_in = '0') ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in <= '0';
end if;
end process;
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Temp_Cx_in, Faulty_C_signals, Cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '1') and (Temp_Cx_in /= (Faulty_C_signals and Cx) ) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in <= '0';
end if;
end process;
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, reconfig_cx_in, reconfig_cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '0') and (reconfig_cx_in /= reconfig_cx) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_reconfig_cx_in_reconfig_cx_equal <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_reconfig_cx_in_reconfig_cx_equal <= '0';
end if;
end process;
process(reconfig_cx, flit_type, empty, grants, Temp_Cx_in, Temp_Cx)
begin
if (reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' and Temp_Cx_in /= Temp_Cx) then
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal <= '1';
else
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal <= '0';
end if;
end process;
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Temp_Cx_in, Temp_Cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '0') and (Temp_Cx_in /= Temp_Cx) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Temp_Cx_equal <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Temp_Cx_equal <= '0';
end if;
end process;
end; |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Cx_Reconf_pseudo_checkers is
port ( reconfig_cx: in std_logic; -- *
flit_type: in std_logic_vector(2 downto 0); -- *
empty: in std_logic; -- *
grants: in std_logic; -- *
Cx_in: in std_logic_vector(3 downto 0); -- *
Temp_Cx: in std_logic_vector(3 downto 0); -- *
reconfig_cx_in: in std_logic; -- *
Cx: in std_logic_vector(3 downto 0); -- *
Faulty_C_N: in std_logic; -- *
Faulty_C_E: in std_logic; -- *
Faulty_C_W: in std_logic; -- *
Faulty_C_S: in std_logic; -- *
Temp_Cx_in: in std_logic_vector(3 downto 0); -- *
-- Checker Outputs
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_reconfig_cx_in_reconfig_cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Temp_Cx_equal : out std_logic
);
end Cx_Reconf_pseudo_checkers;
architecture behavior of Cx_Reconf_pseudo_checkers is
signal Faulty_C_signals: std_logic_vector(3 downto 0);
begin
Faulty_C_signals <= not (Faulty_C_S & Faulty_C_W & Faulty_C_E & Faulty_C_N);
process(reconfig_cx, flit_type, empty, grants, Cx_in, Temp_Cx)
begin
if (reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' and Cx_in /= Temp_Cx) then
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal <= '1';
else
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal <= '0';
end if;
end process;
process(reconfig_cx, flit_type, empty, grants, reconfig_cx_in)
begin
if (reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' and reconfig_cx_in = '1') then
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in <= '1';
else
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in <= '0';
end if;
end process;
process(reconfig_cx, flit_type, empty, grants, Cx_in, Cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and Cx_in /= Cx) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal <= '0';
end if;
end process;
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, reconfig_cx_in)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '1') and (reconfig_cx_in = '0') ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in <= '0';
end if;
end process;
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Temp_Cx_in, Faulty_C_signals, Cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '1') and (Temp_Cx_in /= (Faulty_C_signals and Cx) ) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in <= '0';
end if;
end process;
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, reconfig_cx_in, reconfig_cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '0') and (reconfig_cx_in /= reconfig_cx) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_reconfig_cx_in_reconfig_cx_equal <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_reconfig_cx_in_reconfig_cx_equal <= '0';
end if;
end process;
process(reconfig_cx, flit_type, empty, grants, Temp_Cx_in, Temp_Cx)
begin
if (reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' and Temp_Cx_in /= Temp_Cx) then
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal <= '1';
else
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal <= '0';
end if;
end process;
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Temp_Cx_in, Temp_Cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '0') and (Temp_Cx_in /= Temp_Cx) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Temp_Cx_equal <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Temp_Cx_equal <= '0';
end if;
end process;
end; |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Cx_Reconf_pseudo_checkers is
port ( reconfig_cx: in std_logic; -- *
flit_type: in std_logic_vector(2 downto 0); -- *
empty: in std_logic; -- *
grants: in std_logic; -- *
Cx_in: in std_logic_vector(3 downto 0); -- *
Temp_Cx: in std_logic_vector(3 downto 0); -- *
reconfig_cx_in: in std_logic; -- *
Cx: in std_logic_vector(3 downto 0); -- *
Faulty_C_N: in std_logic; -- *
Faulty_C_E: in std_logic; -- *
Faulty_C_W: in std_logic; -- *
Faulty_C_S: in std_logic; -- *
Temp_Cx_in: in std_logic_vector(3 downto 0); -- *
-- Checker Outputs
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_reconfig_cx_in_reconfig_cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Temp_Cx_equal : out std_logic
);
end Cx_Reconf_pseudo_checkers;
architecture behavior of Cx_Reconf_pseudo_checkers is
signal Faulty_C_signals: std_logic_vector(3 downto 0);
begin
Faulty_C_signals <= not (Faulty_C_S & Faulty_C_W & Faulty_C_E & Faulty_C_N);
process(reconfig_cx, flit_type, empty, grants, Cx_in, Temp_Cx)
begin
if (reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' and Cx_in /= Temp_Cx) then
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal <= '1';
else
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal <= '0';
end if;
end process;
process(reconfig_cx, flit_type, empty, grants, reconfig_cx_in)
begin
if (reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' and reconfig_cx_in = '1') then
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in <= '1';
else
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in <= '0';
end if;
end process;
process(reconfig_cx, flit_type, empty, grants, Cx_in, Cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and Cx_in /= Cx) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal <= '0';
end if;
end process;
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, reconfig_cx_in)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '1') and (reconfig_cx_in = '0') ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in <= '0';
end if;
end process;
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Temp_Cx_in, Faulty_C_signals, Cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '1') and (Temp_Cx_in /= (Faulty_C_signals and Cx) ) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in <= '0';
end if;
end process;
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, reconfig_cx_in, reconfig_cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '0') and (reconfig_cx_in /= reconfig_cx) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_reconfig_cx_in_reconfig_cx_equal <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_reconfig_cx_in_reconfig_cx_equal <= '0';
end if;
end process;
process(reconfig_cx, flit_type, empty, grants, Temp_Cx_in, Temp_Cx)
begin
if (reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' and Temp_Cx_in /= Temp_Cx) then
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal <= '1';
else
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal <= '0';
end if;
end process;
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Temp_Cx_in, Temp_Cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '0') and (Temp_Cx_in /= Temp_Cx) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Temp_Cx_equal <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Temp_Cx_equal <= '0';
end if;
end process;
end; |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Cx_Reconf_pseudo_checkers is
port ( reconfig_cx: in std_logic; -- *
flit_type: in std_logic_vector(2 downto 0); -- *
empty: in std_logic; -- *
grants: in std_logic; -- *
Cx_in: in std_logic_vector(3 downto 0); -- *
Temp_Cx: in std_logic_vector(3 downto 0); -- *
reconfig_cx_in: in std_logic; -- *
Cx: in std_logic_vector(3 downto 0); -- *
Faulty_C_N: in std_logic; -- *
Faulty_C_E: in std_logic; -- *
Faulty_C_W: in std_logic; -- *
Faulty_C_S: in std_logic; -- *
Temp_Cx_in: in std_logic_vector(3 downto 0); -- *
-- Checker Outputs
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_reconfig_cx_in_reconfig_cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Temp_Cx_equal : out std_logic
);
end Cx_Reconf_pseudo_checkers;
architecture behavior of Cx_Reconf_pseudo_checkers is
signal Faulty_C_signals: std_logic_vector(3 downto 0);
begin
Faulty_C_signals <= not (Faulty_C_S & Faulty_C_W & Faulty_C_E & Faulty_C_N);
process(reconfig_cx, flit_type, empty, grants, Cx_in, Temp_Cx)
begin
if (reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' and Cx_in /= Temp_Cx) then
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal <= '1';
else
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal <= '0';
end if;
end process;
process(reconfig_cx, flit_type, empty, grants, reconfig_cx_in)
begin
if (reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' and reconfig_cx_in = '1') then
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in <= '1';
else
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in <= '0';
end if;
end process;
process(reconfig_cx, flit_type, empty, grants, Cx_in, Cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and Cx_in /= Cx) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal <= '0';
end if;
end process;
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, reconfig_cx_in)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '1') and (reconfig_cx_in = '0') ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in <= '0';
end if;
end process;
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Temp_Cx_in, Faulty_C_signals, Cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '1') and (Temp_Cx_in /= (Faulty_C_signals and Cx) ) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in <= '0';
end if;
end process;
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, reconfig_cx_in, reconfig_cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '0') and (reconfig_cx_in /= reconfig_cx) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_reconfig_cx_in_reconfig_cx_equal <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_reconfig_cx_in_reconfig_cx_equal <= '0';
end if;
end process;
process(reconfig_cx, flit_type, empty, grants, Temp_Cx_in, Temp_Cx)
begin
if (reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' and Temp_Cx_in /= Temp_Cx) then
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal <= '1';
else
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal <= '0';
end if;
end process;
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Temp_Cx_in, Temp_Cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '0') and (Temp_Cx_in /= Temp_Cx) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Temp_Cx_equal <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Temp_Cx_equal <= '0';
end if;
end process;
end; |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Cx_Reconf_pseudo_checkers is
port ( reconfig_cx: in std_logic; -- *
flit_type: in std_logic_vector(2 downto 0); -- *
empty: in std_logic; -- *
grants: in std_logic; -- *
Cx_in: in std_logic_vector(3 downto 0); -- *
Temp_Cx: in std_logic_vector(3 downto 0); -- *
reconfig_cx_in: in std_logic; -- *
Cx: in std_logic_vector(3 downto 0); -- *
Faulty_C_N: in std_logic; -- *
Faulty_C_E: in std_logic; -- *
Faulty_C_W: in std_logic; -- *
Faulty_C_S: in std_logic; -- *
Temp_Cx_in: in std_logic_vector(3 downto 0); -- *
-- Checker Outputs
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_reconfig_cx_in_reconfig_cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Temp_Cx_equal : out std_logic
);
end Cx_Reconf_pseudo_checkers;
architecture behavior of Cx_Reconf_pseudo_checkers is
signal Faulty_C_signals: std_logic_vector(3 downto 0);
begin
Faulty_C_signals <= not (Faulty_C_S & Faulty_C_W & Faulty_C_E & Faulty_C_N);
process(reconfig_cx, flit_type, empty, grants, Cx_in, Temp_Cx)
begin
if (reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' and Cx_in /= Temp_Cx) then
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal <= '1';
else
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal <= '0';
end if;
end process;
process(reconfig_cx, flit_type, empty, grants, reconfig_cx_in)
begin
if (reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' and reconfig_cx_in = '1') then
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in <= '1';
else
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in <= '0';
end if;
end process;
process(reconfig_cx, flit_type, empty, grants, Cx_in, Cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and Cx_in /= Cx) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal <= '0';
end if;
end process;
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, reconfig_cx_in)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '1') and (reconfig_cx_in = '0') ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in <= '0';
end if;
end process;
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Temp_Cx_in, Faulty_C_signals, Cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '1') and (Temp_Cx_in /= (Faulty_C_signals and Cx) ) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in <= '0';
end if;
end process;
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, reconfig_cx_in, reconfig_cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '0') and (reconfig_cx_in /= reconfig_cx) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_reconfig_cx_in_reconfig_cx_equal <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_reconfig_cx_in_reconfig_cx_equal <= '0';
end if;
end process;
process(reconfig_cx, flit_type, empty, grants, Temp_Cx_in, Temp_Cx)
begin
if (reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' and Temp_Cx_in /= Temp_Cx) then
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal <= '1';
else
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal <= '0';
end if;
end process;
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Temp_Cx_in, Temp_Cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '0') and (Temp_Cx_in /= Temp_Cx) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Temp_Cx_equal <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Temp_Cx_equal <= '0';
end if;
end process;
end; |
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity Cx_Reconf_pseudo_checkers is
port ( reconfig_cx: in std_logic; -- *
flit_type: in std_logic_vector(2 downto 0); -- *
empty: in std_logic; -- *
grants: in std_logic; -- *
Cx_in: in std_logic_vector(3 downto 0); -- *
Temp_Cx: in std_logic_vector(3 downto 0); -- *
reconfig_cx_in: in std_logic; -- *
Cx: in std_logic_vector(3 downto 0); -- *
Faulty_C_N: in std_logic; -- *
Faulty_C_E: in std_logic; -- *
Faulty_C_W: in std_logic; -- *
Faulty_C_S: in std_logic; -- *
Temp_Cx_in: in std_logic_vector(3 downto 0); -- *
-- Checker Outputs
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_reconfig_cx_in_reconfig_cx_equal,
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal,
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Temp_Cx_equal : out std_logic
);
end Cx_Reconf_pseudo_checkers;
architecture behavior of Cx_Reconf_pseudo_checkers is
signal Faulty_C_signals: std_logic_vector(3 downto 0);
begin
Faulty_C_signals <= not (Faulty_C_S & Faulty_C_W & Faulty_C_E & Faulty_C_N);
process(reconfig_cx, flit_type, empty, grants, Cx_in, Temp_Cx)
begin
if (reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' and Cx_in /= Temp_Cx) then
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal <= '1';
else
err_reconfig_cx_flit_type_Tail_not_empty_grants_Cx_in_Temp_Cx_equal <= '0';
end if;
end process;
process(reconfig_cx, flit_type, empty, grants, reconfig_cx_in)
begin
if (reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' and reconfig_cx_in = '1') then
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in <= '1';
else
err_reconfig_cx_flit_type_Tail_not_empty_grants_not_reconfig_cx_in <= '0';
end if;
end process;
process(reconfig_cx, flit_type, empty, grants, Cx_in, Cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and Cx_in /= Cx) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Cx_in_Cx_equal <= '0';
end if;
end process;
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, reconfig_cx_in)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '1') and (reconfig_cx_in = '0') ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_reconfig_cx_in <= '0';
end if;
end process;
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Temp_Cx_in, Faulty_C_signals, Cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '1') and (Temp_Cx_in /= (Faulty_C_signals and Cx) ) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_Faulty_C_Temp_Cx_in <= '0';
end if;
end process;
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, reconfig_cx_in, reconfig_cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '0') and (reconfig_cx_in /= reconfig_cx) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_reconfig_cx_in_reconfig_cx_equal <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_reconfig_cx_in_reconfig_cx_equal <= '0';
end if;
end process;
process(reconfig_cx, flit_type, empty, grants, Temp_Cx_in, Temp_Cx)
begin
if (reconfig_cx = '1' and flit_type = "100" and empty = '0' and grants = '1' and Temp_Cx_in /= Temp_Cx) then
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal <= '1';
else
err_reconfig_cx_flit_type_Tail_not_empty_grants_Temp_Cx_in_Temp_Cx_equal <= '0';
end if;
end process;
process(reconfig_cx, flit_type, empty, grants, Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S, Temp_Cx_in, Temp_Cx)
begin
if ( (reconfig_cx = '0' or flit_type /= "100" or empty = '1' or grants = '0') and
((Faulty_C_N or Faulty_C_E or Faulty_C_W or Faulty_C_S) = '0') and (Temp_Cx_in /= Temp_Cx) ) then
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Temp_Cx_equal <= '1';
else
err_not_reconfig_cx_flit_type_not_Tail_empty_not_grants_not_Faulty_C_Temp_Cx_in_Temp_Cx_equal <= '0';
end if;
end process;
end; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity runningLED is
port(
clk : in std_logic; -- master clock signal
LED_output : out std_logic_vector(7 downto 0)
);
end runningLED;
architecture default of runningLED is
signal ctr : unsigned(31 downto 0);
signal pattern : std_logic_vector(7 downto 0);
begin
process( clk ) begin
if (clk'event and clk = '1') then
if(ctr = 5000000) then
ctr <= X"0000_0000";
pattern <= pattern + X"1";
LED_output <= pattern;
else
ctr <= ctr + 1;
end if;
end if;
end process;
end architecture; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc580.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:36 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00580ent IS
END c03s04b01x00p01n01i00580ent;
ARCHITECTURE c03s04b01x00p01n01i00580arch OF c03s04b01x00p01n01i00580ent IS
constant C1 : boolean := true;
type boolean_vector is array (natural range <>) of boolean;
subtype boolean_vector_st is boolean_vector(0 to 15);
type boolean_vector_st_file is file of boolean_vector_st;
constant C27 : boolean_vector_st := (others => C1);
BEGIN
TESTING: PROCESS
file filein : boolean_vector_st_file open write_mode is "iofile.28";
BEGIN
for i in 1 to 100 loop
write(filein, C27);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00580 - The output file will be verified by test s010256.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00580arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc580.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:36 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00580ent IS
END c03s04b01x00p01n01i00580ent;
ARCHITECTURE c03s04b01x00p01n01i00580arch OF c03s04b01x00p01n01i00580ent IS
constant C1 : boolean := true;
type boolean_vector is array (natural range <>) of boolean;
subtype boolean_vector_st is boolean_vector(0 to 15);
type boolean_vector_st_file is file of boolean_vector_st;
constant C27 : boolean_vector_st := (others => C1);
BEGIN
TESTING: PROCESS
file filein : boolean_vector_st_file open write_mode is "iofile.28";
BEGIN
for i in 1 to 100 loop
write(filein, C27);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00580 - The output file will be verified by test s010256.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00580arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc580.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:36 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00580ent IS
END c03s04b01x00p01n01i00580ent;
ARCHITECTURE c03s04b01x00p01n01i00580arch OF c03s04b01x00p01n01i00580ent IS
constant C1 : boolean := true;
type boolean_vector is array (natural range <>) of boolean;
subtype boolean_vector_st is boolean_vector(0 to 15);
type boolean_vector_st_file is file of boolean_vector_st;
constant C27 : boolean_vector_st := (others => C1);
BEGIN
TESTING: PROCESS
file filein : boolean_vector_st_file open write_mode is "iofile.28";
BEGIN
for i in 1 to 100 loop
write(filein, C27);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00580 - The output file will be verified by test s010256.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00580arch;
|
--
-- File Name: ScoreBoardPkg_slv.vhd
-- Design Unit Name: ScoreBoardPkg_slv
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis email: [email protected]
--
--
-- Description:
-- Instance of Generic Package ScoreboardGenericPkg for std_logic_vector
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 04/2022 2022.04 Replaced to_hstring with to_hxstring
-- 10/2020 2020.10 Replaced STD_MATCH for std_logic family with AlertLogPkg.MetaMatch
-- 01/2020 2020.01 Updated Licenses to Apache
-- 11/2016 2016.11 Released as part of OSVVM library
-- 08/2014 2013.08 Updated interface for Match and to_string
-- 08/2012 2012.08 Generic Instance of ScoreboardGenericPkg
--
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2006 - 2020 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
use std.textio.all ;
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.numeric_std.all ;
use work.TextUtilPkg.all ;
package ScoreBoardPkg_slv is new work.ScoreboardGenericPkg
generic map (
ExpectedType => std_logic_vector,
ActualType => std_logic_vector,
-- Match => std_match, -- "=", [std_logic_vector, std_logic_vector return boolean]
Match => work.AlertLogPkg.MetaMatch, -- "=", [std_logic_vector, std_logic_vector return boolean]
expected_to_string => to_hxstring, -- [std_logic_vector return string]
actual_to_string => to_hxstring -- [std_logic_vector return string]
) ;
|
-- This file is part of the ethernet_mac project.
--
-- For the full copyright and license information, please read the
-- LICENSE.md file that was distributed with this source code.
-- Self-checking testbench for the complete ethernet_mac (excluding MIIM)
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.ethernet_types.all;
use work.framing_common.all;
use work.utility.all;
use work.crc32.all;
use work.test_common.all;
entity ethernet_mac_tb is
generic(
-- Test configuration
-- Setting to TRUE enables test of all packet sizes from 1 to 1528
TEST_THOROUGH : boolean := FALSE;
-- Enforce GMII setup/hold times
TEST_MII_SETUPHOLD : boolean := FALSE;
-- Print debug information such as all sent/received data bytes
VERBOSE : boolean := FALSE
);
end entity;
architecture behavioral of ethernet_mac_tb is
-- ethernet_with_fifos signals
signal clock_125 : std_ulogic := '0';
signal reset : std_ulogic := '1';
signal mii_tx_clk : std_ulogic := '0';
signal mii_tx_er : std_ulogic := '0';
signal mii_tx_en : std_ulogic := '0';
signal mii_txd : std_ulogic_vector(7 downto 0) := (others => '0');
signal mii_rx_clk : std_ulogic := '0';
signal mii_rx_er : std_ulogic := '0';
signal mii_rx_dv : std_ulogic := '0';
signal mii_rxd : std_ulogic_vector(7 downto 0) := (others => '0');
signal gmii_gtx_clk : std_ulogic := '0';
signal user_clock : std_ulogic := '0';
-- Testbench signals
signal run : boolean := TRUE;
constant MAX_PACKETS_IN_TRANSACTION : integer := 10;
-- Data array length is a bit on the large side so we can send jumbo frames
-- When debugging problems with waveform viewers (or generally using iSim), try smaller values to lessen
-- the burden on the simulator. Note that not all test cases will run then.
type t_packet_data is array (0 to 10000) of t_ethernet_data;
--type t_packet_data is array (0 to 1050) of t_ethernet_data;
--type t_packet_data is array (0 to 70) of t_ethernet_data;
type t_packet_transaction is record
valid : boolean;
data : t_packet_data;
size : integer;
end record;
type t_packet_buffer is array (0 to MAX_PACKETS_IN_TRANSACTION - 1) of t_packet_transaction;
signal speed_override : t_ethernet_speed := SPEED_1000MBPS;
signal send_packet_req : boolean := FALSE;
signal send_packet_ack : boolean := FALSE;
signal send_corrupt_data : boolean := FALSE;
signal send_packet_buffer : t_packet_buffer;
signal receive_packet_req : boolean := FALSE;
signal receive_packet_ack : boolean := FALSE;
signal receive_packet_buffer : t_packet_buffer;
signal receive_packet_count_expected : integer := 0;
signal receive_ipg_duration_bits : integer;
signal test_mode : t_test_mode := TEST_LOOPBACK;
-- Timing definitions
constant clock_125_period : time := 8 ns;
constant clock_25_period : time := 40 ns;
constant clock_2_5_period : time := 400 ns;
constant mii_rx_setup : time := 2 ns;
constant mii_rx_hold : time := 0 ns;
constant mii_tx_setup : time := 2.5 ns;
-- Functions
impure function mii_rx_clk_period return time is
begin
case speed_override is
when SPEED_10MBPS =>
return clock_2_5_period;
when SPEED_100MBPS =>
return clock_25_period;
when others =>
return clock_125_period;
end case;
end function;
-- Compare two packet transactions
-- When respect_address is set, it is taken into account that the
-- source address of the received packet will be different and needs to
-- match the address of the MAC test instance. The second arguments must be
-- the received packet then.
function compare_packet_transactions(left, right : in t_packet_transaction; respect_address : boolean := FALSE) return boolean is
variable data_begin : integer := 0;
begin
if left.valid /= right.valid then
report "Transaction validity state mismatch" severity note;
return FALSE;
elsif left.valid = TRUE then
-- Both are valid
-- Check size
if left.size /= right.size then
report "Transaction size mismatch" severity note;
return FALSE;
end if;
-- Check data
if respect_address = TRUE then
-- Verify that the destination address is untouched
for i in 0 to MAC_ADDRESS_BYTES - 1 loop
if left.data(i) /= right.data(i) then
report "Transaction destination address mismatch at index " & integer'image(i) severity note;
return FALSE;
end if;
end loop;
-- Compare the source address with the constant
for i in 0 to MAC_ADDRESS_BYTES - 1 loop
if right.data(MAC_ADDRESS_BYTES + i) /= extract_byte(TEST_MAC_ADDRESS, i) then
report "Transaction source address mismatch at index " & integer'image(i) severity note;
return FALSE;
end if;
end loop;
-- Start normal verification after the addresses
data_begin := 2 * MAC_ADDRESS_BYTES;
end if;
-- Compare rest of data (or all if respect_address is FALSE)
for i in data_begin to left.size - 1 loop
if left.data(i) /= right.data(i) then
report "Transaction data mismatch at index " & integer'image(i) severity note;
return FALSE;
end if;
end loop;
-- All good
return TRUE;
else
-- Both are invalid, no further check necessary
-- Data does not matter
return TRUE;
end if;
end function;
function "="(left, right : in t_packet_transaction) return boolean is
begin
return compare_packet_transactions(left, right, FALSE);
end function;
-- Compare two packet transaction buffers
-- When respect_address is set, it is taken into account that the
-- source address of the received packets will be different and needs to
-- match the address of the MAC test instance. The second arguments must be
-- the received packets then.
function compare_packet_buffers(left, right : in t_packet_buffer; respect_address : boolean := FALSE) return boolean is
begin
for i in t_packet_buffer'range loop
-- Stop when both elements are invalid (end reached)
exit when (not left(i).valid) and (not right(i).valid);
-- Compare elements
if not compare_packet_transactions(left(i), right(i), respect_address) then
report "Mismatch in buffer element " & integer'image(i) severity note;
return FALSE;
end if;
end loop;
return TRUE;
end function;
function "="(left, right : in t_packet_buffer) return boolean is
begin
return compare_packet_buffers(left, right, FALSE);
end function;
-- "Known good" CRC32 function for comparison from chips example project
-- polynomial: (0 1 2 4 5 7 8 10 11 12 16 22 23 26 32)
-- data width: 8
-- convention: the first serial bit is D[0]
function NEXTCRC32_D8(DATA : std_ulogic_vector(7 downto 0);
CRC : std_ulogic_vector(31 downto 0)) return std_ulogic_vector is
variable D : std_ulogic_vector(7 downto 0);
variable C : std_ulogic_vector(31 downto 0);
variable NEWCRC : std_ulogic_vector(31 downto 0);
begin
D := DATA;
C := CRC;
NewCRC(0) := C(24) xor C(30) xor D(1) xor D(7);
NewCRC(1) := C(25) xor C(31) xor D(0) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(2) := C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(3) := C(27) xor D(4) xor C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(4) := C(28) xor D(3) xor C(27) xor D(4) xor C(26) xor D(5) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(5) := C(29) xor D(2) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25) xor C(31) xor D(0) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(6) := C(30) xor D(1) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(7) := C(31) xor D(0) xor C(29) xor D(2) xor C(27) xor D(4) xor C(26) xor D(5) xor C(24) xor D(7);
NewCRC(8) := C(0) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25) xor D(6) xor C(24) xor D(7);
NewCRC(9) := C(1) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26) xor D(5) xor C(25) xor D(6);
NewCRC(10) := C(2) xor C(29) xor D(2) xor C(27) xor D(4) xor C(26) xor D(5) xor C(24) xor D(7);
NewCRC(11) := C(3) xor C(28) xor D(3) xor C(27) xor D(4) xor C(25) xor D(6) xor C(24) xor D(7);
NewCRC(12) := C(4) xor C(29) xor D(2) xor C(28) xor D(3) xor C(26) xor D(5) xor C(25) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(13) := C(5) xor C(30) xor D(1) xor C(29) xor D(2) xor C(27) xor D(4) xor C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(14) := C(6) xor C(31) xor D(0) xor C(30) xor D(1) xor C(28) xor D(3) xor C(27) xor D(4) xor C(26) xor D(5);
NewCRC(15) := C(7) xor C(31) xor D(0) xor C(29) xor D(2) xor C(28) xor D(3) xor C(27) xor D(4);
NewCRC(16) := C(8) xor C(29) xor D(2) xor C(28) xor D(3) xor C(24) xor D(7);
NewCRC(17) := C(9) xor C(30) xor D(1) xor C(29) xor D(2) xor C(25) xor D(6);
NewCRC(18) := C(10) xor C(31) xor D(0) xor C(30) xor D(1) xor C(26) xor D(5);
NewCRC(19) := C(11) xor C(31) xor D(0) xor C(27) xor D(4);
NewCRC(20) := C(12) xor C(28) xor D(3);
NewCRC(21) := C(13) xor C(29) xor D(2);
NewCRC(22) := C(14) xor C(24) xor D(7);
NewCRC(23) := C(15) xor C(25) xor D(6) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(24) := C(16) xor C(26) xor D(5) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(25) := C(17) xor C(27) xor D(4) xor C(26) xor D(5);
NewCRC(26) := C(18) xor C(28) xor D(3) xor C(27) xor D(4) xor C(24) xor C(30) xor D(1) xor D(7);
NewCRC(27) := C(19) xor C(29) xor D(2) xor C(28) xor D(3) xor C(25) xor C(31) xor D(0) xor D(6);
NewCRC(28) := C(20) xor C(30) xor D(1) xor C(29) xor D(2) xor C(26) xor D(5);
NewCRC(29) := C(21) xor C(31) xor D(0) xor C(30) xor D(1) xor C(27) xor D(4);
NewCRC(30) := C(22) xor C(31) xor D(0) xor C(28) xor D(3);
NewCRC(31) := C(23) xor C(29) xor D(2);
return NEWCRC;
end function;
-- Copy MAC address (or similar) from a concatenated vector into byte units
procedure copy_to_buffer_packet(source : in std_ulogic_vector; signal destination : inout t_packet_buffer; transaction : in integer) is
begin
for i in 0 to source'high / 8 loop
destination(transaction).data(i) <= extract_byte(source, i);
end loop;
end procedure;
-- Copy MAC address (or similar) from byte units into a concatenated vector
procedure copy_from_buffer_packet(source : in t_packet_buffer; transaction : in integer; destination : inout std_ulogic_vector) is
begin
for i in 0 to destination'high / 8 loop
destination(((i + 1) * 8) - 1 downto (i * 8)) := source(transaction).data(i);
end loop;
end procedure;
begin
-- Be aware of simulation mismatch because of delta-delay issues here
user_clock <= clock_125;
-- Instantiate component
ethernet_mac_inst : test_instance
port map(
clock_125_i => clock_125,
user_clock_i => user_clock,
reset_i => reset,
mii_tx_clk_i => mii_tx_clk,
mii_tx_er_o => mii_tx_er,
mii_tx_en_o => mii_tx_en,
mii_txd_o => mii_txd,
mii_rx_clk_i => mii_rx_clk,
mii_rx_er_i => mii_rx_er,
mii_rx_dv_i => mii_rx_dv,
mii_rxd_i => mii_rxd,
gmii_gtx_clk_o => gmii_gtx_clk,
rgmii_tx_ctl_o => open,
rgmii_rx_ctl_i => '0',
speed_override_i => speed_override,
test_mode_i => test_mode
);
-- Generate clocks
clock_125_process : process
begin
if not run then
wait until run;
end if;
clock_125 <= not clock_125;
wait for clock_125_period / 2;
end process;
mii_tx_clk_process : process
begin
if not run then
wait until run;
end if;
case speed_override is
when SPEED_10MBPS =>
mii_tx_clk <= not mii_tx_clk;
wait for clock_2_5_period / 2;
when SPEED_100MBPS =>
mii_tx_clk <= not mii_tx_clk;
wait for clock_25_period / 2;
when others =>
-- MII TX_CLK is inactive in 1 Gbps mode
wait until ((speed_override = SPEED_10MBPS) or (speed_override = SPEED_100MBPS));
end case;
end process;
-- Process for stimulating the MII RX interface
packet_send_process : process is
procedure mii_rx_cycle(data : in std_ulogic_vector(7 downto 0) := "XXXXXXXX";
dv : in std_ulogic := '1';
er : in std_ulogic := '0') is
begin
if TEST_MII_SETUPHOLD then
-- Setup/hold time simulation is only useful in post-synthesis simulation
mii_rx_clk <= '0';
wait for (mii_rx_clk_period / 2) - mii_rx_setup;
mii_rx_dv <= dv;
mii_rx_er <= er;
mii_rxd <= data;
wait for mii_rx_setup;
mii_rx_clk <= '1';
wait for mii_rx_hold;
mii_rxd <= (others => 'X');
mii_rx_dv <= 'X';
mii_rx_er <= 'X';
wait for (mii_rx_clk_period / 2) - mii_rx_hold;
else
mii_rx_clk <= '0';
mii_rx_dv <= dv;
mii_rx_er <= er;
mii_rxd <= data;
wait for mii_rx_clk_period / 2;
mii_rx_clk <= '1';
wait for mii_rx_clk_period / 2;
end if;
end procedure;
procedure mii_rx_put(
data : in std_ulogic_vector(7 downto 0) := "XXXXXXXX";
dv : in std_ulogic := '1';
er : in std_ulogic := '0') is
begin
if VERBOSE and data /= "XXXXXXXX" then
report "Send: " & integer'image(to_integer(unsigned(data)));
end if;
if speed_override = SPEED_1000MBPS then
mii_rx_cycle(data, dv, er);
else
mii_rx_cycle("XXXX" & data(3 downto 0), dv, er);
mii_rx_cycle("XXXX" & data(7 downto 4), dv, er);
end if;
end procedure;
procedure mii_rx_toggle is
begin
mii_rx_put(dv => '0', er => '0', data => open);
end procedure;
variable fcs : t_crc32;
begin
while not send_packet_req loop
mii_rx_toggle;
if not run then
wait until run;
end if;
end loop;
for packet_i in send_packet_buffer'range loop
-- Stop at first invalid packet
exit when not send_packet_buffer(packet_i).valid;
-- Preamble
for i in 0 to 3 loop
mii_rx_put(PREAMBLE_DATA);
end loop;
-- SFD
mii_rx_put(START_FRAME_DELIMITER_DATA);
-- Data
fcs := (others => '1');
for i in 0 to send_packet_buffer(packet_i).size - 1 loop
if send_corrupt_data then
mii_rx_put(send_packet_buffer(packet_i).data(i) and "11011111");
else
mii_rx_put(send_packet_buffer(packet_i).data(i));
end if;
fcs := NEXTCRC32_D8(send_packet_buffer(packet_i).data(i), fcs);
end loop;
-- FCS
mii_rx_put(fcs_output_byte(fcs, 0));
mii_rx_put(fcs_output_byte(fcs, 1));
mii_rx_put(fcs_output_byte(fcs, 2));
mii_rx_put(fcs_output_byte(fcs, 3));
-- IFG
for i in 0 to 11 loop
mii_rx_toggle;
end loop;
end loop;
send_packet_ack <= TRUE;
--report "Done sending" severity note;
while send_packet_req loop
mii_rx_toggle;
end loop;
send_packet_ack <= FALSE;
end process;
-- Process for reading the MII TX interface into a packet buffer
packet_receive_process : process is
variable current_byte : integer;
variable data : t_ethernet_data;
variable fcs : t_crc32;
variable ipg_count_bits : integer;
procedure wait_clk is
begin
case speed_override is
when SPEED_10MBPS | SPEED_100MBPS =>
wait until rising_edge(mii_tx_clk);
when others =>
wait until rising_edge(gmii_gtx_clk);
end case;
assert mii_tx_er = '0' report "MII transmission error flag is set" severity failure;
if TEST_MII_SETUPHOLD then
assert mii_tx_en'last_event > mii_tx_setup report "Setup time violated on TX_EN" severity failure;
assert mii_txd'last_event > mii_tx_setup report "Setup time violated on TXD" severity failure;
end if;
end procedure;
procedure read_byte(output_byte : inout t_ethernet_data) is
variable tx_was_enabled : std_ulogic;
begin
tx_was_enabled := mii_tx_en;
case speed_override is
when SPEED_10MBPS | SPEED_100MBPS =>
output_byte(3 downto 0) := mii_txd(3 downto 0);
wait_clk;
assert mii_tx_en = '1' report "Frame transmission ended between byte boundaries" severity failure;
output_byte(7 downto 4) := mii_txd(3 downto 0);
wait_clk;
when others =>
output_byte := mii_txd;
wait_clk;
end case;
if tx_was_enabled = '1' and VERBOSE then
report "Rcv data: " & integer'image(to_integer(unsigned(output_byte)));
end if;
end procedure;
begin
wait until receive_packet_req;
--report "Start receiver" severity note;
for i in receive_packet_buffer'range loop
receive_packet_buffer(i).valid <= FALSE;
end loop;
packet_loop : for current_packet_i in 0 to receive_packet_count_expected - 1 loop
current_byte := 0;
ipg_count_bits := 0;
-- Wait for beginning of frame
loop
-- Assuming tx_en is deasserted now, this is already the first cycle of the IPG
case speed_override is
when SPEED_10MBPS | SPEED_100MBPS =>
ipg_count_bits := ipg_count_bits + 4;
when others =>
ipg_count_bits := ipg_count_bits + 8;
end case;
wait_clk;
-- Allow receive cancellation
exit packet_loop when not receive_packet_req;
exit when mii_tx_en = '1';
end loop;
-- Measure IPG duration between last two packets when multiple packets are received
if current_packet_i /= 0 then
assert ipg_count_bits >= INTERPACKET_GAP_BYTES * 8 report "Inter-packet gap too short" severity failure;
receive_ipg_duration_bits <= ipg_count_bits;
end if;
--report "Start packet reception" severity note;
for i in 0 to 6 loop
read_byte(data);
assert data = PREAMBLE_DATA and mii_tx_en = '1' report "Packet did not start with correct preamble data" severity failure;
end loop;
read_byte(data);
assert data = START_FRAME_DELIMITER_DATA and mii_tx_en = '1' report "Packet did not start with correct preamble data or start frame delimiter" severity failure;
fcs := (others => '1');
loop
read_byte(data);
receive_packet_buffer(current_packet_i).data(current_byte) <= data;
current_byte := current_byte + 1;
assert current_byte <= t_packet_data'high report "Transmitted packet is too long (size now " & integer'image(current_byte) & ")" severity failure;
fcs := NEXTCRC32_D8(data, fcs);
-- Exit after frame end
exit when mii_tx_en = '0';
end loop;
-- Subtract FCS size
current_byte := current_byte - CRC32_BYTES;
if VERBOSE then
report "Rcv size: " & integer'image(current_byte);
end if;
assert current_byte >= MIN_FRAME_DATA_BYTES report "Transmitted packet is too short" severity failure;
-- Check FCS
assert fcs = CRC32_POSTINVERT_MAGIC report "FCS of transmitted packet did not match contents" severity failure;
receive_packet_buffer(current_packet_i).size <= current_byte;
receive_packet_buffer(current_packet_i).valid <= TRUE;
--report "Received packet index " & integer'image(current_packet_i) & " size " & integer'image(current_byte) severity note;
--assert current_packet_i < receive_packet_buffer'high report "Too many packets were transmitted";
end loop;
if receive_packet_req then
receive_packet_ack <= TRUE;
wait until not receive_packet_req;
receive_packet_ack <= FALSE;
end if;
--report "Stop receiver" severity note;
end process;
-- Main test process
test_process : process is
-- Activate the sender and wait for it to complete
procedure do_send is
begin
send_packet_req <= TRUE;
wait until send_packet_ack;
send_packet_req <= FALSE;
wait until not send_packet_ack;
end procedure;
-- Activate the receiver and wait for it to complete
procedure do_receive is
begin
receive_packet_req <= TRUE;
wait until receive_packet_ack;
receive_packet_req <= FALSE;
wait until not receive_packet_ack;
end procedure;
-- Activate the sender an receiver and wait for both to complete
procedure do_send_receive is
begin
send_packet_req <= TRUE;
receive_packet_req <= TRUE;
wait until send_packet_ack and receive_packet_ack;
send_packet_req <= FALSE;
receive_packet_req <= FALSE;
wait until (not send_packet_ack) and (not receive_packet_ack);
end procedure;
-- Send a packet, receive the mirror packet and check for equality
procedure test_one_size(size : in integer) is
begin
report "Check single frame loopback size " & integer'image(size) severity note;
send_packet_buffer(0).size <= size;
do_send_receive;
assert compare_packet_buffers(send_packet_buffer, receive_packet_buffer, TRUE) report "Packet loopback resulted in different packets" severity failure;
end procedure;
-- Send a packet, check that nothing comes back
procedure test_send_broken is
variable send_corrupt_data_backup : boolean;
variable destination_address_backup : t_mac_address;
begin
-- Enable receiver
receive_packet_req <= TRUE;
do_send;
-- Give it some time to send the packet back if it went through
wait for mii_rx_clk_period * 3000;
-- Nothing should have been received
assert not receive_packet_buffer(0).valid report "Invalid packet was answered by the MAC" severity failure;
-- Now send an OK packet to check that it hasn't deadlocked somewhere
send_corrupt_data_backup := send_corrupt_data;
send_corrupt_data <= FALSE;
copy_from_buffer_packet(send_packet_buffer, 0, destination_address_backup);
-- Make sure the packet doesn't get dropped because of a non-matching address
copy_to_buffer_packet(TEST_MAC_ADDRESS, send_packet_buffer, 0);
test_one_size(100);
send_corrupt_data <= send_corrupt_data_backup;
copy_to_buffer_packet(destination_address_backup, send_packet_buffer, 0);
end procedure;
procedure test_broken_size(size : in integer) is
begin
report "Check single broken frame is not looped back size " & integer'image(size) severity note;
send_packet_buffer(0).size <= size;
test_send_broken;
end procedure;
procedure set_test_mode(new_test_mode : in t_test_mode) is
begin
wait until falling_edge(user_clock);
test_mode <= new_test_mode;
end procedure;
procedure test_one_speed is
variable verify_packet_buffer : t_packet_buffer;
begin
set_test_mode(TEST_LOOPBACK);
send_packet_buffer(0).valid <= TRUE;
send_packet_buffer(1).valid <= FALSE;
receive_packet_count_expected <= 1;
if TRUE then
-- Tests for packets that should pass
if TEST_THOROUGH then
for size in MIN_FRAME_DATA_BYTES to MAX_FRAME_DATA_BYTES loop
test_one_size(size);
end loop;
else
-- Test just a few sizes
test_one_size(MIN_FRAME_DATA_BYTES);
test_one_size(MIN_FRAME_DATA_BYTES + 1);
test_one_size(1000);
test_one_size(MAX_FRAME_DATA_BYTES - 1);
test_one_size(MAX_FRAME_DATA_BYTES);
end if;
-- Test broadcast MAC address instead of unicast
copy_to_buffer_packet(BROADCAST_MAC_ADDRESS, send_packet_buffer, 0);
report "Check broadcast MAC destination address:" severity note;
test_one_size(100);
-- Test multicast address
copy_to_buffer_packet(TEST_MAC_ADDRESS, send_packet_buffer, 0);
-- Set group address bit
send_packet_buffer(0).data(0)(0) <= '1';
-- Make sure the rest is different from the test MAC address
send_packet_buffer(0).data(1) <= not send_packet_buffer(0).data(1);
report "Check multicast MAC destination address:" severity note;
test_one_size(100);
-- Copy entity address back for further tests
copy_to_buffer_packet(TEST_MAC_ADDRESS, send_packet_buffer, 0);
end if;
-- Tests for packets that should get dropped
if TRUE then
if TEST_THOROUGH then
-- Test runt frames
for size in 1 to MIN_FRAME_DATA_BYTES - 1 loop
test_broken_size(size);
end loop;
-- Test jumbo frames
for size in MAX_FRAME_DATA_BYTES + 1 to MAX_FRAME_DATA_BYTES + 10 loop
test_broken_size(size);
end loop;
else
-- Test runt frames
test_broken_size(1);
test_broken_size(2);
test_broken_size(3);
test_broken_size(MIN_FRAME_DATA_BYTES - 2);
test_broken_size(MIN_FRAME_DATA_BYTES - 1);
-- Test jumbo frames
test_broken_size(MAX_FRAME_DATA_BYTES + 1);
test_broken_size(MAX_FRAME_DATA_BYTES + 2);
end if;
-- Test size that overflows 11 bits of size information in FIFOs
test_broken_size(2 ** 11 + 70);
-- Test size that is greater than total RX buffer size
test_broken_size(9999);
-- Test different destination MAC address
for b in 0 to MAC_ADDRESS_BYTES - 1 loop
-- Make sure byte position b does not match
send_packet_buffer(0).data(b)(5) <= not send_packet_buffer(0).data(b)(5);
report "Check MAC destination address mismatch at position " & integer'image(b) & ":" severity note;
test_broken_size(100);
-- Restore original address
copy_to_buffer_packet(TEST_MAC_ADDRESS, send_packet_buffer, 0);
end loop;
-- Test wrong FCS
report "Check single broken frame is not looped back size 100 bad FCS" severity note;
send_packet_buffer(0).size <= 100;
send_corrupt_data <= TRUE;
test_send_broken;
send_corrupt_data <= FALSE;
-- Disable receiver
receive_packet_req <= FALSE;
wait for mii_rx_clk_period * 2;
end if;
if TRUE then
-- Check RX FIFO overflow
for i in 0 to 7 loop
send_packet_buffer(i).valid <= TRUE;
send_packet_buffer(i).size <= 1024;
end loop;
-- Suspend FIFO reader
set_test_mode(TEST_NOTHING);
report "Check RX FIFO overrun: Fill FIFO" severity note;
-- Fill FIFO
do_send;
-- Enable receiver
receive_packet_req <= TRUE;
-- One more than really expected (3)
receive_packet_count_expected <= 4;
-- Resume FIFO reader
set_test_mode(TEST_LOOPBACK);
report "Check RX FIFO overrun: Receive mirrored packets" severity note;
-- Wait for 3rd packet received
wait until receive_packet_buffer(2).valid;
-- Give it some more time to potentially receive another packet
wait for mii_rx_clk_period * 3000;
assert not receive_packet_ack report "Too many packets were received" severity failure;
-- Disable receiver
receive_packet_req <= FALSE;
wait for mii_rx_clk_period * 2;
-- Check IPG duration
report "IPG duration: " & integer'image(receive_ipg_duration_bits) & " bits" severity note;
assert receive_ipg_duration_bits < 20 * 8 report "Received interpacket gap is too long" severity failure;
-- Validate packets that went through
for i in 0 to 2 loop
assert compare_packet_transactions(send_packet_buffer(i), receive_packet_buffer(i), TRUE) report "Packet loopback resulted in different packets" severity failure;
end loop;
-- Check that normal reception is now working again
receive_packet_count_expected <= 1;
send_packet_buffer(1).valid <= FALSE;
test_one_size(100);
end if;
if TRUE then
-- Check TX padding
-- Fill verification data initially
for packet_i in verify_packet_buffer'range loop
verify_packet_buffer(packet_i).valid := FALSE;
end loop;
verify_packet_buffer(0).valid := TRUE;
verify_packet_buffer(0).size := MIN_FRAME_DATA_BYTES;
-- Start transmission
set_test_mode(TEST_TX_PADDING);
for size in 1 to 59 loop
report "Check TX padding size " & integer'image(size) severity note;
-- Fill verification data
for i in 0 to size - 1 loop
verify_packet_buffer(0).data(i) := t_ethernet_data(to_unsigned(i + 1, 8));
end loop;
for i in size to MIN_FRAME_DATA_BYTES - 1 loop
verify_packet_buffer(0).data(i) := PADDING_DATA;
end loop;
-- Receive frame
do_receive;
-- Verify contents
-- Do not check the MAC address: Auto-insertion does not take place in this test
assert compare_packet_buffers(verify_packet_buffer, receive_packet_buffer, FALSE) report "Padded TX message does not have expected size and content" severity failure;
end loop;
-- Stop TX padding test to prevent unwanted packets being sent after a speed change
set_test_mode(TEST_NOTHING);
end if;
-- Check for correct FIFO function when it is filled up exactly to the last byte?
end procedure;
begin
report "MAC functional check starting" severity note;
if TEST_MII_SETUPHOLD then
report "Testing MII setup/hold times" severity note;
end if;
reset <= '1';
speed_override <= SPEED_1000MBPS;
wait for 100 ns;
reset <= '0';
wait for 10 us;
for packet_i in send_packet_buffer'range loop
-- Destination address
copy_to_buffer_packet(TEST_MAC_ADDRESS, send_packet_buffer, packet_i);
-- Source address
for i in MAC_ADDRESS_BYTES to 2 * MAC_ADDRESS_BYTES - 1 loop
-- Destination and source address
send_packet_buffer(packet_i).data(i) <= x"FF";
end loop;
for i in 12 to t_packet_data'high loop
send_packet_buffer(packet_i).data(i) <= std_ulogic_vector(to_unsigned((i + 7 + packet_i) mod 256, 8));
end loop;
end loop;
report "Testing speed: 1 Gbps" severity note;
test_one_speed;
-- Transition on user_clock falling because speed_override
-- must be synchronous to miim_clock (which is equal to user_clock here)
wait until falling_edge(user_clock);
speed_override <= SPEED_100MBPS;
wait for 10 us;
report "Testing speed: 100 Mbps" severity note;
test_one_speed;
wait until falling_edge(user_clock);
speed_override <= SPEED_10MBPS;
wait for 10 us;
report "Testing speed: 10 Mbps" severity note;
test_one_speed;
report "MAC functional check ended OK" severity note;
-- Stop simulation
run <= FALSE;
wait;
end process;
-- Detect when the MAC is not answering
watchdog : process is
begin
wait for 1 ms;
if not run then
wait until run;
end if;
if receive_packet_req and receive_packet_req'last_event > 20 ms then
report "Expected number of frames could not be received within specified timeframe" severity failure;
end if;
end process;
end architecture;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_m_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 05:50:09 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../generic.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_m_e-rtl-a.vhd,v 1.3 2006/06/26 07:42:18 wig Exp $
-- $Date: 2006/06/26 07:42:18 $
-- $Log: inst_m_e-rtl-a.vhd,v $
-- Revision 1.3 2006/06/26 07:42:18 wig
-- Updated io, generic and mde_tests testcases
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_m_e
--
architecture rtl of inst_m_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
-------------------------------------------------------------------------------
--
-- Synthesizable model of TI's TMS9918A, TMS9928A, TMS9929A.
--
-- $Id: vdp18_pattern.vhd,v 1.8 2006/06/18 10:47:06 arnim Exp $
--
-- Pattern Generation Controller
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2006, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.vdp18_pack.opmode_t;
use work.vdp18_pack.access_t;
use work.vdp18_pack.hv_t;
entity vdp18_pattern is
port (
clock_i : in std_logic;
clk_en_5m37_i : in boolean;
clk_en_acc_i : in boolean;
reset_i : in boolean;
opmode_i : in opmode_t;
access_type_i : in access_t;
num_line_i : in hv_t;
vram_d_i : in std_logic_vector(0 to 7);
vert_inc_i : in boolean;
vsync_n_i : in std_logic;
reg_col1_i : in std_logic_vector(0 to 3);
reg_col0_i : in std_logic_vector(0 to 3);
pat_table_o : out std_logic_vector(0 to 9);
pat_name_o : out std_logic_vector(0 to 7);
pat_col_o : out std_logic_vector(0 to 3)
);
end vdp18_pattern;
library ieee;
use ieee.numeric_std.all;
use work.vdp18_pack.all;
architecture rtl of vdp18_pattern is
signal pat_cnt_q : unsigned(0 to 9);
signal pat_name_q,
pat_tmp_q,
pat_shift_q,
pat_col_q : std_logic_vector(0 to 7);
begin
-----------------------------------------------------------------------------
-- Process seq
--
-- Purpose:
-- Implements the sequential elements:
-- * pattern shift register
-- * pattern color register
-- * pattern counter
--
seq: process (clock_i, reset_i)
begin
if reset_i then
pat_cnt_q <= (others => '0');
pat_name_q <= (others => '0');
pat_tmp_q <= (others => '0');
pat_shift_q <= (others => '0');
pat_col_q <= (others => '0');
elsif clock_i'event and clock_i = '1' then
if clk_en_5m37_i then
-- shift pattern with every pixel clock
pat_shift_q(0 to 6) <= pat_shift_q(1 to 7);
end if;
if clk_en_acc_i then
-- determine register update based on current access type -------------
case access_type_i is
when AC_PNT =>
-- store pattern name
pat_name_q <= vram_d_i;
-- increment pattern counter
pat_cnt_q <= pat_cnt_q + 1;
when AC_PCT =>
-- store pattern color in temporary register
pat_tmp_q <= vram_d_i;
when AC_PGT =>
if opmode_i = OPMODE_MULTIC then
-- set shift register to constant value
-- this value generates 4 bits of color1
-- followed by 4 bits of color0
pat_shift_q <= "11110000";
-- set pattern color from pattern generator memory
pat_col_q <= vram_d_i;
else
-- all other modes:
-- store pattern line in shift register
pat_shift_q <= vram_d_i;
-- move pattern color from temporary register to color register
pat_col_q <= pat_tmp_q;
end if;
when others =>
null;
end case;
end if;
if vert_inc_i then
-- redo patterns of if there are more lines inside this pattern
if num_line_i(0) = '0' then
case opmode_i is
when OPMODE_TEXTM =>
if num_line_i(6 to 8) /= "111" then
pat_cnt_q <= pat_cnt_q - 40;
end if;
when OPMODE_GRAPH1 |
OPMODE_GRAPH2 |
OPMODE_MULTIC =>
if num_line_i(6 to 8) /= "111" then
pat_cnt_q <= pat_cnt_q - 32;
end if;
end case;
end if;
end if;
if vsync_n_i = '0' then
-- reset pattern counter at end of active display area
pat_cnt_q <= (others => '0');
end if;
end if;
end process seq;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Process col_gen
--
-- Purpose:
-- Generates the color of the current pattern pixel.
--
col_gen: process (opmode_i,
pat_shift_q,
pat_col_q,
reg_col1_i,
reg_col0_i)
variable pix_v : std_logic;
begin
-- default assignment
pat_col_o <= "0000";
pix_v := pat_shift_q(0);
case opmode_i is
-- Text Mode ------------------------------------------------------------
when OPMODE_TEXTM =>
if pix_v = '1' then
pat_col_o <= reg_col1_i;
else
pat_col_o <= reg_col0_i;
end if;
-- Graphics I, II and Multicolor Mode -----------------------------------
when OPMODE_GRAPH1 |
OPMODE_GRAPH2 |
OPMODE_MULTIC =>
if pix_v = '1' then
pat_col_o <= pat_col_q(0 to 3);
else
pat_col_o <= pat_col_q(4 to 7);
end if;
when others =>
null;
end case;
end process col_gen;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output Mapping
-----------------------------------------------------------------------------
pat_table_o <= std_logic_vector(pat_cnt_q);
pat_name_o <= pat_name_q;
end rtl;
|
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-08 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_04500_good.vhd
-- File Creation date : 2015-04-08
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Clock reassignment: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
-- This example is compliant with the Handbook version 1.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.pkg_HBK.all;
--CODE
entity STD_04500_good is
port (
i_Clock : in std_logic; -- Clock signal
i_Reset_n : in std_logic; -- Reset signal
-- D Flip-flop 3 stages pipeline
-- D Flip-Flop A
i_DA : in std_logic; -- Input signal
o_QA : out std_logic; -- Output signal
-- D Flip-flop B
o_QB : out std_logic; -- Output signal
-- D Flip-Flop C
o_QC : out std_logic -- Output signal
);
end STD_04500_good;
architecture Behavioral of STD_04500_good is
signal QA : std_logic;
signal QB : std_logic;
begin
-- First Flip-Flop
DFF1 : DFlipFlop
port map (
i_Clock => i_Clock,
i_Reset_n => i_Reset_n,
i_D => i_DA,
o_Q => QA,
o_Q_n => open
);
-- Second Flip-Flop
DFF2 : DFlipFlop
port map (
i_Clock => i_Clock,
i_Reset_n => i_Reset_n,
i_D => QA,
o_Q => QB,
o_Q_n => open
);
-- Third Flip-Flop
DFF3 : DFlipFlop
port map (
i_Clock => i_Clock,
i_Reset_n => i_Reset_n,
i_D => QB,
o_Q => o_QC,
o_Q_n => open
);
o_QA <= QA;
o_QB <= QB;
end Behavioral;
--CODE
|
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.7
-- \ \ Application : xaw2vhdl
-- / / Filename : PixelClockGenerator.vhd
-- /___/ /\ Timestamp : 01/02/2014 12:18:56
-- \ \ / \
-- \___\/\___\
--
--Command: xaw2vhdl-intstyle /home/nick/Jarvis/ipcore_dir/PixelClockGenerator.xaw -st PixelClockGenerator.vhd
--Design Name: PixelClockGenerator
--Device: xc3s250e-4vq100
--
-- Module PixelClockGenerator
-- Generated by Xilinx Architecture Wizard
-- Written for synthesis tool: XST
-- Period Jitter (unit interval) for block DCM_SP_INST = 0.06 UI
-- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 2.43 ns
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity PixelClockGenerator is
port ( CLKIN_IN : in std_logic;
RST_IN : in std_logic;
CLKFX_OUT : out std_logic;
CLKIN_IBUFG_OUT : out std_logic;
CLK0_OUT : out std_logic;
LOCKED_OUT : out std_logic);
end PixelClockGenerator;
architecture BEHAVIORAL of PixelClockGenerator is
signal CLKFB_IN : std_logic;
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal CLK0_BUF : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
CLK0_OUT <= CLKFB_IN;
CLKFX_BUFG_INST : BUFG
port map (I=>CLKFX_BUF,
O=>CLKFX_OUT);
CLKIN_IBUFG_INST : IBUFG
port map (I=>CLKIN_IN,
O=>CLKIN_IBUFG);
CLK0_BUFG_INST : BUFG
port map (I=>CLK0_BUF,
O=>CLKFB_IN);
DCM_SP_INST : DCM_SP
generic map( CLK_FEEDBACK => "1X",
CLKDV_DIVIDE => 2.0,
CLKFX_DIVIDE => 32,
CLKFX_MULTIPLY => 25,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 31.250,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map (CLKFB=>CLKFB_IN,
CLKIN=>CLKIN_IBUFG,
DSSEN=>GND_BIT,
PSCLK=>GND_BIT,
PSEN=>GND_BIT,
PSINCDEC=>GND_BIT,
RST=>RST_IN,
CLKDV=>open,
CLKFX=>CLKFX_BUF,
CLKFX180=>open,
CLK0=>CLK0_BUF,
CLK2X=>open,
CLK2X180=>open,
CLK90=>open,
CLK180=>open,
CLK270=>open,
LOCKED=>LOCKED_OUT,
PSDONE=>open,
STATUS=>open);
end BEHAVIORAL;
|
architecture RTL of FIFO is
begin
IF_LABEL : if a = '1' generate
signal signal1 : std_logic;
constant con1 : std_logic;
shared variable var1 : std_logic;
alias a is name;
alias a : subtype_indication is name;
begin
elsif b = '0' generate
signal sig1 : std_logic;
constant constant1 : std_logic;
shared variable var1 : std_logic;
alias a is name;
alias a : subtype_indication is name;
begin
else generate
signal sig1 : std_logic;
constant con1 : std_logic;
shared variable vars1 : std_logic;
alias a is name;
alias a : subtype_indication is name;
begin
end generate;
-- Violations below
IF_LABEL : if a = '1' generate
signal signal1 : std_logic;
constant con1 : std_logic;
shared variable var1 : std_logic;
alias a is name;
alias a : subtype_indication is name;
begin
elsif b = '0' generate
signal sig1 : std_logic;
constant constant1 : std_logic;
shared variable var1 : std_logic;
alias a is name;
alias a : subtype_indication is name;
begin
else generate
signal sig1 : std_logic;
constant con1 : std_logic;
shared variable vars1 : std_logic;
alias a is name;
alias a : subtype_indication is name;
begin
end generate;
end;
--- Test nested generates
architecture nested of fifo is begin
g_0 : if true generate
g_1 : if true generate
signal sig0 : bit;
signal sig00 : bit;
begin end generate g_1;
elsif true generate
g_2a : if true generate
g_2 : if true generate
signal sig0 : bit;
signal sig00 : bit;
begin end generate g_2;
end generate g_2a;
elsif true generate
g_3 : if true generate
signal sig0 : bit;
signal sig00 : bit;
begin
G_X : if true generate
end generate G_X;
end generate g_3;
else generate
g_4a : if true generate
g_4 : if true generate
signal sig0 : bit;
signal sig00 : bit;
begin end generate g_4;
end generate g_4a;
end generate g_0;
end architecture fifo;
|
-- megafunction wizard: %LPM_CONSTANT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_CONSTANT
-- ============================================================
-- File Name: lpm_constant0.vhd
-- Megafunction Name(s):
-- LPM_CONSTANT
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 259 01/25/2012 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_constant0 IS
PORT
(
result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END lpm_constant0;
ARCHITECTURE SYN OF lpm_constant0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT lpm_constant
GENERIC (
lpm_cvalue : NATURAL;
lpm_hint : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(7 DOWNTO 0);
LPM_CONSTANT_component : LPM_CONSTANT
GENERIC MAP (
lpm_cvalue => 228,
lpm_hint => "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=VAL",
lpm_type => "LPM_CONSTANT",
lpm_width => 8
)
PORT MAP (
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
-- Retrieval info: PRIVATE: JTAG_ID STRING "VAL"
-- Retrieval info: PRIVATE: Radix NUMERIC "2"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: Value NUMERIC "228"
-- Retrieval info: PRIVATE: nBit NUMERIC "8"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "228"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=VAL"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
-- Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL "result[7..0]"
-- Retrieval info: CONNECT: result 0 0 8 0 @result 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
-- megafunction wizard: %LPM_CONSTANT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_CONSTANT
-- ============================================================
-- File Name: lpm_constant0.vhd
-- Megafunction Name(s):
-- LPM_CONSTANT
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 259 01/25/2012 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_constant0 IS
PORT
(
result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END lpm_constant0;
ARCHITECTURE SYN OF lpm_constant0 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
COMPONENT lpm_constant
GENERIC (
lpm_cvalue : NATURAL;
lpm_hint : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
result : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(7 DOWNTO 0);
LPM_CONSTANT_component : LPM_CONSTANT
GENERIC MAP (
lpm_cvalue => 228,
lpm_hint => "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=VAL",
lpm_type => "LPM_CONSTANT",
lpm_width => 8
)
PORT MAP (
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
-- Retrieval info: PRIVATE: JTAG_ID STRING "VAL"
-- Retrieval info: PRIVATE: Radix NUMERIC "2"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: Value NUMERIC "228"
-- Retrieval info: PRIVATE: nBit NUMERIC "8"
-- Retrieval info: PRIVATE: new_diagram STRING "1"
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "228"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=VAL"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
-- Retrieval info: USED_PORT: result 0 0 8 0 OUTPUT NODEFVAL "result[7..0]"
-- Retrieval info: CONNECT: result 0 0 8 0 @result 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_constant0_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
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`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 55952)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 55952)
`protect data_block
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|
`protect begin_protected
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect key_block
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`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 55952)
`protect data_block
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`protect end_protected
|
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
GEN_1_G => 3,
GEN_2_G => 4,
GEN_3_G => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
-- Violations below
U_INST1 : INST1
generic map (
GEN_1_W => 3,
GEN_2 => 4,
GEN_3_WR => 5
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
end architecture ARCH;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: dsu
-- File: dsu.vhd
-- Author: Jiri Gaisler, Edvin Catovic - Gaisler Research
-- Description: Combined LEON3 debug support and AHB trace unit
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.leon3.all;
library techmap;
use techmap.gencomp.all;
entity dsu3 is
generic (
hindex : integer := 0;
haddr : integer := 16#900#;
hmask : integer := 16#f00#;
ncpu : integer := 1;
tbits : integer := 30; -- timer bits (instruction trace time tag)
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 0;
testen : integer := 0;
bwidth : integer := 32;
ahbpf : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
dbgi : in l3_debug_out_vector(0 to NCPU-1);
dbgo : out l3_debug_in_vector(0 to NCPU-1);
dsui : in dsu_in_type;
dsuo : out dsu_out_type
);
end;
architecture rtl of dsu3 is
signal gnd, vcc : std_ulogic;
begin
gnd <= '0'; vcc <= '1';
x0 : dsu3x generic map (hindex, haddr, hmask, ncpu, tbits, tech, irq, kbytes, 0, testen, bwidth, ahbpf)
port map (rst, gnd, clk, ahbmi, ahbsi, ahbso, ahbsi, dbgi, dbgo, dsui, dsuo, vcc
);
end;
|
--!
--! @file: synchronous_counter.vhd
--! @brief: synchronous counter cell
--! @author: Antonio Gutierrez
--! @date: 2013-11-27
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
--------------------------------------
entity sync_counter is
--generic declarations
port (
a, b, clk: in std_logic;
andq, q: out std_logic);
end entity sync_counter;
--------------------------------------
architecture circuit of sync_counter is
signal temp: std_logic;
begin
temp <= a and b;
ff: process (clk)
variable q_ff: std_logic;
begin
if (clk'event and clk = '1') then
q_ff := q_ff xor temp;
end if;
end process ff;
q <= q_ff;
andq <= temp;
end architecture circuit;
--------------------------------------
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grpci2
-- File: grpci2.vhd
-- Author: Nils-Johan Wessman - Aeroflex Gaisler
-- Description: PCI master and target interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use grlib.dftlib.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.pci.all;
use work.pcilib2.all;
entity grpci2 is
generic (
memtech : integer := DEFMEMTECH;
tbmemtech : integer := DEFMEMTECH; -- For trace buffers
oepol : integer := 0;
hmindex : integer := 0;
hdmindex : integer := 0;
hsindex : integer := 0;
haddr : integer := 0;
hmask : integer := 0;
ioaddr : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
irq : integer := 0;
irqmode : integer range 0 to 3 := 0;
master : integer range 0 to 1 := 1;
target : integer range 0 to 1 := 1;
dma : integer range 0 to 1 := 1;
tracebuffer : integer range 0 to 16384 := 0;
confspace : integer range 0 to 1 := 1;
vendorid : integer := 16#0000#;
deviceid : integer := 16#0000#;
classcode : integer := 16#000000#;
revisionid : integer := 16#00#;
cap_pointer : integer := 16#40#;
ext_cap_pointer : integer := 16#00#;
iobase : integer := 16#FFF#;
extcfg : integer := 16#0000000#;
bar0 : integer range 0 to 31 := 28;
bar1 : integer range 0 to 31 := 0;
bar2 : integer range 0 to 31 := 0;
bar3 : integer range 0 to 31 := 0;
bar4 : integer range 0 to 31 := 0;
bar5 : integer range 0 to 31 := 0;
bar0_map : integer := 16#000000#;
bar1_map : integer := 16#000000#;
bar2_map : integer := 16#000000#;
bar3_map : integer := 16#000000#;
bar4_map : integer := 16#000000#;
bar5_map : integer := 16#000000#;
bartype : integer range 0 to 65535 := 16#0000#;
barminsize : integer range 5 to 31 := 12;
fifo_depth : integer range 3 to 7 := 3;
fifo_count : integer range 2 to 4 := 2;
conv_endian : integer range 0 to 1 := 1; -- 1: little (PCI) <~> big (AHB), 0: big (PCI) <=> big (AHB)
deviceirq : integer range 0 to 1 := 1;
deviceirqmask : integer range 0 to 15 := 16#0#;
hostirq : integer range 0 to 1 := 1;
hostirqmask : integer range 0 to 15 := 16#0#;
nsync : integer range 0 to 2 := 2; -- with nsync = 0, wrfst needed on syncram...
hostrst : integer range 0 to 2 := 0; -- 0: PCI reset is never driven, 1: PCI reset is driven from AHB reset if host, 2: PCI reset is always driven from AHB reset
bypass : integer range 0 to 1 := 1;
ft : integer range 0 to 1 := 0;
scantest : integer range 0 to 1 := 0;
debug : integer range 0 to 1 := 0;
tbapben : integer range 0 to 1 := 0;
tbpindex : integer := 0;
tbpaddr : integer := 0;
tbpmask : integer := 16#F00#;
netlist : integer range 0 to 1 := 0; -- Use PHY netlist
multifunc : integer range 0 to 1 := 0; -- Enables Multi-function support
multiint : integer range 0 to 1 := 0;
masters : integer := 16#FFFF#;
mf1_deviceid : integer := 16#0000#;
mf1_classcode : integer := 16#000000#;
mf1_revisionid : integer := 16#00#;
mf1_bar0 : integer range 0 to 31 := 0;
mf1_bar1 : integer range 0 to 31 := 0;
mf1_bar2 : integer range 0 to 31 := 0;
mf1_bar3 : integer range 0 to 31 := 0;
mf1_bar4 : integer range 0 to 31 := 0;
mf1_bar5 : integer range 0 to 31 := 0;
mf1_bartype : integer range 0 to 65535 := 16#0000#;
mf1_bar0_map : integer := 16#000000#;
mf1_bar1_map : integer := 16#000000#;
mf1_bar2_map : integer := 16#000000#;
mf1_bar3_map : integer := 16#000000#;
mf1_bar4_map : integer := 16#000000#;
mf1_bar5_map : integer := 16#000000#;
mf1_cap_pointer : integer := 16#40#;
mf1_ext_cap_pointer : integer := 16#00#;
mf1_extcfg : integer := 16#0000000#;
mf1_masters : integer := 16#0000#;
iotest : integer := 0
);
port(
rst : in std_logic;
clk : in std_logic;
pciclk : in std_logic;
dirq : in std_logic_vector(3 downto 0);
pcii : in pci_in_type;
pcio : out pci_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
ahbdmi : in ahb_mst_in_type;
ahbdmo : out ahb_mst_out_type;
ptarst : out std_logic;
tbapbi : in apb_slv_in_type := apb_slv_in_none;
tbapbo : out apb_slv_out_type;
debugo : out std_logic_vector(debug*255 downto 0)
);
end;
architecture rtl of grpci2 is
-- PHY =>
signal phyi : grpci2_phy_in_type;
signal phyo : grpci2_phy_out_type;
signal sig_m_request, sig_m_mabort, sig_t_abort, sig_t_ready, sig_t_retry : std_logic;
signal sig_pr_conf_comm_serren, sig_pr_conf_comm_perren : std_logic;
signal sig_soft_rst : std_logic_vector(2 downto 0);
-- PHY <=
constant PT_DEPTH : integer := 5 + log2(tracebuffer/32);
constant HIOMASK : integer := 16#E00# - 16#200#*conv_integer(conv_std_logic(tracebuffer/=0));
constant MST_ACC_CNT : integer := fifo_count - 1;
constant RAM_LATENCY : integer := 1 + ram_raw_latency(memtech); -- Delay FIFO readout one extra write clock cycle for some technologies
type pci_bars_type is array (0 to 5) of std_logic_vector(31 downto 0);
constant pci_bars_none : pci_bars_type := (others => (others => '0'));
type pci_config_space_type is record
bar : pci_bars_type;
comm : pci_config_command_type;
stat : pci_config_status_type;
ltimer : std_logic_vector(7 downto 0);
iline : std_logic_vector(7 downto 0);
pta_map : pci_bars_type; -- PCI to AHB mapping for each PCI bar
bar_mask : pci_bars_type; -- PCI bar mask (bar size)
cfg_map : std_logic_vector(31 downto 0);-- Map extended PCI configuration space to AHB address
end record;
constant pci_config_space_none : pci_config_space_type := (pci_bars_none, pci_config_command_none, pci_config_status_none, (others => '0'), (others => '0'), pci_bars_none, pci_bars_none, (others => '0'));
type pci_config_space_multi_type is array (0 to multifunc) of pci_config_space_type;
type pci_fifo_out_type is record
data : std_logic_vector(31 downto 0);
err : std_logic_vector(3 downto 0);
end record;
constant pci_fifo_out_none : pci_fifo_out_type := ((others => '0'), (others => '0'));
type pci_fifo_in_type is record
en : std_logic; -- Read/write enable for fifo
addr : std_logic_vector((FIFO_DEPTH+log2(FIFO_COUNT))-1 downto 0); -- Fifo address
data : std_logic_vector(31 downto 0); -- Fifo input data
end record;
constant pci_fifo_in_none : pci_fifo_in_type := ('0', zero32((FIFO_DEPTH+log2(FIFO_COUNT))-1 downto 0), (others => '0'));
type pci_g_acc_trans_type is record
pending : std_logic; -- Access pending (valid)
addr : std_logic_vector(31 downto 0); -- Access start address
acctype : std_logic_vector(3 downto 0); -- Access type (conf_read/write, io_read/write, data_read/write)
accmode : std_logic_vector(2 downto 0); -- Access mode (use cancel, use length, burst)
size : std_logic_vector(2 downto 0); -- Access size
offset : std_logic_vector(1 downto 0); -- Access byte offset
index : integer range 0 to FIFO_COUNT-1;-- FIFO index for first data
length : std_logic_vector(15 downto 0); -- Access length
func : std_logic_vector(2 downto 0); -- The master belongs to this PCI function
--
cbe : std_logic_vector(3 downto 0); -- Byte enable (size and offset)
endianess : std_logic; -- PCI bus endianess
end record;
constant pci_g_acc_trans_none : pci_g_acc_trans_type := ('0', (others => '0'), (others => '0'), (others => '0'), (others => '0'), (others => '0'), 0, (others => '0'), (others => '0'), (others => '0'), '0');
type pci_g_acc_status_trans_type is record
done : std_logic; -- Access done
status : std_logic_vector(3 downto 0); -- Access status
count : std_logic_vector(15 downto 0);-- Access transfer count
end record;
constant pci_g_acc_status_trans_none : pci_g_acc_status_trans_type := ('0', (others => '0'), (others => '0'));
type pci_g_acc_status_trans_multi_type is array (0 to 1) of pci_g_acc_status_trans_type;
constant pci_g_acc_status_trans_multi_none : pci_g_acc_status_trans_multi_type := (others => pci_g_acc_status_trans_none);
type pci_g_fifo_trans_type is record
pending : std_logic_vector(2 downto 0); -- FIFO pending (valid)
start : std_logic_vector(FIFO_DEPTH-1 downto 0);-- FIFO start address (first valid data)
stop : std_logic_vector(FIFO_DEPTH-1 downto 0);-- FIFO stop address (last valid data)
firstf : std_logic; -- First FIFO
lastf : std_logic; -- Last FIFO
status : std_logic_vector(3 downto 0); -- Error status
--
last_cbe : std_logic_vector(3 downto 0); -- Byte enable of last data
end record;
constant pci_g_fifo_trans_none : pci_g_fifo_trans_type := ((others => '0'), zero32(FIFO_DEPTH-1 downto 0), zero32(FIFO_DEPTH-1 downto 0), '0', '0', (others => '0'), (others => '0'));
type pci_g_acc_trans_multi_type is array (0 to 1) of pci_g_acc_trans_type;
constant pci_g_acc_trans_multi_none : pci_g_acc_trans_multi_type := (others => pci_g_acc_trans_none);
type pci_g_acc_trans_vector_type is array (0 to 3) of pci_g_acc_trans_type;
constant pci_g_acc_trans_vector_none : pci_g_acc_trans_vector_type := (others => pci_g_acc_trans_none);
type pci_g_acc_trans_vector_multi_type is array (0 to 1) of pci_g_acc_trans_vector_type;
constant pci_g_acc_trans_vector_multi_none : pci_g_acc_trans_vector_multi_type := (others => pci_g_acc_trans_vector_none);
type pci_g_fifo_trans_vector_type is array (0 to FIFO_COUNT-1) of pci_g_fifo_trans_type;
constant pci_g_fifo_trans_vector_none: pci_g_fifo_trans_vector_type := (others => pci_g_fifo_trans_none);
type pci_g_fifo_trans_vector_multi_type is array (0 to 1) of pci_g_fifo_trans_vector_type;
constant pci_g_fifo_trans_vector_multi_none : pci_g_fifo_trans_vector_multi_type := (others => pci_g_fifo_trans_vector_none);
subtype pci_g_fifo_ack_trans_vector_type is std_logic_vector(FIFO_COUNT-1 downto 0);
constant pci_g_fifo_ack_trans_vector_none : pci_g_fifo_ack_trans_vector_type := (others => '0');
type pci_g_fifo_ack_trans_vector_multi_type is array (0 to 1) of pci_g_fifo_ack_trans_vector_type;
constant pci_g_fifo_ack_trans_vector_multi_none : pci_g_fifo_ack_trans_vector_multi_type := (others => pci_g_fifo_ack_trans_vector_none);
type pci_master_acc_type is record
pending : std_logic; -- Access valid
addr : std_logic_vector(31 downto 0); -- Access start address
cmd : std_logic_vector(3 downto 0); -- Access type (conf_read/write, io_read/write, data_read/write)
cbe : std_logic_vector(3 downto 0); -- Byte enable (size and offset)
endianess : std_logic; -- PCI bus endianess
mode : std_logic_vector(2 downto 0); -- Mode[use length, burst]
length : std_logic_vector(15 downto 0); -- Access length
active : std_logic_vector(1 downto 0); -- [1]: access has data to transfer, [0]: access active
done : std_logic_vector(2 downto 0); -- [2]: access terminated by error, [1]:(PCI master write: all pending fifos acked), [0]: access done
status : std_logic_vector(2 downto 0); -- Error status
first : std_logic; -- First data in access
func : integer range 0 to multifunc; -- PCI function accessed
--
fifo_index : integer range 0 to FIFO_COUNT-1;-- FIFO index for first data
fifo_addr : std_logic_vector(FIFO_DEPTH-1 downto 0); -- Fifo address
fifo_wen : std_logic; -- FIFO write enable
fifo_ren : std_logic; -- FIFO read enable
end record;
constant pci_master_acc_none : pci_master_acc_type := ('0', (others => '0'), (others => '0'), (others => '0'), '0', (others => '0'),
(others => '0'), (others => '0'), (others => '0'), (others => '0'), '0', 0, 0, zero32(FIFO_DEPTH-1 downto 0), '0', '0');
type pci_master_acc_multi_type is array (0 to 1) of pci_master_acc_type;
constant pci_master_acc_multi_none : pci_master_acc_multi_type := (pci_master_acc_none, pci_master_acc_none);
constant acc_sel_ahb : integer := 0;
constant acc_sel_dma : integer := 1;
type ahb_master_acc_type is record
pending : std_logic; -- Access valid
addr : std_logic_vector(31 downto 0); -- Access start address
cbe : std_logic_vector(3 downto 0); -- Access byte enable (size and offset)
endianess : std_logic; -- PCI bus endianess
acctype : std_logic_vector(3 downto 0); --
mode : std_logic_vector(2 downto 0); -- Mode[use length, burst]
length : std_logic_vector(15 downto 0); -- Access length
burst : std_logic; -- Same as accmode(0);
--
fifo_index : integer range 0 to FIFO_COUNT-1;-- FIFO index for first data
fifo_addr : std_logic_vector((FIFO_DEPTH+log2(FIFO_COUNT))-1 downto 0); -- Fifo address
fifo_wen : std_logic; -- FIFO write enable
fifo_ren : std_logic; -- FIFO read enable
fifo_wdata : std_logic_vector(31 downto 0);
end record;
constant ahb_master_acc_none : ahb_master_acc_type := ('0', (others => '0'), (others => '0'), '0', (others => '0'), (others => '0'),
(others => '0'), '0', 0, (others => '0'), '0', '0', (others => '0'));
type pci_fifo_type is record
index : integer range 0 to FIFO_COUNT-1;-- FIFO index
ctrl : pci_fifo_in_type; -- FIFO RAM control signal
end record;
constant pci_fifo_none : pci_fifo_type := (0, pci_fifo_in_none);
type pci_access_type is record
addr : std_logic_vector(31 downto 0); -- Access address
ready : std_logic; -- Data ready
pending : std_logic; -- Access saved and pending
read : std_logic; -- Target read / write access
burst : std_logic; -- Burst access
retry : std_logic; -- Access terminated with retry
acc_type: std_logic_vector(1 downto 0); -- Access type: 00: memory, 10: configuration space, 11: mapping registers, 01: ext conf space mapped to AHB
bar : std_logic_vector(5 downto 0); -- PCI bar accessed
func : integer range 0 to multifunc; -- PCI function accessed
match : std_logic; -- Access matching pending access
continue: std_logic; -- Burst may continue
newacc : std_logic; -- New access, discard old data
oldburst: std_logic; -- When "new access" store last burst
impcfgreg: std_logic; -- Indicates if the current Configuration Space register is implemented
end record;
constant pci_access_none : pci_access_type := ((others => '0'), '0', '0', '0', '0', '0', (others => '0'), (others => '0'), 0, '0', '0', '0', '0', '1');
type pci_access_vector_type is array (0 to 1) of pci_access_type;
constant pci_access_vector_none : pci_access_vector_type := (others => pci_access_none);
type pci_target_type is record
state : pci_target_state_type;
fstate : pci_target_fifo_state_type;
cfifo : pci_core_fifo_vector_type; -- Core FIFO
atp : pci_fifo_type; -- AMBA to PCI FIFO
pta : pci_fifo_type; -- PCI to AMBA FIFO
addr : std_logic_vector(31 downto 0);-- Used as FIFO address during write
cur_acc : pci_access_vector_type; -- Current PCI access
lcount : std_logic_vector(2 downto 0); -- Target latency counter 8 clocks (initial latency should 16 clocks)
preload : std_logic; -- Preload the internal FIFO
preload_count : std_logic_vector(1 downto 0); -- Counter used when preloading the internal FIFO
stop : std_logic;
stoped : std_logic;
hold : std_logic_vector(0 downto 0);
hold_fifo : std_logic;
hold_reset : std_logic;
hold_write : std_logic;
first : std_logic_vector(1 downto 0); -- Used to mark first fifo. bit[1]: first fifo in transfer, bit[0]: first word in fifo
conf_addr : std_logic_vector(3 downto 0);
first_word : std_logic; -- Indicate first word in access
diswithout : std_logic; -- Disconnect without data
addr_perr : std_logic; -- Address Parity Error detected
abort : std_logic; -- Target abort
retry : std_logic;
discard : std_logic;
accbuf : pci_g_acc_trans_vector_type; -- PCI target to AHB master access buffer
blen : std_logic_vector(15 downto 0);-- PCI target burst length boundary
blenmask : std_logic_vector(15 downto 0);-- PCI target burst length boundary mask
saverfifo : std_logic; -- Save prefetched FIFO until next PCI access in case of target termination (disconnect without data)
discardtimeren : std_logic; -- Enable/Disable discard timer
discardtimer : std_logic_vector(15 downto 0);-- Discard prefetched data after 2^15 PCI clock cycles
end record;
constant pci_target_none : pci_target_type := (
pt_idle, ptf_idle, pci_core_fifo_vector_none, pci_fifo_none, pci_fifo_none,
(others => '0'), pci_access_vector_none, (others => '0'), '0', (others => '0'), '0', '0',
(others => '0'), '0', '0', '0', (others => '0'), (others => '0'),
'0', '0', '0', '0', '0', '0', pci_g_acc_trans_vector_none, (others => '0'),
(others => '0'), '0', '0', (others => '0'));
type pci_master_type is record
state : pci_master_state_type;
fstate : pci_master_fifo_state_type;
cfifo : pci_core_fifo_vector_type; -- Core FIFO
abort : std_logic_vector(1 downto 0); -- Master/Target abort [0]: master or target abort; [1]: 1 = target abort, 0 = master abort
ltimer : std_logic_vector(7 downto 0); -- PCI master latency timer
framedel : std_logic; -- Delayed frame
devsel_tout : std_logic_vector(2 downto 0); -- Devsel time out conter;
devsel_asserted : std_logic; -- Devsel asserted;
addr : std_logic_vector(31 downto 0);-- PCI state address
cbe_data : std_logic_vector(3 downto 0);
cbe_cmd : std_logic_vector(3 downto 0);
hold : std_logic_vector(1 downto 0); -- Hold transfer due to no available fifo
hold_fifo : std_logic; -- Hold FIFO due to no available fifo
done_fifo : std_logic; -- No more FIFO Available
done_trans : std_logic; -- No more data in FIFO (transfer done)
term : std_logic_vector(1 downto 0); -- Terminate transfer
done : std_logic; -- Transfer done
first : std_logic_vector(1 downto 0); -- First word in current access
last : std_logic_vector(1 downto 0); -- Last word in transfer
preload : std_logic;
preload_count : std_logic_vector(1 downto 0);
afull : std_logic; -- FIFO almost full on read
afullcnt : std_logic_vector(1 downto 0); -- Counter for the three last word in FIFO on read
burst : std_logic; -- Read burst access => signle accecc or preload
perren : std_logic_vector(1 downto 0); -- bit[0]: Drive output enable for Parity error, bit[1] delayed bit[0]
detectperr : std_logic_vector(1 downto 0); -- bit[2] = 1: Detect Parity error on write
twist : std_logic; -- On for PCI configuration space access, otherwise = pr.pta_trans.ca_twist
first_word : std_logic; -- Indicate first word in access
waitonstop : std_logic;
acc : pci_master_acc_multi_type; -- DMA/AHB slave => PCI master accesses
acc_sel : integer range 0 to 1; -- Active access, 0 = AHB slave; 1 = DMA
acc_cnt : integer range 0 to MST_ACC_CNT; -- Access transfer count (FIFO), for switching DMA/AHB-slave
acc_switch : std_logic; -- Access switching DMA/AHB-slave
fifo_addr : std_logic_vector((FIFO_DEPTH+log2(FIFO_COUNT))-1 downto 0); -- Fifo address
fifo_wdata : std_logic_vector(31 downto 0);
fifo_switch : std_logic;
end record;
constant pci_master_none : pci_master_type := (
pm_idle, pmf_idle, pci_core_fifo_vector_none, (others => '0'), (others => '0'), '0',
(others => '0'), '0', (others => '0'), (others => '0'), (others => '0'), (others => '0'), '0',
'0', '0', (others => '0'), '0', (others => '0'), (others => '0'), '0', (others => '0'), '0',
(others => '0'), '0', (others => '0'), (others => '0'), '0', '0', '0', pci_master_acc_multi_none,
0, 0, '0', zero32((FIFO_DEPTH+log2(FIFO_COUNT))-1 downto 0), (others => '0'), '0');
type pci_trace_to_apb_trans_type is record
enable : std_logic;
armed : std_logic;
wrap : std_logic;
taddr : std_logic_vector(PT_DEPTH-1 downto 0);
start_ack : std_logic;
stop_ack : std_logic;
--
dbg_ad : std_logic_vector(31 downto 0);
dbg_sig : std_logic_vector(16 downto 0);
dbg_cur_ad : std_logic_vector(31 downto 0);
dbg_cur_acc : std_logic_vector(8 downto 0);
end record;
constant pci_trace_to_apb_trans_none : pci_trace_to_apb_trans_type := ('0', '0', '0', zero32(PT_DEPTH-1 downto 0), '0', '0',
(others => '0'), (others => '0'), (others => '0'), (others => '0'));
type apb_to_pci_trace_trans_type is record
start : std_logic;
stop : std_logic;
mode : std_logic_vector(3 downto 0);
count : std_logic_vector(PT_DEPTH-1 downto 0);
tcount : std_logic_vector(7 downto 0);
ad : std_logic_vector(31 downto 0);
admask : std_logic_vector(31 downto 0);
sig : std_logic_vector(16 downto 0);
sigmask : std_logic_vector(16 downto 0);
end record;
constant apb_to_pci_trace_trans_none : apb_to_pci_trace_trans_type := ('0', '0', (others => '0'), zero32(PT_DEPTH-1 downto 0),
(others => '0'), (others => '0'), (others => '0'), (others => '0'), (others => '0'));
type pci_trace_type is record
addr : std_logic_vector(PT_DEPTH-1 downto 0);
count : std_logic_vector(PT_DEPTH-1 downto 0);
tcount : std_logic_vector(7 downto 0);
end record;
constant pci_trace_none : pci_trace_type := (zero32(PT_DEPTH-1 downto 0), zero32(PT_DEPTH-1 downto 0), (others => '0'));
type pci_msd_acc_cancel_acc_multi_type is array (0 to 1) of std_logic_vector(2 downto 0);
type pci_to_ahb_trans_type is record
-- PCI target <=> AHB master
tm_acc : pci_g_acc_trans_type; -- AHB master access (read/write) [PCI target]
tm_acc_cancel : std_logic; -- Cancel access [PCI target]
tm_acc_done_ack : std_logic; -- Ack access done [PCI target]
tm_fifo : pci_g_fifo_trans_vector_type; -- PCI target => AHB master FIFO
tm_fifo_ack : pci_g_fifo_ack_trans_vector_type; -- AHB master => PCI target FIFO ack
-- PCI master <=> AHB slave / DMA
msd_acc_ack : std_logic_vector(0 to 1); -- PCI master access ack [AHB/DMA]
--msd_acc_cancel_ack : std_logic_vector(0 to 1); -- Cancel access ack [AHB/DMA]
msd_acc_cancel_ack : pci_msd_acc_cancel_acc_multi_type; -- Cancel access ack [AHB/DMA]
msd_acc_done : pci_g_acc_status_trans_multi_type; -- Access status [AHB/DMA]
msd_fifo : pci_g_fifo_trans_vector_multi_type; -- PCI master => AHB/DMA slave FIFO
msd_fifo_ack : pci_g_fifo_ack_trans_vector_multi_type; -- AHB/DMA slave => PCI master FIFO ack
-- PCI config space <=> AHB
ca_host : std_logic;
ca_pcimsten : std_logic_vector(0 to multifunc);
ca_twist : std_logic; -- 1: byte twisting litle (PCI) <~> big (AHB), 0: big (PCI) <=> big (AHB)
-- PCI system
pa_serr : std_logic;
pa_discardtout: std_logic;
rst_ack : std_logic_vector(2 downto 0);
end record;
type ahb_to_pci_trans_type is record
-- PCI target <=> AHB master
tm_acc_ack : std_logic; -- AHB master access ack [PCI target]
tm_acc_cancel_ack : std_logic_vector(2 downto 0); -- Cancel access ack [PCI target]
tm_acc_done : pci_g_acc_status_trans_type; -- Access status [PCI target]
tm_fifo : pci_g_fifo_trans_vector_type; -- AHB master => PCI target FIFO
tm_fifo_ack : pci_g_fifo_ack_trans_vector_type; -- PCI target => AHB master FIFO ack
-- PCI master <=> AHB slave / DMA
msd_acc : pci_g_acc_trans_multi_type; -- PCI master access (read/write) [AHB/DMA]
msd_acc_cancel : std_logic_vector(1 downto 0); -- Cancel access [AHB/DMA]
msd_acc_done_ack : std_logic_vector(1 downto 0); -- Ack access done [AHB/DMA]
msd_fifo : pci_g_fifo_trans_vector_multi_type; -- AHB/DMA slave => PCI master FIFO
msd_fifo_ack : pci_g_fifo_ack_trans_vector_multi_type; -- PCI master => AHB/DMA slave FIFO ack
-- PCI system
pa_serr_rst : std_logic;
pa_discardtout_rst: std_logic;
rst : std_logic_vector(2 downto 0);
mstswdis : std_logic;
end record;
type pci_sync_type is array (1 to 2) of ahb_to_pci_trans_type;
type ahb_sync_type is array (1 to 2) of pci_to_ahb_trans_type;
type pci_trace_sync_type is array (1 to 2) of apb_to_pci_trace_trans_type;
type apb_sync_type is array (1 to 2) of pci_trace_to_apb_trans_type;
type ahb_to_pci_map_type is array (0 to 15) of std_logic_vector(31 downto 0);
constant ahb_to_pci_map_none : ahb_to_pci_map_type := (others => (others => '0'));
-- Calculate AADDR_WIDTH for HMASK
function calc_aaddr_width(di : in integer) return integer is
variable bits : integer;
begin
if di = 16#800# then bits := 31;
elsif di = 16#c00# then bits := 30;
elsif di = 16#e00# then bits := 29;
elsif di = 16#f00# then bits := 28;
elsif di = 16#f80# then bits := 27;
elsif di = 16#fc0# then bits := 26;
elsif di = 16#fe0# then bits := 25;
elsif di = 16#ff0# then bits := 24;
elsif di = 16#ff8# then bits := 23;
elsif di = 16#ffc# then bits := 22;
elsif di = 16#ffe# then bits := 21;
elsif di = 16#fff# then bits := 20;
else bits := 4; end if;
return bits;
end function;
constant AADDR_WIDTH : integer := calc_aaddr_width(hmask);
type pci_reg_type is record
conf : pci_config_space_multi_type;-- Configuration Space
po : pci_reg_out_type; -- PCI output signals
m : pci_master_type; -- PCI Master
t : pci_target_type; -- PCI Target
pta_trans : pci_to_ahb_trans_type;-- Signals between PCI clock domain and AHB clock domain (need synchronisation)
sync : pci_sync_type;
pt : pci_trace_type;
ptta_trans: pci_trace_to_apb_trans_type;
pt_sync : pci_trace_sync_type;
pciinten : std_logic_vector(3 downto 0); -- Drives output enable for INTA..D
pci66 : std_logic_vector(1 downto 0);
debug : std_logic_vector(31 downto 0);
end record;
subtype AHB_FIFO_BITS is natural range FIFO_DEPTH + 1 downto 2;
type amba_master_state_type is (am_idle, am_read, am_write, am_error);
type amba_master_type is record
state : amba_master_state_type;
first : std_logic_vector(2 downto 0); -- First data in access (mark starting fifo)
done : std_logic_vector(2 downto 0);
stop : std_logic;
dmai0 : dma_ahb_in_type;
dma_hold : std_logic;
active : std_logic;
retry : std_logic;
retry_blen: std_logic_vector(15 downto 0);
retry_size: std_logic_vector(1 downto 0);
retry_offset: std_logic_vector(1 downto 0);
acc : ahb_master_acc_type; -- PCI target => AHB master accesses
hold : std_logic_vector(2 downto 0);
last : std_logic_vector(2 downto 0);
faddr : std_logic_vector(AHB_FIFO_BITS);
blen : std_logic_vector(15 downto 0);
end record;
constant amba_master_none : amba_master_type := (
am_idle, (others => '0'), (others => '0'), '0', dma_ahb_in_none, '0', '0', '0', (others => '0'), (others => '0'),
(others => '0'), ahb_master_acc_none, (others => '0'), (others => '0'), (others => '0'), (others => '0'));
type amba_slave_state_type is (as_idle, as_checkpcimst, as_read, as_write, as_pcitrace);
type amba_slave_type is record
state : amba_slave_state_type;
atp : pci_fifo_type;
pta : pci_fifo_type;
hready : std_logic;
hwrite : std_logic;
hsel : std_logic;
hmbsel : std_logic_vector(0 to 2);
hresp : std_logic_vector(1 downto 0);
htrans : std_logic_vector(1 downto 0);
hsize : std_logic_vector(2 downto 0);
hmaster : std_logic_vector(3 downto 0);
hburst : std_logic;
haddr : std_logic_vector(31 downto 0);
retry : std_logic;
first : std_logic; -- First access in transfer
firstf : std_logic; -- First fifo
pending : std_logic_vector(1 downto 0);
addr : std_logic_vector(31 downto 0);
offset : std_logic_vector(1 downto 0);
master : std_logic_vector(3 downto 0);
write : std_logic;
oneword : std_logic;
burst : std_logic;
config : std_logic;
io : std_logic;
size : std_logic_vector(2 downto 0);
start : std_logic;
hrdata : std_logic_vector(31 downto 0);
continue : std_logic;
discard : std_logic;
atp_map : ahb_to_pci_map_type;
io_map : std_logic_vector(31 downto 16);
cfg_bus : std_logic_vector(23 downto 16);
cfg_status: std_logic_vector(1 downto 0);
io_cfg_burst : std_logic_vector(1 downto 0); -- Alow burst on PCI IO / CONF
erren : std_logic; -- Enables AHB error response for Master/Target abort
parerren : std_logic; -- Enables AHB error response for PAR error
accbuf : pci_g_acc_trans_vector_type; -- AHB slave to PCI master access buffer
blen : std_logic_vector(7 downto 0); -- AHB slave prefetch burst length
blenmask : std_logic_vector(15 downto 0); -- AHB slave prefetch length AHB master mask
done_fifo : std_logic_vector(1 downto 0);
tb_ren : std_logic; -- PCI trace buffer read enable
fakehost : std_logic; -- Fake device in system slot (HOST)
stoppciacc: std_logic;
end record;
constant amba_slave_none : amba_slave_type := (
as_idle, pci_fifo_none, pci_fifo_none, '1', '0', '0', (others => '0'), (others => '0'),
(others => '0'), (others => '0'), (others => '0'), '0', (others => '0'), '0', '0', '0',
(others => '0'), (others => '0'), (others => '0'), (others => '0'), '0', '0', '0', '0', '0',
(others => '0'), '0', (others => '0'), '0', '0', ahb_to_pci_map_none, (others => '0'),
(others => '0'), (others => '0'), (others => '0'), '0', '0', pci_g_acc_trans_vector_none,
(others => '0'), (others => '0'), (others => '0'), '0', '0', '0');
type irq_reg_type is record
device_mask : std_logic_vector(3 downto 0);
device_force : std_logic;
host_mask : std_logic_vector(3 downto 0);
host_status : std_logic_vector(3 downto 0);
host_pirq_vl : std_logic_vector(3 downto 0);
host_pirq_l : std_logic;
access_en : std_logic; -- Enables IRQ for Master/Target abort and PAR error
access_status: std_logic_vector(2 downto 0);
access_pirq : std_logic;
access_pirq_l: std_logic;
system_en : std_logic; -- Enables IRQ for System error
system_status: std_logic_vector(1 downto 0);
system_pirq : std_logic;
system_pirq_l: std_logic;
dma_pirq_l : std_logic;
irqen : std_logic;
end record;
constant irq_reg_none : irq_reg_type := (
(others => '0'), '0', (others => '0'), (others => '0'), (others => '0'),
'0', '0', (others => '0'), '0', '0', '0', (others => '0'), '0', '0', '0', '0');
type dma_state_type is (dma_idle, dma_read_desc, dma_next_channel, dma_write_status, dma_read, dma_write, dma_error);
type dma_desc_type is record
en : std_logic;
irqen : std_logic;
write : std_logic;
tw : std_logic;
desctype: std_logic_vector(1 downto 0);
cio : std_logic_vector(1 downto 0);
len : std_logic_vector(15 downto 0);
ch : std_logic_vector(31 downto 0);
nextch : std_logic_vector(31 downto 0);
addr : std_logic_vector(31 downto 0);
nextdesc: std_logic_vector(31 downto 0);
cnt : std_logic_vector(15 downto 0);
emptych : std_logic;
chcnt : std_logic_vector(2 downto 0);
paddr : std_logic_vector(31 downto 0);
aaddr : std_logic_vector(31 downto 0);
acctype : std_logic_vector(3 downto 0);
chid : std_logic_vector(2 downto 0);
end record;
constant dma_desc_none : dma_desc_type := (
'0', '0', '0', '0', (others => '0'), (others => '0'), (others => '0'), (others => '0'),
(others => '0'), (others => '0'), (others => '0'), (others => '0'), '0',
(others => '0'), (others => '0'), (others => '0'), (others => '0'), (others => '0'));
type dma_reg_type is record
state : dma_state_type;
dmai1 : dma_ahb_in_type;
desc : dma_desc_type;
dtp : pci_fifo_type;
ptd : pci_fifo_type;
rcnt : std_logic_vector(1 downto 0);
en : std_logic;
err : std_logic_vector(2 downto 0);
errlen : std_logic_vector(15 downto 0);
numch : std_logic_vector(2 downto 0);
dma_hold : std_logic_vector(2 downto 0);
dma_last : std_logic_vector(2 downto 0);
newfifo : std_logic;
active : std_logic;
done : std_logic_vector(1 downto 0);
faddr : std_logic_vector(AHB_FIFO_BITS);
first : std_logic_vector(2 downto 0);
retry : std_logic;
retry_len : std_logic_vector(15 downto 0);
addr : std_logic_vector(31 downto 0);
irq : std_logic;
irqen : std_logic;
irqstatus : std_logic_vector(1 downto 0);
len : std_logic_vector(15 downto 0);
errstatus : std_logic_vector(4 downto 0); -- DMA error status
irqch : std_logic_vector(7 downto 0); -- DMA Channel irq status
running : std_logic; -- DMA is running
end record;
constant dma_reg_none : dma_reg_type := (
dma_idle, dma_ahb_in_none, dma_desc_none, pci_fifo_none, pci_fifo_none,
(others => '0'), '0', (others => '0'), (others => '0'), (others => '0'),
(others => '0'), (others => '0'), '0', '0', (others => '0'), zero32(AHB_FIFO_BITS),
(others => '0'), '0', (others => '0'), (others => '0'), '0', '0', (others => '0'),
(others => '0'), (others => '0'), (others => '0'), '0');
type amba_reg_type is record
m : amba_master_type;
atp_trans : ahb_to_pci_trans_type;
sync : ahb_sync_type;
s : amba_slave_type;
irq : irq_reg_type;
dma : dma_reg_type;
atpt_trans: apb_to_pci_trace_trans_type;
apb_sync : apb_sync_type;
apb_pt_stat : std_logic_vector(31 downto 0);
apb_pr_conf_0_pta_map : pci_bars_type; -- PCI to AHB mapping for each PCI bar (read only)
debug : std_logic_vector(31 downto 0);
debug_pr : std_logic_vector(31 downto 0);
debuga : std_logic_vector(31 downto 0);
end record;
constant REVISION : amba_version_type := 1;
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_GRPCI2, 0, REVISION, irq),
1 => apb_iobar(paddr, pmask));
-- APB DEBUG
constant tbpconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_GRPCI2_TB, 0, REVISION, 0),
1 => apb_iobar(tbpaddr, tbpmask));
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_GRPCI2, 0, REVISION, 0),
4 => ahb_membar(haddr, '0', '0', hmask),
5 => ahb_iobar (ioaddr, HIOMASK),
others => zero32);
constant oeon : std_logic := conv_std_logic_vector(oepol,1)(0);
constant oeoff : std_logic := not conv_std_logic_vector(oepol,1)(0);
constant ones32 : std_logic_vector(31 downto 0) := (others => '1');
signal pr, prin : pci_reg_type;
signal pi, piin : pci_in_type; -- Registered PCI signals.
signal pcirstout : std_logic; -- PCI reset
signal pciasyncrst, pciasyncrst_comb : std_logic; -- PCI asynchronous reset
signal pcirst : std_logic_vector(2 downto 0); -- PCI reset
signal pciinten,pciinten_pad : std_logic_vector(3 downto 0);
signal pcisig : std_logic_vector(16 downto 0);
signal po, poin, po_keep : pci_reg_out_type; -- PCI output signals (to drive pads)
signal poin_keep : std_logic_vector(90 downto 0);
signal raden, rinaden, rinaden_tmp : std_logic_vector(31 downto 0);
signal pr_pta_trans_gated : pci_to_ahb_trans_type; -- PCI Target => AHB Master pending gated with pcirst
signal tm_fifoo_atp : pci_fifo_out_type; -- FIFO output data
signal ms_fifoo_atp : pci_fifo_out_type; -- FIFO output data
signal tm_fifoo_pta : pci_fifo_out_type;
signal ms_fifoo_pta : pci_fifo_out_type;
signal md_fifoo_dtp : pci_fifo_out_type; -- DMA FIFO output data
signal md_fifoo_ptd : pci_fifo_out_type;
signal pt_fifoo_ad : pci_fifo_out_type; -- PCI trace output data
signal pt_fifoo_sig : pci_fifo_out_type;
-- Scan test support
signal scanen : std_logic;
signal testin : std_logic_vector(TESTIN_WIDTH-1 downto 0);
signal scan_prin_t_atp_ctrl_en : std_logic;
signal scan_ar_m_acc_fifo_wen : std_logic;
signal scan_arin_m_acc_fifo_ren : std_logic;
signal scan_pr_t_pta_ctrl_en : std_logic;
signal scan_prin_m_acc_acc_sel_ahb_fifo_ren : std_logic;
signal scan_ar_s_atp_ctrl_en : std_logic;
signal scan_arin_s_pta_ctrl_en : std_logic;
signal scan_pr_m_acc_acc_sel_ahb_fifo_wen : std_logic;
signal scan_prin_m_acc_acc_sel_dma_fifo_ren : std_logic;
signal scan_ar_dma_dtp_ctrl_en : std_logic;
signal scan_arin_dma_ptd_ctrl_en : std_logic;
signal scan_pr_m_acc_acc_sel_dma_fifo_wen : std_logic;
signal scan_tb_ren : std_logic;
signal scan_pr_ptta_trans_enable : std_logic;
signal tb_addr : std_logic_vector(31 downto 0); -- Trace Buffer address
signal tb_ren : std_logic; -- Trace Buffer read enable
signal ar, arin : amba_reg_type;
signal dmao0, dmao1 : dma_ahb_out_type;
signal disabled_dmai : dma_ahb_in_type;
signal ahbmo_con : ahb_mst_out_type; -- Connect AHB-master to ahbmo
signal lpcim_rst, lpcit_rst, lpci_rst: std_ulogic;
signal lahbm_rst, lahbs_rst, lahb_rst: std_ulogic;
signal iotmdin: std_logic_vector(45 downto 0);
signal iotmdout: std_logic_vector(44 downto 0);
signal iotmact, iotmoe: std_ulogic;
attribute sync_set_reset of lpcim_rst : signal is "true";
attribute sync_set_reset of lpcit_rst : signal is "true";
attribute sync_set_reset of lpci_rst : signal is "true";
attribute sync_set_reset of pcirst : signal is "true";
--attribute sync_set_reset of rst : signal is "true";
attribute sync_set_reset of lahbm_rst : signal is "true";
attribute sync_set_reset of lahbs_rst : signal is "true";
attribute sync_set_reset of lahb_rst : signal is "true";
type bar_size_type is array (0 to 5) of integer range 0 to 31;
constant func0_bar_size : bar_size_type := (bar0, bar1, bar2, bar3, bar4, bar5);
constant func1_bar_size : bar_size_type := (mf1_bar0, mf1_bar1, mf1_bar2, mf1_bar3, mf1_bar4, mf1_bar5);
constant none_bar_size : bar_size_type := (0, 0, 0, 0, 0, 0);
type bar_size_vector_type is array (0 to 7) of bar_size_type;
constant bar_size : bar_size_vector_type := (func0_bar_size, func1_bar_size, none_bar_size, none_bar_size,
none_bar_size, none_bar_size, none_bar_size, none_bar_size);
constant func0_bar_type : std_logic_vector(15 downto 0) := conv_std_logic_vector(bartype,16);
constant func1_bar_type : std_logic_vector(15 downto 0) := conv_std_logic_vector(mf1_bartype,16);
constant func0_bar_prefetch : std_logic_vector(5 downto 0) := func0_bar_type(5 downto 0);
constant func1_bar_prefetch : std_logic_vector(5 downto 0) := func1_bar_type(5 downto 0);
type bar_prefetch_vector_type is array (0 to 7) of std_logic_vector(5 downto 0);
constant bar_prefetch : bar_prefetch_vector_type := (func0_bar_prefetch, func1_bar_prefetch, (others => '0'), (others => '0'),
(others => '0'), (others => '0'), (others => '0'), (others => '0'));
constant func0_bar_io : std_logic_vector(5 downto 0) := func0_bar_type(13 downto 8);
constant func1_bar_io : std_logic_vector(5 downto 0) := func1_bar_type(13 downto 8);
constant bar_io : bar_prefetch_vector_type := (func0_bar_io, func1_bar_io, (others => '0'), (others => '0'),
(others => '0'), (others => '0'), (others => '0'), (others => '0'));
type conf_int_vector_type is array (0 to 7) of integer;
constant deviceid_vector : conf_int_vector_type := (deviceid, mf1_deviceid, 0, 0, 0, 0, 0, 0);
constant classcode_vector : conf_int_vector_type := (classcode, mf1_classcode, 0, 0, 0, 0, 0, 0);
constant revisionid_vector : conf_int_vector_type := (revisionid, mf1_revisionid, 0, 0, 0, 0, 0, 0);
constant cap_pointer_vector : conf_int_vector_type := (cap_pointer, mf1_cap_pointer, 0, 0, 0, 0, 0, 0);
constant ext_cap_pointer_vector : conf_int_vector_type := (ext_cap_pointer, mf1_ext_cap_pointer, 0, 0, 0, 0, 0, 0);
constant extcfg_vector : conf_int_vector_type := (extcfg, mf1_extcfg, 0, 0, 0, 0, 0, 0);
type conf_vector16_vector_type is array (0 to 7) of std_logic_vector(15 downto 0);
constant masters_vector : conf_vector16_vector_type := (conv_std_logic_vector(masters, 16), conv_std_logic_vector(mf1_masters, 16),
x"0000", x"0000", x"0000", x"0000", x"0000", x"0000");
constant deviceirq_vector : conf_int_vector_type := (1*deviceirq, (1+1*multiint)*deviceirq, (1+2*multiint)*deviceirq, (1+3*multiint)*deviceirq,
1*deviceirq, (1+1*multiint)*deviceirq, (1+2*multiint)*deviceirq, (1+3*multiint)*deviceirq);
type default_bar_map_type is array (0 to 7) of pci_bars_type;
constant default_bar_map : default_bar_map_type := ((conv_std_logic_vector(bar0_map, 24)&x"00", conv_std_logic_vector(bar1_map, 24)&x"00",
conv_std_logic_vector(bar2_map, 24)&x"00", conv_std_logic_vector(bar3_map, 24)&x"00",
conv_std_logic_vector(bar4_map, 24)&x"00", conv_std_logic_vector(bar5_map, 24)&x"00"),
(conv_std_logic_vector(mf1_bar0_map, 24)&x"00", conv_std_logic_vector(mf1_bar1_map, 24)&x"00",
conv_std_logic_vector(mf1_bar2_map, 24)&x"00", conv_std_logic_vector(mf1_bar3_map, 24)&x"00",
conv_std_logic_vector(mf1_bar4_map, 24)&x"00", conv_std_logic_vector(mf1_bar5_map, 24)&x"00"),
pci_bars_none, pci_bars_none, pci_bars_none, pci_bars_none, pci_bars_none, pci_bars_none);
function blenmask_size(barminsize : in integer)
return integer is
variable res : integer;
begin
res := 16;
if barminsize < 16 then res := barminsize; end if;
return (res - 1);
end function;
function set_pta_addr(paddr : in std_logic_vector(31 downto 0);
pta_map : in pci_bars_type;
bar : in std_logic_vector(5 downto 0);
bar_mask: in pci_bars_type;
barminsize : in integer)
return std_logic_vector is
variable res : std_logic_vector(31 downto 0);
begin
res := paddr;
for i in 0 to 5 loop
if bar(i) = '1' then
res(31 downto barminsize) := (pta_map(i)(31 downto barminsize) and bar_mask(i)(31 downto barminsize)) or
(paddr(31 downto barminsize) and not bar_mask(i)(31 downto barminsize));
end if;
end loop;
return res;
end function;
function byte_twist(di : in std_logic_vector(31 downto 0); twist : in std_logic) return std_logic_vector is
variable do : std_logic_vector(31 downto 0);
begin
if twist = '1' then
for i in 0 to 3 loop
do(31-i*8 downto 24-i*8) := di(31-(3-i)*8 downto 24-(3-i)*8);
end loop;
else
do := di;
end if;
return do;
end function;
function set_size_from_cbe(cbe : in std_logic_vector(3 downto 0))
return std_logic_vector is
variable res : std_logic_vector(1 downto 0);
begin
case cbe is
when "0111" => res := "00";
when "1011" => res := "00";
when "1101" => res := "00";
when "1110" => res := "00";
when "0011" => res := "01";
when "1100" => res := "01";
when others => res := "10";
end case;
return res;
end function;
function set_addr_from_cbe(cbe : in std_logic_vector(3 downto 0);
twist: in std_logic)
return std_logic_vector is
variable res : std_logic_vector(1 downto 0);
begin
if twist = '1' then -- Little (PCI) to big (AHB) endian
case cbe is
when "0111" => res := "11";
when "1011" => res := "10";
when "1101" => res := "01";
when "1110" => res := "00";
when "0011" => res := "10";
when "1100" => res := "00";
when others => res := "00";
end case;
else -- Big (PCI) to big (AHB) endian
case cbe is
when "0111" => res := "00";
when "1011" => res := "01";
when "1101" => res := "10";
when "1110" => res := "11";
when "0011" => res := "00";
when "1100" => res := "10";
when others => res := "00";
end case;
end if;
return res;
end function;
function set_cbe_from_size_addr(size : in std_logic_vector(2 downto 0);
addr : in std_logic_vector(1 downto 0);
twist : in std_logic)
return std_logic_vector is
variable res : std_logic_vector(3 downto 0);
begin
if twist = '1' then
if size = "000" then -- byte
case addr is
when "11" => res := "0111";
when "10" => res := "1011";
when "01" => res := "1101";
when others => res := "1110";
end case;
elsif size = "001" then -- half word
case addr is
when "10" => res := "0011";
when others => res := "1100";
end case;
else
res := "0000";
end if;
else
if size = "000" then -- byte
case addr is
when "11" => res := "1110";
when "10" => res := "1101";
when "01" => res := "1011";
when others => res := "0111";
end case;
elsif size = "001" then -- half word
case addr is
when "10" => res := "1100";
when others => res := "0011";
end case;
else
res := "0000";
end if;
end if;
return res;
end function;
function set_atp_addr(haddr : in std_logic_vector(31 downto 0);
atp_map : in ahb_to_pci_map_type;
hmaster : in std_logic_vector(3 downto 0);
size : in integer)
return std_logic_vector is
variable res : std_logic_vector(31 downto 0);
variable i : integer;
begin
i := conv_integer(hmaster);
res := haddr;
if AADDR_WIDTH /= 4 then
res(31 downto size) := atp_map(i)(31 downto size);
end if;
return res;
end function;
function set_pci_conf_addr(addr : in std_logic_vector(31 downto 0);
cfg_bus : in std_logic_vector(23 downto 16))
return std_logic_vector is
variable res : std_logic_vector(31 downto 0);
variable i : integer range 0 to 21;
begin
res := (others => '0');
i := conv_integer(addr(15 downto 11));
if cfg_bus = zero32(23 downto 16) then -- Type 0 config
if i /= 0 then
res(10 + i) := '1';
end if;
res(10 downto 2) := addr(10 downto 2); -- Function number [10:8], Register address [7:2]
res(0) := '0'; -- Type
else -- Type 1 config
res(23 downto 16) := cfg_bus;
res(15 downto 2) := addr(15 downto 2); -- Function number [10:8], Register address [7:2]
res(0) := '1'; -- Type
end if;
return res;
end function;
function set_pci_io_addr(addr : in std_logic_vector(31 downto 0);
io_map : in std_logic_vector(31 downto 16))
return std_logic_vector is
variable res : std_logic_vector(31 downto 0);
begin
res := io_map & addr(15 downto 0);
return res;
end function;
function set_pci_io_byte_addr(addr : in std_logic_vector(1 downto 0);
size : in std_logic_vector(2 downto 0);
twist : in std_logic)
return std_logic_vector is
variable res : std_logic_vector(1 downto 0);
begin
if twist = '1' then
res := addr;
else
if size = "010" then
res := "00";
elsif size = "001" then
case addr is
when "00" => res := "10";
when others => res := "00";
end case;
else
case addr is
when "00" => res := "11";
when "01" => res := "10";
when "10" => res := "01";
when "11" => res := "00";
when others => res := "00";
end case;
end if;
end if;
return res;
end function;
begin
-- PHY =>
pciphy0 : grpci2_phy_wrapper
generic map(tech => memtech, oepol => oepol,
bypass => bypass, netlist => netlist,
scantest => scantest, iotest => iotest)
port map(
pciclk => pciclk,
pcii => pcii,
phyi => phyi,
pcio => pcio,
phyo => phyo,
iotmact => iotmact,
iotmoe => iotmoe,
iotdout => iotmdout,
iotdin => iotmdin
);
phyi.pciasyncrst <= pciasyncrst;
phyi.pcisoftrst <= sig_soft_rst;
phyi.pcirstout <= pcirstout;
phyi.pciinten <= pciinten_pad;
phyi.m_request <= sig_m_request;
phyi.m_mabort <= sig_m_mabort;
phyi.pr_m_fstate <= pr.m.fstate;
phyi.pr_m_cfifo <= pr.m.cfifo;
phyi.pv_m_cfifo <= prin.m.cfifo;
phyi.pr_m_addr <= pr.m.addr;
phyi.pr_m_cbe_data <= pr.m.cbe_data;
phyi.pr_m_cbe_cmd <= pr.m.cbe_cmd;
phyi.pr_m_first <= pr.m.first(1 downto 0);
phyi.pv_m_term <= prin.m.term(1 downto 0);
phyi.pr_m_ltimer <= pr.m.ltimer;
phyi.pr_m_burst <= pr.m.burst;
phyi.pr_m_abort <= pr.m.abort(0 downto 0);
phyi.pr_m_perren <= pr.m.perren(0 downto 0);
phyi.pr_m_done_fifo <= pr.m.done_fifo;
phyi.t_abort <= sig_t_abort;
phyi.t_ready <= sig_t_ready;
phyi.t_retry <= sig_t_retry;
phyi.pr_t_state <= pr.t.state;
phyi.pv_t_state <= prin.t.state;
phyi.pr_t_fstate <= pr.t.fstate;
phyi.pr_t_cfifo <= pr.t.cfifo;
phyi.pv_t_diswithout <= prin.t.diswithout;
phyi.pr_t_stoped <= pr.t.stoped;
phyi.pr_t_lcount <= pr.t.lcount;
phyi.pr_t_first_word <= pr.t.first_word;
phyi.pr_t_cur_acc_0_read <= pr.t.cur_acc(0).read;
phyi.pv_t_hold_write <= prin.t.hold_write;
phyi.pv_t_hold_reset <= prin.t.hold_reset;
phyi.pr_conf_comm_perren <= sig_pr_conf_comm_perren;
phyi.pr_conf_comm_serren <= sig_pr_conf_comm_serren; -- SERR# only asserted for address parity error
phyi.testen <= ahbsi.testen when scantest=1 else '0';
phyi.testoen <= ahbsi.testoen;
phyi.testrst <= ahbsi.testrst;
pcirst <= (others => phyo.pcirsto(0));
pi <= phyo.pio;
po <= phyo.poo;
-- PHY <=
disabled_dmai <= ('0', '0', (others => '0'), (others => '0'), (others => '0'), '0', '0');
scanen <= (ahbsi.testen and ahbsi.scanen) when (scantest = 1) else '0';
testin <= ahbsi.testen & "0" & ahbsi.testin(TESTIN_WIDTH-3 downto 0);
pciasyncrst <= ahbsi.testrst when (scantest = 1) and (ahbsi.testen = '1') else pcii.rst;
pciasyncrst_comb <= pcii.rst; -- Version used in comb logic, don't mux in testrst
hostrst2 : if hostrst = 2 generate
pcirstout <= rst and not ar.atp_trans.rst(2);
end generate;
hostrst1 : if hostrst = 1 generate
pcirstout <= rst and not ar.atp_trans.rst(2) when pcii.host = '0' else '1';
end generate;
hostrst0 : if hostrst = 0 generate
pcirstout <= '1';
end generate;
-- Propagate PCI reset to AMBA for peripheral devices
ptarst <= pcii.rst when pcii.host = '1' and hostrst /= 2 else '1';
-- PCI trace signal
pcisig <= pi.cbe &
pi.frame & pi.irdy & pi.trdy & pi.stop &
pi.devsel & pi.par & pi.perr & pi.serr &
pi.idsel & pr.po.req & pi.gnt & pi.lock &
pi.rst; -- & "000";
pcomb : process(pr, pi, pcirst(0), pcii, ar.atp_trans, tm_fifoo_atp, ms_fifoo_atp, md_fifoo_dtp, pcirstout, pciinten, pcisig, ar.atpt_trans,
phyo, pciasyncrst_comb, lpcim_rst, lpcit_rst, lpci_rst, iotmact)
variable pv : pci_reg_type;
variable atp_trans : ahb_to_pci_trans_type;
variable pci : pci_in_type;
variable t_hit : std_logic; -- Target bar address match
variable t_chit : std_logic; -- Target configuration space hit
variable t_bar : std_logic_vector(5 downto 0); -- PCI bar with hit
variable t_func : integer range 0 to multifunc;
variable t_ready : std_logic; -- Backend ready to send/receive data
variable t_abort : std_logic; -- Stop PCI access
variable t_retry : std_logic; -- Stop PCI access
variable t_index : integer range 0 to FIFO_COUNT-1;-- FIFO index
variable t_cad : std_logic_vector(31 downto 0); -- Data from PCI Configuration Space Header
variable conf_func : integer range 0 to 7;
variable all_func_serren : std_logic;
variable t_acc_type : std_logic_vector(1 downto 0);
variable t_acc_impcfgreg: std_logic;
variable t_acc_burst: std_logic;
variable t_acc_read : std_logic;
variable tm_acc_pending : std_logic;
variable tm_acc_cancel : std_logic;
variable tm_acc_done : std_logic;
variable tm_fifo_pending : std_logic_vector(FIFO_COUNT-1 downto 0);
variable tm_fifo_empty : std_logic_vector(FIFO_COUNT-1 downto 0);
variable tm_fifo : pci_g_fifo_trans_vector_type;
variable accbufindex : integer range 0 to 3;
-- PCI master
variable m_request : std_logic;
variable m_ready : std_logic;
variable m_mabort : std_logic; -- Master abort
variable m_tabort : std_logic; -- Target abort
variable m_index : integer range 0 to FIFO_COUNT-1;-- FIFO index
variable m_func : integer range 0 to multifunc;
variable acc : pci_master_acc_type;
variable accdone : std_logic; -- Renamed to be synthesized with XST
variable acc_cancel : std_logic;
variable acc_switch : std_logic;
variable fifo : pci_g_fifo_trans_vector_type;
variable fifo_pending : std_logic_vector(FIFO_COUNT-1 downto 0);
variable fifo_empty : std_logic_vector(FIFO_COUNT-1 downto 0);
variable fifo_nindex : integer range 0 to FIFO_COUNT-1;-- FIFO index
variable msd_acc : pci_g_acc_trans_multi_type;
variable ms_acc_pending : std_logic;
variable ms_acc_done : std_logic;
variable ms_acc_cancel : std_logic;
variable ms_fifo_pending : std_logic_vector(FIFO_COUNT-1 downto 0);
variable ms_fifo_empty : std_logic_vector(FIFO_COUNT-1 downto 0);
variable ms_fifo : pci_g_fifo_trans_vector_type;
variable md_acc_pending : std_logic;
variable md_acc_done : std_logic;
variable md_acc_cancel : std_logic;
variable md_fifo_pending : std_logic_vector(FIFO_COUNT-1 downto 0);
variable md_fifo_empty : std_logic_vector(FIFO_COUNT-1 downto 0);
variable md_fifo : pci_g_fifo_trans_vector_type;
-- PCI trace
variable pt_start : std_logic;
variable pt_stop : std_logic;
variable atpt_trans : apb_to_pci_trace_trans_type;
variable pt_setup : apb_to_pci_trace_trans_type;
constant z : std_logic_vector(48 downto 0) := (others => '0');
-- Soft reset
variable pci_target_rst : std_logic;
variable pci_master_rst : std_logic;
variable pci_hard_rst : std_logic;
begin
-- --------------------------------------------------------------------------------
-- Global defaults
-- --------------------------------------------------------------------------------
-- Defaults
pv := pr;
pv.pta_trans.ca_host := pcii.host;
pv.pci66(0) := pcii.pci66; pv.pci66(1) := pr.pci66(0);
-- FIFO and PCI<=>AHB sync
pv.sync(1) := ar.atp_trans; pv.sync(2) := pr.sync(1);
if nsync = 0 then atp_trans := ar.atp_trans;
else atp_trans := pr.sync(nsync); end if;
-- PCI soft reset
pv.pta_trans.rst_ack(0) := atp_trans.rst(0);
pv.pta_trans.rst_ack(1) := atp_trans.rst(1);
pci_target_rst := not pr.pta_trans.rst_ack(0) and (pr.pta_trans.rst_ack(0) xor atp_trans.rst(0));
pci_master_rst := not pr.pta_trans.rst_ack(1) and (pr.pta_trans.rst_ack(1) xor atp_trans.rst(1));
pci_hard_rst := atp_trans.rst(2);
pci := phyo.pciv;
if (pr.po.perr = '0' -- Parity Error detected
and (pr.m.perren /= "00")) then -- During master read
pv.conf(pr.m.acc(pr.m.acc_sel).func).stat.dpe := '1';
end if;
if (pr.po.perr = '0' -- Parity Error detected
and ((pr.t.state = pt_s_data or pr.t.state = pt_turn_ar) and pr.t.cur_acc(0).read = '0')) -- Write to target
or (pr.t.addr_perr = '1') then -- Parity Error in Address phase
pv.conf(pr.t.cur_acc(0).func).stat.dpe := '1';
end if;
-- Signaled System Error
for j in 0 to multifunc loop
if pr.conf(j).comm.perren = '1' and pr.conf(j).comm.serren = '1' and pr.po.serren = oeon then
pv.conf(j).stat.sse := '1';
end if;
end loop;
-- SERR to AHB
if atp_trans.pa_serr_rst = '1' then
pv.pta_trans.pa_serr := '1';
elsif pi.serr = '0' then
pv.pta_trans.pa_serr := '0';
end if;
-- --------------------------------------------------------------------------------
-- PCI master defaults
-- --------------------------------------------------------------------------------
-- Default
m_request := '0';
m_ready := '0';
m_ready := '1';
pv.m.fifo_switch := '0';
pv.m.acc(0).fifo_ren := '0'; -- read enable [AHB]
pv.m.acc(0).fifo_wen := '0'; -- write enable [AHB]
pv.m.acc(1).fifo_ren := '0'; -- read enable [DMA]
pv.m.acc(1).fifo_wen := '0'; -- write enable [DMA]
pv.m.fifo_wdata := byte_twist(pi.ad, pr.m.twist);
pv.m.framedel := pr.po.frame;
ms_acc_pending := atp_trans.msd_acc(0).pending xor pr.pta_trans.msd_acc_ack(0);
ms_acc_done := atp_trans.msd_acc_done_ack(0) xor pr.pta_trans.msd_acc_done(0).done;
ms_acc_cancel := atp_trans.msd_acc_cancel(0) xor pr.pta_trans.msd_acc_cancel_ack(0)(0);
-- Stop_ack also needs to be delayed when pending is delayed
pv.pta_trans.msd_acc_cancel_ack(0)(1) := pr.pta_trans.msd_acc_cancel_ack(0)(0);
pv.pta_trans.msd_acc_cancel_ack(0)(2) := pr.pta_trans.msd_acc_cancel_ack(0)(1);
for i in 0 to FIFO_COUNT-1 loop
ms_fifo_pending(i) := atp_trans.msd_fifo(0)(i).pending(RAM_LATENCY) xor pr.pta_trans.msd_fifo_ack(0)(i);
ms_fifo_empty(i) := not (pr.pta_trans.msd_fifo(0)(i).pending(0) xor atp_trans.msd_fifo_ack(0)(i));
-- To set pending when data is stored in fifo, with this stop_ack also needs to be delayed
pv.pta_trans.msd_fifo(0)(i).pending(1) := pr.pta_trans.msd_fifo(0)(i).pending(0);
pv.pta_trans.msd_fifo(0)(i).pending(2) := pr.pta_trans.msd_fifo(0)(i).pending(1);
end loop;
ms_fifo := ar.atp_trans.msd_fifo(0);
msd_acc(0) := ar.atp_trans.msd_acc(0);
md_acc_pending := atp_trans.msd_acc(1).pending xor pr.pta_trans.msd_acc_ack(1);
md_acc_done := atp_trans.msd_acc_done_ack(1) xor pr.pta_trans.msd_acc_done(1).done;
md_acc_cancel := atp_trans.msd_acc_cancel(1) xor pr.pta_trans.msd_acc_cancel_ack(1)(0);
-- Stop_ack also needs to be delayed when pending is delayed
pv.pta_trans.msd_acc_cancel_ack(1)(1) := pr.pta_trans.msd_acc_cancel_ack(1)(0);
pv.pta_trans.msd_acc_cancel_ack(1)(2) := pr.pta_trans.msd_acc_cancel_ack(1)(1);
for i in 0 to FIFO_COUNT-1 loop
md_fifo_pending(i) := atp_trans.msd_fifo(1)(i).pending(RAM_LATENCY) xor pr.pta_trans.msd_fifo_ack(1)(i);
md_fifo_empty(i) := not (pr.pta_trans.msd_fifo(1)(i).pending(0) xor atp_trans.msd_fifo_ack(1)(i));
-- To set pending when data is stored in fifo, with this stop_ack also needs to be delayed
pv.pta_trans.msd_fifo(1)(i).pending(1) := pr.pta_trans.msd_fifo(1)(i).pending(0);
pv.pta_trans.msd_fifo(1)(i).pending(2) := pr.pta_trans.msd_fifo(1)(i).pending(1);
end loop;
md_fifo := ar.atp_trans.msd_fifo(1);
msd_acc(1) := ar.atp_trans.msd_acc(1);
-- PCI master function
m_func := pr.m.acc(pr.m.acc_sel).func;
-- --------------------------------------------------------------------------------
-- PCI master core
-- --------------------------------------------------------------------------------
if master /= 0 or dma /= 0 then -- PCI master enabled
-- First
if pr.m.state = pm_idle or pr.m.state = pm_turn_ar or pr.m.state = pm_dr_bus then
pv.m.first(0) := '1';
else
pv.m.first(0) := '0';
end if;
pv.m.first(1) := pr.m.first(0);
-- Master Data Parity Error
if pr.m.state = pm_m_data then
if pr.m.fstate = pmf_read then
pv.m.perren(0) := '1';
elsif pr.m.fstate = pmf_fifo then
pv.m.detectperr(0) := '1';
end if;
else
pv.m.perren(0) := '0';
pv.m.detectperr(0) := '0';
end if;
pv.m.perren(1) := pr.m.perren(0);
pv.m.detectperr(1) := pr.m.detectperr(0);
if pr.conf(m_func).comm.perren = '1' and -- Parity error response bit[6] = 1
((pr.m.perren /= "00" and pr.po.perr = '0') -- Parity error is signaled by master on read
or (pr.m.detectperr(1) = '1' and pci.perr = '0')) then-- Parity error is signaled by target on write
pv.conf(m_func).stat.mdpe := '1';
pv.m.acc(pr.m.acc_sel).status(0) := '1';
end if;
-- PCI master latency timer
if (pr.m.framedel and not pr.po.frame) = '1' then
pv.m.ltimer := pr.conf(m_func).ltimer;
elsif pr.m.ltimer /= x"00" and pr.po.frame = '0' then
pv.m.ltimer := pr.m.ltimer - 1;
end if;
-- Devsel time out counter (and master abort signaling)
if pci.devsel = '0' then pv.m.devsel_asserted := '1'; end if;
if (pr.m.framedel and not pr.po.frame) = '1' then
pv.m.devsel_tout := "100";
pv.m.devsel_asserted := '0';
elsif pr.m.devsel_asserted = '1' then
pv.m.devsel_tout := "100";
elsif pr.m.devsel_tout /= "000" then
pv.m.devsel_tout := pr.m.devsel_tout - 1;
end if;
if (pr.m.devsel_tout = "000" and pr.m.devsel_asserted = '0') and pi.devsel = '1' and pr.m.state = pm_m_data then m_mabort := '1'; pv.conf(m_func).stat.rma := '1'; else m_mabort := '0'; end if; -- Master abort -- delayed mabort one cycle (to reduce pci.devsel timing path)
if pi.devsel = '1' and pi.stop = '0' and pr.m.state = pm_s_tar then m_tabort := '1'; pv.conf(m_func).stat.rta := '1'; else m_tabort := '0'; end if; -- Target abort
if (pr.m.state = pm_m_data and m_mabort = '1') or (pr.m.state = pm_s_tar and m_tabort = '1') then
pv.m.abort(0) := '1';
pv.m.abort(1) := m_tabort;
elsif pr.m.state = pm_s_tar or pr.m.state = pm_idle or pr.m.state = pm_dr_bus then
pv.m.abort := (others => '0');
end if;
if pr.m.abort(0) = '1' then pv.m.abort(0) := '0'; end if;
-- Access acknowledge and arbitration [AHB/DMA]
for i in 0 to 1*dma loop
if ((ms_acc_pending = '1' and i = acc_sel_ahb) or (md_acc_pending = '1' and i = acc_sel_dma)) and pr.m.acc(i).pending = '0' then
pv.pta_trans.msd_acc_ack(i) := atp_trans.msd_acc(i).pending;
pv.m.acc(i).pending := '1';
pv.m.acc(i).active := (others => '0');
pv.m.acc(i).done := (others => '0');
pv.m.acc(i).status := (others => '0');
pv.m.acc(i).first := '1';
pv.m.acc(i).addr := msd_acc(i).addr(31 downto 2) & "00";
pv.m.acc(i).func := conv_integer(msd_acc(i).func);
pv.m.acc(i).cmd := msd_acc(i).acctype;
pv.m.acc(i).mode := msd_acc(i).accmode;
pv.m.acc(i).fifo_index := msd_acc(i).index;
if msd_acc(i).acctype(0) = '1' then
pv.m.acc(i).length := (others => '0');
else
pv.m.acc(i).length := msd_acc(i).length;
end if;
if msd_acc(i).acctype = CONF_READ or msd_acc(i).acctype = CONF_WRITE then -- Config
if i = acc_sel_ahb then pv.m.acc(i).endianess := '1'; -- Endianess is not set for AHB slave
else pv.m.acc(i).endianess := msd_acc(i).endianess; end if; -- Endianess is set for DMA
pv.m.acc(i).addr := msd_acc(i).addr; -- PCI CONF address set in AHB slave
pv.m.acc(i).cbe := set_cbe_from_size_addr(msd_acc(i).size, msd_acc(i).offset(1 downto 0), '1'); -- Set CBE depending on AHB size and address
elsif msd_acc(i).acctype = IO_READ or msd_acc(i).acctype = IO_WRITE then -- IO
if i = acc_sel_ahb then pv.m.acc(i).endianess := pr.pta_trans.ca_twist; -- Endianess is not set for AHB slave
else pv.m.acc(i).endianess := msd_acc(i).endianess; end if; -- Endianess is set for DMA
pv.m.acc(i).addr(1 downto 0) := set_pci_io_byte_addr(msd_acc(i).offset(1 downto 0), msd_acc(i).size, pr.pta_trans.ca_twist); -- PCI IO used byte address
pv.m.acc(i).cbe := set_cbe_from_size_addr(msd_acc(i).size, msd_acc(i).offset(1 downto 0), pr.pta_trans.ca_twist); -- Set CBE depending on AHB size and address
else -- Mem
if i = acc_sel_ahb then pv.m.acc(i).endianess := pr.pta_trans.ca_twist; -- Endianess is not set for AHB slave
else pv.m.acc(i).endianess := msd_acc(i).endianess; end if; -- Endianess is set for DMA
pv.m.acc(i).cbe := set_cbe_from_size_addr(msd_acc(i).size, msd_acc(i).offset(1 downto 0), pr.pta_trans.ca_twist); -- Set CBE depending on AHB size and address
end if;
end if;
if pr.m.acc(i).pending = '1' and pr.m.acc(i).active(1) = '0' and pr.m.acc(i).done(0) = '1' and pr.m.acc(i).cmd(0) = '1' then -- Status pending
if pr.m.acc(i).done(2 downto 1) = "10" then
if (i = acc_sel_ahb and ms_fifo_pending(pr.m.acc(i).fifo_index) = '1') or (i = acc_sel_dma and md_fifo_pending(pr.m.acc(i).fifo_index) = '1') then
if pr.m.acc(i).fifo_index /= FIFO_COUNT-1 then pv.m.acc(i).fifo_index := pr.m.acc(i).fifo_index + 1;
else pv.m.acc(i).fifo_index := 0; end if;
pv.pta_trans.msd_fifo_ack(i)(pr.m.acc(i).fifo_index) := not pv.pta_trans.msd_fifo_ack(i)(pr.m.acc(i).fifo_index);
if (i = acc_sel_ahb and ms_fifo(pr.m.acc(i).fifo_index).lastf = '1') or (i = acc_sel_dma and md_fifo(pr.m.acc(i).fifo_index).lastf = '1') then
pv.m.acc(i).done(1) := '1';
end if;
end if;
elsif ((ms_acc_done = '0' and i = acc_sel_ahb) or (md_acc_done = '0' and i = acc_sel_dma)) then
pv.pta_trans.msd_acc_done(i).done := not pr.pta_trans.msd_acc_done(i).done;
pv.pta_trans.msd_acc_done(i).status(2 downto 0) := pr.m.acc(i).status;
if pr.m.acc(i).cmd = CONF_WRITE then pv.pta_trans.msd_acc_done(i).status(3) := '1'; -- Status(3) indicates CONF_WRITE
else pv.pta_trans.msd_acc_done(i).status(3) := '0'; end if;
pv.pta_trans.msd_acc_done(i).count := pr.m.acc(i).length;
pv.m.acc(i).pending := '0';
end if;
end if;
-- Access canceled
if pr.m.acc(i).pending = '1' and pr.m.acc(i).active = "10" and pr.m.acc(i).cmd(0) = '0' then
if ((ms_acc_cancel = '1' and i = acc_sel_ahb) or (md_acc_cancel = '1' and i = acc_sel_dma)) then
pv.m.acc(i).done(0) := '1';
pv.m.acc(i).active(1) := '0';
end if;
end if;
if pr.m.acc(i).pending = '1' and pr.m.acc(i).active(1) = '0' and pr.m.acc(i).done(0) = '1' and pr.m.acc(i).cmd(0) = '0' then -- Status pending
if pr.m.acc(i).done(1 downto 0) = "01" then
if ((ms_acc_cancel = '1' and i = acc_sel_ahb) or (md_acc_cancel = '1' and i = acc_sel_dma)) then
pv.m.acc(pr.m.acc_sel).done(1) := '1';
for j in 0 to FIFO_COUNT-1 loop
if (i = acc_sel_ahb and ms_fifo_empty(j) = '0') or (i = acc_sel_dma and md_fifo_empty(j) = '0') then
pv.pta_trans.msd_fifo(i)(j).pending(0) := not pr.pta_trans.msd_fifo(i)(j).pending(0);
else
pv.pta_trans.msd_fifo(i)(j).pending(0) := pr.pta_trans.msd_fifo(i)(j).pending(0);
end if;
end loop;
end if;
else
pv.pta_trans.msd_acc_cancel_ack(i)(0) := atp_trans.msd_acc_cancel(i);
pv.m.acc(i).pending := '0';
end if;
end if;
end loop;
-- control access switching
if atp_trans.mstswdis = '0' then
if (pr.m.acc_sel = acc_sel_dma and pr.m.acc(0).pending = '1' and pr.m.acc(0).done(0) = '0'
and ((pr.m.acc(0).cmd(0) and ms_fifo_pending(pr.m.acc(0).fifo_index))
or (not pr.m.acc(0).cmd(0) and ms_fifo_empty(pr.m.acc(0).fifo_index))) = '1')
or
(pr.m.acc_sel = acc_sel_ahb and pr.m.acc(1).pending = '1' and pr.m.acc(1).done(0) = '0'
and ((pr.m.acc(1).cmd(0) and md_fifo_pending(pr.m.acc(1).fifo_index))
or (not pr.m.acc(1).cmd(0) and md_fifo_empty(pr.m.acc(1).fifo_index))) = '1')
then
if pr.m.acc_cnt = MST_ACC_CNT then
pv.m.acc_switch := '1';
end if;
end if;
else
pv.m.acc_switch := '0';
end if;
acc_switch := pv.m.acc_switch;
if ((pr.m.acc(0).pending = '1' and pr.m.acc(0).done(0) = '0'
and ms_acc_cancel = '0' and pr.m.acc(1).active(0) = '0'
and ((pr.m.acc(0).cmd(0) and ms_fifo_pending(pr.m.acc(0).fifo_index))
or (not pr.m.acc(0).cmd(0) and ms_fifo_empty(pr.m.acc(0).fifo_index))) = '1')
and not (pr.m.acc_switch = '1' and pr.m.acc_sel = acc_sel_ahb))
or pr.m.acc(0).active(0) = '1' then
acc := pr.m.acc(0);
accdone := ms_acc_done;
acc_cancel := ms_acc_cancel;
pv.m.acc_sel := acc_sel_ahb;
fifo_pending := ms_fifo_pending;
fifo_empty := ms_fifo_empty;
fifo := ms_fifo;
if pr.m.acc_sel = acc_sel_dma then
pv.m.acc_cnt := 0;
pv.m.acc_switch := '0';
end if;
elsif (pr.m.acc(1).pending = '1' and pr.m.acc(1).done(0) = '0'
and md_acc_cancel = '0' and pr.m.acc(0).active(0) = '0'
and ((pr.m.acc(1).cmd(0) and md_fifo_pending(pr.m.acc(1).fifo_index))
or (not pr.m.acc(1).cmd(0) and md_fifo_empty(pr.m.acc(1).fifo_index))) = '1')
or pr.m.acc(1).active(0) = '1' then
acc := pr.m.acc(1);
accdone := md_acc_done;
acc_cancel := md_acc_cancel;
pv.m.acc_sel := acc_sel_dma;
fifo_pending := md_fifo_pending;
fifo_empty := md_fifo_empty;
fifo := md_fifo;
if pr.m.acc_sel = acc_sel_ahb then
pv.m.acc_cnt := 0;
pv.m.acc_switch := '0';
end if;
else
acc := pci_master_acc_none;
accdone := '0';
acc_cancel := '0';
pv.m.acc_sel := acc_sel_ahb;
fifo_pending := (others => '0');
fifo_empty := (others => '0');
fifo := ms_fifo;
pv.m.acc_cnt := 0;
pv.m.acc_switch := '0';
end if;
if acc.fifo_index /= FIFO_COUNT-1 then fifo_nindex := (acc.fifo_index + 1);
else fifo_nindex := 0; end if;
-- FIFO state machine
case pr.m.fstate is
when pmf_idle =>
pv.m.waitonstop := '0';
pv.m.done := '0';
pv.m.done_fifo := '0';
pv.m.done_trans := '0';
pv.m.term := (others => '0');
pv.m.preload := '0';
pv.m.preload_count := (others => '0');
pv.m.afull := '0';
pv.m.afullcnt := (others => '0');
if acc.pending = '1' then
pv.m.addr := acc.addr;
pv.m.twist := acc.endianess;
pv.m.cbe_cmd := acc.cmd;
pv.m.cbe_data := acc.cbe;
pv.m.burst := acc.mode(0);
pv.m.acc_cnt := 0;
if acc.cmd(0) = '1' then -- Write access
pv.m.fstate := pmf_fifo;
pv.m.fifo_addr := conv_std_logic_vector(acc.fifo_index, log2(FIFO_COUNT)) & fifo(acc.fifo_index).start; -- Set fifo start address
else -- Read access
pv.m.fstate := pmf_read;
end if;
pv.m.acc(pv.m.acc_sel).active := "11";
end if;
when pmf_fifo =>
pv.m.acc(pr.m.acc_sel).fifo_ren := fifo_pending(acc.fifo_index);
if pr.m.term = "00" and pr.m.last(0) = '0' and pr.m.done = '0' and (pr.m.cfifo(0).valid = '1' or pr.m.hold(0) = '1')
and m_mabort = '0' and pr.m.abort(0) = '0' then -- request bus if not: latency timer count out; last data phase; transfer done
m_request := '1';
end if;
if (fifo_pending(acc.fifo_index) = '1') and pr.m.done = '0' then -- preload data
pv.m.preload := '1';
pv.m.hold_fifo := '0';
end if;
if ((pi.trdy or pi.irdy) = '0' and (pr.m.state = pm_m_data or pr.m.state = pm_turn_ar or pr.m.state = pm_s_tar)) or pr.m.preload = '1' or (pr.m.abort(0)) = '1' then
if ((pi.trdy or pi.irdy) = '0' and (pr.m.state = pm_m_data or pr.m.state = pm_turn_ar or pr.m.state = pm_s_tar)) or (pr.m.abort(0)) = '1' then
pv.m.cfifo(0) := pr.m.cfifo(1); pv.m.cfifo(1) := pr.m.cfifo(2); -- Preload master core fifo
elsif pr.m.preload = '1' then
if pr.m.cfifo(0).valid = '0' then
pv.m.cfifo(0) := pr.m.cfifo(1); pv.m.cfifo(1) := pr.m.cfifo(2); -- Preload master core fifo
elsif pr.m.cfifo(0).valid = '1' and pr.m.cfifo(1).valid = '0' then
pv.m.cfifo(1) := pr.m.cfifo(2); -- Preload master core fifo
end if;
end if;
if pr.m.acc(0).active(0) = '1' then
pv.m.cfifo(2).data := byte_twist(ms_fifoo_atp.data, acc.endianess); -- shifting in data from backend fifo
elsif pr.m.acc(1).active(0) = '1' then
pv.m.cfifo(2).data := byte_twist(md_fifoo_dtp.data, acc.endianess); -- shifting in data from DMA fifo
end if;
if pr.m.done_fifo = '0' and fifo_pending(acc.fifo_index) = '1' then
if pr.m.fifo_addr(FIFO_DEPTH-1 downto 0) = fifo(acc.fifo_index).stop then -- Mark last word
if pr.m.acc_cnt /= MST_ACC_CNT then pv.m.acc_cnt := pr.m.acc_cnt + 1; end if; -- Switch DAM/AHB-slave after MST_ACC_CNT FIFOs
pv.m.fifo_switch := '1';
pv.m.acc(pr.m.acc_sel).fifo_index := fifo_nindex;
pv.pta_trans.msd_fifo_ack(pr.m.acc_sel)(acc.fifo_index) := fifo(acc.fifo_index).pending(RAM_LATENCY); -- Ack the fifo (done using this data)
pv.m.fifo_addr := conv_std_logic_vector(fifo_nindex, log2(FIFO_COUNT)) & zero32(FIFO_DEPTH-1 downto 0); -- New fifo address (should be ok with [index & zero] or & fifo(fifo_nindex).start)
if fifo_pending(fifo_nindex) = '0' or acc_switch = '1' then -- If no fifo pending => idle
pv.m.cfifo(2).last := '1';
pv.m.done_fifo := '1';
else
pv.m.cfifo(2).hold := '0';
pv.m.cfifo(2).last := '0';
end if;
if fifo(acc.fifo_index).lastf = '1' then -- Last fifo, transfer is done
pv.m.cfifo(2).last := '1';
pv.m.done_fifo := '1';
pv.m.done_trans := '1';
end if;
else
pv.m.cfifo(2).hold := '0';
pv.m.cfifo(2).last := '0';
if pr.m.done_fifo = '0' and fifo_pending(acc.fifo_index) = '1' then
pv.m.fifo_addr(FIFO_DEPTH-1 downto 0) := pr.m.fifo_addr(FIFO_DEPTH-1 downto 0) + 1; -- inc backend fifo address
end if;
end if;
else
pv.m.cfifo(2).hold := '0';
pv.m.cfifo(2).last := '0';
end if;
pv.m.cfifo(2).stlast := '0';
if fifo_pending(acc.fifo_index) = '1' and pr.m.done_fifo = '0' then -- Adding valid data to CFIFO
pv.m.cfifo(2).valid := '1';
else
pv.m.cfifo(2).valid := '0';
pv.m.cfifo(2).last := '0';
pv.m.cfifo(2).stlast := '0';
pv.m.cfifo(2).hold := '0';
end if;
end if;
if (pv.m.cfifo(0).valid = '1' and pv.m.cfifo(1).valid = '1' and pv.m.cfifo(2).valid = '1')
or (pv.m.cfifo(0).valid = '1' and pr.m.done_fifo = '1' and not (pv.m.cfifo(1).valid = '0' and pv.m.cfifo(2).valid = '1')) then
pv.m.preload := '0';
if pr.m.cfifo(0).hold = '1' and pv.m.cfifo(1).valid = '1' then pv.m.cfifo(0).hold := '0'; end if;
if pr.m.cfifo(1).hold = '1' and pv.m.cfifo(2).valid = '1' then pv.m.cfifo(1).hold := '0'; end if;
end if;
if pr.m.abort(0) = '1' then -- Empty core FIFO on master/target abort
for i in 0 to 2 loop
pv.m.cfifo(i).valid := '0';
end loop;
end if;
if ((pi.trdy or pi.irdy) = '0' and (pr.m.state = pm_m_data or pr.m.state = pm_turn_ar or pr.m.state = pm_s_tar)) or (pr.m.abort(0)) = '1' then
pv.m.addr := pr.m.addr + 4;
if acc.mode(1) = '1' and pr.m.abort(0) = '0' then -- Use acc.length
pv.m.acc(pr.m.acc_sel).length := pr.m.acc(pr.m.acc_sel).length + 1;
end if;
if pr.m.last(1) = '1' or pr.m.abort(0) = '1' then pv.m.done := '1'; end if; -- Last data phase is done => transfer done
-- Signal ERROR to AHB
if pr.m.abort(0) = '1' then
pv.m.acc(pr.m.acc_sel).done(2) := '1'; -- Error
pv.m.acc(pr.m.acc_sel).status(2 downto 1) := (not pr.m.abort(1) or m_mabort) & (pr.m.abort(1) or m_tabort); -- Error type: Master abort, Target abort, (PAR error)
end if;
end if;
if (pr.m.state = pm_s_tar or pr.m.state = pm_turn_ar) then
pv.m.term := (others => '0'); m_request := '0';
end if;
if pr.m.done = '1' then
pv.m.fstate := pmf_idle;
pv.m.acc(pr.m.acc_sel).active(0) := '0';
pv.m.acc(pr.m.acc_sel).addr := pr.m.addr;
if pr.m.done_trans = '1' or acc.done(2) = '1' then
pv.m.acc(pr.m.acc_sel).active(1) := '0';
pv.m.acc(pr.m.acc_sel).done(0) := '1';
if pr.m.done_trans = '1' then pv.m.acc(pr.m.acc_sel).done(1) := '1'; end if;
if accdone = '0' and pr.m.done_trans = '1' then
pv.pta_trans.msd_acc_done(pr.m.acc_sel).done := not pr.pta_trans.msd_acc_done(pr.m.acc_sel).done;
pv.pta_trans.msd_acc_done(pr.m.acc_sel).status(2 downto 0) := pv.m.acc(pr.m.acc_sel).status; -- use pv.. (par error detection)
if pr.m.acc(pr.m.acc_sel).cmd = CONF_WRITE then pv.pta_trans.msd_acc_done(pr.m.acc_sel).status(3) := '1'; -- Status(3) indicates CONF_WRITE
else pv.pta_trans.msd_acc_done(pr.m.acc_sel).status(3) := '0'; end if;
pv.pta_trans.msd_acc_done(pr.m.acc_sel).count := pr.m.acc(pr.m.acc_sel).length;
pv.m.acc(pr.m.acc_sel).pending := '0';
end if;
end if;
end if;
if pi.stop = '0' and pr.m.state /= pm_idle then m_request := '0'; end if; -- Second deasserted req cycle
when pmf_read =>
if pr.m.term(0) = '0' and m_mabort = '0' and pr.m.abort(0) = '0' and (pi.stop = '1' or pr.m.first(0) = '1') and pr.m.waitonstop = '0' then -- request bus if not: latency timer count out; no empty fifo to fill
m_request := '1'; -- request should be deasserted earlier
end if;
if pr.m.burst = '0' then -- Single access, only one data phase
if pr.po.frame = '0' then
pv.m.term(0) := '1';
elsif (pi.trdy and not pi.stop) = '1' then -- retry
pv.m.term := (others => '0');
end if;
end if;
if (pi.irdy or pi.trdy) = '0' and (pr.m.state = pm_m_data or pr.m.state = pm_s_tar or pr.m.state = pm_turn_ar)then
pv.m.addr := pr.m.addr + 4;
if acc.mode(1) = '1' then -- Use acc.length
pv.m.acc(pr.m.acc_sel).length := pr.m.acc(pr.m.acc_sel).length - 1;
end if;
if pr.m.addr(AHB_FIFO_BITS) = ones32(FIFO_DEPTH-1 downto 0) or pr.m.burst = '0' or (acc.mode(1) = '1' and acc.length = x"0000") then
if pr.m.acc_cnt /= MST_ACC_CNT then pv.m.acc_cnt := pr.m.acc_cnt + 1; end if; -- Switch DMA/AHB-slave after MST_ACC_CNT FIFOs
pv.m.fifo_switch := '1';
pv.m.acc(pr.m.acc_sel).fifo_index := fifo_nindex;
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).pending(0) := not pr.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).pending(0);
pv.m.acc(pr.m.acc_sel).first := '0';
if acc.first = '1' then
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).firstf := '1';
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).start := acc.addr(AHB_FIFO_BITS);
else
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).firstf := '0';
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).start := (others => '0');
end if;
if (acc.mode(1) = '1' and acc.length = x"0000") or pr.m.burst = '0' then
pv.m.acc(pr.m.acc_sel).done(0) := '1';
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).lastf := '1';
else
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).lastf := '0';
end if;
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).status := (others => '0');
end if;
pv.m.acc(pr.m.acc_sel).fifo_wen := '1';
pv.m.fifo_addr := conv_std_logic_vector(acc.fifo_index, log2(FIFO_COUNT)) & pr.m.addr(AHB_FIFO_BITS);
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).stop := pv.m.fifo_addr(FIFO_DEPTH-1 downto 0);
if ((fifo_empty(fifo_nindex) = '0' or acc_switch = '1') and pr.m.fifo_addr(FIFO_DEPTH-1 downto 0) = conv_std_logic_vector((conv_integer(ones32(FIFO_DEPTH-1 downto 0)) - 3), FIFO_DEPTH)) -- terminate access when 3 words left to store in FIFO or 3 word left i transfer
or (acc.mode(1) = '1' and acc.length = x"0002") then
pv.m.term(0) := '1';
pv.m.afull := '1'; -- almost full
pv.m.afullcnt := "00"; -- reset full counter
end if;
if pr.m.afull = '1' then -- when transfer is terminated, count data phases (1 - 3)
if pr.m.afullcnt = "01" then
pv.m.afullcnt := (others => '0');
pv.m.afull := '0';
else
pv.m.afullcnt := pr.m.afullcnt + 1;
end if;
end if;
end if;
if (pr.m.afull = '1' and pr.m.afullcnt = "01" and pr.m.first(0) = '1' and pr.m.state = pm_addr)
or (pr.m.afull = '1' and pr.m.afullcnt = "00" and pr.m.state = pm_m_data) -- terminate first or second data phase depending on space left in fifo
or (acc.mode(1) = '1' and ((acc.length = x"0000" and pr.m.state = pm_addr) or (acc.length = x"0001" and pr.m.state = pm_m_data)))then pv.m.term(0) := '1'; end if; -- DMA 1 or 2 word to complete transfer
if pr.m.term(0) = '1' and fifo_empty(acc.fifo_index) = '1' and (pr.m.state = pm_idle or pr.m.state = pm_dr_bus) then
pv.m.term := (others => '0'); -- Start new access when a fifo becomes empty
end if;
if pr.m.state = pm_s_tar and fifo_empty(acc.fifo_index) = '1' and pv.m.fifo_switch = '0' then pv.m.term(0) := '0'; end if; -- If disconnected, rerequest the bus if fifo is available (but not if fifo switch)
if (pr.m.state = pm_m_data or pr.m.state = pm_turn_ar or pr.m.state = pm_s_tar) and pi.irdy = '0' and (pi.trdy = '0' or (pi.stop = '0' and pi.devsel = '1')) then pv.m.first_word := '0'; end if;
if (acc.done(0) = '1' and (pv.m.first_word = '0' or acc.done(2) = '1'))
or ((pr.m.acc_switch = '1' or fifo_empty(acc.fifo_index) = '0') and pr.m.fifo_switch = '1') then -- Transfer read is done (or no empty fifo), cancelled or access arbitration
m_request := '0';
pv.m.term(0) := '1';
if ((pi.frame and pi.irdy) = '1' and (pr.m.state = pm_idle or pr.m.state = pm_dr_bus)) then
pv.m.fstate := pmf_idle;
pv.m.term := (others => '0');
pv.m.acc(pr.m.acc_sel).active(0) := '0';
pv.m.acc(pr.m.acc_sel).addr := pr.m.addr;
if acc.done(0) = '1' then
pv.m.acc(pr.m.acc_sel).active(1) := '0';
if acc.mode(2) = '0' or acc.mode(0) = '0' then
pv.m.acc(pr.m.acc_sel).pending := '0';
pv.m.acc(pr.m.acc_sel).done(1) := '1';
else
pv.m.acc(pr.m.acc_sel).done(1) := '0';
end if;
end if;
end if;
end if;
-- Access canceled
if acc_cancel = '1' then
pv.m.acc(pr.m.acc_sel).done(0) := '1';
end if;
-- Access aborted by PCI error
if pr.m.abort(0) = '1' and pr.m.acc(pr.m.acc_sel).done(2) = '0' then
pv.m.acc(pr.m.acc_sel).done(0) := '1';
pv.m.acc(pr.m.acc_sel).done(2) := '1'; -- error
pv.m.acc(pr.m.acc_sel).fifo_index := fifo_nindex;
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).pending(0) := not pr.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).pending(0);
pv.m.acc(pr.m.acc_sel).first := '0';
if acc.first = '1' then
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).firstf := '1';
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).start := acc.addr(AHB_FIFO_BITS);
else
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).firstf := '0';
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).start := (others => '0');
end if;
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).lastf := '1';
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).status := '0' & (not pr.m.abort(1) or m_mabort) & (pr.m.abort(1) or m_tabort) & '0'; -- Error type: Master abort, Target abort, (PAR error)
pv.pta_trans.msd_fifo(pr.m.acc_sel)(acc.fifo_index).stop := pr.m.addr(AHB_FIFO_BITS);
end if;
-- Set PAR error status
if pr.m.fifo_switch = '1' then
pv.pta_trans.msd_fifo(pr.m.acc_sel)(conv_integer(pr.m.fifo_addr(pr.m.fifo_addr'left downto FIFO_DEPTH))).status(0) := pv.m.acc(pr.m.acc_sel).status(0);
pv.m.acc(pr.m.acc_sel).status(0) := '0';
end if;
when others =>
end case;
-- New (Master state machine is moed to PHY)
if pr.m.state = pm_addr then pv.m.first_word := '1'; end if;
end if; -- PCI master enabled
-- --------------------------------------------------------------------------------
-- PCI target defaults
-- --------------------------------------------------------------------------------
-- Defaults
t_hit := '0'; t_chit := '0';
pv.t.cur_acc(0).newacc := '0';
pv.t.hold_reset := '1';
t_cad := (others => '0');
pv.t.first_word := '0';
t_ready := '0'; t_retry := '0';
t_abort := pr.t.stop;
t_acc_read := '1';
t_acc_burst := '1';
t_acc_type := "00";
t_acc_impcfgreg := '1';
-- FIFO (Block RAM enable(read)/write)
pv.t.atp.ctrl.en := '0'; -- read enable
pv.t.pta.ctrl.en := '0'; -- write enable
pv.t.pta.ctrl.data := byte_twist(pi.ad, pr.pta_trans.ca_twist);
tm_acc_pending := pr.pta_trans.tm_acc.pending xor atp_trans.tm_acc_ack;
tm_acc_cancel := pr.pta_trans.tm_acc_cancel xor atp_trans.tm_acc_cancel_ack(RAM_LATENCY);
tm_acc_done := pr.pta_trans.tm_acc_done_ack xor atp_trans.tm_acc_done.done;
for i in 0 to FIFO_COUNT-1 loop
tm_fifo_pending(i) := atp_trans.tm_fifo(i).pending(RAM_LATENCY) xor pr.pta_trans.tm_fifo_ack(i);
tm_fifo_empty(i) := not (pr.pta_trans.tm_fifo(i).pending(0) xor atp_trans.tm_fifo_ack(i));
pv.pta_trans.tm_fifo(i).pending(1) := pr.pta_trans.tm_fifo(i).pending(0);
pv.pta_trans.tm_fifo(i).pending(2) := pr.pta_trans.tm_fifo(i).pending(1);
end loop;
tm_fifo := ar.atp_trans.tm_fifo;
accbufindex := 0;
-- Not used
if tm_acc_done = '1' then
pv.pta_trans.tm_acc_done_ack := atp_trans.tm_acc_done.done;
end if;
-- --------------------------------------------------------------------------------
-- PCI target core
-- --------------------------------------------------------------------------------
if target /= 0 then -- PCI target enabled
-- Target latency counter
if pv.t.state = pt_s_data and pr.po.trdy = '1' and pr.t.lcount /= "111" then
pv.t.lcount := pr.t.lcount + 1;
elsif pr.po.trdy = '0' then
pv.t.lcount := (others => '0');
end if;
-- select next fifo
if pr.t.cur_acc(0).read = '1' then
if pr.t.atp.index /= FIFO_COUNT-1 then t_index := (pr.t.atp.index + 1);
else t_index := 0; end if;
else
if pr.t.pta.index /= FIFO_COUNT-1 then t_index := (pr.t.pta.index + 1);
else t_index := 0; end if;
end if;
-- PCI BAR address matching
t_bar := (others => '0'); t_func := 0;
for j in 0 to multifunc loop
for i in 0 to 5 loop
if (pi.ad(31 downto barminsize) and pr.conf(j).bar_mask(i)(31 downto barminsize)) =
(pr.conf(j).bar(i)(31 downto barminsize) and pr.conf(j).bar_mask(i)(31 downto barminsize)) and
pr.conf(j).bar_mask(i)(31) = '1' then
if pr.conf(j).bar_mask(i)(0) = '0' and (pi.cbe = MEM_READ or pi.cbe = MEM_R_MULT or pi.cbe = MEM_R_LINE
or pi.cbe = MEM_WRITE or pi.cbe = MEM_W_INV) then
t_hit := pr.conf(j).comm.memen; -- Only hit if memory access is enabled
t_bar(i) := '1';
t_func := j;
elsif pr.conf(j).bar_mask(i)(0) = '1' and (pi.cbe = IO_READ or pi.cbe = IO_WRITE) then
t_hit := pr.conf(j).comm.ioen; -- Only hit if io access is enabled
t_bar(i) := '1';
t_func := j;
end if;
end if;
end loop;
end loop;
-- Configuration hit when IDSEL or self config (AD[31:11]=0 => no IDSEL) and in host slot
if ((pi.idsel = '1' or (pi.ad(31 downto 11) = zero32(31 downto 11) and pi.host = '0')) -- IDSEL asserted
and (pi.cbe = CONF_READ or pi.cbe = CONF_WRITE)) and pi.ad(1 downto 0) = "00" -- Command = config read or write, Type = 0
and pi.ad(10 downto 8) <= conv_std_logic_vector(multifunc, 3) then -- Respond to implemented function
t_chit := '1';
end if;
-- Read prefetch discard timer
if atp_trans.pa_discardtout_rst = '1' then
pv.pta_trans.pa_discardtout := '0';
end if;
if pr.t.cur_acc(0).pending = '1' and pr.t.discardtimeren = '1' then
if pr.t.discardtimer = x"0000" then
if pr.t.state = pt_idle then
pv.pta_trans.pa_discardtout := '1';
pv.t.cur_acc(0).pending := '0';
pv.t.cur_acc(0).newacc := '1';
pv.t.cur_acc(0).oldburst := pr.t.cur_acc(0).burst;
end if;
else
pv.t.discardtimer := pr.t.discardtimer - 1;
end if;
end if;
-- Access buffer
if tm_acc_pending = '0' and pr.t.accbuf(0).pending = '1' then
pv.pta_trans.tm_acc := pr.t.accbuf(0);
pv.pta_trans.tm_acc.pending := not pr.pta_trans.tm_acc.pending;
pv.t.accbuf(0) := pr.t.accbuf(1);
pv.t.accbuf(1) := pr.t.accbuf(2);
pv.t.accbuf(2) := pr.t.accbuf(3);
pv.t.accbuf(3).pending := '0';
end if;
pv.pciinten := (others => oeoff);
for i in 0 to 3 loop
if i <= multifunc then
pv.conf(i).stat.intsta := conv_std_logic(pciinten(i) /= oeoff);
if pr.conf(i).comm.intdis = '0' then
pv.pciinten(i) := pciinten(i);
end if;
else
pv.conf(0).stat.intsta := conv_std_logic(pciinten(i) /= oeoff);
if pr.conf(0).comm.intdis = '0' then
pv.pciinten(i) := pciinten(i);
end if;
end if;
end loop;
if multiint = 0 then
if oeoff = '1' then
pciinten_pad(0) <= andv(pr.pciinten);
else
pciinten_pad(0) <= orv(pr.pciinten);
end if;
pciinten_pad(3 downto 1) <= (others => oeoff);
else
pciinten_pad <= pr.pciinten;
end if;
-- PCI Configuration Space Header
conf_func := 0;
if conv_integer(pr.t.cur_acc(0).addr(10 downto 8)) <= multifunc then
conf_func := conv_integer(pr.t.cur_acc(0).addr(10 downto 8));
end if;
-- read
if pr.t.cur_acc(0).impcfgreg = '1' then
if pr.t.cur_acc(0).acc_type(0) = '0' then
case pr.t.conf_addr is
when "0000" => -- Device and Vendor ID
t_cad := conv_std_logic_vector(deviceid_vector(conf_func),16) & conv_std_logic_vector(vendorid,16);
when "0001" => -- Status and Command
t_cad := pr.conf(conf_func).stat.dpe & pr.conf(conf_func).stat.sse & pr.conf(conf_func).stat.rma & pr.conf(conf_func).stat.rta &
pr.conf(conf_func).stat.sta & "01" & pr.conf(conf_func).stat.mdpe & "00"& pr.pci66(1) &
"1"& pr.conf(conf_func).stat.intsta &"000" &
"00000" & pr.conf(conf_func).comm.intdis & "0" & pr.conf(conf_func).comm.serren & "0" & pr.conf(conf_func).comm.perren & "0" &
pr.conf(conf_func).comm.mwien & "0" & pr.conf(conf_func).comm.msten & pr.conf(conf_func).comm.memen & pr.conf(conf_func).comm.ioen;
when "0010" => -- Class Code and Revision ID
t_cad := conv_std_logic_vector(classcode_vector(conf_func),24) & conv_std_logic_vector(revisionid_vector(conf_func),8);
when "0011" => -- BIST, Header Type, Latency Timer and Cache Line Size
t_cad := "00000000" & conv_std_logic(multifunc /= 0) & "0000000" & pr.conf(conf_func).ltimer & "00000000";
when "0100" => -- BAR0
t_cad := pr.conf(conf_func).bar(0);
--t_cad(3) := bar_prefetch(0);
t_cad(3) := pr.conf(conf_func).bar_mask(0)(3);
t_cad(0) := pr.conf(conf_func).bar_mask(0)(0);
when "0101" => -- BAR1
t_cad := pr.conf(conf_func).bar(1);
--t_cad(3) := bar_prefetch(1);
t_cad(3) := pr.conf(conf_func).bar_mask(1)(3);
t_cad(0) := pr.conf(conf_func).bar_mask(1)(0);
when "0110" => -- BAR2
t_cad := pr.conf(conf_func).bar(2);
--t_cad(3) := bar_prefetch(2);
t_cad(3) := pr.conf(conf_func).bar_mask(2)(3);
t_cad(0) := pr.conf(conf_func).bar_mask(2)(0);
when "0111" => -- BAR3
t_cad := pr.conf(conf_func).bar(3);
--t_cad(3) := bar_prefetch(3);
t_cad(3) := pr.conf(conf_func).bar_mask(3)(3);
t_cad(0) := pr.conf(conf_func).bar_mask(3)(0);
when "1000" => -- BAR4
t_cad := pr.conf(conf_func).bar(4);
--t_cad(3) := bar_prefetch(4);
t_cad(3) := pr.conf(conf_func).bar_mask(4)(3);
t_cad(0) := pr.conf(conf_func).bar_mask(4)(0);
when "1001" => -- BAR5
t_cad := pr.conf(conf_func).bar(5);
--t_cad(3) := bar_prefetch(5);
t_cad(3) := pr.conf(conf_func).bar_mask(5)(3);
t_cad(0) := pr.conf(conf_func).bar_mask(5)(0);
when "1010" => -- Cardbus CIS Pointer
t_cad := (others => '0');
when "1011" => -- Subsystem ID and Subsystem Vendor ID
t_cad := (others => '0');
when "1100" => -- Expansion ROM Base Address
t_cad := (others => '0');
when "1101" => -- Reserved and Capabillities Pointer
t_cad := (others => '0');
t_cad(7 downto 0) := conv_std_logic_vector(cap_pointer_vector(conf_func), 8);
when "1110" => -- Reserved
t_cad := (others => '0');
when "1111" => -- Max_Lat, Min_Gnt, Interrupt Pin and Interrupt Line
t_cad := x"00" & x"00" & (x"0"&"0"&conv_std_logic_vector(deviceirq_vector(conf_func), 3)) & pr.conf(conf_func).iline;
when others =>
t_cad := (others => '0');
end case;
else -- Mapping register
case pr.t.conf_addr is
when "0000" =>
t_cad := x"0040" & conv_std_logic_vector(ext_cap_pointer_vector(conf_func), 8) & x"09";
when "0001" =>
t_cad := pr.conf(conf_func).pta_map(0);
when "0010" =>
t_cad := pr.conf(conf_func).pta_map(1);
when "0011" =>
t_cad := pr.conf(conf_func).pta_map(2);
when "0100" =>
t_cad := pr.conf(conf_func).pta_map(3);
when "0101" =>
t_cad := pr.conf(conf_func).pta_map(4);
when "0110" =>
t_cad := pr.conf(conf_func).pta_map(5);
when "0111" =>
t_cad := pr.conf(conf_func).cfg_map;
when "1000" =>
t_cad := conv_std_logic_vector(iobase, 12) & x"0000"&"00"&pr.t.discardtimeren&pr.pta_trans.ca_twist; -- AHB IO base address (used to find P&P information) and byte twisting
when "1001" =>
t_cad := pr.conf(conf_func).bar_mask(0);
when "1010" =>
t_cad := pr.conf(conf_func).bar_mask(1);
when "1011" =>
t_cad := pr.conf(conf_func).bar_mask(2);
when "1100" =>
t_cad := pr.conf(conf_func).bar_mask(3);
when "1101" =>
t_cad := pr.conf(conf_func).bar_mask(4);
when "1110" =>
t_cad := pr.conf(conf_func).bar_mask(5);
when "1111" =>
t_cad := pr.t.saverfifo & "000" & x"000" & pr.t.blenmask; -- Burst lenght boundary mask
when others =>
t_cad := (others => '0');
end case;
end if;
end if;
-- write
if (pi.irdy or pi.trdy) = '0' and pr.t.cur_acc(0).acc_type(1) = '1' and pr.t.cur_acc(0).impcfgreg = '1' and
pr.t.cur_acc(0).read = '0' and pr.t.fstate = ptf_cwrite then
-- Support for all CBE combinations
if pi.cbe(3) = '0' then t_cad(31 downto 24) := pi.ad(31 downto 24); end if;
if pi.cbe(2) = '0' then t_cad(23 downto 16) := pi.ad(23 downto 16); end if;
if pi.cbe(1) = '0' then t_cad(15 downto 8) := pi.ad(15 downto 8); end if;
if pi.cbe(0) = '0' then t_cad( 7 downto 0) := pi.ad( 7 downto 0); end if;
if pr.t.cur_acc(0).acc_type(0) = '0'then
case pr.t.conf_addr is
--when "0000" => -- Device and Vendor ID
when "0001" => -- Status and Command
-- Command register
pv.conf(conf_func).comm.ioen := t_cad(0);
pv.conf(conf_func).comm.memen := t_cad(1);
if MASTER = 1 then
pv.conf(conf_func).comm.msten := t_cad(2);
pv.pta_trans.ca_pcimsten(conf_func) := pv.conf(conf_func).comm.msten;
end if;
pv.conf(conf_func).comm.mwien := t_cad(4);
pv.conf(conf_func).comm.perren := t_cad(6);
pv.conf(conf_func).comm.serren := t_cad(8);
pv.conf(conf_func).comm.intdis := t_cad(10);
-- Status register, sticky bits
pv.conf(conf_func).stat.mdpe := pr.conf(conf_func).stat.mdpe and not t_cad(24);
pv.conf(conf_func).stat.sta := pr.conf(conf_func).stat.sta and not t_cad(27);
pv.conf(conf_func).stat.rta := pr.conf(conf_func).stat.rta and not t_cad(28);
pv.conf(conf_func).stat.rma := pr.conf(conf_func).stat.rma and not t_cad(29);
pv.conf(conf_func).stat.sse := pr.conf(conf_func).stat.sse and not t_cad(30);
pv.conf(conf_func).stat.dpe := pr.conf(conf_func).stat.dpe and not t_cad(31);
--when "0010" => -- Class Code and Revision ID
when "0011" => -- BIST, Header Type, Latency Timer and Cache Line Size
pv.conf(conf_func).ltimer := t_cad(15 downto 8);
when "0100" => -- BAR0
if bar_size(conf_func)(0) /= 0 then
t_cad := t_cad and pr.conf(conf_func).bar_mask(0);
pv.conf(conf_func).bar(0)(31 downto barminsize) := t_cad(31 downto barminsize);
end if;
when "0101" => -- BAR1
if bar_size(conf_func)(1) /= 0 then
t_cad := t_cad and pr.conf(conf_func).bar_mask(1);
pv.conf(conf_func).bar(1)(31 downto barminsize) := t_cad(31 downto barminsize);
end if;
when "0110" => -- BAR2
if bar_size(conf_func)(2) /= 0 then
t_cad := t_cad and pr.conf(conf_func).bar_mask(2);
pv.conf(conf_func).bar(2)(31 downto barminsize) := t_cad(31 downto barminsize);
end if;
when "0111" => -- BAR3
if bar_size(conf_func)(3) /= 0 then
t_cad := t_cad and pr.conf(conf_func).bar_mask(3);
pv.conf(conf_func).bar(3)(31 downto barminsize) := t_cad(31 downto barminsize);
end if;
when "1000" => -- BAR4
if bar_size(conf_func)(4) /= 0 then
t_cad := t_cad and pr.conf(conf_func).bar_mask(4);
pv.conf(conf_func).bar(4)(31 downto barminsize) := t_cad(31 downto barminsize);
end if;
when "1001" => -- BAR5
if bar_size(conf_func)(5) /= 0 then
t_cad := t_cad and pr.conf(conf_func).bar_mask(5);
pv.conf(conf_func).bar(5)(31 downto barminsize) := t_cad(31 downto barminsize);
end if;
--when "1010" => -- Cardbus CIS Pointer
--when "1011" => -- Subsystem ID and Subsystem Vendor ID
--when "1100" => -- Expansion ROM Base Address
--when "1101" => -- Reserved and Capabillities Pointer
--when "1110" => -- Reserved
when "1111" => -- Max_Lat, Min_Gnt, Interrupt Pin and Interrupt Line
pv.conf(conf_func).iline := t_cad(7 downto 0);
when others =>
end case;
else -- Mapping registers
case pr.t.conf_addr is
when "0001" =>
if bar_size(conf_func)(0) /= 0 then
t_cad := t_cad and pr.conf(conf_func).bar_mask(0);
pv.conf(conf_func).pta_map(0)(31 downto barminsize) := t_cad(31 downto barminsize);
end if;
when "0010" =>
if bar_size(conf_func)(1) /= 0 then
t_cad := t_cad and pr.conf(conf_func).bar_mask(1);
pv.conf(conf_func).pta_map(1)(31 downto barminsize) := t_cad(31 downto barminsize);
end if;
when "0011" =>
if bar_size(conf_func)(2) /= 0 then
t_cad := t_cad and pr.conf(conf_func).bar_mask(2);
pv.conf(conf_func).pta_map(2)(31 downto barminsize) := t_cad(31 downto barminsize);
end if;
when "0100" =>
if bar_size(conf_func)(3) /= 0 then
t_cad := t_cad and pr.conf(conf_func).bar_mask(3);
pv.conf(conf_func).pta_map(3)(31 downto barminsize) := t_cad(31 downto barminsize);
end if;
when "0101" =>
if bar_size(conf_func)(4) /= 0 then
t_cad := t_cad and pr.conf(conf_func).bar_mask(4);
pv.conf(conf_func).pta_map(4)(31 downto barminsize) := t_cad(31 downto barminsize);
end if;
when "0110" =>
if bar_size(conf_func)(5) /= 0 then
t_cad := t_cad and pr.conf(conf_func).bar_mask(5);
pv.conf(conf_func).pta_map(5)(31 downto barminsize) := t_cad(31 downto barminsize);
end if;
when "0111" =>
pv.conf(conf_func).cfg_map(31 downto 8) := t_cad(31 downto 8);
when "1000" =>
pv.t.discardtimeren := t_cad(1);
pv.pta_trans.ca_twist := t_cad(0);
when "1001" =>
if bar_size(conf_func)(0) /= 0 then
pv.conf(conf_func).bar_mask(0)(31 downto barminsize) := t_cad(31 downto barminsize);
pv.conf(conf_func).bar_mask(0)(3) := t_cad(3);
pv.conf(conf_func).bar_mask(0)(0) := t_cad(0);
end if;
when "1010" =>
if bar_size(conf_func)(1) /= 0 then
pv.conf(conf_func).bar_mask(1)(31 downto barminsize) := t_cad(31 downto barminsize);
pv.conf(conf_func).bar_mask(1)(3) := t_cad(3);
pv.conf(conf_func).bar_mask(1)(0) := t_cad(0);
end if;
when "1011" =>
if bar_size(conf_func)(2) /= 0 then
pv.conf(conf_func).bar_mask(2)(31 downto barminsize) := t_cad(31 downto barminsize);
pv.conf(conf_func).bar_mask(2)(3) := t_cad(3);
pv.conf(conf_func).bar_mask(2)(0) := t_cad(0);
end if;
when "1100" =>
if bar_size(conf_func)(3) /= 0 then
pv.conf(conf_func).bar_mask(3)(31 downto barminsize) := t_cad(31 downto barminsize);
pv.conf(conf_func).bar_mask(3)(3) := t_cad(3);
pv.conf(conf_func).bar_mask(3)(0) := t_cad(0);
end if;
when "1101" =>
if bar_size(conf_func)(4) /= 0 then
pv.conf(conf_func).bar_mask(4)(31 downto barminsize) := t_cad(31 downto barminsize);
pv.conf(conf_func).bar_mask(4)(3) := t_cad(3);
pv.conf(conf_func).bar_mask(4)(0) := t_cad(0);
end if;
when "1110" =>
if bar_size(conf_func)(5) /= 0 then
pv.conf(conf_func).bar_mask(5)(31 downto barminsize) := t_cad(31 downto barminsize);
pv.conf(conf_func).bar_mask(5)(3) := t_cad(3);
pv.conf(conf_func).bar_mask(5)(0) := t_cad(0);
end if;
when "1111" =>
pv.t.blenmask(blenmask_size(barminsize) downto FIFO_DEPTH) := t_cad(blenmask_size(barminsize) downto FIFO_DEPTH);
pv.t.saverfifo := t_cad(31);
when others =>
end case;
end if;
end if;
-- FIFO State machine
case pr.t.fstate is
when ptf_idle =>
pv.t.first := (others => '1');
pv.t.preload := '0';
pv.t.preload_count := (others => '0');
pv.t.diswithout := '0';
if pr.t.cur_acc(0).pending = '1' then
if pr.t.cur_acc(0).read = '1' then -- Memory and Config read
pv.t.fstate := ptf_fifo;
pv.t.atp.ctrl.addr := conv_std_logic_vector(pr.t.atp.index, log2(FIFO_COUNT)) & pr.t.cur_acc(0).addr(FIFO_DEPTH+1 downto 2);
else
if pr.t.cur_acc(0).acc_type(1) = '1' then -- Config write
pv.t.fstate := ptf_cwrite;
pv.t.conf_addr := pr.t.cur_acc(0).addr(5 downto 2);
t_ready := '1';
elsif tm_fifo_empty(pr.t.pta.index) = '1' then -- Memory write
-- Burst length (only burst up to this boundary)
pv.t.blen := ((not pr.t.cur_acc(0).addr(17 downto 2)) and pr.t.blenmask);
pv.t.fstate := ptf_write;
t_ready := '1';
pv.t.pta.ctrl.addr := conv_std_logic_vector(pr.t.pta.index, log2(FIFO_COUNT)) & pr.t.cur_acc(0).addr(FIFO_DEPTH+1 downto 2);
if pr.t.cur_acc(0).acc_type(0) = '0' then -- memory access
pv.t.addr := set_pta_addr(pr.t.cur_acc(0).addr, pr.conf(pr.t.cur_acc(0).func).pta_map, pr.t.cur_acc(0).bar, pr.conf(pr.t.cur_acc(0).func).bar_mask, barminsize);
else
pv.t.addr := pr.conf(conf_func).cfg_map(31 downto 8) & pr.t.cur_acc(0).addr(7 downto 0);
end if;
else
t_retry := '1';
pv.t.fstate := ptf_idle;
pv.t.cur_acc(0).pending := '0';
end if;
end if;
if pr.t.cur_acc(0).acc_type(1) = '0' and -- Access to AHB
( (pr.t.cur_acc(0).read = '1') -- Read
or (pr.t.cur_acc(0).read = '0' and tm_fifo_empty(pr.t.pta.index) = '1')) then -- Write
if tm_acc_pending = '0' and pr.t.accbuf(0).pending = '0' then
pv.pta_trans.tm_acc.pending := not pr.pta_trans.tm_acc.pending;
if pr.t.cur_acc(0).acc_type(0) = '0' then -- memory access
pv.pta_trans.tm_acc.addr := set_pta_addr(pr.t.cur_acc(0).addr, pr.conf(pr.t.cur_acc(0).func).pta_map, pr.t.cur_acc(0).bar, pr.conf(pr.t.cur_acc(0).func).bar_mask, barminsize);
else
pv.pta_trans.tm_acc.addr := pr.conf(conf_func).cfg_map(31 downto 8) & pr.t.cur_acc(0).addr(7 downto 0);
end if;
pv.pta_trans.tm_acc.acctype := "000" & not pr.t.cur_acc(0).read; -- acctype(0) = write
pv.pta_trans.tm_acc.accmode := "00" & pr.t.cur_acc(0).burst;
pv.pta_trans.tm_acc.size := (others => '0'); -- not used
pv.pta_trans.tm_acc.offset := (others => '0'); -- not used
if pr.t.cur_acc(0).read = '1' then pv.pta_trans.tm_acc.index := pr.t.atp.index;
else pv.pta_trans.tm_acc.index := pr.t.pta.index; end if;
pv.pta_trans.tm_acc.length := ((not pr.t.cur_acc(0).addr(17 downto 2)) and pr.t.blenmask);
pv.pta_trans.tm_acc.cbe := pi.cbe;
pv.pta_trans.tm_acc.endianess := pr.pta_trans.ca_twist;
else
accbufindex := 0;
for i in 3 downto 0 loop
if pv.t.accbuf(i).pending = '0' then accbufindex := i; end if;
end loop;
pv.t.accbuf(accbufindex).pending := '1';
if pr.t.cur_acc(0).acc_type(0) = '0' then -- memory access
pv.t.accbuf(accbufindex).addr := set_pta_addr(pr.t.cur_acc(0).addr, pr.conf(pr.t.cur_acc(0).func).pta_map, pr.t.cur_acc(0).bar, pr.conf(pr.t.cur_acc(0).func).bar_mask, barminsize);
else
pv.t.accbuf(accbufindex).addr := pr.conf(conf_func).cfg_map(31 downto 8) & pr.t.cur_acc(0).addr(7 downto 0);
end if;
pv.t.accbuf(accbufindex).acctype := "000" & not pr.t.cur_acc(0).read; -- acctype(0) = write
pv.t.accbuf(accbufindex).accmode := "00" & pr.t.cur_acc(0).burst;
pv.t.accbuf(accbufindex).size := (others => '0'); -- not used
pv.t.accbuf(accbufindex).offset := (others => '0'); -- not used
if pr.t.cur_acc(0).read = '1' then pv.t.accbuf(accbufindex).index := pr.t.atp.index;
else pv.t.accbuf(accbufindex).index := pr.t.pta.index; end if;
pv.t.accbuf(accbufindex).length := ((not pr.t.cur_acc(0).addr(17 downto 2)) and pr.t.blenmask);
pv.t.accbuf(accbufindex).cbe := pi.cbe;
pv.t.accbuf(accbufindex).endianess := pr.pta_trans.ca_twist;
end if;
end if;
end if;
when ptf_fifo =>
pv.t.atp.ctrl.en := tm_fifo_pending(pr.t.atp.index);
if (pr.t.hold(0) = '0' or pr.t.first_word = '1') and pr.t.cfifo(0).valid = '1' then
t_ready := '1';
end if;
if pr.t.cur_acc(0).newacc = '1' or
(tm_acc_cancel = '1' and pr.t.cur_acc(0).acc_type(1) = '0') or
pr.t.cur_acc(0).read = '0' then
t_ready := '0';
end if;
if (tm_acc_cancel = '0' and tm_fifo_pending(pr.t.atp.index) = '1') or pr.t.preload = '1' or pr.t.cur_acc(0).acc_type(1) = '1' then -- FIFO pending or Config access
pv.t.preload := '1';
if pr.t.preload = '0' then pv.t.hold_fifo := '0'; end if;
end if;
if ((pi.trdy or pi.irdy) = '0' and pr.t.state = pt_s_data) or pr.t.preload = '1' then
if (pi.trdy or pi.irdy) = '0' and pr.t.state = pt_s_data then
pv.t.cfifo(0) := pr.t.cfifo(1); pv.t.cfifo(1) := pr.t.cfifo(2); -- Preload target core fifo
pv.t.cur_acc(0).addr := pr.t.cur_acc(0).addr + 4;
elsif pr.t.preload = '1' then
if pr.t.cfifo(0).valid = '0' then
pv.t.cfifo(0) := pr.t.cfifo(1); pv.t.cfifo(1) := pr.t.cfifo(2); -- Preload target core fifo
elsif pr.t.cfifo(0).valid = '1' and pr.t.cfifo(1).valid = '0' then
pv.t.cfifo(1) := pr.t.cfifo(2); -- Preload target core fifo
end if;
end if;
if pr.t.cur_acc(0).acc_type(1) = '0' then -- Memory access
pv.t.cfifo(2).data := byte_twist(tm_fifoo_atp.data, pr.pta_trans.ca_twist); -- shifting in data from backend fifo
else
pv.t.cfifo(2).data := t_cad; -- Configuration access
end if;
if pr.t.cur_acc(0).acc_type(1) = '0' then -- Memory access
if tm_fifo_pending(pr.t.atp.index) = '1' then
if pr.t.atp.ctrl.addr(FIFO_DEPTH-1 downto 0) = tm_fifo(pr.t.atp.index).stop and pr.t.hold_fifo = '0' then -- Mark last word
pv.t.atp.index := t_index;
pv.t.atp.ctrl.addr := conv_std_logic_vector(pv.t.atp.index, log2(FIFO_COUNT)) & zero32(FIFO_DEPTH-1 downto 0); -- Reset backend fifo address
pv.pta_trans.tm_fifo_ack(pr.t.atp.index) := tm_fifo(pr.t.atp.index).pending(RAM_LATENCY); -- Ack the fifo (done using this data)
if tm_fifo_pending(t_index) = '1' then
pv.t.cfifo(2).hold := '0';
else
pv.t.cfifo(2).hold := '1';
pv.t.hold_fifo := '1';
-- Disconnect on last fifo
if tm_fifo(pr.t.atp.index).lastf = '1' then pv.t.cfifo(2).stlast := '1'; end if;
-- Disable fifo read
pv.t.atp.ctrl.en := '0';
end if;
else
pv.t.cfifo(2).hold := '0';
if pr.t.hold_fifo = '0' then
pv.t.atp.ctrl.addr := conv_std_logic_vector(pv.t.atp.index, log2(FIFO_COUNT)) & pr.t.atp.ctrl.addr(FIFO_DEPTH-1 downto 0) + 1; -- inc backend fifo address
end if;
end if;
if pr.t.atp.ctrl.addr(FIFO_DEPTH-1 downto 0) = tm_fifo(pr.t.atp.index).stop and tm_fifo(pr.t.atp.index).status /= "0000" then
pv.t.cfifo(2).err := '1';
else
pv.t.cfifo(2).err := '0';
end if;
end if;
else -- Configuration access
if pr.t.conf_addr = "1110" then
pv.t.cfifo(2).stlast := '1';
else
pv.t.cfifo(2).stlast := '0';
end if;
if pr.t.conf_addr = "1111" then
pv.t.cfifo(2).hold := '1';
if pr.t.preload_count = "00" then pv.t.cfifo(2).stlast := '1'; end if;
else
pv.t.cfifo(2).hold := '0';
pv.t.conf_addr := pr.t.conf_addr + 1; -- inc backend fifo address
end if;
pv.t.cfifo(2).err := '0';
end if;
if (tm_fifo_pending(pr.t.atp.index) = '1' or pr.t.cur_acc(0).acc_type(1) = '1') and pr.t.hold_fifo = '0' then
pv.t.cfifo(2).valid := '1';
else
pv.t.cfifo(2).valid := '0';
end if;
end if;
if (pv.t.cfifo(0).valid = '1' and pv.t.cfifo(1).valid = '1' and pv.t.cfifo(2).valid = '1')
or (pv.t.cfifo(0).valid = '1' and pr.t.cfifo(0).valid = '0')
or (pv.t.cfifo(0).valid = '1' and pr.t.cfifo(0).hold = '1' and pv.t.cfifo(1).valid = '1') then
pv.t.preload := '0';
if pr.t.preload = '1' or (pr.t.hold_fifo = '1' and pv.t.hold_fifo = '0') then
pv.t.hold_reset := '0';
if pr.t.cfifo(0).hold = '1' and pv.t.cfifo(1).valid = '1' then pv.t.cfifo(0).hold := '0'; end if;
if pr.t.cfifo(1).hold = '1' and pv.t.cfifo(2).valid = '1' then pv.t.cfifo(1).hold := '0'; end if;
if pr.t.cfifo(2).hold = '1' and tm_fifo_pending(pr.t.atp.index) = '1' then pv.t.cfifo(2).hold := '0'; end if;
end if;
end if;
if (pr.t.state = pt_turn_ar and pr.t.cur_acc(0).pending = '0' and pr.t.cur_acc(0).continue = '0')
or (pr.t.cur_acc(0).newacc = '1')
or ((pr.t.abort = '1' or pr.t.diswithout = '1') and (pr.t.state = pt_backoff or pr.t.state = pt_turn_ar))
then
if pr.t.cur_acc(0).burst = '1' and pr.t.abort = '0' then
if pr.t.cur_acc(0).acc_type(1) = '0' or pr.t.cur_acc(0).read = '0' or pr.t.cur_acc(0).pending = '0' then
pv.t.fstate := ptf_idle;
end if;
else
pv.t.fstate := ptf_idle;
if pr.t.abort = '1' then pv.t.cur_acc(0).pending := '0'; end if;
if pr.t.cur_acc(0).burst = '1' then pv.pta_trans.tm_acc_cancel := not pr.pta_trans.tm_acc_cancel; end if;
end if;
pv.t.hold_reset := '0';
for i in 0 to 2 loop
pv.t.cfifo(i).valid := '0';
pv.t.cfifo(i).hold := '0';
pv.t.cfifo(i).stlast := '0';
pv.t.cfifo(i).last := '0';
pv.t.cfifo(i).err := '0';
end loop;
if (pr.t.cur_acc(0).pending = '0' and pr.t.cur_acc(0).acc_type(1) = '0' and pr.t.cur_acc(0).burst = '1') or
(pr.t.cur_acc(0).newacc = '1' and pr.t.cur_acc(0).oldburst = '1') then
pv.pta_trans.tm_acc_cancel := not pr.pta_trans.tm_acc_cancel;
end if;
end if;
when ptf_cwrite =>
if pr.t.hold(0) = '0' then -- can maybe be optimized
t_ready := '1';
end if;
if pr.t.state = pt_turn_ar then
pv.t.fstate := ptf_idle;
pv.t.hold_reset := '0';
end if;
if (pi.trdy or pi.irdy) = '0' then
if pr.t.conf_addr /= "1111" then -- Config access
pv.t.conf_addr := pr.t.conf_addr + 1; -- inc backend fifo address
end if;
end if;
when ptf_write =>
if pr.t.hold(0) = '0' then -- can maybe be optimized
t_ready := '1';
elsif tm_fifo_empty(pr.t.pta.index) = '1' and pr.t.hold_write = '0' then
t_ready := '1';
pv.t.hold_reset := '0';
end if;
if (pr.t.addr(AHB_FIFO_BITS) = ones32(FIFO_DEPTH-1 downto 0) and pr.t.first(0) = '1' and
(tm_fifo_empty(t_index) = '0' or pr.t.blen = x"0000")) or
((pi.trdy or pi.irdy) = '0' and pr.t.blen = x"0001") or
pr.t.cur_acc(0).burst = '0' then
pv.t.diswithout := '1';
end if;
if pr.t.state = pt_turn_ar then
pv.t.fstate := ptf_idle;
pv.t.hold_reset := '0';
end if;
if (pi.trdy or pi.irdy) = '0' then
pv.t.pta.ctrl.en := '1';
pv.t.pta.ctrl.addr := conv_std_logic_vector(pr.t.pta.index, log2(FIFO_COUNT)) & pr.t.addr(AHB_FIFO_BITS);
if pi.cbe /= ones32(3 downto 0) or pr.t.first(0) = '1' then
pv.t.first(0) := '0';
pv.pta_trans.tm_fifo(pr.t.pta.index).stop := pr.t.addr(AHB_FIFO_BITS);
pv.pta_trans.tm_fifo(pr.t.pta.index).last_cbe := pi.cbe;
end if;
if pr.t.first(0) = '1' then -- First data in this fifo
pv.pta_trans.tm_fifo(pr.t.pta.index).start := pr.t.addr(AHB_FIFO_BITS);
end if;
pv.t.addr := pr.t.addr + 4; -- inc backend fifo address
if pr.t.blen /= zero32(15 downto 0) then
pv.t.blen := pr.t.blen - 1;
end if;
if pr.t.addr(AHB_FIFO_BITS) /= ones32(FIFO_DEPTH-1 downto 0) and pi.frame = '0' and pr.t.diswithout = '0' and pi.stop = '1' then
if pr.t.addr(AHB_FIFO_BITS) = conv_std_logic_vector((conv_integer(ones32(FIFO_DEPTH-1 downto 0)) - 1), FIFO_DEPTH) then
if tm_fifo_empty(t_index) = '0' then
pv.t.hold_write := '1';
t_ready := '0';
pv.t.diswithout := '1';
end if;
end if;
else
pv.t.first(0) := '1';
pv.t.first(1) := '0';
pv.t.hold_write := '0';
pv.t.pta.index := t_index;
pv.pta_trans.tm_fifo(pr.t.pta.index).pending(0) := not pr.pta_trans.tm_fifo(pr.t.pta.index).pending(0);
pv.pta_trans.tm_fifo(pr.t.pta.index).status := (others => '0');
if pr.t.first(1) = '1' then pv.pta_trans.tm_fifo(pr.t.pta.index).firstf := '1';
else pv.pta_trans.tm_fifo(pr.t.pta.index).firstf := '0'; end if;
if pi.frame = '1' or pr.t.diswithout = '1' then pv.pta_trans.tm_fifo(pr.t.pta.index).lastf := '1'; -- Mark last fifo
else pv.pta_trans.tm_fifo(pr.t.pta.index).lastf := '0'; end if;
end if;
end if;
when others =>
end case;
-- PCI State machine
case pr.t.state is
when pt_idle => -- The bus is in idle state
pv.t.hold_write := '0';
pv.t.lcount := (others => '0'); -- reset latency counter
pv.t.stoped := '0';
pv.t.retry := '0';
if pi.frame = '0' then
if t_hit = '1' or t_chit = '1' then
pv.t.state := pt_s_data;
pv.t.first_word := '1';
case pi.cbe is
when CONF_READ =>
t_acc_read := '1';
t_acc_burst := '1';
t_acc_type := "10";
pv.t.conf_addr := pi.ad(5 downto 2);
if pi.ad(7 downto 4) >= "0100" then
if ext_cap_pointer_vector(conf_func) /= 16#00# then
t_acc_type := "01";
else
t_acc_impcfgreg := '0';
end if;
if pi.ad(7 downto 4) >= conv_std_logic_vector(cap_pointer, 8)(7 downto 4)
and pi.ad(7 downto 4) < conv_std_logic_vector(cap_pointer + 16#40#, 8)(7 downto 4) then
t_acc_type := "11";
t_acc_impcfgreg := '1';
end if;
end if;
when CONF_WRITE =>
t_acc_read := '0';
t_acc_burst := '1';
t_acc_type := "10";
pv.t.conf_addr := pi.ad(5 downto 2);
if pi.ad(7 downto 4) >= "0100" then
if ext_cap_pointer_vector(conf_func) /= 16#00# then
t_acc_type := "01";
else
t_acc_impcfgreg := '0';
end if;
if pi.ad(7 downto 4) >= conv_std_logic_vector(cap_pointer, 8)(7 downto 4)
and pi.ad(7 downto 4) < conv_std_logic_vector(cap_pointer + 16#40#, 8)(7 downto 4) then
t_acc_type := "11";
t_acc_impcfgreg := '1';
end if;
end if;
when MEM_READ =>
t_acc_read := '1';
t_acc_burst := '0';
t_acc_type := "00";
when MEM_WRITE | MEM_W_INV =>
t_acc_read := '0';
-- Burst ordering: Linear Incrementing
if pi.ad(1 downto 0) = "00" then t_acc_burst := '1';
else t_acc_burst := '0'; end if;
t_acc_type := "00";
when IO_READ =>
t_acc_read := '1';
t_acc_burst := '0';
t_acc_type := "00";
when IO_WRITE =>
t_acc_read := '0';
t_acc_burst := '0';
t_acc_type := "00";
when MEM_R_MULT | MEM_R_LINE =>
t_acc_read := '1';
-- Burst ordering: Linear Incrementing
if pi.ad(1 downto 0) = "00" then t_acc_burst := '1';
else t_acc_burst := '0'; end if;
t_acc_type := "00";
when others =>
t_acc_read := '1';
t_acc_burst := '1';
t_acc_type := "00";
end case;
if (pr.t.cur_acc(0).pending = '1' or pr.t.cur_acc(0).continue = '1') and pr.t.cur_acc(0).addr = pi.ad
and t_acc_read = '1' and pr.t.cur_acc(0).acc_type(1) = '0' then
pv.t.cur_acc(0).match := '1';
pv.t.cur_acc(0).pending := '1';
pv.t.discardtimer := (others => '1');
elsif pr.t.cur_acc(0).pending = '0' then -- Save new access
pv.t.cur_acc(0).addr := pi.ad;
pv.t.cur_acc(0).pending := '1';
pv.t.cur_acc(0).retry := '0';
pv.t.cur_acc(0).read := t_acc_read;
pv.t.cur_acc(0).burst := t_acc_burst;
pv.t.cur_acc(0).acc_type := t_acc_type;
pv.t.cur_acc(0).impcfgreg := t_acc_impcfgreg;
pv.t.cur_acc(0).bar := t_bar;
pv.t.cur_acc(0).func := t_func;
pv.t.cur_acc(0).match := '0';
pv.t.discardtimer := (others => '1');
if pr.t.cur_acc(0).continue = '1' then
pv.t.cur_acc(0).newacc := '1';
pv.t.cur_acc(0).oldburst := pr.t.cur_acc(0).burst;
end if;
else
pv.t.cur_acc(0).match := '0';
end if;
pv.t.cur_acc(0).continue := '0';
else
pv.t.state := pt_b_busy;
end if;
end if;
when pt_b_busy => -- Wait for the current transaction to complete and bus return
-- to idle sate
if (pi.frame and pi.irdy) = '1' then
pv.t.state := pt_idle;
end if;
when pt_s_data => -- Target is transfering data
if (pi.frame and not pi.irdy and ( not pi.trdy or not pi.stop)) = '1' then
pv.t.state := pt_turn_ar;
pv.t.retry := '0';
if pr.t.cur_acc(0).pending = '0' and pr.t.cur_acc(0).acc_type(1) = '0' and
pr.t.cur_acc(0).read = '1' and pi.trdy = '1' and pi.stop = '0' and pr.t.stop = '0' and
pr.t.cur_acc(0).burst = '1' and pr.t.discardtimer /= x"0000" then
if pr.t.saverfifo = '1' then -- FIFO is saved until next access (disconnect without data).
-- If the next access is not the read continuing, the prefetched data is discarded.
pv.t.cur_acc(0).continue := '1';
end if;
end if;
elsif (not pi.frame and not pi.stop) = '1' then
pv.t.state := pt_backoff;
pv.t.retry := '0';
if pr.t.cur_acc(0).pending = '0' and pr.t.cur_acc(0).acc_type(1) = '0' and
pr.t.cur_acc(0).read = '1' and pr.t.stop = '0' and pr.t.stop = '0' and
pr.t.cur_acc(0).burst = '1' and pr.t.discardtimer /= x"0000" then
if pr.t.saverfifo = '1' then -- FIFO is saved until next access (disconnect without data).
-- If the next access is not the read continuing, the prefetched data is discarded.
pv.t.cur_acc(0).continue := '1';
end if;
end if;
end if;
if (not pi.irdy and not pi.trdy) = '1' then pv.t.cur_acc(0).pending := '0'; end if; -- Data transfered, reset pending
-- can maybe be optimized
if ((pr.t.cfifo(0).valid = '0' or pr.t.cur_acc(0).match = '0') and
pr.t.cur_acc(0).pending = '1' and pr.t.cur_acc(0).acc_type(1) = '0' and pr.t.cur_acc(0).read = '1') or
pr.t.retry = '1' then t_retry := '1'; pv.t.retry := '1'; end if;
-- CFIFO valid again after FIFO switch (First word in continued access), to reassert trdy
if pr.t.fstate = ptf_fifo and pr.t.preload = '1' and pr.t.first_word = '0' and
pr.t.cfifo(0).valid = '0' and pr.t.cfifo(1).valid = '1' then
pv.t.first_word := '1';
end if;
-- When FIFO is saved until next access (disconnect without data)
-- the first_word signal needs to be set one extra cycle to be valid the cycle before
-- FIFO state-machine moves to FIFO write state
if pr.t.fstate = ptf_fifo and pr.t.first_word = '1' and
pr.t.cur_acc(0).pending = '1' and pr.t.cur_acc(0).newacc = '1' and
pr.t.cur_acc(0).read = '0' then
if pr.t.saverfifo = '1' then
pv.t.first_word := '1';
end if;
end if;
when pt_backoff => -- STOP# is asserted, waiting on deasserted FRAME#
if pi.frame = '1' then
pv.t.state := pt_turn_ar;
end if;
when pt_turn_ar => -- Deassert active signals before tri-state
-- from idle
pv.t.hold_write := '0';
pv.t.lcount := (others => '0'); -- reset latency counter
pv.t.stoped := '0';
pv.t.retry := '0';
if pi.frame = '1' then
pv.t.state := pt_idle;
elsif pi.frame = '0' then
if t_hit = '1' or t_chit = '1' then
pv.t.state := pt_s_data;
pv.t.first_word := '1';
case pi.cbe is
when CONF_READ =>
t_acc_read := '1';
t_acc_burst := '1';
t_acc_type := "10";
pv.t.conf_addr := pi.ad(5 downto 2);
if pi.ad(7 downto 4) >= "0100" then
if ext_cap_pointer_vector(conf_func) /= 16#00# then
t_acc_type := "01";
else
t_acc_impcfgreg := '0';
end if;
if pi.ad(7 downto 4) >= conv_std_logic_vector(cap_pointer, 8)(7 downto 4)
and pi.ad(7 downto 4) < conv_std_logic_vector(cap_pointer + 16#40#, 8)(7 downto 4) then
t_acc_type := "11";
t_acc_impcfgreg := '1';
end if;
end if;
when CONF_WRITE =>
t_acc_read := '0';
t_acc_burst := '1';
t_acc_type := "10";
pv.t.conf_addr := pi.ad(5 downto 2);
if pi.ad(7 downto 4) >= "0100" then
if ext_cap_pointer_vector(conf_func) /= 16#00# then
t_acc_type := "01";
else
t_acc_impcfgreg := '0';
end if;
if pi.ad(7 downto 4) >= conv_std_logic_vector(cap_pointer, 8)(7 downto 4)
and pi.ad(7 downto 4) < conv_std_logic_vector(cap_pointer + 16#40#, 8)(7 downto 4) then
t_acc_type := "11";
t_acc_impcfgreg := '1';
end if;
end if;
when MEM_READ =>
t_acc_read := '1';
t_acc_burst := '0';
t_acc_type := "00";
when MEM_WRITE | MEM_W_INV =>
t_acc_read := '0';
-- Burst ordering: Linear Incrementing
if pi.ad(1 downto 0) = "00" then t_acc_burst := '1';
else t_acc_burst := '0'; end if;
t_acc_type := "00";
when IO_READ =>
t_acc_read := '1';
t_acc_burst := '0';
t_acc_type := "00";
when IO_WRITE =>
t_acc_read := '0';
t_acc_burst := '0';
t_acc_type := "00";
when MEM_R_MULT | MEM_R_LINE =>
t_acc_read := '1';
-- Burst ordering: Linear Incrementing
if pi.ad(1 downto 0) = "00" then t_acc_burst := '1';
else t_acc_burst := '0'; end if;
t_acc_type := "00";
when others =>
t_acc_read := '1';
t_acc_burst := '1';
t_acc_type := "00";
end case;
if (pr.t.cur_acc(0).pending = '1' or pr.t.cur_acc(0).continue = '1') and pr.t.cur_acc(0).addr = pi.ad and t_acc_read = '1' and pr.t.cur_acc(0).acc_type(1) = '0' then
pv.t.cur_acc(0).match := '1';
pv.t.cur_acc(0).pending := '1';
pv.t.discardtimer := (others => '1');
elsif pr.t.cur_acc(0).pending = '0' then -- Save new access
pv.t.cur_acc(0).addr := pi.ad;
pv.t.cur_acc(0).pending := '1';
pv.t.cur_acc(0).retry := '0';
pv.t.cur_acc(0).read := t_acc_read;
pv.t.cur_acc(0).burst := t_acc_burst;
pv.t.cur_acc(0).acc_type := t_acc_type;
pv.t.cur_acc(0).impcfgreg := t_acc_impcfgreg;
pv.t.cur_acc(0).bar := t_bar;
pv.t.cur_acc(0).func := t_func;
pv.t.cur_acc(0).match := '0';
pv.t.discardtimer := (others => '1');
if pr.t.cur_acc(0).continue = '1' then
pv.t.cur_acc(0).newacc := '1';
pv.t.cur_acc(0).oldburst := pr.t.cur_acc(0).burst;
end if;
else
pv.t.cur_acc(0).match := '0';
end if;
pv.t.cur_acc(0).continue := '0';
else
pv.t.state := pt_b_busy;
end if;
end if;
when others =>
end case;
if pr.t.fstate = ptf_idle then pv.t.hold_reset := '0'; end if;
if pr.po.stop = '0' then pv.t.stoped := '1'; end if;
end if; -- PCI target enabled
-- --------------------------------------------------------------------------------
-- PCI trace
-- --------------------------------------------------------------------------------
-- sync
pv.pt_sync(1) := ar.atpt_trans; pv.pt_sync(2) := pr.pt_sync(1);
if nsync = 0 then atpt_trans := ar.atpt_trans;
else atpt_trans := pr.pt_sync(nsync); end if;
pt_setup := ar.atpt_trans;
pv.ptta_trans.start_ack := atpt_trans.start;
pv.ptta_trans.stop_ack := atpt_trans.stop;
pt_start := not pr.ptta_trans.start_ack and (pr.ptta_trans.start_ack xor atpt_trans.start);
pt_stop := not pr.ptta_trans.stop_ack and (pr.ptta_trans.stop_ack xor atpt_trans.stop);
if tracebuffer /= 0 then -- PCI trace buffer enabled
if pr.ptta_trans.enable = '1' then -- PCI tracing
pv.pt.addr := pr.pt.addr + 1;
if pr.ptta_trans.armed = '1' then -- Check for match
if ((((pi.ad & pcisig) xor (pt_setup.ad & pt_setup.sig)) and (pt_setup.admask & pt_setup.sigmask)) = z) then
if pr.pt.tcount = x"00" then
pv.ptta_trans.armed := '0'; -- Start saving trace
pv.ptta_trans.taddr := pr.pt.addr;
else pv.pt.tcount := pr.pt.tcount - 1; end if;
end if;
if pr.pt.addr = pr.ptta_trans.taddr then pv.ptta_trans.wrap := '1'; end if;
else
if pr.pt.count = zero32(PT_DEPTH-1 downto 0) then pv.ptta_trans.enable := '0'; -- Trace done
else pv.pt.count := pr.pt.count - 1; end if;
end if;
end if;
if pt_stop = '1' then -- Start PCI tracing
pv.ptta_trans.enable := '0';
if pr.ptta_trans.enable = '1' then
pv.ptta_trans.taddr := pr.pt.addr;
end if;
end if;
if pt_start = '1' then -- Start PCI tracing
pv.ptta_trans.enable := '1';
pv.ptta_trans.armed := '1';
pv.ptta_trans.wrap := '0';
pv.pt.count := pt_setup.count;
pv.pt.tcount := pt_setup.tcount;
end if;
--
pv.ptta_trans.dbg_ad := pi.ad;
pv.ptta_trans.dbg_sig := pcisig;
pv.ptta_trans.dbg_cur_ad := pr.t.cur_acc(0).addr;
pv.ptta_trans.dbg_cur_acc := pr.t.cur_acc(0).oldburst &
pr.t.cur_acc(0).acc_type &
pr.t.cur_acc(0).read &
pr.t.cur_acc(0).continue &
pr.t.cur_acc(0).burst &
pr.t.cur_acc(0).newacc &
pr.t.cur_acc(0).match &
pr.t.cur_acc(0).pending;
end if; -- PCI trace buffer enabled
-- --------------------------------------------------------------------------------
-- PCI debug
-- --------------------------------------------------------------------------------
--[31:30] ms_fifo_pending
--[29:28] ms_fifo_empty
--[37:36] tm_fifo_pending
--[25:24] tm_fifo_empty
--[ :23] ms_acc_pending;
--[ :22] ms_acc_cancel;
--[ :21] ms_acc_done;
--[ :20] md_acc_pending;
--[ :19] md_acc_cancel;
--[ :18] md_acc_done;
--[ :17] tm_acc_pending;
--[ :16] tm_acc_cancel;
--[ :15] tm_acc_done;
--[14:12] t.state
--[11: 8] t.fstate
--[ 7: 4] m.state
--[ 3: 0] m.fstate
pv.debug(31 downto 30) := ms_fifo_pending(1 downto 0);
pv.debug(29 downto 28) := ms_fifo_empty(1 downto 0);
pv.debug(27 downto 26) := tm_fifo_pending(1 downto 0);
pv.debug(25 downto 24) := tm_fifo_empty(1 downto 0);
pv.debug( 23) := ms_acc_pending;
pv.debug( 22) := ms_acc_cancel;
pv.debug( 21) := ms_acc_done;
pv.debug( 20) := md_acc_pending;
pv.debug( 19) := md_acc_cancel;
pv.debug( 18) := md_acc_done;
pv.debug( 17) := tm_acc_pending;
pv.debug( 16) := tm_acc_cancel;
pv.debug( 15) := tm_acc_done;
case pr.t.state is
when pt_idle => pv.debug(14 downto 12) := "000";
when pt_b_busy => pv.debug(14 downto 12) := "001";
when pt_s_data => pv.debug(14 downto 12) := "010";
when pt_backoff => pv.debug(14 downto 12) := "011";
when pt_turn_ar => pv.debug(14 downto 12) := "100";
when others => pv.debug(14 downto 12) := "111";
end case;
case pr.t.fstate is
when ptf_idle => pv.debug(11 downto 8) := "0000";
when ptf_fifo => pv.debug(11 downto 8) := "0001";
when ptf_cwrite => pv.debug(11 downto 8) := "0010";
when ptf_write => pv.debug(11 downto 8) := "0011";
when others => pv.debug(11 downto 8) := "1111";
end case;
case pr.m.state is
when pm_idle => pv.debug(7 downto 4) := "0000";
when pm_addr => pv.debug(7 downto 4) := "0001";
when pm_m_data => pv.debug(7 downto 4) := "0010";
when pm_turn_ar => pv.debug(7 downto 4) := "0011";
when pm_s_tar => pv.debug(7 downto 4) := "0100";
when pm_dr_bus => pv.debug(7 downto 4) := "0101";
when others => pv.debug(7 downto 4) := "1111";
end case;
case pr.m.fstate is
when pmf_idle => pv.debug(3 downto 0) := "0000";
when pmf_fifo => pv.debug(3 downto 0) := "0001";
when pmf_read => pv.debug(3 downto 0) := "0010";
when others => pv.debug(3 downto 0) := "1111";
end case;
debugo <= (others => '0');
-- --------------------------------------------------------------------------------
-- PCI reset
-- --------------------------------------------------------------------------------
-- PCI master
lpcim_rst <= pcirst(0) and not pci_master_rst and not pci_hard_rst;
if lpcim_rst = '0' then
-- state
pv.m.fstate := pmf_idle;
for i in 0 to 2 loop
pv.m.cfifo(i).last := '0';
pv.m.cfifo(i).stlast := '0';
pv.m.cfifo(i).hold := '0';
pv.m.cfifo(i).valid := '0';
pv.m.cfifo(i).err := '0';
end loop;
-- core
pv.m.devsel_asserted := '1';
pv.m.abort := (others => '0');
pv.m.hold := (others => '0');
pv.m.hold_fifo := '0';
pv.m.term := (others => '0');
pv.m.acc_cnt := 0;
pv.m.acc_switch := '0';
for i in 0 to 1 loop
pv.m.acc(i).pending := '0';
pv.m.acc(i).active := (others => '0');
pv.m.acc(i).fifo_index := 0;
end loop;
pv.m.fifo_addr := (others => '0');
pv.m.addr := (others => '0'); -- X-prop fix
-- trans
for i in 0 to 1 loop
pv.pta_trans.msd_acc_ack(i) := '0';
pv.pta_trans.msd_acc_cancel_ack(i) := (others => '0');
pv.pta_trans.msd_acc_done(i).done := '0';
for j in 0 to FIFO_COUNT-1 loop
pv.pta_trans.msd_fifo(i)(j).pending := (others => '0');
end loop;
pv.pta_trans.msd_fifo_ack(i) := (others => '0');
end loop;
end if;
-- PCI target
lpcit_rst <= pcirst(0) and not pci_target_rst and not pci_hard_rst;
if lpcit_rst = '0' then
-- state
pv.t.fstate := ptf_idle;
for i in 0 to 2 loop
pv.t.cfifo(i).last := '0';
pv.t.cfifo(i).stlast := '0';
pv.t.cfifo(i).hold := '0';
pv.t.cfifo(i).valid := '0';
pv.t.cfifo(i).err := '0';
end loop;
pv.t.cfifo(0).data := (others => '0'); -- X-prop fix
pv.t.cfifo(1).data := (others => '0'); -- X-prop fix
pv.t.atp.ctrl.addr := (others => '0'); -- X-prop fix
pv.t.cur_acc(0).addr(31) := '0'; -- X-prop fix
-- core
pv.t.discardtimeren := '1';
pv.t.hold := (others => '0');
pv.t.hold_fifo := '0';
pv.t.stop := '0';
pv.t.addr_perr := '0';
pv.t.cur_acc(0).pending := '0';
pv.t.cur_acc(0).continue := '0';
pv.t.cur_acc(0).read := '0';
pv.t.cur_acc(0).impcfgreg := '1';
pv.t.atp.index := 0;
pv.t.pta.index := 0;
pv.t.blenmask := (others => '0');
pv.t.blenmask(blenmask_size(barminsize) downto 0) := (others => '1');
pv.t.saverfifo := '0';
for i in 0 to 3 loop
pv.t.accbuf(i).pending := '0';
end loop;
-- trans
for i in 0 to FIFO_COUNT-1 loop
pv.pta_trans.tm_fifo(i).pending := (others => '0');
end loop;
pv.pta_trans.tm_fifo_ack := (others => '0');
pv.pta_trans.tm_acc.pending := '0';
pv.pta_trans.tm_acc_cancel := '0';
pv.pta_trans.tm_acc_done_ack := '0';
end if;
-- PCI reset
lpci_rst <= pcirst(0) and not pci_hard_rst;
if lpci_rst = '0' then
-- Master state
pv.m.state := pm_idle;
-- Target state
pv.t.state := pt_idle;
-- PCI signals
pv.po.frame := '1'; pv.po.irdy := '1'; pv.po.req := '1';
pv.po.trdy := '1'; pv.po.stop := '1';
pv.po.perr := '1'; pv.po.devsel := '1';
-- PCI system
pv.pta_trans.pa_serr := '1';
pv.pta_trans.pa_discardtout := '0';
-- Configuration space
for j in 0 to multifunc loop
pv.conf(j).comm.ioen := '0';
pv.conf(j).comm.memen := '0';
pv.conf(j).comm.msten := '0';
pv.conf(j).comm.mwien := '0';
pv.conf(j).comm.perren := '0';
pv.conf(j).comm.serren := '0';
pv.conf(j).comm.intdis := '0';
pv.conf(j).stat.intsta := '0';
pv.conf(j).stat.mdpe := '0';
pv.conf(j).stat.sta := '0';
pv.conf(j).stat.rta := '0';
pv.conf(j).stat.rma := '0';
pv.conf(j).stat.sse := '0';
pv.conf(j).stat.dpe := '0';
--pv.conf.clsize := (others => '0');
pv.conf(j).ltimer := (others => '0');
pv.conf(j).iline := (others => '0');
for i in 0 to 5 loop
pv.conf(j).bar(i) := (others => '0');
pv.conf(j).pta_map(i) := default_bar_map(j)(i);
pv.conf(j).bar_mask(i) := (others => '0');
pv.conf(j).bar_mask(i)(31 downto bar_size(j)(i)) := ones32(31 downto bar_size(j)(i));
pv.conf(j).bar_mask(i)(3) := bar_prefetch(j)(i);
pv.conf(j).bar_mask(i)(0) := bar_io(j)(i);
if bar_size(j)(i) <= 1 then pv.conf(j).bar_mask(i) := (others => '0'); end if;
end loop;
pv.conf(j).cfg_map := conv_std_logic_vector(extcfg_vector(j),28) & "0000";
end loop;
pv.pta_trans.ca_pcimsten := (others => '0');
pv.pta_trans.ca_twist := conv_std_logic_vector(conv_endian, 1)(0);
-- PCI trace
pv.ptta_trans.enable := '0';
pv.ptta_trans.armed := '0';
pv.ptta_trans.start_ack := '0';
pv.ptta_trans.stop_ack := '0';
pv.pt.addr := (others => '0');
end if;
if pcirst(0) = '0' then
pv.pta_trans.rst_ack := (others => '0');
end if;
-- Disabled parts
if target = 0 then -- PCI targer disabled
pv.t := pci_target_none;
pv.pta_trans.tm_acc := pci_g_acc_trans_none;
pv.pta_trans.tm_acc_cancel := '0';
pv.pta_trans.tm_acc_done_ack := '0';
pv.pta_trans.tm_fifo := pci_g_fifo_trans_vector_none;
pv.pta_trans.tm_fifo_ack := pci_g_fifo_ack_trans_vector_none;
pv.po.trdy := '1'; pv.po.trdyen := oeoff; pv.po.stop := '1'; pv.po.stopen := oeoff;
pv.po.devsel := '1'; pv.po.devsel := oeoff;
for j in 0 to multifunc loop
pv.conf(j).comm.memen := '0';
pv.conf(j).stat.sta := '0';
for i in 0 to 5 loop
pv.conf(j).bar(i) := (others => '0');
end loop;
if master /= 0 and confspace = 0 then -- No Configuration Space but PCI master => master enabled
pv.conf(j).comm.msten := '1'; pv.pta_trans.ca_pcimsten := (others => '1');
end if;
end loop;
end if;
if master = 0 and dma = 0 then -- PCI master disabled
pv.m := pci_master_none;
pv.pta_trans.msd_acc_ack(0) := '0';
pv.pta_trans.msd_acc_cancel_ack(0) := (others => '0');
pv.pta_trans.msd_acc_done(0) := pci_g_acc_status_trans_none;
pv.pta_trans.msd_fifo(0) := pci_g_fifo_trans_vector_none;
pv.pta_trans.msd_fifo_ack(0) := pci_g_fifo_ack_trans_vector_none;
pv.po.irdy := '1'; pv.po.irdyen := oeoff; pv.po.frame := '1'; pv.po.frameen := oeoff;
pv.po.req := '1'; pv.po.reqen := oeoff;
pv.po.cbe := (others => '0'); pv.po.cbeen := (others => oeoff);
for j in 0 to multifunc loop
pv.conf(j).comm.msten := '0'; pv.pta_trans.ca_pcimsten := (others => '0');
pv.conf(j).comm.mwien := '0';
pv.conf(j).stat.mdpe := '0';
pv.conf(j).stat.rta := '0';
pv.conf(j).stat.rma := '0';
end loop;
end if;
if dma = 0 then -- DMA disabled
pv.m.acc(1) := pci_master_acc_none;
pv.pta_trans.msd_acc_ack(1) := '0';
pv.pta_trans.msd_acc_cancel_ack(1) := (others => '0');
pv.pta_trans.msd_acc_done(1) := pci_g_acc_status_trans_none;
pv.pta_trans.msd_fifo(1) := pci_g_fifo_trans_vector_none;
pv.pta_trans.msd_fifo_ack(1) := pci_g_fifo_ack_trans_vector_none;
end if;
if tracebuffer = 0 then -- PCI trace buffer disabled
pv.pt := pci_trace_none;
pv.ptta_trans := pci_trace_to_apb_trans_none;
end if;
if dma = 0 and master = 0 and target = 0 then
pv.po.par := '1'; pv.po.paren := oeoff; pv.po.perr := '1'; pv.po.perren := oeoff;
pv.po.serren := oeoff; pv.po.inten := oeoff; pv.po.vinten := (others => oeoff);
pv.po.ad := (others => '0'); pv.po.aden := (others => oeoff);
for j in 0 to multifunc loop
pv.conf(j).stat.sse := '0';
pv.conf(j).stat.dpe := '0';
pv.conf(j).comm.perren := '0';
pv.conf(j).comm.serren := '0';
end loop;
end if;
-- --------------
prin <= pv;
-- PHY =>
sig_m_request <= m_request;
sig_m_mabort <= m_mabort;
sig_t_abort <= t_abort;
sig_t_ready <= t_ready;
sig_t_retry <= t_retry;
sig_soft_rst <= pci_hard_rst & pci_master_rst & pci_target_rst;
all_func_serren := '0';
for j in 0 to multifunc loop
all_func_serren := all_func_serren or pr.conf(j).comm.serren;
end loop;
sig_pr_conf_comm_serren <= all_func_serren;
if pr.m.perren /= "00" then
sig_pr_conf_comm_perren <= pr.conf(pr.m.acc(pr.m.acc_sel).func).comm.perren;
else
sig_pr_conf_comm_perren <= pr.conf(pr.t.cur_acc(0).func).comm.perren;
end if;
-- PHY <=
-- Gate PCI target => AHB master pending with pcirst
pr_pta_trans_gated <= pr.pta_trans;
pr_pta_trans_gated.tm_acc.pending <= pr.pta_trans.tm_acc.pending and pciasyncrst_comb;
end process;
acomb : process(ar, rst, pr_pta_trans_gated, dmao0, dmao1, tm_fifoo_pta, ms_fifoo_pta, md_fifoo_ptd, ahbsi, apbi, dirq, pcii.int, pt_fifoo_ad, pt_fifoo_sig, pr.ptta_trans, pcisig, lahbm_rst, lahbs_rst, lahb_rst, iotmact)
variable av : amba_reg_type;
variable pta_trans: pci_to_ahb_trans_type;
variable first : std_logic;
variable tm_nindex : integer range 0 to FIFO_COUNT-1;-- FIFO index
variable tm_acc : pci_g_acc_trans_type;
variable tm_acc_pending : std_logic;
variable tm_acc_done : std_logic;
variable tm_acc_cancel : std_logic;
variable tm_fifo_pending : std_logic_vector(FIFO_COUNT-1 downto 0);
variable tm_fifo_empty : std_logic_vector(FIFO_COUNT-1 downto 0);
variable tm_fifo : pci_g_fifo_trans_vector_type;
-- AHB slave
variable slv_access : std_logic;
variable tb_access : std_logic;
variable ms_index : integer range 0 to FIFO_COUNT-1;-- FIFO index
variable blen : std_logic_vector(15 downto 0);
variable ms_acc_pending : std_logic;
variable ms_acc_cancel : std_logic;
variable ms_acc_done : std_logic;
variable ms_acc_done_status : pci_g_acc_status_trans_type;
variable ms_fifo_pending : std_logic_vector(FIFO_COUNT-1 downto 0);
variable ms_fifo_empty : std_logic_vector(FIFO_COUNT-1 downto 0);
variable ms_fifo : pci_g_fifo_trans_vector_type;
variable accbufindex : integer range 0 to 3;
variable ms_func : std_logic_vector(2 downto 0);
variable ms_vifunc : integer range 0 to multifunc;
-- APB slave
variable apbaddr : std_logic_vector(6 downto 2);
variable prdata : std_logic_vector(31 downto 0);
variable pirq : std_logic_vector(NAHBIRQ-1 downto 0);
variable c_blenmask_update : std_logic;
variable ptta_trans : pci_trace_to_apb_trans_type;
variable pt_status : pci_trace_to_apb_trans_type;
-- DMA
variable md_index : integer range 0 to FIFO_COUNT-1;-- FIFO index
variable md_acc_pending : std_logic;
variable md_acc_cancel : std_logic;
variable md_acc_done : std_logic;
variable md_acc_done_status : pci_g_acc_status_trans_type;
variable md_fifo_pending : std_logic_vector(FIFO_COUNT-1 downto 0);
variable md_fifo_empty : std_logic_vector(FIFO_COUNT-1 downto 0);
variable md_fifo : pci_g_fifo_trans_vector_type;
-- Soft reset
variable pci_master_rst : std_logic;
variable pci_target_rst : std_logic;
variable pci_hard_rst : std_logic;
-- APB DEBUG
variable tbapbaddr : std_logic_vector(6 downto 2);
variable tbprdata : std_logic_vector(31 downto 0);
variable tbpirq : std_logic_vector(NAHBIRQ-1 downto 0);
begin
-- --------------------------------------------------------------------------------
-- AHB global defaults
-- --------------------------------------------------------------------------------
-- defaults
av := ar;
av.irq.access_pirq := '0';
av.irq.system_pirq := '0';
-- FIFO and AHB<=>PCI sync
av.sync(1) := pr_pta_trans_gated; av.sync(2) := ar.sync(1);
if nsync = 0 then pta_trans := pr_pta_trans_gated;
else pta_trans := ar.sync(nsync); end if;
-- PCI trace <=> APB sync
av.apb_sync(1) := pr.ptta_trans; av.apb_sync(2) := ar.apb_sync(1);
if nsync = 0 then ptta_trans := pr.ptta_trans;
else ptta_trans := ar.apb_sync(nsync); end if;
pt_status := pr.ptta_trans;
if tracebuffer = 0 then -- PCI trace buffer disabled
av.atpt_trans.start := '0'; av.atpt_trans.stop := '0'; av.atpt_trans.mode := (others => '0');
av.atpt_trans.count := (others => '0'); av.atpt_trans.tcount := (others => '0');
av.atpt_trans.ad := (others => '0'); av.atpt_trans.admask := (others => '0');
av.atpt_trans.sig := (others => '0'); av.atpt_trans.sigmask := (others => '0');
else
if ptta_trans.start_ack = '1' then av.atpt_trans.start := '0'; end if;
if ptta_trans.stop_ack = '1' then av.atpt_trans.stop := '0'; end if;
end if;
-- Soft reset
if pta_trans.rst_ack(0) = '1' then av.atp_trans.rst(0) := '0'; end if; -- PCI-target/AHB-master reset
if pta_trans.rst_ack(1) = '1' then av.atp_trans.rst(1) := '0'; end if; -- PCI-master/AHB-slave reset
pci_target_rst := pta_trans.rst_ack(0) or ar.atp_trans.rst(0);
pci_master_rst := pta_trans.rst_ack(1) or ar.atp_trans.rst(1);
pci_hard_rst := ar.atp_trans.rst(2);
-- --------------------------------------------------------------------------------
-- AHB master defaults
-- --------------------------------------------------------------------------------
-- FIFO enable(read)/write
av.m.acc.fifo_ren := '0';
av.m.acc.fifo_wen := '0';
av.m.acc.fifo_wdata := dmao0.data;
av.m.dmai0.noreq := '0';
tm_acc_pending := pta_trans.tm_acc.pending xor ar.atp_trans.tm_acc_ack;
tm_acc_done := pta_trans.tm_acc_done_ack xor ar.atp_trans.tm_acc_done.done;
tm_acc_cancel := pta_trans.tm_acc_cancel xor ar.atp_trans.tm_acc_cancel_ack(0);
-- Stop_ack also needs to be delayed when pending is delayed
av.atp_trans.tm_acc_cancel_ack(1) := ar.atp_trans.tm_acc_cancel_ack(0);
av.atp_trans.tm_acc_cancel_ack(2) := ar.atp_trans.tm_acc_cancel_ack(1);
for i in 0 to FIFO_COUNT-1 loop
tm_fifo_pending(i) := pta_trans.tm_fifo(i).pending(RAM_LATENCY) xor ar.atp_trans.tm_fifo_ack(i);
tm_fifo_empty(i) := not (ar.atp_trans.tm_fifo(i).pending(0) xor pta_trans.tm_fifo_ack(i));
-- To set pending when data is stored in fifo, with this stop_ack also needs to be delayed
av.atp_trans.tm_fifo(i).pending(1) := ar.atp_trans.tm_fifo(i).pending(0);
av.atp_trans.tm_fifo(i).pending(2) := ar.atp_trans.tm_fifo(i).pending(1);
end loop;
tm_fifo := pr_pta_trans_gated.tm_fifo;
tm_acc := pr_pta_trans_gated.tm_acc;
-- --------------------------------------------------------------------------------
-- AHB master core
-- --------------------------------------------------------------------------------
if target /= 0 then -- PCI target enabled
-- Select next fifo
if ar.m.acc.fifo_index /= FIFO_COUNT-1 then tm_nindex := ar.m.acc.fifo_index + 1;
else tm_nindex := 0; end if;
-- latch PCI target access
if tm_acc_pending = '1' and ar.m.acc.pending = '0' then
av.atp_trans.tm_acc_ack := pta_trans.tm_acc.pending;
av.m.acc.pending := '1';
av.m.acc.addr := tm_acc.addr;
av.m.acc.mode := tm_acc.accmode;
av.m.acc.burst := tm_acc.accmode(0);
av.m.acc.cbe := tm_acc.cbe;
av.m.acc.endianess := tm_acc.endianess;
av.m.acc.length := tm_acc.length;
av.m.acc.fifo_index := tm_acc.index;
av.m.acc.acctype := tm_acc.acctype;
end if;
-- AHB master state machine
case ar.m.state is
when am_idle =>
av.m.done := (others => '0');
av.m.stop := '0';
av.m.dmai0.req := '0';
av.m.dmai0.burst := '1';
av.m.dma_hold := '0';
av.m.active := '0';
av.m.retry := '0';
if ar.m.acc.pending = '1' then
av.m.dmai0.addr := ar.m.acc.addr;
av.m.dmai0.size := set_size_from_cbe(ar.m.acc.cbe);
av.m.dmai0.addr(1 downto 0) := set_addr_from_cbe(ar.m.acc.cbe, ar.m.acc.endianess);
-- Burst length (only burst up to this boundary)
av.m.blen := ar.m.acc.length;
if ar.m.acc.acctype(0) = '1' then -- Write
av.m.state := am_write;
av.m.first := "010";
av.m.hold := (others => '1');
elsif ar.m.acc.acctype(0) = '0' then -- Read
av.m.state := am_read;
av.m.first := "001";
av.m.hold := (others => '0');
av.m.dmai0.write := '0';
av.m.dmai0.req := '1';
av.m.acc.fifo_addr := conv_std_logic_vector(ar.m.acc.fifo_index, log2(FIFO_COUNT)) & ar.m.acc.addr(AHB_FIFO_BITS); -- Set fifo start address
av.m.faddr := av.m.acc.addr(AHB_FIFO_BITS);
if ar.m.acc.burst = '0' then
av.m.dmai0.size := set_size_from_cbe(ar.m.acc.cbe);
av.m.dmai0.addr(1 downto 0) := set_addr_from_cbe(ar.m.acc.cbe, ar.m.acc.endianess);
av.m.dmai0.burst := '0'; -- sinlge access
else
av.m.dmai0.size := "10";
av.m.dmai0.addr(1 downto 0) := "00";
end if;
end if;
end if;
if tm_acc_cancel = '1' then
av.atp_trans.tm_acc_cancel_ack(0) := pta_trans.tm_acc_cancel;
end if;
when am_read =>
if tm_fifo_empty(ar.m.acc.fifo_index) = '1' and ar.m.hold(0) = '1' and ar.m.done(0) = '0' and ar.m.active = '0' then
av.m.dmai0.req := '1';
av.m.hold := (others => '0');
end if;
if tm_acc_cancel = '1' then
av.m.done(2) := '1';
end if;
if dmao0.grant = '1' then
av.m.active := '1';
av.m.dmai0.addr := ar.m.dmai0.addr + 4;
if ar.m.blen /= zero32(15 downto 0) then
av.m.blen := ar.m.blen - 1;
end if;
if ar.m.dmai0.addr(AHB_FIFO_BITS) = ones32(AHB_FIFO_BITS) or ar.m.done(2) = '1' or ar.m.acc.burst = '0' then
if tm_fifo_empty(tm_nindex) = '0' then
av.m.dmai0.req := '0';
av.m.hold(0) := '1';
end if;
if ar.m.done(2) = '1' or ar.m.acc.burst = '0' or ar.m.blen = zero32(15 downto 0) then
av.m.dmai0.req := '0';
av.m.done(1) := '1';
end if;
end if;
-- Retry save & restore
av.m.retry := '0';
-- Save len for retry
av.m.retry_blen := ar.m.blen;
-- Restore len for retry
if ar.m.retry = '1' then
av.m.blen := ar.m.retry_blen;
end if;
elsif dmao0.retry = '1' then
av.m.dmai0.req := '1';
av.m.dmai0.addr := ar.m.dmai0.addr - 4;
--av.m.blen := ar.m.blen + 1;
av.m.done(1) := '0';
-- Retry save & restore
av.m.retry := '1';
-- Save len for retry
av.m.retry_blen := ar.m.blen;
-- Restore len for retry
av.m.blen := ar.m.retry_blen;
end if;
if dmao0.ready = '1' then
if dmao0.grant = '0' then av.m.active := '0'; end if;
if ar.m.faddr(AHB_FIFO_BITS) /= ones32(AHB_FIFO_BITS) and ar.m.done(1) = '0' then
av.m.faddr(AHB_FIFO_BITS) := ar.m.faddr(AHB_FIFO_BITS) + 1;
else -- Last word in fifo
av.m.faddr(AHB_FIFO_BITS) := (others => '0');
av.m.acc.fifo_index := tm_nindex; -- Go to next fifo
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).pending(0) := not ar.atp_trans.tm_fifo(ar.m.acc.fifo_index).pending(0);
if ar.m.first(0) = '1' then -- Mark first fifo in transfer
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).firstf := '1';
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).start := ar.m.acc.addr(AHB_FIFO_BITS);
av.m.first(0) := '0';
else
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).start := (others => '0');
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).firstf := '0';
end if;
if ar.m.done(1) = '1' then -- Mark last fifo in transfer
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).lastf := '1';
av.m.done(0) := '1';
else
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).lastf := '0';
end if;
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).stop := ar.m.faddr(AHB_FIFO_BITS);
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).status := (others => '0'); -- Not used
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).last_cbe := (others => '0'); -- Not used
end if;
av.m.acc.fifo_wen := '1';
av.m.acc.fifo_addr := conv_std_logic_vector(ar.m.acc.fifo_index, log2(FIFO_COUNT)) & ar.m.faddr(AHB_FIFO_BITS);
elsif dmao0.error = '1' then
av.m.active := '0';
av.m.dmai0.req := '0';
av.m.done(0) := '1';
av.m.acc.fifo_index := tm_nindex; -- Go to next fifo
if ar.m.first(0) = '1' then -- Mark first fifo in transfer
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).firstf := '1';
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).start := ar.m.acc.addr(AHB_FIFO_BITS);
av.m.first(0) := '0';
else
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).firstf := '0';
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).start := (others => '0');
end if;
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).lastf := '1';
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).stop := ar.m.faddr(AHB_FIFO_BITS);
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).pending(0) := not ar.atp_trans.tm_fifo(ar.m.acc.fifo_index).pending(0);
av.atp_trans.tm_fifo(ar.m.acc.fifo_index).status(0) := '1'; -- AHB error
av.m.acc.fifo_wen := '1';
av.m.acc.fifo_addr := conv_std_logic_vector(ar.m.acc.fifo_index, log2(FIFO_COUNT)) & ar.m.faddr(AHB_FIFO_BITS);
end if;
-- to deassert req on last address phase
if av.m.dmai0.addr(AHB_FIFO_BITS) = ones32(AHB_FIFO_BITS) then av.m.dmai0.noreq := '1'; end if;
if ar.m.done(2) = '1' and ar.m.active = '0' and dmao0.grant = '0' then
av.m.dmai0.req := '0';
av.m.done := (others => '1');
end if;
if ar.m.done(0) = '1' then
av.m.dmai0.req := '0';
if ar.m.done(2) = '1' or ar.m.acc.burst = '0' then
if ar.m.done(2) = '1' then
for i in 0 to FIFO_COUNT-1 loop
if tm_fifo_empty(i) = '0' then
av.atp_trans.tm_fifo(i).pending(0) := not ar.atp_trans.tm_fifo(i).pending(0);
else
av.atp_trans.tm_fifo(i).pending(0) := ar.atp_trans.tm_fifo(i).pending(0);
end if;
end loop;
end if;
av.m.state := am_idle;
av.m.acc.pending := '0';
end if;
end if;
when am_write =>
av.m.acc.fifo_ren := tm_fifo_pending(ar.m.acc.fifo_index);
av.m.dmai0.write := '1';
av.m.first(0) := '0';
if tm_fifo_pending(ar.m.acc.fifo_index) = '1' and ar.m.hold(0) = '1' and ar.m.active = '0' and ar.m.done(0) = '0' and ar.m.first(2) = '0' then
av.m.first(0) := '1';
av.m.first(2) := '1';
av.m.hold := "000";
av.m.last := "000";
av.m.acc.fifo_addr := conv_std_logic_vector(ar.m.acc.fifo_index, log2(FIFO_COUNT)) & tm_fifo(ar.m.acc.fifo_index).start; -- Set fifo start address
av.m.faddr := tm_fifo(ar.m.acc.fifo_index).start; -- Set fifo start address
if ar.m.first(1) = '1' then
av.m.first(1) := '0';
end if;
-- Last access is non-word or first/last is no-data
if tm_fifo(ar.m.acc.fifo_index).start = tm_fifo(ar.m.acc.fifo_index).stop then
if ar.m.acc.cbe = ones32(3 downto 0) then
av.m.done(0) := '1';
av.m.first(0) := '0';
av.m.dmai0.req := '0';
av.m.acc.fifo_index := tm_nindex; -- Go to next fifo
av.atp_trans.tm_fifo_ack(ar.m.acc.fifo_index) := pta_trans.tm_fifo(ar.m.acc.fifo_index).pending(RAM_LATENCY);
elsif tm_fifo(ar.m.acc.fifo_index).last_cbe /= ar.m.acc.cbe then
av.m.dmai0.size := set_size_from_cbe(tm_fifo(ar.m.acc.fifo_index).last_cbe);
av.m.dmai0.addr(1 downto 0) := set_addr_from_cbe(tm_fifo(ar.m.acc.fifo_index).last_cbe, ar.m.acc.endianess);
av.m.dmai0.burst := '0';
end if;
elsif ar.m.acc.cbe = ones32(3 downto 0) then
av.m.dmai0.addr := ar.m.dmai0.addr + 4;
av.m.acc.fifo_addr := conv_std_logic_vector(ar.m.acc.fifo_index, log2(FIFO_COUNT)) & (tm_fifo(ar.m.acc.fifo_index).start + 1); -- Set fifo start address
av.m.faddr := (tm_fifo(ar.m.acc.fifo_index).start + 1); -- Set fifo start address
end if;
end if;
if ar.m.first(0) = '1' then -- Latch first word in fifo
av.m.dmai0.req := '1';
if ar.m.acc.fifo_addr(FIFO_DEPTH-1 downto 0) /= tm_fifo(ar.m.acc.fifo_index).stop then
av.m.acc.fifo_addr(FIFO_DEPTH-1 downto 0) := ar.m.acc.fifo_addr(FIFO_DEPTH-1 downto 0) + 1;
else
av.m.hold(0) := '1';
if tm_fifo(ar.m.acc.fifo_index).lastf = '1' then
av.m.last(0) := '1';
if tm_fifo(ar.m.acc.fifo_index).status /= "0000" then
av.m.done(0) := '1';
av.m.dmai0.req := '0';
av.m.acc.fifo_index := tm_nindex; -- Go to next fifo
av.atp_trans.tm_fifo_ack(ar.m.acc.fifo_index) := pta_trans.tm_fifo(ar.m.acc.fifo_index).pending(RAM_LATENCY);
end if;
end if;
end if;
av.m.dmai0.data := tm_fifoo_pta.data;
end if;
if dmao0.grant = '1' then
av.m.active := '1';
av.m.dmai0.addr := ar.m.dmai0.addr + 4;
av.m.faddr := ar.m.faddr + 1;
av.m.retry := '0';
if (ar.m.active = '1' and ar.m.faddr = tm_fifo(ar.m.acc.fifo_index).stop) or ar.m.hold(1 downto 0) /= "00" or ar.m.done(0) = '1' then
if (ar.m.active = '1' and (tm_fifo_pending(tm_nindex) = '0' or tm_fifo(ar.m.acc.fifo_index).lastf = '1')) or ar.m.hold(1 downto 0) /= "00" or ar.m.done(0) = '1' then
av.m.dmai0.req := '0';
av.m.hold(0) := '1';
if tm_fifo(ar.m.acc.fifo_index).lastf = '1' then av.m.last(0) := '1'; end if;
end if;
if tm_fifo_pending(tm_nindex) = '1' then
if tm_fifo(tm_nindex).start = tm_fifo(tm_nindex).stop and tm_fifo(tm_nindex).last_cbe = ones32(3 downto 0) then
av.m.dmai0.req := '0';
av.m.hold(0) := '1';
end if;
end if;
end if;
-- Last access is non-word
if av.m.faddr(AHB_FIFO_BITS) = tm_fifo(ar.m.acc.fifo_index).stop and tm_fifo(ar.m.acc.fifo_index).last_cbe /= ar.m.acc.cbe then
av.m.dmai0.size := set_size_from_cbe(tm_fifo(ar.m.acc.fifo_index).last_cbe);
av.m.dmai0.addr(1 downto 0) := set_addr_from_cbe(tm_fifo(ar.m.acc.fifo_index).last_cbe, ar.m.acc.endianess);
av.m.dmai0.burst := '0';
elsif (tm_fifo(ar.m.acc.fifo_index).lastf = '0' and tm_fifo_pending(tm_nindex) = '1' and
av.m.faddr(AHB_FIFO_BITS) = zero32(AHB_FIFO_BITS) and tm_fifo(tm_nindex).stop = zero32(AHB_FIFO_BITS) and
tm_fifo(tm_nindex).last_cbe /= ar.m.acc.cbe) then
av.m.dmai0.size := set_size_from_cbe(tm_fifo(tm_nindex).last_cbe);
av.m.dmai0.addr(1 downto 0) := set_addr_from_cbe(tm_fifo(tm_nindex).last_cbe, ar.m.acc.endianess);
av.m.dmai0.burst := '0';
end if;
-- Save size and offset for retry
av.m.retry_size := ar.m.dmai0.size;
av.m.retry_offset := ar.m.dmai0.addr(1 downto 0);
-- Restore size and offset for retry
if ar.m.retry = '1' then
av.m.dmai0.size := ar.m.retry_size;
av.m.dmai0.addr(1 downto 0) := ar.m.retry_offset;
end if;
elsif dmao0.retry = '1' then
av.m.dmai0.req := '1';
av.m.dmai0.addr := ar.m.dmai0.addr - 4;
av.m.faddr := ar.m.faddr - 1;
av.m.retry := '1';
-- Save size and offset for retry
av.m.retry_size := ar.m.dmai0.size;
av.m.retry_offset := ar.m.dmai0.addr(1 downto 0);
-- Restore size and offset for retry
av.m.dmai0.size := ar.m.retry_size;
av.m.dmai0.addr(1 downto 0) := ar.m.retry_offset;
end if;
if dmao0.ready = '1' then
av.m.first(2) := '0';
if dmao0.grant = '0' and ar.m.dmai0.req = '0' then av.m.active := '0'; end if;
if ar.m.hold(1 downto 0) = "00" then
av.m.dmai0.data := tm_fifoo_pta.data;
av.m.acc.fifo_addr(FIFO_DEPTH-1 downto 0) := ar.m.acc.fifo_addr(FIFO_DEPTH-1 downto 0) + 1;
end if;
if tm_fifo_pending(ar.m.acc.fifo_index) = '1' and ar.m.acc.fifo_addr(FIFO_DEPTH-1 downto 0) = tm_fifo(ar.m.acc.fifo_index).stop and
ar.m.hold(1 downto 0) /= "11" and ar.m.done(0) = '0' then
av.m.acc.fifo_index := tm_nindex; -- Go to next fifo
av.atp_trans.tm_fifo_ack(ar.m.acc.fifo_index) := pta_trans.tm_fifo(ar.m.acc.fifo_index).pending(RAM_LATENCY);
av.m.acc.fifo_addr := conv_std_logic_vector(av.m.acc.fifo_index, log2(FIFO_COUNT)) & tm_fifo(tm_nindex).start; -- Set fifo start address
if tm_fifo_pending(tm_nindex) = '0' or ar.m.hold(0) = '1' then
av.m.hold(1) := '1';
end if;
if tm_fifo(ar.m.acc.fifo_index).lastf = '1' or ar.m.last(1 downto 0) /= "00" then -- Transfer done
av.m.done(0) := '1';
end if;
end if;
elsif dmao0.error = '1' then
av.m.active := '0';
av.m.dmai0.req := '0';
if ar.m.done(0) = '0' then
if tm_fifo_pending(ar.m.acc.fifo_index) = '1' and tm_fifo(ar.m.acc.fifo_index).lastf = '1' then
av.m.acc.fifo_index := tm_nindex; -- Go to next fifo
av.atp_trans.tm_fifo_ack(ar.m.acc.fifo_index) := pta_trans.tm_fifo(ar.m.acc.fifo_index).pending(RAM_LATENCY);
av.m.done(0) := '1';
else
av.m.state := am_error;
end if;
end if;
end if;
if ar.m.done(0) = '1' and ar.m.active = '0' then
av.m.state := am_idle;
av.m.acc.pending := '0';
end if;
if av.m.dmai0.addr(AHB_FIFO_BITS) = tm_fifo(ar.m.acc.fifo_index).stop or ar.m.done(0) = '1' then av.m.dmai0.noreq := '1'; end if; -- to deassert req on last address phase
when am_error =>
if tm_fifo_pending(ar.m.acc.fifo_index) = '1' and ar.m.done(0) = '0' then
if tm_fifo(ar.m.acc.fifo_index).lastf = '1' then
av.m.done(0) := '1';
end if;
av.m.acc.fifo_index := tm_nindex; -- Go to next fifo
av.atp_trans.tm_fifo_ack(ar.m.acc.fifo_index) := pta_trans.tm_fifo(ar.m.acc.fifo_index).pending(RAM_LATENCY);
end if;
if ar.m.done(0) = '1' then
av.m.state := am_idle;
av.m.acc.pending := '0';
end if;
when others =>
end case;
end if; -- PCI target enabled
-- --------------------------------------------------------------------------------
-- AHB slave defaults
-- --------------------------------------------------------------------------------
-- Default
av.s.hready := '1'; slv_access := '0'; tb_access := '0'; av.s.hresp := HRESP_OKAY;
av.s.retry := '0';
av.s.atp.ctrl.en := '0';
av.s.atp.ctrl.data := ahbreadword(ahbsi.hwdata);
av.s.pta.ctrl.en := '0';
av.s.stoppciacc := '0';
ms_acc_pending := ar.atp_trans.msd_acc(0).pending xor pta_trans.msd_acc_ack(0);
ms_acc_cancel := ar.atp_trans.msd_acc_cancel(0) xor pta_trans.msd_acc_cancel_ack(0)(RAM_LATENCY);
ms_acc_done := ar.atp_trans.msd_acc_done_ack(0) xor pta_trans.msd_acc_done(0).done;
for i in 0 to FIFO_COUNT-1 loop
ms_fifo_pending(i) := pta_trans.msd_fifo(0)(i).pending(RAM_LATENCY) xor ar.atp_trans.msd_fifo_ack(0)(i);
ms_fifo_empty(i) := not (ar.atp_trans.msd_fifo(0)(i).pending(0) xor pta_trans.msd_fifo_ack(0)(i));
av.atp_trans.msd_fifo(0)(i).pending(1) := ar.atp_trans.msd_fifo(0)(i).pending(0);
av.atp_trans.msd_fifo(0)(i).pending(2) := ar.atp_trans.msd_fifo(0)(i).pending(1);
end loop;
ms_fifo := pr_pta_trans_gated.msd_fifo(0);
ms_acc_done_status := pr_pta_trans_gated.msd_acc_done(0);
accbufindex := 0;
-- PCI function number
ms_func := ar.s.atp_map(conv_integer(ar.s.hmaster))(2 downto 0);
ms_vifunc := conv_integer(ar.s.atp_map(conv_integer(av.s.hmaster))(2 downto 0));
if multifunc = 0 then ms_func := (others => '0'); ms_vifunc := 0; end if;
-- --------------------------------------------------------------------------------
-- AHB slave core
-- --------------------------------------------------------------------------------
if master /= 0 then -- PCI master enabled
if ms_acc_done = '1' then -- Handle PCI error on AHB to PCI write
av.atp_trans.msd_acc_done_ack(0) := pta_trans.msd_acc_done(0).done;
if ms_acc_done_status.status(3) = '1' then -- PCI configuration access done
av.s.cfg_status(1) := '1';
if ms_acc_done_status.status(2 downto 0) /= "000" then av.s.cfg_status(0) := '1'; end if;
else
if ar.irq.access_en = '1' and ms_acc_done_status.status(2 downto 0) /= "000" then av.irq.access_pirq := '1'; end if;
av.irq.access_status := ar.irq.access_status or ms_acc_done_status.status(2 downto 0);
end if;
end if;
-- Select next fifo
if ar.s.state = as_write then
if ar.s.atp.index /= FIFO_COUNT-1 then ms_index := ar.s.atp.index + 1;
else ms_index := 0; end if;
else
if ar.s.pta.index /= FIFO_COUNT-1 then ms_index := ar.s.pta.index + 1;
else ms_index := 0; end if;
end if;
-- Access buffer
if ms_acc_pending = '0' and ar.s.accbuf(0).pending = '1' then
av.atp_trans.msd_acc(0) := ar.s.accbuf(0);
av.atp_trans.msd_acc(0).pending := not ar.atp_trans.msd_acc(0).pending;
av.s.accbuf(0) := ar.s.accbuf(1);
av.s.accbuf(1) := ar.s.accbuf(2);
av.s.accbuf(2) := ar.s.accbuf(3);
av.s.accbuf(3).pending := '0';
end if;
-- Set prefetch burst length
blen := x"00" & ar.s.blen;
-- AHB access latchning
if (ahbsi.hready and ahbsi.hsel(hsindex) and ahbsi.htrans(1)) = '1' then
slv_access := '1';
av.s.haddr := ahbsi.haddr; av.s.hwrite := ahbsi.hwrite;
av.s.hsel := ahbsi.hsel(hsindex); av.s.hmbsel := ahbsi.hmbsel(0 to 2);
av.s.htrans := ahbsi.htrans; av.s.hsize := ahbsi.hsize;
av.s.hburst := ahbsi.hburst(0);
av.s.hmaster := ahbsi.hmaster;
end if;
-- PCI trace buffer access
if tracebuffer /= 0 then
if (ahbsi.hsel(hsindex) and ahbsi.hmbsel(1) and ahbsi.haddr(17) and ahbsi.htrans(1)) = '1' then
tb_access := '1';
end if;
end if;
-- Second retry/error cycle
if ar.s.retry = '1' then
if ar.s.hresp = HRESP_ERROR then
av.s.hresp := HRESP_ERROR;
else
av.s.hresp := HRESP_RETRY;
if ar.s.pending = "00" and ar.s.hwrite = '0' and ar.s.start = '0' and ar.s.stoppciacc = '0' then
av.s.pending := "01";
av.s.addr := ar.s.haddr;
av.s.write := ar.s.hwrite;
av.s.master := ar.s.hmaster;
av.s.burst := ar.s.hburst;
av.s.size := ar.s.hsize;
av.s.config := (not ar.s.hmbsel(0) and ar.s.haddr(16));
av.s.io := (not ar.s.hmbsel(0) and not ar.s.haddr(16));
av.s.pta.ctrl.addr := conv_std_logic_vector(ar.s.pta.index, log2(FIFO_COUNT)) & ar.s.haddr(AHB_FIFO_BITS);
-- Change to sigle access on PCI IO and PCI CONF
if ar.s.io_cfg_burst(0) = '0' and av.s.config = '1' then av.s.burst := '0'; end if;
if ar.s.io_cfg_burst(1) = '0' and av.s.io = '1' then av.s.burst := '0'; end if;
-- Use blen if less than 1k limit and AHB-master is unmasked, else use 1k limit
if (not av.s.addr(9 downto 2)) < ar.s.blen(7 downto 0) or ar.s.blenmask(conv_integer(av.s.master)) = '0' then blen(7 downto 0) := (not av.s.addr(9 downto 2)); end if;
if ar.s.continue = '0' then
if ar.s.hmbsel(0) = '0' then -- config access and io access
if ar.s.haddr(16) = '1' then
av.s.addr := set_pci_conf_addr(ar.s.haddr, ar.s.cfg_bus);
else av.s.addr := set_pci_io_addr(ar.s.haddr, ar.s.io_map); end if;
else
av.s.addr := set_atp_addr(ar.s.haddr, ar.s.atp_map, ar.s.hmaster, AADDR_WIDTH);
end if;
if ms_acc_pending = '0' and ar.s.accbuf(0).pending = '0' then
av.atp_trans.msd_acc(0).pending := not ar.atp_trans.msd_acc(0).pending;
av.atp_trans.msd_acc(0).addr := av.s.addr;
av.atp_trans.msd_acc(0).func := ms_func; -- set PCI function
if av.s.config = '1' then av.atp_trans.msd_acc(0).acctype := CONF_READ;
elsif av.s.io = '1' then av.atp_trans.msd_acc(0).acctype := IO_READ;
else
if av.s.burst = '1' then av.atp_trans.msd_acc(0).acctype := MEM_R_MULT;
else av.atp_trans.msd_acc(0).acctype := MEM_READ; end if;
end if;
av.atp_trans.msd_acc(0).accmode := av.s.burst & '1' & av.s.burst;
av.atp_trans.msd_acc(0).size := av.s.size;
av.atp_trans.msd_acc(0).offset := ar.s.haddr(1 downto 0);
av.atp_trans.msd_acc(0).index := ar.s.pta.index;
av.atp_trans.msd_acc(0).length := blen;
av.atp_trans.msd_acc(0).cbe := (others => '0'); -- not used
av.atp_trans.msd_acc(0).endianess := '0'; -- not used
else
accbufindex := 0;
for i in 3 downto 0 loop
if av.s.accbuf(i).pending = '0' then accbufindex := i; end if;
end loop;
av.s.accbuf(accbufindex).pending := '1';
av.s.accbuf(accbufindex).addr := av.s.addr;
av.s.accbuf(accbufindex).func := ms_func; -- set PCI function
if av.s.config = '1' then av.s.accbuf(accbufindex).acctype := CONF_READ;
elsif av.s.io = '1' then av.s.accbuf(accbufindex).acctype := IO_READ;
else
if av.s.burst = '1' then av.s.accbuf(accbufindex).acctype := MEM_R_MULT;
else av.s.accbuf(accbufindex).acctype := MEM_READ; end if;
end if;
av.s.accbuf(accbufindex).accmode := av.s.burst & '1' & av.s.burst;
av.s.accbuf(accbufindex).size := av.s.size;
av.s.accbuf(accbufindex).offset := ar.s.haddr(1 downto 0);
av.s.accbuf(accbufindex).index := ar.s.pta.index;
av.s.accbuf(accbufindex).length := blen;
av.s.accbuf(accbufindex).cbe := (others => '0'); -- not used
av.s.accbuf(accbufindex).endianess := '0'; -- not used
end if;
end if;
end if;
end if;
end if;
if ms_fifo_pending(ar.s.pta.index) = '1' and ar.s.pending = "01" and ar.s.discard = '0' then
av.s.done_fifo := (others => '0');
av.s.pending := "10";
av.s.pta.ctrl.addr := conv_std_logic_vector(ar.s.pta.index, log2(FIFO_COUNT)) & ar.s.pta.ctrl.addr(FIFO_DEPTH-1 downto 0);
elsif ar.s.pending = "10" then
av.s.pending := "11";
av.s.pta.ctrl.addr := conv_std_logic_vector(ar.s.pta.index, log2(FIFO_COUNT)) & (ar.s.pta.ctrl.addr(FIFO_DEPTH-1 downto 0) + 1);
av.s.hrdata := ms_fifoo_pta.data;
if ms_fifo(ar.s.pta.index).start = ms_fifo(ar.s.pta.index).stop then
av.s.oneword := '1';
av.s.pta.ctrl.addr := conv_std_logic_vector(ar.s.pta.index, log2(FIFO_COUNT)) & ar.s.pta.ctrl.addr(FIFO_DEPTH-1 downto 0);
if ms_fifo_pending(ms_index) = '0' then av.s.done_fifo(0) := '1'; end if;
if ms_fifo(ar.s.pta.index).lastf = '1' then av.s.done_fifo(1) := '1'; end if;
else av.s.oneword := '0'; end if;
end if;
-- FIFO read enable
av.s.pta.ctrl.en := ms_fifo_pending(ar.s.pta.index);
-- Discard unused fifo data
if ar.s.discard = '1' then
if ms_acc_cancel = '0' then
-- moved to PCI master
av.s.discard := '0';
end if;
end if;
-- AHB slave state machine
case ar.s.state is
when as_idle =>
av.s.continue := '0';
av.s.first := '1';
av.s.firstf := '1';
av.s.tb_ren := '0';
if slv_access = '1' then
if tb_access = '1' then -- PCI trace
av.s.hready := '0';
av.s.state := as_pcitrace;
av.s.tb_ren := '1';
else
if av.s.hwrite = '1' and ms_fifo_empty(ar.s.atp.index) = '1' and
pta_trans.ca_pcimsten(ms_vifunc) = '1' and (pci_hard_rst or pci_master_rst) = '0' then -- Write
av.s.state := as_write;
elsif ar.s.pending(1) = '1' and ar.s.master = ahbsi.hmaster and
(pci_hard_rst or pci_master_rst) = '0' then -- Read
if (ms_fifo(ar.s.pta.index).status(2 downto 1) /= "00" and
ms_fifo(ar.s.pta.index).start = ms_fifo(ar.s.pta.index).stop) or -- Master/Target abort
(ms_fifo(ar.s.pta.index).status(0) = '1') then -- PAR error
if ar.s.config = '1' then -- Master/target abort during PCI config access
av.s.state := as_read;
av.s.cfg_status := "11";
else
if ar.s.erren = '1' and ms_fifo(ar.s.pta.index).status(2 downto 1) /= "00" and
ms_fifo(ar.s.pta.index).start = ms_fifo(ar.s.pta.index).stop then
av.s.hready := '0';
av.s.hresp := HRESP_ERROR;
av.s.retry := '1';
end if;
if ar.s.parerren = '1' and ms_fifo(ar.s.pta.index).status(0) = '1' then
av.s.hready := '0';
av.s.hresp := HRESP_ERROR;
av.s.retry := '1';
end if;
if ar.s.burst = '1' then
av.atp_trans.msd_acc_cancel(0) := not ar.atp_trans.msd_acc_cancel(0);
av.s.discard := '1';
else
av.s.pta.index := ms_index; -- Go to next fifo
av.atp_trans.msd_fifo_ack(0)(ar.s.pta.index) := pta_trans.msd_fifo(0)(ar.s.pta.index).pending(RAM_LATENCY);
end if;
av.s.pending := (others => '0');
if ar.irq.access_en = '1' then av.irq.access_pirq := '1'; end if; -- If enabled, generate irq on error
av.irq.access_status := ar.irq.access_status or ms_fifo(ar.s.pta.index).status(2 downto 0); -- Update irq status
end if;
else
if ar.s.config = '1' then av.s.cfg_status(1) := '1'; end if;
av.s.state := as_read;
end if;
elsif ms_fifo_empty(ar.s.atp.index) = '1' and pta_trans.ca_pcimsten(ms_vifunc) = '0' and
(pci_hard_rst or pci_master_rst) = '0' then
av.s.state := as_checkpcimst;
av.s.hready := '0';
elsif (pci_hard_rst or pci_master_rst) = '1' then -- Error during reset
av.s.hresp := HRESP_ERROR;
av.s.hready := '0';
av.s.retry := '1';
else -- Retry
av.s.hresp := HRESP_RETRY;
av.s.hready := '0';
av.s.retry := '1';
end if;
end if;
end if;
when as_checkpcimst =>
if ar.s.hmbsel(0) = '0' and ar.s.haddr(16) = '1' and
((ar.s.haddr(15 downto 11) = zero32(15 downto 11) and pta_trans.ca_host = '0') or ar.s.fakehost = '1') then
if ar.s.hwrite = '1' then
av.s.state := as_write;
else
av.s.hresp := HRESP_RETRY;
av.s.hready := '0';
av.s.retry := '1';
av.s.state := as_idle;
end if;
else
av.s.hresp := HRESP_ERROR;
av.s.hready := '0';
av.s.retry := '1';
av.s.state := as_idle;
end if;
when as_read =>
av.s.pending := (others => '0');
if ar.s.hready = '1' then
if ar.s.htrans(1) = '1' then
if ms_fifo_pending(ar.s.pta.index) = '1' then
if ar.s.pta.ctrl.addr(FIFO_DEPTH-1 downto 0) = ms_fifo(ar.s.pta.index).stop or ar.s.burst = '0' or ar.s.oneword = '1' then
av.s.pta.index := ms_index; -- Go to next fifo
av.atp_trans.msd_fifo_ack(0)(ar.s.pta.index) := pta_trans.msd_fifo(0)(ar.s.pta.index).pending(RAM_LATENCY);
if ms_fifo_pending(ms_index) = '0' then av.s.done_fifo(0) := '1'; end if;
if ms_fifo(ar.s.pta.index).lastf = '1' then av.s.done_fifo(1) := '1'; end if;
end if;
end if;
av.s.hrdata := ms_fifoo_pta.data;
av.s.pta.ctrl.addr := conv_std_logic_vector(av.s.pta.index, log2(FIFO_COUNT)) & (ar.s.pta.ctrl.addr(FIFO_DEPTH-1 downto 0) + 1);
end if;
if ahbsi.htrans(1) = '1' and ahbsi.hsel(hsindex) = '1' then
if ahbsi.htrans(0) = '0' then
if ahbsi.hwrite = '1' and ms_fifo_empty(ar.s.atp.index) = '1' then -- new write access
av.s.state := as_write;
if ar.s.burst = '1' then
av.s.discard := '1';
av.atp_trans.msd_acc_cancel(0) := not ar.atp_trans.msd_acc_cancel(0);
end if;
else -- retry
av.s.hready := '0';
av.s.hresp := HRESP_RETRY;
av.s.retry := '1';
av.s.state := as_idle;
if ar.s.burst = '1' then
av.s.discard := '1';
av.atp_trans.msd_acc_cancel(0) := not ar.atp_trans.msd_acc_cancel(0);
end if;
end if;
end if;
if ms_fifo_pending(ar.s.pta.index) = '1' and
((ms_fifo(ar.s.pta.index).status(2 downto 1) /= "00" and -- Master/Target abort
ar.s.pta.ctrl.addr(FIFO_DEPTH-1 downto 0) = ms_fifo(ar.s.pta.index).stop) or
(ms_fifo(ar.s.pta.index).status(0) = '1')) then -- PAR error
if ar.s.config = '1' then -- No AHB error for PCI Config Space
av.s.cfg_status := "11";
av.s.hready := '0';
av.s.hresp := HRESP_RETRY;
av.s.retry := '1';
else
if ar.s.erren = '1' and ms_fifo(ar.s.pta.index).status(2 downto 1) /= "00" and
ar.s.pta.ctrl.addr(FIFO_DEPTH-1 downto 0) = ms_fifo(ar.s.pta.index).stop then
av.s.hready := '0';
av.s.hresp := HRESP_ERROR;
av.s.retry := '1';
end if;
if ar.s.parerren = '1' and ms_fifo(ar.s.pta.index).status(0) = '1' then
av.s.hready := '0';
av.s.hresp := HRESP_ERROR;
av.s.retry := '1';
end if;
av.irq.access_status := ar.irq.access_status or ms_fifo(ar.s.pta.index).status(2 downto 0); -- Update irq status
if ar.irq.access_en = '1' then av.irq.access_pirq := '1'; end if; -- If enabled, generate irq on error
end if;
av.s.state := as_idle;
if ar.s.burst = '1' then
av.s.discard := '1';
av.atp_trans.msd_acc_cancel(0) := not ar.atp_trans.msd_acc_cancel(0);
end if;
elsif (ahbsi.hwrite = '0' and ar.s.done_fifo(0) = '1') or ar.s.burst = '0' or ar.s.oneword = '1' then -- no pending fifo => retry
av.s.hready := '0';
av.s.hresp := HRESP_RETRY;
av.s.retry := '1';
av.s.stoppciacc := not pta_trans.ca_pcimsten(ms_vifunc);
if ar.s.burst = '1' and ahbsi.htrans(0) = '1' then
if ar.s.done_fifo(1) = '1' then
av.s.discard := '1';
av.atp_trans.msd_acc_cancel(0) := not ar.atp_trans.msd_acc_cancel(0);
else
av.s.continue := '1'; -- Only for continuing bursts
end if;
end if;
av.s.state := as_idle;
end if;
elsif ahbsi.hsel(hsindex) = '0' or ahbsi.htrans(0) = '0' then -- idle
av.s.state := as_idle;
if ar.s.burst = '1' then
av.s.discard := '1';
av.atp_trans.msd_acc_cancel(0) := not ar.atp_trans.msd_acc_cancel(0);
end if;
end if;
end if;
when as_write =>
av.s.first := '0';
if ar.s.first = '1' then -- Store fifo start address
if ar.s.hmbsel(0) = '0' then -- mem/io/config access
if ar.s.haddr(16) = '1' then
av.s.addr := set_pci_conf_addr(ar.s.haddr, ar.s.cfg_bus);
av.s.offset := ar.s.haddr(1 downto 0);
else av.s.addr := set_pci_io_addr(ar.s.haddr, ar.s.io_map); end if;
else
av.s.addr := set_atp_addr(ar.s.haddr, ar.s.atp_map, ar.s.hmaster, AADDR_WIDTH);
end if;
av.s.size := ar.s.hsize;
av.s.config := (not ar.s.hmbsel(0) and ar.s.haddr(16));
av.s.io := (not ar.s.hmbsel(0) and not ar.s.haddr(16));
if ms_acc_pending = '0' and ar.s.accbuf(0).pending = '0' then
av.atp_trans.msd_acc(0).pending := not ar.atp_trans.msd_acc(0).pending;
av.atp_trans.msd_acc(0).addr := av.s.addr;
av.atp_trans.msd_acc(0).func := ms_func; -- set PCI function
if av.s.config = '1' then av.atp_trans.msd_acc(0).acctype := CONF_WRITE;
elsif av.s.io = '1' then av.atp_trans.msd_acc(0).acctype := IO_WRITE;
else av.atp_trans.msd_acc(0).acctype := MEM_WRITE; end if;
av.atp_trans.msd_acc(0).accmode := "00" & ar.s.hburst;
av.atp_trans.msd_acc(0).size := av.s.size;
av.atp_trans.msd_acc(0).offset := ar.s.haddr(1 downto 0);
av.atp_trans.msd_acc(0).index := ar.s.atp.index;
av.atp_trans.msd_acc(0).length := (others => '0'); -- not used
av.atp_trans.msd_acc(0).cbe := (others => '0'); -- not used
av.atp_trans.msd_acc(0).endianess := '0'; -- not used
else
accbufindex := 0;
for i in 3 downto 0 loop
if av.s.accbuf(i).pending = '0' then accbufindex := i; end if;
end loop;
av.s.accbuf(accbufindex).pending := '1';
av.s.accbuf(accbufindex).addr := av.s.addr;
av.s.accbuf(accbufindex).func := ms_func; -- set PCI function
if av.s.config = '1' then av.s.accbuf(accbufindex).acctype := CONF_WRITE;
elsif av.s.io = '1' then av.s.accbuf(accbufindex).acctype := IO_WRITE;
else av.s.accbuf(accbufindex).acctype := MEM_WRITE; end if;
av.s.accbuf(accbufindex).accmode := "00" & ar.s.hburst;
av.s.accbuf(accbufindex).size := av.s.size;
av.s.accbuf(accbufindex).offset := ar.s.haddr(1 downto 0);
av.s.accbuf(accbufindex).index := ar.s.atp.index;
av.s.accbuf(accbufindex).length := (others => '0'); -- not used
av.s.accbuf(accbufindex).cbe := (others => '0'); -- not used
av.s.accbuf(accbufindex).endianess := '0'; -- not used
end if;
end if;
if ar.s.hready = '1' then
if ar.s.htrans(1) = '1' then
if ar.s.haddr(AHB_FIFO_BITS) = ones32(AHB_FIFO_BITS) or ahbsi.htrans(0) = '0' then
av.s.firstf := '0';
av.s.atp.index := ms_index; -- Go to next fifo
av.atp_trans.msd_fifo(0)(ar.s.atp.index).pending(0) := not ar.atp_trans.msd_fifo(0)(ar.s.atp.index).pending(0);
if ar.s.firstf = '1' then
av.atp_trans.msd_fifo(0)(ar.s.atp.index).start := av.s.addr(AHB_FIFO_BITS);
av.atp_trans.msd_fifo(0)(ar.s.atp.index).firstf := '1';
else
av.atp_trans.msd_fifo(0)(ar.s.atp.index).start := (others => '0');
av.atp_trans.msd_fifo(0)(ar.s.atp.index).firstf := '0';
end if;
av.atp_trans.msd_fifo(0)(ar.s.atp.index).stop := ar.s.haddr(AHB_FIFO_BITS);
av.atp_trans.msd_fifo(0)(ar.s.atp.index).lastf := not ahbsi.htrans(0) or not ms_fifo_empty(ms_index);
av.atp_trans.msd_fifo(0)(ar.s.atp.index).status := (others => '0'); -- Not used
av.atp_trans.msd_fifo(0)(ar.s.atp.index).last_cbe := (others => '0'); -- Not used
end if;
av.s.atp.ctrl.en := '1';
av.s.atp.ctrl.addr := conv_std_logic_vector(ar.s.atp.index, log2(FIFO_COUNT)) & ar.s.haddr(AHB_FIFO_BITS);
end if;
if ahbsi.htrans(1) = '1' and ahbsi.hsel(hsindex) = '1' then
if ahbsi.htrans(0) = '0' then
if ahbsi.hwrite = '1' and ms_fifo_empty(ms_index) = '1' then -- new write access
av.s.first := '1';
av.s.firstf := '1';
else -- retry
av.s.hready := '0';
av.s.hresp := HRESP_RETRY;
av.s.retry := '1';
av.s.state := as_idle;
end if;
end if;
if ahbsi.hwrite = '1' and ar.s.haddr(AHB_FIFO_BITS) = ones32(AHB_FIFO_BITS) and ms_fifo_empty(ms_index) = '0' then -- no empty fifo => retry
av.s.hready := '0';
av.s.hresp := HRESP_RETRY;
av.s.retry := '1';
av.s.state := as_idle;
end if;
elsif ahbsi.hsel(hsindex) = '0' or ahbsi.htrans(0) = '0' then -- idle
av.s.state := as_idle;
end if;
end if;
when as_pcitrace =>
if ar.s.hready = '1' then
if tb_access = '1' then
av.s.hready := '0';
av.s.tb_ren := '1';
else
av.s.state := as_idle;
if ahbsi.htrans(1) = '1' and ahbsi.hsel(hsindex) = '1' then
av.s.hready := '0';
av.s.retry := '1';
av.s.hresp := HRESP_RETRY;
end if;
end if;
else
av.s.tb_ren := '0';
if ar.s.tb_ren = '0' then
av.s.hready := '1';
if ar.s.haddr(16) = '0' then
av.s.hrdata := pt_fifoo_ad.data;
else
av.s.hrdata := zero32(31 downto 20) & pt_fifoo_sig.data(16 downto 0) & "000";
end if;
else
av.s.hready := '0';
end if;
end if;
when others =>
end case;
end if; -- PCI master enabled
-- --------------------------------------------------------------------------------
-- DMA defaults
-- --------------------------------------------------------------------------------
av.dma.irq := '0';
-- FIFO enable(read)/write
av.dma.ptd.ctrl.en := '0';
av.dma.dtp.ctrl.en := '0';
av.dma.dtp.ctrl.data := dmao1.data;
av.dma.dmai1.noreq := '0';
av.dma.desc.addr(3 downto 0) := (others => '0');
md_acc_pending := ar.atp_trans.msd_acc(1).pending xor pta_trans.msd_acc_ack(1);
md_acc_cancel := ar.atp_trans.msd_acc_cancel(1) xor pta_trans.msd_acc_cancel_ack(1)(RAM_LATENCY);
md_acc_done := ar.atp_trans.msd_acc_done_ack(1) xor pta_trans.msd_acc_done(1).done;
for i in 0 to FIFO_COUNT-1 loop
md_fifo_pending(i) := pta_trans.msd_fifo(1)(i).pending(RAM_LATENCY) xor ar.atp_trans.msd_fifo_ack(1)(i);
md_fifo_empty(i) := not (ar.atp_trans.msd_fifo(1)(i).pending(0) xor pta_trans.msd_fifo_ack(1)(i));
av.atp_trans.msd_fifo(1)(i).pending(1) := ar.atp_trans.msd_fifo(1)(i).pending(0);
av.atp_trans.msd_fifo(1)(i).pending(2) := ar.atp_trans.msd_fifo(1)(i).pending(1);
end loop;
md_fifo := pr_pta_trans_gated.msd_fifo(1);
md_acc_done_status := pr_pta_trans_gated.msd_acc_done(1);
-- --------------------------------------------------------------------------------
-- DMA core
-- --------------------------------------------------------------------------------
if dma /= 0 then -- DMA enabled
-- Select next fifo
if ar.dma.state = dma_read then
if ar.dma.dtp.index /= FIFO_COUNT-1 then md_index := ar.dma.dtp.index + 1;
else md_index := 0; end if;
else
if ar.dma.ptd.index /= FIFO_COUNT-1 then md_index := ar.dma.ptd.index + 1;
else md_index := 0; end if;
end if;
case ar.dma.state is
when dma_idle =>
av.dma.err := (others => '0');
av.dma.running := '0';
av.dma.dmai1.req := '0';
av.dma.dmai1.write := '0';
av.dma.dmai1.burst := '1';
av.dma.dmai1.addr := ar.dma.desc.addr;
av.dma.desc.chcnt := ar.dma.numch;
if ar.dma.errstatus /= "00000" then
av.dma.en := '0';
elsif ar.dma.en = '1' then
av.dma.state := dma_read_desc;
av.dma.rcnt := (others => '0');
av.dma.dmai1.req := '1';
av.dma.dmai1.size := "10";
av.dma.running := '1';
end if;
when dma_read_desc =>
av.dma.active := '0';
av.dma.dma_hold := (others => '0');
av.dma.done := (others => '0');
av.dma.first(0) := '1';
av.dma.retry := '0';
if ar.dma.rcnt = "11" and ar.dma.desc.desctype /= "01"
and (ar.dma.desc.emptych = '0' or ar.dma.desc.chcnt = "000") then av.dma.dmai1.req := '0';
else av.dma.dmai1.req := '1'; end if;
av.dma.dmai1.burst := '1';
if dmao1.grant = '1' then
av.dma.dmai1.addr := ar.dma.dmai1.addr + 4;
if ar.dma.dmai1.addr(3 downto 2) = "11" then
if ar.dma.desc.desctype = "01" then
av.dma.dmai1.addr := dmao1.data;
elsif ar.dma.desc.emptych = '1' then
av.dma.desc.addr := ar.dma.desc.nextch;
av.dma.dmai1.addr := ar.dma.desc.nextch;
if ar.dma.desc.chcnt = "000" then
av.dma.dmai1.req := '0';
end if;
else
av.dma.dmai1.req := '0';
end if;
end if;
elsif dmao1.retry = '1' then
av.dma.dmai1.addr := ar.dma.dmai1.addr - 4;
end if;
if av.dma.dmai1.addr(3 downto 2) = "11" then av.dma.dmai1.noreq := '1'; end if;
if dmao1.ready = '1' then
av.dma.err := (others => '0');
av.dma.rcnt := ar.dma.rcnt + 1;
case ar.dma.rcnt is
when "00" => -- Ctrl
av.dma.desc.en := dmao1.data(31);
av.dma.desc.irqen := dmao1.data(30);
av.dma.desc.write := dmao1.data(29);
av.dma.desc.tw := dmao1.data(28);
av.dma.desc.cio := dmao1.data(27 downto 26);
av.dma.desc.acctype := dmao1.data(25 downto 22);
av.dma.desc.desctype := dmao1.data(21 downto 20);
-- dmao1.data(19) = err
av.dma.desc.len := dmao1.data(15 downto 0);
when "01" => -- PCI address / Next DMA CH
if ar.dma.desc.desctype = "01" then
av.dma.desc.ch := ar.dma.desc.addr;
av.dma.desc.nextch := dmao1.data;
av.dma.desc.cnt := ar.dma.desc.len;
av.dma.desc.chid := ar.dma.desc.acctype(2 downto 0);
av.dma.desc.emptych := '1';
else
if ar.dma.desc.en = '1' then
av.dma.desc.emptych := '0';
end if;
av.dma.desc.paddr := dmao1.data;
end if;
when "10" => -- AHB address / Next desc
if ar.dma.desc.desctype = "01" then
av.dma.desc.addr := dmao1.data;
else
av.dma.desc.aaddr := dmao1.data;
end if;
when "11" => -- Next desc / ----
if ar.dma.desc.en = '1' then
if ar.dma.desc.desctype = "00" then
av.dma.desc.chcnt := ar.dma.numch;
av.dma.desc.nextdesc := dmao1.data;
if ar.dma.desc.write = '1' then -- AHB read => PCI write
av.dma.state := dma_read;
av.dma.dmai1.req := '1';
av.dma.dmai1.write := '0';
av.dma.dmai1.addr := ar.dma.desc.aaddr;
if ar.dma.desc.len /= x"0000" then av.dma.dmai1.burst := '1';
else av.dma.dmai1.burst := '0'; end if;
av.dma.dmai1.size := "10"; -- 32-bit access -- add support for unaligned accesses
av.dma.dtp.ctrl.addr := conv_std_logic_vector(ar.dma.dtp.index, log2(FIFO_COUNT)) & ar.dma.desc.aaddr(AHB_FIFO_BITS); -- Set fifo start address
av.dma.faddr := ar.dma.desc.aaddr(AHB_FIFO_BITS);
av.dma.len := (others => '0');
av.dma.errlen := (others => '0');
else -- PCI read => AHB write
av.dma.state := dma_write;
av.dma.first := "010";
av.dma.dma_hold := "111";
av.dma.addr := ar.dma.desc.aaddr;
av.dma.len := (others => '0');
av.dma.errlen := (others => '0');
end if;
-- Setup access [Read and Write]
av.atp_trans.msd_acc(1).pending := not ar.atp_trans.msd_acc(1).pending;
av.atp_trans.msd_acc(1).addr := ar.dma.desc.paddr;
av.atp_trans.msd_acc(1).func := "000"; -- DMA uses PCI function 0
if ar.dma.desc.write = '1' then -- AHB read => PCI write
av.atp_trans.msd_acc(1).index := ar.dma.dtp.index;
if ar.dma.desc.cio = "01" then -- PCI IO access
av.atp_trans.msd_acc(1).acctype := IO_WRITE;
elsif ar.dma.desc.cio = "01" then -- PCI Configuration access
av.atp_trans.msd_acc(1).acctype := CONF_WRITE;
else -- PCI Memory access
av.atp_trans.msd_acc(1).acctype := MEM_WRITE;
end if;
else
av.atp_trans.msd_acc(1).index := ar.dma.ptd.index;
if ar.dma.desc.cio = "01" then -- PCI IO access
av.atp_trans.msd_acc(1).acctype := IO_READ;
elsif ar.dma.desc.cio = "01" then -- PCI Configuration access
av.atp_trans.msd_acc(1).acctype := CONF_READ;
else -- PCI Memory access
if ar.dma.desc.len /= x"0000" then
av.atp_trans.msd_acc(1).acctype := MEM_R_MULT;
else
av.atp_trans.msd_acc(1).acctype := MEM_READ;
end if;
end if;
end if;
if ar.dma.desc.len /= x"0000" then
av.atp_trans.msd_acc(1).accmode := "011";
else
av.atp_trans.msd_acc(1).accmode := "010";
end if;
av.atp_trans.msd_acc(1).size := "010"; -- add size support
av.atp_trans.msd_acc(1).offset := ar.dma.desc.paddr(1 downto 0);
av.atp_trans.msd_acc(1).length := ar.dma.desc.len;
av.atp_trans.msd_acc(1).cbe := (others => '0'); -- not used
av.atp_trans.msd_acc(1).endianess := av.dma.desc.tw;
end if;
else
if ar.dma.desc.emptych = '0' then
av.dma.state := dma_next_channel;
av.dma.dmai1.req := '1';
av.dma.dmai1.write := '1';
av.dma.dmai1.burst := '0';
av.dma.dmai1.addr := ar.dma.desc.ch + 8;
av.dma.dmai1.data := ar.dma.desc.nextdesc;
else
if ar.dma.desc.chcnt = "000" then
av.dma.en := '0';
av.dma.state := dma_idle;
else
av.dma.desc.chcnt := ar.dma.desc.chcnt - 1;
end if;
end if;
end if;
when others =>
end case;
elsif dmao1.error = '1' then
av.dma.en := '0';
av.dma.state := dma_idle;
av.dma.dmai1.req := '0';
av.dma.irq := '1'; av.dma.irqstatus(0) := '1';
av.dma.errstatus(0) := '1';
end if;
when dma_next_channel =>
if dmao1.grant = '1' then
av.dma.dmai1.req := '0';
elsif dmao1.retry = '1' then
av.dma.dmai1.req := '1';
end if;
if dmao1.ready = '1' then
av.dma.state := dma_read_desc;
av.dma.dmai1.req := '1';
av.dma.dmai1.write := '0';
av.dma.dmai1.burst := '1';
av.dma.desc.addr := ar.dma.desc.nextch;
av.dma.dmai1.addr := ar.dma.desc.nextch;
elsif dmao1.error = '1' then
av.dma.en := '0';
av.dma.state := dma_idle;
av.dma.dmai1.req := '0';
av.dma.irq := '1'; av.dma.irqstatus(0) := '1';
end if;
when dma_write_status =>
if dmao1.grant = '1' then
if ar.dma.desc.cnt = x"0001" then -- Next Channel
av.dma.dmai1.addr := ar.dma.desc.ch + 8;
else
av.dma.dmai1.req := '0';
end if;
elsif dmao1.retry = '1' then
av.dma.dmai1.req := '1';
av.dma.dmai1.addr := ar.dma.desc.addr;
end if;
if dmao1.ready = '1' then
if ar.dma.err /= "000" then
av.dma.en := '0';
av.dma.state := dma_idle;
av.dma.irq := '1'; av.dma.irqstatus(0) := '1';
else
if ar.dma.desc.irqen = '1' then
av.dma.irq := '1';
av.dma.irqstatus(1) := '1';
av.dma.irqch(conv_integer(ar.dma.desc.chid)) := '1';
end if;
if ar.dma.en = '0' then -- DMA disabled
av.dma.state := dma_idle;
av.dma.desc.addr := ar.dma.desc.nextdesc;
else
if ar.dma.desc.cnt = x"0001" then -- Next Channel
av.dma.state := dma_next_channel;
av.dma.dmai1.req := '1';
av.dma.dmai1.write := '1';
av.dma.dmai1.burst := '0';
av.dma.dmai1.data := ar.dma.desc.nextdesc;
else -- Next Desc
if ar.dma.desc.cnt /= x"0000" then
av.dma.desc.cnt := av.dma.desc.cnt - 1;
end if;
av.dma.state := dma_read_desc;
av.dma.dmai1.req := '1';
av.dma.dmai1.write := '0';
av.dma.dmai1.burst := '1';
av.dma.desc.addr := ar.dma.desc.nextdesc;
av.dma.dmai1.addr := ar.dma.desc.nextdesc;
end if;
end if;
end if;
elsif dmao1.error = '1' then
av.dma.en := '0';
av.dma.state := dma_idle;
av.dma.dmai1.req := '0';
av.dma.irq := '1'; av.dma.irqstatus(0) := '1';
av.dma.errstatus(0) := '1';
end if;
when dma_read => -- AHB read => PCI write
if md_fifo_empty(ar.dma.dtp.index) = '1' and ar.dma.dma_hold(0) = '1' and ar.dma.done(0) = '0' and ar.dma.active = '0' then
av.dma.dmai1.req := '1';
av.dma.dma_hold(1 downto 0) := "00";
end if;
if dmao1.grant = '1' then
av.dma.active := '1';
av.dma.dmai1.addr := ar.dma.dmai1.addr + 4;
if ar.dma.len /= ar.dma.desc.len then
av.dma.len := ar.dma.len + 1;
end if;
if ar.dma.dmai1.addr(AHB_FIFO_BITS) = ones32(AHB_FIFO_BITS) or ar.dma.len = ar.dma.desc.len then
if md_fifo_empty(md_index) = '0' then
av.dma.dmai1.req := '0';
av.dma.dma_hold(0) := '1';
end if;
if ar.dma.len = ar.dma.desc.len then
av.dma.dmai1.req := '0';
av.dma.done(1) := '1';
end if;
end if;
-- Retry save & restore
av.dma.retry := '0';
-- Save len for retry
av.dma.retry_len := ar.dma.len;
-- Restore len for retry
if ar.dma.retry = '1' then
av.dma.len := ar.dma.retry_len;
end if;
elsif dmao1.retry = '1' then
av.dma.dmai1.req := '1';
av.dma.dmai1.addr := ar.dma.dmai1.addr - 4;
--av.dma.len := ar.dma.len - 1;
av.dma.done(1) := '0';
-- Retry save & restore
av.dma.retry := '1';
-- Save len for retry
av.dma.retry_len := ar.dma.len;
-- Restore len for retry
av.dma.len := ar.dma.retry_len;
end if;
if dmao1.ready = '1' then
if ar.dma.errlen /= ar.dma.desc.len then
av.dma.errlen := ar.dma.errlen + 1;
end if;
if dmao1.grant = '0' then av.dma.active := '0'; end if;
if ar.dma.faddr(AHB_FIFO_BITS) /= ones32(AHB_FIFO_BITS) and ar.dma.done(1) = '0' then -- Store data in fifo
av.dma.faddr(AHB_FIFO_BITS) := ar.dma.faddr(AHB_FIFO_BITS) + 1;
else -- Last word in fifo
av.dma.faddr(AHB_FIFO_BITS) := (others => '0');
av.dma.dtp.index := md_index; -- Go to next fifo
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).pending(0) := not ar.atp_trans.msd_fifo(1)(ar.dma.dtp.index).pending(0);
if ar.dma.first(0) = '1' then -- Mark first fifo in transfer
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).firstf := '1';
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).start := ar.dma.desc.aaddr(AHB_FIFO_BITS);
av.dma.first(0) := '0';
else
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).start := (others => '0');
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).firstf := '0';
end if;
if ar.dma.done(1) = '1' then -- Mark last fifo in transfer
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).lastf := '1';
av.dma.done(0) := '1';
else
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).lastf := '0';
end if;
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).stop := ar.dma.faddr(AHB_FIFO_BITS);
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).status := (others => '0'); -- Not used
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).last_cbe := (others => '0'); -- Not used
end if;
av.dma.dtp.ctrl.en := '1';
av.dma.dtp.ctrl.addr := conv_std_logic_vector(ar.dma.dtp.index, log2(FIFO_COUNT)) & ar.dma.faddr(AHB_FIFO_BITS);
elsif dmao1.error = '1' then
av.dma.active := '0';
av.dma.dmai1.req := '0';
av.dma.done(0) := '1';
av.dma.err(0) := '1';
av.dma.dtp.index := md_index; -- Go to next fifo
if ar.dma.first(0) = '1' then -- Mark first fifo in transfer
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).firstf := '1';
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).start := ar.dma.desc.aaddr(AHB_FIFO_BITS);
av.dma.first(0) := '0';
else
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).firstf := '0';
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).start := (others => '0');
end if;
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).lastf := '1';
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).stop := ar.dma.faddr(AHB_FIFO_BITS);
av.atp_trans.msd_fifo(1)(ar.dma.dtp.index).pending(0) := not ar.atp_trans.msd_fifo(1)(ar.dma.dtp.index).pending(0);
av.dma.dtp.ctrl.en := '1';
av.dma.dtp.ctrl.addr := conv_std_logic_vector(ar.dma.dtp.index, log2(FIFO_COUNT)) & ar.dma.faddr(AHB_FIFO_BITS);
end if;
if av.dma.dmai1.addr(AHB_FIFO_BITS) = ones32(AHB_FIFO_BITS) or av.dma.len = ar.dma.desc.len then av.dma.dmai1.noreq := '1'; end if; -- to deassert req on last address phase
if ar.dma.done(0) = '1' then
av.dma.dmai1.req := '0';
if md_acc_done = '1' then
av.atp_trans.msd_acc_done_ack(1) := not ar.atp_trans.msd_acc_done_ack(1);
av.dma.state := dma_write_status;
av.dma.dmai1.req := '1';
av.dma.dmai1.write := '1';
av.dma.dmai1.burst := '0';
av.dma.dmai1.addr := ar.dma.desc.addr;
av.dma.dmai1.data := (others => '0');
av.dma.dmai1.data(30) := ar.dma.desc.irqen;
av.dma.dmai1.data(29) := ar.dma.desc.write;
av.dma.dmai1.data(28) := ar.dma.desc.tw;
av.dma.dmai1.data(21 downto 20) := ar.dma.desc.desctype;
if ar.dma.err(0) = '1' then
av.dma.dmai1.data(19) := '1';
av.dma.dmai1.data(15 downto 0) := ar.dma.errlen;
av.dma.errstatus(1) := '1';
elsif md_acc_done_status.status /= "0000" then
av.dma.err(2) := '1';
av.dma.dmai1.data(19) := '1';
av.dma.dmai1.data(15 downto 0) := md_acc_done_status.count;
av.dma.errstatus(4 downto 2) := md_acc_done_status.status(2 downto 0);
else
av.dma.dmai1.data(19) := '0';
av.dma.dmai1.data(15 downto 0) := ar.dma.errlen;
end if;
end if;
end if;
when dma_write => -- PCI read => AHB write
av.dma.ptd.ctrl.en := md_fifo_pending(ar.dma.ptd.index);
av.dma.dmai1.write := '1';
av.dma.first(0) := '0';
if md_fifo_pending(ar.dma.ptd.index) = '1' and ar.dma.dma_hold(0) = '1' and ar.dma.active = '0' and ar.dma.done(0) = '0' and ar.dma.first(2) = '0' then
av.dma.first(0) := '1';
av.dma.first(2) := '1';
av.dma.dma_hold := "000";
av.dma.dma_last := "000";
av.dma.newfifo := '0';
av.dma.ptd.ctrl.addr := conv_std_logic_vector(ar.dma.ptd.index, log2(FIFO_COUNT)) & md_fifo(ar.dma.ptd.index).start; -- Set fifo start address
av.dma.faddr := md_fifo(ar.dma.ptd.index).start; -- Set fifo start address
if ar.dma.first(1) = '1' then
av.dma.first(1) := '0';
av.dma.dmai1.addr := ar.dma.addr;
av.dma.dmai1.size := "10";
av.dma.dmai1.addr(1 downto 0) := "00";
end if;
end if;
if ar.dma.first(0) = '1' then -- Latch first word in fifo
av.dma.dmai1.req := '1';
if ar.dma.ptd.ctrl.addr(FIFO_DEPTH-1 downto 0) /= md_fifo(ar.dma.ptd.index).stop then
av.dma.ptd.ctrl.addr(FIFO_DEPTH-1 downto 0) := ar.dma.ptd.ctrl.addr(FIFO_DEPTH-1 downto 0) + 1;
else
av.dma.dma_hold(0) := '1';
if md_fifo(ar.dma.ptd.index).lastf = '1' then
av.dma.dma_last(0) := '1';
if md_fifo(ar.dma.ptd.index).status /= "0000" then
av.dma.done(0) := '1';
av.dma.dmai1.req := '0';
av.dma.err(2) := '1'; -- PCI error
av.dma.errlen := ar.dma.errlen;
av.dma.ptd.index := md_index; -- Go to next fifo
av.atp_trans.msd_fifo_ack(1)(ar.dma.ptd.index) := pta_trans.msd_fifo(1)(ar.dma.ptd.index).pending(RAM_LATENCY);
av.dma.errstatus(4 downto 2) := md_fifo(ar.dma.ptd.index).status(2 downto 0);
end if;
end if;
end if;
av.dma.dmai1.data := md_fifoo_ptd.data;
end if;
if dmao1.grant = '1' then
av.dma.active := '1';
av.dma.newfifo := '0';
av.dma.dmai1.addr := ar.dma.dmai1.addr + 4;
av.dma.faddr := ar.dma.faddr + 1;
if (ar.dma.active = '1' and ar.dma.faddr = md_fifo(ar.dma.ptd.index).stop) or ar.dma.dma_hold(1 downto 0) /= "00" or ar.dma.done(0) = '1' then
if (ar.dma.active = '1' and md_fifo_pending(md_index) = '0') or ar.dma.dma_hold(1 downto 0) /= "00" or ar.dma.done(0) = '1' then
av.dma.dmai1.req := '0';
av.dma.dma_hold(0) := '1';
end if;
end if;
elsif dmao1.retry = '1' then
av.dma.dmai1.req := '1';
av.dma.dmai1.addr := ar.dma.dmai1.addr - 4;
av.dma.faddr := ar.dma.faddr - 1;
end if;
if dmao1.ready = '1' then
av.dma.first(2) := '0';
if ar.dma.errlen /= ar.dma.desc.len then
av.dma.errlen := ar.dma.errlen + 1;
end if;
if dmao1.grant = '0' and ar.dma.dmai1.req = '0' then av.dma.active := '0'; end if;
if ar.dma.dma_hold(1 downto 0) = "00" then
av.dma.dmai1.data := md_fifoo_ptd.data;
av.dma.ptd.ctrl.addr(FIFO_DEPTH-1 downto 0) := ar.dma.ptd.ctrl.addr(FIFO_DEPTH-1 downto 0) + 1;
end if;
if md_fifo_pending(ar.dma.ptd.index) = '1' and ar.dma.ptd.ctrl.addr(FIFO_DEPTH-1 downto 0) = md_fifo(ar.dma.ptd.index).stop and
ar.dma.dma_hold(1 downto 0) /= "11" and ar.dma.done(0) = '0' then
av.dma.ptd.index := md_index; -- Go to next fifo
av.atp_trans.msd_fifo_ack(1)(ar.dma.ptd.index) := pta_trans.msd_fifo(1)(ar.dma.ptd.index).pending(RAM_LATENCY);
av.dma.ptd.ctrl.addr := conv_std_logic_vector(av.dma.ptd.index, log2(FIFO_COUNT)) & md_fifo(md_index).start; -- Set fifo start address
if md_fifo_pending(md_index) = '0' or ar.dma.dma_hold(0) = '1' then
av.dma.dma_hold(1) := '1';
end if;
if md_fifo(ar.dma.ptd.index).lastf = '1' or ar.dma.dma_last(1 downto 0) /= "00" then -- Transfer done
av.dma.done(0) := '1';
if md_fifo(ar.dma.ptd.index).status /= "0000" then
av.dma.err(2) := '1'; -- PCI error
av.dma.errlen := ar.dma.errlen;
av.dma.errstatus(4 downto 2) := md_fifo(ar.dma.ptd.index).status(2 downto 0);
end if;
end if;
end if;
elsif dmao1.error = '1' then
av.dma.err(0) := '1';
av.dma.errstatus(1) := '1';
av.dma.active := '0';
av.dma.dmai1.req := '0';
if ar.dma.done(0) = '0' then
if md_fifo_pending(ar.dma.ptd.index) = '1' and md_fifo(ar.dma.ptd.index).lastf = '1' then
av.dma.ptd.index := md_index; -- Go to next fifo
av.atp_trans.msd_fifo_ack(1)(ar.dma.ptd.index) := pta_trans.msd_fifo(1)(ar.dma.ptd.index).pending(RAM_LATENCY);
av.dma.done(0) := '1';
else
av.dma.state := dma_error;
end if;
end if;
end if;
if ar.dma.done(0) = '1' and ar.dma.active = '0' then
av.dma.state := dma_write_status;
av.dma.dmai1.req := '1';
av.dma.dmai1.write := '1';
av.dma.dmai1.burst := '0';
av.dma.dmai1.addr := ar.dma.desc.addr;
av.dma.dmai1.data := (others => '0');
av.dma.dmai1.data(30) := ar.dma.desc.irqen;
av.dma.dmai1.data(29) := ar.dma.desc.write;
av.dma.dmai1.data(28) := ar.dma.desc.tw;
av.dma.dmai1.data(21 downto 20) := ar.dma.desc.desctype;
if ar.dma.err(0) = '1' or ar.dma.err(2) = '1' then
av.dma.dmai1.data(19) := '1';
av.dma.dmai1.data(15 downto 0) := ar.dma.errlen;
else
av.dma.dmai1.data(19) := '0';
av.dma.dmai1.data(15 downto 0) := ar.dma.errlen;
end if;
end if;
if av.dma.dmai1.addr(AHB_FIFO_BITS) = md_fifo(ar.dma.ptd.index).stop or ar.dma.done(0) = '1' then av.dma.dmai1.noreq := '1'; end if; -- to deassert req on last address phase
when dma_error => -- Wait for last fifo
if md_fifo_pending(ar.dma.ptd.index) = '1' and ar.dma.done(0) = '0' then
if md_fifo(ar.dma.ptd.index).lastf = '1' then
av.dma.done(0) := '1';
end if;
av.dma.ptd.index := md_index; -- Go to next fifo
av.atp_trans.msd_fifo_ack(1)(ar.dma.ptd.index) := pta_trans.msd_fifo(1)(ar.dma.ptd.index).pending(RAM_LATENCY);
end if;
if ar.dma.done(0) = '1' then
av.dma.state := dma_write_status;
av.dma.dmai1.req := '1';
av.dma.dmai1.write := '1';
av.dma.dmai1.burst := '0';
av.dma.dmai1.addr := ar.dma.desc.addr;
av.dma.dmai1.data := (others => '0');
av.dma.dmai1.data(30) := ar.dma.desc.irqen;
av.dma.dmai1.data(29) := ar.dma.desc.write;
av.dma.dmai1.data(28) := ar.dma.desc.tw;
av.dma.dmai1.data(21 downto 20) := ar.dma.desc.desctype;
if ar.dma.err(0) = '1' or ar.dma.err(2) = '1' then
av.dma.dmai1.data(19) := '1';
av.dma.dmai1.data(15 downto 0) := ar.dma.errlen;
else
av.dma.dmai1.data(19) := '0';
av.dma.dmai1.data(15 downto 0) := ar.dma.errlen;
end if;
end if;
when others =>
end case;
end if; -- DMA enabled
-- --------------------------------------------------------------------------------
-- IRQ
-- --------------------------------------------------------------------------------
pirq := (others => '0');
-- PCI device driving PCI INTA
if deviceirq = 1 then
pciinten(0) <= oeoff xor (ar.irq.device_mask(0) and (ar.irq.device_force or dirq(0)));
pciinten(1) <= oeoff xor (ar.irq.device_mask(1) and (ar.irq.device_force or dirq(1)));
pciinten(2) <= oeoff xor (ar.irq.device_mask(2) and (ar.irq.device_force or dirq(2)));
pciinten(3) <= oeoff xor (ar.irq.device_mask(3) and (ar.irq.device_force or dirq(3)));
else
av.irq.device_mask := (others => '0');
av.irq.device_force := '0';
pciinten <= (others => oeoff);
end if;
-- PCI host sampling PCI INTA..D
if hostirq = 1 then
av.irq.host_pirq_vl := (pcii.int(3) or not ar.irq.host_mask(3))
& (pcii.int(2) or not ar.irq.host_mask(2))
& (pcii.int(1) or not ar.irq.host_mask(1))
& (pcii.int(0) or not ar.irq.host_mask(0));
av.irq.host_pirq_l := not ( av.irq.host_pirq_vl(0) and av.irq.host_pirq_vl(1)
and av.irq.host_pirq_vl(2) and av.irq.host_pirq_vl(3));
av.irq.host_status := pcii.int(3)
& pcii.int(2)
& pcii.int(1)
& pcii.int(0);
else
av.irq.host_mask := (others => '0');
av.irq.host_status := (others => '0');
av.irq.host_pirq_vl:= (others => '0');
av.irq.host_pirq_l := '0';
end if;
-- System error irq (SERR)
if pta_trans.pa_serr = '1' and ar.atp_trans.pa_serr_rst = '1' then
av.irq.system_status(0) := '0';
av.atp_trans.pa_serr_rst := '0';
elsif pta_trans.pa_serr = '0' then
av.irq.system_status(0) := '1';
if ar.irq.system_en = '1' and ar.irq.system_status(0) = '0' then
av.irq.system_pirq := '1';
end if;
end if;
-- System error irq (Discard time out)
if pta_trans.pa_discardtout = '0' and ar.atp_trans.pa_discardtout_rst = '1' then
av.irq.system_status(1) := '0';
av.atp_trans.pa_discardtout_rst := '0';
elsif pta_trans.pa_discardtout = '1' then
av.irq.system_status(1) := '1';
if ar.irq.system_en = '1' and ar.irq.system_status(1) = '0' then
av.irq.system_pirq := '1';
end if;
end if;
-- Level IRQ
av.irq.system_pirq_l := ar.irq.system_en and orv(ar.irq.system_status);
av.irq.access_pirq_l := ar.irq.access_en and orv(ar.irq.access_status);
av.irq.dma_pirq_l := ar.dma.irqen and orv(ar.dma.irqstatus);
if irqmode = 0 then -- PCI INTA..D, Error irq and DMA irq on the same interrupt
pirq(irq) := ar.irq.host_pirq_l or ar.irq.access_pirq_l or ar.irq.dma_pirq_l or ar.irq.system_pirq_l; -- All level irq
elsif irqmode = 1 then -- PCI INTA..D and Error irq on the same interrupt. DMA irq no next interrupt
pirq(irq) := ar.irq.host_pirq_l or ar.irq.access_pirq_l or ar.irq.system_pirq_l;
pirq(irq+1) := (ar.dma.irqen and ar.dma.irq);
elsif irqmode = 2 then -- PCI INTA..D on separate interrupt, Error irq and DMA irq on first interrupt
pirq(irq) := not ar.irq.host_pirq_vl(0) or ar.irq.access_pirq_l or ar.irq.dma_pirq_l or ar.irq.system_pirq_l;
pirq(irq+1) := not ar.irq.host_pirq_vl(1);
pirq(irq+2) := not ar.irq.host_pirq_vl(2);
pirq(irq+3) := not ar.irq.host_pirq_vl(3);
else --if irqmode = 3 then -- PCI INTA..D on separate interrupt, Error irq on first interrupt, DMA irq on interrupt after PCI INTD
pirq(irq) := not ar.irq.host_pirq_vl(0) or ar.irq.access_pirq_l or ar.irq.system_pirq_l;
pirq(irq+1) := not ar.irq.host_pirq_vl(1);
pirq(irq+2) := not ar.irq.host_pirq_vl(2);
pirq(irq+3) := not ar.irq.host_pirq_vl(3);
pirq(irq+4) := (ar.dma.irqen and ar.dma.irq);
end if;
-- --------------------------------------------------------------------------------
-- APB Slave
-- --------------------------------------------------------------------------------
av.apb_pt_stat := zero32(15 downto PT_DEPTH) & pt_status.taddr
& pt_status.armed & ptta_trans.enable & pt_status.wrap & "0"
& conv_std_logic_vector(PT_DEPTH, 8)
& "00" & ar.atpt_trans.stop & ar.atpt_trans.start;
av.debug_pr := pr.debug;
av.apb_pr_conf_0_pta_map := pr.conf(0).pta_map;
prdata := (others => '0');
apbaddr := apbi.paddr(6 downto 2);
if iotest/=0 and iotmact='0' then av.debuga(5 downto 0) := "000000"; end if;
if (apbi.psel(pindex) and apbi.penable) = '1' then
if apbi.paddr(7) = '0' then -- PCI core and DMA
case apbaddr is
when "00000" => -- 0x00 Control
prdata(31 downto 29) := ar.atp_trans.rst(2 downto 0);
prdata( 28) := '0';
prdata( 27) := ar.irq.system_en;
prdata( 26) := ar.s.parerren;
prdata( 25) := ar.s.erren;
prdata( 24) := ar.irq.access_en;
prdata(23 downto 16) := ar.s.cfg_bus;
prdata(15 downto 12) := (others => '0'); -- RESERVED
prdata( 11) := ar.atp_trans.mstswdis;
prdata(10 downto 9) := ar.s.io_cfg_burst;
prdata( 8) := ar.irq.device_force;
prdata( 7 downto 4) := ar.irq.device_mask;
prdata( 3 downto 0) := ar.irq.host_mask;
if apbi.pwrite = '1' then
av.atp_trans.rst(2) := apbi.pwdata(31);
av.atp_trans.rst(1 downto 0) := ar.atp_trans.rst(1 downto 0) or apbi.pwdata(30 downto 29);
av.irq.system_en := apbi.pwdata( 27);
av.s.parerren := apbi.pwdata( 26);
av.s.erren := apbi.pwdata( 25);
av.irq.access_en := apbi.pwdata( 24);
av.s.cfg_bus := apbi.pwdata(23 downto 16);
-- := apbi.pwdata(15 downto 12);
av.atp_trans.mstswdis:= apbi.pwdata( 11);
av.s.io_cfg_burst := apbi.pwdata(10 downto 9);
av.irq.device_force := apbi.pwdata( 8);
av.irq.device_mask := apbi.pwdata( 7 downto 4);
av.irq.host_mask := apbi.pwdata( 3 downto 0);
end if;
when "00001" => -- 0x04 Status
prdata(31) := (pta_trans.ca_host and not ar.s.fakehost);
prdata(30) := conv_std_logic(master/=0);
prdata(29) := conv_std_logic(target/=0);
prdata(28) := conv_std_logic(dma/=0);
prdata(27) := conv_std_logic(deviceirq/=0);
prdata(26) := conv_std_logic(hostirq/=0);
prdata(25 downto 24) := conv_std_logic_vector(irqmode, 2);
prdata(23) := conv_std_logic(tracebuffer/=0);
prdata(22 downto 22) := (others => '0'); -- RESERVED
prdata( 21) := ar.s.fakehost;
prdata(20 downto 19) := ar.s.cfg_status;
prdata(18 downto 17) := ar.irq.system_status;
prdata(16 downto 12) := ar.dma.irqstatus & ar.irq.access_status;
prdata(11 downto 8) := ar.irq.host_status;
prdata( 7 downto 5) := (others => '0');-- conv_std_logic_vector(dma_fifo_depth, 2);
prdata( 4 downto 2) := conv_std_logic_vector(fifo_depth, 3);
prdata( 1 downto 0) := conv_std_logic_vector(fifo_count, 2);
if apbi.pwrite = '1' then
av.s.fakehost := ar.s.fakehost xor apbi.pwdata(21);
av.s.cfg_status(0) := ar.s.cfg_status(0) and not (apbi.pwdata(20) or apbi.pwdata(19)); -- Clear cfg_status
av.s.cfg_status(1) := ar.s.cfg_status(1) and not (apbi.pwdata(20) or apbi.pwdata(19)); -- Clear cfg_status
av.atp_trans.pa_discardtout_rst := ar.atp_trans.pa_discardtout_rst or apbi.pwdata(18);
av.atp_trans.pa_serr_rst := ar.atp_trans.pa_serr_rst or apbi.pwdata(17);
av.dma.irqstatus := ar.dma.irqstatus and not apbi.pwdata(16 downto 15);
av.irq.access_status := ar.irq.access_status and not apbi.pwdata(14 downto 12);
end if;
when "00010" => -- 0x08 AHB slave burst lenght and AHB-master mask
if apbi.pwrite = '1' then
av.s.blen := apbi.pwdata(7 downto 0);
av.s.blenmask := apbi.pwdata(31 downto 16);
end if;
prdata(31 downto 0) := ar.s.blenmask & zero32(15 downto 8) & ar.s.blen;
when "00011" => -- 0x0c AHB to PCI IO map
if apbi.pwrite = '1' then
av.s.io_map := apbi.pwdata(31 downto 16);
end if;
prdata(31 downto 0) := ar.s.io_map & zero32(15 downto 0);
when "00100" => -- 0x10 DMA Control
if apbi.pwrite = '1' then
av.dma.irqch := ar.dma.irqch and not apbi.pwdata(19 downto 12);
av.dma.errstatus := ar.dma.errstatus and not apbi.pwdata(11 downto 7);
if apbi.pwdata(31) = '1' then -- Safety guard for update of control fields
av.dma.numch := apbi.pwdata(6 downto 4);
av.dma.irqen := apbi.pwdata(1);
end if;
av.dma.en := (ar.dma.en and not apbi.pwdata(2)) or apbi.pwdata(0); -- bit[2] = disable/stop bit[0] = enable/start
end if;
prdata(31) := '1';
prdata(30 downto 0) := (others => '0');
prdata(19 downto 12) := ar.dma.irqch;
prdata(11 downto 7) := ar.dma.errstatus;
prdata(6 downto 4) := ar.dma.numch;
prdata(3) := ar.dma.running;
prdata(2) := '0';
prdata(1) := ar.dma.irqen;
prdata(0) := ar.dma.en;
when "00101" => -- 0x14 DMA Data desc
if apbi.pwrite = '1' then
av.dma.desc.addr(31 downto 4) := apbi.pwdata(31 downto 4);
end if;
prdata(31 downto 0) := ar.dma.desc.addr;
when "00110" => -- 0x18 DMA Channel desc
prdata(31 downto 0) := ar.dma.desc.ch;
when "00111" => -- 0x1c Reserved
prdata(31 downto 0) := ar.debuga;
if apbi.pwrite = '1' then
av.debuga := apbi.pwdata;
end if;
when "01000" => -- 0x20 PCI BAR0 to AHB map (read only)
prdata(31 downto 0) := ar.apb_pr_conf_0_pta_map(0);
when "01001" => -- 0x24 PCI BAR1 to AHB map (read only)
prdata(31 downto 0) := ar.apb_pr_conf_0_pta_map(1);
when "01010" => -- 0x28 PCI BAR2 to AHB map (read only)
prdata(31 downto 0) := ar.apb_pr_conf_0_pta_map(2);
when "01011" => -- 0x2c PCI BAR3 to AHB map (read only)
prdata(31 downto 0) := ar.apb_pr_conf_0_pta_map(3);
when "01100" => -- 0x30 PCI BAR4 to AHB map (read only)
prdata(31 downto 0) := ar.apb_pr_conf_0_pta_map(4);
when "01101" => -- 0x34 PCI BAR5 to AHB map (read only)
prdata(31 downto 0) := ar.apb_pr_conf_0_pta_map(5);
when "01110" => -- 0x38 Reserved
--prdata(31 downto 0) := (others => '0');
prdata := ar.debug;
when "01111" => -- 0x3c Reserved
--prdata(31 downto 0) := (others => '0');
prdata := ar.debug_pr;
when "10000" => -- 0x40 AHB master00 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(0)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(0)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(0);
when "10001" => -- 0x44 AHB master01 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(1)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(1)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(1);
when "10010" => -- 0x48 AHB master02 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(2)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(2)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(2);
when "10011" => -- 0x4c AHB master03 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(3)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(3)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(3);
when "10100" => -- 0x50 AHB master04 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(4)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(4)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(4);
when "10101" => -- 0x54 AHB master05 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(5)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(5)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(5);
when "10110" => -- 0x58 AHB master06 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(6)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(6)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(6);
when "10111" => -- 0x5c AHB master07 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(7)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(7)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(7);
when "11000" => -- 0x60 AHB master08 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(8)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(8)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(8);
when "11001" => -- 0x64 AHB master09 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(9)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(9)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(9);
when "11010" => -- 0x68 AHB master10 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(10)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(10)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(10);
when "11011" => -- 0x6c AHB master11 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(11)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(11)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(11);
when "11100" => -- 0x70 AHB master12 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(12)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(12)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(12);
when "11101" => -- 0x74 AHB master13 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(13)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(13)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(13);
when "11110" => -- 0x78 AHB master14 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(14)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(14)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(14);
when "11111" => -- 0x7c AHB master15 to PCI map
if apbi.pwrite = '1' then
av.s.atp_map(15)(31 downto 3) := (others => '0');
if AADDR_WIDTH /= 4 then
av.s.atp_map(15)(31 downto AADDR_WIDTH) := apbi.pwdata(31 downto AADDR_WIDTH);
end if;
end if;
prdata(31 downto 0) := ar.s.atp_map(15);
when others =>
prdata(31 downto 0) := (others => '0');
end case;
elsif tracebuffer /= 0 then -- PCI trace buffer enabled
case apbaddr is
when "00000" => -- 0x80 PCI trace control & status
if apbi.pwrite = '1' then
av.atpt_trans.start := ar.atpt_trans.start or apbi.pwdata(0);
av.atpt_trans.stop := ar.atpt_trans.stop or apbi.pwdata(1);
end if;
prdata(31 downto 0) := ar.apb_pt_stat;
when "00001" => -- 0x84 PCI trace count & mode
if apbi.pwrite = '1' then
av.atpt_trans.mode := apbi.pwdata(27 downto 24);
av.atpt_trans.tcount := apbi.pwdata(23 downto 16);
av.atpt_trans.count := apbi.pwdata(PT_DEPTH-1 downto 0);
end if;
prdata(31 downto 0) := x"0" & ar.atpt_trans.mode & ar.atpt_trans.tcount & zero32(15 downto PT_DEPTH) & ar.atpt_trans.count;
when "00010" => -- 0x88 PCI trace AD pattern
if apbi.pwrite = '1' then
av.atpt_trans.ad := apbi.pwdata;
end if;
prdata(31 downto 0) := ar.atpt_trans.ad;
when "00011" => -- 0x8c PCI trace AD mask
if apbi.pwrite = '1' then
av.atpt_trans.admask := apbi.pwdata;
end if;
prdata(31 downto 0) := ar.atpt_trans.admask;
when "00100" => -- 0x90 PCI trace Signal pattern
if apbi.pwrite = '1' then
av.atpt_trans.sig := apbi.pwdata(19 downto 3);
end if;
prdata(31 downto 0) := x"000" & ar.atpt_trans.sig & "000";
when "00101" => -- 0x94 PCI trace Signal mask
if apbi.pwrite = '1' then
av.atpt_trans.sigmask := apbi.pwdata(19 downto 3);
end if;
prdata(31 downto 0) := x"000" & ar.atpt_trans.sigmask & "000";
when "00110" => -- 0x98 PCI AD
prdata(31 downto 0) := ptta_trans.dbg_ad;
when "00111" => -- 0x9c PCI Ctrl signal
prdata(19 downto 0) := ptta_trans.dbg_sig & "000";
prdata(31 downto 16) := (others => '0');
when "01000" => -- 0xA0 tmp target cur addr
prdata(31 downto 0) := ptta_trans.dbg_cur_ad;
when "01001" => -- 0xA4 tmp target cur state
prdata(31 downto 8) := (others => '0');
prdata(8 downto 0) := ptta_trans.dbg_cur_acc;
when others =>
prdata(31 downto 0) := (others => '0');
end case;
end if;
end if;
apbo.pirq <= pirq;
apbo.prdata <= prdata;
apbo.pconfig <= pconfig;
apbo.pindex <= pindex;
-- --------------------------------------------------------------------------------
-- APB DEBUG Slave
-- --------------------------------------------------------------------------------
tb_ren <= ar.s.tb_ren;
tb_addr <= ar.s.haddr;
tbpirq := (others => '0');
tbprdata := (others => '0');
tbapbaddr := tbapbi.paddr(6 downto 2);
if tbapben = 1 then
if (tbapbi.psel(tbpindex) and tbapbi.paddr(17)) = '1' then
tb_ren <= '1'; tb_addr <= tbapbi.paddr;
end if;
if (tbapbi.psel(tbpindex) and tbapbi.penable) = '1' then
if tbapbi.paddr(17) = '1' then
if tbapbi.paddr(16) = '0' then
tbprdata := pt_fifoo_ad.data;
else
tbprdata := zero32(31 downto 20) & pt_fifoo_sig.data(16 downto 0) & "000";
end if;
else
if tbapbi.paddr(7) = '0' then -- PCI core and DMA
case tbapbaddr is
when "01110" => -- 0x38 Reserved
--prdata(31 downto 0) := (others => '0');
tbprdata := ar.debug;
when "01111" => -- 0x3c Reserved
--prdata(31 downto 0) := (others => '0');
tbprdata := ar.debug_pr;
when others =>
tbprdata(31 downto 0) := (others => '0');
end case;
elsif tracebuffer /= 0 then -- PCI trace buffer enabled
case tbapbaddr is
when "00000" => -- 0x80 PCI trace control & status
if tbapbi.pwrite = '1' then
av.atpt_trans.start := ar.atpt_trans.start or tbapbi.pwdata(0);
av.atpt_trans.stop := ar.atpt_trans.stop or tbapbi.pwdata(1);
end if;
tbprdata(31 downto 0) := ar.apb_pt_stat;
when "00001" => -- 0x84 PCI trace count & mode
if tbapbi.pwrite = '1' then
av.atpt_trans.mode := tbapbi.pwdata(27 downto 24);
av.atpt_trans.tcount := tbapbi.pwdata(23 downto 16);
av.atpt_trans.count := tbapbi.pwdata(PT_DEPTH-1 downto 0);
end if;
tbprdata(31 downto 0) := x"0" & ar.atpt_trans.mode & ar.atpt_trans.tcount & zero32(15 downto PT_DEPTH) & ar.atpt_trans.count;
when "00010" => -- 0x88 PCI trace AD pattern
if tbapbi.pwrite = '1' then
av.atpt_trans.ad := tbapbi.pwdata;
end if;
tbprdata(31 downto 0) := ar.atpt_trans.ad;
when "00011" => -- 0x8c PCI trace AD mask
if tbapbi.pwrite = '1' then
av.atpt_trans.admask := tbapbi.pwdata;
end if;
tbprdata(31 downto 0) := ar.atpt_trans.admask;
when "00100" => -- 0x90 PCI trace Signal pattern
if tbapbi.pwrite = '1' then
av.atpt_trans.sig := tbapbi.pwdata(19 downto 3);
end if;
tbprdata(31 downto 0) := x"000" & ar.atpt_trans.sig & "000";
when "00101" => -- 0x94 PCI trace Signal mask
if tbapbi.pwrite = '1' then
av.atpt_trans.sigmask := tbapbi.pwdata(19 downto 3);
end if;
tbprdata(31 downto 0) := x"000" & ar.atpt_trans.sigmask & "000";
when "00110" => -- 0x98 PCI AD
tbprdata(31 downto 0) := ptta_trans.dbg_ad;
when "00111" => -- 0x9c PCI Ctrl signal
tbprdata(19 downto 0) := ptta_trans.dbg_sig & "000";
tbprdata(31 downto 16) := (others => '0');
when "01000" => -- 0xA0 tmp target cur addr
tbprdata(31 downto 0) := ptta_trans.dbg_cur_ad;
when "01001" => -- 0xA4 tmp target cur state
tbprdata(31 downto 8) := (others => '0');
tbprdata(8 downto 0) := ptta_trans.dbg_cur_acc;
when others =>
tbprdata(31 downto 0) := (others => '0');
end case;
end if;
end if;
end if;
tbapbo.pirq <= tbpirq;
tbapbo.prdata <= tbprdata;
tbapbo.pconfig <= tbpconfig;
tbapbo.pindex <= tbpindex;
else
tbapbo <= apb_none;
end if;
-- --------------------------------------------------------------------------------
-- AHB global signal assignments
-- --------------------------------------------------------------------------------
ahbso.hready <= ar.s.hready;
ahbso.hresp <= ar.s.hresp;
ahbso.hrdata <= ahbdrivedata(ar.s.hrdata);
ahbso.hindex <= hsindex;
ahbso.hconfig <= hconfig;
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
if master = 0 then
ahbso <= ahbs_none;
end if;
-- --------------------------------------------------------------------------------
-- AHB debug
-- --------------------------------------------------------------------------------
--[31:30] s_pending
--[29:28] s_empty
--[27:26] tm_pending
--[25:24] tm_empty
--[ :23] ms_acc_pending
--[ :22] ms_acc_cancel
--[ :21] ms_acc_done
--[ :20] tm_acc_pending
--[ :19] tm_acc_cancel
--[ :18] tm_acc_done
--[ :17] md_acc_pending
--[ :16] md_acc_cancel
--[ :15] md_acc_done
--[ :14] ..
--[13:12] dma_done
--[11:10] s_pending
--[ 9: 7] m_done
--[ 6: 4] dma.state
--[ 3: 2] m.state
--[ 1: 0] s.state
av.debug(31 downto 30) := ms_fifo_pending(1 downto 0);
av.debug(29 downto 28) := ms_fifo_empty(1 downto 0);
av.debug(27 downto 26) := tm_fifo_pending(1 downto 0);
av.debug(25 downto 24) := tm_fifo_empty(1 downto 0);
av.debug( 23) := ms_acc_pending;
av.debug( 22) := ms_acc_cancel;
av.debug( 21) := ms_acc_done;
av.debug( 20) := tm_acc_pending;
av.debug( 19) := tm_acc_cancel;
av.debug( 18) := tm_acc_done;
av.debug( 17) := md_acc_pending;
av.debug( 16) := md_acc_cancel;
av.debug( 15) := md_acc_done;
av.debug( 14) := '0';
av.debug(13 downto 12) := ar.dma.done;
av.debug(11 downto 10) := ar.s.pending;
av.debug( 9 downto 7) := ar.m.done;
case ar.dma.state is
when dma_idle => av.debug(6 downto 4) := "000";
when dma_read_desc => av.debug(6 downto 4) := "001";
when dma_next_channel => av.debug(6 downto 4) := "010";
when dma_write_status => av.debug(6 downto 4) := "011";
when dma_read => av.debug(6 downto 4) := "100";
when dma_write => av.debug(6 downto 4) := "101";
when dma_error => av.debug(6 downto 4) := "110";
end case;
case ar.m.state is
when am_idle => av.debug(3 downto 2) := "00";
when am_read => av.debug(3 downto 2) := "01";
when am_write => av.debug(3 downto 2) := "10";
when am_error => av.debug(3 downto 2) := "11";
when others => av.debug(3 downto 2) := "00";
end case;
case ar.s.state is
when as_idle => av.debug(1 downto 0) := "00";
when as_checkpcimst => av.debug(1 downto 0) := "01";
when as_read => av.debug(1 downto 0) := "10";
when as_write => av.debug(1 downto 0) := "11";
when others => av.debug(1 downto 0) := "00";
end case;
-- --------------------------------------------------------------------------------
-- AHB reset
-- --------------------------------------------------------------------------------
-- AHB master
lahbm_rst <= rst and not pci_target_rst and not pci_hard_rst;
if lahbm_rst = '0' then
av.m.state := am_idle;
av.m.acc.fifo_index := 0;
av.m.acc.pending := '0';
av.m.retry := '0';
av.m.dmai0.addr := (others => '0');
av.atp_trans.mstswdis := '0';
av.atp_trans.tm_acc_ack := '0';
av.atp_trans.tm_acc_cancel_ack := (others => '0');
av.atp_trans.tm_acc_done.done := '0';
for i in 0 to FIFO_COUNT-1 loop
av.atp_trans.tm_fifo(i).pending := (others => '0');
end loop;
av.atp_trans.tm_fifo_ack := (others => '0');
end if;
-- AHB slave
lahbs_rst <= rst and not pci_master_rst and not pci_hard_rst;
if lahbs_rst = '0' then
av.s.state := as_idle;
av.s.atp.index := 0;
av.s.pta.index := 0;
av.s.pending := (others => '0');
av.s.discard := '0';
av.s.start := '0';
av.s.cfg_bus := (others => '0');
av.s.cfg_status := (others => '0');
av.s.parerren := '0';
av.s.erren := '0';
av.s.blen := (others => '1');
av.s.blenmask := (others => '0');
av.s.io_cfg_burst := (others => '0');
av.s.fakehost := '0';
for i in 0 to 3 loop
av.s.accbuf(i).pending := '0';
end loop;
for j in 0 to FIFO_COUNT-1 loop
av.atp_trans.msd_fifo(0)(j).pending := (others => '0');
end loop;
av.atp_trans.msd_fifo_ack(0) := (others => '0');
av.atp_trans.msd_acc(0).pending := '0';
av.atp_trans.msd_acc_cancel(0) := '0';
av.atp_trans.msd_acc_done_ack(0) := '0';
for i in 0 to 15 loop
if multifunc = 0 then
av.s.atp_map(i)(2 downto 0) := "000";
else
for j in 0 to multifunc loop
if masters_vector(j)(i) = '1' then
av.s.atp_map(i)(2 downto 0) := conv_std_logic_vector(j, 3);
end if;
end loop;
end if;
end loop;
end if;
-- DMA
if lahbs_rst = '0' then
av.dma.state := dma_idle;
av.dma.en := '0';
av.dma.irq := '0';
av.dma.irqen := '0';
av.dma.irqstatus := (others => '0');
av.dma.errstatus := (others => '0');
av.dma.irqch := (others => '0');
av.dma.desc.chid := (others => '0');
av.dma.dtp.index := 0;
av.dma.ptd.index := 0;
for j in 0 to FIFO_COUNT-1 loop
av.atp_trans.msd_fifo(1)(j).pending := (others => '0');
end loop;
av.atp_trans.msd_fifo_ack(1) := (others => '0');
av.atp_trans.msd_acc(1).pending := '0';
av.atp_trans.msd_acc_cancel(1) := '0';
av.atp_trans.msd_acc_done_ack(1) := '0';
end if;
-- AHB reset
lahb_rst <= rst and not pci_hard_rst;
if lahb_rst = '0' then
if deviceirq = 1 then
av.irq.device_mask := conv_std_logic_vector(deviceirqmask, 4);
av.irq.device_force := '0';
end if;
if hostirq = 1 then
av.irq.host_mask := conv_std_logic_vector(hostirqmask, 4);
av.irq.host_status := (others => '0');
av.irq.host_pirq_vl := (others => '0');
end if;
av.irq.irqen := '0';
av.irq.access_en := '0';
av.irq.access_status := (others => '0');
av.irq.system_en := '0';
av.irq.system_status := (others => '0');
av.atp_trans.pa_serr_rst := '0';
av.atp_trans.pa_discardtout_rst := '0';
-- APB (PCI trace)
av.atpt_trans.start := '0';
av.atpt_trans.stop := '1';
-- Soft reset
av.atp_trans.rst(1 downto 0) := (others => '0');
end if;
if rst = '0' then
-- Hard reset
av.atp_trans.rst(2) := '0';
if iotest /= 0 then
av.debuga(5 downto 0) := "000000";
end if;
end if;
-- Disabled parts
if target = 0 then -- PCI targer disabled
av.m := amba_master_none;
av.atp_trans.tm_acc_ack := '0';
av.atp_trans.tm_acc_cancel_ack := (others => '0');
av.atp_trans.tm_acc_done := pci_g_acc_status_trans_none;
av.atp_trans.tm_fifo := pci_g_fifo_trans_vector_none;
av.atp_trans.tm_fifo_ack := pci_g_fifo_ack_trans_vector_none;
end if;
if master = 0 then -- PCI master disabled
av.s := amba_slave_none;
av.atp_trans.msd_acc(0) := pci_g_acc_trans_none;
av.atp_trans.msd_acc_cancel(0) := '0';
av.atp_trans.msd_acc_done_ack(0) := '0';
av.atp_trans.msd_fifo(0) := pci_g_fifo_trans_vector_none;
av.atp_trans.msd_fifo_ack(0) := pci_g_fifo_ack_trans_vector_none;
end if;
if dma = 0 then -- DMA disabled
av.dma := dma_reg_none;
av.atp_trans.msd_acc(1) := pci_g_acc_trans_none;
av.atp_trans.msd_acc_cancel(1) := '0';
av.atp_trans.msd_acc_done_ack(1) := '0';
av.atp_trans.msd_fifo(1) := pci_g_fifo_trans_vector_none;
av.atp_trans.msd_fifo_ack(1) := pci_g_fifo_ack_trans_vector_none;
end if;
if tracebuffer = 0 then -- PCI trace buffer disabled
av.atpt_trans := apb_to_pci_trace_trans_none;
end if;
-- --------------
arin <= av;
end process;
preg : process(pciclk, phyo)
begin
if rising_edge(pciclk) then
pr <= prin;
end if;
-- PHY =>
pr.po <= phyo.pr_po;
pr.m.state <= phyo.pr_m_state;
pr.m.last <= phyo.pr_m_last;
pr.m.hold <= phyo.pr_m_hold;
pr.m.term <= phyo.pr_m_term;
pr.t.hold <= phyo.pr_t_hold;
pr.t.stop <= phyo.pr_t_stop;
pr.t.abort <= phyo.pr_t_abort;
pr.t.diswithout <= phyo.pr_t_diswithout;
pr.t.addr_perr <= phyo.pr_t_addr_perr;
-- PHY <=
end process;
areg : process(clk)
begin
if rising_edge(clk) then ar <= arin; end if;
end process;
-- AHB master
target_ahbm0 : if target /= 0 generate
ahbm0 : grpci2_ahb_mst generic map (hindex => hmindex, devid => GAISLER_GRPCI2, version => REVISION)
port map (rst, clk, ahbmi, ahbmo_con, ar.m.dmai0, dmao0, disabled_dmai, open);
ahbmo <= ahbmo_con;
end generate;
no_target_ahbm0 : if target = 0 generate
ahbmo <= ahbm_none;
end generate;
dma_ahbm0 : if dma /= 0 generate
ahbm1 : grpci2_ahb_mst generic map (hindex => hdmindex, devid => GAISLER_GRPCI2_DMA, version => REVISION)
port map (rst, clk, ahbdmi, ahbdmo, ar.dma.dmai1, dmao1, disabled_dmai, open);
end generate;
no_dma_ahbm0 : if dma = 0 generate
ahbdmo <= ahbm_none;
end generate;
target_fifo0 : if target /= 0 generate
scan_prin_t_atp_ctrl_en <= (prin.t.atp.ctrl.en and not scanen);
scan_ar_m_acc_fifo_wen <= (ar.m.acc.fifo_wen and not scanen);
scan_arin_m_acc_fifo_ren <= (arin.m.acc.fifo_ren and not scanen);
scan_pr_t_pta_ctrl_en <= (pr.t.pta.ctrl.en and not scanen);
ft0 : if ft /= 0 generate
-- AHB master to PCI target FIFO
atp_fifo0 : syncram_2pft generic map (tech => memtech, abits => FIFO_DEPTH+log2(FIFO_COUNT),
dbits => 32, sepclk => 1, wrfst => 0, ft => ft,
testen => scantest, custombits => memtest_vlen)
port map (pciclk, scan_prin_t_atp_ctrl_en, prin.t.atp.ctrl.addr, tm_fifoo_atp.data,
clk, scan_ar_m_acc_fifo_wen, ar.m.acc.fifo_addr, ar.m.acc.fifo_wdata,
tm_fifoo_atp.err, testin
);
-- PCI target to AHB master FIFO
pta_fifo0 : syncram_2pft generic map (tech => memtech, abits => FIFO_DEPTH+log2(FIFO_COUNT),
dbits => 32, sepclk => 1, wrfst => 0, ft => ft,
testen => scantest, custombits => memtest_vlen)
port map (clk, scan_arin_m_acc_fifo_ren, arin.m.acc.fifo_addr, tm_fifoo_pta.data,
pciclk, scan_pr_t_pta_ctrl_en, pr.t.pta.ctrl.addr, pr.t.pta.ctrl.data,
tm_fifoo_pta.err, testin
);
-- AHB master to PCI target FIFO
end generate;
noft0 : if ft = 0 generate
atp_fifo0 : syncram_2p generic map (tech => memtech, abits => FIFO_DEPTH+log2(FIFO_COUNT),
dbits => 32, sepclk => 1, wrfst => 0, testen => scantest,
custombits => memtest_vlen)
port map (pciclk, scan_prin_t_atp_ctrl_en, prin.t.atp.ctrl.addr, tm_fifoo_atp.data,
clk, scan_ar_m_acc_fifo_wen, ar.m.acc.fifo_addr, ar.m.acc.fifo_wdata,
testin
);
-- PCI target to AHB master FIFO
pta_fifo0 : syncram_2p generic map (tech => memtech, abits => FIFO_DEPTH+log2(FIFO_COUNT),
dbits => 32, sepclk => 1, wrfst => 0, testen => scantest,
custombits => memtest_vlen)
port map (clk, scan_arin_m_acc_fifo_ren, arin.m.acc.fifo_addr, tm_fifoo_pta.data,
pciclk, scan_pr_t_pta_ctrl_en, pr.t.pta.ctrl.addr, pr.t.pta.ctrl.data,
testin
);
end generate;
end generate;
master_fifo0 : if master /= 0 generate
scan_prin_m_acc_acc_sel_ahb_fifo_ren <= (prin.m.acc(acc_sel_ahb).fifo_ren and not scanen);
scan_ar_s_atp_ctrl_en <= (ar.s.atp.ctrl.en and not scanen);
scan_arin_s_pta_ctrl_en <= (arin.s.pta.ctrl.en and not scanen);
scan_pr_m_acc_acc_sel_ahb_fifo_wen <= (pr.m.acc(acc_sel_ahb).fifo_wen and not scanen);
ft0 : if ft /= 0 generate
-- AHB slave to PCI master FIFO
atp_fifo1 : syncram_2pft generic map (tech => memtech, abits => FIFO_DEPTH+log2(FIFO_COUNT),
dbits => 32, sepclk => 1, wrfst => 0, ft => ft,
testen => scantest, custombits => memtest_vlen)
port map (pciclk, scan_prin_m_acc_acc_sel_ahb_fifo_ren, prin.m.fifo_addr, ms_fifoo_atp.data,
clk, scan_ar_s_atp_ctrl_en, ar.s.atp.ctrl.addr, ar.s.atp.ctrl.data,
ms_fifoo_atp.err
);
-- PCI master to AHB slave FIFO
pta_fifo1 : syncram_2pft generic map (tech => memtech, abits => FIFO_DEPTH+log2(FIFO_COUNT),
dbits => 32, sepclk => 1, wrfst => 0, ft => ft,
testen => scantest, custombits => memtest_vlen)
port map (clk, scan_arin_s_pta_ctrl_en, arin.s.pta.ctrl.addr, ms_fifoo_pta.data,
pciclk, scan_pr_m_acc_acc_sel_ahb_fifo_wen, pr.m.fifo_addr, pr.m.fifo_wdata,
ms_fifoo_pta.err
);
end generate;
noft0 : if ft = 0 generate
-- AHB slave to PCI master FIFO
atp_fifo1 : syncram_2p generic map (tech => memtech, abits => FIFO_DEPTH+log2(FIFO_COUNT),
dbits => 32, sepclk => 1, wrfst => 0,
testen => scantest, custombits => memtest_vlen)
port map (pciclk, scan_prin_m_acc_acc_sel_ahb_fifo_ren, prin.m.fifo_addr, ms_fifoo_atp.data,
clk, scan_ar_s_atp_ctrl_en, ar.s.atp.ctrl.addr, ar.s.atp.ctrl.data,
testin
);
-- PCI master to AHB slave FIFO
pta_fifo1 : syncram_2p generic map (tech => memtech, abits => FIFO_DEPTH+log2(FIFO_COUNT),
dbits => 32, sepclk => 1, wrfst => 0,
testen => scantest, custombits => memtest_vlen)
port map (clk, scan_arin_s_pta_ctrl_en, arin.s.pta.ctrl.addr, ms_fifoo_pta.data,
pciclk, scan_pr_m_acc_acc_sel_ahb_fifo_wen, pr.m.fifo_addr, pr.m.fifo_wdata,
testin
);
end generate;
end generate;
dma_fifo0 : if dma /= 0 generate
scan_prin_m_acc_acc_sel_dma_fifo_ren <= (prin.m.acc(acc_sel_dma).fifo_ren and not scanen);
scan_ar_dma_dtp_ctrl_en <= (ar.dma.dtp.ctrl.en and not scanen);
scan_arin_dma_ptd_ctrl_en <= (arin.dma.ptd.ctrl.en and not scanen);
scan_pr_m_acc_acc_sel_dma_fifo_wen <= (pr.m.acc(acc_sel_dma).fifo_wen and not scanen);
ft0 : if ft /= 0 generate
-- DMA to PCI master FIFO
dtp_fifo2 : syncram_2pft generic map (tech => memtech, abits => FIFO_DEPTH+log2(FIFO_COUNT),
dbits => 32, sepclk => 1, wrfst => 0, ft => ft,
testen => scantest, custombits => memtest_vlen)
port map (pciclk, scan_prin_m_acc_acc_sel_dma_fifo_ren, prin.m.fifo_addr, md_fifoo_dtp.data,
clk, scan_ar_dma_dtp_ctrl_en, ar.dma.dtp.ctrl.addr, ar.dma.dtp.ctrl.data,
md_fifoo_dtp.err, testin
);
-- PCI master to DMA
ptd_fifo2 : syncram_2pft generic map (tech => memtech, abits => FIFO_DEPTH+log2(FIFO_COUNT),
dbits => 32, sepclk => 1, wrfst => 0, ft => ft,
testen => scantest, custombits => memtest_vlen)
port map (clk, scan_arin_dma_ptd_ctrl_en, arin.dma.ptd.ctrl.addr, md_fifoo_ptd.data,
pciclk, scan_pr_m_acc_acc_sel_dma_fifo_wen, pr.m.fifo_addr, pr.m.fifo_wdata,
md_fifoo_dtp.err, testin
);
end generate;
noft0 : if ft = 0 generate
-- DMA to PCI master FIFO
dtp_fifo2 : syncram_2p generic map (tech => memtech, abits => FIFO_DEPTH+log2(FIFO_COUNT),
dbits => 32, sepclk => 1, wrfst => 0,
testen => scantest, custombits => memtest_vlen)
port map (pciclk, scan_prin_m_acc_acc_sel_dma_fifo_ren, prin.m.fifo_addr, md_fifoo_dtp.data,
clk, scan_ar_dma_dtp_ctrl_en, ar.dma.dtp.ctrl.addr, ar.dma.dtp.ctrl.data,
testin
);
-- PCI master to DMA
ptd_fifo2 : syncram_2p generic map (tech => memtech, abits => FIFO_DEPTH+log2(FIFO_COUNT),
dbits => 32, sepclk => 1, wrfst => 0,
testen => scantest, custombits => memtest_vlen)
port map (clk, scan_arin_dma_ptd_ctrl_en, arin.dma.ptd.ctrl.addr, md_fifoo_ptd.data,
pciclk, scan_pr_m_acc_acc_sel_dma_fifo_wen, pr.m.fifo_addr, pr.m.fifo_wdata,
testin
);
end generate;
end generate;
-- PCI trace
trace_fifo0 : if tracebuffer /= 0 generate
scan_tb_ren <= (tb_ren and not scanen);
scan_pr_ptta_trans_enable <= (pr.ptta_trans.enable and not scanen);
pt_fifo0 : syncram_2p generic map (tech => tbmemtech, abits => PT_DEPTH, dbits => 32, sepclk => 1, wrfst => 0,
testen => scantest, custombits => memtest_vlen)
port map (clk, scan_tb_ren, tb_addr(PT_DEPTH+1 downto 2), pt_fifoo_ad.data,
pciclk, scan_pr_ptta_trans_enable, pr.pt.addr, pi.ad,
testin
);
pt_fifoo_ad.err <= (others => '0');
pt_fifo1 : syncram_2p generic map (tech => tbmemtech, abits => PT_DEPTH, dbits => 17, sepclk => 1, wrfst => 0,
testen => scantest, custombits => memtest_vlen)
port map (clk, scan_tb_ren, tb_addr(PT_DEPTH+1 downto 2), pt_fifoo_sig.data(16 downto 0),
pciclk, scan_pr_ptta_trans_enable, pr.pt.addr, pcisig,
testin
);
pt_fifoo_sig.err <= (others => '0');
end generate;
-- IO test module
iotgen : if iotest /= 0 generate
iotm : synciotest
generic map (ninputs => 2, noutputs => 1, nbidir => 44)
port map (
clk => pciclk,
rstn => pcii.rst,
datain => iotmdin,
dataout => iotmdout,
tmode => ar.debuga(5 downto 0),
tmodeact => iotmact,
tmodeoe => iotmoe
);
end generate;
iotngen : if iotest = 0 generate
iotmdout <= (others => '0');
iotmact <= '0';
iotmoe <= '0';
end generate;
--pragma translate_off
bootmsg : report_version
generic map ("grpci2" & tost(hmindex) &
": 32-bit PCI/AHB bridge rev, " & tost(REVISION) &
", " & tost(2**FIFO_DEPTH) & "-word FIFOs" & ", PCI trace: " & tost(((2**PT_DEPTH)*conv_integer(conv_std_logic(tracebuffer/=0)))));
--pragma translate_on
end;
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: acache
-- File: acache.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: Interface module between I/D cache controllers and Amba AHB
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned."+";
use IEEE.std_logic_arith.conv_unsigned;
use work.target.all;
use work.config.all;
use work.iface.all;
use work.amba.all;
use work.macro.all;
entity acache is
port (
rst : in std_logic;
clk : in clk_type;
mcii : in memory_ic_in_type;
mcio : out memory_ic_out_type;
mcdi : in memory_dc_in_type;
mcdo : out memory_dc_out_type;
iuo : in iu_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type
);
end;
architecture rtl of acache is
-- cache control register type
type cctrltype is record
ib : std_logic; -- icache burst enable
dfrz : std_logic; -- dcache freeze enable
ifrz : std_logic; -- icache freeze enable
dsnoop : std_logic; -- data cache snooping
dcs : std_logic_vector(1 downto 0); -- dcache state
ics : std_logic_vector(1 downto 0); -- icache state
end record;
type reg_type is record
bg : std_logic; -- bus grant
bo : std_logic; -- bus owner
ba : std_logic; -- bus active
retry : std_logic; -- retry/split pending
werr : std_logic; -- write error
cctrl : cctrltype;
pwd : std_logic; -- power-down
hcache: std_logic; -- cacheable access
end record;
signal r, rin : reg_type;
begin
comb : process(ahbi, r, rst, mcii, mcdi, iuo, apbi)
variable v : reg_type;
variable haddr : std_logic_vector(31 downto 0); -- address bus
variable htrans : std_logic_vector(1 downto 0); -- transfer type
variable hwrite : std_logic; -- read/write
variable hlock : std_logic; -- bus lock
variable hsize : std_logic_vector(2 downto 0); -- transfer size
variable hburst : std_logic_vector(2 downto 0); -- burst type
variable hwdata : std_logic_vector(31 downto 0); -- write data
variable hbusreq : std_logic; -- bus request
variable iflush, dflush : std_logic;
variable iready, dready : std_logic;
variable igrant, dgrant : std_logic;
variable iretry, dretry : std_logic;
variable ihcache, dhcache, hcache : std_logic;
variable imexc, dmexc, nbo, dreq : std_logic;
variable su : std_logic;
variable cctrl : std_logic_vector(31 downto 0);
begin
-- initialisation
htrans := HTRANS_IDLE;
v := r; iready := '0'; v.werr := '0';
dready := '0'; igrant := '0'; dgrant := '0';
imexc := '0'; dmexc := '0'; hlock := '0'; iretry := '0'; dretry := '0';
ihcache := '0'; dhcache := '0';
iflush := '0'; dflush := '0'; su := '0';
-- decode cacheability
hcache := '0';
for i in PROC_CACHETABLE'range loop --'
if (haddr(31 downto 32-PROC_CACHE_ADDR_MSB) >= PROC_CACHETABLE(i).firstaddr) and
(haddr(31 downto 32-PROC_CACHE_ADDR_MSB) <= PROC_CACHETABLE(i).lastaddr)
then hcache := '1'; end if;
end loop;
-- generate AHB signals
dreq := mcdi.req and not r.pwd;
hbusreq := mcii.req or dreq;
if hbusreq = '1' then htrans := HTRANS_NONSEQ; end if;
hwdata := mcdi.data;
nbo := (dreq and not (r.ba and mcii.req and not r.bo));
if nbo = '0' then
haddr := mcii.address; hwrite := '0'; hsize := HSIZE_WORD; hlock := '0';
su := mcii.su;
if mcii.burst = '1' then hburst := HBURST_INCR;
else hburst := HBURST_SINGLE; end if;
if (mcii.req and r.ba and not r.bo and not r.retry) = '1' then
htrans := HTRANS_SEQ; haddr(4 downto 2) := haddr(4 downto 2) +1;
hburst := HBURST_INCR;
end if;
if (mcii.req and r.bg and ahbi.hready and not r.retry) = '1'
then igrant := '1'; end if;
else
haddr := mcdi.address; hwrite := not mcdi.read; hsize := '0' & mcdi.size;
hlock := mcdi.lock;
if mcdi.asi /= "1010" then su := '1'; else su := '0'; end if;
if (hsize = "011") or ((hcache and mcdi.read) = '1') then
hsize := "010";
end if;
if mcdi.burst = '1' then hburst := HBURST_INCR;
else hburst := HBURST_SINGLE; end if;
if (dreq and r.ba and r.bo and not r.retry) = '1' then
htrans := HTRANS_SEQ; haddr(4 downto 2) := haddr(4 downto 2) +1;
hburst := HBURST_INCR;
end if;
if (dreq and r.bg and ahbi.hready and not r.retry) = '1'
then dgrant := '1'; end if;
end if;
if mcii.req = '0' then hlock := mcdi.lock; end if;
if (r.ba = '1') and
((ahbi.hresp = HRESP_RETRY) or (ahbi.hresp = HRESP_SPLIT))
then v.retry := not ahbi.hready; else v.retry := '0'; end if;
if r.retry = '1' then htrans := HTRANS_IDLE; end if;
if r.bo = '0' then
if r.ba = '1' then
ihcache := r.hcache;
if ahbi.hready = '1' then
case ahbi.hresp is
when HRESP_OKAY => iready := '1';
when HRESP_RETRY | HRESP_SPLIT=> iretry := '1';
when others => iready := '1'; imexc := '1';
end case;
end if;
end if;
else
if r.ba = '1' then
dhcache := r.hcache;
if ahbi.hready = '1' then
case ahbi.hresp is
when HRESP_OKAY => dready := '1';
when HRESP_RETRY | HRESP_SPLIT=> dretry := '1';
when others => dready := '1'; dmexc := '1'; v.werr := not mcdi.read;
end case;
end if;
end if;
hlock := mcdi.lock;
end if;
if ahbi.hready = '1' then
v.hcache := hcache; v.bo := nbo; v.bg := ahbi.hgrant;
if (htrans = HTRANS_NONSEQ) or (htrans = HTRANS_SEQ) then
v.ba := r.bg;
else v.ba := '0'; end if;
end if;
-- cache control and power-down handling
-- cache freeze operation
if (r.cctrl.ifrz and iuo.intack and r.cctrl.ics(0)) = '1' then
v.cctrl.ics := "01";
end if;
if (r.cctrl.dfrz and iuo.intack and r.cctrl.dcs(0)) = '1' then
v.cctrl.dcs := "01";
end if;
if (apbi.psel and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(2 downto 2) is
when "1" =>
v.cctrl.dsnoop := apbi.pwdata(23);
dflush := apbi.pwdata(22);
iflush := apbi.pwdata(21);
v.cctrl.ib := apbi.pwdata(16);
v.cctrl.dfrz := apbi.pwdata(5);
v.cctrl.ifrz := apbi.pwdata(4);
v.cctrl.dcs := apbi.pwdata(3 downto 2);
v.cctrl.ics := apbi.pwdata(1 downto 0);
when others =>
v.pwd := '1';
end case;
end if;
cctrl := (others => '0');
if DSNOOP then cctrl(23) := r.cctrl.dsnoop; end if;
cctrl(16 downto 14) := r.cctrl.ib & mcii.flush & mcdi.flush;
cctrl(5 downto 0) := r.cctrl.dfrz & r.cctrl.ifrz & r.cctrl.dcs & r.cctrl.ics;
-- exit power-down in DSU debug mode
if DEBUG_UNIT then
v.pwd := v.pwd and (not iuo.ipend) and not iuo.debug.dbreak;
else v.pwd := v.pwd and not iuo.ipend; end if;
-- reset operation
if rst = '0' then
v.bg := '0'; v.bo := '0'; v.ba := '0'; v.retry := '0'; v.werr := '0';
v.cctrl.dcs := "00"; v.cctrl.ics := "00"; v.hcache := '0';
v.cctrl.ib := '0'; v.pwd := '0'; v.cctrl.dsnoop := '0';
end if;
-- drive ports
ahbo.haddr <= haddr ;
ahbo.htrans <= htrans;
ahbo.hbusreq <= hbusreq;
ahbo.hwdata <= hwdata;
ahbo.hlock <= hlock;
ahbo.hwrite <= hwrite;
ahbo.hsize <= hsize;
ahbo.hburst <= hburst;
ahbo.hprot <= hcache & hcache & su & nbo;
mcio.grant <= igrant;
mcio.ready <= iready;
mcio.mexc <= imexc;
mcio.retry <= iretry;
mcio.cache <= ihcache;
mcdo.grant <= dgrant;
mcdo.ready <= dready;
mcdo.mexc <= dmexc;
mcdo.retry <= dretry;
mcdo.werr <= r.werr;
mcdo.cache <= dhcache;
mcdo.iflush <= iflush;
mcdo.dflush <= dflush;
mcdo.ba <= r.ba;
mcdo.bg <= r.bg;
mcdo.dsnoop <= r.cctrl.dsnoop;
apbo.prdata <= cctrl;
rin <= v;
end process;
mcio.data <= ahbi.hrdata; mcdo.data <= ahbi.hrdata;
mcio.ics <= r.cctrl.ics; mcdo.dcs <= r.cctrl.dcs;
mcio.burst <= r.cctrl.ib;
reg : process(clk)
begin if rising_edge(clk) then r <= rin; end if; end process;
end;
|
----------------------------------------------------------------------------------------------
-- This file is part of mblite_ip.
--
-- mblite_ip is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- mblite_ip is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with mblite_ip. If not, see <http://www.gnu.org/licenses/>.
--
-- Input file : execute.vhd
-- Design name : execute
-- Author : Tamar Kranenburg
-- Company : Delft University of Technology
-- : Faculty EEMCS, Department ME&CE
-- : Systems and Circuits group
--
-- Description : The Execution Unit performs all arithmetic operations and makes
-- the branch decision. Furthermore the forwarding logic is located
-- here. Everything is computed within a single clock-cycle
--
--
----------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library mblite;
use mblite.config_pkg.all;
use mblite.core_pkg.all;
use mblite.std_pkg.all;
entity execute is generic
(
G_USE_HW_MUL : boolean := CFG_USE_HW_MUL;
G_USE_BARREL : boolean := CFG_USE_BARREL
);
port
(
exec_o : out execute_out_type;
exec_i : in execute_in_type;
ena_i : in std_logic;
rst_i : in std_logic;
clk_i : in std_logic
);
end execute;
architecture arch of execute is
type execute_reg_type is record
carry : std_logic;
flush_ex : std_logic;
end record;
signal r, rin : execute_out_type;
signal reg, regin : execute_reg_type;
begin
exec_o <= r;
execute_comb: process(exec_i,exec_i.fwd_mem,exec_i.ctrl_ex,
exec_i.ctrl_wrb,exec_i.ctrl_mem,
exec_i.ctrl_mem.transfer_size,
exec_i.ctrl_mem_wrb,exec_i.fwd_dec,
r,r.ctrl_mem,r.ctrl_mem.transfer_size,
r.ctrl_wrb,reg)
variable v : execute_out_type;
variable v_reg : execute_reg_type;
variable alu_src_a : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
variable alu_src_b : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
variable carry : std_logic;
variable result : std_logic_vector(CFG_DMEM_WIDTH downto 0);
variable result_add : std_logic_vector(CFG_DMEM_WIDTH downto 0);
variable zero : std_logic;
variable dat_a, dat_b : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
variable sel_dat_a, sel_dat_b, sel_dat_d : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
variable mem_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
begin
v := r;
sel_dat_a := select_register_data(exec_i.dat_a, exec_i.reg_a, exec_i.fwd_dec_result, forward_condition(exec_i.fwd_dec.reg_write, exec_i.fwd_dec.reg_d, exec_i.reg_a));
sel_dat_b := select_register_data(exec_i.dat_b, exec_i.reg_b, exec_i.fwd_dec_result, forward_condition(exec_i.fwd_dec.reg_write, exec_i.fwd_dec.reg_d, exec_i.reg_b));
sel_dat_d := select_register_data(exec_i.dat_d, exec_i.ctrl_wrb.reg_d, exec_i.fwd_dec_result, forward_condition(exec_i.fwd_dec.reg_write, exec_i.fwd_dec.reg_d, exec_i.ctrl_wrb.reg_d));
if reg.flush_ex = '1' then
v.ctrl_mem.mem_write := '0';
v.ctrl_mem.mem_read := '0';
v.ctrl_wrb.reg_write := '0';
v.ctrl_wrb.reg_d := (others => '0');
else
v.ctrl_mem := exec_i.ctrl_mem;
v.ctrl_wrb := exec_i.ctrl_wrb;
end if;
if exec_i.ctrl_mem_wrb.mem_read = '1' then
mem_result := align_mem_load(exec_i.mem_result, exec_i.ctrl_mem_wrb.transfer_size, exec_i.alu_result(1 downto 0));
else
mem_result := exec_i.alu_result;
end if;
if forward_condition(r.ctrl_wrb.reg_write, r.ctrl_wrb.reg_d, exec_i.reg_a) = '1' then
-- Forward Execution Result to REG a
dat_a := r.alu_result;
elsif forward_condition(exec_i.fwd_mem.reg_write, exec_i.fwd_mem.reg_d, exec_i.reg_a) = '1' then
-- Forward Memory Result to REG a
dat_a := mem_result;
else
-- DEFAULT: value of REG a
dat_a := sel_dat_a;
end if;
if forward_condition(r.ctrl_wrb.reg_write, r.ctrl_wrb.reg_d, exec_i.reg_b) = '1' then
-- Forward (latched) Execution Result to REG b
dat_b := r.alu_result;
elsif forward_condition(exec_i.fwd_mem.reg_write, exec_i.fwd_mem.reg_d, exec_i.reg_b) = '1' then
-- Forward Memory Result to REG b
dat_b := mem_result;
else
-- DEFAULT: value of REG b
dat_b := sel_dat_b;
end if;
if forward_condition(r.ctrl_wrb.reg_write, r.ctrl_wrb.reg_d, exec_i.ctrl_wrb.reg_d) = '1' then
-- Forward Execution Result to REG d
v.dat_d := align_mem_store(r.alu_result, exec_i.ctrl_mem.transfer_size);
elsif forward_condition(exec_i.fwd_mem.reg_write, exec_i.fwd_mem.reg_d, exec_i.ctrl_wrb.reg_d) = '1' then
-- Forward Memory Result to REG d
v.dat_d := align_mem_store(mem_result, exec_i.ctrl_mem.transfer_size);
else
-- DEFAULT: value of REG d
v.dat_d := align_mem_store(sel_dat_d, exec_i.ctrl_mem.transfer_size);
end if;
-- Set the first operand of the ALU
case exec_i.ctrl_ex.alu_src_a is
when ALU_SRC_PC => alu_src_a := sign_extend(exec_i.program_counter, '0', 32);
when ALU_SRC_NOT_REGA => alu_src_a := not dat_a;
when ALU_SRC_ZERO => alu_src_a := (others => '0');
when others => alu_src_a := dat_a;
end case;
-- Set the second operand of the ALU
case exec_i.ctrl_ex.alu_src_b is
when ALU_SRC_IMM => alu_src_b := exec_i.imm;
when ALU_SRC_NOT_IMM => alu_src_b := not exec_i.imm;
when ALU_SRC_NOT_REGB => alu_src_b := not dat_b;
when others => alu_src_b := dat_b;
end case;
-- Determine value of carry in
case exec_i.ctrl_ex.carry is
when CARRY_ALU => carry := reg.carry;
when CARRY_ONE => carry := '1';
when CARRY_ARITH => carry := alu_src_a(CFG_DMEM_WIDTH - 1);
when others => carry := '0';
end case;
result_add := add(alu_src_a, alu_src_b, carry);
case exec_i.ctrl_ex.alu_op is
when ALU_ADD => result := result_add;
when ALU_OR => result := '0' & (alu_src_a or alu_src_b);
when ALU_AND => result := '0' & (alu_src_a and alu_src_b);
when ALU_XOR => result := '0' & (alu_src_a xor alu_src_b);
when ALU_SHIFT => result := alu_src_a(0) & carry & alu_src_a(CFG_DMEM_WIDTH - 1 downto 1);
when ALU_SEXT8 => result := '0' & sign_extend(alu_src_a(7 downto 0), alu_src_a(7), 32);
when ALU_SEXT16 => result := '0' & sign_extend(alu_src_a(15 downto 0), alu_src_a(15), 32);
when ALU_MUL =>
if G_USE_HW_MUL = true then
result := '0' & multiply(alu_src_a, alu_src_b);
else
result := (others => '0');
end if;
when ALU_BS =>
if G_USE_BARREL = true then
result := '0' & shift(alu_src_a, alu_src_b(4 downto 0), exec_i.imm(10), exec_i.imm(9));
else
result := (others => '0');
end if;
when others =>
result := (others => '0');
--report "Invalid ALU operation" severity FAILURE;
end case;
-- Set carry register
if exec_i.ctrl_ex.carry_keep = CARRY_KEEP then
v_reg.carry := reg.carry;
else
v_reg.carry := result(CFG_DMEM_WIDTH);
end if;
zero := is_zero(dat_a);
-- Overwrite branch condition
if reg.flush_ex = '1' then
v.branch := '0';
else
-- Determine branch condition
case exec_i.ctrl_ex.branch_cond is
when BNC => v.branch := '1';
when BEQ => v.branch := zero;
when BNE => v.branch := not zero;
when BLT => v.branch := dat_a(CFG_DMEM_WIDTH - 1);
when BLE => v.branch := dat_a(CFG_DMEM_WIDTH - 1) or zero;
when BGT => v.branch := not (dat_a(CFG_DMEM_WIDTH - 1) or zero);
when BGE => v.branch := not dat_a(CFG_DMEM_WIDTH - 1);
when others => v.branch := '0';
end case;
end if;
-- Handle CMPU
if ( exec_i.ctrl_ex.operation and not (alu_src_a(CFG_DMEM_WIDTH - 1) xor alu_src_b(CFG_DMEM_WIDTH - 1))) = '1' then
-- Set MSB
v.alu_result(CFG_DMEM_WIDTH - 1 downto 0) := (not result(CFG_DMEM_WIDTH - 1)) & result(CFG_DMEM_WIDTH - 2 downto 0);
else
-- Use ALU result
v.alu_result := result(CFG_DMEM_WIDTH - 1 downto 0);
end if;
v.program_counter := exec_i.program_counter;
-- Determine flush signals
v.flush_id := v.branch;
v_reg.flush_ex := v.branch and not exec_i.ctrl_ex.delay;
rin <= v;
regin <= v_reg;
end process;
execute_seq: process(clk_i)
procedure proc_execute_reset is
begin
r.alu_result <= (others => '0');
r.dat_d <= (others => '0');
r.branch <= '0';
r.program_counter <= (others => '0');
r.flush_id <= '0';
r.ctrl_mem.mem_write <= '0';
r.ctrl_mem.mem_read <= '0';
r.ctrl_mem.transfer_size <= WORD;
r.ctrl_wrb.reg_d <= (others => '0');
r.ctrl_wrb.reg_write <= '0';
reg.carry <= '0';
reg.flush_ex <= '0';
end procedure proc_execute_reset;
begin
if rising_edge(clk_i) then
if rst_i = '1' then
proc_execute_reset;
elsif ena_i = '1' then
r <= rin;
reg <= regin;
end if;
end if;
end process;
end arch;
|
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
--
-- Title Thread Manager
--
-- 26 Jul 2004: Mike Finley: Original author
-- 08 Jun 2005: Erik Anderson: Changes for new interface between TM and
-- Scheduler. Also adding function isQueue().
-- 15 Apr 2009: Jim Stevens: Ported to PLB version 4.6.
--
---------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_NUM_REG -- Number of software accessible registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Addr -- Bus to IP address bus
-- Bus2IP_CS -- Bus to IP chip select
-- Bus2IP_RNW -- Bus to IP read/not write
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 1;
-- DO NOT EDIT ABOVE THIS LINE ---------------------
C_RESET_TIMEOUT : natural := 4096
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to 31);
Bus2IP_CS : in std_logic_vector(0 to 0);
Bus2IP_RNW : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic;
-- DO NOT EDIT ABOVE THIS LINE ---------------------
Access_Intr : out std_logic;
Scheduler_Reset : out std_logic;
Scheduler_Reset_Done : in std_logic;
Semaphore_Reset : out std_logic;
Semaphore_Reset_Done : in std_logic;
SpinLock_Reset : out std_logic;
SpinLock_Reset_Done : in std_logic;
User_IP_Reset : out std_logic;
User_IP_Reset_Done : in std_logic;
Soft_Stop : out std_logic;
tm2sch_cpu_thread_id : out std_logic_vector(0 to 7);
tm2sch_opcode : out std_logic_vector(0 to 5);
tm2sch_data : out std_logic_vector(0 to 7);
tm2sch_request : out std_logic;
tm2sch_DOB : out std_logic_vector(0 to 31);
sch2tm_ADDRB : in std_logic_vector(0 to 8);
sch2tm_DIB : in std_logic_vector(0 to 31);
sch2tm_ENB : in std_logic;
sch2tm_WEB : in std_logic;
sch2tm_busy : in std_logic;
sch2tm_data : in std_logic_vector(0 to 7);
sch2tm_next_id : in std_logic_vector(0 to 7);
sch2tm_next_id_valid : in std_logic
);
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Reset : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
-- Define the memory map for each register, Address[16 to 21]
--
constant C_CLEAR_THREAD : std_logic_vector(0 to 5) := "000000";
constant C_JOIN_THREAD : std_logic_vector(0 to 5) := "000001";
constant C_READ_THREAD : std_logic_vector(0 to 5) := "000011";
constant C_ADD_THREAD : std_logic_vector(0 to 5) := "000100";
constant C_CREATE_THREAD_J : std_logic_vector(0 to 5) := "000101";
constant C_CREATE_THREAD_D : std_logic_vector(0 to 5) := "000110";
constant C_EXIT_THREAD : std_logic_vector(0 to 5) := "000111";
constant C_NEXT_THREAD : std_logic_vector(0 to 5) := "001000";
constant C_YIELD_THREAD : std_logic_vector(0 to 5) := "001001";
constant C_CURRENT_THREAD : std_logic_vector(0 to 5) := "010000";
constant C_IS_DETACHED : std_logic_vector(0 to 5) := "011000";
constant C_IS_QUEUED : std_logic_vector(0 to 5) := "011001";
constant C_EXCEPTION_ADDR : std_logic_vector(0 to 5) := "010011";
constant C_EXCEPTION_REG : std_logic_vector(0 to 5) := "010100";
constant C_SOFT_START : std_logic_vector(0 to 5) := "010101";
constant C_SOFT_STOP : std_logic_vector(0 to 5) := "010110";
constant C_SOFT_RESET : std_logic_vector(0 to 5) := "010111";
constant C_SCHED_LINES : std_logic_vector(0 to 5) := "011010";
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
constant OPCODE_IS_QUEUED : std_logic_vector(0 to 5) := "000001";
constant OPCODE_ENQUEUE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DEQUEUE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_IS_EMPTY : std_logic_vector(0 to 5) := "000110";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
constant H32 : std_logic_vector(0 to 31) := (others => '1');
constant MAX_QUEUE_SIZE : std_logic_vector(0 to 7) := (others => '1');
constant TOUT_CYCLES : natural := 3; -- assert timeout suppress
signal cycle_count : std_logic_vector(0 to 15);
signal timeout_expired : std_logic;
-- Extended Thread Error Codes returned in lower 4 bits
constant ERROR_IN_STATUS : std_logic_vector(0 to 3) := "0001";
constant THREAD_ALREADY_TERMINATED : std_logic_vector(0 to 3) := "0011";
constant THREAD_ALREADY_QUEUED : std_logic_vector(0 to 3) := "0101";
constant ERROR_FROM_SCHEDULER : std_logic_vector(0 to 3) := "0111";
constant JOIN_ERROR_CHILD_JOINED : std_logic_vector(0 to 3) := "1001";
constant JOIN_ERROR_NOT_CHILD : std_logic_vector(0 to 3) := "1011";
constant JOIN_ERROR_CHILD_DETACHED : std_logic_vector(0 to 3) := "1101";
constant JOIN_ERROR_CHILD_NOT_USED : std_logic_vector(0 to 3) := "1111";
constant JOIN_ERROR_UNKNOWN : std_logic_vector(0 to 3) := "0001";
constant CLEAR_ERROR_NOT_USED : std_logic_vector(0 to 3) := "1001";
-- Exception "cause" returned in Exception register
constant EXCEPTION_WRITE_TO_READ_ONLY : std_logic_vector(0 to 3) := "0001";
constant EXCEPTION_UNDEFINED_ADDRESS : std_logic_vector(0 to 3) := "0010";
constant EXCEPTION_TO_SOFT_RESET : std_logic_vector(0 to 3) := "0011";
constant EXCEPTION_TO_SCHD_ISQUEUED : std_logic_vector(0 to 3) := "0100";
constant EXCEPTION_TO_SCHD_ENQUEUE : std_logic_vector(0 to 3) := "0101";
constant EXCEPTION_TO_SCHD_DEQUEUE : std_logic_vector(0 to 3) := "0110";
constant EXCEPTION_TO_SCHD_ISEMPTY : std_logic_vector(0 to 3) := "0111";
constant EXCEPTION_TO_SCHD_NEXT_THREAD : std_logic_vector(0 to 3) := "1000";
constant EXCEPTION_SCHD_INVALID_THREAD : std_logic_vector(0 to 3) := "1001";
constant EXCEPTION_ILLEGAL_STATE : std_logic_vector(0 to 3) := "1111";
-- BRAM constants
constant BRAM_ADDRESS_BITS : integer := 9;
constant BRAM_DATA_BITS : integer := 32;
-- Address,Cause for access exceptions
--
signal Exception_Address : std_logic_vector(0 to 31);
signal Exception_Address_next : std_logic_vector(0 to 31);
signal Exception_Cause : std_logic_vector(0 to 3);
signal Exception_Cause_next : std_logic_vector(0 to 3);
signal access_error : std_logic;
-- Debug control signals
--
-- Soft reset signals, LSB = SWTM reset; reset IP(s) if '1'
-- Resets done, handshake from IPs if done resetting(1)
-- core_stop , halt state machines at next appropriate point if '1'
--
signal soft_resets : std_logic_vector(0 to 4);
signal soft_resets_next : std_logic_vector(0 to 4);
signal resets_done : std_logic_vector(0 to 4);
signal reset_status : std_logic_vector(0 to 4);
signal reset_status_next : std_logic_vector(0 to 4);
signal core_stop : std_logic;
signal core_stop_next : std_logic;
-- Declarations for each register
-- Current thread,Idle thread : bits 0..7 = ID, bit 8 = '1' = invalid
signal current_cpu_thread : std_logic_vector(0 to 8);
signal current_cpu_thread_next : std_logic_vector(0 to 8);
-- internal signals
signal next_ID : std_logic_vector(0 to 8);
signal next_ID_next : std_logic_vector(0 to 8);
signal temp_thread_id : std_logic_vector(0 to 7);
signal temp_thread_id_next : std_logic_vector(0 to 7);
signal temp_thread_id2 : std_logic_vector(0 to 7);
signal temp_thread_id2_next : std_logic_vector(0 to 7);
signal reset_ID : std_logic_vector(0 to 8);
type swtm_state_type is
(IDLE_STATE,
SOFT_RESET_WRITE_INIT,
SOFT_RESET_INIT_TABLE,
SOFT_RESET_WAIT,
READ_THREAD_INIT,
READ_THREAD_RD_WAIT,
READ_THREAD_DONE,
CREATE_THREAD_INIT,
CT_NEW_ID_RD_WAIT,
CT_NEW_ID_AVAILABLE,
CT_ENTRY_RD_WAIT,
CT_ENTRY_AVAILABLE,
CT_DONE,
CLEAR_THREAD_INIT,
CLEAR_ENTRY_RD_WAIT,
CLEAR_ENTRY_AVAIABLE,
DEALLOCATE_ID,
DEALLOCATE_NEXT_ENTRY_RD_WAIT,
DEALLOCATE_NEXT_ENTRY_AVAIL,
JOIN_THREAD_INIT,
JOIN_RD_ENTRY_RD_WAIT,
JOIN_RD_ENTRY_AVAILABLE,
IS_QUEUED_INIT,
IS_QUEUED_DONE,
IS_DETACHED_THREAD_INIT,
IS_DETACHED_ENTRY_RD_WAIT,
IS_DETACHED_ENTRY_AVAILABLE,
NEXT_THREAD_INIT,
NEXT_THREAD_WAIT4_SCHEDULER,
NEXT_THREAD_RD_WAIT,
NEXT_THREAD_AVAILABLE,
NEXT_THREAD_CHECK_DEQUEUE,
ADD_THREAD_INIT,
AT_ENTRY_RD_WAIT,
AT_ENTRY_AVAILABLE,
AT_ISQUEUED_WAIT,
AT_CHECK_ISQUEUE,
AT_ENQUEUE_WAIT,
AT_CHECK_ENQUEUE,
ISQUEUED_WAIT_ACK,
ISQUEUED_WAIT_COMPLETE,
ENQUEUE_WAIT_ACK,
ENQUEUE_WAIT_COMPLETE,
DEQUEUE_WAIT_ACK,
DEQUEUE_WAIT_COMPLETE,
IS_QUEUE_EMPTY_WAIT_ACK,
IS_QUEUE_EMPTY_WAIT_COMPLETE,
YIELD_THREAD_INIT,
YIELD_CURRENT_THREAD_RD_WAIT,
YIELD_CURRENT_THREAD_AVAILABLE,
YIELD_CHECK_QUEUE_EMPTY,
YIELD_ENQUEUE,
YIELD_CHECK_ENQUEUE,
-- YIELD_dummy_is_queued,
YIELD_DEQUEUE,
YIELD_CHECK_DEQUEUE,
EXIT_THREAD_INIT,
EXIT_THREAD_RD_WAIT,
EXIT_THREAD_AVAIABLE,
EXIT_DEALLOCATE,
EXIT_NEXT_THREAD_RD_WAIT,
EXIT_NEXT_THREAD_AVAILABLE,
EXIT_READ_PARENT,
EXIT_READ_PARENT_WAIT,
EXIT_READ_PARENT_AVAILABLE,
EXIT_CHECK_ENQUEUE,
RAISE_EXCEPTION,
END_TRANSACTION,
END_TRANSACTION_WAIT);
signal current_state, next_state : swtm_state_type := IDLE_STATE;
signal return_state, return_state_next : swtm_state_type := IDLE_STATE;
signal bus_data_out : std_logic_vector(0 to 31);
signal bus_data_out_next : std_logic_vector(0 to 31);
signal current_status : std_logic_vector(0 to 31);
signal current_status_next : std_logic_vector(0 to 31);
signal Swtm_Reset_Done : std_logic;
signal Swtm_Reset_Done_next : std_logic;
signal new_ID : std_logic_vector(0 to 7);
signal new_ID_next : std_logic_vector(0 to 7);
signal tm2sch_request_next : std_logic;
signal tm2sch_request_reg : std_logic;
signal tm2sch_data_next : std_logic_vector(0 to 7);
signal tm2sch_data_reg : std_logic_vector(0 to 7);
signal tm2sch_opcode_next : std_logic_vector(0 to 5);
signal tm2sch_opcode_reg : std_logic_vector(0 to 5);
-- Signals for thread table BRAM
signal ENA : std_logic;
signal WEA : std_logic;
signal ADDRA : std_logic_vector(0 to BRAM_ADDRESS_BITS - 1);
signal DIA : std_logic_vector(0 to BRAM_DATA_BITS - 1);
signal DOA : std_logic_vector(0 to BRAM_DATA_BITS - 1);
alias addr :std_logic_vector(0 to 5) is Bus2IP_Addr(16 to 21);
---------------------------------------------------------------------------
-- Component Instantiation of inferred dual ported block RAM
---------------------------------------------------------------------------
component infer_bram_dual_port is
generic (
ADDRESS_BITS : integer := 9;
DATA_BITS : integer := 32
);
port (
CLKA : in std_logic;
ENA : in std_logic;
WEA : in std_logic;
ADDRA : in std_logic_vector(0 to ADDRESS_BITS - 1);
DIA : in std_logic_vector(0 to DATA_BITS - 1);
DOA : out std_logic_vector(0 to DATA_BITS - 1);
CLKB : in std_logic;
ENB : in std_logic;
WEB : in std_logic;
ADDRB : in std_logic_vector(0 to ADDRESS_BITS - 1);
DIB : in std_logic_vector(0 to DATA_BITS - 1);
DOB : out std_logic_vector(0 to DATA_BITS - 1)
);
end component infer_bram_dual_port;
-------------------------------------------------------------------
-- ICON core signal declarations
-------------------------------------------------------------------
signal control0 : std_logic_vector(35 downto 0);
signal my_ack, my_tout_sup, my_error, my_sched_req : std_logic; -- TODO: This line might be gone.
signal my_counter : std_logic_vector(0 to 31);
-------------------------------------------------------------------
-- ICON core component declaration
-------------------------------------------------------------------
-- simulation translate_off
--component chipscope_icon_v1_03_a
-- port
-- (
-- control0 : out std_logic_vector(35 downto 0)
-- );
--end component;
-- simulation translate_on
-------------------------------------------------------------------
-- ILA core component declaration
-------------------------------------------------------------------
-- simulation translate_off
--component chipscope_ila_v1_02_a
-- port
-- (
--- control : in std_logic_vector(35 downto 0);
-- clk : in std_logic;
-- trig0 : in std_logic_vector(63 downto 0);
-- trig1 : in std_logic_vector(63 downto 0);
-- trig2 : in std_logic_vector(31 downto 0);
-- trig3 : in std_logic_vector(31 downto 0);
-- trig4 : in std_logic_vector(15 downto 0)
-- );
--end component;
-- simulation translate_on
begin
-----------------------------------------------------------------------
-- thread_data_bram_tmp : infer_bram
-- generic map
-- (
-- ADDRESS_BITS => BRAM_ADDRESS_BITS,
-- DATA_BITS => BRAM_DATA_BITS
-- )
-- port map
-- (
-- CLKA => Bus2IP_Clk,
-- ENA => ENA,
-- WEA => WEA,
-- ADDRA => ADDRA,
-- DIA => DIA,
-- DOA => DOA
-- );
-----------------------------------------------------------------------
thread_table_bram : infer_bram_dual_port
generic map (
ADDRESS_BITS => BRAM_ADDRESS_BITS,
DATA_BITS => BRAM_DATA_BITS
)
port map (
CLKA => Bus2IP_Clk,
ENA => ENA,
WEA => WEA,
ADDRA => ADDRA,
DIA => DIA,
DOA => DOA,
CLKB => Bus2IP_Clk,
ENB => sch2tm_ENB,
WEB => sch2tm_WEB,
ADDRB => sch2tm_ADDRB,
DIB => sch2tm_DIB,
DOB => tm2sch_DOB
);
tm2sch_opcode <= tm2sch_opcode_reg;
tm2sch_data <= tm2sch_data_reg;
tm2sch_request <= tm2sch_request_reg;
Soft_Stop <= core_stop;
Scheduler_Reset <= soft_resets(3);
Semaphore_Reset <= soft_resets(2);
SpinLock_Reset <= soft_resets(1);
User_IP_Reset <= soft_resets(0);
Access_Intr <= access_error;
CYCLE_PROC : process (Bus2IP_Clk, Bus2IP_CS) is
begin
if( Bus2IP_Clk'event and Bus2IP_Clk='1' ) then
if( Bus2IP_CS(0) = '0' ) then
cycle_count <= (others => '0');
else
cycle_count <= cycle_count + 1;
end if;
end if;
end process CYCLE_PROC;
--
-- create a counter for the number of elapsed cycles
-- in each bus transaction.
-- assert TimeOut suppress when count = TOUT_CYCLES
--
CYCLE_CONTROL : process( cycle_count ) is
begin
IP2Bus_Error <= '0'; -- no error
--
-- count the number of elapsed clock cycles in transaction
--
if cycle_count < C_RESET_TIMEOUT then
timeout_expired <= '0';
else
--timeout_expired <= '1';
timeout_expired <= '0'; -- Disable timeouts.
end if;
--
-- activate time out suppress if count exceeds TOUT_CYCLES
-- edk. Why isn't this done inside the clk_event ???
--
-- if cycle_count > TOUT_CYCLES then
-- --IP2Bus_ToutSup <= '1'; -- halt time out counter
-- my_tout_sup <= '1'; -- halt time out counter
-- else
-- --IP2Bus_ToutSup <= '0'; -- release
-- my_tout_sup <= '0'; -- release
-- end if;
end process CYCLE_CONTROL;
-- IP2Bus_ToutSup <= my_tout_sup;
RESET_PROC : process (Bus2IP_Clk, addr, current_state)
begin
if( Bus2IP_Clk'event and Bus2IP_Clk = '1' ) then
if( addr = C_SOFT_RESET and current_state = SOFT_RESET_WRITE_INIT ) then
reset_ID <= (others => '0');
else
reset_ID <= reset_ID + 1;
end if;
end if;
end process;
ACK_PROC : process(my_ack, Bus2IP_RdCE, Bus2IP_WrCE)
begin
if (Bus2IP_RdCE(0) = '1') then
IP2Bus_RdAck <= my_ack;
else
IP2Bus_RdAck <= '0';
end if;
if (Bus2IP_WrCE(0) = '1') then
IP2Bus_WrAck <= my_ack;
else
IP2Bus_WrAck <= '0';
end if;
end process;
SWTM_STATE_PROC : process (Bus2IP_Clk, core_stop_next, new_ID_next, next_ID_next, temp_thread_id_next, temp_thread_id2_next, current_cpu_thread_next, Current_status_next, soft_resets_next, reset_status_next, Swtm_Reset_Done_next, Scheduler_Reset_Done, Semaphore_Reset_Done, SpinLock_Reset_Done, User_IP_Reset_Done, next_state, return_state_next, Bus2IP_Reset,Exception_Cause_next) is
begin
if (Bus2IP_Clk'event and (Bus2IP_Clk = '1')) then
core_stop <= core_stop_next;
new_ID <= new_ID_next;
next_ID <= next_ID_next;
temp_thread_id <= temp_thread_id_next;
temp_thread_id2 <= temp_thread_id2_next;
current_cpu_thread <= current_cpu_thread_next;
tm2sch_cpu_thread_id <= current_cpu_thread_next(0 to 7);
tm2sch_data_reg <= tm2sch_data_next;
tm2sch_opcode_reg <= tm2sch_opcode_next;
tm2sch_request_reg <= tm2sch_request_next;
current_status <= current_status_next;
Exception_Address <= Exception_Address_next;
Exception_Cause <= Exception_Cause_next;
soft_resets <= soft_resets_next;
reset_status <= reset_status_next;
bus_data_out <= bus_data_out_next;
Swtm_Reset_Done <= Swtm_Reset_Done_next;
resets_done(4) <= Swtm_Reset_Done_next;
resets_done(3) <= Scheduler_Reset_Done;
resets_done(2) <= Semaphore_Reset_Done;
resets_done(1) <= SpinLock_Reset_Done;
resets_done(0) <= User_IP_Reset_Done;
return_state <= return_state_next;
if( Bus2IP_Reset = '1' ) then
current_state <= IDLE_STATE;
else
current_state <= next_state;
end if;
end if;
end process SWTM_STATE_PROC;
-- IP2Bus_Ack <= my_ack; -- pulse(010) to end bus transaction
SWTM_LOGIC_PROC : process (current_state, core_stop, new_ID, next_ID, current_cpu_thread, current_status, reset_status, Swtm_Reset_Done, soft_resets, Bus2IP_Addr, Bus2IP_Data, Exception_Address, Bus2IP_WrCE, addr, Bus2IP_RdCE, reset_ID, resets_done, timeout_expired, DOA, sch2tm_next_id_valid, sch2tm_next_id, sch2tm_busy, bus_data_out, Exception_Cause, tm2sch_request_reg, tm2sch_data_reg, tm2sch_opcode_reg, temp_thread_id, temp_thread_id2) is
begin
-- -------------------------------------------------
-- default output signal assignments
-- -------------------------------------------------
my_ack <= '0'; -- pulse(010) to end bus transaction
access_error <= '0'; -- pulse(010) for access error interrupt
IP2Bus_Data <= (others => '0');
ADDRA <= (others => '0');
ENA <= '0';
WEA <= '0';
DIA <= (others => '0');
-- -------------------------------------------------
-- default register assignments
-- -------------------------------------------------
next_state <= current_state;
return_state_next <= return_state;
core_stop_next <= core_stop;
new_ID_next <= new_ID;
next_ID_next <= next_ID;
temp_thread_id_next <= temp_thread_id;
temp_thread_id2_next <= temp_thread_id2;
current_cpu_thread_next <= current_cpu_thread;
current_status_next <= current_status;
Exception_Address_next <= Exception_Address;
reset_status_next <= reset_status;
Swtm_Reset_Done_next <= Swtm_Reset_Done;
Exception_Cause_next <= Exception_Cause;
tm2sch_request_next <= tm2sch_request_reg;
tm2sch_data_next <= tm2sch_data_reg;
tm2sch_opcode_next <= tm2sch_opcode_reg;
bus_data_out_next <= bus_data_out;
soft_resets_next <= soft_resets;
case current_state is
-- Command (addr) decode whenever we are waiting for something new to do.
when IDLE_STATE =>
bus_data_out_next <= (others => '0');
if (Bus2IP_WrCE(0) = '1') then
case addr is
when C_SOFT_START =>
-- Any write to soft_start address clears
-- all soft reset signals and the Soft_Stop signal
soft_resets_next <= (others => '0');
swtm_reset_done_next <= '0'; -- clear SWTM's reset done
core_stop_next <= '0'; -- clear core_stop
next_state <= END_TRANSACTION;
when C_SOFT_STOP =>
-- write any data to Soft_Stop to assert the Soft_Stop signal
core_stop_next <= '1';
next_state <= END_TRANSACTION;
when C_SOFT_RESET =>
next_state <= SOFT_RESET_WRITE_INIT;
when C_READ_THREAD =>
if (core_stop = '1') then
ADDRA <= '0' & Bus2IP_Addr(22 to 29); -- thread ID
WEA <= '1';
ENA <= '1';
DIA <= Bus2IP_Data(0 to 31);
next_state <= END_TRANSACTION;
else
Exception_Cause_next <= EXCEPTION_WRITE_TO_READ_ONLY;
next_state <= RAISE_EXCEPTION;
end if;
when others =>
Exception_Cause_next <= EXCEPTION_UNDEFINED_ADDRESS;
next_state <= RAISE_EXCEPTION;
end case;
elsif (Bus2IP_RdCE(0) = '1') then
case addr is
when C_SOFT_START =>
bus_data_out_next <= (others => '0');
next_state <= END_TRANSACTION;
when C_SOFT_STOP =>
-- returns signal level in LSB on read
bus_data_out_next <= Z32(0 to 30) & core_stop;
next_state <= END_TRANSACTION;
when C_SOFT_RESET =>
-- returns 1's in bit positions that failed
bus_data_out_next <= Z32(0 to 26) & reset_status;
next_state <= END_TRANSACTION;
when C_CURRENT_THREAD =>
bus_data_out_next <= Z32(0 to 22) & current_cpu_thread;
next_state <= END_TRANSACTION;
when C_EXCEPTION_ADDR =>
bus_data_out_next <= Exception_Address;
Exception_Address_next <= (others => '0');
next_state <= END_TRANSACTION;
when C_EXCEPTION_REG =>
bus_data_out_next <= Z32(0 to 27) & Exception_Cause;
Exception_Cause_next <= (others => '0');
next_state <= END_TRANSACTION;
when C_SCHED_LINES =>
bus_data_out_next <= Z32(0 to 6) & sch2tm_busy & sch2tm_data &
Z32(16 to 22) & sch2tm_next_id_valid &
sch2tm_next_id;
next_state <= END_TRANSACTION;
when C_READ_THREAD => next_state <= READ_THREAD_INIT;
when C_CREATE_THREAD_D => next_state <= CREATE_THREAD_INIT;
when C_CREATE_THREAD_J => next_state <= CREATE_THREAD_INIT;
when C_CLEAR_THREAD => next_state <= CLEAR_THREAD_INIT;
when C_JOIN_THREAD => next_state <= JOIN_THREAD_INIT;
when C_IS_DETACHED => next_state <= IS_DETACHED_THREAD_INIT;
when C_IS_QUEUED => next_state <= IS_QUEUED_INIT;
when C_NEXT_THREAD => next_state <= NEXT_THREAD_INIT;
when C_ADD_THREAD => next_state <= ADD_THREAD_INIT;
when C_YIELD_THREAD => next_state <= YIELD_THREAD_INIT;
when C_EXIT_THREAD => next_state <= EXIT_THREAD_INIT;
when others =>
Exception_Cause_next <= EXCEPTION_UNDEFINED_ADDRESS;
next_state <= RAISE_EXCEPTION;
end case;
end if;
--
-- read/write to the soft resets register (1 bit per IP)
-- write '1' to reset, reads '1' if timeout error occured
-- before IP reports finished
--
-- SW Thread Manager = bit#4 (LSB)
-- Scheduler = bit#3
-- Semaphore = bit#2
-- SpinLock = bit#1
-- User_IP = bit#0
--
when SOFT_RESET_WRITE_INIT =>
soft_resets_next <= Bus2IP_Data(27 to 31);
reset_status_next <= (others => '0');
swtm_reset_done_next <= '0'; -- clear SWTM's reset_done
if (Bus2IP_Data(31) = '1') then -- soft_resets(4)
--
-- perform a soft reset on SWTM
--
bus_data_out_next <= (others => '0');
new_ID_next <= (others => '0');
next_ID_next <= (others => '0');
temp_thread_id_next <= (others => '0');
current_cpu_thread_next <= Z32(0 to 7) & '1';
core_stop_next <= '0';
tm2sch_opcode_next <= OPCODE_NOOP;
tm2sch_data_next <= (others => '0');
tm2sch_request_next <= '0';
next_state <= SOFT_RESET_INIT_TABLE;
else
next_state <= SOFT_RESET_WAIT;
end if;
-- initialize the thread ID table to all zeros
-- and the next available stack to 0..255
when SOFT_RESET_INIT_TABLE =>
ADDRA <= reset_ID;
ENA <= '1';
WEA <= '1';
if( reset_ID(0) = '0' ) then
-- init available ID stack & thread ID table
DIA <= reset_ID(1 to 8) & Z32(0 to 23);
else
-- clear 2nd half of table (unused)
DIA <= Z32(0 to 31);
end if;
if( reset_ID = H32(0 to 8) ) then
swtm_reset_done_next<= '1'; -- done
next_state <= soft_reset_wait;
end if;
-- wait for all IPs to finish initialization or
-- the maximum time to be exceeded then
-- ack to finish transaction
when SOFT_RESET_WAIT =>
if (resets_done = soft_resets) then -- done
next_state <= END_TRANSACTION;
elsif (timeout_expired = '1') then
reset_status_next <= (resets_done xor soft_resets);
Exception_Cause_next <= EXCEPTION_TO_SOFT_RESET;
next_state <= RAISE_EXCEPTION; -- timeout
else
next_state <= current_state;
end if;
when READ_THREAD_INIT =>
ADDRA <= '0' & Bus2IP_Addr(22 to 29); -- thread ID
WEA <= '0';
ENA <= '1';
next_state <= READ_THREAD_RD_WAIT;
when READ_THREAD_RD_WAIT =>
next_state <= READ_THREAD_DONE;
when READ_THREAD_DONE =>
bus_data_out_next <= DOA;
next_state <= END_TRANSACTION;
when CREATE_THREAD_INIT =>
if next_ID(0) = '1' then
-- no IDs available, return with error bit set
--
bus_data_out_next <= Z32(0 to 30) & '1';
next_state <= END_TRANSACTION;
else
-- read next ID from stack
--
ADDRA <= next_ID;
ENA <= '1';
next_state <= CT_NEW_ID_RD_WAIT;
end if;
when CT_NEW_ID_RD_WAIT =>
next_state <= CT_NEW_ID_AVAILABLE;
when CT_NEW_ID_AVAILABLE =>
new_ID_next <= DOA(0 to 7); -- save new ID#
ADDRA <= '0' & DOA(0 to 7); -- point to new thread
ENA <= '1';
next_state <= CT_ENTRY_RD_WAIT;
when CT_ENTRY_RD_WAIT =>
next_state <= CT_ENTRY_AVAILABLE;
when CT_ENTRY_AVAILABLE =>
ADDRA <= '0' & new_ID;
ENA <= '1';
WEA <= '1'; -- enable write to bram
-- Determine if the thread to create is DETACHED / JOINABLE
if addr = C_CREATE_THREAD_D then -- set new thread status
-- create detached
DIA <= DOA(0 to 7) & Z32(0 to 7) &
Z32(0 to 7) & "1011" & Z32(0 to 3);
else
-- create joinable
DIA <= DOA(0 to 7) & Z32(0 to 7) &
current_cpu_thread(0 to 7) & "0011" & Z32(0 to 3);
end if;
next_state <= CT_DONE;
when CT_DONE =>
-- return new ID with no error,
bus_data_out_next <= Z32(0 to 22) & new_ID & '0';
-- point to next available ID
next_ID_next <= next_ID + 1;
next_state <= END_TRANSACTION;
when CLEAR_THREAD_INIT =>
-- clear the encoded thread ID if it is used and exited
ADDRA <= '0' & Bus2IP_Addr(22 to 29); -- thread ID
ENA <= '1';
next_state <= CLEAR_ENTRY_RD_WAIT;
when CLEAR_ENTRY_RD_WAIT =>
next_state <= CLEAR_ENTRY_AVAIABLE ;
when CLEAR_ENTRY_AVAIABLE =>
if (DOA(26 to 27) = "10") then -- used and exited
bus_data_out_next <= Z32; -- success, return zero
ADDRA <= '0' & Bus2IP_Addr(22 to 29); -- thread ID
ENA <= '1';
WEA <= '1'; -- clear old status but
DIA <= DOA(0 to 7) & Z32(0 to 23); -- preserve ID stack
next_state <= DEALLOCATE_ID;
else
-- error occurred, return thread status w/ LSB=1
bus_data_out_next <= DOA(0 to 27) & CLEAR_ERROR_NOT_USED;
next_state <= END_TRANSACTION;
end if;
when DEALLOCATE_ID =>
if (next_ID /= Z32(0 to 8)) then
ADDRA <= next_ID - 1;
ENA <= '1';
next_ID_next <= next_ID - 1;
next_state <= DEALLOCATE_NEXT_ENTRY_RD_WAIT;
else
next_state <= END_TRANSACTION;
end if;
when DEALLOCATE_NEXT_ENTRY_RD_WAIT =>
next_state <= DEALLOCATE_NEXT_ENTRY_AVAIL;
when DEALLOCATE_NEXT_ENTRY_AVAIL =>
-- put ID back on stack, preserve other bits
ADDRA <= next_ID;
ENA <= '1';
WEA <= '1';
DIA <= Bus2IP_Addr(22 to 29) & DOA(8 to 31);
next_state <= END_TRANSACTION;
when JOIN_THREAD_INIT =>
-- join on the encoded thread ID if its PID = current_thread
-- and its status = used,~joined,~detached
ADDRA <= '0' & Bus2IP_Addr(22 to 29); -- thread ID
ENA <= '1';
next_state <= JOIN_RD_ENTRY_RD_WAIT;
when JOIN_RD_ENTRY_RD_WAIT =>
next_state <= JOIN_RD_ENTRY_AVAILABLE;
when JOIN_RD_ENTRY_AVAILABLE =>
if ((DOA(16 to 23) & '0' = current_cpu_thread) and -- PID = current thread
(DOA(24 to 25) = "00") and -- ~detached,~joined
(DOA(26 to 27) /= "00")) then -- not unused
if DOA(27) = '0' then
-- thread has already exited, return a WARNING code
bus_data_out_next <= Z32(0 to 27) & THREAD_ALREADY_TERMINATED;
next_state <= END_TRANSACTION;
else
-- thread has not exited
bus_data_out_next <= Z32; -- success, return zero
ADDRA <= '0' & Bus2IP_Addr(22 to 29); -- thread ID
ENA <= '1';
WEA <= '1';
-- clear old status but
-- set joined bit; and preserve all other bits
DIA <= DOA(0 to 24) & '1' & DOA(26 to 31);
next_state <= END_TRANSACTION;
end if;
else
-- An error occured. Determine the error and return correct error code.
if( DOA(24) = '1' ) then
-- trying to join on a detached thread
bus_data_out_next <= DOA(0 to 27) & JOIN_ERROR_CHILD_DETACHED;
elsif ( DOA(24 to 25) = "01" ) then
-- tyring to join on a thread that is already joined
bus_data_out_next <= DOA(0 to 27) & JOIN_ERROR_CHILD_JOINED;
elsif( DOA(26) = '0' ) then
-- trying to join on a thread that is not used
bus_data_out_next <= DOA(0 to 27) & JOIN_ERROR_CHILD_NOT_USED;
elsif( DOA(16 to 23) & '0' /= current_cpu_thread ) then
-- trying to join to a thread that is not the current thread's child
bus_data_out_next <= DOA(0 to 27) & JOIN_ERROR_NOT_CHILD;
else
bus_data_out_next <= DOA(0 to 27) & JOIN_ERROR_UNKNOWN;
end if;
next_state <= END_TRANSACTION;
end if;
when IS_DETACHED_THREAD_INIT =>
-- Returns a 1 if the encoded thread ID is detached, else returns 0
ADDRA <= '0' & Bus2IP_Addr(22 to 29); -- thread ID
ENA <= '1';
next_state <= IS_DETACHED_ENTRY_RD_WAIT;
when IS_DETACHED_ENTRY_RD_WAIT =>
next_state <= IS_DETACHED_ENTRY_AVAILABLE;
when IS_DETACHED_ENTRY_AVAILABLE =>
if (DOA(24) = '1' and DOA(26) = '1') then
-- Thread is detached, return 1
bus_data_out_next <= Z32(0 to 29) & "10"; -- The 0 in the last bit indicates no error
else
-- Thread is not detached, or not used, return 0
bus_data_out_next <= Z32;
end if;
next_state <= END_TRANSACTION;
when IS_QUEUED_INIT =>
tm2sch_opcode_next <= OPCODE_IS_QUEUED;
tm2sch_request_next <= '1';
tm2sch_data_next <= Bus2IP_Addr(22 to 29); -- thread ID
next_state <= ISQUEUED_WAIT_ACK;
return_state_next <= IS_QUEUED_DONE;
when IS_QUEUED_DONE =>
bus_data_out_next <= Z32(0 to 22) & sch2tm_data & '0';
next_state <= END_TRANSACTION;
when NEXT_THREAD_INIT =>
-- Return to the caller the value of the next thread to run
if sch2tm_next_id_valid = '1' then
-- the next thread has been identified,
-- read from Scheduler and check thread status
-- as stored by SWTM for consistency
ADDRA <= '0' & sch2tm_next_id;
ENA <= '1';
next_state <= NEXT_THREAD_RD_WAIT;
else
next_state <= NEXT_THREAD_WAIT4_SCHEDULER;
end if;
when NEXT_THREAD_WAIT4_SCHEDULER =>
if (sch2tm_next_id_valid = '1') then
-- Scheduler has made a scheduling decision
ADDRA <= '0' & sch2tm_next_id;
ENA <= '1';
next_state <= NEXT_THREAD_RD_WAIT;
elsif (timeout_expired = '1') then
-- Timed out waiting for scheduler
Exception_Cause_next <= EXCEPTION_TO_SCHD_NEXT_THREAD;
next_state <= RAISE_EXCEPTION; -- timeout
else
-- Continue waiting for scheduler
next_state <= current_state;
end if;
when NEXT_THREAD_RD_WAIT =>
next_state <= NEXT_THREAD_AVAILABLE;
when NEXT_THREAD_AVAILABLE =>
if DOA(26 to 27) = "11" then
-- thread status is used and not exited
-- dequeue the next_thread_id from the scheduler's queue
current_cpu_thread_next <= sch2tm_next_id & '0';
-- Send dequeue opperation to scheduler
tm2sch_opcode_next <= OPCODE_DEQUEUE;
tm2sch_request_next <= '1';
tm2sch_data_next <= Z32(0 to 7);
next_state <= DEQUEUE_WAIT_ACK;
return_state_next <= NEXT_THREAD_CHECK_DEQUEUE;
else
-- TM and SCHEDULER disagree if thread was used and not exited
-- return thread ID, set error bit and raise exception
bus_data_out_next <= Z32(0 to 22) & sch2tm_next_id & '1';
Exception_Cause_next <= EXCEPTION_SCHD_INVALID_THREAD;
next_state <= RAISE_EXCEPTION; -- timeout
end if;
when NEXT_THREAD_CHECK_DEQUEUE =>
-- Perform a check to make sure scheduler completed successfully
if sch2tm_data(7) = '1' then
-- error during enqueue
bus_data_out_next <= Z32(0 to 27) & ERROR_FROM_SCHEDULER;
next_state <= END_TRANSACTION;
else
-- enqueue completed correctly
-- return the value of the next thread id (which by now is in the current_cpu_thread register)
bus_data_out_next <= Z32(0 to 22) & current_cpu_thread(0 to 7) & '0';
next_state <= END_TRANSACTION;
end if;
when ADD_THREAD_INIT =>
-- if the thread is !used or exited return error
-- call scheduler to check queued status
-- if queued return error
-- call scheduler to enqueue thread ID
ADDRA <= '0' & Bus2IP_Addr(22 to 29); -- encoded thread ID
ENA <= '1';
next_state <= AT_ENTRY_RD_WAIT;
when AT_ENTRY_RD_WAIT =>
next_state <= AT_ENTRY_AVAILABLE;
when AT_ENTRY_AVAILABLE =>
-- check to see if the thread is used and !exited
if (DOA(26 to 27) = "11") then
-- thread is used and not exited
-- call scheduler isQueued
tm2sch_request_next <= '1';
tm2sch_data_next <= Bus2IP_Addr(22 to 29);
tm2sch_opcode_next <= OPCODE_IS_QUEUED;
next_state <= ISQUEUED_WAIT_ACK;
return_state_next <= AT_CHECK_ISQUEUE;
else
-- thread is unused or exited (or both)
-- operation failed, return error code
bus_data_out_next <= DOA(0 to 27) & ERROR_IN_STATUS;
next_state <= END_TRANSACTION;
end if;
when AT_CHECK_ISQUEUE =>
-- Check to see if the thread is queued
if sch2tm_data(7) = '0' then
-- Thread is not queued, call scheduler's enqueue
tm2sch_request_next <= '1';
tm2sch_data_next <= Bus2IP_Addr(22 to 29);
tm2sch_opcode_next <= OPCODE_ENQUEUE;
next_state <= ENQUEUE_WAIT_ACK;
return_state_next <= AT_CHECK_ENQUEUE;
else
-- Thread is queued, return error
bus_data_out_next <= DOA(0 to 7) & sch2tm_data & DOA(16 to 27) & THREAD_ALREADY_QUEUED;
next_state <= END_TRANSACTION;
end if;
when AT_CHECK_ENQUEUE =>
-- Check to make sure the scheduler added the thread correctly
if sch2tm_data(7) = '1' then
-- error during enqueue
bus_data_out_next <= Z32(0 to 7) & sch2tm_data & Z32(16 to 27) & ERROR_FROM_SCHEDULER;
next_state <= END_TRANSACTION;
else
-- enqueue completed correctly
bus_data_out_next <= Z32(0 to 7) & sch2tm_data & Z32(16 to 31);
next_state <= END_TRANSACTION;
end if;
when ISQUEUED_WAIT_ACK =>
-- wait for the scheduler to acknowledge the isqueued request
if sch2tm_busy = '0' then
-- scheduler has not yet responded to request
next_state <= current_state;
elsif (timeout_expired = '1') then
-- timed out waiting for scheduler
Exception_Cause_next <= EXCEPTION_TO_SCHD_ISQUEUED;
next_state <= RAISE_EXCEPTION;
else
-- scheduler acknowledged request, lower request line
tm2sch_request_next <= '0';
tm2sch_data_next <= Z32(0 to 7);
tm2sch_opcode_next <= OPCODE_NOOP;
next_state <= ISQUEUED_WAIT_COMPLETE;
end if;
when ISQUEUED_WAIT_COMPLETE =>
-- wait for the scheduler to complete the isqueued request
if sch2tm_busy = '1' then
-- scheduler has not yet completed request
next_state <= current_state;
elsif (timeout_expired = '1') then
-- timed out waiting for scheduler
Exception_Cause_next <= EXCEPTION_TO_SCHD_ISQUEUED;
next_state <= RAISE_EXCEPTION;
else
-- scheduler finished request, and (should) have data on data_return line
tm2sch_data_next <= Z32(0 to 7);
tm2sch_opcode_next <= OPCODE_NOOP;
next_state <= return_state;
end if;
when ENQUEUE_WAIT_ACK =>
-- Wait for the scheduler to acknowledge the enqueue request
if sch2tm_busy = '0' then
-- Scheduler has not yet responded
next_state <= current_state;
elsif (timeout_expired = '1') then
-- Timed out waiting for queue
Exception_Cause_next <= EXCEPTION_TO_SCHD_ENQUEUE;
next_state <= RAISE_EXCEPTION;
else
-- Scheduler has acknowledged the request
tm2sch_request_next <= '0';
tm2sch_data_next <= Z32(0 to 7);
tm2sch_opcode_next <= OPCODE_NOOP;
next_state <= ENQUEUE_WAIT_COMPLETE;
end if;
when ENQUEUE_WAIT_COMPLETE =>
-- wait for the scheduler to complete the enqueue request
if sch2tm_busy = '1' then
-- scheduler has notyet completed request
elsif (timeout_expired = '1') then
-- Timed out waiting for queue
Exception_Cause_next <= EXCEPTION_TO_SCHD_ENQUEUE;
next_state <= RAISE_EXCEPTION;
else
-- Scheduler has completed the request
tm2sch_data_next <= Z32(0 to 7);
tm2sch_opcode_next <= OPCODE_NOOP;
next_state <= return_state;
end if;
when DEQUEUE_WAIT_ACK =>
-- Wait for the scheduler to acknowledge the dequeue request
if sch2tm_busy = '0' then
-- Scheduler has not yet responded
next_state <= current_state;
elsif (timeout_expired = '1') then
-- Timed out waiting for queue
Exception_Cause_next <= EXCEPTION_TO_SCHD_DEQUEUE;
next_state <= RAISE_EXCEPTION;
else
-- Scheduler has acknowledged the request
tm2sch_request_next <= '0';
tm2sch_data_next <= Z32(0 to 7);
tm2sch_opcode_next <= OPCODE_NOOP;
next_state <= DEQUEUE_WAIT_COMPLETE;
end if;
when DEQUEUE_WAIT_COMPLETE =>
-- wait for the scheduler to complete the dequeue request
if sch2tm_busy = '1' then
-- scheduler has not yet completed request
elsif (timeout_expired = '1') then
-- Timed out waiting for queue
Exception_Cause_next <= EXCEPTION_TO_SCHD_DEQUEUE;
next_state <= RAISE_EXCEPTION;
else
-- Scheduler has completed the request
tm2sch_data_next <= Z32(0 to 7);
tm2sch_opcode_next <= OPCODE_NOOP;
next_state <= return_state;
end if;
when IS_QUEUE_EMPTY_WAIT_ACK =>
-- Wait for the scheduler to acknowledge the is queue empty request
if sch2tm_busy = '0' then
-- Scheduler has not yet responded
next_state <= current_state;
elsif (timeout_expired = '1') then
-- Timed out waiting for queue
Exception_Cause_next <= EXCEPTION_TO_SCHD_ISEMPTY;
next_state <= RAISE_EXCEPTION;
else
-- Scheduler has acknowledged the request
tm2sch_request_next <= '0';
tm2sch_data_next <= Z32(0 to 7);
tm2sch_opcode_next <= OPCODE_NOOP;
next_state <= IS_QUEUE_EMPTY_WAIT_COMPLETE;
end if;
when IS_QUEUE_EMPTY_WAIT_COMPLETE =>
-- wait for the scheduler to complete the is queue empty request
if sch2tm_busy = '1' then
-- scheduler has not yet completed request
elsif (timeout_expired = '1') then
-- Timed out waiting for queue
Exception_Cause_next <= EXCEPTION_TO_SCHD_ISEMPTY;
next_state <= RAISE_EXCEPTION;
else
-- Scheduler has completed the request
tm2sch_data_next <= Z32(0 to 7);
tm2sch_opcode_next <= OPCODE_NOOP;
next_state <= return_state;
end if;
when YIELD_THREAD_INIT =>
-- Retrieve the status of the current cpu thread
ADDRA <= '0' & current_cpu_thread(0 to 7);
ENA <= '1';
next_state <= YIELD_CURRENT_THREAD_RD_WAIT;
when YIELD_CURRENT_THREAD_RD_WAIT =>
next_state <= YIELD_CURRENT_THREAD_AVAILABLE;
when YIELD_CURRENT_THREAD_AVAILABLE =>
-- check to see if thread's status is used,~exited,~queued
if (DOA(26 to 27) = "11") then
-- check to see if the scheduler's queue is empty
tm2sch_request_next <= '1';
tm2sch_opcode_next <= OPCODE_IS_EMPTY;
tm2sch_data_next <= Z32(0 to 7);
next_state <= IS_QUEUE_EMPTY_WAIT_ACK;
return_state_next <= YIELD_CHECK_QUEUE_EMPTY;
else
-- operation failed, return error code
bus_data_out_next <= DOA(0 to 27) & ERROR_IN_STATUS;
next_state <= END_TRANSACTION;
end if;
when YIELD_CHECK_QUEUE_EMPTY =>
if (sch2tm_data(7) = '1') then
-- Queue is empty, return the current thread id
bus_data_out_next <= Z32(0 to 22) & current_cpu_thread;
next_state <= END_TRANSACTION;
else
-- Queue is not empty, add currently running thread to Q and then follow with a DEQ
next_state <= YIELD_ENQUEUE;
end if;
when YIELD_ENQUEUE =>
tm2sch_request_next <= '1';
tm2sch_opcode_next <= OPCODE_ENQUEUE;
tm2sch_data_next <= current_cpu_thread(0 to 7);
next_state <= ENQUEUE_WAIT_ACK;
return_state_next <= YIELD_CHECK_ENQUEUE;
when YIELD_CHECK_ENQUEUE =>
if (sch2tm_data(7) = '0') then
-- ENQ was successful, now DEQ to get next scheduling decision
current_cpu_thread_next <= sch2tm_next_id & '0'; -- update the currently running thread to the one that is scheduled to run next (AKA to be DEQ'd)
-- next_state <= YIELD_dummy_is_queued;
next_state <= YIELD_DEQUEUE;
else
-- ENQ failed, return error to caller
bus_data_out_next <= Z32(0 to 27) & ERROR_FROM_SCHEDULER;
next_state <= END_TRANSACTION;
end if;
-- when YIELD_dummy_is_queued =>
-- tm2sch_request_next <= '1'; -- request the dummy is_queued operation
-- tm2sch_opcode_next <= OPCODE_IS_QUEUED;
-- tm2sch_data_next <= "11111111";
-- next_state <= ISQUEUED_WAIT_ACK;
-- return_state_next <= YIELD_DEQUEUE;
when YIELD_DEQUEUE =>
tm2sch_request_next <= '1'; -- request the DEQ operation to remove the thread to run from Q
tm2sch_opcode_next <= OPCODE_DEQUEUE;
tm2sch_data_next <= Z32(0 to 7);
next_state <= DEQUEUE_WAIT_ACK;
return_state_next <= YIELD_CHECK_DEQUEUE;
when YIELD_CHECK_DEQUEUE =>
if (sch2tm_data(7) = '1') then
-- error during DEQ...
bus_data_out_next <= Z32(0 to 27) & ERROR_FROM_SCHEDULER;
next_state <= END_TRANSACTION;
else
-- DEQ completed successfully, end operation
bus_data_out_next <= Z32(0 to 22) & current_cpu_thread(0 to 7) & '0'; -- setup the return value of the next thread to run (now in the currently running thread)
next_state <= END_TRANSACTION;
end if;
when EXIT_THREAD_INIT =>
bus_data_out_next <= Z32; -- change if failure occurs
ADDRA <= '0' & Bus2IP_Addr(22 to 29);
ENA <= '1';
next_state <= EXIT_THREAD_RD_WAIT;
when EXIT_THREAD_RD_WAIT =>
next_state <= EXIT_THREAD_AVAIABLE;
when EXIT_THREAD_AVAIABLE =>
-- full entry for the current_thread is required in later states
current_status_next <= DOA(0 to 31);
ADDRA <= '0' & Bus2IP_Addr(22 to 29);
ENA <= '1';
WEA <= '1';
if (DOA(24) = '1') then
-- Thread is detached
-- Make the thread status used and exited.
DIA <= DOA(0 to 25) & "10" & DOA(28 to 31);
next_state <= END_TRANSACTION;
elsif (DOA(25) = '1') then
-- Thread is joined
-- Make the thread status used and exited, and wake the parent
DIA <= DOA(0 to 25) & "10" & DOA(28 to 31);
next_state <= EXIT_READ_PARENT;
else
-- Thread is not detached and still joinable
-- Set the thread status to used and exited
DIA <= DOA(0 to 25) & "10" & DOA(28 to 31);
next_state <= END_TRANSACTION;
end if;
when EXIT_READ_PARENT =>
-- The thread that is exiting was joined, wake the parent up
ADDRA <= '0' & current_status(16 to 23);
ENA <= '1';
next_state <= EXIT_READ_PARENT_WAIT;
when EXIT_READ_PARENT_WAIT =>
next_state <= EXIT_READ_PARENT_AVAILABLE;
when EXIT_READ_PARENT_AVAILABLE =>
-- Make sure the parent thread is used and not exited
if (DOA(26 to 27) = "11") then
-- Parent thread is used and not exited.
-- Add the parent thread tothe scheduler's queue
tm2sch_opcode_next <= OPCODE_ENQUEUE;
tm2sch_request_next <= '1';
tm2sch_data_next <= current_status(16 to 23);
return_state_next <= EXIT_CHECK_ENQUEUE;
next_state <= ENQUEUE_WAIT_ACK;
else
-- Parent thread is either unused or exited, neither of which it should be
-- operation failed, return error code
bus_data_out_next <= DOA(0 to 27) & ERROR_IN_STATUS;
next_state <= END_TRANSACTION;
end if;
when EXIT_CHECK_ENQUEUE =>
-- Check to make sure the scheduler added the thread correctly
if sch2tm_data(7) = '1' then
-- error during enqueue
bus_data_out_next <= Z32(0 to 27) & ERROR_FROM_SCHEDULER;
next_state <= END_TRANSACTION;
else
-- enqueue completed correctly
bus_data_out_next <= Z32(0 to 31);
next_state <= END_TRANSACTION;
end if;
when RAISE_EXCEPTION =>
-- NOTE !!! You must assign Exception_Cause
-- where-ever you assign next_state <= RAISE_EXCEPTION;
Exception_Address_next <= Bus2IP_Addr(0 to 31); -- save address
access_error <= '1'; -- assert interrupt
my_ack <= '1'; -- done, "ack" the bus
next_state <= END_TRANSACTION_WAIT;
when END_TRANSACTION =>
IP2Bus_Data <= bus_data_out;
my_ack <= '1'; -- done, "ack" the bus
next_state <= END_TRANSACTION_WAIT;
when END_TRANSACTION_WAIT =>
if( Bus2IP_RdCE(0)='0' and Bus2IP_WrCE(0)='0' ) then
next_state <= IDLE_STATE;
else
next_state <= current_state;
end if;
when others =>
Exception_Cause_next <= EXCEPTION_ILLEGAL_STATE;
next_state <= RAISE_EXCEPTION;
end case; -- case current_state
end process SWTM_LOGIC_PROC;
-------------------------------------------------------------------
-- ICON core instance
-------------------------------------------------------------------
-- -- simulation translate_off
-- i_icon : chipscope_icon_v1_03_a
-- port map
-- (
-- control0 => control0
-- );
-- -- simulation translate_on
--
-- COUNTER_PROC : process (Bus2IP_Clk) is
-- begin
-- if( Bus2IP_Clk'event and Bus2IP_Clk='1' ) then
-- if (Bus2IP_Reset = '1') then
-- my_counter <= (others => '0');
-- else
-- my_counter <= my_counter + 1;
-- end if;
-- end if;
-- end process COUNTER_PROC;
--
-- --
--
-- -------------------------------------------------------------------
-- -- ILA core instance
-- -------------------------------------------------------------------
--
-- -- simulation translate_off
-- i_ila : chipscope_ila_v1_02_a
-- port map
-- (
-- control => control0,
-- clk => Bus2IP_Clk,
-- trig0(63 downto 32) => Bus2IP_Data,
-- trig0(31 downto 0) => my_counter, -- 64 bits -- Add in chipscope signals and run on board!!!!
-- trig1(63 downto 32) => Bus2IP_Addr,
-- trig1(31 downto 0) => bus_data_out, -- 64 bits
-- trig2 => current_status, -- 32 bits
-- trig3 => Bus2IP_Addr, -- 32 bits
-- trig4(0) => Bus2IP_RdCE, -- 16 bits
-- trig4(1) => Bus2IP_WrCE,
-- trig4(2) => my_ack,
-- trig4(3) => my_tout_sup,
-- trig4(4) => Bus2IP_Reset,
-- trig4(5) => '0',
-- trig4(6) => tm2sch_request_reg,
-- trig4(7) => next_ID(0),
-- trig4(8) => next_ID(1),
-- trig4(9) => next_ID(2),
-- trig4(10) => next_ID(3),
-- trig4(11) => next_ID(4),
-- trig4(12) => next_ID(5),
-- trig4(13) => next_ID(6),
-- trig4(14) => next_ID(7),
-- trig4(15) => next_ID(8)
-- );
-- -- simulation translate_on
--
end IMP;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2011 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file afifo_32_v6.vhd when simulating
-- the core, afifo_32_v6. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY afifo_32_v6 IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END afifo_32_v6;
ARCHITECTURE afifo_32_v6_a OF afifo_32_v6 IS
-- synthesis translate_off
COMPONENT wrapped_afifo_32_v6
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_afifo_32_v6 USE ENTITY XilinxCoreLib.fifo_generator_v8_2(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 0,
c_count_type => 0,
c_data_count_width => 4,
c_default_value => "BlankString",
c_din_width => 32,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "0",
c_dout_width => 32,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "virtex6",
c_full_flags_rst_val => 1,
c_has_almost_empty => 0,
c_has_almost_full => 0,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 0,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 0,
c_has_rd_rst => 0,
c_has_rst => 1,
c_has_slave_ce => 0,
c_has_srst => 0,
c_has_underflow => 0,
c_has_valid => 0,
c_has_wr_ack => 0,
c_has_wr_data_count => 0,
c_has_wr_rst => 0,
c_implementation_type => 2,
c_implementation_type_axis => 1,
c_implementation_type_rach => 1,
c_implementation_type_rdch => 1,
c_implementation_type_wach => 1,
c_implementation_type_wdch => 1,
c_implementation_type_wrch => 1,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 2,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 1,
c_preload_regs => 0,
c_prim_fifo_type => "512x36",
c_prog_empty_thresh_assert_val => 2,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 3,
c_prog_empty_type => 0,
c_prog_empty_type_axis => 5,
c_prog_empty_type_rach => 5,
c_prog_empty_type_rdch => 5,
c_prog_empty_type_wach => 5,
c_prog_empty_type_wdch => 5,
c_prog_empty_type_wrch => 5,
c_prog_full_thresh_assert_val => 13,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 12,
c_prog_full_type => 0,
c_prog_full_type_axis => 5,
c_prog_full_type_rach => 5,
c_prog_full_type_rdch => 5,
c_prog_full_type_wach => 5,
c_prog_full_type_wdch => 5,
c_prog_full_type_wrch => 5,
c_rach_type => 0,
c_rd_data_count_width => 4,
c_rd_depth => 16,
c_rd_freq => 1,
c_rd_pntr_width => 4,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 1,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 0,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 4,
c_wr_depth => 16,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 4,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_afifo_32_v6
PORT MAP (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty
);
-- synthesis translate_on
END afifo_32_v6_a;
|
-- NEED RESULT: ARCH00278: Block Statement with label on end of stm passed
-- NEED RESULT: ARCH00278: Block Statement with no label on end of stm passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00278
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.1 (1)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00278)
-- ENT00278_Test_Bench(ARCH00278_Test_Bench)
--
-- REVISION HISTORY:
--
-- 21-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00278 of E00000 is
signal S : boolean := true ;
begin
B1 :
block
begin
P1 :
process ( S )
begin
test_report ( "ARCH00278" ,
"Block Statement with label on end of stm" ,
True ) ;
end process P1 ;
end block B1 ;
B2 :
block
signal S : boolean := true ;
begin
P1 :
process ( S )
begin
test_report ( "ARCH00278" ,
"Block Statement with no label on end of stm" ,
True ) ;
end process P1 ;
end block ;
end ARCH00278 ;
entity ENT00278_Test_Bench is
end ENT00278_Test_Bench ;
architecture ARCH00278_Test_Bench of ENT00278_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00278 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00278_Test_Bench ;
|
library ieee;
use ieee.std_logic_1164.all;
package wr_fabric_pkg is
constant c_WRF_DATA : std_logic_vector(1 downto 0) := "00";
constant c_WRF_OOB : std_logic_vector(1 downto 0) := "01";
constant c_WRF_STATUS : std_logic_vector(1 downto 0) := "10";
constant c_WRF_USER : std_logic_vector(1 downto 0) := "11";
constant c_WRF_OOB_TYPE_RX : std_logic_vector(3 downto 0) := "0000";
constant c_WRF_OOB_TYPE_TX : std_logic_vector(3 downto 0) := "0001";
type t_wrf_status_reg is record
is_hp : std_logic;
has_smac : std_logic;
has_crc : std_logic;
error : std_logic;
tag_me : std_logic;
match_class : std_logic_vector(7 downto 0);
end record;
type t_wrf_source_out is record
adr : std_logic_vector(1 downto 0);
dat : std_logic_vector(15 downto 0);
cyc : std_logic;
stb : std_logic;
we : std_logic;
sel : std_logic_vector(1 downto 0);
end record;
type t_wrf_source_in is record
ack : std_logic;
stall : std_logic;
err : std_logic;
rty : std_logic;
end record;
type t_wrf_oob is record
valid: std_logic;
oob_type : std_logic_vector(3 downto 0);
ts_r : std_logic_vector(27 downto 0);
ts_f : std_logic_vector(3 downto 0);
frame_id : std_logic_vector(15 downto 0);
port_id : std_logic_vector(5 downto 0);
end record;
subtype t_wrf_sink_in is t_wrf_source_out;
subtype t_wrf_sink_out is t_wrf_source_in;
type t_wrf_source_in_array is array (natural range <>) of t_wrf_source_in;
type t_wrf_source_out_array is array (natural range <>) of t_wrf_source_out;
subtype t_wrf_sink_in_array is t_wrf_source_out_array;
subtype t_wrf_sink_out_array is t_wrf_source_in_array;
function f_marshall_wrf_status (stat : t_wrf_status_reg) return std_logic_vector;
function f_unmarshall_wrf_status(stat : std_logic_vector) return t_wrf_status_reg;
constant c_dummy_src_in : t_wrf_source_in :=
('0', '0', '0', '0');
constant c_dummy_snk_in : t_wrf_sink_in :=
("XX", "XXXXXXXXXXXXXXXX", '0', '0', '0', "XX");
end wr_fabric_pkg;
package body wr_fabric_pkg is
function f_marshall_wrf_status(stat : t_wrf_status_reg)
return std_logic_vector is
variable tmp : std_logic_vector(15 downto 0);
begin
tmp(0) := stat.is_hp;
tmp(1) := stat.error;
tmp(2) := stat.has_smac;
tmp(3) := stat.has_crc;
tmp(15 downto 8) := stat.match_class;
return tmp;
end function;
function f_unmarshall_wrf_status(stat : std_logic_vector) return t_wrf_status_reg is
variable tmp : t_wrf_status_reg;
begin
tmp.is_hp := stat(0);
tmp.error := stat(1);
tmp.has_smac := stat(2);
tmp.has_crc := stat(3);
tmp.match_class := stat(15 downto 8);
return tmp;
end function;
end wr_fabric_pkg;
|
-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: RAM.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY RAM IS
PORT
(
address : IN STD_LOGIC_VECTOR (14 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
END RAM;
ARCHITECTURE SYN OF ram IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0);
BEGIN
q <= sub_wire0(15 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "BYPASS",
clock_enable_output_a => "BYPASS",
init_file => "cpuram.mif",
intended_device_family => "Cyclone II",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
lpm_type => "altsyncram",
numwords_a => 32768,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "CLOCK0",
power_up_uninitialized => "FALSE",
widthad_a => 15,
width_a => 16,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
data_a => data,
wren_a => wren,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "0"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "cpuram.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32768"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "15"
-- Retrieval info: PRIVATE: WidthData NUMERIC "16"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INIT_FILE STRING "cpuram.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32768"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "15"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 15 0 INPUT NODEFVAL "address[14..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
-- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-- Retrieval info: CONNECT: @address_a 0 0 15 0 address 0 0 15 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
library IEEE;
use IEEE.Std_Logic_1164.all;
entity contador_pontos is
port (compara, user, cont_match, clock, reset: in std_logic;
ledred, ledgrn: out std_logic_vector(7 downto 0)
);
end contador_pontos;
architecture behv of contador_pontos is
signal tempLedRed, tempLedGrn: std_logic_vector(7 downto 0);
begin
process(clock, reset)
begin
if (reset = '0') then
-- reset assincrono
tempLedRed <= "00000000";
tempLedGrn <= "00000000";
elsif rising_edge(clock) and (cont_match = '1') and (compara = '1') then
-- se o match e o enable do comparador estiverem em 1, desloca os pontos do jogador para a esquerda e adiciona um ponto no final
if user = '0' then
tempLedRed(7 downto 1) <= tempLedRed(6 downto 0);
tempLedRed(0) <= '1';
else
tempLedGrn(7 downto 1) <= tempLedGrn(6 downto 0);
tempLedGrn(0) <= '1';
end if;
end if;
ledred <= tempLedRed;
ledgrn <= tempLedGrn;
end process;
end behv; |
library verilog;
use verilog.vl_types.all;
entity usb_system_cpu_register_bank_b_module is
generic(
lpm_file : string := "UNUSED"
);
port(
clock : in vl_logic;
data : in vl_logic_vector(31 downto 0);
rdaddress : in vl_logic_vector(4 downto 0);
wraddress : in vl_logic_vector(4 downto 0);
wren : in vl_logic;
q : out vl_logic_vector(31 downto 0)
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of lpm_file : constant is 1;
end usb_system_cpu_register_bank_b_module;
|
-------------------------------------------------------------------------------
-- axi_vdma_mm2s_linebuf
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_mm2s_linebuf.vhd
-- Description: This entity encompases the mm2s line buffer logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library lib_cdc_v1_0_2;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_vdma_mm2s_linebuf is
generic (
C_DATA_WIDTH : integer range 8 to 1024 := 32;
C_M_AXIS_MM2S_TDATA_WIDTH : integer range 8 to 1024 := 32;
-- Line Buffer Data Width
C_INCLUDE_S2MM : integer range 0 to 1 := 0;
C_INCLUDE_MM2S_SF : integer range 0 to 1 := 0;
-- Include or exclude MM2S Store And Forward Functionality
-- 0 = Exclude MM2S Store and Forward
-- 1 = Include MM2S Store and Forward
C_INCLUDE_MM2S_DRE : integer range 0 to 1 := 0;
C_MM2S_SOF_ENABLE : integer range 0 to 1 := 0;
-- Enable/Disable start of frame generation on tuser(0). This
-- is only valid for external frame sync (C_USE_FSYNC = 1)
-- 0 = disable SOF
-- 1 = enable SOF
C_M_AXIS_MM2S_TUSER_BITS : integer range 1 to 1 := 1;
-- Master AXI Stream User Width for MM2S Channel
C_TOPLVL_LINEBUFFER_DEPTH : integer range 0 to 65536 := 512; -- CR625142
-- Depth as set by user at top level parameter
C_LINEBUFFER_DEPTH : integer range 0 to 65536 := 512;
-- Linebuffer depth in Bytes. Must be a power of 2
C_LINEBUFFER_AE_THRESH : integer range 1 to 65536 := 1;
-- Linebuffer almost empty threshold in Bytes. Must be a power of 2
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0 ;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
--C_ENABLE_DEBUG_INFO : string := "1111111111111111"; -- 1 to 16 --
--C_ENABLE_DEBUG_INFO : bit_vector(15 downto 0) := (others => '1'); --15 downto 0 --
C_ENABLE_DEBUG_ALL : integer range 0 to 1 := 1;
-- Setting this make core backward compatible to 2012.4 version in terms of ports and registers
C_ENABLE_DEBUG_INFO_0 : integer range 0 to 1 := 1;
-- Enable debug information bit 0
C_ENABLE_DEBUG_INFO_1 : integer range 0 to 1 := 1;
-- Enable debug information bit 1
C_ENABLE_DEBUG_INFO_2 : integer range 0 to 1 := 1;
-- Enable debug information bit 2
C_ENABLE_DEBUG_INFO_3 : integer range 0 to 1 := 1;
-- Enable debug information bit 3
C_ENABLE_DEBUG_INFO_4 : integer range 0 to 1 := 1;
-- Enable debug information bit 4
C_ENABLE_DEBUG_INFO_5 : integer range 0 to 1 := 1;
-- Enable debug information bit 5
C_ENABLE_DEBUG_INFO_6 : integer range 0 to 1 := 1;
-- Enable debug information bit 6
C_ENABLE_DEBUG_INFO_7 : integer range 0 to 1 := 1;
-- Enable debug information bit 7
C_ENABLE_DEBUG_INFO_8 : integer range 0 to 1 := 1;
-- Enable debug information bit 8
C_ENABLE_DEBUG_INFO_9 : integer range 0 to 1 := 1;
-- Enable debug information bit 9
C_ENABLE_DEBUG_INFO_10 : integer range 0 to 1 := 1;
-- Enable debug information bit 10
C_ENABLE_DEBUG_INFO_11 : integer range 0 to 1 := 1;
-- Enable debug information bit 11
C_ENABLE_DEBUG_INFO_12 : integer range 0 to 1 := 1;
-- Enable debug information bit 12
C_ENABLE_DEBUG_INFO_13 : integer range 0 to 1 := 1;
-- Enable debug information bit 13
C_ENABLE_DEBUG_INFO_14 : integer range 0 to 1 := 1;
-- Enable debug information bit 14
C_ENABLE_DEBUG_INFO_15 : integer range 0 to 1 := 1;
-- Enable debug information bit 15
ENABLE_FLUSH_ON_FSYNC : integer range 0 to 1 := 0 ;
C_FAMILY : string := "virtex7"
-- Device family used for proper BRAM selection
);
port (
-- MM2S AXIS Input Side (i.e. Datamover side)
s_axis_aclk : in std_logic ; --
s_axis_resetn : in std_logic ; --
--
-- MM2S AXIS Output Side --
m_axis_aclk : in std_logic ; --
m_axis_resetn : in std_logic ; --
mm2s_axis_linebuf_reset_out : out std_logic ; --
s2mm_axis_resetn : in std_logic := '1' ; --
s_axis_s2mm_aclk : in std_logic := '0' ; --
mm2s_fsync : in std_logic ; --
s2mm_fsync : in std_logic ; --
mm2s_fsync_core : out std_logic ; --
mm2s_fsize_mismatch_err_s : out std_logic ; --
mm2s_fsize_mismatch_err_m : out std_logic ; --
mm2s_vsize_cntr_clr_flag : out std_logic ; --
MM2S_DROP_RESIDUAL_OF_FSIZE_ERR_FRAME_S : out std_logic ; --
fsync_src_select : in std_logic_vector(1 downto 0) ; --
--
run_stop : in std_logic ; --
-- Graceful shut down control --
dm_halt : in std_logic ; --
dm_halt_reg_out : out std_logic ; --
cmdsts_idle : in std_logic ; --
stop : in std_logic ; -- CR623291
stop_reg_out : out std_logic ; -- CR623291
--
-- Vertical Line Count control --
fsync_out : in std_logic ; -- CR616211
fsync_out_m : out std_logic ; -- CR616211
mm2s_fsize_mismatch_err_flag: in std_logic ; -- CR616211
frame_sync : in std_logic ; -- CR616211
crnt_vsize : in std_logic_vector --
(VSIZE_DWIDTH-1 downto 0) ; -- CR616211
crnt_vsize_d2_out : out std_logic_vector --
(VSIZE_DWIDTH-1 downto 0) ; -- CR616211
--
linebuf_threshold : in std_logic_vector --
(LINEBUFFER_THRESH_WIDTH-1 downto 0); --
--
-- Stream In (Datamover To Line Buffer) --
s_axis_tdata : in std_logic_vector --
(C_DATA_WIDTH-1 downto 0) ; --
s_axis_tkeep : in std_logic_vector --
((C_DATA_WIDTH/8)-1 downto 0) ; --
s_axis_tlast : in std_logic ; --
s_axis_tvalid : in std_logic ; --
s_axis_tready : out std_logic ; --
--
--
-- Stream Out (Line Buffer To MM2S AXIS) --
m_axis_tdata : out std_logic_vector --
(C_DATA_WIDTH-1 downto 0) ; --
m_axis_tkeep : out std_logic_vector --
((C_DATA_WIDTH/8)-1 downto 0) ; --
m_axis_tlast : out std_logic ; --
m_axis_tvalid : out std_logic ; --
m_axis_tready : in std_logic ; --
m_axis_tuser : out std_logic_vector --
(C_M_AXIS_MM2S_TUSER_BITS-1 downto 0); --
--
-- Fifo Status Flags --
dwidth_fifo_pipe_empty : in std_logic ; --
dwidth_fifo_pipe_empty_m : out std_logic ; --
mm2s_fifo_pipe_empty : out std_logic ; --
mm2s_fifo_empty : out std_logic ; --
mm2s_fifo_almost_empty : out std_logic ; --
mm2s_all_lines_xfred_s_dwidth : in std_logic ; --
mm2s_all_lines_xfred_s : out std_logic ; --
mm2s_all_lines_xfred : out std_logic -- CR616211
);
end axi_vdma_mm2s_linebuf;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_mm2s_linebuf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Bufer depth
--constant BUFFER_DEPTH : integer := max2(128,C_LINEBUFFER_DEPTH/(C_DATA_WIDTH/8));
constant BUFFER_DEPTH : integer := C_LINEBUFFER_DEPTH;
-- Buffer width is data width + strobe width + 1 bit for tlast
-- Increase data width by 1 when tuser support included.
--constant BUFFER_WIDTH : integer := C_DATA_WIDTH + (C_DATA_WIDTH/8) + 1;
constant BUFFER_WIDTH : integer := C_DATA_WIDTH -- tdata
+ (C_DATA_WIDTH/8)*C_INCLUDE_MM2S_DRE -- tkeep
+ 1 -- tlast
+ (C_MM2S_SOF_ENABLE -- tuser
*C_M_AXIS_MM2S_TUSER_BITS);
-- Buffer data count width
constant DATACOUNT_WIDTH : integer := clog2(BUFFER_DEPTH);
constant DATA_COUNT_ZERO : std_logic_vector(DATACOUNT_WIDTH-1 downto 0)
:= (others => '0');
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
constant ZERO_VALUE_VECT : std_logic_vector(255 downto 0) := (others => '0');
-- Constants for line tracking logic
constant VSIZE_ONE_VALUE : std_logic_vector(VSIZE_DWIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(1,VSIZE_DWIDTH));
constant VSIZE_ZERO_VALUE : std_logic_vector(VSIZE_DWIDTH-1 downto 0)
:= (others => '0');
-- Linebuffer threshold support
constant THRESHOLD_LSB_INDEX : integer := clog2((C_DATA_WIDTH/8));
constant THRESHOLD_PAD : std_logic_vector(THRESHOLD_LSB_INDEX-1 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal fifo_din : std_logic_vector(BUFFER_WIDTH - 1 downto 0) := (others => '0');
signal fifo_dout : std_logic_vector(BUFFER_WIDTH - 1 downto 0) := (others => '0');
signal fifo_wren : std_logic := '0';
signal fifo_rden : std_logic := '0';
signal fifo_empty_i : std_logic := '0';
signal fifo_full_i : std_logic := '0';
signal fifo_ainit : std_logic := '0';
signal fifo_rdcount : std_logic_vector(DATACOUNT_WIDTH -1 downto 0) := (others => '0');
signal s_axis_tready_i : std_logic := '0'; -- CR619293
signal m_axis_tready_i : std_logic := '0';
signal m_axis_tvalid_i : std_logic := '0';
signal m_axis_tlast_i : std_logic := '0';
signal m_axis_tdata_i : std_logic_vector(C_DATA_WIDTH-1 downto 0):= (others => '0');
signal m_axis_tkeep_i : std_logic_vector((C_DATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_axis_tkeep_signal : std_logic_vector((C_DATA_WIDTH/8)-1 downto 0) := (others => '0');
signal s_axis_tkeep_signal : std_logic_vector((C_DATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_axis_tuser_i : std_logic_vector(C_M_AXIS_MM2S_TUSER_BITS - 1 downto 0) := (others => '0');
signal m_axis_tready_d1 : std_logic := '0';
signal m_axis_tlast_d1 : std_logic := '0';
signal m_axis_tvalid_d1 : std_logic := '0';
signal crnt_vsize_cdc_tig : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0'); -- CR575884
signal crnt_vsize_d1 : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0'); -- CR575884
signal crnt_vsize_d2 : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0'); -- CR575884
signal vsize_counter : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0'); -- CR575884
signal decr_vcount : std_logic := '0'; -- CR575884
signal all_lines_xfred : std_logic := '0'; -- CR616211
signal all_lines_xfred_no_dwidth : std_logic := '0'; -- CR616211
signal mm2s_all_lines_xfred_s_sig : std_logic := '0'; -- CR616211
signal m_axis_tvalid_out : std_logic := '0'; -- CR576993
signal m_axis_tlast_out : std_logic := '0'; -- CR616211
signal slv2skid_s_axis_tvalid : std_logic := '0'; -- CR576993
signal fifo_empty_d1 : std_logic := '0'; -- CR576993
-- FIFO Pipe empty signals
signal fifo_pipe_empty : std_logic := '0';
signal fifo_wren_d1 : std_logic := '0'; -- CR579191
signal pot_empty : std_logic := '0'; -- CR579191
signal fifo_almost_empty_i : std_logic := '1'; -- CR604273/CR604272
signal fifo_almost_empty_d1 : std_logic := '1';
signal fifo_almost_empty_fe : std_logic := '0'; -- CR604273/CR604272
signal fifo_almost_empty_reg : std_logic := '1';
signal data_count_ae_threshold_cdc_tig : std_logic_vector(DATACOUNT_WIDTH-1 downto 0) := (others => '0');
signal data_count_ae_threshold_d1 : std_logic_vector(DATACOUNT_WIDTH-1 downto 0) := (others => '0');
signal data_count_ae_threshold : std_logic_vector(DATACOUNT_WIDTH-1 downto 0) := (others => '0');
signal m_data_count_ae_thresh : std_logic_vector(DATACOUNT_WIDTH-1 downto 0) := (others => '0');
signal sf_threshold_met : std_logic := '0';
signal cmdsts_idle_d1 : std_logic := '0';
signal cmdsts_idle_fe : std_logic := '0';
signal stop_reg : std_logic := '0'; --CR623291
signal s_axis_fifo_ainit : std_logic := '0';
signal m_axis_fifo_ainit : std_logic := '0';
signal s_axis_fifo_ainit_nosync : std_logic := '0';
signal s_axis_fifo_ainit_nosync_reg : std_logic := '0';
signal m_axis_fifo_ainit_nosync : std_logic := '0';
signal dm_decr_vcount : std_logic := '0'; -- CR619293
signal dm_xfred_all_lines : std_logic := '0'; -- CR619293
signal dm_vsize_counter : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0'); -- CR619293
signal dm_xfred_all_lines_reg : std_logic := '0'; -- CR619293
signal sof_flag : std_logic := '0';
signal mm2s_fifo_pipe_empty_i : std_logic := '0';
signal frame_sync_d1 : std_logic := '0';
signal m_skid_reset : std_logic := '0';
signal dm_halt_reg : std_logic := '0';
signal mm2s_axis_linebuf_reset_out_inv : std_logic := '0' ; --
signal sof_reset : std_logic := '0';
signal wr_rst_busy_sig : std_logic := '0';
signal rd_rst_busy_sig : std_logic := '0';
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF crnt_vsize_cdc_tig : SIGNAL IS "true";
ATTRIBUTE async_reg OF crnt_vsize_d1 : SIGNAL IS "true";
ATTRIBUTE async_reg OF data_count_ae_threshold_cdc_tig : SIGNAL IS "true";
ATTRIBUTE async_reg OF data_count_ae_threshold_d1 : SIGNAL IS "true";
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
mm2s_fifo_pipe_empty <= mm2s_fifo_pipe_empty_i;
dm_halt_reg_out <= dm_halt_reg;
stop_reg_out <= stop_reg;
crnt_vsize_d2_out <= crnt_vsize_d2;
GEN_MM2S_DRE_ON : if C_INCLUDE_MM2S_DRE = 1 generate
begin
m_axis_tkeep <= m_axis_tkeep_signal;
s_axis_tkeep_signal <= s_axis_tkeep;
end generate GEN_MM2S_DRE_ON;
GEN_MM2S_DRE_OFF : if C_INCLUDE_MM2S_DRE = 0 generate
begin
m_axis_tkeep <= (others => '1');
s_axis_tkeep_signal <= (others => '1');
end generate GEN_MM2S_DRE_OFF;
GEN_LINEBUF_NO_SOF : if (ENABLE_FLUSH_ON_FSYNC = 0 or C_MM2S_SOF_ENABLE = 0) generate
begin
mm2s_fsync_core <= mm2s_fsync;
MM2S_DROP_RESIDUAL_OF_FSIZE_ERR_FRAME_S <= '0';
mm2s_fsize_mismatch_err_s <= '0';
--*****************************************************************************--
--** LINE BUFFER MODE (Sync or Async) **--
--*****************************************************************************--
GEN_LINEBUFFER : if C_LINEBUFFER_DEPTH /= 0 generate
begin
-- Divide by number bytes per data beat and add padding to dynamic
-- threshold setting
data_count_ae_threshold <= linebuf_threshold((DATACOUNT_WIDTH-1) + THRESHOLD_LSB_INDEX
downto THRESHOLD_LSB_INDEX);
-- Synchronous clock therefore instantiate an Asynchronous FIFO
GEN_SYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2_8.axi_vdma_sfifo
generic map(
UW_DATA_WIDTH => BUFFER_WIDTH ,
C_FULL_FLAGS_RST_VAL => 1 ,
UW_FIFO_DEPTH => BUFFER_DEPTH ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
rst => s_axis_fifo_ainit_nosync ,
sleep => '0' ,
wr_rst_busy => wr_rst_busy_sig ,
rd_rst_busy => rd_rst_busy_sig ,
clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i ,
data_count => fifo_rdcount
);
--wr_rst_busy_sig <= '0';
--rd_rst_busy_sig <= '0';
end generate GEN_SYNC_FIFO;
-- Asynchronous clock therefore instantiate an Asynchronous FIFO
GEN_ASYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
LB_BRAM : if ( (C_ENABLE_DEBUG_INFO_1 = 1 or C_ENABLE_DEBUG_ALL = 1) )
generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2_8.axi_vdma_afifo
generic map(
UW_DATA_WIDTH => BUFFER_WIDTH ,
C_FULL_FLAGS_RST_VAL => 1 ,
UW_FIFO_DEPTH => BUFFER_DEPTH ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
rst => s_axis_fifo_ainit_nosync_reg ,
sleep => '0' ,
wr_rst_busy => open ,
rd_rst_busy => open ,
wr_clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_clk => m_axis_aclk ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i ,
wr_data_count => open , --CR622702
rd_data_count => fifo_rdcount
);
wr_rst_busy_sig <= '0';
rd_rst_busy_sig <= '0';
end generate LB_BRAM;
LB_BUILT_IN : if ( (C_ENABLE_DEBUG_INFO_1 = 0 and C_ENABLE_DEBUG_ALL = 0) )
generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2_8.axi_vdma_afifo_builtin
generic map(
PL_FIFO_TYPE => "BUILT_IN" ,
PL_READ_MODE => "FWFT" ,
PL_FASTER_CLOCK => "WR_CLK" , --RD_CLK
PL_FULL_FLAGS_RST_VAL => 0 , -- ?
PL_DATA_WIDTH => BUFFER_WIDTH ,
C_FAMILY => C_FAMILY ,
PL_FIFO_DEPTH => BUFFER_DEPTH
)
port map(
-- Inputs
rst => s_axis_fifo_ainit_nosync_reg ,
sleep => '0' ,
wr_rst_busy => wr_rst_busy_sig ,
rd_rst_busy => rd_rst_busy_sig ,
wr_clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_clk => m_axis_aclk ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i
);
end generate LB_BUILT_IN;
end generate GEN_ASYNC_FIFO;
-- Generate an SOF on tuser(0). currently vdma only support 1 tuser bit that is set by
-- frame sync and driven out on first data beat of mm2s packet.
GEN_SOF : if ENABLE_FLUSH_ON_FSYNC = 0 and C_MM2S_SOF_ENABLE = 1 generate
--signal sof_reset : std_logic := '0';
begin
sof_reset <= '1' when (s_axis_resetn = '0')
or (dm_halt = '1')
else '0';
-- On frame sync set flag and then clear flag when
-- sof written to fifo.
SOF_FLAG_PROCESS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(sof_reset = '1' or fifo_wren = '1')then
sof_flag <= '0';
elsif(frame_sync = '1')then
sof_flag <= '1';
end if;
end if;
end process SOF_FLAG_PROCESS;
GEN_MM2S_DRE_ENABLED_TKEEP : if C_INCLUDE_MM2S_DRE = 1 generate
begin
-- AXI Slave Side of FIFO
fifo_din <= sof_flag & s_axis_tlast & s_axis_tkeep_signal & s_axis_tdata;
fifo_wren <= s_axis_tvalid and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
s_axis_tready <= s_axis_tready_i; -- CR619293
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready_i and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig and sf_threshold_met;
m_axis_tdata_i <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_i <= fifo_dout(BUFFER_WIDTH-3 downto (BUFFER_WIDTH-3) - (C_DATA_WIDTH/8) + 1);
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-2);
m_axis_tuser_i(0) <= fifo_dout(BUFFER_WIDTH-1);
end generate GEN_MM2S_DRE_ENABLED_TKEEP;
GEN_NO_MM2S_DRE_DISABLE_TKEEP : if C_INCLUDE_MM2S_DRE = 0 generate
begin
-- AXI Slave Side of FIFO
fifo_din <= sof_flag & s_axis_tlast & s_axis_tdata;
fifo_wren <= s_axis_tvalid and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
s_axis_tready <= s_axis_tready_i; -- CR619293
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready_i and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig and sf_threshold_met;
m_axis_tdata_i <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_i <= (others => '1');
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-2);
m_axis_tuser_i(0) <= fifo_dout(BUFFER_WIDTH-1);
end generate GEN_NO_MM2S_DRE_DISABLE_TKEEP;
end generate GEN_SOF;
-- SOF turned off therefore do not generate SOF on tuser
GEN_NO_SOF : if C_MM2S_SOF_ENABLE = 0 generate
begin
GEN_MM2S_DRE_ENABLED_TKEEP : if C_INCLUDE_MM2S_DRE = 1 generate
begin
sof_flag <= '0';
-- AXI Slave Side of FIFO
fifo_din <= s_axis_tlast & s_axis_tkeep_signal & s_axis_tdata;
fifo_wren <= s_axis_tvalid and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
s_axis_tready <= s_axis_tready_i; -- CR619293
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready_i and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig and sf_threshold_met;
m_axis_tdata_i <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_i <= fifo_dout(BUFFER_WIDTH-2 downto (BUFFER_WIDTH-2) - (C_DATA_WIDTH/8) + 1);
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-1);
m_axis_tuser_i <= (others => '0');
end generate GEN_MM2S_DRE_ENABLED_TKEEP;
GEN_NO_MM2S_DRE_DISABLE_TKEEP : if C_INCLUDE_MM2S_DRE = 0 generate
begin
sof_flag <= '0';
-- AXI Slave Side of FIFO
fifo_din <= s_axis_tlast & s_axis_tdata;
fifo_wren <= s_axis_tvalid and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
s_axis_tready <= s_axis_tready_i; -- CR619293
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready_i and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig and sf_threshold_met;
m_axis_tdata_i <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_i <= (others => '1');
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-1);
m_axis_tuser_i <= (others => '0');
end generate GEN_NO_MM2S_DRE_DISABLE_TKEEP;
end generate GEN_NO_SOF;
-- Top level line buffer depth not equal to zero therefore gererate threshold
-- flags. (CR625142)
GEN_THRESHOLD_ENABLED : if C_TOPLVL_LINEBUFFER_DEPTH /= 0 and (C_ENABLE_DEBUG_INFO_1 = 1 or C_ENABLE_DEBUG_ALL = 1) generate
begin
-- Almost empty flag (note: asserts when empty also)
REG_ALMST_EMPTY : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
fifo_almost_empty_reg <= '1';
--elsif(fifo_rdcount(DATACOUNT_WIDTH-1 downto 0) <= DATA_COUNT_AE_THRESHOLD or fifo_empty_i = '1')then
--elsif((fifo_rdcount(DATACOUNT_WIDTH-1 downto 0) <= m_data_count_ae_thresh
-- or fifo_empty_i = '1') and fifo_full_i = '0')then
elsif((fifo_rdcount(DATACOUNT_WIDTH-1 downto 0) <= m_data_count_ae_thresh
or (fifo_empty_i = '1' or rd_rst_busy_sig = '1')))then
fifo_almost_empty_reg <= '1';
else
fifo_almost_empty_reg <= '0';
end if;
end if;
end process REG_ALMST_EMPTY;
mm2s_fifo_almost_empty <= fifo_almost_empty_reg
or (not sf_threshold_met) -- CR622777
or (not m_axis_tvalid_out); -- CR625724
mm2s_fifo_empty <= not m_axis_tvalid_out;
end generate GEN_THRESHOLD_ENABLED;
-- Top level line buffer depth is zero therefore turn off threshold logic.
-- this occurs for async operation where the async fifo is needed for CDC (CR625142)
GEN_THRESHOLD_DISABLED : if C_TOPLVL_LINEBUFFER_DEPTH = 0 or (C_ENABLE_DEBUG_INFO_1 = 0 and C_ENABLE_DEBUG_ALL = 0) generate
begin
mm2s_fifo_empty <= '0';
mm2s_fifo_almost_empty <= '0';
fifo_almost_empty_reg <= '0';
end generate GEN_THRESHOLD_DISABLED;
-- CR#578903
-- FIFO, FIFO Pipe, and Skid Buffer are all empty. This is used to safely
-- assert reset on shutdown and also used to safely generate fsync in free-run mode
-- CR622702 - need to look at write side of fifo to prevent false empties due to async fifo
--fifo_pipe_empty <= '1' when (fifo_wrcount(DATACOUNT_WIDTH-1 downto 0) = DATA_COUNT_ZERO -- Data count is 0
-- and m_axis_tvalid_out = '0') -- Skid Buffer is done
-- -- Forced stop and Threshold not met (CR623291)
-- or (sf_threshold_met = '0' and stop_reg = '1')
-- else '0';
-- CR623879 fixed flase fifo_pipe_assertions due to extreme AXI4 throttling on
-- mm2s reads causing fifo to go empty for extended periods of time. This then
-- caused flase idles to be flagged and frame syncs were then generated in free run mode
-------- fifo_pipe_empty <= '1' when (all_lines_xfred = '1' and m_axis_tvalid_out = '0') -- All data for frame transmitted
-------- or (sf_threshold_met = '0' -- Or Threshold not met
-------- and stop_reg = '1' -- Commanded to stop
-------- and m_axis_tvalid_out = '0') -- And NOT driving tvalid
-------- else '0';
--------
-- If store and forward is turned on by user then gate tvalid with
-- threshold met
GEN_THRESH_MET_FOR_SNF : if C_INCLUDE_MM2S_SF = 1 and C_TOPLVL_LINEBUFFER_DEPTH /= 0 and (C_ENABLE_DEBUG_INFO_1 = 1 or C_ENABLE_DEBUG_ALL = 1) generate
begin
-- Register fifo_almost empty in order to generate
-- almost empty fall edge pulse
REG_ALMST_EMPTY_FE : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
fifo_almost_empty_d1 <= '1';
else
fifo_almost_empty_d1 <= fifo_almost_empty_reg;
end if;
end if;
end process REG_ALMST_EMPTY_FE;
-- Almost empty falling edge
fifo_almost_empty_fe <= not fifo_almost_empty_reg and fifo_almost_empty_d1;
-- Store and Forward threshold met
THRESH_MET : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
sf_threshold_met <= '0';
elsif(fsync_out = '1')then
sf_threshold_met <= '0';
-- Reached threshold or all reads done for the frame
elsif(fifo_almost_empty_fe = '1'
or (dm_xfred_all_lines_reg = '1'))then
sf_threshold_met <= '1';
end if;
end if;
end process THRESH_MET;
end generate GEN_THRESH_MET_FOR_SNF;
-- Store and forward off therefore do not need to meet threshold
GEN_NO_THRESH_MET_FOR_SNF : if C_INCLUDE_MM2S_SF = 0 or C_TOPLVL_LINEBUFFER_DEPTH = 0 or (C_ENABLE_DEBUG_INFO_1 = 0 and C_ENABLE_DEBUG_ALL = 0) generate
begin
sf_threshold_met <= '1';
end generate GEN_NO_THRESH_MET_FOR_SNF;
--*********************************************************--
--** MM2S MASTER SKID BUFFER **--
--*********************************************************--
I_MSTR_SKID : entity axi_vdma_v6_2_8.axi_vdma_skid_buf
generic map(
C_WDATA_WIDTH => C_DATA_WIDTH ,
C_TUSER_WIDTH => C_M_AXIS_MM2S_TUSER_BITS
)
port map(
-- System Ports
ACLK => m_axis_aclk ,
ARST => m_axis_fifo_ainit_nosync ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => '0' ,
-- Slave Side (Stream Data Input)
S_VALID => m_axis_tvalid_i ,
S_READY => m_axis_tready_i ,
S_Data => m_axis_tdata_i ,
S_STRB => m_axis_tkeep_i ,
S_Last => m_axis_tlast_i ,
S_User => m_axis_tuser_i ,
-- Master Side (Stream Data Output)
M_VALID => m_axis_tvalid_out ,
M_READY => m_axis_tready ,
M_Data => m_axis_tdata ,
M_STRB => m_axis_tkeep_signal ,
M_Last => m_axis_tlast_out ,
M_User => m_axis_tuser
);
-- Pass out of core
m_axis_tvalid <= m_axis_tvalid_out;
m_axis_tlast <= m_axis_tlast_out;
-- Register to break long timing paths for use in
-- transfer complete generation
REG_STRM_SIGS : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
m_axis_tlast_d1 <= '0';
m_axis_tvalid_d1 <= '0';
m_axis_tready_d1 <= '0';
else
m_axis_tlast_d1 <= m_axis_tlast_out;
m_axis_tvalid_d1 <= m_axis_tvalid_out;
m_axis_tready_d1 <= m_axis_tready;
end if;
end if;
end process REG_STRM_SIGS;
end generate GEN_LINEBUFFER;
--*****************************************************************************--
--** NO LINE BUFFER MODE (Sync Only) **--
--*****************************************************************************--
-- LineBuffer forced on if asynchronous mode is enabled
GEN_NO_LINEBUFFER : if (C_LINEBUFFER_DEPTH = 0) generate -- No Line Buffer
begin
-- Map Datamover to AXIS Master Out
m_axis_tdata <= s_axis_tdata;
m_axis_tkeep_signal <= s_axis_tkeep_signal;
m_axis_tvalid <= s_axis_tvalid;
m_axis_tlast <= s_axis_tlast;
s_axis_tready <= m_axis_tready;
-- Tie FIFO Flags off
mm2s_fifo_empty <= '0';
mm2s_fifo_almost_empty <= '0';
-- Generate sof on tuser(0)
GEN_SOF : if C_MM2S_SOF_ENABLE = 1 generate
begin
-- On frame sync set flag and then clear flag when
-- sof written to fifo.
SOF_FLAG_PROCESS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit = '1' or (s_axis_tvalid = '1' and m_axis_tready = '1'))then
sof_flag <= '0';
elsif(frame_sync = '1')then
sof_flag <= '1';
end if;
end if;
end process SOF_FLAG_PROCESS;
m_axis_tuser(0) <= sof_flag;
end generate GEN_SOF;
-- Do not generate sof on tuser(0)
GEN_NO_SOF : if C_MM2S_SOF_ENABLE = 0 generate
begin
sof_flag <= '0';
m_axis_tuser <= (others => '0');
end generate GEN_NO_SOF;
-- CR#578903
-- Register tvalid to break timing paths for use in
-- psuedo fifo empty for channel idle generation and
-- for xfer complete generation.
REG_STRM_SIGS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
m_axis_tvalid_d1 <= '0';
m_axis_tlast_d1 <= '0';
m_axis_tready_d1 <= '0';
else
m_axis_tvalid_d1 <= s_axis_tvalid;
m_axis_tlast_d1 <= s_axis_tlast;
m_axis_tready_d1 <= m_axis_tready;
end if;
end if;
end process REG_STRM_SIGS;
-- CR#578903
-- Psuedo FIFO, FIFO Pipe, and Skid Buffer are all empty. This is used to safely
-- assert reset on shutdown and also used to safely generate fsync in free-run mode
-- This flag is looked at at the end of frames.
-- Order of else-if is critical
-- CR579191 modified method to prevent double fsync assertions
REG_PIPE_EMPTY : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
fifo_pipe_empty <= '1';
-- Command/Status not idle indicates pending datamover commands
-- set psuedo fifo empty to NOT empty.
elsif(cmdsts_idle_fe = '1')then
fifo_pipe_empty <= '0';
-- On accepted tlast then clear psuedo empty flag back to being empty
elsif(pot_empty = '1' and cmdsts_idle = '1')then
fifo_pipe_empty <= '1';
end if;
end if;
end process REG_PIPE_EMPTY;
REG_IDLE_FE : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
cmdsts_idle_d1 <= '1';
else
cmdsts_idle_d1 <= cmdsts_idle;
end if;
end if;
end process REG_IDLE_FE;
-- CR579586 Use falling edge to set pfifo empty
cmdsts_idle_fe <= not cmdsts_idle and cmdsts_idle_d1;
-- CR579191
POTENTIAL_EMPTY_PROCESS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
pot_empty <= '1';
elsif(m_axis_tvalid_d1 = '1' and m_axis_tlast_d1 = '1' and m_axis_tready_d1 = '1')then
pot_empty <= '1';
elsif(m_axis_tvalid_d1 = '1' and m_axis_tlast_d1 = '0')then
pot_empty <= '0';
end if;
end if;
end process POTENTIAL_EMPTY_PROCESS;
end generate GEN_NO_LINEBUFFER;
--*****************************************************************************--
--** MM2S ASYNCH CLOCK SUPPORT **--
--*****************************************************************************--
-- Cross fifo pipe empty flag to secondary clock domain
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Pipe Empty and Shutdown reset CDC
---- SHUTDOWN_RST_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => fifo_pipe_empty ,
---- scndry_out => mm2s_fifo_pipe_empty_i ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
SHUTDOWN_RST_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => fifo_pipe_empty,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => mm2s_fifo_pipe_empty_i,
scndry_vect_out => open
);
-- Vertical Count and All Lines Transferred CDC (CR616211)
---- ALL_LINES_XFRED_P_S_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' , -- CR619293
---- prmry_out => open , -- CR619293
---- prmry_in => all_lines_xfred ,
---- scndry_out => mm2s_all_lines_xfred ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
----
ALL_LINES_XFRED_P_S_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => all_lines_xfred,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => mm2s_all_lines_xfred,
scndry_vect_out => open
);
-- Vertical Count and All Lines Transferred CDC (CR616211)
---- ALL_LINES_XFRED_S_P_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => dm_xfred_all_lines , -- CR619293
---- prmry_out => dm_xfred_all_lines_reg , -- CR619293
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
ALL_LINES_XFRED_S_P_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => dm_xfred_all_lines,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => dm_xfred_all_lines_reg,
scndry_vect_out => open
);
VSIZE_CNT_CROSSING : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
crnt_vsize_cdc_tig <= crnt_vsize;
crnt_vsize_d1 <= crnt_vsize_cdc_tig;
end if;
end process VSIZE_CNT_CROSSING;
crnt_vsize_d2 <= crnt_vsize_d1;
-- Cross stop signal (CR623291)
---- STOP_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => stop ,
---- prmry_out => stop_reg ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
STOP_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => stop,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => stop_reg,
scndry_vect_out => open
);
-- Cross datamover halt and threshold signals
---- HALT_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => dm_halt ,
---- prmry_out => dm_halt_reg ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- scndry_vect_out => open
---- );
----
HALT_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => dm_halt,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => dm_halt_reg,
scndry_vect_out => open
);
THRESH_CNT_CROSSING : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
data_count_ae_threshold_cdc_tig <= data_count_ae_threshold;
data_count_ae_threshold_d1 <= data_count_ae_threshold_cdc_tig;
end if;
end process THRESH_CNT_CROSSING;
m_data_count_ae_thresh <= data_count_ae_threshold_d1;
end generate GEN_FOR_ASYNC;
--*****************************************************************************--
--** MM2S SYNCH CLOCK SUPPORT **--
--*****************************************************************************--
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
mm2s_fifo_pipe_empty_i <= fifo_pipe_empty;
crnt_vsize_d2 <= crnt_vsize; -- CR616211
mm2s_all_lines_xfred <= all_lines_xfred; -- CR616211
dm_xfred_all_lines_reg <= dm_xfred_all_lines; -- CR619293
stop_reg <= stop; -- CR623291
dm_halt_reg <= dm_halt;
m_data_count_ae_thresh <= data_count_ae_threshold;
end generate GEN_FOR_SYNC;
--*****************************************************************************
--** Vertical Line Tracking (CR616211)
--*****************************************************************************
-- Decrement vertical count with each accept tlast
decr_vcount <= '1' when m_axis_tlast_d1 = '1'
and m_axis_tvalid_d1 = '1'
and m_axis_tready_d1 = '1'
else '0';
-- Drive ready at fsync out then de-assert once all lines have
-- been accepted.
VERT_COUNTER : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1' and fsync_out = '0')then
vsize_counter <= (others => '0');
all_lines_xfred <= '1';
elsif(fsync_out = '1')then
vsize_counter <= crnt_vsize_d2;
all_lines_xfred <= '0';
elsif(decr_vcount = '1' and vsize_counter = VSIZE_ONE_VALUE)then
vsize_counter <= (others => '0');
all_lines_xfred <= '1';
elsif(decr_vcount = '1' and vsize_counter /= VSIZE_ZERO_VALUE)then
vsize_counter <= std_logic_vector(unsigned(vsize_counter) - 1);
all_lines_xfred <= '0';
end if;
end if;
end process VERT_COUNTER;
-- Store and forward or no line buffer (CR619293)
GEN_VCOUNT_FOR_SNF : if C_LINEBUFFER_DEPTH /= 0 and C_INCLUDE_MM2S_SF = 1 generate
begin
dm_decr_vcount <= '1' when s_axis_tlast = '1'
and s_axis_tvalid = '1'
and s_axis_tready_i = '1'
else '0';
-- Delay 1 pipe to align with cnrt_vsize
REG_FSYNC_TO_ALIGN : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit = '1' and frame_sync = '0')then
frame_sync_d1 <= '0';
else
frame_sync_d1 <= frame_sync;
end if;
end if;
end process REG_FSYNC_TO_ALIGN;
-- Count lines to determine when datamover done. Used for snf mode
-- for threshold met (CR619293)
DM_DONE : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit = '1')then
dm_vsize_counter <= (others => '0');
dm_xfred_all_lines <= '0';
--elsif(fsync_out = '1')then -- CR623088
elsif(frame_sync_d1 = '1')then -- CR623088
dm_vsize_counter <= crnt_vsize;
dm_xfred_all_lines <= '0';
elsif(dm_decr_vcount = '1' and dm_vsize_counter = VSIZE_ONE_VALUE)then
dm_vsize_counter <= (others => '0');
dm_xfred_all_lines <= '1';
elsif(dm_decr_vcount = '1' and dm_vsize_counter /= VSIZE_ZERO_VALUE)then
dm_vsize_counter <= std_logic_vector(unsigned(dm_vsize_counter) - 1);
dm_xfred_all_lines <= '0';
end if;
end if;
end process DM_DONE;
end generate GEN_VCOUNT_FOR_SNF;
-- Not store and forward or no line buffer (CR619293)
GEN_NO_VCOUNT_FOR_SNF : if C_LINEBUFFER_DEPTH = 0 or C_INCLUDE_MM2S_SF = 0 generate
begin
dm_vsize_counter <= (others => '0');
dm_xfred_all_lines <= '0';
dm_decr_vcount <= '0';
end generate GEN_NO_VCOUNT_FOR_SNF;
--*****************************************************************************--
--** SPECIAL RESET GENERATION **--
--*****************************************************************************--
-- Assert reset to skid buffer on hard reset or on shutdown when fifo pipe empty
-- Waiting for fifo_pipe_empty is required to prevent a AXIS protocol violation
-- when channel shut down early
REG_SKID_RESET : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_resetn = '0')then
m_skid_reset <= '1';
elsif(fifo_pipe_empty = '1')then
if(fsync_out = '1' or dm_halt_reg = '1')then
m_skid_reset <= '1';
else
m_skid_reset <= '0';
end if;
else
m_skid_reset <= '0';
end if;
end if;
end process REG_SKID_RESET;
-- Fifo/logic reset for slave side clock domain (m_axi_mm2s_aclk)
-- If error (dm_halt=1) then halt immediatly without protocol violation
s_axis_fifo_ainit <= '1' when s_axis_resetn = '0'
or frame_sync = '1' -- Frame sync
or dm_halt = '1' -- Datamover being halted (halt due to error)
else '0';
-- Fifo/logic reset for master side clock domain (m_axis_mm2s_aclk)
m_axis_fifo_ainit <= '1' when m_axis_resetn = '0'
or fsync_out = '1' -- Frame sync
or dm_halt_reg = '1' -- Datamover being halted
else '0';
-- Fifo/logic reset for slave side clock domain (m_axi_mm2s_aclk)
-- If error (dm_halt=1) then halt immediatly without protocol violation
s_axis_fifo_ainit_nosync <= '1' when s_axis_resetn = '0'
or dm_halt = '1' -- Datamover being halted (halt due to error)
else '0';
process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
s_axis_fifo_ainit_nosync_reg <= s_axis_fifo_ainit_nosync;
end if;
end process ;
-- Fifo/logic reset for master side clock domain (m_axis_mm2s_aclk)
m_axis_fifo_ainit_nosync <= '1' when m_axis_resetn = '0'
or dm_halt_reg = '1' -- Datamover being halted
else '0';
--reset for axis_dwidth
mm2s_axis_linebuf_reset_out_inv <= m_axis_fifo_ainit_nosync;
mm2s_axis_linebuf_reset_out <= not (mm2s_axis_linebuf_reset_out_inv);
MM2S_DWIDTH_CONV_IS : if (C_DATA_WIDTH /= C_M_AXIS_MM2S_TDATA_WIDTH) generate
begin
fifo_pipe_empty <= dwidth_fifo_pipe_empty;
dwidth_fifo_pipe_empty_m <= mm2s_fifo_pipe_empty_i;
end generate MM2S_DWIDTH_CONV_IS;
MM2S_DWIDTH_CONV_IS_NOT : if (C_DATA_WIDTH = C_M_AXIS_MM2S_TDATA_WIDTH) generate
begin
fifo_pipe_empty <= '1' when (all_lines_xfred = '1' and m_axis_tvalid_out = '0') -- All data for frame transmitted
or (sf_threshold_met = '0' -- Or Threshold not met
and stop_reg = '1' -- Commanded to stop
and m_axis_tvalid_out = '0') -- And NOT driving tvalid
else '0';
dwidth_fifo_pipe_empty_m <= '1';
end generate MM2S_DWIDTH_CONV_IS_NOT;
mm2s_all_lines_xfred_s <= '0';
fsync_out_m <= '0';
mm2s_vsize_cntr_clr_flag <= '0';
mm2s_fsize_mismatch_err_m <= '0';
end generate GEN_LINEBUF_NO_SOF;
GEN_LINEBUF_FLUSH_SOF : if (ENABLE_FLUSH_ON_FSYNC = 1 and C_MM2S_SOF_ENABLE = 1) generate
signal s2mm_fsync_mm2s_s : std_logic := '0';
signal run_stop_reg : std_logic := '0';
signal fsync_out_d1 : std_logic := '0';
signal mm2s_fsync_int : std_logic := '0';
signal fsize_mismatch_err_int_s : std_logic := '0';
signal fsize_mismatch_err_int_m : std_logic := '0';
signal fsize_mismatch_err_flag_s : std_logic := '0';
signal fsize_mismatch_err_flag_vsize_cntr_clr : std_logic := '0';
signal fsize_mismatch_err_flag_cmb_s : std_logic := '0';
signal fsync_src_select_cdc_tig : std_logic_vector(1 downto 0) := (others => '0');
signal fsync_src_select_d1 : std_logic_vector(1 downto 0) := (others => '0');
signal fsync_src_select_s_int : std_logic_vector(1 downto 0) := (others => '0');
signal fsize_err_to_dm_halt_flag : std_logic := '0';
signal fsize_err_to_dm_halt_flag_ored : std_logic := '0';
signal delay_fsync_fsize_err_till_dm_halt_cmplt_pulse_s : std_logic := '0';
signal delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s : std_logic := '0';
signal delay_fsync_fsize_err_till_dm_halt_cmplt_s_d1 : std_logic := '0';
signal d_fsync_halt_cmplt_s : std_logic := '0';
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF fsync_src_select_cdc_tig : SIGNAL IS "true";
ATTRIBUTE async_reg OF fsync_src_select_d1 : SIGNAL IS "true";
begin
--*****************************************************************************--
--** LINE BUFFER MODE (Sync or Async) **--
--*****************************************************************************--
GEN_LINEBUFFER : if C_LINEBUFFER_DEPTH /= 0 generate
begin
-- Divide by number bytes per data beat and add padding to dynamic
-- threshold setting
data_count_ae_threshold <= linebuf_threshold((DATACOUNT_WIDTH-1) + THRESHOLD_LSB_INDEX
downto THRESHOLD_LSB_INDEX);
-- Synchronous clock therefore instantiate an Asynchronous FIFO
GEN_SYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2_8.axi_vdma_sfifo
generic map(
UW_DATA_WIDTH => BUFFER_WIDTH ,
C_FULL_FLAGS_RST_VAL => 1 ,
UW_FIFO_DEPTH => BUFFER_DEPTH ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
rst => s_axis_fifo_ainit_nosync ,
sleep => '0' ,
wr_rst_busy => wr_rst_busy_sig ,
rd_rst_busy => rd_rst_busy_sig ,
clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i ,
data_count => fifo_rdcount
);
--wr_rst_busy_sig <= '0';
--rd_rst_busy_sig <= '0';
end generate GEN_SYNC_FIFO;
-- Asynchronous clock therefore instantiate an Asynchronous FIFO
GEN_ASYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
LB_BRAM : if ( (C_ENABLE_DEBUG_INFO_1 = 1 or C_ENABLE_DEBUG_ALL = 1) )
generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2_8.axi_vdma_afifo
generic map(
UW_DATA_WIDTH => BUFFER_WIDTH ,
C_FULL_FLAGS_RST_VAL => 1 ,
UW_FIFO_DEPTH => BUFFER_DEPTH ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
rst => s_axis_fifo_ainit_nosync_reg ,
sleep => '0' ,
wr_rst_busy => open ,
rd_rst_busy => open ,
wr_clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_clk => m_axis_aclk ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i ,
wr_data_count => open , --CR622702
rd_data_count => fifo_rdcount
);
wr_rst_busy_sig <= '0';
rd_rst_busy_sig <= '0';
end generate LB_BRAM;
LB_BUILT_IN : if ( (C_ENABLE_DEBUG_INFO_1 = 0 and C_ENABLE_DEBUG_ALL = 0) )
generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2_8.axi_vdma_afifo_builtin
generic map(
PL_FIFO_TYPE => "BUILT_IN" ,
PL_READ_MODE => "FWFT" ,
PL_FASTER_CLOCK => "WR_CLK" , --RD_CLK
PL_FULL_FLAGS_RST_VAL => 0 , -- ?
PL_DATA_WIDTH => BUFFER_WIDTH ,
C_FAMILY => C_FAMILY ,
PL_FIFO_DEPTH => BUFFER_DEPTH
)
port map(
-- Inputs
rst => s_axis_fifo_ainit_nosync_reg ,
sleep => '0' ,
wr_rst_busy => wr_rst_busy_sig ,
rd_rst_busy => rd_rst_busy_sig ,
wr_clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_clk => m_axis_aclk ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i
);
end generate LB_BUILT_IN;
end generate GEN_ASYNC_FIFO;
-- Generate an SOF on tuser(0). currently vdma only support 1 tuser bit that is set by
-- frame sync and driven out on first data beat of mm2s packet.
------ GEN_SOF : if C_MM2S_SOF_ENABLE = 1 generate
------ signal sof_reset : std_logic := '0';
------ begin
sof_reset <= '1' when (s_axis_resetn = '0')
or (dm_halt = '1')
else '0';
-- On frame sync set flag and then clear flag when
-- sof written to fifo.
SOF_FLAG_PROCESS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(sof_reset = '1' or fifo_wren = '1')then
sof_flag <= '0';
elsif(frame_sync = '1')then
sof_flag <= '1';
end if;
end if;
end process SOF_FLAG_PROCESS;
GEN_MM2S_DRE_ENABLED_TKEEP : if C_INCLUDE_MM2S_DRE = 1 generate
begin
-- AXI Slave Side of FIFO
fifo_din <= sof_flag & s_axis_tlast & s_axis_tkeep_signal & s_axis_tdata;
fifo_wren <= s_axis_tvalid and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
s_axis_tready <= s_axis_tready_i; -- CR619293
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready_i and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig and sf_threshold_met;
m_axis_tdata_i <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_i <= fifo_dout(BUFFER_WIDTH-3 downto (BUFFER_WIDTH-3) - (C_DATA_WIDTH/8) + 1);
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-2);
m_axis_tuser_i(0) <= fifo_dout(BUFFER_WIDTH-1);
end generate GEN_MM2S_DRE_ENABLED_TKEEP;
GEN_NO_MM2S_DRE_DISABLE_TKEEP : if C_INCLUDE_MM2S_DRE = 0 generate
begin
-- AXI Slave Side of FIFO
fifo_din <= sof_flag & s_axis_tlast & s_axis_tdata;
fifo_wren <= s_axis_tvalid and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
s_axis_tready <= s_axis_tready_i; -- CR619293
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready_i and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig and sf_threshold_met;
m_axis_tdata_i <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_i <= (others => '1');
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-2);
m_axis_tuser_i(0) <= fifo_dout(BUFFER_WIDTH-1);
end generate GEN_NO_MM2S_DRE_DISABLE_TKEEP;
------ end generate GEN_SOF;
------
------
-- SOF turned off therefore do not generate SOF on tuser
---------- GEN_NO_SOF : if C_MM2S_SOF_ENABLE = 0 generate
---------- begin
----------
---------- sof_flag <= '0';
----------
---------- -- AXI Slave Side of FIFO
---------- fifo_din <= s_axis_tlast & s_axis_tkeep & s_axis_tdata;
---------- fifo_wren <= s_axis_tvalid and not fifo_full_i and not s_axis_fifo_ainit;
---------- s_axis_tready_i <= not fifo_full_i and not s_axis_fifo_ainit;
---------- s_axis_tready <= s_axis_tready_i; -- CR619293
----------
---------- -- AXI Master Side of FIFO
---------- fifo_rden <= m_axis_tready_i and not fifo_empty_i and sf_threshold_met;
---------- m_axis_tvalid_i <= not fifo_empty_i and sf_threshold_met;
---------- m_axis_tdata_i <= fifo_dout(C_DATA_WIDTH-1 downto 0);
---------- m_axis_tkeep_i <= fifo_dout(BUFFER_WIDTH-2 downto (BUFFER_WIDTH-2) - (C_DATA_WIDTH/8) + 1);
---------- m_axis_tlast_i <= not fifo_empty_i and fifo_dout(BUFFER_WIDTH-1);
---------- m_axis_tuser_i <= (others => '0');
----------
---------- end generate GEN_NO_SOF;
-- Top level line buffer depth not equal to zero therefore gererate threshold
-- flags. (CR625142)
GEN_THRESHOLD_ENABLED : if C_TOPLVL_LINEBUFFER_DEPTH /= 0 and (C_ENABLE_DEBUG_INFO_1 = 1 or C_ENABLE_DEBUG_ALL = 1) generate
begin
-- Almost empty flag (note: asserts when empty also)
REG_ALMST_EMPTY : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
fifo_almost_empty_reg <= '1';
--elsif(fifo_rdcount(DATACOUNT_WIDTH-1 downto 0) <= DATA_COUNT_AE_THRESHOLD or fifo_empty_i = '1')then
--elsif((fifo_rdcount(DATACOUNT_WIDTH-1 downto 0) <= m_data_count_ae_thresh
-- or fifo_empty_i = '1') and fifo_full_i = '0')then
elsif((fifo_rdcount(DATACOUNT_WIDTH-1 downto 0) <= m_data_count_ae_thresh
or (fifo_empty_i = '1' or rd_rst_busy_sig = '1')))then
fifo_almost_empty_reg <= '1';
else
fifo_almost_empty_reg <= '0';
end if;
end if;
end process REG_ALMST_EMPTY;
mm2s_fifo_almost_empty <= fifo_almost_empty_reg
or (not sf_threshold_met) -- CR622777
or (not m_axis_tvalid_out); -- CR625724
mm2s_fifo_empty <= not m_axis_tvalid_out;
end generate GEN_THRESHOLD_ENABLED;
-- Top level line buffer depth is zero therefore turn off threshold logic.
-- this occurs for async operation where the async fifo is needed for CDC (CR625142)
GEN_THRESHOLD_DISABLED : if C_TOPLVL_LINEBUFFER_DEPTH = 0 or (C_ENABLE_DEBUG_INFO_1 = 0 and C_ENABLE_DEBUG_ALL = 0) generate
begin
mm2s_fifo_empty <= '0';
mm2s_fifo_almost_empty <= '0';
fifo_almost_empty_reg <= '0';
end generate GEN_THRESHOLD_DISABLED;
-- CR#578903
-- FIFO, FIFO Pipe, and Skid Buffer are all empty. This is used to safely
-- assert reset on shutdown and also used to safely generate fsync in free-run mode
-- CR622702 - need to look at write side of fifo to prevent false empties due to async fifo
--fifo_pipe_empty <= '1' when (fifo_wrcount(DATACOUNT_WIDTH-1 downto 0) = DATA_COUNT_ZERO -- Data count is 0
-- and m_axis_tvalid_out = '0') -- Skid Buffer is done
-- -- Forced stop and Threshold not met (CR623291)
-- or (sf_threshold_met = '0' and stop_reg = '1')
-- else '0';
-- CR623879 fixed flase fifo_pipe_assertions due to extreme AXI4 throttling on
-- mm2s reads causing fifo to go empty for extended periods of time. This then
-- caused flase idles to be flagged and frame syncs were then generated in free run mode
---------------- fifo_pipe_empty <= '1' when (all_lines_xfred = '1' and m_axis_tvalid_out = '0') -- All data for frame transmitted
---------------- or (sf_threshold_met = '0' -- Or Threshold not met
---------------- and stop_reg = '1' -- Commanded to stop
---------------- and m_axis_tvalid_out = '0') -- And NOT driving tvalid
---------------- else '0';
----------------
-- If store and forward is turned on by user then gate tvalid with
-- threshold met
GEN_THRESH_MET_FOR_SNF : if C_INCLUDE_MM2S_SF = 1 and C_TOPLVL_LINEBUFFER_DEPTH /= 0 and (C_ENABLE_DEBUG_INFO_1 = 1 or C_ENABLE_DEBUG_ALL = 1) generate
begin
-- Register fifo_almost empty in order to generate
-- almost empty fall edge pulse
REG_ALMST_EMPTY_FE : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
fifo_almost_empty_d1 <= '1';
else
fifo_almost_empty_d1 <= fifo_almost_empty_reg;
end if;
end if;
end process REG_ALMST_EMPTY_FE;
-- Almost empty falling edge
fifo_almost_empty_fe <= not fifo_almost_empty_reg and fifo_almost_empty_d1;
-- Store and Forward threshold met
THRESH_MET : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
sf_threshold_met <= '0';
elsif(fsync_out = '1')then
sf_threshold_met <= '0';
-- Reached threshold or all reads done for the frame
elsif(fifo_almost_empty_fe = '1'
or (dm_xfred_all_lines_reg = '1'))then
sf_threshold_met <= '1';
end if;
end if;
end process THRESH_MET;
end generate GEN_THRESH_MET_FOR_SNF;
-- Store and forward off therefore do not need to meet threshold
GEN_NO_THRESH_MET_FOR_SNF : if C_INCLUDE_MM2S_SF = 0 or C_TOPLVL_LINEBUFFER_DEPTH = 0 or (C_ENABLE_DEBUG_INFO_1 = 0 and C_ENABLE_DEBUG_ALL = 0) generate
begin
sf_threshold_met <= '1';
end generate GEN_NO_THRESH_MET_FOR_SNF;
--*********************************************************--
--** MM2S MASTER SKID BUFFER **--
--*********************************************************--
I_MSTR_SKID : entity axi_vdma_v6_2_8.axi_vdma_skid_buf
generic map(
C_WDATA_WIDTH => C_DATA_WIDTH ,
C_TUSER_WIDTH => C_M_AXIS_MM2S_TUSER_BITS
)
port map(
-- System Ports
ACLK => m_axis_aclk ,
ARST => m_axis_fifo_ainit_nosync ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => '0' ,
-- Slave Side (Stream Data Input)
S_VALID => m_axis_tvalid_i ,
S_READY => m_axis_tready_i ,
S_Data => m_axis_tdata_i ,
S_STRB => m_axis_tkeep_i ,
S_Last => m_axis_tlast_i ,
S_User => m_axis_tuser_i ,
-- Master Side (Stream Data Output)
M_VALID => m_axis_tvalid_out ,
M_READY => m_axis_tready ,
M_Data => m_axis_tdata ,
M_STRB => m_axis_tkeep_signal ,
M_Last => m_axis_tlast_out ,
M_User => m_axis_tuser
);
-- Pass out of core
m_axis_tvalid <= m_axis_tvalid_out;
m_axis_tlast <= m_axis_tlast_out;
-- Register to break long timing paths for use in
-- transfer complete generation
REG_STRM_SIGS : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
m_axis_tlast_d1 <= '0';
m_axis_tvalid_d1 <= '0';
m_axis_tready_d1 <= '0';
else
m_axis_tlast_d1 <= m_axis_tlast_out;
m_axis_tvalid_d1 <= m_axis_tvalid_out;
m_axis_tready_d1 <= m_axis_tready;
end if;
end if;
end process REG_STRM_SIGS;
end generate GEN_LINEBUFFER;
--*****************************************************************************--
--** NO LINE BUFFER MODE (Sync Only) **--
--*****************************************************************************--
-- LineBuffer forced on if asynchronous mode is enabled
GEN_NO_LINEBUFFER : if (C_LINEBUFFER_DEPTH = 0) generate -- No Line Buffer
begin
-- Map Datamover to AXIS Master Out
m_axis_tdata <= s_axis_tdata;
m_axis_tkeep_signal <= s_axis_tkeep_signal;
m_axis_tvalid <= s_axis_tvalid;
m_axis_tlast <= s_axis_tlast;
s_axis_tready <= m_axis_tready;
-- Tie FIFO Flags off
mm2s_fifo_empty <= '0';
mm2s_fifo_almost_empty <= '0';
-- Generate sof on tuser(0)
---- GEN_SOF : if C_MM2S_SOF_ENABLE = 1 generate
--- begin
-- On frame sync set flag and then clear flag when
-- sof written to fifo.
SOF_FLAG_PROCESS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit = '1' or (s_axis_tvalid = '1' and m_axis_tready = '1'))then
sof_flag <= '0';
elsif(frame_sync = '1')then
sof_flag <= '1';
end if;
end if;
end process SOF_FLAG_PROCESS;
m_axis_tuser(0) <= sof_flag;
--- end generate GEN_SOF;
-- Do not generate sof on tuser(0)
----- GEN_NO_SOF : if C_MM2S_SOF_ENABLE = 0 generate
----- begin
----- sof_flag <= '0';
----- m_axis_tuser <= (others => '0');
----- end generate GEN_NO_SOF;
-- CR#578903
-- Register tvalid to break timing paths for use in
-- psuedo fifo empty for channel idle generation and
-- for xfer complete generation.
REG_STRM_SIGS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
m_axis_tvalid_d1 <= '0';
m_axis_tlast_d1 <= '0';
m_axis_tready_d1 <= '0';
else
m_axis_tvalid_d1 <= s_axis_tvalid;
m_axis_tlast_d1 <= s_axis_tlast;
m_axis_tready_d1 <= m_axis_tready;
end if;
end if;
end process REG_STRM_SIGS;
-- CR#578903
-- Psuedo FIFO, FIFO Pipe, and Skid Buffer are all empty. This is used to safely
-- assert reset on shutdown and also used to safely generate fsync in free-run mode
-- This flag is looked at at the end of frames.
-- Order of else-if is critical
-- CR579191 modified method to prevent double fsync assertions
REG_PIPE_EMPTY : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
fifo_pipe_empty <= '1';
-- Command/Status not idle indicates pending datamover commands
-- set psuedo fifo empty to NOT empty.
elsif(cmdsts_idle_fe = '1')then
fifo_pipe_empty <= '0';
-- On accepted tlast then clear psuedo empty flag back to being empty
elsif(pot_empty = '1' and cmdsts_idle = '1')then
fifo_pipe_empty <= '1';
end if;
end if;
end process REG_PIPE_EMPTY;
REG_IDLE_FE : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
cmdsts_idle_d1 <= '1';
else
cmdsts_idle_d1 <= cmdsts_idle;
end if;
end if;
end process REG_IDLE_FE;
-- CR579586 Use falling edge to set pfifo empty
cmdsts_idle_fe <= not cmdsts_idle and cmdsts_idle_d1;
-- CR579191
POTENTIAL_EMPTY_PROCESS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
pot_empty <= '1';
elsif(m_axis_tvalid_d1 = '1' and m_axis_tlast_d1 = '1' and m_axis_tready_d1 = '1')then
pot_empty <= '1';
elsif(m_axis_tvalid_d1 = '1' and m_axis_tlast_d1 = '0')then
pot_empty <= '0';
end if;
end if;
end process POTENTIAL_EMPTY_PROCESS;
end generate GEN_NO_LINEBUFFER;
--*****************************************************************************--
--** MM2S ASYNCH CLOCK SUPPORT **--
--*****************************************************************************--
-- Cross fifo pipe empty flag to secondary clock domain
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Pipe Empty and Shutdown reset CDC
---- SHUTDOWN_RST_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => fifo_pipe_empty ,
---- scndry_out => mm2s_fifo_pipe_empty_i ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
SHUTDOWN_RST_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => fifo_pipe_empty,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => mm2s_fifo_pipe_empty_i,
scndry_vect_out => open
);
-- Vertical Count and All Lines Transferred CDC (CR616211)
---- ALL_LINES_XFRED_P_S_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' , -- CR619293
---- prmry_out => open , -- CR619293
---- prmry_in => all_lines_xfred ,
---- scndry_out => mm2s_all_lines_xfred ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
ALL_LINES_XFRED_P_S_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => all_lines_xfred,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => mm2s_all_lines_xfred,
scndry_vect_out => open
);
-- Vertical Count and All Lines Transferred CDC (CR616211)
---- ALL_LINES_XFRED_S_P_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => dm_xfred_all_lines , -- CR619293
---- prmry_out => dm_xfred_all_lines_reg , -- CR619293
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
ALL_LINES_XFRED_S_P_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => dm_xfred_all_lines,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => dm_xfred_all_lines_reg,
scndry_vect_out => open
);
VSIZE_CNT_CROSSING : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
crnt_vsize_cdc_tig <= crnt_vsize;
crnt_vsize_d1 <= crnt_vsize_cdc_tig;
end if;
end process VSIZE_CNT_CROSSING;
crnt_vsize_d2 <= crnt_vsize_d1;
-- Cross stop signal (CR623291)
---- STOP_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => stop ,
---- prmry_out => stop_reg ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
STOP_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => stop,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => stop_reg,
scndry_vect_out => open
);
---- MM2S_RUN_STOP_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => run_stop ,
---- prmry_out => run_stop_reg ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
MM2S_RUN_STOP_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => run_stop,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => run_stop_reg,
scndry_vect_out => open
);
---- MM2S_FSIZE_ERR_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => fsize_mismatch_err_int_s ,
---- scndry_out => fsize_mismatch_err_int_m ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
MM2S_FSIZE_ERR_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => fsize_mismatch_err_int_s,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => fsize_mismatch_err_int_m,
scndry_vect_out => open
);
---- MM2S_FSYNC_OUT_CDC_I_FLUSH_SOF : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' , -- Not Used
---- prmry_out => open , -- Not Used
---- prmry_in => fsync_out ,
---- scndry_out => fsync_out_m ,
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => '0' , -- Not Used
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- scndry_vect_out => open -- Not Used
---- );
----
MM2S_FSYNC_OUT_CDC_I_FLUSH_SOF : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => fsync_out,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => fsync_out_m,
scndry_vect_out => open
);
GEN_FSYNC_SEL_CROSSING : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
fsync_src_select_cdc_tig <= fsync_src_select;
fsync_src_select_d1 <= fsync_src_select_cdc_tig;
end if;
end process GEN_FSYNC_SEL_CROSSING;
fsync_src_select_s_int <= fsync_src_select_d1;
-- Cross datamover halt and threshold signals
---- HALT_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => dm_halt ,
---- prmry_out => dm_halt_reg ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- scndry_vect_out => open
---- );
----
HALT_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => dm_halt,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => dm_halt_reg,
scndry_vect_out => open
);
THRESH_CNT_CROSSING : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
data_count_ae_threshold_cdc_tig <= data_count_ae_threshold;
data_count_ae_threshold_d1 <= data_count_ae_threshold_cdc_tig;
end if;
end process THRESH_CNT_CROSSING;
m_data_count_ae_thresh <= data_count_ae_threshold_d1;
GEN_ASYNC_CROSS_FSYNC : if C_INCLUDE_S2MM = 1 generate
begin
---- CROSS_FSYNC_CDC_I_FLUSH_MM2S_SOF : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => s_axis_s2mm_aclk ,
---- prmry_resetn => s2mm_axis_resetn ,
---- scndry_aclk => m_axis_aclk ,
---- scndry_resetn => m_axis_resetn ,
---- scndry_in => '0' , -- Not Used
---- prmry_out => open , -- Not Used
---- prmry_in => s2mm_fsync ,
---- scndry_out => s2mm_fsync_mm2s_s ,
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => '0' , -- Not Used
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- scndry_vect_out => open -- Not Used
---- );
----
CROSS_FSYNC_CDC_I_FLUSH_MM2S_SOF : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_s2mm_aclk,
prmry_resetn => s2mm_axis_resetn,
prmry_in => s2mm_fsync,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => s2mm_fsync_mm2s_s,
scndry_vect_out => open
);
end generate GEN_ASYNC_CROSS_FSYNC;
GEN_ASYNC_NO_CROSS_FSYNC : if C_INCLUDE_S2MM = 0 generate
begin
s2mm_fsync_mm2s_s <= '0';
end generate GEN_ASYNC_NO_CROSS_FSYNC;
end generate GEN_FOR_ASYNC;
--*****************************************************************************--
--** MM2S SYNCH CLOCK SUPPORT **--
--*****************************************************************************--
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
mm2s_fifo_pipe_empty_i <= fifo_pipe_empty;
crnt_vsize_d2 <= crnt_vsize; -- CR616211
mm2s_all_lines_xfred <= all_lines_xfred; -- CR616211
dm_xfred_all_lines_reg <= dm_xfred_all_lines; -- CR619293
stop_reg <= stop; -- CR623291
run_stop_reg <= run_stop; -- CR623291
fsync_out_m <= fsync_out; -- CR623291
dm_halt_reg <= dm_halt;
m_data_count_ae_thresh <= data_count_ae_threshold;
fsync_src_select_s_int <= fsync_src_select;
fsize_mismatch_err_int_m <= fsize_mismatch_err_int_s;
GEN_SYNC_CROSS_FSYNC : if C_INCLUDE_S2MM = 1 generate
begin
s2mm_fsync_mm2s_s <= s2mm_fsync;
end generate GEN_SYNC_CROSS_FSYNC;
GEN_SYNC_NO_CROSS_FSYNC : if C_INCLUDE_S2MM = 0 generate
begin
s2mm_fsync_mm2s_s <= '0';
end generate GEN_SYNC_NO_CROSS_FSYNC;
end generate GEN_FOR_SYNC;
NO_DWIDTH_VERT_COUNTER : if (C_DATA_WIDTH = C_M_AXIS_MM2S_TDATA_WIDTH) generate
begin
--*****************************************************************************
--** Vertical Line Tracking (CR616211)
--*****************************************************************************
-- Decrement vertical count with each accept tlast
decr_vcount <= '1' when m_axis_tlast_d1 = '1'
and m_axis_tvalid_d1 = '1'
and m_axis_tready_d1 = '1'
else '0';
-- Drive ready at fsync out then de-assert once all lines have
-- been accepted.
VERT_COUNTER : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if((m_axis_fifo_ainit = '1' and fsync_out = '0') or fsize_mismatch_err_flag_vsize_cntr_clr = '1' )then
vsize_counter <= (others => '0');
all_lines_xfred_no_dwidth <= '1';
elsif(fsync_out = '1')then
vsize_counter <= crnt_vsize_d2;
all_lines_xfred_no_dwidth <= '0';
elsif(decr_vcount = '1' and vsize_counter = VSIZE_ONE_VALUE)then
vsize_counter <= (others => '0');
all_lines_xfred_no_dwidth <= '1';
elsif(decr_vcount = '1' and vsize_counter /= VSIZE_ZERO_VALUE)then
vsize_counter <= std_logic_vector(unsigned(vsize_counter) - 1);
all_lines_xfred_no_dwidth <= '0';
end if;
end if;
end process VERT_COUNTER;
end generate NO_DWIDTH_VERT_COUNTER;
-- Store and forward or no line buffer (CR619293)
GEN_VCOUNT_FOR_SNF : if C_LINEBUFFER_DEPTH /= 0 and C_INCLUDE_MM2S_SF = 1 generate
begin
dm_decr_vcount <= '1' when s_axis_tlast = '1'
and s_axis_tvalid = '1'
and s_axis_tready_i = '1'
else '0';
-- Delay 1 pipe to align with cnrt_vsize
REG_FSYNC_TO_ALIGN : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit = '1' and frame_sync = '0')then
frame_sync_d1 <= '0';
else
frame_sync_d1 <= frame_sync;
end if;
end if;
end process REG_FSYNC_TO_ALIGN;
-- Count lines to determine when datamover done. Used for snf mode
-- for threshold met (CR619293)
DM_DONE : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit = '1')then
dm_vsize_counter <= (others => '0');
dm_xfred_all_lines <= '0';
--elsif(fsync_out = '1')then -- CR623088
elsif(frame_sync_d1 = '1')then -- CR623088
dm_vsize_counter <= crnt_vsize;
dm_xfred_all_lines <= '0';
elsif(dm_decr_vcount = '1' and dm_vsize_counter = VSIZE_ONE_VALUE)then
dm_vsize_counter <= (others => '0');
dm_xfred_all_lines <= '1';
elsif(dm_decr_vcount = '1' and dm_vsize_counter /= VSIZE_ZERO_VALUE)then
dm_vsize_counter <= std_logic_vector(unsigned(dm_vsize_counter) - 1);
dm_xfred_all_lines <= '0';
end if;
end if;
end process DM_DONE;
end generate GEN_VCOUNT_FOR_SNF;
-- Not store and forward or no line buffer (CR619293)
GEN_NO_VCOUNT_FOR_SNF : if C_LINEBUFFER_DEPTH = 0 or C_INCLUDE_MM2S_SF = 0 generate
begin
dm_vsize_counter <= (others => '0');
dm_xfred_all_lines <= '0';
dm_decr_vcount <= '0';
end generate GEN_NO_VCOUNT_FOR_SNF;
--*****************************************************************************--
--** SPECIAL RESET GENERATION **--
--*****************************************************************************--
-- Assert reset to skid buffer on hard reset or on shutdown when fifo pipe empty
-- Waiting for fifo_pipe_empty is required to prevent a AXIS protocol violation
-- when channel shut down early
REG_SKID_RESET : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_resetn = '0')then
m_skid_reset <= '1';
elsif(fifo_pipe_empty = '1')then
if(fsync_out = '1' or dm_halt_reg = '1')then
m_skid_reset <= '1';
else
m_skid_reset <= '0';
end if;
else
m_skid_reset <= '0';
end if;
end if;
end process REG_SKID_RESET;
-- Fifo/logic reset for slave side clock domain (m_axi_mm2s_aclk)
-- If error (dm_halt=1) then halt immediatly without protocol violation
s_axis_fifo_ainit <= '1' when s_axis_resetn = '0'
or frame_sync = '1' -- Frame sync
or dm_halt = '1' -- Datamover being halted (halt due to error)
else '0';
-- Fifo/logic reset for master side clock domain (m_axis_mm2s_aclk)
m_axis_fifo_ainit <= '1' when m_axis_resetn = '0'
or fsync_out = '1' -- Frame sync
or dm_halt_reg = '1' -- Datamover being halted
else '0';
-- Fifo/logic reset for slave side clock domain (m_axi_mm2s_aclk)
-- If error (dm_halt=1) then halt immediatly without protocol violation
s_axis_fifo_ainit_nosync <= '1' when s_axis_resetn = '0'
or dm_halt = '1' -- Datamover being halted (halt due to error)
else '0';
process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
s_axis_fifo_ainit_nosync_reg <= s_axis_fifo_ainit_nosync;
end if;
end process ;
-- Fifo/logic reset for master side clock domain (m_axis_mm2s_aclk)
m_axis_fifo_ainit_nosync <= '1' when m_axis_resetn = '0'
or dm_halt_reg = '1' -- Datamover being halted
else '0';
--reset for axis_dwidth
mm2s_axis_linebuf_reset_out_inv <= m_axis_fifo_ainit_nosync;
mm2s_axis_linebuf_reset_out <= not (mm2s_axis_linebuf_reset_out_inv);
all_lines_xfred <= mm2s_all_lines_xfred_s_sig;
mm2s_all_lines_xfred_s <= mm2s_all_lines_xfred_s_sig;
--C_DATA_WIDTH = C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED
MM2S_DWIDTH_CONV_IS : if (C_DATA_WIDTH /= C_M_AXIS_MM2S_TDATA_WIDTH) generate
begin
mm2s_all_lines_xfred_s_sig <= mm2s_all_lines_xfred_s_dwidth;
fifo_pipe_empty <= dwidth_fifo_pipe_empty;
dwidth_fifo_pipe_empty_m <= mm2s_fifo_pipe_empty_i;
end generate MM2S_DWIDTH_CONV_IS;
MM2S_DWIDTH_CONV_IS_NOT : if (C_DATA_WIDTH = C_M_AXIS_MM2S_TDATA_WIDTH) generate
begin
mm2s_all_lines_xfred_s_sig <= all_lines_xfred_no_dwidth;
fifo_pipe_empty <= '1' when (all_lines_xfred = '1' and m_axis_tvalid_out = '0') -- All data for frame transmitted
or (sf_threshold_met = '0' -- Or Threshold not met
and stop_reg = '1' -- Commanded to stop
and m_axis_tvalid_out = '0') -- And NOT driving tvalid
else '0';
dwidth_fifo_pipe_empty_m <= '1';
end generate MM2S_DWIDTH_CONV_IS_NOT;
mm2s_fsync_int <= mm2s_fsync and run_stop_reg;
-- Frame sync cross bar
---- FSYNC_CROSSBAR_MM2S_S : process(fsync_src_select_s_int,
---- run_stop_reg,
---- mm2s_fsync,
---- s2mm_fsync_mm2s_s)
---- begin
---- case fsync_src_select_s_int is
----
---- when "00" => -- primary fsync (default)
---- mm2s_fsync_int <= mm2s_fsync and run_stop_reg;
---- when "01" => -- other channel fsync
---- mm2s_fsync_int <= s2mm_fsync_mm2s_s and run_stop_reg;
---- when others =>
---- mm2s_fsync_int <= '0';
---- end case;
---- end process FSYNC_CROSSBAR_MM2S_S;
FSIZE_MISMATCH_MM2S_FLUSH_SOF_s : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk='1')then
if(m_axis_resetn = '0')then
fsize_mismatch_err_int_s <= '0';
-- fsync occurred when not all lines transferred
elsif(mm2s_fsync_int = '1' and mm2s_all_lines_xfred_s_sig = '0')then
fsize_mismatch_err_int_s <= '1';
else
fsize_mismatch_err_int_s <= '0';
end if;
end if;
end process FSIZE_MISMATCH_MM2S_FLUSH_SOF_s;
FSIZE_MISMATCH_FLAG_MM2S_FLUSH_SOF_s : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk='1')then
if(m_axis_resetn = '0' or mm2s_fsync_int = '1')then
fsize_mismatch_err_flag_s <= '0';
elsif(fsize_mismatch_err_int_s = '1')then
fsize_mismatch_err_flag_s <= '1';
end if;
end if;
end process FSIZE_MISMATCH_FLAG_MM2S_FLUSH_SOF_s;
fsize_mismatch_err_flag_cmb_s <= fsize_mismatch_err_int_s or fsize_mismatch_err_flag_s;
MM2S_DROP_RESIDUAL_OF_FSIZE_ERR_FRAME_S <= fsize_mismatch_err_flag_cmb_s;
mm2s_fsize_mismatch_err_s <= fsize_mismatch_err_int_s;
mm2s_fsize_mismatch_err_m <= fsize_mismatch_err_int_m;
mm2s_vsize_cntr_clr_flag <= fsize_mismatch_err_flag_vsize_cntr_clr or fsize_mismatch_err_int_s;
D1_FSYNC_OUT : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk='1')then
if(m_axis_resetn = '0')then
fsync_out_d1 <= '0';
else
fsync_out_d1 <= fsync_out;
end if;
end if;
end process D1_FSYNC_OUT;
FLAG_VSIZE_CNTR_CLR : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk='1')then
if(m_axis_resetn = '0' or fsync_out_d1 = '1')then
fsize_mismatch_err_flag_vsize_cntr_clr <= '0';
elsif(fsize_mismatch_err_int_s = '1')then
fsize_mismatch_err_flag_vsize_cntr_clr <= '1';
end if;
end if;
end process FLAG_VSIZE_CNTR_CLR;
MM2S_FSIZE_ERR_TO_DM_HALT_FLAG : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_resetn = '0' or dm_halt_reg = '1')then
fsize_err_to_dm_halt_flag <= '0';
elsif(fsize_mismatch_err_int_s = '1')then
fsize_err_to_dm_halt_flag <= '1';
end if;
end if;
end process MM2S_FSIZE_ERR_TO_DM_HALT_FLAG;
fsize_err_to_dm_halt_flag_ored <= fsize_mismatch_err_int_s or fsize_err_to_dm_halt_flag or dm_halt_reg;
delay_fsync_fsize_err_till_dm_halt_cmplt_pulse_s <= '1' when fsize_err_to_dm_halt_flag_ored = '1' and mm2s_fsync_int = '1'
else '0';
MM2S_FSIZE_LESS_DM_HALT_CMPLT_FLAG : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_resetn = '0' or fsize_err_to_dm_halt_flag_ored = '0')then
delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s <= '0';
elsif(delay_fsync_fsize_err_till_dm_halt_cmplt_pulse_s = '1')then
delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s <= '1';
end if;
end if;
end process MM2S_FSIZE_LESS_DM_HALT_CMPLT_FLAG;
MM2S_REG_D_FSYNC : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_resetn = '0')then
delay_fsync_fsize_err_till_dm_halt_cmplt_s_d1 <= '0';
else
delay_fsync_fsize_err_till_dm_halt_cmplt_s_d1 <= delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s;
end if;
end if;
end process MM2S_REG_D_FSYNC;
d_fsync_halt_cmplt_s <= delay_fsync_fsize_err_till_dm_halt_cmplt_s_d1 and not delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s;
mm2s_fsync_core <= (mm2s_fsync_int and not (delay_fsync_fsize_err_till_dm_halt_cmplt_pulse_s)) or d_fsync_halt_cmplt_s;
--mm2s_fsync_core <= mm2s_fsync_int;
end generate GEN_LINEBUF_FLUSH_SOF;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_vdma_mm2s_linebuf
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_mm2s_linebuf.vhd
-- Description: This entity encompases the mm2s line buffer logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library lib_cdc_v1_0_2;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_vdma_mm2s_linebuf is
generic (
C_DATA_WIDTH : integer range 8 to 1024 := 32;
C_M_AXIS_MM2S_TDATA_WIDTH : integer range 8 to 1024 := 32;
-- Line Buffer Data Width
C_INCLUDE_S2MM : integer range 0 to 1 := 0;
C_INCLUDE_MM2S_SF : integer range 0 to 1 := 0;
-- Include or exclude MM2S Store And Forward Functionality
-- 0 = Exclude MM2S Store and Forward
-- 1 = Include MM2S Store and Forward
C_INCLUDE_MM2S_DRE : integer range 0 to 1 := 0;
C_MM2S_SOF_ENABLE : integer range 0 to 1 := 0;
-- Enable/Disable start of frame generation on tuser(0). This
-- is only valid for external frame sync (C_USE_FSYNC = 1)
-- 0 = disable SOF
-- 1 = enable SOF
C_M_AXIS_MM2S_TUSER_BITS : integer range 1 to 1 := 1;
-- Master AXI Stream User Width for MM2S Channel
C_TOPLVL_LINEBUFFER_DEPTH : integer range 0 to 65536 := 512; -- CR625142
-- Depth as set by user at top level parameter
C_LINEBUFFER_DEPTH : integer range 0 to 65536 := 512;
-- Linebuffer depth in Bytes. Must be a power of 2
C_LINEBUFFER_AE_THRESH : integer range 1 to 65536 := 1;
-- Linebuffer almost empty threshold in Bytes. Must be a power of 2
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0 ;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
--C_ENABLE_DEBUG_INFO : string := "1111111111111111"; -- 1 to 16 --
--C_ENABLE_DEBUG_INFO : bit_vector(15 downto 0) := (others => '1'); --15 downto 0 --
C_ENABLE_DEBUG_ALL : integer range 0 to 1 := 1;
-- Setting this make core backward compatible to 2012.4 version in terms of ports and registers
C_ENABLE_DEBUG_INFO_0 : integer range 0 to 1 := 1;
-- Enable debug information bit 0
C_ENABLE_DEBUG_INFO_1 : integer range 0 to 1 := 1;
-- Enable debug information bit 1
C_ENABLE_DEBUG_INFO_2 : integer range 0 to 1 := 1;
-- Enable debug information bit 2
C_ENABLE_DEBUG_INFO_3 : integer range 0 to 1 := 1;
-- Enable debug information bit 3
C_ENABLE_DEBUG_INFO_4 : integer range 0 to 1 := 1;
-- Enable debug information bit 4
C_ENABLE_DEBUG_INFO_5 : integer range 0 to 1 := 1;
-- Enable debug information bit 5
C_ENABLE_DEBUG_INFO_6 : integer range 0 to 1 := 1;
-- Enable debug information bit 6
C_ENABLE_DEBUG_INFO_7 : integer range 0 to 1 := 1;
-- Enable debug information bit 7
C_ENABLE_DEBUG_INFO_8 : integer range 0 to 1 := 1;
-- Enable debug information bit 8
C_ENABLE_DEBUG_INFO_9 : integer range 0 to 1 := 1;
-- Enable debug information bit 9
C_ENABLE_DEBUG_INFO_10 : integer range 0 to 1 := 1;
-- Enable debug information bit 10
C_ENABLE_DEBUG_INFO_11 : integer range 0 to 1 := 1;
-- Enable debug information bit 11
C_ENABLE_DEBUG_INFO_12 : integer range 0 to 1 := 1;
-- Enable debug information bit 12
C_ENABLE_DEBUG_INFO_13 : integer range 0 to 1 := 1;
-- Enable debug information bit 13
C_ENABLE_DEBUG_INFO_14 : integer range 0 to 1 := 1;
-- Enable debug information bit 14
C_ENABLE_DEBUG_INFO_15 : integer range 0 to 1 := 1;
-- Enable debug information bit 15
ENABLE_FLUSH_ON_FSYNC : integer range 0 to 1 := 0 ;
C_FAMILY : string := "virtex7"
-- Device family used for proper BRAM selection
);
port (
-- MM2S AXIS Input Side (i.e. Datamover side)
s_axis_aclk : in std_logic ; --
s_axis_resetn : in std_logic ; --
--
-- MM2S AXIS Output Side --
m_axis_aclk : in std_logic ; --
m_axis_resetn : in std_logic ; --
mm2s_axis_linebuf_reset_out : out std_logic ; --
s2mm_axis_resetn : in std_logic := '1' ; --
s_axis_s2mm_aclk : in std_logic := '0' ; --
mm2s_fsync : in std_logic ; --
s2mm_fsync : in std_logic ; --
mm2s_fsync_core : out std_logic ; --
mm2s_fsize_mismatch_err_s : out std_logic ; --
mm2s_fsize_mismatch_err_m : out std_logic ; --
mm2s_vsize_cntr_clr_flag : out std_logic ; --
MM2S_DROP_RESIDUAL_OF_FSIZE_ERR_FRAME_S : out std_logic ; --
fsync_src_select : in std_logic_vector(1 downto 0) ; --
--
run_stop : in std_logic ; --
-- Graceful shut down control --
dm_halt : in std_logic ; --
dm_halt_reg_out : out std_logic ; --
cmdsts_idle : in std_logic ; --
stop : in std_logic ; -- CR623291
stop_reg_out : out std_logic ; -- CR623291
--
-- Vertical Line Count control --
fsync_out : in std_logic ; -- CR616211
fsync_out_m : out std_logic ; -- CR616211
mm2s_fsize_mismatch_err_flag: in std_logic ; -- CR616211
frame_sync : in std_logic ; -- CR616211
crnt_vsize : in std_logic_vector --
(VSIZE_DWIDTH-1 downto 0) ; -- CR616211
crnt_vsize_d2_out : out std_logic_vector --
(VSIZE_DWIDTH-1 downto 0) ; -- CR616211
--
linebuf_threshold : in std_logic_vector --
(LINEBUFFER_THRESH_WIDTH-1 downto 0); --
--
-- Stream In (Datamover To Line Buffer) --
s_axis_tdata : in std_logic_vector --
(C_DATA_WIDTH-1 downto 0) ; --
s_axis_tkeep : in std_logic_vector --
((C_DATA_WIDTH/8)-1 downto 0) ; --
s_axis_tlast : in std_logic ; --
s_axis_tvalid : in std_logic ; --
s_axis_tready : out std_logic ; --
--
--
-- Stream Out (Line Buffer To MM2S AXIS) --
m_axis_tdata : out std_logic_vector --
(C_DATA_WIDTH-1 downto 0) ; --
m_axis_tkeep : out std_logic_vector --
((C_DATA_WIDTH/8)-1 downto 0) ; --
m_axis_tlast : out std_logic ; --
m_axis_tvalid : out std_logic ; --
m_axis_tready : in std_logic ; --
m_axis_tuser : out std_logic_vector --
(C_M_AXIS_MM2S_TUSER_BITS-1 downto 0); --
--
-- Fifo Status Flags --
dwidth_fifo_pipe_empty : in std_logic ; --
dwidth_fifo_pipe_empty_m : out std_logic ; --
mm2s_fifo_pipe_empty : out std_logic ; --
mm2s_fifo_empty : out std_logic ; --
mm2s_fifo_almost_empty : out std_logic ; --
mm2s_all_lines_xfred_s_dwidth : in std_logic ; --
mm2s_all_lines_xfred_s : out std_logic ; --
mm2s_all_lines_xfred : out std_logic -- CR616211
);
end axi_vdma_mm2s_linebuf;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_mm2s_linebuf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Bufer depth
--constant BUFFER_DEPTH : integer := max2(128,C_LINEBUFFER_DEPTH/(C_DATA_WIDTH/8));
constant BUFFER_DEPTH : integer := C_LINEBUFFER_DEPTH;
-- Buffer width is data width + strobe width + 1 bit for tlast
-- Increase data width by 1 when tuser support included.
--constant BUFFER_WIDTH : integer := C_DATA_WIDTH + (C_DATA_WIDTH/8) + 1;
constant BUFFER_WIDTH : integer := C_DATA_WIDTH -- tdata
+ (C_DATA_WIDTH/8)*C_INCLUDE_MM2S_DRE -- tkeep
+ 1 -- tlast
+ (C_MM2S_SOF_ENABLE -- tuser
*C_M_AXIS_MM2S_TUSER_BITS);
-- Buffer data count width
constant DATACOUNT_WIDTH : integer := clog2(BUFFER_DEPTH);
constant DATA_COUNT_ZERO : std_logic_vector(DATACOUNT_WIDTH-1 downto 0)
:= (others => '0');
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
constant ZERO_VALUE_VECT : std_logic_vector(255 downto 0) := (others => '0');
-- Constants for line tracking logic
constant VSIZE_ONE_VALUE : std_logic_vector(VSIZE_DWIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(1,VSIZE_DWIDTH));
constant VSIZE_ZERO_VALUE : std_logic_vector(VSIZE_DWIDTH-1 downto 0)
:= (others => '0');
-- Linebuffer threshold support
constant THRESHOLD_LSB_INDEX : integer := clog2((C_DATA_WIDTH/8));
constant THRESHOLD_PAD : std_logic_vector(THRESHOLD_LSB_INDEX-1 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal fifo_din : std_logic_vector(BUFFER_WIDTH - 1 downto 0) := (others => '0');
signal fifo_dout : std_logic_vector(BUFFER_WIDTH - 1 downto 0) := (others => '0');
signal fifo_wren : std_logic := '0';
signal fifo_rden : std_logic := '0';
signal fifo_empty_i : std_logic := '0';
signal fifo_full_i : std_logic := '0';
signal fifo_ainit : std_logic := '0';
signal fifo_rdcount : std_logic_vector(DATACOUNT_WIDTH -1 downto 0) := (others => '0');
signal s_axis_tready_i : std_logic := '0'; -- CR619293
signal m_axis_tready_i : std_logic := '0';
signal m_axis_tvalid_i : std_logic := '0';
signal m_axis_tlast_i : std_logic := '0';
signal m_axis_tdata_i : std_logic_vector(C_DATA_WIDTH-1 downto 0):= (others => '0');
signal m_axis_tkeep_i : std_logic_vector((C_DATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_axis_tkeep_signal : std_logic_vector((C_DATA_WIDTH/8)-1 downto 0) := (others => '0');
signal s_axis_tkeep_signal : std_logic_vector((C_DATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_axis_tuser_i : std_logic_vector(C_M_AXIS_MM2S_TUSER_BITS - 1 downto 0) := (others => '0');
signal m_axis_tready_d1 : std_logic := '0';
signal m_axis_tlast_d1 : std_logic := '0';
signal m_axis_tvalid_d1 : std_logic := '0';
signal crnt_vsize_cdc_tig : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0'); -- CR575884
signal crnt_vsize_d1 : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0'); -- CR575884
signal crnt_vsize_d2 : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0'); -- CR575884
signal vsize_counter : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0'); -- CR575884
signal decr_vcount : std_logic := '0'; -- CR575884
signal all_lines_xfred : std_logic := '0'; -- CR616211
signal all_lines_xfred_no_dwidth : std_logic := '0'; -- CR616211
signal mm2s_all_lines_xfred_s_sig : std_logic := '0'; -- CR616211
signal m_axis_tvalid_out : std_logic := '0'; -- CR576993
signal m_axis_tlast_out : std_logic := '0'; -- CR616211
signal slv2skid_s_axis_tvalid : std_logic := '0'; -- CR576993
signal fifo_empty_d1 : std_logic := '0'; -- CR576993
-- FIFO Pipe empty signals
signal fifo_pipe_empty : std_logic := '0';
signal fifo_wren_d1 : std_logic := '0'; -- CR579191
signal pot_empty : std_logic := '0'; -- CR579191
signal fifo_almost_empty_i : std_logic := '1'; -- CR604273/CR604272
signal fifo_almost_empty_d1 : std_logic := '1';
signal fifo_almost_empty_fe : std_logic := '0'; -- CR604273/CR604272
signal fifo_almost_empty_reg : std_logic := '1';
signal data_count_ae_threshold_cdc_tig : std_logic_vector(DATACOUNT_WIDTH-1 downto 0) := (others => '0');
signal data_count_ae_threshold_d1 : std_logic_vector(DATACOUNT_WIDTH-1 downto 0) := (others => '0');
signal data_count_ae_threshold : std_logic_vector(DATACOUNT_WIDTH-1 downto 0) := (others => '0');
signal m_data_count_ae_thresh : std_logic_vector(DATACOUNT_WIDTH-1 downto 0) := (others => '0');
signal sf_threshold_met : std_logic := '0';
signal cmdsts_idle_d1 : std_logic := '0';
signal cmdsts_idle_fe : std_logic := '0';
signal stop_reg : std_logic := '0'; --CR623291
signal s_axis_fifo_ainit : std_logic := '0';
signal m_axis_fifo_ainit : std_logic := '0';
signal s_axis_fifo_ainit_nosync : std_logic := '0';
signal s_axis_fifo_ainit_nosync_reg : std_logic := '0';
signal m_axis_fifo_ainit_nosync : std_logic := '0';
signal dm_decr_vcount : std_logic := '0'; -- CR619293
signal dm_xfred_all_lines : std_logic := '0'; -- CR619293
signal dm_vsize_counter : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0'); -- CR619293
signal dm_xfred_all_lines_reg : std_logic := '0'; -- CR619293
signal sof_flag : std_logic := '0';
signal mm2s_fifo_pipe_empty_i : std_logic := '0';
signal frame_sync_d1 : std_logic := '0';
signal m_skid_reset : std_logic := '0';
signal dm_halt_reg : std_logic := '0';
signal mm2s_axis_linebuf_reset_out_inv : std_logic := '0' ; --
signal sof_reset : std_logic := '0';
signal wr_rst_busy_sig : std_logic := '0';
signal rd_rst_busy_sig : std_logic := '0';
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF crnt_vsize_cdc_tig : SIGNAL IS "true";
ATTRIBUTE async_reg OF crnt_vsize_d1 : SIGNAL IS "true";
ATTRIBUTE async_reg OF data_count_ae_threshold_cdc_tig : SIGNAL IS "true";
ATTRIBUTE async_reg OF data_count_ae_threshold_d1 : SIGNAL IS "true";
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
mm2s_fifo_pipe_empty <= mm2s_fifo_pipe_empty_i;
dm_halt_reg_out <= dm_halt_reg;
stop_reg_out <= stop_reg;
crnt_vsize_d2_out <= crnt_vsize_d2;
GEN_MM2S_DRE_ON : if C_INCLUDE_MM2S_DRE = 1 generate
begin
m_axis_tkeep <= m_axis_tkeep_signal;
s_axis_tkeep_signal <= s_axis_tkeep;
end generate GEN_MM2S_DRE_ON;
GEN_MM2S_DRE_OFF : if C_INCLUDE_MM2S_DRE = 0 generate
begin
m_axis_tkeep <= (others => '1');
s_axis_tkeep_signal <= (others => '1');
end generate GEN_MM2S_DRE_OFF;
GEN_LINEBUF_NO_SOF : if (ENABLE_FLUSH_ON_FSYNC = 0 or C_MM2S_SOF_ENABLE = 0) generate
begin
mm2s_fsync_core <= mm2s_fsync;
MM2S_DROP_RESIDUAL_OF_FSIZE_ERR_FRAME_S <= '0';
mm2s_fsize_mismatch_err_s <= '0';
--*****************************************************************************--
--** LINE BUFFER MODE (Sync or Async) **--
--*****************************************************************************--
GEN_LINEBUFFER : if C_LINEBUFFER_DEPTH /= 0 generate
begin
-- Divide by number bytes per data beat and add padding to dynamic
-- threshold setting
data_count_ae_threshold <= linebuf_threshold((DATACOUNT_WIDTH-1) + THRESHOLD_LSB_INDEX
downto THRESHOLD_LSB_INDEX);
-- Synchronous clock therefore instantiate an Asynchronous FIFO
GEN_SYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2_8.axi_vdma_sfifo
generic map(
UW_DATA_WIDTH => BUFFER_WIDTH ,
C_FULL_FLAGS_RST_VAL => 1 ,
UW_FIFO_DEPTH => BUFFER_DEPTH ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
rst => s_axis_fifo_ainit_nosync ,
sleep => '0' ,
wr_rst_busy => wr_rst_busy_sig ,
rd_rst_busy => rd_rst_busy_sig ,
clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i ,
data_count => fifo_rdcount
);
--wr_rst_busy_sig <= '0';
--rd_rst_busy_sig <= '0';
end generate GEN_SYNC_FIFO;
-- Asynchronous clock therefore instantiate an Asynchronous FIFO
GEN_ASYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
LB_BRAM : if ( (C_ENABLE_DEBUG_INFO_1 = 1 or C_ENABLE_DEBUG_ALL = 1) )
generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2_8.axi_vdma_afifo
generic map(
UW_DATA_WIDTH => BUFFER_WIDTH ,
C_FULL_FLAGS_RST_VAL => 1 ,
UW_FIFO_DEPTH => BUFFER_DEPTH ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
rst => s_axis_fifo_ainit_nosync_reg ,
sleep => '0' ,
wr_rst_busy => open ,
rd_rst_busy => open ,
wr_clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_clk => m_axis_aclk ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i ,
wr_data_count => open , --CR622702
rd_data_count => fifo_rdcount
);
wr_rst_busy_sig <= '0';
rd_rst_busy_sig <= '0';
end generate LB_BRAM;
LB_BUILT_IN : if ( (C_ENABLE_DEBUG_INFO_1 = 0 and C_ENABLE_DEBUG_ALL = 0) )
generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2_8.axi_vdma_afifo_builtin
generic map(
PL_FIFO_TYPE => "BUILT_IN" ,
PL_READ_MODE => "FWFT" ,
PL_FASTER_CLOCK => "WR_CLK" , --RD_CLK
PL_FULL_FLAGS_RST_VAL => 0 , -- ?
PL_DATA_WIDTH => BUFFER_WIDTH ,
C_FAMILY => C_FAMILY ,
PL_FIFO_DEPTH => BUFFER_DEPTH
)
port map(
-- Inputs
rst => s_axis_fifo_ainit_nosync_reg ,
sleep => '0' ,
wr_rst_busy => wr_rst_busy_sig ,
rd_rst_busy => rd_rst_busy_sig ,
wr_clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_clk => m_axis_aclk ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i
);
end generate LB_BUILT_IN;
end generate GEN_ASYNC_FIFO;
-- Generate an SOF on tuser(0). currently vdma only support 1 tuser bit that is set by
-- frame sync and driven out on first data beat of mm2s packet.
GEN_SOF : if ENABLE_FLUSH_ON_FSYNC = 0 and C_MM2S_SOF_ENABLE = 1 generate
--signal sof_reset : std_logic := '0';
begin
sof_reset <= '1' when (s_axis_resetn = '0')
or (dm_halt = '1')
else '0';
-- On frame sync set flag and then clear flag when
-- sof written to fifo.
SOF_FLAG_PROCESS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(sof_reset = '1' or fifo_wren = '1')then
sof_flag <= '0';
elsif(frame_sync = '1')then
sof_flag <= '1';
end if;
end if;
end process SOF_FLAG_PROCESS;
GEN_MM2S_DRE_ENABLED_TKEEP : if C_INCLUDE_MM2S_DRE = 1 generate
begin
-- AXI Slave Side of FIFO
fifo_din <= sof_flag & s_axis_tlast & s_axis_tkeep_signal & s_axis_tdata;
fifo_wren <= s_axis_tvalid and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
s_axis_tready <= s_axis_tready_i; -- CR619293
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready_i and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig and sf_threshold_met;
m_axis_tdata_i <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_i <= fifo_dout(BUFFER_WIDTH-3 downto (BUFFER_WIDTH-3) - (C_DATA_WIDTH/8) + 1);
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-2);
m_axis_tuser_i(0) <= fifo_dout(BUFFER_WIDTH-1);
end generate GEN_MM2S_DRE_ENABLED_TKEEP;
GEN_NO_MM2S_DRE_DISABLE_TKEEP : if C_INCLUDE_MM2S_DRE = 0 generate
begin
-- AXI Slave Side of FIFO
fifo_din <= sof_flag & s_axis_tlast & s_axis_tdata;
fifo_wren <= s_axis_tvalid and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
s_axis_tready <= s_axis_tready_i; -- CR619293
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready_i and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig and sf_threshold_met;
m_axis_tdata_i <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_i <= (others => '1');
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-2);
m_axis_tuser_i(0) <= fifo_dout(BUFFER_WIDTH-1);
end generate GEN_NO_MM2S_DRE_DISABLE_TKEEP;
end generate GEN_SOF;
-- SOF turned off therefore do not generate SOF on tuser
GEN_NO_SOF : if C_MM2S_SOF_ENABLE = 0 generate
begin
GEN_MM2S_DRE_ENABLED_TKEEP : if C_INCLUDE_MM2S_DRE = 1 generate
begin
sof_flag <= '0';
-- AXI Slave Side of FIFO
fifo_din <= s_axis_tlast & s_axis_tkeep_signal & s_axis_tdata;
fifo_wren <= s_axis_tvalid and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
s_axis_tready <= s_axis_tready_i; -- CR619293
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready_i and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig and sf_threshold_met;
m_axis_tdata_i <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_i <= fifo_dout(BUFFER_WIDTH-2 downto (BUFFER_WIDTH-2) - (C_DATA_WIDTH/8) + 1);
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-1);
m_axis_tuser_i <= (others => '0');
end generate GEN_MM2S_DRE_ENABLED_TKEEP;
GEN_NO_MM2S_DRE_DISABLE_TKEEP : if C_INCLUDE_MM2S_DRE = 0 generate
begin
sof_flag <= '0';
-- AXI Slave Side of FIFO
fifo_din <= s_axis_tlast & s_axis_tdata;
fifo_wren <= s_axis_tvalid and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
s_axis_tready <= s_axis_tready_i; -- CR619293
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready_i and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig and sf_threshold_met;
m_axis_tdata_i <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_i <= (others => '1');
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-1);
m_axis_tuser_i <= (others => '0');
end generate GEN_NO_MM2S_DRE_DISABLE_TKEEP;
end generate GEN_NO_SOF;
-- Top level line buffer depth not equal to zero therefore gererate threshold
-- flags. (CR625142)
GEN_THRESHOLD_ENABLED : if C_TOPLVL_LINEBUFFER_DEPTH /= 0 and (C_ENABLE_DEBUG_INFO_1 = 1 or C_ENABLE_DEBUG_ALL = 1) generate
begin
-- Almost empty flag (note: asserts when empty also)
REG_ALMST_EMPTY : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
fifo_almost_empty_reg <= '1';
--elsif(fifo_rdcount(DATACOUNT_WIDTH-1 downto 0) <= DATA_COUNT_AE_THRESHOLD or fifo_empty_i = '1')then
--elsif((fifo_rdcount(DATACOUNT_WIDTH-1 downto 0) <= m_data_count_ae_thresh
-- or fifo_empty_i = '1') and fifo_full_i = '0')then
elsif((fifo_rdcount(DATACOUNT_WIDTH-1 downto 0) <= m_data_count_ae_thresh
or (fifo_empty_i = '1' or rd_rst_busy_sig = '1')))then
fifo_almost_empty_reg <= '1';
else
fifo_almost_empty_reg <= '0';
end if;
end if;
end process REG_ALMST_EMPTY;
mm2s_fifo_almost_empty <= fifo_almost_empty_reg
or (not sf_threshold_met) -- CR622777
or (not m_axis_tvalid_out); -- CR625724
mm2s_fifo_empty <= not m_axis_tvalid_out;
end generate GEN_THRESHOLD_ENABLED;
-- Top level line buffer depth is zero therefore turn off threshold logic.
-- this occurs for async operation where the async fifo is needed for CDC (CR625142)
GEN_THRESHOLD_DISABLED : if C_TOPLVL_LINEBUFFER_DEPTH = 0 or (C_ENABLE_DEBUG_INFO_1 = 0 and C_ENABLE_DEBUG_ALL = 0) generate
begin
mm2s_fifo_empty <= '0';
mm2s_fifo_almost_empty <= '0';
fifo_almost_empty_reg <= '0';
end generate GEN_THRESHOLD_DISABLED;
-- CR#578903
-- FIFO, FIFO Pipe, and Skid Buffer are all empty. This is used to safely
-- assert reset on shutdown and also used to safely generate fsync in free-run mode
-- CR622702 - need to look at write side of fifo to prevent false empties due to async fifo
--fifo_pipe_empty <= '1' when (fifo_wrcount(DATACOUNT_WIDTH-1 downto 0) = DATA_COUNT_ZERO -- Data count is 0
-- and m_axis_tvalid_out = '0') -- Skid Buffer is done
-- -- Forced stop and Threshold not met (CR623291)
-- or (sf_threshold_met = '0' and stop_reg = '1')
-- else '0';
-- CR623879 fixed flase fifo_pipe_assertions due to extreme AXI4 throttling on
-- mm2s reads causing fifo to go empty for extended periods of time. This then
-- caused flase idles to be flagged and frame syncs were then generated in free run mode
-------- fifo_pipe_empty <= '1' when (all_lines_xfred = '1' and m_axis_tvalid_out = '0') -- All data for frame transmitted
-------- or (sf_threshold_met = '0' -- Or Threshold not met
-------- and stop_reg = '1' -- Commanded to stop
-------- and m_axis_tvalid_out = '0') -- And NOT driving tvalid
-------- else '0';
--------
-- If store and forward is turned on by user then gate tvalid with
-- threshold met
GEN_THRESH_MET_FOR_SNF : if C_INCLUDE_MM2S_SF = 1 and C_TOPLVL_LINEBUFFER_DEPTH /= 0 and (C_ENABLE_DEBUG_INFO_1 = 1 or C_ENABLE_DEBUG_ALL = 1) generate
begin
-- Register fifo_almost empty in order to generate
-- almost empty fall edge pulse
REG_ALMST_EMPTY_FE : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
fifo_almost_empty_d1 <= '1';
else
fifo_almost_empty_d1 <= fifo_almost_empty_reg;
end if;
end if;
end process REG_ALMST_EMPTY_FE;
-- Almost empty falling edge
fifo_almost_empty_fe <= not fifo_almost_empty_reg and fifo_almost_empty_d1;
-- Store and Forward threshold met
THRESH_MET : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
sf_threshold_met <= '0';
elsif(fsync_out = '1')then
sf_threshold_met <= '0';
-- Reached threshold or all reads done for the frame
elsif(fifo_almost_empty_fe = '1'
or (dm_xfred_all_lines_reg = '1'))then
sf_threshold_met <= '1';
end if;
end if;
end process THRESH_MET;
end generate GEN_THRESH_MET_FOR_SNF;
-- Store and forward off therefore do not need to meet threshold
GEN_NO_THRESH_MET_FOR_SNF : if C_INCLUDE_MM2S_SF = 0 or C_TOPLVL_LINEBUFFER_DEPTH = 0 or (C_ENABLE_DEBUG_INFO_1 = 0 and C_ENABLE_DEBUG_ALL = 0) generate
begin
sf_threshold_met <= '1';
end generate GEN_NO_THRESH_MET_FOR_SNF;
--*********************************************************--
--** MM2S MASTER SKID BUFFER **--
--*********************************************************--
I_MSTR_SKID : entity axi_vdma_v6_2_8.axi_vdma_skid_buf
generic map(
C_WDATA_WIDTH => C_DATA_WIDTH ,
C_TUSER_WIDTH => C_M_AXIS_MM2S_TUSER_BITS
)
port map(
-- System Ports
ACLK => m_axis_aclk ,
ARST => m_axis_fifo_ainit_nosync ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => '0' ,
-- Slave Side (Stream Data Input)
S_VALID => m_axis_tvalid_i ,
S_READY => m_axis_tready_i ,
S_Data => m_axis_tdata_i ,
S_STRB => m_axis_tkeep_i ,
S_Last => m_axis_tlast_i ,
S_User => m_axis_tuser_i ,
-- Master Side (Stream Data Output)
M_VALID => m_axis_tvalid_out ,
M_READY => m_axis_tready ,
M_Data => m_axis_tdata ,
M_STRB => m_axis_tkeep_signal ,
M_Last => m_axis_tlast_out ,
M_User => m_axis_tuser
);
-- Pass out of core
m_axis_tvalid <= m_axis_tvalid_out;
m_axis_tlast <= m_axis_tlast_out;
-- Register to break long timing paths for use in
-- transfer complete generation
REG_STRM_SIGS : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
m_axis_tlast_d1 <= '0';
m_axis_tvalid_d1 <= '0';
m_axis_tready_d1 <= '0';
else
m_axis_tlast_d1 <= m_axis_tlast_out;
m_axis_tvalid_d1 <= m_axis_tvalid_out;
m_axis_tready_d1 <= m_axis_tready;
end if;
end if;
end process REG_STRM_SIGS;
end generate GEN_LINEBUFFER;
--*****************************************************************************--
--** NO LINE BUFFER MODE (Sync Only) **--
--*****************************************************************************--
-- LineBuffer forced on if asynchronous mode is enabled
GEN_NO_LINEBUFFER : if (C_LINEBUFFER_DEPTH = 0) generate -- No Line Buffer
begin
-- Map Datamover to AXIS Master Out
m_axis_tdata <= s_axis_tdata;
m_axis_tkeep_signal <= s_axis_tkeep_signal;
m_axis_tvalid <= s_axis_tvalid;
m_axis_tlast <= s_axis_tlast;
s_axis_tready <= m_axis_tready;
-- Tie FIFO Flags off
mm2s_fifo_empty <= '0';
mm2s_fifo_almost_empty <= '0';
-- Generate sof on tuser(0)
GEN_SOF : if C_MM2S_SOF_ENABLE = 1 generate
begin
-- On frame sync set flag and then clear flag when
-- sof written to fifo.
SOF_FLAG_PROCESS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit = '1' or (s_axis_tvalid = '1' and m_axis_tready = '1'))then
sof_flag <= '0';
elsif(frame_sync = '1')then
sof_flag <= '1';
end if;
end if;
end process SOF_FLAG_PROCESS;
m_axis_tuser(0) <= sof_flag;
end generate GEN_SOF;
-- Do not generate sof on tuser(0)
GEN_NO_SOF : if C_MM2S_SOF_ENABLE = 0 generate
begin
sof_flag <= '0';
m_axis_tuser <= (others => '0');
end generate GEN_NO_SOF;
-- CR#578903
-- Register tvalid to break timing paths for use in
-- psuedo fifo empty for channel idle generation and
-- for xfer complete generation.
REG_STRM_SIGS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
m_axis_tvalid_d1 <= '0';
m_axis_tlast_d1 <= '0';
m_axis_tready_d1 <= '0';
else
m_axis_tvalid_d1 <= s_axis_tvalid;
m_axis_tlast_d1 <= s_axis_tlast;
m_axis_tready_d1 <= m_axis_tready;
end if;
end if;
end process REG_STRM_SIGS;
-- CR#578903
-- Psuedo FIFO, FIFO Pipe, and Skid Buffer are all empty. This is used to safely
-- assert reset on shutdown and also used to safely generate fsync in free-run mode
-- This flag is looked at at the end of frames.
-- Order of else-if is critical
-- CR579191 modified method to prevent double fsync assertions
REG_PIPE_EMPTY : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
fifo_pipe_empty <= '1';
-- Command/Status not idle indicates pending datamover commands
-- set psuedo fifo empty to NOT empty.
elsif(cmdsts_idle_fe = '1')then
fifo_pipe_empty <= '0';
-- On accepted tlast then clear psuedo empty flag back to being empty
elsif(pot_empty = '1' and cmdsts_idle = '1')then
fifo_pipe_empty <= '1';
end if;
end if;
end process REG_PIPE_EMPTY;
REG_IDLE_FE : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
cmdsts_idle_d1 <= '1';
else
cmdsts_idle_d1 <= cmdsts_idle;
end if;
end if;
end process REG_IDLE_FE;
-- CR579586 Use falling edge to set pfifo empty
cmdsts_idle_fe <= not cmdsts_idle and cmdsts_idle_d1;
-- CR579191
POTENTIAL_EMPTY_PROCESS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
pot_empty <= '1';
elsif(m_axis_tvalid_d1 = '1' and m_axis_tlast_d1 = '1' and m_axis_tready_d1 = '1')then
pot_empty <= '1';
elsif(m_axis_tvalid_d1 = '1' and m_axis_tlast_d1 = '0')then
pot_empty <= '0';
end if;
end if;
end process POTENTIAL_EMPTY_PROCESS;
end generate GEN_NO_LINEBUFFER;
--*****************************************************************************--
--** MM2S ASYNCH CLOCK SUPPORT **--
--*****************************************************************************--
-- Cross fifo pipe empty flag to secondary clock domain
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Pipe Empty and Shutdown reset CDC
---- SHUTDOWN_RST_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => fifo_pipe_empty ,
---- scndry_out => mm2s_fifo_pipe_empty_i ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
SHUTDOWN_RST_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => fifo_pipe_empty,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => mm2s_fifo_pipe_empty_i,
scndry_vect_out => open
);
-- Vertical Count and All Lines Transferred CDC (CR616211)
---- ALL_LINES_XFRED_P_S_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' , -- CR619293
---- prmry_out => open , -- CR619293
---- prmry_in => all_lines_xfred ,
---- scndry_out => mm2s_all_lines_xfred ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
----
ALL_LINES_XFRED_P_S_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => all_lines_xfred,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => mm2s_all_lines_xfred,
scndry_vect_out => open
);
-- Vertical Count and All Lines Transferred CDC (CR616211)
---- ALL_LINES_XFRED_S_P_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => dm_xfred_all_lines , -- CR619293
---- prmry_out => dm_xfred_all_lines_reg , -- CR619293
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
ALL_LINES_XFRED_S_P_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => dm_xfred_all_lines,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => dm_xfred_all_lines_reg,
scndry_vect_out => open
);
VSIZE_CNT_CROSSING : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
crnt_vsize_cdc_tig <= crnt_vsize;
crnt_vsize_d1 <= crnt_vsize_cdc_tig;
end if;
end process VSIZE_CNT_CROSSING;
crnt_vsize_d2 <= crnt_vsize_d1;
-- Cross stop signal (CR623291)
---- STOP_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => stop ,
---- prmry_out => stop_reg ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
STOP_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => stop,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => stop_reg,
scndry_vect_out => open
);
-- Cross datamover halt and threshold signals
---- HALT_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => dm_halt ,
---- prmry_out => dm_halt_reg ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- scndry_vect_out => open
---- );
----
HALT_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => dm_halt,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => dm_halt_reg,
scndry_vect_out => open
);
THRESH_CNT_CROSSING : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
data_count_ae_threshold_cdc_tig <= data_count_ae_threshold;
data_count_ae_threshold_d1 <= data_count_ae_threshold_cdc_tig;
end if;
end process THRESH_CNT_CROSSING;
m_data_count_ae_thresh <= data_count_ae_threshold_d1;
end generate GEN_FOR_ASYNC;
--*****************************************************************************--
--** MM2S SYNCH CLOCK SUPPORT **--
--*****************************************************************************--
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
mm2s_fifo_pipe_empty_i <= fifo_pipe_empty;
crnt_vsize_d2 <= crnt_vsize; -- CR616211
mm2s_all_lines_xfred <= all_lines_xfred; -- CR616211
dm_xfred_all_lines_reg <= dm_xfred_all_lines; -- CR619293
stop_reg <= stop; -- CR623291
dm_halt_reg <= dm_halt;
m_data_count_ae_thresh <= data_count_ae_threshold;
end generate GEN_FOR_SYNC;
--*****************************************************************************
--** Vertical Line Tracking (CR616211)
--*****************************************************************************
-- Decrement vertical count with each accept tlast
decr_vcount <= '1' when m_axis_tlast_d1 = '1'
and m_axis_tvalid_d1 = '1'
and m_axis_tready_d1 = '1'
else '0';
-- Drive ready at fsync out then de-assert once all lines have
-- been accepted.
VERT_COUNTER : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1' and fsync_out = '0')then
vsize_counter <= (others => '0');
all_lines_xfred <= '1';
elsif(fsync_out = '1')then
vsize_counter <= crnt_vsize_d2;
all_lines_xfred <= '0';
elsif(decr_vcount = '1' and vsize_counter = VSIZE_ONE_VALUE)then
vsize_counter <= (others => '0');
all_lines_xfred <= '1';
elsif(decr_vcount = '1' and vsize_counter /= VSIZE_ZERO_VALUE)then
vsize_counter <= std_logic_vector(unsigned(vsize_counter) - 1);
all_lines_xfred <= '0';
end if;
end if;
end process VERT_COUNTER;
-- Store and forward or no line buffer (CR619293)
GEN_VCOUNT_FOR_SNF : if C_LINEBUFFER_DEPTH /= 0 and C_INCLUDE_MM2S_SF = 1 generate
begin
dm_decr_vcount <= '1' when s_axis_tlast = '1'
and s_axis_tvalid = '1'
and s_axis_tready_i = '1'
else '0';
-- Delay 1 pipe to align with cnrt_vsize
REG_FSYNC_TO_ALIGN : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit = '1' and frame_sync = '0')then
frame_sync_d1 <= '0';
else
frame_sync_d1 <= frame_sync;
end if;
end if;
end process REG_FSYNC_TO_ALIGN;
-- Count lines to determine when datamover done. Used for snf mode
-- for threshold met (CR619293)
DM_DONE : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit = '1')then
dm_vsize_counter <= (others => '0');
dm_xfred_all_lines <= '0';
--elsif(fsync_out = '1')then -- CR623088
elsif(frame_sync_d1 = '1')then -- CR623088
dm_vsize_counter <= crnt_vsize;
dm_xfred_all_lines <= '0';
elsif(dm_decr_vcount = '1' and dm_vsize_counter = VSIZE_ONE_VALUE)then
dm_vsize_counter <= (others => '0');
dm_xfred_all_lines <= '1';
elsif(dm_decr_vcount = '1' and dm_vsize_counter /= VSIZE_ZERO_VALUE)then
dm_vsize_counter <= std_logic_vector(unsigned(dm_vsize_counter) - 1);
dm_xfred_all_lines <= '0';
end if;
end if;
end process DM_DONE;
end generate GEN_VCOUNT_FOR_SNF;
-- Not store and forward or no line buffer (CR619293)
GEN_NO_VCOUNT_FOR_SNF : if C_LINEBUFFER_DEPTH = 0 or C_INCLUDE_MM2S_SF = 0 generate
begin
dm_vsize_counter <= (others => '0');
dm_xfred_all_lines <= '0';
dm_decr_vcount <= '0';
end generate GEN_NO_VCOUNT_FOR_SNF;
--*****************************************************************************--
--** SPECIAL RESET GENERATION **--
--*****************************************************************************--
-- Assert reset to skid buffer on hard reset or on shutdown when fifo pipe empty
-- Waiting for fifo_pipe_empty is required to prevent a AXIS protocol violation
-- when channel shut down early
REG_SKID_RESET : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_resetn = '0')then
m_skid_reset <= '1';
elsif(fifo_pipe_empty = '1')then
if(fsync_out = '1' or dm_halt_reg = '1')then
m_skid_reset <= '1';
else
m_skid_reset <= '0';
end if;
else
m_skid_reset <= '0';
end if;
end if;
end process REG_SKID_RESET;
-- Fifo/logic reset for slave side clock domain (m_axi_mm2s_aclk)
-- If error (dm_halt=1) then halt immediatly without protocol violation
s_axis_fifo_ainit <= '1' when s_axis_resetn = '0'
or frame_sync = '1' -- Frame sync
or dm_halt = '1' -- Datamover being halted (halt due to error)
else '0';
-- Fifo/logic reset for master side clock domain (m_axis_mm2s_aclk)
m_axis_fifo_ainit <= '1' when m_axis_resetn = '0'
or fsync_out = '1' -- Frame sync
or dm_halt_reg = '1' -- Datamover being halted
else '0';
-- Fifo/logic reset for slave side clock domain (m_axi_mm2s_aclk)
-- If error (dm_halt=1) then halt immediatly without protocol violation
s_axis_fifo_ainit_nosync <= '1' when s_axis_resetn = '0'
or dm_halt = '1' -- Datamover being halted (halt due to error)
else '0';
process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
s_axis_fifo_ainit_nosync_reg <= s_axis_fifo_ainit_nosync;
end if;
end process ;
-- Fifo/logic reset for master side clock domain (m_axis_mm2s_aclk)
m_axis_fifo_ainit_nosync <= '1' when m_axis_resetn = '0'
or dm_halt_reg = '1' -- Datamover being halted
else '0';
--reset for axis_dwidth
mm2s_axis_linebuf_reset_out_inv <= m_axis_fifo_ainit_nosync;
mm2s_axis_linebuf_reset_out <= not (mm2s_axis_linebuf_reset_out_inv);
MM2S_DWIDTH_CONV_IS : if (C_DATA_WIDTH /= C_M_AXIS_MM2S_TDATA_WIDTH) generate
begin
fifo_pipe_empty <= dwidth_fifo_pipe_empty;
dwidth_fifo_pipe_empty_m <= mm2s_fifo_pipe_empty_i;
end generate MM2S_DWIDTH_CONV_IS;
MM2S_DWIDTH_CONV_IS_NOT : if (C_DATA_WIDTH = C_M_AXIS_MM2S_TDATA_WIDTH) generate
begin
fifo_pipe_empty <= '1' when (all_lines_xfred = '1' and m_axis_tvalid_out = '0') -- All data for frame transmitted
or (sf_threshold_met = '0' -- Or Threshold not met
and stop_reg = '1' -- Commanded to stop
and m_axis_tvalid_out = '0') -- And NOT driving tvalid
else '0';
dwidth_fifo_pipe_empty_m <= '1';
end generate MM2S_DWIDTH_CONV_IS_NOT;
mm2s_all_lines_xfred_s <= '0';
fsync_out_m <= '0';
mm2s_vsize_cntr_clr_flag <= '0';
mm2s_fsize_mismatch_err_m <= '0';
end generate GEN_LINEBUF_NO_SOF;
GEN_LINEBUF_FLUSH_SOF : if (ENABLE_FLUSH_ON_FSYNC = 1 and C_MM2S_SOF_ENABLE = 1) generate
signal s2mm_fsync_mm2s_s : std_logic := '0';
signal run_stop_reg : std_logic := '0';
signal fsync_out_d1 : std_logic := '0';
signal mm2s_fsync_int : std_logic := '0';
signal fsize_mismatch_err_int_s : std_logic := '0';
signal fsize_mismatch_err_int_m : std_logic := '0';
signal fsize_mismatch_err_flag_s : std_logic := '0';
signal fsize_mismatch_err_flag_vsize_cntr_clr : std_logic := '0';
signal fsize_mismatch_err_flag_cmb_s : std_logic := '0';
signal fsync_src_select_cdc_tig : std_logic_vector(1 downto 0) := (others => '0');
signal fsync_src_select_d1 : std_logic_vector(1 downto 0) := (others => '0');
signal fsync_src_select_s_int : std_logic_vector(1 downto 0) := (others => '0');
signal fsize_err_to_dm_halt_flag : std_logic := '0';
signal fsize_err_to_dm_halt_flag_ored : std_logic := '0';
signal delay_fsync_fsize_err_till_dm_halt_cmplt_pulse_s : std_logic := '0';
signal delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s : std_logic := '0';
signal delay_fsync_fsize_err_till_dm_halt_cmplt_s_d1 : std_logic := '0';
signal d_fsync_halt_cmplt_s : std_logic := '0';
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF fsync_src_select_cdc_tig : SIGNAL IS "true";
ATTRIBUTE async_reg OF fsync_src_select_d1 : SIGNAL IS "true";
begin
--*****************************************************************************--
--** LINE BUFFER MODE (Sync or Async) **--
--*****************************************************************************--
GEN_LINEBUFFER : if C_LINEBUFFER_DEPTH /= 0 generate
begin
-- Divide by number bytes per data beat and add padding to dynamic
-- threshold setting
data_count_ae_threshold <= linebuf_threshold((DATACOUNT_WIDTH-1) + THRESHOLD_LSB_INDEX
downto THRESHOLD_LSB_INDEX);
-- Synchronous clock therefore instantiate an Asynchronous FIFO
GEN_SYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2_8.axi_vdma_sfifo
generic map(
UW_DATA_WIDTH => BUFFER_WIDTH ,
C_FULL_FLAGS_RST_VAL => 1 ,
UW_FIFO_DEPTH => BUFFER_DEPTH ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
rst => s_axis_fifo_ainit_nosync ,
sleep => '0' ,
wr_rst_busy => wr_rst_busy_sig ,
rd_rst_busy => rd_rst_busy_sig ,
clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i ,
data_count => fifo_rdcount
);
--wr_rst_busy_sig <= '0';
--rd_rst_busy_sig <= '0';
end generate GEN_SYNC_FIFO;
-- Asynchronous clock therefore instantiate an Asynchronous FIFO
GEN_ASYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
LB_BRAM : if ( (C_ENABLE_DEBUG_INFO_1 = 1 or C_ENABLE_DEBUG_ALL = 1) )
generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2_8.axi_vdma_afifo
generic map(
UW_DATA_WIDTH => BUFFER_WIDTH ,
C_FULL_FLAGS_RST_VAL => 1 ,
UW_FIFO_DEPTH => BUFFER_DEPTH ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
rst => s_axis_fifo_ainit_nosync_reg ,
sleep => '0' ,
wr_rst_busy => open ,
rd_rst_busy => open ,
wr_clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_clk => m_axis_aclk ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i ,
wr_data_count => open , --CR622702
rd_data_count => fifo_rdcount
);
wr_rst_busy_sig <= '0';
rd_rst_busy_sig <= '0';
end generate LB_BRAM;
LB_BUILT_IN : if ( (C_ENABLE_DEBUG_INFO_1 = 0 and C_ENABLE_DEBUG_ALL = 0) )
generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2_8.axi_vdma_afifo_builtin
generic map(
PL_FIFO_TYPE => "BUILT_IN" ,
PL_READ_MODE => "FWFT" ,
PL_FASTER_CLOCK => "WR_CLK" , --RD_CLK
PL_FULL_FLAGS_RST_VAL => 0 , -- ?
PL_DATA_WIDTH => BUFFER_WIDTH ,
C_FAMILY => C_FAMILY ,
PL_FIFO_DEPTH => BUFFER_DEPTH
)
port map(
-- Inputs
rst => s_axis_fifo_ainit_nosync_reg ,
sleep => '0' ,
wr_rst_busy => wr_rst_busy_sig ,
rd_rst_busy => rd_rst_busy_sig ,
wr_clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_clk => m_axis_aclk ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i
);
end generate LB_BUILT_IN;
end generate GEN_ASYNC_FIFO;
-- Generate an SOF on tuser(0). currently vdma only support 1 tuser bit that is set by
-- frame sync and driven out on first data beat of mm2s packet.
------ GEN_SOF : if C_MM2S_SOF_ENABLE = 1 generate
------ signal sof_reset : std_logic := '0';
------ begin
sof_reset <= '1' when (s_axis_resetn = '0')
or (dm_halt = '1')
else '0';
-- On frame sync set flag and then clear flag when
-- sof written to fifo.
SOF_FLAG_PROCESS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(sof_reset = '1' or fifo_wren = '1')then
sof_flag <= '0';
elsif(frame_sync = '1')then
sof_flag <= '1';
end if;
end if;
end process SOF_FLAG_PROCESS;
GEN_MM2S_DRE_ENABLED_TKEEP : if C_INCLUDE_MM2S_DRE = 1 generate
begin
-- AXI Slave Side of FIFO
fifo_din <= sof_flag & s_axis_tlast & s_axis_tkeep_signal & s_axis_tdata;
fifo_wren <= s_axis_tvalid and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
s_axis_tready <= s_axis_tready_i; -- CR619293
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready_i and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig and sf_threshold_met;
m_axis_tdata_i <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_i <= fifo_dout(BUFFER_WIDTH-3 downto (BUFFER_WIDTH-3) - (C_DATA_WIDTH/8) + 1);
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-2);
m_axis_tuser_i(0) <= fifo_dout(BUFFER_WIDTH-1);
end generate GEN_MM2S_DRE_ENABLED_TKEEP;
GEN_NO_MM2S_DRE_DISABLE_TKEEP : if C_INCLUDE_MM2S_DRE = 0 generate
begin
-- AXI Slave Side of FIFO
fifo_din <= sof_flag & s_axis_tlast & s_axis_tdata;
fifo_wren <= s_axis_tvalid and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
s_axis_tready <= s_axis_tready_i; -- CR619293
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready_i and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig and sf_threshold_met;
m_axis_tdata_i <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_i <= (others => '1');
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-2);
m_axis_tuser_i(0) <= fifo_dout(BUFFER_WIDTH-1);
end generate GEN_NO_MM2S_DRE_DISABLE_TKEEP;
------ end generate GEN_SOF;
------
------
-- SOF turned off therefore do not generate SOF on tuser
---------- GEN_NO_SOF : if C_MM2S_SOF_ENABLE = 0 generate
---------- begin
----------
---------- sof_flag <= '0';
----------
---------- -- AXI Slave Side of FIFO
---------- fifo_din <= s_axis_tlast & s_axis_tkeep & s_axis_tdata;
---------- fifo_wren <= s_axis_tvalid and not fifo_full_i and not s_axis_fifo_ainit;
---------- s_axis_tready_i <= not fifo_full_i and not s_axis_fifo_ainit;
---------- s_axis_tready <= s_axis_tready_i; -- CR619293
----------
---------- -- AXI Master Side of FIFO
---------- fifo_rden <= m_axis_tready_i and not fifo_empty_i and sf_threshold_met;
---------- m_axis_tvalid_i <= not fifo_empty_i and sf_threshold_met;
---------- m_axis_tdata_i <= fifo_dout(C_DATA_WIDTH-1 downto 0);
---------- m_axis_tkeep_i <= fifo_dout(BUFFER_WIDTH-2 downto (BUFFER_WIDTH-2) - (C_DATA_WIDTH/8) + 1);
---------- m_axis_tlast_i <= not fifo_empty_i and fifo_dout(BUFFER_WIDTH-1);
---------- m_axis_tuser_i <= (others => '0');
----------
---------- end generate GEN_NO_SOF;
-- Top level line buffer depth not equal to zero therefore gererate threshold
-- flags. (CR625142)
GEN_THRESHOLD_ENABLED : if C_TOPLVL_LINEBUFFER_DEPTH /= 0 and (C_ENABLE_DEBUG_INFO_1 = 1 or C_ENABLE_DEBUG_ALL = 1) generate
begin
-- Almost empty flag (note: asserts when empty also)
REG_ALMST_EMPTY : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
fifo_almost_empty_reg <= '1';
--elsif(fifo_rdcount(DATACOUNT_WIDTH-1 downto 0) <= DATA_COUNT_AE_THRESHOLD or fifo_empty_i = '1')then
--elsif((fifo_rdcount(DATACOUNT_WIDTH-1 downto 0) <= m_data_count_ae_thresh
-- or fifo_empty_i = '1') and fifo_full_i = '0')then
elsif((fifo_rdcount(DATACOUNT_WIDTH-1 downto 0) <= m_data_count_ae_thresh
or (fifo_empty_i = '1' or rd_rst_busy_sig = '1')))then
fifo_almost_empty_reg <= '1';
else
fifo_almost_empty_reg <= '0';
end if;
end if;
end process REG_ALMST_EMPTY;
mm2s_fifo_almost_empty <= fifo_almost_empty_reg
or (not sf_threshold_met) -- CR622777
or (not m_axis_tvalid_out); -- CR625724
mm2s_fifo_empty <= not m_axis_tvalid_out;
end generate GEN_THRESHOLD_ENABLED;
-- Top level line buffer depth is zero therefore turn off threshold logic.
-- this occurs for async operation where the async fifo is needed for CDC (CR625142)
GEN_THRESHOLD_DISABLED : if C_TOPLVL_LINEBUFFER_DEPTH = 0 or (C_ENABLE_DEBUG_INFO_1 = 0 and C_ENABLE_DEBUG_ALL = 0) generate
begin
mm2s_fifo_empty <= '0';
mm2s_fifo_almost_empty <= '0';
fifo_almost_empty_reg <= '0';
end generate GEN_THRESHOLD_DISABLED;
-- CR#578903
-- FIFO, FIFO Pipe, and Skid Buffer are all empty. This is used to safely
-- assert reset on shutdown and also used to safely generate fsync in free-run mode
-- CR622702 - need to look at write side of fifo to prevent false empties due to async fifo
--fifo_pipe_empty <= '1' when (fifo_wrcount(DATACOUNT_WIDTH-1 downto 0) = DATA_COUNT_ZERO -- Data count is 0
-- and m_axis_tvalid_out = '0') -- Skid Buffer is done
-- -- Forced stop and Threshold not met (CR623291)
-- or (sf_threshold_met = '0' and stop_reg = '1')
-- else '0';
-- CR623879 fixed flase fifo_pipe_assertions due to extreme AXI4 throttling on
-- mm2s reads causing fifo to go empty for extended periods of time. This then
-- caused flase idles to be flagged and frame syncs were then generated in free run mode
---------------- fifo_pipe_empty <= '1' when (all_lines_xfred = '1' and m_axis_tvalid_out = '0') -- All data for frame transmitted
---------------- or (sf_threshold_met = '0' -- Or Threshold not met
---------------- and stop_reg = '1' -- Commanded to stop
---------------- and m_axis_tvalid_out = '0') -- And NOT driving tvalid
---------------- else '0';
----------------
-- If store and forward is turned on by user then gate tvalid with
-- threshold met
GEN_THRESH_MET_FOR_SNF : if C_INCLUDE_MM2S_SF = 1 and C_TOPLVL_LINEBUFFER_DEPTH /= 0 and (C_ENABLE_DEBUG_INFO_1 = 1 or C_ENABLE_DEBUG_ALL = 1) generate
begin
-- Register fifo_almost empty in order to generate
-- almost empty fall edge pulse
REG_ALMST_EMPTY_FE : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
fifo_almost_empty_d1 <= '1';
else
fifo_almost_empty_d1 <= fifo_almost_empty_reg;
end if;
end if;
end process REG_ALMST_EMPTY_FE;
-- Almost empty falling edge
fifo_almost_empty_fe <= not fifo_almost_empty_reg and fifo_almost_empty_d1;
-- Store and Forward threshold met
THRESH_MET : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
sf_threshold_met <= '0';
elsif(fsync_out = '1')then
sf_threshold_met <= '0';
-- Reached threshold or all reads done for the frame
elsif(fifo_almost_empty_fe = '1'
or (dm_xfred_all_lines_reg = '1'))then
sf_threshold_met <= '1';
end if;
end if;
end process THRESH_MET;
end generate GEN_THRESH_MET_FOR_SNF;
-- Store and forward off therefore do not need to meet threshold
GEN_NO_THRESH_MET_FOR_SNF : if C_INCLUDE_MM2S_SF = 0 or C_TOPLVL_LINEBUFFER_DEPTH = 0 or (C_ENABLE_DEBUG_INFO_1 = 0 and C_ENABLE_DEBUG_ALL = 0) generate
begin
sf_threshold_met <= '1';
end generate GEN_NO_THRESH_MET_FOR_SNF;
--*********************************************************--
--** MM2S MASTER SKID BUFFER **--
--*********************************************************--
I_MSTR_SKID : entity axi_vdma_v6_2_8.axi_vdma_skid_buf
generic map(
C_WDATA_WIDTH => C_DATA_WIDTH ,
C_TUSER_WIDTH => C_M_AXIS_MM2S_TUSER_BITS
)
port map(
-- System Ports
ACLK => m_axis_aclk ,
ARST => m_axis_fifo_ainit_nosync ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => '0' ,
-- Slave Side (Stream Data Input)
S_VALID => m_axis_tvalid_i ,
S_READY => m_axis_tready_i ,
S_Data => m_axis_tdata_i ,
S_STRB => m_axis_tkeep_i ,
S_Last => m_axis_tlast_i ,
S_User => m_axis_tuser_i ,
-- Master Side (Stream Data Output)
M_VALID => m_axis_tvalid_out ,
M_READY => m_axis_tready ,
M_Data => m_axis_tdata ,
M_STRB => m_axis_tkeep_signal ,
M_Last => m_axis_tlast_out ,
M_User => m_axis_tuser
);
-- Pass out of core
m_axis_tvalid <= m_axis_tvalid_out;
m_axis_tlast <= m_axis_tlast_out;
-- Register to break long timing paths for use in
-- transfer complete generation
REG_STRM_SIGS : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
m_axis_tlast_d1 <= '0';
m_axis_tvalid_d1 <= '0';
m_axis_tready_d1 <= '0';
else
m_axis_tlast_d1 <= m_axis_tlast_out;
m_axis_tvalid_d1 <= m_axis_tvalid_out;
m_axis_tready_d1 <= m_axis_tready;
end if;
end if;
end process REG_STRM_SIGS;
end generate GEN_LINEBUFFER;
--*****************************************************************************--
--** NO LINE BUFFER MODE (Sync Only) **--
--*****************************************************************************--
-- LineBuffer forced on if asynchronous mode is enabled
GEN_NO_LINEBUFFER : if (C_LINEBUFFER_DEPTH = 0) generate -- No Line Buffer
begin
-- Map Datamover to AXIS Master Out
m_axis_tdata <= s_axis_tdata;
m_axis_tkeep_signal <= s_axis_tkeep_signal;
m_axis_tvalid <= s_axis_tvalid;
m_axis_tlast <= s_axis_tlast;
s_axis_tready <= m_axis_tready;
-- Tie FIFO Flags off
mm2s_fifo_empty <= '0';
mm2s_fifo_almost_empty <= '0';
-- Generate sof on tuser(0)
---- GEN_SOF : if C_MM2S_SOF_ENABLE = 1 generate
--- begin
-- On frame sync set flag and then clear flag when
-- sof written to fifo.
SOF_FLAG_PROCESS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit = '1' or (s_axis_tvalid = '1' and m_axis_tready = '1'))then
sof_flag <= '0';
elsif(frame_sync = '1')then
sof_flag <= '1';
end if;
end if;
end process SOF_FLAG_PROCESS;
m_axis_tuser(0) <= sof_flag;
--- end generate GEN_SOF;
-- Do not generate sof on tuser(0)
----- GEN_NO_SOF : if C_MM2S_SOF_ENABLE = 0 generate
----- begin
----- sof_flag <= '0';
----- m_axis_tuser <= (others => '0');
----- end generate GEN_NO_SOF;
-- CR#578903
-- Register tvalid to break timing paths for use in
-- psuedo fifo empty for channel idle generation and
-- for xfer complete generation.
REG_STRM_SIGS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
m_axis_tvalid_d1 <= '0';
m_axis_tlast_d1 <= '0';
m_axis_tready_d1 <= '0';
else
m_axis_tvalid_d1 <= s_axis_tvalid;
m_axis_tlast_d1 <= s_axis_tlast;
m_axis_tready_d1 <= m_axis_tready;
end if;
end if;
end process REG_STRM_SIGS;
-- CR#578903
-- Psuedo FIFO, FIFO Pipe, and Skid Buffer are all empty. This is used to safely
-- assert reset on shutdown and also used to safely generate fsync in free-run mode
-- This flag is looked at at the end of frames.
-- Order of else-if is critical
-- CR579191 modified method to prevent double fsync assertions
REG_PIPE_EMPTY : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
fifo_pipe_empty <= '1';
-- Command/Status not idle indicates pending datamover commands
-- set psuedo fifo empty to NOT empty.
elsif(cmdsts_idle_fe = '1')then
fifo_pipe_empty <= '0';
-- On accepted tlast then clear psuedo empty flag back to being empty
elsif(pot_empty = '1' and cmdsts_idle = '1')then
fifo_pipe_empty <= '1';
end if;
end if;
end process REG_PIPE_EMPTY;
REG_IDLE_FE : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
cmdsts_idle_d1 <= '1';
else
cmdsts_idle_d1 <= cmdsts_idle;
end if;
end if;
end process REG_IDLE_FE;
-- CR579586 Use falling edge to set pfifo empty
cmdsts_idle_fe <= not cmdsts_idle and cmdsts_idle_d1;
-- CR579191
POTENTIAL_EMPTY_PROCESS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
pot_empty <= '1';
elsif(m_axis_tvalid_d1 = '1' and m_axis_tlast_d1 = '1' and m_axis_tready_d1 = '1')then
pot_empty <= '1';
elsif(m_axis_tvalid_d1 = '1' and m_axis_tlast_d1 = '0')then
pot_empty <= '0';
end if;
end if;
end process POTENTIAL_EMPTY_PROCESS;
end generate GEN_NO_LINEBUFFER;
--*****************************************************************************--
--** MM2S ASYNCH CLOCK SUPPORT **--
--*****************************************************************************--
-- Cross fifo pipe empty flag to secondary clock domain
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Pipe Empty and Shutdown reset CDC
---- SHUTDOWN_RST_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => fifo_pipe_empty ,
---- scndry_out => mm2s_fifo_pipe_empty_i ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
SHUTDOWN_RST_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => fifo_pipe_empty,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => mm2s_fifo_pipe_empty_i,
scndry_vect_out => open
);
-- Vertical Count and All Lines Transferred CDC (CR616211)
---- ALL_LINES_XFRED_P_S_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' , -- CR619293
---- prmry_out => open , -- CR619293
---- prmry_in => all_lines_xfred ,
---- scndry_out => mm2s_all_lines_xfred ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
ALL_LINES_XFRED_P_S_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => all_lines_xfred,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => mm2s_all_lines_xfred,
scndry_vect_out => open
);
-- Vertical Count and All Lines Transferred CDC (CR616211)
---- ALL_LINES_XFRED_S_P_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => dm_xfred_all_lines , -- CR619293
---- prmry_out => dm_xfred_all_lines_reg , -- CR619293
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
ALL_LINES_XFRED_S_P_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => dm_xfred_all_lines,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => dm_xfred_all_lines_reg,
scndry_vect_out => open
);
VSIZE_CNT_CROSSING : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
crnt_vsize_cdc_tig <= crnt_vsize;
crnt_vsize_d1 <= crnt_vsize_cdc_tig;
end if;
end process VSIZE_CNT_CROSSING;
crnt_vsize_d2 <= crnt_vsize_d1;
-- Cross stop signal (CR623291)
---- STOP_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => stop ,
---- prmry_out => stop_reg ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
STOP_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => stop,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => stop_reg,
scndry_vect_out => open
);
---- MM2S_RUN_STOP_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => run_stop ,
---- prmry_out => run_stop_reg ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
MM2S_RUN_STOP_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => run_stop,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => run_stop_reg,
scndry_vect_out => open
);
---- MM2S_FSIZE_ERR_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => fsize_mismatch_err_int_s ,
---- scndry_out => fsize_mismatch_err_int_m ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
MM2S_FSIZE_ERR_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => fsize_mismatch_err_int_s,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => fsize_mismatch_err_int_m,
scndry_vect_out => open
);
---- MM2S_FSYNC_OUT_CDC_I_FLUSH_SOF : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' , -- Not Used
---- prmry_out => open , -- Not Used
---- prmry_in => fsync_out ,
---- scndry_out => fsync_out_m ,
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => '0' , -- Not Used
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- scndry_vect_out => open -- Not Used
---- );
----
MM2S_FSYNC_OUT_CDC_I_FLUSH_SOF : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => fsync_out,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => fsync_out_m,
scndry_vect_out => open
);
GEN_FSYNC_SEL_CROSSING : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
fsync_src_select_cdc_tig <= fsync_src_select;
fsync_src_select_d1 <= fsync_src_select_cdc_tig;
end if;
end process GEN_FSYNC_SEL_CROSSING;
fsync_src_select_s_int <= fsync_src_select_d1;
-- Cross datamover halt and threshold signals
---- HALT_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => dm_halt ,
---- prmry_out => dm_halt_reg ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- scndry_vect_out => open
---- );
----
HALT_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => dm_halt,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => dm_halt_reg,
scndry_vect_out => open
);
THRESH_CNT_CROSSING : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
data_count_ae_threshold_cdc_tig <= data_count_ae_threshold;
data_count_ae_threshold_d1 <= data_count_ae_threshold_cdc_tig;
end if;
end process THRESH_CNT_CROSSING;
m_data_count_ae_thresh <= data_count_ae_threshold_d1;
GEN_ASYNC_CROSS_FSYNC : if C_INCLUDE_S2MM = 1 generate
begin
---- CROSS_FSYNC_CDC_I_FLUSH_MM2S_SOF : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => s_axis_s2mm_aclk ,
---- prmry_resetn => s2mm_axis_resetn ,
---- scndry_aclk => m_axis_aclk ,
---- scndry_resetn => m_axis_resetn ,
---- scndry_in => '0' , -- Not Used
---- prmry_out => open , -- Not Used
---- prmry_in => s2mm_fsync ,
---- scndry_out => s2mm_fsync_mm2s_s ,
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => '0' , -- Not Used
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- scndry_vect_out => open -- Not Used
---- );
----
CROSS_FSYNC_CDC_I_FLUSH_MM2S_SOF : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_s2mm_aclk,
prmry_resetn => s2mm_axis_resetn,
prmry_in => s2mm_fsync,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => s2mm_fsync_mm2s_s,
scndry_vect_out => open
);
end generate GEN_ASYNC_CROSS_FSYNC;
GEN_ASYNC_NO_CROSS_FSYNC : if C_INCLUDE_S2MM = 0 generate
begin
s2mm_fsync_mm2s_s <= '0';
end generate GEN_ASYNC_NO_CROSS_FSYNC;
end generate GEN_FOR_ASYNC;
--*****************************************************************************--
--** MM2S SYNCH CLOCK SUPPORT **--
--*****************************************************************************--
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
mm2s_fifo_pipe_empty_i <= fifo_pipe_empty;
crnt_vsize_d2 <= crnt_vsize; -- CR616211
mm2s_all_lines_xfred <= all_lines_xfred; -- CR616211
dm_xfred_all_lines_reg <= dm_xfred_all_lines; -- CR619293
stop_reg <= stop; -- CR623291
run_stop_reg <= run_stop; -- CR623291
fsync_out_m <= fsync_out; -- CR623291
dm_halt_reg <= dm_halt;
m_data_count_ae_thresh <= data_count_ae_threshold;
fsync_src_select_s_int <= fsync_src_select;
fsize_mismatch_err_int_m <= fsize_mismatch_err_int_s;
GEN_SYNC_CROSS_FSYNC : if C_INCLUDE_S2MM = 1 generate
begin
s2mm_fsync_mm2s_s <= s2mm_fsync;
end generate GEN_SYNC_CROSS_FSYNC;
GEN_SYNC_NO_CROSS_FSYNC : if C_INCLUDE_S2MM = 0 generate
begin
s2mm_fsync_mm2s_s <= '0';
end generate GEN_SYNC_NO_CROSS_FSYNC;
end generate GEN_FOR_SYNC;
NO_DWIDTH_VERT_COUNTER : if (C_DATA_WIDTH = C_M_AXIS_MM2S_TDATA_WIDTH) generate
begin
--*****************************************************************************
--** Vertical Line Tracking (CR616211)
--*****************************************************************************
-- Decrement vertical count with each accept tlast
decr_vcount <= '1' when m_axis_tlast_d1 = '1'
and m_axis_tvalid_d1 = '1'
and m_axis_tready_d1 = '1'
else '0';
-- Drive ready at fsync out then de-assert once all lines have
-- been accepted.
VERT_COUNTER : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if((m_axis_fifo_ainit = '1' and fsync_out = '0') or fsize_mismatch_err_flag_vsize_cntr_clr = '1' )then
vsize_counter <= (others => '0');
all_lines_xfred_no_dwidth <= '1';
elsif(fsync_out = '1')then
vsize_counter <= crnt_vsize_d2;
all_lines_xfred_no_dwidth <= '0';
elsif(decr_vcount = '1' and vsize_counter = VSIZE_ONE_VALUE)then
vsize_counter <= (others => '0');
all_lines_xfred_no_dwidth <= '1';
elsif(decr_vcount = '1' and vsize_counter /= VSIZE_ZERO_VALUE)then
vsize_counter <= std_logic_vector(unsigned(vsize_counter) - 1);
all_lines_xfred_no_dwidth <= '0';
end if;
end if;
end process VERT_COUNTER;
end generate NO_DWIDTH_VERT_COUNTER;
-- Store and forward or no line buffer (CR619293)
GEN_VCOUNT_FOR_SNF : if C_LINEBUFFER_DEPTH /= 0 and C_INCLUDE_MM2S_SF = 1 generate
begin
dm_decr_vcount <= '1' when s_axis_tlast = '1'
and s_axis_tvalid = '1'
and s_axis_tready_i = '1'
else '0';
-- Delay 1 pipe to align with cnrt_vsize
REG_FSYNC_TO_ALIGN : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit = '1' and frame_sync = '0')then
frame_sync_d1 <= '0';
else
frame_sync_d1 <= frame_sync;
end if;
end if;
end process REG_FSYNC_TO_ALIGN;
-- Count lines to determine when datamover done. Used for snf mode
-- for threshold met (CR619293)
DM_DONE : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit = '1')then
dm_vsize_counter <= (others => '0');
dm_xfred_all_lines <= '0';
--elsif(fsync_out = '1')then -- CR623088
elsif(frame_sync_d1 = '1')then -- CR623088
dm_vsize_counter <= crnt_vsize;
dm_xfred_all_lines <= '0';
elsif(dm_decr_vcount = '1' and dm_vsize_counter = VSIZE_ONE_VALUE)then
dm_vsize_counter <= (others => '0');
dm_xfred_all_lines <= '1';
elsif(dm_decr_vcount = '1' and dm_vsize_counter /= VSIZE_ZERO_VALUE)then
dm_vsize_counter <= std_logic_vector(unsigned(dm_vsize_counter) - 1);
dm_xfred_all_lines <= '0';
end if;
end if;
end process DM_DONE;
end generate GEN_VCOUNT_FOR_SNF;
-- Not store and forward or no line buffer (CR619293)
GEN_NO_VCOUNT_FOR_SNF : if C_LINEBUFFER_DEPTH = 0 or C_INCLUDE_MM2S_SF = 0 generate
begin
dm_vsize_counter <= (others => '0');
dm_xfred_all_lines <= '0';
dm_decr_vcount <= '0';
end generate GEN_NO_VCOUNT_FOR_SNF;
--*****************************************************************************--
--** SPECIAL RESET GENERATION **--
--*****************************************************************************--
-- Assert reset to skid buffer on hard reset or on shutdown when fifo pipe empty
-- Waiting for fifo_pipe_empty is required to prevent a AXIS protocol violation
-- when channel shut down early
REG_SKID_RESET : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_resetn = '0')then
m_skid_reset <= '1';
elsif(fifo_pipe_empty = '1')then
if(fsync_out = '1' or dm_halt_reg = '1')then
m_skid_reset <= '1';
else
m_skid_reset <= '0';
end if;
else
m_skid_reset <= '0';
end if;
end if;
end process REG_SKID_RESET;
-- Fifo/logic reset for slave side clock domain (m_axi_mm2s_aclk)
-- If error (dm_halt=1) then halt immediatly without protocol violation
s_axis_fifo_ainit <= '1' when s_axis_resetn = '0'
or frame_sync = '1' -- Frame sync
or dm_halt = '1' -- Datamover being halted (halt due to error)
else '0';
-- Fifo/logic reset for master side clock domain (m_axis_mm2s_aclk)
m_axis_fifo_ainit <= '1' when m_axis_resetn = '0'
or fsync_out = '1' -- Frame sync
or dm_halt_reg = '1' -- Datamover being halted
else '0';
-- Fifo/logic reset for slave side clock domain (m_axi_mm2s_aclk)
-- If error (dm_halt=1) then halt immediatly without protocol violation
s_axis_fifo_ainit_nosync <= '1' when s_axis_resetn = '0'
or dm_halt = '1' -- Datamover being halted (halt due to error)
else '0';
process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
s_axis_fifo_ainit_nosync_reg <= s_axis_fifo_ainit_nosync;
end if;
end process ;
-- Fifo/logic reset for master side clock domain (m_axis_mm2s_aclk)
m_axis_fifo_ainit_nosync <= '1' when m_axis_resetn = '0'
or dm_halt_reg = '1' -- Datamover being halted
else '0';
--reset for axis_dwidth
mm2s_axis_linebuf_reset_out_inv <= m_axis_fifo_ainit_nosync;
mm2s_axis_linebuf_reset_out <= not (mm2s_axis_linebuf_reset_out_inv);
all_lines_xfred <= mm2s_all_lines_xfred_s_sig;
mm2s_all_lines_xfred_s <= mm2s_all_lines_xfred_s_sig;
--C_DATA_WIDTH = C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED
MM2S_DWIDTH_CONV_IS : if (C_DATA_WIDTH /= C_M_AXIS_MM2S_TDATA_WIDTH) generate
begin
mm2s_all_lines_xfred_s_sig <= mm2s_all_lines_xfred_s_dwidth;
fifo_pipe_empty <= dwidth_fifo_pipe_empty;
dwidth_fifo_pipe_empty_m <= mm2s_fifo_pipe_empty_i;
end generate MM2S_DWIDTH_CONV_IS;
MM2S_DWIDTH_CONV_IS_NOT : if (C_DATA_WIDTH = C_M_AXIS_MM2S_TDATA_WIDTH) generate
begin
mm2s_all_lines_xfred_s_sig <= all_lines_xfred_no_dwidth;
fifo_pipe_empty <= '1' when (all_lines_xfred = '1' and m_axis_tvalid_out = '0') -- All data for frame transmitted
or (sf_threshold_met = '0' -- Or Threshold not met
and stop_reg = '1' -- Commanded to stop
and m_axis_tvalid_out = '0') -- And NOT driving tvalid
else '0';
dwidth_fifo_pipe_empty_m <= '1';
end generate MM2S_DWIDTH_CONV_IS_NOT;
mm2s_fsync_int <= mm2s_fsync and run_stop_reg;
-- Frame sync cross bar
---- FSYNC_CROSSBAR_MM2S_S : process(fsync_src_select_s_int,
---- run_stop_reg,
---- mm2s_fsync,
---- s2mm_fsync_mm2s_s)
---- begin
---- case fsync_src_select_s_int is
----
---- when "00" => -- primary fsync (default)
---- mm2s_fsync_int <= mm2s_fsync and run_stop_reg;
---- when "01" => -- other channel fsync
---- mm2s_fsync_int <= s2mm_fsync_mm2s_s and run_stop_reg;
---- when others =>
---- mm2s_fsync_int <= '0';
---- end case;
---- end process FSYNC_CROSSBAR_MM2S_S;
FSIZE_MISMATCH_MM2S_FLUSH_SOF_s : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk='1')then
if(m_axis_resetn = '0')then
fsize_mismatch_err_int_s <= '0';
-- fsync occurred when not all lines transferred
elsif(mm2s_fsync_int = '1' and mm2s_all_lines_xfred_s_sig = '0')then
fsize_mismatch_err_int_s <= '1';
else
fsize_mismatch_err_int_s <= '0';
end if;
end if;
end process FSIZE_MISMATCH_MM2S_FLUSH_SOF_s;
FSIZE_MISMATCH_FLAG_MM2S_FLUSH_SOF_s : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk='1')then
if(m_axis_resetn = '0' or mm2s_fsync_int = '1')then
fsize_mismatch_err_flag_s <= '0';
elsif(fsize_mismatch_err_int_s = '1')then
fsize_mismatch_err_flag_s <= '1';
end if;
end if;
end process FSIZE_MISMATCH_FLAG_MM2S_FLUSH_SOF_s;
fsize_mismatch_err_flag_cmb_s <= fsize_mismatch_err_int_s or fsize_mismatch_err_flag_s;
MM2S_DROP_RESIDUAL_OF_FSIZE_ERR_FRAME_S <= fsize_mismatch_err_flag_cmb_s;
mm2s_fsize_mismatch_err_s <= fsize_mismatch_err_int_s;
mm2s_fsize_mismatch_err_m <= fsize_mismatch_err_int_m;
mm2s_vsize_cntr_clr_flag <= fsize_mismatch_err_flag_vsize_cntr_clr or fsize_mismatch_err_int_s;
D1_FSYNC_OUT : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk='1')then
if(m_axis_resetn = '0')then
fsync_out_d1 <= '0';
else
fsync_out_d1 <= fsync_out;
end if;
end if;
end process D1_FSYNC_OUT;
FLAG_VSIZE_CNTR_CLR : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk='1')then
if(m_axis_resetn = '0' or fsync_out_d1 = '1')then
fsize_mismatch_err_flag_vsize_cntr_clr <= '0';
elsif(fsize_mismatch_err_int_s = '1')then
fsize_mismatch_err_flag_vsize_cntr_clr <= '1';
end if;
end if;
end process FLAG_VSIZE_CNTR_CLR;
MM2S_FSIZE_ERR_TO_DM_HALT_FLAG : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_resetn = '0' or dm_halt_reg = '1')then
fsize_err_to_dm_halt_flag <= '0';
elsif(fsize_mismatch_err_int_s = '1')then
fsize_err_to_dm_halt_flag <= '1';
end if;
end if;
end process MM2S_FSIZE_ERR_TO_DM_HALT_FLAG;
fsize_err_to_dm_halt_flag_ored <= fsize_mismatch_err_int_s or fsize_err_to_dm_halt_flag or dm_halt_reg;
delay_fsync_fsize_err_till_dm_halt_cmplt_pulse_s <= '1' when fsize_err_to_dm_halt_flag_ored = '1' and mm2s_fsync_int = '1'
else '0';
MM2S_FSIZE_LESS_DM_HALT_CMPLT_FLAG : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_resetn = '0' or fsize_err_to_dm_halt_flag_ored = '0')then
delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s <= '0';
elsif(delay_fsync_fsize_err_till_dm_halt_cmplt_pulse_s = '1')then
delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s <= '1';
end if;
end if;
end process MM2S_FSIZE_LESS_DM_HALT_CMPLT_FLAG;
MM2S_REG_D_FSYNC : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_resetn = '0')then
delay_fsync_fsize_err_till_dm_halt_cmplt_s_d1 <= '0';
else
delay_fsync_fsize_err_till_dm_halt_cmplt_s_d1 <= delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s;
end if;
end if;
end process MM2S_REG_D_FSYNC;
d_fsync_halt_cmplt_s <= delay_fsync_fsize_err_till_dm_halt_cmplt_s_d1 and not delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s;
mm2s_fsync_core <= (mm2s_fsync_int and not (delay_fsync_fsize_err_till_dm_halt_cmplt_pulse_s)) or d_fsync_halt_cmplt_s;
--mm2s_fsync_core <= mm2s_fsync_int;
end generate GEN_LINEBUF_FLUSH_SOF;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_vdma_mm2s_linebuf
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_mm2s_linebuf.vhd
-- Description: This entity encompases the mm2s line buffer logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library lib_cdc_v1_0_2;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_vdma_mm2s_linebuf is
generic (
C_DATA_WIDTH : integer range 8 to 1024 := 32;
C_M_AXIS_MM2S_TDATA_WIDTH : integer range 8 to 1024 := 32;
-- Line Buffer Data Width
C_INCLUDE_S2MM : integer range 0 to 1 := 0;
C_INCLUDE_MM2S_SF : integer range 0 to 1 := 0;
-- Include or exclude MM2S Store And Forward Functionality
-- 0 = Exclude MM2S Store and Forward
-- 1 = Include MM2S Store and Forward
C_INCLUDE_MM2S_DRE : integer range 0 to 1 := 0;
C_MM2S_SOF_ENABLE : integer range 0 to 1 := 0;
-- Enable/Disable start of frame generation on tuser(0). This
-- is only valid for external frame sync (C_USE_FSYNC = 1)
-- 0 = disable SOF
-- 1 = enable SOF
C_M_AXIS_MM2S_TUSER_BITS : integer range 1 to 1 := 1;
-- Master AXI Stream User Width for MM2S Channel
C_TOPLVL_LINEBUFFER_DEPTH : integer range 0 to 65536 := 512; -- CR625142
-- Depth as set by user at top level parameter
C_LINEBUFFER_DEPTH : integer range 0 to 65536 := 512;
-- Linebuffer depth in Bytes. Must be a power of 2
C_LINEBUFFER_AE_THRESH : integer range 1 to 65536 := 1;
-- Linebuffer almost empty threshold in Bytes. Must be a power of 2
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0 ;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
--C_ENABLE_DEBUG_INFO : string := "1111111111111111"; -- 1 to 16 --
--C_ENABLE_DEBUG_INFO : bit_vector(15 downto 0) := (others => '1'); --15 downto 0 --
C_ENABLE_DEBUG_ALL : integer range 0 to 1 := 1;
-- Setting this make core backward compatible to 2012.4 version in terms of ports and registers
C_ENABLE_DEBUG_INFO_0 : integer range 0 to 1 := 1;
-- Enable debug information bit 0
C_ENABLE_DEBUG_INFO_1 : integer range 0 to 1 := 1;
-- Enable debug information bit 1
C_ENABLE_DEBUG_INFO_2 : integer range 0 to 1 := 1;
-- Enable debug information bit 2
C_ENABLE_DEBUG_INFO_3 : integer range 0 to 1 := 1;
-- Enable debug information bit 3
C_ENABLE_DEBUG_INFO_4 : integer range 0 to 1 := 1;
-- Enable debug information bit 4
C_ENABLE_DEBUG_INFO_5 : integer range 0 to 1 := 1;
-- Enable debug information bit 5
C_ENABLE_DEBUG_INFO_6 : integer range 0 to 1 := 1;
-- Enable debug information bit 6
C_ENABLE_DEBUG_INFO_7 : integer range 0 to 1 := 1;
-- Enable debug information bit 7
C_ENABLE_DEBUG_INFO_8 : integer range 0 to 1 := 1;
-- Enable debug information bit 8
C_ENABLE_DEBUG_INFO_9 : integer range 0 to 1 := 1;
-- Enable debug information bit 9
C_ENABLE_DEBUG_INFO_10 : integer range 0 to 1 := 1;
-- Enable debug information bit 10
C_ENABLE_DEBUG_INFO_11 : integer range 0 to 1 := 1;
-- Enable debug information bit 11
C_ENABLE_DEBUG_INFO_12 : integer range 0 to 1 := 1;
-- Enable debug information bit 12
C_ENABLE_DEBUG_INFO_13 : integer range 0 to 1 := 1;
-- Enable debug information bit 13
C_ENABLE_DEBUG_INFO_14 : integer range 0 to 1 := 1;
-- Enable debug information bit 14
C_ENABLE_DEBUG_INFO_15 : integer range 0 to 1 := 1;
-- Enable debug information bit 15
ENABLE_FLUSH_ON_FSYNC : integer range 0 to 1 := 0 ;
C_FAMILY : string := "virtex7"
-- Device family used for proper BRAM selection
);
port (
-- MM2S AXIS Input Side (i.e. Datamover side)
s_axis_aclk : in std_logic ; --
s_axis_resetn : in std_logic ; --
--
-- MM2S AXIS Output Side --
m_axis_aclk : in std_logic ; --
m_axis_resetn : in std_logic ; --
mm2s_axis_linebuf_reset_out : out std_logic ; --
s2mm_axis_resetn : in std_logic := '1' ; --
s_axis_s2mm_aclk : in std_logic := '0' ; --
mm2s_fsync : in std_logic ; --
s2mm_fsync : in std_logic ; --
mm2s_fsync_core : out std_logic ; --
mm2s_fsize_mismatch_err_s : out std_logic ; --
mm2s_fsize_mismatch_err_m : out std_logic ; --
mm2s_vsize_cntr_clr_flag : out std_logic ; --
MM2S_DROP_RESIDUAL_OF_FSIZE_ERR_FRAME_S : out std_logic ; --
fsync_src_select : in std_logic_vector(1 downto 0) ; --
--
run_stop : in std_logic ; --
-- Graceful shut down control --
dm_halt : in std_logic ; --
dm_halt_reg_out : out std_logic ; --
cmdsts_idle : in std_logic ; --
stop : in std_logic ; -- CR623291
stop_reg_out : out std_logic ; -- CR623291
--
-- Vertical Line Count control --
fsync_out : in std_logic ; -- CR616211
fsync_out_m : out std_logic ; -- CR616211
mm2s_fsize_mismatch_err_flag: in std_logic ; -- CR616211
frame_sync : in std_logic ; -- CR616211
crnt_vsize : in std_logic_vector --
(VSIZE_DWIDTH-1 downto 0) ; -- CR616211
crnt_vsize_d2_out : out std_logic_vector --
(VSIZE_DWIDTH-1 downto 0) ; -- CR616211
--
linebuf_threshold : in std_logic_vector --
(LINEBUFFER_THRESH_WIDTH-1 downto 0); --
--
-- Stream In (Datamover To Line Buffer) --
s_axis_tdata : in std_logic_vector --
(C_DATA_WIDTH-1 downto 0) ; --
s_axis_tkeep : in std_logic_vector --
((C_DATA_WIDTH/8)-1 downto 0) ; --
s_axis_tlast : in std_logic ; --
s_axis_tvalid : in std_logic ; --
s_axis_tready : out std_logic ; --
--
--
-- Stream Out (Line Buffer To MM2S AXIS) --
m_axis_tdata : out std_logic_vector --
(C_DATA_WIDTH-1 downto 0) ; --
m_axis_tkeep : out std_logic_vector --
((C_DATA_WIDTH/8)-1 downto 0) ; --
m_axis_tlast : out std_logic ; --
m_axis_tvalid : out std_logic ; --
m_axis_tready : in std_logic ; --
m_axis_tuser : out std_logic_vector --
(C_M_AXIS_MM2S_TUSER_BITS-1 downto 0); --
--
-- Fifo Status Flags --
dwidth_fifo_pipe_empty : in std_logic ; --
dwidth_fifo_pipe_empty_m : out std_logic ; --
mm2s_fifo_pipe_empty : out std_logic ; --
mm2s_fifo_empty : out std_logic ; --
mm2s_fifo_almost_empty : out std_logic ; --
mm2s_all_lines_xfred_s_dwidth : in std_logic ; --
mm2s_all_lines_xfred_s : out std_logic ; --
mm2s_all_lines_xfred : out std_logic -- CR616211
);
end axi_vdma_mm2s_linebuf;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_mm2s_linebuf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Bufer depth
--constant BUFFER_DEPTH : integer := max2(128,C_LINEBUFFER_DEPTH/(C_DATA_WIDTH/8));
constant BUFFER_DEPTH : integer := C_LINEBUFFER_DEPTH;
-- Buffer width is data width + strobe width + 1 bit for tlast
-- Increase data width by 1 when tuser support included.
--constant BUFFER_WIDTH : integer := C_DATA_WIDTH + (C_DATA_WIDTH/8) + 1;
constant BUFFER_WIDTH : integer := C_DATA_WIDTH -- tdata
+ (C_DATA_WIDTH/8)*C_INCLUDE_MM2S_DRE -- tkeep
+ 1 -- tlast
+ (C_MM2S_SOF_ENABLE -- tuser
*C_M_AXIS_MM2S_TUSER_BITS);
-- Buffer data count width
constant DATACOUNT_WIDTH : integer := clog2(BUFFER_DEPTH);
constant DATA_COUNT_ZERO : std_logic_vector(DATACOUNT_WIDTH-1 downto 0)
:= (others => '0');
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
constant ZERO_VALUE_VECT : std_logic_vector(255 downto 0) := (others => '0');
-- Constants for line tracking logic
constant VSIZE_ONE_VALUE : std_logic_vector(VSIZE_DWIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(1,VSIZE_DWIDTH));
constant VSIZE_ZERO_VALUE : std_logic_vector(VSIZE_DWIDTH-1 downto 0)
:= (others => '0');
-- Linebuffer threshold support
constant THRESHOLD_LSB_INDEX : integer := clog2((C_DATA_WIDTH/8));
constant THRESHOLD_PAD : std_logic_vector(THRESHOLD_LSB_INDEX-1 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal fifo_din : std_logic_vector(BUFFER_WIDTH - 1 downto 0) := (others => '0');
signal fifo_dout : std_logic_vector(BUFFER_WIDTH - 1 downto 0) := (others => '0');
signal fifo_wren : std_logic := '0';
signal fifo_rden : std_logic := '0';
signal fifo_empty_i : std_logic := '0';
signal fifo_full_i : std_logic := '0';
signal fifo_ainit : std_logic := '0';
signal fifo_rdcount : std_logic_vector(DATACOUNT_WIDTH -1 downto 0) := (others => '0');
signal s_axis_tready_i : std_logic := '0'; -- CR619293
signal m_axis_tready_i : std_logic := '0';
signal m_axis_tvalid_i : std_logic := '0';
signal m_axis_tlast_i : std_logic := '0';
signal m_axis_tdata_i : std_logic_vector(C_DATA_WIDTH-1 downto 0):= (others => '0');
signal m_axis_tkeep_i : std_logic_vector((C_DATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_axis_tkeep_signal : std_logic_vector((C_DATA_WIDTH/8)-1 downto 0) := (others => '0');
signal s_axis_tkeep_signal : std_logic_vector((C_DATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_axis_tuser_i : std_logic_vector(C_M_AXIS_MM2S_TUSER_BITS - 1 downto 0) := (others => '0');
signal m_axis_tready_d1 : std_logic := '0';
signal m_axis_tlast_d1 : std_logic := '0';
signal m_axis_tvalid_d1 : std_logic := '0';
signal crnt_vsize_cdc_tig : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0'); -- CR575884
signal crnt_vsize_d1 : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0'); -- CR575884
signal crnt_vsize_d2 : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0'); -- CR575884
signal vsize_counter : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0'); -- CR575884
signal decr_vcount : std_logic := '0'; -- CR575884
signal all_lines_xfred : std_logic := '0'; -- CR616211
signal all_lines_xfred_no_dwidth : std_logic := '0'; -- CR616211
signal mm2s_all_lines_xfred_s_sig : std_logic := '0'; -- CR616211
signal m_axis_tvalid_out : std_logic := '0'; -- CR576993
signal m_axis_tlast_out : std_logic := '0'; -- CR616211
signal slv2skid_s_axis_tvalid : std_logic := '0'; -- CR576993
signal fifo_empty_d1 : std_logic := '0'; -- CR576993
-- FIFO Pipe empty signals
signal fifo_pipe_empty : std_logic := '0';
signal fifo_wren_d1 : std_logic := '0'; -- CR579191
signal pot_empty : std_logic := '0'; -- CR579191
signal fifo_almost_empty_i : std_logic := '1'; -- CR604273/CR604272
signal fifo_almost_empty_d1 : std_logic := '1';
signal fifo_almost_empty_fe : std_logic := '0'; -- CR604273/CR604272
signal fifo_almost_empty_reg : std_logic := '1';
signal data_count_ae_threshold_cdc_tig : std_logic_vector(DATACOUNT_WIDTH-1 downto 0) := (others => '0');
signal data_count_ae_threshold_d1 : std_logic_vector(DATACOUNT_WIDTH-1 downto 0) := (others => '0');
signal data_count_ae_threshold : std_logic_vector(DATACOUNT_WIDTH-1 downto 0) := (others => '0');
signal m_data_count_ae_thresh : std_logic_vector(DATACOUNT_WIDTH-1 downto 0) := (others => '0');
signal sf_threshold_met : std_logic := '0';
signal cmdsts_idle_d1 : std_logic := '0';
signal cmdsts_idle_fe : std_logic := '0';
signal stop_reg : std_logic := '0'; --CR623291
signal s_axis_fifo_ainit : std_logic := '0';
signal m_axis_fifo_ainit : std_logic := '0';
signal s_axis_fifo_ainit_nosync : std_logic := '0';
signal s_axis_fifo_ainit_nosync_reg : std_logic := '0';
signal m_axis_fifo_ainit_nosync : std_logic := '0';
signal dm_decr_vcount : std_logic := '0'; -- CR619293
signal dm_xfred_all_lines : std_logic := '0'; -- CR619293
signal dm_vsize_counter : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0'); -- CR619293
signal dm_xfred_all_lines_reg : std_logic := '0'; -- CR619293
signal sof_flag : std_logic := '0';
signal mm2s_fifo_pipe_empty_i : std_logic := '0';
signal frame_sync_d1 : std_logic := '0';
signal m_skid_reset : std_logic := '0';
signal dm_halt_reg : std_logic := '0';
signal mm2s_axis_linebuf_reset_out_inv : std_logic := '0' ; --
signal sof_reset : std_logic := '0';
signal wr_rst_busy_sig : std_logic := '0';
signal rd_rst_busy_sig : std_logic := '0';
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF crnt_vsize_cdc_tig : SIGNAL IS "true";
ATTRIBUTE async_reg OF crnt_vsize_d1 : SIGNAL IS "true";
ATTRIBUTE async_reg OF data_count_ae_threshold_cdc_tig : SIGNAL IS "true";
ATTRIBUTE async_reg OF data_count_ae_threshold_d1 : SIGNAL IS "true";
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
mm2s_fifo_pipe_empty <= mm2s_fifo_pipe_empty_i;
dm_halt_reg_out <= dm_halt_reg;
stop_reg_out <= stop_reg;
crnt_vsize_d2_out <= crnt_vsize_d2;
GEN_MM2S_DRE_ON : if C_INCLUDE_MM2S_DRE = 1 generate
begin
m_axis_tkeep <= m_axis_tkeep_signal;
s_axis_tkeep_signal <= s_axis_tkeep;
end generate GEN_MM2S_DRE_ON;
GEN_MM2S_DRE_OFF : if C_INCLUDE_MM2S_DRE = 0 generate
begin
m_axis_tkeep <= (others => '1');
s_axis_tkeep_signal <= (others => '1');
end generate GEN_MM2S_DRE_OFF;
GEN_LINEBUF_NO_SOF : if (ENABLE_FLUSH_ON_FSYNC = 0 or C_MM2S_SOF_ENABLE = 0) generate
begin
mm2s_fsync_core <= mm2s_fsync;
MM2S_DROP_RESIDUAL_OF_FSIZE_ERR_FRAME_S <= '0';
mm2s_fsize_mismatch_err_s <= '0';
--*****************************************************************************--
--** LINE BUFFER MODE (Sync or Async) **--
--*****************************************************************************--
GEN_LINEBUFFER : if C_LINEBUFFER_DEPTH /= 0 generate
begin
-- Divide by number bytes per data beat and add padding to dynamic
-- threshold setting
data_count_ae_threshold <= linebuf_threshold((DATACOUNT_WIDTH-1) + THRESHOLD_LSB_INDEX
downto THRESHOLD_LSB_INDEX);
-- Synchronous clock therefore instantiate an Asynchronous FIFO
GEN_SYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2_8.axi_vdma_sfifo
generic map(
UW_DATA_WIDTH => BUFFER_WIDTH ,
C_FULL_FLAGS_RST_VAL => 1 ,
UW_FIFO_DEPTH => BUFFER_DEPTH ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
rst => s_axis_fifo_ainit_nosync ,
sleep => '0' ,
wr_rst_busy => wr_rst_busy_sig ,
rd_rst_busy => rd_rst_busy_sig ,
clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i ,
data_count => fifo_rdcount
);
--wr_rst_busy_sig <= '0';
--rd_rst_busy_sig <= '0';
end generate GEN_SYNC_FIFO;
-- Asynchronous clock therefore instantiate an Asynchronous FIFO
GEN_ASYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
LB_BRAM : if ( (C_ENABLE_DEBUG_INFO_1 = 1 or C_ENABLE_DEBUG_ALL = 1) )
generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2_8.axi_vdma_afifo
generic map(
UW_DATA_WIDTH => BUFFER_WIDTH ,
C_FULL_FLAGS_RST_VAL => 1 ,
UW_FIFO_DEPTH => BUFFER_DEPTH ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
rst => s_axis_fifo_ainit_nosync_reg ,
sleep => '0' ,
wr_rst_busy => open ,
rd_rst_busy => open ,
wr_clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_clk => m_axis_aclk ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i ,
wr_data_count => open , --CR622702
rd_data_count => fifo_rdcount
);
wr_rst_busy_sig <= '0';
rd_rst_busy_sig <= '0';
end generate LB_BRAM;
LB_BUILT_IN : if ( (C_ENABLE_DEBUG_INFO_1 = 0 and C_ENABLE_DEBUG_ALL = 0) )
generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2_8.axi_vdma_afifo_builtin
generic map(
PL_FIFO_TYPE => "BUILT_IN" ,
PL_READ_MODE => "FWFT" ,
PL_FASTER_CLOCK => "WR_CLK" , --RD_CLK
PL_FULL_FLAGS_RST_VAL => 0 , -- ?
PL_DATA_WIDTH => BUFFER_WIDTH ,
C_FAMILY => C_FAMILY ,
PL_FIFO_DEPTH => BUFFER_DEPTH
)
port map(
-- Inputs
rst => s_axis_fifo_ainit_nosync_reg ,
sleep => '0' ,
wr_rst_busy => wr_rst_busy_sig ,
rd_rst_busy => rd_rst_busy_sig ,
wr_clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_clk => m_axis_aclk ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i
);
end generate LB_BUILT_IN;
end generate GEN_ASYNC_FIFO;
-- Generate an SOF on tuser(0). currently vdma only support 1 tuser bit that is set by
-- frame sync and driven out on first data beat of mm2s packet.
GEN_SOF : if ENABLE_FLUSH_ON_FSYNC = 0 and C_MM2S_SOF_ENABLE = 1 generate
--signal sof_reset : std_logic := '0';
begin
sof_reset <= '1' when (s_axis_resetn = '0')
or (dm_halt = '1')
else '0';
-- On frame sync set flag and then clear flag when
-- sof written to fifo.
SOF_FLAG_PROCESS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(sof_reset = '1' or fifo_wren = '1')then
sof_flag <= '0';
elsif(frame_sync = '1')then
sof_flag <= '1';
end if;
end if;
end process SOF_FLAG_PROCESS;
GEN_MM2S_DRE_ENABLED_TKEEP : if C_INCLUDE_MM2S_DRE = 1 generate
begin
-- AXI Slave Side of FIFO
fifo_din <= sof_flag & s_axis_tlast & s_axis_tkeep_signal & s_axis_tdata;
fifo_wren <= s_axis_tvalid and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
s_axis_tready <= s_axis_tready_i; -- CR619293
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready_i and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig and sf_threshold_met;
m_axis_tdata_i <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_i <= fifo_dout(BUFFER_WIDTH-3 downto (BUFFER_WIDTH-3) - (C_DATA_WIDTH/8) + 1);
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-2);
m_axis_tuser_i(0) <= fifo_dout(BUFFER_WIDTH-1);
end generate GEN_MM2S_DRE_ENABLED_TKEEP;
GEN_NO_MM2S_DRE_DISABLE_TKEEP : if C_INCLUDE_MM2S_DRE = 0 generate
begin
-- AXI Slave Side of FIFO
fifo_din <= sof_flag & s_axis_tlast & s_axis_tdata;
fifo_wren <= s_axis_tvalid and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
s_axis_tready <= s_axis_tready_i; -- CR619293
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready_i and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig and sf_threshold_met;
m_axis_tdata_i <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_i <= (others => '1');
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-2);
m_axis_tuser_i(0) <= fifo_dout(BUFFER_WIDTH-1);
end generate GEN_NO_MM2S_DRE_DISABLE_TKEEP;
end generate GEN_SOF;
-- SOF turned off therefore do not generate SOF on tuser
GEN_NO_SOF : if C_MM2S_SOF_ENABLE = 0 generate
begin
GEN_MM2S_DRE_ENABLED_TKEEP : if C_INCLUDE_MM2S_DRE = 1 generate
begin
sof_flag <= '0';
-- AXI Slave Side of FIFO
fifo_din <= s_axis_tlast & s_axis_tkeep_signal & s_axis_tdata;
fifo_wren <= s_axis_tvalid and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
s_axis_tready <= s_axis_tready_i; -- CR619293
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready_i and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig and sf_threshold_met;
m_axis_tdata_i <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_i <= fifo_dout(BUFFER_WIDTH-2 downto (BUFFER_WIDTH-2) - (C_DATA_WIDTH/8) + 1);
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-1);
m_axis_tuser_i <= (others => '0');
end generate GEN_MM2S_DRE_ENABLED_TKEEP;
GEN_NO_MM2S_DRE_DISABLE_TKEEP : if C_INCLUDE_MM2S_DRE = 0 generate
begin
sof_flag <= '0';
-- AXI Slave Side of FIFO
fifo_din <= s_axis_tlast & s_axis_tdata;
fifo_wren <= s_axis_tvalid and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
s_axis_tready <= s_axis_tready_i; -- CR619293
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready_i and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig and sf_threshold_met;
m_axis_tdata_i <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_i <= (others => '1');
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-1);
m_axis_tuser_i <= (others => '0');
end generate GEN_NO_MM2S_DRE_DISABLE_TKEEP;
end generate GEN_NO_SOF;
-- Top level line buffer depth not equal to zero therefore gererate threshold
-- flags. (CR625142)
GEN_THRESHOLD_ENABLED : if C_TOPLVL_LINEBUFFER_DEPTH /= 0 and (C_ENABLE_DEBUG_INFO_1 = 1 or C_ENABLE_DEBUG_ALL = 1) generate
begin
-- Almost empty flag (note: asserts when empty also)
REG_ALMST_EMPTY : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
fifo_almost_empty_reg <= '1';
--elsif(fifo_rdcount(DATACOUNT_WIDTH-1 downto 0) <= DATA_COUNT_AE_THRESHOLD or fifo_empty_i = '1')then
--elsif((fifo_rdcount(DATACOUNT_WIDTH-1 downto 0) <= m_data_count_ae_thresh
-- or fifo_empty_i = '1') and fifo_full_i = '0')then
elsif((fifo_rdcount(DATACOUNT_WIDTH-1 downto 0) <= m_data_count_ae_thresh
or (fifo_empty_i = '1' or rd_rst_busy_sig = '1')))then
fifo_almost_empty_reg <= '1';
else
fifo_almost_empty_reg <= '0';
end if;
end if;
end process REG_ALMST_EMPTY;
mm2s_fifo_almost_empty <= fifo_almost_empty_reg
or (not sf_threshold_met) -- CR622777
or (not m_axis_tvalid_out); -- CR625724
mm2s_fifo_empty <= not m_axis_tvalid_out;
end generate GEN_THRESHOLD_ENABLED;
-- Top level line buffer depth is zero therefore turn off threshold logic.
-- this occurs for async operation where the async fifo is needed for CDC (CR625142)
GEN_THRESHOLD_DISABLED : if C_TOPLVL_LINEBUFFER_DEPTH = 0 or (C_ENABLE_DEBUG_INFO_1 = 0 and C_ENABLE_DEBUG_ALL = 0) generate
begin
mm2s_fifo_empty <= '0';
mm2s_fifo_almost_empty <= '0';
fifo_almost_empty_reg <= '0';
end generate GEN_THRESHOLD_DISABLED;
-- CR#578903
-- FIFO, FIFO Pipe, and Skid Buffer are all empty. This is used to safely
-- assert reset on shutdown and also used to safely generate fsync in free-run mode
-- CR622702 - need to look at write side of fifo to prevent false empties due to async fifo
--fifo_pipe_empty <= '1' when (fifo_wrcount(DATACOUNT_WIDTH-1 downto 0) = DATA_COUNT_ZERO -- Data count is 0
-- and m_axis_tvalid_out = '0') -- Skid Buffer is done
-- -- Forced stop and Threshold not met (CR623291)
-- or (sf_threshold_met = '0' and stop_reg = '1')
-- else '0';
-- CR623879 fixed flase fifo_pipe_assertions due to extreme AXI4 throttling on
-- mm2s reads causing fifo to go empty for extended periods of time. This then
-- caused flase idles to be flagged and frame syncs were then generated in free run mode
-------- fifo_pipe_empty <= '1' when (all_lines_xfred = '1' and m_axis_tvalid_out = '0') -- All data for frame transmitted
-------- or (sf_threshold_met = '0' -- Or Threshold not met
-------- and stop_reg = '1' -- Commanded to stop
-------- and m_axis_tvalid_out = '0') -- And NOT driving tvalid
-------- else '0';
--------
-- If store and forward is turned on by user then gate tvalid with
-- threshold met
GEN_THRESH_MET_FOR_SNF : if C_INCLUDE_MM2S_SF = 1 and C_TOPLVL_LINEBUFFER_DEPTH /= 0 and (C_ENABLE_DEBUG_INFO_1 = 1 or C_ENABLE_DEBUG_ALL = 1) generate
begin
-- Register fifo_almost empty in order to generate
-- almost empty fall edge pulse
REG_ALMST_EMPTY_FE : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
fifo_almost_empty_d1 <= '1';
else
fifo_almost_empty_d1 <= fifo_almost_empty_reg;
end if;
end if;
end process REG_ALMST_EMPTY_FE;
-- Almost empty falling edge
fifo_almost_empty_fe <= not fifo_almost_empty_reg and fifo_almost_empty_d1;
-- Store and Forward threshold met
THRESH_MET : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
sf_threshold_met <= '0';
elsif(fsync_out = '1')then
sf_threshold_met <= '0';
-- Reached threshold or all reads done for the frame
elsif(fifo_almost_empty_fe = '1'
or (dm_xfred_all_lines_reg = '1'))then
sf_threshold_met <= '1';
end if;
end if;
end process THRESH_MET;
end generate GEN_THRESH_MET_FOR_SNF;
-- Store and forward off therefore do not need to meet threshold
GEN_NO_THRESH_MET_FOR_SNF : if C_INCLUDE_MM2S_SF = 0 or C_TOPLVL_LINEBUFFER_DEPTH = 0 or (C_ENABLE_DEBUG_INFO_1 = 0 and C_ENABLE_DEBUG_ALL = 0) generate
begin
sf_threshold_met <= '1';
end generate GEN_NO_THRESH_MET_FOR_SNF;
--*********************************************************--
--** MM2S MASTER SKID BUFFER **--
--*********************************************************--
I_MSTR_SKID : entity axi_vdma_v6_2_8.axi_vdma_skid_buf
generic map(
C_WDATA_WIDTH => C_DATA_WIDTH ,
C_TUSER_WIDTH => C_M_AXIS_MM2S_TUSER_BITS
)
port map(
-- System Ports
ACLK => m_axis_aclk ,
ARST => m_axis_fifo_ainit_nosync ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => '0' ,
-- Slave Side (Stream Data Input)
S_VALID => m_axis_tvalid_i ,
S_READY => m_axis_tready_i ,
S_Data => m_axis_tdata_i ,
S_STRB => m_axis_tkeep_i ,
S_Last => m_axis_tlast_i ,
S_User => m_axis_tuser_i ,
-- Master Side (Stream Data Output)
M_VALID => m_axis_tvalid_out ,
M_READY => m_axis_tready ,
M_Data => m_axis_tdata ,
M_STRB => m_axis_tkeep_signal ,
M_Last => m_axis_tlast_out ,
M_User => m_axis_tuser
);
-- Pass out of core
m_axis_tvalid <= m_axis_tvalid_out;
m_axis_tlast <= m_axis_tlast_out;
-- Register to break long timing paths for use in
-- transfer complete generation
REG_STRM_SIGS : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
m_axis_tlast_d1 <= '0';
m_axis_tvalid_d1 <= '0';
m_axis_tready_d1 <= '0';
else
m_axis_tlast_d1 <= m_axis_tlast_out;
m_axis_tvalid_d1 <= m_axis_tvalid_out;
m_axis_tready_d1 <= m_axis_tready;
end if;
end if;
end process REG_STRM_SIGS;
end generate GEN_LINEBUFFER;
--*****************************************************************************--
--** NO LINE BUFFER MODE (Sync Only) **--
--*****************************************************************************--
-- LineBuffer forced on if asynchronous mode is enabled
GEN_NO_LINEBUFFER : if (C_LINEBUFFER_DEPTH = 0) generate -- No Line Buffer
begin
-- Map Datamover to AXIS Master Out
m_axis_tdata <= s_axis_tdata;
m_axis_tkeep_signal <= s_axis_tkeep_signal;
m_axis_tvalid <= s_axis_tvalid;
m_axis_tlast <= s_axis_tlast;
s_axis_tready <= m_axis_tready;
-- Tie FIFO Flags off
mm2s_fifo_empty <= '0';
mm2s_fifo_almost_empty <= '0';
-- Generate sof on tuser(0)
GEN_SOF : if C_MM2S_SOF_ENABLE = 1 generate
begin
-- On frame sync set flag and then clear flag when
-- sof written to fifo.
SOF_FLAG_PROCESS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit = '1' or (s_axis_tvalid = '1' and m_axis_tready = '1'))then
sof_flag <= '0';
elsif(frame_sync = '1')then
sof_flag <= '1';
end if;
end if;
end process SOF_FLAG_PROCESS;
m_axis_tuser(0) <= sof_flag;
end generate GEN_SOF;
-- Do not generate sof on tuser(0)
GEN_NO_SOF : if C_MM2S_SOF_ENABLE = 0 generate
begin
sof_flag <= '0';
m_axis_tuser <= (others => '0');
end generate GEN_NO_SOF;
-- CR#578903
-- Register tvalid to break timing paths for use in
-- psuedo fifo empty for channel idle generation and
-- for xfer complete generation.
REG_STRM_SIGS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
m_axis_tvalid_d1 <= '0';
m_axis_tlast_d1 <= '0';
m_axis_tready_d1 <= '0';
else
m_axis_tvalid_d1 <= s_axis_tvalid;
m_axis_tlast_d1 <= s_axis_tlast;
m_axis_tready_d1 <= m_axis_tready;
end if;
end if;
end process REG_STRM_SIGS;
-- CR#578903
-- Psuedo FIFO, FIFO Pipe, and Skid Buffer are all empty. This is used to safely
-- assert reset on shutdown and also used to safely generate fsync in free-run mode
-- This flag is looked at at the end of frames.
-- Order of else-if is critical
-- CR579191 modified method to prevent double fsync assertions
REG_PIPE_EMPTY : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
fifo_pipe_empty <= '1';
-- Command/Status not idle indicates pending datamover commands
-- set psuedo fifo empty to NOT empty.
elsif(cmdsts_idle_fe = '1')then
fifo_pipe_empty <= '0';
-- On accepted tlast then clear psuedo empty flag back to being empty
elsif(pot_empty = '1' and cmdsts_idle = '1')then
fifo_pipe_empty <= '1';
end if;
end if;
end process REG_PIPE_EMPTY;
REG_IDLE_FE : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
cmdsts_idle_d1 <= '1';
else
cmdsts_idle_d1 <= cmdsts_idle;
end if;
end if;
end process REG_IDLE_FE;
-- CR579586 Use falling edge to set pfifo empty
cmdsts_idle_fe <= not cmdsts_idle and cmdsts_idle_d1;
-- CR579191
POTENTIAL_EMPTY_PROCESS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
pot_empty <= '1';
elsif(m_axis_tvalid_d1 = '1' and m_axis_tlast_d1 = '1' and m_axis_tready_d1 = '1')then
pot_empty <= '1';
elsif(m_axis_tvalid_d1 = '1' and m_axis_tlast_d1 = '0')then
pot_empty <= '0';
end if;
end if;
end process POTENTIAL_EMPTY_PROCESS;
end generate GEN_NO_LINEBUFFER;
--*****************************************************************************--
--** MM2S ASYNCH CLOCK SUPPORT **--
--*****************************************************************************--
-- Cross fifo pipe empty flag to secondary clock domain
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Pipe Empty and Shutdown reset CDC
---- SHUTDOWN_RST_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => fifo_pipe_empty ,
---- scndry_out => mm2s_fifo_pipe_empty_i ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
SHUTDOWN_RST_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => fifo_pipe_empty,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => mm2s_fifo_pipe_empty_i,
scndry_vect_out => open
);
-- Vertical Count and All Lines Transferred CDC (CR616211)
---- ALL_LINES_XFRED_P_S_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' , -- CR619293
---- prmry_out => open , -- CR619293
---- prmry_in => all_lines_xfred ,
---- scndry_out => mm2s_all_lines_xfred ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
----
ALL_LINES_XFRED_P_S_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => all_lines_xfred,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => mm2s_all_lines_xfred,
scndry_vect_out => open
);
-- Vertical Count and All Lines Transferred CDC (CR616211)
---- ALL_LINES_XFRED_S_P_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => dm_xfred_all_lines , -- CR619293
---- prmry_out => dm_xfred_all_lines_reg , -- CR619293
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
ALL_LINES_XFRED_S_P_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => dm_xfred_all_lines,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => dm_xfred_all_lines_reg,
scndry_vect_out => open
);
VSIZE_CNT_CROSSING : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
crnt_vsize_cdc_tig <= crnt_vsize;
crnt_vsize_d1 <= crnt_vsize_cdc_tig;
end if;
end process VSIZE_CNT_CROSSING;
crnt_vsize_d2 <= crnt_vsize_d1;
-- Cross stop signal (CR623291)
---- STOP_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => stop ,
---- prmry_out => stop_reg ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
STOP_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => stop,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => stop_reg,
scndry_vect_out => open
);
-- Cross datamover halt and threshold signals
---- HALT_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => dm_halt ,
---- prmry_out => dm_halt_reg ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- scndry_vect_out => open
---- );
----
HALT_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => dm_halt,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => dm_halt_reg,
scndry_vect_out => open
);
THRESH_CNT_CROSSING : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
data_count_ae_threshold_cdc_tig <= data_count_ae_threshold;
data_count_ae_threshold_d1 <= data_count_ae_threshold_cdc_tig;
end if;
end process THRESH_CNT_CROSSING;
m_data_count_ae_thresh <= data_count_ae_threshold_d1;
end generate GEN_FOR_ASYNC;
--*****************************************************************************--
--** MM2S SYNCH CLOCK SUPPORT **--
--*****************************************************************************--
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
mm2s_fifo_pipe_empty_i <= fifo_pipe_empty;
crnt_vsize_d2 <= crnt_vsize; -- CR616211
mm2s_all_lines_xfred <= all_lines_xfred; -- CR616211
dm_xfred_all_lines_reg <= dm_xfred_all_lines; -- CR619293
stop_reg <= stop; -- CR623291
dm_halt_reg <= dm_halt;
m_data_count_ae_thresh <= data_count_ae_threshold;
end generate GEN_FOR_SYNC;
--*****************************************************************************
--** Vertical Line Tracking (CR616211)
--*****************************************************************************
-- Decrement vertical count with each accept tlast
decr_vcount <= '1' when m_axis_tlast_d1 = '1'
and m_axis_tvalid_d1 = '1'
and m_axis_tready_d1 = '1'
else '0';
-- Drive ready at fsync out then de-assert once all lines have
-- been accepted.
VERT_COUNTER : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1' and fsync_out = '0')then
vsize_counter <= (others => '0');
all_lines_xfred <= '1';
elsif(fsync_out = '1')then
vsize_counter <= crnt_vsize_d2;
all_lines_xfred <= '0';
elsif(decr_vcount = '1' and vsize_counter = VSIZE_ONE_VALUE)then
vsize_counter <= (others => '0');
all_lines_xfred <= '1';
elsif(decr_vcount = '1' and vsize_counter /= VSIZE_ZERO_VALUE)then
vsize_counter <= std_logic_vector(unsigned(vsize_counter) - 1);
all_lines_xfred <= '0';
end if;
end if;
end process VERT_COUNTER;
-- Store and forward or no line buffer (CR619293)
GEN_VCOUNT_FOR_SNF : if C_LINEBUFFER_DEPTH /= 0 and C_INCLUDE_MM2S_SF = 1 generate
begin
dm_decr_vcount <= '1' when s_axis_tlast = '1'
and s_axis_tvalid = '1'
and s_axis_tready_i = '1'
else '0';
-- Delay 1 pipe to align with cnrt_vsize
REG_FSYNC_TO_ALIGN : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit = '1' and frame_sync = '0')then
frame_sync_d1 <= '0';
else
frame_sync_d1 <= frame_sync;
end if;
end if;
end process REG_FSYNC_TO_ALIGN;
-- Count lines to determine when datamover done. Used for snf mode
-- for threshold met (CR619293)
DM_DONE : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit = '1')then
dm_vsize_counter <= (others => '0');
dm_xfred_all_lines <= '0';
--elsif(fsync_out = '1')then -- CR623088
elsif(frame_sync_d1 = '1')then -- CR623088
dm_vsize_counter <= crnt_vsize;
dm_xfred_all_lines <= '0';
elsif(dm_decr_vcount = '1' and dm_vsize_counter = VSIZE_ONE_VALUE)then
dm_vsize_counter <= (others => '0');
dm_xfred_all_lines <= '1';
elsif(dm_decr_vcount = '1' and dm_vsize_counter /= VSIZE_ZERO_VALUE)then
dm_vsize_counter <= std_logic_vector(unsigned(dm_vsize_counter) - 1);
dm_xfred_all_lines <= '0';
end if;
end if;
end process DM_DONE;
end generate GEN_VCOUNT_FOR_SNF;
-- Not store and forward or no line buffer (CR619293)
GEN_NO_VCOUNT_FOR_SNF : if C_LINEBUFFER_DEPTH = 0 or C_INCLUDE_MM2S_SF = 0 generate
begin
dm_vsize_counter <= (others => '0');
dm_xfred_all_lines <= '0';
dm_decr_vcount <= '0';
end generate GEN_NO_VCOUNT_FOR_SNF;
--*****************************************************************************--
--** SPECIAL RESET GENERATION **--
--*****************************************************************************--
-- Assert reset to skid buffer on hard reset or on shutdown when fifo pipe empty
-- Waiting for fifo_pipe_empty is required to prevent a AXIS protocol violation
-- when channel shut down early
REG_SKID_RESET : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_resetn = '0')then
m_skid_reset <= '1';
elsif(fifo_pipe_empty = '1')then
if(fsync_out = '1' or dm_halt_reg = '1')then
m_skid_reset <= '1';
else
m_skid_reset <= '0';
end if;
else
m_skid_reset <= '0';
end if;
end if;
end process REG_SKID_RESET;
-- Fifo/logic reset for slave side clock domain (m_axi_mm2s_aclk)
-- If error (dm_halt=1) then halt immediatly without protocol violation
s_axis_fifo_ainit <= '1' when s_axis_resetn = '0'
or frame_sync = '1' -- Frame sync
or dm_halt = '1' -- Datamover being halted (halt due to error)
else '0';
-- Fifo/logic reset for master side clock domain (m_axis_mm2s_aclk)
m_axis_fifo_ainit <= '1' when m_axis_resetn = '0'
or fsync_out = '1' -- Frame sync
or dm_halt_reg = '1' -- Datamover being halted
else '0';
-- Fifo/logic reset for slave side clock domain (m_axi_mm2s_aclk)
-- If error (dm_halt=1) then halt immediatly without protocol violation
s_axis_fifo_ainit_nosync <= '1' when s_axis_resetn = '0'
or dm_halt = '1' -- Datamover being halted (halt due to error)
else '0';
process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
s_axis_fifo_ainit_nosync_reg <= s_axis_fifo_ainit_nosync;
end if;
end process ;
-- Fifo/logic reset for master side clock domain (m_axis_mm2s_aclk)
m_axis_fifo_ainit_nosync <= '1' when m_axis_resetn = '0'
or dm_halt_reg = '1' -- Datamover being halted
else '0';
--reset for axis_dwidth
mm2s_axis_linebuf_reset_out_inv <= m_axis_fifo_ainit_nosync;
mm2s_axis_linebuf_reset_out <= not (mm2s_axis_linebuf_reset_out_inv);
MM2S_DWIDTH_CONV_IS : if (C_DATA_WIDTH /= C_M_AXIS_MM2S_TDATA_WIDTH) generate
begin
fifo_pipe_empty <= dwidth_fifo_pipe_empty;
dwidth_fifo_pipe_empty_m <= mm2s_fifo_pipe_empty_i;
end generate MM2S_DWIDTH_CONV_IS;
MM2S_DWIDTH_CONV_IS_NOT : if (C_DATA_WIDTH = C_M_AXIS_MM2S_TDATA_WIDTH) generate
begin
fifo_pipe_empty <= '1' when (all_lines_xfred = '1' and m_axis_tvalid_out = '0') -- All data for frame transmitted
or (sf_threshold_met = '0' -- Or Threshold not met
and stop_reg = '1' -- Commanded to stop
and m_axis_tvalid_out = '0') -- And NOT driving tvalid
else '0';
dwidth_fifo_pipe_empty_m <= '1';
end generate MM2S_DWIDTH_CONV_IS_NOT;
mm2s_all_lines_xfred_s <= '0';
fsync_out_m <= '0';
mm2s_vsize_cntr_clr_flag <= '0';
mm2s_fsize_mismatch_err_m <= '0';
end generate GEN_LINEBUF_NO_SOF;
GEN_LINEBUF_FLUSH_SOF : if (ENABLE_FLUSH_ON_FSYNC = 1 and C_MM2S_SOF_ENABLE = 1) generate
signal s2mm_fsync_mm2s_s : std_logic := '0';
signal run_stop_reg : std_logic := '0';
signal fsync_out_d1 : std_logic := '0';
signal mm2s_fsync_int : std_logic := '0';
signal fsize_mismatch_err_int_s : std_logic := '0';
signal fsize_mismatch_err_int_m : std_logic := '0';
signal fsize_mismatch_err_flag_s : std_logic := '0';
signal fsize_mismatch_err_flag_vsize_cntr_clr : std_logic := '0';
signal fsize_mismatch_err_flag_cmb_s : std_logic := '0';
signal fsync_src_select_cdc_tig : std_logic_vector(1 downto 0) := (others => '0');
signal fsync_src_select_d1 : std_logic_vector(1 downto 0) := (others => '0');
signal fsync_src_select_s_int : std_logic_vector(1 downto 0) := (others => '0');
signal fsize_err_to_dm_halt_flag : std_logic := '0';
signal fsize_err_to_dm_halt_flag_ored : std_logic := '0';
signal delay_fsync_fsize_err_till_dm_halt_cmplt_pulse_s : std_logic := '0';
signal delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s : std_logic := '0';
signal delay_fsync_fsize_err_till_dm_halt_cmplt_s_d1 : std_logic := '0';
signal d_fsync_halt_cmplt_s : std_logic := '0';
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF fsync_src_select_cdc_tig : SIGNAL IS "true";
ATTRIBUTE async_reg OF fsync_src_select_d1 : SIGNAL IS "true";
begin
--*****************************************************************************--
--** LINE BUFFER MODE (Sync or Async) **--
--*****************************************************************************--
GEN_LINEBUFFER : if C_LINEBUFFER_DEPTH /= 0 generate
begin
-- Divide by number bytes per data beat and add padding to dynamic
-- threshold setting
data_count_ae_threshold <= linebuf_threshold((DATACOUNT_WIDTH-1) + THRESHOLD_LSB_INDEX
downto THRESHOLD_LSB_INDEX);
-- Synchronous clock therefore instantiate an Asynchronous FIFO
GEN_SYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2_8.axi_vdma_sfifo
generic map(
UW_DATA_WIDTH => BUFFER_WIDTH ,
C_FULL_FLAGS_RST_VAL => 1 ,
UW_FIFO_DEPTH => BUFFER_DEPTH ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
rst => s_axis_fifo_ainit_nosync ,
sleep => '0' ,
wr_rst_busy => wr_rst_busy_sig ,
rd_rst_busy => rd_rst_busy_sig ,
clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i ,
data_count => fifo_rdcount
);
--wr_rst_busy_sig <= '0';
--rd_rst_busy_sig <= '0';
end generate GEN_SYNC_FIFO;
-- Asynchronous clock therefore instantiate an Asynchronous FIFO
GEN_ASYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
LB_BRAM : if ( (C_ENABLE_DEBUG_INFO_1 = 1 or C_ENABLE_DEBUG_ALL = 1) )
generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2_8.axi_vdma_afifo
generic map(
UW_DATA_WIDTH => BUFFER_WIDTH ,
C_FULL_FLAGS_RST_VAL => 1 ,
UW_FIFO_DEPTH => BUFFER_DEPTH ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
rst => s_axis_fifo_ainit_nosync_reg ,
sleep => '0' ,
wr_rst_busy => open ,
rd_rst_busy => open ,
wr_clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_clk => m_axis_aclk ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i ,
wr_data_count => open , --CR622702
rd_data_count => fifo_rdcount
);
wr_rst_busy_sig <= '0';
rd_rst_busy_sig <= '0';
end generate LB_BRAM;
LB_BUILT_IN : if ( (C_ENABLE_DEBUG_INFO_1 = 0 and C_ENABLE_DEBUG_ALL = 0) )
generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2_8.axi_vdma_afifo_builtin
generic map(
PL_FIFO_TYPE => "BUILT_IN" ,
PL_READ_MODE => "FWFT" ,
PL_FASTER_CLOCK => "WR_CLK" , --RD_CLK
PL_FULL_FLAGS_RST_VAL => 0 , -- ?
PL_DATA_WIDTH => BUFFER_WIDTH ,
C_FAMILY => C_FAMILY ,
PL_FIFO_DEPTH => BUFFER_DEPTH
)
port map(
-- Inputs
rst => s_axis_fifo_ainit_nosync_reg ,
sleep => '0' ,
wr_rst_busy => wr_rst_busy_sig ,
rd_rst_busy => rd_rst_busy_sig ,
wr_clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_clk => m_axis_aclk ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i
);
end generate LB_BUILT_IN;
end generate GEN_ASYNC_FIFO;
-- Generate an SOF on tuser(0). currently vdma only support 1 tuser bit that is set by
-- frame sync and driven out on first data beat of mm2s packet.
------ GEN_SOF : if C_MM2S_SOF_ENABLE = 1 generate
------ signal sof_reset : std_logic := '0';
------ begin
sof_reset <= '1' when (s_axis_resetn = '0')
or (dm_halt = '1')
else '0';
-- On frame sync set flag and then clear flag when
-- sof written to fifo.
SOF_FLAG_PROCESS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(sof_reset = '1' or fifo_wren = '1')then
sof_flag <= '0';
elsif(frame_sync = '1')then
sof_flag <= '1';
end if;
end if;
end process SOF_FLAG_PROCESS;
GEN_MM2S_DRE_ENABLED_TKEEP : if C_INCLUDE_MM2S_DRE = 1 generate
begin
-- AXI Slave Side of FIFO
fifo_din <= sof_flag & s_axis_tlast & s_axis_tkeep_signal & s_axis_tdata;
fifo_wren <= s_axis_tvalid and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
s_axis_tready <= s_axis_tready_i; -- CR619293
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready_i and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig and sf_threshold_met;
m_axis_tdata_i <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_i <= fifo_dout(BUFFER_WIDTH-3 downto (BUFFER_WIDTH-3) - (C_DATA_WIDTH/8) + 1);
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-2);
m_axis_tuser_i(0) <= fifo_dout(BUFFER_WIDTH-1);
end generate GEN_MM2S_DRE_ENABLED_TKEEP;
GEN_NO_MM2S_DRE_DISABLE_TKEEP : if C_INCLUDE_MM2S_DRE = 0 generate
begin
-- AXI Slave Side of FIFO
fifo_din <= sof_flag & s_axis_tlast & s_axis_tdata;
fifo_wren <= s_axis_tvalid and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
s_axis_tready <= s_axis_tready_i; -- CR619293
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready_i and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig and sf_threshold_met;
m_axis_tdata_i <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_i <= (others => '1');
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-2);
m_axis_tuser_i(0) <= fifo_dout(BUFFER_WIDTH-1);
end generate GEN_NO_MM2S_DRE_DISABLE_TKEEP;
------ end generate GEN_SOF;
------
------
-- SOF turned off therefore do not generate SOF on tuser
---------- GEN_NO_SOF : if C_MM2S_SOF_ENABLE = 0 generate
---------- begin
----------
---------- sof_flag <= '0';
----------
---------- -- AXI Slave Side of FIFO
---------- fifo_din <= s_axis_tlast & s_axis_tkeep & s_axis_tdata;
---------- fifo_wren <= s_axis_tvalid and not fifo_full_i and not s_axis_fifo_ainit;
---------- s_axis_tready_i <= not fifo_full_i and not s_axis_fifo_ainit;
---------- s_axis_tready <= s_axis_tready_i; -- CR619293
----------
---------- -- AXI Master Side of FIFO
---------- fifo_rden <= m_axis_tready_i and not fifo_empty_i and sf_threshold_met;
---------- m_axis_tvalid_i <= not fifo_empty_i and sf_threshold_met;
---------- m_axis_tdata_i <= fifo_dout(C_DATA_WIDTH-1 downto 0);
---------- m_axis_tkeep_i <= fifo_dout(BUFFER_WIDTH-2 downto (BUFFER_WIDTH-2) - (C_DATA_WIDTH/8) + 1);
---------- m_axis_tlast_i <= not fifo_empty_i and fifo_dout(BUFFER_WIDTH-1);
---------- m_axis_tuser_i <= (others => '0');
----------
---------- end generate GEN_NO_SOF;
-- Top level line buffer depth not equal to zero therefore gererate threshold
-- flags. (CR625142)
GEN_THRESHOLD_ENABLED : if C_TOPLVL_LINEBUFFER_DEPTH /= 0 and (C_ENABLE_DEBUG_INFO_1 = 1 or C_ENABLE_DEBUG_ALL = 1) generate
begin
-- Almost empty flag (note: asserts when empty also)
REG_ALMST_EMPTY : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
fifo_almost_empty_reg <= '1';
--elsif(fifo_rdcount(DATACOUNT_WIDTH-1 downto 0) <= DATA_COUNT_AE_THRESHOLD or fifo_empty_i = '1')then
--elsif((fifo_rdcount(DATACOUNT_WIDTH-1 downto 0) <= m_data_count_ae_thresh
-- or fifo_empty_i = '1') and fifo_full_i = '0')then
elsif((fifo_rdcount(DATACOUNT_WIDTH-1 downto 0) <= m_data_count_ae_thresh
or (fifo_empty_i = '1' or rd_rst_busy_sig = '1')))then
fifo_almost_empty_reg <= '1';
else
fifo_almost_empty_reg <= '0';
end if;
end if;
end process REG_ALMST_EMPTY;
mm2s_fifo_almost_empty <= fifo_almost_empty_reg
or (not sf_threshold_met) -- CR622777
or (not m_axis_tvalid_out); -- CR625724
mm2s_fifo_empty <= not m_axis_tvalid_out;
end generate GEN_THRESHOLD_ENABLED;
-- Top level line buffer depth is zero therefore turn off threshold logic.
-- this occurs for async operation where the async fifo is needed for CDC (CR625142)
GEN_THRESHOLD_DISABLED : if C_TOPLVL_LINEBUFFER_DEPTH = 0 or (C_ENABLE_DEBUG_INFO_1 = 0 and C_ENABLE_DEBUG_ALL = 0) generate
begin
mm2s_fifo_empty <= '0';
mm2s_fifo_almost_empty <= '0';
fifo_almost_empty_reg <= '0';
end generate GEN_THRESHOLD_DISABLED;
-- CR#578903
-- FIFO, FIFO Pipe, and Skid Buffer are all empty. This is used to safely
-- assert reset on shutdown and also used to safely generate fsync in free-run mode
-- CR622702 - need to look at write side of fifo to prevent false empties due to async fifo
--fifo_pipe_empty <= '1' when (fifo_wrcount(DATACOUNT_WIDTH-1 downto 0) = DATA_COUNT_ZERO -- Data count is 0
-- and m_axis_tvalid_out = '0') -- Skid Buffer is done
-- -- Forced stop and Threshold not met (CR623291)
-- or (sf_threshold_met = '0' and stop_reg = '1')
-- else '0';
-- CR623879 fixed flase fifo_pipe_assertions due to extreme AXI4 throttling on
-- mm2s reads causing fifo to go empty for extended periods of time. This then
-- caused flase idles to be flagged and frame syncs were then generated in free run mode
---------------- fifo_pipe_empty <= '1' when (all_lines_xfred = '1' and m_axis_tvalid_out = '0') -- All data for frame transmitted
---------------- or (sf_threshold_met = '0' -- Or Threshold not met
---------------- and stop_reg = '1' -- Commanded to stop
---------------- and m_axis_tvalid_out = '0') -- And NOT driving tvalid
---------------- else '0';
----------------
-- If store and forward is turned on by user then gate tvalid with
-- threshold met
GEN_THRESH_MET_FOR_SNF : if C_INCLUDE_MM2S_SF = 1 and C_TOPLVL_LINEBUFFER_DEPTH /= 0 and (C_ENABLE_DEBUG_INFO_1 = 1 or C_ENABLE_DEBUG_ALL = 1) generate
begin
-- Register fifo_almost empty in order to generate
-- almost empty fall edge pulse
REG_ALMST_EMPTY_FE : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
fifo_almost_empty_d1 <= '1';
else
fifo_almost_empty_d1 <= fifo_almost_empty_reg;
end if;
end if;
end process REG_ALMST_EMPTY_FE;
-- Almost empty falling edge
fifo_almost_empty_fe <= not fifo_almost_empty_reg and fifo_almost_empty_d1;
-- Store and Forward threshold met
THRESH_MET : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
sf_threshold_met <= '0';
elsif(fsync_out = '1')then
sf_threshold_met <= '0';
-- Reached threshold or all reads done for the frame
elsif(fifo_almost_empty_fe = '1'
or (dm_xfred_all_lines_reg = '1'))then
sf_threshold_met <= '1';
end if;
end if;
end process THRESH_MET;
end generate GEN_THRESH_MET_FOR_SNF;
-- Store and forward off therefore do not need to meet threshold
GEN_NO_THRESH_MET_FOR_SNF : if C_INCLUDE_MM2S_SF = 0 or C_TOPLVL_LINEBUFFER_DEPTH = 0 or (C_ENABLE_DEBUG_INFO_1 = 0 and C_ENABLE_DEBUG_ALL = 0) generate
begin
sf_threshold_met <= '1';
end generate GEN_NO_THRESH_MET_FOR_SNF;
--*********************************************************--
--** MM2S MASTER SKID BUFFER **--
--*********************************************************--
I_MSTR_SKID : entity axi_vdma_v6_2_8.axi_vdma_skid_buf
generic map(
C_WDATA_WIDTH => C_DATA_WIDTH ,
C_TUSER_WIDTH => C_M_AXIS_MM2S_TUSER_BITS
)
port map(
-- System Ports
ACLK => m_axis_aclk ,
ARST => m_axis_fifo_ainit_nosync ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => '0' ,
-- Slave Side (Stream Data Input)
S_VALID => m_axis_tvalid_i ,
S_READY => m_axis_tready_i ,
S_Data => m_axis_tdata_i ,
S_STRB => m_axis_tkeep_i ,
S_Last => m_axis_tlast_i ,
S_User => m_axis_tuser_i ,
-- Master Side (Stream Data Output)
M_VALID => m_axis_tvalid_out ,
M_READY => m_axis_tready ,
M_Data => m_axis_tdata ,
M_STRB => m_axis_tkeep_signal ,
M_Last => m_axis_tlast_out ,
M_User => m_axis_tuser
);
-- Pass out of core
m_axis_tvalid <= m_axis_tvalid_out;
m_axis_tlast <= m_axis_tlast_out;
-- Register to break long timing paths for use in
-- transfer complete generation
REG_STRM_SIGS : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
m_axis_tlast_d1 <= '0';
m_axis_tvalid_d1 <= '0';
m_axis_tready_d1 <= '0';
else
m_axis_tlast_d1 <= m_axis_tlast_out;
m_axis_tvalid_d1 <= m_axis_tvalid_out;
m_axis_tready_d1 <= m_axis_tready;
end if;
end if;
end process REG_STRM_SIGS;
end generate GEN_LINEBUFFER;
--*****************************************************************************--
--** NO LINE BUFFER MODE (Sync Only) **--
--*****************************************************************************--
-- LineBuffer forced on if asynchronous mode is enabled
GEN_NO_LINEBUFFER : if (C_LINEBUFFER_DEPTH = 0) generate -- No Line Buffer
begin
-- Map Datamover to AXIS Master Out
m_axis_tdata <= s_axis_tdata;
m_axis_tkeep_signal <= s_axis_tkeep_signal;
m_axis_tvalid <= s_axis_tvalid;
m_axis_tlast <= s_axis_tlast;
s_axis_tready <= m_axis_tready;
-- Tie FIFO Flags off
mm2s_fifo_empty <= '0';
mm2s_fifo_almost_empty <= '0';
-- Generate sof on tuser(0)
---- GEN_SOF : if C_MM2S_SOF_ENABLE = 1 generate
--- begin
-- On frame sync set flag and then clear flag when
-- sof written to fifo.
SOF_FLAG_PROCESS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit = '1' or (s_axis_tvalid = '1' and m_axis_tready = '1'))then
sof_flag <= '0';
elsif(frame_sync = '1')then
sof_flag <= '1';
end if;
end if;
end process SOF_FLAG_PROCESS;
m_axis_tuser(0) <= sof_flag;
--- end generate GEN_SOF;
-- Do not generate sof on tuser(0)
----- GEN_NO_SOF : if C_MM2S_SOF_ENABLE = 0 generate
----- begin
----- sof_flag <= '0';
----- m_axis_tuser <= (others => '0');
----- end generate GEN_NO_SOF;
-- CR#578903
-- Register tvalid to break timing paths for use in
-- psuedo fifo empty for channel idle generation and
-- for xfer complete generation.
REG_STRM_SIGS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
m_axis_tvalid_d1 <= '0';
m_axis_tlast_d1 <= '0';
m_axis_tready_d1 <= '0';
else
m_axis_tvalid_d1 <= s_axis_tvalid;
m_axis_tlast_d1 <= s_axis_tlast;
m_axis_tready_d1 <= m_axis_tready;
end if;
end if;
end process REG_STRM_SIGS;
-- CR#578903
-- Psuedo FIFO, FIFO Pipe, and Skid Buffer are all empty. This is used to safely
-- assert reset on shutdown and also used to safely generate fsync in free-run mode
-- This flag is looked at at the end of frames.
-- Order of else-if is critical
-- CR579191 modified method to prevent double fsync assertions
REG_PIPE_EMPTY : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
fifo_pipe_empty <= '1';
-- Command/Status not idle indicates pending datamover commands
-- set psuedo fifo empty to NOT empty.
elsif(cmdsts_idle_fe = '1')then
fifo_pipe_empty <= '0';
-- On accepted tlast then clear psuedo empty flag back to being empty
elsif(pot_empty = '1' and cmdsts_idle = '1')then
fifo_pipe_empty <= '1';
end if;
end if;
end process REG_PIPE_EMPTY;
REG_IDLE_FE : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
cmdsts_idle_d1 <= '1';
else
cmdsts_idle_d1 <= cmdsts_idle;
end if;
end if;
end process REG_IDLE_FE;
-- CR579586 Use falling edge to set pfifo empty
cmdsts_idle_fe <= not cmdsts_idle and cmdsts_idle_d1;
-- CR579191
POTENTIAL_EMPTY_PROCESS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
pot_empty <= '1';
elsif(m_axis_tvalid_d1 = '1' and m_axis_tlast_d1 = '1' and m_axis_tready_d1 = '1')then
pot_empty <= '1';
elsif(m_axis_tvalid_d1 = '1' and m_axis_tlast_d1 = '0')then
pot_empty <= '0';
end if;
end if;
end process POTENTIAL_EMPTY_PROCESS;
end generate GEN_NO_LINEBUFFER;
--*****************************************************************************--
--** MM2S ASYNCH CLOCK SUPPORT **--
--*****************************************************************************--
-- Cross fifo pipe empty flag to secondary clock domain
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Pipe Empty and Shutdown reset CDC
---- SHUTDOWN_RST_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => fifo_pipe_empty ,
---- scndry_out => mm2s_fifo_pipe_empty_i ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
SHUTDOWN_RST_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => fifo_pipe_empty,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => mm2s_fifo_pipe_empty_i,
scndry_vect_out => open
);
-- Vertical Count and All Lines Transferred CDC (CR616211)
---- ALL_LINES_XFRED_P_S_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' , -- CR619293
---- prmry_out => open , -- CR619293
---- prmry_in => all_lines_xfred ,
---- scndry_out => mm2s_all_lines_xfred ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
ALL_LINES_XFRED_P_S_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => all_lines_xfred,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => mm2s_all_lines_xfred,
scndry_vect_out => open
);
-- Vertical Count and All Lines Transferred CDC (CR616211)
---- ALL_LINES_XFRED_S_P_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => dm_xfred_all_lines , -- CR619293
---- prmry_out => dm_xfred_all_lines_reg , -- CR619293
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
ALL_LINES_XFRED_S_P_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => dm_xfred_all_lines,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => dm_xfred_all_lines_reg,
scndry_vect_out => open
);
VSIZE_CNT_CROSSING : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
crnt_vsize_cdc_tig <= crnt_vsize;
crnt_vsize_d1 <= crnt_vsize_cdc_tig;
end if;
end process VSIZE_CNT_CROSSING;
crnt_vsize_d2 <= crnt_vsize_d1;
-- Cross stop signal (CR623291)
---- STOP_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => stop ,
---- prmry_out => stop_reg ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
STOP_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => stop,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => stop_reg,
scndry_vect_out => open
);
---- MM2S_RUN_STOP_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => run_stop ,
---- prmry_out => run_stop_reg ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
MM2S_RUN_STOP_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => run_stop,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => run_stop_reg,
scndry_vect_out => open
);
---- MM2S_FSIZE_ERR_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => fsize_mismatch_err_int_s ,
---- scndry_out => fsize_mismatch_err_int_m ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
MM2S_FSIZE_ERR_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => fsize_mismatch_err_int_s,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => fsize_mismatch_err_int_m,
scndry_vect_out => open
);
---- MM2S_FSYNC_OUT_CDC_I_FLUSH_SOF : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' , -- Not Used
---- prmry_out => open , -- Not Used
---- prmry_in => fsync_out ,
---- scndry_out => fsync_out_m ,
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => '0' , -- Not Used
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- scndry_vect_out => open -- Not Used
---- );
----
MM2S_FSYNC_OUT_CDC_I_FLUSH_SOF : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => fsync_out,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => fsync_out_m,
scndry_vect_out => open
);
GEN_FSYNC_SEL_CROSSING : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
fsync_src_select_cdc_tig <= fsync_src_select;
fsync_src_select_d1 <= fsync_src_select_cdc_tig;
end if;
end process GEN_FSYNC_SEL_CROSSING;
fsync_src_select_s_int <= fsync_src_select_d1;
-- Cross datamover halt and threshold signals
---- HALT_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => dm_halt ,
---- prmry_out => dm_halt_reg ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- scndry_vect_out => open
---- );
----
HALT_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => dm_halt,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => dm_halt_reg,
scndry_vect_out => open
);
THRESH_CNT_CROSSING : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
data_count_ae_threshold_cdc_tig <= data_count_ae_threshold;
data_count_ae_threshold_d1 <= data_count_ae_threshold_cdc_tig;
end if;
end process THRESH_CNT_CROSSING;
m_data_count_ae_thresh <= data_count_ae_threshold_d1;
GEN_ASYNC_CROSS_FSYNC : if C_INCLUDE_S2MM = 1 generate
begin
---- CROSS_FSYNC_CDC_I_FLUSH_MM2S_SOF : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => s_axis_s2mm_aclk ,
---- prmry_resetn => s2mm_axis_resetn ,
---- scndry_aclk => m_axis_aclk ,
---- scndry_resetn => m_axis_resetn ,
---- scndry_in => '0' , -- Not Used
---- prmry_out => open , -- Not Used
---- prmry_in => s2mm_fsync ,
---- scndry_out => s2mm_fsync_mm2s_s ,
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => '0' , -- Not Used
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- scndry_vect_out => open -- Not Used
---- );
----
CROSS_FSYNC_CDC_I_FLUSH_MM2S_SOF : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_s2mm_aclk,
prmry_resetn => s2mm_axis_resetn,
prmry_in => s2mm_fsync,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => s2mm_fsync_mm2s_s,
scndry_vect_out => open
);
end generate GEN_ASYNC_CROSS_FSYNC;
GEN_ASYNC_NO_CROSS_FSYNC : if C_INCLUDE_S2MM = 0 generate
begin
s2mm_fsync_mm2s_s <= '0';
end generate GEN_ASYNC_NO_CROSS_FSYNC;
end generate GEN_FOR_ASYNC;
--*****************************************************************************--
--** MM2S SYNCH CLOCK SUPPORT **--
--*****************************************************************************--
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
mm2s_fifo_pipe_empty_i <= fifo_pipe_empty;
crnt_vsize_d2 <= crnt_vsize; -- CR616211
mm2s_all_lines_xfred <= all_lines_xfred; -- CR616211
dm_xfred_all_lines_reg <= dm_xfred_all_lines; -- CR619293
stop_reg <= stop; -- CR623291
run_stop_reg <= run_stop; -- CR623291
fsync_out_m <= fsync_out; -- CR623291
dm_halt_reg <= dm_halt;
m_data_count_ae_thresh <= data_count_ae_threshold;
fsync_src_select_s_int <= fsync_src_select;
fsize_mismatch_err_int_m <= fsize_mismatch_err_int_s;
GEN_SYNC_CROSS_FSYNC : if C_INCLUDE_S2MM = 1 generate
begin
s2mm_fsync_mm2s_s <= s2mm_fsync;
end generate GEN_SYNC_CROSS_FSYNC;
GEN_SYNC_NO_CROSS_FSYNC : if C_INCLUDE_S2MM = 0 generate
begin
s2mm_fsync_mm2s_s <= '0';
end generate GEN_SYNC_NO_CROSS_FSYNC;
end generate GEN_FOR_SYNC;
NO_DWIDTH_VERT_COUNTER : if (C_DATA_WIDTH = C_M_AXIS_MM2S_TDATA_WIDTH) generate
begin
--*****************************************************************************
--** Vertical Line Tracking (CR616211)
--*****************************************************************************
-- Decrement vertical count with each accept tlast
decr_vcount <= '1' when m_axis_tlast_d1 = '1'
and m_axis_tvalid_d1 = '1'
and m_axis_tready_d1 = '1'
else '0';
-- Drive ready at fsync out then de-assert once all lines have
-- been accepted.
VERT_COUNTER : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if((m_axis_fifo_ainit = '1' and fsync_out = '0') or fsize_mismatch_err_flag_vsize_cntr_clr = '1' )then
vsize_counter <= (others => '0');
all_lines_xfred_no_dwidth <= '1';
elsif(fsync_out = '1')then
vsize_counter <= crnt_vsize_d2;
all_lines_xfred_no_dwidth <= '0';
elsif(decr_vcount = '1' and vsize_counter = VSIZE_ONE_VALUE)then
vsize_counter <= (others => '0');
all_lines_xfred_no_dwidth <= '1';
elsif(decr_vcount = '1' and vsize_counter /= VSIZE_ZERO_VALUE)then
vsize_counter <= std_logic_vector(unsigned(vsize_counter) - 1);
all_lines_xfred_no_dwidth <= '0';
end if;
end if;
end process VERT_COUNTER;
end generate NO_DWIDTH_VERT_COUNTER;
-- Store and forward or no line buffer (CR619293)
GEN_VCOUNT_FOR_SNF : if C_LINEBUFFER_DEPTH /= 0 and C_INCLUDE_MM2S_SF = 1 generate
begin
dm_decr_vcount <= '1' when s_axis_tlast = '1'
and s_axis_tvalid = '1'
and s_axis_tready_i = '1'
else '0';
-- Delay 1 pipe to align with cnrt_vsize
REG_FSYNC_TO_ALIGN : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit = '1' and frame_sync = '0')then
frame_sync_d1 <= '0';
else
frame_sync_d1 <= frame_sync;
end if;
end if;
end process REG_FSYNC_TO_ALIGN;
-- Count lines to determine when datamover done. Used for snf mode
-- for threshold met (CR619293)
DM_DONE : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit = '1')then
dm_vsize_counter <= (others => '0');
dm_xfred_all_lines <= '0';
--elsif(fsync_out = '1')then -- CR623088
elsif(frame_sync_d1 = '1')then -- CR623088
dm_vsize_counter <= crnt_vsize;
dm_xfred_all_lines <= '0';
elsif(dm_decr_vcount = '1' and dm_vsize_counter = VSIZE_ONE_VALUE)then
dm_vsize_counter <= (others => '0');
dm_xfred_all_lines <= '1';
elsif(dm_decr_vcount = '1' and dm_vsize_counter /= VSIZE_ZERO_VALUE)then
dm_vsize_counter <= std_logic_vector(unsigned(dm_vsize_counter) - 1);
dm_xfred_all_lines <= '0';
end if;
end if;
end process DM_DONE;
end generate GEN_VCOUNT_FOR_SNF;
-- Not store and forward or no line buffer (CR619293)
GEN_NO_VCOUNT_FOR_SNF : if C_LINEBUFFER_DEPTH = 0 or C_INCLUDE_MM2S_SF = 0 generate
begin
dm_vsize_counter <= (others => '0');
dm_xfred_all_lines <= '0';
dm_decr_vcount <= '0';
end generate GEN_NO_VCOUNT_FOR_SNF;
--*****************************************************************************--
--** SPECIAL RESET GENERATION **--
--*****************************************************************************--
-- Assert reset to skid buffer on hard reset or on shutdown when fifo pipe empty
-- Waiting for fifo_pipe_empty is required to prevent a AXIS protocol violation
-- when channel shut down early
REG_SKID_RESET : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_resetn = '0')then
m_skid_reset <= '1';
elsif(fifo_pipe_empty = '1')then
if(fsync_out = '1' or dm_halt_reg = '1')then
m_skid_reset <= '1';
else
m_skid_reset <= '0';
end if;
else
m_skid_reset <= '0';
end if;
end if;
end process REG_SKID_RESET;
-- Fifo/logic reset for slave side clock domain (m_axi_mm2s_aclk)
-- If error (dm_halt=1) then halt immediatly without protocol violation
s_axis_fifo_ainit <= '1' when s_axis_resetn = '0'
or frame_sync = '1' -- Frame sync
or dm_halt = '1' -- Datamover being halted (halt due to error)
else '0';
-- Fifo/logic reset for master side clock domain (m_axis_mm2s_aclk)
m_axis_fifo_ainit <= '1' when m_axis_resetn = '0'
or fsync_out = '1' -- Frame sync
or dm_halt_reg = '1' -- Datamover being halted
else '0';
-- Fifo/logic reset for slave side clock domain (m_axi_mm2s_aclk)
-- If error (dm_halt=1) then halt immediatly without protocol violation
s_axis_fifo_ainit_nosync <= '1' when s_axis_resetn = '0'
or dm_halt = '1' -- Datamover being halted (halt due to error)
else '0';
process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
s_axis_fifo_ainit_nosync_reg <= s_axis_fifo_ainit_nosync;
end if;
end process ;
-- Fifo/logic reset for master side clock domain (m_axis_mm2s_aclk)
m_axis_fifo_ainit_nosync <= '1' when m_axis_resetn = '0'
or dm_halt_reg = '1' -- Datamover being halted
else '0';
--reset for axis_dwidth
mm2s_axis_linebuf_reset_out_inv <= m_axis_fifo_ainit_nosync;
mm2s_axis_linebuf_reset_out <= not (mm2s_axis_linebuf_reset_out_inv);
all_lines_xfred <= mm2s_all_lines_xfred_s_sig;
mm2s_all_lines_xfred_s <= mm2s_all_lines_xfred_s_sig;
--C_DATA_WIDTH = C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED
MM2S_DWIDTH_CONV_IS : if (C_DATA_WIDTH /= C_M_AXIS_MM2S_TDATA_WIDTH) generate
begin
mm2s_all_lines_xfred_s_sig <= mm2s_all_lines_xfred_s_dwidth;
fifo_pipe_empty <= dwidth_fifo_pipe_empty;
dwidth_fifo_pipe_empty_m <= mm2s_fifo_pipe_empty_i;
end generate MM2S_DWIDTH_CONV_IS;
MM2S_DWIDTH_CONV_IS_NOT : if (C_DATA_WIDTH = C_M_AXIS_MM2S_TDATA_WIDTH) generate
begin
mm2s_all_lines_xfred_s_sig <= all_lines_xfred_no_dwidth;
fifo_pipe_empty <= '1' when (all_lines_xfred = '1' and m_axis_tvalid_out = '0') -- All data for frame transmitted
or (sf_threshold_met = '0' -- Or Threshold not met
and stop_reg = '1' -- Commanded to stop
and m_axis_tvalid_out = '0') -- And NOT driving tvalid
else '0';
dwidth_fifo_pipe_empty_m <= '1';
end generate MM2S_DWIDTH_CONV_IS_NOT;
mm2s_fsync_int <= mm2s_fsync and run_stop_reg;
-- Frame sync cross bar
---- FSYNC_CROSSBAR_MM2S_S : process(fsync_src_select_s_int,
---- run_stop_reg,
---- mm2s_fsync,
---- s2mm_fsync_mm2s_s)
---- begin
---- case fsync_src_select_s_int is
----
---- when "00" => -- primary fsync (default)
---- mm2s_fsync_int <= mm2s_fsync and run_stop_reg;
---- when "01" => -- other channel fsync
---- mm2s_fsync_int <= s2mm_fsync_mm2s_s and run_stop_reg;
---- when others =>
---- mm2s_fsync_int <= '0';
---- end case;
---- end process FSYNC_CROSSBAR_MM2S_S;
FSIZE_MISMATCH_MM2S_FLUSH_SOF_s : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk='1')then
if(m_axis_resetn = '0')then
fsize_mismatch_err_int_s <= '0';
-- fsync occurred when not all lines transferred
elsif(mm2s_fsync_int = '1' and mm2s_all_lines_xfred_s_sig = '0')then
fsize_mismatch_err_int_s <= '1';
else
fsize_mismatch_err_int_s <= '0';
end if;
end if;
end process FSIZE_MISMATCH_MM2S_FLUSH_SOF_s;
FSIZE_MISMATCH_FLAG_MM2S_FLUSH_SOF_s : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk='1')then
if(m_axis_resetn = '0' or mm2s_fsync_int = '1')then
fsize_mismatch_err_flag_s <= '0';
elsif(fsize_mismatch_err_int_s = '1')then
fsize_mismatch_err_flag_s <= '1';
end if;
end if;
end process FSIZE_MISMATCH_FLAG_MM2S_FLUSH_SOF_s;
fsize_mismatch_err_flag_cmb_s <= fsize_mismatch_err_int_s or fsize_mismatch_err_flag_s;
MM2S_DROP_RESIDUAL_OF_FSIZE_ERR_FRAME_S <= fsize_mismatch_err_flag_cmb_s;
mm2s_fsize_mismatch_err_s <= fsize_mismatch_err_int_s;
mm2s_fsize_mismatch_err_m <= fsize_mismatch_err_int_m;
mm2s_vsize_cntr_clr_flag <= fsize_mismatch_err_flag_vsize_cntr_clr or fsize_mismatch_err_int_s;
D1_FSYNC_OUT : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk='1')then
if(m_axis_resetn = '0')then
fsync_out_d1 <= '0';
else
fsync_out_d1 <= fsync_out;
end if;
end if;
end process D1_FSYNC_OUT;
FLAG_VSIZE_CNTR_CLR : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk='1')then
if(m_axis_resetn = '0' or fsync_out_d1 = '1')then
fsize_mismatch_err_flag_vsize_cntr_clr <= '0';
elsif(fsize_mismatch_err_int_s = '1')then
fsize_mismatch_err_flag_vsize_cntr_clr <= '1';
end if;
end if;
end process FLAG_VSIZE_CNTR_CLR;
MM2S_FSIZE_ERR_TO_DM_HALT_FLAG : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_resetn = '0' or dm_halt_reg = '1')then
fsize_err_to_dm_halt_flag <= '0';
elsif(fsize_mismatch_err_int_s = '1')then
fsize_err_to_dm_halt_flag <= '1';
end if;
end if;
end process MM2S_FSIZE_ERR_TO_DM_HALT_FLAG;
fsize_err_to_dm_halt_flag_ored <= fsize_mismatch_err_int_s or fsize_err_to_dm_halt_flag or dm_halt_reg;
delay_fsync_fsize_err_till_dm_halt_cmplt_pulse_s <= '1' when fsize_err_to_dm_halt_flag_ored = '1' and mm2s_fsync_int = '1'
else '0';
MM2S_FSIZE_LESS_DM_HALT_CMPLT_FLAG : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_resetn = '0' or fsize_err_to_dm_halt_flag_ored = '0')then
delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s <= '0';
elsif(delay_fsync_fsize_err_till_dm_halt_cmplt_pulse_s = '1')then
delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s <= '1';
end if;
end if;
end process MM2S_FSIZE_LESS_DM_HALT_CMPLT_FLAG;
MM2S_REG_D_FSYNC : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_resetn = '0')then
delay_fsync_fsize_err_till_dm_halt_cmplt_s_d1 <= '0';
else
delay_fsync_fsize_err_till_dm_halt_cmplt_s_d1 <= delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s;
end if;
end if;
end process MM2S_REG_D_FSYNC;
d_fsync_halt_cmplt_s <= delay_fsync_fsize_err_till_dm_halt_cmplt_s_d1 and not delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s;
mm2s_fsync_core <= (mm2s_fsync_int and not (delay_fsync_fsize_err_till_dm_halt_cmplt_pulse_s)) or d_fsync_halt_cmplt_s;
--mm2s_fsync_core <= mm2s_fsync_int;
end generate GEN_LINEBUF_FLUSH_SOF;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_vdma_mm2s_linebuf
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_mm2s_linebuf.vhd
-- Description: This entity encompases the mm2s line buffer logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdma_intrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_reg_if.vhd
-- | |- axi_vdma_lite_if.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sg_if.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdsts_if.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sg_if.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdsts_if.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library lib_cdc_v1_0_2;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_vdma_mm2s_linebuf is
generic (
C_DATA_WIDTH : integer range 8 to 1024 := 32;
C_M_AXIS_MM2S_TDATA_WIDTH : integer range 8 to 1024 := 32;
-- Line Buffer Data Width
C_INCLUDE_S2MM : integer range 0 to 1 := 0;
C_INCLUDE_MM2S_SF : integer range 0 to 1 := 0;
-- Include or exclude MM2S Store And Forward Functionality
-- 0 = Exclude MM2S Store and Forward
-- 1 = Include MM2S Store and Forward
C_INCLUDE_MM2S_DRE : integer range 0 to 1 := 0;
C_MM2S_SOF_ENABLE : integer range 0 to 1 := 0;
-- Enable/Disable start of frame generation on tuser(0). This
-- is only valid for external frame sync (C_USE_FSYNC = 1)
-- 0 = disable SOF
-- 1 = enable SOF
C_M_AXIS_MM2S_TUSER_BITS : integer range 1 to 1 := 1;
-- Master AXI Stream User Width for MM2S Channel
C_TOPLVL_LINEBUFFER_DEPTH : integer range 0 to 65536 := 512; -- CR625142
-- Depth as set by user at top level parameter
C_LINEBUFFER_DEPTH : integer range 0 to 65536 := 512;
-- Linebuffer depth in Bytes. Must be a power of 2
C_LINEBUFFER_AE_THRESH : integer range 1 to 65536 := 1;
-- Linebuffer almost empty threshold in Bytes. Must be a power of 2
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0 ;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
--C_ENABLE_DEBUG_INFO : string := "1111111111111111"; -- 1 to 16 --
--C_ENABLE_DEBUG_INFO : bit_vector(15 downto 0) := (others => '1'); --15 downto 0 --
C_ENABLE_DEBUG_ALL : integer range 0 to 1 := 1;
-- Setting this make core backward compatible to 2012.4 version in terms of ports and registers
C_ENABLE_DEBUG_INFO_0 : integer range 0 to 1 := 1;
-- Enable debug information bit 0
C_ENABLE_DEBUG_INFO_1 : integer range 0 to 1 := 1;
-- Enable debug information bit 1
C_ENABLE_DEBUG_INFO_2 : integer range 0 to 1 := 1;
-- Enable debug information bit 2
C_ENABLE_DEBUG_INFO_3 : integer range 0 to 1 := 1;
-- Enable debug information bit 3
C_ENABLE_DEBUG_INFO_4 : integer range 0 to 1 := 1;
-- Enable debug information bit 4
C_ENABLE_DEBUG_INFO_5 : integer range 0 to 1 := 1;
-- Enable debug information bit 5
C_ENABLE_DEBUG_INFO_6 : integer range 0 to 1 := 1;
-- Enable debug information bit 6
C_ENABLE_DEBUG_INFO_7 : integer range 0 to 1 := 1;
-- Enable debug information bit 7
C_ENABLE_DEBUG_INFO_8 : integer range 0 to 1 := 1;
-- Enable debug information bit 8
C_ENABLE_DEBUG_INFO_9 : integer range 0 to 1 := 1;
-- Enable debug information bit 9
C_ENABLE_DEBUG_INFO_10 : integer range 0 to 1 := 1;
-- Enable debug information bit 10
C_ENABLE_DEBUG_INFO_11 : integer range 0 to 1 := 1;
-- Enable debug information bit 11
C_ENABLE_DEBUG_INFO_12 : integer range 0 to 1 := 1;
-- Enable debug information bit 12
C_ENABLE_DEBUG_INFO_13 : integer range 0 to 1 := 1;
-- Enable debug information bit 13
C_ENABLE_DEBUG_INFO_14 : integer range 0 to 1 := 1;
-- Enable debug information bit 14
C_ENABLE_DEBUG_INFO_15 : integer range 0 to 1 := 1;
-- Enable debug information bit 15
ENABLE_FLUSH_ON_FSYNC : integer range 0 to 1 := 0 ;
C_FAMILY : string := "virtex7"
-- Device family used for proper BRAM selection
);
port (
-- MM2S AXIS Input Side (i.e. Datamover side)
s_axis_aclk : in std_logic ; --
s_axis_resetn : in std_logic ; --
--
-- MM2S AXIS Output Side --
m_axis_aclk : in std_logic ; --
m_axis_resetn : in std_logic ; --
mm2s_axis_linebuf_reset_out : out std_logic ; --
s2mm_axis_resetn : in std_logic := '1' ; --
s_axis_s2mm_aclk : in std_logic := '0' ; --
mm2s_fsync : in std_logic ; --
s2mm_fsync : in std_logic ; --
mm2s_fsync_core : out std_logic ; --
mm2s_fsize_mismatch_err_s : out std_logic ; --
mm2s_fsize_mismatch_err_m : out std_logic ; --
mm2s_vsize_cntr_clr_flag : out std_logic ; --
MM2S_DROP_RESIDUAL_OF_FSIZE_ERR_FRAME_S : out std_logic ; --
fsync_src_select : in std_logic_vector(1 downto 0) ; --
--
run_stop : in std_logic ; --
-- Graceful shut down control --
dm_halt : in std_logic ; --
dm_halt_reg_out : out std_logic ; --
cmdsts_idle : in std_logic ; --
stop : in std_logic ; -- CR623291
stop_reg_out : out std_logic ; -- CR623291
--
-- Vertical Line Count control --
fsync_out : in std_logic ; -- CR616211
fsync_out_m : out std_logic ; -- CR616211
mm2s_fsize_mismatch_err_flag: in std_logic ; -- CR616211
frame_sync : in std_logic ; -- CR616211
crnt_vsize : in std_logic_vector --
(VSIZE_DWIDTH-1 downto 0) ; -- CR616211
crnt_vsize_d2_out : out std_logic_vector --
(VSIZE_DWIDTH-1 downto 0) ; -- CR616211
--
linebuf_threshold : in std_logic_vector --
(LINEBUFFER_THRESH_WIDTH-1 downto 0); --
--
-- Stream In (Datamover To Line Buffer) --
s_axis_tdata : in std_logic_vector --
(C_DATA_WIDTH-1 downto 0) ; --
s_axis_tkeep : in std_logic_vector --
((C_DATA_WIDTH/8)-1 downto 0) ; --
s_axis_tlast : in std_logic ; --
s_axis_tvalid : in std_logic ; --
s_axis_tready : out std_logic ; --
--
--
-- Stream Out (Line Buffer To MM2S AXIS) --
m_axis_tdata : out std_logic_vector --
(C_DATA_WIDTH-1 downto 0) ; --
m_axis_tkeep : out std_logic_vector --
((C_DATA_WIDTH/8)-1 downto 0) ; --
m_axis_tlast : out std_logic ; --
m_axis_tvalid : out std_logic ; --
m_axis_tready : in std_logic ; --
m_axis_tuser : out std_logic_vector --
(C_M_AXIS_MM2S_TUSER_BITS-1 downto 0); --
--
-- Fifo Status Flags --
dwidth_fifo_pipe_empty : in std_logic ; --
dwidth_fifo_pipe_empty_m : out std_logic ; --
mm2s_fifo_pipe_empty : out std_logic ; --
mm2s_fifo_empty : out std_logic ; --
mm2s_fifo_almost_empty : out std_logic ; --
mm2s_all_lines_xfred_s_dwidth : in std_logic ; --
mm2s_all_lines_xfred_s : out std_logic ; --
mm2s_all_lines_xfred : out std_logic -- CR616211
);
end axi_vdma_mm2s_linebuf;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_mm2s_linebuf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Bufer depth
--constant BUFFER_DEPTH : integer := max2(128,C_LINEBUFFER_DEPTH/(C_DATA_WIDTH/8));
constant BUFFER_DEPTH : integer := C_LINEBUFFER_DEPTH;
-- Buffer width is data width + strobe width + 1 bit for tlast
-- Increase data width by 1 when tuser support included.
--constant BUFFER_WIDTH : integer := C_DATA_WIDTH + (C_DATA_WIDTH/8) + 1;
constant BUFFER_WIDTH : integer := C_DATA_WIDTH -- tdata
+ (C_DATA_WIDTH/8)*C_INCLUDE_MM2S_DRE -- tkeep
+ 1 -- tlast
+ (C_MM2S_SOF_ENABLE -- tuser
*C_M_AXIS_MM2S_TUSER_BITS);
-- Buffer data count width
constant DATACOUNT_WIDTH : integer := clog2(BUFFER_DEPTH);
constant DATA_COUNT_ZERO : std_logic_vector(DATACOUNT_WIDTH-1 downto 0)
:= (others => '0');
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
constant ZERO_VALUE_VECT : std_logic_vector(255 downto 0) := (others => '0');
-- Constants for line tracking logic
constant VSIZE_ONE_VALUE : std_logic_vector(VSIZE_DWIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(1,VSIZE_DWIDTH));
constant VSIZE_ZERO_VALUE : std_logic_vector(VSIZE_DWIDTH-1 downto 0)
:= (others => '0');
-- Linebuffer threshold support
constant THRESHOLD_LSB_INDEX : integer := clog2((C_DATA_WIDTH/8));
constant THRESHOLD_PAD : std_logic_vector(THRESHOLD_LSB_INDEX-1 downto 0) := (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal fifo_din : std_logic_vector(BUFFER_WIDTH - 1 downto 0) := (others => '0');
signal fifo_dout : std_logic_vector(BUFFER_WIDTH - 1 downto 0) := (others => '0');
signal fifo_wren : std_logic := '0';
signal fifo_rden : std_logic := '0';
signal fifo_empty_i : std_logic := '0';
signal fifo_full_i : std_logic := '0';
signal fifo_ainit : std_logic := '0';
signal fifo_rdcount : std_logic_vector(DATACOUNT_WIDTH -1 downto 0) := (others => '0');
signal s_axis_tready_i : std_logic := '0'; -- CR619293
signal m_axis_tready_i : std_logic := '0';
signal m_axis_tvalid_i : std_logic := '0';
signal m_axis_tlast_i : std_logic := '0';
signal m_axis_tdata_i : std_logic_vector(C_DATA_WIDTH-1 downto 0):= (others => '0');
signal m_axis_tkeep_i : std_logic_vector((C_DATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_axis_tkeep_signal : std_logic_vector((C_DATA_WIDTH/8)-1 downto 0) := (others => '0');
signal s_axis_tkeep_signal : std_logic_vector((C_DATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_axis_tuser_i : std_logic_vector(C_M_AXIS_MM2S_TUSER_BITS - 1 downto 0) := (others => '0');
signal m_axis_tready_d1 : std_logic := '0';
signal m_axis_tlast_d1 : std_logic := '0';
signal m_axis_tvalid_d1 : std_logic := '0';
signal crnt_vsize_cdc_tig : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0'); -- CR575884
signal crnt_vsize_d1 : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0'); -- CR575884
signal crnt_vsize_d2 : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0'); -- CR575884
signal vsize_counter : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0'); -- CR575884
signal decr_vcount : std_logic := '0'; -- CR575884
signal all_lines_xfred : std_logic := '0'; -- CR616211
signal all_lines_xfred_no_dwidth : std_logic := '0'; -- CR616211
signal mm2s_all_lines_xfred_s_sig : std_logic := '0'; -- CR616211
signal m_axis_tvalid_out : std_logic := '0'; -- CR576993
signal m_axis_tlast_out : std_logic := '0'; -- CR616211
signal slv2skid_s_axis_tvalid : std_logic := '0'; -- CR576993
signal fifo_empty_d1 : std_logic := '0'; -- CR576993
-- FIFO Pipe empty signals
signal fifo_pipe_empty : std_logic := '0';
signal fifo_wren_d1 : std_logic := '0'; -- CR579191
signal pot_empty : std_logic := '0'; -- CR579191
signal fifo_almost_empty_i : std_logic := '1'; -- CR604273/CR604272
signal fifo_almost_empty_d1 : std_logic := '1';
signal fifo_almost_empty_fe : std_logic := '0'; -- CR604273/CR604272
signal fifo_almost_empty_reg : std_logic := '1';
signal data_count_ae_threshold_cdc_tig : std_logic_vector(DATACOUNT_WIDTH-1 downto 0) := (others => '0');
signal data_count_ae_threshold_d1 : std_logic_vector(DATACOUNT_WIDTH-1 downto 0) := (others => '0');
signal data_count_ae_threshold : std_logic_vector(DATACOUNT_WIDTH-1 downto 0) := (others => '0');
signal m_data_count_ae_thresh : std_logic_vector(DATACOUNT_WIDTH-1 downto 0) := (others => '0');
signal sf_threshold_met : std_logic := '0';
signal cmdsts_idle_d1 : std_logic := '0';
signal cmdsts_idle_fe : std_logic := '0';
signal stop_reg : std_logic := '0'; --CR623291
signal s_axis_fifo_ainit : std_logic := '0';
signal m_axis_fifo_ainit : std_logic := '0';
signal s_axis_fifo_ainit_nosync : std_logic := '0';
signal s_axis_fifo_ainit_nosync_reg : std_logic := '0';
signal m_axis_fifo_ainit_nosync : std_logic := '0';
signal dm_decr_vcount : std_logic := '0'; -- CR619293
signal dm_xfred_all_lines : std_logic := '0'; -- CR619293
signal dm_vsize_counter : std_logic_vector(VSIZE_DWIDTH-1 downto 0) := (others => '0'); -- CR619293
signal dm_xfred_all_lines_reg : std_logic := '0'; -- CR619293
signal sof_flag : std_logic := '0';
signal mm2s_fifo_pipe_empty_i : std_logic := '0';
signal frame_sync_d1 : std_logic := '0';
signal m_skid_reset : std_logic := '0';
signal dm_halt_reg : std_logic := '0';
signal mm2s_axis_linebuf_reset_out_inv : std_logic := '0' ; --
signal sof_reset : std_logic := '0';
signal wr_rst_busy_sig : std_logic := '0';
signal rd_rst_busy_sig : std_logic := '0';
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF crnt_vsize_cdc_tig : SIGNAL IS "true";
ATTRIBUTE async_reg OF crnt_vsize_d1 : SIGNAL IS "true";
ATTRIBUTE async_reg OF data_count_ae_threshold_cdc_tig : SIGNAL IS "true";
ATTRIBUTE async_reg OF data_count_ae_threshold_d1 : SIGNAL IS "true";
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
mm2s_fifo_pipe_empty <= mm2s_fifo_pipe_empty_i;
dm_halt_reg_out <= dm_halt_reg;
stop_reg_out <= stop_reg;
crnt_vsize_d2_out <= crnt_vsize_d2;
GEN_MM2S_DRE_ON : if C_INCLUDE_MM2S_DRE = 1 generate
begin
m_axis_tkeep <= m_axis_tkeep_signal;
s_axis_tkeep_signal <= s_axis_tkeep;
end generate GEN_MM2S_DRE_ON;
GEN_MM2S_DRE_OFF : if C_INCLUDE_MM2S_DRE = 0 generate
begin
m_axis_tkeep <= (others => '1');
s_axis_tkeep_signal <= (others => '1');
end generate GEN_MM2S_DRE_OFF;
GEN_LINEBUF_NO_SOF : if (ENABLE_FLUSH_ON_FSYNC = 0 or C_MM2S_SOF_ENABLE = 0) generate
begin
mm2s_fsync_core <= mm2s_fsync;
MM2S_DROP_RESIDUAL_OF_FSIZE_ERR_FRAME_S <= '0';
mm2s_fsize_mismatch_err_s <= '0';
--*****************************************************************************--
--** LINE BUFFER MODE (Sync or Async) **--
--*****************************************************************************--
GEN_LINEBUFFER : if C_LINEBUFFER_DEPTH /= 0 generate
begin
-- Divide by number bytes per data beat and add padding to dynamic
-- threshold setting
data_count_ae_threshold <= linebuf_threshold((DATACOUNT_WIDTH-1) + THRESHOLD_LSB_INDEX
downto THRESHOLD_LSB_INDEX);
-- Synchronous clock therefore instantiate an Asynchronous FIFO
GEN_SYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2_8.axi_vdma_sfifo
generic map(
UW_DATA_WIDTH => BUFFER_WIDTH ,
C_FULL_FLAGS_RST_VAL => 1 ,
UW_FIFO_DEPTH => BUFFER_DEPTH ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
rst => s_axis_fifo_ainit_nosync ,
sleep => '0' ,
wr_rst_busy => wr_rst_busy_sig ,
rd_rst_busy => rd_rst_busy_sig ,
clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i ,
data_count => fifo_rdcount
);
--wr_rst_busy_sig <= '0';
--rd_rst_busy_sig <= '0';
end generate GEN_SYNC_FIFO;
-- Asynchronous clock therefore instantiate an Asynchronous FIFO
GEN_ASYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
LB_BRAM : if ( (C_ENABLE_DEBUG_INFO_1 = 1 or C_ENABLE_DEBUG_ALL = 1) )
generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2_8.axi_vdma_afifo
generic map(
UW_DATA_WIDTH => BUFFER_WIDTH ,
C_FULL_FLAGS_RST_VAL => 1 ,
UW_FIFO_DEPTH => BUFFER_DEPTH ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
rst => s_axis_fifo_ainit_nosync_reg ,
sleep => '0' ,
wr_rst_busy => open ,
rd_rst_busy => open ,
wr_clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_clk => m_axis_aclk ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i ,
wr_data_count => open , --CR622702
rd_data_count => fifo_rdcount
);
wr_rst_busy_sig <= '0';
rd_rst_busy_sig <= '0';
end generate LB_BRAM;
LB_BUILT_IN : if ( (C_ENABLE_DEBUG_INFO_1 = 0 and C_ENABLE_DEBUG_ALL = 0) )
generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2_8.axi_vdma_afifo_builtin
generic map(
PL_FIFO_TYPE => "BUILT_IN" ,
PL_READ_MODE => "FWFT" ,
PL_FASTER_CLOCK => "WR_CLK" , --RD_CLK
PL_FULL_FLAGS_RST_VAL => 0 , -- ?
PL_DATA_WIDTH => BUFFER_WIDTH ,
C_FAMILY => C_FAMILY ,
PL_FIFO_DEPTH => BUFFER_DEPTH
)
port map(
-- Inputs
rst => s_axis_fifo_ainit_nosync_reg ,
sleep => '0' ,
wr_rst_busy => wr_rst_busy_sig ,
rd_rst_busy => rd_rst_busy_sig ,
wr_clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_clk => m_axis_aclk ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i
);
end generate LB_BUILT_IN;
end generate GEN_ASYNC_FIFO;
-- Generate an SOF on tuser(0). currently vdma only support 1 tuser bit that is set by
-- frame sync and driven out on first data beat of mm2s packet.
GEN_SOF : if ENABLE_FLUSH_ON_FSYNC = 0 and C_MM2S_SOF_ENABLE = 1 generate
--signal sof_reset : std_logic := '0';
begin
sof_reset <= '1' when (s_axis_resetn = '0')
or (dm_halt = '1')
else '0';
-- On frame sync set flag and then clear flag when
-- sof written to fifo.
SOF_FLAG_PROCESS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(sof_reset = '1' or fifo_wren = '1')then
sof_flag <= '0';
elsif(frame_sync = '1')then
sof_flag <= '1';
end if;
end if;
end process SOF_FLAG_PROCESS;
GEN_MM2S_DRE_ENABLED_TKEEP : if C_INCLUDE_MM2S_DRE = 1 generate
begin
-- AXI Slave Side of FIFO
fifo_din <= sof_flag & s_axis_tlast & s_axis_tkeep_signal & s_axis_tdata;
fifo_wren <= s_axis_tvalid and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
s_axis_tready <= s_axis_tready_i; -- CR619293
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready_i and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig and sf_threshold_met;
m_axis_tdata_i <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_i <= fifo_dout(BUFFER_WIDTH-3 downto (BUFFER_WIDTH-3) - (C_DATA_WIDTH/8) + 1);
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-2);
m_axis_tuser_i(0) <= fifo_dout(BUFFER_WIDTH-1);
end generate GEN_MM2S_DRE_ENABLED_TKEEP;
GEN_NO_MM2S_DRE_DISABLE_TKEEP : if C_INCLUDE_MM2S_DRE = 0 generate
begin
-- AXI Slave Side of FIFO
fifo_din <= sof_flag & s_axis_tlast & s_axis_tdata;
fifo_wren <= s_axis_tvalid and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
s_axis_tready <= s_axis_tready_i; -- CR619293
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready_i and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig and sf_threshold_met;
m_axis_tdata_i <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_i <= (others => '1');
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-2);
m_axis_tuser_i(0) <= fifo_dout(BUFFER_WIDTH-1);
end generate GEN_NO_MM2S_DRE_DISABLE_TKEEP;
end generate GEN_SOF;
-- SOF turned off therefore do not generate SOF on tuser
GEN_NO_SOF : if C_MM2S_SOF_ENABLE = 0 generate
begin
GEN_MM2S_DRE_ENABLED_TKEEP : if C_INCLUDE_MM2S_DRE = 1 generate
begin
sof_flag <= '0';
-- AXI Slave Side of FIFO
fifo_din <= s_axis_tlast & s_axis_tkeep_signal & s_axis_tdata;
fifo_wren <= s_axis_tvalid and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
s_axis_tready <= s_axis_tready_i; -- CR619293
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready_i and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig and sf_threshold_met;
m_axis_tdata_i <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_i <= fifo_dout(BUFFER_WIDTH-2 downto (BUFFER_WIDTH-2) - (C_DATA_WIDTH/8) + 1);
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-1);
m_axis_tuser_i <= (others => '0');
end generate GEN_MM2S_DRE_ENABLED_TKEEP;
GEN_NO_MM2S_DRE_DISABLE_TKEEP : if C_INCLUDE_MM2S_DRE = 0 generate
begin
sof_flag <= '0';
-- AXI Slave Side of FIFO
fifo_din <= s_axis_tlast & s_axis_tdata;
fifo_wren <= s_axis_tvalid and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
s_axis_tready <= s_axis_tready_i; -- CR619293
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready_i and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig and sf_threshold_met;
m_axis_tdata_i <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_i <= (others => '1');
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-1);
m_axis_tuser_i <= (others => '0');
end generate GEN_NO_MM2S_DRE_DISABLE_TKEEP;
end generate GEN_NO_SOF;
-- Top level line buffer depth not equal to zero therefore gererate threshold
-- flags. (CR625142)
GEN_THRESHOLD_ENABLED : if C_TOPLVL_LINEBUFFER_DEPTH /= 0 and (C_ENABLE_DEBUG_INFO_1 = 1 or C_ENABLE_DEBUG_ALL = 1) generate
begin
-- Almost empty flag (note: asserts when empty also)
REG_ALMST_EMPTY : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
fifo_almost_empty_reg <= '1';
--elsif(fifo_rdcount(DATACOUNT_WIDTH-1 downto 0) <= DATA_COUNT_AE_THRESHOLD or fifo_empty_i = '1')then
--elsif((fifo_rdcount(DATACOUNT_WIDTH-1 downto 0) <= m_data_count_ae_thresh
-- or fifo_empty_i = '1') and fifo_full_i = '0')then
elsif((fifo_rdcount(DATACOUNT_WIDTH-1 downto 0) <= m_data_count_ae_thresh
or (fifo_empty_i = '1' or rd_rst_busy_sig = '1')))then
fifo_almost_empty_reg <= '1';
else
fifo_almost_empty_reg <= '0';
end if;
end if;
end process REG_ALMST_EMPTY;
mm2s_fifo_almost_empty <= fifo_almost_empty_reg
or (not sf_threshold_met) -- CR622777
or (not m_axis_tvalid_out); -- CR625724
mm2s_fifo_empty <= not m_axis_tvalid_out;
end generate GEN_THRESHOLD_ENABLED;
-- Top level line buffer depth is zero therefore turn off threshold logic.
-- this occurs for async operation where the async fifo is needed for CDC (CR625142)
GEN_THRESHOLD_DISABLED : if C_TOPLVL_LINEBUFFER_DEPTH = 0 or (C_ENABLE_DEBUG_INFO_1 = 0 and C_ENABLE_DEBUG_ALL = 0) generate
begin
mm2s_fifo_empty <= '0';
mm2s_fifo_almost_empty <= '0';
fifo_almost_empty_reg <= '0';
end generate GEN_THRESHOLD_DISABLED;
-- CR#578903
-- FIFO, FIFO Pipe, and Skid Buffer are all empty. This is used to safely
-- assert reset on shutdown and also used to safely generate fsync in free-run mode
-- CR622702 - need to look at write side of fifo to prevent false empties due to async fifo
--fifo_pipe_empty <= '1' when (fifo_wrcount(DATACOUNT_WIDTH-1 downto 0) = DATA_COUNT_ZERO -- Data count is 0
-- and m_axis_tvalid_out = '0') -- Skid Buffer is done
-- -- Forced stop and Threshold not met (CR623291)
-- or (sf_threshold_met = '0' and stop_reg = '1')
-- else '0';
-- CR623879 fixed flase fifo_pipe_assertions due to extreme AXI4 throttling on
-- mm2s reads causing fifo to go empty for extended periods of time. This then
-- caused flase idles to be flagged and frame syncs were then generated in free run mode
-------- fifo_pipe_empty <= '1' when (all_lines_xfred = '1' and m_axis_tvalid_out = '0') -- All data for frame transmitted
-------- or (sf_threshold_met = '0' -- Or Threshold not met
-------- and stop_reg = '1' -- Commanded to stop
-------- and m_axis_tvalid_out = '0') -- And NOT driving tvalid
-------- else '0';
--------
-- If store and forward is turned on by user then gate tvalid with
-- threshold met
GEN_THRESH_MET_FOR_SNF : if C_INCLUDE_MM2S_SF = 1 and C_TOPLVL_LINEBUFFER_DEPTH /= 0 and (C_ENABLE_DEBUG_INFO_1 = 1 or C_ENABLE_DEBUG_ALL = 1) generate
begin
-- Register fifo_almost empty in order to generate
-- almost empty fall edge pulse
REG_ALMST_EMPTY_FE : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
fifo_almost_empty_d1 <= '1';
else
fifo_almost_empty_d1 <= fifo_almost_empty_reg;
end if;
end if;
end process REG_ALMST_EMPTY_FE;
-- Almost empty falling edge
fifo_almost_empty_fe <= not fifo_almost_empty_reg and fifo_almost_empty_d1;
-- Store and Forward threshold met
THRESH_MET : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
sf_threshold_met <= '0';
elsif(fsync_out = '1')then
sf_threshold_met <= '0';
-- Reached threshold or all reads done for the frame
elsif(fifo_almost_empty_fe = '1'
or (dm_xfred_all_lines_reg = '1'))then
sf_threshold_met <= '1';
end if;
end if;
end process THRESH_MET;
end generate GEN_THRESH_MET_FOR_SNF;
-- Store and forward off therefore do not need to meet threshold
GEN_NO_THRESH_MET_FOR_SNF : if C_INCLUDE_MM2S_SF = 0 or C_TOPLVL_LINEBUFFER_DEPTH = 0 or (C_ENABLE_DEBUG_INFO_1 = 0 and C_ENABLE_DEBUG_ALL = 0) generate
begin
sf_threshold_met <= '1';
end generate GEN_NO_THRESH_MET_FOR_SNF;
--*********************************************************--
--** MM2S MASTER SKID BUFFER **--
--*********************************************************--
I_MSTR_SKID : entity axi_vdma_v6_2_8.axi_vdma_skid_buf
generic map(
C_WDATA_WIDTH => C_DATA_WIDTH ,
C_TUSER_WIDTH => C_M_AXIS_MM2S_TUSER_BITS
)
port map(
-- System Ports
ACLK => m_axis_aclk ,
ARST => m_axis_fifo_ainit_nosync ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => '0' ,
-- Slave Side (Stream Data Input)
S_VALID => m_axis_tvalid_i ,
S_READY => m_axis_tready_i ,
S_Data => m_axis_tdata_i ,
S_STRB => m_axis_tkeep_i ,
S_Last => m_axis_tlast_i ,
S_User => m_axis_tuser_i ,
-- Master Side (Stream Data Output)
M_VALID => m_axis_tvalid_out ,
M_READY => m_axis_tready ,
M_Data => m_axis_tdata ,
M_STRB => m_axis_tkeep_signal ,
M_Last => m_axis_tlast_out ,
M_User => m_axis_tuser
);
-- Pass out of core
m_axis_tvalid <= m_axis_tvalid_out;
m_axis_tlast <= m_axis_tlast_out;
-- Register to break long timing paths for use in
-- transfer complete generation
REG_STRM_SIGS : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
m_axis_tlast_d1 <= '0';
m_axis_tvalid_d1 <= '0';
m_axis_tready_d1 <= '0';
else
m_axis_tlast_d1 <= m_axis_tlast_out;
m_axis_tvalid_d1 <= m_axis_tvalid_out;
m_axis_tready_d1 <= m_axis_tready;
end if;
end if;
end process REG_STRM_SIGS;
end generate GEN_LINEBUFFER;
--*****************************************************************************--
--** NO LINE BUFFER MODE (Sync Only) **--
--*****************************************************************************--
-- LineBuffer forced on if asynchronous mode is enabled
GEN_NO_LINEBUFFER : if (C_LINEBUFFER_DEPTH = 0) generate -- No Line Buffer
begin
-- Map Datamover to AXIS Master Out
m_axis_tdata <= s_axis_tdata;
m_axis_tkeep_signal <= s_axis_tkeep_signal;
m_axis_tvalid <= s_axis_tvalid;
m_axis_tlast <= s_axis_tlast;
s_axis_tready <= m_axis_tready;
-- Tie FIFO Flags off
mm2s_fifo_empty <= '0';
mm2s_fifo_almost_empty <= '0';
-- Generate sof on tuser(0)
GEN_SOF : if C_MM2S_SOF_ENABLE = 1 generate
begin
-- On frame sync set flag and then clear flag when
-- sof written to fifo.
SOF_FLAG_PROCESS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit = '1' or (s_axis_tvalid = '1' and m_axis_tready = '1'))then
sof_flag <= '0';
elsif(frame_sync = '1')then
sof_flag <= '1';
end if;
end if;
end process SOF_FLAG_PROCESS;
m_axis_tuser(0) <= sof_flag;
end generate GEN_SOF;
-- Do not generate sof on tuser(0)
GEN_NO_SOF : if C_MM2S_SOF_ENABLE = 0 generate
begin
sof_flag <= '0';
m_axis_tuser <= (others => '0');
end generate GEN_NO_SOF;
-- CR#578903
-- Register tvalid to break timing paths for use in
-- psuedo fifo empty for channel idle generation and
-- for xfer complete generation.
REG_STRM_SIGS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
m_axis_tvalid_d1 <= '0';
m_axis_tlast_d1 <= '0';
m_axis_tready_d1 <= '0';
else
m_axis_tvalid_d1 <= s_axis_tvalid;
m_axis_tlast_d1 <= s_axis_tlast;
m_axis_tready_d1 <= m_axis_tready;
end if;
end if;
end process REG_STRM_SIGS;
-- CR#578903
-- Psuedo FIFO, FIFO Pipe, and Skid Buffer are all empty. This is used to safely
-- assert reset on shutdown and also used to safely generate fsync in free-run mode
-- This flag is looked at at the end of frames.
-- Order of else-if is critical
-- CR579191 modified method to prevent double fsync assertions
REG_PIPE_EMPTY : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
fifo_pipe_empty <= '1';
-- Command/Status not idle indicates pending datamover commands
-- set psuedo fifo empty to NOT empty.
elsif(cmdsts_idle_fe = '1')then
fifo_pipe_empty <= '0';
-- On accepted tlast then clear psuedo empty flag back to being empty
elsif(pot_empty = '1' and cmdsts_idle = '1')then
fifo_pipe_empty <= '1';
end if;
end if;
end process REG_PIPE_EMPTY;
REG_IDLE_FE : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
cmdsts_idle_d1 <= '1';
else
cmdsts_idle_d1 <= cmdsts_idle;
end if;
end if;
end process REG_IDLE_FE;
-- CR579586 Use falling edge to set pfifo empty
cmdsts_idle_fe <= not cmdsts_idle and cmdsts_idle_d1;
-- CR579191
POTENTIAL_EMPTY_PROCESS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
pot_empty <= '1';
elsif(m_axis_tvalid_d1 = '1' and m_axis_tlast_d1 = '1' and m_axis_tready_d1 = '1')then
pot_empty <= '1';
elsif(m_axis_tvalid_d1 = '1' and m_axis_tlast_d1 = '0')then
pot_empty <= '0';
end if;
end if;
end process POTENTIAL_EMPTY_PROCESS;
end generate GEN_NO_LINEBUFFER;
--*****************************************************************************--
--** MM2S ASYNCH CLOCK SUPPORT **--
--*****************************************************************************--
-- Cross fifo pipe empty flag to secondary clock domain
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Pipe Empty and Shutdown reset CDC
---- SHUTDOWN_RST_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => fifo_pipe_empty ,
---- scndry_out => mm2s_fifo_pipe_empty_i ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
SHUTDOWN_RST_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => fifo_pipe_empty,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => mm2s_fifo_pipe_empty_i,
scndry_vect_out => open
);
-- Vertical Count and All Lines Transferred CDC (CR616211)
---- ALL_LINES_XFRED_P_S_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' , -- CR619293
---- prmry_out => open , -- CR619293
---- prmry_in => all_lines_xfred ,
---- scndry_out => mm2s_all_lines_xfred ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
----
ALL_LINES_XFRED_P_S_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => all_lines_xfred,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => mm2s_all_lines_xfred,
scndry_vect_out => open
);
-- Vertical Count and All Lines Transferred CDC (CR616211)
---- ALL_LINES_XFRED_S_P_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => dm_xfred_all_lines , -- CR619293
---- prmry_out => dm_xfred_all_lines_reg , -- CR619293
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
ALL_LINES_XFRED_S_P_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => dm_xfred_all_lines,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => dm_xfred_all_lines_reg,
scndry_vect_out => open
);
VSIZE_CNT_CROSSING : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
crnt_vsize_cdc_tig <= crnt_vsize;
crnt_vsize_d1 <= crnt_vsize_cdc_tig;
end if;
end process VSIZE_CNT_CROSSING;
crnt_vsize_d2 <= crnt_vsize_d1;
-- Cross stop signal (CR623291)
---- STOP_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => stop ,
---- prmry_out => stop_reg ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
STOP_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => stop,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => stop_reg,
scndry_vect_out => open
);
-- Cross datamover halt and threshold signals
---- HALT_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => dm_halt ,
---- prmry_out => dm_halt_reg ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- scndry_vect_out => open
---- );
----
HALT_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => dm_halt,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => dm_halt_reg,
scndry_vect_out => open
);
THRESH_CNT_CROSSING : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
data_count_ae_threshold_cdc_tig <= data_count_ae_threshold;
data_count_ae_threshold_d1 <= data_count_ae_threshold_cdc_tig;
end if;
end process THRESH_CNT_CROSSING;
m_data_count_ae_thresh <= data_count_ae_threshold_d1;
end generate GEN_FOR_ASYNC;
--*****************************************************************************--
--** MM2S SYNCH CLOCK SUPPORT **--
--*****************************************************************************--
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
mm2s_fifo_pipe_empty_i <= fifo_pipe_empty;
crnt_vsize_d2 <= crnt_vsize; -- CR616211
mm2s_all_lines_xfred <= all_lines_xfred; -- CR616211
dm_xfred_all_lines_reg <= dm_xfred_all_lines; -- CR619293
stop_reg <= stop; -- CR623291
dm_halt_reg <= dm_halt;
m_data_count_ae_thresh <= data_count_ae_threshold;
end generate GEN_FOR_SYNC;
--*****************************************************************************
--** Vertical Line Tracking (CR616211)
--*****************************************************************************
-- Decrement vertical count with each accept tlast
decr_vcount <= '1' when m_axis_tlast_d1 = '1'
and m_axis_tvalid_d1 = '1'
and m_axis_tready_d1 = '1'
else '0';
-- Drive ready at fsync out then de-assert once all lines have
-- been accepted.
VERT_COUNTER : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1' and fsync_out = '0')then
vsize_counter <= (others => '0');
all_lines_xfred <= '1';
elsif(fsync_out = '1')then
vsize_counter <= crnt_vsize_d2;
all_lines_xfred <= '0';
elsif(decr_vcount = '1' and vsize_counter = VSIZE_ONE_VALUE)then
vsize_counter <= (others => '0');
all_lines_xfred <= '1';
elsif(decr_vcount = '1' and vsize_counter /= VSIZE_ZERO_VALUE)then
vsize_counter <= std_logic_vector(unsigned(vsize_counter) - 1);
all_lines_xfred <= '0';
end if;
end if;
end process VERT_COUNTER;
-- Store and forward or no line buffer (CR619293)
GEN_VCOUNT_FOR_SNF : if C_LINEBUFFER_DEPTH /= 0 and C_INCLUDE_MM2S_SF = 1 generate
begin
dm_decr_vcount <= '1' when s_axis_tlast = '1'
and s_axis_tvalid = '1'
and s_axis_tready_i = '1'
else '0';
-- Delay 1 pipe to align with cnrt_vsize
REG_FSYNC_TO_ALIGN : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit = '1' and frame_sync = '0')then
frame_sync_d1 <= '0';
else
frame_sync_d1 <= frame_sync;
end if;
end if;
end process REG_FSYNC_TO_ALIGN;
-- Count lines to determine when datamover done. Used for snf mode
-- for threshold met (CR619293)
DM_DONE : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit = '1')then
dm_vsize_counter <= (others => '0');
dm_xfred_all_lines <= '0';
--elsif(fsync_out = '1')then -- CR623088
elsif(frame_sync_d1 = '1')then -- CR623088
dm_vsize_counter <= crnt_vsize;
dm_xfred_all_lines <= '0';
elsif(dm_decr_vcount = '1' and dm_vsize_counter = VSIZE_ONE_VALUE)then
dm_vsize_counter <= (others => '0');
dm_xfred_all_lines <= '1';
elsif(dm_decr_vcount = '1' and dm_vsize_counter /= VSIZE_ZERO_VALUE)then
dm_vsize_counter <= std_logic_vector(unsigned(dm_vsize_counter) - 1);
dm_xfred_all_lines <= '0';
end if;
end if;
end process DM_DONE;
end generate GEN_VCOUNT_FOR_SNF;
-- Not store and forward or no line buffer (CR619293)
GEN_NO_VCOUNT_FOR_SNF : if C_LINEBUFFER_DEPTH = 0 or C_INCLUDE_MM2S_SF = 0 generate
begin
dm_vsize_counter <= (others => '0');
dm_xfred_all_lines <= '0';
dm_decr_vcount <= '0';
end generate GEN_NO_VCOUNT_FOR_SNF;
--*****************************************************************************--
--** SPECIAL RESET GENERATION **--
--*****************************************************************************--
-- Assert reset to skid buffer on hard reset or on shutdown when fifo pipe empty
-- Waiting for fifo_pipe_empty is required to prevent a AXIS protocol violation
-- when channel shut down early
REG_SKID_RESET : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_resetn = '0')then
m_skid_reset <= '1';
elsif(fifo_pipe_empty = '1')then
if(fsync_out = '1' or dm_halt_reg = '1')then
m_skid_reset <= '1';
else
m_skid_reset <= '0';
end if;
else
m_skid_reset <= '0';
end if;
end if;
end process REG_SKID_RESET;
-- Fifo/logic reset for slave side clock domain (m_axi_mm2s_aclk)
-- If error (dm_halt=1) then halt immediatly without protocol violation
s_axis_fifo_ainit <= '1' when s_axis_resetn = '0'
or frame_sync = '1' -- Frame sync
or dm_halt = '1' -- Datamover being halted (halt due to error)
else '0';
-- Fifo/logic reset for master side clock domain (m_axis_mm2s_aclk)
m_axis_fifo_ainit <= '1' when m_axis_resetn = '0'
or fsync_out = '1' -- Frame sync
or dm_halt_reg = '1' -- Datamover being halted
else '0';
-- Fifo/logic reset for slave side clock domain (m_axi_mm2s_aclk)
-- If error (dm_halt=1) then halt immediatly without protocol violation
s_axis_fifo_ainit_nosync <= '1' when s_axis_resetn = '0'
or dm_halt = '1' -- Datamover being halted (halt due to error)
else '0';
process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
s_axis_fifo_ainit_nosync_reg <= s_axis_fifo_ainit_nosync;
end if;
end process ;
-- Fifo/logic reset for master side clock domain (m_axis_mm2s_aclk)
m_axis_fifo_ainit_nosync <= '1' when m_axis_resetn = '0'
or dm_halt_reg = '1' -- Datamover being halted
else '0';
--reset for axis_dwidth
mm2s_axis_linebuf_reset_out_inv <= m_axis_fifo_ainit_nosync;
mm2s_axis_linebuf_reset_out <= not (mm2s_axis_linebuf_reset_out_inv);
MM2S_DWIDTH_CONV_IS : if (C_DATA_WIDTH /= C_M_AXIS_MM2S_TDATA_WIDTH) generate
begin
fifo_pipe_empty <= dwidth_fifo_pipe_empty;
dwidth_fifo_pipe_empty_m <= mm2s_fifo_pipe_empty_i;
end generate MM2S_DWIDTH_CONV_IS;
MM2S_DWIDTH_CONV_IS_NOT : if (C_DATA_WIDTH = C_M_AXIS_MM2S_TDATA_WIDTH) generate
begin
fifo_pipe_empty <= '1' when (all_lines_xfred = '1' and m_axis_tvalid_out = '0') -- All data for frame transmitted
or (sf_threshold_met = '0' -- Or Threshold not met
and stop_reg = '1' -- Commanded to stop
and m_axis_tvalid_out = '0') -- And NOT driving tvalid
else '0';
dwidth_fifo_pipe_empty_m <= '1';
end generate MM2S_DWIDTH_CONV_IS_NOT;
mm2s_all_lines_xfred_s <= '0';
fsync_out_m <= '0';
mm2s_vsize_cntr_clr_flag <= '0';
mm2s_fsize_mismatch_err_m <= '0';
end generate GEN_LINEBUF_NO_SOF;
GEN_LINEBUF_FLUSH_SOF : if (ENABLE_FLUSH_ON_FSYNC = 1 and C_MM2S_SOF_ENABLE = 1) generate
signal s2mm_fsync_mm2s_s : std_logic := '0';
signal run_stop_reg : std_logic := '0';
signal fsync_out_d1 : std_logic := '0';
signal mm2s_fsync_int : std_logic := '0';
signal fsize_mismatch_err_int_s : std_logic := '0';
signal fsize_mismatch_err_int_m : std_logic := '0';
signal fsize_mismatch_err_flag_s : std_logic := '0';
signal fsize_mismatch_err_flag_vsize_cntr_clr : std_logic := '0';
signal fsize_mismatch_err_flag_cmb_s : std_logic := '0';
signal fsync_src_select_cdc_tig : std_logic_vector(1 downto 0) := (others => '0');
signal fsync_src_select_d1 : std_logic_vector(1 downto 0) := (others => '0');
signal fsync_src_select_s_int : std_logic_vector(1 downto 0) := (others => '0');
signal fsize_err_to_dm_halt_flag : std_logic := '0';
signal fsize_err_to_dm_halt_flag_ored : std_logic := '0';
signal delay_fsync_fsize_err_till_dm_halt_cmplt_pulse_s : std_logic := '0';
signal delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s : std_logic := '0';
signal delay_fsync_fsize_err_till_dm_halt_cmplt_s_d1 : std_logic := '0';
signal d_fsync_halt_cmplt_s : std_logic := '0';
ATTRIBUTE async_reg : STRING;
ATTRIBUTE async_reg OF fsync_src_select_cdc_tig : SIGNAL IS "true";
ATTRIBUTE async_reg OF fsync_src_select_d1 : SIGNAL IS "true";
begin
--*****************************************************************************--
--** LINE BUFFER MODE (Sync or Async) **--
--*****************************************************************************--
GEN_LINEBUFFER : if C_LINEBUFFER_DEPTH /= 0 generate
begin
-- Divide by number bytes per data beat and add padding to dynamic
-- threshold setting
data_count_ae_threshold <= linebuf_threshold((DATACOUNT_WIDTH-1) + THRESHOLD_LSB_INDEX
downto THRESHOLD_LSB_INDEX);
-- Synchronous clock therefore instantiate an Asynchronous FIFO
GEN_SYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2_8.axi_vdma_sfifo
generic map(
UW_DATA_WIDTH => BUFFER_WIDTH ,
C_FULL_FLAGS_RST_VAL => 1 ,
UW_FIFO_DEPTH => BUFFER_DEPTH ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
rst => s_axis_fifo_ainit_nosync ,
sleep => '0' ,
wr_rst_busy => wr_rst_busy_sig ,
rd_rst_busy => rd_rst_busy_sig ,
clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i ,
data_count => fifo_rdcount
);
--wr_rst_busy_sig <= '0';
--rd_rst_busy_sig <= '0';
end generate GEN_SYNC_FIFO;
-- Asynchronous clock therefore instantiate an Asynchronous FIFO
GEN_ASYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
LB_BRAM : if ( (C_ENABLE_DEBUG_INFO_1 = 1 or C_ENABLE_DEBUG_ALL = 1) )
generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2_8.axi_vdma_afifo
generic map(
UW_DATA_WIDTH => BUFFER_WIDTH ,
C_FULL_FLAGS_RST_VAL => 1 ,
UW_FIFO_DEPTH => BUFFER_DEPTH ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
rst => s_axis_fifo_ainit_nosync_reg ,
sleep => '0' ,
wr_rst_busy => open ,
rd_rst_busy => open ,
wr_clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_clk => m_axis_aclk ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i ,
wr_data_count => open , --CR622702
rd_data_count => fifo_rdcount
);
wr_rst_busy_sig <= '0';
rd_rst_busy_sig <= '0';
end generate LB_BRAM;
LB_BUILT_IN : if ( (C_ENABLE_DEBUG_INFO_1 = 0 and C_ENABLE_DEBUG_ALL = 0) )
generate
begin
I_LINEBUFFER_FIFO : entity axi_vdma_v6_2_8.axi_vdma_afifo_builtin
generic map(
PL_FIFO_TYPE => "BUILT_IN" ,
PL_READ_MODE => "FWFT" ,
PL_FASTER_CLOCK => "WR_CLK" , --RD_CLK
PL_FULL_FLAGS_RST_VAL => 0 , -- ?
PL_DATA_WIDTH => BUFFER_WIDTH ,
C_FAMILY => C_FAMILY ,
PL_FIFO_DEPTH => BUFFER_DEPTH
)
port map(
-- Inputs
rst => s_axis_fifo_ainit_nosync_reg ,
sleep => '0' ,
wr_rst_busy => wr_rst_busy_sig ,
rd_rst_busy => rd_rst_busy_sig ,
wr_clk => s_axis_aclk ,
wr_en => fifo_wren ,
din => fifo_din ,
rd_clk => m_axis_aclk ,
rd_en => fifo_rden ,
-- Outputs
dout => fifo_dout ,
full => fifo_full_i ,
empty => fifo_empty_i
);
end generate LB_BUILT_IN;
end generate GEN_ASYNC_FIFO;
-- Generate an SOF on tuser(0). currently vdma only support 1 tuser bit that is set by
-- frame sync and driven out on first data beat of mm2s packet.
------ GEN_SOF : if C_MM2S_SOF_ENABLE = 1 generate
------ signal sof_reset : std_logic := '0';
------ begin
sof_reset <= '1' when (s_axis_resetn = '0')
or (dm_halt = '1')
else '0';
-- On frame sync set flag and then clear flag when
-- sof written to fifo.
SOF_FLAG_PROCESS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(sof_reset = '1' or fifo_wren = '1')then
sof_flag <= '0';
elsif(frame_sync = '1')then
sof_flag <= '1';
end if;
end if;
end process SOF_FLAG_PROCESS;
GEN_MM2S_DRE_ENABLED_TKEEP : if C_INCLUDE_MM2S_DRE = 1 generate
begin
-- AXI Slave Side of FIFO
fifo_din <= sof_flag & s_axis_tlast & s_axis_tkeep_signal & s_axis_tdata;
fifo_wren <= s_axis_tvalid and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
s_axis_tready <= s_axis_tready_i; -- CR619293
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready_i and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig and sf_threshold_met;
m_axis_tdata_i <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_i <= fifo_dout(BUFFER_WIDTH-3 downto (BUFFER_WIDTH-3) - (C_DATA_WIDTH/8) + 1);
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-2);
m_axis_tuser_i(0) <= fifo_dout(BUFFER_WIDTH-1);
end generate GEN_MM2S_DRE_ENABLED_TKEEP;
GEN_NO_MM2S_DRE_DISABLE_TKEEP : if C_INCLUDE_MM2S_DRE = 0 generate
begin
-- AXI Slave Side of FIFO
fifo_din <= sof_flag & s_axis_tlast & s_axis_tdata;
fifo_wren <= s_axis_tvalid and s_axis_tready_i;
s_axis_tready_i <= not fifo_full_i and not wr_rst_busy_sig and not s_axis_fifo_ainit;
s_axis_tready <= s_axis_tready_i; -- CR619293
-- AXI Master Side of FIFO
fifo_rden <= m_axis_tready_i and m_axis_tvalid_i;
m_axis_tvalid_i <= not fifo_empty_i and not rd_rst_busy_sig and sf_threshold_met;
m_axis_tdata_i <= fifo_dout(C_DATA_WIDTH-1 downto 0);
m_axis_tkeep_i <= (others => '1');
m_axis_tlast_i <= fifo_dout(BUFFER_WIDTH-2);
m_axis_tuser_i(0) <= fifo_dout(BUFFER_WIDTH-1);
end generate GEN_NO_MM2S_DRE_DISABLE_TKEEP;
------ end generate GEN_SOF;
------
------
-- SOF turned off therefore do not generate SOF on tuser
---------- GEN_NO_SOF : if C_MM2S_SOF_ENABLE = 0 generate
---------- begin
----------
---------- sof_flag <= '0';
----------
---------- -- AXI Slave Side of FIFO
---------- fifo_din <= s_axis_tlast & s_axis_tkeep & s_axis_tdata;
---------- fifo_wren <= s_axis_tvalid and not fifo_full_i and not s_axis_fifo_ainit;
---------- s_axis_tready_i <= not fifo_full_i and not s_axis_fifo_ainit;
---------- s_axis_tready <= s_axis_tready_i; -- CR619293
----------
---------- -- AXI Master Side of FIFO
---------- fifo_rden <= m_axis_tready_i and not fifo_empty_i and sf_threshold_met;
---------- m_axis_tvalid_i <= not fifo_empty_i and sf_threshold_met;
---------- m_axis_tdata_i <= fifo_dout(C_DATA_WIDTH-1 downto 0);
---------- m_axis_tkeep_i <= fifo_dout(BUFFER_WIDTH-2 downto (BUFFER_WIDTH-2) - (C_DATA_WIDTH/8) + 1);
---------- m_axis_tlast_i <= not fifo_empty_i and fifo_dout(BUFFER_WIDTH-1);
---------- m_axis_tuser_i <= (others => '0');
----------
---------- end generate GEN_NO_SOF;
-- Top level line buffer depth not equal to zero therefore gererate threshold
-- flags. (CR625142)
GEN_THRESHOLD_ENABLED : if C_TOPLVL_LINEBUFFER_DEPTH /= 0 and (C_ENABLE_DEBUG_INFO_1 = 1 or C_ENABLE_DEBUG_ALL = 1) generate
begin
-- Almost empty flag (note: asserts when empty also)
REG_ALMST_EMPTY : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
fifo_almost_empty_reg <= '1';
--elsif(fifo_rdcount(DATACOUNT_WIDTH-1 downto 0) <= DATA_COUNT_AE_THRESHOLD or fifo_empty_i = '1')then
--elsif((fifo_rdcount(DATACOUNT_WIDTH-1 downto 0) <= m_data_count_ae_thresh
-- or fifo_empty_i = '1') and fifo_full_i = '0')then
elsif((fifo_rdcount(DATACOUNT_WIDTH-1 downto 0) <= m_data_count_ae_thresh
or (fifo_empty_i = '1' or rd_rst_busy_sig = '1')))then
fifo_almost_empty_reg <= '1';
else
fifo_almost_empty_reg <= '0';
end if;
end if;
end process REG_ALMST_EMPTY;
mm2s_fifo_almost_empty <= fifo_almost_empty_reg
or (not sf_threshold_met) -- CR622777
or (not m_axis_tvalid_out); -- CR625724
mm2s_fifo_empty <= not m_axis_tvalid_out;
end generate GEN_THRESHOLD_ENABLED;
-- Top level line buffer depth is zero therefore turn off threshold logic.
-- this occurs for async operation where the async fifo is needed for CDC (CR625142)
GEN_THRESHOLD_DISABLED : if C_TOPLVL_LINEBUFFER_DEPTH = 0 or (C_ENABLE_DEBUG_INFO_1 = 0 and C_ENABLE_DEBUG_ALL = 0) generate
begin
mm2s_fifo_empty <= '0';
mm2s_fifo_almost_empty <= '0';
fifo_almost_empty_reg <= '0';
end generate GEN_THRESHOLD_DISABLED;
-- CR#578903
-- FIFO, FIFO Pipe, and Skid Buffer are all empty. This is used to safely
-- assert reset on shutdown and also used to safely generate fsync in free-run mode
-- CR622702 - need to look at write side of fifo to prevent false empties due to async fifo
--fifo_pipe_empty <= '1' when (fifo_wrcount(DATACOUNT_WIDTH-1 downto 0) = DATA_COUNT_ZERO -- Data count is 0
-- and m_axis_tvalid_out = '0') -- Skid Buffer is done
-- -- Forced stop and Threshold not met (CR623291)
-- or (sf_threshold_met = '0' and stop_reg = '1')
-- else '0';
-- CR623879 fixed flase fifo_pipe_assertions due to extreme AXI4 throttling on
-- mm2s reads causing fifo to go empty for extended periods of time. This then
-- caused flase idles to be flagged and frame syncs were then generated in free run mode
---------------- fifo_pipe_empty <= '1' when (all_lines_xfred = '1' and m_axis_tvalid_out = '0') -- All data for frame transmitted
---------------- or (sf_threshold_met = '0' -- Or Threshold not met
---------------- and stop_reg = '1' -- Commanded to stop
---------------- and m_axis_tvalid_out = '0') -- And NOT driving tvalid
---------------- else '0';
----------------
-- If store and forward is turned on by user then gate tvalid with
-- threshold met
GEN_THRESH_MET_FOR_SNF : if C_INCLUDE_MM2S_SF = 1 and C_TOPLVL_LINEBUFFER_DEPTH /= 0 and (C_ENABLE_DEBUG_INFO_1 = 1 or C_ENABLE_DEBUG_ALL = 1) generate
begin
-- Register fifo_almost empty in order to generate
-- almost empty fall edge pulse
REG_ALMST_EMPTY_FE : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
fifo_almost_empty_d1 <= '1';
else
fifo_almost_empty_d1 <= fifo_almost_empty_reg;
end if;
end if;
end process REG_ALMST_EMPTY_FE;
-- Almost empty falling edge
fifo_almost_empty_fe <= not fifo_almost_empty_reg and fifo_almost_empty_d1;
-- Store and Forward threshold met
THRESH_MET : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
sf_threshold_met <= '0';
elsif(fsync_out = '1')then
sf_threshold_met <= '0';
-- Reached threshold or all reads done for the frame
elsif(fifo_almost_empty_fe = '1'
or (dm_xfred_all_lines_reg = '1'))then
sf_threshold_met <= '1';
end if;
end if;
end process THRESH_MET;
end generate GEN_THRESH_MET_FOR_SNF;
-- Store and forward off therefore do not need to meet threshold
GEN_NO_THRESH_MET_FOR_SNF : if C_INCLUDE_MM2S_SF = 0 or C_TOPLVL_LINEBUFFER_DEPTH = 0 or (C_ENABLE_DEBUG_INFO_1 = 0 and C_ENABLE_DEBUG_ALL = 0) generate
begin
sf_threshold_met <= '1';
end generate GEN_NO_THRESH_MET_FOR_SNF;
--*********************************************************--
--** MM2S MASTER SKID BUFFER **--
--*********************************************************--
I_MSTR_SKID : entity axi_vdma_v6_2_8.axi_vdma_skid_buf
generic map(
C_WDATA_WIDTH => C_DATA_WIDTH ,
C_TUSER_WIDTH => C_M_AXIS_MM2S_TUSER_BITS
)
port map(
-- System Ports
ACLK => m_axis_aclk ,
ARST => m_axis_fifo_ainit_nosync ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => '0' ,
-- Slave Side (Stream Data Input)
S_VALID => m_axis_tvalid_i ,
S_READY => m_axis_tready_i ,
S_Data => m_axis_tdata_i ,
S_STRB => m_axis_tkeep_i ,
S_Last => m_axis_tlast_i ,
S_User => m_axis_tuser_i ,
-- Master Side (Stream Data Output)
M_VALID => m_axis_tvalid_out ,
M_READY => m_axis_tready ,
M_Data => m_axis_tdata ,
M_STRB => m_axis_tkeep_signal ,
M_Last => m_axis_tlast_out ,
M_User => m_axis_tuser
);
-- Pass out of core
m_axis_tvalid <= m_axis_tvalid_out;
m_axis_tlast <= m_axis_tlast_out;
-- Register to break long timing paths for use in
-- transfer complete generation
REG_STRM_SIGS : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_fifo_ainit = '1')then
m_axis_tlast_d1 <= '0';
m_axis_tvalid_d1 <= '0';
m_axis_tready_d1 <= '0';
else
m_axis_tlast_d1 <= m_axis_tlast_out;
m_axis_tvalid_d1 <= m_axis_tvalid_out;
m_axis_tready_d1 <= m_axis_tready;
end if;
end if;
end process REG_STRM_SIGS;
end generate GEN_LINEBUFFER;
--*****************************************************************************--
--** NO LINE BUFFER MODE (Sync Only) **--
--*****************************************************************************--
-- LineBuffer forced on if asynchronous mode is enabled
GEN_NO_LINEBUFFER : if (C_LINEBUFFER_DEPTH = 0) generate -- No Line Buffer
begin
-- Map Datamover to AXIS Master Out
m_axis_tdata <= s_axis_tdata;
m_axis_tkeep_signal <= s_axis_tkeep_signal;
m_axis_tvalid <= s_axis_tvalid;
m_axis_tlast <= s_axis_tlast;
s_axis_tready <= m_axis_tready;
-- Tie FIFO Flags off
mm2s_fifo_empty <= '0';
mm2s_fifo_almost_empty <= '0';
-- Generate sof on tuser(0)
---- GEN_SOF : if C_MM2S_SOF_ENABLE = 1 generate
--- begin
-- On frame sync set flag and then clear flag when
-- sof written to fifo.
SOF_FLAG_PROCESS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit = '1' or (s_axis_tvalid = '1' and m_axis_tready = '1'))then
sof_flag <= '0';
elsif(frame_sync = '1')then
sof_flag <= '1';
end if;
end if;
end process SOF_FLAG_PROCESS;
m_axis_tuser(0) <= sof_flag;
--- end generate GEN_SOF;
-- Do not generate sof on tuser(0)
----- GEN_NO_SOF : if C_MM2S_SOF_ENABLE = 0 generate
----- begin
----- sof_flag <= '0';
----- m_axis_tuser <= (others => '0');
----- end generate GEN_NO_SOF;
-- CR#578903
-- Register tvalid to break timing paths for use in
-- psuedo fifo empty for channel idle generation and
-- for xfer complete generation.
REG_STRM_SIGS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
m_axis_tvalid_d1 <= '0';
m_axis_tlast_d1 <= '0';
m_axis_tready_d1 <= '0';
else
m_axis_tvalid_d1 <= s_axis_tvalid;
m_axis_tlast_d1 <= s_axis_tlast;
m_axis_tready_d1 <= m_axis_tready;
end if;
end if;
end process REG_STRM_SIGS;
-- CR#578903
-- Psuedo FIFO, FIFO Pipe, and Skid Buffer are all empty. This is used to safely
-- assert reset on shutdown and also used to safely generate fsync in free-run mode
-- This flag is looked at at the end of frames.
-- Order of else-if is critical
-- CR579191 modified method to prevent double fsync assertions
REG_PIPE_EMPTY : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
fifo_pipe_empty <= '1';
-- Command/Status not idle indicates pending datamover commands
-- set psuedo fifo empty to NOT empty.
elsif(cmdsts_idle_fe = '1')then
fifo_pipe_empty <= '0';
-- On accepted tlast then clear psuedo empty flag back to being empty
elsif(pot_empty = '1' and cmdsts_idle = '1')then
fifo_pipe_empty <= '1';
end if;
end if;
end process REG_PIPE_EMPTY;
REG_IDLE_FE : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
cmdsts_idle_d1 <= '1';
else
cmdsts_idle_d1 <= cmdsts_idle;
end if;
end if;
end process REG_IDLE_FE;
-- CR579586 Use falling edge to set pfifo empty
cmdsts_idle_fe <= not cmdsts_idle and cmdsts_idle_d1;
-- CR579191
POTENTIAL_EMPTY_PROCESS : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_resetn = '0' or dm_halt = '1')then
pot_empty <= '1';
elsif(m_axis_tvalid_d1 = '1' and m_axis_tlast_d1 = '1' and m_axis_tready_d1 = '1')then
pot_empty <= '1';
elsif(m_axis_tvalid_d1 = '1' and m_axis_tlast_d1 = '0')then
pot_empty <= '0';
end if;
end if;
end process POTENTIAL_EMPTY_PROCESS;
end generate GEN_NO_LINEBUFFER;
--*****************************************************************************--
--** MM2S ASYNCH CLOCK SUPPORT **--
--*****************************************************************************--
-- Cross fifo pipe empty flag to secondary clock domain
GEN_FOR_ASYNC : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
begin
-- Pipe Empty and Shutdown reset CDC
---- SHUTDOWN_RST_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => fifo_pipe_empty ,
---- scndry_out => mm2s_fifo_pipe_empty_i ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
SHUTDOWN_RST_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => fifo_pipe_empty,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => mm2s_fifo_pipe_empty_i,
scndry_vect_out => open
);
-- Vertical Count and All Lines Transferred CDC (CR616211)
---- ALL_LINES_XFRED_P_S_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_P_S ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' , -- CR619293
---- prmry_out => open , -- CR619293
---- prmry_in => all_lines_xfred ,
---- scndry_out => mm2s_all_lines_xfred ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
ALL_LINES_XFRED_P_S_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => all_lines_xfred,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => mm2s_all_lines_xfred,
scndry_vect_out => open
);
-- Vertical Count and All Lines Transferred CDC (CR616211)
---- ALL_LINES_XFRED_S_P_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => dm_xfred_all_lines , -- CR619293
---- prmry_out => dm_xfred_all_lines_reg , -- CR619293
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
ALL_LINES_XFRED_S_P_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => dm_xfred_all_lines,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => dm_xfred_all_lines_reg,
scndry_vect_out => open
);
VSIZE_CNT_CROSSING : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
crnt_vsize_cdc_tig <= crnt_vsize;
crnt_vsize_d1 <= crnt_vsize_cdc_tig;
end if;
end process VSIZE_CNT_CROSSING;
crnt_vsize_d2 <= crnt_vsize_d1;
-- Cross stop signal (CR623291)
---- STOP_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => stop ,
---- prmry_out => stop_reg ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
STOP_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => stop,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => stop_reg,
scndry_vect_out => open
);
---- MM2S_RUN_STOP_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => run_stop ,
---- prmry_out => run_stop_reg ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
MM2S_RUN_STOP_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => run_stop,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => run_stop_reg,
scndry_vect_out => open
);
---- MM2S_FSIZE_ERR_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' ,
---- prmry_out => open ,
---- prmry_in => fsize_mismatch_err_int_s ,
---- scndry_out => fsize_mismatch_err_int_m ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- scndry_vect_out => open
---- );
----
MM2S_FSIZE_ERR_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => fsize_mismatch_err_int_s,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => fsize_mismatch_err_int_m,
scndry_vect_out => open
);
---- MM2S_FSYNC_OUT_CDC_I_FLUSH_SOF : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => '0' , -- Not Used
---- prmry_out => open , -- Not Used
---- prmry_in => fsync_out ,
---- scndry_out => fsync_out_m ,
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => '0' , -- Not Used
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- scndry_vect_out => open -- Not Used
---- );
----
MM2S_FSYNC_OUT_CDC_I_FLUSH_SOF : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => m_axis_aclk,
prmry_resetn => m_axis_resetn,
prmry_in => fsync_out,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => s_axis_aclk,
scndry_resetn => s_axis_resetn,
scndry_out => fsync_out_m,
scndry_vect_out => open
);
GEN_FSYNC_SEL_CROSSING : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
fsync_src_select_cdc_tig <= fsync_src_select;
fsync_src_select_d1 <= fsync_src_select_cdc_tig;
end if;
end process GEN_FSYNC_SEL_CROSSING;
fsync_src_select_s_int <= fsync_src_select_d1;
-- Cross datamover halt and threshold signals
---- HALT_CDC_I : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_LEVEL_S_P ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => m_axis_aclk ,
---- prmry_resetn => m_axis_resetn ,
---- scndry_aclk => s_axis_aclk ,
---- scndry_resetn => s_axis_resetn ,
---- scndry_in => dm_halt ,
---- prmry_out => dm_halt_reg ,
---- prmry_in => '0' ,
---- scndry_out => open ,
---- scndry_vect_s_h => '0' ,
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) ,
---- prmry_vect_out => open ,
---- prmry_vect_s_h => '0' ,
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0),
---- scndry_vect_out => open
---- );
----
HALT_CDC_I : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_aclk,
prmry_resetn => s_axis_resetn,
prmry_in => dm_halt,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => dm_halt_reg,
scndry_vect_out => open
);
THRESH_CNT_CROSSING : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
data_count_ae_threshold_cdc_tig <= data_count_ae_threshold;
data_count_ae_threshold_d1 <= data_count_ae_threshold_cdc_tig;
end if;
end process THRESH_CNT_CROSSING;
m_data_count_ae_thresh <= data_count_ae_threshold_d1;
GEN_ASYNC_CROSS_FSYNC : if C_INCLUDE_S2MM = 1 generate
begin
---- CROSS_FSYNC_CDC_I_FLUSH_MM2S_SOF : entity axi_vdma_v6_2_8.axi_vdma_cdc
---- generic map(
---- C_CDC_TYPE => CDC_TYPE_PULSE_P_S_OPEN_ENDED ,
---- C_VECTOR_WIDTH => 1
---- )
---- port map (
---- prmry_aclk => s_axis_s2mm_aclk ,
---- prmry_resetn => s2mm_axis_resetn ,
---- scndry_aclk => m_axis_aclk ,
---- scndry_resetn => m_axis_resetn ,
---- scndry_in => '0' , -- Not Used
---- prmry_out => open , -- Not Used
---- prmry_in => s2mm_fsync ,
---- scndry_out => s2mm_fsync_mm2s_s ,
---- scndry_vect_s_h => '0' , -- Not Used
---- scndry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- prmry_vect_out => open , -- Not Used
---- prmry_vect_s_h => '0' , -- Not Used
---- prmry_vect_in => ZERO_VALUE_VECT(0 downto 0) , -- Not Used
---- scndry_vect_out => open -- Not Used
---- );
----
CROSS_FSYNC_CDC_I_FLUSH_MM2S_SOF : entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 0,
C_FLOP_INPUT => 1, --valid only for level CDC
C_RESET_STATE => 1,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => s_axis_s2mm_aclk,
prmry_resetn => s2mm_axis_resetn,
prmry_in => s2mm_fsync,
prmry_vect_in => (others => '0'),
prmry_ack => open,
scndry_aclk => m_axis_aclk,
scndry_resetn => m_axis_resetn,
scndry_out => s2mm_fsync_mm2s_s,
scndry_vect_out => open
);
end generate GEN_ASYNC_CROSS_FSYNC;
GEN_ASYNC_NO_CROSS_FSYNC : if C_INCLUDE_S2MM = 0 generate
begin
s2mm_fsync_mm2s_s <= '0';
end generate GEN_ASYNC_NO_CROSS_FSYNC;
end generate GEN_FOR_ASYNC;
--*****************************************************************************--
--** MM2S SYNCH CLOCK SUPPORT **--
--*****************************************************************************--
GEN_FOR_SYNC : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
begin
mm2s_fifo_pipe_empty_i <= fifo_pipe_empty;
crnt_vsize_d2 <= crnt_vsize; -- CR616211
mm2s_all_lines_xfred <= all_lines_xfred; -- CR616211
dm_xfred_all_lines_reg <= dm_xfred_all_lines; -- CR619293
stop_reg <= stop; -- CR623291
run_stop_reg <= run_stop; -- CR623291
fsync_out_m <= fsync_out; -- CR623291
dm_halt_reg <= dm_halt;
m_data_count_ae_thresh <= data_count_ae_threshold;
fsync_src_select_s_int <= fsync_src_select;
fsize_mismatch_err_int_m <= fsize_mismatch_err_int_s;
GEN_SYNC_CROSS_FSYNC : if C_INCLUDE_S2MM = 1 generate
begin
s2mm_fsync_mm2s_s <= s2mm_fsync;
end generate GEN_SYNC_CROSS_FSYNC;
GEN_SYNC_NO_CROSS_FSYNC : if C_INCLUDE_S2MM = 0 generate
begin
s2mm_fsync_mm2s_s <= '0';
end generate GEN_SYNC_NO_CROSS_FSYNC;
end generate GEN_FOR_SYNC;
NO_DWIDTH_VERT_COUNTER : if (C_DATA_WIDTH = C_M_AXIS_MM2S_TDATA_WIDTH) generate
begin
--*****************************************************************************
--** Vertical Line Tracking (CR616211)
--*****************************************************************************
-- Decrement vertical count with each accept tlast
decr_vcount <= '1' when m_axis_tlast_d1 = '1'
and m_axis_tvalid_d1 = '1'
and m_axis_tready_d1 = '1'
else '0';
-- Drive ready at fsync out then de-assert once all lines have
-- been accepted.
VERT_COUNTER : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if((m_axis_fifo_ainit = '1' and fsync_out = '0') or fsize_mismatch_err_flag_vsize_cntr_clr = '1' )then
vsize_counter <= (others => '0');
all_lines_xfred_no_dwidth <= '1';
elsif(fsync_out = '1')then
vsize_counter <= crnt_vsize_d2;
all_lines_xfred_no_dwidth <= '0';
elsif(decr_vcount = '1' and vsize_counter = VSIZE_ONE_VALUE)then
vsize_counter <= (others => '0');
all_lines_xfred_no_dwidth <= '1';
elsif(decr_vcount = '1' and vsize_counter /= VSIZE_ZERO_VALUE)then
vsize_counter <= std_logic_vector(unsigned(vsize_counter) - 1);
all_lines_xfred_no_dwidth <= '0';
end if;
end if;
end process VERT_COUNTER;
end generate NO_DWIDTH_VERT_COUNTER;
-- Store and forward or no line buffer (CR619293)
GEN_VCOUNT_FOR_SNF : if C_LINEBUFFER_DEPTH /= 0 and C_INCLUDE_MM2S_SF = 1 generate
begin
dm_decr_vcount <= '1' when s_axis_tlast = '1'
and s_axis_tvalid = '1'
and s_axis_tready_i = '1'
else '0';
-- Delay 1 pipe to align with cnrt_vsize
REG_FSYNC_TO_ALIGN : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit = '1' and frame_sync = '0')then
frame_sync_d1 <= '0';
else
frame_sync_d1 <= frame_sync;
end if;
end if;
end process REG_FSYNC_TO_ALIGN;
-- Count lines to determine when datamover done. Used for snf mode
-- for threshold met (CR619293)
DM_DONE : process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
if(s_axis_fifo_ainit = '1')then
dm_vsize_counter <= (others => '0');
dm_xfred_all_lines <= '0';
--elsif(fsync_out = '1')then -- CR623088
elsif(frame_sync_d1 = '1')then -- CR623088
dm_vsize_counter <= crnt_vsize;
dm_xfred_all_lines <= '0';
elsif(dm_decr_vcount = '1' and dm_vsize_counter = VSIZE_ONE_VALUE)then
dm_vsize_counter <= (others => '0');
dm_xfred_all_lines <= '1';
elsif(dm_decr_vcount = '1' and dm_vsize_counter /= VSIZE_ZERO_VALUE)then
dm_vsize_counter <= std_logic_vector(unsigned(dm_vsize_counter) - 1);
dm_xfred_all_lines <= '0';
end if;
end if;
end process DM_DONE;
end generate GEN_VCOUNT_FOR_SNF;
-- Not store and forward or no line buffer (CR619293)
GEN_NO_VCOUNT_FOR_SNF : if C_LINEBUFFER_DEPTH = 0 or C_INCLUDE_MM2S_SF = 0 generate
begin
dm_vsize_counter <= (others => '0');
dm_xfred_all_lines <= '0';
dm_decr_vcount <= '0';
end generate GEN_NO_VCOUNT_FOR_SNF;
--*****************************************************************************--
--** SPECIAL RESET GENERATION **--
--*****************************************************************************--
-- Assert reset to skid buffer on hard reset or on shutdown when fifo pipe empty
-- Waiting for fifo_pipe_empty is required to prevent a AXIS protocol violation
-- when channel shut down early
REG_SKID_RESET : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_resetn = '0')then
m_skid_reset <= '1';
elsif(fifo_pipe_empty = '1')then
if(fsync_out = '1' or dm_halt_reg = '1')then
m_skid_reset <= '1';
else
m_skid_reset <= '0';
end if;
else
m_skid_reset <= '0';
end if;
end if;
end process REG_SKID_RESET;
-- Fifo/logic reset for slave side clock domain (m_axi_mm2s_aclk)
-- If error (dm_halt=1) then halt immediatly without protocol violation
s_axis_fifo_ainit <= '1' when s_axis_resetn = '0'
or frame_sync = '1' -- Frame sync
or dm_halt = '1' -- Datamover being halted (halt due to error)
else '0';
-- Fifo/logic reset for master side clock domain (m_axis_mm2s_aclk)
m_axis_fifo_ainit <= '1' when m_axis_resetn = '0'
or fsync_out = '1' -- Frame sync
or dm_halt_reg = '1' -- Datamover being halted
else '0';
-- Fifo/logic reset for slave side clock domain (m_axi_mm2s_aclk)
-- If error (dm_halt=1) then halt immediatly without protocol violation
s_axis_fifo_ainit_nosync <= '1' when s_axis_resetn = '0'
or dm_halt = '1' -- Datamover being halted (halt due to error)
else '0';
process(s_axis_aclk)
begin
if(s_axis_aclk'EVENT and s_axis_aclk = '1')then
s_axis_fifo_ainit_nosync_reg <= s_axis_fifo_ainit_nosync;
end if;
end process ;
-- Fifo/logic reset for master side clock domain (m_axis_mm2s_aclk)
m_axis_fifo_ainit_nosync <= '1' when m_axis_resetn = '0'
or dm_halt_reg = '1' -- Datamover being halted
else '0';
--reset for axis_dwidth
mm2s_axis_linebuf_reset_out_inv <= m_axis_fifo_ainit_nosync;
mm2s_axis_linebuf_reset_out <= not (mm2s_axis_linebuf_reset_out_inv);
all_lines_xfred <= mm2s_all_lines_xfred_s_sig;
mm2s_all_lines_xfred_s <= mm2s_all_lines_xfred_s_sig;
--C_DATA_WIDTH = C_M_AXIS_MM2S_TDATA_WIDTH_CALCULATED
MM2S_DWIDTH_CONV_IS : if (C_DATA_WIDTH /= C_M_AXIS_MM2S_TDATA_WIDTH) generate
begin
mm2s_all_lines_xfred_s_sig <= mm2s_all_lines_xfred_s_dwidth;
fifo_pipe_empty <= dwidth_fifo_pipe_empty;
dwidth_fifo_pipe_empty_m <= mm2s_fifo_pipe_empty_i;
end generate MM2S_DWIDTH_CONV_IS;
MM2S_DWIDTH_CONV_IS_NOT : if (C_DATA_WIDTH = C_M_AXIS_MM2S_TDATA_WIDTH) generate
begin
mm2s_all_lines_xfred_s_sig <= all_lines_xfred_no_dwidth;
fifo_pipe_empty <= '1' when (all_lines_xfred = '1' and m_axis_tvalid_out = '0') -- All data for frame transmitted
or (sf_threshold_met = '0' -- Or Threshold not met
and stop_reg = '1' -- Commanded to stop
and m_axis_tvalid_out = '0') -- And NOT driving tvalid
else '0';
dwidth_fifo_pipe_empty_m <= '1';
end generate MM2S_DWIDTH_CONV_IS_NOT;
mm2s_fsync_int <= mm2s_fsync and run_stop_reg;
-- Frame sync cross bar
---- FSYNC_CROSSBAR_MM2S_S : process(fsync_src_select_s_int,
---- run_stop_reg,
---- mm2s_fsync,
---- s2mm_fsync_mm2s_s)
---- begin
---- case fsync_src_select_s_int is
----
---- when "00" => -- primary fsync (default)
---- mm2s_fsync_int <= mm2s_fsync and run_stop_reg;
---- when "01" => -- other channel fsync
---- mm2s_fsync_int <= s2mm_fsync_mm2s_s and run_stop_reg;
---- when others =>
---- mm2s_fsync_int <= '0';
---- end case;
---- end process FSYNC_CROSSBAR_MM2S_S;
FSIZE_MISMATCH_MM2S_FLUSH_SOF_s : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk='1')then
if(m_axis_resetn = '0')then
fsize_mismatch_err_int_s <= '0';
-- fsync occurred when not all lines transferred
elsif(mm2s_fsync_int = '1' and mm2s_all_lines_xfred_s_sig = '0')then
fsize_mismatch_err_int_s <= '1';
else
fsize_mismatch_err_int_s <= '0';
end if;
end if;
end process FSIZE_MISMATCH_MM2S_FLUSH_SOF_s;
FSIZE_MISMATCH_FLAG_MM2S_FLUSH_SOF_s : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk='1')then
if(m_axis_resetn = '0' or mm2s_fsync_int = '1')then
fsize_mismatch_err_flag_s <= '0';
elsif(fsize_mismatch_err_int_s = '1')then
fsize_mismatch_err_flag_s <= '1';
end if;
end if;
end process FSIZE_MISMATCH_FLAG_MM2S_FLUSH_SOF_s;
fsize_mismatch_err_flag_cmb_s <= fsize_mismatch_err_int_s or fsize_mismatch_err_flag_s;
MM2S_DROP_RESIDUAL_OF_FSIZE_ERR_FRAME_S <= fsize_mismatch_err_flag_cmb_s;
mm2s_fsize_mismatch_err_s <= fsize_mismatch_err_int_s;
mm2s_fsize_mismatch_err_m <= fsize_mismatch_err_int_m;
mm2s_vsize_cntr_clr_flag <= fsize_mismatch_err_flag_vsize_cntr_clr or fsize_mismatch_err_int_s;
D1_FSYNC_OUT : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk='1')then
if(m_axis_resetn = '0')then
fsync_out_d1 <= '0';
else
fsync_out_d1 <= fsync_out;
end if;
end if;
end process D1_FSYNC_OUT;
FLAG_VSIZE_CNTR_CLR : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk='1')then
if(m_axis_resetn = '0' or fsync_out_d1 = '1')then
fsize_mismatch_err_flag_vsize_cntr_clr <= '0';
elsif(fsize_mismatch_err_int_s = '1')then
fsize_mismatch_err_flag_vsize_cntr_clr <= '1';
end if;
end if;
end process FLAG_VSIZE_CNTR_CLR;
MM2S_FSIZE_ERR_TO_DM_HALT_FLAG : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_resetn = '0' or dm_halt_reg = '1')then
fsize_err_to_dm_halt_flag <= '0';
elsif(fsize_mismatch_err_int_s = '1')then
fsize_err_to_dm_halt_flag <= '1';
end if;
end if;
end process MM2S_FSIZE_ERR_TO_DM_HALT_FLAG;
fsize_err_to_dm_halt_flag_ored <= fsize_mismatch_err_int_s or fsize_err_to_dm_halt_flag or dm_halt_reg;
delay_fsync_fsize_err_till_dm_halt_cmplt_pulse_s <= '1' when fsize_err_to_dm_halt_flag_ored = '1' and mm2s_fsync_int = '1'
else '0';
MM2S_FSIZE_LESS_DM_HALT_CMPLT_FLAG : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_resetn = '0' or fsize_err_to_dm_halt_flag_ored = '0')then
delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s <= '0';
elsif(delay_fsync_fsize_err_till_dm_halt_cmplt_pulse_s = '1')then
delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s <= '1';
end if;
end if;
end process MM2S_FSIZE_LESS_DM_HALT_CMPLT_FLAG;
MM2S_REG_D_FSYNC : process(m_axis_aclk)
begin
if(m_axis_aclk'EVENT and m_axis_aclk = '1')then
if(m_axis_resetn = '0')then
delay_fsync_fsize_err_till_dm_halt_cmplt_s_d1 <= '0';
else
delay_fsync_fsize_err_till_dm_halt_cmplt_s_d1 <= delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s;
end if;
end if;
end process MM2S_REG_D_FSYNC;
d_fsync_halt_cmplt_s <= delay_fsync_fsize_err_till_dm_halt_cmplt_s_d1 and not delay_fsync_fsize_err_till_dm_halt_cmplt_flag_s;
mm2s_fsync_core <= (mm2s_fsync_int and not (delay_fsync_fsize_err_till_dm_halt_cmplt_pulse_s)) or d_fsync_halt_cmplt_s;
--mm2s_fsync_core <= mm2s_fsync_int;
end generate GEN_LINEBUF_FLUSH_SOF;
end implementation;
|
-- file: vga_clk_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard demonstration testbench
------------------------------------------------------------------------------
-- This demonstration testbench instantiates the example design for the
-- clocking wizard. Input clocks are toggled, which cause the clocking
-- network to lock and the counters to increment.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
use work.all;
entity vga_clk_tb is
end vga_clk_tb;
architecture test of vga_clk_tb is
-- Clock to Q delay of 100 ps
constant TCQ : time := 100 ps;
-- timescale is 1ps
constant ONE_NS : time := 1 ns;
-- how many cycles to run
constant COUNT_PHASE : integer := 1024 + 1;
-- we'll be using the period in many locations
constant PER1 : time := 31.25 ns;
-- Declare the input clock signals
signal CLK_IN1 : std_logic := '1';
-- The high bit of the sampling counter
signal COUNT : std_logic;
signal COUNTER_RESET : std_logic := '0';
signal timeout_counter : std_logic_vector (13 downto 0) := (others => '0');
-- signal defined to stop mti simulation without severity failure in the report
signal end_of_sim : std_logic := '0';
signal CLK_OUT : std_logic_vector(1 downto 1);
--Freq Check using the M & D values setting and actual Frequency generated
component vga_clk_exdes
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(1 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic
);
end component;
begin
-- Input clock generation
--------------------------------------
process begin
CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
end process;
-- Test sequence
process
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
procedure simfreqprint (period : time; clk_num : integer) is
variable outputline : LINE;
variable str1 : string(1 to 16);
variable str2 : integer;
variable str3 : string(1 to 2);
variable str4 : integer;
variable str5 : string(1 to 4);
begin
str1 := "Freq of CLK_OUT(";
str2 := clk_num;
str3 := ") ";
str4 := 1000000 ps/period ;
str5 := " MHz" ;
write(outputline, str1 );
write(outputline, str2);
write(outputline, str3);
write(outputline, str4);
write(outputline, str5);
writeline(output, outputline);
end simfreqprint;
begin
report "Timing checks are not valid" severity note;
-- can't probe into hierarchy, wait "some time" for lock
wait for (PER1*2500);
wait for (PER1*20);
COUNTER_RESET <= '1';
wait for (PER1*19.5);
COUNTER_RESET <= '0';
wait for (PER1*1);
report "Timing checks are valid" severity note;
wait for (PER1*COUNT_PHASE);
simtimeprint;
end_of_sim <= '1';
wait for 1 ps;
report "Simulation Stopped." severity failure;
wait;
end process;
-- Instantiation of the example design containing the clock
-- network and sampling counters
-----------------------------------------------------------
dut : vga_clk_exdes
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Reset for logic in example design
COUNTER_RESET => COUNTER_RESET,
CLK_OUT => CLK_OUT,
-- High bits of the counters
COUNT => COUNT);
-- Freq Check
end test;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for ent_t
--
-- Generated
-- by: wig
-- on: Mon Jul 18 16:07:27 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -sheet HIER=HIER_MIXED -strip -nodelta ../../verilog.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_t-e.vhd,v 1.4 2005/07/19 07:13:20 wig Exp $
-- $Date: 2005/07/19 07:13:20 $
-- $Log: ent_t-e.vhd,v $
-- Revision 1.4 2005/07/19 07:13:20 wig
-- Update testcases. Added highlow/nolowbus
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity ent_t
--
entity ent_t is
-- Generics:
-- No Generated Generics for Entity ent_t
-- Generated Port Declaration:
port(
-- Generated Port for Entity ent_t
sig_i_a : in std_ulogic;
sig_i_a2 : in std_ulogic;
sig_i_ae : in std_ulogic_vector(6 downto 0);
sig_o_a : out std_ulogic;
sig_o_a2 : out std_ulogic;
sig_o_ae : out std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity ent_t
);
end ent_t;
--
-- End of Generated Entity ent_t
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity tb_analog_switch is
end tb_analog_switch;
architecture TB_analog_switch of tb_analog_switch is
-- Component declarations
-- Signal declarations
terminal in_ana_src : electrical;
terminal in_switch : electrical;
signal clock_out : std_logic;
begin
-- Signal assignments
-- Component instances
vdc1 : entity work.v_constant(ideal)
generic map(
level => 1.0
)
port map(
pos => in_ana_src,
neg => ELECTRICAL_REF
);
Clk1 : entity work.clock(ideal)
generic map(
period => 10.0ms
)
port map(
clk_out => clock_out
);
R1 : entity work.resistor(ideal)
generic map(
res => 100.0
)
port map(
p1 => in_ana_src,
p2 => in_switch
);
swtch : entity work.analog_switch(ideal)
port map(
n1 => in_switch,
n2 => ELECTRICAL_REF,
control => clock_out
);
end TB_analog_switch;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity tb_analog_switch is
end tb_analog_switch;
architecture TB_analog_switch of tb_analog_switch is
-- Component declarations
-- Signal declarations
terminal in_ana_src : electrical;
terminal in_switch : electrical;
signal clock_out : std_logic;
begin
-- Signal assignments
-- Component instances
vdc1 : entity work.v_constant(ideal)
generic map(
level => 1.0
)
port map(
pos => in_ana_src,
neg => ELECTRICAL_REF
);
Clk1 : entity work.clock(ideal)
generic map(
period => 10.0ms
)
port map(
clk_out => clock_out
);
R1 : entity work.resistor(ideal)
generic map(
res => 100.0
)
port map(
p1 => in_ana_src,
p2 => in_switch
);
swtch : entity work.analog_switch(ideal)
port map(
n1 => in_switch,
n2 => ELECTRICAL_REF,
control => clock_out
);
end TB_analog_switch;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE;
use IEEE.std_logic_1164.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
entity tb_analog_switch is
end tb_analog_switch;
architecture TB_analog_switch of tb_analog_switch is
-- Component declarations
-- Signal declarations
terminal in_ana_src : electrical;
terminal in_switch : electrical;
signal clock_out : std_logic;
begin
-- Signal assignments
-- Component instances
vdc1 : entity work.v_constant(ideal)
generic map(
level => 1.0
)
port map(
pos => in_ana_src,
neg => ELECTRICAL_REF
);
Clk1 : entity work.clock(ideal)
generic map(
period => 10.0ms
)
port map(
clk_out => clock_out
);
R1 : entity work.resistor(ideal)
generic map(
res => 100.0
)
port map(
p1 => in_ana_src,
p2 => in_switch
);
swtch : entity work.analog_switch(ideal)
port map(
n1 => in_switch,
n2 => ELECTRICAL_REF,
control => clock_out
);
end TB_analog_switch;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Tue May 09 14:50:53 2017
-- Host : DESKTOP-7MUQLTN running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/Users/Kiwi/Desktop/Projet_VHDL_-_Paint/04_IP_Xillinx/Clk_Wizard/Clk_Wizard_stub.vhdl
-- Design : Clk_Wizard
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a100tcsg324-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Clk_Wizard is
Port (
VGA_clock : out STD_LOGIC;
Main_clock : out STD_LOGIC;
resetn : in STD_LOGIC;
locked : out STD_LOGIC;
Clock_Board : in STD_LOGIC
);
end Clk_Wizard;
architecture stub of Clk_Wizard is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "VGA_clock,Main_clock,resetn,locked,Clock_Board";
begin
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc69.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x02p07n05i00069ent IS
END c04s03b01x02p07n05i00069ent;
ARCHITECTURE c04s03b01x02p07n05i00069arch OF c04s03b01x02p07n05i00069ent IS
signal S1 : BIT_VECTOR(0 to 3) := ("0101" and "0101");
BEGIN
TESTING: PROCESS
BEGIN
wait for 10 ns;
assert NOT( S1(0) = '0' and
S1(1) = '1' and
S1(2) = '0' and
S1(3) = '1' )
report "***PASSED TEST: c04s03b01x02p07n05i00069"
severity NOTE;
assert ( S1(0) = '0' and
S1(1) = '1' and
S1(2) = '0' and
S1(3) = '1' )
report "***FAILED TEST: c04s03b01x02p07n05i00069 - Each subelement of the value of the composite subtype is the default value of the corresponding subelement of the signal."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b01x02p07n05i00069arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc69.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x02p07n05i00069ent IS
END c04s03b01x02p07n05i00069ent;
ARCHITECTURE c04s03b01x02p07n05i00069arch OF c04s03b01x02p07n05i00069ent IS
signal S1 : BIT_VECTOR(0 to 3) := ("0101" and "0101");
BEGIN
TESTING: PROCESS
BEGIN
wait for 10 ns;
assert NOT( S1(0) = '0' and
S1(1) = '1' and
S1(2) = '0' and
S1(3) = '1' )
report "***PASSED TEST: c04s03b01x02p07n05i00069"
severity NOTE;
assert ( S1(0) = '0' and
S1(1) = '1' and
S1(2) = '0' and
S1(3) = '1' )
report "***FAILED TEST: c04s03b01x02p07n05i00069 - Each subelement of the value of the composite subtype is the default value of the corresponding subelement of the signal."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b01x02p07n05i00069arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc69.vhd,v 1.2 2001-10-26 16:29:59 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x02p07n05i00069ent IS
END c04s03b01x02p07n05i00069ent;
ARCHITECTURE c04s03b01x02p07n05i00069arch OF c04s03b01x02p07n05i00069ent IS
signal S1 : BIT_VECTOR(0 to 3) := ("0101" and "0101");
BEGIN
TESTING: PROCESS
BEGIN
wait for 10 ns;
assert NOT( S1(0) = '0' and
S1(1) = '1' and
S1(2) = '0' and
S1(3) = '1' )
report "***PASSED TEST: c04s03b01x02p07n05i00069"
severity NOTE;
assert ( S1(0) = '0' and
S1(1) = '1' and
S1(2) = '0' and
S1(3) = '1' )
report "***FAILED TEST: c04s03b01x02p07n05i00069 - Each subelement of the value of the composite subtype is the default value of the corresponding subelement of the signal."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b01x02p07n05i00069arch;
|
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|
`protect begin_protected
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12384)
`protect data_block
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`protect end_protected
|
-------------------------------------------------------------------------------
-- $Id: reset_mir.vhd,v 1.1.2.1 2009/10/06 21:15:02 gburch Exp $
-------------------------------------------------------------------------------
--reset_mir.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: reset_mir.vhd
--
-- Description: SW reset / MIR register.
--
-------------------------------------------------------------------------------
-- Structure:
-- reset_mir.vhd
--
-------------------------------------------------------------------------------
-- Author: F.Ostler
--
-- History:
-- FLO Aug 16, 2001
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
---------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.std_logic_arith.conv_std_logic_vector;
----------------------------------------------------------------------
entity reset_mir is
Generic (
C_DWIDTH : integer := 32;
C_INCLUDE_SW_RST : integer := 1;
C_INCLUDE_MIR : integer := 1;
C_MIR_MAJOR_VERSION : integer := 0;
C_MIR_MINOR_VERSION : integer := 0;
C_MIR_REVISION : integer := 1;
C_MIR_BLK_ID : integer := 1;
C_MIR_TYPE : integer := 1
);
port (
Reset : in std_logic;
Bus2IP_Clk : in std_logic;
SW_Reset_WrCE : in std_logic;
SW_Reset_RdCE : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1);
Bus2IP_Reset : out std_logic;
Reset2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1);
Reset2Bus_Ack : out std_logic;
Reset2Bus_Error : out std_logic;
Reset2Bus_Retry : out std_logic;
Reset2Bus_ToutSup : out std_logic
);
end reset_mir;
architecture implementation of reset_mir is
--------------------------------------------------------------------------------
-- Value of data LSBs required for a reset-register write to be valid.
--------------------------------------------------------------------------------
constant RESET_MATCH : std_logic_vector(0 to 3) := "1010";
signal sw_reset : std_logic;
signal sw_rst_cond : std_logic;
signal sw_rst_cond_d1 : std_logic;
signal data_is_non_reset_match : std_logic;
begin
----------------------------------------------------------------------------
-- Response signal generation
----------------------------------------------------------------------------
Reset2Bus_Ack <= '1' -- Always acknowledge immediately
when C_INCLUDE_SW_RST = 1 or C_INCLUDE_MIR = 1
else '0';
Reset2Bus_Error <= SW_Reset_WrCE and data_is_non_reset_match
when C_INCLUDE_SW_RST = 1
else '0';
Reset2Bus_Retry <= '0';
Reset2Bus_ToutSup <= '0';
data_is_non_reset_match <=
'0' when Bus2IP_Data(C_DWIDTH-4 to C_DWIDTH-1) = RESET_MATCH
else '1';
--------------------------------------------------------------------------------
-- SW Reset
--------------------------------------------------------------------------------
INCLUDE_SW_RESET_GEN : if C_INCLUDE_SW_RST = 1 generate
----------------------------------------------------------------------------
-- ToDo, sw_reset could be implemented by instantiating a LUT, muxcy,
-- orcy and two FFs.
----------------------------------------------------------------------------
sw_rst_cond <= SW_Reset_WrCE and not data_is_non_reset_match;
--
RST_PULSE_PROC : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
if (Reset = '1') Then
sw_rst_cond_d1 <= '0';
sw_reset <= '0';
else
sw_rst_cond_d1 <= sw_rst_cond;
sw_reset <= sw_rst_cond or sw_rst_cond_d1;
end if;
end if;
End process;
--
Bus2IP_Reset <= Reset or sw_reset;
end generate;
--
--
EXCLUDE_SW_RESET : if C_INCLUDE_SW_RST = 0 generate
Bus2IP_Reset <= Reset;
end generate;
--------------------------------------------------------------------------------
-- MIR
--------------------------------------------------------------------------------
EXCLUDE_MIR_GEN : if C_INCLUDE_MIR = 0 generate
Reset2Bus_Data <= (others => '0');
end generate;
--
--
INCLUDE_MIR_GEN : if C_INCLUDE_MIR = 1 generate
signal mir_value : std_logic_vector(0 to 31);
begin
----------------------------------------------------------------------
-- assemble the MIR fields from the Applicable Generics
----------------------------------------------------------------------
mir_value(0 to 3) <= CONV_STD_LOGIC_VECTOR(C_MIR_MAJOR_VERSION, 4);
mir_value(4 to 10) <= CONV_STD_LOGIC_VECTOR(C_MIR_MINOR_VERSION, 7);
mir_value(11 to 15) <= CONV_STD_LOGIC_VECTOR(C_MIR_REVISION, 5);
mir_value(16 to 23) <= CONV_STD_LOGIC_VECTOR(C_MIR_BLK_ID, 8);
mir_value(24 to 31) <= CONV_STD_LOGIC_VECTOR(C_MIR_TYPE, 8);
READ_MUX : process(SW_Reset_RdCE,mir_value)
begin
if(SW_Reset_RdCE = '1')then
Reset2Bus_Data <= mir_value;
else
Reset2Bus_Data <= (others => '0');
end if;
end process READ_MUX;
end generate;
end implementation;
|
-------------------------------------------------------------------------------
-- $Id: reset_mir.vhd,v 1.1.2.1 2009/10/06 21:15:02 gburch Exp $
-------------------------------------------------------------------------------
--reset_mir.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: reset_mir.vhd
--
-- Description: SW reset / MIR register.
--
-------------------------------------------------------------------------------
-- Structure:
-- reset_mir.vhd
--
-------------------------------------------------------------------------------
-- Author: F.Ostler
--
-- History:
-- FLO Aug 16, 2001
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
---------------------------------------------------------------------
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.std_logic_arith.conv_std_logic_vector;
----------------------------------------------------------------------
entity reset_mir is
Generic (
C_DWIDTH : integer := 32;
C_INCLUDE_SW_RST : integer := 1;
C_INCLUDE_MIR : integer := 1;
C_MIR_MAJOR_VERSION : integer := 0;
C_MIR_MINOR_VERSION : integer := 0;
C_MIR_REVISION : integer := 1;
C_MIR_BLK_ID : integer := 1;
C_MIR_TYPE : integer := 1
);
port (
Reset : in std_logic;
Bus2IP_Clk : in std_logic;
SW_Reset_WrCE : in std_logic;
SW_Reset_RdCE : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_DWIDTH-1);
Bus2IP_Reset : out std_logic;
Reset2Bus_Data : out std_logic_vector(0 to C_DWIDTH-1);
Reset2Bus_Ack : out std_logic;
Reset2Bus_Error : out std_logic;
Reset2Bus_Retry : out std_logic;
Reset2Bus_ToutSup : out std_logic
);
end reset_mir;
architecture implementation of reset_mir is
--------------------------------------------------------------------------------
-- Value of data LSBs required for a reset-register write to be valid.
--------------------------------------------------------------------------------
constant RESET_MATCH : std_logic_vector(0 to 3) := "1010";
signal sw_reset : std_logic;
signal sw_rst_cond : std_logic;
signal sw_rst_cond_d1 : std_logic;
signal data_is_non_reset_match : std_logic;
begin
----------------------------------------------------------------------------
-- Response signal generation
----------------------------------------------------------------------------
Reset2Bus_Ack <= '1' -- Always acknowledge immediately
when C_INCLUDE_SW_RST = 1 or C_INCLUDE_MIR = 1
else '0';
Reset2Bus_Error <= SW_Reset_WrCE and data_is_non_reset_match
when C_INCLUDE_SW_RST = 1
else '0';
Reset2Bus_Retry <= '0';
Reset2Bus_ToutSup <= '0';
data_is_non_reset_match <=
'0' when Bus2IP_Data(C_DWIDTH-4 to C_DWIDTH-1) = RESET_MATCH
else '1';
--------------------------------------------------------------------------------
-- SW Reset
--------------------------------------------------------------------------------
INCLUDE_SW_RESET_GEN : if C_INCLUDE_SW_RST = 1 generate
----------------------------------------------------------------------------
-- ToDo, sw_reset could be implemented by instantiating a LUT, muxcy,
-- orcy and two FFs.
----------------------------------------------------------------------------
sw_rst_cond <= SW_Reset_WrCE and not data_is_non_reset_match;
--
RST_PULSE_PROC : process (Bus2IP_Clk)
Begin
if (Bus2IP_Clk'EVENT and Bus2IP_Clk = '1') Then
if (Reset = '1') Then
sw_rst_cond_d1 <= '0';
sw_reset <= '0';
else
sw_rst_cond_d1 <= sw_rst_cond;
sw_reset <= sw_rst_cond or sw_rst_cond_d1;
end if;
end if;
End process;
--
Bus2IP_Reset <= Reset or sw_reset;
end generate;
--
--
EXCLUDE_SW_RESET : if C_INCLUDE_SW_RST = 0 generate
Bus2IP_Reset <= Reset;
end generate;
--------------------------------------------------------------------------------
-- MIR
--------------------------------------------------------------------------------
EXCLUDE_MIR_GEN : if C_INCLUDE_MIR = 0 generate
Reset2Bus_Data <= (others => '0');
end generate;
--
--
INCLUDE_MIR_GEN : if C_INCLUDE_MIR = 1 generate
signal mir_value : std_logic_vector(0 to 31);
begin
----------------------------------------------------------------------
-- assemble the MIR fields from the Applicable Generics
----------------------------------------------------------------------
mir_value(0 to 3) <= CONV_STD_LOGIC_VECTOR(C_MIR_MAJOR_VERSION, 4);
mir_value(4 to 10) <= CONV_STD_LOGIC_VECTOR(C_MIR_MINOR_VERSION, 7);
mir_value(11 to 15) <= CONV_STD_LOGIC_VECTOR(C_MIR_REVISION, 5);
mir_value(16 to 23) <= CONV_STD_LOGIC_VECTOR(C_MIR_BLK_ID, 8);
mir_value(24 to 31) <= CONV_STD_LOGIC_VECTOR(C_MIR_TYPE, 8);
READ_MUX : process(SW_Reset_RdCE,mir_value)
begin
if(SW_Reset_RdCE = '1')then
Reset2Bus_Data <= mir_value;
else
Reset2Bus_Data <= (others => '0');
end if;
end process READ_MUX;
end generate;
end implementation;
|
-- $Id: pdp11_mmu_mmr12.vhd 1291 2022-09-03 07:00:27Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2022 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_mmu_mmr12 - syn
-- Description: pdp11: mmu register mmr1 and mmr2
--
-- Dependencies: ib_sel
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4-2022.1; ghdl 0.18-2.0.0
--
-- Revision History:
-- Date Rev Version Comment
-- 2022-08-30 1291 1.2.4 use ra_delta to steer mmr1 updates
-- 2022-08-13 1279 1.2.3 ssr->mmr rename
-- 2011-11-18 427 1.2.2 now numeric_std clean
-- 2010-10-23 335 1.2.1 use ib_sel
-- 2010-10-17 333 1.2 use ibus V2 interface
-- 2009-05-30 220 1.1.4 final removal of snoopers (were already commented)
-- 2008-08-22 161 1.1.3 rename ubf_ -> ibf_; use iblib
-- 2008-03-02 121 1.1.2 remove snoopers
-- 2008-01-05 110 1.1.1 rename IB_MREQ(ena->req) SRES(sel->ack, hold->busy)
-- 2007-12-30 107 1.1 use IB_MREQ/IB_SRES interface now
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_mmu_mmr12 is -- mmu register mmr1 and mmr2
port (
CLK : in slbit; -- clock
CRESET : in slbit; -- cpu reset
TRACE : in slbit; -- trace enable
MONI : in mmu_moni_type; -- MMU monitor port data
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end pdp11_mmu_mmr12;
architecture syn of pdp11_mmu_mmr12 is
constant ibaddr_mmr1 : slv16 := slv(to_unsigned(8#177574#,16));
constant ibaddr_mmr2 : slv16 := slv(to_unsigned(8#177576#,16));
subtype mmr1_ibf_rb_delta is integer range 15 downto 11;
subtype mmr1_ibf_rb_num is integer range 10 downto 8;
subtype mmr1_ibf_ra_delta is integer range 7 downto 3;
subtype mmr1_ibf_ra_num is integer range 2 downto 0;
signal IBSEL_MMR1 : slbit := '0';
signal IBSEL_MMR2 : slbit := '0';
signal R_MMR1 : mmu_mmr1_type := mmu_mmr1_init;
signal R_MMR2 : slv16 := (others=>'0');
signal N_MMR1 : mmu_mmr1_type := mmu_mmr1_init;
signal N_MMR2 : slv16 := (others=>'0');
begin
SEL_MMR1 : ib_sel
generic map (
IB_ADDR => ibaddr_mmr1)
port map (
CLK => CLK,
IB_MREQ => IB_MREQ,
SEL => IBSEL_MMR1
);
SEL_MMR2 : ib_sel
generic map (
IB_ADDR => ibaddr_mmr2)
port map (
CLK => CLK,
IB_MREQ => IB_MREQ,
SEL => IBSEL_MMR2
);
proc_ibres : process (IBSEL_MMR1, IBSEL_MMR2, IB_MREQ, R_MMR1, R_MMR2)
variable mmr1out : slv16 := (others=>'0');
variable mmr2out : slv16 := (others=>'0');
begin
mmr1out := (others=>'0');
if IBSEL_MMR1 = '1' then
mmr1out(mmr1_ibf_rb_delta) := R_MMR1.rb_delta;
mmr1out(mmr1_ibf_rb_num) := R_MMR1.rb_num;
mmr1out(mmr1_ibf_ra_delta) := R_MMR1.ra_delta;
mmr1out(mmr1_ibf_ra_num) := R_MMR1.ra_num;
end if;
mmr2out := (others=>'0');
if IBSEL_MMR2 = '1' then
mmr2out := R_MMR2;
end if;
IB_SRES.dout <= mmr1out or mmr2out;
IB_SRES.ack <= (IBSEL_MMR1 or IBSEL_MMR2) and
(IB_MREQ.re or IB_MREQ.we); -- ack all
IB_SRES.busy <= '0';
end process proc_ibres;
proc_regs : process (CLK)
begin
if rising_edge(CLK) then
R_MMR1 <= N_MMR1;
R_MMR2 <= N_MMR2;
end if;
end process proc_regs;
proc_comb : process (CRESET, IBSEL_MMR1, IB_MREQ,
R_MMR1, R_MMR2, TRACE, MONI)
variable nmmr1 : mmu_mmr1_type := mmu_mmr1_init;
variable nmmr2 : slv16 := (others=>'0');
variable delta : slv5 := (others=>'0');
begin
nmmr1 := R_MMR1;
nmmr2 := R_MMR2;
delta := "0" & MONI.delta;
if CRESET = '1' then
nmmr1 := mmu_mmr1_init;
nmmr2 := (others=>'0');
elsif IBSEL_MMR1='1' and IB_MREQ.we='1' then
if IB_MREQ.be1 = '1' then
nmmr1.rb_delta := IB_MREQ.din(mmr1_ibf_rb_delta);
nmmr1.rb_num := IB_MREQ.din(mmr1_ibf_rb_num);
end if;
if IB_MREQ.be0 = '1' then
nmmr1.ra_delta := IB_MREQ.din(mmr1_ibf_ra_delta);
nmmr1.ra_num := IB_MREQ.din(mmr1_ibf_ra_num);
end if;
elsif TRACE = '1' then
if MONI.istart = '1' then
nmmr1 := mmu_mmr1_init;
nmmr2 := MONI.pc;
elsif MONI.regmod = '1' then
if R_MMR1.ra_delta = "00000" then
nmmr1.ra_num := MONI.regnum;
if MONI.isdec = '0' then
nmmr1.ra_delta := delta;
else
nmmr1.ra_delta := slv(-signed(delta));
end if;
else
nmmr1.rb_num := MONI.regnum;
if MONI.isdec = '0' then
nmmr1.rb_delta := delta;
else
nmmr1.rb_delta := slv(-signed(delta));
end if;
end if;
end if;
end if;
N_MMR1 <= nmmr1;
N_MMR2 <= nmmr2;
end process proc_comb;
end syn;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 02:28:59 11/25/2009
-- Design Name:
-- Module Name: FlashReadTest - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity FlashReadTest is
Port ( mclk : in STD_LOGIC;
DQ : in STD_LOGIC_VECTOR(15 downto 0);
A : out STD_LOGIC_VECTOR(22 downto 0);
an : out STD_LOGIC_VECTOR(3 downto 0);
a_to_g : out STD_LOGIC_VECTOR(6 downto 0);
clk_led : out STD_LOGIC;
FlashCE_L : out STD_LOGIC;
FlashRP_L : out STD_LOGIC;
WE_L : out STD_LOGIC;
OE_L : out STD_LOGIC;
CE_L : out STD_LOGIC);
end FlashReadTest;
architecture Behavioral of FlashReadTest is
signal clk_1hz : STD_LOGIC := '0';
signal to_decoder : STD_LOGIC_VECTOR(3 downto 0);
component Comp_7segDecoder is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
seg : out STD_LOGIC_VECTOR (6 downto 0));
end component;
begin
FlashCE_L <= '0';
CE_L <= '1';
WE_L <= '1';
FlashRP_L <= '1';
OE_L <= '0';
clocker: process (mclk) is
variable count : integer := 0;
begin
if rising_edge(mclk) then
count := count + 1;
end if;
if count = 50000000 then
count := 0;
clk_1hz <= '0';
end if;
if count = 25000000 then
clk_1hz <= '1';
end if;
end process;
counter: process (clk_1hz) is
variable addr_count : STD_LOGIC_VECTOR(22 downto 0) := b"00000000000000000000000";
begin
if rising_edge(clk_1hz) then
addr_count := addr_count + 1;
end if;
A <= addr_count;
end process;
disp_data: process(DQ, mclk) is
variable clk_count : integer := 0;
variable disp_count : integer := 0;
begin
if rising_edge(mclk) then
clk_count := clk_count + 1;
if clk_count = 250000 then
disp_count := disp_count + 1;
clk_count := 0;
if disp_count = 4 then
disp_count := 0;
end if;
end if;
end if;
if disp_count = 0 then
an <= "1110";
to_decoder <= DQ(3 downto 0);
elsif disp_count = 1 then
an <= "1101";
to_decoder <= DQ(7 downto 4);
elsif disp_count = 2 then
an <= "1011";
to_decoder <= DQ(11 downto 8);
elsif disp_count = 3 then
an <= "0111";
to_decoder <= DQ(15 downto 12);
end if;
end process;
decoder : Comp_7segDecoder port map (to_decoder,
a_to_g);
clk_led <= clk_1Hz;
end Behavioral;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of cpu
--
-- Generated
-- by: wig
-- on: Fri Apr 25 14:04:07 2003
-- cmd: H:\work\mix\mix_0.pl -nodelta ..\nreset2.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: cpu-rtl-a.vhd,v 1.1 2004/04/06 10:50:35 wig Exp $
-- $Date: 2004/04/06 10:50:35 $
-- $Log: cpu-rtl-a.vhd,v $
-- Revision 1.1 2004/04/06 10:50:35 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.15 2003/04/01 14:28:00 wig Exp
--
-- Generator: mix_0.pl /mix/0.1, [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of cpu
--
architecture rtl of cpu is
--
-- Components
--
-- Generated Components
--
-- Nets
--
--
-- Generated Signals
--
--
-- End of Generated Signals
--
--Generated Constant Declarations
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
end rtl;
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
entity repro1 is
end repro1;
architecture behav of repro1 is
begin
process
variable var : natural;
procedure proc (var : natural) is
begin
assert var = 5;
end;
begin
var := 5;
proc (var => var);
wait;
end process;
end behav;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY RF_tb IS
END RF_tb;
ARCHITECTURE behavior OF RF_tb IS
COMPONENT RF
PORT(
Rs1 : IN std_logic_vector(4 downto 0);
Rs2 : IN std_logic_vector(4 downto 0);
Rd : IN std_logic_vector(4 downto 0);
Rst : IN std_logic;
Dwr : IN std_logic_vector(31 downto 0);
ORs1 : OUT std_logic_vector(31 downto 0);
ORs2 : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal Rs1 : std_logic_vector(4 downto 0) := (others => '0');
signal Rs2 : std_logic_vector(4 downto 0) := (others => '0');
signal Rd : std_logic_vector(4 downto 0) := (others => '0');
signal Rst : std_logic := '0';
signal Dwr : std_logic_vector(31 downto 0) := (others => '0');
signal ORs1 : std_logic_vector(31 downto 0);
signal ORs2 : std_logic_vector(31 downto 0);
BEGIN
uut: RF PORT MAP (
Rs1 => Rs1,
Rs2 => Rs2,
Rd => Rd,
Rst => Rst,
Dwr => Dwr,
ORs1 => ORs1,
ORs2 => ORs2
);
stim_proc: process
begin
Dwr <= "00000000000000000000000000001000";
Rd <= "00011";
rs1 <= "00011";
rs2 <= "00010";
wait for 30 ns;
rs1 <= "10000";
rs2 <= "10001";
wait for 30 ns;
end process;
END;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY RF_tb IS
END RF_tb;
ARCHITECTURE behavior OF RF_tb IS
COMPONENT RF
PORT(
Rs1 : IN std_logic_vector(4 downto 0);
Rs2 : IN std_logic_vector(4 downto 0);
Rd : IN std_logic_vector(4 downto 0);
Rst : IN std_logic;
Dwr : IN std_logic_vector(31 downto 0);
ORs1 : OUT std_logic_vector(31 downto 0);
ORs2 : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal Rs1 : std_logic_vector(4 downto 0) := (others => '0');
signal Rs2 : std_logic_vector(4 downto 0) := (others => '0');
signal Rd : std_logic_vector(4 downto 0) := (others => '0');
signal Rst : std_logic := '0';
signal Dwr : std_logic_vector(31 downto 0) := (others => '0');
signal ORs1 : std_logic_vector(31 downto 0);
signal ORs2 : std_logic_vector(31 downto 0);
BEGIN
uut: RF PORT MAP (
Rs1 => Rs1,
Rs2 => Rs2,
Rd => Rd,
Rst => Rst,
Dwr => Dwr,
ORs1 => ORs1,
ORs2 => ORs2
);
stim_proc: process
begin
Dwr <= "00000000000000000000000000001000";
Rd <= "00011";
rs1 <= "00011";
rs2 <= "00010";
wait for 30 ns;
rs1 <= "10000";
rs2 <= "10001";
wait for 30 ns;
end process;
END;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY RF_tb IS
END RF_tb;
ARCHITECTURE behavior OF RF_tb IS
COMPONENT RF
PORT(
Rs1 : IN std_logic_vector(4 downto 0);
Rs2 : IN std_logic_vector(4 downto 0);
Rd : IN std_logic_vector(4 downto 0);
Rst : IN std_logic;
Dwr : IN std_logic_vector(31 downto 0);
ORs1 : OUT std_logic_vector(31 downto 0);
ORs2 : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal Rs1 : std_logic_vector(4 downto 0) := (others => '0');
signal Rs2 : std_logic_vector(4 downto 0) := (others => '0');
signal Rd : std_logic_vector(4 downto 0) := (others => '0');
signal Rst : std_logic := '0';
signal Dwr : std_logic_vector(31 downto 0) := (others => '0');
signal ORs1 : std_logic_vector(31 downto 0);
signal ORs2 : std_logic_vector(31 downto 0);
BEGIN
uut: RF PORT MAP (
Rs1 => Rs1,
Rs2 => Rs2,
Rd => Rd,
Rst => Rst,
Dwr => Dwr,
ORs1 => ORs1,
ORs2 => ORs2
);
stim_proc: process
begin
Dwr <= "00000000000000000000000000001000";
Rd <= "00011";
rs1 <= "00011";
rs2 <= "00010";
wait for 30 ns;
rs1 <= "10000";
rs2 <= "10001";
wait for 30 ns;
end process;
END;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_a_e
--
-- Generated
-- by: wig
-- on: Mon Jul 18 10:55:02 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../logic.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_a_e-e.vhd,v 1.3 2005/07/18 08:59:29 wig Exp $
-- $Date: 2005/07/18 08:59:29 $
-- $Log: inst_a_e-e.vhd,v $
-- Revision 1.3 2005/07/18 08:59:29 wig
-- do not write config for simple logic
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.56 2005/07/15 16:39:38 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_a_e
--
entity inst_a_e is
-- Generics:
-- No Generated Generics for Entity inst_a_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_a_e
and_o1 : out std_ulogic;
and_o2 : out std_ulogic_vector(15 downto 0);
or_o1 : out std_ulogic;
or_o2 : out std_ulogic_vector(15 downto 0);
wire_bus_i : in std_ulogic_vector(7 downto 0);
wire_bus_o : out std_ulogic_vector(7 downto 0);
wire_i : in std_ulogic;
wire_o : out std_ulogic
-- End of Generated Port for Entity inst_a_e
);
end inst_a_e;
--
-- End of Generated Entity inst_a_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
-- Altera Microperipheral Reference Design Version 0802
--------------------------------------------------------
--
-- FILE NAME : a8255.vhd
-- PROJECT : Altera A8255 Peripheral Interface Adapter
-- PURPOSE : This file contains the entity and architecture
-- for the top level of the A8255 design.
--
--Copyright © 2002 Altera Corporation. All rights reserved. Altera products are
--protected under numerous U.S. and foreign patents, maskwork rights, copyrights and
--other intellectual property laws.
--This reference design file, and your use thereof, is subject to and governed by
--the terms and conditions of the applicable Altera Reference Design License Agreement.
--By using this reference design file, you indicate your acceptance of such terms and
--conditions between you and Altera Corporation. In the event that you do not agree with
--such terms and conditions, you may not use the reference design file. Please promptly
--destroy any copies you have made.
--This reference design file being provided on an "as-is" basis and as an accommodation
--and therefore all warranties, representations or guarantees of any kind
--(whether express, implied or statutory) including, without limitation, warranties of
--merchantability, non-infringement, or fitness for a particular purpose, are
--specifically disclaimed. By making this reference design file available, Altera
--expressly does not recommend, suggest or require that this reference design file be
--used in combination with any other product not provided by Altera.
--
--------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY a8255 IS
PORT(
RESET : IN std_logic;
CLK : IN std_logic;
nCS : IN std_logic;
nRD : IN std_logic;
nWR : IN std_logic;
A : IN std_logic_vector (1 DOWNTO 0);
DIN : IN std_logic_vector (7 DOWNTO 0);
PAIN : IN std_logic_vector (7 DOWNTO 0);
PBIN : IN std_logic_vector (7 DOWNTO 0);
PCIN : IN std_logic_vector (7 DOWNTO 0);
DOUT : OUT std_logic_vector (7 DOWNTO 0);
PAOUT : OUT std_logic_vector (7 DOWNTO 0);
PAEN : OUT std_logic;
PBOUT : OUT std_logic_vector (7 DOWNTO 0);
PBEN : OUT std_logic;
PCOUT : OUT std_logic_vector (7 DOWNTO 0);
PCEN : OUT std_logic_vector (7 DOWNTO 0)
);
END a8255;
ARCHITECTURE structure OF a8255 IS
-- SIGNAL DECLARATIONS
SIGNAL DOUTSelect : std_logic_vector(2 DOWNTO 0);
SIGNAL ControlReg : std_logic_vector(7 DOWNTO 0);
SIGNAL PortAOutLd : std_logic;
SIGNAL PortBOutLd : std_logic;
SIGNAL PortCOverride : std_logic;
SIGNAL PortCOutLd : std_logic_vector (7 DOWNTO 0);
SIGNAL PortAInReg : std_logic_vector (7 DOWNTO 0);
SIGNAL PortBInReg : std_logic_vector (7 DOWNTO 0);
SIGNAL PortARead : std_logic;
SIGNAL PortBRead : std_logic;
SIGNAL PortAWrite : std_logic;
SIGNAL PortBWrite : std_logic;
SIGNAL PortCStatus : std_logic_vector (7 DOWNTO 0);
SIGNAL CompositePortCStatus : std_logic_vector (7 DOWNTO 0);
-- COMPONENT_DECLARATIONS
COMPONENT dout_mux
PORT(
DOUTSelect : IN std_logic_vector (2 DOWNTO 0);
ControlReg : IN std_logic_vector (7 DOWNTO 0);
PortAInReg : IN std_logic_vector (7 DOWNTO 0);
PAIN : IN std_logic_vector (7 DOWNTO 0);
PortBInReg : IN std_logic_vector (7 DOWNTO 0);
PBIN : IN std_logic_vector (7 DOWNTO 0);
PortCStatus : IN std_logic_vector (7 DOWNTO 0);
DOUT : OUT std_logic_vector(7 DOWNTO 0)
);
END COMPONENT;
COMPONENT cntl_log
PORT(
RESET : IN std_logic;
CLK : IN std_logic;
nCS : IN std_logic;
nRD : IN std_logic;
nWR : IN std_logic;
A : IN std_logic_vector (1 DOWNTO 0);
DIN : IN std_logic_vector(7 DOWNTO 0);
PCIN : IN std_logic_vector(7 DOWNTO 0);
PAEN : OUT std_logic;
PBEN : OUT std_logic;
PCEN : OUT std_logic_vector (7 DOWNTO 0);
DOUTSelect : OUT std_logic_vector (2 DOWNTO 0);
ControlReg : OUT std_logic_vector (7 DOWNTO 0);
PortARead : OUT std_logic;
PortBRead : OUT std_logic;
PortAWrite : OUT std_logic;
PortBWrite : OUT std_logic;
PortAOutLd : OUT std_logic;
PortBOutLd : OUT std_logic;
PortCOverride : OUT std_logic;
PortCOutLd : OUT std_logic_vector (7 DOWNTO 0)
);
END COMPONENT;
COMPONENT portaout
PORT(
DIN : IN std_logic_vector (7 DOWNTO 0);
RESET : IN std_logic;
CLK : IN std_logic;
PortAOutLd : IN std_logic;
PAOUT : OUT std_logic_vector (7 DOWNTO 0)
);
END COMPONENT;
COMPONENT portain
PORT(
PAIN : IN std_logic_vector (7 DOWNTO 0);
RESET : IN std_logic;
CLK : IN std_logic;
PortAInLd : IN std_logic;
PortAInReg : OUT std_logic_vector (7 DOWNTO 0)
);
END COMPONENT;
COMPONENT portbout
PORT(
DIN : IN std_logic_vector (7 DOWNTO 0);
RESET : IN std_logic;
CLK : IN std_logic;
PortBOutLd : IN std_logic;
PBOUT : OUT std_logic_vector (7 DOWNTO 0)
);
END COMPONENT;
COMPONENT portbin
PORT(
PBIN : IN std_logic_vector (7 DOWNTO 0);
RESET : IN std_logic;
CLK : IN std_logic;
PortBInLd : IN std_logic;
PortBInReg : OUT std_logic_vector (7 DOWNTO 0)
);
END COMPONENT;
COMPONENT portcout
PORT(
RESET : IN std_logic;
CLK : IN std_logic;
DIN : IN std_logic_vector (7 DOWNTO 0);
PCIN : IN std_logic_vector (7 DOWNTO 0);
ControlReg : IN std_logic_vector (7 DOWNTO 0);
PortARead : IN std_logic;
PortBRead : IN std_logic;
PortAWrite : IN std_logic;
PortBWrite : IN std_logic;
PortCOverride : IN std_logic;
PortCOutLd : IN std_logic_vector (7 DOWNTO 0);
PortCStatus : OUT std_logic_vector (7 DOWNTO 0);
PCOUT : OUT std_logic_vector (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
-- CONCURRENT SIGNAL ASSIGNMENTS
CompositePortCStatus <= PCIN(7) &
PortCStatus(6) &
PCIN(5) &
PortCStatus(4) &
PCIN(3) &
PortCStatus(2) &
PCIN(1) &
PCIN(0);
-- COMPONENT INSTANTIATIONS
I_dout_mux : dout_mux
PORT MAP(
DOUTSelect => DOUTSelect ,
ControlReg => ControlReg ,
PortAInReg => PortAInReg ,
PAIN => PAIN ,
PortBInReg => PortBInReg ,
PBIN => PBIN ,
PortCStatus => CompositePortCStatus,
DOUT => DOUT
);
I_cntl_log : cntl_log
PORT MAP(
RESET => RESET ,
CLK => CLK ,
nCS => nCS ,
nRD => nRD ,
nWR => nWR ,
A => A ,
DIN => DIN ,
PCIN => PCIN ,
PAEN => PAEN ,
PBEN => PBEN ,
PCEN => PCEN ,
DOUTSelect => DOUTSelect ,
ControlReg => ControlReg ,
PortARead => PortARead ,
PortBRead => PortBRead ,
PortAWrite => PortAWrite ,
PortBWrite => PortBWrite ,
PortAOutLd => PortAOutLd ,
PortBOutLd => PortBOutLd ,
PortCOverride => PortCOverride ,
PortCOutLd => PortCOutLd
);
I_portaout : portaout
PORT MAP(
DIN => DIN ,
RESET => RESET ,
CLK => CLK ,
PortAOutLd => PortAOutLd,
PAOUT => PAOUT
);
I_portain : portain
PORT MAP(
PAIN => PAIN ,
RESET => RESET ,
CLK => CLK ,
PortAInLd => PCIN (4) ,
PortAInReg => PortAInReg
);
I_portbout : portbout
PORT MAP(
DIN => DIN ,
RESET => RESET ,
CLK => CLK ,
PortBOutLd => PortBOutLd,
PBOUT => PBOUT
);
I_portbin : portbin
PORT MAP(
PBIN => PBIN ,
RESET => RESET ,
CLK => CLK ,
PortBInLd => PCIN (2) ,
PortBInReg => PortBInReg
);
I_portcout : portcout
PORT MAP(
RESET => RESET ,
CLK => CLK ,
DIN => DIN ,
PCIN => PCIN ,
ControlReg => ControlReg ,
PortARead => PortARead ,
PortBRead => PortBRead ,
PortAWrite => PortAWrite ,
PortBWrite => PortBWrite ,
PortCOutLd => PortCOutLd ,
PortCOverride => PortCOverride,
PortCStatus => PortCStatus ,
PCOUT => PCOUT
);
END structure;
|
library verilog;
use verilog.vl_types.all;
entity dcfifo_dffpipe is
generic(
lpm_delay : integer := 1;
lpm_width : integer := 64;
delay : vl_notype
);
port(
d : in vl_logic_vector;
clock : in vl_logic;
aclr : in vl_logic;
q : out vl_logic_vector
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of lpm_delay : constant is 1;
attribute mti_svvh_generic_type of lpm_width : constant is 1;
attribute mti_svvh_generic_type of delay : constant is 3;
end dcfifo_dffpipe;
|
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|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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|
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