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-------------------------------------------------------------------------------
--
-- File: ChannelBond.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module de-skews data channels relative to each other. TMDS specs
-- allow 0.2 Tcharacter + 1.78ns skew between channels. To re-align the
-- channels all are buffered in FIFOs until a special marker (the beginning
-- of a blanking period) is found on all the channels.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.DVI_Constants.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ChannelBond is
Port (
PixelClk : in std_logic;
pDataInRaw : in std_logic_vector(9 downto 0);
pMeVld : in std_logic;
pOtherChVld : in std_logic_vector(1 downto 0);
pOtherChRdy : in std_logic_vector(1 downto 0);
pDataInBnd : out std_logic_vector(9 downto 0);
pMeRdy : out std_logic
);
end ChannelBond;
architecture Behavioral of ChannelBond is
constant kFIFO_Depth : natural := 32;
type FIFO_t is array (0 to kFIFO_Depth-1) of std_logic_vector(9 downto 0);
signal pFIFO : FIFO_t;
signal pDataFIFO : std_logic_vector(9 downto 0);
signal pRdA, pWrA : natural range 0 to kFIFO_Depth-1;
signal pRdEn : std_logic;
signal pAllVld, pAllVld_q, pMeRdy_int: std_logic;
signal pBlnkBgnFlag, pTokenFlag, pTokenFlag_q, pAllVldBgnFlag : std_logic;
begin
pAllVld <= pMeVld and pOtherChVld(0) and pOtherChVld(1);
pDataInBnd <= pDataFIFO; -- raw data with skew removed
pMeRdy <= pMeRdy_int; -- data is de-skewed and valid
-- The process below should result in a dual-port distributed RAM with registered output
FIFO: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pAllVld = '1') then -- begin writing in FIFO as soon as all the channels have valid data
pFIFO(pWrA) <= pDataInRaw;
end if;
pDataFIFO <= pFIFO(pRdA); -- register FIFO output
end if;
end process FIFO;
-- FIFO address counters
FIFO_WrA: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pAllVld = '1') then
pWrA <= pWrA + 1;
else -- when invalid data, go back to the beginning
pWrA <= 0;
end if;
end if;
end process FIFO_WrA;
FIFO_RdA: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pAllVld = '0') then
pRdA <= 0;
elsif (pRdEn = '1') then
pRdA <= pRdA + 1;
end if;
end if;
end process FIFO_RdA;
DataValidFlag: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
pAllVld_q <= pAllVld;
pAllVldBgnFlag <= not pAllVld_q and pAllVld; -- this flag used below delays enabling read, thus making sure data is written first before being read
end if;
end process DataValidFlag;
-------------------------------------------------------------------------------
-- Channel bonding is done here:
-- 1 When all the channels have valid data (ie. alignment lock), FIFO is flow-through
-- 2 When marker is found on this channel, FIFO read is paused, thus holding data
-- 3 When all channels report the marker, FIFO read begins again, thus syncing markers
-------------------------------------------------------------------------------
FIFO_RdEn: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pAllVld = '0') then
pRdEn <= '0';
elsif (pAllVldBgnFlag = '1' or (pMeRdy_int = '1' and pOtherChRdy = "11")) then
pRdEn <= '1';
elsif (pBlnkBgnFlag = '1' and not (pMeRdy_int = '1' and pOtherChRdy = "11")) then
pRdEn <= '0';
end if;
end if;
end process FIFO_RdEn;
-- Detect blanking period begin
TokenDetect: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pRdEn = '0' or pDataFIFO = kCtlTkn0 or pDataFIFO = kCtlTkn1 or pDataFIFO = kCtlTkn2 or pDataFIFO = kCtlTkn3) then
pTokenFlag <= '1'; --token flag activates on invalid data, which avoids a BlnkBgn pulse if the valid signal goes up in the middle of a blanking period
else
pTokenFlag <= '0';
end if;
pTokenFlag_q <= pTokenFlag;
pBlnkBgnFlag <= not pTokenFlag_q and pTokenFlag;
end if;
end process TokenDetect;
-- Ready signal when marker is received
IAmReady: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pAllVld = '0') then -- if not all channels are valid, we are not ready either
pMeRdy_int <= '0';
elsif (pBlnkBgnFlag = '1') then
pMeRdy_int <= '1';
end if;
end if;
end process IAmReady;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- File: ChannelBond.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module de-skews data channels relative to each other. TMDS specs
-- allow 0.2 Tcharacter + 1.78ns skew between channels. To re-align the
-- channels all are buffered in FIFOs until a special marker (the beginning
-- of a blanking period) is found on all the channels.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.DVI_Constants.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ChannelBond is
Port (
PixelClk : in std_logic;
pDataInRaw : in std_logic_vector(9 downto 0);
pMeVld : in std_logic;
pOtherChVld : in std_logic_vector(1 downto 0);
pOtherChRdy : in std_logic_vector(1 downto 0);
pDataInBnd : out std_logic_vector(9 downto 0);
pMeRdy : out std_logic
);
end ChannelBond;
architecture Behavioral of ChannelBond is
constant kFIFO_Depth : natural := 32;
type FIFO_t is array (0 to kFIFO_Depth-1) of std_logic_vector(9 downto 0);
signal pFIFO : FIFO_t;
signal pDataFIFO : std_logic_vector(9 downto 0);
signal pRdA, pWrA : natural range 0 to kFIFO_Depth-1;
signal pRdEn : std_logic;
signal pAllVld, pAllVld_q, pMeRdy_int: std_logic;
signal pBlnkBgnFlag, pTokenFlag, pTokenFlag_q, pAllVldBgnFlag : std_logic;
begin
pAllVld <= pMeVld and pOtherChVld(0) and pOtherChVld(1);
pDataInBnd <= pDataFIFO; -- raw data with skew removed
pMeRdy <= pMeRdy_int; -- data is de-skewed and valid
-- The process below should result in a dual-port distributed RAM with registered output
FIFO: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pAllVld = '1') then -- begin writing in FIFO as soon as all the channels have valid data
pFIFO(pWrA) <= pDataInRaw;
end if;
pDataFIFO <= pFIFO(pRdA); -- register FIFO output
end if;
end process FIFO;
-- FIFO address counters
FIFO_WrA: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pAllVld = '1') then
pWrA <= pWrA + 1;
else -- when invalid data, go back to the beginning
pWrA <= 0;
end if;
end if;
end process FIFO_WrA;
FIFO_RdA: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pAllVld = '0') then
pRdA <= 0;
elsif (pRdEn = '1') then
pRdA <= pRdA + 1;
end if;
end if;
end process FIFO_RdA;
DataValidFlag: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
pAllVld_q <= pAllVld;
pAllVldBgnFlag <= not pAllVld_q and pAllVld; -- this flag used below delays enabling read, thus making sure data is written first before being read
end if;
end process DataValidFlag;
-------------------------------------------------------------------------------
-- Channel bonding is done here:
-- 1 When all the channels have valid data (ie. alignment lock), FIFO is flow-through
-- 2 When marker is found on this channel, FIFO read is paused, thus holding data
-- 3 When all channels report the marker, FIFO read begins again, thus syncing markers
-------------------------------------------------------------------------------
FIFO_RdEn: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pAllVld = '0') then
pRdEn <= '0';
elsif (pAllVldBgnFlag = '1' or (pMeRdy_int = '1' and pOtherChRdy = "11")) then
pRdEn <= '1';
elsif (pBlnkBgnFlag = '1' and not (pMeRdy_int = '1' and pOtherChRdy = "11")) then
pRdEn <= '0';
end if;
end if;
end process FIFO_RdEn;
-- Detect blanking period begin
TokenDetect: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pRdEn = '0' or pDataFIFO = kCtlTkn0 or pDataFIFO = kCtlTkn1 or pDataFIFO = kCtlTkn2 or pDataFIFO = kCtlTkn3) then
pTokenFlag <= '1'; --token flag activates on invalid data, which avoids a BlnkBgn pulse if the valid signal goes up in the middle of a blanking period
else
pTokenFlag <= '0';
end if;
pTokenFlag_q <= pTokenFlag;
pBlnkBgnFlag <= not pTokenFlag_q and pTokenFlag;
end if;
end process TokenDetect;
-- Ready signal when marker is received
IAmReady: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pAllVld = '0') then -- if not all channels are valid, we are not ready either
pMeRdy_int <= '0';
elsif (pBlnkBgnFlag = '1') then
pMeRdy_int <= '1';
end if;
end if;
end process IAmReady;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- File: ChannelBond.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module de-skews data channels relative to each other. TMDS specs
-- allow 0.2 Tcharacter + 1.78ns skew between channels. To re-align the
-- channels all are buffered in FIFOs until a special marker (the beginning
-- of a blanking period) is found on all the channels.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.DVI_Constants.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ChannelBond is
Port (
PixelClk : in std_logic;
pDataInRaw : in std_logic_vector(9 downto 0);
pMeVld : in std_logic;
pOtherChVld : in std_logic_vector(1 downto 0);
pOtherChRdy : in std_logic_vector(1 downto 0);
pDataInBnd : out std_logic_vector(9 downto 0);
pMeRdy : out std_logic
);
end ChannelBond;
architecture Behavioral of ChannelBond is
constant kFIFO_Depth : natural := 32;
type FIFO_t is array (0 to kFIFO_Depth-1) of std_logic_vector(9 downto 0);
signal pFIFO : FIFO_t;
signal pDataFIFO : std_logic_vector(9 downto 0);
signal pRdA, pWrA : natural range 0 to kFIFO_Depth-1;
signal pRdEn : std_logic;
signal pAllVld, pAllVld_q, pMeRdy_int: std_logic;
signal pBlnkBgnFlag, pTokenFlag, pTokenFlag_q, pAllVldBgnFlag : std_logic;
begin
pAllVld <= pMeVld and pOtherChVld(0) and pOtherChVld(1);
pDataInBnd <= pDataFIFO; -- raw data with skew removed
pMeRdy <= pMeRdy_int; -- data is de-skewed and valid
-- The process below should result in a dual-port distributed RAM with registered output
FIFO: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pAllVld = '1') then -- begin writing in FIFO as soon as all the channels have valid data
pFIFO(pWrA) <= pDataInRaw;
end if;
pDataFIFO <= pFIFO(pRdA); -- register FIFO output
end if;
end process FIFO;
-- FIFO address counters
FIFO_WrA: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pAllVld = '1') then
pWrA <= pWrA + 1;
else -- when invalid data, go back to the beginning
pWrA <= 0;
end if;
end if;
end process FIFO_WrA;
FIFO_RdA: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pAllVld = '0') then
pRdA <= 0;
elsif (pRdEn = '1') then
pRdA <= pRdA + 1;
end if;
end if;
end process FIFO_RdA;
DataValidFlag: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
pAllVld_q <= pAllVld;
pAllVldBgnFlag <= not pAllVld_q and pAllVld; -- this flag used below delays enabling read, thus making sure data is written first before being read
end if;
end process DataValidFlag;
-------------------------------------------------------------------------------
-- Channel bonding is done here:
-- 1 When all the channels have valid data (ie. alignment lock), FIFO is flow-through
-- 2 When marker is found on this channel, FIFO read is paused, thus holding data
-- 3 When all channels report the marker, FIFO read begins again, thus syncing markers
-------------------------------------------------------------------------------
FIFO_RdEn: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pAllVld = '0') then
pRdEn <= '0';
elsif (pAllVldBgnFlag = '1' or (pMeRdy_int = '1' and pOtherChRdy = "11")) then
pRdEn <= '1';
elsif (pBlnkBgnFlag = '1' and not (pMeRdy_int = '1' and pOtherChRdy = "11")) then
pRdEn <= '0';
end if;
end if;
end process FIFO_RdEn;
-- Detect blanking period begin
TokenDetect: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pRdEn = '0' or pDataFIFO = kCtlTkn0 or pDataFIFO = kCtlTkn1 or pDataFIFO = kCtlTkn2 or pDataFIFO = kCtlTkn3) then
pTokenFlag <= '1'; --token flag activates on invalid data, which avoids a BlnkBgn pulse if the valid signal goes up in the middle of a blanking period
else
pTokenFlag <= '0';
end if;
pTokenFlag_q <= pTokenFlag;
pBlnkBgnFlag <= not pTokenFlag_q and pTokenFlag;
end if;
end process TokenDetect;
-- Ready signal when marker is received
IAmReady: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pAllVld = '0') then -- if not all channels are valid, we are not ready either
pMeRdy_int <= '0';
elsif (pBlnkBgnFlag = '1') then
pMeRdy_int <= '1';
end if;
end if;
end process IAmReady;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- File: ChannelBond.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module de-skews data channels relative to each other. TMDS specs
-- allow 0.2 Tcharacter + 1.78ns skew between channels. To re-align the
-- channels all are buffered in FIFOs until a special marker (the beginning
-- of a blanking period) is found on all the channels.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.DVI_Constants.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ChannelBond is
Port (
PixelClk : in std_logic;
pDataInRaw : in std_logic_vector(9 downto 0);
pMeVld : in std_logic;
pOtherChVld : in std_logic_vector(1 downto 0);
pOtherChRdy : in std_logic_vector(1 downto 0);
pDataInBnd : out std_logic_vector(9 downto 0);
pMeRdy : out std_logic
);
end ChannelBond;
architecture Behavioral of ChannelBond is
constant kFIFO_Depth : natural := 32;
type FIFO_t is array (0 to kFIFO_Depth-1) of std_logic_vector(9 downto 0);
signal pFIFO : FIFO_t;
signal pDataFIFO : std_logic_vector(9 downto 0);
signal pRdA, pWrA : natural range 0 to kFIFO_Depth-1;
signal pRdEn : std_logic;
signal pAllVld, pAllVld_q, pMeRdy_int: std_logic;
signal pBlnkBgnFlag, pTokenFlag, pTokenFlag_q, pAllVldBgnFlag : std_logic;
begin
pAllVld <= pMeVld and pOtherChVld(0) and pOtherChVld(1);
pDataInBnd <= pDataFIFO; -- raw data with skew removed
pMeRdy <= pMeRdy_int; -- data is de-skewed and valid
-- The process below should result in a dual-port distributed RAM with registered output
FIFO: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pAllVld = '1') then -- begin writing in FIFO as soon as all the channels have valid data
pFIFO(pWrA) <= pDataInRaw;
end if;
pDataFIFO <= pFIFO(pRdA); -- register FIFO output
end if;
end process FIFO;
-- FIFO address counters
FIFO_WrA: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pAllVld = '1') then
pWrA <= pWrA + 1;
else -- when invalid data, go back to the beginning
pWrA <= 0;
end if;
end if;
end process FIFO_WrA;
FIFO_RdA: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pAllVld = '0') then
pRdA <= 0;
elsif (pRdEn = '1') then
pRdA <= pRdA + 1;
end if;
end if;
end process FIFO_RdA;
DataValidFlag: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
pAllVld_q <= pAllVld;
pAllVldBgnFlag <= not pAllVld_q and pAllVld; -- this flag used below delays enabling read, thus making sure data is written first before being read
end if;
end process DataValidFlag;
-------------------------------------------------------------------------------
-- Channel bonding is done here:
-- 1 When all the channels have valid data (ie. alignment lock), FIFO is flow-through
-- 2 When marker is found on this channel, FIFO read is paused, thus holding data
-- 3 When all channels report the marker, FIFO read begins again, thus syncing markers
-------------------------------------------------------------------------------
FIFO_RdEn: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pAllVld = '0') then
pRdEn <= '0';
elsif (pAllVldBgnFlag = '1' or (pMeRdy_int = '1' and pOtherChRdy = "11")) then
pRdEn <= '1';
elsif (pBlnkBgnFlag = '1' and not (pMeRdy_int = '1' and pOtherChRdy = "11")) then
pRdEn <= '0';
end if;
end if;
end process FIFO_RdEn;
-- Detect blanking period begin
TokenDetect: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pRdEn = '0' or pDataFIFO = kCtlTkn0 or pDataFIFO = kCtlTkn1 or pDataFIFO = kCtlTkn2 or pDataFIFO = kCtlTkn3) then
pTokenFlag <= '1'; --token flag activates on invalid data, which avoids a BlnkBgn pulse if the valid signal goes up in the middle of a blanking period
else
pTokenFlag <= '0';
end if;
pTokenFlag_q <= pTokenFlag;
pBlnkBgnFlag <= not pTokenFlag_q and pTokenFlag;
end if;
end process TokenDetect;
-- Ready signal when marker is received
IAmReady: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pAllVld = '0') then -- if not all channels are valid, we are not ready either
pMeRdy_int <= '0';
elsif (pBlnkBgnFlag = '1') then
pMeRdy_int <= '1';
end if;
end if;
end process IAmReady;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- File: ChannelBond.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module de-skews data channels relative to each other. TMDS specs
-- allow 0.2 Tcharacter + 1.78ns skew between channels. To re-align the
-- channels all are buffered in FIFOs until a special marker (the beginning
-- of a blanking period) is found on all the channels.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.DVI_Constants.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ChannelBond is
Port (
PixelClk : in std_logic;
pDataInRaw : in std_logic_vector(9 downto 0);
pMeVld : in std_logic;
pOtherChVld : in std_logic_vector(1 downto 0);
pOtherChRdy : in std_logic_vector(1 downto 0);
pDataInBnd : out std_logic_vector(9 downto 0);
pMeRdy : out std_logic
);
end ChannelBond;
architecture Behavioral of ChannelBond is
constant kFIFO_Depth : natural := 32;
type FIFO_t is array (0 to kFIFO_Depth-1) of std_logic_vector(9 downto 0);
signal pFIFO : FIFO_t;
signal pDataFIFO : std_logic_vector(9 downto 0);
signal pRdA, pWrA : natural range 0 to kFIFO_Depth-1;
signal pRdEn : std_logic;
signal pAllVld, pAllVld_q, pMeRdy_int: std_logic;
signal pBlnkBgnFlag, pTokenFlag, pTokenFlag_q, pAllVldBgnFlag : std_logic;
begin
pAllVld <= pMeVld and pOtherChVld(0) and pOtherChVld(1);
pDataInBnd <= pDataFIFO; -- raw data with skew removed
pMeRdy <= pMeRdy_int; -- data is de-skewed and valid
-- The process below should result in a dual-port distributed RAM with registered output
FIFO: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pAllVld = '1') then -- begin writing in FIFO as soon as all the channels have valid data
pFIFO(pWrA) <= pDataInRaw;
end if;
pDataFIFO <= pFIFO(pRdA); -- register FIFO output
end if;
end process FIFO;
-- FIFO address counters
FIFO_WrA: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pAllVld = '1') then
pWrA <= pWrA + 1;
else -- when invalid data, go back to the beginning
pWrA <= 0;
end if;
end if;
end process FIFO_WrA;
FIFO_RdA: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pAllVld = '0') then
pRdA <= 0;
elsif (pRdEn = '1') then
pRdA <= pRdA + 1;
end if;
end if;
end process FIFO_RdA;
DataValidFlag: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
pAllVld_q <= pAllVld;
pAllVldBgnFlag <= not pAllVld_q and pAllVld; -- this flag used below delays enabling read, thus making sure data is written first before being read
end if;
end process DataValidFlag;
-------------------------------------------------------------------------------
-- Channel bonding is done here:
-- 1 When all the channels have valid data (ie. alignment lock), FIFO is flow-through
-- 2 When marker is found on this channel, FIFO read is paused, thus holding data
-- 3 When all channels report the marker, FIFO read begins again, thus syncing markers
-------------------------------------------------------------------------------
FIFO_RdEn: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pAllVld = '0') then
pRdEn <= '0';
elsif (pAllVldBgnFlag = '1' or (pMeRdy_int = '1' and pOtherChRdy = "11")) then
pRdEn <= '1';
elsif (pBlnkBgnFlag = '1' and not (pMeRdy_int = '1' and pOtherChRdy = "11")) then
pRdEn <= '0';
end if;
end if;
end process FIFO_RdEn;
-- Detect blanking period begin
TokenDetect: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pRdEn = '0' or pDataFIFO = kCtlTkn0 or pDataFIFO = kCtlTkn1 or pDataFIFO = kCtlTkn2 or pDataFIFO = kCtlTkn3) then
pTokenFlag <= '1'; --token flag activates on invalid data, which avoids a BlnkBgn pulse if the valid signal goes up in the middle of a blanking period
else
pTokenFlag <= '0';
end if;
pTokenFlag_q <= pTokenFlag;
pBlnkBgnFlag <= not pTokenFlag_q and pTokenFlag;
end if;
end process TokenDetect;
-- Ready signal when marker is received
IAmReady: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pAllVld = '0') then -- if not all channels are valid, we are not ready either
pMeRdy_int <= '0';
elsif (pBlnkBgnFlag = '1') then
pMeRdy_int <= '1';
end if;
end if;
end process IAmReady;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- File: ChannelBond.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module de-skews data channels relative to each other. TMDS specs
-- allow 0.2 Tcharacter + 1.78ns skew between channels. To re-align the
-- channels all are buffered in FIFOs until a special marker (the beginning
-- of a blanking period) is found on all the channels.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.DVI_Constants.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ChannelBond is
Port (
PixelClk : in std_logic;
pDataInRaw : in std_logic_vector(9 downto 0);
pMeVld : in std_logic;
pOtherChVld : in std_logic_vector(1 downto 0);
pOtherChRdy : in std_logic_vector(1 downto 0);
pDataInBnd : out std_logic_vector(9 downto 0);
pMeRdy : out std_logic
);
end ChannelBond;
architecture Behavioral of ChannelBond is
constant kFIFO_Depth : natural := 32;
type FIFO_t is array (0 to kFIFO_Depth-1) of std_logic_vector(9 downto 0);
signal pFIFO : FIFO_t;
signal pDataFIFO : std_logic_vector(9 downto 0);
signal pRdA, pWrA : natural range 0 to kFIFO_Depth-1;
signal pRdEn : std_logic;
signal pAllVld, pAllVld_q, pMeRdy_int: std_logic;
signal pBlnkBgnFlag, pTokenFlag, pTokenFlag_q, pAllVldBgnFlag : std_logic;
begin
pAllVld <= pMeVld and pOtherChVld(0) and pOtherChVld(1);
pDataInBnd <= pDataFIFO; -- raw data with skew removed
pMeRdy <= pMeRdy_int; -- data is de-skewed and valid
-- The process below should result in a dual-port distributed RAM with registered output
FIFO: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pAllVld = '1') then -- begin writing in FIFO as soon as all the channels have valid data
pFIFO(pWrA) <= pDataInRaw;
end if;
pDataFIFO <= pFIFO(pRdA); -- register FIFO output
end if;
end process FIFO;
-- FIFO address counters
FIFO_WrA: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pAllVld = '1') then
pWrA <= pWrA + 1;
else -- when invalid data, go back to the beginning
pWrA <= 0;
end if;
end if;
end process FIFO_WrA;
FIFO_RdA: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pAllVld = '0') then
pRdA <= 0;
elsif (pRdEn = '1') then
pRdA <= pRdA + 1;
end if;
end if;
end process FIFO_RdA;
DataValidFlag: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
pAllVld_q <= pAllVld;
pAllVldBgnFlag <= not pAllVld_q and pAllVld; -- this flag used below delays enabling read, thus making sure data is written first before being read
end if;
end process DataValidFlag;
-------------------------------------------------------------------------------
-- Channel bonding is done here:
-- 1 When all the channels have valid data (ie. alignment lock), FIFO is flow-through
-- 2 When marker is found on this channel, FIFO read is paused, thus holding data
-- 3 When all channels report the marker, FIFO read begins again, thus syncing markers
-------------------------------------------------------------------------------
FIFO_RdEn: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pAllVld = '0') then
pRdEn <= '0';
elsif (pAllVldBgnFlag = '1' or (pMeRdy_int = '1' and pOtherChRdy = "11")) then
pRdEn <= '1';
elsif (pBlnkBgnFlag = '1' and not (pMeRdy_int = '1' and pOtherChRdy = "11")) then
pRdEn <= '0';
end if;
end if;
end process FIFO_RdEn;
-- Detect blanking period begin
TokenDetect: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pRdEn = '0' or pDataFIFO = kCtlTkn0 or pDataFIFO = kCtlTkn1 or pDataFIFO = kCtlTkn2 or pDataFIFO = kCtlTkn3) then
pTokenFlag <= '1'; --token flag activates on invalid data, which avoids a BlnkBgn pulse if the valid signal goes up in the middle of a blanking period
else
pTokenFlag <= '0';
end if;
pTokenFlag_q <= pTokenFlag;
pBlnkBgnFlag <= not pTokenFlag_q and pTokenFlag;
end if;
end process TokenDetect;
-- Ready signal when marker is received
IAmReady: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pAllVld = '0') then -- if not all channels are valid, we are not ready either
pMeRdy_int <= '0';
elsif (pBlnkBgnFlag = '1') then
pMeRdy_int <= '1';
end if;
end if;
end process IAmReady;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- File: ChannelBond.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module de-skews data channels relative to each other. TMDS specs
-- allow 0.2 Tcharacter + 1.78ns skew between channels. To re-align the
-- channels all are buffered in FIFOs until a special marker (the beginning
-- of a blanking period) is found on all the channels.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.DVI_Constants.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ChannelBond is
Port (
PixelClk : in std_logic;
pDataInRaw : in std_logic_vector(9 downto 0);
pMeVld : in std_logic;
pOtherChVld : in std_logic_vector(1 downto 0);
pOtherChRdy : in std_logic_vector(1 downto 0);
pDataInBnd : out std_logic_vector(9 downto 0);
pMeRdy : out std_logic
);
end ChannelBond;
architecture Behavioral of ChannelBond is
constant kFIFO_Depth : natural := 32;
type FIFO_t is array (0 to kFIFO_Depth-1) of std_logic_vector(9 downto 0);
signal pFIFO : FIFO_t;
signal pDataFIFO : std_logic_vector(9 downto 0);
signal pRdA, pWrA : natural range 0 to kFIFO_Depth-1;
signal pRdEn : std_logic;
signal pAllVld, pAllVld_q, pMeRdy_int: std_logic;
signal pBlnkBgnFlag, pTokenFlag, pTokenFlag_q, pAllVldBgnFlag : std_logic;
begin
pAllVld <= pMeVld and pOtherChVld(0) and pOtherChVld(1);
pDataInBnd <= pDataFIFO; -- raw data with skew removed
pMeRdy <= pMeRdy_int; -- data is de-skewed and valid
-- The process below should result in a dual-port distributed RAM with registered output
FIFO: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pAllVld = '1') then -- begin writing in FIFO as soon as all the channels have valid data
pFIFO(pWrA) <= pDataInRaw;
end if;
pDataFIFO <= pFIFO(pRdA); -- register FIFO output
end if;
end process FIFO;
-- FIFO address counters
FIFO_WrA: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pAllVld = '1') then
pWrA <= pWrA + 1;
else -- when invalid data, go back to the beginning
pWrA <= 0;
end if;
end if;
end process FIFO_WrA;
FIFO_RdA: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pAllVld = '0') then
pRdA <= 0;
elsif (pRdEn = '1') then
pRdA <= pRdA + 1;
end if;
end if;
end process FIFO_RdA;
DataValidFlag: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
pAllVld_q <= pAllVld;
pAllVldBgnFlag <= not pAllVld_q and pAllVld; -- this flag used below delays enabling read, thus making sure data is written first before being read
end if;
end process DataValidFlag;
-------------------------------------------------------------------------------
-- Channel bonding is done here:
-- 1 When all the channels have valid data (ie. alignment lock), FIFO is flow-through
-- 2 When marker is found on this channel, FIFO read is paused, thus holding data
-- 3 When all channels report the marker, FIFO read begins again, thus syncing markers
-------------------------------------------------------------------------------
FIFO_RdEn: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pAllVld = '0') then
pRdEn <= '0';
elsif (pAllVldBgnFlag = '1' or (pMeRdy_int = '1' and pOtherChRdy = "11")) then
pRdEn <= '1';
elsif (pBlnkBgnFlag = '1' and not (pMeRdy_int = '1' and pOtherChRdy = "11")) then
pRdEn <= '0';
end if;
end if;
end process FIFO_RdEn;
-- Detect blanking period begin
TokenDetect: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pRdEn = '0' or pDataFIFO = kCtlTkn0 or pDataFIFO = kCtlTkn1 or pDataFIFO = kCtlTkn2 or pDataFIFO = kCtlTkn3) then
pTokenFlag <= '1'; --token flag activates on invalid data, which avoids a BlnkBgn pulse if the valid signal goes up in the middle of a blanking period
else
pTokenFlag <= '0';
end if;
pTokenFlag_q <= pTokenFlag;
pBlnkBgnFlag <= not pTokenFlag_q and pTokenFlag;
end if;
end process TokenDetect;
-- Ready signal when marker is received
IAmReady: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pAllVld = '0') then -- if not all channels are valid, we are not ready either
pMeRdy_int <= '0';
elsif (pBlnkBgnFlag = '1') then
pMeRdy_int <= '1';
end if;
end if;
end process IAmReady;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- File: ChannelBond.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 8 October 2014
--
-------------------------------------------------------------------------------
-- (c) 2014 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module de-skews data channels relative to each other. TMDS specs
-- allow 0.2 Tcharacter + 1.78ns skew between channels. To re-align the
-- channels all are buffered in FIFOs until a special marker (the beginning
-- of a blanking period) is found on all the channels.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.DVI_Constants.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ChannelBond is
Port (
PixelClk : in std_logic;
pDataInRaw : in std_logic_vector(9 downto 0);
pMeVld : in std_logic;
pOtherChVld : in std_logic_vector(1 downto 0);
pOtherChRdy : in std_logic_vector(1 downto 0);
pDataInBnd : out std_logic_vector(9 downto 0);
pMeRdy : out std_logic
);
end ChannelBond;
architecture Behavioral of ChannelBond is
constant kFIFO_Depth : natural := 32;
type FIFO_t is array (0 to kFIFO_Depth-1) of std_logic_vector(9 downto 0);
signal pFIFO : FIFO_t;
signal pDataFIFO : std_logic_vector(9 downto 0);
signal pRdA, pWrA : natural range 0 to kFIFO_Depth-1;
signal pRdEn : std_logic;
signal pAllVld, pAllVld_q, pMeRdy_int: std_logic;
signal pBlnkBgnFlag, pTokenFlag, pTokenFlag_q, pAllVldBgnFlag : std_logic;
begin
pAllVld <= pMeVld and pOtherChVld(0) and pOtherChVld(1);
pDataInBnd <= pDataFIFO; -- raw data with skew removed
pMeRdy <= pMeRdy_int; -- data is de-skewed and valid
-- The process below should result in a dual-port distributed RAM with registered output
FIFO: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pAllVld = '1') then -- begin writing in FIFO as soon as all the channels have valid data
pFIFO(pWrA) <= pDataInRaw;
end if;
pDataFIFO <= pFIFO(pRdA); -- register FIFO output
end if;
end process FIFO;
-- FIFO address counters
FIFO_WrA: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pAllVld = '1') then
pWrA <= pWrA + 1;
else -- when invalid data, go back to the beginning
pWrA <= 0;
end if;
end if;
end process FIFO_WrA;
FIFO_RdA: process (PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pAllVld = '0') then
pRdA <= 0;
elsif (pRdEn = '1') then
pRdA <= pRdA + 1;
end if;
end if;
end process FIFO_RdA;
DataValidFlag: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
pAllVld_q <= pAllVld;
pAllVldBgnFlag <= not pAllVld_q and pAllVld; -- this flag used below delays enabling read, thus making sure data is written first before being read
end if;
end process DataValidFlag;
-------------------------------------------------------------------------------
-- Channel bonding is done here:
-- 1 When all the channels have valid data (ie. alignment lock), FIFO is flow-through
-- 2 When marker is found on this channel, FIFO read is paused, thus holding data
-- 3 When all channels report the marker, FIFO read begins again, thus syncing markers
-------------------------------------------------------------------------------
FIFO_RdEn: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pAllVld = '0') then
pRdEn <= '0';
elsif (pAllVldBgnFlag = '1' or (pMeRdy_int = '1' and pOtherChRdy = "11")) then
pRdEn <= '1';
elsif (pBlnkBgnFlag = '1' and not (pMeRdy_int = '1' and pOtherChRdy = "11")) then
pRdEn <= '0';
end if;
end if;
end process FIFO_RdEn;
-- Detect blanking period begin
TokenDetect: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pRdEn = '0' or pDataFIFO = kCtlTkn0 or pDataFIFO = kCtlTkn1 or pDataFIFO = kCtlTkn2 or pDataFIFO = kCtlTkn3) then
pTokenFlag <= '1'; --token flag activates on invalid data, which avoids a BlnkBgn pulse if the valid signal goes up in the middle of a blanking period
else
pTokenFlag <= '0';
end if;
pTokenFlag_q <= pTokenFlag;
pBlnkBgnFlag <= not pTokenFlag_q and pTokenFlag;
end if;
end process TokenDetect;
-- Ready signal when marker is received
IAmReady: process(PixelClk)
begin
if Rising_Edge(PixelClk) then
if (pAllVld = '0') then -- if not all channels are valid, we are not ready either
pMeRdy_int <= '0';
elsif (pBlnkBgnFlag = '1') then
pMeRdy_int <= '1';
end if;
end if;
end process IAmReady;
end Behavioral;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
library work;
use work.gencores_pkg.all;
entity top_module is
port(
clk_i : in std_logic;
locked_i : in std_logic;
blink_o : out std_logic_vector(7 downto 0)
);
end top_module;
architecture rtl of top_module is
-- Constant declaration
constant c_blink_num_pins : natural := 8;
constant c_counter_width : natural := 4;
-- Global clock and reset signals
--signal s_locked : std_logic;
signal clk_sys_rstn : std_logic;
-- Only one clock domain
signal reset_clks : std_logic_vector(0 downto 0);
signal reset_rstn : std_logic_vector(0 downto 0);
-- Global Clock Single ended
signal clk_sys : std_logic;
-- Counter signal
signal s_counter : unsigned(c_counter_width-1 downto 0);
constant s_counter_full : integer := 4;
signal s_blink : std_logic_vector(c_blink_num_pins-1 downto 0);
begin
-- Reset synchronization
cmp_reset : gc_reset
generic map(
g_logdelay => 1,
g_syncdepth => 2
)
port map(
free_clk_i => clk_sys,
locked_i => locked_i,
clks_i => reset_clks,
rstn_o => reset_rstn
);
-- Simulation only
clk_sys <= clk_i;
-- End of simulation only!
reset_clks(0) <= clk_sys;
clk_sys_rstn <= reset_rstn(0);
p_counter : process (clk_sys)
begin
if rising_edge(clk_sys) then
if clk_sys_rstn = '0' then
s_counter <= (others => '0');
s_blink <= x"01";
else
if (s_counter = s_counter_full-1) then
s_counter <= (others => '0');
s_blink <= s_blink(c_blink_num_pins-2 downto 0) & s_blink(c_blink_num_pins-1);
else
s_counter <= s_counter + 1;
end if;
end if;
end if;
end process;
blink_o <= s_blink;
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity faultify_simulator is
generic (
numInj : integer := 56;
numIn : integer := 10;
numOut : integer := 10);
port (
clk : in std_logic;
clk_m : in std_logic;
circ_ce : in std_logic;
circ_rst : in std_logic;
test : out std_logic_vector(31 downto 0);
testvector : in std_logic_vector(numIn-1 downto 0);
resultvector_o : out std_logic_vector(numOut-1 downto 0);
resultvector_f : out std_logic_vector(numOut-1 downto 0);
seed_in_en : in std_logic;
seed_in : in std_logic;
prob_in_en : in std_logic;
prob_in : in std_logic;
shift_en : in std_logic;
rst_n : in std_logic);
end faultify_simulator;
-- 866:0
architecture behav of faultify_simulator is
component faultify_binomial_gen
generic (
width : integer);
port (
clk : in std_logic;
rst_n : in std_logic;
seed_in_en : in std_logic;
seed_in : in std_logic;
seed_out_c : out std_logic;
prob_in_en : in std_logic;
prob_in : in std_logic;
prob_out_c : out std_logic;
shift_en : in std_logic;
data_out : out std_logic;
data_out_valid : out std_logic);
end component;
component circuit_under_test
port (
clk : in std_logic;
rst : in std_logic;
testvector : in std_logic_vector(numIn-1 downto 0);
resultvector : out std_logic_vector(numOut-1 downto 0);
injectionvector : in std_logic_vector(578-1 downto 0));
end component;
component golden_circuit
port (
clk : in std_logic;
rst : in std_logic;
testvector : in std_logic_vector(numIn-1 downto 0);
resultvector : out std_logic_vector(numOut-1 downto 0));
end component;
signal injectionvector : std_logic_vector(numInj-1 downto 0);
signal injectionvector_reg : std_logic_vector(numInj-1 downto 0);
signal injectionvector_reg_o : std_logic_vector(numInj-1 downto 0);
signal seed_chain : std_logic_vector(numInj downto 0);
signal prob_chain : std_logic_vector(numInj downto 0);
signal rst : std_logic;
signal clk_ce_m : std_logic;
signal testvector_reg : std_logic_vector(numIn-1 downto 0);
attribute syn_noprune : boolean;
attribute syn_noprune of circuit_under_test_inst : label is true;
attribute syn_noprune of golden_circuit_inst : label is true;
attribute xc_props : string;
attribute xc_props of circuit_under_test_inst : label is "KEEP_HIERARCHY=TRUE";
attribute xc_props of golden_circuit_inst : label is "KEEP_HIERARCHY=TRUE";
signal injectionvector_reg_cat : std_logic_vector(578-1 downto 0);
begin -- behav
rst <= not rst_n;
-----------------------------------------------------------------------------
-- debug...
-----------------------------------------------------------------------------
-- resultvector_f <= (others => '1');
-- resultvector_o <= (others => '1');
cgate : bufgce
port map (
I => clk_m,
O => clk_ce_m,
CE => '1');
process (clk_ce_m, rst_n)
begin -- process
if rst_n = '0' then -- asynchronous reset (active low)
testvector_reg <= (others => '0');
elsif clk_ce_m'event and clk_ce_m = '1' then -- rising clock edge
testvector_reg <= testvector;
end if;
end process;
circuit_under_test_inst : circuit_under_test
port map (
clk => clk_ce_m,
rst => circ_rst,
testvector => testvector_reg,
resultvector => resultvector_f,
injectionvector => injectionvector_reg_cat);
injectionvector_reg_cat(199 downto 0) <= (others => '0');
injectionvector_reg_cat(399 downto 200) <= (others => '0');
injectionvector_reg_cat(578-1 downto 400) <= injectionvector_reg;
golden_circuit_inst : golden_circuit
port map (
clk => clk_ce_m,
rst => circ_rst,
testvector => testvector_reg,
resultvector => resultvector_o
);
seed_chain(0) <= seed_in;
prob_chain(0) <= prob_in;
prsn_loop : for i in 0 to numInj-1 generate
prsn_top_1 : faultify_binomial_gen
generic map (
width => 32)
port map (
clk => clk,
rst_n => rst_n,
seed_in_en => seed_in_en,
seed_in => seed_chain(i),
seed_out_c => seed_chain(i+1),
prob_in_en => prob_in_en,
prob_in => prob_chain(i),
prob_out_c => prob_chain(i+1),
shift_en => shift_en,
data_out => injectionvector(i),
data_out_valid => open);
end generate prsn_loop;
reg : process (clk_ce_m, rst_n)
begin -- process reg
if rst_n = '0' then -- asynchronous reset (active low)
injectionvector_reg <= (others => '0');
--injectionvector_reg_o <= (others => '0');
--test <= (others => '0');
elsif clk_ce_m'event and clk_ce_m = '1' then -- rising clock edge
injectionvector_reg <= injectionvector;
--injectionvector_reg <= (others => '0');
--test <= injectionvector_reg_o(31 downto 0);
--injectionvector_reg_o(31 downto 0) <= injectionvector_reg_o(31 downto 0) or (resultvector_f(31 downto 0) xor resultvector_o(31 downto 0));
end if;
end process reg;
end behav;
|
-- SIMON 64/128
-- key scheduling function
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
-- Parameters:
-- r: round index
-- k_0..k_3: key
-- subkey_out: round subkey
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity key_schedule is
port (
r : in std_logic_vector(7 downto 0);
-- we don't need k_2 here because of the way we schedule k(r) in the simon component
k_0 : in std_logic_vector(31 downto 0);
k_1 : in std_logic_vector(31 downto 0);
k_3 : in std_logic_vector(31 downto 0);
subkey_out : out std_logic_vector(31 downto 0));
end key_schedule;
architecture Behavioral of key_schedule is
signal op_3_s : std_logic_vector(31 downto 0);
signal op_xor_0 : std_logic_vector(31 downto 0);
signal op_1_s : std_logic_vector(31 downto 0);
signal seqC : std_logic_vector(31 downto 0);
signal sequence : std_logic_vector(61 downto 0);
begin
-- C ^ sequence[(r-4) % 62]
sequence <= "11110000101100111001010001001000000111101001100011010111011011"; -- z3
-- 0xFFFFFFFFFFFFFFFC xor sequence[(r-4) % 62]
-- TODO: 1-bit latch for seqC(0) is used, not recommended...
seqC <= ("1111111111111111111111111111110" & sequence((to_integer(unsigned(r)) - 4) mod 62)) when (to_integer(unsigned(r)) > 3) else ("11111111111111111111111111111100");
-- tmp = K[3] >> 3
op_3_s <= std_logic_vector(rotate_right(unsigned(k_3), 3));
-- tmp = tmp xor k[1]
op_xor_0 <= (op_3_s xor k_1);
-- tmp >> 1
op_1_s <= std_logic_vector(rotate_right(unsigned(op_xor_0), 1));
-- Original NSA specification lists ~K[0] ^ 3 but this can be rewritten to K[0] ^ ((1 << word_size)-4) where the latter can be stored as a constant for speed
subkey_out <= k_0 when (to_integer(unsigned(r)) < 4) else (op_1_s xor op_xor_0 xor k_0 xor seqC);
end Behavioral; |
entity test is
type test1 is (foo);
subtype test2 is test1.test1;
begin end;
|
-- $Id: iob_reg_i.vhd 314 2010-07-09 17:38:41Z mueller $
--
-- Copyright 2007- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: iob_reg_i - syn
-- Description: Registered IOB, input only
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan, Virtex
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2007-12-16 101 1.0.1 add INIT generic port
-- 2007-12-08 100 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.xlib.all;
entity iob_reg_i is -- registered IOB, input
generic (
INIT : slbit := '0'); -- initial state
port (
CLK : in slbit; -- clock
CE : in slbit := '1'; -- clock enable
DI : out slbit; -- input data
PAD : in slbit -- i/o pad
);
end iob_reg_i;
architecture syn of iob_reg_i is
begin
IOB : iob_reg_i_gen
generic map (
DWIDTH => 1,
INIT => INIT)
port map (
CLK => CLK,
CE => CE,
DI(0) => DI,
PAD(0) => PAD
);
end syn;
|
-- $Id: iob_reg_i.vhd 314 2010-07-09 17:38:41Z mueller $
--
-- Copyright 2007- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: iob_reg_i - syn
-- Description: Registered IOB, input only
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan, Virtex
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2007-12-16 101 1.0.1 add INIT generic port
-- 2007-12-08 100 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
use work.xlib.all;
entity iob_reg_i is -- registered IOB, input
generic (
INIT : slbit := '0'); -- initial state
port (
CLK : in slbit; -- clock
CE : in slbit := '1'; -- clock enable
DI : out slbit; -- input data
PAD : in slbit -- i/o pad
);
end iob_reg_i;
architecture syn of iob_reg_i is
begin
IOB : iob_reg_i_gen
generic map (
DWIDTH => 1,
INIT => INIT)
port map (
CLK => CLK,
CE => CE,
DI(0) => DI,
PAD(0) => PAD
);
end syn;
|
-------------------------------------------------------------------------------
--
-- Title : openMAC_16to32conv
-- Design : POWERLINK
--
-------------------------------------------------------------------------------
--
-- File : openMAC_16to32conv.vhd
-- Generated : Mon Sep 12 15:35:37 2011
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2011
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This is a 32-to-16 bit converter which is necessary for e.g. Xilinx PLB.
-- The component has to be connected to openMAC_Ethernet or powerlink.
-- NOT use this directly with openMAC!
--
-------------------------------------------------------------------------------
-- 2011-09-12 V0.01 zelenkaj Initial creation
-- 2011-10-10 V0.02 zelenkaj Split bus ack into wr/rd and bug fix
-- 2012-03-21 V0.03 zelenkaj Added endian generic
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
entity openMAC_16to32conv is
generic(
gEndian : string := "little";
bus_address_width : integer := 10
);
port(
clk : in std_logic;
rst : in std_logic;
--port from 32bit bus
bus_select : in std_logic;
bus_write : in std_logic;
bus_read : in std_logic;
bus_byteenable : in std_logic_vector(3 downto 0);
bus_writedata : in std_logic_vector(31 downto 0);
bus_readdata : out std_logic_vector(31 downto 0);
bus_address : in std_logic_vector(bus_address_width-1 downto 0);
bus_ack_wr : out std_logic;
bus_ack_rd : out std_logic;
--port to openMAC_Ethernet
s_chipselect : out std_logic;
s_write : out std_logic;
s_read : out std_logic;
s_address : out std_logic_vector(bus_address_width-1 downto 0);
s_byteenable : out std_logic_vector(1 downto 0);
s_waitrequest : in std_logic;
s_readdata : in std_logic_vector(15 downto 0);
s_writedata : out std_logic_vector(15 downto 0)
);
end openMAC_16to32conv;
architecture rtl of openMAC_16to32conv is
-- types
type fsm_t is (idle, doAccess);
type bus_access_t is (none, dword, word);
-- fsm
signal fsm, fsm_next : fsm_t;
signal bus_access : bus_access_t;
-- cnt
signal cnt, cnt_next, cnt_load_val : std_logic_vector(1 downto 0);
signal cnt_load, cnt_dec, cnt_zero : std_logic;
signal bus_ack : std_logic;
-- word register
signal word_reg, word_reg_next : std_logic_vector(15 downto 0);
begin
process(clk, rst)
begin
if rst = '1' then
cnt <= (others => '0');
fsm <= idle;
word_reg <= (others => '0');
elsif clk = '1' and clk'event then
cnt <= cnt_next;
fsm <= fsm_next;
word_reg <= word_reg_next;
end if;
end process;
word_reg_next <= s_readdata when bus_access = dword and cnt = 2 and s_waitrequest = '0' else
word_reg;
s_chipselect <= bus_select; --not cnt_zero;
s_write <= bus_write and bus_select;
s_read <= bus_read and bus_select;
cnt_dec <= (not s_waitrequest) and bus_select;
bus_readdata <= s_readdata & word_reg when bus_access = dword else
s_readdata & s_readdata;
bus_ack <= '1' when cnt = 1 and s_waitrequest = '0' and bus_access = dword else
'1' when s_waitrequest = '0' and bus_access = word else
'0';
bus_ack_wr <= bus_ack and bus_write;
bus_ack_rd <= bus_ack and bus_read;
s_address(bus_address_width-1 downto 1) <= '0' & bus_address(bus_address_width-1 downto 2);
--word address set to +0 (little) when first dword access or word access with selected word/byte
s_address(0) <= '0' when bus_access = dword and (cnt = 2 or cnt = 0) and gEndian = "little" else --first word of dword access
'1' when bus_access = dword and cnt = 1 and gEndian = "little" else
'1' when bus_access = dword and (cnt = 2 or cnt = 0) and gEndian = "big" else
'0' when bus_access = dword and cnt = 1 and gEndian = "big" else --first word of dword access
bus_address(1);
s_byteenable <= "11" when bus_access = dword else
bus_byteenable(3 downto 2) or bus_byteenable(1 downto 0);
s_writedata <= bus_writedata(15 downto 0) when bus_access = dword and (cnt = 2 or cnt = 0) else
bus_writedata(31 downto 16) when bus_access = dword and cnt = 1 else
bus_writedata(15 downto 0) when bus_address(1) = '0' else
bus_writedata(31 downto 16); --when bus_address(1) = '1' else
--fsm
bus_access <= none when bus_select /= '1' else
dword when bus_byteenable = "1111" else
word;
fsm_next <= doAccess when fsm = idle and cnt_zero = '1' and bus_access = dword else
idle when fsm = doAccess and cnt_zero = '1' and bus_access = none else
fsm;
--if dword, access twice, otherwise (byte, word) access once
cnt_load_val <= "10" when bus_byteenable = "1111" and bus_read = '1' else "01";
cnt_load <= '1' when fsm_next = doAccess and fsm = idle else '0';
--counter
cnt_next <= cnt_load_val when cnt_load = '1' else
cnt - 1 when cnt_dec = '1' and bus_access = dword else
cnt;
cnt_zero <= '1' when cnt = 0 else '0';
end rtl;
|
-------------------------------------------------------------------------------
--
-- Title : openMAC_16to32conv
-- Design : POWERLINK
--
-------------------------------------------------------------------------------
--
-- File : openMAC_16to32conv.vhd
-- Generated : Mon Sep 12 15:35:37 2011
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2011
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This is a 32-to-16 bit converter which is necessary for e.g. Xilinx PLB.
-- The component has to be connected to openMAC_Ethernet or powerlink.
-- NOT use this directly with openMAC!
--
-------------------------------------------------------------------------------
-- 2011-09-12 V0.01 zelenkaj Initial creation
-- 2011-10-10 V0.02 zelenkaj Split bus ack into wr/rd and bug fix
-- 2012-03-21 V0.03 zelenkaj Added endian generic
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
entity openMAC_16to32conv is
generic(
gEndian : string := "little";
bus_address_width : integer := 10
);
port(
clk : in std_logic;
rst : in std_logic;
--port from 32bit bus
bus_select : in std_logic;
bus_write : in std_logic;
bus_read : in std_logic;
bus_byteenable : in std_logic_vector(3 downto 0);
bus_writedata : in std_logic_vector(31 downto 0);
bus_readdata : out std_logic_vector(31 downto 0);
bus_address : in std_logic_vector(bus_address_width-1 downto 0);
bus_ack_wr : out std_logic;
bus_ack_rd : out std_logic;
--port to openMAC_Ethernet
s_chipselect : out std_logic;
s_write : out std_logic;
s_read : out std_logic;
s_address : out std_logic_vector(bus_address_width-1 downto 0);
s_byteenable : out std_logic_vector(1 downto 0);
s_waitrequest : in std_logic;
s_readdata : in std_logic_vector(15 downto 0);
s_writedata : out std_logic_vector(15 downto 0)
);
end openMAC_16to32conv;
architecture rtl of openMAC_16to32conv is
-- types
type fsm_t is (idle, doAccess);
type bus_access_t is (none, dword, word);
-- fsm
signal fsm, fsm_next : fsm_t;
signal bus_access : bus_access_t;
-- cnt
signal cnt, cnt_next, cnt_load_val : std_logic_vector(1 downto 0);
signal cnt_load, cnt_dec, cnt_zero : std_logic;
signal bus_ack : std_logic;
-- word register
signal word_reg, word_reg_next : std_logic_vector(15 downto 0);
begin
process(clk, rst)
begin
if rst = '1' then
cnt <= (others => '0');
fsm <= idle;
word_reg <= (others => '0');
elsif clk = '1' and clk'event then
cnt <= cnt_next;
fsm <= fsm_next;
word_reg <= word_reg_next;
end if;
end process;
word_reg_next <= s_readdata when bus_access = dword and cnt = 2 and s_waitrequest = '0' else
word_reg;
s_chipselect <= bus_select; --not cnt_zero;
s_write <= bus_write and bus_select;
s_read <= bus_read and bus_select;
cnt_dec <= (not s_waitrequest) and bus_select;
bus_readdata <= s_readdata & word_reg when bus_access = dword else
s_readdata & s_readdata;
bus_ack <= '1' when cnt = 1 and s_waitrequest = '0' and bus_access = dword else
'1' when s_waitrequest = '0' and bus_access = word else
'0';
bus_ack_wr <= bus_ack and bus_write;
bus_ack_rd <= bus_ack and bus_read;
s_address(bus_address_width-1 downto 1) <= '0' & bus_address(bus_address_width-1 downto 2);
--word address set to +0 (little) when first dword access or word access with selected word/byte
s_address(0) <= '0' when bus_access = dword and (cnt = 2 or cnt = 0) and gEndian = "little" else --first word of dword access
'1' when bus_access = dword and cnt = 1 and gEndian = "little" else
'1' when bus_access = dword and (cnt = 2 or cnt = 0) and gEndian = "big" else
'0' when bus_access = dword and cnt = 1 and gEndian = "big" else --first word of dword access
bus_address(1);
s_byteenable <= "11" when bus_access = dword else
bus_byteenable(3 downto 2) or bus_byteenable(1 downto 0);
s_writedata <= bus_writedata(15 downto 0) when bus_access = dword and (cnt = 2 or cnt = 0) else
bus_writedata(31 downto 16) when bus_access = dword and cnt = 1 else
bus_writedata(15 downto 0) when bus_address(1) = '0' else
bus_writedata(31 downto 16); --when bus_address(1) = '1' else
--fsm
bus_access <= none when bus_select /= '1' else
dword when bus_byteenable = "1111" else
word;
fsm_next <= doAccess when fsm = idle and cnt_zero = '1' and bus_access = dword else
idle when fsm = doAccess and cnt_zero = '1' and bus_access = none else
fsm;
--if dword, access twice, otherwise (byte, word) access once
cnt_load_val <= "10" when bus_byteenable = "1111" and bus_read = '1' else "01";
cnt_load <= '1' when fsm_next = doAccess and fsm = idle else '0';
--counter
cnt_next <= cnt_load_val when cnt_load = '1' else
cnt - 1 when cnt_dec = '1' and bus_access = dword else
cnt;
cnt_zero <= '1' when cnt = 0 else '0';
end rtl;
|
-------------------------------------------------------------------------------
--
-- Title : openMAC_16to32conv
-- Design : POWERLINK
--
-------------------------------------------------------------------------------
--
-- File : openMAC_16to32conv.vhd
-- Generated : Mon Sep 12 15:35:37 2011
-- From : interface description file
-- By : Itf2Vhdl ver. 1.22
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2011
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This is a 32-to-16 bit converter which is necessary for e.g. Xilinx PLB.
-- The component has to be connected to openMAC_Ethernet or powerlink.
-- NOT use this directly with openMAC!
--
-------------------------------------------------------------------------------
-- 2011-09-12 V0.01 zelenkaj Initial creation
-- 2011-10-10 V0.02 zelenkaj Split bus ack into wr/rd and bug fix
-- 2012-03-21 V0.03 zelenkaj Added endian generic
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
entity openMAC_16to32conv is
generic(
gEndian : string := "little";
bus_address_width : integer := 10
);
port(
clk : in std_logic;
rst : in std_logic;
--port from 32bit bus
bus_select : in std_logic;
bus_write : in std_logic;
bus_read : in std_logic;
bus_byteenable : in std_logic_vector(3 downto 0);
bus_writedata : in std_logic_vector(31 downto 0);
bus_readdata : out std_logic_vector(31 downto 0);
bus_address : in std_logic_vector(bus_address_width-1 downto 0);
bus_ack_wr : out std_logic;
bus_ack_rd : out std_logic;
--port to openMAC_Ethernet
s_chipselect : out std_logic;
s_write : out std_logic;
s_read : out std_logic;
s_address : out std_logic_vector(bus_address_width-1 downto 0);
s_byteenable : out std_logic_vector(1 downto 0);
s_waitrequest : in std_logic;
s_readdata : in std_logic_vector(15 downto 0);
s_writedata : out std_logic_vector(15 downto 0)
);
end openMAC_16to32conv;
architecture rtl of openMAC_16to32conv is
-- types
type fsm_t is (idle, doAccess);
type bus_access_t is (none, dword, word);
-- fsm
signal fsm, fsm_next : fsm_t;
signal bus_access : bus_access_t;
-- cnt
signal cnt, cnt_next, cnt_load_val : std_logic_vector(1 downto 0);
signal cnt_load, cnt_dec, cnt_zero : std_logic;
signal bus_ack : std_logic;
-- word register
signal word_reg, word_reg_next : std_logic_vector(15 downto 0);
begin
process(clk, rst)
begin
if rst = '1' then
cnt <= (others => '0');
fsm <= idle;
word_reg <= (others => '0');
elsif clk = '1' and clk'event then
cnt <= cnt_next;
fsm <= fsm_next;
word_reg <= word_reg_next;
end if;
end process;
word_reg_next <= s_readdata when bus_access = dword and cnt = 2 and s_waitrequest = '0' else
word_reg;
s_chipselect <= bus_select; --not cnt_zero;
s_write <= bus_write and bus_select;
s_read <= bus_read and bus_select;
cnt_dec <= (not s_waitrequest) and bus_select;
bus_readdata <= s_readdata & word_reg when bus_access = dword else
s_readdata & s_readdata;
bus_ack <= '1' when cnt = 1 and s_waitrequest = '0' and bus_access = dword else
'1' when s_waitrequest = '0' and bus_access = word else
'0';
bus_ack_wr <= bus_ack and bus_write;
bus_ack_rd <= bus_ack and bus_read;
s_address(bus_address_width-1 downto 1) <= '0' & bus_address(bus_address_width-1 downto 2);
--word address set to +0 (little) when first dword access or word access with selected word/byte
s_address(0) <= '0' when bus_access = dword and (cnt = 2 or cnt = 0) and gEndian = "little" else --first word of dword access
'1' when bus_access = dword and cnt = 1 and gEndian = "little" else
'1' when bus_access = dword and (cnt = 2 or cnt = 0) and gEndian = "big" else
'0' when bus_access = dword and cnt = 1 and gEndian = "big" else --first word of dword access
bus_address(1);
s_byteenable <= "11" when bus_access = dword else
bus_byteenable(3 downto 2) or bus_byteenable(1 downto 0);
s_writedata <= bus_writedata(15 downto 0) when bus_access = dword and (cnt = 2 or cnt = 0) else
bus_writedata(31 downto 16) when bus_access = dword and cnt = 1 else
bus_writedata(15 downto 0) when bus_address(1) = '0' else
bus_writedata(31 downto 16); --when bus_address(1) = '1' else
--fsm
bus_access <= none when bus_select /= '1' else
dword when bus_byteenable = "1111" else
word;
fsm_next <= doAccess when fsm = idle and cnt_zero = '1' and bus_access = dword else
idle when fsm = doAccess and cnt_zero = '1' and bus_access = none else
fsm;
--if dword, access twice, otherwise (byte, word) access once
cnt_load_val <= "10" when bus_byteenable = "1111" and bus_read = '1' else "01";
cnt_load <= '1' when fsm_next = doAccess and fsm = idle else '0';
--counter
cnt_next <= cnt_load_val when cnt_load = '1' else
cnt - 1 when cnt_dec = '1' and bus_access = dword else
cnt;
cnt_zero <= '1' when cnt = 0 else '0';
end rtl;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2013 Fredrik Ringhage, Aeroflex Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.i2c.all;
use gaisler.spi.all;
use gaisler.misc.all;
use gaisler.jtag.all;
use gaisler.spacewire.all;
use gaisler.net.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3core is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
scantest : integer := CFG_SCAN
);
port (
resetn : in std_ulogic;
clksel : in std_logic_vector(1 downto 0);
clk : in std_ulogic;
clkapb : in std_ulogic;
clklock : in std_ulogic;
errorn : out std_ulogic;
address : out std_logic_vector(27 downto 0);
datain : in std_logic_vector(31 downto 0);
dataout : out std_logic_vector(31 downto 0);
dataen : out std_logic_vector(31 downto 0);
cbin : in std_logic_vector(7 downto 0);
cbout : out std_logic_vector(7 downto 0);
cben : out std_logic_vector(7 downto 0);
sdcsn : out std_logic_vector (1 downto 0); -- sdram chip select
sdwen : out std_ulogic; -- sdram write enable
sdrasn : out std_ulogic; -- sdram ras
sdcasn : out std_ulogic; -- sdram cas
sddqm : out std_logic_vector (3 downto 0); -- sdram dqm
dsutx : out std_ulogic; -- DSU tx data
dsurx : in std_ulogic; -- DSU rx data
dsuen : in std_ulogic;
dsubre : in std_ulogic;
dsuact : out std_ulogic;
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
txd2 : out std_ulogic; -- UART2 tx data
rxd2 : in std_ulogic; -- UART2 rx data
ramsn : out std_logic_vector (4 downto 0);
ramoen : out std_logic_vector (4 downto 0);
rwen : out std_logic_vector (3 downto 0);
oen : out std_ulogic;
writen : out std_ulogic;
read : out std_ulogic;
iosn : out std_ulogic;
romsn : out std_logic_vector (1 downto 0);
brdyn : in std_ulogic;
bexcn : in std_ulogic;
wdogn : out std_ulogic;
gpioin : in std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
gpioout : out std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
gpioen : out std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0); -- I/O port
i2c_sclout : out std_ulogic;
i2c_sclen : out std_ulogic;
i2c_sclin : in std_ulogic;
i2c_sdaout : out std_ulogic;
i2c_sdaen : out std_ulogic;
i2c_sdain : in std_ulogic;
spi_miso : in std_ulogic;
spi_mosi : out std_ulogic;
spi_sck : out std_ulogic;
spi_slvsel : out std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
prom32 : in std_ulogic;
spw_clksel : in std_logic_vector(1 downto 0);
spw_clk : in std_ulogic;
spw_rxd : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_rxs : in std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txd : out std_logic_vector(0 to CFG_SPW_NUM-1);
spw_txs : out std_logic_vector(0 to CFG_SPW_NUM-1);
gtx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(7 downto 0);
erx_dv : in std_ulogic;
etx_clk : in std_ulogic;
etxd : out std_logic_vector(7 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
emdint : in std_ulogic;
emdioin : in std_logic;
emdioout : out std_logic;
emdioen : out std_logic;
emdc : out std_ulogic;
trst : in std_ulogic;
tck : in std_ulogic;
tms : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
tdoen : out std_ulogic;
scanen : in std_ulogic;
testen : in std_ulogic;
testrst : in std_ulogic;
testoen : in std_ulogic;
chain_tck : out std_ulogic;
chain_tckn : out std_ulogic;
chain_tdi : out std_ulogic;
chain_tdo : in std_ulogic;
bsshft : out std_ulogic;
bscapt : out std_ulogic;
bsupdi : out std_ulogic;
bsupdo : out std_ulogic;
bsdrive : out std_ulogic;
bshighz : out std_ulogic
);
end;
architecture rtl of leon3core is
--constant is_asic : integer := 1 - is_fpga(fabtech);
--constant blength : integer := 12;
--constant CFG_NCLKS : integer := 7;
constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH;
constant maxahbm : integer := (CFG_SPW_NUM*CFG_SPW_EN) + maxahbmsp;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdram_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal rstn, rstraw : std_ulogic;
signal rstapbn, rstapbraw : std_ulogic;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal gpioi, gpioi2 : gpio_in_type;
signal gpioo, gpioo2 : gpio_out_type;
signal i2ci : i2c_in_type;
signal i2co : i2c_out_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal ethi : eth_in_type;
signal etho : eth_out_type;
-- signal tck, tms, tdi, tdo : std_ulogic;
signal jtck, jtckn, jtdi, jrst, jtdo, jcapt, jshft, jupd, jiupd: std_ulogic;
signal jninst: std_logic_vector(7 downto 0);
signal spwi : grspw_in_type_vector(0 to CFG_SPW_NUM-1);
signal spwo : grspw_out_type_vector(0 to CFG_SPW_NUM-1);
signal spw_rxclk : std_logic_vector(CFG_SPW_NUM*2-1 downto 0);
signal dtmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal stmp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal stati : ahbstat_in_type;
-- SPW Clock Gating signals
signal enphy : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal spwrstn : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal gspwclk : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal rxclko : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal lspwclkn : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal spwclkn : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal rxclkphyo : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal disclk : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal disrxclk0 : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal disrxclk1 : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal distxclk : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal distxclkn : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal gclk : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal grxclk0 : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal grxclk1 : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal gtxclk : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal gtxclkn : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal grst : std_logic_vector(CFG_SPW_NUM-1 downto 0);
signal crst : std_logic_vector(CFG_SPW_NUM-1 downto 0);
constant IOAEN : integer := 0;
constant CFG_SDEN : integer := CFG_MCTRL_LEON2;
constant CFG_INVCLK : integer := CFG_MCTRL_INVCLK;
constant BOARD_FREQ : integer := 50000; -- Board frequency in KHz
constant sysfreq : integer := (CFG_CLKMUL/CFG_CLKDIV)*40000;
constant OEPOL : integer := padoen_polarity(padtech);
constant CPU_FREQ : integer := 100000;
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
wpo.wprothit <= '0'; -- no write protection
rstgen0 : rstgen -- reset generator
generic map (syncrst => CFG_NOASYNC, scanen => scantest, syncin => 1)
port map (resetn, clk, clklock, rstn, rstraw, testrst);
rstgen1 : rstgen -- reset generator
generic map (syncrst => CFG_NOASYNC, scanen => scantest, syncin => 1)
port map (resetn, clkapb, clklock, rstapbn, rstapbraw, testrst);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahbctrl0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clk, ahbmi, ahbmo, ahbsi, ahbso,
testen, testrst, scanen, testoen);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
cpu : for i in 0 to CFG_NCPU-1 generate
leon3s0 : leon3cg -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clk, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i), clk);
end generate;
errorn <= dbgo(0).error when OEPOL = 0 else not dbgo(0).error;
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clk, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= dsuen; dsui.break <= dsubre; dsuact <= dsuo.active;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
ahbuart0: ahbuart -- Debug UART
generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
port map (rstn, clk, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
dui.rxd <= dsurx; dsutx <= duo.txd;
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, part => JTAG_EXAMPLE_PART,
hindex => CFG_NCPU+CFG_AHB_UART, scantest => scantest, oepol => OEPOL)
port map(rstn, clk, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
jtck, jtdi, open, jrst, jcapt, jshft, jupd, jtdo, trst, tdoen, '0', jtckn, jninst, jiupd);
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
address <= memo.address(27 downto 0);
ramsn <= memo.ramsn(4 downto 0); romsn <= memo.romsn(1 downto 0);
oen <= memo.oen; rwen <= memo.wrn; ramoen <= memo.ramoen(4 downto 0);
writen <= memo.writen; read <= memo.read; iosn <= memo.iosn;
dataout <= memo.data(31 downto 0); dataen <= memo.vbdrive(31 downto 0);
memi.data(31 downto 0) <= datain;
sdwen <= sdo.sdwen; sdrasn <= sdo.rasn; sdcasn <= sdo.casn;
sddqm <= sdo.dqm(3 downto 0); sdcsn <= sdo.sdcsn;
cbout <= memo.cb(7 downto 0); cben <= memo.vcdrive(7 downto 0);
memi.bwidth <= prom32 & '0';
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
mctrl0 : mctrl generic map (hindex => 0, pindex => 0, paddr => 0,
srbanks => 4+CFG_MCTRL_5CS, sden => CFG_MCTRL_SDEN,
ram8 => CFG_MCTRL_RAM8BIT, ram16 => CFG_MCTRL_RAM16BIT,
invclk => CFG_MCTRL_INVCLK, sepbus => CFG_MCTRL_SEPBUS,
sdbits => 32 + 32*CFG_MCTRL_SD64, pageburst => CFG_MCTRL_PAGE,
oepol => OEPOL)
port map (rstn, clk, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
end generate;
nosd0 : if (CFG_SDEN = 0) generate -- no SDRAM controller
sdo.sdcsn <= (others => '1');
end generate;
memi.writen <= '1'; memi.wrn <= "1111";
memi.brdyn <= brdyn; memi.bexcn <= bexcn;
mg0 : if CFG_MCTRL_LEON2 = 0 generate -- None PROM/SRAM controller
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
memo.ramsn <= (others => '1'); memo.romsn <= (others => '1');
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apbctrl0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstapbn, clkapb, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
apbuart0 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstapbn, clkapb, apbi, apbo(1), u1i, u1o);
u1i.ctsn <= '0'; u1i.extclk <= '0';
txd1 <= u1o.txd; u1i.rxd <= rxd1;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
ua2 : if CFG_UART2_ENABLE /= 0 generate
uart2 : apbuart -- UART 2
generic map (pindex => 9, paddr => 9, pirq => 9, fifosize => CFG_UART2_FIFO)
port map (rstapbn, clkapb, apbi, apbo(9), u2i, u2o);
u2i.rxd <= rxd2; u2i.ctsn <= '0'; u2i.extclk <= '0'; txd2 <= u2o.txd;
end generate;
noua1 : if CFG_UART2_ENABLE = 0 generate apbo(9) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clk, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
gptimer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW, wdog => CFG_GPT_WDOGEN*CFG_GPT_WDOG)
port map (rstapbn, clkapb, apbi, apbo(3), gpti, gpto);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
wdogn <= gpto.wdogn when OEPOL = 0 else gpto.wdog;
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
grgpio0: grgpio
generic map( pindex => 6, paddr => 6, imask => CFG_GRGPIO_IMASK,
nbits => CFG_GRGPIO_WIDTH, oepol => OEPOL, syncrst => CFG_NOASYNC)
port map( rstapbn, clkapb, apbi, apbo(6), gpioi, gpioo);
gpioout <= gpioo.dout(CFG_GRGPIO_WIDTH-1 downto 0);
gpioen <= gpioo.oen(CFG_GRGPIO_WIDTH-1 downto 0);
gpioi.din(CFG_GRGPIO_WIDTH-1 downto 0) <= gpioin;
end generate;
nogpio : if CFG_GRGPIO_ENABLE = 0 generate apbo(5) <= apb_none; end generate;
i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master
i2c0 : i2cmst generic map (pindex => 5, paddr => 5, pmask => 16#FFF#, pirq => 13, filter => 9)
port map (rstapbn, clkapb, apbi, apbo(5), i2ci, i2co);
i2c_sclout <= i2co.scl;
i2c_sclen <= i2co.scloen;
i2ci.scl <= i2c_sclin;
i2c_sdaout <= i2co.sda;
i2c_sdaen <= i2co.sdaoen;
i2ci.sda <= i2c_sdain;
end generate i2cm;
noi2cm: if CFG_I2C_ENABLE = 0 generate apbo(5) <= apb_none; end generate;
spic: if CFG_SPICTRL_ENABLE = 1 generate -- SPI controller
spictrl0 : spictrl
generic map(
pindex => 8,
paddr => 8,
pmask => 16#fff#,
pirq => 8,
fdepth => CFG_SPICTRL_FIFO,
slvselen => CFG_SPICTRL_SLVREG,
slvselsz => CFG_SPICTRL_SLVS,
oepol => oepol,
odmode => CFG_SPICTRL_ODMODE,
automode => CFG_SPICTRL_AM,
aslvsel => CFG_SPICTRL_ASEL,
twen => CFG_SPICTRL_TWEN,
maxwlen => CFG_SPICTRL_MAXWLEN,
syncram => CFG_SPICTRL_SYNCRAM,
memtech => memtech,
ft => CFG_SPICTRL_FT,
scantest => scantest)
port map(
rstn => rstapbn,
clk => clkapb,
apbi => apbi,
apbo => apbo(8),
spii => spii,
spio => spio,
slvsel => spi_slvsel);
spii.sck <= '0';
spii.mosi <= '0';
spii.miso <= spi_miso;
spi_mosi <= spio.mosi;
spi_sck <= spio.sck;
spii.astart <= '0'; --unused
spii.spisel <= '1'; --unused (master only)
end generate spic;
nospi: if CFG_SPICTRL_ENABLE = 0 generate apbo(14) <= apb_none; end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
stati.cerror(0) <= memo.ce;
ahbstat0 : ahbstat
generic map (pindex => 15, paddr => 15, pirq => 1, nftslv => CFG_AHBSTATN)
port map (rstn, clk, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
nop2 : if CFG_AHBSTAT = 0 generate apbo(15) <= apb_none; end generate;
-------------------------------------------------------------------------------
-- JTAG Boundary scan
-------------------------------------------------------------------------------
bscangen: if CFG_BOUNDSCAN_EN /= 0 generate
xtapgen: if CFG_AHB_JTAG = 0 generate
t0: tap
generic map (tech => fabtech, irlen => 6, scantest => scantest, oepol => OEPOL)
port map (trst,tck,tms,tdi,tdo,
jtck,jtdi,open,jrst,jcapt,jshft,jupd,open,open,'1',jtdo,'0',jninst,jiupd,jtckn,testen,testrst,testoen,tdoen,'0');
end generate;
bc0: bscanctrl
port map (
trst,jtck,jtckn,jtdi,jninst,jiupd,jrst,jcapt,jshft,jupd,jtdo,
chain_tdi, chain_tdo, bsshft, bscapt, bsupdi, bsupdo, bsdrive, bshighz,
gnd(0), gnd(0), testen, testrst, open, gnd(0));
chain_tck <= jtck;
chain_tckn <= jtckn;
end generate;
nobscangen: if CFG_BOUNDSCAN_EN = 0 generate
chain_tck <= '0';
chain_tckn <= '0';
chain_tdi <= '0';
bsshft <= '0';
bscapt <= '0';
bsupdi <= '0';
bsupdo <= '0';
bsdrive <= '0';
bshighz <= '0';
end generate;
-----------------------------------------------------------------------
--- SPACEWIRE -------------------------------------------------------
-----------------------------------------------------------------------
spw : if CFG_SPW_EN > 0 generate
swloop : for i in 0 to CFG_SPW_NUM-1 generate
spwi(i).clkdiv10 <=
"000" & gpioo.val(10 downto 8) & "11" when spw_clksel(1 downto 0) = "11" else
"0000" & gpioo.val(10 downto 8) & '1' when spw_clksel(1 downto 0) = "10" else
"00000" & gpioo.val(10 downto 8);
spwi(i).timerrstval <=
'0' & gpioo.val(15 downto 11) & "111111" when clksel(1 downto 0) = "11" else
"00" & gpioo.val(15 downto 11) & "11111" when clksel(1 downto 0) = "10" else
"000" & gpioo.val(15 downto 11) & "1111";
spwi(i).dcrstval <=
"00" & gpioo.val(15 downto 11) & "111" when clksel(1 downto 0) = "11" else
"000" & gpioo.val(15 downto 11) & "10" when clksel(1 downto 0) = "10" else
"0000" & gpioo.val(15 downto 11) & '0';
-- GRSPW PHY #1
spw1_input: if CFG_SPW_GRSPW = 1 generate
x : process
begin
assert false
report "ASIC Leon3 Ref design do not support GRSPW #1"
severity failure;
wait;
end process;
end generate spw1_input;
-- GRSPW PHY #2
spw2_input: if CFG_SPW_GRSPW = 2 generate
------------------------------------------------------------------------------
-- SpW Physical layer
------------------------------------------------------------------------------
--phy_loop : for i in 0 to CFG_SPWRTR_SPWPORTS-1 generate
rstphy0 : rstgen
generic map(
acthigh => 0, -- CFG_RSTGEN_ACTHIGH,
syncrst => CFG_NOASYNC, -- CFG_RSTGEN_SYNCRST,
scanen => scantest,
syncin => 1)
port map (
rstin => rstn,
clk => spw_clk,
clklock => clklock,
rstout => spwrstn(i),
rstoutraw => open,
testrst => testrst,
testen => testen);
-- Only add clockgating to tech lib which supports clock gates
clkgatephygen : if (has_clkand(fabtech) = 1) generate
-- Sync clock to clock domain
spwclkreg : process(spw_clk) is
begin
if rising_edge(spw_clk) then
-- Only disable phy when rx and tx is disabled
-- TODO: Add SW register to enable/disable the router
enphy(i) <= '1';
end if;
end process;
-- Disable spw phy clock when port is not used
spw_phy0_enable : clkand
generic map (
tech => fabtech,
ren => 0)
port map (
i => spw_clk,
en => enphy(i),
o => gspwclk(i),
tsten => testen);
-- Select rx clock (Should be removed by optimization if RX and TX clock is same i.e. normal case for ASIC)
spw_rxclk(i) <= spw_clk when (CFG_SPW_RTSAME = 1) else rxclkphyo(i);
end generate;
noclkgategen : if (has_clkand(fabtech) = 0) generate
enphy(i) <= '1';
gspwclk(i) <= spw_clk;
spw_rxclk(i) <= spw_clk when (CFG_SPW_RTSAME = 1) else rxclkphyo(i);
end generate;
notecclkmux : if (has_clkmux(fabtech) = 0) generate
spwclkn(i) <= spw_clk when (testen = '1' and scantest = 1) else not spw_clk;
end generate;
tecclkmux : if (has_clkmux(fabtech) = 1) generate
-- Use SET protected cells
spwclkni0: clkinv generic map (tech => fabtech) port map (spw_clk, lspwclkn(i));
spwclknm0 : clkmux generic map (tech => fabtech) port map (lspwclkn(i),spw_clk,testen,spwclkn(i));
end generate;
spw_phy0 : grspw2_phy
generic map(
scantest => scantest,
tech => fabtech,
input_type => CFG_SPW_INPUT,
rxclkbuftype => 0)
port map(
rstn => spwrstn(i),
rxclki => gspwclk(i),
rxclkin => spwclkn(i),
nrxclki => spwclkn(i),
di => dtmp(i),
si => stmp(i),
do => spwi(i).d(1 downto 0),
dov => spwi(i).dv(1 downto 0),
dconnect => spwi(i).dconnect(1 downto 0),
rxclko => rxclkphyo(i),
testrst => testrst,
testen => testen);
dtmp(i) <= spw_rxd(i); stmp(i) <= spw_rxs(i);
spw_txd(i) <= spwo(i).d(0); spw_txs(i) <= spwo(i).s(0);
spwi(i).nd <= (others => '0'); -- Only used in GRSPW
spwi(i).dv(3 downto 2) <= "00"; -- For second port
--end generate;
end generate spw2_input;
spw1_codec: if CFG_SPW_GRSPW = 1 generate
x : process
begin
assert false
report "ASIC Leon3 Ref design do not support GRSPW #1"
severity failure;
wait;
end process;
end generate spw1_codec;
spw2_codec: if CFG_SPW_GRSPW = 2 generate
rstcodec0 : rstgen
generic map(
acthigh => 0, -- CFG_RSTGEN_ACTHIGH,
syncrst => CFG_NOASYNC, -- CFG_RSTGEN_SYNCRST,
scanen => scantest,
syncin => 1)
port map (
rstin => rstn,
clk => spw_clk,
clklock => clklock,
rstout => crst(i),
rstoutraw => open,
testrst => testrst,
testen => testen);
-- TODO: Fix SW control signals
disclk(i) <= '0';
disrxclk0(i) <= '0';
disrxclk1(i) <= '0';
distxclk(i) <= '0';
distxclkn(i) <= '0';
port0_clkgate : grspw_codec_clockgate
generic map (
tech => fabtech,
scantest => scantest,
ports => CFG_SPW_PORTS,
output_type => CFG_SPW_OUTPUT,
clkgate => 1
)
port map (
rst => crst(i),
clk => spw_clk,
rxclk0 => spw_rxclk(i),
rxclk1 => '0',
txclk => spw_clk,
txclkn => '0',
testen => testen,
testrst => testrst,
disableclk => disclk(i),
disablerxclk0 => disrxclk0(i),
disablerxclk1 => disrxclk1(i),
disabletxclk => distxclk(i),
disabletxclkn => distxclkn(i),
grst => grst(i),
gclk => gclk(i),
grxclk0 => grxclk0(i),
grxclk1 => grxclk1(i),
gtxclk => gtxclk(i),
gtxclkn => gtxclkn(i)
);
grspw0 : grspw2
generic map(
tech => fabtech, -- : integer range 0 to NTECH := inferred;
hindex => maxahbmsp+i, -- : integer range 0 to NAHBMST-1 := 0;
pindex => i+10, -- : integer range 0 to NAPBSLV-1 := 0;
paddr => i+10, -- : integer range 0 to 16#FFF# := 0;
--pmask : integer range 0 to 16#FFF# := 16#FFF#;
pirq => i+10, -- : integer range 0 to NAHBIRQ-1 := 0;
rmap => CFG_SPW_RMAP, -- : integer range 0 to 2 := 0;
rmapcrc => CFG_SPW_RMAPCRC, -- : integer range 0 to 1 := 0;
fifosize1 => CFG_SPW_AHBFIFO, -- : integer range 4 to 32 := 32;
fifosize2 => CFG_SPW_RXFIFO, -- : integer range 16 to 64 := 64;
rxunaligned => CFG_SPW_RXUNAL, -- : integer range 0 to 1 := 0;
rmapbufs => CFG_SPW_RMAPBUF, -- : integer range 2 to 8 := 4;
ft => CFG_SPW_FT, -- : integer range 0 to 2 := 0;
scantest => scantest, -- : integer range 0 to 1 := 0;
ports => CFG_SPW_PORTS, -- : integer range 1 to 2 := 1;
dmachan => CFG_SPW_DMACHAN, -- : integer range 1 to 4 := 1;
memtech => memtech, -- : integer range 0 to NTECH := DEFMEMTECH;
techfifo => has_2pram(memtech), -- : integer range 0 to 1 := 1;
input_type => CFG_SPW_INPUT, -- : integer range 0 to 4 := 0;
output_type => CFG_SPW_OUTPUT, -- : integer range 0 to 2 := 0;
rxtx_sameclk => CFG_SPW_RTSAME, -- : integer range 0 to 1 := 0;
netlist => CFG_SPW_NETLIST -- : integer range 0 to 1 := 0;
)
port map (
rst => grst(i),
clk => gclk(i),
rxclk0 => grxclk0(i),
rxclk1 => grxclk1(i),
txclk => gtxclk(i),
txclkn => gtxclkn(i),
ahbmi => ahbmi,
ahbmo => ahbmo(maxahbmsp+i),
apbi => apbi,
apbo => apbo(i+10),
swni => spwi(i),
swno => spwo(i)
);
end generate spw2_codec;
end generate;
end generate;
nospw : if CFG_SPW_EN = 0 generate
spw_txd <= (others => '0');
spw_txs <= (others => '0');
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm
generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 13, paddr => 13, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 7,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G,
enable_mdint => 1)
port map(rst => rstn, clk => clk, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
apbi => apbi, apbo => apbo(13), ethi => ethi, etho => etho);
ethi.gtx_clk <= gtx_clk;
ethi.rx_clk <= erx_clk;
ethi.rxd(7 downto 0) <= erxd;
ethi.rx_dv <= erx_dv;
ethi.tx_clk <= etx_clk;
etxd <= etho.txd(7 downto 0);
etx_en <= etho.tx_en;
etx_er <= etho.tx_er;
ethi.mdint <= emdint;
ethi.mdio_i <= emdioin;
emdioout <= etho.mdio_o;
emdioen <= etho.mdio_oe;
emdc <= etho.mdc;
ethi.rx_er <= erx_er;
ethi.rx_col <= erx_col;
ethi.rx_crs <= erx_crs;
end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
noam1 : for i in maxahbm to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-- noap0 : for i in 12+(CFG_SPW_NUM*CFG_SPW_EN) to NAPBSLV-1-CFG_AHBSTAT
-- generate apbo(i) <= apb_none; end generate;
noah0 : for i in 9 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 ASIC Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
-- file: pll1.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____21.429______0.000______50.0______418.290____232.343
-- CLK_OUT2____85.716______0.000______50.0______305.832____232.343
-- CLK_OUT3____85.716____-90.000______50.0______305.832____232.343
-- CLK_OUT4_____8.000______0.000______50.0______508.185____232.343
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary__________48.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity pll1 is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic;
CLK_OUT3 : out std_logic;
CLK_OUT4 : out std_logic
);
end pll1;
architecture xilinx of pll1 is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "pll1,clk_wiz_v3_6,{component_name=pll1,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=PLL_BASE,num_out_clk=4,clkin1_period=20.833,clkin2_period=20.833,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout : std_logic;
signal clkfbout_buf : std_logic;
signal clkout0 : std_logic;
signal clkout1 : std_logic;
signal clkout2 : std_logic;
signal clkout3 : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
-- Unused status signals
signal locked_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1_buf : BUFG
port map
(O => clkin1,
I => CLK_IN1);
-- Clocking primitive
--------------------------------------
-- Instantiation of the PLL primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
pll_base_inst : PLL_BASE
generic map
(BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "SYSTEM_SYNCHRONOUS",
DIVCLK_DIVIDE => 2,
CLKFBOUT_MULT => 25,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 28,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 7,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 7,
CLKOUT2_PHASE => -90.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKOUT3_DIVIDE => 75,
CLKOUT3_PHASE => 0.000,
CLKOUT3_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 20.833,
REF_JITTER => 0.010)
port map
-- Output clocks
(CLKFBOUT => clkfbout,
CLKOUT0 => clkout0,
CLKOUT1 => clkout1,
CLKOUT2 => clkout2,
CLKOUT3 => clkout3,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
LOCKED => locked_unused,
RST => '0',
-- Input clock control
CLKFBIN => clkfbout_buf,
CLKIN => clkin1);
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfbout_buf,
I => clkfbout);
clkout1_buf : BUFG
port map
(O => CLK_OUT1,
I => clkout0);
clkout2_buf : BUFG
port map
(O => CLK_OUT2,
I => clkout1);
clkout3_buf : BUFG
port map
(O => CLK_OUT3,
I => clkout2);
clkout4_buf : BUFG
port map
(O => CLK_OUT4,
I => clkout3);
end xilinx;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_gestor_display IS
END tb_gestor_display;
ARCHITECTURE behavior OF tb_gestor_display IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT gestor_display
PORT(
CLK : IN std_logic;
piso_now : IN std_logic_vector(1 downto 0);
piso_obj : IN std_logic_vector(1 downto 0);
piso_seleccionado : OUT std_logic_vector(1 downto 0);
piso_actual : OUT std_logic_vector(1 downto 0);
accion : OUT std_logic_vector(1 downto 0)
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal piso_now : std_logic_vector(1 downto 0) := (others => '0');
signal piso_obj : std_logic_vector(1 downto 0) := (others => '0');
--Outputs
signal piso_seleccionado : std_logic_vector(1 downto 0);
signal piso_actual : std_logic_vector(1 downto 0);
signal accion : std_logic_vector(1 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: gestor_display PORT MAP (
CLK => CLK,
piso_now => piso_now,
piso_obj => piso_obj,
piso_seleccionado => piso_seleccionado,
piso_actual => piso_actual,
accion => accion
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
WAIT FOR 2 ns;
piso_now <= "01";
piso_obj <= "11";
WAIT FOR 20 ns;
piso_now <= "10";
WAIT FOR 20 ns;
piso_now <= "11";
WAIT FOR 20 ns;
piso_obj <= "00";
WAIT FOR 20 ns;
piso_now <= "10";
WAIT FOR 20 ns;
piso_obj <= "01";
WAIT FOR 20 ns;
piso_now <= "11";
WAIT FOR 20 ns;
piso_now <= "00";
WAIT FOR 20 ns;
ASSERT false
REPORT "Simulación finalizada. Test superado."
SEVERITY FAILURE;
end process;
END;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Stimulus Generator For TDP
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For TDP
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_TDP IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_TDP;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_TDP IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLKA : IN STD_LOGIC;
CLKB : IN STD_LOGIC;
TB_RST : IN STD_LOGIC;
ADDRA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
WEB : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0');
ADDRB : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
DINB : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
CHECK_DATA: OUT STD_LOGIC_VECTOR(1 DOWNTO 0):=(OTHERS => '0')
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
CONSTANT ADDR_ZERO : STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
CONSTANT DATA_PART_CNT_A : INTEGER:= DIVROUNDUP(32,32);
CONSTANT DATA_PART_CNT_B : INTEGER:= DIVROUNDUP(32,32);
SIGNAL WRITE_ADDR_A : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_B : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT_A : STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT_A : STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT_B : STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT_B : STD_LOGIC_VECTOR(11 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_A : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_B : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINB_INT : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL MAX_COUNT : STD_LOGIC_VECTOR(10 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(4096,11);
SIGNAL DO_WRITE_A : STD_LOGIC := '0';
SIGNAL DO_READ_A : STD_LOGIC := '0';
SIGNAL DO_WRITE_B : STD_LOGIC := '0';
SIGNAL DO_READ_B : STD_LOGIC := '0';
SIGNAL COUNT_NO : STD_LOGIC_VECTOR (10 DOWNTO 0):=(OTHERS => '0');
SIGNAL DO_READ_RA : STD_LOGIC := '0';
SIGNAL DO_READ_RB : STD_LOGIC := '0';
SIGNAL DO_READ_REG_A: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
SIGNAL DO_READ_REG_B: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
SIGNAL COUNT : integer := 0;
SIGNAL COUNT_B : integer := 0;
CONSTANT WRITE_CNT_A : integer := 6;
CONSTANT READ_CNT_A : integer := 6;
CONSTANT WRITE_CNT_B : integer := 4;
CONSTANT READ_CNT_B : integer := 4;
signal porta_wr_rd : std_logic:='0';
signal portb_wr_rd : std_logic:='0';
signal porta_wr_rd_complete: std_logic:='0';
signal portb_wr_rd_complete: std_logic:='0';
signal incr_cnt : std_logic :='0';
signal incr_cnt_b : std_logic :='0';
SIGNAL PORTB_WR_RD_HAPPENED: STD_LOGIC :='0';
SIGNAL LATCH_PORTA_WR_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_L1 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_L2 :STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_R1 :STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_R2 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_HAPPENED: STD_LOGIC :='0';
SIGNAL LATCH_PORTB_WR_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_L1 :STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_L2 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_R1 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_R2 :STD_LOGIC :='0';
BEGIN
WRITE_ADDR_INT_A(11 DOWNTO 0) <= WRITE_ADDR_A(11 DOWNTO 0);
READ_ADDR_INT_A(11 DOWNTO 0) <= READ_ADDR_A(11 DOWNTO 0);
ADDRA <= IF_THEN_ELSE(DO_WRITE_A='1',WRITE_ADDR_INT_A,READ_ADDR_INT_A) ;
WRITE_ADDR_INT_B(11 DOWNTO 0) <= WRITE_ADDR_B(11 DOWNTO 0);
--To avoid collision during idle period, negating the read_addr of port A
READ_ADDR_INT_B(11 DOWNTO 0) <= IF_THEN_ELSE( (DO_WRITE_B='0' AND DO_READ_B='0'),ADDR_ZERO,READ_ADDR_B(11 DOWNTO 0));
ADDRB <= IF_THEN_ELSE(DO_WRITE_B='1',WRITE_ADDR_INT_B,READ_ADDR_INT_B) ;
DINA <= DINA_INT ;
DINB <= DINB_INT ;
CHECK_DATA(0) <= DO_READ_A;
CHECK_DATA(1) <= DO_READ_B;
RD_ADDR_GEN_INST_A:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 4096,
RST_INC => 1 )
PORT MAP(
CLK => CLKA,
RST => TB_RST,
EN => DO_READ_A,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR_A
);
WR_ADDR_GEN_INST_A:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH =>4096 ,
RST_INC => 1 )
PORT MAP(
CLK => CLKA,
RST => TB_RST,
EN => DO_WRITE_A,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR_A
);
RD_ADDR_GEN_INST_B:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 4096 ,
RST_INC => 1 )
PORT MAP(
CLK => CLKB,
RST => TB_RST,
EN => DO_READ_B,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR_B
);
WR_ADDR_GEN_INST_B:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 4096 ,
RST_INC => 1 )
PORT MAP(
CLK => CLKB,
RST => TB_RST,
EN => DO_WRITE_B,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR_B
);
WR_DATA_GEN_INST_A:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>32,
DOUT_WIDTH => 32,
DATA_PART_CNT => 1,
SEED => 2)
PORT MAP (
CLK =>CLKA,
RST => TB_RST,
EN => DO_WRITE_A,
DATA_OUT => DINA_INT
);
WR_DATA_GEN_INST_B:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>32,
DOUT_WIDTH =>32 ,
DATA_PART_CNT =>1,
SEED => 2)
PORT MAP (
CLK =>CLKB,
RST => TB_RST,
EN => DO_WRITE_B,
DATA_OUT => DINB_INT
);
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
LATCH_PORTB_WR_RD_COMPLETE<='0';
ELSIF(PORTB_WR_RD_COMPLETE='1') THEN
LATCH_PORTB_WR_RD_COMPLETE <='1';
ELSIF(PORTA_WR_RD_HAPPENED='1') THEN
LATCH_PORTB_WR_RD_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTB_WR_RD_L1 <='0';
PORTB_WR_RD_L2 <='0';
ELSE
PORTB_WR_RD_L1 <= LATCH_PORTB_WR_RD_COMPLETE;
PORTB_WR_RD_L2 <= PORTB_WR_RD_L1;
END IF;
END IF;
END PROCESS;
PORTA_WR_RD_EN: PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTA_WR_RD <='1';
ELSE
PORTA_WR_RD <= PORTB_WR_RD_L2;
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTA_WR_RD_R1 <='0';
PORTA_WR_RD_R2 <='0';
ELSE
PORTA_WR_RD_R1 <=PORTA_WR_RD;
PORTA_WR_RD_R2 <=PORTA_WR_RD_R1;
END IF;
END IF;
END PROCESS;
PORTA_WR_RD_HAPPENED <= PORTA_WR_RD_R2;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
LATCH_PORTA_WR_RD_COMPLETE<='0';
ELSIF(PORTA_WR_RD_COMPLETE='1') THEN
LATCH_PORTA_WR_RD_COMPLETE <='1';
ELSIF(PORTB_WR_RD_HAPPENED='1') THEN
LATCH_PORTA_WR_RD_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTA_WR_RD_L1 <='0';
PORTA_WR_RD_L2 <='0';
ELSE
PORTA_WR_RD_L1 <= LATCH_PORTA_WR_RD_COMPLETE;
PORTA_WR_RD_L2 <= PORTA_WR_RD_L1;
END IF;
END IF;
END PROCESS;
PORTB_EN: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTB_WR_RD <='0';
ELSE
PORTB_WR_RD <= PORTA_WR_RD_L2;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTB_WR_RD_R1 <='0';
PORTB_WR_RD_R2 <='0';
ELSE
PORTB_WR_RD_R1 <=PORTB_WR_RD;
PORTB_WR_RD_R2 <=PORTB_WR_RD_R1;
END IF;
END IF;
END PROCESS;
---double registered of porta complete on portb clk
PORTB_WR_RD_HAPPENED <= PORTB_WR_RD_R2;
PORTA_WR_RD_COMPLETE <= '1' when count=(WRITE_CNT_A+READ_CNT_A) else '0';
start_counter: process(clka)
begin
if(rising_edge(clka)) then
if(TB_RST='1') then
incr_cnt <= '0';
elsif(porta_wr_rd ='1') then
incr_cnt <='1';
elsif(porta_wr_rd_complete='1') then
incr_cnt <='0';
end if;
end if;
end process;
COUNTER: process(clka)
begin
if(rising_edge(clka)) then
if(TB_RST='1') then
count <= 0;
elsif(incr_cnt='1') then
count<=count+1;
end if;
if(count=(WRITE_CNT_A+READ_CNT_A)) then
count<=0;
end if;
end if;
end process;
DO_WRITE_A<='1' when (count <WRITE_CNT_A and incr_cnt='1') else '0';
DO_READ_A <='1' when (count >WRITE_CNT_A and incr_cnt='1') else '0';
PORTB_WR_RD_COMPLETE <= '1' when count_b=(WRITE_CNT_B+READ_CNT_B) else '0';
startb_counter: process(clkb)
begin
if(rising_edge(clkb)) then
if(TB_RST='1') then
incr_cnt_b <= '0';
elsif(portb_wr_rd ='1') then
incr_cnt_b <='1';
elsif(portb_wr_rd_complete='1') then
incr_cnt_b <='0';
end if;
end if;
end process;
COUNTER_B: process(clkb)
begin
if(rising_edge(clkb)) then
if(TB_RST='1') then
count_b <= 0;
elsif(incr_cnt_b='1') then
count_b<=count_b+1;
end if;
if(count_b=WRITE_CNT_B+READ_CNT_B) then
count_b<=0;
end if;
end if;
end process;
DO_WRITE_B<='1' when (count_b <WRITE_CNT_B and incr_cnt_b='1') else '0';
DO_READ_B <='1' when (count_b >WRITE_CNT_B and incr_cnt_b='1') else '0';
BEGIN_SHIFT_REG_A: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_A(0),
CLK =>CLKA,
RST=>TB_RST,
D =>DO_READ_A
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_A(I),
CLK =>CLKA,
RST=>TB_RST,
D =>DO_READ_REG_A(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG_A;
BEGIN_SHIFT_REG_B: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_B(0),
CLK =>CLKB,
RST=>TB_RST,
D =>DO_READ_B
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_B(I),
CLK =>CLKB,
RST=>TB_RST,
D =>DO_READ_REG_B(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG_B;
REGCEA_PROCESS: PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
DO_READ_RA <= '0';
ELSE
DO_READ_RA <= DO_READ_A;
END IF;
END IF;
END PROCESS;
REGCEB_PROCESS: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
DO_READ_RB <= '0';
ELSE
DO_READ_RB <= DO_READ_B;
END IF;
END IF;
END PROCESS;
---REGCEB SHOULD BE SET AT THE CORE OUTPUT REGISTER/EMBEEDED OUTPUT REGISTER
--- WHEN CORE OUTPUT REGISTER IS SET REGCE SHOUD BE SET TO '1' WHEN THE READ DATA IS AVAILABLE AT THE CORE OUTPUT REGISTER
--WHEN CORE OUTPUT REGISTER IS '0' AND OUTPUT_PRIMITIVE_REG ='1', REGCE SHOULD BE SET WHEN THE DATA IS AVAILABLE AT THE PRIMITIVE OUTPUT REGISTER.
-- HERE, TO GENERAILIZE REGCE IS ASSERTED
WEA(0) <= IF_THEN_ELSE(DO_WRITE_A='1','1','0') ;
WEB(0) <= IF_THEN_ELSE(DO_WRITE_B='1','1','0') ;
END ARCHITECTURE;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: cycloneiii_ddr_phy
-- File: cycloneiii_ddr_phy.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: DDR PHY for Altera FPGAs
------------------------------------------------------------------------------
LIBRARY cycloneiii;
USE cycloneiii.all;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY altdqs_cyciii_adqs_n7i2 IS
generic (width : integer := 2; period : string := "10000ps");
PORT
(
dll_delayctrlout : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0);
dqsundelayedout : OUT STD_LOGIC_VECTOR (width-1 downto 0);
inclk : IN STD_LOGIC := '0';
oe : IN STD_LOGIC_VECTOR (width-1 downto 0) := (OTHERS => '1');
outclk : IN STD_LOGIC_VECTOR (width-1 downto 0);
outclkena : IN STD_LOGIC_VECTOR (width-1 downto 0) := (OTHERS => '1')
);
END altdqs_cyciii_adqs_n7i2;
ARCHITECTURE RTL OF altdqs_cyciii_adqs_n7i2 IS
-- ATTRIBUTE synthesis_clearbox : boolean;
-- ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS true;
SIGNAL wire_cyciii_dll1_delayctrlout : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_cyciii_dll1_dqsupdate : STD_LOGIC;
SIGNAL wire_cyciii_dll1_offsetctrlout : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL wire_cyciii_io2a_combout : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_cyciii_io2a_datain : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_cyciii_io2a_ddiodatain : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_cyciii_io2a_dqsbusout : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_cyciii_io2a_oe : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_cyciii_io2a_outclk : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL wire_cyciii_io2a_outclkena : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL delay_ctrl : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL dqs_update : STD_LOGIC;
SIGNAL offset_ctrl : STD_LOGIC_VECTOR (5 DOWNTO 0);
COMPONENT cycloneiii_dll
GENERIC
(
DELAY_BUFFER_MODE : STRING := "low";
DELAY_CHAIN_LENGTH : NATURAL := 12;
DELAYCTRLOUT_MODE : STRING := "normal";
INPUT_FREQUENCY : STRING;
JITTER_REDUCTION : STRING := "false";
OFFSETCTRLOUT_MODE : STRING := "static";
SIM_LOOP_DELAY_INCREMENT : NATURAL := 0;
SIM_LOOP_INTRINSIC_DELAY : NATURAL := 0;
SIM_VALID_LOCK : NATURAL := 5;
SIM_VALID_LOCKCOUNT : NATURAL := 0;
STATIC_DELAY_CTRL : NATURAL := 0;
STATIC_OFFSET : STRING;
USE_UPNDNIN : STRING := "false";
USE_UPNDNINCLKENA : STRING := "false";
lpm_type : STRING := "cycloneiii_dll"
);
PORT
(
addnsub : IN STD_LOGIC := '1';
aload : IN STD_LOGIC := '0';
clk : IN STD_LOGIC;
delayctrlout : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
dqsupdate : OUT STD_LOGIC;
offset : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
offsetctrlout : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
upndnin : IN STD_LOGIC := '0';
upndninclkena : IN STD_LOGIC := '1';
upndnout : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT cycloneiii_io
GENERIC
(
BUS_HOLD : STRING := "false";
DDIO_MODE : STRING := "none";
DDIOINCLK_INPUT : STRING := "negated_inclk";
DQS_CTRL_LATCHES_ENABLE : STRING := "false";
DQS_DELAY_BUFFER_MODE : STRING := "none";
DQS_EDGE_DETECT_ENABLE : STRING := "false";
DQS_INPUT_FREQUENCY : STRING := "unused";
DQS_OFFSETCTRL_ENABLE : STRING := "false";
DQS_OUT_MODE : STRING := "none";
DQS_PHASE_SHIFT : NATURAL := 0;
EXTEND_OE_DISABLE : STRING := "false";
GATED_DQS : STRING := "false";
INCLK_INPUT : STRING := "normal";
INPUT_ASYNC_RESET : STRING := "none";
INPUT_POWER_UP : STRING := "low";
INPUT_REGISTER_MODE : STRING := "none";
INPUT_SYNC_RESET : STRING := "none";
OE_ASYNC_RESET : STRING := "none";
OE_POWER_UP : STRING := "low";
OE_REGISTER_MODE : STRING := "none";
OE_SYNC_RESET : STRING := "none";
OPEN_DRAIN_OUTPUT : STRING := "false";
OPERATION_MODE : STRING;
OUTPUT_ASYNC_RESET : STRING := "none";
OUTPUT_POWER_UP : STRING := "low";
OUTPUT_REGISTER_MODE : STRING := "none";
OUTPUT_SYNC_RESET : STRING := "none";
SIM_DQS_DELAY_INCREMENT : NATURAL := 0;
SIM_DQS_INTRINSIC_DELAY : NATURAL := 0;
SIM_DQS_OFFSET_INCREMENT : NATURAL := 0;
TIE_OFF_OE_CLOCK_ENABLE : STRING := "false";
TIE_OFF_OUTPUT_CLOCK_ENABLE : STRING := "false";
lpm_type : STRING := "cycloneiii_io"
);
PORT
(
areset : IN STD_LOGIC := '0';
combout : OUT STD_LOGIC;
datain : IN STD_LOGIC := '0';
ddiodatain : IN STD_LOGIC := '0';
ddioinclk : IN STD_LOGIC := '0';
ddioregout : OUT STD_LOGIC;
delayctrlin : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
dqsbusout : OUT STD_LOGIC;
dqsupdateen : IN STD_LOGIC := '1';
inclk : IN STD_LOGIC := '0';
inclkena : IN STD_LOGIC := '1';
linkin : IN STD_LOGIC := '0';
linkout : OUT STD_LOGIC;
oe : IN STD_LOGIC := '1';
offsetctrlin : IN STD_LOGIC_VECTOR(5 DOWNTO 0) := (OTHERS => '0');
outclk : IN STD_LOGIC := '0';
outclkena : IN STD_LOGIC := '1';
padio : INOUT STD_LOGIC;
regout : OUT STD_LOGIC;
sreset : IN STD_LOGIC := '0';
terminationcontrol : IN STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0')
);
END COMPONENT;
BEGIN
delay_ctrl <= wire_cyciii_dll1_delayctrlout;
dll_delayctrlout <= delay_ctrl;
dqinclk <= wire_cyciii_io2a_dqsbusout;
dqs_update <= wire_cyciii_dll1_dqsupdate;
dqsundelayedout <= wire_cyciii_io2a_combout;
offset_ctrl <= wire_cyciii_dll1_offsetctrlout;
cyciii_dll1 : cycloneiii_dll
GENERIC MAP (
DELAY_BUFFER_MODE => "low",
DELAY_CHAIN_LENGTH => 12,
DELAYCTRLOUT_MODE => "normal",
INPUT_FREQUENCY => period, --"10000ps",
JITTER_REDUCTION => "false",
OFFSETCTRLOUT_MODE => "static",
SIM_LOOP_DELAY_INCREMENT => 132,
SIM_LOOP_INTRINSIC_DELAY => 3840,
SIM_VALID_LOCK => 1,
SIM_VALID_LOCKCOUNT => 46,
STATIC_OFFSET => "0",
USE_UPNDNIN => "false",
USE_UPNDNINCLKENA => "false"
)
PORT MAP (
clk => inclk,
delayctrlout => wire_cyciii_dll1_delayctrlout,
dqsupdate => wire_cyciii_dll1_dqsupdate,
offsetctrlout => wire_cyciii_dll1_offsetctrlout
);
wire_cyciii_io2a_datain <= dqs_datain_h;
wire_cyciii_io2a_ddiodatain <= dqs_datain_l;
wire_cyciii_io2a_oe <= oe;
wire_cyciii_io2a_outclk <= outclk;
wire_cyciii_io2a_outclkena <= outclkena;
loop0 : FOR i IN 0 TO width-1 GENERATE
cyciii_io2a : cycloneiii_io
GENERIC MAP (
DDIO_MODE => "output",
DQS_CTRL_LATCHES_ENABLE => "true",
DQS_DELAY_BUFFER_MODE => "low",
DQS_EDGE_DETECT_ENABLE => "false",
DQS_INPUT_FREQUENCY => period, --"10000ps",
DQS_OFFSETCTRL_ENABLE => "true",
DQS_OUT_MODE => "delay_chain3",
DQS_PHASE_SHIFT => 9000,
EXTEND_OE_DISABLE => "false",
GATED_DQS => "false",
OE_ASYNC_RESET => "none",
OE_POWER_UP => "low",
OE_REGISTER_MODE => "register",
OE_SYNC_RESET => "none",
OPEN_DRAIN_OUTPUT => "false",
OPERATION_MODE => "bidir",
OUTPUT_ASYNC_RESET => "none",
OUTPUT_POWER_UP => "low",
OUTPUT_REGISTER_MODE => "register",
OUTPUT_SYNC_RESET => "none",
SIM_DQS_DELAY_INCREMENT => 22,
SIM_DQS_INTRINSIC_DELAY => 960,
SIM_DQS_OFFSET_INCREMENT => 11,
TIE_OFF_OE_CLOCK_ENABLE => "false",
TIE_OFF_OUTPUT_CLOCK_ENABLE => "false"
)
PORT MAP (
combout => wire_cyciii_io2a_combout(i),
datain => wire_cyciii_io2a_datain(i),
ddiodatain => wire_cyciii_io2a_ddiodatain(i),
delayctrlin => delay_ctrl,
dqsbusout => wire_cyciii_io2a_dqsbusout(i),
dqsupdateen => dqs_update,
oe => wire_cyciii_io2a_oe(i),
offsetctrlin => offset_ctrl,
outclk => wire_cyciii_io2a_outclk(i),
outclkena => wire_cyciii_io2a_outclkena(i),
padio => dqs_padio(i)
);
END GENERATE loop0;
END RTL; --altdqs_cyciii_adqs_n7i2
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY altdqs_cyciii IS
generic (width : integer := 2; period : string := "10000ps");
PORT
(
dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
inclk : IN STD_LOGIC ;
oe : IN STD_LOGIC_VECTOR (width-1 downto 0);
outclk : IN STD_LOGIC_VECTOR (width-1 downto 0);
dll_delayctrlout : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0);
dqsundelayedout : OUT STD_LOGIC_VECTOR (width-1 downto 0)
);
END;
ARCHITECTURE RTL OF altdqs_cyciii IS
-- ATTRIBUTE synthesis_clearbox: boolean;
-- ATTRIBUTE synthesis_clearbox OF RTL: ARCHITECTURE IS TRUE;
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL sub_wire2 : STD_LOGIC_VECTOR (width-1 downto 0);
SIGNAL sub_wire3_bv : BIT_VECTOR (width-1 downto 0);
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (width-1 downto 0);
COMPONENT altdqs_cyciii_adqs_n7i2
generic (width : integer := 2; period : string := "10000ps");
PORT (
outclk : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0);
outclkena : IN STD_LOGIC_VECTOR (width-1 downto 0);
oe : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
inclk : IN STD_LOGIC ;
dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
dll_delayctrlout : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
dqsundelayedout : OUT STD_LOGIC_VECTOR (width-1 downto 0)
);
END COMPONENT;
BEGIN
sub_wire3_bv(width-1 downto 0) <= (others => '1');
sub_wire3 <= To_stdlogicvector(sub_wire3_bv);
dll_delayctrlout <= sub_wire0(5 DOWNTO 0);
dqinclk <= not sub_wire1(width-1 downto 0);
dqsundelayedout <= sub_wire2(width-1 downto 0);
altdqs_cyciii_adqs_n7i2_component : altdqs_cyciii_adqs_n7i2
generic map (width, period)
PORT MAP (
outclk => outclk,
outclkena => sub_wire3,
oe => oe,
dqs_datain_h => dqs_datain_h,
inclk => inclk,
dqs_datain_l => dqs_datain_l,
dll_delayctrlout => sub_wire0,
dqinclk => sub_wire1,
dqsundelayedout => sub_wire2,
dqs_padio => dqs_padio
);
END RTL;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
------------------------------------------------------------------
-- CYCLONEIII DDR PHY --------------------------------------------
------------------------------------------------------------------
entity cycloneiii_ddr_phy is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0)
);
end;
architecture rtl of cycloneiii_ddr_phy is
signal vcc, gnd, dqsn, oe, lockl : std_logic;
signal ddr_clk_fb_outr : std_ulogic;
signal ddr_clk_fbl, fbclk : std_ulogic;
signal ddr_rasnr, ddr_casnr, ddr_wenr : std_ulogic;
signal ddr_clkl, ddr_clkbl : std_logic_vector(2 downto 0);
signal ddr_csnr, ddr_ckenr, ckel : std_logic_vector(1 downto 0);
signal clk_0ro, clk_90ro, clk_180ro, clk_270ro : std_ulogic;
signal clk_0r, clk_90r, clk_180r, clk_270r : std_ulogic;
signal clk0r, clk90r, clk180r, clk270r : std_ulogic;
signal locked, vlockl, ddrclkfbl : std_ulogic;
signal clk4, clk5 : std_logic;
signal ddr_dqin : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqout : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_dqoen : std_logic_vector (dbits-1 downto 0); -- ddr data
signal ddr_adr : std_logic_vector (13 downto 0); -- ddr address
signal ddr_bar : std_logic_vector (1 downto 0); -- ddr address
signal ddr_dmr : std_logic_vector (dbits/8-1 downto 0); -- ddr address
signal ddr_dqsin : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoen : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal ddr_dqsoutl : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsdel, dqsclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal da : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dqinl : std_logic_vector (dbits-1 downto 0); -- ddr data
signal dllrst : std_logic_vector(0 to 3);
signal dll0rst : std_logic_vector(0 to 3);
signal mlock, mclkfb, mclk, mclkfx, mclk0 : std_ulogic;
signal gndv : std_logic_vector (dbits-1 downto 0); -- ddr dqs
signal pclkout : std_logic_vector (5 downto 1);
signal ddr_clkin : std_logic_vector(0 to 2);
signal dqinclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsoclk : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
signal dqsnv : std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
constant DDR_FREQ : integer := (MHz * clk_mul) / clk_div;
component altdqs_cyciii
generic (width : integer := 2; period : string := "10000ps");
PORT
(
dqs_datain_h : IN STD_LOGIC_VECTOR (width-1 downto 0);
dqs_datain_l : IN STD_LOGIC_VECTOR (width-1 downto 0);
inclk : IN STD_LOGIC ;
oe : IN STD_LOGIC_VECTOR (width-1 downto 0);
outclk : IN STD_LOGIC_VECTOR (width-1 downto 0);
dll_delayctrlout : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
dqinclk : OUT STD_LOGIC_VECTOR (width-1 downto 0);
dqs_padio : INOUT STD_LOGIC_VECTOR (width-1 downto 0);
dqsundelayedout : OUT STD_LOGIC_VECTOR (width-1 downto 0)
);
END component;
type phasevec is array (1 to 3) of string(1 to 4);
type phasevecarr is array (10 to 13) of phasevec;
constant phasearr : phasevecarr := (
("2500", "5000", "7500"), ("2273", "4545", "6818"), -- 100 & 110 MHz
("2083", "4167", "6250"), ("1923", "3846", "5769")); -- 120 & 130 MHz
type periodtype is array (10 to 13) of string(1 to 6);
constant periodstr : periodtype := ("9999ps", "9090ps", "8333ps", "7692ps");
begin
oe <= not oen; vcc <= '1'; gnd <= '0'; gndv <= (others => '0');
mclk <= clk;
-- clkout <= clk_270r;
-- clkout <= clk_0r when DDR_FREQ >= 110 else clk_270r;
clkout <= clk_90r when DDR_FREQ > 120 else clk_0r;
clk0r <= clk_270r; clk90r <= clk_0r;
clk180r <= clk_90r; clk270r <= clk_180r;
dll : altpll
generic map (
intended_device_family => "CycloneIII",
operation_mode => "NORMAL",
inclk0_input_frequency => 1000000/MHz,
inclk1_input_frequency => 1000000/MHz,
clk4_multiply_by => clk_mul, clk4_divide_by => clk_div,
clk3_multiply_by => clk_mul, clk3_divide_by => clk_div,
clk2_multiply_by => clk_mul, clk2_divide_by => clk_div,
clk1_multiply_by => clk_mul, clk1_divide_by => clk_div,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk3_phase_shift => phasearr(DDR_FREQ/10)(3),
clk2_phase_shift => phasearr(DDR_FREQ/10)(2),
clk1_phase_shift => phasearr(DDR_FREQ/10)(1)
-- clk3_phase_shift => "6250", clk2_phase_shift => "4167", clk1_phase_shift => "2083"
-- clk3_phase_shift => "7500", clk2_phase_shift => "5000", clk1_phase_shift => "2500"
)
port map ( inclk(0) => mclk, inclk(1) => gnd, clk(0) => clk_0r,
clk(1) => clk_90r, clk(2) => clk_180r, clk(3) => clk_270r,
clk(4) => clk4, clk(5) => clk5, locked => lockl);
rstdel : process (mclk, rst, lockl)
begin
if rst = '0' then dllrst <= (others => '1');
elsif rising_edge(mclk) then
dllrst <= dllrst(1 to 3) & '0';
end if;
end process;
rdel : if rstdelay /= 0 generate
rcnt : process (clk_0r)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk_0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*DDR_FREQ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-- Generate external DDR clock
-- fbclkpad : altddio_out generic map (width => 1)
-- port map ( datain_h(0) => vcc, datain_l(0) => gnd,
-- outclock => clk90r, dataout(0) => ddr_clk_fb_out);
ddrclocks : for i in 0 to 2 generate
clkpad : altddio_out generic map (width => 1, INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h(0) => vcc, datain_l(0) => gnd,
outclock => clk90r, dataout(0) => ddr_clk(i));
clknpad : altddio_out generic map (width => 1, INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h(0) => gnd, datain_l(0) => vcc,
outclock => clk90r, dataout(0) => ddr_clkb(i));
end generate;
csnpads : altddio_out generic map (width => 2, INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h => csn(1 downto 0), datain_l => csn(1 downto 0),
outclock => clk0r, dataout => ddr_csb(1 downto 0));
ckepads : altddio_out generic map (width => 2, INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h => ckel(1 downto 0), datain_l => ckel(1 downto 0),
outclock => clk0r, dataout => ddr_cke(1 downto 0));
ddrbanks : for i in 0 to 1 generate
ckel(i) <= cke(i) and locked;
end generate;
rasnpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h(0) => rasn, datain_l(0) => rasn,
outclock => clk0r, dataout(0) => ddr_rasb);
casnpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h(0) => casn, datain_l(0) => casn,
outclock => clk0r, dataout(0) => ddr_casb);
wenpad : altddio_out generic map (width => 1,
INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map ( datain_h(0) => wen, datain_l(0) => wen,
outclock => clk0r, dataout(0) => ddr_web);
dmpads : altddio_out generic map (width => dbits/8,
INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map (
datain_h => dm(dbits/8*2-1 downto dbits/8),
datain_l => dm(dbits/8-1 downto 0),
outclock => clk0r, dataout => ddr_dm
);
bapads : altddio_out generic map (width => 2)
port map (
datain_h => ba, datain_l => ba,
outclock => clk0r, dataout => ddr_ba
);
addrpads : altddio_out generic map (width => 14)
port map (
datain_h => addr, datain_l => addr,
outclock => clk0r, dataout => ddr_ad
);
-- DQS generation
dqsnv <= (others => dqsn);
dqsoclk <= (others => clk90r);
altdqs0 : altdqs_cyciii generic map (dbits/8, periodstr(DDR_FREQ/10))
port map (dqs_datain_h => dqsnv, dqs_datain_l => gndv(dbits/8-1 downto 0),
inclk => clk270r, oe => ddr_dqsoen, outclk => dqsoclk,
dll_delayctrlout => open, dqinclk => dqinclk, dqs_padio => ddr_dqs,
dqsundelayedout => open );
-- Data bus
dqgen : for i in 0 to dbits/8-1 generate
qi : altddio_bidir generic map (width => 8, oe_reg =>"REGISTERED",
INTENDED_DEVICE_FAMILY => "CYCLONEIII")
port map (
datain_l => dqout(i*8+7 downto i*8),
datain_h => dqout(i*8+7+dbits downto dbits+i*8),
inclock => dqinclk(i), --clk270r,
outclock => clk0r, oe => oe,
dataout_h => dqin(i*8+7 downto i*8),
dataout_l => dqin(i*8+7+dbits downto dbits+i*8), --dqinl(i*8+7 downto i*8),
padio => ddr_dq(i*8+7 downto i*8));
end generate;
dqsreg : process(clk180r)
begin
if rising_edge(clk180r) then
dqsn <= oe;
end if;
end process;
oereg : process(clk0r)
begin
if rising_edge(clk0r) then
ddr_dqsoen(dbits/8-1 downto 0) <= (others => not dqsoen);
end if;
end process;
end;
|
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-- more details.
--
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Generates all control signals for the DACs, multiplexes the values for the
-- dual DAC and adds an offset to the DAC value to make it purely positive.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity DACController is
generic
(
-- The width of the DAC values.
data_width: natural
);
port
(
-- The system clock.
clk: in std_logic;
-- The value for DAC channel 0.
channel_0_value : in signed(data_width-1 downto 0);
-- The value for DAC channel 1.
channel_1_value : in signed(data_width-1 downto 0);
-- The DAC´s channel selection signal.
dac_channel_select: out std_logic;
-- The DAC´s write signal.
dac_write: out std_logic;
-- The currently selected DAC value with an offset added.
dac_value : out unsigned(data_width-1 downto 0)
);
end entity;
architecture stdarch of DACController is
type reg_type is record
dac_channel_select, dac_write: std_logic;
dac_value : unsigned(data_width-1 downto 0);
end record;
signal state, next_state: reg_type :=
(
dac_channel_select => '0',
dac_write => '0',
dac_value => (others => '0')
);
begin
--------------------------------------------------------------------------------
-- State register.
--------------------------------------------------------------------------------
state_register: process is
begin
wait until rising_edge(clk);
state <= next_state;
end process;
--------------------------------------------------------------------------------
-- Next state logic.
--------------------------------------------------------------------------------
next_state_logic: process(state, channel_0_value, channel_1_value) is
variable next_dac_value: signed(data_width-1 downto 0);
begin
-- Defaults.
next_state <= state;
-- Switch to the next channel when the write signal gets deactivated.
if (state.dac_write = '1') then
-- Switch to the next channel and get this channel´s value.
if state.dac_channel_select = '0' then
next_state.dac_channel_select <= '1';
next_dac_value := channel_1_value;
else
next_state.dac_channel_select <= '0';
next_dac_value := channel_0_value;
end if;
-- Toggle the sign bit, i.e. convert the signed value to an unsigned value
-- with an offset.
next_dac_value(data_width-1) := not next_dac_value(data_width-1);
next_state.dac_value <= unsigned(next_dac_value);
end if;
-- Toggle the write signal.
next_state.dac_write <= not state.dac_write;
end process;
--------------------------------------------------------------------------------
-- Output logic.
--------------------------------------------------------------------------------
dac_channel_select <= state.dac_channel_select;
dac_write <= state.dac_write;
dac_value <= state.dac_value;
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1070.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p03n01i01070ent IS
PORT ( ii: INOUT integer);
TYPE A IS ARRAY (NATURAL RANGE <>) OF INTEGER;
SUBTYPE A6 IS A (1 TO 6);
SUBTYPE A8 IS A (1 TO 8);
FUNCTION func1 (a,b : INTEGER := 3) RETURN A6 IS
BEGIN
IF (a=3) AND (b=3) THEN
RETURN (1,2,3,4,5,6);
ELSE
IF (a=3) THEN
RETURN (11,22,33,44,55,66);
ELSE
RETURN (111,222,333,444,555,666);
END IF;
END IF;
END;
END c06s04b00x00p03n01i01070ent;
ARCHITECTURE c06s04b00x00p03n01i01070arch OF c06s04b00x00p03n01i01070ent IS
BEGIN
TESTING: PROCESS
VARIABLE q : A8;
BEGIN
q(1) := func1(3,3)(1);
q(2) := func1(0,3)(2);
q(3) := func1(3,0)(3);
q(4) := func1(0,3)(4);
q(5) := func1(3,3)(5);
q(6) := func1(3,0)(6);
q(7) := func1(3,3)(3);
q(8) := func1(0,3)(1);
WAIT FOR 1 ns;
assert NOT(q(1 TO 8) = (1=>1,2=>222,3=>33,4=>444,5=>5,6=>66,7=>3,8=>111))
report "***PASSED TEST: c06s04b00x00p03n01i01070"
severity NOTE;
assert (q(1 TO 8) = (1=>1,2=>222,3=>33,4=>444,5=>5,6=>66,7=>3,8=>111))
report "***FAILED TEST: c06s04b00x00p03n01i01070 - Index on functin call test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p03n01i01070arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1070.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p03n01i01070ent IS
PORT ( ii: INOUT integer);
TYPE A IS ARRAY (NATURAL RANGE <>) OF INTEGER;
SUBTYPE A6 IS A (1 TO 6);
SUBTYPE A8 IS A (1 TO 8);
FUNCTION func1 (a,b : INTEGER := 3) RETURN A6 IS
BEGIN
IF (a=3) AND (b=3) THEN
RETURN (1,2,3,4,5,6);
ELSE
IF (a=3) THEN
RETURN (11,22,33,44,55,66);
ELSE
RETURN (111,222,333,444,555,666);
END IF;
END IF;
END;
END c06s04b00x00p03n01i01070ent;
ARCHITECTURE c06s04b00x00p03n01i01070arch OF c06s04b00x00p03n01i01070ent IS
BEGIN
TESTING: PROCESS
VARIABLE q : A8;
BEGIN
q(1) := func1(3,3)(1);
q(2) := func1(0,3)(2);
q(3) := func1(3,0)(3);
q(4) := func1(0,3)(4);
q(5) := func1(3,3)(5);
q(6) := func1(3,0)(6);
q(7) := func1(3,3)(3);
q(8) := func1(0,3)(1);
WAIT FOR 1 ns;
assert NOT(q(1 TO 8) = (1=>1,2=>222,3=>33,4=>444,5=>5,6=>66,7=>3,8=>111))
report "***PASSED TEST: c06s04b00x00p03n01i01070"
severity NOTE;
assert (q(1 TO 8) = (1=>1,2=>222,3=>33,4=>444,5=>5,6=>66,7=>3,8=>111))
report "***FAILED TEST: c06s04b00x00p03n01i01070 - Index on functin call test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p03n01i01070arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1070.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p03n01i01070ent IS
PORT ( ii: INOUT integer);
TYPE A IS ARRAY (NATURAL RANGE <>) OF INTEGER;
SUBTYPE A6 IS A (1 TO 6);
SUBTYPE A8 IS A (1 TO 8);
FUNCTION func1 (a,b : INTEGER := 3) RETURN A6 IS
BEGIN
IF (a=3) AND (b=3) THEN
RETURN (1,2,3,4,5,6);
ELSE
IF (a=3) THEN
RETURN (11,22,33,44,55,66);
ELSE
RETURN (111,222,333,444,555,666);
END IF;
END IF;
END;
END c06s04b00x00p03n01i01070ent;
ARCHITECTURE c06s04b00x00p03n01i01070arch OF c06s04b00x00p03n01i01070ent IS
BEGIN
TESTING: PROCESS
VARIABLE q : A8;
BEGIN
q(1) := func1(3,3)(1);
q(2) := func1(0,3)(2);
q(3) := func1(3,0)(3);
q(4) := func1(0,3)(4);
q(5) := func1(3,3)(5);
q(6) := func1(3,0)(6);
q(7) := func1(3,3)(3);
q(8) := func1(0,3)(1);
WAIT FOR 1 ns;
assert NOT(q(1 TO 8) = (1=>1,2=>222,3=>33,4=>444,5=>5,6=>66,7=>3,8=>111))
report "***PASSED TEST: c06s04b00x00p03n01i01070"
severity NOTE;
assert (q(1 TO 8) = (1=>1,2=>222,3=>33,4=>444,5=>5,6=>66,7=>3,8=>111))
report "***FAILED TEST: c06s04b00x00p03n01i01070 - Index on functin call test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p03n01i01070arch;
|
library ieee;
use ieee.std_logic_1164.all;
entity LFSR_Out is
generic (i:integer := 2);
port(
CLK: in std_logic;
RST: in std_logic;
LS: in std_logic;
Pin: in std_logic_vector(0 to 2**i-1);
Pout: out std_logic_vector(0 to 2**i-1)
);
end LFSR_Out;
architecture Beh of LFSR_Out is
signal sreg: std_logic_vector(0 to 2**i-1);
signal sdat: std_logic_vector(0 to 2**i-1);
Begin
Main: process (CLK, RST, sdat)
begin
if RST = '1' then
sreg <= (others => '0');
elsif rising_edge(CLK) then
sreg <= sdat;
end if;
end process;
Data: process (LS, Pin, sreg)
begin
if LS = '0' then
sdat <= Pin;
else
sdat <= (sreg(2**i-1) xor sreg(0)) & sreg(0 to 2**i-2);
end if;
end process;
Pout <= sreg;
End Beh; |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:25:04 07/06/05
-- Design Name:
-- Module Name: half_adder - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity half_adder is
port(x,y : in std_logic;
Hsum,Hcarry : out std_logic );
end half_adder;
architecture Behavioral of half_adder is
begin
Hsum <= x xor y ;
Hcarry <= x and y ;
end Behavioral;
|
-- GR USB 2.0 Device Controller
constant CFG_GRUSBDC : integer := CONFIG_GRUSBDC_ENABLE;
constant CFG_GRUSBDC_AIFACE : integer := CONFIG_GRUSBDC_AIFACE;
constant CFG_GRUSBDC_UIFACE : integer := CONFIG_GRUSBDC_UIFACE;
constant CFG_GRUSBDC_DW : integer := CONFIG_GRUSBDC_DW;
constant CFG_GRUSBDC_NEPI : integer := CONFIG_GRUSBDC_NEPI;
constant CFG_GRUSBDC_NEPO : integer := CONFIG_GRUSBDC_NEPO;
constant CFG_GRUSBDC_I0 : integer := CONFIG_GRUSBDC_I0;
constant CFG_GRUSBDC_I1 : integer := CONFIG_GRUSBDC_I1;
constant CFG_GRUSBDC_I2 : integer := CONFIG_GRUSBDC_I2;
constant CFG_GRUSBDC_I3 : integer := CONFIG_GRUSBDC_I3;
constant CFG_GRUSBDC_I4 : integer := CONFIG_GRUSBDC_I4;
constant CFG_GRUSBDC_I5 : integer := CONFIG_GRUSBDC_I5;
constant CFG_GRUSBDC_I6 : integer := CONFIG_GRUSBDC_I6;
constant CFG_GRUSBDC_I7 : integer := CONFIG_GRUSBDC_I7;
constant CFG_GRUSBDC_I8 : integer := CONFIG_GRUSBDC_I8;
constant CFG_GRUSBDC_I9 : integer := CONFIG_GRUSBDC_I9;
constant CFG_GRUSBDC_I10 : integer := CONFIG_GRUSBDC_I10;
constant CFG_GRUSBDC_I11 : integer := CONFIG_GRUSBDC_I11;
constant CFG_GRUSBDC_I12 : integer := CONFIG_GRUSBDC_I12;
constant CFG_GRUSBDC_I13 : integer := CONFIG_GRUSBDC_I13;
constant CFG_GRUSBDC_I14 : integer := CONFIG_GRUSBDC_I14;
constant CFG_GRUSBDC_I15 : integer := CONFIG_GRUSBDC_I15;
constant CFG_GRUSBDC_O0 : integer := CONFIG_GRUSBDC_O0;
constant CFG_GRUSBDC_O1 : integer := CONFIG_GRUSBDC_O1;
constant CFG_GRUSBDC_O2 : integer := CONFIG_GRUSBDC_O2;
constant CFG_GRUSBDC_O3 : integer := CONFIG_GRUSBDC_O3;
constant CFG_GRUSBDC_O4 : integer := CONFIG_GRUSBDC_O4;
constant CFG_GRUSBDC_O5 : integer := CONFIG_GRUSBDC_O5;
constant CFG_GRUSBDC_O6 : integer := CONFIG_GRUSBDC_O6;
constant CFG_GRUSBDC_O7 : integer := CONFIG_GRUSBDC_O7;
constant CFG_GRUSBDC_O8 : integer := CONFIG_GRUSBDC_O8;
constant CFG_GRUSBDC_O9 : integer := CONFIG_GRUSBDC_O9;
constant CFG_GRUSBDC_O10 : integer := CONFIG_GRUSBDC_O10;
constant CFG_GRUSBDC_O11 : integer := CONFIG_GRUSBDC_O11;
constant CFG_GRUSBDC_O12 : integer := CONFIG_GRUSBDC_O12;
constant CFG_GRUSBDC_O13 : integer := CONFIG_GRUSBDC_O13;
constant CFG_GRUSBDC_O14 : integer := CONFIG_GRUSBDC_O14;
constant CFG_GRUSBDC_O15 : integer := CONFIG_GRUSBDC_O15;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for ent_bb
--
-- Generated
-- by: wig
-- on: Sat Mar 3 18:34:27 2007
-- cmd: /home/wig/work/MIX/mix_0.pl ../sigport.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_bb-rtl-conf-c.vhd,v 1.1 2007/03/05 13:35:50 wig Exp $
-- $Date: 2007/03/05 13:35:50 $
-- $Log: ent_bb-rtl-conf-c.vhd,v $
-- Revision 1.1 2007/03/05 13:35:50 wig
-- Reworked testcase sigport (changed case of generated files).
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.104 2007/03/03 17:24:06 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration ent_bb_RTL_CONF / ent_bb
--
configuration ent_bb_RTL_CONF of ent_bb is
for rtl
-- Generated Configuration
end for;
end ent_bb_RTL_CONF;
--
-- End of Generated Configuration ent_bb_RTL_CONF
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file k7_bram4096x64.vhd when simulating
-- the core, k7_bram4096x64. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY k7_bram4096x64 IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END k7_bram4096x64;
ARCHITECTURE k7_bram4096x64_a OF k7_bram4096x64 IS
-- synthesis translate_off
COMPONENT wrapped_k7_bram4096x64
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_k7_bram4096x64 USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 12,
c_addrb_width => 12,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 8,
c_common_clk => 0,
c_default_data => "0",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "kintex7",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 1,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "no_coe_file_loaded",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 0,
c_mem_type => 2,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 4096,
c_read_depth_b => 4096,
c_read_width_a => 64,
c_read_width_b => 64,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 1,
c_use_byte_web => 1,
c_use_default_data => 0,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 8,
c_web_width => 8,
c_write_depth_a => 4096,
c_write_depth_b => 4096,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 64,
c_write_width_b => 64,
c_xdevicefamily => "kintex7"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_k7_bram4096x64
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb
);
-- synthesis translate_on
END k7_bram4096x64_a;
|
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|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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LQ+7cpFcsg2KbuXVS771Co1sOrB9vBpStd/P0rWArS3mSRpY2YN524uendGyt017SdtdqOdJCCze
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Ub4Zq/yTvE599DxJegdm+6WGooIMhv3lVN0liA==
`protect end_protected
|
package wishbone_types is
type wb_slave_out_t is record
dat : bit_vector;
ack : bit;
stall : bit;
end record;
-- Common subtypes
constant wb_cpu_data_bits : integer := 64;
subtype wb_cpu_in_t is wb_slave_out_t(dat(wb_cpu_data_bits-1 downto 0));
-- GHDL: Works
-- subtype wishbone_slave_out is wb_slave_out_t(dat(wb_cpu_data_bits-1 downto 0));
-- GHDL: Breaks
subtype wishbone_slave_out is wb_cpu_in_t;
end package wishbone_types;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Rtype for register to register operations
-- Itype for immediate value to register operations and loading
-- Stype for storing
-- Utype for unconditional branch (jump)
-- SBtype for branches
package config is
-- System word size
subtype doubleword is std_logic_vector(63 downto 0);
subtype word is std_logic_vector(31 downto 0);
constant zero_word: std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
constant ones_word: std_logic_vector(31 downto 0) := "11111111111111111111111111111111";
constant byte_mask_1: std_logic_vector(63 downto 0) := "0000000000000000000000000000000000000000000000000000000011111111";
constant byte_mask_2: std_logic_vector(63 downto 0) := "0000000000000000000000000000000000000000000000001111111111111111";
constant byte_mask_4: std_logic_vector(63 downto 0) := "0000000000000000000000000000000011111111111111111111111111111111";
-- Masks for CSR access
-- NOTES: Unacceptable with our Vivado version:
-- constant MASK_WIRI_MIP: std_logic_vector(63 downto 0) := x"bbb"; -- Can't elaborate, but looks fine in IDE
-- constant MASK_WIRI_MIP: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(x"bbb")); -- Thinks this is a string literal
-- constant MASK_WIRI_MIP: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#bbb#)); -- Needs bit size for result
constant MASK_WIRI_MIP: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#bbb#, 64));
constant MASK_WIRI_MIE: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#bbb#, 64));
constant MASK_WIRI_SIP: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#db#, 64));
constant MASK_WIRI_SIE: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_A: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_AB: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_AC: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_AD: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_AE: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_AF: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
constant MASK_AG: std_logic_vector(63 downto 0) := std_logic_vector(to_unsigned(16#0#, 64));
-- Special CSR return values for r/w filter functions
constant CSR_TRAP_VALUE : doubleword := (others => '0');
constant CSR_IGNORE_VALUE : doubleword := (others => '1');
-- Familiar names for CSR registers
constant CSR_ERROR :integer := -1; -- Not implemented, trap
constant CSR_ZERO :integer := 0; -- Not implemented, read 0, ignore write
constant CSR_FFLAGS :integer := 1;
constant CSR_FRM :integer := 2;
constant CSR_FCSR :integer := 3;
constant CSR_CYCLE :integer := 4;
constant CSR_TIME :integer := 5;
constant CSR_INSTRET :integer := 6;
constant CSR_SIE :integer := 7;
constant CSR_STVEC :integer := 8;
constant CSR_SCOUNTEREN :integer := 9;
constant CSR_SSCRATCH :integer := 10;
constant CSR_SEPC :integer := 11;
constant CSR_SCAUSE :integer := 12;
constant CSR_STVAL :integer := 13;
constant CSR_SIP :integer := 14;
constant CSR_SSTATUS :integer := 15;
constant CSR_SATP :integer := 16;
constant CSR_MSTATUS :integer := 17;
constant CSR_MISA :integer := 18;
constant CSR_MEDELEG :integer := 19;
constant CSR_MIDELEG :integer := 20;
constant CSR_MIE :integer := 21;
constant CSR_MTVEC :integer := 22;
constant CSR_MCOUNTEREN :integer := 23;
constant CSR_MSCRATCH :integer := 24;
constant CSR_MEPC :integer := 25;
constant CSR_MCAUSE :integer := 26;
constant CSR_MTVAL :integer := 27;
constant CSR_MIP :integer := 28;
constant CSR_MCYCLE :integer := 29;
constant CSR_MINSTRET :integer := 30;
-- CSR 12-bit addresses per specification
constant CSR_ADDR_USTATUS : std_logic_vector(11 downto 0) := x"000";
constant CSR_ADDR_UIE : std_logic_vector(11 downto 0) := x"004";
constant CSR_ADDR_UTVEC : std_logic_vector(11 downto 0) := x"005";
constant CSR_ADDR_USCRATCH : std_logic_vector(11 downto 0) := x"040";
constant CSR_ADDR_UEPC : std_logic_vector(11 downto 0) := x"041";
constant CSR_ADDR_UCAUSE : std_logic_vector(11 downto 0) := x"042";
constant CSR_ADDR_UTVAL : std_logic_vector(11 downto 0) := x"043";
constant CSR_ADDR_UIP : std_logic_vector(11 downto 0) := x"044";
constant CSR_ADDR_FFLAGS : std_logic_vector(11 downto 0) := x"001";
constant CSR_ADDR_FRM : std_logic_vector(11 downto 0) := x"002";
constant CSR_ADDR_FCSR : std_logic_vector(11 downto 0) := x"003";
constant CSR_ADDR_CYCLE : std_logic_vector(11 downto 0) := x"c00";
constant CSR_ADDR_TIME : std_logic_vector(11 downto 0) := x"c01";
constant CSR_ADDR_INSTRET : std_logic_vector(11 downto 0) := x"c02";
constant CSR_ADDR_HPMCOUNTER3: std_logic_vector(11 downto 0) := x"c03";
constant CSR_ADDR_HPMCOUNTER4: std_logic_vector(11 downto 0) := x"c04";
constant CSR_ADDR_HPMCOUNTER5: std_logic_vector(11 downto 0) := x"c05";
constant CSR_ADDR_HPMCOUNTER6: std_logic_vector(11 downto 0) := x"c06";
constant CSR_ADDR_HPMCOUNTER7: std_logic_vector(11 downto 0) := x"c07";
constant CSR_ADDR_HPMCOUNTER8: std_logic_vector(11 downto 0) := x"c08";
constant CSR_ADDR_HPMCOUNTER9: std_logic_vector(11 downto 0) := x"c09";
constant CSR_ADDR_HPMCOUNTER10: std_logic_vector(11 downto 0) := x"c0a";
constant CSR_ADDR_HPMCOUNTER11: std_logic_vector(11 downto 0) := x"c0b";
constant CSR_ADDR_HPMCOUNTER12: std_logic_vector(11 downto 0) := x"c0c";
constant CSR_ADDR_HPMCOUNTER13: std_logic_vector(11 downto 0) := x"c0d";
constant CSR_ADDR_HPMCOUNTER14: std_logic_vector(11 downto 0) := x"c0e";
constant CSR_ADDR_HPMCOUNTER15: std_logic_vector(11 downto 0) := x"c0f";
constant CSR_ADDR_HPMCOUNTER16: std_logic_vector(11 downto 0) := x"c10";
constant CSR_ADDR_HPMCOUNTER17: std_logic_vector(11 downto 0) := x"c11";
constant CSR_ADDR_HPMCOUNTER18: std_logic_vector(11 downto 0) := x"c12";
constant CSR_ADDR_HPMCOUNTER19: std_logic_vector(11 downto 0) := x"c13";
constant CSR_ADDR_HPMCOUNTER20: std_logic_vector(11 downto 0) := x"c14";
constant CSR_ADDR_HPMCOUNTER21: std_logic_vector(11 downto 0) := x"c15";
constant CSR_ADDR_HPMCOUNTER22: std_logic_vector(11 downto 0) := x"c16";
constant CSR_ADDR_HPMCOUNTER23: std_logic_vector(11 downto 0) := x"c17";
constant CSR_ADDR_HPMCOUNTER24: std_logic_vector(11 downto 0) := x"c18";
constant CSR_ADDR_HPMCOUNTER25: std_logic_vector(11 downto 0) := x"c19";
constant CSR_ADDR_HPMCOUNTER26: std_logic_vector(11 downto 0) := x"c1a";
constant CSR_ADDR_HPMCOUNTER27: std_logic_vector(11 downto 0) := x"c1b";
constant CSR_ADDR_HPMCOUNTER28: std_logic_vector(11 downto 0) := x"c1c";
constant CSR_ADDR_HPMCOUNTER29: std_logic_vector(11 downto 0) := x"c1d";
constant CSR_ADDR_HPMCOUNTER30: std_logic_vector(11 downto 0) := x"c1e";
constant CSR_ADDR_HPMCOUNTER31 : std_logic_vector(11 downto 0) := x"c1f";
constant CSR_ADDR_SSTATUS : std_logic_vector(11 downto 0) := x"100";
constant CSR_ADDR_SEDELEG : std_logic_vector(11 downto 0) := x"102";
constant CSR_ADDR_SIDELEG : std_logic_vector(11 downto 0) := x"103";
constant CSR_ADDR_SIE : std_logic_vector(11 downto 0) := x"104";
constant CSR_ADDR_STVEC : std_logic_vector(11 downto 0) := x"105";
constant CSR_ADDR_SCOUNTEREN : std_logic_vector(11 downto 0) := x"106";
constant CSR_ADDR_SSCRATCH : std_logic_vector(11 downto 0) := x"140";
constant CSR_ADDR_SEPC : std_logic_vector(11 downto 0) := x"141";
constant CSR_ADDR_SCAUSE : std_logic_vector(11 downto 0) := x"142";
constant CSR_ADDR_STVAL : std_logic_vector(11 downto 0) := x"143";
constant CSR_ADDR_SIP : std_logic_vector(11 downto 0) := x"144";
constant CSR_ADDR_SATP : std_logic_vector(11 downto 0) := x"180";
constant CSR_ADDR_MVENDORID : std_logic_vector(11 downto 0) := x"f11";
constant CSR_ADDR_MARCHID : std_logic_vector(11 downto 0) := x"f12";
constant CSR_ADDR_MIMPID : std_logic_vector(11 downto 0) := x"f13";
constant CSR_ADDR_MHARTID : std_logic_vector(11 downto 0) := x"f14";
constant CSR_ADDR_MSTATUS : std_logic_vector(11 downto 0) := x"300";
constant CSR_ADDR_MISA : std_logic_vector(11 downto 0) := x"301";
constant CSR_ADDR_MEDELEG : std_logic_vector(11 downto 0) := x"302";
constant CSR_ADDR_MIDELEG : std_logic_vector(11 downto 0) := x"303";
constant CSR_ADDR_MIE : std_logic_vector(11 downto 0) := x"304";
constant CSR_ADDR_MTVEC : std_logic_vector(11 downto 0) := x"305";
constant CSR_ADDR_MCOUNTEREN : std_logic_vector(11 downto 0) := x"306";
constant CSR_ADDR_MSCRATCH : std_logic_vector(11 downto 0) := x"340";
constant CSR_ADDR_MEPC : std_logic_vector(11 downto 0) := x"341";
constant CSR_ADDR_MCAUSE : std_logic_vector(11 downto 0) := x"342";
constant CSR_ADDR_MTVAL : std_logic_vector(11 downto 0) := x"343";
constant CSR_ADDR_MIP : std_logic_vector(11 downto 0) := x"344";
constant CSR_ADDR_MCYCLE : std_logic_vector(11 downto 0) := x"b00";
constant CSR_ADDR_MINSTRET : std_logic_vector(11 downto 0) := x"b02";
constant CSR_ADDR_MHPMCOUNTER3 : std_logic_vector(11 downto 0) := x"b03";
constant CSR_ADDR_MHPMCOUNTER4 : std_logic_vector(11 downto 0) := x"b04";
constant CSR_ADDR_MHPMCOUNTER5 : std_logic_vector(11 downto 0) := x"b05";
constant CSR_ADDR_MHPMCOUNTER6 : std_logic_vector(11 downto 0) := x"b06";
constant CSR_ADDR_MHPMCOUNTER7 : std_logic_vector(11 downto 0) := x"b07";
constant CSR_ADDR_MHPMCOUNTER8 : std_logic_vector(11 downto 0) := x"b08";
constant CSR_ADDR_MHPMCOUNTER9 : std_logic_vector(11 downto 0) := x"b09";
constant CSR_ADDR_MHPMCOUNTER10 : std_logic_vector(11 downto 0) := x"b0a";
constant CSR_ADDR_MHPMCOUNTER11 : std_logic_vector(11 downto 0) := x"b0b";
constant CSR_ADDR_MHPMCOUNTER12 : std_logic_vector(11 downto 0) := x"b0c";
constant CSR_ADDR_MHPMCOUNTER13 : std_logic_vector(11 downto 0) := x"b0d";
constant CSR_ADDR_MHPMCOUNTER14 : std_logic_vector(11 downto 0) := x"b0e";
constant CSR_ADDR_MHPMCOUNTER15 : std_logic_vector(11 downto 0) := x"b0f";
constant CSR_ADDR_MHPMCOUNTER16 : std_logic_vector(11 downto 0) := x"b10";
constant CSR_ADDR_MHPMCOUNTER17 : std_logic_vector(11 downto 0) := x"b11";
constant CSR_ADDR_MHPMCOUNTER18 : std_logic_vector(11 downto 0) := x"b12";
constant CSR_ADDR_MHPMCOUNTER19 : std_logic_vector(11 downto 0) := x"b13";
constant CSR_ADDR_MHPMCOUNTER20 : std_logic_vector(11 downto 0) := x"b14";
constant CSR_ADDR_MHPMCOUNTER21 : std_logic_vector(11 downto 0) := x"b15";
constant CSR_ADDR_MHPMCOUNTER22 : std_logic_vector(11 downto 0) := x"b16";
constant CSR_ADDR_MHPMCOUNTER23 : std_logic_vector(11 downto 0) := x"b17";
constant CSR_ADDR_MHPMCOUNTER24 : std_logic_vector(11 downto 0) := x"b18";
constant CSR_ADDR_MHPMCOUNTER25 : std_logic_vector(11 downto 0) := x"b19";
constant CSR_ADDR_MHPMCOUNTER26 : std_logic_vector(11 downto 0) := x"b1a";
constant CSR_ADDR_MHPMCOUNTER27 : std_logic_vector(11 downto 0) := x"b1b";
constant CSR_ADDR_MHPMCOUNTER28 : std_logic_vector(11 downto 0) := x"b1c";
constant CSR_ADDR_MHPMCOUNTER29 : std_logic_vector(11 downto 0) := x"b1d";
constant CSR_ADDR_MHPMCOUNTER30 : std_logic_vector(11 downto 0) := x"b1e";
constant CSR_ADDR_MHPMCOUNTER31 : std_logic_vector(11 downto 0) := x"b1f";
constant CSR_ADDR_MHPMEVENT3 : std_logic_vector(11 downto 0) := x"323";
constant CSR_ADDR_MHPMEVENT4 : std_logic_vector(11 downto 0) := x"324";
constant CSR_ADDR_MHPMEVENT5 : std_logic_vector(11 downto 0) := x"325";
constant CSR_ADDR_MHPMEVENT6 : std_logic_vector(11 downto 0) := x"326";
constant CSR_ADDR_MHPMEVENT7 : std_logic_vector(11 downto 0) := x"327";
constant CSR_ADDR_MHPMEVENT8 : std_logic_vector(11 downto 0) := x"328";
constant CSR_ADDR_MHPMEVENT9 : std_logic_vector(11 downto 0) := x"329";
constant CSR_ADDR_MHPMEVENT10 : std_logic_vector(11 downto 0) := x"32a";
constant CSR_ADDR_MHPMEVENT11 : std_logic_vector(11 downto 0) := x"32b";
constant CSR_ADDR_MHPMEVENT12 : std_logic_vector(11 downto 0) := x"32c";
constant CSR_ADDR_MHPMEVENT13 : std_logic_vector(11 downto 0) := x"32d";
constant CSR_ADDR_MHPMEVENT14 : std_logic_vector(11 downto 0) := x"32e";
constant CSR_ADDR_MHPMEVENT15 : std_logic_vector(11 downto 0) := x"32f";
constant CSR_ADDR_MHPMEVENT16 : std_logic_vector(11 downto 0) := x"330";
constant CSR_ADDR_MHPMEVENT17 : std_logic_vector(11 downto 0) := x"331";
constant CSR_ADDR_MHPMEVENT18 : std_logic_vector(11 downto 0) := x"332";
constant CSR_ADDR_MHPMEVENT19 : std_logic_vector(11 downto 0) := x"333";
constant CSR_ADDR_MHPMEVENT20 : std_logic_vector(11 downto 0) := x"334";
constant CSR_ADDR_MHPMEVENT21 : std_logic_vector(11 downto 0) := x"335";
constant CSR_ADDR_MHPMEVENT22 : std_logic_vector(11 downto 0) := x"336";
constant CSR_ADDR_MHPMEVENT23 : std_logic_vector(11 downto 0) := x"337";
constant CSR_ADDR_MHPMEVENT24 : std_logic_vector(11 downto 0) := x"338";
constant CSR_ADDR_MHPMEVENT25 : std_logic_vector(11 downto 0) := x"339";
constant CSR_ADDR_MHPMEVENT26 : std_logic_vector(11 downto 0) := x"33a";
constant CSR_ADDR_MHPMEVENT27 : std_logic_vector(11 downto 0) := x"33b";
constant CSR_ADDR_MHPMEVENT28 : std_logic_vector(11 downto 0) := x"33c";
constant CSR_ADDR_MHPMEVENT29 : std_logic_vector(11 downto 0) := x"33d";
constant CSR_ADDR_MHPMEVENT30 : std_logic_vector(11 downto 0) := x"33e";
constant CSR_ADDR_MHPMEVENT31 : std_logic_vector(11 downto 0) := x"33f";
-- Privilege modes
constant USER_MODE : std_logic_vector(1 downto 0) := "00";
constant SUPERVISOR_MODE : std_logic_vector(1 downto 0) := "01";
constant MACHINE_MODE : std_logic_vector(1 downto 0) := "11";
-- Debug output bus
type regfile_arr is array (0 to 31) of doubleword;
-- Familiar names for instruction fields
subtype funct7_t is std_logic_vector(6 downto 0);
subtype opcode_t is std_logic_vector(6 downto 0);
subtype funct3_t is std_logic_vector(2 downto 0);
subtype funct6_t is std_logic_vector(5 downto 0);
subtype reg_t is std_logic_vector(4 downto 0);
-- Instruction type populated by decoder
subtype instr_t is std_logic_vector(7 downto 0);
-- Control types for ALU
subtype ctrl_t is std_logic_vector(5 downto 0);
-- Opcodes determine overall instruction families, thus
-- they are a logical way to group them.
-- Load upper immediate
constant LUI_T : opcode_t := "0110111";
-- Add upper immedaite to PC
constant AUIPC_T : opcode_t := "0010111";
-- Jump and link
constant JAL_T : opcode_t := "1101111";
-- Jump and link register
constant JALR_T : opcode_t := "1100111";
-- Branch types, general
constant BRANCH_T : opcode_t := "1100011";
-- Load types, includes all but atomic load and LUI
constant LOAD_T : opcode_t := "0000011";
-- Store types, includes all but atomic
constant STORE_T : opcode_t := "0100011";
-- ALU immediate types
constant ALUI_T : opcode_t := "0010011";
-- ALU types, includes integer mul/div
constant ALU_T : opcode_t := "0110011";
-- Special fence instructions
constant FENCE_T : opcode_t := "0001111";
-- CSR manipulation and ecalls
constant CSR_T : opcode_t := "1110011";
-- ALU types, low word
constant ALUW_T : opcode_t := "0111011";
-- ALU immediate types, low word
constant ALUIW_T : opcode_t := "0011011";
-- Atomic types
constant ATOM_T : opcode_t := "0101111";
-- Floating point load types
constant FLOAD_T : opcode_t := "0000111";
-- Floating point store types
constant FSTORE_T : opcode_t := "0100111";
-- Floating point multiply-then-add
constant FMADD_T : opcode_t := "1000011";
-- Floating point multiply-then-sub
constant FMSUB_T : opcode_t := "1000111";
-- Floating point negate-multiply-then-add
constant FNADD_T : opcode_t := "1001011";
-- Floating point negate-multiply-then-sub
constant FNSUB_T : opcode_t := "1001111";
-- Floating point arithmetic types
constant FPALU_T : opcode_t := "1010011";
-- Operation names for ALU
constant op_SLL : ctrl_t := "000000";
constant op_SLLI : ctrl_t := "000001";
constant op_SRL : ctrl_t := "000010";
constant op_SRLI : ctrl_t := "000011";
constant op_SRA : ctrl_t := "000100";
constant op_SRAI : ctrl_t := "000101";
constant op_ADD : ctrl_t := "000110";
constant op_ADDI : ctrl_t := "000111";
constant op_SUB : ctrl_t := "001000";
constant op_LUI : ctrl_t := "001001";
constant op_AUIPC : ctrl_t := "001010";
constant op_XOR : ctrl_t := "001011";
constant op_XORI : ctrl_t := "001100";
constant op_OR : ctrl_t := "001101";
constant op_ORI : ctrl_t := "001110";
constant op_AND : ctrl_t := "001111";
constant op_ANDI : ctrl_t := "010000";
constant op_SLT : ctrl_t := "010001";
constant op_SLTI : ctrl_t := "010010";
constant op_SLTU : ctrl_t := "010011";
constant op_SLTIU : ctrl_t := "010100";
constant op_SLLW : ctrl_t := "010101";
constant op_SLLIW : ctrl_t := "010110";
constant op_SRLW : ctrl_t := "010111";
constant op_SRLIW : ctrl_t := "011000";
constant op_SRAW : ctrl_t := "011001";
constant op_SRAIW : ctrl_t := "011010";
constant op_ADDW : ctrl_t := "011011";
constant op_ADDIW : ctrl_t := "011100";
constant op_SUBW : ctrl_t := "011101";
constant op_MUL : ctrl_t := "011110";
constant op_MULH : ctrl_t := "011111";
constant op_MULHU : ctrl_t := "100000";
constant op_MULHSU : ctrl_t := "100001";
constant op_DIV : ctrl_t := "100010";
constant op_DIVU : ctrl_t := "100011";
constant op_REM : ctrl_t := "100100";
constant op_REMU : ctrl_t := "100101";
constant op_MULW : ctrl_t := "100110";
constant op_DIVW : ctrl_t := "100111";
constant op_DIVUW : ctrl_t := "101000";
constant op_REMW : ctrl_t := "101001";
constant op_REMUW : ctrl_t := "101010";
-- Instruction names for core (see intr.py to generate)
constant instr_LUI : instr_t := "00000000";
constant instr_AUIPC : instr_t := "00000001";
constant instr_JAL : instr_t := "00000010";
constant instr_JALR : instr_t := "00000011";
constant instr_BEQ : instr_t := "00000100";
constant instr_BNE : instr_t := "00000101";
constant instr_BLT : instr_t := "00000110";
constant instr_BGE : instr_t := "00000111";
constant instr_BLTU : instr_t := "00001000";
constant instr_BGEU : instr_t := "00001001";
constant instr_LB : instr_t := "00001010";
constant instr_LH : instr_t := "00001011";
constant instr_LW : instr_t := "00001100";
constant instr_LBU : instr_t := "00001101";
constant instr_LHU : instr_t := "00001110";
constant instr_SB : instr_t := "00001111";
constant instr_SH : instr_t := "00010000";
constant instr_SW : instr_t := "00010001";
constant instr_ADDI : instr_t := "00010010";
constant instr_SLTI : instr_t := "00010011";
constant instr_SLTIU : instr_t := "00010100";
constant instr_XORI : instr_t := "00010101";
constant instr_ORI : instr_t := "00010110";
constant instr_ANDI : instr_t := "00010111";
constant instr_SLLI : instr_t := "00011000";
constant instr_SRLI : instr_t := "00011001";
constant instr_SRAI : instr_t := "00011010";
constant instr_ADD : instr_t := "00011011";
constant instr_SUB : instr_t := "00011100";
constant instr_SLL : instr_t := "00011101";
constant instr_SLT : instr_t := "00011110";
constant instr_SLTU : instr_t := "00011111";
constant instr_XOR : instr_t := "00100000";
constant instr_SRL : instr_t := "00100001";
constant instr_SRA : instr_t := "00100010";
constant instr_OR : instr_t := "00100011";
constant instr_AND : instr_t := "00100100";
constant instr_FENCE : instr_t := "00100101";
constant instr_FENCEI : instr_t := "00100110";
constant instr_ECALL : instr_t := "00100111";
constant instr_EBREAK : instr_t := "00101000";
constant instr_CSRRW : instr_t := "00101001";
constant instr_CSRRS : instr_t := "00101010";
constant instr_CSRRC : instr_t := "00101011";
constant instr_CSRRWI : instr_t := "00101100";
constant instr_CSRRSI : instr_t := "00101101";
constant instr_CSRRCI : instr_t := "00101110";
constant instr_LWU : instr_t := "00101111";
constant instr_LD : instr_t := "00110000";
constant instr_SD : instr_t := "00110001";
constant instr_SLLI6 : instr_t := "00110010";
constant instr_SRLI6 : instr_t := "00110011";
constant instr_SRAI6 : instr_t := "00110100";
constant instr_ADDIW : instr_t := "00110101";
constant instr_SLLIW : instr_t := "00110110";
constant instr_SRLIW : instr_t := "00110111";
constant instr_SRAIW : instr_t := "00111000";
constant instr_ADDW : instr_t := "00111001";
constant instr_SUBW : instr_t := "00111010";
constant instr_SLLW : instr_t := "00111011";
constant instr_SRLW : instr_t := "00111100";
constant instr_SRAW : instr_t := "00111101";
constant instr_MUL : instr_t := "00111110";
constant instr_MULH : instr_t := "00111111";
constant instr_MULHSU : instr_t := "01000000";
constant instr_MULHU : instr_t := "01000001";
constant instr_DIV : instr_t := "01000010";
constant instr_DIVU : instr_t := "01000011";
constant instr_REM : instr_t := "01000100";
constant instr_REMU : instr_t := "01000101";
constant instr_MULW : instr_t := "01000110";
constant instr_DIVW : instr_t := "01000111";
constant instr_DIVUW : instr_t := "01001000";
constant instr_REMW : instr_t := "01001001";
constant instr_REMUW : instr_t := "01001010";
constant instr_LRW : instr_t := "01001011";
constant instr_SCW : instr_t := "01001100";
constant instr_AMOSWAPW : instr_t := "01001101";
constant instr_AMOADDW : instr_t := "01001110";
constant instr_AMOXORW : instr_t := "01001111";
constant instr_AMOANDW : instr_t := "01010000";
constant instr_AMOORW : instr_t := "01010001";
constant instr_AMOMINW : instr_t := "01010010";
constant instr_AMOMAXW : instr_t := "01010011";
constant instr_AMOMINUW : instr_t := "01010100";
constant instr_AMOMAXUW : instr_t := "01010101";
constant instr_LRD : instr_t := "01010110";
constant instr_SCD : instr_t := "01010111";
constant instr_AMOSWAPD : instr_t := "01011000";
constant instr_AMOADDD : instr_t := "01011001";
constant instr_AMOXORD : instr_t := "01011010";
constant instr_AMOANDD : instr_t := "01011011";
constant instr_AMOORD : instr_t := "01011100";
constant instr_AMOMIND : instr_t := "01011101";
constant instr_AMOMAXD : instr_t := "01011110";
constant instr_AMOMINUD : instr_t := "01011111";
constant instr_AMOMAXUD : instr_t := "01100000";
constant instr_FLW : instr_t := "01100001";
constant instr_FSW : instr_t := "01100010";
constant instr_FMADDS : instr_t := "01100011";
constant instr_FMSUBS : instr_t := "01100100";
constant instr_FNMSUBS : instr_t := "01100101";
constant instr_FNMADDS : instr_t := "01100110";
constant instr_FADDS : instr_t := "01100111";
constant instr_FSUBS : instr_t := "01101000";
constant instr_FMULS : instr_t := "01101001";
constant instr_FDIVS : instr_t := "01101010";
constant instr_FSQRTS : instr_t := "01101011";
constant instr_FSGNJS : instr_t := "01101100";
constant instr_FSGNJNS : instr_t := "01101101";
constant instr_FSGNJXS : instr_t := "01101110";
constant instr_FMINS : instr_t := "01101111";
constant instr_FMAXS : instr_t := "01110000";
constant instr_FCVTWS : instr_t := "01110001";
constant instr_FCVTWUS : instr_t := "01110010";
constant instr_FMVXW : instr_t := "01110011";
constant instr_FEQS : instr_t := "01110100";
constant instr_FLTS : instr_t := "01110101";
constant instr_FLES : instr_t := "01110110";
constant instr_FCLASSS : instr_t := "01110111";
constant instr_FCVTSW : instr_t := "01111000";
constant instr_FCVTSWU : instr_t := "01111001";
constant instr_FMVWX : instr_t := "01111010";
constant instr_FCVTLS : instr_t := "01111011";
constant instr_FCVTLUS : instr_t := "01111100";
constant instr_FCVTSL : instr_t := "01111101";
constant instr_FCVTSLU : instr_t := "01111110";
constant instr_FLD : instr_t := "01111111";
constant instr_FSD : instr_t := "10000000";
constant instr_FMADDD : instr_t := "10000001";
constant instr_FMSUBD : instr_t := "10000010";
constant instr_FNMSUBD : instr_t := "10000011";
constant instr_FNMADDD : instr_t := "10000100";
constant instr_FADDD : instr_t := "10000101";
constant instr_FSUBD : instr_t := "10000110";
constant instr_FMULD : instr_t := "10000111";
constant instr_FDIVD : instr_t := "10001000";
constant instr_FSQRTD : instr_t := "10001001";
constant instr_FSGNJD : instr_t := "10001010";
constant instr_FSGNJND : instr_t := "10001011";
constant instr_FSGNJXD : instr_t := "10001100";
constant instr_FMIND : instr_t := "10001101";
constant instr_FMAXD : instr_t := "10001110";
constant instr_FCVTSD : instr_t := "10001111";
constant instr_FCVTDS : instr_t := "10010000";
constant instr_FEQD : instr_t := "10010001";
constant instr_FLTD : instr_t := "10010010";
constant instr_FLED : instr_t := "10010011";
constant instr_FCLASSD : instr_t := "10010100";
constant instr_FCVTWD : instr_t := "10010101";
constant instr_FCVTWUD : instr_t := "10010110";
constant instr_FCVTDW : instr_t := "10010111";
constant instr_FCVTDWU : instr_t := "10011000";
constant instr_FCVTLD : instr_t := "10011001";
constant instr_FCVTLUD : instr_t := "10011010";
constant instr_FMVXD : instr_t := "10011011";
constant instr_FCVTDL : instr_t := "10011100";
constant instr_FCVTDLU : instr_t := "10011101";
constant instr_FMVDX : instr_t := "10011110";
constant instr_URET : instr_t := "10011111";
constant instr_SRET : instr_t := "10100000";
constant instr_MRET : instr_t := "10100001";
constant instr_WFI : instr_t := "10100010";
constant instr_SFENCEVM : instr_t := "10100011";
-- Forward declare static functions
function CSR_write(CSR: natural; value: doubleword) return doubleword;
function CSR_read(CSR: natural; value: doubleword) return doubleword;
function HEX_TO_ASCII(word: std_logic_vector(3 downto 0)) return std_logic_vector;
function ASCII_TO_HEX(word: std_logic_vector(7 downto 0)) return integer;
end package config;
-- Package body defined derived constants and subroutines (i.e. functions)
package body config is
-- TODO - Might need additional parameters to specify the privilege mode, double check
-- CSR function for writing as a function of CSR register
--@param CSR The familiar name of the CSR register, encoded above in the package declaration
--@param value The raw value to be written
--@return the modified value to be written back the the given CSR
function CSR_write(CSR: natural; value: doubleword) return doubleword is
begin
return zero_word & zero_word;
end;
-- CSR function for reading as a function of CSR register
--@param CSR The familiar name of the CSR register, encoded above in the package declaration
--@param value The raw contents of the given CSR
--@return the adjusted value of the CSR to be reported back
function CSR_read(CSR: natural; value: doubleword) return doubleword is
begin
return value;
end;
function HEX_TO_ASCII(word: std_logic_vector(3 downto 0)) return std_logic_vector is
begin
if(unsigned(word) < 10) then
return "0011" & word;
elsif(unsigned(word) = 11) then
return "01100001";
elsif(unsigned(word) = 12) then
return "01100010";
elsif(unsigned(word) = 13) then
return "01100011";
elsif(unsigned(word) = 14) then
return "01100100";
elsif(unsigned(word) = 15) then
return "01100100";
else
return "00110000";
end if;
end;
-- Takes an ASCII character and returns an integer value
function ASCII_TO_HEX(word: std_logic_vector(7 downto 0)) return integer is
begin
if(unsigned(word) > 47 AND unsigned(word) < 58) then
return to_integer(unsigned(word)) - 48;
elsif(unsigned(word) > 96 AND unsigned(word) < 103) then
-- We want to return 11 for a, 12 for b, so on
return to_integer(unsigned(word)) - 86;
else --Which happens when the user puts garbage in
return 99;
end if;
end;
end config;
|
-- -----------------------------------------------------------------------
--
-- This is a table driven 65Cx2 core by A.Daly
-- This is a derivative of the excellent FPGA64 core see below
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2008 by Peter Wendrich ([email protected])
-- http://www.syntiac.com/fpga64.html
-- -----------------------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
entity R65C02 is
port (
reset : in std_logic;
clk : in std_logic;
enable : in std_logic;
nmi_n : in std_logic;
irq_n : in std_logic;
di : in unsigned(7 downto 0);
do : out unsigned(7 downto 0);
addr : out unsigned(15 downto 0);
nwe : out std_logic;
sync : out std_logic;
sync_irq : out std_logic;
-- 6502 registers (MSB) PC, SP, P, Y, X, A (LSB)
Regs : out std_logic_vector(63 downto 0)
);
end R65C02;
-- Store Zp (3) => fetch, cycle2, cycleEnd
-- Store Zp,x (4) => fetch, cycle2, preWrite, cycleEnd
-- Read Zp,x (4) => fetch, cycle2, cycleRead, cycleRead2
-- Rmw Zp,x (6) => fetch, cycle2, cycleRead, cycleRead2, cycleRmw, cycleEnd
-- Store Abs (4) => fetch, cycle2, cycle3, cycleEnd
-- Store Abs,x (5) => fetch, cycle2, cycle3, preWrite, cycleEnd
-- Rts (6) => fetch, cycle2, cycle3, cycleRead, cycleJump, cycleIncrEnd
-- Rti (6) => fetch, cycle2, stack1, stack2, stack3, cycleJump
-- Jsr (6) => fetch, cycle2, .. cycle5, cycle6, cycleJump
-- Jmp abs (-) => fetch, cycle2, .., cycleJump
-- Jmp (ind) (-) => fetch, cycle2, .., cycleJump
-- Brk / irq (6) => fetch, cycle2, stack2, stack3, stack4
-- -----------------------------------------------------------------------
architecture Behavioral of R65C02 is
-- signal counter : unsigned(27 downto 0);
-- signal mask_irq : std_logic;
-- signal mask_enable : std_logic;
-- Statemachine
type cpuCycles is (
opcodeFetch, -- New opcode is read and registers updated
cycle2,
cycle3,
cyclePreIndirect,
cycleIndirect,
cycleBranchTaken,
cycleBranchPage,
cyclePreRead, -- Cycle before read while doing zeropage indexed addressing.
cycleRead, -- Read cycle
cycleRead2, -- Second read cycle after page-boundary crossing.
cycleRmw, -- Calculate ALU output for read-modify-write instr.
cyclePreWrite, -- Cycle before write when doing indexed addressing.
cycleWrite, -- Write cycle for zeropage or absolute addressing.
cycleStack1,
cycleStack2,
cycleStack3,
cycleStack4,
cycleJump, -- Last cycle of Jsr, Jmp. Next fetch address is target addr.
cycleEnd
);
signal theCpuCycle : cpuCycles;
signal nextCpuCycle : cpuCycles;
signal updateRegisters : boolean;
signal processIrq : std_logic;
signal nmiReg: std_logic;
signal nmiEdge: std_logic;
signal irqReg : std_logic; -- Delay IRQ input with one clock cycle.
signal soReg : std_logic; -- SO pin edge detection
-- Opcode decoding
constant opcUpdateA : integer := 0;
constant opcUpdateX : integer := 1;
constant opcUpdateY : integer := 2;
constant opcUpdateS : integer := 3;
constant opcUpdateN : integer := 4;
constant opcUpdateV : integer := 5;
constant opcUpdateD : integer := 6;
constant opcUpdateI : integer := 7;
constant opcUpdateZ : integer := 8;
constant opcUpdateC : integer := 9;
constant opcSecondByte : integer := 10;
constant opcAbsolute : integer := 11;
constant opcZeroPage : integer := 12;
constant opcIndirect : integer := 13;
constant opcStackAddr : integer := 14; -- Push/Pop address
constant opcStackData : integer := 15; -- Push/Pop status/data
constant opcJump : integer := 16;
constant opcBranch : integer := 17;
constant indexX : integer := 18;
constant indexY : integer := 19;
constant opcStackUp : integer := 20;
constant opcWrite : integer := 21;
constant opcRmw : integer := 22;
constant opcIncrAfter : integer := 23; -- Insert extra cycle to increment PC (RTS)
constant opcRti : integer := 24;
constant opcIRQ : integer := 25;
constant opcInA : integer := 26;
constant opcInBrk : integer := 27;
constant opcInX : integer := 28;
constant opcInY : integer := 29;
constant opcInS : integer := 30;
constant opcInT : integer := 31;
constant opcInH : integer := 32;
constant opcInClear : integer := 33;
constant aluMode1From : integer := 34;
--
constant aluMode1To : integer := 37;
constant aluMode2From : integer := 38;
--
constant aluMode2To : integer := 40;
--
constant opcInCmp : integer := 41;
constant opcInCpx : integer := 42;
constant opcInCpy : integer := 43;
subtype addrDef is unsigned(0 to 15);
--
-- is Interrupt -----------------+
-- instruction is RTI ----------------+|
-- PC++ on last cycle (RTS) ---------------+||
-- RMW --------------+|||
-- Write -------------+||||
-- Pop/Stack up -------------+|||||
-- Branch ---------+ ||||||
-- Jump ----------+| ||||||
-- Push or Pop data -------+|| ||||||
-- Push or Pop addr ------+||| ||||||
-- Indirect -----+|||| ||||||
-- ZeroPage ----+||||| ||||||
-- Absolute ---+|||||| ||||||
-- PC++ on cycle2 --+||||||| ||||||
-- |AZI||JBXY|WM|||
constant immediate : addrDef := "1000000000000000";
constant implied : addrDef := "0000000000000000";
-- Zero page
constant readZp : addrDef := "1010000000000000";
constant writeZp : addrDef := "1010000000010000";
constant rmwZp : addrDef := "1010000000001000";
-- Zero page indexed
constant readZpX : addrDef := "1010000010000000";
constant writeZpX : addrDef := "1010000010010000";
constant rmwZpX : addrDef := "1010000010001000";
constant readZpY : addrDef := "1010000001000000";
constant writeZpY : addrDef := "1010000001010000";
constant rmwZpY : addrDef := "1010000001001000";
-- Zero page indirect
constant readIndX : addrDef := "1001000010000000";
constant writeIndX : addrDef := "1001000010010000";
constant rmwIndX : addrDef := "1001000010001000";
constant readIndY : addrDef := "1001000001000000";
constant writeIndY : addrDef := "1001000001010000";
constant rmwIndY : addrDef := "1001000001001000";
constant rmwInd : addrDef := "1001000000001000";
constant readInd : addrDef := "1001000000000000";
constant writeInd : addrDef := "1001000000010000";
-- |AZI||JBXY|WM||
-- Absolute
constant readAbs : addrDef := "1100000000000000";
constant writeAbs : addrDef := "1100000000010000";
constant rmwAbs : addrDef := "1100000000001000";
constant readAbsX : addrDef := "1100000010000000";
constant writeAbsX : addrDef := "1100000010010000";
constant rmwAbsX : addrDef := "1100000010001000";
constant readAbsY : addrDef := "1100000001000000";
constant writeAbsY : addrDef := "1100000001010000";
constant rmwAbsY : addrDef := "1100000001001000";
-- PHA PHP
constant push : addrDef := "0000010000000000";
-- PLA PLP
constant pop : addrDef := "0000010000100000";
-- Jumps
constant jsr : addrDef := "1000101000000000";
constant jumpAbs : addrDef := "1000001000000000";
constant jumpInd : addrDef := "1100001000000000";
constant jumpIndX : addrDef := "1100001010000000";
constant relative : addrDef := "1000000100000000";
-- Specials
constant rts : addrDef := "0000101000100100";
constant rti : addrDef := "0000111000100010";
constant brk : addrDef := "1000111000000001";
-- constant irq : addrDef := "0000111000000001";
-- constant : unsigned(0 to 0) := "0";
constant xxxxxxxx : addrDef := "----------0---00";
-- A = accu
-- X = index X
-- Y = index Y
-- S = Stack pointer
-- H = indexH
--
-- AEXYSTHc
constant aluInA : unsigned(0 to 7) := "10000000";
constant aluInBrk : unsigned(0 to 7) := "01000000";
constant aluInX : unsigned(0 to 7) := "00100000";
constant aluInY : unsigned(0 to 7) := "00010000";
constant aluInS : unsigned(0 to 7) := "00001000";
constant aluInT : unsigned(0 to 7) := "00000100";
constant aluInClr : unsigned(0 to 7) := "00000001";
constant aluInSet : unsigned(0 to 7) := "00000000";
constant aluInXXX : unsigned(0 to 7) := "--------";
-- Most of the aluModes are just like the opcodes.
-- aluModeInp -> input is output. calculate N and Z
-- aluModeCmp -> Compare for CMP, CPX, CPY
-- aluModeFlg -> input to flags needed for PLP, RTI and CLC, SEC, CLV
-- aluModeInc -> for INC but also INX, INY
-- aluModeDec -> for DEC but also DEX, DEY
subtype aluMode1 is unsigned(0 to 3);
subtype aluMode2 is unsigned(0 to 2);
subtype aluMode is unsigned(0 to 9);
-- Logic/Shift ALU
constant aluModeInp : aluMode1 := "0000";
constant aluModeP : aluMode1 := "0001";
constant aluModeInc : aluMode1 := "0010";
constant aluModeDec : aluMode1 := "0011";
constant aluModeFlg : aluMode1 := "0100";
constant aluModeBit : aluMode1 := "0101";
-- 0110
-- 0111
constant aluModeLsr : aluMode1 := "1000";
constant aluModeRor : aluMode1 := "1001";
constant aluModeAsl : aluMode1 := "1010";
constant aluModeRol : aluMode1 := "1011";
constant aluModeTSB : aluMode1 := "1100";
constant aluModeTRB : aluMode1 := "1101";
-- 1110
-- 1111;
-- Arithmetic ALU
constant aluModePss : aluMode2 := "000";
constant aluModeCmp : aluMode2 := "001";
constant aluModeAdc : aluMode2 := "010";
constant aluModeSbc : aluMode2 := "011";
constant aluModeAnd : aluMode2 := "100";
constant aluModeOra : aluMode2 := "101";
constant aluModeEor : aluMode2 := "110";
constant aluModeNoF : aluMode2 := "111";
--aluModeBRK
--constant aluBrk : aluMode := aluModeBRK & aluModePss & "---";
--constant aluFix : aluMode := aluModeInp & aluModeNoF & "---";
constant aluInp : aluMode := aluModeInp & aluModePss & "---";
constant aluP : aluMode := aluModeP & aluModePss & "---";
constant aluInc : aluMode := aluModeInc & aluModePss & "---";
constant aluDec : aluMode := aluModeDec & aluModePss & "---";
constant aluFlg : aluMode := aluModeFlg & aluModePss & "---";
constant aluBit : aluMode := aluModeBit & aluModeAnd & "---";
constant aluRor : aluMode := aluModeRor & aluModePss & "---";
constant aluLsr : aluMode := aluModeLsr & aluModePss & "---";
constant aluRol : aluMode := aluModeRol & aluModePss & "---";
constant aluAsl : aluMode := aluModeAsl & aluModePss & "---";
constant aluTSB : aluMode := aluModeTSB & aluModePss & "---";
constant aluTRB : aluMode := aluModeTRB & aluModePss & "---";
constant aluCmp : aluMode := aluModeInp & aluModeCmp & "100";
constant aluCpx : aluMode := aluModeInp & aluModeCmp & "010";
constant aluCpy : aluMode := aluModeInp & aluModeCmp & "001";
constant aluAdc : aluMode := aluModeInp & aluModeAdc & "---";
constant aluSbc : aluMode := aluModeInp & aluModeSbc & "---";
constant aluAnd : aluMode := aluModeInp & aluModeAnd & "---";
constant aluOra : aluMode := aluModeInp & aluModeOra & "---";
constant aluEor : aluMode := aluModeInp & aluModeEor & "---";
constant aluXXX : aluMode := (others => '-');
-- Stack operations. Push/Pop/None
constant stackInc : unsigned(0 to 0) := "0";
constant stackDec : unsigned(0 to 0) := "1";
constant stackXXX : unsigned(0 to 0) := "-";
subtype decodedBitsDef is unsigned(0 to 43);
type opcodeInfoTableDef is array(0 to 255) of decodedBitsDef;
constant opcodeInfoTable : opcodeInfoTableDef := (
-- +------- Update register A
-- |+------ Update register X
-- ||+----- Update register Y
-- |||+---- Update register S
-- |||| +-- Update Flags
-- |||| |
-- |||| _|__
-- |||| / \
-- AXYS NVDIZC addressing aluInput aluMode
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "001100" & brk & aluInBrk & aluP, -- 00 BRK
"1000" & "100010" & readIndX & aluInT & aluOra, -- 01 ORA (zp,x)
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- 02 NOP ------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 03 NOP ------- 65C02
"0000" & "000010" & rmwZp & aluInT & aluTSB, -- 04 TSB zp ----------- 65C02
"1000" & "100010" & readZp & aluInT & aluOra, -- 05 ORA zp
"0000" & "100011" & rmwZp & aluInT & aluAsl, -- 06 ASL zp
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 07 NOP ------- 65C02
"0000" & "000000" & push & aluInXXX & aluP, -- 08 PHP
"1000" & "100010" & immediate & aluInT & aluOra, -- 09 ORA imm
"1000" & "100011" & implied & aluInA & aluAsl, -- 0A ASL accu
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 0B NOP ------- 65C02
"0000" & "000010" & rmwAbs & aluInT & aluTSB, -- 0C TSB abs ---------- 65C02
"1000" & "100010" & readAbs & aluInT & aluOra, -- 0D ORA abs
"0000" & "100011" & rmwAbs & aluInT & aluAsl, -- 0E ASL abs
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 0F NOP ------- 65C02
"0000" & "000000" & relative & aluInXXX & aluXXX, -- 10 BPL
"1000" & "100010" & readIndY & aluInT & aluOra, -- 11 ORA (zp),y
"1000" & "100010" & readInd & aluInT & aluOra, -- 12 ORA (zp) --------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 13 NOP ------- 65C02
"0000" & "000010" & rmwZp & aluInT & aluTRB, -- 14 TRB zp ~---------- 65C02
"1000" & "100010" & readZpX & aluInT & aluOra, -- 15 ORA zp,x
"0000" & "100011" & rmwZpX & aluInT & aluAsl, -- 16 ASL zp,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 17 NOP ------- 65C02
"0000" & "000001" & implied & aluInClr & aluFlg, -- 18 CLC
"1000" & "100010" & readAbsY & aluInT & aluOra, -- 19 ORA abs,y
"1000" & "100010" & implied & aluInA & aluInc, -- 1A INC accu --------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 1B NOP ------- 65C02
"0000" & "000010" & rmwAbs & aluInT & aluTRB, -- 1C TRB abs ~----- --- 65C02
"1000" & "100010" & readAbsX & aluInT & aluOra, -- 1D ORA abs,x
"0000" & "100011" & rmwAbsX & aluInT & aluAsl, -- 1E ASL abs,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 1F NOP ------- 65C02
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "000000" & jsr & aluInXXX & aluXXX, -- 20 JSR
"1000" & "100010" & readIndX & aluInT & aluAnd, -- 21 AND (zp,x)
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- 22 NOP ------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 23 NOP ------- 65C02
"0000" & "110010" & readZp & aluInT & aluBit, -- 24 BIT zp
"1000" & "100010" & readZp & aluInT & aluAnd, -- 25 AND zp
"0000" & "100011" & rmwZp & aluInT & aluRol, -- 26 ROL zp
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 27 NOP ------- 65C02
"0000" & "111111" & pop & aluInT & aluFlg, -- 28 PLP
"1000" & "100010" & immediate & aluInT & aluAnd, -- 29 AND imm
"1000" & "100011" & implied & aluInA & aluRol, -- 2A ROL accu
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 2B NOP ------- 65C02
"0000" & "110010" & readAbs & aluInT & aluBit, -- 2C BIT abs
"1000" & "100010" & readAbs & aluInT & aluAnd, -- 2D AND abs
"0000" & "100011" & rmwAbs & aluInT & aluRol, -- 2E ROL abs
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 2F NOP ------- 65C02
"0000" & "000000" & relative & aluInXXX & aluXXX, -- 30 BMI
"1000" & "100010" & readIndY & aluInT & aluAnd, -- 31 AND (zp),y
"1000" & "100010" & readInd & aluInT & aluAnd, -- 32 AND (zp) -------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 33 NOP ------- 65C02
"0000" & "110010" & readZpX & aluInT & aluBit, -- 34 BIT zp,x -------- 65C02
"1000" & "100010" & readZpX & aluInT & aluAnd, -- 35 AND zp,x
"0000" & "100011" & rmwZpX & aluInT & aluRol, -- 36 ROL zp,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 37 NOP ------- 65C02
"0000" & "000001" & implied & aluInSet & aluFlg, -- 38 SEC
"1000" & "100010" & readAbsY & aluInT & aluAnd, -- 39 AND abs,y
"1000" & "100010" & implied & aluInA & aluDec, -- 3A DEC accu -------- 65C12
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 3B NOP ------- 65C02
"0000" & "110010" & readAbsX & aluInT & aluBit, -- 3C BIT abs,x ------- 65C02
"1000" & "100010" & readAbsX & aluInT & aluAnd, -- 3D AND abs,x
"0000" & "100011" & rmwAbsX & aluInT & aluRol, -- 3E ROL abs,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 3F NOP ------- 65C02
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "111111" & rti & aluInT & aluFlg, -- 40 RTI
"1000" & "100010" & readIndX & aluInT & aluEor, -- 41 EOR (zp,x)
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- 42 NOP ------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 43 NOP ------- 65C02
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- 44 NOP ------- 65C02
"1000" & "100010" & readZp & aluInT & aluEor, -- 45 EOR zp
"0000" & "100011" & rmwZp & aluInT & aluLsr, -- 46 LSR zp
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 47 NOP ------- 65C02
"0000" & "000000" & push & aluInA & aluInp, -- 48 PHA
"1000" & "100010" & immediate & aluInT & aluEor, -- 49 EOR imm
"1000" & "100011" & implied & aluInA & aluLsr, -- 4A LSR accu -------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 4B NOP ------- 65C02
"0000" & "000000" & jumpAbs & aluInXXX & aluXXX, -- 4C JMP abs
"1000" & "100010" & readAbs & aluInT & aluEor, -- 4D EOR abs
"0000" & "100011" & rmwAbs & aluInT & aluLsr, -- 4E LSR abs
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 4F NOP ------- 65C02
"0000" & "000000" & relative & aluInXXX & aluXXX, -- 50 BVC
"1000" & "100010" & readIndY & aluInT & aluEor, -- 51 EOR (zp),y
"1000" & "100010" & readInd & aluInT & aluEor, -- 52 EOR (zp) -------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 53 NOP ------- 65C02
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- 54 NOP ------- 65C02
"1000" & "100010" & readZpX & aluInT & aluEor, -- 55 EOR zp,x
"0000" & "100011" & rmwZpX & aluInT & aluLsr, -- 56 LSR zp,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 57 NOP ------- 65C02
"0000" & "000100" & implied & aluInClr & aluXXX, -- 58 CLI
"1000" & "100010" & readAbsY & aluInT & aluEor, -- 59 EOR abs,y
"0000" & "000000" & push & aluInY & aluInp, -- 5A PHY ------------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 5B NOP ------- 65C02
"0000" & "000000" & readAbs & aluInXXX & aluXXX, -- 5C NOP ------- 65C02
"1000" & "100010" & readAbsX & aluInT & aluEor, -- 5D EOR abs,x
"0000" & "100011" & rmwAbsX & aluInT & aluLsr, -- 5E LSR abs,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 5F NOP ------- 65C02
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "000000" & rts & aluInXXX & aluXXX, -- 60 RTS
"1000" & "110011" & readIndX & aluInT & aluAdc, -- 61 ADC (zp,x)
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- 62 NOP ------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 63 NOP ------- 65C02
"0000" & "000000" & writeZp & aluInClr & aluInp, -- 64 STZ zp ---------- 65C02
"1000" & "110011" & readZp & aluInT & aluAdc, -- 65 ADC zp
"0000" & "100011" & rmwZp & aluInT & aluRor, -- 66 ROR zp
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 67 NOP ------- 65C02
"1000" & "100010" & pop & aluInT & aluInp, -- 68 PLA
"1000" & "110011" & immediate & aluInT & aluAdc, -- 69 ADC imm
"1000" & "100011" & implied & aluInA & aluRor, -- 6A ROR accu
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 6B NOP ------ 65C02
"0000" & "000000" & jumpInd & aluInXXX & aluXXX, -- 6C JMP indirect
"1000" & "110011" & readAbs & aluInT & aluAdc, -- 6D ADC abs
"0000" & "100011" & rmwAbs & aluInT & aluRor, -- 6E ROR abs
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 6F NOP ------ 65C02
"0000" & "000000" & relative & aluInXXX & aluXXX, -- 70 BVS
"1000" & "110011" & readIndY & aluInT & aluAdc, -- 71 ADC (zp),y
"1000" & "110011" & readInd & aluInT & aluAdc, -- 72 ADC (zp) -------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 73 NOP ------ 65C02
"0000" & "000000" & writeZpX & aluInClr & aluInp, -- 74 STZ zp,x -------- 65C02
"1000" & "110011" & readZpX & aluInT & aluAdc, -- 75 ADC zp,x
"0000" & "100011" & rmwZpX & aluInT & aluRor, -- 76 ROR zp,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 77 NOP ----- 65C02
"0000" & "000100" & implied & aluInSet & aluXXX, -- 78 SEI
"1000" & "110011" & readAbsY & aluInT & aluAdc, -- 79 ADC abs,y
"0010" & "100010" & pop & aluInT & aluInp, -- 7A PLY ------------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 7B NOP ----- 65C02
"0000" & "000000" & jumpIndX & aluInXXX & aluXXX, -- 7C JMP indirect,x -- 65C02
--"0000" & "000000" & jumpInd & aluInXXX & aluXXX, -- 6C JMP indirect
"1000" & "110011" & readAbsX & aluInT & aluAdc, -- 7D ADC abs,x
"0000" & "100011" & rmwAbsX & aluInT & aluRor, -- 7E ROR abs,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 7F NOP ----- 65C02
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "000000" & relative & aluInXXX & aluXXX, -- 80 BRA ----------- 65C02
"0000" & "000000" & writeIndX & aluInA & aluInp, -- 81 STA (zp,x)
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- 82 NOP ----- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 83 NOP ----- 65C02
"0000" & "000000" & writeZp & aluInY & aluInp, -- 84 STY zp
"0000" & "000000" & writeZp & aluInA & aluInp, -- 85 STA zp
"0000" & "000000" & writeZp & aluInX & aluInp, -- 86 STX zp
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 87 NOP ----- 65C02
"0010" & "100010" & implied & aluInY & aluDec, -- 88 DEY
"0000" & "000010" & immediate & aluInT & aluBit, -- 89 BIT imm ------- 65C02
"1000" & "100010" & implied & aluInX & aluInp, -- 8A TXA
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 8B NOP ----- 65C02
"0000" & "000000" & writeAbs & aluInY & aluInp, -- 8C STY abs ------- 65C02
"0000" & "000000" & writeAbs & aluInA & aluInp, -- 8D STA abs
"0000" & "000000" & writeAbs & aluInX & aluInp, -- 8E STX abs
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 8F NOP ----- 65C02
"0000" & "000000" & relative & aluInXXX & aluXXX, -- 90 BCC
"0000" & "000000" & writeIndY & aluInA & aluInp, -- 91 STA (zp),y
"0000" & "000000" & writeInd & aluInA & aluInp, -- 92 STA (zp) ------ 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 93 NOP ----- 65C02
"0000" & "000000" & writeZpX & aluInY & aluInp, -- 94 STY zp,x
"0000" & "000000" & writeZpX & aluInA & aluInp, -- 95 STA zp,x
"0000" & "000000" & writeZpY & aluInX & aluInp, -- 96 STX zp,y
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 97 NOP ----- 65C02
"1000" & "100010" & implied & aluInY & aluInp, -- 98 TYA
"0000" & "000000" & writeAbsY & aluInA & aluInp, -- 99 STA abs,y
"0001" & "000000" & implied & aluInX & aluInp, -- 9A TXS
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 9B NOP ----- 65C02
"0000" & "000000" & writeAbs & aluInClr & aluInp, -- 9C STZ Abs ------- 65C02
"0000" & "000000" & writeAbsX & aluInA & aluInp, -- 9D STA abs,x
"0000" & "000000" & writeAbsX & aluInClr & aluInp, -- 9C STZ Abs,x ----- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 9F NOP ----- 65C02
-- AXYS NVDIZC addressing aluInput aluMode
"0010" & "100010" & immediate & aluInT & aluInp, -- A0 LDY imm
"1000" & "100010" & readIndX & aluInT & aluInp, -- A1 LDA (zp,x)
"0100" & "100010" & immediate & aluInT & aluInp, -- A2 LDX imm
"0000" & "000000" & implied & aluInXXX & aluXXX, -- A3 NOP ----- 65C02
"0010" & "100010" & readZp & aluInT & aluInp, -- A4 LDY zp
"1000" & "100010" & readZp & aluInT & aluInp, -- A5 LDA zp
"0100" & "100010" & readZp & aluInT & aluInp, -- A6 LDX zp
"0000" & "000000" & implied & aluInXXX & aluXXX, -- A7 NOP ----- 65C02
"0010" & "100010" & implied & aluInA & aluInp, -- A8 TAY
"1000" & "100010" & immediate & aluInT & aluInp, -- A9 LDA imm
"0100" & "100010" & implied & aluInA & aluInp, -- AA TAX
"0000" & "000000" & implied & aluInXXX & aluXXX, -- AB NOP ----- 65C02
"0010" & "100010" & readAbs & aluInT & aluInp, -- AC LDY abs
"1000" & "100010" & readAbs & aluInT & aluInp, -- AD LDA abs
"0100" & "100010" & readAbs & aluInT & aluInp, -- AE LDX abs
"0000" & "000000" & implied & aluInXXX & aluXXX, -- AF NOP ----- 65C02
"0000" & "000000" & relative & aluInXXX & aluXXX, -- B0 BCS
"1000" & "100010" & readIndY & aluInT & aluInp, -- B1 LDA (zp),y
"1000" & "100010" & readInd & aluInT & aluInp, -- B2 LDA (zp) ------ 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- B3 NOP ----- 65C02
"0010" & "100010" & readZpX & aluInT & aluInp, -- B4 LDY zp,x
"1000" & "100010" & readZpX & aluInT & aluInp, -- B5 LDA zp,x
"0100" & "100010" & readZpY & aluInT & aluInp, -- B6 LDX zp,y
"0000" & "000000" & implied & aluInXXX & aluXXX, -- B7 NOP ----- 65C02
"0000" & "010000" & implied & aluInClr & aluFlg, -- B8 CLV
"1000" & "100010" & readAbsY & aluInT & aluInp, -- B9 LDA abs,y
"0100" & "100010" & implied & aluInS & aluInp, -- BA TSX
"0000" & "000000" & implied & aluInXXX & aluXXX, -- BB NOP ----- 65C02
"0010" & "100010" & readAbsX & aluInT & aluInp, -- BC LDY abs,x
"1000" & "100010" & readAbsX & aluInT & aluInp, -- BD LDA abs,x
"0100" & "100010" & readAbsY & aluInT & aluInp, -- BE LDX abs,y
"0000" & "000000" & implied & aluInXXX & aluXXX, -- BF NOP ----- 65C02
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "100011" & immediate & aluInT & aluCpy, -- C0 CPY imm
"0000" & "100011" & readIndX & aluInT & aluCmp, -- C1 CMP (zp,x)
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- C2 NOP ----- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- C3 NOP ----- 65C02
"0000" & "100011" & readZp & aluInT & aluCpy, -- C4 CPY zp
"0000" & "100011" & readZp & aluInT & aluCmp, -- C5 CMP zp
"0000" & "100010" & rmwZp & aluInT & aluDec, -- C6 DEC zp
"0000" & "000000" & implied & aluInXXX & aluXXX, -- C7 NOP ----- 65C02
"0010" & "100010" & implied & aluInY & aluInc, -- C8 INY
"0000" & "100011" & immediate & aluInT & aluCmp, -- C9 CMP imm
"0100" & "100010" & implied & aluInX & aluDec, -- CA DEX
"0000" & "000000" & implied & aluInXXX & aluXXX, -- CB NOP ----- 65C02
"0000" & "100011" & readAbs & aluInT & aluCpy, -- CC CPY abs
"0000" & "100011" & readAbs & aluInT & aluCmp, -- CD CMP abs
"0000" & "100010" & rmwAbs & aluInT & aluDec, -- CE DEC abs
"0000" & "000000" & implied & aluInXXX & aluXXX, -- CF NOP ----- 65C02
"0000" & "000000" & relative & aluInXXX & aluXXX, -- D0 BNE
"0000" & "100011" & readIndY & aluInT & aluCmp, -- D1 CMP (zp),y
"0000" & "100011" & readInd & aluInT & aluCmp, -- D2 CMP (zp) ------ 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- D3 NOP ----- 65C02
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- D4 NOP ----- 65C02
"0000" & "100011" & readZpX & aluInT & aluCmp, -- D5 CMP zp,x
"0000" & "100010" & rmwZpX & aluInT & aluDec, -- D6 DEC zp,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- D7 NOP ----- 65C02
"0000" & "001000" & implied & aluInClr & aluXXX, -- D8 CLD
"0000" & "100011" & readAbsY & aluInT & aluCmp, -- D9 CMP abs,y
"0000" & "000000" & push & aluInX & aluInp, -- DA PHX ----------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- DB NOP ----- 65C02
"0000" & "000000" & readAbs & aluInXXX & aluXXX, -- DC NOP ----- 65C02
"0000" & "100011" & readAbsX & aluInT & aluCmp, -- DD CMP abs,x
"0000" & "100010" & rmwAbsX & aluInT & aluDec, -- DE DEC abs,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- DF NOP ----- 65C02
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "100011" & immediate & aluInT & aluCpx, -- E0 CPX imm
"1000" & "110011" & readIndX & aluInT & aluSbc, -- E1 SBC (zp,x)
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- E2 NOP ----- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- E3 NOP ----- 65C02
"0000" & "100011" & readZp & aluInT & aluCpx, -- E4 CPX zp
"1000" & "110011" & readZp & aluInT & aluSbc, -- E5 SBC zp
"0000" & "100010" & rmwZp & aluInT & aluInc, -- E6 INC zp
"0000" & "000000" & implied & aluInXXX & aluXXX, -- E7 NOP ----- 65C02
"0100" & "100010" & implied & aluInX & aluInc, -- E8 INX
"1000" & "110011" & immediate & aluInT & aluSbc, -- E9 SBC imm
"0000" & "000000" & implied & aluInXXX & aluXXX, -- EA NOP
"0000" & "000000" & implied & aluInXXX & aluXXX, -- EB NOP ----- 65C02
"0000" & "100011" & readAbs & aluInT & aluCpx, -- EC CPX abs
"1000" & "110011" & readAbs & aluInT & aluSbc, -- ED SBC abs
"0000" & "100010" & rmwAbs & aluInT & aluInc, -- EE INC abs
"0000" & "000000" & implied & aluInXXX & aluXXX, -- EF NOP ----- 65C02
"0000" & "000000" & relative & aluInXXX & aluXXX, -- F0 BEQ
"1000" & "110011" & readIndY & aluInT & aluSbc, -- F1 SBC (zp),y
"1000" & "110011" & readInd & aluInT & aluSbc, -- F2 SBC (zp) ------ 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- F3 NOP ----- 65C02
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- F4 NOP ----- 65C02
"1000" & "110011" & readZpX & aluInT & aluSbc, -- F5 SBC zp,x
"0000" & "100010" & rmwZpX & aluInT & aluInc, -- F6 INC zp,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- F7 NOP ---- 65C02
"0000" & "001000" & implied & aluInSet & aluXXX, -- F8 SED
"1000" & "110011" & readAbsY & aluInT & aluSbc, -- F9 SBC abs,y
"0100" & "100010" & pop & aluInT & aluInp, -- FA PLX ----------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- FB NOP ----- 65C02
"0000" & "000000" & readAbs & aluInXXX & aluXXX, -- FC NOP ----- 65C02
"1000" & "110011" & readAbsX & aluInT & aluSbc, -- FD SBC abs,x
"0000" & "100010" & rmwAbsX & aluInT & aluInc, -- FE INC abs,x
"0000" & "000000" & implied & aluInXXX & aluXXX -- FF NOP ----- 65C02
);
signal opcInfo : decodedBitsDef;
signal nextOpcInfo : decodedBitsDef; -- Next opcode (decoded)
signal nextOpcInfoReg : decodedBitsDef; -- Next opcode (decoded) pipelined
signal theOpcode : unsigned(7 downto 0);
signal nextOpcode : unsigned(7 downto 0);
-- Program counter
signal PC : unsigned(15 downto 0); -- Program counter
-- Address generation
type nextAddrDef is (
nextAddrHold,
nextAddrIncr,
nextAddrIncrL, -- Increment low bits only (zeropage accesses)
nextAddrIncrH, -- Increment high bits only (page-boundary)
nextAddrDecrH, -- Decrement high bits (branch backwards)
nextAddrPc,
nextAddrIrq,
nextAddrReset,
nextAddrAbs,
nextAddrAbsIndexed,
nextAddrZeroPage,
nextAddrZPIndexed,
nextAddrStack,
nextAddrRelative
);
signal nextAddr : nextAddrDef;
signal myAddr : unsigned(15 downto 0);
signal myAddrIncr : unsigned(15 downto 0);
signal myAddrIncrH : unsigned(7 downto 0);
signal myAddrDecrH : unsigned(7 downto 0);
signal theWe : std_logic;
signal irqActive : std_logic;
-- Output register
signal doReg : unsigned(7 downto 0);
-- Buffer register
signal T : unsigned(7 downto 0);
-- General registers
signal A: unsigned(7 downto 0); -- Accumulator
signal X: unsigned(7 downto 0); -- Index X
signal Y: unsigned(7 downto 0); -- Index Y
signal S: unsigned(7 downto 0); -- stack pointer
-- Status register
signal C: std_logic; -- Carry
signal Z: std_logic; -- Zero flag
signal I: std_logic; -- Interrupt flag
signal D: std_logic; -- Decimal mode
signal B: std_logic; -- Break software interrupt
signal R: std_logic; -- always 1
signal V: std_logic; -- Overflow
signal N: std_logic; -- Negative
-- ALU
-- ALU input
signal aluInput : unsigned(7 downto 0);
signal aluCmpInput : unsigned(7 downto 0);
-- ALU output
signal aluRegisterOut : unsigned(7 downto 0);
signal aluRmwOut : unsigned(7 downto 0);
signal aluC : std_logic;
signal aluZ : std_logic;
signal aluV : std_logic;
signal aluN : std_logic;
-- Indexing
signal indexOut : unsigned(8 downto 0);
signal realbrk : std_logic;
begin
processAluInput: process(clk, opcInfo, A, X, Y, T, S)
variable temp : unsigned(7 downto 0);
begin
temp := (others => '1');
if opcInfo(opcInA) = '1' then
temp := temp and A;
end if;
if opcInfo(opcInX) = '1' then
temp := temp and X;
end if;
if opcInfo(opcInY) = '1' then
temp := temp and Y;
end if;
if opcInfo(opcInS) = '1' then
temp := temp and S;
end if;
if opcInfo(opcInT) = '1' then
temp := temp and T;
end if;
if opcInfo(opcInBrk) = '1' then
temp := temp and "11100111"; -- also DMB clear D (bit 3)
end if;
if opcInfo(opcInClear) = '1' then
temp := (others => '0');
end if;
aluInput <= temp;
end process;
processCmpInput: process(clk, opcInfo, A, X, Y)
variable temp : unsigned(7 downto 0);
begin
temp := (others => '1');
if opcInfo(opcInCmp) = '1' then
temp := temp and A;
end if;
if opcInfo(opcInCpx) = '1' then
temp := temp and X;
end if;
if opcInfo(opcInCpy) = '1' then
temp := temp and Y;
end if;
aluCmpInput <= temp;
end process;
-- ALU consists of two parts
-- Read-Modify-Write or index instructions: INC/DEC/ASL/LSR/ROR/ROL
-- Accumulator instructions: ADC, SBC, EOR, AND, EOR, ORA
-- Some instructions are both RMW and accumulator so for most
-- instructions the rmw results are routed through accu alu too.
-- The B flag
------------
--No actual "B" flag exists inside the 6502's processor status register. The B
--flag only exists in the status flag byte pushed to the stack. Naturally,
--when the flags are restored (via PLP or RTI), the B bit is discarded.
--
--Depending on the means, the B status flag will be pushed to the stack as
--either 0 or 1.
--
--software instructions BRK & PHP will push the B flag as being 1.
--hardware interrupts IRQ & NMI will push the B flag as being 0.
processAlu: process(clk, opcInfo, aluInput, aluCmpInput, A, T, irqActive, N, V, R, D, I, Z, C)
variable lowBits: unsigned(5 downto 0);
variable nineBits: unsigned(8 downto 0);
variable rmwBits: unsigned(8 downto 0);
variable tsxBits: unsigned(8 downto 0);
variable varC : std_logic;
variable varZ : std_logic;
variable varV : std_logic;
variable varN : std_logic;
begin
lowBits := (others => '-');
nineBits := (others => '-');
rmwBits := (others => '-');
tsxBits := (others => '-');
R <= '1';
-- Shift unit
case opcInfo(aluMode1From to aluMode1To) is
when aluModeInp => rmwBits := C & aluInput;
when aluModeP => rmwBits := C & N & V & R & (not irqActive) & D & I & Z & C; -- irqActive
when aluModeInc => rmwBits := C & (aluInput + 1);
when aluModeDec => rmwBits := C & (aluInput - 1);
when aluModeAsl => rmwBits := aluInput & "0";
when aluModeTSB => rmwBits := "0" & (aluInput(7 downto 0) or A); -- added by alan for 65c02
tsxBits := "0" & (aluInput(7 downto 0) and A);
when aluModeTRB => rmwBits := "0" & (aluInput(7 downto 0) and (not A)); -- added by alan for 65c02
tsxBits := "0" & (aluInput(7 downto 0) and A);
when aluModeFlg => rmwBits := aluInput(0) & aluInput;
when aluModeLsr => rmwBits := aluInput(0) & "0" & aluInput(7 downto 1);
when aluModeRol => rmwBits := aluInput & C;
when aluModeRoR => rmwBits := aluInput(0) & C & aluInput(7 downto 1);
when others => rmwBits := C & aluInput;
end case;
-- ALU
case opcInfo(aluMode2From to aluMode2To) is
when aluModeAdc => lowBits := ("0" & A(3 downto 0) & rmwBits(8)) + ("0" & rmwBits(3 downto 0) & "1");
ninebits := ("0" & A) + ("0" & rmwBits(7 downto 0)) + (B"00000000" & rmwBits(8));
when aluModeSbc => lowBits := ("0" & A(3 downto 0) & rmwBits(8)) + ("0" & (not rmwBits(3 downto 0)) & "1");
ninebits := ("0" & A) + ("0" & (not rmwBits(7 downto 0))) + (B"00000000" & rmwBits(8));
when aluModeCmp => ninebits := ("0" & aluCmpInput) + ("0" & (not rmwBits(7 downto 0))) + "000000001";
when aluModeAnd => ninebits := rmwBits(8) & (A and rmwBits(7 downto 0));
when aluModeEor => ninebits := rmwBits(8) & (A xor rmwBits(7 downto 0));
when aluModeOra => ninebits := rmwBits(8) & (A or rmwBits(7 downto 0));
when aluModeNoF => ninebits := "000110000";
when others => ninebits := rmwBits;
end case;
varV := aluInput(6); -- Default for BIT / PLP / RTI
if (opcInfo(aluMode1From to aluMode1To) = aluModeFlg) then
varZ := rmwBits(1);
elsif (opcInfo(aluMode1From to aluMode1To) = aluModeTSB) or (opcInfo(aluMode1From to aluMode1To) = aluModeTRB) then
if tsxBits(7 downto 0) = X"00" then
varZ := '1';
else
varZ := '0';
end if;
elsif ninebits(7 downto 0) = X"00" then
varZ := '1';
else
varZ := '0';
end if;
if (opcInfo(aluMode1From to aluMode1To) = aluModeBit) or (opcInfo(aluMode1From to aluMode1To) = aluModeFlg) then
varN := rmwBits(7);
else
varN := nineBits(7);
end if;
varC := ninebits(8);
case opcInfo(aluMode2From to aluMode2To) is
-- Flags Affected: n v — — — — z c
-- n Set if most significant bit of result is set; else cleared.
-- v Set if signed overflow; cleared if valid signed result.
-- z Set if result is zero; else cleared.
-- c Set if unsigned overflow; cleared if valid unsigned result
when aluModeAdc =>
-- decimal mode low bits correction, is done after setting Z flag.
if D = '1' then
if lowBits(5 downto 1) > 9 then
ninebits(3 downto 0) := ninebits(3 downto 0) + 6;
if lowBits(5) = '0' then
ninebits(8 downto 4) := ninebits(8 downto 4) + 1;
end if;
end if;
end if;
when others => null;
end case;
case opcInfo(aluMode2From to aluMode2To) is
when aluModeAdc =>
-- decimal mode high bits correction, is done after setting Z and N flags
varV := (A(7) xor ninebits(7)) and (rmwBits(7) xor ninebits(7));
if D = '1' then
if ninebits(8 downto 4) > 9 then
ninebits(8 downto 4) := ninebits(8 downto 4) + 6;
varC := '1';
end if;
end if;
when aluModeSbc =>
varV := (A(7) xor ninebits(7)) and ((not rmwBits(7)) xor ninebits(7));
if D = '1' then
-- Check for borrow (lower 4 bits)
if lowBits(5) = '0' then
ninebits(7 downto 0) := ninebits(7 downto 0) - 6;
end if;
-- Check for borrow (upper 4 bits)
if ninebits(8) = '0' then
ninebits(8 downto 4) := ninebits(8 downto 4) - 6;
end if;
end if;
when others => null;
end case;
-- fix n and z flag for 65c02 adc sbc instructions in decimal mode
case opcInfo(aluMode2From to aluMode2To) is
when aluModeAdc =>
if D = '1' then
if ninebits(7 downto 0) = X"00" then
varZ := '1';
else
varZ := '0';
end if;
varN := ninebits(7);
end if;
when aluModeSbc =>
if D = '1' then
if ninebits(7 downto 0) = X"00" then
varZ := '1';
else
varZ := '0';
end if;
varN := ninebits(7);
end if;
when others => null;
end case;
-- DMB Remove Pipelining
-- if rising_edge(clk) then
aluRmwOut <= rmwBits(7 downto 0);
aluRegisterOut <= ninebits(7 downto 0);
aluC <= varC;
aluZ <= varZ;
aluV <= varV;
aluN <= varN;
-- end if;
end process;
calcInterrupt: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
if theCpuCycle = cycleStack4 or reset = '0' then
nmiReg <= '1';
end if;
if nextCpuCycle /= cycleBranchTaken and nextCpuCycle /= opcodeFetch then
irqReg <= irq_n;
nmiEdge <= nmi_n;
if (nmiEdge = '1') and (nmi_n = '0') then
nmiReg <= '0';
end if;
end if;
-- The 'or opcInfo(opcSetI)' prevents NMI immediately after BRK or IRQ.
-- Presumably this is done in the real 6502/6510 to prevent a double IRQ.
processIrq <= not ((nmiReg and (irqReg or I)) or opcInfo(opcIRQ));
end if;
end if;
end process;
--pipeirq: process(clk)
-- begin
-- if rising_edge(clk) then
-- if enable = '1' then
-- if (reset = '0') or (theCpuCycle = opcodeFetch) then
-- -- The 'or opcInfo(opcSetI)' prevents NMI immediately after BRK or IRQ.
-- -- Presumably this is done in the real 6502/6510 to prevent a double IRQ.
-- processIrq <= not ((nmiReg and (irqReg or I)) or opcInfo(opcIRQ));
-- end if;
-- end if;
-- end if;
-- end process;
calcNextOpcode: process(clk, di, reset, processIrq)
variable myNextOpcode : unsigned(7 downto 0);
begin
-- Next opcode is read from input unless a reset or IRQ is pending.
myNextOpcode := di;
if reset = '0' then
myNextOpcode := X"4C";
elsif processIrq = '1' then
myNextOpcode := X"00";
end if;
nextOpcode <= myNextOpcode;
end process;
nextOpcInfo <= opcodeInfoTable(to_integer(nextOpcode));
-- DMB Remove Pipelining
-- process(clk)
-- begin
-- if rising_edge(clk) then
nextOpcInfoReg <= nextOpcInfo;
-- end if;
-- end process;
-- Read bits and flags from opcodeInfoTable and store in opcInfo.
-- This info is used to control the execution of the opcode.
calcOpcInfo: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
if (reset = '0') or (theCpuCycle = opcodeFetch) then
opcInfo <= nextOpcInfo;
end if;
end if;
end if;
end process;
calcTheOpcode: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
if theCpuCycle = opcodeFetch then
irqActive <= '0';
if processIrq = '1' then
irqActive <= '1';
end if;
-- Fetch opcode
theOpcode <= nextOpcode;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- State machine
-- -----------------------------------------------------------------------
process(enable, theCpuCycle, opcInfo)
begin
updateRegisters <= false;
if enable = '1' then
if opcInfo(opcRti) = '1' then
if theCpuCycle = cycleRead then
updateRegisters <= true;
end if;
elsif theCpuCycle = opcodeFetch then
updateRegisters <= true;
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
theCpuCycle <= nextCpuCycle;
end if;
if reset = '0' then
theCpuCycle <= cycle2;
end if;
end if;
end process;
-- Determine the next cpu cycle. After the last cycle we always
-- go to opcodeFetch to get the next opcode.
calcNextCpuCycle: process(theCpuCycle, opcInfo, theOpcode, indexOut, T, N, V, C, Z)
begin
nextCpuCycle <= opcodeFetch;
case theCpuCycle is
when opcodeFetch => nextCpuCycle <= cycle2;
when cycle2 => if opcInfo(opcBranch) = '1' then
if (N = theOpcode(5) and theOpcode(7 downto 6) = "00")
or (V = theOpcode(5) and theOpcode(7 downto 6) = "01")
or (C = theOpcode(5) and theOpcode(7 downto 6) = "10")
or (Z = theOpcode(5) and theOpcode(7 downto 6) = "11")
or (theOpcode(7 downto 0) = x"80") then -- Branch condition is true
nextCpuCycle <= cycleBranchTaken;
end if;
elsif (opcInfo(opcStackUp) = '1') then
nextCpuCycle <= cycleStack1;
elsif opcInfo(opcStackAddr) = '1' and opcInfo(opcStackData) = '1' then
nextCpuCycle <= cycleStack2;
elsif opcInfo(opcStackAddr) = '1' then
nextCpuCycle <= cycleStack1;
elsif opcInfo(opcStackData) = '1' then
nextCpuCycle <= cycleWrite;
elsif opcInfo(opcAbsolute) = '1' then
nextCpuCycle <= cycle3;
elsif opcInfo(opcIndirect) = '1' then
if opcInfo(indexX) = '1' then
nextCpuCycle <= cyclePreIndirect;
else
nextCpuCycle <= cycleIndirect;
end if;
elsif opcInfo(opcZeroPage) = '1' then
if opcInfo(opcWrite) = '1' then
if (opcInfo(indexX) = '1') or (opcInfo(indexY) = '1') then
nextCpuCycle <= cyclePreWrite;
else
nextCpuCycle <= cycleWrite;
end if;
else
if (opcInfo(indexX) = '1') or (opcInfo(indexY) = '1') then
nextCpuCycle <= cyclePreRead;
else
nextCpuCycle <= cycleRead2;
end if;
end if;
elsif opcInfo(opcJump) = '1' then
nextCpuCycle <= cycleJump;
end if;
when cycle3 => nextCpuCycle <= cycleRead;
if opcInfo(opcWrite) = '1' then
if (opcInfo(indexX) = '1') or (opcInfo(indexY) = '1') then
nextCpuCycle <= cyclePreWrite;
else
nextCpuCycle <= cycleWrite;
end if;
end if;
if (opcInfo(opcIndirect) = '1') and (opcInfo(indexX) = '1') then
if opcInfo(opcWrite) = '1' then
nextCpuCycle <= cycleWrite;
else
nextCpuCycle <= cycleRead2;
end if;
end if;
when cyclePreIndirect => nextCpuCycle <= cycleIndirect;
when cycleIndirect => nextCpuCycle <= cycle3;
when cycleBranchTaken => if indexOut(8) /= T(7) then
nextCpuCycle <= cycleBranchPage;
end if;
when cyclePreRead => if opcInfo(opcZeroPage) = '1' then
nextCpuCycle <= cycleRead2;
end if;
when cycleRead =>
if opcInfo(opcJump) = '1' then
nextCpuCycle <= cycleJump;
elsif indexOut(8) = '1' then
nextCpuCycle <= cycleRead2;
elsif opcInfo(opcRmw) = '1' then
nextCpuCycle <= cycleRmw;
if opcInfo(indexX) = '1' or opcInfo(indexY) = '1' then
nextCpuCycle <= cycleRead2;
end if;
end if;
when cycleRead2 => if opcInfo(opcRmw) = '1' then
nextCpuCycle <= cycleRmw;
end if;
when cycleRmw => nextCpuCycle <= cycleWrite;
when cyclePreWrite => nextCpuCycle <= cycleWrite;
when cycleStack1 => nextCpuCycle <= cycleRead;
if opcInfo(opcStackAddr) = '1' then
nextCpuCycle <= cycleStack2;
end if;
when cycleStack2 => nextCpuCycle <= cycleStack3;
if opcInfo(opcRti) = '1' then
nextCpuCycle <= cycleRead;
end if;
if opcInfo(opcStackData) = '0' and opcInfo(opcStackUp) = '1' then
nextCpuCycle <= cycleJump;
end if;
when cycleStack3 => nextCpuCycle <= cycleRead;
if opcInfo(opcStackData) = '0' or opcInfo(opcStackUp) = '1' then
nextCpuCycle <= cycleJump;
elsif opcInfo(opcStackAddr) = '1' then
nextCpuCycle <= cycleStack4;
end if;
when cycleStack4 => nextCpuCycle <= cycleRead;
when cycleJump => if opcInfo(opcIncrAfter) = '1' then
nextCpuCycle <= cycleEnd;
end if;
when others => null;
end case;
end process;
-- -----------------------------------------------------------------------
-- T register
-- -----------------------------------------------------------------------
calcT: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
case theCpuCycle is
when cycle2 => T <= di;
when cycleStack1 | cycleStack2 =>
if opcInfo(opcStackUp) = '1' then
if theOpcode = x"28" or theOpcode = x"40" then -- plp or rti pulling the flags off the stack
T <= (di or "00110000"); -- Read from stack
else
T <= di;
end if;
end if;
when cycleIndirect | cycleRead | cycleRead2 => T <= di;
when others => null;
end case;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- A register
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateA) = '1' then
A <= aluRegisterOut;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- X register
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateX) = '1' then
X <= aluRegisterOut;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Y register
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateY) = '1' then
Y <= aluRegisterOut;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- C flag
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateC) = '1' then
C <= aluC;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Z flag
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateZ) = '1' then
Z <= aluZ;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- I flag interupt flag
-- -----------------------------------------------------------------------
process(clk, reset)
begin
if reset = '0' then
I <= '1';
elsif rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateI) = '1' then
I <= aluInput(2);
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- D flag
-- -----------------------------------------------------------------------
process(clk, reset)
begin
if reset = '0' then
D <= '0';
elsif rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateD) = '1' then
D <= aluInput(3);
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- V flag
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateV) = '1' then
V <= aluV;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- N flag
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateN) = '1' then
N <= aluN;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Stack pointer
-- -----------------------------------------------------------------------
process(clk)
variable sIncDec : unsigned(7 downto 0);
variable updateFlag : boolean;
begin
if rising_edge(clk) then
if opcInfo(opcStackUp) = '1' then
sIncDec := S + 1;
else
sIncDec := S - 1;
end if;
if enable = '1' then
updateFlag := false;
case nextCpuCycle is
when cycleStack1 =>
if (opcInfo(opcStackUp) = '1') or (opcInfo(opcStackData) = '1') then
updateFlag := true;
end if;
when cycleStack2 => updateFlag := true;
when cycleStack3 => updateFlag := true;
when cycleStack4 => updateFlag := true;
when cycleRead => if opcInfo(opcRti) = '1' then
updateFlag := true;
end if;
when cycleWrite => if opcInfo(opcStackData) = '1' then
updateFlag := true;
end if;
when others => null;
end case;
if updateFlag then
S <= sIncDec;
end if;
end if;
if updateRegisters then
if opcInfo(opcUpdateS) = '1' then
S <= aluRegisterOut;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Data out
-- -----------------------------------------------------------------------
calcDo: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
doReg <= aluRmwOut;
case nextCpuCycle is
when cycleStack2 => if opcInfo(opcIRQ) = '1' and irqActive = '0' then
doReg <= myAddrIncr(15 downto 8);
else
doReg <= PC(15 downto 8);
end if;
when cycleStack3 => doReg <= PC(7 downto 0);
when cycleRmw => doReg <= di; -- Read-modify-write write old value first.
when others => null;
end case;
end if;
end if;
end process;
do <= doReg;
-- -----------------------------------------------------------------------
-- Write enable
-- -----------------------------------------------------------------------
calcWe: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
theWe <= '1';
case nextCpuCycle is
when cycleStack1 =>
if opcInfo(opcStackUp) = '0' and ((opcInfo(opcStackAddr) = '0') or (opcInfo(opcStackData) = '1')) then
theWe <= '0';
end if;
when cycleStack2 | cycleStack3 | cycleStack4 =>
if opcInfo(opcStackUp) = '0' then
theWe <= '0';
end if;
when cycleRmw => theWe <= '0';
when cycleWrite => theWe <= '0';
when others => null;
end case;
end if;
end if;
--nwe <= theWe;
end process;
nwe <= theWe;
-- -----------------------------------------------------------------------
-- Program counter
-- -----------------------------------------------------------------------
calcPC: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
case theCpuCycle is
when opcodeFetch => PC <= myAddr;
when cycle2 => if irqActive = '0' then
if opcInfo(opcSecondByte) = '1' then
PC <= myAddrIncr;
else
PC <= myAddr;
end if;
end if;
when cycle3 => if opcInfo(opcAbsolute) = '1' then
PC <= myAddrIncr;
end if;
when others => null;
end case;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Address generation
-- -----------------------------------------------------------------------
calcNextAddr: process(theCpuCycle, opcInfo, indexOut, T, reset)
begin
nextAddr <= nextAddrIncr;
case theCpuCycle is
when cycle2 => if opcInfo(opcStackAddr) = '1' or opcInfo(opcStackData) = '1' then
nextAddr <= nextAddrStack;
elsif opcInfo(opcAbsolute) = '1' then
nextAddr <= nextAddrIncr;
elsif opcInfo(opcZeroPage) = '1' then
nextAddr <= nextAddrZeroPage;
elsif opcInfo(opcIndirect) = '1' then
nextAddr <= nextAddrZeroPage;
elsif opcInfo(opcSecondByte) = '1' then
nextAddr <= nextAddrIncr;
else
nextAddr <= nextAddrHold;
end if;
when cycle3 => if (opcInfo(opcIndirect) = '1') and (opcInfo(indexX) = '1') then
nextAddr <= nextAddrAbs;
else
nextAddr <= nextAddrAbsIndexed;
end if;
when cyclePreIndirect => nextAddr <= nextAddrZPIndexed;
when cycleIndirect => nextAddr <= nextAddrIncrL;
when cycleBranchTaken => nextAddr <= nextAddrRelative;
when cycleBranchPage => if T(7) = '0' then
nextAddr <= nextAddrIncrH;
else
nextAddr <= nextAddrDecrH;
end if;
when cyclePreRead => nextAddr <= nextAddrZPIndexed;
when cycleRead => nextAddr <= nextAddrPc;
if opcInfo(opcJump) = '1' then
-- Emulate 6510 bug, jmp(xxFF) fetches from same page.
-- Replace with nextAddrIncr if emulating 65C02 or later cpu.
nextAddr <= nextAddrIncr;
--nextAddr <= nextAddrIncrL;
elsif indexOut(8) = '1' then
nextAddr <= nextAddrIncrH;
elsif opcInfo(opcRmw) = '1' then
nextAddr <= nextAddrHold;
end if;
when cycleRead2 => nextAddr <= nextAddrPc;
if opcInfo(opcRmw) = '1' then
nextAddr <= nextAddrHold;
end if;
when cycleRmw => nextAddr <= nextAddrHold;
when cyclePreWrite => nextAddr <= nextAddrHold;
if opcInfo(opcZeroPage) = '1' then
nextAddr <= nextAddrZPIndexed;
elsif indexOut(8) = '1' then
nextAddr <= nextAddrIncrH;
end if;
when cycleWrite => nextAddr <= nextAddrPc;
when cycleStack1 => nextAddr <= nextAddrStack;
when cycleStack2 => nextAddr <= nextAddrStack;
when cycleStack3 => nextAddr <= nextAddrStack;
if opcInfo(opcStackData) = '0' then
nextAddr <= nextAddrPc;
end if;
when cycleStack4 => nextAddr <= nextAddrIrq;
when cycleJump => nextAddr <= nextAddrAbs;
when others => null;
end case;
if reset = '0' then
nextAddr <= nextAddrReset;
end if;
end process;
indexAlu: process(opcInfo, myAddr, T, X, Y)
begin
if opcInfo(indexX) = '1' then
indexOut <= (B"0" & T) + (B"0" & X);
elsif opcInfo(indexY) = '1' then
indexOut <= (B"0" & T) + (B"0" & Y);
elsif opcInfo(opcBranch) = '1' then
indexOut <= (B"0" & T) + (B"0" & myAddr(7 downto 0));
else
indexOut <= B"0" & T;
end if;
end process;
calcAddr: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
case nextAddr is
when nextAddrIncr => myAddr <= myAddrIncr;
when nextAddrIncrL => myAddr(7 downto 0) <= myAddrIncr(7 downto 0);
when nextAddrIncrH => myAddr(15 downto 8) <= myAddrIncrH;
when nextAddrDecrH => myAddr(15 downto 8) <= myAddrDecrH;
when nextAddrPc => myAddr <= PC;
when nextAddrIrq =>myAddr <= X"FFFE";
if nmiReg = '0' then
myAddr <= X"FFFA";
end if;
when nextAddrReset => myAddr <= X"FFFC";
when nextAddrAbs => myAddr <= di & T;
when nextAddrAbsIndexed =>--myAddr <= di & indexOut(7 downto 0);
if theOpcode = x"7C" then
myAddr <= (di & T) + (x"00"& X);
else
myAddr <= di & indexOut(7 downto 0);
end if;
when nextAddrZeroPage => myAddr <= "00000000" & di;
when nextAddrZPIndexed => myAddr <= "00000000" & indexOut(7 downto 0);
when nextAddrStack => myAddr <= "00000001" & S;
when nextAddrRelative => myAddr(7 downto 0) <= indexOut(7 downto 0);
when others => null;
end case;
end if;
end if;
end process;
myAddrIncr <= myAddr + 1;
myAddrIncrH <= myAddr(15 downto 8) + 1;
myAddrDecrH <= myAddr(15 downto 8) - 1;
addr <= myAddr;
-- DMB This looked plain broken and inferred a latch
--
-- calcsync: process(clk)
-- begin
--
-- if enable = '1' then
-- case theCpuCycle is
-- when opcodeFetch => sync <= '1';
-- when others => sync <= '0';
-- end case;
-- end if;
-- end process;
sync <= '1' when theCpuCycle = opcodeFetch else '0';
sync_irq <= irqActive;
Regs <= std_logic_vector(PC) &
"00000001" & std_logic_vector(S)&
N & V & R & B & D & I & Z & C &
std_logic_vector(Y) &
std_logic_vector(X) &
std_logic_vector(A);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity DCM0 is
port (CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic);
end DCM0;
architecture BEHAVIORAL of DCM0 is
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKFX_BUFG_INST : BUFG
port map (I => CLKFX_BUF, O => CLK0_OUT);
DCM_INST : DCM
generic map(CLK_FEEDBACK => "NONE",
CLKDV_DIVIDE => 4.0, -- 25.368 =49.152 * 16 / 31
CLKFX_DIVIDE => 31,
CLKFX_MULTIPLY => 16,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => 20.344,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => true,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => false)
port map (CLKFB => GND_BIT,
CLKIN => CLKIN_IN,
DSSEN => GND_BIT,
PSCLK => GND_BIT,
PSEN => GND_BIT,
PSINCDEC => GND_BIT,
RST => GND_BIT,
CLKDV => open,
CLKFX => CLKFX_BUF,
CLKFX180 => open,
CLK0 => open,
CLK2X => CLK2X_OUT,
CLK2X180 => open,
CLK90 => open,
CLK180 => open,
CLK270 => open,
LOCKED => open,
PSDONE => open,
STATUS => open);
end BEHAVIORAL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity DCM0 is
port (CLKIN_IN : in std_logic;
CLK0_OUT : out std_logic;
CLK0_OUT1 : out std_logic;
CLK2X_OUT : out std_logic);
end DCM0;
architecture BEHAVIORAL of DCM0 is
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKFX_BUFG_INST : BUFG
port map (I => CLKFX_BUF, O => CLK0_OUT);
DCM_INST : DCM
generic map(CLK_FEEDBACK => "NONE",
CLKDV_DIVIDE => 4.0, -- 25.368 =49.152 * 16 / 31
CLKFX_DIVIDE => 31,
CLKFX_MULTIPLY => 16,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => 20.344,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => true,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => false)
port map (CLKFB => GND_BIT,
CLKIN => CLKIN_IN,
DSSEN => GND_BIT,
PSCLK => GND_BIT,
PSEN => GND_BIT,
PSINCDEC => GND_BIT,
RST => GND_BIT,
CLKDV => open,
CLKFX => CLKFX_BUF,
CLKFX180 => open,
CLK0 => open,
CLK2X => CLK2X_OUT,
CLK2X180 => open,
CLK90 => open,
CLK180 => open,
CLK270 => open,
LOCKED => open,
PSDONE => open,
STATUS => open);
end BEHAVIORAL;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: mmu_cache
-- File: mmu_cache.vhd
-- Author: Jiri Gaisler
-- Description: Cache controllers and AHB interface
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.libiu.all;
use gaisler.libcache.all;
use gaisler.libleon3.all;
use gaisler.mmuconfig.all;
use gaisler.mmuiface.all;
use gaisler.libmmu.all;
entity mmu_cache is
generic (
hindex : integer := 0;
memtech : integer range 0 to NTECH := 0;
dsu : integer range 0 to 1 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 0;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 0;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
cached : integer := 0;
clk2x : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
smp : integer := 0;
mmuen : integer range 0 to 1 := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ici : in icache_in_type;
ico : out icache_out_type;
dci : in dcache_in_type;
dco : out dcache_out_type;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
crami : out cram_in_type;
cramo : in cram_out_type;
fpuholdn : in std_ulogic;
hclk, sclk : in std_ulogic;
hclken : in std_ulogic
);
end;
architecture rtl of mmu_cache is
signal icol : icache_out_type;
signal dcol : dcache_out_type;
signal mcii : memory_ic_in_type;
signal mcio : memory_ic_out_type;
signal mcdi : memory_dc_in_type;
signal mcdo : memory_dc_out_type;
signal mcmmi : memory_mm_in_type;
signal mcmmo : memory_mm_out_type;
signal mmudci : mmudc_in_type;
signal mmudco : mmudc_out_type;
signal mmuici : mmuic_in_type;
signal mmuico : mmuic_out_type;
signal ahbsi2 : ahb_slv_in_type;
signal ahbi2 : ahb_mst_in_type;
signal ahbo2 : ahb_mst_out_type;
signal gndv: std_logic_vector(1 downto 0);
begin
gndv <= (others => '0');
icache0 : mmu_icache
generic map (icen, irepl, isets, ilinesize, isetsize, isetlock, ilram,
ilramsize, ilramstart,
mmuen)
port map (rst, clk, ici, icol, dci, dcol, mcii, mcio,
crami.icramin, cramo.icramo, fpuholdn, mmudci, mmuici, mmuico);
dcache0 : mmu_dcache
generic map (dsu, dcen, drepl, dsets, dlinesize, dsetsize, dsetlock, dsnoop,
dlram, dlramsize, dlramstart, ilram, ilramstart,
itlbnum, dtlbnum, tlb_type,
memtech, cached, mmupgsz, smp, mmuen)
port map (rst, clk, dci, dcol, icol, mcdi, mcdo, ahbsi2,
crami.dcramin, cramo.dcramo, fpuholdn, mmudci, mmudco, sclk, ahbso);
-- AMBA AHB interface
a0 : mmu_acache
generic map (hindex, ilinesize, cached, clk2x, scantest
)
port map (rst, sclk, mcii, mcio, mcdi, mcdo, mcmmi, mcmmo, ahbi2, ahbo2, ahbso, hclken);
-- MMU
mmugen : if mmuen = 1 generate
m0 : mmu
generic map (memtech, itlbnum, dtlbnum, tlb_type, tlb_rep, mmupgsz, 1)
port map (rst, clk, mmudci, mmudco, mmuici, mmuico, mcmmo, mcmmi,
gndv(0), gndv(1 downto 0), open);
end generate;
nommu : if mmuen = 0 generate
mcmmi <= mci_zero; mmudco <= mmudco_zero; mmuico <= mmuico_zero;
end generate;
ico <= icol;
dco <= dcol;
clk2xgen: if clk2x /= 0 generate
sync0 : clk2xsync generic map (hindex, clk2x)
port map (rst, hclk, clk, ahbi, ahbi2, ahbo2, ahbo, ahbsi, ahbsi2,
mcii, mcdi, mcdo, mcmmi.req, mcmmo.grant, hclken);
end generate;
noclk2x : if clk2x = 0 generate
ahbsi2 <= ahbsi;
ahbi2 <= ahbi;
ahbo <= ahbo2;
end generate;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use work.arch_defs.all;
use work.txt_utils.all;
entity MUX1bit is
-- With VHDL2008 we could MAX type generic and make this obsolete
port (
sel: in ctrl_t;
input0 : in std_logic;
input1 : in std_logic;
output : out std_logic
);
end entity;
architecture behav of MUX1bit is
begin
output <= input0 when sel = '0' else input1;
end architecture behav;
|
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`protect end_protected
|
`protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13056)
`protect data_block
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gW7H
`protect end_protected
|
library verilog;
use verilog.vl_types.all;
entity altlvds_rx is
generic(
number_of_channels: integer := 1;
deserialization_factor: integer := 4;
registered_output: string := "ON";
inclock_period : integer := 10000;
inclock_boost : vl_notype;
cds_mode : string := "UNUSED";
intended_device_family: string := "Stratix";
input_data_rate : integer := 0;
inclock_data_alignment: string := "UNUSED";
registered_data_align_input: string := "ON";
common_rx_tx_pll: string := "ON";
enable_dpa_mode : string := "OFF";
enable_dpa_calibration: string := "ON";
enable_dpa_pll_calibration: string := "OFF";
enable_dpa_fifo : string := "ON";
use_dpll_rawperror: string := "OFF";
use_coreclock_input: string := "OFF";
dpll_lock_count : integer := 0;
dpll_lock_window: integer := 0;
outclock_resource: string := "AUTO";
data_align_rollover: vl_notype;
lose_lock_on_one_change: string := "OFF";
reset_fifo_at_first_lock: string := "ON";
use_external_pll: string := "OFF";
implement_in_les: string := "OFF";
buffer_implementation: string := "RAM";
port_rx_data_align: string := "PORT_CONNECTIVITY";
port_rx_channel_data_align: string := "PORT_CONNECTIVITY";
pll_operation_mode: string := "NORMAL";
x_on_bitslip : string := "ON";
use_no_phase_shift: string := "ON";
rx_align_data_reg: string := "RISING_EDGE";
inclock_phase_shift: integer := 0;
enable_soft_cdr_mode: string := "OFF";
sim_dpa_output_clock_phase_shift: integer := 0;
sim_dpa_is_negative_ppm_drift: string := "OFF";
sim_dpa_net_ppm_variation: integer := 0;
enable_dpa_align_to_rising_edge_only: string := "OFF";
enable_dpa_initial_phase_selection: string := "OFF";
dpa_initial_phase_value: integer := 0;
pll_self_reset_on_loss_lock: string := "OFF";
refclk_frequency: string := "UNUSED";
enable_clock_pin_mode: string := "UNUSED";
data_rate : string := "UNUSED";
lpm_hint : string := "UNUSED";
lpm_type : string := "altlvds_rx";
clk_src_is_pll : string := "off";
STRATIX_RX_STYLE: vl_notype;
STRATIXGX_DPA_RX_STYLE: vl_notype;
STRATIXII_RX_STYLE: vl_notype;
CYCLONE_RX_STYLE: vl_notype;
CYCLONEII_RX_STYLE: vl_notype;
STRATIXIII_RX_STYLE: vl_notype;
ARRIAII_RX_STYLE: vl_notype;
STRATIXV_RX_STYLE: vl_notype;
CYCLONEIII_RX_STYLE: vl_notype;
FAMILY_HAS_FLEXIBLE_LVDS: vl_notype;
FAMILY_HAS_STRATIX_STYLE_PLL: vl_notype;
FAMILY_HAS_STRATIXII_STYLE_PLL: vl_notype;
FAMILY_HAS_STRATIXIII_STYLE_PLL: vl_notype;
INT_CLOCK_BOOST : vl_notype;
PLL_M_VALUE : vl_notype;
PLL_D_VALUE : vl_notype;
STRATIX_INCLOCK_BOOST: vl_notype;
PHASE_SHIFT : vl_notype;
STXII_PHASE_SHIFT: vl_notype;
STXII_LE_PHASE_SHIFT: vl_notype;
STXIII_LE_PHASE_SHIFT: vl_notype;
REGISTER_WIDTH : vl_notype;
CLOCK_PERIOD : vl_notype;
FAST_CLK_ENA_PHASE_SHIFT: vl_notype;
use_dpa_calibration: vl_notype
);
port(
rx_in : in vl_logic_vector;
rx_inclock : in vl_logic;
rx_syncclock : in vl_logic;
rx_dpaclock : in vl_logic;
rx_readclock : in vl_logic;
rx_enable : in vl_logic;
rx_deskew : in vl_logic;
rx_pll_enable : in vl_logic;
rx_data_align : in vl_logic;
rx_data_align_reset: in vl_logic;
rx_reset : in vl_logic_vector;
rx_dpll_reset : in vl_logic_vector;
rx_dpll_hold : in vl_logic_vector;
rx_dpll_enable : in vl_logic_vector;
rx_fifo_reset : in vl_logic_vector;
rx_channel_data_align: in vl_logic_vector;
rx_cda_reset : in vl_logic_vector;
rx_coreclk : in vl_logic_vector;
pll_areset : in vl_logic;
pll_phasedone : in vl_logic;
dpa_pll_recal : in vl_logic;
rx_dpa_lock_reset: in vl_logic_vector;
rx_out : out vl_logic_vector;
rx_outclock : out vl_logic;
rx_locked : out vl_logic;
rx_dpa_locked : out vl_logic_vector;
rx_cda_max : out vl_logic_vector;
rx_divfwdclk : out vl_logic_vector;
pll_phasestep : out vl_logic;
pll_phaseupdown : out vl_logic;
pll_phasecounterselect: out vl_logic_vector(3 downto 0);
pll_scanclk : out vl_logic;
dpa_pll_cal_busy: out vl_logic;
rx_data_reset : in vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of number_of_channels : constant is 1;
attribute mti_svvh_generic_type of deserialization_factor : constant is 1;
attribute mti_svvh_generic_type of registered_output : constant is 1;
attribute mti_svvh_generic_type of inclock_period : constant is 1;
attribute mti_svvh_generic_type of inclock_boost : constant is 3;
attribute mti_svvh_generic_type of cds_mode : constant is 1;
attribute mti_svvh_generic_type of intended_device_family : constant is 1;
attribute mti_svvh_generic_type of input_data_rate : constant is 1;
attribute mti_svvh_generic_type of inclock_data_alignment : constant is 1;
attribute mti_svvh_generic_type of registered_data_align_input : constant is 1;
attribute mti_svvh_generic_type of common_rx_tx_pll : constant is 1;
attribute mti_svvh_generic_type of enable_dpa_mode : constant is 1;
attribute mti_svvh_generic_type of enable_dpa_calibration : constant is 1;
attribute mti_svvh_generic_type of enable_dpa_pll_calibration : constant is 1;
attribute mti_svvh_generic_type of enable_dpa_fifo : constant is 1;
attribute mti_svvh_generic_type of use_dpll_rawperror : constant is 1;
attribute mti_svvh_generic_type of use_coreclock_input : constant is 1;
attribute mti_svvh_generic_type of dpll_lock_count : constant is 1;
attribute mti_svvh_generic_type of dpll_lock_window : constant is 1;
attribute mti_svvh_generic_type of outclock_resource : constant is 1;
attribute mti_svvh_generic_type of data_align_rollover : constant is 3;
attribute mti_svvh_generic_type of lose_lock_on_one_change : constant is 1;
attribute mti_svvh_generic_type of reset_fifo_at_first_lock : constant is 1;
attribute mti_svvh_generic_type of use_external_pll : constant is 1;
attribute mti_svvh_generic_type of implement_in_les : constant is 1;
attribute mti_svvh_generic_type of buffer_implementation : constant is 1;
attribute mti_svvh_generic_type of port_rx_data_align : constant is 1;
attribute mti_svvh_generic_type of port_rx_channel_data_align : constant is 1;
attribute mti_svvh_generic_type of pll_operation_mode : constant is 1;
attribute mti_svvh_generic_type of x_on_bitslip : constant is 1;
attribute mti_svvh_generic_type of use_no_phase_shift : constant is 1;
attribute mti_svvh_generic_type of rx_align_data_reg : constant is 1;
attribute mti_svvh_generic_type of inclock_phase_shift : constant is 1;
attribute mti_svvh_generic_type of enable_soft_cdr_mode : constant is 1;
attribute mti_svvh_generic_type of sim_dpa_output_clock_phase_shift : constant is 1;
attribute mti_svvh_generic_type of sim_dpa_is_negative_ppm_drift : constant is 1;
attribute mti_svvh_generic_type of sim_dpa_net_ppm_variation : constant is 1;
attribute mti_svvh_generic_type of enable_dpa_align_to_rising_edge_only : constant is 1;
attribute mti_svvh_generic_type of enable_dpa_initial_phase_selection : constant is 1;
attribute mti_svvh_generic_type of dpa_initial_phase_value : constant is 1;
attribute mti_svvh_generic_type of pll_self_reset_on_loss_lock : constant is 1;
attribute mti_svvh_generic_type of refclk_frequency : constant is 1;
attribute mti_svvh_generic_type of enable_clock_pin_mode : constant is 1;
attribute mti_svvh_generic_type of data_rate : constant is 1;
attribute mti_svvh_generic_type of lpm_hint : constant is 1;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
attribute mti_svvh_generic_type of clk_src_is_pll : constant is 1;
attribute mti_svvh_generic_type of STRATIX_RX_STYLE : constant is 3;
attribute mti_svvh_generic_type of STRATIXGX_DPA_RX_STYLE : constant is 3;
attribute mti_svvh_generic_type of STRATIXII_RX_STYLE : constant is 3;
attribute mti_svvh_generic_type of CYCLONE_RX_STYLE : constant is 3;
attribute mti_svvh_generic_type of CYCLONEII_RX_STYLE : constant is 3;
attribute mti_svvh_generic_type of STRATIXIII_RX_STYLE : constant is 3;
attribute mti_svvh_generic_type of ARRIAII_RX_STYLE : constant is 3;
attribute mti_svvh_generic_type of STRATIXV_RX_STYLE : constant is 3;
attribute mti_svvh_generic_type of CYCLONEIII_RX_STYLE : constant is 3;
attribute mti_svvh_generic_type of FAMILY_HAS_FLEXIBLE_LVDS : constant is 3;
attribute mti_svvh_generic_type of FAMILY_HAS_STRATIX_STYLE_PLL : constant is 3;
attribute mti_svvh_generic_type of FAMILY_HAS_STRATIXII_STYLE_PLL : constant is 3;
attribute mti_svvh_generic_type of FAMILY_HAS_STRATIXIII_STYLE_PLL : constant is 3;
attribute mti_svvh_generic_type of INT_CLOCK_BOOST : constant is 3;
attribute mti_svvh_generic_type of PLL_M_VALUE : constant is 3;
attribute mti_svvh_generic_type of PLL_D_VALUE : constant is 3;
attribute mti_svvh_generic_type of STRATIX_INCLOCK_BOOST : constant is 3;
attribute mti_svvh_generic_type of PHASE_SHIFT : constant is 3;
attribute mti_svvh_generic_type of STXII_PHASE_SHIFT : constant is 3;
attribute mti_svvh_generic_type of STXII_LE_PHASE_SHIFT : constant is 3;
attribute mti_svvh_generic_type of STXIII_LE_PHASE_SHIFT : constant is 3;
attribute mti_svvh_generic_type of REGISTER_WIDTH : constant is 3;
attribute mti_svvh_generic_type of CLOCK_PERIOD : constant is 3;
attribute mti_svvh_generic_type of FAST_CLK_ENA_PHASE_SHIFT : constant is 3;
attribute mti_svvh_generic_type of use_dpa_calibration : constant is 3;
end altlvds_rx;
|
----------------------------------------------------------------------------------
--
-- Author: Adam Howard - [email protected], Ben Olson - [email protected]
-- ECE-351: Course Project - Greenhouse Monitor
-- Notes: Project top module.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity control is
PORT(
mclk : in std_logic; --main clock
rst : in std_logic; --async reset
swi_bus : in std_logic_vector(7 downto 0); --input from switches
btn_bus : in std_logic_vector(3 downto 0); --input from buttons
led_bus : out std_logic_vector(7 downto 0); --output to LEDs
seg_bus : out std_logic_vector(0 to 7); --output to the 7-seg cathodes
digi_bus : out std_logic_vector(0 to 3); --output to the 7-seg anodes
als_clk : out std_logic;
als_cs : out std_logic;
als_sda : in std_logic
);
end control;
architecture control_arch of control is
component clk_divider is
Port (
rst: in std_logic;
clk_in : in std_logic;
clk_out : out std_logic;
const : in INTEGER);
end component clk_divider;
component btn_control is
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
btn_bus : in STD_LOGIC_VECTOR (3 downto 0);
output_bus : out STD_LOGIC_VECTOR (3 downto 0));
end component btn_control;
component interface is
Port (
rst : in std_logic;
clk : in std_logic;
btn_bus : in std_logic_vector (3 downto 0);
t_data : in std_logic_vector (7 downto 0);
l_data : in std_logic_vector (7 downto 0);
seg_bus : out std_logic_vector (0 to 7);
digi_bus : out std_logic_vector (0 to 3);
led_bus : out std_logic_vector (7 downto 0));
end component interface;
component als_driver is
Port (
rst : in STD_LOGIC;
clk : in STD_LOGIC;
cs : out STD_LOGIC;
scl : out STD_LOGIC;
sda : in STD_LOGIC;
data_out : out STD_LOGIC_VECTOR (7 downto 0));
end component als_driver;
signal btn_buffer : std_logic_vector(3 downto 0) := "0000";
signal l_data, t_data : std_logic_vector(7 downto 0) := "00000000";
begin
--l_data <= swi_bus;
t_data <= swi_bus;
SYS_MAIN: interface port map (
rst => rst,
clk => mclk,
btn_bus => btn_buffer,
t_data => t_data,
l_data => l_data,
seg_bus => seg_bus,
digi_bus => digi_bus,
led_bus => led_bus
);
DEBOUNCE: btn_control port map (
clk => mclk,
rst => rst,
btn_bus => btn_bus,
output_bus => btn_buffer
);
LIGHT_SENSOR: als_driver port map (
rst => rst,
clk => mclk,
cs => als_cs,
scl => als_clk,
sda => als_sda,
data_out => l_data
);
end control_arch;
|
entity FIFO is
port (
I_WR_EN : in std_logic;
I_DATA : in std_logic_vector(31 downto 0);
I_RD_EN : in std_logic;
O_DATA : out std_logic_vector(31 downto 0)
);
end entity FIFO;
entity FIFO is
port (
I_WR_EN : in std_logic;
I_DATA : in std_logic_vector(31 downto 0);
I_RD_EN : in std_logic;
O_DATA : out std_logic_vector(31 downto 0)
);
end entity FIFO;
|
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Toplevel : CPU86, 256Byte ROM, 16550 UART, 40K8 SRAM (all blockrams used)--
-------------------------------------------------------------------------------
-- Revision History: --
-- --
-- Date: Revision Author --
-- --
-- 30 Dec 2007 0.1 H. Tiggeler First version --
-- 17 May 2008 0.75 H. Tiggeler Updated for CPU86 ver0.75 --
-- 27 Jun 2008 0.79 H. Tiggeler Changed UART to Opencores 16750 --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY drigmorn1_top IS
PORT(
CLOCK_40MHZ : IN std_logic;
CTS : IN std_logic := '1';
PIN3 : IN std_logic;
RXD : IN std_logic;
LED1 : OUT std_logic;
LED2N : OUT std_logic;
LED3N : OUT std_logic;
PIN4 : OUT std_logic;
RTS : OUT std_logic;
TXD : OUT std_logic
);
END drigmorn1_top ;
ARCHITECTURE struct OF drigmorn1_top IS
-- Architecture declarations
signal csromn : std_logic;
-- Internal signal declarations
SIGNAL DCDn : std_logic := '1';
SIGNAL DSRn : std_logic := '1';
SIGNAL RIn : std_logic := '1';
SIGNAL abus : std_logic_vector(19 DOWNTO 0);
SIGNAL clk : std_logic;
SIGNAL cscom1 : std_logic;
SIGNAL dbus_com1 : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_in : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_in_cpu : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_out : std_logic_vector(7 DOWNTO 0);
SIGNAL dbus_rom : std_logic_vector(7 DOWNTO 0);
SIGNAL dout : std_logic;
SIGNAL dout1 : std_logic;
SIGNAL intr : std_logic;
SIGNAL iom : std_logic;
SIGNAL nmi : std_logic;
SIGNAL por : std_logic;
SIGNAL rdn : std_logic;
SIGNAL resoutn : std_logic;
SIGNAL sel_s : std_logic_vector(1 DOWNTO 0);
SIGNAL wea : std_logic_VECTOR(0 DOWNTO 0);
SIGNAL wran : std_logic;
SIGNAL wrcom : std_logic;
SIGNAL wrn : std_logic;
signal rxclk_s : std_logic;
-- Component Declarations
COMPONENT cpu86
PORT(
clk : IN std_logic;
dbus_in : IN std_logic_vector (7 DOWNTO 0);
intr : IN std_logic;
nmi : IN std_logic;
por : IN std_logic;
abus : OUT std_logic_vector (19 DOWNTO 0);
dbus_out : OUT std_logic_vector (7 DOWNTO 0);
cpuerror : OUT std_logic;
inta : OUT std_logic;
iom : OUT std_logic;
rdn : OUT std_logic;
resoutn : OUT std_logic;
wran : OUT std_logic;
wrn : OUT std_logic
);
END COMPONENT;
COMPONENT blk_mem_40K
PORT (
addra : IN std_logic_VECTOR (15 DOWNTO 0);
clka : IN std_logic;
dina : IN std_logic_VECTOR (7 DOWNTO 0);
wea : IN std_logic_VECTOR (0 DOWNTO 0);
douta : OUT std_logic_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
COMPONENT bootstrap
PORT (
abus : IN std_logic_vector (7 DOWNTO 0);
dbus : OUT std_logic_vector (7 DOWNTO 0)
);
END COMPONENT;
COMPONENT uart_top
PORT (
BR_clk : IN std_logic ;
CTSn : IN std_logic := '1';
DCDn : IN std_logic := '1';
DSRn : IN std_logic := '1';
RIn : IN std_logic := '1';
abus : IN std_logic_vector (2 DOWNTO 0);
clk : IN std_logic ;
csn : IN std_logic ;
dbus_in : IN std_logic_vector (7 DOWNTO 0);
rdn : IN std_logic ;
resetn : IN std_logic ;
sRX : IN std_logic ;
wrn : IN std_logic ;
B_CLK : OUT std_logic ;
DTRn : OUT std_logic ;
IRQ : OUT std_logic ;
OUT1n : OUT std_logic ;
OUT2n : OUT std_logic ;
RTSn : OUT std_logic ;
dbus_out : OUT std_logic_vector (7 DOWNTO 0);
stx : OUT std_logic
);
END COMPONENT;
BEGIN
-- Architecture concurrent statements
-- HDL Embedded Text Block 4 mux
-- dmux 1
process(sel_s,dbus_com1,dbus_in,dbus_rom)
begin
case sel_s is
when "01" => dbus_in_cpu <= dbus_com1; -- UART
when "10" => dbus_in_cpu <= dbus_rom; -- BootStrap Loader
when others=> dbus_in_cpu <= dbus_in; -- Embedded SRAM
end case;
end process;
-- HDL Embedded Text Block 7 clogic
clk <= CLOCK_40MHZ;
wrcom <= not wrn;
wea(0)<= not wrn;
PIN4 <= resoutn; -- For debug only
-- dbus_in_cpu multiplexer
sel_s <= cscom1 & csromn;
-- chip_select
-- Comport, uart_16550
-- COM1, 0x3F8-0x3FF
cscom1 <= '0' when (abus(15 downto 3)="0000001111111" AND iom='1') else '1';
-- Bootstrap ROM 256 bytes
-- FFFFF-FF=FFF00
csromn <= '0' when ((abus(19 downto 8)=X"FFF") AND iom='0') else '1';
nmi <= '0';
intr <= '0';
dout <= '0';
dout1 <= '0';
DCDn <= '0';
DSRn <= '0';
RIn <= '0';
por <= NOT(PIN3);
-- Instance port mappings.
U_1 : cpu86
PORT MAP (
clk => clk,
dbus_in => dbus_in_cpu,
intr => intr,
nmi => nmi,
por => por,
abus => abus,
cpuerror => LED1,
dbus_out => dbus_out,
inta => OPEN,
iom => iom,
rdn => rdn,
resoutn => resoutn,
wran => wran,
wrn => wrn
);
U_3 : blk_mem_40K
PORT MAP (
clka => clk,
dina => dbus_out,
addra => abus(15 DOWNTO 0),
wea => wea,
douta => dbus_in
);
U_2 : bootstrap
PORT MAP (
abus => abus(7 DOWNTO 0),
dbus => dbus_rom
);
U_0 : uart_top
PORT MAP (
BR_clk => rxclk_s,
CTSn => CTS,
DCDn => DCDn,
DSRn => DSRn,
RIn => RIn,
abus => abus(2 DOWNTO 0),
clk => clk,
csn => cscom1,
dbus_in => dbus_out,
rdn => rdn,
resetn => resoutn,
sRX => RXD,
wrn => wrn,
B_CLK => rxclk_s,
DTRn => OPEN,
IRQ => OPEN,
OUT1n => led2n,
OUT2n => led3n,
RTSn => RTS,
dbus_out => dbus_com1,
stx => TXD
);
END struct;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2207.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02207ent IS
END c07s02b06x00p01n01i02207ent;
ARCHITECTURE c07s02b06x00p01n01i02207arch OF c07s02b06x00p01n01i02207ent IS
BEGIN
TESTING: PROCESS
constant x : real := 15.5;
constant y : integer := 9;
variable z : integer;
BEGIN
z := x mod y; -- Failure_here
-- mod is not defined for real types.
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02207 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02207arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2207.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02207ent IS
END c07s02b06x00p01n01i02207ent;
ARCHITECTURE c07s02b06x00p01n01i02207arch OF c07s02b06x00p01n01i02207ent IS
BEGIN
TESTING: PROCESS
constant x : real := 15.5;
constant y : integer := 9;
variable z : integer;
BEGIN
z := x mod y; -- Failure_here
-- mod is not defined for real types.
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02207 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02207arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2207.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02207ent IS
END c07s02b06x00p01n01i02207ent;
ARCHITECTURE c07s02b06x00p01n01i02207arch OF c07s02b06x00p01n01i02207ent IS
BEGIN
TESTING: PROCESS
constant x : real := 15.5;
constant y : integer := 9;
variable z : integer;
BEGIN
z := x mod y; -- Failure_here
-- mod is not defined for real types.
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02207 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02207arch;
|
----------------------------------------------------------------------------------
-- stage.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Programmable 32 channel trigger stage. It can operate in serial
-- and parallel mode. In serial mode any of the la_input channels
-- can be used as la_input for the 32bit shift register. Comparison
-- is done using the value and mask registers on the la_input in
-- parallel mode and on the shift register in serial mode.
-- If armed and 'level' has reached the configured minimum value,
-- the stage will start to check for a match.
-- The match and run output signal delay can be configured.
-- The stage will disarm itself after a match occured or when reset is set.
--
-- The stage supports "high speed demux" operation in serial and parallel
-- mode. (Lower and upper 16 channels contain a 16bit sample each.)
--
-- Matching is done using a pipeline. This should not increase the minimum
-- time needed between two dependend trigger stage matches, because the
-- dependence is evaluated in the last pipeline step.
-- It does however increase the delay for the capturing process, but this
-- can easily be compensated by software.
-- (By adjusting the before/after ratio.)
--
-- Changes: Synchronous reset.
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity stage is
port(
la_input : in std_logic_vector (31 downto 0);
la_inputReady : in std_logic;
data : in std_logic_vector (31 downto 0);
clock : in std_logic;
reset : in std_logic;
wrMask : in std_logic;
wrValue : in std_logic;
wrConfig : in std_logic;
arm : in std_logic;
level : in std_logic_vector (1 downto 0);
demuxed : in std_logic;
run : out std_logic;
match : out std_logic
);
end stage;
architecture behavioral of stage is
type STATES is (OFF, ARMED, MATCHED);
signal maskRegister, valueRegister : std_logic_vector (31 downto 0);
signal intermediateRegister, shiftRegister : std_logic_vector (31 downto 0);
signal testValue: std_logic_vector (31 downto 0);
signal cfgStart, cfgSerial : std_logic;
signal cfgChannel : std_logic_vector(4 downto 0);
signal cfgLevel : std_logic_vector(1 downto 0);
signal counter, cfgDelay : std_logic_vector(15 downto 0);
signal matchL16, matchH16, match32Register : std_logic;
signal state : STATES;
signal serialChannelL16, serialChannelH16 : std_logic;
begin
-- use shift register or la_input depending on configuration
testValue <= shiftRegister when cfgSerial = '1' else la_input;
-- apply mask and value and create a additional pipeline step
process(clock)
begin
if rising_edge(clock) then
intermediateRegister <= (testValue xor valueRegister) and maskRegister;
end if;
end process;
-- match upper and lower word separately
matchL16 <= '1' when intermediateRegister(15 downto 0) = "0000000000000000" else '0';
matchH16 <= '1' when intermediateRegister(31 downto 16) = "0000000000000000" else '0';
-- in demux mode only one half must match, in normal mode both words must match
process(clock)
begin
if rising_edge(clock) then
if demuxed = '1' then
match32Register <= matchL16 or matchH16;
else
match32Register <= matchL16 and matchH16;
end if;
end if;
end process;
-- select serial channel based on cfgChannel
process(la_input, cfgChannel)
begin
for i in 0 to 15 loop
if conv_integer(cfgChannel(3 downto 0)) = i then
serialChannelL16 <= la_input(i);
serialChannelH16 <= la_input(i + 16);
end if;
end loop;
end process;
-- shift in bit from selected channel whenever la_input is ready
process(clock)
begin
if rising_edge(clock) then
if la_inputReady = '1' then
if demuxed = '1' then -- in demux mode two bits come in per sample
shiftRegister <= shiftRegister(29 downto 0) & serialChannelH16 & serialChannelL16;
elsif cfgChannel(4) = '1' then
shiftRegister <= shiftRegister(30 downto 0) & serialChannelH16;
else
shiftRegister <= shiftRegister(30 downto 0) & serialChannelL16;
end if;
end if;
end if;
end process;
-- trigger state machine
process(clock, reset)
begin
if rising_edge(clock) then
if reset = '1' then
state <= OFF;
else
run <= '0';
match <= '0';
case state is
when OFF =>
if arm = '1' then
state <= ARMED;
end if;
when ARMED =>
if match32Register = '1' and level >= cfgLevel then
counter <= cfgDelay;
state <= MATCHED;
end if;
when MATCHED =>
if la_inputReady = '1' then
if counter = "0000000000000000" then
run <= cfgStart;
match <= not cfgStart;
state <= OFF;
else
counter <= counter - 1;
end if;
end if;
end case;
end if;
end if;
end process;
-- handle mask, value & config register write requests
process(clock)
begin
if rising_edge(clock) then
if wrMask = '1' then
maskRegister <= data;
end if;
if wrValue = '1' then
valueRegister <= data;
end if;
if wrConfig = '1' then
cfgStart <= data(27);
cfgSerial <= data(26);
cfgChannel <= data(24 downto 20);
cfgLevel <= data(17 downto 16);
cfgDelay <= data(15 downto 0);
end if;
end if;
end process;
end behavioral;
|
----------------------------------------------------------------------------------
-- stage.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Programmable 32 channel trigger stage. It can operate in serial
-- and parallel mode. In serial mode any of the la_input channels
-- can be used as la_input for the 32bit shift register. Comparison
-- is done using the value and mask registers on the la_input in
-- parallel mode and on the shift register in serial mode.
-- If armed and 'level' has reached the configured minimum value,
-- the stage will start to check for a match.
-- The match and run output signal delay can be configured.
-- The stage will disarm itself after a match occured or when reset is set.
--
-- The stage supports "high speed demux" operation in serial and parallel
-- mode. (Lower and upper 16 channels contain a 16bit sample each.)
--
-- Matching is done using a pipeline. This should not increase the minimum
-- time needed between two dependend trigger stage matches, because the
-- dependence is evaluated in the last pipeline step.
-- It does however increase the delay for the capturing process, but this
-- can easily be compensated by software.
-- (By adjusting the before/after ratio.)
--
-- Changes: Synchronous reset.
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity stage is
port(
la_input : in std_logic_vector (31 downto 0);
la_inputReady : in std_logic;
data : in std_logic_vector (31 downto 0);
clock : in std_logic;
reset : in std_logic;
wrMask : in std_logic;
wrValue : in std_logic;
wrConfig : in std_logic;
arm : in std_logic;
level : in std_logic_vector (1 downto 0);
demuxed : in std_logic;
run : out std_logic;
match : out std_logic
);
end stage;
architecture behavioral of stage is
type STATES is (OFF, ARMED, MATCHED);
signal maskRegister, valueRegister : std_logic_vector (31 downto 0);
signal intermediateRegister, shiftRegister : std_logic_vector (31 downto 0);
signal testValue: std_logic_vector (31 downto 0);
signal cfgStart, cfgSerial : std_logic;
signal cfgChannel : std_logic_vector(4 downto 0);
signal cfgLevel : std_logic_vector(1 downto 0);
signal counter, cfgDelay : std_logic_vector(15 downto 0);
signal matchL16, matchH16, match32Register : std_logic;
signal state : STATES;
signal serialChannelL16, serialChannelH16 : std_logic;
begin
-- use shift register or la_input depending on configuration
testValue <= shiftRegister when cfgSerial = '1' else la_input;
-- apply mask and value and create a additional pipeline step
process(clock)
begin
if rising_edge(clock) then
intermediateRegister <= (testValue xor valueRegister) and maskRegister;
end if;
end process;
-- match upper and lower word separately
matchL16 <= '1' when intermediateRegister(15 downto 0) = "0000000000000000" else '0';
matchH16 <= '1' when intermediateRegister(31 downto 16) = "0000000000000000" else '0';
-- in demux mode only one half must match, in normal mode both words must match
process(clock)
begin
if rising_edge(clock) then
if demuxed = '1' then
match32Register <= matchL16 or matchH16;
else
match32Register <= matchL16 and matchH16;
end if;
end if;
end process;
-- select serial channel based on cfgChannel
process(la_input, cfgChannel)
begin
for i in 0 to 15 loop
if conv_integer(cfgChannel(3 downto 0)) = i then
serialChannelL16 <= la_input(i);
serialChannelH16 <= la_input(i + 16);
end if;
end loop;
end process;
-- shift in bit from selected channel whenever la_input is ready
process(clock)
begin
if rising_edge(clock) then
if la_inputReady = '1' then
if demuxed = '1' then -- in demux mode two bits come in per sample
shiftRegister <= shiftRegister(29 downto 0) & serialChannelH16 & serialChannelL16;
elsif cfgChannel(4) = '1' then
shiftRegister <= shiftRegister(30 downto 0) & serialChannelH16;
else
shiftRegister <= shiftRegister(30 downto 0) & serialChannelL16;
end if;
end if;
end if;
end process;
-- trigger state machine
process(clock, reset)
begin
if rising_edge(clock) then
if reset = '1' then
state <= OFF;
else
run <= '0';
match <= '0';
case state is
when OFF =>
if arm = '1' then
state <= ARMED;
end if;
when ARMED =>
if match32Register = '1' and level >= cfgLevel then
counter <= cfgDelay;
state <= MATCHED;
end if;
when MATCHED =>
if la_inputReady = '1' then
if counter = "0000000000000000" then
run <= cfgStart;
match <= not cfgStart;
state <= OFF;
else
counter <= counter - 1;
end if;
end if;
end case;
end if;
end if;
end process;
-- handle mask, value & config register write requests
process(clock)
begin
if rising_edge(clock) then
if wrMask = '1' then
maskRegister <= data;
end if;
if wrValue = '1' then
valueRegister <= data;
end if;
if wrConfig = '1' then
cfgStart <= data(27);
cfgSerial <= data(26);
cfgChannel <= data(24 downto 20);
cfgLevel <= data(17 downto 16);
cfgDelay <= data(15 downto 0);
end if;
end if;
end process;
end behavioral;
|
----------------------------------------------------------------------------------
-- stage.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Programmable 32 channel trigger stage. It can operate in serial
-- and parallel mode. In serial mode any of the la_input channels
-- can be used as la_input for the 32bit shift register. Comparison
-- is done using the value and mask registers on the la_input in
-- parallel mode and on the shift register in serial mode.
-- If armed and 'level' has reached the configured minimum value,
-- the stage will start to check for a match.
-- The match and run output signal delay can be configured.
-- The stage will disarm itself after a match occured or when reset is set.
--
-- The stage supports "high speed demux" operation in serial and parallel
-- mode. (Lower and upper 16 channels contain a 16bit sample each.)
--
-- Matching is done using a pipeline. This should not increase the minimum
-- time needed between two dependend trigger stage matches, because the
-- dependence is evaluated in the last pipeline step.
-- It does however increase the delay for the capturing process, but this
-- can easily be compensated by software.
-- (By adjusting the before/after ratio.)
--
-- Changes: Synchronous reset.
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity stage is
port(
la_input : in std_logic_vector (31 downto 0);
la_inputReady : in std_logic;
data : in std_logic_vector (31 downto 0);
clock : in std_logic;
reset : in std_logic;
wrMask : in std_logic;
wrValue : in std_logic;
wrConfig : in std_logic;
arm : in std_logic;
level : in std_logic_vector (1 downto 0);
demuxed : in std_logic;
run : out std_logic;
match : out std_logic
);
end stage;
architecture behavioral of stage is
type STATES is (OFF, ARMED, MATCHED);
signal maskRegister, valueRegister : std_logic_vector (31 downto 0);
signal intermediateRegister, shiftRegister : std_logic_vector (31 downto 0);
signal testValue: std_logic_vector (31 downto 0);
signal cfgStart, cfgSerial : std_logic;
signal cfgChannel : std_logic_vector(4 downto 0);
signal cfgLevel : std_logic_vector(1 downto 0);
signal counter, cfgDelay : std_logic_vector(15 downto 0);
signal matchL16, matchH16, match32Register : std_logic;
signal state : STATES;
signal serialChannelL16, serialChannelH16 : std_logic;
begin
-- use shift register or la_input depending on configuration
testValue <= shiftRegister when cfgSerial = '1' else la_input;
-- apply mask and value and create a additional pipeline step
process(clock)
begin
if rising_edge(clock) then
intermediateRegister <= (testValue xor valueRegister) and maskRegister;
end if;
end process;
-- match upper and lower word separately
matchL16 <= '1' when intermediateRegister(15 downto 0) = "0000000000000000" else '0';
matchH16 <= '1' when intermediateRegister(31 downto 16) = "0000000000000000" else '0';
-- in demux mode only one half must match, in normal mode both words must match
process(clock)
begin
if rising_edge(clock) then
if demuxed = '1' then
match32Register <= matchL16 or matchH16;
else
match32Register <= matchL16 and matchH16;
end if;
end if;
end process;
-- select serial channel based on cfgChannel
process(la_input, cfgChannel)
begin
for i in 0 to 15 loop
if conv_integer(cfgChannel(3 downto 0)) = i then
serialChannelL16 <= la_input(i);
serialChannelH16 <= la_input(i + 16);
end if;
end loop;
end process;
-- shift in bit from selected channel whenever la_input is ready
process(clock)
begin
if rising_edge(clock) then
if la_inputReady = '1' then
if demuxed = '1' then -- in demux mode two bits come in per sample
shiftRegister <= shiftRegister(29 downto 0) & serialChannelH16 & serialChannelL16;
elsif cfgChannel(4) = '1' then
shiftRegister <= shiftRegister(30 downto 0) & serialChannelH16;
else
shiftRegister <= shiftRegister(30 downto 0) & serialChannelL16;
end if;
end if;
end if;
end process;
-- trigger state machine
process(clock, reset)
begin
if rising_edge(clock) then
if reset = '1' then
state <= OFF;
else
run <= '0';
match <= '0';
case state is
when OFF =>
if arm = '1' then
state <= ARMED;
end if;
when ARMED =>
if match32Register = '1' and level >= cfgLevel then
counter <= cfgDelay;
state <= MATCHED;
end if;
when MATCHED =>
if la_inputReady = '1' then
if counter = "0000000000000000" then
run <= cfgStart;
match <= not cfgStart;
state <= OFF;
else
counter <= counter - 1;
end if;
end if;
end case;
end if;
end if;
end process;
-- handle mask, value & config register write requests
process(clock)
begin
if rising_edge(clock) then
if wrMask = '1' then
maskRegister <= data;
end if;
if wrValue = '1' then
valueRegister <= data;
end if;
if wrConfig = '1' then
cfgStart <= data(27);
cfgSerial <= data(26);
cfgChannel <= data(24 downto 20);
cfgLevel <= data(17 downto 16);
cfgDelay <= data(15 downto 0);
end if;
end if;
end process;
end behavioral;
|
----------------------------------------------------------------------------------
-- stage.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Programmable 32 channel trigger stage. It can operate in serial
-- and parallel mode. In serial mode any of the la_input channels
-- can be used as la_input for the 32bit shift register. Comparison
-- is done using the value and mask registers on the la_input in
-- parallel mode and on the shift register in serial mode.
-- If armed and 'level' has reached the configured minimum value,
-- the stage will start to check for a match.
-- The match and run output signal delay can be configured.
-- The stage will disarm itself after a match occured or when reset is set.
--
-- The stage supports "high speed demux" operation in serial and parallel
-- mode. (Lower and upper 16 channels contain a 16bit sample each.)
--
-- Matching is done using a pipeline. This should not increase the minimum
-- time needed between two dependend trigger stage matches, because the
-- dependence is evaluated in the last pipeline step.
-- It does however increase the delay for the capturing process, but this
-- can easily be compensated by software.
-- (By adjusting the before/after ratio.)
--
-- Changes: Synchronous reset.
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity stage is
port(
la_input : in std_logic_vector (31 downto 0);
la_inputReady : in std_logic;
data : in std_logic_vector (31 downto 0);
clock : in std_logic;
reset : in std_logic;
wrMask : in std_logic;
wrValue : in std_logic;
wrConfig : in std_logic;
arm : in std_logic;
level : in std_logic_vector (1 downto 0);
demuxed : in std_logic;
run : out std_logic;
match : out std_logic
);
end stage;
architecture behavioral of stage is
type STATES is (OFF, ARMED, MATCHED);
signal maskRegister, valueRegister : std_logic_vector (31 downto 0);
signal intermediateRegister, shiftRegister : std_logic_vector (31 downto 0);
signal testValue: std_logic_vector (31 downto 0);
signal cfgStart, cfgSerial : std_logic;
signal cfgChannel : std_logic_vector(4 downto 0);
signal cfgLevel : std_logic_vector(1 downto 0);
signal counter, cfgDelay : std_logic_vector(15 downto 0);
signal matchL16, matchH16, match32Register : std_logic;
signal state : STATES;
signal serialChannelL16, serialChannelH16 : std_logic;
begin
-- use shift register or la_input depending on configuration
testValue <= shiftRegister when cfgSerial = '1' else la_input;
-- apply mask and value and create a additional pipeline step
process(clock)
begin
if rising_edge(clock) then
intermediateRegister <= (testValue xor valueRegister) and maskRegister;
end if;
end process;
-- match upper and lower word separately
matchL16 <= '1' when intermediateRegister(15 downto 0) = "0000000000000000" else '0';
matchH16 <= '1' when intermediateRegister(31 downto 16) = "0000000000000000" else '0';
-- in demux mode only one half must match, in normal mode both words must match
process(clock)
begin
if rising_edge(clock) then
if demuxed = '1' then
match32Register <= matchL16 or matchH16;
else
match32Register <= matchL16 and matchH16;
end if;
end if;
end process;
-- select serial channel based on cfgChannel
process(la_input, cfgChannel)
begin
for i in 0 to 15 loop
if conv_integer(cfgChannel(3 downto 0)) = i then
serialChannelL16 <= la_input(i);
serialChannelH16 <= la_input(i + 16);
end if;
end loop;
end process;
-- shift in bit from selected channel whenever la_input is ready
process(clock)
begin
if rising_edge(clock) then
if la_inputReady = '1' then
if demuxed = '1' then -- in demux mode two bits come in per sample
shiftRegister <= shiftRegister(29 downto 0) & serialChannelH16 & serialChannelL16;
elsif cfgChannel(4) = '1' then
shiftRegister <= shiftRegister(30 downto 0) & serialChannelH16;
else
shiftRegister <= shiftRegister(30 downto 0) & serialChannelL16;
end if;
end if;
end if;
end process;
-- trigger state machine
process(clock, reset)
begin
if rising_edge(clock) then
if reset = '1' then
state <= OFF;
else
run <= '0';
match <= '0';
case state is
when OFF =>
if arm = '1' then
state <= ARMED;
end if;
when ARMED =>
if match32Register = '1' and level >= cfgLevel then
counter <= cfgDelay;
state <= MATCHED;
end if;
when MATCHED =>
if la_inputReady = '1' then
if counter = "0000000000000000" then
run <= cfgStart;
match <= not cfgStart;
state <= OFF;
else
counter <= counter - 1;
end if;
end if;
end case;
end if;
end if;
end process;
-- handle mask, value & config register write requests
process(clock)
begin
if rising_edge(clock) then
if wrMask = '1' then
maskRegister <= data;
end if;
if wrValue = '1' then
valueRegister <= data;
end if;
if wrConfig = '1' then
cfgStart <= data(27);
cfgSerial <= data(26);
cfgChannel <= data(24 downto 20);
cfgLevel <= data(17 downto 16);
cfgDelay <= data(15 downto 0);
end if;
end if;
end process;
end behavioral;
|
----------------------------------------------------------------------------------
-- stage.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Programmable 32 channel trigger stage. It can operate in serial
-- and parallel mode. In serial mode any of the la_input channels
-- can be used as la_input for the 32bit shift register. Comparison
-- is done using the value and mask registers on the la_input in
-- parallel mode and on the shift register in serial mode.
-- If armed and 'level' has reached the configured minimum value,
-- the stage will start to check for a match.
-- The match and run output signal delay can be configured.
-- The stage will disarm itself after a match occured or when reset is set.
--
-- The stage supports "high speed demux" operation in serial and parallel
-- mode. (Lower and upper 16 channels contain a 16bit sample each.)
--
-- Matching is done using a pipeline. This should not increase the minimum
-- time needed between two dependend trigger stage matches, because the
-- dependence is evaluated in the last pipeline step.
-- It does however increase the delay for the capturing process, but this
-- can easily be compensated by software.
-- (By adjusting the before/after ratio.)
--
-- Changes: Synchronous reset.
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity stage is
port(
la_input : in std_logic_vector (31 downto 0);
la_inputReady : in std_logic;
data : in std_logic_vector (31 downto 0);
clock : in std_logic;
reset : in std_logic;
wrMask : in std_logic;
wrValue : in std_logic;
wrConfig : in std_logic;
arm : in std_logic;
level : in std_logic_vector (1 downto 0);
demuxed : in std_logic;
run : out std_logic;
match : out std_logic
);
end stage;
architecture behavioral of stage is
type STATES is (OFF, ARMED, MATCHED);
signal maskRegister, valueRegister : std_logic_vector (31 downto 0);
signal intermediateRegister, shiftRegister : std_logic_vector (31 downto 0);
signal testValue: std_logic_vector (31 downto 0);
signal cfgStart, cfgSerial : std_logic;
signal cfgChannel : std_logic_vector(4 downto 0);
signal cfgLevel : std_logic_vector(1 downto 0);
signal counter, cfgDelay : std_logic_vector(15 downto 0);
signal matchL16, matchH16, match32Register : std_logic;
signal state : STATES;
signal serialChannelL16, serialChannelH16 : std_logic;
begin
-- use shift register or la_input depending on configuration
testValue <= shiftRegister when cfgSerial = '1' else la_input;
-- apply mask and value and create a additional pipeline step
process(clock)
begin
if rising_edge(clock) then
intermediateRegister <= (testValue xor valueRegister) and maskRegister;
end if;
end process;
-- match upper and lower word separately
matchL16 <= '1' when intermediateRegister(15 downto 0) = "0000000000000000" else '0';
matchH16 <= '1' when intermediateRegister(31 downto 16) = "0000000000000000" else '0';
-- in demux mode only one half must match, in normal mode both words must match
process(clock)
begin
if rising_edge(clock) then
if demuxed = '1' then
match32Register <= matchL16 or matchH16;
else
match32Register <= matchL16 and matchH16;
end if;
end if;
end process;
-- select serial channel based on cfgChannel
process(la_input, cfgChannel)
begin
for i in 0 to 15 loop
if conv_integer(cfgChannel(3 downto 0)) = i then
serialChannelL16 <= la_input(i);
serialChannelH16 <= la_input(i + 16);
end if;
end loop;
end process;
-- shift in bit from selected channel whenever la_input is ready
process(clock)
begin
if rising_edge(clock) then
if la_inputReady = '1' then
if demuxed = '1' then -- in demux mode two bits come in per sample
shiftRegister <= shiftRegister(29 downto 0) & serialChannelH16 & serialChannelL16;
elsif cfgChannel(4) = '1' then
shiftRegister <= shiftRegister(30 downto 0) & serialChannelH16;
else
shiftRegister <= shiftRegister(30 downto 0) & serialChannelL16;
end if;
end if;
end if;
end process;
-- trigger state machine
process(clock, reset)
begin
if rising_edge(clock) then
if reset = '1' then
state <= OFF;
else
run <= '0';
match <= '0';
case state is
when OFF =>
if arm = '1' then
state <= ARMED;
end if;
when ARMED =>
if match32Register = '1' and level >= cfgLevel then
counter <= cfgDelay;
state <= MATCHED;
end if;
when MATCHED =>
if la_inputReady = '1' then
if counter = "0000000000000000" then
run <= cfgStart;
match <= not cfgStart;
state <= OFF;
else
counter <= counter - 1;
end if;
end if;
end case;
end if;
end if;
end process;
-- handle mask, value & config register write requests
process(clock)
begin
if rising_edge(clock) then
if wrMask = '1' then
maskRegister <= data;
end if;
if wrValue = '1' then
valueRegister <= data;
end if;
if wrConfig = '1' then
cfgStart <= data(27);
cfgSerial <= data(26);
cfgChannel <= data(24 downto 20);
cfgLevel <= data(17 downto 16);
cfgDelay <= data(15 downto 0);
end if;
end if;
end process;
end behavioral;
|
----------------------------------------------------------------------------------
-- stage.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Programmable 32 channel trigger stage. It can operate in serial
-- and parallel mode. In serial mode any of the la_input channels
-- can be used as la_input for the 32bit shift register. Comparison
-- is done using the value and mask registers on the la_input in
-- parallel mode and on the shift register in serial mode.
-- If armed and 'level' has reached the configured minimum value,
-- the stage will start to check for a match.
-- The match and run output signal delay can be configured.
-- The stage will disarm itself after a match occured or when reset is set.
--
-- The stage supports "high speed demux" operation in serial and parallel
-- mode. (Lower and upper 16 channels contain a 16bit sample each.)
--
-- Matching is done using a pipeline. This should not increase the minimum
-- time needed between two dependend trigger stage matches, because the
-- dependence is evaluated in the last pipeline step.
-- It does however increase the delay for the capturing process, but this
-- can easily be compensated by software.
-- (By adjusting the before/after ratio.)
--
-- Changes: Synchronous reset.
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity stage is
port(
la_input : in std_logic_vector (31 downto 0);
la_inputReady : in std_logic;
data : in std_logic_vector (31 downto 0);
clock : in std_logic;
reset : in std_logic;
wrMask : in std_logic;
wrValue : in std_logic;
wrConfig : in std_logic;
arm : in std_logic;
level : in std_logic_vector (1 downto 0);
demuxed : in std_logic;
run : out std_logic;
match : out std_logic
);
end stage;
architecture behavioral of stage is
type STATES is (OFF, ARMED, MATCHED);
signal maskRegister, valueRegister : std_logic_vector (31 downto 0);
signal intermediateRegister, shiftRegister : std_logic_vector (31 downto 0);
signal testValue: std_logic_vector (31 downto 0);
signal cfgStart, cfgSerial : std_logic;
signal cfgChannel : std_logic_vector(4 downto 0);
signal cfgLevel : std_logic_vector(1 downto 0);
signal counter, cfgDelay : std_logic_vector(15 downto 0);
signal matchL16, matchH16, match32Register : std_logic;
signal state : STATES;
signal serialChannelL16, serialChannelH16 : std_logic;
begin
-- use shift register or la_input depending on configuration
testValue <= shiftRegister when cfgSerial = '1' else la_input;
-- apply mask and value and create a additional pipeline step
process(clock)
begin
if rising_edge(clock) then
intermediateRegister <= (testValue xor valueRegister) and maskRegister;
end if;
end process;
-- match upper and lower word separately
matchL16 <= '1' when intermediateRegister(15 downto 0) = "0000000000000000" else '0';
matchH16 <= '1' when intermediateRegister(31 downto 16) = "0000000000000000" else '0';
-- in demux mode only one half must match, in normal mode both words must match
process(clock)
begin
if rising_edge(clock) then
if demuxed = '1' then
match32Register <= matchL16 or matchH16;
else
match32Register <= matchL16 and matchH16;
end if;
end if;
end process;
-- select serial channel based on cfgChannel
process(la_input, cfgChannel)
begin
for i in 0 to 15 loop
if conv_integer(cfgChannel(3 downto 0)) = i then
serialChannelL16 <= la_input(i);
serialChannelH16 <= la_input(i + 16);
end if;
end loop;
end process;
-- shift in bit from selected channel whenever la_input is ready
process(clock)
begin
if rising_edge(clock) then
if la_inputReady = '1' then
if demuxed = '1' then -- in demux mode two bits come in per sample
shiftRegister <= shiftRegister(29 downto 0) & serialChannelH16 & serialChannelL16;
elsif cfgChannel(4) = '1' then
shiftRegister <= shiftRegister(30 downto 0) & serialChannelH16;
else
shiftRegister <= shiftRegister(30 downto 0) & serialChannelL16;
end if;
end if;
end if;
end process;
-- trigger state machine
process(clock, reset)
begin
if rising_edge(clock) then
if reset = '1' then
state <= OFF;
else
run <= '0';
match <= '0';
case state is
when OFF =>
if arm = '1' then
state <= ARMED;
end if;
when ARMED =>
if match32Register = '1' and level >= cfgLevel then
counter <= cfgDelay;
state <= MATCHED;
end if;
when MATCHED =>
if la_inputReady = '1' then
if counter = "0000000000000000" then
run <= cfgStart;
match <= not cfgStart;
state <= OFF;
else
counter <= counter - 1;
end if;
end if;
end case;
end if;
end if;
end process;
-- handle mask, value & config register write requests
process(clock)
begin
if rising_edge(clock) then
if wrMask = '1' then
maskRegister <= data;
end if;
if wrValue = '1' then
valueRegister <= data;
end if;
if wrConfig = '1' then
cfgStart <= data(27);
cfgSerial <= data(26);
cfgChannel <= data(24 downto 20);
cfgLevel <= data(17 downto 16);
cfgDelay <= data(15 downto 0);
end if;
end if;
end process;
end behavioral;
|
----------------------------------------------------------------------------------
-- stage.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Programmable 32 channel trigger stage. It can operate in serial
-- and parallel mode. In serial mode any of the la_input channels
-- can be used as la_input for the 32bit shift register. Comparison
-- is done using the value and mask registers on the la_input in
-- parallel mode and on the shift register in serial mode.
-- If armed and 'level' has reached the configured minimum value,
-- the stage will start to check for a match.
-- The match and run output signal delay can be configured.
-- The stage will disarm itself after a match occured or when reset is set.
--
-- The stage supports "high speed demux" operation in serial and parallel
-- mode. (Lower and upper 16 channels contain a 16bit sample each.)
--
-- Matching is done using a pipeline. This should not increase the minimum
-- time needed between two dependend trigger stage matches, because the
-- dependence is evaluated in the last pipeline step.
-- It does however increase the delay for the capturing process, but this
-- can easily be compensated by software.
-- (By adjusting the before/after ratio.)
--
-- Changes: Synchronous reset.
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity stage is
port(
la_input : in std_logic_vector (31 downto 0);
la_inputReady : in std_logic;
data : in std_logic_vector (31 downto 0);
clock : in std_logic;
reset : in std_logic;
wrMask : in std_logic;
wrValue : in std_logic;
wrConfig : in std_logic;
arm : in std_logic;
level : in std_logic_vector (1 downto 0);
demuxed : in std_logic;
run : out std_logic;
match : out std_logic
);
end stage;
architecture behavioral of stage is
type STATES is (OFF, ARMED, MATCHED);
signal maskRegister, valueRegister : std_logic_vector (31 downto 0);
signal intermediateRegister, shiftRegister : std_logic_vector (31 downto 0);
signal testValue: std_logic_vector (31 downto 0);
signal cfgStart, cfgSerial : std_logic;
signal cfgChannel : std_logic_vector(4 downto 0);
signal cfgLevel : std_logic_vector(1 downto 0);
signal counter, cfgDelay : std_logic_vector(15 downto 0);
signal matchL16, matchH16, match32Register : std_logic;
signal state : STATES;
signal serialChannelL16, serialChannelH16 : std_logic;
begin
-- use shift register or la_input depending on configuration
testValue <= shiftRegister when cfgSerial = '1' else la_input;
-- apply mask and value and create a additional pipeline step
process(clock)
begin
if rising_edge(clock) then
intermediateRegister <= (testValue xor valueRegister) and maskRegister;
end if;
end process;
-- match upper and lower word separately
matchL16 <= '1' when intermediateRegister(15 downto 0) = "0000000000000000" else '0';
matchH16 <= '1' when intermediateRegister(31 downto 16) = "0000000000000000" else '0';
-- in demux mode only one half must match, in normal mode both words must match
process(clock)
begin
if rising_edge(clock) then
if demuxed = '1' then
match32Register <= matchL16 or matchH16;
else
match32Register <= matchL16 and matchH16;
end if;
end if;
end process;
-- select serial channel based on cfgChannel
process(la_input, cfgChannel)
begin
for i in 0 to 15 loop
if conv_integer(cfgChannel(3 downto 0)) = i then
serialChannelL16 <= la_input(i);
serialChannelH16 <= la_input(i + 16);
end if;
end loop;
end process;
-- shift in bit from selected channel whenever la_input is ready
process(clock)
begin
if rising_edge(clock) then
if la_inputReady = '1' then
if demuxed = '1' then -- in demux mode two bits come in per sample
shiftRegister <= shiftRegister(29 downto 0) & serialChannelH16 & serialChannelL16;
elsif cfgChannel(4) = '1' then
shiftRegister <= shiftRegister(30 downto 0) & serialChannelH16;
else
shiftRegister <= shiftRegister(30 downto 0) & serialChannelL16;
end if;
end if;
end if;
end process;
-- trigger state machine
process(clock, reset)
begin
if rising_edge(clock) then
if reset = '1' then
state <= OFF;
else
run <= '0';
match <= '0';
case state is
when OFF =>
if arm = '1' then
state <= ARMED;
end if;
when ARMED =>
if match32Register = '1' and level >= cfgLevel then
counter <= cfgDelay;
state <= MATCHED;
end if;
when MATCHED =>
if la_inputReady = '1' then
if counter = "0000000000000000" then
run <= cfgStart;
match <= not cfgStart;
state <= OFF;
else
counter <= counter - 1;
end if;
end if;
end case;
end if;
end if;
end process;
-- handle mask, value & config register write requests
process(clock)
begin
if rising_edge(clock) then
if wrMask = '1' then
maskRegister <= data;
end if;
if wrValue = '1' then
valueRegister <= data;
end if;
if wrConfig = '1' then
cfgStart <= data(27);
cfgSerial <= data(26);
cfgChannel <= data(24 downto 20);
cfgLevel <= data(17 downto 16);
cfgDelay <= data(15 downto 0);
end if;
end if;
end process;
end behavioral;
|
----------------------------------------------------------------------------------
-- stage.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Programmable 32 channel trigger stage. It can operate in serial
-- and parallel mode. In serial mode any of the la_input channels
-- can be used as la_input for the 32bit shift register. Comparison
-- is done using the value and mask registers on the la_input in
-- parallel mode and on the shift register in serial mode.
-- If armed and 'level' has reached the configured minimum value,
-- the stage will start to check for a match.
-- The match and run output signal delay can be configured.
-- The stage will disarm itself after a match occured or when reset is set.
--
-- The stage supports "high speed demux" operation in serial and parallel
-- mode. (Lower and upper 16 channels contain a 16bit sample each.)
--
-- Matching is done using a pipeline. This should not increase the minimum
-- time needed between two dependend trigger stage matches, because the
-- dependence is evaluated in the last pipeline step.
-- It does however increase the delay for the capturing process, but this
-- can easily be compensated by software.
-- (By adjusting the before/after ratio.)
--
-- Changes: Synchronous reset.
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity stage is
port(
la_input : in std_logic_vector (31 downto 0);
la_inputReady : in std_logic;
data : in std_logic_vector (31 downto 0);
clock : in std_logic;
reset : in std_logic;
wrMask : in std_logic;
wrValue : in std_logic;
wrConfig : in std_logic;
arm : in std_logic;
level : in std_logic_vector (1 downto 0);
demuxed : in std_logic;
run : out std_logic;
match : out std_logic
);
end stage;
architecture behavioral of stage is
type STATES is (OFF, ARMED, MATCHED);
signal maskRegister, valueRegister : std_logic_vector (31 downto 0);
signal intermediateRegister, shiftRegister : std_logic_vector (31 downto 0);
signal testValue: std_logic_vector (31 downto 0);
signal cfgStart, cfgSerial : std_logic;
signal cfgChannel : std_logic_vector(4 downto 0);
signal cfgLevel : std_logic_vector(1 downto 0);
signal counter, cfgDelay : std_logic_vector(15 downto 0);
signal matchL16, matchH16, match32Register : std_logic;
signal state : STATES;
signal serialChannelL16, serialChannelH16 : std_logic;
begin
-- use shift register or la_input depending on configuration
testValue <= shiftRegister when cfgSerial = '1' else la_input;
-- apply mask and value and create a additional pipeline step
process(clock)
begin
if rising_edge(clock) then
intermediateRegister <= (testValue xor valueRegister) and maskRegister;
end if;
end process;
-- match upper and lower word separately
matchL16 <= '1' when intermediateRegister(15 downto 0) = "0000000000000000" else '0';
matchH16 <= '1' when intermediateRegister(31 downto 16) = "0000000000000000" else '0';
-- in demux mode only one half must match, in normal mode both words must match
process(clock)
begin
if rising_edge(clock) then
if demuxed = '1' then
match32Register <= matchL16 or matchH16;
else
match32Register <= matchL16 and matchH16;
end if;
end if;
end process;
-- select serial channel based on cfgChannel
process(la_input, cfgChannel)
begin
for i in 0 to 15 loop
if conv_integer(cfgChannel(3 downto 0)) = i then
serialChannelL16 <= la_input(i);
serialChannelH16 <= la_input(i + 16);
end if;
end loop;
end process;
-- shift in bit from selected channel whenever la_input is ready
process(clock)
begin
if rising_edge(clock) then
if la_inputReady = '1' then
if demuxed = '1' then -- in demux mode two bits come in per sample
shiftRegister <= shiftRegister(29 downto 0) & serialChannelH16 & serialChannelL16;
elsif cfgChannel(4) = '1' then
shiftRegister <= shiftRegister(30 downto 0) & serialChannelH16;
else
shiftRegister <= shiftRegister(30 downto 0) & serialChannelL16;
end if;
end if;
end if;
end process;
-- trigger state machine
process(clock, reset)
begin
if rising_edge(clock) then
if reset = '1' then
state <= OFF;
else
run <= '0';
match <= '0';
case state is
when OFF =>
if arm = '1' then
state <= ARMED;
end if;
when ARMED =>
if match32Register = '1' and level >= cfgLevel then
counter <= cfgDelay;
state <= MATCHED;
end if;
when MATCHED =>
if la_inputReady = '1' then
if counter = "0000000000000000" then
run <= cfgStart;
match <= not cfgStart;
state <= OFF;
else
counter <= counter - 1;
end if;
end if;
end case;
end if;
end if;
end process;
-- handle mask, value & config register write requests
process(clock)
begin
if rising_edge(clock) then
if wrMask = '1' then
maskRegister <= data;
end if;
if wrValue = '1' then
valueRegister <= data;
end if;
if wrConfig = '1' then
cfgStart <= data(27);
cfgSerial <= data(26);
cfgChannel <= data(24 downto 20);
cfgLevel <= data(17 downto 16);
cfgDelay <= data(15 downto 0);
end if;
end if;
end process;
end behavioral;
|
----------------------------------------------------------------------------------
-- stage.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Programmable 32 channel trigger stage. It can operate in serial
-- and parallel mode. In serial mode any of the la_input channels
-- can be used as la_input for the 32bit shift register. Comparison
-- is done using the value and mask registers on the la_input in
-- parallel mode and on the shift register in serial mode.
-- If armed and 'level' has reached the configured minimum value,
-- the stage will start to check for a match.
-- The match and run output signal delay can be configured.
-- The stage will disarm itself after a match occured or when reset is set.
--
-- The stage supports "high speed demux" operation in serial and parallel
-- mode. (Lower and upper 16 channels contain a 16bit sample each.)
--
-- Matching is done using a pipeline. This should not increase the minimum
-- time needed between two dependend trigger stage matches, because the
-- dependence is evaluated in the last pipeline step.
-- It does however increase the delay for the capturing process, but this
-- can easily be compensated by software.
-- (By adjusting the before/after ratio.)
--
-- Changes: Synchronous reset.
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity stage is
port(
la_input : in std_logic_vector (31 downto 0);
la_inputReady : in std_logic;
data : in std_logic_vector (31 downto 0);
clock : in std_logic;
reset : in std_logic;
wrMask : in std_logic;
wrValue : in std_logic;
wrConfig : in std_logic;
arm : in std_logic;
level : in std_logic_vector (1 downto 0);
demuxed : in std_logic;
run : out std_logic;
match : out std_logic
);
end stage;
architecture behavioral of stage is
type STATES is (OFF, ARMED, MATCHED);
signal maskRegister, valueRegister : std_logic_vector (31 downto 0);
signal intermediateRegister, shiftRegister : std_logic_vector (31 downto 0);
signal testValue: std_logic_vector (31 downto 0);
signal cfgStart, cfgSerial : std_logic;
signal cfgChannel : std_logic_vector(4 downto 0);
signal cfgLevel : std_logic_vector(1 downto 0);
signal counter, cfgDelay : std_logic_vector(15 downto 0);
signal matchL16, matchH16, match32Register : std_logic;
signal state : STATES;
signal serialChannelL16, serialChannelH16 : std_logic;
begin
-- use shift register or la_input depending on configuration
testValue <= shiftRegister when cfgSerial = '1' else la_input;
-- apply mask and value and create a additional pipeline step
process(clock)
begin
if rising_edge(clock) then
intermediateRegister <= (testValue xor valueRegister) and maskRegister;
end if;
end process;
-- match upper and lower word separately
matchL16 <= '1' when intermediateRegister(15 downto 0) = "0000000000000000" else '0';
matchH16 <= '1' when intermediateRegister(31 downto 16) = "0000000000000000" else '0';
-- in demux mode only one half must match, in normal mode both words must match
process(clock)
begin
if rising_edge(clock) then
if demuxed = '1' then
match32Register <= matchL16 or matchH16;
else
match32Register <= matchL16 and matchH16;
end if;
end if;
end process;
-- select serial channel based on cfgChannel
process(la_input, cfgChannel)
begin
for i in 0 to 15 loop
if conv_integer(cfgChannel(3 downto 0)) = i then
serialChannelL16 <= la_input(i);
serialChannelH16 <= la_input(i + 16);
end if;
end loop;
end process;
-- shift in bit from selected channel whenever la_input is ready
process(clock)
begin
if rising_edge(clock) then
if la_inputReady = '1' then
if demuxed = '1' then -- in demux mode two bits come in per sample
shiftRegister <= shiftRegister(29 downto 0) & serialChannelH16 & serialChannelL16;
elsif cfgChannel(4) = '1' then
shiftRegister <= shiftRegister(30 downto 0) & serialChannelH16;
else
shiftRegister <= shiftRegister(30 downto 0) & serialChannelL16;
end if;
end if;
end if;
end process;
-- trigger state machine
process(clock, reset)
begin
if rising_edge(clock) then
if reset = '1' then
state <= OFF;
else
run <= '0';
match <= '0';
case state is
when OFF =>
if arm = '1' then
state <= ARMED;
end if;
when ARMED =>
if match32Register = '1' and level >= cfgLevel then
counter <= cfgDelay;
state <= MATCHED;
end if;
when MATCHED =>
if la_inputReady = '1' then
if counter = "0000000000000000" then
run <= cfgStart;
match <= not cfgStart;
state <= OFF;
else
counter <= counter - 1;
end if;
end if;
end case;
end if;
end if;
end process;
-- handle mask, value & config register write requests
process(clock)
begin
if rising_edge(clock) then
if wrMask = '1' then
maskRegister <= data;
end if;
if wrValue = '1' then
valueRegister <= data;
end if;
if wrConfig = '1' then
cfgStart <= data(27);
cfgSerial <= data(26);
cfgChannel <= data(24 downto 20);
cfgLevel <= data(17 downto 16);
cfgDelay <= data(15 downto 0);
end if;
end if;
end process;
end behavioral;
|
----------------------------------------------------------------------------------
-- stage.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Programmable 32 channel trigger stage. It can operate in serial
-- and parallel mode. In serial mode any of the la_input channels
-- can be used as la_input for the 32bit shift register. Comparison
-- is done using the value and mask registers on the la_input in
-- parallel mode and on the shift register in serial mode.
-- If armed and 'level' has reached the configured minimum value,
-- the stage will start to check for a match.
-- The match and run output signal delay can be configured.
-- The stage will disarm itself after a match occured or when reset is set.
--
-- The stage supports "high speed demux" operation in serial and parallel
-- mode. (Lower and upper 16 channels contain a 16bit sample each.)
--
-- Matching is done using a pipeline. This should not increase the minimum
-- time needed between two dependend trigger stage matches, because the
-- dependence is evaluated in the last pipeline step.
-- It does however increase the delay for the capturing process, but this
-- can easily be compensated by software.
-- (By adjusting the before/after ratio.)
--
-- Changes: Synchronous reset.
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity stage is
port(
la_input : in std_logic_vector (31 downto 0);
la_inputReady : in std_logic;
data : in std_logic_vector (31 downto 0);
clock : in std_logic;
reset : in std_logic;
wrMask : in std_logic;
wrValue : in std_logic;
wrConfig : in std_logic;
arm : in std_logic;
level : in std_logic_vector (1 downto 0);
demuxed : in std_logic;
run : out std_logic;
match : out std_logic
);
end stage;
architecture behavioral of stage is
type STATES is (OFF, ARMED, MATCHED);
signal maskRegister, valueRegister : std_logic_vector (31 downto 0);
signal intermediateRegister, shiftRegister : std_logic_vector (31 downto 0);
signal testValue: std_logic_vector (31 downto 0);
signal cfgStart, cfgSerial : std_logic;
signal cfgChannel : std_logic_vector(4 downto 0);
signal cfgLevel : std_logic_vector(1 downto 0);
signal counter, cfgDelay : std_logic_vector(15 downto 0);
signal matchL16, matchH16, match32Register : std_logic;
signal state : STATES;
signal serialChannelL16, serialChannelH16 : std_logic;
begin
-- use shift register or la_input depending on configuration
testValue <= shiftRegister when cfgSerial = '1' else la_input;
-- apply mask and value and create a additional pipeline step
process(clock)
begin
if rising_edge(clock) then
intermediateRegister <= (testValue xor valueRegister) and maskRegister;
end if;
end process;
-- match upper and lower word separately
matchL16 <= '1' when intermediateRegister(15 downto 0) = "0000000000000000" else '0';
matchH16 <= '1' when intermediateRegister(31 downto 16) = "0000000000000000" else '0';
-- in demux mode only one half must match, in normal mode both words must match
process(clock)
begin
if rising_edge(clock) then
if demuxed = '1' then
match32Register <= matchL16 or matchH16;
else
match32Register <= matchL16 and matchH16;
end if;
end if;
end process;
-- select serial channel based on cfgChannel
process(la_input, cfgChannel)
begin
for i in 0 to 15 loop
if conv_integer(cfgChannel(3 downto 0)) = i then
serialChannelL16 <= la_input(i);
serialChannelH16 <= la_input(i + 16);
end if;
end loop;
end process;
-- shift in bit from selected channel whenever la_input is ready
process(clock)
begin
if rising_edge(clock) then
if la_inputReady = '1' then
if demuxed = '1' then -- in demux mode two bits come in per sample
shiftRegister <= shiftRegister(29 downto 0) & serialChannelH16 & serialChannelL16;
elsif cfgChannel(4) = '1' then
shiftRegister <= shiftRegister(30 downto 0) & serialChannelH16;
else
shiftRegister <= shiftRegister(30 downto 0) & serialChannelL16;
end if;
end if;
end if;
end process;
-- trigger state machine
process(clock, reset)
begin
if rising_edge(clock) then
if reset = '1' then
state <= OFF;
else
run <= '0';
match <= '0';
case state is
when OFF =>
if arm = '1' then
state <= ARMED;
end if;
when ARMED =>
if match32Register = '1' and level >= cfgLevel then
counter <= cfgDelay;
state <= MATCHED;
end if;
when MATCHED =>
if la_inputReady = '1' then
if counter = "0000000000000000" then
run <= cfgStart;
match <= not cfgStart;
state <= OFF;
else
counter <= counter - 1;
end if;
end if;
end case;
end if;
end if;
end process;
-- handle mask, value & config register write requests
process(clock)
begin
if rising_edge(clock) then
if wrMask = '1' then
maskRegister <= data;
end if;
if wrValue = '1' then
valueRegister <= data;
end if;
if wrConfig = '1' then
cfgStart <= data(27);
cfgSerial <= data(26);
cfgChannel <= data(24 downto 20);
cfgLevel <= data(17 downto 16);
cfgDelay <= data(15 downto 0);
end if;
end if;
end process;
end behavioral;
|
----------------------------------------------------------------------------------
-- stage.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Programmable 32 channel trigger stage. It can operate in serial
-- and parallel mode. In serial mode any of the la_input channels
-- can be used as la_input for the 32bit shift register. Comparison
-- is done using the value and mask registers on the la_input in
-- parallel mode and on the shift register in serial mode.
-- If armed and 'level' has reached the configured minimum value,
-- the stage will start to check for a match.
-- The match and run output signal delay can be configured.
-- The stage will disarm itself after a match occured or when reset is set.
--
-- The stage supports "high speed demux" operation in serial and parallel
-- mode. (Lower and upper 16 channels contain a 16bit sample each.)
--
-- Matching is done using a pipeline. This should not increase the minimum
-- time needed between two dependend trigger stage matches, because the
-- dependence is evaluated in the last pipeline step.
-- It does however increase the delay for the capturing process, but this
-- can easily be compensated by software.
-- (By adjusting the before/after ratio.)
--
-- Changes: Synchronous reset.
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity stage is
port(
la_input : in std_logic_vector (31 downto 0);
la_inputReady : in std_logic;
data : in std_logic_vector (31 downto 0);
clock : in std_logic;
reset : in std_logic;
wrMask : in std_logic;
wrValue : in std_logic;
wrConfig : in std_logic;
arm : in std_logic;
level : in std_logic_vector (1 downto 0);
demuxed : in std_logic;
run : out std_logic;
match : out std_logic
);
end stage;
architecture behavioral of stage is
type STATES is (OFF, ARMED, MATCHED);
signal maskRegister, valueRegister : std_logic_vector (31 downto 0);
signal intermediateRegister, shiftRegister : std_logic_vector (31 downto 0);
signal testValue: std_logic_vector (31 downto 0);
signal cfgStart, cfgSerial : std_logic;
signal cfgChannel : std_logic_vector(4 downto 0);
signal cfgLevel : std_logic_vector(1 downto 0);
signal counter, cfgDelay : std_logic_vector(15 downto 0);
signal matchL16, matchH16, match32Register : std_logic;
signal state : STATES;
signal serialChannelL16, serialChannelH16 : std_logic;
begin
-- use shift register or la_input depending on configuration
testValue <= shiftRegister when cfgSerial = '1' else la_input;
-- apply mask and value and create a additional pipeline step
process(clock)
begin
if rising_edge(clock) then
intermediateRegister <= (testValue xor valueRegister) and maskRegister;
end if;
end process;
-- match upper and lower word separately
matchL16 <= '1' when intermediateRegister(15 downto 0) = "0000000000000000" else '0';
matchH16 <= '1' when intermediateRegister(31 downto 16) = "0000000000000000" else '0';
-- in demux mode only one half must match, in normal mode both words must match
process(clock)
begin
if rising_edge(clock) then
if demuxed = '1' then
match32Register <= matchL16 or matchH16;
else
match32Register <= matchL16 and matchH16;
end if;
end if;
end process;
-- select serial channel based on cfgChannel
process(la_input, cfgChannel)
begin
for i in 0 to 15 loop
if conv_integer(cfgChannel(3 downto 0)) = i then
serialChannelL16 <= la_input(i);
serialChannelH16 <= la_input(i + 16);
end if;
end loop;
end process;
-- shift in bit from selected channel whenever la_input is ready
process(clock)
begin
if rising_edge(clock) then
if la_inputReady = '1' then
if demuxed = '1' then -- in demux mode two bits come in per sample
shiftRegister <= shiftRegister(29 downto 0) & serialChannelH16 & serialChannelL16;
elsif cfgChannel(4) = '1' then
shiftRegister <= shiftRegister(30 downto 0) & serialChannelH16;
else
shiftRegister <= shiftRegister(30 downto 0) & serialChannelL16;
end if;
end if;
end if;
end process;
-- trigger state machine
process(clock, reset)
begin
if rising_edge(clock) then
if reset = '1' then
state <= OFF;
else
run <= '0';
match <= '0';
case state is
when OFF =>
if arm = '1' then
state <= ARMED;
end if;
when ARMED =>
if match32Register = '1' and level >= cfgLevel then
counter <= cfgDelay;
state <= MATCHED;
end if;
when MATCHED =>
if la_inputReady = '1' then
if counter = "0000000000000000" then
run <= cfgStart;
match <= not cfgStart;
state <= OFF;
else
counter <= counter - 1;
end if;
end if;
end case;
end if;
end if;
end process;
-- handle mask, value & config register write requests
process(clock)
begin
if rising_edge(clock) then
if wrMask = '1' then
maskRegister <= data;
end if;
if wrValue = '1' then
valueRegister <= data;
end if;
if wrConfig = '1' then
cfgStart <= data(27);
cfgSerial <= data(26);
cfgChannel <= data(24 downto 20);
cfgLevel <= data(17 downto 16);
cfgDelay <= data(15 downto 0);
end if;
end if;
end process;
end behavioral;
|
----------------------------------------------------------------------------------
-- stage.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Programmable 32 channel trigger stage. It can operate in serial
-- and parallel mode. In serial mode any of the la_input channels
-- can be used as la_input for the 32bit shift register. Comparison
-- is done using the value and mask registers on the la_input in
-- parallel mode and on the shift register in serial mode.
-- If armed and 'level' has reached the configured minimum value,
-- the stage will start to check for a match.
-- The match and run output signal delay can be configured.
-- The stage will disarm itself after a match occured or when reset is set.
--
-- The stage supports "high speed demux" operation in serial and parallel
-- mode. (Lower and upper 16 channels contain a 16bit sample each.)
--
-- Matching is done using a pipeline. This should not increase the minimum
-- time needed between two dependend trigger stage matches, because the
-- dependence is evaluated in the last pipeline step.
-- It does however increase the delay for the capturing process, but this
-- can easily be compensated by software.
-- (By adjusting the before/after ratio.)
--
-- Changes: Synchronous reset.
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity stage is
port(
la_input : in std_logic_vector (31 downto 0);
la_inputReady : in std_logic;
data : in std_logic_vector (31 downto 0);
clock : in std_logic;
reset : in std_logic;
wrMask : in std_logic;
wrValue : in std_logic;
wrConfig : in std_logic;
arm : in std_logic;
level : in std_logic_vector (1 downto 0);
demuxed : in std_logic;
run : out std_logic;
match : out std_logic
);
end stage;
architecture behavioral of stage is
type STATES is (OFF, ARMED, MATCHED);
signal maskRegister, valueRegister : std_logic_vector (31 downto 0);
signal intermediateRegister, shiftRegister : std_logic_vector (31 downto 0);
signal testValue: std_logic_vector (31 downto 0);
signal cfgStart, cfgSerial : std_logic;
signal cfgChannel : std_logic_vector(4 downto 0);
signal cfgLevel : std_logic_vector(1 downto 0);
signal counter, cfgDelay : std_logic_vector(15 downto 0);
signal matchL16, matchH16, match32Register : std_logic;
signal state : STATES;
signal serialChannelL16, serialChannelH16 : std_logic;
begin
-- use shift register or la_input depending on configuration
testValue <= shiftRegister when cfgSerial = '1' else la_input;
-- apply mask and value and create a additional pipeline step
process(clock)
begin
if rising_edge(clock) then
intermediateRegister <= (testValue xor valueRegister) and maskRegister;
end if;
end process;
-- match upper and lower word separately
matchL16 <= '1' when intermediateRegister(15 downto 0) = "0000000000000000" else '0';
matchH16 <= '1' when intermediateRegister(31 downto 16) = "0000000000000000" else '0';
-- in demux mode only one half must match, in normal mode both words must match
process(clock)
begin
if rising_edge(clock) then
if demuxed = '1' then
match32Register <= matchL16 or matchH16;
else
match32Register <= matchL16 and matchH16;
end if;
end if;
end process;
-- select serial channel based on cfgChannel
process(la_input, cfgChannel)
begin
for i in 0 to 15 loop
if conv_integer(cfgChannel(3 downto 0)) = i then
serialChannelL16 <= la_input(i);
serialChannelH16 <= la_input(i + 16);
end if;
end loop;
end process;
-- shift in bit from selected channel whenever la_input is ready
process(clock)
begin
if rising_edge(clock) then
if la_inputReady = '1' then
if demuxed = '1' then -- in demux mode two bits come in per sample
shiftRegister <= shiftRegister(29 downto 0) & serialChannelH16 & serialChannelL16;
elsif cfgChannel(4) = '1' then
shiftRegister <= shiftRegister(30 downto 0) & serialChannelH16;
else
shiftRegister <= shiftRegister(30 downto 0) & serialChannelL16;
end if;
end if;
end if;
end process;
-- trigger state machine
process(clock, reset)
begin
if rising_edge(clock) then
if reset = '1' then
state <= OFF;
else
run <= '0';
match <= '0';
case state is
when OFF =>
if arm = '1' then
state <= ARMED;
end if;
when ARMED =>
if match32Register = '1' and level >= cfgLevel then
counter <= cfgDelay;
state <= MATCHED;
end if;
when MATCHED =>
if la_inputReady = '1' then
if counter = "0000000000000000" then
run <= cfgStart;
match <= not cfgStart;
state <= OFF;
else
counter <= counter - 1;
end if;
end if;
end case;
end if;
end if;
end process;
-- handle mask, value & config register write requests
process(clock)
begin
if rising_edge(clock) then
if wrMask = '1' then
maskRegister <= data;
end if;
if wrValue = '1' then
valueRegister <= data;
end if;
if wrConfig = '1' then
cfgStart <= data(27);
cfgSerial <= data(26);
cfgChannel <= data(24 downto 20);
cfgLevel <= data(17 downto 16);
cfgDelay <= data(15 downto 0);
end if;
end if;
end process;
end behavioral;
|
----------------------------------------------------------------------------------
-- stage.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Programmable 32 channel trigger stage. It can operate in serial
-- and parallel mode. In serial mode any of the la_input channels
-- can be used as la_input for the 32bit shift register. Comparison
-- is done using the value and mask registers on the la_input in
-- parallel mode and on the shift register in serial mode.
-- If armed and 'level' has reached the configured minimum value,
-- the stage will start to check for a match.
-- The match and run output signal delay can be configured.
-- The stage will disarm itself after a match occured or when reset is set.
--
-- The stage supports "high speed demux" operation in serial and parallel
-- mode. (Lower and upper 16 channels contain a 16bit sample each.)
--
-- Matching is done using a pipeline. This should not increase the minimum
-- time needed between two dependend trigger stage matches, because the
-- dependence is evaluated in the last pipeline step.
-- It does however increase the delay for the capturing process, but this
-- can easily be compensated by software.
-- (By adjusting the before/after ratio.)
--
-- Changes: Synchronous reset.
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity stage is
port(
la_input : in std_logic_vector (31 downto 0);
la_inputReady : in std_logic;
data : in std_logic_vector (31 downto 0);
clock : in std_logic;
reset : in std_logic;
wrMask : in std_logic;
wrValue : in std_logic;
wrConfig : in std_logic;
arm : in std_logic;
level : in std_logic_vector (1 downto 0);
demuxed : in std_logic;
run : out std_logic;
match : out std_logic
);
end stage;
architecture behavioral of stage is
type STATES is (OFF, ARMED, MATCHED);
signal maskRegister, valueRegister : std_logic_vector (31 downto 0);
signal intermediateRegister, shiftRegister : std_logic_vector (31 downto 0);
signal testValue: std_logic_vector (31 downto 0);
signal cfgStart, cfgSerial : std_logic;
signal cfgChannel : std_logic_vector(4 downto 0);
signal cfgLevel : std_logic_vector(1 downto 0);
signal counter, cfgDelay : std_logic_vector(15 downto 0);
signal matchL16, matchH16, match32Register : std_logic;
signal state : STATES;
signal serialChannelL16, serialChannelH16 : std_logic;
begin
-- use shift register or la_input depending on configuration
testValue <= shiftRegister when cfgSerial = '1' else la_input;
-- apply mask and value and create a additional pipeline step
process(clock)
begin
if rising_edge(clock) then
intermediateRegister <= (testValue xor valueRegister) and maskRegister;
end if;
end process;
-- match upper and lower word separately
matchL16 <= '1' when intermediateRegister(15 downto 0) = "0000000000000000" else '0';
matchH16 <= '1' when intermediateRegister(31 downto 16) = "0000000000000000" else '0';
-- in demux mode only one half must match, in normal mode both words must match
process(clock)
begin
if rising_edge(clock) then
if demuxed = '1' then
match32Register <= matchL16 or matchH16;
else
match32Register <= matchL16 and matchH16;
end if;
end if;
end process;
-- select serial channel based on cfgChannel
process(la_input, cfgChannel)
begin
for i in 0 to 15 loop
if conv_integer(cfgChannel(3 downto 0)) = i then
serialChannelL16 <= la_input(i);
serialChannelH16 <= la_input(i + 16);
end if;
end loop;
end process;
-- shift in bit from selected channel whenever la_input is ready
process(clock)
begin
if rising_edge(clock) then
if la_inputReady = '1' then
if demuxed = '1' then -- in demux mode two bits come in per sample
shiftRegister <= shiftRegister(29 downto 0) & serialChannelH16 & serialChannelL16;
elsif cfgChannel(4) = '1' then
shiftRegister <= shiftRegister(30 downto 0) & serialChannelH16;
else
shiftRegister <= shiftRegister(30 downto 0) & serialChannelL16;
end if;
end if;
end if;
end process;
-- trigger state machine
process(clock, reset)
begin
if rising_edge(clock) then
if reset = '1' then
state <= OFF;
else
run <= '0';
match <= '0';
case state is
when OFF =>
if arm = '1' then
state <= ARMED;
end if;
when ARMED =>
if match32Register = '1' and level >= cfgLevel then
counter <= cfgDelay;
state <= MATCHED;
end if;
when MATCHED =>
if la_inputReady = '1' then
if counter = "0000000000000000" then
run <= cfgStart;
match <= not cfgStart;
state <= OFF;
else
counter <= counter - 1;
end if;
end if;
end case;
end if;
end if;
end process;
-- handle mask, value & config register write requests
process(clock)
begin
if rising_edge(clock) then
if wrMask = '1' then
maskRegister <= data;
end if;
if wrValue = '1' then
valueRegister <= data;
end if;
if wrConfig = '1' then
cfgStart <= data(27);
cfgSerial <= data(26);
cfgChannel <= data(24 downto 20);
cfgLevel <= data(17 downto 16);
cfgDelay <= data(15 downto 0);
end if;
end if;
end process;
end behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1929.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n02i01929ent IS
END c07s02b01x00p01n02i01929ent;
ARCHITECTURE c07s02b01x00p01n02i01929arch OF c07s02b01x00p01n02i01929ent IS
BEGIN
TESTING: PROCESS
type B is array ( 1 to 1, 1 to 1 ) of BIT;
variable B1 : B;
BEGIN
B1 := not B'(1=>(1=>'0')); -- Failure_here
-- SEMANTIC ERROR: "not" not defined for multi-dimensional arrays.
assert FALSE
report "***FAILED TEST: c07s02b01x00p01n02i01929 - Logical operators are not valid for multi-dimensional arrays."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n02i01929arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1929.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n02i01929ent IS
END c07s02b01x00p01n02i01929ent;
ARCHITECTURE c07s02b01x00p01n02i01929arch OF c07s02b01x00p01n02i01929ent IS
BEGIN
TESTING: PROCESS
type B is array ( 1 to 1, 1 to 1 ) of BIT;
variable B1 : B;
BEGIN
B1 := not B'(1=>(1=>'0')); -- Failure_here
-- SEMANTIC ERROR: "not" not defined for multi-dimensional arrays.
assert FALSE
report "***FAILED TEST: c07s02b01x00p01n02i01929 - Logical operators are not valid for multi-dimensional arrays."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n02i01929arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1929.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n02i01929ent IS
END c07s02b01x00p01n02i01929ent;
ARCHITECTURE c07s02b01x00p01n02i01929arch OF c07s02b01x00p01n02i01929ent IS
BEGIN
TESTING: PROCESS
type B is array ( 1 to 1, 1 to 1 ) of BIT;
variable B1 : B;
BEGIN
B1 := not B'(1=>(1=>'0')); -- Failure_here
-- SEMANTIC ERROR: "not" not defined for multi-dimensional arrays.
assert FALSE
report "***FAILED TEST: c07s02b01x00p01n02i01929 - Logical operators are not valid for multi-dimensional arrays."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n02i01929arch;
|
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
-- Date : Thu May 22 13:06:25 2014
-- Host : macbook running 64-bit Arch Linux
-- Command : write_vhdl -force -mode synth_stub
-- /home/keith/Documents/VHDL-lib/top/mono_radio/ip/fir_lp_800kHz/fir_lp_800kHz_stub.vhdl
-- Design : fir_lp_800kHz
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fir_lp_800kHz is
Port (
aclk : in STD_LOGIC;
s_axis_data_tvalid : in STD_LOGIC;
s_axis_data_tready : out STD_LOGIC;
s_axis_data_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_data_tvalid : out STD_LOGIC;
m_axis_data_tdata : out STD_LOGIC_VECTOR ( 111 downto 0 )
);
end fir_lp_800kHz;
architecture stub of fir_lp_800kHz is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_data_tvalid,s_axis_data_tready,s_axis_data_tdata[31:0],m_axis_data_tvalid,m_axis_data_tdata[111:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "fir_compiler_v7_1,Vivado 2014.1";
begin
end;
|
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`protect end_protected
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use ieee.math_real.all;
use work.types_pkg.all;
use work.adaptations_pkg.all;
package string_methods_pkg is
-- Need a low level "alert" in the form of a simple assertion (as string handling may also fail)
procedure bitvis_assert(
val : boolean;
severeness : severity_level;
msg : string;
scope : string
);
-- DEPRECATED.
-- Function will be removed in future versions of UVVM-Util
function justify(
val : string;
width : natural := 0;
justified : side := RIGHT;
format: t_format_string := AS_IS -- No defaults on 4 first param - to avoid ambiguity with std.textio
) return string;
-- DEPRECATED.
-- Function will be removed in future versions of UVVM-Util
function justify(
val : string;
justified : side;
width : natural;
format_spaces : t_format_spaces;
truncate : t_truncate_string
) return string;
function justify(
val : string;
justified : t_justify_center;
width : natural;
format_spaces : t_format_spaces;
truncate : t_truncate_string
) return string;
function pos_of_leftmost(
target : character;
vector : string;
result_if_not_found : natural := 1
) return natural;
function pos_of_rightmost(
target : character;
vector : string;
result_if_not_found : natural := 1
) return natural;
function pos_of_leftmost_non_zero(
vector : string;
result_if_not_found : natural := 1
) return natural;
function pos_of_rightmost_non_whitespace(
vector : string;
result_if_not_found : natural := 1
) return natural;
function valid_length( -- of string excluding trailing NULs
vector : string
) return natural;
function get_string_between_delimiters(
val : string;
delim_left : character;
delim_right: character;
start_from : SIDE; -- search from left or right (Only RIGHT implemented so far)
occurrence : positive := 1 -- stop on N'th occurrence of delimeter pair. Default first occurrence
) return string;
impure function get_procedure_name_from_instance_name(
val : string
) return string;
impure function get_process_name_from_instance_name(
val : string
) return string;
impure function get_entity_name_from_instance_name(
val : string
) return string;
function return_string_if_true(
val : string;
return_val : boolean
) return string;
function return_string1_if_true_otherwise_string2(
val1 : string;
val2 : string;
return_val : boolean
) return string;
function to_upper(
val : string
) return string;
function fill_string(
val : character;
width : natural
) return string;
function pad_string(
val : string;
char : character;
width : natural;
side : side := LEFT
) return string;
function replace_backslash_n_with_lf(
source : string
) return string;
function replace_backslash_r_with_lf(
source : string
) return string;
function remove_initial_chars(
source : string;
num : natural
) return string;
function wrap_lines(
constant text_string : string;
constant alignment_pos1 : natural; -- Line position of first aligned character in line 1
constant alignment_pos2 : natural; -- Line position of first aligned character in line 2, etc...
constant line_width : natural
) return string;
procedure wrap_lines(
variable text_lines : inout line;
constant alignment_pos1 : natural; -- Line position prior to first aligned character (incl. Prefix)
constant alignment_pos2 : natural;
constant line_width : natural
);
procedure prefix_lines(
variable text_lines : inout line;
constant prefix : string := C_LOG_PREFIX
);
function replace(
val : string;
target_char : character;
exchange_char : character
) return string;
procedure replace(
variable text_line : inout line;
target_char : character;
exchange_char : character
);
--========================================================
-- Handle missing overloads from 'standard_additions'
--========================================================
function to_string(
val : boolean;
width : natural;
justified : side;
format_spaces : t_format_spaces;
truncate : t_truncate_string := DISALLOW_TRUNCATE
) return string;
impure function to_string(
val : integer;
width : natural;
justified : side;
format_spaces : t_format_spaces;
truncate : t_truncate_string := DISALLOW_TRUNCATE;
radix : t_radix := DEC;
prefix : t_radix_prefix := EXCL_RADIX;
format : t_format_zeros := SKIP_LEADING_0 -- | KEEP_LEADING_0
) return string;
impure function to_string(
val : integer;
radix : t_radix;
prefix : t_radix_prefix;
format : t_format_zeros := SKIP_LEADING_0 -- | KEEP_LEADING_0
) return string;
-- This function has been deprecated and will be removed in the next major release
-- DEPRECATED
function to_string(
val : boolean;
width : natural;
justified : side := right;
format: t_format_string := AS_IS
) return string;
-- This function has been deprecated and will be removed in the next major release
-- DEPRECATED
function to_string(
val : integer;
width : natural;
justified : side := right;
format : t_format_string := AS_IS
) return string;
function to_string(
val : std_logic_vector;
radix : t_radix;
format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string;
function to_string(
val : unsigned;
radix : t_radix;
format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string;
function to_string(
val : signed;
radix : t_radix;
format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string;
function to_string(
val : t_slv_array;
radix : t_radix := HEX_BIN_IF_INVALID;
format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string;
function to_string(
val : t_signed_array;
radix : t_radix := HEX_BIN_IF_INVALID;
format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string;
function to_string(
val : t_unsigned_array;
radix : t_radix := HEX_BIN_IF_INVALID;
format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string;
impure function to_string(
val : integer_vector;
radix : t_radix := DEC;
format : t_format_zeros := SKIP_LEADING_0; -- | KEEP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string;
impure function to_string(
val : t_natural_vector;
radix : t_radix := DEC;
format : t_format_zeros := SKIP_LEADING_0; -- | KEEP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string;
function to_string(
val : real_vector
) return string;
function to_string(
val : time_vector
) return string;
--========================================================
-- Handle types defined at lower levels
--========================================================
function to_string(
val : t_alert_level;
width : natural;
justified : side := right
) return string;
function to_string(
val : t_msg_id;
width : natural;
justified : side := right
) return string;
function to_string(
val : t_attention;
width : natural;
justified : side := right
) return string;
function to_string(
val : t_check_type;
width : natural;
justified : side := right
) return string;
procedure to_string(
val : t_alert_attention_counters;
order : t_order := FINAL
);
procedure to_string(
val : t_check_counters_array;
order : t_order := FINAL
);
function ascii_to_char(
ascii_pos : integer range 0 to 255;
ascii_allow : t_ascii_allow := ALLOW_ALL
) return character;
function char_to_ascii(
char : character
) return integer;
-- return string with only valid ascii characters
function to_string(
val : string
) return string;
function add_msg_delimiter(
msg : string
) return string;
-- Returns a string with a timestamp and a text. Used in report headers
function timestamp_header(
value : time;
txt : string) return string;
end package string_methods_pkg;
package body string_methods_pkg is
-- Need a low level "alert" in the form of a simple assertion (as string handling may also fail)
procedure bitvis_assert(
val : boolean;
severeness : severity_level;
msg : string;
scope : string
) is
begin
assert val
report LF & C_LOG_PREFIX & " *** " & to_string(severeness) & "*** caused by Bitvis Util > string handling > "
& scope & LF & C_LOG_PREFIX & " " & add_msg_delimiter(msg) & LF
severity severeness;
end;
function to_upper(
val : string
) return string is
variable v_result : string (val'range) := val;
variable char : character;
begin
for i in val'range loop
-- NOTE: Illegal characters are allowed and will pass through (check Mentor's std_developers_kit)
if ( v_result(i) >= 'a' and v_result(i) <= 'z') then
v_result(i) := character'val( character'pos(v_result(i)) - character'pos('a') + character'pos('A') );
end if;
end loop;
return v_result;
end to_upper;
function fill_string(
val : character;
width : natural
) return string is
variable v_result : string (1 to maximum(1, width));
begin
if (width = 0) then
return "";
else
for i in 1 to width loop
v_result(i) := val;
end loop;
end if;
return v_result;
end fill_string;
function pad_string(
val : string;
char : character;
width : natural;
side : side := LEFT
) return string is
variable v_result : string (1 to maximum(1, width));
begin
if (width = 0) then
return "";
elsif (width <= val'length) then
return val(1 to width);
else
v_result := (others => char);
if side = LEFT then
v_result(1 to val'length) := val;
else
v_result(v_result'length-val'length+1 to v_result'length) := val;
end if;
end if;
return v_result;
end pad_string;
-- This procedure has been deprecated, and will be removed in the near future.
function justify(
val : string;
width : natural := 0;
justified : side := RIGHT;
format : t_format_string := AS_IS -- No defaults on 4 first param - to avoid ambiguity with std.textio
) return string is
constant val_length : natural := val'length;
variable result : string(1 to width) := (others => ' ');
begin
-- return val if width is too small
if val_length >= width then
if (format = TRUNCATE) then
return val(1 to width);
else
return val;
end if;
end if;
if justified = left then
result(1 to val_length) := val;
elsif justified = right then
result(width - val_length + 1 to width) := val;
end if;
return result;
end function;
-- This procedure has been deprecated, and will be removed in the near future.
function justify(
val : string;
justified : side;
width : natural;
format_spaces : t_format_spaces;
truncate : t_truncate_string
) return string is
variable v_val_length : natural := val'length;
variable v_formatted_val : string (1 to val'length);
variable v_num_leading_space : natural := 0;
variable v_result : string(1 to width) := (others => ' ');
begin
-- Remove leading space if format_spaces is SKIP_LEADING_SPACE
if format_spaces = SKIP_LEADING_SPACE then
-- Find how many leading spaces there are
while( (val(v_num_leading_space+1) = ' ') and (v_num_leading_space < v_val_length)) loop
v_num_leading_space := v_num_leading_space + 1;
end loop;
-- Remove leading space if any
v_formatted_val := pad_string(remove_initial_chars(val,v_num_leading_space),' ',v_formatted_val'length,LEFT);
v_val_length := v_val_length - v_num_leading_space;
else
v_formatted_val := val;
end if;
-- Truncate and return if the string is wider that allowed
if v_val_length >= width then
if (truncate = ALLOW_TRUNCATE) then
return v_formatted_val(1 to width);
else
return v_formatted_val(1 to v_val_length);
end if;
end if;
-- Justify if string is within the width specifications
if justified = left then
v_result(1 to v_val_length) := v_formatted_val(1 to v_val_length);
elsif justified = right then
v_result(width - v_val_length + 1 to width) := v_formatted_val(1 to v_val_length);
end if;
return v_result;
end function;
function justify(
val : string;
justified : t_justify_center;
width : natural;
format_spaces : t_format_spaces;
truncate : t_truncate_string
) return string is
variable v_val_length : natural := val'length;
variable v_start_pos : natural;
variable v_formatted_val : string (1 to val'length);
variable v_num_leading_space : natural := 0;
variable v_result : string(1 to width) := (others => ' ');
begin
-- Remove leading space if format_spaces is SKIP_LEADING_SPACE
if format_spaces = SKIP_LEADING_SPACE then
-- Find how many leading spaces there are
while( (val(v_num_leading_space+1) = ' ') and (v_num_leading_space < v_val_length)) loop
v_num_leading_space := v_num_leading_space + 1;
end loop;
-- Remove leading space if any
v_formatted_val := pad_string(remove_initial_chars(val,v_num_leading_space),' ',v_formatted_val'length,LEFT);
v_val_length := v_val_length - v_num_leading_space;
else
v_formatted_val := val;
end if;
-- Truncate and return if the string is wider that allowed
if v_val_length >= width then
if (truncate = ALLOW_TRUNCATE) then
return v_formatted_val(1 to width);
else
return v_formatted_val(1 to v_val_length);
end if;
end if;
-- Justify if string is within the width specifications
v_start_pos := natural(ceil((real(width)-real(v_val_length))/real(2))) + 1;
v_result(v_start_pos to v_start_pos + v_val_length-1) := v_formatted_val(1 to v_val_length);
return v_result;
end function;
function pos_of_leftmost(
target : character;
vector : string;
result_if_not_found : natural := 1
) return natural is
alias a_vector : string(1 to vector'length) is vector;
begin
bitvis_assert(vector'length > 0, FAILURE, "String input is empty", "pos_of_leftmost()");
bitvis_assert(vector'ascending, FAILURE, "Only implemented for string(N to M)", "pos_of_leftmost()");
for i in a_vector'left to a_vector'right loop
if (a_vector(i) = target) then
return i;
end if;
end loop;
return result_if_not_found;
end;
function pos_of_rightmost(
target : character;
vector : string;
result_if_not_found : natural := 1
) return natural is
alias a_vector : string(1 to vector'length) is vector;
begin
bitvis_assert(vector'length > 0, FAILURE, "String input is empty", "pos_of_rightmost()");
bitvis_assert(vector'ascending, FAILURE, "Only implemented for string(N to M)", "pos_of_rightmost()");
for i in a_vector'right downto a_vector'left loop
if (a_vector(i) = target) then
return i;
end if;
end loop;
return result_if_not_found;
end;
function pos_of_leftmost_non_zero(
vector : string;
result_if_not_found : natural := 1
) return natural is
alias a_vector : string(1 to vector'length) is vector;
begin
bitvis_assert(vector'length > 0, FAILURE, "String input is empty", "pos_of_leftmost_non_zero()");
for i in a_vector'left to a_vector'right loop
if (a_vector(i) /= '0' and a_vector(i) /= ' ') then
return i;
end if;
end loop;
return result_if_not_found;
end;
function pos_of_rightmost_non_whitespace(
vector : string;
result_if_not_found : natural := 1
) return natural is
alias a_vector : string(1 to vector'length) is vector;
begin
bitvis_assert(vector'length > 0, FAILURE, "String input is empty", "pos_of_rightmost_non_whitespace()");
for i in a_vector'right downto a_vector'left loop
if a_vector(i) /= ' ' then
return i;
end if;
end loop;
return result_if_not_found;
end;
function valid_length( -- of string excluding trailing NULs
vector : string
) return natural is
begin
return pos_of_leftmost(NUL, vector, vector'length) - 1;
end;
function string_contains_char(
val : string;
char : character
) return boolean is
alias a_val : string(1 to val'length) is val;
begin
if (val'length = 0) then
return false;
else
for i in val'left to val'right loop
if (val(i) = char) then
return true;
end if;
end loop;
-- falls through only if not found
return false;
end if;
end;
-- get_*_name
-- Note: for sub-programs the following is given: library:package:procedure:object
-- Note: for design hierachy the following is given: complete hierarchy from sim-object down to process object
-- e.g. 'sbi_tb:i_test_harness:i2_sbi_vvc:p_constructor:v_msg'
-- Attribute instance_name also gives [procedure signature] or @entity-name(architecture name)
function get_string_between_delimiters(
val : string;
delim_left : character;
delim_right: character;
start_from : SIDE; -- search from left or right (Only RIGHT implemented so far)
occurrence : positive := 1 -- stop on N'th occurrence of delimeter pair. Default first occurrence
) return string is
variable v_left : natural := 0;
variable v_right : natural := 0;
variable v_start : natural := val'length;
variable v_occurrence : natural := 0;
alias a_val : string(1 to val'length) is val;
begin
bitvis_assert(a_val'length > 2, FAILURE, "String input is not wide enough (<3)", "get_string_between_delimiters()");
bitvis_assert(start_from = RIGHT, FAILURE, "Only search from RIGHT is implemented so far", "get_string_between_delimiters()");
loop
-- RIGHT
v_left := 0; -- default
v_right := pos_of_rightmost(delim_right, a_val(1 to v_start), 0);
if v_right > 0 then -- i.e. found
L1: for i in v_right-1 downto 1 loop -- searching backwards for delimeter
if (a_val(i) = delim_left) then
v_left := i;
v_start := i; -- Previous end delimeter could also be a start delimeter for next section
v_occurrence := v_occurrence + 1;
exit L1;
end if;
end loop; -- searching backwards
end if;
if v_right = 0 or v_left = 0 then
return ""; -- No delimeter pair found, and none can be found in the rest (with chars in between)
end if;
if v_occurrence = occurrence then
-- Match
if (v_right - v_left) < 2 then
return ""; -- no chars in between delimeters
else
return a_val(v_left+1 to v_right-1);
end if;
end if;
if v_start < 3 then
return ""; -- No delimeter pair found, and none can be found in the rest (with chars in between)
end if;
end loop; -- Will continue until match or not found
end;
-- ':sbi_tb(func):i_test_harness@test_harness(struct):i2_sbi_vvc@sbi_vvc(struct):p_constructor:instance'
-- ':sbi_tb:i_test_harness:i1_sbi_vvc:p_constructor:instance'
-- - Process name: Search for 2nd last param in path name
-- - Entity name: Search for 3nd last param in path name
--':bitvis_vip_sbi:sbi_bfm_pkg:sbi_write[unsigned,std_logic_vector,string,std_logic,std_logic,unsigned,
-- std_logic,std_logic,std_logic,std_logic_vector,time,string,t_msg_id_panel,t_sbi_config]:msg'
-- - Procedure name: Search for 2nd last param in path name and remove all inside []
impure function get_procedure_name_from_instance_name(
val : string
) return string is
variable v_line : line;
variable v_msg_line : line;
impure function return_and_deallocate return string is
constant r : string := v_line.all;
begin
DEALLOCATE(v_line);
return r;
end function;
begin
bitvis_assert(val'length > 2, FAILURE, "String input is not wide enough (<3)", "get_procedure_name_from_instance_name()");
write(v_line, get_string_between_delimiters(val, ':', '[', RIGHT));
if (string_contains_char(val, '@')) then
write(v_msg_line, string'("Must be called with <sub-program object>'instance_name"));
else
write(v_msg_line, string'(" "));
end if;
bitvis_assert(v_line'length > 0, ERROR, "No procedure name found. " & v_msg_line.all, "get_procedure_name_from_instance_name()");
DEALLOCATE(v_msg_line);
return return_and_deallocate;
end;
impure function get_process_name_from_instance_name(
val : string
) return string is
variable v_line : line;
variable v_msg_line : line;
impure function return_and_deallocate return string is
constant r : string := v_line.all;
begin
DEALLOCATE(v_line);
return r;
end function;
begin
bitvis_assert(val'length > 2, FAILURE, "String input is not wide enough (<3)", "get_process_name_from_instance_name()");
write(v_line, get_string_between_delimiters(val, ':', ':', RIGHT));
if (string_contains_char(val, '[')) then
write(v_msg_line, string'("Must be called with <process-local object>'instance_name"));
else
write(v_msg_line, string'(" "));
end if;
bitvis_assert(v_line'length > 0, ERROR, "No process name found", "get_process_name_from_instance_name()");
return return_and_deallocate;
end;
impure function get_entity_name_from_instance_name(
val : string
) return string is
variable v_line : line;
variable v_msg_line : line;
impure function return_and_deallocate return string is
constant r : string := v_line.all;
begin
DEALLOCATE(v_line);
return r;
end function;
begin
bitvis_assert(val'length > 2, FAILURE, "String input is not wide enough (<3)", "get_entity_name_from_instance_name()");
if string_contains_char(val, '@') then -- for path with instantiations
write(v_line, get_string_between_delimiters(val, '@', '(', RIGHT));
else -- for path with only a single entity
write(v_line, get_string_between_delimiters(val, ':', '(', RIGHT));
end if;
if (string_contains_char(val, '[')) then
write(v_msg_line, string'("Must be called with <Entity/arch-local object>'instance_name"));
else
write(v_msg_line, string'(" "));
end if;
bitvis_assert(v_line'length > 0, ERROR, "No entity name found", "get_entity_name_from_instance_name()");
return return_and_deallocate;
end;
function adjust_leading_0(
val : string;
format : t_format_zeros := SKIP_LEADING_0
) return string is
alias a_val : string(1 to val'length) is val;
constant leftmost_non_zero : natural := pos_of_leftmost_non_zero(a_val, 1);
begin
if val'length <= 1 then
return val;
end if;
if format = SKIP_LEADING_0 then
return a_val(leftmost_non_zero to val'length);
else
return a_val;
end if;
end function;
function return_string_if_true(
val : string;
return_val : boolean
) return string is
begin
if return_val then
return val;
else
return "";
end if;
end function;
function return_string1_if_true_otherwise_string2(
val1 : string;
val2 : string;
return_val : boolean
) return string is
begin
if return_val then
return val1;
else
return val2;
end if;
end function;
function replace_backslash_n_with_lf(
source : string
) return string is
variable v_source_idx : natural := 0;
variable v_dest_idx : natural := 0;
variable v_dest : string(1 to source'length);
begin
if source'length = 0 then
return "";
else
if C_USE_BACKSLASH_N_AS_LF then
loop
v_source_idx := v_source_idx + 1;
v_dest_idx := v_dest_idx + 1;
if (v_source_idx < source'length) then
if (source(v_source_idx to v_source_idx +1) /= "\n") then
v_dest(v_dest_idx) := source(v_source_idx);
else
v_dest(v_dest_idx) := LF;
v_source_idx := v_source_idx + 1; -- Additional increment as two chars (\n) are consumed
if (v_source_idx = source'length) then
exit;
end if;
end if;
else
-- Final character in string
v_dest(v_dest_idx) := source(v_source_idx);
exit;
end if;
end loop;
else
v_dest := source;
v_dest_idx := source'length;
end if;
return v_dest(1 to v_dest_idx);
end if;
end;
function replace_backslash_r_with_lf(
source : string
) return string is
variable v_source_idx : natural := 0;
variable v_dest_idx : natural := 0;
variable v_dest : string(1 to source'length);
begin
if source'length = 0 then
return "";
else
if C_USE_BACKSLASH_R_AS_LF then
loop
if (source(v_source_idx to v_source_idx+1) = "\r") then
v_dest_idx := v_dest_idx + 1;
v_dest(v_dest_idx) := LF;
v_source_idx := v_source_idx + 2;
else
exit;
end if;
end loop;
else
return "";
end if;
end if;
return v_dest(1 to v_dest_idx);
end;
function remove_initial_chars(
source : string;
num : natural
) return string is
begin
if source'length <= num then
return "";
else
return source(1 + num to source'right);
end if;
end;
function wrap_lines(
constant text_string : string;
constant alignment_pos1 : natural; -- Line position of first aligned character in line 1
constant alignment_pos2 : natural; -- Line position of first aligned character in line 2
constant line_width : natural
) return string is
variable v_text_lines : line;
variable v_result : string(1 to 2 * text_string'length + alignment_pos1 + 100); -- Margin for aligns and LF insertions
variable v_result_width : natural;
begin
write(v_text_lines, text_string);
wrap_lines(v_text_lines, alignment_pos1, alignment_pos2, line_width);
v_result_width := v_text_lines'length;
bitvis_assert(v_result_width <= v_result'length, FAILURE,
" String is too long after wrapping. Increase v_result string size.", "wrap_lines()");
v_result(1 to v_result_width) := v_text_lines.all;
deallocate(v_text_lines);
return v_result(1 to v_result_width);
end;
procedure wrap_lines(
variable text_lines : inout line;
constant alignment_pos1 : natural; -- Line position of first aligned character in line 1
constant alignment_pos2 : natural; -- Line position of first aligned character in line 2
constant line_width : natural
) is
constant v_string : string(1 to text_lines'length) := text_lines.all;
constant v_string_width : natural := text_lines'length;
variable v_line_no : natural := 0;
variable v_last_string_wrap : natural := 0;
variable v_min_string_wrap : natural;
variable v_max_string_wrap : natural;
begin
deallocate(text_lines); -- empty the line prior to filling it up again
l_line: loop -- For every tekstline found in text_lines
v_line_no := v_line_no + 1;
-- Find position to wrap in v_string
if (v_line_no = 1) then
v_min_string_wrap := 1; -- Minimum 1 character of input line
v_max_string_wrap := minimum(line_width - alignment_pos1 + 1, v_string_width);
write(text_lines, fill_string(' ', alignment_pos1 - 1));
else
v_min_string_wrap := v_last_string_wrap + 1; -- Minimum 1 character further into the inpit line
v_max_string_wrap := minimum(v_last_string_wrap + (line_width - alignment_pos2 + 1), v_string_width);
write(text_lines, fill_string(' ', alignment_pos2 - 1));
end if;
-- 1. First handle any potential explicit line feed in the current maximum text line
-- Search forward for potential LF
for i in (v_last_string_wrap + 1) to minimum(v_max_string_wrap + 1, v_string_width) loop
if (character(v_string(i)) = LF) then
write(text_lines, v_string((v_last_string_wrap + 1) to i)); -- LF now terminates this part
v_last_string_wrap := i;
next l_line; -- next line
end if;
end loop;
-- 2. Then check if remaining text fits into a single text line
if (v_string_width <= v_max_string_wrap) then
-- No (more) wrapping required
write(text_lines, v_string((v_last_string_wrap + 1) to v_string_width));
exit; -- No more lines
end if;
-- 3. Search for blanks from char after max msg width and downwards (in the left direction)
for i in v_max_string_wrap + 1 downto (v_last_string_wrap + 1) loop
if (character(v_string(i)) = ' ') then
write(text_lines, v_string((v_last_string_wrap + 1) to i-1)); -- Exchange last blank with LF
v_last_string_wrap := i;
if (i = v_string_width ) then
exit l_line;
end if;
-- Skip any potential extra blanks in the string
for j in (i+1) to v_string_width loop
if (v_string(j) = ' ') then
v_last_string_wrap := j;
if (j = v_string_width ) then
exit l_line;
end if;
else
write(text_lines, LF); -- Exchange last blanks with LF, provided not at the end of the string
exit;
end if;
end loop;
next l_line; -- next line
end if;
end loop;
-- 4. At this point no LF or blank is found in the searched section of the string.
-- Hence just break the string - and continue.
write(text_lines, v_string((v_last_string_wrap + 1) to v_max_string_wrap) & LF); -- Added LF termination
v_last_string_wrap := v_max_string_wrap;
end loop;
end;
procedure prefix_lines(
variable text_lines : inout line;
constant prefix : string := C_LOG_PREFIX
) is
constant v_string : string(1 to text_lines'length) := text_lines.all;
constant v_string_width : natural := text_lines'length;
constant prefix_width : natural := prefix'length;
variable v_last_string_wrap : natural := 0;
variable i : natural := 0; -- for indexing v_string
begin
deallocate(text_lines); -- empty the line prior to filling it up again
l_line : loop
-- 1. Write prefix
write(text_lines, prefix);
-- 2. Write rest of text line (or rest of input line if no LF)
l_char: loop
i := i + 1;
if (i < v_string_width) then
if (character(v_string(i)) = LF) then
write(text_lines, v_string((v_last_string_wrap + 1) to i));
v_last_string_wrap := i;
exit l_char;
end if;
else
-- 3. Reached end of string. Hence just write the rest.
write(text_lines, v_string((v_last_string_wrap + 1) to v_string_width));
-- But ensure new line with prefix if ending with LF
if (v_string(i) = LF) then
write(text_lines, prefix);
end if;
exit l_char;
end if;
end loop;
if (i = v_string_width) then
exit;
end if;
end loop;
end;
function replace(
val : string;
target_char : character;
exchange_char : character
) return string is
variable result : string(1 to val'length) := val;
begin
for i in val'range loop
if val(i) = target_char then
result(i) := exchange_char;
end if;
end loop;
return result;
end;
procedure replace(
variable text_line : inout line;
target_char : character;
exchange_char : character
) is
variable v_string : string(1 to text_line'length) := text_line.all;
variable v_string_width : natural := text_line'length;
variable i : natural := 0; -- for indexing v_string
begin
if v_string_width > 0 then
deallocate(text_line); -- empty the line prior to filling it up again
-- 1. Loop through string and replace characters
l_char: loop
i := i + 1;
if (i < v_string_width) then
if (character(v_string(i)) = target_char) then
v_string(i) := exchange_char;
end if;
else
-- 2. Reached end of string. Hence just write the new string.
write(text_line, v_string);
exit l_char;
end if;
end loop;
end if;
end;
--========================================================
-- Handle missing overloads from 'standard_additions' + advanced overloads
--========================================================
function to_string(
val : boolean;
width : natural;
justified : side;
format_spaces : t_format_spaces;
truncate : t_truncate_string := DISALLOW_TRUNCATE
) return string is
begin
return justify(to_string(val), justified, width, format_spaces, truncate);
end;
impure function to_string(
val : integer;
width : natural;
justified : side;
format_spaces : t_format_spaces;
truncate : t_truncate_string := DISALLOW_TRUNCATE;
radix : t_radix := DEC;
prefix : t_radix_prefix := EXCL_RADIX;
format : t_format_zeros := SKIP_LEADING_0 -- | KEEP_LEADING_0
) return string is
variable v_val_slv : std_logic_vector(31 downto 0) := std_logic_vector(to_signed(val, 32));
variable v_line : line;
variable v_width : natural;
variable v_use_end_char : boolean := false;
impure function return_and_deallocate return string is
constant r : string := v_line.all;
begin
DEALLOCATE(v_line);
return r;
end function;
begin
if radix = DEC then
if prefix = INCL_RADIX then
write(v_line, string'("d"""));
v_use_end_char := true;
end if;
write(v_line, justify(to_string(val), justified, width, format_spaces, truncate));
elsif radix = BIN then
if prefix = INCL_RADIX then
write(v_line, string'("b"""));
v_use_end_char := true;
end if;
write(v_line, adjust_leading_0(justify(to_string(v_val_slv), justified, width, format_spaces, truncate), format));
else -- HEX
if prefix = INCL_RADIX then
write(v_line, string'("x"""));
v_use_end_char := true;
end if;
write(v_line, adjust_leading_0(justify(to_hstring(v_val_slv), justified, width, format_spaces, truncate), format));
end if;
if v_use_end_char then
write(v_line, string'(""""));
end if;
return return_and_deallocate;
end;
impure function to_string(
val : integer;
radix : t_radix;
prefix : t_radix_prefix;
format : t_format_zeros := SKIP_LEADING_0 -- | KEEP_LEADING_0
) return string is
variable v_line : line;
variable v_len : natural;
begin
write(v_line, to_string(val));
v_len := v_line'length;
deallocate(v_line);
return to_string(val, v_len, LEFT, SKIP_LEADING_SPACE, DISALLOW_TRUNCATE, radix, prefix, format);
end;
-- This function has been deprecated and will be removed in the next major release
function to_string(
val : boolean;
width : natural;
justified : side := right;
format : t_format_string := AS_IS
) return string is
begin
return justify(to_string(val), width, justified, format);
end;
-- This function has been deprecated and will be removed in the next major release
function to_string(
val : integer;
width : natural;
justified : side := right;
format : t_format_string := AS_IS
) return string is
begin
return justify(to_string(val), width, justified, format);
end;
function to_string(
val : std_logic_vector;
radix : t_radix;
format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string is
variable v_line : line;
alias a_val : std_logic_vector(val'length - 1 downto 0) is val;
variable v_result : string(1 to 10 + 2 * val'length); --
variable v_width : natural;
variable v_use_end_char : boolean := false;
begin
if val'length = 0 then
-- Value length is zero,
-- return empty string.
return "";
end if;
if radix = BIN then
if prefix = INCL_RADIX then
write(v_line, string'("b"""));
v_use_end_char := true;
end if;
write(v_line, adjust_leading_0(to_string(val), format));
elsif radix = HEX then
if prefix = INCL_RADIX then
write(v_line, string'("x"""));
v_use_end_char := true;
end if;
write(v_line, adjust_leading_0(to_hstring(val), format));
elsif radix = DEC then
-- Assuming that val is not signed
if (val'length > 31) then
if prefix = INCL_RADIX then
write(v_line, string'("x"""));
v_use_end_char := true;
end if;
write(v_line, to_hstring(val) & " (too wide to be converted to integer)" );
else
if prefix = INCL_RADIX then
write(v_line, string'("d"""));
v_use_end_char := true;
end if;
write(v_line, adjust_leading_0(to_string(to_integer(unsigned(val))), format));
end if;
elsif radix = HEX_BIN_IF_INVALID then
if prefix = INCL_RADIX then
write(v_line, string'("x"""));
end if;
if is_x(val) then
write(v_line, adjust_leading_0(to_hstring(val), format));
if prefix = INCL_RADIX then
write(v_line, string'("""")); -- terminate hex value
end if;
write(v_line, string'(" (b"""));
write(v_line, adjust_leading_0(to_string(val), format));
write(v_line, string'(""""));
write(v_line, string'(")"));
else
write(v_line, adjust_leading_0(to_hstring(val), format));
if prefix = INCL_RADIX then
write(v_line, string'(""""));
end if;
end if;
end if;
if v_use_end_char then
write(v_line, string'(""""));
end if;
v_width := v_line'length;
v_result(1 to v_width) := v_line.all;
deallocate(v_line);
return v_result(1 to v_width);
end;
function to_string(
val : unsigned;
radix : t_radix;
format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string is
begin
return to_string(std_logic_vector(val), radix, format, prefix);
end;
function to_string(
val : signed;
radix : t_radix;
format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string is
variable v_line : line;
variable v_result : string(1 to 20 + 2 * val'length); --
variable v_width : natural;
variable v_use_end_char : boolean := false;
begin
-- Support negative numbers by _not_ using the slv overload when converting to decimal
if radix = DEC then
if val'length = 0 then
-- Value length is zero,
-- return empty string.
return "";
end if;
if (val'length > 32) then
write(v_line, to_string(std_logic_vector(val), HEX, format, prefix) & " (too wide to be converted to integer)" );
else
if prefix = INCL_RADIX then
write(v_line, string'("d"""));
v_use_end_char := true;
end if;
write(v_line, adjust_leading_0(to_string(to_integer(signed(val))), format));
end if;
if v_use_end_char then
write(v_line, string'(""""));
end if;
v_width := v_line'length;
v_result(1 to v_width) := v_line.all;
deallocate(v_line);
return v_result(1 to v_width);
else -- No decimal convertion: May be treated as slv, so use the slv overload
return to_string(std_logic_vector(val), radix, format, prefix);
end if;
end;
function to_string(
val : t_slv_array;
radix : t_radix := HEX_BIN_IF_INVALID;
format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string is
-- helper function to prevent null arrays
function get_string_len(val : t_slv_array) return integer is
variable v_parantheses : integer := 2; -- parentheses
variable v_commas : integer := 0; -- commas
variable v_radix_prefix : integer := 0; -- Radix prefixes
variable v_max_array_element_len : integer := 0; -- Maximum length of the array elements
variable v_max_ext_msg_len : integer := 0; -- Extra length of element in case of potential message "too wide to convert to integer"
begin
if val'length > 0 then
v_commas := 2 * (val'length - 1);
v_radix_prefix := 3 * val'length;
v_max_ext_msg_len := 14 * val'length;
if val'low >= 0 then
v_max_array_element_len := val(val'low)'length * val'length;
end if;
end if;
return (v_parantheses + v_commas + v_radix_prefix + v_max_array_element_len + v_max_ext_msg_len);
end function;
variable v_line : line;
variable v_result : string(1 to get_string_len(val));
variable v_width : natural;
begin
if val'length = 0 then
return "";
else
-- Comma-separate all array members and return
write(v_line, string'("("));
for idx in val'range loop
write(v_line, to_string(val(idx), radix, format, prefix));
if (idx < val'right) and (val'ascending) then
write(v_line, string'(", "));
elsif (idx > val'right) and not(val'ascending) then
write(v_line, string'(", "));
end if;
end loop;
write(v_line, string'(")"));
v_width := v_line'length;
v_result(1 to v_width) := v_line.all;
deallocate(v_line);
return v_result(1 to v_width);
end if;
end function;
function to_string(
val : t_signed_array;
radix : t_radix := HEX_BIN_IF_INVALID;
format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string is
-- helper function to prevent null arrays
function get_string_len(val : t_signed_array) return integer is
variable v_parantheses : integer := 2; -- parentheses
variable v_commas : integer := 0; -- commas
variable v_radix_prefix : integer := 0; -- Radix prefixes
variable v_max_array_element_len : integer := 0; -- Maximum length of the array elements
variable v_max_ext_msg_len : integer := 0; -- Extra length of element in case of potential message "too wide to convert to integer"
begin
if val'length > 0 then
v_commas := 2 * (val'length - 1);
v_radix_prefix := 3 * val'length;
v_max_ext_msg_len := 14 * val'length;
if val'low >= 0 then
v_max_array_element_len := val(val'low)'length * val'length;
end if;
end if;
return (v_parantheses + v_commas + v_radix_prefix + v_max_array_element_len + v_max_ext_msg_len);
end function;
variable v_line : line;
variable v_result : string(1 to get_string_len(val));
variable v_width : natural;
begin
if val'length = 0 then
return "";
else
-- Comma-separate all array members and return
write(v_line, string'("("));
for idx in val'range loop
write(v_line, to_string(val(idx), radix, format, prefix));
if (idx < val'right) and (val'ascending) then
write(v_line, string'(", "));
elsif (idx > val'right) and not(val'ascending) then
write(v_line, string'(", "));
end if;
end loop;
write(v_line, string'(")"));
v_width := v_line'length;
v_result(1 to v_width) := v_line.all;
deallocate(v_line);
return v_result(1 to v_width);
end if;
end function;
function to_string(
val : t_unsigned_array;
radix : t_radix := HEX_BIN_IF_INVALID;
format : t_format_zeros := KEEP_LEADING_0; -- | SKIP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string is
-- helper function to prevent null arrays
function get_string_len(val : t_unsigned_array) return integer is
variable v_parantheses : integer := 2; -- parentheses
variable v_commas : integer := 0; -- commas
variable v_radix_prefix : integer := 0; -- Radix prefixes
variable v_max_array_element_len : integer := 0; -- Maximum length of the array elements
variable v_max_ext_msg_len : integer := 0; -- Extra length of element in case of potential message "too wide to convert to integer"
begin
if val'length > 0 then
v_commas := 2 * (val'length - 1);
v_radix_prefix := 3 * val'length;
v_max_ext_msg_len := 14 * val'length;
if val'low >= 0 then
v_max_array_element_len := val(val'low)'length * val'length;
end if;
end if;
return (v_parantheses + v_commas + v_radix_prefix + v_max_array_element_len + v_max_ext_msg_len);
end function;
variable v_line : line;
variable v_result : string(1 to get_string_len(val));
variable v_width : natural;
begin
if val'length = 0 then
return "";
else
-- Comma-separate all array members and return
write(v_line, string'("("));
for idx in val'range loop
write(v_line, to_string(val(idx), radix, format, prefix));
if (idx < val'right) and (val'ascending) then
write(v_line, string'(", "));
elsif (idx > val'right) and not(val'ascending) then
write(v_line, string'(", "));
end if;
end loop;
write(v_line, string'(")"));
v_width := v_line'length;
v_result(1 to v_width) := v_line.all;
deallocate(v_line);
return v_result(1 to v_width);
end if;
end function;
impure function to_string(
val : integer_vector;
radix : t_radix := DEC;
format : t_format_zeros := SKIP_LEADING_0; -- | KEEP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string is
variable v_line : line;
variable v_result : string(1 to 2 + -- parentheses
2*(val'length - 1) + -- commas
32*val'length);
variable v_width : natural;
begin
if val'length = 0 then
return "";
else
-- Comma-separate all array members and return
write(v_line, string'("("));
for idx in val'range loop
write(v_line, to_string(val(idx), radix, prefix, format));
if (idx < val'right) and (val'ascending) then
write(v_line, string'(", "));
elsif (idx > val'right) and not(val'ascending) then
write(v_line, string'(", "));
end if;
end loop;
write(v_line, string'(")"));
v_width := v_line'length;
v_result(1 to v_width) := v_line.all;
deallocate(v_line);
return v_result(1 to v_width);
end if;
end function;
impure function to_string(
val : t_natural_vector;
radix : t_radix := DEC;
format : t_format_zeros := SKIP_LEADING_0; -- | KEEP_LEADING_0
prefix : t_radix_prefix := EXCL_RADIX -- Insert radix prefix in string?
) return string is
begin
return to_string(integer_vector(val), radix, format, prefix);
end function;
function to_string(
val : real_vector
) return string is
variable v_line : line;
variable v_result : string(1 to 2 + -- parentheses
2*(val'length - 1) + -- commas
32*val'length);
variable v_width : natural;
begin
if val'length = 0 then
return "";
else
-- Comma-separate all array members and return
write(v_line, string'("("));
for idx in val'range loop
write(v_line, to_string(val(idx)));
if (idx < val'right) and (val'ascending) then
write(v_line, string'(", "));
elsif (idx > val'right) and not(val'ascending) then
write(v_line, string'(", "));
end if;
end loop;
write(v_line, string'(")"));
v_width := v_line'length;
v_result(1 to v_width) := v_line.all;
deallocate(v_line);
return v_result(1 to v_width);
end if;
end function;
function to_string(
val : time_vector
) return string is
variable v_line : line;
variable v_result : string(1 to 2 + -- parentheses
2*(val'length - 1) + -- commas
32*val'length);
variable v_width : natural;
begin
if val'length = 0 then
return "";
else
-- Comma-separate all array members and return
write(v_line, string'("("));
for idx in val'range loop
write(v_line, to_string(val(idx)));
if (idx < val'right) and (val'ascending) then
write(v_line, string'(", "));
elsif (idx > val'right) and not(val'ascending) then
write(v_line, string'(", "));
end if;
end loop;
write(v_line, string'(")"));
v_width := v_line'length;
v_result(1 to v_width) := v_line.all;
deallocate(v_line);
return v_result(1 to v_width);
end if;
end function;
--========================================================
-- Handle types defined at lower levels
--========================================================
function to_string(
val : t_alert_level;
width : natural;
justified : side := right
) return string is
constant inner_string : string := t_alert_level'image(val);
begin
return to_upper(justify(inner_string, justified, width));
end function;
function to_string(
val : t_msg_id;
width : natural;
justified : side := right
) return string is
constant inner_string : string := t_msg_id'image(val);
begin
return to_upper(justify(inner_string, justified, width));
end function;
function to_string(
val : t_attention;
width : natural;
justified : side := right
) return string is
begin
return to_upper(justify(t_attention'image(val), justified, width));
end;
function to_string(
val : t_check_type;
width : natural;
justified : side := right
) return string is
constant inner_string : string := t_check_type'image(val);
begin
return to_upper(justify(inner_string, justified, width));
end function;
procedure to_string(
val : t_alert_attention_counters;
order : t_order := FINAL
) is
variable v_line : line;
variable v_line_copy : line;
variable v_more_than_expected_alerts : boolean := false;
variable v_less_than_expected_alerts : boolean := false;
variable v_more_than_expected_minor_alerts : boolean := false;
variable v_less_than_expected_minor_alerts : boolean := false;
constant prefix : string := C_LOG_PREFIX & " ";
-- NOTE, TB_NOTE, WARNING, TB_WARNING, MANUAL_CHECK
begin
if order = INTERMEDIATE then
write(v_line,
LF &
fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
"*** INTERMEDIATE SUMMARY OF ALL ALERTS ***" & LF &
fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
" REGARDED EXPECTED IGNORED Comment?" & LF);
else -- order=FINAL
write(v_line,
LF &
fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
"*** FINAL SUMMARY OF ALL ALERTS ***" & LF &
fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
" REGARDED EXPECTED IGNORED Comment?" & LF);
end if;
for i in NOTE to t_alert_level'right loop
write(v_line, " " & to_upper(to_string(i, 13, LEFT)) & ": "); -- Severity
for j in t_attention'left to t_attention'right loop
write(v_line, to_string(integer'(val(i)(j)), 6, RIGHT, KEEP_LEADING_SPACE) & " ");
end loop;
if (val(i)(REGARD) = val(i)(EXPECT)) then
write(v_line, " ok" & LF);
else
write(v_line, " *** " & to_string(i,0) & " ***" & LF);
if (i > MANUAL_CHECK) then
if (val(i)(REGARD) < val(i)(EXPECT)) then
v_less_than_expected_alerts := true;
else
v_more_than_expected_alerts := true;
end if;
else
if (val(i)(REGARD) < val(i)(EXPECT)) then
v_less_than_expected_minor_alerts := true;
else
v_more_than_expected_minor_alerts := true;
end if;
end if;
end if;
end loop;
write(v_line, fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF);
-- Print a conclusion when called from the FINAL part of the test sequencer
-- but not when called from in the middle of the test sequence (order=INTERMEDIATE)
if order = FINAL then
if v_more_than_expected_alerts then
write(v_line, ">> Simulation FAILED, with unexpected serious alert(s)" & LF);
elsif v_less_than_expected_alerts then
write(v_line, ">> Simulation FAILED: Mismatch between counted and expected serious alerts" & LF);
elsif v_more_than_expected_minor_alerts or v_less_than_expected_minor_alerts then
write(v_line, ">> Simulation SUCCESS: No mismatch between counted and expected serious alerts, but mismatch in minor alerts" & LF);
else
write(v_line, ">> Simulation SUCCESS: No mismatch between counted and expected serious alerts" & LF);
end if;
write(v_line, fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF & LF);
end if;
wrap_lines(v_line, 1, 1, C_LOG_LINE_WIDTH-prefix'length);
prefix_lines(v_line, prefix);
-- Write the info string to the target file
write (v_line_copy, v_line.all); -- copy line
writeline(OUTPUT, v_line);
writeline(LOG_FILE, v_line_copy);
deallocate(v_line);
deallocate(v_line_copy);
end;
procedure to_string(
val : t_check_counters_array;
order : t_order := FINAL
) is
variable v_line : line;
variable v_line_copy : line;
variable v_more_than_expected_alerts : boolean := false;
variable v_less_than_expected_alerts : boolean := false;
constant prefix : string := C_LOG_PREFIX & " ";
begin
if order = INTERMEDIATE then
write(v_line,
LF &
fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
"*** INTERMEDIATE SUMMARY OF ALL CHECK COUNTERS ***" & LF &
fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF);
else -- order=FINAL
write(v_line,
LF &
fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
"*** FINAL SUMMARY OF ALL CHECK COUNTERS ***" & LF &
fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF);
end if;
for i in CHECK_VALUE to t_check_type'right loop
write(v_line, " " & to_upper(to_string(i, 22, LEFT)) & ": ");
write(v_line, to_string(integer'(val(i)), 10, RIGHT, KEEP_LEADING_SPACE) & " ");
write(v_line, "" & LF);
end loop;
write(v_line, fill_string('=', (C_LOG_LINE_WIDTH - prefix'length)) & LF & LF);
wrap_lines(v_line, 1, 1, C_LOG_LINE_WIDTH-prefix'length);
prefix_lines(v_line, prefix);
-- Write the info string to the target file
write (v_line_copy, v_line.all); -- copy line
writeline(OUTPUT, v_line);
writeline(LOG_FILE, v_line_copy);
deallocate(v_line);
deallocate(v_line_copy);
end;
-- Convert from ASCII to character
-- Inputs:
-- ascii_pos (integer) : ASCII number input
-- ascii_allow (t_ascii_allow) : Decide what to do with invisible control characters:
-- - If ascii_allow = ALLOW_ALL (default) : return the character for any ascii_pos
-- - If ascii_allow = ALLOW_PRINTABLE_ONLY : return the character only if it is printable
function ascii_to_char(
ascii_pos : integer range 0 to 255; -- Supporting Extended ASCII
ascii_allow : t_ascii_allow := ALLOW_ALL
) return character is
variable v_printable : boolean := true;
begin
if ascii_pos < 32 or -- NUL, SOH, STX etc
(ascii_pos >= 128 and ascii_pos < 160) then -- C128 to C159
v_printable := false;
end if;
if ascii_allow = ALLOW_ALL or
(ascii_allow = ALLOW_PRINTABLE_ONLY and v_printable) then
return character'val(ascii_pos);
else
return ' '; -- Must return something when invisible control signals
end if;
end;
-- Convert from character to ASCII integer
function char_to_ascii(
char : character
) return integer is
begin
return character'pos(char);
end;
-- return string with only valid ascii characters
function to_string(
val : string
) return string is
variable v_new_string : string(1 to val'length);
variable v_char_idx : natural := 0;
variable v_ascii_pos : natural;
begin
for i in val'range loop
v_ascii_pos := character'pos(val(i));
if (v_ascii_pos < 32 and v_ascii_pos /= 10) or -- NUL, SOH, STX etc, LF(10) is not removed.
(v_ascii_pos >= 128 and v_ascii_pos < 160) then -- C128 to C159
-- illegal char
null;
else
-- legal char
v_char_idx := v_char_idx + 1;
v_new_string(v_char_idx) := val(i);
end if;
end loop;
if v_char_idx = 0 then
return "";
else
return v_new_string(1 to v_char_idx);
end if;
end;
function add_msg_delimiter(
msg : string
) return string is
begin
if msg'length /= 0 then
if valid_length(msg) /= 1 then
if msg(1) = C_MSG_DELIMITER then
return msg;
else
return C_MSG_DELIMITER & msg & C_MSG_DELIMITER;
end if;
end if;
end if;
return "";
end;
-- Returns a string with a timestamp and a text. Used in report headers
function timestamp_header(
value : time;
txt : string) return string is
variable v_line : line;
variable v_delimiter_pos : natural;
variable v_timestamp_width : natural;
variable v_result : string(1 to 50);
variable v_return : string(1 to txt'length) := txt;
begin
-- get a time stamp
write(v_line, value, LEFT, 0, C_LOG_TIME_BASE);
v_timestamp_width := v_line'length;
v_result(1 to v_timestamp_width) := v_line.all;
deallocate(v_line);
v_delimiter_pos := pos_of_leftmost('.', v_result(1 to v_timestamp_width), 0);
-- truncate decimals and add units
if v_delimiter_pos > 0 then
if C_LOG_TIME_BASE = ns then
v_result(v_delimiter_pos+2 to v_delimiter_pos+4) := " ns";
else
v_result(v_delimiter_pos+2 to v_delimiter_pos+4) := " ps";
end if;
v_timestamp_width := v_delimiter_pos + 4;
end if;
-- add a space after the timestamp
v_timestamp_width := v_timestamp_width + 1;
v_result(v_timestamp_width to v_timestamp_width) := " ";
-- add time string to return string
v_return := v_result(1 to v_timestamp_width) & txt(1 to txt'length-v_timestamp_width);
return v_return(1 to txt'length);
end function timestamp_header;
end package body string_methods_pkg;
|
-------------------------------------------------------------------------------
--
-- $Id: tb_pack-p.vhd,v 1.3 2006-05-27 19:09:29 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t400_pack.pc_t;
package tb_pack is
component tb_elems
generic (
period_g : time := 4.75 us;
d_width_g : integer := 4;
g_width_g : integer := 4
);
port (
io_l_i : in std_logic_vector(7 downto 0);
io_d_i : in std_logic_vector(d_width_g-1 downto 0);
io_g_i : in std_logic_vector(g_width_g-1 downto 0);
io_in_o : out std_logic_vector(g_width_g-1 downto 0);
so_i : in std_logic;
si_o : out std_logic;
sk_i : in std_logic;
ck_o : out std_logic
);
end component;
signal tb_pc_s : pc_t;
signal tb_sa_s : pc_t;
end tb_pack;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.2 2006/05/23 01:17:25 arniml
-- drive IN port
--
-- Revision 1.1 2006/05/15 21:55:27 arniml
-- initial check-in
--
-------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:29:49 03/30/2016
-- Design Name:
-- Module Name: DATA_CTL - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DATA_CTL is
Port ( CLK : in STD_LOGIC;
EN : in STD_LOGIC;
OP : in STD_LOGIC_VECTOR (3 downto 0);
RD_EN : out STD_LOGIC;
WR_EN : out STD_LOGIC);
end DATA_CTL;
architecture Behavioral of DATA_CTL is
signal RD, WR : STD_LOGIC := '0';
begin
RD_EN <= RD;
WR_EN <= WR;
process(CLK)
begin
if(rising_edge(CLK)) then
case OP is
when "1001" => RD <= '1';
WR <= '0';
when "1010" => RD <= '0';
WR <= '1';
when OTHERS => RD <= '0';
WR <= '0';
end case;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:29:49 03/30/2016
-- Design Name:
-- Module Name: DATA_CTL - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DATA_CTL is
Port ( CLK : in STD_LOGIC;
EN : in STD_LOGIC;
OP : in STD_LOGIC_VECTOR (3 downto 0);
RD_EN : out STD_LOGIC;
WR_EN : out STD_LOGIC);
end DATA_CTL;
architecture Behavioral of DATA_CTL is
signal RD, WR : STD_LOGIC := '0';
begin
RD_EN <= RD;
WR_EN <= WR;
process(CLK)
begin
if(rising_edge(CLK)) then
case OP is
when "1001" => RD <= '1';
WR <= '0';
when "1010" => RD <= '0';
WR <= '1';
when OTHERS => RD <= '0';
WR <= '0';
end case;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:29:49 03/30/2016
-- Design Name:
-- Module Name: DATA_CTL - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DATA_CTL is
Port ( CLK : in STD_LOGIC;
EN : in STD_LOGIC;
OP : in STD_LOGIC_VECTOR (3 downto 0);
RD_EN : out STD_LOGIC;
WR_EN : out STD_LOGIC);
end DATA_CTL;
architecture Behavioral of DATA_CTL is
signal RD, WR : STD_LOGIC := '0';
begin
RD_EN <= RD;
WR_EN <= WR;
process(CLK)
begin
if(rising_edge(CLK)) then
case OP is
when "1001" => RD <= '1';
WR <= '0';
when "1010" => RD <= '0';
WR <= '1';
when OTHERS => RD <= '0';
WR <= '0';
end case;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:29:49 03/30/2016
-- Design Name:
-- Module Name: DATA_CTL - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DATA_CTL is
Port ( CLK : in STD_LOGIC;
EN : in STD_LOGIC;
OP : in STD_LOGIC_VECTOR (3 downto 0);
RD_EN : out STD_LOGIC;
WR_EN : out STD_LOGIC);
end DATA_CTL;
architecture Behavioral of DATA_CTL is
signal RD, WR : STD_LOGIC := '0';
begin
RD_EN <= RD;
WR_EN <= WR;
process(CLK)
begin
if(rising_edge(CLK)) then
case OP is
when "1001" => RD <= '1';
WR <= '0';
when "1010" => RD <= '0';
WR <= '1';
when OTHERS => RD <= '0';
WR <= '0';
end case;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:29:49 03/30/2016
-- Design Name:
-- Module Name: DATA_CTL - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DATA_CTL is
Port ( CLK : in STD_LOGIC;
EN : in STD_LOGIC;
OP : in STD_LOGIC_VECTOR (3 downto 0);
RD_EN : out STD_LOGIC;
WR_EN : out STD_LOGIC);
end DATA_CTL;
architecture Behavioral of DATA_CTL is
signal RD, WR : STD_LOGIC := '0';
begin
RD_EN <= RD;
WR_EN <= WR;
process(CLK)
begin
if(rising_edge(CLK)) then
case OP is
when "1001" => RD <= '1';
WR <= '0';
when "1010" => RD <= '0';
WR <= '1';
when OTHERS => RD <= '0';
WR <= '0';
end case;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:29:49 03/30/2016
-- Design Name:
-- Module Name: DATA_CTL - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DATA_CTL is
Port ( CLK : in STD_LOGIC;
EN : in STD_LOGIC;
OP : in STD_LOGIC_VECTOR (3 downto 0);
RD_EN : out STD_LOGIC;
WR_EN : out STD_LOGIC);
end DATA_CTL;
architecture Behavioral of DATA_CTL is
signal RD, WR : STD_LOGIC := '0';
begin
RD_EN <= RD;
WR_EN <= WR;
process(CLK)
begin
if(rising_edge(CLK)) then
case OP is
when "1001" => RD <= '1';
WR <= '0';
when "1010" => RD <= '0';
WR <= '1';
when OTHERS => RD <= '0';
WR <= '0';
end case;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:29:49 03/30/2016
-- Design Name:
-- Module Name: DATA_CTL - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DATA_CTL is
Port ( CLK : in STD_LOGIC;
EN : in STD_LOGIC;
OP : in STD_LOGIC_VECTOR (3 downto 0);
RD_EN : out STD_LOGIC;
WR_EN : out STD_LOGIC);
end DATA_CTL;
architecture Behavioral of DATA_CTL is
signal RD, WR : STD_LOGIC := '0';
begin
RD_EN <= RD;
WR_EN <= WR;
process(CLK)
begin
if(rising_edge(CLK)) then
case OP is
when "1001" => RD <= '1';
WR <= '0';
when "1010" => RD <= '0';
WR <= '1';
when OTHERS => RD <= '0';
WR <= '0';
end case;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:29:49 03/30/2016
-- Design Name:
-- Module Name: DATA_CTL - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DATA_CTL is
Port ( CLK : in STD_LOGIC;
EN : in STD_LOGIC;
OP : in STD_LOGIC_VECTOR (3 downto 0);
RD_EN : out STD_LOGIC;
WR_EN : out STD_LOGIC);
end DATA_CTL;
architecture Behavioral of DATA_CTL is
signal RD, WR : STD_LOGIC := '0';
begin
RD_EN <= RD;
WR_EN <= WR;
process(CLK)
begin
if(rising_edge(CLK)) then
case OP is
when "1001" => RD <= '1';
WR <= '0';
when "1010" => RD <= '0';
WR <= '1';
when OTHERS => RD <= '0';
WR <= '0';
end case;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:29:49 03/30/2016
-- Design Name:
-- Module Name: DATA_CTL - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DATA_CTL is
Port ( CLK : in STD_LOGIC;
EN : in STD_LOGIC;
OP : in STD_LOGIC_VECTOR (3 downto 0);
RD_EN : out STD_LOGIC;
WR_EN : out STD_LOGIC);
end DATA_CTL;
architecture Behavioral of DATA_CTL is
signal RD, WR : STD_LOGIC := '0';
begin
RD_EN <= RD;
WR_EN <= WR;
process(CLK)
begin
if(rising_edge(CLK)) then
case OP is
when "1001" => RD <= '1';
WR <= '0';
when "1010" => RD <= '0';
WR <= '1';
when OTHERS => RD <= '0';
WR <= '0';
end case;
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- RapidIO IP Library Core
--
-- This file is part of the RapidIO IP library project
-- http://www.opencores.org/cores/rio/
--
-- To Do:
-- -
--
-- Author(s):
-- - A. Demirezen, [email protected]
--
-------------------------------------------------------------------------------
--
-- Copyright (C) 2013 Authors and OPENCORES.ORG
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--
------------------------------------------------------------------------------
------------------------------------------------------------------------------
--
-- File name: ccs_timer.vhd
-- Rev: 0.0
-- Description: This entity watches the CCS (clock compensation sequence)
-- insertion according to RIO Sepec. Part-6, subchapter 4.7.1
--
------------------------------------------------------------------------------
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use work.rio_common.all;
entity ccs_timer is
generic (
TCQ : time := 100 ps
);
port (
rst_n : in std_logic;
UCLK : in std_logic;
send_ccs : out std_logic;
ccs_timer_rst : in std_logic
);
end ccs_timer;
architecture RTL of ccs_timer is
--------------------------------------------------------------------------------------
signal ccs_counter : std_logic_vector(11 downto 0) := (others => '0');
constant CCS_INTERVAL : std_logic_vector(11 downto 0) := x"7FF"; -- = 4096 chars
--------------------------------------------------------------------------------------
begin
-- CCS counter process
process(rst_n, UCLK)
begin
if rst_n = '0' then
ccs_counter <= CCS_INTERVAL;
send_ccs <= '0';
elsif rising_edge(UCLK) then
if ccs_timer_rst = '0' then
if ccs_counter = CCS_INTERVAL then
send_ccs <= '1';
else
send_ccs <= '0';
ccs_counter <= ccs_counter + '1';
end if;
else
send_ccs <= '0';
ccs_counter <= (others => '0');
end if;
end if;
end process;
end RTL;
---------------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- RapidIO IP Library Core
--
-- This file is part of the RapidIO IP library project
-- http://www.opencores.org/cores/rio/
--
-- To Do:
-- -
--
-- Author(s):
-- - A. Demirezen, [email protected]
--
-------------------------------------------------------------------------------
--
-- Copyright (C) 2013 Authors and OPENCORES.ORG
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--
------------------------------------------------------------------------------
------------------------------------------------------------------------------
--
-- File name: idle_generator.vhd
-- Rev: 0.0
-- Description: This entity generates IDLE1 sequence for SRIO PHY
-- RIO Sepec. Part-6, subchapter 4.7.2
--
------------------------------------------------------------------------------
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use work.rio_common.all;
entity idle_generator is
generic (
lfsr_init : std_logic_vector(7 downto 0) := x"01";
TCQ : time := 100 ps
);
port (
UCLK : in std_logic;
rst_n : in std_logic;
send_idle : in std_logic;
send_K : out std_logic;
send_A : out std_logic;
send_R : out std_logic
);
end idle_generator;
architecture RTL of idle_generator is
-------------------------------------------------------------------------------------------------------------------------------------------
signal q_pseudo_random_number : std_logic_vector(7 downto 0) := (others => '0');
signal pseudo_random_bit : std_logic := '0';
signal down_counter_load_value : std_logic_vector(4 downto 0) := (others => '0');
signal down_counter : std_logic_vector(4 downto 0) := (others => '0');
signal Acntr_eq_zero : std_logic := '0';
signal send_idle_q : std_logic := '0';
--
COMPONENT pseudo_random_number_generator
GENERIC (
lfsr_init : std_logic_vector(7 downto 0)
);
PORT(
clk : IN std_logic;
rst_n : IN std_logic;
q : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
-------------------------------------------------------------------------------------------------------------------------------------------
begin
inst_prng: pseudo_random_number_generator GENERIC MAP(
lfsr_init => lfsr_init --x"01"
)
PORT MAP(
clk => UCLK,
rst_n => rst_n,
q => q_pseudo_random_number
);
pseudo_random_bit <= q_pseudo_random_number(0);
down_counter_load_value <= '1' & q_pseudo_random_number(6) & q_pseudo_random_number(4) & q_pseudo_random_number(3) & q_pseudo_random_number(1);
-- down counter process
process(rst_n, UCLK)
begin
if rst_n = '0' then
down_counter <= (others => '0');
elsif rising_edge(UCLK) then
if Acntr_eq_zero = '1' then
down_counter <= down_counter_load_value;
else
down_counter <= down_counter - '1';
end if;
end if;
end process;
Acntr_eq_zero <= '1' when down_counter = "00000" else '0';
-- send_idle delay process
process(rst_n, UCLK)
begin
if rst_n = '0' then
send_idle_q <= '0';
elsif rising_edge(UCLK) then
send_idle_q <= send_idle;
end if;
end process;
send_K <= send_idle and (not(send_idle_q) or (send_idle_q and not(Acntr_eq_zero) and pseudo_random_bit));
send_A <= send_idle and send_idle_q and Acntr_eq_zero;
send_R <= send_idle and send_idle_q and not(Acntr_eq_zero) and not(pseudo_random_bit);
end RTL;
-------------------------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- RapidIO IP Library Core
--
-- This file is part of the RapidIO IP library project
-- http://www.opencores.org/cores/rio/
--
-- To Do:
-- -
--
-- Author(s):
-- - A. Demirezen, [email protected]
--
-------------------------------------------------------------------------------
--
-- Copyright (C) 2013 Authors and OPENCORES.ORG
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--
------------------------------------------------------------------------------
------------------------------------------------------------------------------
--
-- File name: idle_generator_dual.vhd
-- Rev: 0.0
-- Description: This entity generates IDLE1 sequence for SRIO PHY
-- RIO Sepec. Part-6, subchapter 4.7.2
--
------------------------------------------------------------------------------
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use work.rio_common.all;
entity idle_generator_dual is
generic (
TCQ : time := 100 ps
);
port (
UCLK : in std_logic;
rst_n : in std_logic;
send_idle : in std_logic_vector(1 downto 0);
send_K : out std_logic_vector(1 downto 0);
send_A : out std_logic_vector(1 downto 0);
send_R : out std_logic_vector(1 downto 0)
);
end idle_generator_dual;
architecture RTL of idle_generator_dual is
-------------------------------------------------------------------------------------------------------------------------------------------
COMPONENT idle_generator
generic (
lfsr_init : std_logic_vector(7 downto 0);
TCQ : time
);
PORT(
UCLK : IN std_logic;
rst_n : IN std_logic;
send_idle : IN std_logic;
send_K : OUT std_logic;
send_A : OUT std_logic;
send_R : OUT std_logic
);
END COMPONENT;
-------------------------------------------------------------------------------------------------------------------------------------------
begin
Inst_idle_generator_0: idle_generator GENERIC MAP(
TCQ => 100 ps,
lfsr_init => x"0F"
)
PORT MAP(
UCLK => UCLK,
rst_n => rst_n,
send_idle => send_idle(0),
send_K => send_K(0),
send_A => send_A(0),
send_R => send_R(0)
);
Inst_idle_generator_1: idle_generator GENERIC MAP(
TCQ => 100 ps,
lfsr_init => x"F0"
)
PORT MAP(
UCLK => UCLK,
rst_n => rst_n,
send_idle => send_idle(1),
send_K => send_K(1),
send_A => send_A(1),
send_R => send_R(1)
);
end RTL;
-------------------------------------------------------------------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- RapidIO IP Library Core
--
-- This file is part of the RapidIO IP library project
-- http://www.opencores.org/cores/rio/
--
-- To Do:
-- -
--
-- Author(s):
-- - A. Demirezen, [email protected]
--
-------------------------------------------------------------------------------
--
-- Copyright (C) 2013 Authors and OPENCORES.ORG
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--
------------------------------------------------------------------------------
------------------------------------------------------------------------------
--
-- File name: pcs_rx_controller.vhd
-- Rev: 0.0
-- Description: This entity controls the RX stream
--
--
------------------------------------------------------------------------------
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use work.rio_common.all;
entity pcs_rx_controller is
generic (
TCQ : time := 100 ps
);
port (
rst_n : in std_logic;
rio_clk : in std_logic; -- ~150 MHz
UCLK_x2 : in std_logic; -- 312,5 MHz
UCLK : in std_logic; -- 156,25 MHz
UCLK_x2_DV2 : in std_logic; -- 312,5 MHz @ x4 mode / 78,125 @ x1 (fallback mode)
UCLK_or_DV4 : in std_logic; -- 156,25 MHz @ x4 mode / 39,0625 @ x1 (fallback mode)
-- UCLK_DV4 : in std_logic; -- 39,0625
--
-- Interface to the RioSerial
inboundRead_i : in std_logic;
inboundEmpty_o : out std_logic;
inboundSymbol_o : out std_logic_vector(33 downto 0);
--
-- Interface to the GTX transceivers
RXDATA_i : in std_logic_vector(63 downto 0); -- N = 4
RXCHARISK_i : in std_logic_vector(7 downto 0);
RXCHARISvalid_i : in std_logic_vector(7 downto 0);
--
-- Interface to the port init
port_initalized_i : in std_logic;
mode_sel_i : in std_logic;
mode_0_lane_sel_i : in std_logic
);
end pcs_rx_controller;
architecture RTL of pcs_rx_controller is
-------------------------------------------------------------------------------
COMPONENT pcs_rx_boudary_32b_out_64b_in
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(67 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(33 DOWNTO 0);
full : OUT STD_LOGIC;
almost_full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
END COMPONENT;
-------------------------------------------------------------------------------
signal rst : std_logic:= '0';
signal RXDATA_swap : std_logic_vector(63 downto 0) := (others => '0');
signal RXCHARISK_swap : std_logic_vector(7 downto 0) := (others => '0');
signal RXCHARISvalid_swap : std_logic_vector(7 downto 0) := (others => '0');
signal RXDATA_u : std_logic_vector(31 downto 0) := (others => '0');
signal RXCHARISK_u : std_logic_vector(3 downto 0) := (others => '0');
signal RXDATA_l : std_logic_vector(31 downto 0) := (others => '0');
signal RXCHARISK_l : std_logic_vector(3 downto 0) := (others => '0');
signal RXCHARISvalid_u : std_logic_vector(3 downto 0) := (others => '0');
signal RXCHARISvalid_l : std_logic_vector(3 downto 0) := (others => '0');
signal inboundValid : std_logic:= '0';
signal rx_fifo_wr_en : std_logic:= '0';
signal rx_fifo_wr_en_q : std_logic:= '0';
signal rx_fifo_full : std_logic:= '0';
signal rx_fifo_almost_full : std_logic:= '0';
signal rx_fifo_almost_empty : std_logic:= '0';
signal rx_fifo_data_in : std_logic_vector(67 downto 0) := (others => '0');
signal rx_fifo_data_in_q : std_logic_vector(67 downto 0) := (others => '0');
signal rx_fifo_data_swapped : std_logic_vector(67 downto 0) := (others => '0');
signal rx_fifo_full_p : std_logic:= '0';
signal port_initalized : std_logic:= '0';
signal mode_sel : std_logic:= '0';
signal mode_0_lane_sel : std_logic:= '0';
signal port_state : std_logic_vector(2 downto 0) := (others => '0');
signal upper_symbol_type : std_logic_vector(1 downto 0) := (others => '0');
signal lower_symbol_type : std_logic_vector(1 downto 0) := (others => '0');
signal upper_symbol_not_idle : std_logic:= '0';
signal lower_symbol_not_idle : std_logic:= '0';
signal upper_symbol_valid : std_logic:= '0';
signal lower_symbol_valid : std_logic:= '0';
signal upper_symbol_not_error : std_logic:= '0';
signal lower_symbol_not_error : std_logic:= '0';
-- signal RXDATA_sr : std_logic_vector(63 downto 0) := (others => '0');
-- signal RXCHARISK_sr : std_logic_vector(7 downto 0) := (others => '0');
-- signal RXCHARISvalid_sr : std_logic_vector(7 downto 0) := (others => '0');
signal RXDATA_sr_done : std_logic_vector(63 downto 0) := (others => '0');
signal RXCHARISK_sr_done : std_logic_vector(7 downto 0) := (others => '0');
signal RXCHARISvalid_sr_done : std_logic_vector(7 downto 0) := (others => '0');
signal RXDATA_sr : std_logic_vector(71 downto 0) := (others => '0');
signal RXCHARISK_sr : std_logic_vector(8 downto 0) := (others => '0');
signal RXCHARISvalid_sr : std_logic_vector(8 downto 0) := (others => '0');
signal RXDATA_R_lane : std_logic_vector(15 downto 0) := (others => '0');
signal RXCHARISK_R_lane : std_logic_vector(1 downto 0) := (others => '0');
signal RXCHARISvalid_R_lane : std_logic_vector(1 downto 0) := (others => '0');
signal valid_byte_cntr : std_logic_vector(2 downto 0) := (others => '0');
signal irregular_stream : std_logic:= '0';
signal done_cntr : std_logic_vector(1 downto 0) := (others => '0');
signal rx_done : std_logic:= '0';
signal u_l_switch : std_logic:= '0';
-- signal sr_symbol_not_idle : std_logic:= '0';
-- signal sr_symbol_not_idle_q : std_logic:= '0';
-- signal sr_symbol_not_error : std_logic:= '0';
-- signal sr_symbol_not_error_q : std_logic:= '0';
-- signal RXDATA_sr : std_logic_vector(31 downto 0) := (others => '0');
-- signal RXCHARISK_sr : std_logic_vector(3 downto 0) := (others => '0');
-- signal RXCHARISvalid_sr : std_logic_vector(3 downto 0) := (others => '0');
-- signal sr_symbol_type : std_logic_vector(1 downto 0) := (others => '0');
signal sr_u_symbol_not_idle : std_logic:= '0';
signal sr_u_symbol_not_idle_q : std_logic:= '0';
signal sr_u_symbol_not_error : std_logic:= '0';
signal sr_u_symbol_not_error_q : std_logic:= '0';
signal RXDATA_u_sr : std_logic_vector(31 downto 0) := (others => '0');
signal RXCHARISK_u_sr : std_logic_vector(3 downto 0) := (others => '0');
signal RXCHARISvalid_u_sr : std_logic_vector(3 downto 0) := (others => '0');
signal sr_u_symbol_type : std_logic_vector(1 downto 0) := (others => '0');
signal sr_l_symbol_not_idle : std_logic:= '0';
signal sr_l_symbol_not_idle_q : std_logic:= '0';
signal sr_l_symbol_not_error : std_logic:= '0';
signal sr_l_symbol_not_error_q : std_logic:= '0';
signal RXDATA_sr_l : std_logic_vector(31 downto 0) := (others => '0');
signal RXCHARISK_sr_l : std_logic_vector(3 downto 0) := (others => '0');
signal RXCHARISvalid_sr_l : std_logic_vector(3 downto 0) := (others => '0');
signal sr_l_symbol_type : std_logic_vector(1 downto 0) := (others => '0');
signal started_once : std_logic:= '0';
signal word_switch : std_logic:= '0';
signal shift_cntr : std_logic_vector(1 downto 0) := (others => '0');
----------------------------------------------------------------------------------
begin
rst <= not(rst_n);
rx_boundary_fifo : pcs_rx_boudary_32b_out_64b_in -- FWFT FIFO
PORT MAP (
rst => rst,
rd_clk => rio_clk,
rd_en => inboundRead_i,
dout => inboundSymbol_o,
valid => inboundValid,
empty => inboundEmpty_o,
almost_empty => rx_fifo_almost_empty,
wr_clk => UCLK_or_DV4,
wr_en => rx_fifo_wr_en_q, -- rx_fifo_wr_en, -- rx_fifo_wr_en_q, --
din => rx_fifo_data_in_q, -- rx_fifo_data_in, -- rx_fifo_data_in_q, --
full => rx_fifo_full, -- rx_fifo_full
almost_full => rx_fifo_almost_full -- rx_fifo_full
);
-- Pipelining RX write
process(UCLK_or_DV4)
begin
if rising_edge(UCLK_or_DV4) then
rx_fifo_wr_en_q <= rx_fifo_wr_en;
rx_fifo_data_in_q <= rx_fifo_data_in;
end if;
end process;
-- rx_fifo_data_swapped <= rx_fifo_data_in(33 downto 32)
-- & rx_fifo_data_in(7 downto 0) & rx_fifo_data_in(15 downto 8) & rx_fifo_data_in(23 downto 16) & rx_fifo_data_in(31 downto 24);
port_initalized <= port_initalized_i;
mode_sel <= mode_sel_i;
mode_0_lane_sel <= mode_0_lane_sel_i;
port_state <= port_initalized & mode_sel & mode_0_lane_sel;
-- RX management / FIFO write process
process(rst_n, UCLK) -- _x2
begin
if rst_n = '0' then
rx_fifo_wr_en <= '0';
word_switch <= '0';
started_once <= '0';
rx_fifo_data_in <= (others => '0');
-- RXDATA_sr <= (others => '0');
-- RXCHARISK_sr <= (others => '1');
-- RXCHARISvalid_sr <= (others => '0');
shift_cntr <= (others => '0');
elsif rising_edge(UCLK) then
-- Alternative If-Else Statement
if port_initalized = '0' then -- Port has not been initialized yet
rx_fifo_wr_en <= '0';
rx_fifo_data_in <= (others => '0');
else -- Port has been initialized
-- if mode_sel = '1' then -- x4 mode is active
if upper_symbol_valid = '1' and lower_symbol_valid = '1' then
rx_fifo_data_in <= upper_symbol_type & RXDATA_u & lower_symbol_type & RXDATA_l;
rx_fifo_wr_en <= not(rx_fifo_almost_full);
elsif upper_symbol_valid = '1' then
rx_fifo_data_in <= upper_symbol_type & RXDATA_u & SYMBOL_IDLE & x"00000000";
rx_fifo_wr_en <= not(rx_fifo_almost_full);
elsif lower_symbol_valid = '1' then
rx_fifo_data_in <= SYMBOL_IDLE & x"00000000" & lower_symbol_type & RXDATA_l;
rx_fifo_wr_en <= not(rx_fifo_almost_full);
else
rx_fifo_wr_en <= '0';
end if;
-- else -- x1 fallback mode is active
-- if upper_symbol_valid = '1' and lower_symbol_valid = '1' then
-- rx_fifo_data_in <= upper_symbol_type & RXDATA_u & lower_symbol_type & RXDATA_l;
-- rx_fifo_wr_en <= not(rx_fifo_full);
-- elsif upper_symbol_valid = '1' then
-- rx_fifo_data_in <= upper_symbol_type & RXDATA_u & SYMBOL_IDLE & RXDATA_l;
-- rx_fifo_wr_en <= not(rx_fifo_full);
-- elsif lower_symbol_valid = '1' then
-- rx_fifo_data_in <= SYMBOL_IDLE & RXDATA_u & lower_symbol_type & RXDATA_l;
-- rx_fifo_wr_en <= not(rx_fifo_full);
-- else
-- rx_fifo_wr_en <= '0';
-- end if;
-- end if;
end if;
end if;
end process;
-------------------------------------------------------------------------------------------------------------------------------------------------------
-- -- Pipelining RX stream
-- process(UCLK)
-- begin
-- if rising_edge(UCLK) then
-- RXDATA_swap <= RXDATA_i(15 downto 0) & RXDATA_i(31 downto 16) & RXDATA_i(47 downto 32) & RXDATA_i(63 downto 48);
-- RXCHARISK_swap <= RXCHARISK_i(1 downto 0) & RXCHARISK_i(3 downto 2) & RXCHARISK_i(5 downto 4) & RXCHARISK_i(7 downto 6);
-- RXCHARISvalid_swap <= RXCHARISvalid_i(1 downto 0) & RXCHARISvalid_i(3 downto 2) & RXCHARISvalid_i(5 downto 4) & RXCHARISvalid_i(7 downto 6);
-- end if;
-- end process;
-- Pipelining RX stream
process(UCLK)
begin
if rising_edge(UCLK) then
RXDATA_swap <= RXDATA_i(15 downto 0) & RXDATA_i(31 downto 16) & RXDATA_i(47 downto 32) & RXDATA_i(63 downto 48);
RXCHARISK_swap <= RXCHARISK_i(1 downto 0) & RXCHARISK_i(3 downto 2) & RXCHARISK_i(5 downto 4) & RXCHARISK_i(7 downto 6);
RXCHARISvalid_swap <= RXCHARISvalid_i(1 downto 0) & RXCHARISvalid_i(3 downto 2) & RXCHARISvalid_i(5 downto 4) & RXCHARISvalid_i(7 downto 6);
-- if mode_sel = '1' then -- x4 mode is active
-- else -- x1 fallback mode is active
--
-- RXDATA_swap <= RXDATA_sr_done ;
-- RXCHARISK_swap <= RXCHARISK_sr_done ;
-- RXCHARISvalid_swap <= RXCHARISvalid_sr_done ;
--
-- end if;
end if;
end process;
--- Lane 0 active Lane 2 active
RXDATA_R_lane <= RXDATA_i(15 downto 0) when mode_0_lane_sel = '0' else RXDATA_i(47 downto 32) ;
RXCHARISK_R_lane <= RXCHARISK_i(1 downto 0) when mode_0_lane_sel = '0' else RXCHARISK_i(5 downto 4) ;
RXCHARISvalid_R_lane <= RXCHARISvalid_i(1 downto 0) when mode_0_lane_sel = '0' else RXCHARISvalid_i(5 downto 4) ;
-- RXDATA shifting process for x1 mode
process(UCLK) -- _x2 rst_n,
begin
-- if rst_n = '0' then
--
-- RXDATA_sr <= (others => '0');
-- RXCHARISK_sr <= (others => '1');
-- RXCHARISvalid_sr <= (others => '0');
-- valid_byte_cntr <= (others => '0');
--
-- RXDATA_sr_done <= (others => '0');
-- RXCHARISK_sr_done <= (others => '1');
-- RXCHARISvalid_sr_done <= (others => '0');
--
-- done_cntr <= (others => '0');
-- rx_done <= '0';
--
-- els
if rising_edge(UCLK) then
if port_initalized = '0' then -- Port has not been initialized yet
RXDATA_sr <= (others => '0');
RXCHARISK_sr <= (others => '1');
RXCHARISvalid_sr <= (others => '0');
valid_byte_cntr <= (others => '0');
RXDATA_sr_done <= (others => '0');
RXCHARISK_sr_done <= (others => '1');
RXCHARISvalid_sr_done <= (others => '0');
done_cntr <= (others => '0');
rx_done <= '0';
else
done_cntr <= done_cntr + rx_done;
if RXCHARISvalid_R_lane(0) = '1' and (RXCHARISK_R_lane(0) = '0' or (RXCHARISK_R_lane(0) = '1' and (RXDATA_R_lane(7 downto 0) = SC or RXDATA_R_lane(7 downto 0) = PD))) then
if RXCHARISvalid_R_lane(1) = '1' and (RXCHARISK_R_lane(1) = '0' or (RXCHARISK_R_lane(1) = '1' and (RXDATA_R_lane(15 downto 8) = SC or RXDATA_R_lane(15 downto 8) = PD))) then
--- [VVVV] It may appear anytime
valid_byte_cntr <= valid_byte_cntr + "10";
RXDATA_sr <= RXDATA_sr(55 downto 0) & RXDATA_R_lane(15 downto 0);
RXCHARISK_sr <= RXCHARISK_sr(6 downto 0) & RXCHARISK_R_lane(1 downto 0);
RXCHARISvalid_sr <= RXCHARISvalid_sr(6 downto 0) & RXCHARISvalid_R_lane(1 downto 0);
if valid_byte_cntr = "110" then
irregular_stream <= '0';
rx_done <= '1';
done_cntr <= (others => '0');
RXDATA_sr_done <= RXDATA_sr(47 downto 0) & RXDATA_R_lane(15 downto 0);
RXCHARISK_sr_done <= RXCHARISK_sr(5 downto 0) & RXCHARISK_R_lane(1 downto 0);
RXCHARISvalid_sr_done <= RXCHARISvalid_sr(5 downto 0) & RXCHARISvalid_R_lane(1 downto 0);
elsif valid_byte_cntr = "111" then
irregular_stream <= '1';
rx_done <= '1';
done_cntr <= (others => '0');
RXDATA_sr_done <= RXDATA_sr(55 downto 0) & RXDATA_R_lane(15 downto 8);
RXCHARISK_sr_done <= RXCHARISK_sr(6 downto 0) & RXCHARISK_R_lane(1);
RXCHARISvalid_sr_done <= RXCHARISvalid_sr(6 downto 0) & RXCHARISvalid_R_lane(1);
elsif done_cntr = "11" then
rx_done <= '0';
RXCHARISK_sr_done <= (others => '1');
RXCHARISvalid_sr_done <= (others => '0');
end if;
else
--- [__VV] : It can appear only in the beginning
if valid_byte_cntr = "100" then
valid_byte_cntr <= valid_byte_cntr + '1';
else -- either it is an irregular start or something went wrong
valid_byte_cntr <= "001";
irregular_stream <= '1';
end if;
RXDATA_sr <= RXDATA_sr(63 downto 0) & RXDATA_R_lane(7 downto 0);
RXCHARISK_sr <= RXCHARISK_sr(7 downto 0) & RXCHARISK_R_lane(0);
RXCHARISvalid_sr <= RXCHARISvalid_sr(7 downto 0) & RXCHARISvalid_R_lane(0);
if done_cntr = "11" then
rx_done <= '0';
RXCHARISK_sr_done <= (others => '1');
RXCHARISvalid_sr_done <= (others => '0');
end if;
end if;
else
if RXCHARISvalid_R_lane(1) = '1' and (RXCHARISK_R_lane(1) = '0' or (RXCHARISK_R_lane(1) = '1' and (RXDATA_R_lane(15 downto 8) = SC or RXDATA_R_lane(15 downto 8) = PD))) then
--- [VV__] : It can appear only in the end
RXDATA_sr <= RXDATA_sr(63 downto 0) & RXDATA_R_lane(15 downto 8);
RXCHARISK_sr <= RXCHARISK_sr(7 downto 0) & RXCHARISK_R_lane(1);
RXCHARISvalid_sr <= RXCHARISvalid_sr(7 downto 0) & RXCHARISvalid_R_lane(1);
if valid_byte_cntr = "011" then
valid_byte_cntr <= valid_byte_cntr + '1';
irregular_stream <= '0'; -- irregularity has been compensated for the first symbol
if done_cntr = "11" then
rx_done <= '0';
RXCHARISK_sr_done <= (others => '1');
RXCHARISvalid_sr_done <= (others => '0');
end if;
elsif valid_byte_cntr = "111" then -- 2 symbols (2x32b) are done
valid_byte_cntr <= (others => '0');
irregular_stream <= '0'; -- irregularity has been compensated for the second symbol
rx_done <= '1';
done_cntr <= (others => '0');
RXDATA_sr_done <= RXDATA_sr(55 downto 0) & RXDATA_R_lane(15 downto 8);
RXCHARISK_sr_done <= RXCHARISK_sr(6 downto 0) & RXCHARISK_R_lane(1);
RXCHARISvalid_sr_done <= RXCHARISvalid_sr(6 downto 0) & RXCHARISvalid_R_lane(1);
else -- something went wrong
valid_byte_cntr <= (others => '0');
irregular_stream <= '0';
if done_cntr = "11" then
rx_done <= '0';
RXCHARISK_sr_done <= (others => '1');
RXCHARISvalid_sr_done <= (others => '0');
end if;
end if;
else
--- [____]
if valid_byte_cntr /= "100" then -- No IDLE allowed, unless between two symbols: Something went wrong probably
valid_byte_cntr <= "000";
irregular_stream <= '0';
end if;
if done_cntr = "11" then
rx_done <= '0';
RXCHARISK_sr_done <= (others => '1');
RXCHARISvalid_sr_done <= (others => '0');
end if;
end if;
end if;
end if;
end if;
end process;
RXDATA_u <= RXDATA_swap(63 downto 56) & RXDATA_swap(47 downto 40) & RXDATA_swap(31 downto 24) & RXDATA_swap(15 downto 8) when mode_sel = '1' else -- x4 mode
RXDATA_sr_done(63 downto 32); -- x1 mode
RXCHARISK_u <= RXCHARISK_swap(7) & RXCHARISK_swap(5) & RXCHARISK_swap(3) & RXCHARISK_swap(1) when mode_sel = '1' else -- x4 mode
RXCHARISK_sr_done(7 downto 4); -- x1 mode
RXCHARISvalid_u <= RXCHARISvalid_swap(7) & RXCHARISvalid_swap(5) & RXCHARISvalid_swap(3) & RXCHARISvalid_swap(1) when mode_sel = '1' else -- x4 mode
RXCHARISvalid_sr_done(7 downto 4); -- x1 mode
RXDATA_l <= RXDATA_swap(55 downto 48) & RXDATA_swap(39 downto 32) & RXDATA_swap(23 downto 16) & RXDATA_swap(7 downto 0) when mode_sel = '1' else -- x4 mode
RXDATA_sr_done(31 downto 0); -- x1 mode
RXCHARISK_l <= RXCHARISK_swap(6) & RXCHARISK_swap(4) & RXCHARISK_swap(2) & RXCHARISK_swap(0) when mode_sel = '1' else -- x4 mode
RXCHARISK_sr_done(3 downto 0); -- x1 mode
RXCHARISvalid_l <= RXCHARISvalid_swap(6) & RXCHARISvalid_swap(4) & RXCHARISvalid_swap(2) & RXCHARISvalid_swap(0) when mode_sel = '1' else -- x4 mode
RXCHARISvalid_sr_done(3 downto 0); -- x1 mode
-- RXDATA_u <= RXDATA_swap(63 downto 56) & RXDATA_swap(47 downto 40) & RXDATA_swap(31 downto 24) & RXDATA_swap(15 downto 8);
-- RXCHARISK_u <= RXCHARISK_swap(7) & RXCHARISK_swap(5) & RXCHARISK_swap(3) & RXCHARISK_swap(1);
-- RXDATA_l <= RXDATA_swap(55 downto 48) & RXDATA_swap(39 downto 32) & RXDATA_swap(23 downto 16) & RXDATA_swap(7 downto 0);
-- RXCHARISK_l <= RXCHARISK_swap(6) & RXCHARISK_swap(4) & RXCHARISK_swap(2) & RXCHARISK_swap(0);
-- RXCHARISvalid_u <= RXCHARISvalid_swap(7) & RXCHARISvalid_swap(5) & RXCHARISvalid_swap(3) & RXCHARISvalid_swap(1);
-- RXCHARISvalid_l <= RXCHARISvalid_swap(6) & RXCHARISvalid_swap(4) & RXCHARISvalid_swap(2) & RXCHARISvalid_swap(0);
upper_symbol_type <= SYMBOL_IDLE when RXCHARISK_u = "1111" and RXCHARISvalid_u = "1111" else
SYMBOL_CONTROL when RXCHARISK_u = "1000" and RXCHARISvalid_u = "1111" and (RXDATA_u(31 downto 24) = SC or RXDATA_u(31 downto 24) = PD) else
SYMBOL_DATA when RXCHARISK_u = "0000" and RXCHARISvalid_u = "1111" else
SYMBOL_ERROR;
lower_symbol_type <= SYMBOL_IDLE when RXCHARISK_l = "1111" and RXCHARISvalid_l = "1111" else
SYMBOL_CONTROL when RXCHARISK_l = "1000" and RXCHARISvalid_l = "1111" and (RXDATA_l(31 downto 24) = SC or RXDATA_l(31 downto 24) = PD) else
SYMBOL_DATA when RXCHARISK_l = "0000" and RXCHARISvalid_l = "1111" else
SYMBOL_ERROR;
--
upper_symbol_not_idle <= '0' when upper_symbol_type = SYMBOL_IDLE else '1';
lower_symbol_not_idle <= '0' when lower_symbol_type = SYMBOL_IDLE else '1';
upper_symbol_not_error <= '0' when upper_symbol_type = SYMBOL_ERROR else '1';
lower_symbol_not_error <= '0' when lower_symbol_type = SYMBOL_ERROR else '1';
upper_symbol_valid <= upper_symbol_not_idle and upper_symbol_not_error;
lower_symbol_valid <= lower_symbol_not_idle and lower_symbol_not_error;
end RTL;
---------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------------------------------------------------------------------------
--
-- RapidIO IP Library Core
--
-- This file is part of the RapidIO IP library project
-- http://www.opencores.org/cores/rio/
--
-- To Do:
-- -
--
-- Author(s):
-- - A. Demirezen, [email protected]
--
-------------------------------------------------------------------------------
--
-- Copyright (C) 2013 Authors and OPENCORES.ORG
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--
------------------------------------------------------------------------------
------------------------------------------------------------------------------
--
-- File name: pcs_tx_controller.vhd
-- Rev: 0.0
-- Description: This entity controls the TX stream
--
--
------------------------------------------------------------------------------
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use work.rio_common.all;
entity pcs_tx_controller is
generic (
TCQ : time := 100 ps
);
port (
rst_n : in std_logic;
rio_clk : in std_logic; -- ~150 MHz
UCLK_x2 : in std_logic; -- 312,5 MHz
UCLK : in std_logic; -- 156,25 MHz
UCLK_x2_DV2 : in std_logic; -- 312,5 MHz @ x4 mode / 78,125 @ x1 (fallback mode)
UCLK_or_DV4 : in std_logic; -- 156,25 MHz @ x4 mode / 39,0625 @ x1 (fallback mode)
--
-- Interface to the RioSerial
outboundWrite_i : in std_logic;
outboundFull_o : out std_logic;
outboundSymbol_i : in std_logic_vector(33 downto 0);
-- outboundSymbolEmpty_i : in std_logic;
-- outboundSymbolRead_o : out std_logic;
-- outboundSymbol_i : in std_logic_vector(33 downto 0);
--
-- Interface to the GTX transceivers
TXDATA_o : out std_logic_vector(63 downto 0); -- N = 4
TXCHARISK_o : out std_logic_vector(7 downto 0);
--
-- Interface to the other blocks
send_ccs_i : in std_logic;
ccs_timer_rst_o : out std_logic;
send_idle_o : out std_logic_vector(1 downto 0);
send_K_i : in std_logic_vector(1 downto 0);
send_A_i : in std_logic_vector(1 downto 0);
send_R_i : in std_logic_vector(1 downto 0);
--
-- Interface to the port init
TXINHIBIT_02 : in std_logic;
TXINHIBIT_others : in std_logic;
port_initalized_i : in std_logic;
mode_sel_i : in std_logic;
mode_0_lane_sel_i : in std_logic
);
end pcs_tx_controller;
architecture RTL of pcs_tx_controller is
-------------------------------------------------------------------------------
COMPONENT pcs_tx_boudary_32b_in_64b_out
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(33 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(67 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
almost_empty : out STD_LOGIC;
almost_full : out STD_LOGIC;
valid : OUT STD_LOGIC
);
END COMPONENT;
-------------------------------------------------------------------------------
-- COMPONENT pcs_tx_boudary_32b_v2
-- PORT (
-- rst : IN STD_LOGIC;
-- wr_clk : IN STD_LOGIC;
-- rd_clk : IN STD_LOGIC;
-- din : IN STD_LOGIC_VECTOR(33 DOWNTO 0);
-- wr_en : IN STD_LOGIC;
-- rd_en : IN STD_LOGIC;
-- dout : OUT STD_LOGIC_VECTOR(33 DOWNTO 0);
-- full : OUT STD_LOGIC;
-- empty : OUT STD_LOGIC;
-- almost_empty : OUT STD_LOGIC;
-- valid : OUT STD_LOGIC
-- );
-- END COMPONENT;
-------------------------------------------------------------------------------
signal rst : std_logic:= '0';
signal fragment_counter : std_logic_vector(9 downto 0) := (others => '0');
signal outboundSymbolType : std_logic_vector(1 downto 0) := (others => '0');
signal outboundSymbol : std_logic_vector(33 downto 0) := (others => '0');
signal outboundSymbolRead : std_logic:= '0';
signal non_idle : std_logic:= '0';
signal decrement_frag_cntr : std_logic:= '0';
signal tx_fifo_full : std_logic:= '0';
signal symbol_empty : std_logic:= '0';
signal symbol_almost_empty : std_logic:= '0';
signal symbol_read : std_logic:= '0';
signal symbol_valid : std_logic:= '0';
-- signal symbol : std_logic_vector(33 downto 0) := (others => '0');
signal symbol : std_logic_vector(67 downto 0) := (others => '0');
signal symbol_u : std_logic_vector(33 downto 0) := (others => '0');
signal symbol_l : std_logic_vector(33 downto 0) := (others => '0');
-- signal symbol_type : std_logic_vector(1 downto 0) := (others => '0');
signal symbol_type : std_logic_vector(3 downto 0) := (others => '0');
signal symbol_type_u : std_logic_vector(1 downto 0) := (others => '0');
signal symbol_type_l : std_logic_vector(1 downto 0) := (others => '0');
signal TXDATA : std_logic_vector(63 downto 0); -- N = 4
signal TXCHARISK : std_logic_vector(7 downto 0);
signal TXDATA_u : std_logic_vector(31 downto 0);
signal TXCHARISK_u : std_logic_vector(3 downto 0);
signal TXDATA_l : std_logic_vector(31 downto 0);
signal TXCHARISK_l : std_logic_vector(3 downto 0);
signal TXDATA_u_idle : std_logic_vector(31 downto 0);
signal TXDATA_l_idle : std_logic_vector(31 downto 0);
signal word_switch : std_logic:= '0';
signal lane_switch : std_logic_vector(1 downto 0) := (others => '0');
signal cycle_switch : std_logic_vector(1 downto 0) := (others => '0');
signal read_switch : std_logic_vector(1 downto 0) := (others => '0');
signal send_idle_q : std_logic:= '0';
signal send_idle_reg : std_logic_vector(1 downto 0) := (others => '0');
signal send_idle : std_logic_vector(1 downto 0) := (others => '0');
signal idle_char_type_0 : std_logic_vector(2 downto 0) := (others => '0');
signal idle_char_type_1 : std_logic_vector(2 downto 0) := (others => '0');
signal send_ccs_cntr : std_logic_vector(1 downto 0) := (others => '0');
signal send_K : std_logic_vector(1 downto 0) := (others => '0');
signal send_A : std_logic_vector(1 downto 0) := (others => '0');
signal send_R : std_logic_vector(1 downto 0) := (others => '0');
signal send_ccs : std_logic:= '0';
signal send_ccs_q : std_logic:= '0';
signal do_not_interrupt : std_logic:= '0';
signal be_silent : std_logic:= '0';
signal fifo_wr_selective : std_logic:= '0';
signal fifo_wr_selective_q : std_logic:= '0';
signal fifo_wr_always_even : std_logic:= '0';
signal fifo_wr_odd_or_even : std_logic:= '0';
signal fifo_wr_evenly : std_logic:= '0';
signal outboundSymbolisData : std_logic:= '0';
signal outboundSymbolisData_q : std_logic:= '0';
signal outboundSymbol_q : std_logic_vector(33 downto 0) := (others => '0');
signal fifo_wr_evenly_q : std_logic:= '0';
-- signal send_K_ccs : std_logic:= '0';
-- signal send_R_ccs : std_logic:= '0';
-- signal send_K_q : std_logic:= '0';
-- signal send_A_q : std_logic:= '0';
-- signal send_R_q : std_logic:= '0';
----------------------------------------------------------------------------------
begin
--
rst <= not(rst_n);
outboundSymbolType <= outboundSymbol_i(33 downto 32);
-- Filtering the ERROR symbol out
outboundSymbol <= outboundSymbol_i when (outboundSymbolType = SYMBOL_DATA or outboundSymbolType = SYMBOL_CONTROL) else
SYMBOL_IDLE & outboundSymbol_i(31 downto 0);
fifo_wr_selective <= outboundWrite_i when (outboundSymbolType = SYMBOL_DATA or outboundSymbolType = SYMBOL_CONTROL) else '0';
fifo_wr_always_even <= fifo_wr_selective or (fifo_wr_selective_q and fifo_wr_odd_or_even);
outboundSymbolisData <= '1' when outboundSymbolType = SYMBOL_DATA else '0';
fifo_wr_evenly <= fifo_wr_selective or (fifo_wr_selective_q and fifo_wr_odd_or_even and not(outboundSymbolisData_q));
-- Writing to the FIFO
process(rio_clk)
begin
if rising_edge(rio_clk) then
fifo_wr_selective_q <= fifo_wr_selective;
outboundSymbolisData_q <= outboundSymbolisData;
if fifo_wr_selective = '1' then
fifo_wr_odd_or_even <= not(fifo_wr_odd_or_even);
elsif fifo_wr_selective_q = '1' then
fifo_wr_odd_or_even <= fifo_wr_odd_or_even and outboundSymbolisData_q; -- '0';
end if;
outboundSymbol_q <= outboundSymbol;
fifo_wr_evenly_q <= fifo_wr_evenly;
end if;
end process;
send_K <= send_K_i;
send_A <= send_A_i;
send_R <= send_R_i;
-- idle_char_type <= send_K & send_A & send_R;
idle_char_type_0 <= send_K(0) & send_A(0) & send_R(0);
idle_char_type_1 <= send_K(1) & send_A(1) & send_R(1);
be_silent <= '1' when TXINHIBIT_02 = '1' and TXINHIBIT_others = '1' else '0';
-- symbol_type <= symbol(33 downto 32);
symbol_type_u <= symbol_u(33 downto 32);
symbol_type_l <= symbol_l(33 downto 32);
symbol_u <= symbol(67 downto 34);
symbol_l <= symbol(33 downto 0);
send_idle(1) <= '1' when (send_ccs = '0') and
((symbol_read = '1' and symbol_type_u = SYMBOL_IDLE) or
(symbol_read = '0') or
(port_initalized_i = '0'))
else
'0';
send_idle(0) <= '1' when (send_ccs = '0') and
((symbol_read = '1' and symbol_type_l = SYMBOL_IDLE) or
(symbol_read = '0') or
(port_initalized_i = '0'))
else
'0';
send_idle_o <= send_idle; -- _reg;
-- symbol_read <= not(symbol_empty) and not(send_ccs) and not(send_ccs_q);
-- Pipelining
process(UCLK) -- _x2
begin
if rising_edge(UCLK) then
send_ccs <= not(do_not_interrupt) and send_ccs_i; -- will be high only during real CCS transmission
-- send_idle_reg <= send_idle;
end if;
end process;
-- Reading from the FIFO
process(UCLK_or_DV4) -- UCLK_x2_DV2
begin
if rising_edge(UCLK_or_DV4) then
-- case symbol_read is
-- when '0' =>
-- symbol_read <= not(symbol_empty) and not(send_ccs) and not(send_ccs_q); -- after TCQ;
-- when '1' =>
-- symbol_read <= not(symbol_almost_empty); -- after TCQ; -- and not(send_ccs) and not(send_ccs_q);
-- when others =>
-- symbol_read <= '0'; -- after TCQ;
-- end case;
end if;
end process;
tx_boundary_fifo : pcs_tx_boudary_32b_in_64b_out -- FWFT FIFO
PORT MAP (
rst => rst,
wr_clk => rio_clk,
wr_en => fifo_wr_evenly_q, --fifo_wr_always_even, --outboundWrite_i,
din => outboundSymbol_q,
full => open, -- outboundFull_o,
almost_full => outboundFull_o,
rd_clk => UCLK_or_DV4,
rd_en => symbol_read,
dout => symbol,
empty => symbol_empty,
almost_empty => symbol_almost_empty,
valid => symbol_valid
);
-- FIFO read / TX output process
process(rst_n, UCLK) -- UCLK_x2
begin
if rst_n = '0' then
ccs_timer_rst_o <= '0';
do_not_interrupt <= '0';
TXDATA_u <= (others => '0');
TXCHARISK_u <= (others => '0');
TXDATA_l <= (others => '0');
TXCHARISK_l <= (others => '0');
cycle_switch <= (others => '0');
read_switch <= (others => '0');
symbol_read <= '0';
elsif rising_edge(UCLK) then
if be_silent = '0' then -- Transmitters are NOT inhibitied
if send_ccs = '1' or send_ccs_q = '1' then -- Transmitting the clock compensation sequence (ccs) = |K|,|R|,|R|,|R|
symbol_read <= '0';
if send_ccs_q = '0' then
TXDATA_u <= K_column;
TXCHARISK_u <= (others => '1');
TXDATA_l <= R_column;
TXCHARISK_l <= (others => '1');
ccs_timer_rst_o <= '1';
else
TXDATA_u <= R_column;
TXCHARISK_u <= (others => '1');
TXDATA_l <= R_column;
TXCHARISK_l <= (others => '1');
end if;
else -- Transmitting the IDLE sequence or the CONTROL/DATA symbols
read_switch <= read_switch + '1';
if read_switch = "00" then
case symbol_read is
when '0' =>
symbol_read <= not(symbol_empty); -- and not(send_ccs) and not(send_ccs_q); -- after TCQ;
do_not_interrupt <= not(symbol_empty);
when '1' =>
symbol_read <= not(symbol_almost_empty); -- after TCQ; -- and not(send_ccs) and not(send_ccs_q);
do_not_interrupt <= not(symbol_almost_empty);
when others =>
symbol_read <= '0'; -- after TCQ;
do_not_interrupt <= '0';
end case;
end if;
ccs_timer_rst_o <= '0';
if symbol_read = '1' then -- two symbols have been read, at least one of them is non-idle, they should be forwarded in 1 or 4 cycles
case mode_sel_i is
when '1' => -- Lane stripping (x4 mode: rd_clk = UCLK)
case symbol_type_u is
when SYMBOL_DATA =>
TXDATA_u <= symbol_u(31 downto 24) & symbol_u(23 downto 16) & symbol_u(15 downto 8) & symbol_u(7 downto 0);
TXCHARISK_u <= (others => '0');
when SYMBOL_CONTROL =>
TXDATA_u <= symbol_u(31 downto 24) & symbol_u(23 downto 16) & symbol_u(15 downto 8) & symbol_u(7 downto 0);
TXCHARISK_u <= "1000";
when SYMBOL_IDLE =>
TXDATA_u <= TXDATA_u_idle;
TXCHARISK_u <= (others => '1');
when others =>
-- dummy
TXDATA_u <= TXDATA_u_idle;
TXCHARISK_u <= (others => '1');
end case;
case symbol_type_l is
when SYMBOL_DATA =>
TXDATA_l <= symbol_l(31 downto 24) & symbol_l(23 downto 16) & symbol_l(15 downto 8) & symbol_l(7 downto 0);
TXCHARISK_l <= (others => '0');
when SYMBOL_CONTROL =>
TXDATA_l <= symbol_l(31 downto 24) & symbol_l(23 downto 16) & symbol_l(15 downto 8) & symbol_l(7 downto 0);
TXCHARISK_l <= "1000";
when SYMBOL_IDLE =>
TXDATA_l <= TXDATA_l_idle;
TXCHARISK_l <= (others => '1');
when others =>
-- dummy
TXDATA_l <= TXDATA_l_idle;
TXCHARISK_l <= (others => '1');
end case;
when '0' => -- Slow motion read (x1 mode: rd_clk = UCLK_DV4)
cycle_switch <= cycle_switch + '1';
-- Cycle | Symbol part to be sent
---------|----------------------
-- 00 | symbol_u(31 downto 16)
-- 01 | symbol_u(15 downto 0)
-- 10 | symbol_l(31 downto 16)
-- 11 | symbol_l(15 downto 0)
case cycle_switch(1) is
when '0' =>
case cycle_switch(0) is
when '0' => -- 00
if symbol_type_u /= SYMBOL_IDLE then
TXDATA_u <= symbol_u(31 downto 24) & symbol_u(31 downto 24) & symbol_u(31 downto 24) & symbol_u(31 downto 24);
if symbol_type_u = SYMBOL_DATA then
TXCHARISK_u <= (others => '0');
else -- if symbol_type_u = SYMBOL_CONTROL then
TXCHARISK_u <= (others => '1');
end if;
TXDATA_l <= symbol_u(23 downto 16) & symbol_u(23 downto 16) & symbol_u(23 downto 16) & symbol_u(23 downto 16);
TXCHARISK_l <= (others => '0');
else -- if symbol_type_u = SYMBOL_IDLE then
TXDATA_u <= TXDATA_u_idle;
TXCHARISK_u <= (others => '1');
TXDATA_l <= TXDATA_l_idle;
TXCHARISK_l <= (others => '1');
end if;
when '1' => -- 01
if symbol_type_u /= SYMBOL_IDLE then
TXDATA_u <= symbol_u(15 downto 8) & symbol_u(15 downto 8) & symbol_u(15 downto 8) & symbol_u(15 downto 8);
TXCHARISK_u <= (others => '0'); -- This is the second part: does not matter control or data
TXDATA_l <= symbol_u(7 downto 0) & symbol_u(7 downto 0) & symbol_u(7 downto 0) & symbol_u(7 downto 0);
TXCHARISK_l <= (others => '0');
else -- if symbol_type_u = SYMBOL_IDLE then
TXDATA_u <= TXDATA_u_idle;
TXCHARISK_u <= (others => '1');
TXDATA_l <= TXDATA_l_idle;
TXCHARISK_l <= (others => '1');
end if;
when others =>
-- dummy
end case;
when '1' =>
case cycle_switch(0) is
when '0' =>
if symbol_type_l /= SYMBOL_IDLE then
TXDATA_u <= symbol_l(31 downto 24) & symbol_l(31 downto 24) & symbol_l(31 downto 24) & symbol_l(31 downto 24);
if symbol_type_l = SYMBOL_DATA then
TXCHARISK_u <= (others => '0');
else -- if symbol_type_l = SYMBOL_CONTROL then
TXCHARISK_u <= (others => '1');
end if;
TXDATA_l <= symbol_l(23 downto 16) & symbol_l(23 downto 16) & symbol_l(23 downto 16) & symbol_l(23 downto 16);
TXCHARISK_l <= (others => '0');
else -- if symbol_type_l = SYMBOL_IDLE then
TXDATA_u <= TXDATA_u_idle;
TXCHARISK_u <= (others => '1');
TXDATA_l <= TXDATA_l_idle;
TXCHARISK_l <= (others => '1');
end if;
when '1' =>
if symbol_type_l /= SYMBOL_IDLE then
TXDATA_u <= symbol_l(15 downto 8) & symbol_l(15 downto 8) & symbol_l(15 downto 8) & symbol_l(15 downto 8);
TXCHARISK_u <= (others => '0'); -- This is the second part: does not matter control or data
TXDATA_l <= symbol_l(7 downto 0) & symbol_l(7 downto 0) & symbol_l(7 downto 0) & symbol_l(7 downto 0);
TXCHARISK_l <= (others => '0');
else -- if symbol_type_l = SYMBOL_IDLE then
TXDATA_u <= TXDATA_u_idle;
TXCHARISK_u <= (others => '1');
TXDATA_l <= TXDATA_l_idle;
TXCHARISK_l <= (others => '1');
end if;
when others =>
-- dummy
end case;
when others =>
-- dummy
end case;
when others =>
-- dummy
end case;
-----------------------------------------------------------------------------
else -- No Symbols are present at the FIFO output: Transmitting an idle sequence: |K| or |A| or |R|
TXDATA_u <= TXDATA_u_idle;
TXCHARISK_u <= (others => '1');
TXDATA_l <= TXDATA_l_idle;
TXCHARISK_l <= (others => '1');
end if;
end if;
else -- Transmitters are inhibitied
TXDATA_u <= x"BCBCBCBC" ;
TXCHARISK_u <= (others => '1');
TXDATA_l <= x"FDFDFDFD" ;
TXCHARISK_l <= (others => '1');
end if;
end if;
end process;
-- Combinational idle drive process
process(idle_char_type_0, idle_char_type_1)
begin
case idle_char_type_1 is
when "100" => -- |K| (~%50)
TXDATA_u_idle <= K_column;
when "010" => -- |A| (1/16 .. 1/32)
TXDATA_u_idle <= A_column;
when "001" => -- |R| (~%50)
TXDATA_u_idle <= R_column;
when others =>
-- dummy
TXDATA_u_idle <= K_column;
end case;
case idle_char_type_0 is
when "100" => -- |K| (~%50)
TXDATA_l_idle <= K_column;
when "010" => -- |A| (1/16 .. 1/32)
TXDATA_l_idle <= A_column;
when "001" => -- |R| (~%50)
TXDATA_l_idle <= R_column;
when others =>
-- dummy
TXDATA_l_idle <= R_column;
end case;
end process;
-- TXDATA buffering by UCLK
process(UCLK)
begin
if rising_edge(UCLK) then
------------------
-- MUST BE SWAPPED
TXDATA_o <= TXDATA_u( 7 downto 0) & TXDATA_l( 7 downto 0) & TXDATA_u(15 downto 8) & TXDATA_l(15 downto 8)
& TXDATA_u(23 downto 16) & TXDATA_l(23 downto 16) & TXDATA_u(31 downto 24) & TXDATA_l(31 downto 24);
TXCHARISK_o <= TXCHARISK_u(0) & TXCHARISK_l(0) & TXCHARISK_u(1) & TXCHARISK_l(1) & TXCHARISK_u(2) & TXCHARISK_l(2) & TXCHARISK_u(3) & TXCHARISK_l(3);
------------------
end if;
end process;
-- Delaying send_ccs
process(UCLK)
begin
if rising_edge(UCLK) then
if be_silent = '0' then
send_ccs_q <= send_ccs; ---
else
send_ccs_q <= '0';
end if;
end if;
end process;
end RTL;
----------------------------------------------------------------------------------------------------------------------------------------------------------------------
--
-- RapidIO IP Library Core
--
-- This file is part of the RapidIO IP library project
-- http://www.opencores.org/cores/rio/
--
-- To Do:
-- -
--
-- Author(s):
-- - A. Demirezen, [email protected]
--
-------------------------------------------------------------------------------
--
-- Copyright (C) 2013 Authors and OPENCORES.ORG
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--
------------------------------------------------------------------------------
------------------------------------------------------------------------------
--
-- File name: port_init_fsms.vhd
-- Rev: 0.0
-- Description: This entity does the 1x/Nx port init according to the
-- RIO Sepec. Part-6, subchapter 4.2
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use work.rio_common.all;
--use work.rio_common_sim.all;
entity port_init_fsms is
generic (
TCQ : time := 100 ps
);
port (
rst_n : in std_logic;
UCLK_x2 : in std_logic;
UCLK : in std_logic;
UCLK_DV4 : in std_logic;
UCLK_DV_1024 : in std_logic;
force_reinit : in std_logic:='0'; -- force retraining
mode_sel : out std_logic; -- 0: x1 fallback mode / 1: xN Mode
mode_0_lane_sel : out std_logic; -- If mode_sel = 0 then 0: Lane 0 is active(R), 1: Lane 2 is active else don't care
port_initalized : out std_logic; -- 1: Port initialization is successfully complete
lane_sync : out std_logic_vector(N-1 downto 0); -- Lane is synchoronised
RXCHARISvalid : out std_logic_vector(N*2-1 downto 0);
-- GTXRESET : out std_logic;
TXINHIBIT_02 : out std_logic;
TXINHIBIT_others : out std_logic;
ENCHANSYNC : out std_logic;
-- TXDATA : out std_logic_vector(N*16-1 downto 0);
-- TXCHARISK : out std_logic_vector(N*2-1 downto 0);
PLLLKDET : in std_logic;
RXDATA : in std_logic_vector(N*16-1 downto 0);
RXCHARISK : in std_logic_vector(N*2-1 downto 0);
RXCHARISCOMMA : in std_logic_vector(N*2-1 downto 0);
RXBYTEISALIGNED : in std_logic_vector(N-1 downto 0);
RXBYTEREALIGN : in std_logic_vector(N-1 downto 0);
RXELECIDLE : in std_logic_vector(N-1 downto 0);
RXDISPERR : in std_logic_vector(N*2-1 downto 0);
RXNOTINTABLE : in std_logic_vector(N*2-1 downto 0);
RXBUFERR : in std_logic;
RXBUFRST : out std_logic;
CHBONDDONE : in std_logic_vector(N-1 downto 0)
);
end port_init_fsms;
architecture rtl of port_init_fsms is
-------------------------------------------------------------------------------------------------------------------------------------------
-- Lane_Synchronization State Machine
type lane_sync_states is (NO_SYNC, NO_SYNC_1, NO_SYNC_2, NO_SYNC_2a, NO_SYNC_2b, NO_SYNC_3, SYNC, SYNCa, SYNCb, SYNC_1, SYNC_2, SYNC_2a, SYNC_2b, SYNC_3, SYNC_4);
type lane_sync_states_array is array (N-1 downto 0) of lane_sync_states;
signal lane_sync_state_n : lane_sync_states_array := (others => NO_SYNC);
signal lane_sync_n : std_logic_vector(N-1 downto 0) := (others => '0');
signal Kcounter_n : Kcounter_array_type := (others => (others => '0'));
signal Vcounter_n : Vcounter_array_type := (others => (others => '0'));
signal Icounter_n : Icounter_array_type := (others => (others => '0'));
signal code_group_valid : std_logic_vector(N*2-1 downto 0) := (others => '0');
-------------------------------------------------------------------------------------------------------------------------------------------
-- Lane_Alignment State Machine
type lane_alignment_states is (NOT_ALIGNED, NOT_ALIGNED_1, NOT_ALIGNED_2, ALIGNED, ALIGNED_1, ALIGNED_2, ALIGNED_3);
signal lane_alignment_state : lane_alignment_states := NOT_ALIGNED;
signal N_lanes_aligned : std_logic := '0';
signal Acounter : std_logic_vector(2 downto 0) := (others => '0');
signal Mcounter : Mcounter_type := (others => '0');
signal lane_alignment_reset : std_logic := '0';
signal N_lane_sync : std_logic := '0';
constant N_lanes_all_high : std_logic_vector(N-1 downto 0) := (others => '1');
constant N_lanes_all_low : std_logic_vector(N-1 downto 0) := (others => '0');
signal A_column_valid : std_logic := '0';
signal align_error : std_logic := '0';
signal A_column_valid_upper : std_logic := '0';
signal align_error_upper : std_logic := '0';
signal A_column_valid_lower : std_logic := '0';
signal align_error_lower : std_logic := '0';
signal RXCHARIS_A_upper : std_logic_vector(N-1 downto 0) := (others => '0');
signal RXCHARIS_A_lower : std_logic_vector(N-1 downto 0) := (others => '0');
-------------------------------------------------------------------------------------------------------------------------------------------
-- begin --dummy
-- 1x/Nx Mode Init State Machine
type mode_init_states is (SILENT, SEEK, DISCOVERY, x1_RECOVERY, Nx_MODE, x1_MODE_LANE0, x1_MODE_LANE2);
signal mode_init_state : mode_init_states := SILENT;
signal lanes02_drvr_oe : std_logic := '0';
signal N_lanes_drvr_oe : std_logic := '0';
signal Nx_mode_active : std_logic := '0';
signal receive_lane2 : std_logic := '0';
signal force_reinit_reg : std_logic := '0';
signal force_reinit_clear : std_logic := '0';
signal silence_timer_en : std_logic := '0';
signal silence_timer_done : std_logic := '0';
signal silence_timer : std_logic_vector(4 downto 0) := (others => '0');
signal disc_tmr_en : std_logic := '0';
signal disc_tmr_done : std_logic := '0';
signal disc_tmr : std_logic_vector(15 downto 0) := (others => '0');
signal port_initalized_reg : std_logic := '0';
signal idle_selected : std_logic := '1'; -- Only IDLE1 is to be used
signal Nx_mode_enabled : std_logic := '1'; -- Nx mode is to be always enabled
signal force_1x_mode : std_logic := '0'; -- don't force 1x mode
signal force_laneR : std_logic := '0'; -- don't care, when force_1x_mode = 0
signal lane_ready_n : std_logic_vector(N-1 downto 0) := (others => '0');
signal rcvr_trained_n : std_logic_vector(N-1 downto 0) := (others => '0');
signal N_lanes_ready : std_logic := '0';
signal rxbufrst_cntr : std_logic_vector(2 downto 0) := (others => '0');
signal rxbuferr_reg : std_logic := '0';
-------------------------------------------------------------------------------------------------------------------------------------------
begin
lane_sync <= lane_sync_n;
----------------------------------------------------------------
-- Figure 4-14. Lane_Synchronization State Machine for N Lanes
GEN_LANE_SYNC_FSM: for i in 0 to N-1 generate
code_group_valid(i*2) <= not(RXNOTINTABLE(i*2) ) and not(RXDISPERR(i*2) );
code_group_valid(i*2+1) <= not(RXNOTINTABLE(i*2+1)) and not(RXDISPERR(i*2+1));
RXCHARISvalid(i*2) <= code_group_valid(i*2) ;
RXCHARISvalid(i*2+1) <= code_group_valid(i*2+1);
process(rst_n, UCLK) -- (UCLK_x2) --
begin
if rst_n = '0' then
lane_sync_state_n(i) <= NO_SYNC;
lane_sync_n(i) <= '0';
Kcounter_n(i) <= (others => '0');
Vcounter_n(i) <= (others => '0');
elsif rising_edge(UCLK) then
case lane_sync_state_n(i) is
when NO_SYNC =>
-- change(signal_detect[n])
if RXELECIDLE(i) = '1' then
lane_sync_n(i) <= '0';
Kcounter_n(i) <= (others => '0');
Vcounter_n(i) <= (others => '0');
-- signal_detect[n] & /COMMA/ [ KK-- ] : /K/ is being detected at the upper half
elsif (code_group_valid(i*2+1) = '1' and RXCHARISCOMMA(i*2+1) = '1') then
-- signal_detect[n] & /COMMA/ [ --KK ] : /K/ is being detected also at the lower half
if (code_group_valid(i*2) = '1' and RXCHARISCOMMA(i*2) = '1') then
lane_sync_state_n(i) <= NO_SYNC_2;
Kcounter_n(i) <= Kcounter_n(i) + "10";
Vcounter_n(i) <= Vcounter_n(i) + "10";
-- signal_detect[n] [ --VV ] : At the lower half: no comma, but valid
elsif (code_group_valid(i*2) = '1') then
lane_sync_state_n(i) <= NO_SYNC_2;
Kcounter_n(i) <= Kcounter_n(i) + '1';
Vcounter_n(i) <= Vcounter_n(i) + "10";
-- do nothing
else
lane_sync_n(i) <= '0';
Kcounter_n(i) <= (others => '0');
Vcounter_n(i) <= (others => '0');
end if;
----------------------------------------------------------------------------------------------
-- signal_detect[n] & /COMMA/ [ --KK ] : /K/ is being detected only at the lower half
elsif (code_group_valid(i*2) = '1' and RXCHARISCOMMA(i*2) = '1') then
lane_sync_state_n(i) <= NO_SYNC_2;
Kcounter_n(i) <= Kcounter_n(i) + '1';
Vcounter_n(i) <= Vcounter_n(i) + '1';
----------------------------------------------------------------------------------------------
-- !signal_detect[n] | !/COMMA/
else
lane_sync_n(i) <= '0';
Kcounter_n(i) <= (others => '0');
Vcounter_n(i) <= (others => '0');
end if;
-- -- change(signal_detect[n])
-- if RXELECIDLE(i) = '1' then
-- lane_sync_n(i) <= '0';
-- Kcounter_n(i) <= (others => '0');
-- Vcounter_n(i) <= (others => '0');
-- -- signal_detect[n] & /COMMA/ [ KK-- ] : /K/ is being detected at the upper half
-- elsif (code_group_valid(i*2+1) = '1' and RXCHARISCOMMA(i*2+1) = '1') then
-- lane_sync_state_n(i) <= NO_SYNC_2a;
-- Kcounter_n(i) <= Kcounter_n(i) + '1';
-- Vcounter_n(i) <= Vcounter_n(i) + '1';
-- -- signal_detect[n] & /COMMA/ [ --KK ] : /K/ is being detected at the lower half
-- elsif (code_group_valid(i*2) = '1' and RXCHARISCOMMA(i*2) = '1') then
-- lane_sync_state_n(i) <= NO_SYNC_2b;
-- Kcounter_n(i) <= Kcounter_n(i) + '1';
-- Vcounter_n(i) <= Vcounter_n(i) + '1';
-- -- !signal_detect[n] | !/COMMA/
-- else
-- lane_sync_n(i) <= '0';
-- Kcounter_n(i) <= (others => '0');
-- Vcounter_n(i) <= (others => '0');
-- end if;
-- when NO_SYNC_1 =>
when NO_SYNC_2 =>
-- [ IIXX or XXII ] -- One of both /INVALID/
if (code_group_valid(i*2) = '0' or code_group_valid(i*2+1) = '0') then
lane_sync_state_n(i) <= NO_SYNC;
lane_sync_n(i) <= '0';
Kcounter_n(i) <= (others => '0');
Vcounter_n(i) <= (others => '0');
-- [ KKKK ] -- Both /COMMA/
elsif (RXCHARISCOMMA(i*2) = '1' and RXCHARISCOMMA(i*2+1) = '1') then
-- (Kcounter[n] > 126) & (Vcounter[n] > Vmin-1)
if Kcounter_n(i) >= Kmin and Vcounter_n(i) >= Vmin then
lane_sync_state_n(i) <= SYNC;
-- (Kcounter[n] < 127) | (Vcounter[n] < Vmin)
else
Kcounter_n(i) <= Kcounter_n(i) + "10";
Vcounter_n(i) <= Vcounter_n(i) + "10";
end if;
-- [ KKVV or VVKK ] -- One of both /COMMA/
elsif (RXCHARISCOMMA(i*2) = '1' or RXCHARISCOMMA(i*2+1) = '1') then
-- (Kcounter[n] > 126) & (Vcounter[n] > Vmin-1)
if Kcounter_n(i) >= Kmin and Vcounter_n(i) >= Vmin then
lane_sync_state_n(i) <= SYNC;
-- (Kcounter[n] < 127) | (Vcounter[n] < Vmin)
else
Kcounter_n(i) <= Kcounter_n(i) + '1' ;
Vcounter_n(i) <= Vcounter_n(i) + "10";
end if;
-- [ VVVV ] -- None of both /COMMA/, but both /VALID/
else -- if RXCHARISCOMMA(i*2) = '0') and RXCHARISCOMMA(i*2+1) = '0') then
-- (Kcounter[n] > 126) & (Vcounter[n] > Vmin-1)
if Kcounter_n(i) >= Kmin and Vcounter_n(i) >= Vmin then
lane_sync_state_n(i) <= SYNC;
-- (Kcounter[n] < 127) | (Vcounter[n] < Vmin)
else
Vcounter_n(i) <= Vcounter_n(i) + "10";
end if;
end if;
-- when NO_SYNC_2a =>
-- -- !(/COMMA/|/INVALID/)
-- if (code_group_valid(i*2) = '1' and not(RXCHARISCOMMA(i*2) = '1')) then --RXCHARISK(i*2) = '1' and RXDATA(i*16+7 downto i*16) = x"BC")) then
-- lane_sync_state_n(i) <= NO_SYNC_2b;
-- Vcounter_n(i) <= Vcounter_n(i) + '1';
-- -- /COMMA/
-- elsif (code_group_valid(i*2) = '1' and RXCHARISCOMMA(i*2) = '1') then --RXCHARISK(i*2) = '1' and RXDATA(i*16+7 downto i*16) = x"BC") then
-- -- (Kcounter[n] > 126) & (Vcounter[n] > Vmin-1)
-- if Kcounter_n(i) >= Kmin and Vcounter_n(i) >= Vmin then
-- lane_sync_state_n(i) <= SYNCb;
-- -- (Kcounter[n] < 127) | (Vcounter[n] < Vmin)
-- else
-- lane_sync_state_n(i) <= NO_SYNC_2b;
-- Kcounter_n(i) <= Kcounter_n(i) + '1';
-- Vcounter_n(i) <= Vcounter_n(i) + '1';
-- end if;
-- -- /INVALID/
-- elsif (code_group_valid(i*2) = '0') then
-- lane_sync_state_n(i) <= NO_SYNC;
-- lane_sync_n(i) <= '0';
-- Kcounter_n(i) <= (others => '0');
-- Vcounter_n(i) <= (others => '0');
-- end if;
--
-- when NO_SYNC_2b =>
-- -- !(/COMMA/|/INVALID/)
-- if (code_group_valid(i*2+1) = '1' and not(RXCHARISCOMMA(i*2+1) = '1')) then --RXCHARISK(i*2+1) = '1' and RXDATA(i*16+15 downto i*16+8) = x"BC")) then
-- lane_sync_state_n(i) <= NO_SYNC_2a;
-- Vcounter_n(i) <= Vcounter_n(i) + '1';
-- -- /COMMA/
-- elsif (code_group_valid(i*2+1) = '1' and RXCHARISCOMMA(i*2+1) = '1') then --RXCHARISK(i*2+1) = '1' and RXDATA(i*16+15 downto i*16+8) = x"BC") then
-- -- (Kcounter[n] > 126) & (Vcounter[n] > Vmin-1)
-- if Kcounter_n(i) >= Kmin and Vcounter_n(i) >= Vmin then
-- lane_sync_state_n(i) <= SYNCa;
-- -- (Kcounter[n] < 127) | (Vcounter[n] < Vmin)
-- else
-- lane_sync_state_n(i) <= NO_SYNC_2a;
-- Kcounter_n(i) <= Kcounter_n(i) + '1';
-- Vcounter_n(i) <= Vcounter_n(i) + '1';
-- end if;
-- -- /INVALID/
-- elsif (code_group_valid(i*2+1) = '0') then
-- lane_sync_state_n(i) <= NO_SYNC;
-- lane_sync_n(i) <= '0';
-- Kcounter_n(i) <= (others => '0');
-- Vcounter_n(i) <= (others => '0');
-- end if;
-- when NO_SYNC_3 =>
when SYNC =>
-- Both /VALID/
if (code_group_valid(i*2) = '1' and code_group_valid(i*2+1) = '1') then
lane_sync_n(i) <= '1';
Icounter_n(i) <= (others => '0');
-- One of both /INVALID/
elsif (code_group_valid(i*2) = '1' or code_group_valid(i*2+1) = '1') then
Icounter_n(i) <= Icounter_n(i) + '1';
lane_sync_state_n(i) <= SYNC_2;
-- Both /INVALID/
else
Icounter_n(i) <= Icounter_n(i) + "10";
lane_sync_state_n(i) <= SYNC_2;
end if;
--
-- when SYNCa =>
-- -- /INVALID/
-- if (code_group_valid(i*2) = '0') then
-- Icounter_n(i) <= Icounter_n(i) + '1';
-- lane_sync_state_n(i) <= SYNC_2b;
-- -- /VALID/
-- else
-- lane_sync_state_n(i) <= SYNCb;
-- lane_sync_n(i) <= '1';
-- Icounter_n(i) <= (others => '0');
-- end if;
--
-- when SYNCb =>
-- -- /INVALID/
-- if (code_group_valid(i*2+1) = '0') then
-- Icounter_n(i) <= Icounter_n(i) + '1';
-- lane_sync_state_n(i) <= SYNC_2a;
-- -- /VALID/
-- else
-- lane_sync_state_n(i) <= SYNCa;
-- lane_sync_n(i) <= '1';
-- Icounter_n(i) <= (others => '0');
-- end if;
-- when SYNC_1 =>
when SYNC_2 =>
-- Both /VALID/
if (code_group_valid(i*2) = '1' and code_group_valid(i*2+1) = '1') then
Vcounter_n(i) <= Vcounter_n(i) + "10";
-- (Vcounter[n] < 255)
if Vcounter_n(i) < x"FF" then
-- do nothing
lane_sync_state_n(i) <= SYNC_2;
-- (Vcounter[n] = 255)
else
Icounter_n(i) <= Icounter_n(i) - '1';
Vcounter_n(i) <= (others => '0');
-- (Icounter[n] > 0)
if Icounter_n(i) > Ione then
-- do nothing
lane_sync_state_n(i) <= SYNC_2;
-- (Icounter[n] = 0)
else
lane_sync_state_n(i) <= SYNC;
end if;
end if;
-- One of both /INVALID/
elsif (code_group_valid(i*2) = '1' or code_group_valid(i*2+1) = '1') then
Icounter_n(i) <= Icounter_n(i) + '1';
Vcounter_n(i) <= (others => '0');
-- (Icounter[n] = Imax)
if Icounter_n(i) = Imax then
lane_sync_state_n(i) <= NO_SYNC;
lane_sync_n(i) <= '0';
Kcounter_n(i) <= (others => '0');
-- (Icounter[n] < Imax)
else
-- do nothing
lane_sync_state_n(i) <= SYNC_2;
end if;
-- Both /INVALID/
else
Icounter_n(i) <= Icounter_n(i) + "10";
Vcounter_n(i) <= (others => '0');
-- (Icounter[n] = Imax)
if Icounter_n(i) = Imax then
lane_sync_state_n(i) <= NO_SYNC;
lane_sync_n(i) <= '0';
Kcounter_n(i) <= (others => '0');
-- (Icounter[n] < Imax)
else
-- do nothing
lane_sync_state_n(i) <= SYNC_2;
end if;
end if;
----------------------------------------------
-- when SYNC_2a =>
-- -- /INVALID/
-- if (code_group_valid(i*2+1) = '0') then
-- Icounter_n(i) <= Icounter_n(i) + '1';
-- Vcounter_n(i) <= (others => '0');
-- -- (Icounter[n] = Imax)
-- if Icounter_n(i) = Imax then
-- lane_sync_state_n(i) <= NO_SYNC;
-- lane_sync_n(i) <= '0';
-- Kcounter_n(i) <= (others => '0');
-- -- (Icounter[n] < Imax)
-- else
-- lane_sync_state_n(i) <= SYNC_2b;
-- end if;
-- -- /VALID/
-- else
-- Vcounter_n(i) <= Vcounter_n(i) + '1';
-- -- (Vcounter[n] < 255)
-- if Vcounter_n(i) < x"FF" then
-- lane_sync_state_n(i) <= SYNC_2b;
-- -- (Vcounter[n] = 255)
-- else
-- Icounter_n(i) <= Icounter_n(i) - '1';
-- Vcounter_n(i) <= (others => '0');
-- -- (Icounter[n] > 0)
-- if Icounter_n(i) > Izero then
-- lane_sync_state_n(i) <= SYNC_2b;
-- -- (Icounter[n] = 0)
-- else
-- lane_sync_state_n(i) <= SYNCb;
-- end if;
-- end if;
-- end if;
--
-- when SYNC_2b =>
-- -- /INVALID/
-- if (code_group_valid(i*2+1) = '0') then
-- Icounter_n(i) <= Icounter_n(i) + '1';
-- Vcounter_n(i) <= (others => '0');
-- -- (Icounter[n] = Imax)
-- if Icounter_n(i) = Imax then
-- lane_sync_state_n(i) <= NO_SYNC;
-- lane_sync_n(i) <= '0';
-- Kcounter_n(i) <= (others => '0');
-- -- (Icounter[n] < Imax)
-- else
-- lane_sync_state_n(i) <= SYNC_2a;
-- end if;
-- -- /VALID/
-- else
-- Vcounter_n(i) <= Vcounter_n(i) + '1';
-- -- (Vcounter[n] < 255)
-- if Vcounter_n(i) < x"FF" then
-- lane_sync_state_n(i) <= SYNC_2a;
-- -- (Vcounter[n] = 255)
-- else
-- Icounter_n(i) <= Icounter_n(i) - '1';
-- Vcounter_n(i) <= (others => '0');
-- -- (Icounter[n] > 0)
-- if Icounter_n(i) > Izero then
-- lane_sync_state_n(i) <= SYNC_2a;
-- -- (Icounter[n] = 0)
-- else
-- lane_sync_state_n(i) <= SYNCa;
-- end if;
-- end if;
-- end if;
-- when SYNC_3 =>
-- when SYNC_4 =>
when others =>
lane_sync_state_n(i) <= NO_SYNC;
lane_sync_n(i) <= '0';
Kcounter_n(i) <= (others => '0');
Vcounter_n(i) <= (others => '0');
end case;
end if;
end process;
end generate GEN_LANE_SYNC_FSM;
----------------------------------------------------------------
-- Figure 4-15. Lane_Alignment State Machine (for N lanes)
N_lane_sync <= '1' when lane_sync_n = N_lanes_all_high else '0';
lane_alignment_reset <= N_lane_sync and rst_n;
A_column_valid_upper <= '1' when (RXCHARIS_A_upper = N_lanes_all_high) else '0';
A_column_valid_lower <= '1' when (RXCHARIS_A_lower = N_lanes_all_high) else '0';
A_column_valid <= A_column_valid_upper or A_column_valid_lower;
align_error_upper <= '1' when (RXCHARIS_A_upper /= N_lanes_all_low) and (RXCHARIS_A_upper /= N_lanes_all_high) else '0';
align_error_lower <= '1' when (RXCHARIS_A_lower /= N_lanes_all_low) and (RXCHARIS_A_lower /= N_lanes_all_high) else '0';
align_error <= align_error_upper or align_error_lower;
GEN_CHAR_A_CHECKER: for i in 0 to N-1 generate
RXCHARIS_A_upper(i) <= '1' when (code_group_valid(i*2+1) = '1') and (RXCHARISK(i*2+1) = '1') and (RXDATA(i*16+15 downto i*16+8) = A_align) else '0';
RXCHARIS_A_lower(i) <= '1' when (code_group_valid(i*2) = '1' ) and (RXCHARISK(i*2) = '1' ) and (RXDATA(i*16+7 downto i*16 ) = A_align) else '0';
end generate GEN_CHAR_A_CHECKER;
process(lane_alignment_reset, UCLK)
begin
if lane_alignment_reset = '0' then
lane_alignment_state <= NOT_ALIGNED;
N_lanes_aligned <= '0';
Acounter <= (others => '0');
-- Mcounter <= (others => '0');
elsif rising_edge(UCLK) then
-- if lane_alignment_reset = '1' then
case lane_alignment_state is
when NOT_ALIGNED =>
-- N_lane_sync & ||A||
if N_lane_sync = '1' and A_column_valid = '1' then
Acounter <= Acounter + '1';
lane_alignment_state <= NOT_ALIGNED_2;
end if;
-- when NOT_ALIGNED_1 =>
when NOT_ALIGNED_2 =>
-- align_error
if align_error = '1' then
lane_alignment_state <= NOT_ALIGNED;
N_lanes_aligned <= '0';
Acounter <= (others => '0');
-- ||A||
elsif A_column_valid = '1' then
Acounter <= Acounter + '1';
-- Acounter = 4
if Acounter = "100" then
lane_alignment_state <= ALIGNED;
-- Acounter < 4
else
lane_alignment_state <= NOT_ALIGNED_2;
end if;
-- !align_error & !||A||
else
-- Do nothing: Wait for the next column
end if;
when ALIGNED =>
N_lanes_aligned <= '1';
Mcounter <= (others => '0');
-- align_error
if align_error = '1' then
Acounter <= (others => '0');
Mcounter <= Mcounter + '1';
lane_alignment_state <= ALIGNED_2;
-- !(align_error)
else
-- Do nothing extra: Wait for the next column
end if;
-- when ALIGNED_1 =>
when ALIGNED_2 =>
-- align_error
if align_error = '1' then
Acounter <= (others => '0');
Mcounter <= Mcounter + '1';
-- Mcounter = Mmax
if Mcounter = Mmax then
lane_alignment_state <= NOT_ALIGNED;
N_lanes_aligned <= '0';
-- Mcounter < Mmax
else
-- Do nothing extra: Wait for the next column
end if;
-- ||A||
elsif A_column_valid = '1' then
Acounter <= Acounter + '1';
-- Acounter = 4
if Acounter = "100" then
lane_alignment_state <= ALIGNED;
-- Acounter < 4
else
-- Do nothing extra: Wait for the next column
end if;
-- !align_error & !||A||
else
-- Do nothing: Wait for the next column
end if;
-- when ALIGNED_3 =>
when others =>
lane_alignment_state <= NOT_ALIGNED;
N_lanes_aligned <= '0';
Acounter <= (others => '0');
Mcounter <= (others => '0');
end case;
-- else
-- lane_alignment_state <= NOT_ALIGNED;
-- N_lanes_aligned <= '0';
-- Acounter <= (others => '0');
-- end if;
end if;
end process;
-- Figure 4-18. 1x/Nx_Initialization State Machine for N = 4
TXINHIBIT_02 <= not(lanes02_drvr_oe);
TXINHIBIT_others <= not(N_lanes_drvr_oe);
rcvr_trained_n <= CHBONDDONE; -- TBD
lane_ready_n <= lane_sync_n and rcvr_trained_n;
-- lane_ready_n <= lane_sync_n; -- and rcvr_trained_n;
N_lanes_ready <= '1' when N_lanes_aligned = '1' and lane_ready_n = N_lanes_all_high else '0';
-- process(UCLK)
-- begin
-- if rising_edge(UCLK) then
-- mode_sel <= Nx_mode_active;
-- mode_0_lane_sel <= receive_lane2;
-- port_initalized <= port_initalized_reg;
-- end if;
-- end process;
mode_sel <= Nx_mode_active;
mode_0_lane_sel <= receive_lane2;
port_initalized <= port_initalized_reg;
process(rst_n, UCLK)
begin
if rst_n = '0' then
mode_init_state <= SILENT;
disc_tmr_en <= '0';
lanes02_drvr_oe <= '0';
N_lanes_drvr_oe <= '0';
port_initalized_reg <= '0';
Nx_mode_active <= '0';
receive_lane2 <= '0';
force_reinit_clear <= '0';
silence_timer_en <= '0';
idle_selected <= '1';
elsif rising_edge(UCLK) then
case mode_init_state is
when SILENT =>
disc_tmr_en <= '0';
lanes02_drvr_oe <= '0';
N_lanes_drvr_oe <= '0';
port_initalized_reg <= '0';
Nx_mode_active <= '0';
receive_lane2 <= '0';
force_reinit_clear <= '1'; -- = force_reinit <= '0';
silence_timer_en <= '1';
-- force_reinit
if force_reinit_reg = '1' then
mode_init_state <= SILENT;
-- silence_timer_done
elsif silence_timer_done = '1' then
mode_init_state <= SEEK;
end if;
when SEEK =>
lanes02_drvr_oe <= '1';
silence_timer_en <= '0';
-- (lane_sync_0 | lane_sync_2) & idle_selected
if (lane_sync_n(0) = '1' or lane_sync_n(2) = '1') and idle_selected = '1' then
mode_init_state <= DISCOVERY;
end if;
when DISCOVERY =>
port_initalized_reg <= '0';
Nx_mode_active <= '0';
N_lanes_drvr_oe <= Nx_mode_enabled;
disc_tmr_en <= '1';
-- Nx_mode_enabled & N_lanes_ready
if Nx_mode_enabled = '1' and N_lanes_ready = '1' then
mode_init_state <= Nx_MODE;
-- lane_ready[0] & (force_1x_mode & (!force_laneR | force_laneR & disc_tmr_done & !lane_ready[2])
-- | !force_1x_mode & disc_tmr_done & !N_lanes_ready)
elsif lane_ready_n(0) = '1' and ((force_1x_mode = '1' and (force_laneR = '0' or (force_laneR = '1' and disc_tmr_done = '1' and lane_ready_n(2) = '0')))
or (force_1x_mode = '0' and disc_tmr_done = '1' and N_lanes_ready = '0')) then
mode_init_state <= x1_MODE_LANE0;
-- lane_ready[2] & (force_1x_mode & force_laneR | disc_tmr_done & !lane_ready[0]
-- & (force_1x_mode & !force_laneR | !force_1x_mode & !N_lanes_ready))
elsif lane_ready_n(2) = '1' and ((force_1x_mode = '1' and force_laneR = '1') or
(disc_tmr_done = '1' and lane_ready_n(0) = '0' and
((force_1x_mode = '1' and force_laneR = '0') or (force_1x_mode = '0' and N_lanes_ready = '0')))) then
mode_init_state <= x1_MODE_LANE2;
---- -- !lane_sync[0] & !lane_sync[2] | disc_tmr_done & !lane_ready[0] & !lane_ready[2]
---- elsif (lane_sync_n(0) = '0' and lane_sync_n(2) = '0') or (disc_tmr_done = '1' and lane_ready_n(0) = '0' and lane_ready_n(2) = '0') then
-- disc_tmr_done & !lane_ready[0] & !lane_ready[2]
elsif (disc_tmr_done = '1' and lane_ready_n(0) = '0' and lane_ready_n(2) = '0') then
mode_init_state <= SILENT;
end if;
when Nx_MODE =>
disc_tmr_en <= '0';
port_initalized_reg <= '1';
Nx_mode_active <= '1';
-- !N_lanes_ready & (lane_sync[0] | lane_sync[2])
if N_lanes_ready = '0' and (lane_sync_n(0) = '1' or lane_sync_n(2) = '1') then
mode_init_state <= DISCOVERY;
-- !N_lanes_ready & !lane_sync[0] & !lane_sync[2]
elsif N_lanes_ready = '0' and lane_sync_n(0) = '0' and lane_sync_n(2) = '0' then
mode_init_state <= SILENT;
end if;
when x1_MODE_LANE0 =>
disc_tmr_en <= '0';
N_lanes_drvr_oe <= '0';
port_initalized_reg <= '1';
-- !lane_sync[0]
if lane_sync_n(0) = '0' then
mode_init_state <= SILENT;
-- !lane_ready[0] & lane_sync[0]
elsif lane_ready_n(0) = '0' and lane_sync_n(0) = '1' then
mode_init_state <= x1_RECOVERY;
end if;
when x1_MODE_LANE2 =>
disc_tmr_en <= '0';
receive_lane2 <= '1';
N_lanes_drvr_oe <= '0';
port_initalized_reg <= '1';
-- !lane_sync[2]
if lane_sync_n(2) = '0' then
mode_init_state <= SILENT;
-- !lane_ready[2] & lane_sync[2]
elsif lane_ready_n(2) = '0' and lane_sync_n(2) = '1' then
mode_init_state <= x1_RECOVERY;
end if;
when x1_RECOVERY =>
port_initalized_reg <= '0';
disc_tmr_en <= '1';
-- !lane_sync[0] & !lane_sync[2] & disc_tmr_done (!!!)
if lane_sync_n(0) = '0' and lane_sync_n(2) = '0' and disc_tmr_done = '1' then
mode_init_state <= SILENT;
-- lane_ready[0] & !receive_lane2 & !disc_tmr_done
elsif lane_sync_n(0) = '1' and receive_lane2 = '0' and disc_tmr_done = '0' then
mode_init_state <= x1_MODE_LANE0;
-- lane_ready[2] & receive_lane2 & !disc_tmr_done
elsif lane_sync_n(2) = '1' and receive_lane2 = '1' and disc_tmr_done = '0' then
mode_init_state <= x1_MODE_LANE2;
end if;
when others =>
port_initalized_reg <= '0';
mode_init_state <= SILENT;
end case;
end if;
end process;
-- Sticky force_reinit set-reset register
process(rst_n, UCLK)
begin
if rst_n = '0' then
force_reinit_reg <= '0';
elsif rising_edge(UCLK) then
case force_reinit_reg is
when '0' =>
force_reinit_reg <= force_reinit or rxbuferr_reg;
when '1' =>
-- force_reinit_reg <= not(force_reinit_clear) and not(force_reinit);
force_reinit_reg <= not(force_reinit_clear and not(force_reinit) and not(rxbuferr_reg));
when others =>
force_reinit_reg <= '0';
end case;
end if;
end process;
-- RXBUFRST handler
process(rst_n, UCLK)
begin
if rst_n = '0' then
rxbufrst_cntr <= (others => '0');
rxbuferr_reg <= '0';
RXBUFRST <= '0';
elsif rising_edge(UCLK) then
case rxbuferr_reg is
when '0' =>
rxbuferr_reg <= RXBUFERR;
RXBUFRST <= '0';
when '1' =>
if rxbufrst_cntr = "111" then
rxbuferr_reg <= '0';
rxbufrst_cntr <= (others => '0');
else
RXBUFRST <= '1';
rxbufrst_cntr <= rxbufrst_cntr + '1';
end if;
when others =>
rxbuferr_reg <= '0';
end case;
end if;
end process;
-- Silence Timer Process
-- silence_timer_done: Asserted when silence_timer_en has been continuously asserted
-- for 120 +/- 40 µs and the state machine is in the SILENT state. The assertion of
-- silence_timer_done causes silence_timer_en to be de-asserted. When the state
-- machine is not in the SILENT state, silence_timer_done is de-asserted.
process(rst_n, UCLK_DV_1024)
begin
if rst_n = '0' then
silence_timer_done <= '0';
silence_timer <= (others => '0');
elsif rising_edge(UCLK_DV_1024) then
case silence_timer_en is
when '0' =>
silence_timer <= (others => '0');
silence_timer_done <= '0';
when '1' =>
if silence_timer = SILENT_ENOUGH then
if mode_init_state = SILENT then
silence_timer_done <= '1';
else
silence_timer_done <= '0';
end if;
else
silence_timer <= silence_timer + '1';
end if;
when others =>
silence_timer <= (others => '0');
end case;
end if;
end process;
-- Discovery Timer Process
-- disc_tmr_done: Asserted when disc_tmr_en has been continuously asserted for 28 +/- 4 ms
-- and the state machine is in the DISCOVERY or a RECOVERY state. The assertion of
-- disc_tmr_done causes disc_tmr_en to be de-asserted. When the state machine is in
-- a state other than the DISCOVERY or a RECOVERY state, disc_tmr_done is de-asserted.
process(rst_n, UCLK_DV_1024)
begin
if rst_n = '0' then
disc_tmr_done <= '0';
disc_tmr <= (others => '0');
elsif rising_edge(UCLK_DV_1024) then
case disc_tmr_en is
when '0' =>
disc_tmr <= (others => '0');
disc_tmr_done <= '0';
when '1' =>
if disc_tmr = DISCOVERY_ENDS then
if mode_init_state = DISCOVERY or mode_init_state = x1_RECOVERY then
disc_tmr_done <= '1';
else
disc_tmr_done <= '0';
end if;
else
disc_tmr <= disc_tmr + '1';
end if;
when others =>
disc_tmr <= (others => '0');
end case;
end if;
end process;
ENCHANSYNC <= '0';
end rtl;
-------------------------------------------------------------------------------
--
-- RapidIO IP Library Core
--
-- This file is part of the RapidIO IP library project
-- http://www.opencores.org/cores/rio/
--
-- To Do:
-- -
--
-- Author(s):
-- - A. Demirezen, [email protected]
--
-------------------------------------------------------------------------------
--
-- Copyright (C) 2013 Authors and OPENCORES.ORG
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--
------------------------------------------------------------------------------
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity pseudo_random_number_generator is
Generic (
lfsr_init : std_logic_vector(7 downto 0) := x"01"
);
Port (
clk : in STD_LOGIC;
rst_n : in STD_LOGIC;
-- Pseudo random number
q : out STD_LOGIC_VECTOR(7 downto 0)
);
end pseudo_random_number_generator;
architecture Behavioral of pseudo_random_number_generator is
signal lfsr : std_logic_vector(7 downto 0) := x"01";
signal q0 : std_logic;
begin
q <= lfsr;
-- Polynomial: x^7 + x^6 + 1
q0 <= lfsr(7) xnor lfsr(6) xnor lfsr(0) ;
process (clk, rst_n) begin
if rst_n = '0' then
lfsr <= lfsr_init; -- x"01"; --(others => '0');
elsif rising_edge(clk) then
lfsr <= lfsr(6 downto 0) & q0;
end if;
end process;
end Behavioral;
-------------------------------------------------------------------------------
--
-- RapidIO IP Library Core
--
-- This file is part of the RapidIO IP library project
-- http://www.opencores.org/cores/rio/
--
-- To Do:
-- -
--
-- Author(s):
-- - A. Demirezen, [email protected]
--
-------------------------------------------------------------------------------
--
-- Copyright (C) 2013 Authors and OPENCORES.ORG
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--
------------------------------------------------------------------------------
------------------------------------------------------------------------------
--
-- File name: serdes_wrapper_v0.vhd
-- Rev: 0.0
-- Description: This entity instantiates 4-Lane SerDes (GTX-Quad) of Virtex-6
--
------------------------------------------------------------------------------
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.rio_common.all;
entity serdes_wrapper_v0 is
port (
REFCLK : in std_logic;
RXUSRCLK : in std_logic;
RXUSRCLK2 : in std_logic;
TXUSRCLK : in std_logic;
TXUSRCLK2 : in std_logic;
GTXRESET : in std_logic;
RXBUFRST : in std_logic;
-- RXN : in std_logic_vector(N-1 downto 0);
-- RXP : in std_logic_vector(N-1 downto 0);
RXN : in std_logic_vector(0 to N-1);
RXP : in std_logic_vector(0 to N-1);
TXINHIBIT_02 : in std_logic;
TXINHIBIT_others : in std_logic;
ENCHANSYNC : in std_logic;
TXDATA : in std_logic_vector(N*16-1 downto 0);
TXCHARISK : in std_logic_vector(N*2-1 downto 0);
-- TXN : out std_logic_vector(N-1 downto 0);
-- TXP : out std_logic_vector(N-1 downto 0);
TXN : out std_logic_vector(0 to N-1);
TXP : out std_logic_vector(0 to N-1);
PLLLKDET : out std_logic;
RXDATA : out std_logic_vector(N*16-1 downto 0);
RXCHARISK : out std_logic_vector(N*2-1 downto 0);
RXCHARISCOMMA : out std_logic_vector(N*2-1 downto 0);
RXBYTEISALIGNED : out std_logic_vector(N-1 downto 0);
RXBYTEREALIGN : out std_logic_vector(N-1 downto 0);
RXELECIDLE : out std_logic_vector(N-1 downto 0);
RXDISPERR : out std_logic_vector(N*2-1 downto 0);
RXNOTINTABLE : out std_logic_vector(N*2-1 downto 0);
RXBUFERR : out std_logic;
CHBONDDONE : out std_logic_vector(N-1 downto 0)
);
end serdes_wrapper_v0;
architecture struct of serdes_wrapper_v0 is
COMPONENT srio_gt_wrapper_v6_4x
PORT(
REFCLK : IN std_logic;
RXUSRCLK : IN std_logic;
RXUSRCLK2 : IN std_logic;
TXUSRCLK : IN std_logic;
TXUSRCLK2 : IN std_logic;
GTXRESET : IN std_logic;
RXBUFRST : IN std_logic;
RXN0 : IN std_logic;
RXN1 : IN std_logic;
RXN2 : IN std_logic;
RXN3 : IN std_logic;
RXP0 : IN std_logic;
RXP1 : IN std_logic;
RXP2 : IN std_logic;
RXP3 : IN std_logic;
TXINHIBIT_02 : IN std_logic;
TXINHIBIT_13 : IN std_logic;
ENCHANSYNC : IN std_logic;
TXDATA0 : IN std_logic_vector(15 downto 0);
TXDATA1 : IN std_logic_vector(15 downto 0);
TXDATA2 : IN std_logic_vector(15 downto 0);
TXDATA3 : IN std_logic_vector(15 downto 0);
TXCHARISK0 : IN std_logic_vector(1 downto 0);
TXCHARISK1 : IN std_logic_vector(1 downto 0);
TXCHARISK2 : IN std_logic_vector(1 downto 0);
TXCHARISK3 : IN std_logic_vector(1 downto 0);
TXN0 : OUT std_logic;
TXN1 : OUT std_logic;
TXN2 : OUT std_logic;
TXN3 : OUT std_logic;
TXP0 : OUT std_logic;
TXP1 : OUT std_logic;
TXP2 : OUT std_logic;
TXP3 : OUT std_logic;
PLLLKDET : OUT std_logic;
RXDATA0 : OUT std_logic_vector(15 downto 0);
RXDATA1 : OUT std_logic_vector(15 downto 0);
RXDATA2 : OUT std_logic_vector(15 downto 0);
RXDATA3 : OUT std_logic_vector(15 downto 0);
RXCHARISK0 : OUT std_logic_vector(1 downto 0);
RXCHARISK1 : OUT std_logic_vector(1 downto 0);
RXCHARISK2 : OUT std_logic_vector(1 downto 0);
RXCHARISK3 : OUT std_logic_vector(1 downto 0);
RXCHARISCOMMA0 : OUT std_logic_vector(1 downto 0);
RXCHARISCOMMA1 : OUT std_logic_vector(1 downto 0);
RXCHARISCOMMA2 : OUT std_logic_vector(1 downto 0);
RXCHARISCOMMA3 : OUT std_logic_vector(1 downto 0);
RXBYTEISALIGNED: OUT std_logic_vector(3 downto 0);
RXBYTEREALIGN : OUT std_logic_vector(3 downto 0);
RXELECIDLE : OUT std_logic_vector(3 downto 0);
RXDISPERR0 : OUT std_logic_vector(1 downto 0);
RXDISPERR1 : OUT std_logic_vector(1 downto 0);
RXDISPERR2 : OUT std_logic_vector(1 downto 0);
RXDISPERR3 : OUT std_logic_vector(1 downto 0);
RXNOTINTABLE0 : OUT std_logic_vector(1 downto 0);
RXNOTINTABLE1 : OUT std_logic_vector(1 downto 0);
RXNOTINTABLE2 : OUT std_logic_vector(1 downto 0);
RXNOTINTABLE3 : OUT std_logic_vector(1 downto 0);
RXBUFERR : OUT std_logic;
CHBONDDONE0 : OUT std_logic;
CHBONDDONE1 : OUT std_logic;
CHBONDDONE2 : OUT std_logic;
CHBONDDONE3 : OUT std_logic
);
END COMPONENT;
begin
Inst_srio_gt_wrapper_v6_4x: srio_gt_wrapper_v6_4x PORT MAP(
REFCLK => REFCLK ,
RXUSRCLK => RXUSRCLK ,
RXUSRCLK2 => RXUSRCLK2 ,
TXUSRCLK => TXUSRCLK ,
TXUSRCLK2 => TXUSRCLK2 ,
GTXRESET => GTXRESET ,
RXBUFRST => RXBUFRST ,
RXN0 => RXN(0) ,
RXN1 => RXN(1) ,
RXN2 => RXN(2) ,
RXN3 => RXN(3) ,
RXP0 => RXP(0) ,
RXP1 => RXP(1) ,
RXP2 => RXP(2) ,
RXP3 => RXP(3) ,
TXINHIBIT_02 => TXINHIBIT_02 ,
TXINHIBIT_13 => TXINHIBIT_others ,
ENCHANSYNC => ENCHANSYNC ,
TXDATA0 => TXDATA(15 downto 0) ,
TXDATA1 => TXDATA(31 downto 16) ,
TXDATA2 => TXDATA(47 downto 32) ,
TXDATA3 => TXDATA(63 downto 48) ,
TXCHARISK0 => TXCHARISK(1 downto 0) ,
TXCHARISK1 => TXCHARISK(3 downto 2) ,
TXCHARISK2 => TXCHARISK(5 downto 4) ,
TXCHARISK3 => TXCHARISK(7 downto 6) ,
TXN0 => TXN(0) ,
TXN1 => TXN(1) ,
TXN2 => TXN(2) ,
TXN3 => TXN(3) ,
TXP0 => TXP(0) ,
TXP1 => TXP(1) ,
TXP2 => TXP(2) ,
TXP3 => TXP(3) ,
PLLLKDET => PLLLKDET ,
RXDATA0 => RXDATA(15 downto 0) ,
RXDATA1 => RXDATA(31 downto 16) ,
RXDATA2 => RXDATA(47 downto 32) ,
RXDATA3 => RXDATA(63 downto 48) ,
RXCHARISK0 => RXCHARISK(1 downto 0) ,
RXCHARISK1 => RXCHARISK(3 downto 2) ,
RXCHARISK2 => RXCHARISK(5 downto 4) ,
RXCHARISK3 => RXCHARISK(7 downto 6) ,
RXCHARISCOMMA0 => RXCHARISCOMMA(1 downto 0) ,
RXCHARISCOMMA1 => RXCHARISCOMMA(3 downto 2) ,
RXCHARISCOMMA2 => RXCHARISCOMMA(5 downto 4) ,
RXCHARISCOMMA3 => RXCHARISCOMMA(7 downto 6) ,
RXBYTEISALIGNED => RXBYTEISALIGNED ,
RXBYTEREALIGN => RXBYTEREALIGN ,
RXELECIDLE => RXELECIDLE ,
RXDISPERR0 => RXDISPERR(1 downto 0) ,
RXDISPERR1 => RXDISPERR(3 downto 2) ,
RXDISPERR2 => RXDISPERR(5 downto 4) ,
RXDISPERR3 => RXDISPERR(7 downto 6) ,
RXNOTINTABLE0 => RXNOTINTABLE(1 downto 0) ,
RXNOTINTABLE1 => RXNOTINTABLE(3 downto 2) ,
RXNOTINTABLE2 => RXNOTINTABLE(5 downto 4) ,
RXNOTINTABLE3 => RXNOTINTABLE(7 downto 6) ,
RXBUFERR => RXBUFERR ,
CHBONDDONE0 => CHBONDDONE(0) ,
CHBONDDONE1 => CHBONDDONE(1) ,
CHBONDDONE2 => CHBONDDONE(2) ,
CHBONDDONE3 => CHBONDDONE(3)
);
end struct;
-------------------------------------------------------------------------------
--
-- RapidIO IP Library Core
--
-- This file is part of the RapidIO IP library project
-- http://www.opencores.org/cores/rio/
--
-- To Do:
-- -
--
-- Author(s):
-- - A. Demirezen, [email protected]
--
-------------------------------------------------------------------------------
--
-- Copyright (C) 2013 Authors and OPENCORES.ORG
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity srio_pcs_struct is
port ( CHBONDDONE : in std_logic_vector (3 downto 0);
force_reinit_i : in std_logic;
inboundRead_i : in std_logic;
outboundSymbol_i : in std_logic_vector (33 downto 0);
outboundWrite_i : in std_logic;
PLLLKDET : in std_logic;
rio_clk : in std_logic;
rst_n : in std_logic;
RXBUFERR : in std_logic;
RXBYTEISALIGNED : in std_logic_vector (3 downto 0);
RXBYTEREALIGN : in std_logic_vector (3 downto 0);
RXCAHRISCOMMA : in std_logic_vector (7 downto 0);
RXCAHRISK : in std_logic_vector (7 downto 0);
RXDATA : in std_logic_vector (63 downto 0);
RXDISPERR : in std_logic_vector (7 downto 0);
RXELECIDLE : in std_logic_vector (3 downto 0);
RXNOTINTABLE : in std_logic_vector (7 downto 0);
UCLK : in std_logic;
UCLK_DV4 : in std_logic;
UCLK_DV1024 : in std_logic;
UCLK_or_DV4 : in std_logic;
UCLK_x2 : in std_logic;
UCLK_x2_DV2 : in std_logic;
ENCHANSYNC : out std_logic;
inboundEmpty_o : out std_logic;
inboundSymbol_o : out std_logic_vector (33 downto 0);
lane_sync_o : out std_logic_vector (3 downto 0);
mode_sel_o : out std_logic;
mode_0_lane_sel_o : out std_logic;
outboundFull_o : out std_logic;
port_initialized_o : out std_logic;
RXBUFRST : out std_logic;
TXCAHRISK : out std_logic_vector (7 downto 0);
TXDATA : out std_logic_vector (63 downto 0);
TXINHIBIT_others : out std_logic;
TXINHIBIT_02 : out std_logic);
end srio_pcs_struct;
architecture BEHAVIORAL of srio_pcs_struct is
signal ccs_timer_rst : std_logic;
signal RXCAHRISvalid : std_logic_vector (7 downto 0);
signal send_A : std_logic_vector (1 downto 0);
signal send_ccs : std_logic;
signal send_idle : std_logic_vector (1 downto 0);
signal send_K : std_logic_vector (1 downto 0);
signal send_R : std_logic_vector (1 downto 0);
signal mode_0_lane_sel_o_DUMMY : std_logic;
signal TXINHIBIT_02_DUMMY : std_logic;
signal mode_sel_o_DUMMY : std_logic;
signal port_initialized_o_DUMMY : std_logic;
signal TXINHIBIT_others_DUMMY : std_logic;
component ccs_timer
port ( rst_n : in std_logic;
ccs_timer_rst : in std_logic;
send_ccs : out std_logic;
UCLK : in std_logic);
end component;
component idle_generator_dual
port ( UCLK : in std_logic;
rst_n : in std_logic;
send_K : out std_logic_vector (1 downto 0);
send_A : out std_logic_vector (1 downto 0);
send_R : out std_logic_vector (1 downto 0);
send_idle : in std_logic_vector (1 downto 0));
end component;
component port_init_fsms
port ( rst_n : in std_logic;
UCLK_x2 : in std_logic;
UCLK : in std_logic;
UCLK_DV4 : in std_logic;
UCLK_DV_1024 : in std_logic;
force_reinit : in std_logic;
PLLLKDET : in std_logic;
RXBUFERR : in std_logic;
RXDATA : in std_logic_vector (63 downto 0);
RXCHARISK : in std_logic_vector (7 downto 0);
RXCHARISCOMMA : in std_logic_vector (7 downto 0);
RXBYTEISALIGNED : in std_logic_vector (3 downto 0);
RXBYTEREALIGN : in std_logic_vector (3 downto 0);
RXELECIDLE : in std_logic_vector (3 downto 0);
RXDISPERR : in std_logic_vector (7 downto 0);
RXNOTINTABLE : in std_logic_vector (7 downto 0);
CHBONDDONE : in std_logic_vector (3 downto 0);
mode_sel : out std_logic;
port_initalized : out std_logic;
TXINHIBIT_02 : out std_logic;
TXINHIBIT_others : out std_logic;
ENCHANSYNC : out std_logic;
RXBUFRST : out std_logic;
lane_sync : out std_logic_vector (3 downto 0);
mode_0_lane_sel : out std_logic;
RXCHARISvalid : out std_logic_vector (7 downto 0));
end component;
component pcs_rx_controller
port ( rst_n : in std_logic;
rio_clk : in std_logic;
UCLK_x2 : in std_logic;
UCLK : in std_logic;
UCLK_x2_DV2 : in std_logic;
inboundRead_i : in std_logic;
port_initalized_i : in std_logic;
mode_sel_i : in std_logic;
mode_0_lane_sel_i : in std_logic;
RXDATA_i : in std_logic_vector (63 downto 0);
RXCHARISK_i : in std_logic_vector (7 downto 0);
RXCHARISvalid_i : in std_logic_vector (7 downto 0);
inboundEmpty_o : out std_logic;
inboundSymbol_o : out std_logic_vector (33 downto 0);
UCLK_or_DV4 : in std_logic);
end component;
component pcs_tx_controller
port ( rst_n : in std_logic;
rio_clk : in std_logic;
UCLK_x2 : in std_logic;
UCLK : in std_logic;
UCLK_x2_DV2 : in std_logic;
UCLK_or_DV4 : in std_logic;
outboundWrite_i : in std_logic;
send_ccs_i : in std_logic;
TXINHIBIT_02 : in std_logic;
TXINHIBIT_others : in std_logic;
port_initalized_i : in std_logic;
mode_sel_i : in std_logic;
mode_0_lane_sel_i : in std_logic;
outboundSymbol_i : in std_logic_vector (33 downto 0);
send_K_i : in std_logic_vector (1 downto 0);
send_A_i : in std_logic_vector (1 downto 0);
send_R_i : in std_logic_vector (1 downto 0);
outboundFull_o : out std_logic;
ccs_timer_rst_o : out std_logic;
TXDATA_o : out std_logic_vector (63 downto 0);
TXCHARISK_o : out std_logic_vector (7 downto 0);
send_idle_o : out std_logic_vector (1 downto 0));
end component;
begin
mode_sel_o <= mode_sel_o_DUMMY;
mode_0_lane_sel_o <= mode_0_lane_sel_o_DUMMY;
port_initialized_o <= port_initialized_o_DUMMY;
TXINHIBIT_others <= TXINHIBIT_others_DUMMY;
TXINHIBIT_02 <= TXINHIBIT_02_DUMMY;
ccs_timer_inst : ccs_timer
port map (ccs_timer_rst=>ccs_timer_rst,
rst_n=>rst_n,
UCLK=>UCLK,
send_ccs=>send_ccs);
dual_idle_generator : idle_generator_dual
port map (rst_n=>rst_n,
send_idle(1 downto 0)=>send_idle(1 downto 0),
UCLK=>UCLK,
send_A(1 downto 0)=>send_A(1 downto 0),
send_K(1 downto 0)=>send_K(1 downto 0),
send_R(1 downto 0)=>send_R(1 downto 0));
port_init_fsms_inst : port_init_fsms
port map (CHBONDDONE(3 downto 0)=>CHBONDDONE(3 downto 0),
force_reinit=>force_reinit_i,
PLLLKDET=>PLLLKDET,
rst_n=>rst_n,
RXBUFERR=>RXBUFERR,
RXBYTEISALIGNED(3 downto 0)=>RXBYTEISALIGNED(3 downto 0),
RXBYTEREALIGN(3 downto 0)=>RXBYTEREALIGN(3 downto 0),
RXCHARISCOMMA(7 downto 0)=>RXCAHRISCOMMA(7 downto 0),
RXCHARISK(7 downto 0)=>RXCAHRISK(7 downto 0),
RXDATA(63 downto 0)=>RXDATA(63 downto 0),
RXDISPERR(7 downto 0)=>RXDISPERR(7 downto 0),
RXELECIDLE(3 downto 0)=>RXELECIDLE(3 downto 0),
RXNOTINTABLE(7 downto 0)=>RXNOTINTABLE(7 downto 0),
UCLK=>UCLK,
UCLK_DV_1024=>UCLK_DV1024,
UCLK_DV4=>UCLK_DV4,
UCLK_x2=>UCLK_x2,
ENCHANSYNC=>ENCHANSYNC,
lane_sync(3 downto 0)=>lane_sync_o(3 downto 0),
mode_sel=>mode_sel_o_DUMMY,
mode_0_lane_sel=>mode_0_lane_sel_o_DUMMY,
port_initalized=>port_initialized_o_DUMMY,
RXBUFRST=>RXBUFRST,
RXCHARISvalid(7 downto 0)=>RXCAHRISvalid(7 downto 0),
TXINHIBIT_others=>TXINHIBIT_others_DUMMY,
TXINHIBIT_02=>TXINHIBIT_02_DUMMY);
rx_controller_inst : pcs_rx_controller
port map (inboundRead_i=>inboundRead_i,
mode_sel_i=>mode_sel_o_DUMMY,
mode_0_lane_sel_i=>mode_0_lane_sel_o_DUMMY,
port_initalized_i=>port_initialized_o_DUMMY,
rio_clk=>rio_clk,
rst_n=>rst_n,
RXCHARISK_i(7 downto 0)=>RXCAHRISK(7 downto 0),
RXCHARISvalid_i(7 downto 0)=>RXCAHRISvalid(7 downto 0),
RXDATA_i(63 downto 0)=>RXDATA(63 downto 0),
UCLK=>UCLK,
UCLK_or_DV4=>UCLK_or_DV4,
UCLK_x2=>UCLK_x2,
UCLK_x2_DV2=>UCLK_x2_DV2,
inboundEmpty_o=>inboundEmpty_o,
inboundSymbol_o(33 downto 0)=>inboundSymbol_o(33 downto 0));
tx_controller_inst : pcs_tx_controller
port map (mode_sel_i=>mode_sel_o_DUMMY,
mode_0_lane_sel_i=>mode_0_lane_sel_o_DUMMY,
outboundSymbol_i(33 downto 0)=>outboundSymbol_i(33 downto 0),
outboundWrite_i=>outboundWrite_i,
port_initalized_i=>port_initialized_o_DUMMY,
rio_clk=>rio_clk,
rst_n=>rst_n,
send_A_i(1 downto 0)=>send_A(1 downto 0),
send_ccs_i=>send_ccs,
send_K_i(1 downto 0)=>send_K(1 downto 0),
send_R_i(1 downto 0)=>send_R(1 downto 0),
TXINHIBIT_others=>TXINHIBIT_others_DUMMY,
TXINHIBIT_02=>TXINHIBIT_02_DUMMY,
UCLK=>UCLK,
UCLK_or_DV4=>UCLK_or_DV4,
UCLK_x2=>UCLK_x2,
UCLK_x2_DV2=>UCLK_x2_DV2,
ccs_timer_rst_o=>ccs_timer_rst,
outboundFull_o=>outboundFull_o,
send_idle_o(1 downto 0)=>send_idle(1 downto 0),
TXCHARISK_o(7 downto 0)=>TXCAHRISK(7 downto 0),
TXDATA_o(63 downto 0)=>TXDATA(63 downto 0));
end BEHAVIORAL;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:40:43 05/22/2013
-- Design Name:
-- Module Name: JK - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity JK is
Port ( JK : in STD_LOGIC_VECTOR (1 downto 0);
Q : inout STD_LOGIC;
Qn : inout STD_LOGIC;
clk : in STD_LOGIC);
end JK;
architecture Behavioral of JK is
begin
process(clk)
begin
if(clk'event and clk='1') then
case JK is
when "00" => null;
when "10" => Q <= '1' ; qn <= '0';
when "01" => q <= '0' ; Qn <= '1';
when "11" => Q <= not q ; Qn <= not Qn;
when others => null;
end case;
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- Testbench for the T410 system toplevel.
--
-- $Id: tb_t410.vhd,v 1.1 2006-06-11 22:19:32 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
entity tb_t410 is
end tb_t410;
library ieee;
use ieee.std_logic_1164.all;
use work.t400_system_comp_pack.t410;
use work.tb_pack.tb_elems;
use work.t400_opt_pack.all;
architecture behav of tb_t410 is
-- 210.4 kHz clock
constant period_c : time := 4.75 us;
signal ck_s : std_logic;
signal reset_n_s : std_logic;
signal io_l_s : std_logic_vector(7 downto 0);
signal io_d_s : std_logic_vector(3 downto 0);
signal io_g_s : std_logic_vector(3 downto 0);
signal si_s,
so_s,
sk_s : std_logic;
signal vdd_s : std_logic;
begin
vdd_s <= '1';
reset_n_s <= '1';
-----------------------------------------------------------------------------
-- DUT
-----------------------------------------------------------------------------
t410_b : t410
generic map (
opt_ck_div_g => t400_opt_ck_div_8_c
)
port map (
ck_i => ck_s,
ck_en_i => vdd_s,
reset_n_i => reset_n_s,
si_i => si_s,
so_o => so_s,
sk_o => sk_s,
io_l_b => io_l_s,
io_d_o => io_d_s,
io_g_b => io_g_s
);
io_l_s <= (others => 'H');
io_d_s <= (others => 'H');
io_g_s <= (others => 'H');
-----------------------------------------------------------------------------
-- Testbench elements
-----------------------------------------------------------------------------
tb_elems_b : tb_elems
generic map (
period_g => period_c,
d_width_g => 4,
g_width_g => 4
)
port map (
io_l_i => io_l_s,
io_d_i => io_d_s,
io_g_i => io_g_s,
io_in_o => open,
so_i => so_s,
si_o => si_s,
sk_i => sk_s,
ck_o => ck_s
);
end behav;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-- Revision 1.6 2006/06/05 18:50:45 arniml
-- remove obsolete en_clk_s
--
-- Revision 1.5 2006/05/27 19:10:12 arniml
-- explicitly select clock divider 8
--
-- Revision 1.4 2006/05/23 01:18:26 arniml
-- consider IN port
--
-- Revision 1.3 2006/05/15 21:56:02 arniml
-- moved elements to separate design unit tb_elems
--
-- Revision 1.2 2006/05/06 13:34:25 arniml
-- remove delta cycle filter on sk_s
--
-- Revision 1.1.1.1 2006/05/06 01:56:44 arniml
-- import from local CVS repository, LOC_CVS_0_1
--
-------------------------------------------------------------------------------
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_eb_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:29 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_eb_e-rtl-a.vhd,v 1.1 2004/04/06 10:50:24 wig Exp $
-- $Date: 2004/04/06 10:50:24 $
-- $Log: inst_eb_e-rtl-a.vhd,v $
-- Revision 1.1 2004/04/06 10:50:24 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Revision: 1.26 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_eb_e
--
architecture rtl of inst_eb_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component inst_eba_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_eba_e
mbist_aci_fail_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
mbist_vcd_fail_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
reset_n : in std_ulogic;
reset_n_s : in std_ulogic;
vclkl27 : in std_ulogic
-- End of Generated Port for Entity inst_eba_e
);
end component;
-- ---------
component inst_ebb_e --
-- No Generated Generics
port (
-- Generated Port for Entity inst_ebb_e
mbist_sum_fail_o : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
req_select_o : out std_ulogic_vector(5 downto 0);
reset_n : in std_ulogic;
reset_n_s : in std_ulogic;
vclkl27 : in std_ulogic
-- End of Generated Port for Entity inst_ebb_e
);
end component;
-- ---------
component inst_ebc_e --
-- No Generated Generics
-- Generated Generics for Entity inst_ebc_e
-- End of Generated Generics for Entity inst_ebc_e
port (
-- Generated Port for Entity inst_ebc_e
nreset : in std_ulogic;
nreset_s : in std_ulogic
-- End of Generated Port for Entity inst_ebc_e
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal nreset : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal nreset_s : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal tmi_sbist_fail : std_ulogic_vector(12 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal v_select : std_ulogic_vector(5 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
nreset <= p_mix_nreset_gi; -- __I_I_BIT_PORT
nreset_s <= p_mix_nreset_s_gi; -- __I_I_BIT_PORT
p_mix_tmi_sbist_fail_12_10_go(2 downto 0) <= tmi_sbist_fail(12 downto 10); -- __I_O_SLICE_PORT
p_mix_v_select_5_0_go <= v_select; -- __I_O_BUS_PORT
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for inst_eba
inst_eba: inst_eba_e
port map (
mbist_aci_fail_o => tmi_sbist_fail(10),
mbist_vcd_fail_o => tmi_sbist_fail(11),
reset_n => nreset, -- GlobalRESET(Verilogmacro)
reset_n_s => nreset_s, -- GlobalRESET(Verilogmacro)
vclkl27 => vclkl27 -- ClockSignalsClocksforMacrosglobalsignaldefinitonsclock,reset&powerdown
);
-- End of Generated Instance Port Map for inst_eba
-- Generated Instance Port Map for inst_ebb
inst_ebb: inst_ebb_e
port map (
mbist_sum_fail_o => tmi_sbist_fail(12),
req_select_o => v_select, -- VPUinterfaceRequestBusinterface:RequestBus#6(VPU)requestbusinterfaceforcgpandcgclientserver
reset_n => nreset, -- GlobalRESET(Verilogmacro)
reset_n_s => nreset_s, -- GlobalRESET(Verilogmacro)
vclkl27 => vclkl27 -- ClockSignalsClocksforMacrosglobalsignaldefinitonsclock,reset&powerdown
);
-- End of Generated Instance Port Map for inst_ebb
-- Generated Instance Port Map for inst_ebc
inst_ebc: inst_ebc_e
port map (
nreset => nreset, -- GlobalRESET(Verilogmacro)
nreset_s => nreset_s -- GlobalRESET(Verilogmacro)
);
-- End of Generated Instance Port Map for inst_ebc
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 63088)
`protect data_block
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`protect end_protected
|
library ieee;
use ieee.std_logic_1164.all;
entity pwm_tb is
end pwm_tb;
architecture behavior of pwm_tb is
use work.pwm_pkg.all;
signal clk : std_logic := '0';
signal clk_en : std_logic := '1';
signal reset : std_logic := '1';
signal value : std_logic_vector(11 downto 0) := (others => '0');
signal output : std_logic;
begin
clk <= not clk after 10 ns; -- 50 Mhz clock
reset <= '1', '0' after 50 ns; -- erzeugt Resetsignal: --__
tb : process
begin
value <= x"7FF";
wait for 200 us;
value <= x"001";
wait for 200 us;
value <= x"FFE";
wait for 200 us;
value <= x"000";
wait for 200 us;
value <= x"FFF";
wait for 200 us;
end process;
uut : pwm
generic map (width => 12)
port map(
clk => clk,
clk_en_p => clk_en,
reset => reset,
value_p => value,
output_p => output);
end;
|
library ieee;
use ieee.std_logic_1164.all;
entity pwm_tb is
end pwm_tb;
architecture behavior of pwm_tb is
use work.pwm_pkg.all;
signal clk : std_logic := '0';
signal clk_en : std_logic := '1';
signal reset : std_logic := '1';
signal value : std_logic_vector(11 downto 0) := (others => '0');
signal output : std_logic;
begin
clk <= not clk after 10 ns; -- 50 Mhz clock
reset <= '1', '0' after 50 ns; -- erzeugt Resetsignal: --__
tb : process
begin
value <= x"7FF";
wait for 200 us;
value <= x"001";
wait for 200 us;
value <= x"FFE";
wait for 200 us;
value <= x"000";
wait for 200 us;
value <= x"FFF";
wait for 200 us;
end process;
uut : pwm
generic map (width => 12)
port map(
clk => clk,
clk_en_p => clk_en,
reset => reset,
value_p => value,
output_p => output);
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1727.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s06b01x00p04n03i01727ent IS
END c12s06b01x00p04n03i01727ent;
ARCHITECTURE c12s06b01x00p04n03i01727arch OF c12s06b01x00p04n03i01727ent IS
signal B : BIT := '1';
BEGIN
TESTING: PROCESS
variable ShouldBeTime : TIME;
BEGIN
B <= '1','0' after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on B;
assert NOT(( NOW = ShouldBeTime ) and ( B = '0' ))
report "***PASSED TEST: c12s06b01x00p04n03i01727"
severity NOTE;
assert (( NOW = ShouldBeTime ) and ( B = '0' ))
report "***FAILED TEST: c12s06b01x00p04n03i01727 - As time passes, the current transaction is deleted from the projected output waveform of that driver and the new tra nsaction takes its place."
severity ERROR;
wait;
END PROCESS TESTING;
END c12s06b01x00p04n03i01727arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1727.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s06b01x00p04n03i01727ent IS
END c12s06b01x00p04n03i01727ent;
ARCHITECTURE c12s06b01x00p04n03i01727arch OF c12s06b01x00p04n03i01727ent IS
signal B : BIT := '1';
BEGIN
TESTING: PROCESS
variable ShouldBeTime : TIME;
BEGIN
B <= '1','0' after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on B;
assert NOT(( NOW = ShouldBeTime ) and ( B = '0' ))
report "***PASSED TEST: c12s06b01x00p04n03i01727"
severity NOTE;
assert (( NOW = ShouldBeTime ) and ( B = '0' ))
report "***FAILED TEST: c12s06b01x00p04n03i01727 - As time passes, the current transaction is deleted from the projected output waveform of that driver and the new tra nsaction takes its place."
severity ERROR;
wait;
END PROCESS TESTING;
END c12s06b01x00p04n03i01727arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1727.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s06b01x00p04n03i01727ent IS
END c12s06b01x00p04n03i01727ent;
ARCHITECTURE c12s06b01x00p04n03i01727arch OF c12s06b01x00p04n03i01727ent IS
signal B : BIT := '1';
BEGIN
TESTING: PROCESS
variable ShouldBeTime : TIME;
BEGIN
B <= '1','0' after 10 ns;
ShouldBeTime := NOW + 10 ns;
wait on B;
assert NOT(( NOW = ShouldBeTime ) and ( B = '0' ))
report "***PASSED TEST: c12s06b01x00p04n03i01727"
severity NOTE;
assert (( NOW = ShouldBeTime ) and ( B = '0' ))
report "***FAILED TEST: c12s06b01x00p04n03i01727 - As time passes, the current transaction is deleted from the projected output waveform of that driver and the new tra nsaction takes its place."
severity ERROR;
wait;
END PROCESS TESTING;
END c12s06b01x00p04n03i01727arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1435.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s07b00x00p02n01i01435ent IS
END c08s07b00x00p02n01i01435ent;
ARCHITECTURE c08s07b00x00p02n01i01435arch OF c08s07b00x00p02n01i01435ent IS
begin
TEST_PROCESS: process
variable I : INTEGER := 47;
begin
-- Missing 'then' on 'elsif'.
if (I /= 47) then
NULL;
elsif (I = 47)
NULL;
end if;
assert FALSE
report "***FAILED TEST: c08s07b00x00p02n01i01435 - reserved word 'then' after 'elsif' is missing"
severity ERROR;
wait;
end process TEST_PROCESS;
END c08s07b00x00p02n01i01435arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1435.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s07b00x00p02n01i01435ent IS
END c08s07b00x00p02n01i01435ent;
ARCHITECTURE c08s07b00x00p02n01i01435arch OF c08s07b00x00p02n01i01435ent IS
begin
TEST_PROCESS: process
variable I : INTEGER := 47;
begin
-- Missing 'then' on 'elsif'.
if (I /= 47) then
NULL;
elsif (I = 47)
NULL;
end if;
assert FALSE
report "***FAILED TEST: c08s07b00x00p02n01i01435 - reserved word 'then' after 'elsif' is missing"
severity ERROR;
wait;
end process TEST_PROCESS;
END c08s07b00x00p02n01i01435arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1435.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s07b00x00p02n01i01435ent IS
END c08s07b00x00p02n01i01435ent;
ARCHITECTURE c08s07b00x00p02n01i01435arch OF c08s07b00x00p02n01i01435ent IS
begin
TEST_PROCESS: process
variable I : INTEGER := 47;
begin
-- Missing 'then' on 'elsif'.
if (I /= 47) then
NULL;
elsif (I = 47)
NULL;
end if;
assert FALSE
report "***FAILED TEST: c08s07b00x00p02n01i01435 - reserved word 'then' after 'elsif' is missing"
severity ERROR;
wait;
end process TEST_PROCESS;
END c08s07b00x00p02n01i01435arch;
|
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