content
stringlengths 1
1.04M
⌀ |
|---|
--
-- ADC for ZPUINO
--
--
--
-- Version: 1.0
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use IEEE.std_logic_unsigned.all;
library work;
use work.zpu_config.all;
use work.zpupkg.all;
use work.zpuinopkg.all;
use work.zpuino_config.all;
entity zpuino_ov7670 is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_adr_i: in std_logic_vector(maxIObit downto minIObit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_ack_o: out std_logic;
wb_inta_o:out std_logic;
CLK50 : in STD_LOGIC;
OV7670_VSYNC : in STD_LOGIC;
OV7670_HREF : in STD_LOGIC;
OV7670_PCLK : in STD_LOGIC;
OV7670_XCLK : out STD_LOGIC;
OV7670_D : in STD_LOGIC_VECTOR(7 downto 0)
);
end entity zpuino_ov7670;
architecture behave of zpuino_ov7670 is
COMPONENT ov7670_capture
PORT(
pclk : IN std_logic;
vsync : IN std_logic;
href : IN std_logic;
d : IN std_logic_vector(7 downto 0);
addr : OUT std_logic_vector(18 downto 0);
dout : OUT std_logic_vector(15 downto 0);
we : OUT std_logic
);
END COMPONENT;
COMPONENT frame_buffer
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(14 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;
signal capture_addr : std_logic_vector(18 downto 0);
signal capture_data : std_logic_vector(15 downto 0);
signal capture_we : std_logic_vector(0 downto 0);
signal frame_addr : std_logic_vector(18 downto 0);
signal frame_pixel : std_logic_vector(15 downto 0);
signal ov7670_sys_clk : std_logic := '0';
begin
wb_ack_o <= wb_cyc_i and wb_stb_i;
wb_inta_o <= '0';
process(CLK50)
begin
if rising_edge(CLK50) then
ov7670_sys_clk <= not ov7670_sys_clk;
end if;
end process;
OV7670_XCLK <= ov7670_sys_clk;
-- Read
--
process(wb_adr_i)
begin
case wb_adr_i(5 downto 2) is
when X"0" =>
wb_dat_o <= (others=>'0');
wb_dat_o( 15 downto 0 ) <= frame_pixel;
when X"1" =>
when others =>
wb_dat_o <= (others => DontCareValue);
end case;
end process;
-- Write
--
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
elsif wb_stb_i='1' and wb_cyc_i='1' and wb_we_i='1' then
case wb_adr_i(5 downto 2) is
when X"0" =>
frame_addr <= wb_dat_i( 18 downto 0 );
when X"1" =>
when others =>
end case;
end if;
end if;
end process;
capture: ov7670_capture
PORT MAP(
pclk => OV7670_PCLK,
vsync => OV7670_VSYNC,
href => OV7670_HREF,
d => OV7670_D,
addr => capture_addr,
dout => capture_data,
we => capture_we(0)
);
fb : frame_buffer
PORT MAP (
clka => OV7670_PCLK,
wea => capture_we,
addra => capture_addr( 14 downto 0 ),
dina => capture_data,
clkb => wb_clk_i,
addrb => frame_addr( 14 downto 0 ),
doutb => frame_pixel
);
end behave;
|
-------------------------------------------------------------------------------
-- Copyright (c) 2013 Xilinx, Inc.
-- All Rights Reserved
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 13.4
-- \ \ Application: XILINX CORE Generator
-- / / Filename : chipscope_icon_2_port.vhd
-- /___/ /\ Timestamp : Wed Dec 18 09:37:02 BRST 2013
-- \ \ / \
-- \___\/\___\
--
-- Design Name: VHDL Synthesis Wrapper
-------------------------------------------------------------------------------
-- This wrapper is used to integrate with Project Navigator and PlanAhead
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY chipscope_icon_2_port IS
port (
CONTROL0: inout std_logic_vector(35 downto 0);
CONTROL1: inout std_logic_vector(35 downto 0));
END chipscope_icon_2_port;
ARCHITECTURE chipscope_icon_2_port_a OF chipscope_icon_2_port IS
BEGIN
END chipscope_icon_2_port_a;
|
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 07/13/2014
--! Module Name: EPROC_FIFO_DRIVER
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.all;
use work.centralRouter_package.all;
--! a driver for EPROC FIFO, manages block header and sub-chunk trailer
entity EPROC_FIFO_DRIVER is
generic (
GBTid : integer := 0;
egroupID : integer := 0;
epathID : integer := 0;
toHostTimeoutBitn : integer := 8
);
port (
clk40 : in std_logic;
clk160 : in std_logic;
rst : in std_logic;
----------
encoding : in std_logic_vector (1 downto 0);
maxCLEN : in std_logic_vector (2 downto 0);
---------
DIN : in std_logic_vector (9 downto 0);
DIN_RDY : in std_logic;
----------
xoff : in std_logic;
timeCntIn : in std_logic_vector ((toHostTimeoutBitn-1) downto 0);
TimeoutEnaIn: in std_logic;
----------
wordOUT : out std_logic_vector (15 downto 0);
wordOUT_RDY : out std_logic
);
end EPROC_FIFO_DRIVER;
architecture Behavioral of EPROC_FIFO_DRIVER is
--
signal DIN_r : std_logic_vector (7 downto 0) := (others => '0');
signal DIN_CODE_r : std_logic_vector (1 downto 0) := (others => '0');
signal DIN_s : std_logic_vector (9 downto 0);
signal DIN_RDY_r : std_logic := '0';
---
signal receiving_state, data_shift_trig, trailer_shift_trig, trailer_shift_trig_s,
EOC_error, SOC_error, rst_clen_counter, data16bit_rdy,
data16bit_rdy_shifted, truncating_state, truncation_trailer_sent : std_logic := '0';
signal send_trailer_trig,data_shift_trig_s : std_logic;
signal DIN_prev_is_zeroByte, DIN_is_zeroByte : std_logic := '0';
signal direct_data_mode, direct_data_boundary_detected : std_logic;
signal trailer_trunc_bit, trailer_cerr_bit, first_subchunk, first_subchunk_on : std_logic := '0';
signal trailer_mod_bits : std_logic_vector (1 downto 0);
signal trailer_type_bits : std_logic_vector (2 downto 0) := (others => '0');
signal EOB_MARK, truncateDataFlag, flushed, flush_trig, data_rdy : std_logic;
signal trailer_shift_trigs, trailer_shift_trig0, header_shift_trigs : std_logic;
signal trailer_shift_trig1 : std_logic := '0';
signal data16bit_rdy_code : std_logic_vector (2 downto 0);
signal trailer, trailer0, trailer1, header, data : std_logic_vector (15 downto 0);
signal wordOUT_s : std_logic_vector (15 downto 0) := (others => '0');
signal pathENA, DIN_RDY_s : std_logic := '0';
signal pathENAtrig, blockCountRdy,timeout_trailer_send,xoff_s : std_logic;
--
signal timeCnt_lastClk : std_logic_vector ((toHostTimeoutBitn-1) downto 0);
signal do_transmit_timeout_trailers,timout_ena,truncation_from_timeout,truncating_state_clk40 : std_logic := '0';
signal zero_trailer_send_pulse_count : std_logic_vector (2 downto 0) := (others=>'0');
signal zero_trailer_send_pulse,truncation_from_timeout_trig,timeout_event_clk0,timeout_event_clk1,data_on_input,data_on_input_clk40 : std_logic;
--
constant zero_data_trailer : std_logic_vector(15 downto 0) := "0000000000000000"; -- "000"=null chunk, "00"=no truncation & no cerr, '0', 10 bit length is zero;
constant timeout_trailer : std_logic_vector(15 downto 0) := "1010000000000000"; -- "101"=timeout, "00"=no truncation & no cerr, '0', 10 bit length is zero;
signal work_state,sop_in : std_logic := '0';
--
begin
------------------------------------------------------------
-- time out counter for triggering the send-out of an
-- incomplete block
------------------------------------------------------------
--data_on_input <= '1' when (DIN_RDY = '1' and DIN(9 downto 8) /= "11" and truncating_state_clk40 = '0') else '0';
--
process(clk160,rst)
begin
if rst = '1' then
data_on_input <= '0';
elsif rising_edge (clk160) then
if DIN_RDY = '1' then
if DIN(9 downto 8) /= "11" then -- data
data_on_input <= not truncating_state_clk40;
if DIN(9 downto 8) = "10" then -- sop
sop_in <= '1';
else
sop_in <= '0';
end if;
else
data_on_input <= '0';
sop_in <= '0';
end if;
else
data_on_input <= '0';
end if;
end if;
end process;
--
tcdc: entity work.pulse_pdxx_pwxx generic map(pd=>0,pw=>5) port map(clk160, data_on_input, data_on_input_clk40);
--
process(clk40,rst)
begin
if rst = '1' then
timeCnt_lastClk <= (others=>'1');
truncating_state_clk40 <= '0';
work_state <= '0';
elsif rising_edge (clk40) then
if TimeoutEnaIn = '0' then
timeCnt_lastClk <= (others=>'1');
truncating_state_clk40 <= '0';
work_state <= '0';
else
truncating_state_clk40 <= truncating_state; -- cdc
--
if timeCntIn(0) = '1' then
work_state <= TimeoutEnaIn;
end if;
--
if (data_on_input_clk40 = '1' or timout_ena = '0') and work_state = '1' then
timeCnt_lastClk <= timeCntIn; -- [valid data] or [disabled timeout] re-set counter cycle start point
end if;
end if;
end if;
end process;
--
--
process(clk40,rst)
begin
if rst = '1' then
timeout_event_clk0 <= '0';
elsif rising_edge (clk40) then --
if timeCnt_lastClk = timeCntIn then
timeout_event_clk0 <= TimeoutEnaIn;
else
timeout_event_clk0 <= '0';
end if;
--
timeout_event_clk1 <= timeout_event_clk0 and (not sop_in);
--
end if;
end process;
--
--t0: entity work.pulse_pdxx_pwxx generic map(pd=>1,pw=>1) port map(clk40, timeout_event_clk0, timeout_event_clk1);
--
truncation_from_timeout <= timeout_event_clk0 and (not sop_in);
p0: entity work.pulse_pdxx_pwxx generic map(pd=>0,pw=>1) port map(clk160, truncation_from_timeout, truncation_from_timeout_trig);
--
--
process(clk160,rst)
begin
if rst = '1' then
do_transmit_timeout_trailers <= '0';
elsif rising_edge (clk160) then
if timeout_event_clk1 = '1' then --timeCnt_lastClk = timeCntIn and timout_ena = '1' and TimeoutEnaIn = '1' then
do_transmit_timeout_trailers <= TimeoutEnaIn;
elsif (data_on_input = '1' or EOB_MARK = '1') then
do_transmit_timeout_trailers <= '0';
end if;
end if;
end process;
--
--
p1: entity work.pulse_pdxx_pwxx generic map(pd=>0,pw=>1) port map(clk160, do_transmit_timeout_trailers, timeout_trailer_send);
xoff_s <= xoff or truncation_from_timeout;
--
process(clk160,rst)
begin
if rst = '1' then
timout_ena <= '0';
elsif rising_edge (clk160) then
if do_transmit_timeout_trailers = '1' then
timout_ena <= '0';
elsif receiving_state = '1' then
timout_ena <= '1';
end if;
end if;
end process;
--
---------------------------------------------
-- CLK1: register the input
---------------------------------------------
process(clk160)
begin
if rising_edge (clk160) then
if DIN_RDY = '1' then
DIN_s <= DIN;
DIN_RDY_s <= '1';
else
DIN_RDY_s <= '0';
end if;
end if;
end process;
-- for the direct data case:
-- register the input byte comparator result
-- for the direct data case to detect zeros as data delimeter
direct_data_mode <= not(encoding(1) or encoding(0));
--
process(clk160)
begin
if rising_edge (clk160) then
if DIN_RDY = '1' then
if DIN(7 downto 0) = "00000000" then
DIN_is_zeroByte <= '1';
else
DIN_is_zeroByte <= '0';
end if;
end if;
end if;
end process;
-- pipeline the input byte comparator result
process(clk160)
begin
if rising_edge (clk160) then
if DIN_RDY = '1' then
DIN_prev_is_zeroByte <= DIN_is_zeroByte;
end if;
end if;
end process;
--
direct_data_boundary_detected <= '1' when (DIN_is_zeroByte = '1' and DIN_prev_is_zeroByte = '1') else '0';
--
---------------------------------------------
-- initial enabling of the path:
-- enabled after reset on the first
-- valid input symbol (must be comma!)
-- the first symbol is then lost! as we are sending
-- a bloack header when it is detected
---------------------------------------------
process(clk160)
begin
if rising_edge (clk160) then
if rst = '1' then
pathENA <= '0';
elsif DIN_RDY_s = '1' then --
pathENA <= '1';
end if;
end if;
end process;
-- trigger to restart the block counter
pathENA1clk: entity work.pulse_pdxx_pwxx GENERIC MAP(pd=>0,pw=>1) PORT MAP(clk160, pathENA, pathENAtrig);
---------------------------------------------
-- CLK2:
---------------------------------------------
--
DIN_RDY_r <= (DIN_RDY_s and (not truncateDataFlag)) or truncation_from_timeout_trig; --and pathENA; --blockCountRdy;
DIN_r <= DIN_s(7 downto 0);
--
process(direct_data_mode, direct_data_boundary_detected, DIN_s(9 downto 8), truncateDataFlag)
begin
if direct_data_mode = '1' then
DIN_CODE_r <= direct_data_boundary_detected & '0'; -- "10"=soc, "00"=data
else
if truncateDataFlag = '0' then
DIN_CODE_r <= DIN_s(9 downto 8);
else
DIN_CODE_r <= "00";
end if;
end if;
end process;
--
-----------------------------------------------------------
-- clock 3
-- case of the input word code:
-- "00" => data, "01" => EOC, "10" => SOC, "11" => COMMA
-----------------------------------------------------------
process(clk160, rst)
begin
if rst = '1' then
--
receiving_state <= '0';
trailer_trunc_bit <= '1';
trailer_cerr_bit <= '1';
trailer_type_bits <= "000"; -- not a legal code
data_shift_trig <= '0';
trailer_shift_trig <= '0';
EOC_error <= '0';
SOC_error <= '0';
rst_clen_counter <= '0';
first_subchunk_on <= '0';
truncating_state <= '0';
--
elsif rising_edge (clk160) then
if DIN_RDY_r = '1' then
case (DIN_CODE_r) is
when "00" => -- data
--
data_shift_trig <= (receiving_state) and (not truncateDataFlag); -- shift-in data if in the receiving state
-- if block filled up after that, chunk trailer and block header will be shifted-in as well
trailer_trunc_bit <= truncateDataFlag; -- truncation mark in case of CLEN_error
trailer_cerr_bit <= truncateDataFlag; -- CLEN_error is '1' in case of receiving data after CLEN is reached
trailer_type_bits <= (not (truncateDataFlag or first_subchunk)) & truncateDataFlag & first_subchunk; -- 001_first, 011_whole, 100_middle, 010_last
trailer_shift_trig <= truncateDataFlag and receiving_state; -- send a trailer once when CLEN value is reached (SOC will rst the chunk-len-counter)
receiving_state <= receiving_state and (not truncateDataFlag); -- switching off receiving in case of truncateDataFlag, waiting for SOC now
EOC_error <= '0';
SOC_error <= not receiving_state; -- if current state is not 'receiving', flag an error, do nothing
rst_clen_counter <= '0';
first_subchunk_on <= '0';
truncating_state <= truncateDataFlag and receiving_state; -- truncation trailer is sent in this 'case' (once)
--
when "01" => -- EOC
--
trailer_shift_trig <= receiving_state or do_transmit_timeout_trailers; -- if '1' => correct state, shift-in a trailer, if not, do nothing
-- sending a trailer is including padding with zeros ('flush') in case of even word count (should be flagged somewhere...)
trailer_trunc_bit <= '0'; -- no truncation, proper ending
trailer_cerr_bit <= '0';
trailer_type_bits <= do_transmit_timeout_trailers & '1' & first_subchunk; -- 'last sub-chunk' or 'whole sub-chunk' mark
EOC_error <= not receiving_state; -- if current state was not 'receiving', flag an error, do nothing
receiving_state <= '0';
--
truncating_state <= truncating_state;
rst_clen_counter <= '0';
first_subchunk_on <= '0';
data_shift_trig <= '0';
SOC_error <= '0';
--
when "10" => -- SOC
--
trailer_shift_trig <= (receiving_state and (not direct_data_mode)) or (truncateDataFlag and (not truncation_trailer_sent)); -- if '1' => incorrect state, shift-in a trailer to finish the unfinished chunk
-- sending a trailer is including padding with zeros ('flush') in case of even word count (should be flagged somewhere...)
trailer_trunc_bit <= '1'; -- truncation mark in case of sending a trailer (this is when EOC was not received)
trailer_cerr_bit <= '1';
trailer_type_bits <= "01" & (first_subchunk or truncateDataFlag); -- 'last sub-chunk' or 'whole sub-chunk' mark
SOC_error <= receiving_state; -- if current state was already 'receiving', flag an error
receiving_state <= not truncateDataFlag; --'1';
rst_clen_counter <= '1';
first_subchunk_on <= '1';
truncating_state <= truncateDataFlag and (not truncation_trailer_sent); -- truncation trailer is sent in this 'case' (once)
--
data_shift_trig <= '0';
EOC_error <= '0';
--
when "11" => -- COMMA
--
-- do nothing
receiving_state <= receiving_state;
truncating_state <= truncating_state;
trailer_trunc_bit <= '0';
trailer_cerr_bit <= '0';
trailer_type_bits <= "000";
data_shift_trig <= '0';
trailer_shift_trig <= '0';
EOC_error <= '0';
SOC_error <= '0';
rst_clen_counter <= '0';
first_subchunk_on <= '0';
--
when others =>
end case;
else
receiving_state <= receiving_state;
trailer_trunc_bit <= trailer_trunc_bit;
trailer_cerr_bit <= trailer_cerr_bit;
trailer_type_bits <= trailer_type_bits; --"000";
truncating_state <= truncating_state;
data_shift_trig <= '0';
trailer_shift_trig <= '0';
EOC_error <= '0';
SOC_error <= '0';
rst_clen_counter <= '0';
first_subchunk_on <= '0';
end if;
end if;
end process;
-----------------------------------------------------------
-- truncation trailer should be only sent once (the first one)
-----------------------------------------------------------
process(clk160)
begin
if rising_edge (clk160) then
if truncateDataFlag = '0' then
truncation_trailer_sent <= '0';
else -- truncateDataFlag = '1':
if trailer_shift_trig = '1' then
truncation_trailer_sent <= '1'; -- latch, send only one truncation trailer
end if;
end if;
end if;
end process;
--
-----------------------------------------------------------
-- clock3, writing to the shift register
-- data8bit ready pulse
-----------------------------------------------------------
process(clk160)
begin
if rising_edge (clk160) then -- first, try to flush the shift register
trailer_shift_trig_s <= trailer_shift_trig and (not EOB_MARK); -- this trailer is a result of {eoc} or {soc without eoc} or {max clen violation}
end if;
end process;
--
send_trailer_trig <= trailer_shift_trig_s or EOB_MARK; -- or truncation_from_timeout_trig;
data_shift_trig_s <= data_shift_trig;
flush_trig <= trailer_shift_trig;-- and (not truncateDataFlag); -- no need for flush in truncation case
--
DATA_shift_r: entity work.reg8to16bit -- only for data or 'flush' padding
PORT MAP(
rst => rst,
clk => clk160,
flush => flush_trig, --trailer_shift_trig,
din => DIN_r,
din_rdy => data_shift_trig_s,
-----
flushed => flushed,
dout => data,
dout_rdy => data_rdy
);
-----------------------------------------------------------
-- clock
-- BLOCK_WORD_COUNTER
-----------------------------------------------------------
BLOCK_WORD_COUNTER_inst: entity work.BLOCK_WORD_COUNTER
generic map (GBTid=>GBTid, egroupID=>egroupID, epathID=>epathID)
port map (
CLK => clk160,
RESET => rst,
RESTART => pathENAtrig,
BW_RDY => data16bit_rdy, -- counts everything that is written to EPROC FIFO
EOB_MARK => EOB_MARK, -- End-Of-Block: 'send the chunk trailer' trigger
BLOCK_HEADER_OUT => header,
BLOCK_HEADER_OUT_RDY => header_shift_trigs,
BLOCK_COUNT_RDY => blockCountRdy
);
--
process(clk160)
begin
if rising_edge (clk160) then
if first_subchunk_on = '1' or rst = '1' then
first_subchunk <= '1';
elsif EOB_MARK = '1' then
first_subchunk <= '0';
end if;
end if;
end process;
-----------------------------------------------------------
-- Sub-Chunk Data manager
-- sends a trailer in 2 clocks (current clock and the next)
-----------------------------------------------------------
--
trailer_mod_bits <= trailer_trunc_bit & trailer_cerr_bit;
--
SCDataMANAGER_inst: entity work.SCDataMANAGER
PORT MAP(
CLK => clk160,
rst => rst,
xoff => xoff_s,
maxCLEN => maxCLEN,
rstCLENcount => rst_clen_counter,
truncateCdata => truncateDataFlag, -- out, next data will be truncated, a trailer will be sent instead
trailerMOD => trailer_mod_bits, -- in, keeps its value till the next DIN_RDY_s
trailerTYPE => trailer_type_bits, -- in, keeps its value till the next DIN_RDY_s
trailerRSRVbit => xoff_s,
-------
trailerSENDtrig => send_trailer_trig,
dataCNTena => data_shift_trig_s, -- counts data Bytes (not 16-bit words)data_rdy, -- counts only data (or 'flush' padding), no header, no trailer
-------
trailerOUT => trailer0,
trailerOUTrdy => trailer_shift_trig0
);
--
--
process(clk160)
begin
if rising_edge (clk160) then
trailer_shift_trig1 <= flushed;
trailer1 <= trailer0;
end if;
end process;
--
trailer_shift_trigs <= (trailer_shift_trig0 and (not flushed)) or trailer_shift_trig1;
--
process(trailer_shift_trig1, trailer1, trailer0)
begin
if trailer_shift_trig1 = '1' then
trailer <= trailer1;
else
trailer <= trailer0;
end if;
end process;
-----------------------------------------------------------
-- 16 bit output MUX, goes to a EPROC FIFO
-----------------------------------------------------------
--process(clk160)
--begin
-- if clk160'event and clk160 = '0' then
-- data16bit_rdy_shifted <= data16bit_rdy;
-- end if;
--end process;
--
data16bit_rdy <= data_rdy or trailer_shift_trigs or header_shift_trigs or timeout_trailer_send or zero_trailer_send_pulse;
data16bit_rdy_code(0) <= (not trailer_shift_trigs) and (data_rdy xor header_shift_trigs);
data16bit_rdy_code(1) <= (not header_shift_trigs) and (data_rdy xor trailer_shift_trigs);
data16bit_rdy_code(2) <= do_transmit_timeout_trailers;
--
--process(data16bit_rdy_code, data, header, trailer)
process(clk160)
begin
if rising_edge (clk160) then
case (data16bit_rdy_code) is
when "001" => -- header
wordOUT_s <= header;
when "010" => -- trailer
wordOUT_s <= trailer;
when "011" => -- data
wordOUT_s <= data;
when "100" => -- time-out trailer
if timeout_trailer_send = '1' then
wordOUT_s <= timeout_trailer;
else
wordOUT_s <= zero_data_trailer;
end if;
when "101" => -- time-out trailer
if timeout_trailer_send = '1' then
wordOUT_s <= timeout_trailer;
else
wordOUT_s <= zero_data_trailer;
end if;
when "110" => -- time-out trailer
if timeout_trailer_send = '1' then
wordOUT_s <= timeout_trailer;
else
wordOUT_s <= zero_data_trailer;
end if;
when "111" => -- time-out trailer
if timeout_trailer_send = '1' then
wordOUT_s <= timeout_trailer;
else
wordOUT_s <= zero_data_trailer;
end if;
when others =>
--wordOUT_s <= (others => '0');
end case;
end if;
end process;
--
--
process(clk160)
begin
if rising_edge (clk160) then
if do_transmit_timeout_trailers = '0' then
zero_trailer_send_pulse_count <= (others=>'0');
else
zero_trailer_send_pulse_count <= zero_trailer_send_pulse_count + 1;
end if;
end if;
end process;
--
zero_trailer_send_pulse <= '1' when (zero_trailer_send_pulse_count = "111") else '0';
--
--
process(clk160)
begin
if rising_edge (clk160) then
if rst = '1' then
wordOUT_RDY <= '0';
else
wordOUT_RDY <= data16bit_rdy;-- or data16bit_rdy_shifted;
end if;
end if;
end process;
--
wordOUT <= wordOUT_s;
end Behavioral;
|
-- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-------------------------------------------------------------------------------------
-- This module is a clock generator for the SD card interface. It takes a 50 MHz
-- clock as input and produces a clock signal that depends on the mode in which the
-- SD card interface is in. For a card identification mode a clock with a frequency of
-- 390.625 kHz is generated. For the data transfer mode, a clock with a frequency of
-- 12.5MHz is generated.
--
-- In addition, the generator produces a clock_mode value that identifies the frequency
-- of the o_SD_clock that is currently being generated.
--
-- NOTES/REVISIONS:
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Altera_UP_SD_Card_Clock is
port
(
i_clock : in std_logic;
i_reset_n : in std_logic;
i_enable : in std_logic;
i_mode : in std_logic; -- 0 for card identification mode, 1 for data transfer mode.
o_SD_clock : out std_logic;
o_clock_mode : out std_logic;
o_trigger_receive : out std_logic;
o_trigger_send : out std_logic
);
end entity;
architecture rtl of Altera_UP_SD_Card_Clock is
-- Local wires
-- REGISTERED
signal counter : std_logic_vector(6 downto 0);
signal local_mode : std_logic;
-- UNREGISTERED
begin
process(i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
counter <= (OTHERS => '0');
local_mode <= '0';
else
if (rising_edge(i_clock)) then
if (i_enable = '1') then
counter <= counter + '1';
end if;
-- Change the clock pulse only when at the positive edge of the clock
if (counter = "1000000") then
local_mode <= i_mode;
end if;
end if;
end if;
end process;
o_clock_mode <= local_mode;
o_SD_clock <= counter(6) when (local_mode = '0') else counter(1);
o_trigger_receive <= '1' when ((local_mode = '0') and (counter = "0111111")) else
((not counter(1)) and (counter(0))) when (local_mode = '1') else '0';
o_trigger_send <= '1' when ((local_mode = '0') and (counter = "0011111")) else
((counter(1)) and (counter(0))) when (local_mode = '1') else '0';
end rtl; |
-- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-------------------------------------------------------------------------------------
-- This module is a clock generator for the SD card interface. It takes a 50 MHz
-- clock as input and produces a clock signal that depends on the mode in which the
-- SD card interface is in. For a card identification mode a clock with a frequency of
-- 390.625 kHz is generated. For the data transfer mode, a clock with a frequency of
-- 12.5MHz is generated.
--
-- In addition, the generator produces a clock_mode value that identifies the frequency
-- of the o_SD_clock that is currently being generated.
--
-- NOTES/REVISIONS:
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Altera_UP_SD_Card_Clock is
port
(
i_clock : in std_logic;
i_reset_n : in std_logic;
i_enable : in std_logic;
i_mode : in std_logic; -- 0 for card identification mode, 1 for data transfer mode.
o_SD_clock : out std_logic;
o_clock_mode : out std_logic;
o_trigger_receive : out std_logic;
o_trigger_send : out std_logic
);
end entity;
architecture rtl of Altera_UP_SD_Card_Clock is
-- Local wires
-- REGISTERED
signal counter : std_logic_vector(6 downto 0);
signal local_mode : std_logic;
-- UNREGISTERED
begin
process(i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
counter <= (OTHERS => '0');
local_mode <= '0';
else
if (rising_edge(i_clock)) then
if (i_enable = '1') then
counter <= counter + '1';
end if;
-- Change the clock pulse only when at the positive edge of the clock
if (counter = "1000000") then
local_mode <= i_mode;
end if;
end if;
end if;
end process;
o_clock_mode <= local_mode;
o_SD_clock <= counter(6) when (local_mode = '0') else counter(1);
o_trigger_receive <= '1' when ((local_mode = '0') and (counter = "0111111")) else
((not counter(1)) and (counter(0))) when (local_mode = '1') else '0';
o_trigger_send <= '1' when ((local_mode = '0') and (counter = "0011111")) else
((counter(1)) and (counter(0))) when (local_mode = '1') else '0';
end rtl; |
-- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-------------------------------------------------------------------------------------
-- This module is a clock generator for the SD card interface. It takes a 50 MHz
-- clock as input and produces a clock signal that depends on the mode in which the
-- SD card interface is in. For a card identification mode a clock with a frequency of
-- 390.625 kHz is generated. For the data transfer mode, a clock with a frequency of
-- 12.5MHz is generated.
--
-- In addition, the generator produces a clock_mode value that identifies the frequency
-- of the o_SD_clock that is currently being generated.
--
-- NOTES/REVISIONS:
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Altera_UP_SD_Card_Clock is
port
(
i_clock : in std_logic;
i_reset_n : in std_logic;
i_enable : in std_logic;
i_mode : in std_logic; -- 0 for card identification mode, 1 for data transfer mode.
o_SD_clock : out std_logic;
o_clock_mode : out std_logic;
o_trigger_receive : out std_logic;
o_trigger_send : out std_logic
);
end entity;
architecture rtl of Altera_UP_SD_Card_Clock is
-- Local wires
-- REGISTERED
signal counter : std_logic_vector(6 downto 0);
signal local_mode : std_logic;
-- UNREGISTERED
begin
process(i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
counter <= (OTHERS => '0');
local_mode <= '0';
else
if (rising_edge(i_clock)) then
if (i_enable = '1') then
counter <= counter + '1';
end if;
-- Change the clock pulse only when at the positive edge of the clock
if (counter = "1000000") then
local_mode <= i_mode;
end if;
end if;
end if;
end process;
o_clock_mode <= local_mode;
o_SD_clock <= counter(6) when (local_mode = '0') else counter(1);
o_trigger_receive <= '1' when ((local_mode = '0') and (counter = "0111111")) else
((not counter(1)) and (counter(0))) when (local_mode = '1') else '0';
o_trigger_send <= '1' when ((local_mode = '0') and (counter = "0011111")) else
((counter(1)) and (counter(0))) when (local_mode = '1') else '0';
end rtl; |
-- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-------------------------------------------------------------------------------------
-- This module is a clock generator for the SD card interface. It takes a 50 MHz
-- clock as input and produces a clock signal that depends on the mode in which the
-- SD card interface is in. For a card identification mode a clock with a frequency of
-- 390.625 kHz is generated. For the data transfer mode, a clock with a frequency of
-- 12.5MHz is generated.
--
-- In addition, the generator produces a clock_mode value that identifies the frequency
-- of the o_SD_clock that is currently being generated.
--
-- NOTES/REVISIONS:
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Altera_UP_SD_Card_Clock is
port
(
i_clock : in std_logic;
i_reset_n : in std_logic;
i_enable : in std_logic;
i_mode : in std_logic; -- 0 for card identification mode, 1 for data transfer mode.
o_SD_clock : out std_logic;
o_clock_mode : out std_logic;
o_trigger_receive : out std_logic;
o_trigger_send : out std_logic
);
end entity;
architecture rtl of Altera_UP_SD_Card_Clock is
-- Local wires
-- REGISTERED
signal counter : std_logic_vector(6 downto 0);
signal local_mode : std_logic;
-- UNREGISTERED
begin
process(i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
counter <= (OTHERS => '0');
local_mode <= '0';
else
if (rising_edge(i_clock)) then
if (i_enable = '1') then
counter <= counter + '1';
end if;
-- Change the clock pulse only when at the positive edge of the clock
if (counter = "1000000") then
local_mode <= i_mode;
end if;
end if;
end if;
end process;
o_clock_mode <= local_mode;
o_SD_clock <= counter(6) when (local_mode = '0') else counter(1);
o_trigger_receive <= '1' when ((local_mode = '0') and (counter = "0111111")) else
((not counter(1)) and (counter(0))) when (local_mode = '1') else '0';
o_trigger_send <= '1' when ((local_mode = '0') and (counter = "0011111")) else
((counter(1)) and (counter(0))) when (local_mode = '1') else '0';
end rtl; |
-- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-------------------------------------------------------------------------------------
-- This module is a clock generator for the SD card interface. It takes a 50 MHz
-- clock as input and produces a clock signal that depends on the mode in which the
-- SD card interface is in. For a card identification mode a clock with a frequency of
-- 390.625 kHz is generated. For the data transfer mode, a clock with a frequency of
-- 12.5MHz is generated.
--
-- In addition, the generator produces a clock_mode value that identifies the frequency
-- of the o_SD_clock that is currently being generated.
--
-- NOTES/REVISIONS:
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Altera_UP_SD_Card_Clock is
port
(
i_clock : in std_logic;
i_reset_n : in std_logic;
i_enable : in std_logic;
i_mode : in std_logic; -- 0 for card identification mode, 1 for data transfer mode.
o_SD_clock : out std_logic;
o_clock_mode : out std_logic;
o_trigger_receive : out std_logic;
o_trigger_send : out std_logic
);
end entity;
architecture rtl of Altera_UP_SD_Card_Clock is
-- Local wires
-- REGISTERED
signal counter : std_logic_vector(6 downto 0);
signal local_mode : std_logic;
-- UNREGISTERED
begin
process(i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
counter <= (OTHERS => '0');
local_mode <= '0';
else
if (rising_edge(i_clock)) then
if (i_enable = '1') then
counter <= counter + '1';
end if;
-- Change the clock pulse only when at the positive edge of the clock
if (counter = "1000000") then
local_mode <= i_mode;
end if;
end if;
end if;
end process;
o_clock_mode <= local_mode;
o_SD_clock <= counter(6) when (local_mode = '0') else counter(1);
o_trigger_receive <= '1' when ((local_mode = '0') and (counter = "0111111")) else
((not counter(1)) and (counter(0))) when (local_mode = '1') else '0';
o_trigger_send <= '1' when ((local_mode = '0') and (counter = "0011111")) else
((counter(1)) and (counter(0))) when (local_mode = '1') else '0';
end rtl; |
-- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-------------------------------------------------------------------------------------
-- This module is a clock generator for the SD card interface. It takes a 50 MHz
-- clock as input and produces a clock signal that depends on the mode in which the
-- SD card interface is in. For a card identification mode a clock with a frequency of
-- 390.625 kHz is generated. For the data transfer mode, a clock with a frequency of
-- 12.5MHz is generated.
--
-- In addition, the generator produces a clock_mode value that identifies the frequency
-- of the o_SD_clock that is currently being generated.
--
-- NOTES/REVISIONS:
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Altera_UP_SD_Card_Clock is
port
(
i_clock : in std_logic;
i_reset_n : in std_logic;
i_enable : in std_logic;
i_mode : in std_logic; -- 0 for card identification mode, 1 for data transfer mode.
o_SD_clock : out std_logic;
o_clock_mode : out std_logic;
o_trigger_receive : out std_logic;
o_trigger_send : out std_logic
);
end entity;
architecture rtl of Altera_UP_SD_Card_Clock is
-- Local wires
-- REGISTERED
signal counter : std_logic_vector(6 downto 0);
signal local_mode : std_logic;
-- UNREGISTERED
begin
process(i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
counter <= (OTHERS => '0');
local_mode <= '0';
else
if (rising_edge(i_clock)) then
if (i_enable = '1') then
counter <= counter + '1';
end if;
-- Change the clock pulse only when at the positive edge of the clock
if (counter = "1000000") then
local_mode <= i_mode;
end if;
end if;
end if;
end process;
o_clock_mode <= local_mode;
o_SD_clock <= counter(6) when (local_mode = '0') else counter(1);
o_trigger_receive <= '1' when ((local_mode = '0') and (counter = "0111111")) else
((not counter(1)) and (counter(0))) when (local_mode = '1') else '0';
o_trigger_send <= '1' when ((local_mode = '0') and (counter = "0011111")) else
((counter(1)) and (counter(0))) when (local_mode = '1') else '0';
end rtl; |
-- (C) 2001-2015 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-------------------------------------------------------------------------------------
-- This module is a clock generator for the SD card interface. It takes a 50 MHz
-- clock as input and produces a clock signal that depends on the mode in which the
-- SD card interface is in. For a card identification mode a clock with a frequency of
-- 390.625 kHz is generated. For the data transfer mode, a clock with a frequency of
-- 12.5MHz is generated.
--
-- In addition, the generator produces a clock_mode value that identifies the frequency
-- of the o_SD_clock that is currently being generated.
--
-- NOTES/REVISIONS:
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Altera_UP_SD_Card_Clock is
port
(
i_clock : in std_logic;
i_reset_n : in std_logic;
i_enable : in std_logic;
i_mode : in std_logic; -- 0 for card identification mode, 1 for data transfer mode.
o_SD_clock : out std_logic;
o_clock_mode : out std_logic;
o_trigger_receive : out std_logic;
o_trigger_send : out std_logic
);
end entity;
architecture rtl of Altera_UP_SD_Card_Clock is
-- Local wires
-- REGISTERED
signal counter : std_logic_vector(6 downto 0);
signal local_mode : std_logic;
-- UNREGISTERED
begin
process(i_clock, i_reset_n)
begin
if (i_reset_n = '0') then
counter <= (OTHERS => '0');
local_mode <= '0';
else
if (rising_edge(i_clock)) then
if (i_enable = '1') then
counter <= counter + '1';
end if;
-- Change the clock pulse only when at the positive edge of the clock
if (counter = "1000000") then
local_mode <= i_mode;
end if;
end if;
end if;
end process;
o_clock_mode <= local_mode;
o_SD_clock <= counter(6) when (local_mode = '0') else counter(1);
o_trigger_receive <= '1' when ((local_mode = '0') and (counter = "0111111")) else
((not counter(1)) and (counter(0))) when (local_mode = '1') else '0';
o_trigger_send <= '1' when ((local_mode = '0') and (counter = "0011111")) else
((counter(1)) and (counter(0))) when (local_mode = '1') else '0';
end rtl; |
entity tb is
end tb;
architecture sim of tb is
-- Extra tests for 'image and 'value on enumeration types (other than boolean)
-- Type with less than 256 values
type e8 is (one, two, three, four);
-- Type with more than 256 values
type e32 is (T0, T1, T2, T3, T4, T5, T6, T7, T8, T9,
T20, T21, T22, T23, T24, T25, T26, T27, T28, T29,
T30, T31, T32, T33, T34, T35, T36, T37, T38, T39,
T40, T41, T42, T43, T44, T45, T46, T47, T48, T49,
T50, T51, T52, T53, T54, T55, T56, T57, T58, T59,
T60, T61, T62, T63, T64, T65, T66, T67, T68, T69,
T70, T71, T72, T73, T74, T75, T76, T77, T78, T79,
T80, T81, T82, T83, T84, T85, T86, T87, T88, T89,
T90, T91, T92, T93, T94, T95, T96, T97, T98, T99,
T100, T101, T102, T103, T104, T105, T106, T107, T108, T109,
T110, T111, T112, T113, T114, T115, T116, T117, T118, T119,
T120, T121, T122, T123, T124, T125, T126, T127, T128, T129,
T130, T131, T132, T133, T134, T135, T136, T137, T138, T139,
T140, T141, T142, T143, T144, T145, T146, T147, T148, T149,
T150, T151, T152, T153, T154, T155, T156, T157, T158, T159,
T160, T161, T162, T163, T164, T165, T166, T167, T168, T169,
T170, T171, T172, T173, T174, T175, T176, T177, T178, T179,
T180, T181, T182, T183, T184, T185, T186, T187, T188, T189,
T190, T191, T192, T193, T194, T195, T196, T197, T198, T199,
T200, T201, T202, T203, T204, T205, T206, T207, T208, T209,
T210, T211, T212, T213, T214, T215, T216, T217, T218, T219,
T220, T221, T222, T223, T224, T225, T226, T227, T228, T229,
T230, T231, T232, T233, T234, T235, T236, T237, T238, T239,
T240, T241, T242, T243, T244, T245, T246, T247, T248, T249,
T250, T251, T252, T253, T254, T255, T256, T257, T258, T259,
T260, T261, T262, T263, T264, T265, T266, T267, T268, T269,
T270, T271, T272, T273, T274, T275, T276, T277, T278, T279,
T280, T281, T282, T283, T284, T285, T286, T287, T288, T289,
T290, T291, T292, T293, T294, T295, T296, T297, T298, T299 );
-------------- static value ----------------------
-- static value : enumeration
constant e8str : string := "three";
constant e8val : e8 := e8'value("TWO");
constant e32str_1 : string := "T254";
constant e32str_2 : string := "T257";
constant e32val_1 : e32 := e32'value("T250");
constant e32val_2 : e32 := e32'value("T260");
-------------- static image ----------------------
-- static image : enumeration
constant e8_img1 : string := e8'image(One);
constant e8_img2 : string := e8'image(Two);
constant e32_img1 : string := e32'image(T1);
constant e32_img2 : string := e32'image(T299);
-------------- runtime value ----------------------
-- runtime enumeration
signal my_e8 : e8 := One;
signal my_e8_str : string(1 to 3) := "Two";
signal my_e32 : e32 := T298;
signal my_e32_str : string(1 to 3) := "T22";
function e_val (s : string) return e8 is
begin
return e8'value(s);
end e_val;
function e_val (s : string) return e32 is
begin
return e32'value(s);
end e_val;
-------------- runtime image ----------------------
-- runtime enumeration
signal sig_e8 : e8 := e8'value("Three");
signal sig_e32 : e32 := e32'value("T123");
function e_img (e : e8) return string is
begin
return e8'image(e);
end e_img;
function e_img (e : e32) return string is
begin
return e32'image(e);
end e_img;
function t_val (t : string) return time is
begin
return time'value (t);
end t_val;
begin
-- At least one test for each constant, signal or function
-- Value tests : static enumeration expressions.
Assert e8'value("One") = Two report "Assertion 1 triggered ... correctly" severity NOTE;
Assert e8'value("One") = One report "Assertion 2 triggered ... wrongly" severity FAILURE;
Assert e8'value(e8str) = Two report "Assertion 3 triggered ... correctly" severity NOTE;
Assert e8'value(e8str) = Three report "Assertion 4 triggered ... wrongly" severity FAILURE;
Assert e8val = Four report "Assertion 5 triggered ... correctly" severity NOTE;
Assert e8val = Two report "Assertion 6 triggered ... wrongly" severity FAILURE;
Assert e32'value("T1") = T2 report "Assertion 7 triggered ... correctly" severity NOTE;
Assert e32'value("T2") = T2 report "Assertion 8 triggered ... wrongly" severity FAILURE;
Assert e32'value(e32str_1) = T257 report "Assertion 9 triggered ... correctly" severity NOTE;
Assert e32'value(e32str_2) = T257 report "Assertion 10 triggered ... wrongly" severity FAILURE;
Assert e32val_1 = T260 report "Assertion 11 triggered ... correctly" severity NOTE;
Assert e32val_2 = T260 report "Assertion 12 triggered ... wrongly" severity FAILURE;
-- static image : enumeration
Assert e8_img1 = "One" report "Assertion 13 triggered ... correctly" severity NOTE;
Assert e8_img2 = "two" report "Assertion 14 triggered ... wrongly" severity FAILURE;
Assert e32_img1 = "T1" report "Assertion 15 triggered ... correctly" severity NOTE;
Assert e32_img2 = "t299" report "Assertion 16 triggered ... wrongly" severity FAILURE;
-------------- runtime value ----------------------
my_e8 <= Two after 10 ns;
my_e8_str <= "One" after 20 ns;
Assert my_e8 = One report "Assertion 17 triggered ... correctly" severity NOTE;
Assert my_e8 = Two report "Assertion 18 triggered ... correctly" severity NOTE;
Assert e_val(my_e8_str) = Three report "Assertion 19 triggered ... correctly" severity NOTE;
Assert e_val(my_e8_str) = Two report "Assertion 20 triggered ... wrongly except at 20ns" severity NOTE;
my_e32 <= T297 after 30 ns;
Assert my_e32 = T296 report "Assertion 21 triggered ... correctly" severity NOTE;
my_e32_str <= "T24" after 40 ns;
Assert e_val(my_e32_str) = T23 report "Assertion 22 triggered ... correctly" severity NOTE;
Assert e_val(my_e32_str) = T22 report "Assertion 23 triggered ... wrongly except at 40ns" severity NOTE;
-- Check white spaces and case.
assert e_val(" one") = one report "assertion 31" severity failure;
assert e_val(" one ") = one report "assertion 32" severity failure;
assert e_val("one ") = one report "assertion 33" severity failure;
assert e_val("oNe") = one report "assertion 34" severity failure;
assert e_val(" T1") = t1 report "assertion 35" severity failure;
assert e_val(" t2 ") = t2 report "assertion 36" severity failure;
assert e_val("t3 ") = t3 report "assertion 37" severity failure;
assert e_val("t39") = t39 report "assertion 38" severity failure;
assert t_val("1 ns") = 1 ns report "assertion 40" severity failure;
assert t_val(" 1 nS") = 1 ns report "assertion 41" severity failure;
assert t_val(" 1 Ns ") = 1 ns report "assertion 42" severity failure;
assert t_val(" -1.5 ns ") = -1500 ps report "assertion 44" severity failure;
-------------- runtime image ----------------------
-- runtime enumeration
sig_e8 <= Two after 50 ns, Four after 60 ns;
Assert sig_e8 = One report "Sig_e8 = " & e8'image(sig_e8) & " fn returns " & e_img(sig_e8) severity Note;
sig_e32 <= T124 after 70 ns, T125 after 80 ns;
Assert sig_e32 = T122 report "Sig_e32 = " & e32'image(sig_e32) & " fn returns " & e_img(sig_e32) severity Note;
end sim;
|
entity tb is
end tb;
architecture sim of tb is
-- Extra tests for 'image and 'value on enumeration types (other than boolean)
-- Type with less than 256 values
type e8 is (one, two, three, four);
-- Type with more than 256 values
type e32 is (T0, T1, T2, T3, T4, T5, T6, T7, T8, T9,
T20, T21, T22, T23, T24, T25, T26, T27, T28, T29,
T30, T31, T32, T33, T34, T35, T36, T37, T38, T39,
T40, T41, T42, T43, T44, T45, T46, T47, T48, T49,
T50, T51, T52, T53, T54, T55, T56, T57, T58, T59,
T60, T61, T62, T63, T64, T65, T66, T67, T68, T69,
T70, T71, T72, T73, T74, T75, T76, T77, T78, T79,
T80, T81, T82, T83, T84, T85, T86, T87, T88, T89,
T90, T91, T92, T93, T94, T95, T96, T97, T98, T99,
T100, T101, T102, T103, T104, T105, T106, T107, T108, T109,
T110, T111, T112, T113, T114, T115, T116, T117, T118, T119,
T120, T121, T122, T123, T124, T125, T126, T127, T128, T129,
T130, T131, T132, T133, T134, T135, T136, T137, T138, T139,
T140, T141, T142, T143, T144, T145, T146, T147, T148, T149,
T150, T151, T152, T153, T154, T155, T156, T157, T158, T159,
T160, T161, T162, T163, T164, T165, T166, T167, T168, T169,
T170, T171, T172, T173, T174, T175, T176, T177, T178, T179,
T180, T181, T182, T183, T184, T185, T186, T187, T188, T189,
T190, T191, T192, T193, T194, T195, T196, T197, T198, T199,
T200, T201, T202, T203, T204, T205, T206, T207, T208, T209,
T210, T211, T212, T213, T214, T215, T216, T217, T218, T219,
T220, T221, T222, T223, T224, T225, T226, T227, T228, T229,
T230, T231, T232, T233, T234, T235, T236, T237, T238, T239,
T240, T241, T242, T243, T244, T245, T246, T247, T248, T249,
T250, T251, T252, T253, T254, T255, T256, T257, T258, T259,
T260, T261, T262, T263, T264, T265, T266, T267, T268, T269,
T270, T271, T272, T273, T274, T275, T276, T277, T278, T279,
T280, T281, T282, T283, T284, T285, T286, T287, T288, T289,
T290, T291, T292, T293, T294, T295, T296, T297, T298, T299 );
-------------- static value ----------------------
-- static value : enumeration
constant e8str : string := "three";
constant e8val : e8 := e8'value("TWO");
constant e32str_1 : string := "T254";
constant e32str_2 : string := "T257";
constant e32val_1 : e32 := e32'value("T250");
constant e32val_2 : e32 := e32'value("T260");
-------------- static image ----------------------
-- static image : enumeration
constant e8_img1 : string := e8'image(One);
constant e8_img2 : string := e8'image(Two);
constant e32_img1 : string := e32'image(T1);
constant e32_img2 : string := e32'image(T299);
-------------- runtime value ----------------------
-- runtime enumeration
signal my_e8 : e8 := One;
signal my_e8_str : string(1 to 3) := "Two";
signal my_e32 : e32 := T298;
signal my_e32_str : string(1 to 3) := "T22";
function e_val (s : string) return e8 is
begin
return e8'value(s);
end e_val;
function e_val (s : string) return e32 is
begin
return e32'value(s);
end e_val;
-------------- runtime image ----------------------
-- runtime enumeration
signal sig_e8 : e8 := e8'value("Three");
signal sig_e32 : e32 := e32'value("T123");
function e_img (e : e8) return string is
begin
return e8'image(e);
end e_img;
function e_img (e : e32) return string is
begin
return e32'image(e);
end e_img;
function t_val (t : string) return time is
begin
return time'value (t);
end t_val;
begin
-- At least one test for each constant, signal or function
-- Value tests : static enumeration expressions.
Assert e8'value("One") = Two report "Assertion 1 triggered ... correctly" severity NOTE;
Assert e8'value("One") = One report "Assertion 2 triggered ... wrongly" severity FAILURE;
Assert e8'value(e8str) = Two report "Assertion 3 triggered ... correctly" severity NOTE;
Assert e8'value(e8str) = Three report "Assertion 4 triggered ... wrongly" severity FAILURE;
Assert e8val = Four report "Assertion 5 triggered ... correctly" severity NOTE;
Assert e8val = Two report "Assertion 6 triggered ... wrongly" severity FAILURE;
Assert e32'value("T1") = T2 report "Assertion 7 triggered ... correctly" severity NOTE;
Assert e32'value("T2") = T2 report "Assertion 8 triggered ... wrongly" severity FAILURE;
Assert e32'value(e32str_1) = T257 report "Assertion 9 triggered ... correctly" severity NOTE;
Assert e32'value(e32str_2) = T257 report "Assertion 10 triggered ... wrongly" severity FAILURE;
Assert e32val_1 = T260 report "Assertion 11 triggered ... correctly" severity NOTE;
Assert e32val_2 = T260 report "Assertion 12 triggered ... wrongly" severity FAILURE;
-- static image : enumeration
Assert e8_img1 = "One" report "Assertion 13 triggered ... correctly" severity NOTE;
Assert e8_img2 = "two" report "Assertion 14 triggered ... wrongly" severity FAILURE;
Assert e32_img1 = "T1" report "Assertion 15 triggered ... correctly" severity NOTE;
Assert e32_img2 = "t299" report "Assertion 16 triggered ... wrongly" severity FAILURE;
-------------- runtime value ----------------------
my_e8 <= Two after 10 ns;
my_e8_str <= "One" after 20 ns;
Assert my_e8 = One report "Assertion 17 triggered ... correctly" severity NOTE;
Assert my_e8 = Two report "Assertion 18 triggered ... correctly" severity NOTE;
Assert e_val(my_e8_str) = Three report "Assertion 19 triggered ... correctly" severity NOTE;
Assert e_val(my_e8_str) = Two report "Assertion 20 triggered ... wrongly except at 20ns" severity NOTE;
my_e32 <= T297 after 30 ns;
Assert my_e32 = T296 report "Assertion 21 triggered ... correctly" severity NOTE;
my_e32_str <= "T24" after 40 ns;
Assert e_val(my_e32_str) = T23 report "Assertion 22 triggered ... correctly" severity NOTE;
Assert e_val(my_e32_str) = T22 report "Assertion 23 triggered ... wrongly except at 40ns" severity NOTE;
-- Check white spaces and case.
assert e_val(" one") = one report "assertion 31" severity failure;
assert e_val(" one ") = one report "assertion 32" severity failure;
assert e_val("one ") = one report "assertion 33" severity failure;
assert e_val("oNe") = one report "assertion 34" severity failure;
assert e_val(" T1") = t1 report "assertion 35" severity failure;
assert e_val(" t2 ") = t2 report "assertion 36" severity failure;
assert e_val("t3 ") = t3 report "assertion 37" severity failure;
assert e_val("t39") = t39 report "assertion 38" severity failure;
assert t_val("1 ns") = 1 ns report "assertion 40" severity failure;
assert t_val(" 1 nS") = 1 ns report "assertion 41" severity failure;
assert t_val(" 1 Ns ") = 1 ns report "assertion 42" severity failure;
assert t_val(" -1.5 ns ") = -1500 ps report "assertion 44" severity failure;
-------------- runtime image ----------------------
-- runtime enumeration
sig_e8 <= Two after 50 ns, Four after 60 ns;
Assert sig_e8 = One report "Sig_e8 = " & e8'image(sig_e8) & " fn returns " & e_img(sig_e8) severity Note;
sig_e32 <= T124 after 70 ns, T125 after 80 ns;
Assert sig_e32 = T122 report "Sig_e32 = " & e32'image(sig_e32) & " fn returns " & e_img(sig_e32) severity Note;
end sim;
|
entity tb is
end tb;
architecture sim of tb is
-- Extra tests for 'image and 'value on enumeration types (other than boolean)
-- Type with less than 256 values
type e8 is (one, two, three, four);
-- Type with more than 256 values
type e32 is (T0, T1, T2, T3, T4, T5, T6, T7, T8, T9,
T20, T21, T22, T23, T24, T25, T26, T27, T28, T29,
T30, T31, T32, T33, T34, T35, T36, T37, T38, T39,
T40, T41, T42, T43, T44, T45, T46, T47, T48, T49,
T50, T51, T52, T53, T54, T55, T56, T57, T58, T59,
T60, T61, T62, T63, T64, T65, T66, T67, T68, T69,
T70, T71, T72, T73, T74, T75, T76, T77, T78, T79,
T80, T81, T82, T83, T84, T85, T86, T87, T88, T89,
T90, T91, T92, T93, T94, T95, T96, T97, T98, T99,
T100, T101, T102, T103, T104, T105, T106, T107, T108, T109,
T110, T111, T112, T113, T114, T115, T116, T117, T118, T119,
T120, T121, T122, T123, T124, T125, T126, T127, T128, T129,
T130, T131, T132, T133, T134, T135, T136, T137, T138, T139,
T140, T141, T142, T143, T144, T145, T146, T147, T148, T149,
T150, T151, T152, T153, T154, T155, T156, T157, T158, T159,
T160, T161, T162, T163, T164, T165, T166, T167, T168, T169,
T170, T171, T172, T173, T174, T175, T176, T177, T178, T179,
T180, T181, T182, T183, T184, T185, T186, T187, T188, T189,
T190, T191, T192, T193, T194, T195, T196, T197, T198, T199,
T200, T201, T202, T203, T204, T205, T206, T207, T208, T209,
T210, T211, T212, T213, T214, T215, T216, T217, T218, T219,
T220, T221, T222, T223, T224, T225, T226, T227, T228, T229,
T230, T231, T232, T233, T234, T235, T236, T237, T238, T239,
T240, T241, T242, T243, T244, T245, T246, T247, T248, T249,
T250, T251, T252, T253, T254, T255, T256, T257, T258, T259,
T260, T261, T262, T263, T264, T265, T266, T267, T268, T269,
T270, T271, T272, T273, T274, T275, T276, T277, T278, T279,
T280, T281, T282, T283, T284, T285, T286, T287, T288, T289,
T290, T291, T292, T293, T294, T295, T296, T297, T298, T299 );
-------------- static value ----------------------
-- static value : enumeration
constant e8str : string := "three";
constant e8val : e8 := e8'value("TWO");
constant e32str_1 : string := "T254";
constant e32str_2 : string := "T257";
constant e32val_1 : e32 := e32'value("T250");
constant e32val_2 : e32 := e32'value("T260");
-------------- static image ----------------------
-- static image : enumeration
constant e8_img1 : string := e8'image(One);
constant e8_img2 : string := e8'image(Two);
constant e32_img1 : string := e32'image(T1);
constant e32_img2 : string := e32'image(T299);
-------------- runtime value ----------------------
-- runtime enumeration
signal my_e8 : e8 := One;
signal my_e8_str : string(1 to 3) := "Two";
signal my_e32 : e32 := T298;
signal my_e32_str : string(1 to 3) := "T22";
function e_val (s : string) return e8 is
begin
return e8'value(s);
end e_val;
function e_val (s : string) return e32 is
begin
return e32'value(s);
end e_val;
-------------- runtime image ----------------------
-- runtime enumeration
signal sig_e8 : e8 := e8'value("Three");
signal sig_e32 : e32 := e32'value("T123");
function e_img (e : e8) return string is
begin
return e8'image(e);
end e_img;
function e_img (e : e32) return string is
begin
return e32'image(e);
end e_img;
function t_val (t : string) return time is
begin
return time'value (t);
end t_val;
begin
-- At least one test for each constant, signal or function
-- Value tests : static enumeration expressions.
Assert e8'value("One") = Two report "Assertion 1 triggered ... correctly" severity NOTE;
Assert e8'value("One") = One report "Assertion 2 triggered ... wrongly" severity FAILURE;
Assert e8'value(e8str) = Two report "Assertion 3 triggered ... correctly" severity NOTE;
Assert e8'value(e8str) = Three report "Assertion 4 triggered ... wrongly" severity FAILURE;
Assert e8val = Four report "Assertion 5 triggered ... correctly" severity NOTE;
Assert e8val = Two report "Assertion 6 triggered ... wrongly" severity FAILURE;
Assert e32'value("T1") = T2 report "Assertion 7 triggered ... correctly" severity NOTE;
Assert e32'value("T2") = T2 report "Assertion 8 triggered ... wrongly" severity FAILURE;
Assert e32'value(e32str_1) = T257 report "Assertion 9 triggered ... correctly" severity NOTE;
Assert e32'value(e32str_2) = T257 report "Assertion 10 triggered ... wrongly" severity FAILURE;
Assert e32val_1 = T260 report "Assertion 11 triggered ... correctly" severity NOTE;
Assert e32val_2 = T260 report "Assertion 12 triggered ... wrongly" severity FAILURE;
-- static image : enumeration
Assert e8_img1 = "One" report "Assertion 13 triggered ... correctly" severity NOTE;
Assert e8_img2 = "two" report "Assertion 14 triggered ... wrongly" severity FAILURE;
Assert e32_img1 = "T1" report "Assertion 15 triggered ... correctly" severity NOTE;
Assert e32_img2 = "t299" report "Assertion 16 triggered ... wrongly" severity FAILURE;
-------------- runtime value ----------------------
my_e8 <= Two after 10 ns;
my_e8_str <= "One" after 20 ns;
Assert my_e8 = One report "Assertion 17 triggered ... correctly" severity NOTE;
Assert my_e8 = Two report "Assertion 18 triggered ... correctly" severity NOTE;
Assert e_val(my_e8_str) = Three report "Assertion 19 triggered ... correctly" severity NOTE;
Assert e_val(my_e8_str) = Two report "Assertion 20 triggered ... wrongly except at 20ns" severity NOTE;
my_e32 <= T297 after 30 ns;
Assert my_e32 = T296 report "Assertion 21 triggered ... correctly" severity NOTE;
my_e32_str <= "T24" after 40 ns;
Assert e_val(my_e32_str) = T23 report "Assertion 22 triggered ... correctly" severity NOTE;
Assert e_val(my_e32_str) = T22 report "Assertion 23 triggered ... wrongly except at 40ns" severity NOTE;
-- Check white spaces and case.
assert e_val(" one") = one report "assertion 31" severity failure;
assert e_val(" one ") = one report "assertion 32" severity failure;
assert e_val("one ") = one report "assertion 33" severity failure;
assert e_val("oNe") = one report "assertion 34" severity failure;
assert e_val(" T1") = t1 report "assertion 35" severity failure;
assert e_val(" t2 ") = t2 report "assertion 36" severity failure;
assert e_val("t3 ") = t3 report "assertion 37" severity failure;
assert e_val("t39") = t39 report "assertion 38" severity failure;
assert t_val("1 ns") = 1 ns report "assertion 40" severity failure;
assert t_val(" 1 nS") = 1 ns report "assertion 41" severity failure;
assert t_val(" 1 Ns ") = 1 ns report "assertion 42" severity failure;
assert t_val(" -1.5 ns ") = -1500 ps report "assertion 44" severity failure;
-------------- runtime image ----------------------
-- runtime enumeration
sig_e8 <= Two after 50 ns, Four after 60 ns;
Assert sig_e8 = One report "Sig_e8 = " & e8'image(sig_e8) & " fn returns " & e_img(sig_e8) severity Note;
sig_e32 <= T124 after 70 ns, T125 after 80 ns;
Assert sig_e32 = T122 report "Sig_e32 = " & e32'image(sig_e32) & " fn returns " & e_img(sig_e32) severity Note;
end sim;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.types.all;
entity ALU is
port (
clk : in std_logic;
code : in std_logic_vector(3 downto 0);
tagD : in tag_t;
valA : in value_t;
valB : in value_t;
emitTag : out tag_t := (others => '0');
emitVal : out value_t);
end ALU;
architecture twoproc of ALU is
signal c : std_logic_vector(3 downto 0) := "0000";
signal s : value_t := (others => '0');
signal t : value_t := (others => '0');
function boolean_value(b : boolean) return value_t;
function boolean_value(b : boolean) return value_t is
constant z31 : std_logic_vector(31 downto 1) := (others => '0');
begin
if b then
return z31 & '1';
else
return z31 & '0';
end if;
end boolean_value;
begin
sequential : process(clk)
begin
if rising_edge(clk) then
c <= code;
emitTag <= tagD;
s <= valA;
t <= valB;
end if;
end process;
combinatorial : process(c, s, t)
variable d_add, d_sub, d_xor, d_and, d_or, d_sll, d_srl, d_sra, d_cat, d_mul : value_t;
variable d_eq, d_lt, d_feq, d_flt : boolean;
variable tmp_lt, tmp_z_s, tmp_z_t : boolean;
begin
d_add := std_logic_vector(unsigned(s) + unsigned(t));
d_sub := std_logic_vector(unsigned(s) - unsigned(t));
tmp_lt := unsigned(s(30 downto 0)) < unsigned(t(30 downto 0));
tmp_z_s := unsigned(s(30 downto 0)) = 0;
tmp_z_t := unsigned(t(30 downto 0)) = 0;
d_eq := s = t;
d_lt := (s(31) = '1' and t(31) = '0') or (s(31) = t(31) and tmp_lt);
d_and := s and t;
d_xor := s xor t;
d_or := s or t;
d_sll := std_logic_vector(shift_left(unsigned(s), to_integer(unsigned(t(4 downto 0)))));
d_srl := std_logic_vector(shift_right(unsigned(s), to_integer(unsigned(t(4 downto 0)))));
d_sra := std_logic_vector(shift_right(signed(s), to_integer(unsigned(t(4 downto 0)))));
d_cat := t(15 downto 0) & s(15 downto 0);
d_mul := value_t((unsigned(s(15 downto 0)) * unsigned(t(15 downto 0))));
d_feq := d_eq or (tmp_z_s and tmp_z_t);
d_flt := not d_feq and
( (s(31) = '1' and t(31) = '0') or
(s(31) = '0' and t(31) = '0' and tmp_lt) or
(s(31) = '1' and t(31) = '1' and not tmp_lt));
case c is
when "0000" => emitVal <= d_add;
when "0001" => emitVal <= d_sub;
when "0010" => emitVal <= boolean_value(d_eq);
when "0011" => emitVal <= boolean_value(d_lt);
when "0100" => emitVal <= d_and;
when "0101" => emitVal <= d_or;
when "0110" => emitVal <= d_xor;
when "0111" => emitVal <= d_sll;
when "1000" => emitVal <= d_srl;
when "1001" => emitVal <= d_sra;
when "1010" => emitVal <= d_cat;
when "1011" => emitVal <= d_mul;
when "1100" => emitVal <= s;
when "1101" => assert(false); emitVal <= s;
when "1110" => emitVal <= boolean_value(d_feq);
when "1111" => emitVal <= boolean_value(d_flt);
when others => assert false;
end case;
end process;
end twoproc;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2219.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02219ent IS
END c07s02b06x00p01n01i02219ent;
ARCHITECTURE c07s02b06x00p01n01i02219arch OF c07s02b06x00p01n01i02219ent IS
BEGIN
TESTING: PROCESS
variable k : integer;
BEGIN
k := '0' rem '2';
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02219 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02219arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2219.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02219ent IS
END c07s02b06x00p01n01i02219ent;
ARCHITECTURE c07s02b06x00p01n01i02219arch OF c07s02b06x00p01n01i02219ent IS
BEGIN
TESTING: PROCESS
variable k : integer;
BEGIN
k := '0' rem '2';
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02219 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02219arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2219.vhd,v 1.2 2001-10-26 16:30:16 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02219ent IS
END c07s02b06x00p01n01i02219ent;
ARCHITECTURE c07s02b06x00p01n01i02219arch OF c07s02b06x00p01n01i02219ent IS
BEGIN
TESTING: PROCESS
variable k : integer;
BEGIN
k := '0' rem '2';
assert FALSE
report "***FAILED TEST: c07s02b06x00p01n01i02219 - Operators mod and rem are predefined for any integer type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02219arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package pack0 is
procedure inc(signal val:inout std_logic_vector);
procedure inc(signal val:inout unsigned);
procedure inc(signal val:inout signed);
procedure inc(signal val:inout integer);
procedure dec(signal val:inout std_logic_vector);
procedure dec(signal val:inout unsigned);
procedure dec(signal val:inout signed);
procedure dec(signal val:inout integer);
end pack0;
package body pack0 is
procedure inc(signal val:inout std_logic_vector) is
begin
val<= std_logic_vector(unsigned(val) + 1);
end;
procedure inc(signal val:inout signed) is
begin
val<= val + 1;
end;
procedure inc(signal val:inout unsigned) is
begin
val<= val + 1;
end;
procedure inc(signal val:inout integer) is
begin
val<= val + 1;
end;
procedure dec(signal val:inout std_logic_vector) is
begin
val<= std_logic_vector(unsigned(val) - 1);
end;
procedure dec(signal val:inout unsigned) is
begin
val<= val - 1;
end;
procedure dec(signal val:inout signed) is
begin
val<= val - 1;
end;
procedure dec(signal val:inout integer) is
begin
val<= val - 1;
end;
end;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package pack1 is
procedure inc(variable val:inout unsigned);
procedure inc(variable val:inout integer);
procedure dec(variable val:inout unsigned);
procedure dec(variable val:inout integer);
end pack1;
package body pack1 is
procedure inc(variable val:inout unsigned) is
begin
val := val + 1;
end;
procedure inc(variable val:inout integer) is
begin
val := val + 1;
end;
procedure dec(variable val:inout unsigned) is
begin
val := val - 1;
end;
procedure dec(variable val:inout integer) is
begin
val := val - 1;
end;
end;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.pack0.all;
use work.pack1.all;
entity overload is
end entity;
architecture foo of overload is
signal sig: unsigned ( 7 downto 0) := (others => '0');
signal int: integer range 0 to 255; -- 'LEFT = 0 initial value
begin
process
variable isig: unsigned ( 7 downto 0) := (others => '0');
variable iint: integer range 0 to 255;
begin
inc(sig);
inc(isig);
inc(int);
inc(iint);
wait for 0 ns;
dec(sig);
dec(isig);
dec(int);
dec(iint);
wait;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package pack0 is
procedure inc(signal val:inout std_logic_vector);
procedure inc(signal val:inout unsigned);
procedure inc(signal val:inout signed);
procedure inc(signal val:inout integer);
procedure dec(signal val:inout std_logic_vector);
procedure dec(signal val:inout unsigned);
procedure dec(signal val:inout signed);
procedure dec(signal val:inout integer);
end pack0;
package body pack0 is
procedure inc(signal val:inout std_logic_vector) is
begin
val<= std_logic_vector(unsigned(val) + 1);
end;
procedure inc(signal val:inout signed) is
begin
val<= val + 1;
end;
procedure inc(signal val:inout unsigned) is
begin
val<= val + 1;
end;
procedure inc(signal val:inout integer) is
begin
val<= val + 1;
end;
procedure dec(signal val:inout std_logic_vector) is
begin
val<= std_logic_vector(unsigned(val) - 1);
end;
procedure dec(signal val:inout unsigned) is
begin
val<= val - 1;
end;
procedure dec(signal val:inout signed) is
begin
val<= val - 1;
end;
procedure dec(signal val:inout integer) is
begin
val<= val - 1;
end;
end;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package pack1 is
procedure inc(variable val:inout unsigned);
procedure inc(variable val:inout integer);
procedure dec(variable val:inout unsigned);
procedure dec(variable val:inout integer);
end pack1;
package body pack1 is
procedure inc(variable val:inout unsigned) is
begin
val := val + 1;
end;
procedure inc(variable val:inout integer) is
begin
val := val + 1;
end;
procedure dec(variable val:inout unsigned) is
begin
val := val - 1;
end;
procedure dec(variable val:inout integer) is
begin
val := val - 1;
end;
end;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.pack0.all;
use work.pack1.all;
entity overload is
end entity;
architecture foo of overload is
signal sig: unsigned ( 7 downto 0) := (others => '0');
signal int: integer range 0 to 255; -- 'LEFT = 0 initial value
begin
process
variable isig: unsigned ( 7 downto 0) := (others => '0');
variable iint: integer range 0 to 255;
begin
inc(sig);
inc(isig);
inc(int);
inc(iint);
wait for 0 ns;
dec(sig);
dec(isig);
dec(int);
dec(iint);
wait;
end process;
end architecture;
|
Library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity nbit_XtoY_mux is
generic(
bitPerInput: integer:=2;
numInputs: integer:=4
);
port(
enable: in std_logic;
input:in std_logic_vector(bitPerInput*numInputs-1 downto 0);
output:out std_logic_vector(bitPerInput-1 downto 0);
selectors: in std_logic_vector(integer(log2(real(numInputs)))-1 downto 0)
);
end entity;
architecture primary of nbit_XtoY_mux is
type inputArray is array (numInputs-1 downto 0) of std_logic_vector(bitPerInput-1 downto 0);
signal inputs: inputArray;
begin
process(input,enable,inputs,selectors) begin
if(enable ='1') then
for i in 0 to numInputs-1 loop
inputs(i) <= input(((i+1)*bitPerInput)-1 downto i*bitPerInput);
end loop;
output <= inputs(to_integer(unsigned(selectors)));
else
output <= (others=>'0');
for i in 0 to numInputs-1 loop
inputs(i) <= (others=>'0');
end loop;
end if;
end process;
end primary;
|
-- Copyright (c) 2012 Brian Nezvadovitz <http://nezzen.net>
-- This software is distributed under the terms of the MIT License shown below.
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to
-- deal in the Software without restriction, including without limitation the
-- rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
-- sell copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
-- IN THE SOFTWARE.
-- Implements an adder of variable width with carry signals.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity adder is
generic (
WIDTH : positive := 8
);
port (
input1 : in std_logic_vector(WIDTH-1 downto 0);
input2 : in std_logic_vector(WIDTH-1 downto 0);
c_in : in std_logic;
output : out std_logic_vector(WIDTH-1 downto 0);
c_out : out std_logic
);
end;
architecture BHV of adder is
signal full_sum : std_logic_vector(WIDTH downto 0);
signal c_in_vec : std_logic_vector(0 downto 0);
begin
c_in_vec(0) <= c_in;
full_sum <= std_logic_vector( resize(unsigned(input1), WIDTH+1) + resize(unsigned(input2), WIDTH+1) + resize(unsigned(c_in_vec), WIDTH+1) );
output <= full_sum(WIDTH-1 downto 0);
c_out <= full_sum(WIDTH);
end BHV;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc186.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s04b00x00p12n01i00186ent IS
END c04s04b00x00p12n01i00186ent;
ARCHITECTURE c04s04b00x00p12n01i00186arch OF c04s04b00x00p12n01i00186ent IS
attribute POSI : NATURAL;
attribute POSI of S: signal is 10; --- Failure_here
signal S : Integer;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s04b00x00p12n01i00186 - Entity declaration does not exist."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s04b00x00p12n01i00186arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc186.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s04b00x00p12n01i00186ent IS
END c04s04b00x00p12n01i00186ent;
ARCHITECTURE c04s04b00x00p12n01i00186arch OF c04s04b00x00p12n01i00186ent IS
attribute POSI : NATURAL;
attribute POSI of S: signal is 10; --- Failure_here
signal S : Integer;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s04b00x00p12n01i00186 - Entity declaration does not exist."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s04b00x00p12n01i00186arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc186.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s04b00x00p12n01i00186ent IS
END c04s04b00x00p12n01i00186ent;
ARCHITECTURE c04s04b00x00p12n01i00186arch OF c04s04b00x00p12n01i00186ent IS
attribute POSI : NATURAL;
attribute POSI of S: signal is 10; --- Failure_here
signal S : Integer;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s04b00x00p12n01i00186 - Entity declaration does not exist."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s04b00x00p12n01i00186arch;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.std_logic_arith.all;
ENTITY test_fetch_register IS
END test_fetch_register;
ARCHITECTURE behavior OF test_fetch_register IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT fetch_register
PORT(
mem_addr : IN std_logic_vector(5 downto 0);
mem_amount : IN std_logic_vector(4 downto 0);
reg_val : OUT std_logic_vector(127 downto 0);
masterReset : IN std_logic;
clk : IN std_logic
);
END COMPONENT;
--Inputs
signal mem_addr : std_logic_vector(5 downto 0) := (others => '0');
signal mem_amount : std_logic_vector(4 downto 0) := (others => '0');
signal masterReset : std_logic := '0';
signal clk : std_logic := '0';
--Outputs
signal reg_val : std_logic_vector(127 downto 0) := (others => '0');
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
uut: fetch_register PORT MAP (
mem_addr => mem_addr,
mem_amount => mem_amount,
reg_val => reg_val,
masterReset => masterReset,
clk => clk
);
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
mem_addr <= std_logic_vector(ieee.numeric_std.to_unsigned(44, 6));
mem_amount <= std_logic_vector(ieee.numeric_std.to_unsigned(8, 5));
-- Stimulus process
stim_proc: process
begin
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
|
--------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Entity: SinglePulseGenerator
-- Date:2011-11-10
-- Author: Andrzej Paluch
--
-- Description ${cursor}
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.utilPkg.all;
entity SinglePulseGenerator is
generic (
WIDTH : integer := 3
);
port (
reset : in std_logic;
clk : in std_logic;
t_in: in std_logic;
t_out : out std_logic;
pulse : out std_logic
);
end SinglePulseGenerator;
architecture arch of SinglePulseGenerator is
signal rcount : integer range 0 to WIDTH;
signal i_t_out : std_logic;
begin
pulse <= to_stdl(t_in /= i_t_out);
t_out <= i_t_out;
-- buffer reset generator
process (reset, clk, t_in) begin
if reset = '1' then
i_t_out <= t_in;
rcount <= 0;
elsif rising_edge(clk) then
if t_in /= i_t_out then
rcount <= rcount + 1;
if rcount = WIDTH then
rcount <= 0;
i_t_out <= t_in;
end if;
end if;
end if;
end process;
end arch;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 20 13:53:00 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- c:/ZyboIP/general_ip/affine_transform/affine_transform.srcs/sources_1/bd/affine_block/ip/affine_block_ieee754_fp_adder_subtractor_0_1/affine_block_ieee754_fp_adder_subtractor_0_1_stub.vhdl
-- Design : affine_block_ieee754_fp_adder_subtractor_0_1
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity affine_block_ieee754_fp_adder_subtractor_0_1 is
Port (
x : in STD_LOGIC_VECTOR ( 31 downto 0 );
y : in STD_LOGIC_VECTOR ( 31 downto 0 );
z : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end affine_block_ieee754_fp_adder_subtractor_0_1;
architecture stub of affine_block_ieee754_fp_adder_subtractor_0_1 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "x[31:0],y[31:0],z[31:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "ieee754_fp_adder_subtractor,Vivado 2016.4";
begin
end;
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
-- Cache Replacement Algorithm
library ieee;
use ieee.std_logic_1164.all;
use work.cpu_l1mem_data_cache_pkg.all;
use work.cpu_l1mem_data_cache_replace_pkg.all;
entity cpu_l1mem_data_cache_replace is
port (
clk : in std_ulogic;
rstn : in std_ulogic;
cpu_l1mem_data_cache_replace_ctrl_in : in cpu_l1mem_data_cache_replace_ctrl_in_type;
cpu_l1mem_data_cache_replace_ctrl_out : out cpu_l1mem_data_cache_replace_ctrl_out_type;
cpu_l1mem_data_cache_replace_dp_in : in cpu_l1mem_data_cache_replace_dp_in_type;
cpu_l1mem_data_cache_replace_dp_out : out cpu_l1mem_data_cache_replace_dp_out_type
);
end;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.VHDL_lib.all;
entity debounce is
generic(
delay:integer := 50000
);
port(
clk: in std_logic;
input: in std_logic;
output: out std_logic
);
end debounce;
architecture Behavioral of debounce is
signal press : std_logic;
signal debounce_enable : std_logic;
signal debounce_pulse : std_logic;
signal hold_check : std_logic;
signal hold_pulse: std_logic;
-- signal rapid_pulse: std_logic;
-- signal rapid_enable: std_logic;
type states is (idle,wait_noise,check,debounced,holding,held);
signal state : states := idle;
begin
output <= press;
pulser1: pulser generic map(delay=>delay) port map(clk,debounce_enable,debounce_pulse);
pulser2: pulser generic map(delay=>delay*2) port map(clk,hold_check,hold_pulse);
debounce_signal: process(clk)
begin
if(clk'event and clk = '1')then
case state is
when idle =>
debounce_enable <= '0';
hold_check <= '0';
press <= '0';
if(input = '1')then
state <= wait_noise;
end if;
when wait_noise =>
debounce_enable <= '1';
if(debounce_pulse = '1')then
state <= check;
end if;
when check =>
if(input = '1')then
state <= debounced;
else
state <= idle;
end if;
when debounced =>
press <= '1';
state <= holding;
when holding =>
press <= '0';
hold_check <= '1';
if(hold_pulse = '1')then
state <= held;
end if;
when held =>
if(input = '1')then
state <= debounced;
else
state <= idle;
end if;
end case;
end if;
end process;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.Types.all;
use work.Consts.all;
use work.Funcs.all;
entity tbDataPath is
end tbDataPath;
architecture tb_data_path_arch of tbDataPath is
constant ADDR_SIZE : integer := C_SYS_ADDR_SIZE;
constant DATA_SIZE : integer := C_SYS_DATA_SIZE;
constant ISTR_SIZE : integer := C_SYS_ISTR_SIZE;
constant OPCD_SIZE : integer := C_SYS_OPCD_SIZE;
constant IMME_SIZE : integer := C_SYS_IMME_SIZE;
constant CWRD_SIZE : integer := C_SYS_CWRD_SIZE;
constant CALU_SIZE : integer := C_CTR_CALU_SIZE;
constant DRCW_SIZE : integer := C_CTR_DRCW_SIZE;
component DataPath is
generic (
ADDR_SIZE : integer := C_SYS_ADDR_SIZE;
DATA_SIZE : integer := C_SYS_DATA_SIZE;
ISTR_SIZE : integer := C_SYS_ISTR_SIZE;
OPCD_SIZE : integer := C_SYS_OPCD_SIZE;
IMME_SIZE : integer := C_SYS_IMME_SIZE;
CWRD_SIZE : integer := C_SYS_CWRD_SIZE; -- Datapath Contrl Word
CALU_SIZE : integer := C_CTR_CALU_SIZE;
DRCW_SIZE : integer := C_CTR_DRCW_SIZE
);
port (
clk : in std_logic;
rst : in std_logic;
istr_addr : out std_logic_vector(ADDR_SIZE-1 downto 0);
istr_val : in std_logic_vector(ISTR_SIZE-1 downto 0);
ir_out : out std_logic_vector(ISTR_SIZE-1 downto 0);
reg_a_out : out std_logic_vector(DATA_SIZE-1 downto 0);
data_addr : out std_logic_vector(ADDR_SIZE-1 downto 0);
data_i_val : in std_logic_vector(DATA_SIZE-1 downto 0);
data_o_val : out std_logic_vector(DATA_SIZE-1 downto 0);
cw : in std_logic_vector(CWRD_SIZE-1 downto 0);
dr_cw : out std_logic_vector(DRCW_SIZE-1 downto 0);
calu : in std_logic_vector(CALU_SIZE-1 downto 0)
);
end component;
signal clk : std_logic := '0';
signal rst : std_logic;
signal istr_addr : std_logic_vector(ADDR_SIZE-1 downto 0);
signal istr_val : std_logic_vector(ISTR_SIZE-1 downto 0);
signal ir_out : std_logic_vector(ISTR_SIZE-1 downto 0);
signal reg_a_out : std_logic_vector(DATA_SIZE-1 downto 0);
signal data_addr : std_logic_vector(ADDR_SIZE-1 downto 0);
signal data_i_val : std_logic_vector(DATA_SIZE-1 downto 0);
signal data_o_val : std_logic_vector(DATA_SIZE-1 downto 0);
signal cw : std_logic_vector(CWRD_SIZE-1 downto 0);
signal dr_cw : std_logic_vector(DRCW_SIZE-1 downto 0);
signal calu : std_logic_vector(CALU_SIZE-1 downto 0);
begin
DP: DataPath
port map(clk,rst,istr_addr,istr_val,ir_out,reg_a_out,data_addr,data_i_val,data_o_val,cw,dr_cw,calu);
CLK0: process(clk)
begin
clk <= not (clk) after 0.5 ns;
end process;
rst <= '0', '1' after 1 ns;
istr_val <= x"20410001", x"20420002" after 2 ns, x"20430003" after 3 ns, x"20440004" after 4 ns;
data_i_val <= x"00000000";
cw <= "1010101000011";
calu <= "00000";
end tb_data_path_arch;
configuration tb_data_path_cfg of tbDataPath is
for tb_data_path_arch
end for;
end tb_data_path_cfg;
|
library verilog;
use verilog.vl_types.all;
entity finalproject_mm_interconnect_0_router_002 is
port(
clk : in vl_logic;
reset : in vl_logic;
sink_valid : in vl_logic;
sink_data : in vl_logic_vector(104 downto 0);
sink_startofpacket: in vl_logic;
sink_endofpacket: in vl_logic;
sink_ready : out vl_logic;
src_valid : out vl_logic;
src_data : out vl_logic_vector(104 downto 0);
src_channel : out vl_logic_vector(5 downto 0);
src_startofpacket: out vl_logic;
src_endofpacket : out vl_logic;
src_ready : in vl_logic
);
end finalproject_mm_interconnect_0_router_002;
|
library verilog;
use verilog.vl_types.all;
entity arm_n_cntr is
port(
clk : in vl_logic;
reset : in vl_logic;
cout : out vl_logic;
modulus : in vl_logic_vector(31 downto 0)
);
end arm_n_cntr;
|
-------------------------------------------------------------------------------
-- Entity: cpu_ctrl
-- Author: Waj
-------------------------------------------------------------------------------
-- Description:
-- Control unit without instruction pipelining for the RISC-CPU of the
-- von-Neuman MCU.
-------------------------------------------------------------------------------
-- Total # of FFs: (2*16 + 2) + 3
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity cpu_ctrl is
port(rst : in std_logic;
clk : in std_logic;
-- bus interface signals
data_in : in std_logic_vector(DW-1 downto 0);
addr : out std_logic_vector(AW-1 downto 0);
data_out : out std_logic_vector(DW-1 downto 0);
r_wb : out std_logic;
-- CPU internal interfaces
reg_in : in t_reg2ctr;
reg_out : out t_ctr2reg;
prc_in : in t_prc2ctr;
prc_out : out t_ctr2prc;
alu_in : in t_alu2ctr;
alu_out : out t_ctr2alu
);
end cpu_ctrl;
architecture rtl of cpu_ctrl is
-- FSM signals
type state is (s_if, s_id, s_ex, s_ma, s_rw);
signal c_st, n_st : state;
-- Instruction register & decoding
signal instr_reg : std_logic_vector(DW-1 downto 0);
signal instr_enb : std_logic;
-- register write enable signals registered
signal reg_enb_low : std_logic;
signal reg_enb_high : std_logic;
-- opcode signal decoded from instruction register(used in several processes)
-- This signal could be of type t_instr when using 'val attribute,
-- but this is not supported by ISE XST.
-- t_instr'val(to_integer(unsigned(instr_reg(DW-1 downto DW-(OPCW-OPAW)))))
signal opcode : natural range 0 to 2**DW-1;
begin
-----------------------------------------------------------------------------
-- Bus Interface
-----------------------------------------------------------------------------
data_out <= reg_in.data;
-----------------------------------------------------------------------------
-- PC Interface
-----------------------------------------------------------------------------
prc_out.addr <= instr_reg(AW-1 downto 0);
-----------------------------------------------------------------------------
-- Instruction register & data register to Register Block
-----------------------------------------------------------------------------
P_ir: process(clk)
begin
if rising_edge(clk) then
-- instruction register
if instr_enb = '1' then
instr_reg <= data_in;
end if;
-- write enable and data signals to reg block; registered to break comb.
-- path from ROM to register block
reg_out.enb_data_low <= reg_enb_low;
reg_out.enb_data_high <= reg_enb_high;
if opcode = 16 then
-- load instruction, register low & high byte from bus system
reg_out.data <= data_in;
elsif opcode = 15 then
-- setih instruction, register low byte from instr. reg as high byte
reg_out.data(DW-1 downto DW/2) <= instr_reg(DW/2-1 downto 0);
else
-- e.g. setil instruction, register low byte from instr. reg as low byte
reg_out.data <= instr_reg;
end if;
end if;
end process;
-- Instruction register decoding
opcode <= to_integer(unsigned(instr_reg(DW-1 downto DW-OPCW)));
alu_out.op <= instr_reg(DW-1-(OPCW-OPAW) downto DW-OPCW);
alu_out.imm <= instr_reg(IOWW-1 downto 0);
reg_out.dest <= instr_reg(10 downto 8);
reg_out.src1 <= instr_reg(10 downto 8) when (opcode = 12 or opcode = 13) else
instr_reg( 7 downto 5);
reg_out.src2 <= instr_reg( 4 downto 2);
-----------------------------------------------------------------------------
-- FSM: Mealy-type
-- Inputs : c_st, opcode
-- Outputs: n_st, r_wb, instr_enb, reg_out.enb_res, reg_enb_low,
-- reg_enb_high, alu_out.enb, prc_out.enb, prc_out.mode
-----------------------------------------------------------------------------
-- memoryless process
p_fsm_com: process (c_st, opcode, alu_in, reg_in, prc_in)
begin
-- default assignments
n_st <= c_st; -- remain in current state
r_wb <= '1'; -- default: read
instr_enb <= '0';
reg_out.enb_res <= '0';
reg_enb_low <= '0';
reg_enb_high <= '0';
alu_out.enb <= '0';
prc_out.enb <= '0';
prc_out.mode <= linear;
addr <= (others => '1'); -- reset vector
-- specific assignments
case c_st is
when s_if =>
-- instruction fetch -------------------------------------------------
if prc_in.exc = no_err then
-- normal fetch if no exception, otherwise go to reset vector
addr <= prc_in.pc;
end if;
n_st <= s_id;
when s_id =>
-- instruction decode ------------------------------------------------
instr_enb <= '1';
n_st <= s_ex;
when s_ex =>
-- instruction execute -----------------------------------------------
if opcode <= 7 or opcode = 12 or opcode = 13 then
-- reg/reg-instruction or addil/h instruction
-- increase PC, store result/flags from ALU, start next instr. cycle
prc_out.enb <= '1';
reg_out.enb_res <= '1';
alu_out.enb <= '1';
n_st <= s_if;
elsif opcode = 14 then
-- setil instruction
-- increase PC, enable storage of low-byte, start next instr. cycle
prc_out.enb <= '1';
reg_enb_low <= '1';
n_st <= s_if;
elsif opcode = 15 then
-- setih instruction
-- increase PC, enable storage of high-byte, start next instr. cycle
prc_out.enb <= '1';
reg_enb_high <= '1';
n_st <= s_if;
elsif opcode = 16 or opcode = 17 then
-- load/store instruction
-- increase PC, go to "Memory Access" state
prc_out.enb <= '1';
n_st <= s_ma;
elsif opcode = 24 then
-- jump instruction
-- set PC to absolute address, start next instr. cycle
prc_out.enb <= '1';
prc_out.mode <= abs_jump;
n_st <= s_if;
elsif opcode >= 25 and opcode <= 29 then
-- branch instructions
prc_out.enb <= '1';
n_st <= s_if;
-- bne: branch if not equal (not Z)
if opcode = 25 and alu_in.flag(Z) = '0' then
prc_out.mode <= rel_offset;
end if;
-- bge: branch if greater/equal (not N or Z)
if opcode = 26 and (alu_in.flag(N) = '0' or alu_in.flag(Z) = '1') then
prc_out.mode <= rel_offset;
end if;
-- blt: branch if less than (N)
if opcode = 27 and alu_in.flag(N) = '1' then
prc_out.mode <= rel_offset;
end if;
-- bca: branch if carry set (C)
if opcode = 28 and alu_in.flag(C) = '1' then
prc_out.mode <= rel_offset;
end if;
-- bov: branch if overflow set (O)
if opcode = 29 and alu_in.flag(O) = '1' then
prc_out.mode <= rel_offset;
end if;
else
-- NOP instruction
prc_out.enb <= '1';
n_st <= s_if;
end if;
when s_ma =>
-- memory access ---------------------------------------------------
if opcode = 16 then
-- load instruction
-- read data from memory and go to "Register Write-Back" state
n_st <= s_rw;
else
-- store instruction
-- write data from register to memory and start next instr. cycle
r_wb <= '0'; -- active-low write
n_st <= s_if;
end if;
addr <= reg_in.addr;
when s_rw =>
-- register write-back --------------------------------------------
-- store data from memory in register and start next instr. cycle
reg_enb_low <= '1';
reg_enb_high <= '1';
n_st <= s_if;
when others =>
n_st <= s_if; -- handle parasitic states
end case;
end process;
-------------------------------------------------------------------------
-- sequential process
-- # of FFs: 3 (assuming binary state encoding)
P_fsm_seq: process(rst, clk)
begin
if rst = '1' then
c_st <= s_if;
elsif rising_edge(clk) then
c_st <= n_st;
end if;
end process;
end rtl;
|
-------------------------------------------------------------------------------
-- Entity: cpu_ctrl
-- Author: Waj
-------------------------------------------------------------------------------
-- Description:
-- Control unit without instruction pipelining for the RISC-CPU of the
-- von-Neuman MCU.
-------------------------------------------------------------------------------
-- Total # of FFs: (2*16 + 2) + 3
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity cpu_ctrl is
port(rst : in std_logic;
clk : in std_logic;
-- bus interface signals
data_in : in std_logic_vector(DW-1 downto 0);
addr : out std_logic_vector(AW-1 downto 0);
data_out : out std_logic_vector(DW-1 downto 0);
r_wb : out std_logic;
-- CPU internal interfaces
reg_in : in t_reg2ctr;
reg_out : out t_ctr2reg;
prc_in : in t_prc2ctr;
prc_out : out t_ctr2prc;
alu_in : in t_alu2ctr;
alu_out : out t_ctr2alu
);
end cpu_ctrl;
architecture rtl of cpu_ctrl is
-- FSM signals
type state is (s_if, s_id, s_ex, s_ma, s_rw);
signal c_st, n_st : state;
-- Instruction register & decoding
signal instr_reg : std_logic_vector(DW-1 downto 0);
signal instr_enb : std_logic;
-- register write enable signals registered
signal reg_enb_low : std_logic;
signal reg_enb_high : std_logic;
-- opcode signal decoded from instruction register(used in several processes)
-- This signal could be of type t_instr when using 'val attribute,
-- but this is not supported by ISE XST.
-- t_instr'val(to_integer(unsigned(instr_reg(DW-1 downto DW-(OPCW-OPAW)))))
signal opcode : natural range 0 to 2**DW-1;
begin
-----------------------------------------------------------------------------
-- Bus Interface
-----------------------------------------------------------------------------
data_out <= reg_in.data;
-----------------------------------------------------------------------------
-- PC Interface
-----------------------------------------------------------------------------
prc_out.addr <= instr_reg(AW-1 downto 0);
-----------------------------------------------------------------------------
-- Instruction register & data register to Register Block
-----------------------------------------------------------------------------
P_ir: process(clk)
begin
if rising_edge(clk) then
-- instruction register
if instr_enb = '1' then
instr_reg <= data_in;
end if;
-- write enable and data signals to reg block; registered to break comb.
-- path from ROM to register block
reg_out.enb_data_low <= reg_enb_low;
reg_out.enb_data_high <= reg_enb_high;
if opcode = 16 then
-- load instruction, register low & high byte from bus system
reg_out.data <= data_in;
elsif opcode = 15 then
-- setih instruction, register low byte from instr. reg as high byte
reg_out.data(DW-1 downto DW/2) <= instr_reg(DW/2-1 downto 0);
else
-- e.g. setil instruction, register low byte from instr. reg as low byte
reg_out.data <= instr_reg;
end if;
end if;
end process;
-- Instruction register decoding
opcode <= to_integer(unsigned(instr_reg(DW-1 downto DW-OPCW)));
alu_out.op <= instr_reg(DW-1-(OPCW-OPAW) downto DW-OPCW);
alu_out.imm <= instr_reg(IOWW-1 downto 0);
reg_out.dest <= instr_reg(10 downto 8);
reg_out.src1 <= instr_reg(10 downto 8) when (opcode = 12 or opcode = 13) else
instr_reg( 7 downto 5);
reg_out.src2 <= instr_reg( 4 downto 2);
-----------------------------------------------------------------------------
-- FSM: Mealy-type
-- Inputs : c_st, opcode
-- Outputs: n_st, r_wb, instr_enb, reg_out.enb_res, reg_enb_low,
-- reg_enb_high, alu_out.enb, prc_out.enb, prc_out.mode
-----------------------------------------------------------------------------
-- memoryless process
p_fsm_com: process (c_st, opcode, alu_in, reg_in, prc_in)
begin
-- default assignments
n_st <= c_st; -- remain in current state
r_wb <= '1'; -- default: read
instr_enb <= '0';
reg_out.enb_res <= '0';
reg_enb_low <= '0';
reg_enb_high <= '0';
alu_out.enb <= '0';
prc_out.enb <= '0';
prc_out.mode <= linear;
addr <= (others => '1'); -- reset vector
-- specific assignments
case c_st is
when s_if =>
-- instruction fetch -------------------------------------------------
if prc_in.exc = no_err then
-- normal fetch if no exception, otherwise go to reset vector
addr <= prc_in.pc;
end if;
n_st <= s_id;
when s_id =>
-- instruction decode ------------------------------------------------
instr_enb <= '1';
n_st <= s_ex;
when s_ex =>
-- instruction execute -----------------------------------------------
if opcode <= 7 or opcode = 12 or opcode = 13 then
-- reg/reg-instruction or addil/h instruction
-- increase PC, store result/flags from ALU, start next instr. cycle
prc_out.enb <= '1';
reg_out.enb_res <= '1';
alu_out.enb <= '1';
n_st <= s_if;
elsif opcode = 14 then
-- setil instruction
-- increase PC, enable storage of low-byte, start next instr. cycle
prc_out.enb <= '1';
reg_enb_low <= '1';
n_st <= s_if;
elsif opcode = 15 then
-- setih instruction
-- increase PC, enable storage of high-byte, start next instr. cycle
prc_out.enb <= '1';
reg_enb_high <= '1';
n_st <= s_if;
elsif opcode = 16 or opcode = 17 then
-- load/store instruction
-- increase PC, go to "Memory Access" state
prc_out.enb <= '1';
n_st <= s_ma;
elsif opcode = 24 then
-- jump instruction
-- set PC to absolute address, start next instr. cycle
prc_out.enb <= '1';
prc_out.mode <= abs_jump;
n_st <= s_if;
elsif opcode >= 25 and opcode <= 29 then
-- branch instructions
prc_out.enb <= '1';
n_st <= s_if;
-- bne: branch if not equal (not Z)
if opcode = 25 and alu_in.flag(Z) = '0' then
prc_out.mode <= rel_offset;
end if;
-- bge: branch if greater/equal (not N or Z)
if opcode = 26 and (alu_in.flag(N) = '0' or alu_in.flag(Z) = '1') then
prc_out.mode <= rel_offset;
end if;
-- blt: branch if less than (N)
if opcode = 27 and alu_in.flag(N) = '1' then
prc_out.mode <= rel_offset;
end if;
-- bca: branch if carry set (C)
if opcode = 28 and alu_in.flag(C) = '1' then
prc_out.mode <= rel_offset;
end if;
-- bov: branch if overflow set (O)
if opcode = 29 and alu_in.flag(O) = '1' then
prc_out.mode <= rel_offset;
end if;
else
-- NOP instruction
prc_out.enb <= '1';
n_st <= s_if;
end if;
when s_ma =>
-- memory access ---------------------------------------------------
if opcode = 16 then
-- load instruction
-- read data from memory and go to "Register Write-Back" state
n_st <= s_rw;
else
-- store instruction
-- write data from register to memory and start next instr. cycle
r_wb <= '0'; -- active-low write
n_st <= s_if;
end if;
addr <= reg_in.addr;
when s_rw =>
-- register write-back --------------------------------------------
-- store data from memory in register and start next instr. cycle
reg_enb_low <= '1';
reg_enb_high <= '1';
n_st <= s_if;
when others =>
n_st <= s_if; -- handle parasitic states
end case;
end process;
-------------------------------------------------------------------------
-- sequential process
-- # of FFs: 3 (assuming binary state encoding)
P_fsm_seq: process(rst, clk)
begin
if rst = '1' then
c_st <= s_if;
elsif rising_edge(clk) then
c_st <= n_st;
end if;
end process;
end rtl;
|
-----------------------------------------------------------------------
-- Design : Counter VHDL top module, SPEC (Simple PCIe Carrier)
-- Author : Javier D. Garcia-Lasheras
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity spec_top is
port (
clear_i: in std_logic;
count_i: in std_logic;
clock_i: in std_logic;
led_o: out std_logic_vector(3 downto 0)
);
end spec_top;
-----------------------------------------------------------------------
architecture structure of spec_top is
component counter
port (
clock: in std_logic;
clear: in std_logic;
count: in std_logic;
Q: out std_logic_vector(7 downto 0)
);
end component;
signal s_clock: std_logic;
signal s_clear: std_logic;
signal s_count: std_logic;
signal s_Q: std_logic_vector(7 downto 0);
begin
U_counter: counter
port map (
clock => s_clock,
clear => s_clear,
count => s_count,
Q => s_Q
);
s_clock <= clock_i;
s_clear <= not clear_i;
s_count <= not count_i;
led_o(3 downto 0) <= not s_Q(7 downto 4);
end architecture structure;
-----------------------------------------------------------------------
|
-----------------------------------------------------------------------
-- Design : Counter VHDL top module, SPEC (Simple PCIe Carrier)
-- Author : Javier D. Garcia-Lasheras
-----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity spec_top is
port (
clear_i: in std_logic;
count_i: in std_logic;
clock_i: in std_logic;
led_o: out std_logic_vector(3 downto 0)
);
end spec_top;
-----------------------------------------------------------------------
architecture structure of spec_top is
component counter
port (
clock: in std_logic;
clear: in std_logic;
count: in std_logic;
Q: out std_logic_vector(7 downto 0)
);
end component;
signal s_clock: std_logic;
signal s_clear: std_logic;
signal s_count: std_logic;
signal s_Q: std_logic_vector(7 downto 0);
begin
U_counter: counter
port map (
clock => s_clock,
clear => s_clear,
count => s_count,
Q => s_Q
);
s_clock <= clock_i;
s_clear <= not clear_i;
s_count <= not count_i;
led_o(3 downto 0) <= not s_Q(7 downto 4);
end architecture structure;
-----------------------------------------------------------------------
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_8_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 05:50:09 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../generic.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_8_e-rtl-a.vhd,v 1.4 2006/06/26 07:42:18 wig Exp $
-- $Date: 2006/06/26 07:42:18 $
-- $Log: inst_8_e-rtl-a.vhd,v $
-- Revision 1.4 2006/06/26 07:42:18 wig
-- Updated io, generic and mde_tests testcases
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_8_e
--
architecture rtl of inst_8_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
---------------------------------------------------------------------------------------------------
-- divider_f2m.vhd ---
----------------------------------------------------------------------------------------------------
-- Author : Miguel Morales-Sandoval ---
-- Project : "Hardware Arquitecture for ECC and Lossless Data Compression ---
-- Organization : INAOE, Computer Science Department ---
-- Date : July, 2004. ---
----------------------------------------------------------------------------------------------------
-- Inverter for F_2^m
----------------------------------------------------------------------------------------------------
-- Coments: This is an implementation of the division algorithm. Dirent to the other implemented inverter
-- in this, the division is performed directly.
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;
----------------------------------------------------------------------------------------------------
entity f2m_divider_277 is
generic(
NUM_BITS : positive := 277
);
port(
x : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
y : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
done : out STD_LOGIC;
Ux : out STD_LOGIC_VECTOR(NUM_BITS-1 downto 0) -- U = x/y mod Fx,
);
end;
----------------------------------------------------------------------------------------------------
architecture behave of f2m_divider_277 is
----------------------------------------------------------------------------------------------------
-- Signal for up-date regsiters A and B
signal A,B : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
signal U, V : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
----------------------------------------------------------------------------------------------------
-- m = 163, the irreductible polynomial
--constant F : std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011001001";
-- m = 233 x233 + x74 + 1
--constant F: std_logic_vector(NUM_BITS downto 0) := "100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000001";
-- m = 277 x277 + x74 + 1
constant F: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000001001001"; --277 bits
-- m = 283 x283 + x12 + x7 + x5 + 1
--constant F: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000010100001";
-- m = 409 x409 + x87 + 1
--constant F: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
-- m = 571 x571 + x10 + x5 + x2 + 1
--constant F: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000100101";
----------------------------------------------------------------------------------------------------
-- control signals
signal a_greater_b, a_eq_b, A_par, B_par, U_par, V_par, u_mas_v_par: std_logic;
signal A_div_t, B_div_t, U_div_t, V_div_t : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
signal u_mas_M, v_mas_M, u_mas_v, u_mas_v_mas_M, a_mas_b : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
signal u_mas_M_div_t, v_mas_M_div_t, u_mas_v_div_t, u_mas_v_mas_M_div_t, a_mas_b_div_t: STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
----------------------------------------------------------------------------------------------------------------------------------------------------------
type CurrentState_type is (END_STATE, INIT, CYCLE);
signal currentState: CurrentState_type;
----------------------------------------------------------------------------------------------------
begin
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
-- Control signals
A_par <= '1' when A(0) = '0' else
'0';
B_par <= '1' when B(0) = '0' else
'0';
U_par <= '1' when U(0) = '0' else
'0';
V_par <= '1' when V(0) = '0' else
'0';
a_greater_b <= '1' when A > B else
'0';
a_eq_b <= '1' when A = B else
'0';
----------------------------------------------------------------------------------------------------
-- Mux definitions
----------------------------------------------------------------------------------------------------
u_mas_M <= U xor F;
v_mas_M <= V xor F;
u_mas_v <= U xor V;
u_mas_v_mas_M <= u_mas_v xor F;
a_mas_b <= A xor B;
-- Muxes for A and B
a_div_t <= '0'& A(NUM_BITS downto 1);
b_div_t <= '0'& B(NUM_BITS downto 1);
u_div_t <= '0'& U(NUM_BITS downto 1);
v_div_t <= '0'& V(NUM_BITS downto 1);
u_mas_M_div_t <= '0' & u_mas_M(NUM_BITS downto 1);
v_mas_M_div_t <= '0' & v_mas_M(NUM_BITS downto 1);
u_mas_v_div_t <= '0' & u_mas_v(NUM_BITS downto 1);
u_mas_v_mas_M_div_t <= '0' & u_mas_v_mas_M(NUM_BITS downto 1);
a_mas_b_div_t <= '0' & a_mas_b(NUM_BITS downto 1);
----------------------------------------------------------------------------------------------------
-- Finite state machine
----------------------------------------------------------------------------------------------------
EEAL: process (clk)
begin -- syncronous reset
if CLK'event and CLK = '1' then
if (rst = '1')then
A <= '0' & y;
B <= F;
U <= '0' & x;
v <= (others => '0');
Ux <= (others => '0');
done <= '0';
currentState <= CYCLE;
else
case currentState is
-----------------------------------------------------------------------------------
when CYCLE =>
if A_eq_B = '1' then
currentState <= END_STATE;
Done <= '1';
Ux <= U(NUM_BITS-1 downto 0);
elsif A_par = '1' then
A <= A_div_t;
if U_par = '1' then
U <= U_div_t;
else
U <= u_mas_M_div_t;
end if;
elsif B_par = '1' then
B <= B_div_t;
if V_par = '1' then
V <= V_div_t;
else
V <= V_mas_M_div_t;
end if;
elsif a_greater_b = '1' then
A <= a_mas_b_div_t;
if u_mas_v(0) = '0' then
U <= u_mas_v_div_t;
else
U <= u_mas_v_mas_M_div_t;
end if;
else
B <= a_mas_b_div_t;
if u_mas_v(0) = '0' then
V <= u_mas_v_div_t;
else
V <= u_mas_v_mas_M_div_t;
end if;
end if;
-----------------------------------------------------------------------------------
when END_STATE => -- Do nothing
currentState <= END_STATE;
done <= '0'; -- para generar el pulso, quitarlo entity caso contrario
-----------------------------------------------------------------------------------
when others =>
null;
end case;
end if;
end if;
end process;
end behave; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3051.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s02b04x00p03n01i03051ent IS
END c12s02b04x00p03n01i03051ent;
ARCHITECTURE c12s02b04x00p03n01i03051arch OF c12s02b04x00p03n01i03051ent IS
signal si:integer := 14;
signal sr:real := 1.4;
signal sb:bit := '0';
BEGIN
-- test for middle port associated
bl3: block
port (i:integer:=4;r:real:=6.4;b:bit:='1');
port map (r=>sr);
begin
assert (i=4)
report "Default expression for unassociated integer port I incorrect"
severity failure;
assert (b='1')
report "Default expression for unassociated bit port B incorrect"
severity failure;
TESTING: PROCESS
BEGIN
assert NOT( i=4 and r=1.4 and b='1' )
report "***PASSED TEST: c12s02b04x00p03n01i03051"
severity NOTE;
assert ( i=4 and r=1.4 and b='1' )
report "***FAILED TEST: c12s02b04x00p03n01i03051 - Unassociated and associated ports are not correctly evaluated for the ports of a block."
severity ERROR;
wait;
END PROCESS TESTING;
end block;
END c12s02b04x00p03n01i03051arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3051.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s02b04x00p03n01i03051ent IS
END c12s02b04x00p03n01i03051ent;
ARCHITECTURE c12s02b04x00p03n01i03051arch OF c12s02b04x00p03n01i03051ent IS
signal si:integer := 14;
signal sr:real := 1.4;
signal sb:bit := '0';
BEGIN
-- test for middle port associated
bl3: block
port (i:integer:=4;r:real:=6.4;b:bit:='1');
port map (r=>sr);
begin
assert (i=4)
report "Default expression for unassociated integer port I incorrect"
severity failure;
assert (b='1')
report "Default expression for unassociated bit port B incorrect"
severity failure;
TESTING: PROCESS
BEGIN
assert NOT( i=4 and r=1.4 and b='1' )
report "***PASSED TEST: c12s02b04x00p03n01i03051"
severity NOTE;
assert ( i=4 and r=1.4 and b='1' )
report "***FAILED TEST: c12s02b04x00p03n01i03051 - Unassociated and associated ports are not correctly evaluated for the ports of a block."
severity ERROR;
wait;
END PROCESS TESTING;
end block;
END c12s02b04x00p03n01i03051arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3051.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s02b04x00p03n01i03051ent IS
END c12s02b04x00p03n01i03051ent;
ARCHITECTURE c12s02b04x00p03n01i03051arch OF c12s02b04x00p03n01i03051ent IS
signal si:integer := 14;
signal sr:real := 1.4;
signal sb:bit := '0';
BEGIN
-- test for middle port associated
bl3: block
port (i:integer:=4;r:real:=6.4;b:bit:='1');
port map (r=>sr);
begin
assert (i=4)
report "Default expression for unassociated integer port I incorrect"
severity failure;
assert (b='1')
report "Default expression for unassociated bit port B incorrect"
severity failure;
TESTING: PROCESS
BEGIN
assert NOT( i=4 and r=1.4 and b='1' )
report "***PASSED TEST: c12s02b04x00p03n01i03051"
severity NOTE;
assert ( i=4 and r=1.4 and b='1' )
report "***FAILED TEST: c12s02b04x00p03n01i03051 - Unassociated and associated ports are not correctly evaluated for the ports of a block."
severity ERROR;
wait;
END PROCESS TESTING;
end block;
END c12s02b04x00p03n01i03051arch;
|
-------------------------------------------------------------------------------
-- Title : MIPS Processor
-- Project :
-------------------------------------------------------------------------------
-- File : MIPS_CPU.vhd
-- Author : Robert Jarzmik <[email protected]>
-- Company :
-- Created : 2016-11-11
-- Last update: 2017-01-04
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: A MIPS v1 processor, not pipelined
-------------------------------------------------------------------------------
-- Copyright (c) 2016
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2016-11-11 1.0 rj Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.cpu_defs.all;
use work.cache_defs.all;
use work.instruction_defs.instr_tag_t;
use work.instruction_prediction.prediction_t;
-------------------------------------------------------------------------------
entity MIPS_CPU is
generic (
ADDR_WIDTH : integer := 32;
DATA_WIDTH : integer := 32;
NB_REGISTERS_GP : positive := 32; -- r0 to r31
NB_REGISTERS_SPECIAL : positive := 2 -- mflo and mfhi
);
port (
clk : in std_logic;
rst : in std_logic;
-- L2 cache lines
o_creq : out cache_request_t;
i_cresp : in cache_response_t;
-- Temprorary Data Memory interface
o_mem_addr : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
i_mem_rd_valid : in std_logic;
i_mem_rd_data : in std_logic_vector(DATA_WIDTH - 1 downto 0);
o_mem_wr_en : out std_logic;
o_mem_word_width : out std_logic;
o_mem_wr_data : out std_logic_vector(DATA_WIDTH - 1 downto 0);
i_mem_wr_ack : in std_logic;
-- Debug signals
signal o_dbg_if_pc : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal o_dbg_di_pc : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal o_dbg_ex_pc : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal o_dbg_mem_m0_pc : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal o_dbg_mem_m1_pc : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal o_dbg_mem_m2_pc : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal o_dbg_wb_pc : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal o_dbg_commited_pc : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal o_dbg_ife_killed : out std_logic;
signal o_dbg_di_killed : out std_logic;
signal o_dbg_ex_killed : out std_logic;
signal o_dbg_mem_killed : out std_logic;
signal o_dbg_wb_killed : out std_logic;
signal o_dbg_pc_stalled : out std_logic;
signal o_dbg_ife_stalled : out std_logic;
signal o_dbg_di_stalled : out std_logic;
signal o_dbg_ex_stalled : out std_logic;
signal o_dbg_mem_stalled : out std_logic;
signal o_dbg_wb_stalled : out std_logic;
signal o_dbg_jump_pc : out std_logic;
signal o_dbg_jump_target : out std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal o_dbg_commited_instr_tag : out instr_tag_t;
signal o_dbg_wb2di_reg1 : out register_port_type;
signal o_dbg_wb2di_reg2 : out register_port_type;
signal o_dbg_if_instr_tag : out instr_tag_t;
signal o_dbg_di_instr_tag : out instr_tag_t;
signal o_dbg_ex_instr_tag : out instr_tag_t;
signal o_dbg_mem_m0_instr_tag : out instr_tag_t;
signal o_dbg_mem_m1_instr_tag : out instr_tag_t;
signal o_dbg_mem_m2_instr_tag : out instr_tag_t;
signal o_dbg_wb_instr_tag : out instr_tag_t;
signal o_dbg_if_prediction : out prediction_t
);
end entity MIPS_CPU;
-------------------------------------------------------------------------------
architecture rtl of MIPS_CPU is
-----------------------------------------------------------------------------
-- Internal signal declarations
-----------------------------------------------------------------------------
signal current_pc : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal next_pc : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal jump_target : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal fetched_instruction : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal fetched_pc : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal if_instr_tag : instr_tag_t;
signal di_instr_tag : instr_tag_t;
signal alu_op : alu_op_type;
signal di2ex_ra : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal di2ex_rb : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal di2ex_reg1 : register_port_type;
signal di2ex_reg1_we : std_logic;
signal di2ex_reg1_idx : natural range 0 to NB_REGISTERS_GP + NB_REGISTERS_SPECIAL - 1;
signal di2ex_reg2 : register_port_type;
signal di2ex_reg2_we : std_logic;
signal di2ex_reg2_idx : natural range 0 to NB_REGISTERS_GP + NB_REGISTERS_SPECIAL - 1;
signal di2ex_divide_0 : std_logic;
signal jump_pc : std_logic;
signal di2ctrl_reg1_idx : natural range 0 to NB_REGISTERS_GP + NB_REGISTERS_SPECIAL - 1;
signal di2ctrl_reg2_idx : natural range 0 to NB_REGISTERS_GP + NB_REGISTERS_SPECIAL - 1;
signal wb2di_reg1 : register_port_type;
signal wb2di_reg2 : register_port_type;
signal di2ex_jump_target : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal di2ex_jump_op : jump_type;
signal di2ex_mem_data : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal di2ex_mem_op : memory_op_type;
signal ex_instr_tag : instr_tag_t;
signal ex2mem_reg1 : register_port_type;
signal ex2mem_reg2 : register_port_type;
signal ex2mem_jump_target : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal ex2mem_is_jump : std_logic;
signal ex2mem_mem_data : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal ex2mem_mem_op : memory_op_type;
signal mem_instr_tag : instr_tag_t;
signal mem_m0_instr_tag : instr_tag_t;
signal mem_m1_instr_tag : instr_tag_t;
signal mem_m2_instr_tag : instr_tag_t;
signal mem2ctrl_stage1_reg1 : register_port_type;
signal mem2ctrl_stage1_reg2 : register_port_type;
signal mem2ctrl_stage2_reg1 : register_port_type;
signal mem2ctrl_stage2_reg2 : register_port_type;
signal mem2wb_reg1 : register_port_type;
signal mem2wb_reg2 : register_port_type;
signal mem2wb_jump_target : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal mem2wb_is_jump : std_logic;
signal wb_instr_tag : instr_tag_t;
signal wb_is_jump : std_logic;
signal wb_jump_target : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal commited_instr_tag : instr_tag_t;
-- Bypass signals
signal bp2di_reg1 : register_port_type;
signal bp2di_reg2 : register_port_type;
-- Control signals
--- Dependencies checkers
signal RaW_detected : std_logic;
signal mem2upstream_stall_req : std_logic;
--- Exception signals
signal mem_exception : std_logic;
--- Pipeline stage stallers
signal pc_stalled : std_logic;
signal ife_stalled : std_logic;
signal di_stalled : std_logic;
signal ex_stalled : std_logic;
signal mem_stalled : std_logic;
signal wb_stalled : std_logic;
--- Pipeline stage output killers (ie. "nop" replacement of stage output)
signal mispredict_kills_pipeline : std_logic;
signal ife_killed : std_logic;
signal di_killed : std_logic;
signal ex_killed : std_logic;
signal mem_killed : std_logic;
signal wb_killed : std_logic;
-- Debug signals
signal dbg_if_pc : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal dbg_di_pc : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal dbg_ex_pc : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal dbg_mem_m0_pc : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal dbg_mem_m1_pc : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal dbg_mem_m2_pc : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal dbg_wb_pc : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal dbg_commited_pc : std_logic_vector(ADDR_WIDTH - 1 downto 0);
signal dbg_if_prediction : prediction_t;
begin -- architecture rtl
-----------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------
ife : entity work.Fetch(rtl3)
generic map (
ADDR_WIDTH => ADDR_WIDTH,
DATA_WIDTH => DATA_WIDTH)
port map (
clk => clk,
rst => rst,
stall_req => ife_stalled,
kill_req => ife_killed,
o_instruction => fetched_instruction,
o_pc_instr => fetched_pc,
o_instr_tag => di_instr_tag,
o_mispredict_kill_pipeline => mispredict_kills_pipeline,
o_creq => o_creq,
i_cresp => i_cresp,
i_is_jump => wb_is_jump,
i_jump_target => wb_jump_target,
i_commited_instr_tag => commited_instr_tag,
o_dbg_if_fetching_pc => dbg_if_pc,
o_dbg_if_pc => dbg_di_pc,
o_dbg_if_fetching_instr_tag => if_instr_tag,
o_dbg_prediction => dbg_if_prediction);
di : entity work.Decode
generic map (
ADDR_WIDTH => ADDR_WIDTH,
DATA_WIDTH => DATA_WIDTH,
NB_REGISTERS => NB_REGISTERS_GP + NB_REGISTERS_SPECIAL,
NB_REGISTERS_SPECIAL => NB_REGISTERS_SPECIAL,
REG_IDX_MFLO => 32,
REG_IDX_MFHI => 33)
port map (
clk => clk,
rst => rst,
stall_req => di_stalled,
kill_req => di_killed,
i_instruction => fetched_instruction,
i_pc => fetched_pc,
i_instr_tag => di_instr_tag,
i_rwb_reg1 => wb2di_reg1,
i_rwb_reg2 => wb2di_reg2,
i_bp_reg1 => bp2di_reg1,
i_bp_reg2 => bp2di_reg2,
o_alu_op => alu_op,
o_reg1 => di2ex_reg1,
o_reg2 => di2ex_reg2,
o_jump_target => di2ex_jump_target,
o_jump_op => di2ex_jump_op,
o_mem_data => di2ex_mem_data,
o_mem_op => di2ex_mem_op,
o_divide_0 => di2ex_divide_0,
o_instr_tag => ex_instr_tag,
o_src_reg1_idx => di2ctrl_reg1_idx,
o_src_reg2_idx => di2ctrl_reg2_idx,
i_dbg_di_pc => dbg_di_pc,
o_dbg_di_pc => dbg_ex_pc);
ex : entity work.ALU
generic map (
ADDR_WIDTH => ADDR_WIDTH,
DATA_WIDTH => DATA_WIDTH,
NB_REGISTERS => NB_REGISTERS_GP + NB_REGISTERS_SPECIAL)
port map (
clk => clk,
rst => rst,
stall_req => ex_stalled,
kill_req => ex_killed,
alu_op => alu_op,
i_reg1 => di2ex_reg1,
i_reg2 => di2ex_reg2,
i_jump_target => di2ex_jump_target,
i_jump_op => di2ex_jump_op,
i_mem_data => di2ex_mem_data,
i_mem_op => di2ex_mem_op,
i_instr_tag => ex_instr_tag,
i_divide_0 => di2ex_divide_0,
o_reg1 => ex2mem_reg1,
o_reg2 => ex2mem_reg2,
o_jump_target => ex2mem_jump_target,
o_is_jump => ex2mem_is_jump,
o_mem_data => ex2mem_mem_data,
o_mem_op => ex2mem_mem_op,
o_instr_tag => mem_m0_instr_tag,
i_dbg_ex_pc => dbg_ex_pc,
o_dbg_ex_pc => dbg_mem_m0_pc);
mem_stage : entity work.Memory_access
generic map (
ADDR_WIDTH => ADDR_WIDTH,
DATA_WIDTH => DATA_WIDTH)
port map (
clk => clk, -- input clk
rst => rst, -- input async reset
stall_req => mem_stalled,
kill_req => mem_killed,
o_exception => mem_exception,
i_reg1 => ex2mem_reg1,
i_reg2 => ex2mem_reg2,
i_mem_op => ex2mem_mem_op,
i_mem_data => ex2mem_mem_data,
i_is_jump => ex2mem_is_jump,
i_jump_target => ex2mem_jump_target,
i_instr_tag => mem_m0_instr_tag,
o_reg1 => mem2wb_reg1,
o_reg2 => mem2wb_reg2,
o_jump_target => mem2wb_jump_target,
o_is_jump => mem2wb_is_jump,
o_stage1_reg1 => mem2ctrl_stage1_reg1,
o_stage1_reg2 => mem2ctrl_stage1_reg2,
o_stage2_reg1 => mem2ctrl_stage2_reg1,
o_stage2_reg2 => mem2ctrl_stage2_reg2,
o_m0_instr_tag => mem_m1_instr_tag,
o_m1_instr_tag => mem_m2_instr_tag,
o_m2_instr_tag => wb_instr_tag,
-- Memory interface
i_mem_rd_valid => i_mem_rd_valid,
i_mem_rd_data => i_mem_rd_data,
o_mem_wr_en => o_mem_wr_en,
o_mem_word_width => o_mem_word_width,
i_mem_wr_ack => i_mem_wr_ack,
o_mem_addr => o_mem_addr,
o_mem_wr_data => o_mem_wr_data,
o_need_stall => mem2upstream_stall_req,
-- debug signals
i_dbg_mem_pc => dbg_mem_m0_pc,
o_dbg_mem0_pc => dbg_mem_m1_pc,
o_dbg_mem1_pc => dbg_mem_m2_pc,
o_dbg_mem2_pc => dbg_wb_pc);
wb : entity work.Writeback
generic map (
ADDR_WIDTH => ADDR_WIDTH,
DATA_WIDTH => DATA_WIDTH,
NB_REGISTERS => NB_REGISTERS_GP + NB_REGISTERS_SPECIAL)
port map (
clk => clk,
rst => rst,
stall_req => wb_stalled,
kill_req => wb_killed,
i_reg1 => mem2wb_reg1,
i_reg2 => mem2wb_reg2,
i_jump_target => mem2wb_jump_target,
i_is_jump => mem2wb_is_jump,
o_reg1 => wb2di_reg1,
o_reg2 => wb2di_reg2,
o_is_jump => wb_is_jump,
o_jump_target => wb_jump_target,
i_instr_tag => wb_instr_tag,
o_instr_tag => commited_instr_tag,
i_dbg_wb_pc => dbg_wb_pc,
o_dbg_wb_pc => dbg_commited_pc);
ctrl_decode_deps : entity work.Control_Decode_Dependencies
generic map (
NB_REGISTERS => NB_REGISTERS_GP + NB_REGISTERS_SPECIAL)
port map (
clk => clk,
rst => rst,
rsi => di2ctrl_reg1_idx,
rti => di2ctrl_reg2_idx,
i_di2ex_reg1 => di2ex_reg1,
i_di2ex_reg2 => di2ex_reg2,
i_ex2mem_reg1 => ex2mem_reg1,
i_ex2mem_reg2 => ex2mem_reg2,
i_mem2ctrl_stage1_reg1 => mem2ctrl_stage1_reg1,
i_mem2ctrl_stage1_reg2 => mem2ctrl_stage1_reg2,
i_mem2ctrl_stage2_reg1 => mem2ctrl_stage2_reg1,
i_mem2ctrl_stage2_reg2 => mem2ctrl_stage2_reg2,
i_mem2wb_reg1 => mem2wb_reg1,
i_mem2wb_reg2 => mem2wb_reg2,
i_wb2di_reg1 => wb2di_reg1,
i_wb2di_reg2 => wb2di_reg2,
o_raw_detected => RaW_detected);
bypass : entity work.Bypass
generic map (
NB_REGISTERS => NB_REGISTERS_GP + NB_REGISTERS_SPECIAL)
port map (
clk => clk,
rst => rst,
i_ex2mem_reg1 => ex2mem_reg1,
i_ex2mem_reg2 => ex2mem_reg2,
i_mem2m1_reg1 => mem2ctrl_stage1_reg1,
i_mem2m1_reg2 => mem2ctrl_stage1_reg2,
i_m12m2_reg1 => mem2ctrl_stage2_reg1,
i_m12m2_reg2 => mem2ctrl_stage2_reg2,
i_mem2wb_reg1 => mem2wb_reg1,
i_mem2wb_reg2 => mem2wb_reg2,
i_wb2di_reg1 => wb2di_reg1,
i_wb2di_reg2 => wb2di_reg2,
i_src_reg1_idx => di2ctrl_reg1_idx,
i_src_reg2_idx => di2ctrl_reg2_idx,
o_reg1 => bp2di_reg1,
o_reg2 => bp2di_reg2);
-- Control signals
pc_stalled <= mem2upstream_stall_req;
ife_stalled <= '1' when (RaW_detected = '1' and bp2di_reg1.we = '0' and bp2di_reg2.we = '0') or mem2upstream_stall_req = '1' else '0';
di_stalled <= mem2upstream_stall_req;
ex_stalled <= mem2upstream_stall_req;
mem_stalled <= '0';
wb_stalled <= '0';
ife_killed <= mispredict_kills_pipeline;
di_killed <= '1' when mispredict_kills_pipeline = '1' or (RaW_detected = '1' and bp2di_reg1.we = '0' and bp2di_reg2.we = '0') else '0';
mem_killed <= mispredict_kills_pipeline;
ex_killed <= mispredict_kills_pipeline;
wb_killed <= mispredict_kills_pipeline;
-- Debug signal
o_dbg_if_pc <= dbg_if_pc;
o_dbg_di_pc <= dbg_di_pc;
o_dbg_ex_pc <= dbg_ex_pc;
o_dbg_mem_m0_pc <= dbg_mem_m0_pc;
o_dbg_mem_m1_pc <= dbg_mem_m1_pc;
o_dbg_mem_m2_pc <= dbg_mem_m2_pc;
o_dbg_wb_pc <= dbg_wb_pc;
o_dbg_commited_pc <= dbg_commited_pc;
o_dbg_ife_killed <= ife_killed;
o_dbg_di_killed <= di_killed;
o_dbg_ex_killed <= ex_killed;
o_dbg_mem_killed <= mem_killed;
o_dbg_wb_killed <= wb_killed;
o_dbg_pc_stalled <= pc_stalled;
o_dbg_ife_stalled <= ife_stalled;
o_dbg_di_stalled <= di_stalled;
o_dbg_ex_stalled <= ex_stalled;
o_dbg_mem_stalled <= mem_stalled;
o_dbg_wb_stalled <= wb_stalled;
o_dbg_jump_pc <= wb_is_jump;
o_dbg_jump_target <= wb_jump_target;
o_dbg_commited_instr_tag <= commited_instr_tag;
o_dbg_wb2di_reg1 <= wb2di_reg1;
o_dbg_wb2di_reg2 <= wb2di_reg2;
o_dbg_if_instr_tag <= if_instr_tag;
o_dbg_di_instr_tag <= di_instr_tag;
o_dbg_ex_instr_tag <= ex_instr_tag;
o_dbg_mem_m0_instr_tag <= mem_m0_instr_tag;
o_dbg_mem_m1_instr_tag <= mem_m1_instr_tag;
o_dbg_mem_m2_instr_tag <= mem_m2_instr_tag;
o_dbg_wb_instr_tag <= wb_instr_tag;
o_dbg_if_prediction <= dbg_if_prediction;
end architecture rtl;
-------------------------------------------------------------------------------
|
-- Company: Team 5
-- Engineer:
-- -Timothy Doucette Jr
-- -Robert Mushrall III
-- -Christopher Parks
--
-- Create Date: 14:26:47 03/31/2016
-- Design Name:
-- Module Name: Instruction_Memory_TL - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Instruction_Memory_TL is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
RA : out STD_LOGIC_VECTOR (3 downto 0);
RB : out STD_LOGIC_VECTOR (3 downto 0);
OP : out STD_LOGIC_VECTOR (3 downto 0);
IMM : out STD_LOGIC_VECTOR (7 downto 0));
end Instruction_Memory_TL;
architecture Structural of Instruction_Memory_TL is
--Program counter
signal EN : STD_LOGIC := '1';
--signal RST : STD_LOGIC := '0';
signal INSADR :STD_LOGIC_VECTOR (4 downto 0) := (OTHERS => '0');
--INSTRUCTION MEMORY--
signal ADDRA : STD_LOGIC_VECTOR (4 downto 0) := (OTHERS => '0');
signal DINA : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
signal WEA: STD_LOGIC := '0';
signal DOUTA : STD_LOGIC_VECTOR (15 downto 0) := (OTHERS => '0');
begin
OP <= DOUTA(15 downto 12);
RA <= DOUTA(11 downto 8);
RB <= DOUTA(7 downto 4);
IMM <= DOUTA(7 downto 0);
U1: entity work.programCounter
generic map(PCWIDTH => 5)
port map(CLK => CLK,
EN => EN,
RST => RST,
INSADR => ADDRA);
U2: entity work.Instr_Mem
port map(CLKA => not CLK,
ADDRA => ADDRA ,
DINA => DINA,
WEA(0) => WEA,
DOUTA => DOUTA);
end Structural; |
------------------------------------------------------------------
-- Processador Intel 8086 arquiteturado em pipeline e simplificado
------------------------------------------------------------------
-- Desenvolvedores: Jimmy Pinto Stelzer, Bruno Goulart e Bruno Paes
-- Baseado no exemplo de implementação do MIPS dos professores Fernando Moraes e Ney Calazans.
------------------------------------------------------------------
------------------------
-- Definições Gerais
------------------------
library IEEE;
use IEEE.std_logic_1164.all;
package p_intel_8086 is
type instructions is
(JMP,CMP,JZ,LOOPNZ,HLT,ADD,MOVRR,MOVRI,MOVRM,NOP);
type microinstruction is record
op: instructions; -- meneumonicos
rsCode: STD_LOGIC_VECTOR (2 downto 0);
rdCode: STD_LOGIC_VECTOR (2 downto 0);
param: STD_LOGIC_VECTOR (31 downto 0);
modc: STD_LOGIC_VECTOR (1 downto 0);
w: std_logic;
ex: std_logic;
mem: std_logic;
wb: std_logic;
end record;
end p_intel_8086;
-------------------------------------
-- Registrador do pipeline
-------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.p_intel_8086.all;
entity regpl is
generic( INIT_VALUE : STD_LOGIC_VECTOR(83 downto 0) := (others=>'0') );
port( clock, reset, enable : in std_logic;
D : in STD_LOGIC_VECTOR (83 downto 0);
I : in instructions;
O : out instructions;
Q : out STD_LOGIC_VECTOR (83 downto 0)
);
end regpl;
architecture regpl of regpl is
begin
process(clock, reset)
begin
if reset = '1' then
Q <= INIT_VALUE(83 downto 0);
O <= NOP;
elsif clock'event and clock = '0' then
if enable = '1' then
Q <= D;
O <= I;
end if;
end if;
end process;
end regpl;
-------------------------------------
-- Registrador de 16bits para AX, BX, CX, DX, SP, BP, SI, DI, ES, DS, SS e ES.
-------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity reg16 is
generic( INIT_VALUE : STD_LOGIC_VECTOR(15 downto 0) := (others=>'0') );
port( clock, reset, enable : in std_logic;
D : in STD_LOGIC_VECTOR (15 downto 0);
Q : out STD_LOGIC_VECTOR (15 downto 0)
);
end reg16;
architecture reg16 of reg16 is
begin
process(clock, reset)
begin
if reset = '1' then
Q <= INIT_VALUE(15 downto 0);
elsif clock'event and clock = '0' then
if enable = '1' then
Q <= D;
end if;
end if;
end process;
end reg16;
-------------------------------------
-- Banco de Registradores
-------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use work.p_intel_8086.all;
entity reg_bank is
port( clock, reset, enable : in std_logic;
w : in std_logic;
RsCode, RdCode : in std_logic_vector( 2 downto 0);
RD : in std_logic_vector(15 downto 0);
R1, R2: out std_logic_vector(15 downto 0));
end reg_bank;
architecture reg_bank of reg_bank is
type bank is array(0 to 7) of std_logic_vector(15 downto 0);
signal reg : bank;
begin
g1: for i in 0 to 7 generate
rx: entity work.reg16 port map(clock=>clock, reset=>reset, enable=>'1', D=>RD, Q=>reg(i));
end generate g1;
R1 <= reg(CONV_INTEGER(RsCode)) when w='1' else --AX CX DX BX SP BP SI DI
"00000000" & reg(0)(7 downto 0) when CONV_INTEGER(RsCode)=0 and w='0' else --AL
"00000000" & reg(1)(7 downto 0) when CONV_INTEGER(RsCode)=0 and w='0' else --CL
"00000000" & reg(2)(7 downto 0) when CONV_INTEGER(RsCode)=0 and w='0' else --DL
"00000000" & reg(3)(7 downto 0) when CONV_INTEGER(RsCode)=0 and w='0' else --BL
"00000000" & reg(4)(15 downto 8) when CONV_INTEGER(RsCode)=0 and w='0' else --AH
"00000000" & reg(5)(15 downto 8) when CONV_INTEGER(RsCode)=0 and w='0' else --CH
"00000000" & reg(6)(15 downto 8) when CONV_INTEGER(RsCode)=0 and w='0' else --DH
"00000000" & reg(7)(15 downto 8) when CONV_INTEGER(RsCode)=0 and w='0'; --BH
R2 <= reg(CONV_INTEGER(RdCode)) when w='1' else --AX CX DX BX SP BP SI DI
"00000000" & reg(0)(7 downto 0) when CONV_INTEGER(RdCode)=0 and w='0' else --AL
"00000000" & reg(1)(7 downto 0) when CONV_INTEGER(RdCode)=0 and w='0' else --CL
"00000000" & reg(2)(7 downto 0) when CONV_INTEGER(RdCode)=0 and w='0' else --DL
"00000000" & reg(3)(7 downto 0) when CONV_INTEGER(RdCode)=0 and w='0' else --BL
"00000000" & reg(4)(15 downto 8) when CONV_INTEGER(RdCode)=0 and w='0' else --AH
"00000000" & reg(5)(15 downto 8) when CONV_INTEGER(RdCode)=0 and w='0' else --CH
"00000000" & reg(6)(15 downto 8) when CONV_INTEGER(RdCode)=0 and w='0' else --DH
"00000000" & reg(7)(15 downto 8) when CONV_INTEGER(RdCode)=0 and w='0'; --BH
end reg_bank;
-------------------------------------
-- ULA
-------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use work.p_intel_8086.all;
entity alu is
port( op1, op2 : in std_logic_vector(15 downto 0);
param : in std_logic_vector(31 downto 0);
dest : out std_logic_vector(15 downto 0);
opalu : in instructions;
w : in std_logic
);
end alu;
architecture alu of alu is
signal flags : std_logic_vector(15 downto 0) := (others=>'0');
signal soma : std_logic_vector(15 downto 0) := (others=>'0');
begin
-- FLAGS
soma <= (op1+op2);
-- ZF
flags(6) <= '1' when (op2-op1)=0 and (opalu=ADD or opalu=CMP or opalu=LOOPNZ) else
'0' when (op2-op1)/=0 and (opalu=ADD or opalu=CMP or opalu=LOOPNZ);
-- SF
flags(7) <= '1' when soma<0 and opalu=ADD else
'0' when soma>0 and opalu=ADD;
-- CF
flags(0) <= '1' when soma>255 and w='0' and opalu=ADD else
'0' when soma<255 and w='0' and opalu=ADD;
-- OF
flags(11) <= '1' when (soma<-128 or (op1+op2)>127) and w='0' and opalu=ADD else
'0' when (soma>-128 and (op1+op2)<127) and w='0' and opalu=ADD;
-- AF
flags(4) <= '1' when soma>65535 and w='1' and opalu=ADD else
'0' when soma<65535 and w='1' and opalu=ADD;
-- PF
flags(2) <= '1' when CONV_INTEGER(soma) mod 2=0 and w='0' and opalu=ADD else
'0' when CONV_INTEGER(soma) mod 2/=0 and w='0' and opalu=ADD;
--(JMP,CMP,JZ,LOOPNZ,HLT,ADD,MOVRR,MOVRI,MOVRM,NOP)
dest <=
op1 + op2 when opalu=ADD else
op2 when opalu=MOVRR else
param(31 downto 16) when opalu=MOVRI else
op1 - 2 when opalu=LOOPNZ else -- CX--
(others=>'1') when opalu=JZ and flags(6)='1' else -- seta dest
(others=>'0'); --nop, hlt, cmp, movrm, jmp,
end alu;
-----------------------------------------
-- Control
-----------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
use work.p_intel_8086.all;
entity control_unit is
port(clock, reset : in std_logic;
uins : out microinstruction;
ir : in std_logic_vector(39 downto 0)
);
end control_unit;
architecture control_unit of control_unit is
signal i : instructions;
signal di : std_logic;
begin
i <= MOVRI when ir(39 downto 36)="1011" else
MOVRR when ir(39 downto 34)="100010" else
ADD when ir(39 downto 34)="000000" else
CMP when ir(39 downto 34)="100000" else
MOVRM when ir(39 downto 33)="0110011" else
HLT when ir(39 downto 32)="11110100" else
LOOPNZ when ir(39 downto 32)="11100000" else
JZ when ir(39 downto 32)="01110100" else
JMP when ir(39 downto 32)="11101001" else
NOP;
uins.op <= i;
-- execution
uins.ex <= '1' when i/=NOP and i/=JMP else
'0';
-- write back
uins.wb <= '0' when i=NOP or i=HLT or i=JZ or i=CMP or i=JMP else
'1';
-- memory
uins.mem <= '1' when i=MOVRM else
'0';
-- w
uins.w <= ir(35) when i=MOVRI else
ir(32) when i=MOVRM or i=CMP or i=ADD or i=MOVRR else
--'1' when i=LOOPNZ else --?
'X'; --Unknown
-- mod
uins.modc <= ir(31 downto 30) when i=MOVRM or i=CMP or i=ADD or i=MOVRR else
"XX"; -- Unknown
-- di
di <= ir(33) when i=CMP or i=ADD or i=MOVRR else
'X';
-- rdCode
uins.rdCode <= ir(34 downto 32) when i=MOVRI else
ir(26 downto 24) when i=MOVRM or (di='1' and (i=CMP or i=ADD or i=MOVRR)) else
ir(29 downto 27) when di='0' and (i=CMP or i=ADD or i=MOVRR) else
"001" when i=LOOPNZ else
(others=>'X');
-- rsCode
uins.rsCode <= ir(26 downto 24) when i=MOVRM or (di='0' and (i=CMP or i=ADD or i=MOVRR)) else
ir(29 downto 27) when di='1' and (i=CMP or i=ADD or i=MOVRR) else
(others=>'X');
-- param -- usado para carregar as informações como offset(-low|-high), seg(-low|-high), data(-low|-high), addr(-low|-high), disp
uins.param <= "00000000" & "00000000" & "00000000" & ir(31 downto 24) when (i=JZ or i=LOOPNZ) and ir(31)='0' else
"11111111" & "11111111" & "11111111" & ir(31 downto 24) when (i=JZ or i=LOOPNZ) and ir(31)='1' else
"00000000" & "00000000" & "00000000" & ir(23 downto 16) when i=CMP and ir(23)='0' else
"11111111" & "11111111" & "11111111" & ir(23 downto 16) when i=CMP and ir(23)='1' else
"00000000" & ir(7 downto 0) & ir(15 downto 8) & ir(23 downto 16) when i=MOVRM and ir(23)='0' else
"11111111" & ir(7 downto 0) & ir(15 downto 8) & ir(23 downto 16) when i=MOVRM and ir(23)='1' else
ir(7 downto 0) & ir(15 downto 8) & ir(23 downto 16) & ir(31 downto 24) when i=MOVRI else
(others=>'X');
--39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24
--1 0 1 1 w d d d MOVRI Param(7-0 & 15-8 & 23-16 & 31-24) se w = 1 else Param(31-24)
--0 1 1 0 0 1 1 w m m s s s d d d MOVRM Param(7-0 & 15-8 & 23-16)
--1 0 0 0 0 0 di w m m s s s d d d CMP Param(23-16) se di = 0 inverte sss e ddd
--0 0 0 0 0 0 di w m m s s s d d d ADD Param() se di = 0 inverte sss e ddd
--1 0 0 0 1 0 di w m m s s s d d d MOVRR Param() se di = 0 inverte sss e ddd
--1 1 1 1 0 1 0 0 HLT
--1 1 1 0 0 0 0 0 LOOPNZ Param(31-24) | w = 1 | rd = 001
--0 1 1 1 0 1 0 0 JZ Param(31-24) | w=0
--1 1 1 0 1 0 0 1 JMP Param(7-0 & 15-8 & 23-16 & 31-24)
-- NOP
end control_unit;
---------------------------
-- BIU - Bus Interface Unit (simplificada)
---------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity biu is
port( addr : in std_logic_vector(19 downto 0); -- endereço
clock : in std_logic;
reset : in std_logic;
mode : in std_logic; -- modo -> 0 = leitura; 1 = escrita
mtype : in std_logic; -- tipo -> 0 = instruções; 1 = dados;
memc : inout std_logic_vector(0 to 1023); -- 1024bits -> 128bytes -- entrada e saida da memoria de instruções
memd : inout std_logic_vector(0 to 1023); -- 1024bits -> 128bytes -- entrada e saida da memoria de dados
datain : in std_logic_vector(39 downto 0); -- dados a serem gravados
dataout : out std_logic_vector(39 downto 0) -- dados lidos
);
end biu;
architecture biu of biu is
signal datai : std_logic_vector(39 downto 0);
signal posi : integer;
signal posf : integer;
begin
gen : process(clock,reset)
begin
if (reset = '1') then
datai <= (others=>'X');
posi <= 0;
posf <= 0;
elsif(clock'event and clock='1') then
case mtype is
when '0' => -- memoria de instruções
if mode='0' then -- leitura
posi <= CONV_INTEGER(addr);
posf <= CONV_INTEGER(addr) + 39;
datai <= memc(posi to posf);
elsif mode='1' then -- escrita
posi <= CONV_INTEGER(addr);
posf <= CONV_INTEGER(addr) + 39;
memc(posi to posf) <= datain;
end if;
when '1' => -- memoria de dados
if mode='0' then -- leitura
posi <= CONV_INTEGER(addr);
posf <= CONV_INTEGER(addr) + 39;
datai <= memd(posi to posf);
elsif mode='1' then -- escrita
posi <= CONV_INTEGER(addr);
posf <= CONV_INTEGER(addr) + 39;
memd(posi to posf) <= datain;
end if;
when others =>
datai <= (others=>'X');
end case;
end if;
end process;
dataout<= datai;
end biu;
--------------------------------
-- Chip
--------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
use work.p_intel_8086.all;
entity chip is
port( clock, reset : in std_logic;
memc : inout std_logic_vector(0 to 1023); -- 1024bits -> 128bytes -- entrada e saida da memoria de instruções
memd : inout std_logic_vector(0 to 1023) -- 1024bits -> 128bytes -- entrada e saida da memoria de dados
);
end chip;
architecture chip of chip is
signal IP,addr: std_logic_vector(19 downto 0) := (others=>'0');
signal mode,mtype,wrb,walu,enablerb: std_logic := 'X';
signal datain,dataout,ir: std_logic_vector(39 downto 0) := (others=>'X');
signal uins: microinstruction;
signal opalu: instructions;
signal RD,R1,R2,op1,op2,dest : std_logic_vector(15 downto 0);
signal param : std_logic_vector(31 downto 0);
signal RsCode, RdCode : std_logic_vector(2 downto 0);
begin
biu: entity work.biu port map(addr=>addr, clock=>clock, reset=>reset, mode=>mode, mtype=>mtype, memc=>memc, memd=>memd,datain=>datain,dataout=>dataout);
ctrl: entity work.control_unit port map(clock=>clock, reset=>reset, uins=>uins, ir=>ir);
alu: entity work.alu port map(op1=>op1, op2=>op2, param=>param, dest=>dest, opalu=>opalu, w=>walu);
rb: entity work.reg_bank port map(clock=>clock, reset=>reset, enable=>enablerb, w=>wrb, RsCode=>RsCode, RdCode=>RdCode, RD=>RD, R1=>R1,R2=>R2);
--entity regpl is
-- port( clock, reset, enable : in std_logic;
-- D : in STD_LOGIC_VECTOR (83 downto 0);
-- I : in instructions;
-- O : out instructions;
-- Q : out STD_LOGIC_VECTOR (83 downto 0)
-- );
end chip; |
-------------------------------------------------------------------------------
-- Copyright (c) 2014 Potential Ventures Ltd
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
-- * Neither the name of Potential Ventures Ltd nor
-- names of its contributors may be used to endorse or promote products
-- derived from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL POTENTIAL VENTURES LTD BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------
--
--
-- Endian swapping module.
--
-- Simple example with Avalon streaming interfaces and a CSR bus
--
-- Avalon-ST has readyLatency of 0
-- Avalon-MM has fixed readLatency of 1
--
-- Exposes 2 32-bit registers via the Avalon-MM interface
--
-- Address 0: bit 0 [R/W] byteswap enable
-- bits 31-1: [N/A] reserved
-- Adress 1: bits 31-0: [RO] packet count
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity endian_swapper_vhdl is
generic (
DATA_BYTES : integer := 8);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
stream_in_data : in std_ulogic_vector(DATA_BYTES*8-1 downto 0);
stream_in_empty : in std_ulogic_vector(2 downto 0);
stream_in_valid : in std_ulogic;
stream_in_startofpacket : in std_ulogic;
stream_in_endofpacket : in std_ulogic;
stream_in_ready : out std_ulogic;
stream_out_data : out std_ulogic_vector(DATA_BYTES*8-1 downto 0);
stream_out_empty : out std_ulogic_vector(2 downto 0);
stream_out_valid : out std_ulogic;
stream_out_startofpacket: out std_ulogic;
stream_out_endofpacket : out std_ulogic;
stream_out_ready : in std_ulogic;
csr_address : in std_ulogic_vector(1 downto 0);
csr_readdata : out std_ulogic_vector(31 downto 0);
csr_readdatavalid : out std_ulogic;
csr_read : in std_ulogic;
csr_write : in std_ulogic;
csr_waitrequest : out std_ulogic;
csr_writedata : in std_ulogic_vector(31 downto 0)
);
end;
architecture impl of endian_swapper_vhdl is
function byteswap(data : in std_ulogic_vector(63 downto 0)) return std_ulogic_vector is begin
return data(7 downto 0) &
data(15 downto 8) &
data(23 downto 16) &
data(31 downto 24) &
data(39 downto 32) &
data(47 downto 40) &
data(55 downto 48) &
data(63 downto 56);
end;
signal csr_waitrequest_int : std_ulogic;
signal stream_out_endofpacket_int: std_ulogic;
signal flush_pipe : std_ulogic;
signal in_packet : std_ulogic;
signal byteswapping : std_ulogic;
signal packet_count : unsigned(31 downto 0);
begin
process (clk, reset_n) begin
if (reset_n = '0') then
flush_pipe <= '0';
in_packet <= '0';
packet_count <= to_unsigned(0, 32);
elsif rising_edge(clk) then
if (flush_pipe = '1' and stream_out_ready = '1') then
flush_pipe <= stream_in_endofpacket and stream_in_valid and stream_out_ready;
elsif (flush_pipe = '0') then
flush_pipe <= stream_in_endofpacket and stream_in_valid and stream_out_ready;
end if;
if (stream_out_ready = '1' and stream_in_valid = '1') then
stream_out_empty <= stream_in_empty;
stream_out_startofpacket <= stream_in_startofpacket;
stream_out_endofpacket_int <= stream_in_endofpacket;
if (byteswapping = '0') then
stream_out_data <= stream_in_data;
else
stream_out_data <= byteswap(stream_in_data);
end if;
if (stream_in_startofpacket = '1' and stream_in_valid = '1') then
packet_count <= packet_count + 1;
in_packet <= '1';
end if;
if (stream_in_endofpacket = '1' and stream_in_valid = '1') then
in_packet <= '0';
end if;
end if;
end if;
end process;
stream_in_ready <= stream_out_ready;
stream_out_endofpacket <= stream_out_endofpacket_int;
stream_out_valid <= '1' when (stream_in_valid = '1' and stream_out_endofpacket_int = '0') or flush_pipe = '1' else '0';
-- Hold off CSR accesses during packet transfers to prevent changing of endian configuration mid-packet
csr_waitrequest_int <= '1' when reset_n = '0' or in_packet = '1' or (stream_in_startofpacket = '1' and stream_in_valid = '1') or flush_pipe = '1' else '0';
csr_waitrequest <= csr_waitrequest_int;
process (clk, reset_n) begin
if (reset_n = '0') then
byteswapping <= '0';
csr_readdatavalid <= '0';
elsif rising_edge(clk) then
if (csr_read = '1') then
csr_readdatavalid <= not csr_waitrequest_int;
case csr_address is
when "00" => csr_readdata <= (31 downto 1 => '0') & byteswapping;
when "01" => csr_readdata <= std_ulogic_vector(packet_count);
when others => csr_readdata <= (31 downto 0 => 'X');
end case;
elsif (csr_write = '1' and csr_waitrequest_int = '0') then
case csr_address is
when "00" => byteswapping <= csr_writedata(0);
when others => null;
end case;
end if;
end if;
end process;
-- Unfortunately this workaround is required for Aldec: Need to schedule an event
fake_process :process
begin
wait for 50 ns;
end process;
end architecture;
|
-------------------------------------------------------------------------------
-- Copyright (c) 2014 Potential Ventures Ltd
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
-- * Neither the name of Potential Ventures Ltd nor
-- names of its contributors may be used to endorse or promote products
-- derived from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL POTENTIAL VENTURES LTD BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-------------------------------------------------------------------------------
--
--
-- Endian swapping module.
--
-- Simple example with Avalon streaming interfaces and a CSR bus
--
-- Avalon-ST has readyLatency of 0
-- Avalon-MM has fixed readLatency of 1
--
-- Exposes 2 32-bit registers via the Avalon-MM interface
--
-- Address 0: bit 0 [R/W] byteswap enable
-- bits 31-1: [N/A] reserved
-- Adress 1: bits 31-0: [RO] packet count
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity endian_swapper_vhdl is
generic (
DATA_BYTES : integer := 8);
port (
clk : in std_ulogic;
reset_n : in std_ulogic;
stream_in_data : in std_ulogic_vector(DATA_BYTES*8-1 downto 0);
stream_in_empty : in std_ulogic_vector(2 downto 0);
stream_in_valid : in std_ulogic;
stream_in_startofpacket : in std_ulogic;
stream_in_endofpacket : in std_ulogic;
stream_in_ready : out std_ulogic;
stream_out_data : out std_ulogic_vector(DATA_BYTES*8-1 downto 0);
stream_out_empty : out std_ulogic_vector(2 downto 0);
stream_out_valid : out std_ulogic;
stream_out_startofpacket: out std_ulogic;
stream_out_endofpacket : out std_ulogic;
stream_out_ready : in std_ulogic;
csr_address : in std_ulogic_vector(1 downto 0);
csr_readdata : out std_ulogic_vector(31 downto 0);
csr_readdatavalid : out std_ulogic;
csr_read : in std_ulogic;
csr_write : in std_ulogic;
csr_waitrequest : out std_ulogic;
csr_writedata : in std_ulogic_vector(31 downto 0)
);
end;
architecture impl of endian_swapper_vhdl is
function byteswap(data : in std_ulogic_vector(63 downto 0)) return std_ulogic_vector is begin
return data(7 downto 0) &
data(15 downto 8) &
data(23 downto 16) &
data(31 downto 24) &
data(39 downto 32) &
data(47 downto 40) &
data(55 downto 48) &
data(63 downto 56);
end;
signal csr_waitrequest_int : std_ulogic;
signal stream_out_endofpacket_int: std_ulogic;
signal flush_pipe : std_ulogic;
signal in_packet : std_ulogic;
signal byteswapping : std_ulogic;
signal packet_count : unsigned(31 downto 0);
begin
process (clk, reset_n) begin
if (reset_n = '0') then
flush_pipe <= '0';
in_packet <= '0';
packet_count <= to_unsigned(0, 32);
elsif rising_edge(clk) then
if (flush_pipe = '1' and stream_out_ready = '1') then
flush_pipe <= stream_in_endofpacket and stream_in_valid and stream_out_ready;
elsif (flush_pipe = '0') then
flush_pipe <= stream_in_endofpacket and stream_in_valid and stream_out_ready;
end if;
if (stream_out_ready = '1' and stream_in_valid = '1') then
stream_out_empty <= stream_in_empty;
stream_out_startofpacket <= stream_in_startofpacket;
stream_out_endofpacket_int <= stream_in_endofpacket;
if (byteswapping = '0') then
stream_out_data <= stream_in_data;
else
stream_out_data <= byteswap(stream_in_data);
end if;
if (stream_in_startofpacket = '1' and stream_in_valid = '1') then
packet_count <= packet_count + 1;
in_packet <= '1';
end if;
if (stream_in_endofpacket = '1' and stream_in_valid = '1') then
in_packet <= '0';
end if;
end if;
end if;
end process;
stream_in_ready <= stream_out_ready;
stream_out_endofpacket <= stream_out_endofpacket_int;
stream_out_valid <= '1' when (stream_in_valid = '1' and stream_out_endofpacket_int = '0') or flush_pipe = '1' else '0';
-- Hold off CSR accesses during packet transfers to prevent changing of endian configuration mid-packet
csr_waitrequest_int <= '1' when reset_n = '0' or in_packet = '1' or (stream_in_startofpacket = '1' and stream_in_valid = '1') or flush_pipe = '1' else '0';
csr_waitrequest <= csr_waitrequest_int;
process (clk, reset_n) begin
if (reset_n = '0') then
byteswapping <= '0';
csr_readdatavalid <= '0';
elsif rising_edge(clk) then
if (csr_read = '1') then
csr_readdatavalid <= not csr_waitrequest_int;
case csr_address is
when "00" => csr_readdata <= (31 downto 1 => '0') & byteswapping;
when "01" => csr_readdata <= std_ulogic_vector(packet_count);
when others => csr_readdata <= (31 downto 0 => 'X');
end case;
elsif (csr_write = '1' and csr_waitrequest_int = '0') then
case csr_address is
when "00" => byteswapping <= csr_writedata(0);
when others => null;
end case;
end if;
end if;
end process;
-- Unfortunately this workaround is required for Aldec: Need to schedule an event
fake_process :process
begin
wait for 50 ns;
end process;
end architecture;
|
-- NEED RESULT: ARCH00345.P1: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00345.P2: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00345.P3: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00345.P4: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00345.P5: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00345.P6: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00345.P7: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00345.P8: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00345.P9: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00345: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00345: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00345: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00345: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00345: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00345: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00345: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00345: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00345: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00345: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00345: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00345: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00345: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00345: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00345: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00345: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00345: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00345: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: P9: Transport transactions completed entirely passed
-- NEED RESULT: P8: Transport transactions completed entirely passed
-- NEED RESULT: P7: Transport transactions completed entirely passed
-- NEED RESULT: P6: Transport transactions completed entirely passed
-- NEED RESULT: P5: Transport transactions completed entirely passed
-- NEED RESULT: P4: Transport transactions completed entirely passed
-- NEED RESULT: P3: Transport transactions completed entirely passed
-- NEED RESULT: P2: Transport transactions completed entirely passed
-- NEED RESULT: P1: Transport transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00345
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (2)
-- 9.5.1 (1)
-- 9.5.1 (2)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00345(ARCH00345)
-- ENT00345_Test_Bench(ARCH00345_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00345 is
end ENT00345 ;
--
--
architecture ARCH00345 of ENT00345 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_boolean_vector : chk_sig_type := -1 ;
signal chk_st_severity_level_vector : chk_sig_type := -1 ;
signal chk_st_string : chk_sig_type := -1 ;
signal chk_st_enum1_vector : chk_sig_type := -1 ;
signal chk_st_integer_vector : chk_sig_type := -1 ;
signal chk_st_time_vector : chk_sig_type := -1 ;
signal chk_st_real_vector : chk_sig_type := -1 ;
signal chk_st_rec1_vector : chk_sig_type := -1 ;
signal chk_st_arr2_vector : chk_sig_type := -1 ;
--
subtype chk_time_type is Time ;
signal s_st_boolean_vector_savt : chk_time_type := 0 ns ;
signal s_st_severity_level_vector_savt : chk_time_type := 0 ns ;
signal s_st_string_savt : chk_time_type := 0 ns ;
signal s_st_enum1_vector_savt : chk_time_type := 0 ns ;
signal s_st_integer_vector_savt : chk_time_type := 0 ns ;
signal s_st_time_vector_savt : chk_time_type := 0 ns ;
signal s_st_real_vector_savt : chk_time_type := 0 ns ;
signal s_st_rec1_vector_savt : chk_time_type := 0 ns ;
signal s_st_arr2_vector_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_boolean_vector_cnt : chk_cnt_type := 0 ;
signal s_st_severity_level_vector_cnt : chk_cnt_type := 0 ;
signal s_st_string_cnt : chk_cnt_type := 0 ;
signal s_st_enum1_vector_cnt : chk_cnt_type := 0 ;
signal s_st_integer_vector_cnt : chk_cnt_type := 0 ;
signal s_st_time_vector_cnt : chk_cnt_type := 0 ;
signal s_st_real_vector_cnt : chk_cnt_type := 0 ;
signal s_st_rec1_vector_cnt : chk_cnt_type := 0 ;
signal s_st_arr2_vector_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 3 ;
signal st_boolean_vector_select : select_type := 1 ;
signal st_severity_level_vector_select : select_type := 1 ;
signal st_string_select : select_type := 1 ;
signal st_enum1_vector_select : select_type := 1 ;
signal st_integer_vector_select : select_type := 1 ;
signal st_time_vector_select : select_type := 1 ;
signal st_real_vector_select : select_type := 1 ;
signal st_rec1_vector_select : select_type := 1 ;
signal st_arr2_vector_select : select_type := 1 ;
--
signal s_st_boolean_vector : st_boolean_vector
:= c_st_boolean_vector_1 ;
signal s_st_severity_level_vector : st_severity_level_vector
:= c_st_severity_level_vector_1 ;
signal s_st_string : st_string
:= c_st_string_1 ;
signal s_st_enum1_vector : st_enum1_vector
:= c_st_enum1_vector_1 ;
signal s_st_integer_vector : st_integer_vector
:= c_st_integer_vector_1 ;
signal s_st_time_vector : st_time_vector
:= c_st_time_vector_1 ;
signal s_st_real_vector : st_real_vector
:= c_st_real_vector_1 ;
signal s_st_rec1_vector : st_rec1_vector
:= c_st_rec1_vector_1 ;
signal s_st_arr2_vector : st_arr2_vector
:= c_st_arr2_vector_1 ;
--
begin
CHG1 :
process ( s_st_boolean_vector )
variable correct : boolean ;
begin
case s_st_boolean_vector_cnt is
when 0
=> null ;
-- s_st_boolean_vector(lowb to highb-1) <= transport
-- c_st_boolean_vector_2(lowb to highb-1) after 10 ns,
-- c_st_boolean_vector_1(lowb to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_boolean_vector(lowb to highb-1) =
c_st_boolean_vector_2(lowb to highb-1) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_boolean_vector(lowb to highb-1) =
c_st_boolean_vector_1(lowb to highb-1) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00345.P1" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_boolean_vector_select <= transport 2 ;
-- s_st_boolean_vector(lowb to highb-1) <= transport
-- c_st_boolean_vector_2(lowb to highb-1) after 10 ns ,
-- c_st_boolean_vector_1(lowb to highb-1) after 20 ns ,
-- c_st_boolean_vector_2(lowb to highb-1) after 30 ns ,
-- c_st_boolean_vector_1(lowb to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_boolean_vector(lowb to highb-1) =
c_st_boolean_vector_2(lowb to highb-1) and
(s_st_boolean_vector_savt + 10 ns) = Std.Standard.Now ;
st_boolean_vector_select <= transport 3 ;
-- s_st_boolean_vector(lowb to highb-1) <= transport
-- c_st_boolean_vector_1(lowb to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_boolean_vector(lowb to highb-1) =
c_st_boolean_vector_1(lowb to highb-1) and
(s_st_boolean_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00345" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00345" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00345" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_boolean_vector_savt <= transport Std.Standard.Now ;
chk_st_boolean_vector <= transport s_st_boolean_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_boolean_vector_cnt <= transport s_st_boolean_vector_cnt + 1 ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_st_boolean_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions completed entirely",
chk_st_boolean_vector = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
s_st_boolean_vector(lowb to highb-1) <= transport
c_st_boolean_vector_2(lowb to highb-1) after 10 ns,
c_st_boolean_vector_1(lowb to highb-1) after 20 ns
when st_boolean_vector_select = 1 else
--
c_st_boolean_vector_2(lowb to highb-1) after 10 ns ,
c_st_boolean_vector_1(lowb to highb-1) after 20 ns ,
c_st_boolean_vector_2(lowb to highb-1) after 30 ns ,
c_st_boolean_vector_1(lowb to highb-1) after 40 ns
when st_boolean_vector_select = 2 else
--
c_st_boolean_vector_1(lowb to highb-1) after 5 ns ;
--
CHG2 :
process ( s_st_severity_level_vector )
variable correct : boolean ;
begin
case s_st_severity_level_vector_cnt is
when 0
=> null ;
-- s_st_severity_level_vector(lowb to highb-1) <= transport
-- c_st_severity_level_vector_2(lowb to highb-1) after 10 ns,
-- c_st_severity_level_vector_1(lowb to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_severity_level_vector(lowb to highb-1) =
c_st_severity_level_vector_2(lowb to highb-1) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_severity_level_vector(lowb to highb-1) =
c_st_severity_level_vector_1(lowb to highb-1) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00345.P2" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_severity_level_vector_select <= transport 2 ;
-- s_st_severity_level_vector(lowb to highb-1) <= transport
-- c_st_severity_level_vector_2(lowb to highb-1) after 10 ns ,
-- c_st_severity_level_vector_1(lowb to highb-1) after 20 ns ,
-- c_st_severity_level_vector_2(lowb to highb-1) after 30 ns ,
-- c_st_severity_level_vector_1(lowb to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_severity_level_vector(lowb to highb-1) =
c_st_severity_level_vector_2(lowb to highb-1) and
(s_st_severity_level_vector_savt + 10 ns) = Std.Standard.Now ;
st_severity_level_vector_select <= transport 3 ;
-- s_st_severity_level_vector(lowb to highb-1) <= transport
-- c_st_severity_level_vector_1(lowb to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_severity_level_vector(lowb to highb-1) =
c_st_severity_level_vector_1(lowb to highb-1) and
(s_st_severity_level_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00345" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00345" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00345" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_severity_level_vector_savt <= transport Std.Standard.Now ;
chk_st_severity_level_vector <= transport s_st_severity_level_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_severity_level_vector_cnt <= transport s_st_severity_level_vector_cnt
+ 1 ;
--
end process CHG2 ;
--
PGEN_CHKP_2 :
process ( chk_st_severity_level_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions completed entirely",
chk_st_severity_level_vector = 4 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
s_st_severity_level_vector(lowb to highb-1) <= transport
c_st_severity_level_vector_2(lowb to highb-1) after 10 ns,
c_st_severity_level_vector_1(lowb to highb-1) after 20 ns
when st_severity_level_vector_select = 1 else
--
c_st_severity_level_vector_2(lowb to highb-1) after 10 ns ,
c_st_severity_level_vector_1(lowb to highb-1) after 20 ns ,
c_st_severity_level_vector_2(lowb to highb-1) after 30 ns ,
c_st_severity_level_vector_1(lowb to highb-1) after 40 ns
when st_severity_level_vector_select = 2 else
--
c_st_severity_level_vector_1(lowb to highb-1) after 5 ns ;
--
CHG3 :
process ( s_st_string )
variable correct : boolean ;
begin
case s_st_string_cnt is
when 0
=> null ;
-- s_st_string(highb-1 to highb-1) <= transport
-- c_st_string_2(highb-1 to highb-1) after 10 ns,
-- c_st_string_1(highb-1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_string(highb-1 to highb-1) =
c_st_string_2(highb-1 to highb-1) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_string(highb-1 to highb-1) =
c_st_string_1(highb-1 to highb-1) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00345.P3" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_string_select <= transport 2 ;
-- s_st_string(highb-1 to highb-1) <= transport
-- c_st_string_2(highb-1 to highb-1) after 10 ns ,
-- c_st_string_1(highb-1 to highb-1) after 20 ns ,
-- c_st_string_2(highb-1 to highb-1) after 30 ns ,
-- c_st_string_1(highb-1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_string(highb-1 to highb-1) =
c_st_string_2(highb-1 to highb-1) and
(s_st_string_savt + 10 ns) = Std.Standard.Now ;
st_string_select <= transport 3 ;
-- s_st_string(highb-1 to highb-1) <= transport
-- c_st_string_1(highb-1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_string(highb-1 to highb-1) =
c_st_string_1(highb-1 to highb-1) and
(s_st_string_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00345" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00345" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00345" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_string_savt <= transport Std.Standard.Now ;
chk_st_string <= transport s_st_string_cnt
after (1 us - Std.Standard.Now) ;
s_st_string_cnt <= transport s_st_string_cnt + 1 ;
--
end process CHG3 ;
--
PGEN_CHKP_3 :
process ( chk_st_string )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Transport transactions completed entirely",
chk_st_string = 4 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
s_st_string(highb-1 to highb-1) <= transport
c_st_string_2(highb-1 to highb-1) after 10 ns,
c_st_string_1(highb-1 to highb-1) after 20 ns
when st_string_select = 1 else
--
c_st_string_2(highb-1 to highb-1) after 10 ns ,
c_st_string_1(highb-1 to highb-1) after 20 ns ,
c_st_string_2(highb-1 to highb-1) after 30 ns ,
c_st_string_1(highb-1 to highb-1) after 40 ns
when st_string_select = 2 else
--
c_st_string_1(highb-1 to highb-1) after 5 ns ;
--
CHG4 :
process ( s_st_enum1_vector )
variable correct : boolean ;
begin
case s_st_enum1_vector_cnt is
when 0
=> null ;
-- s_st_enum1_vector(highb-1 to highb-1) <= transport
-- c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns,
-- c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_enum1_vector(highb-1 to highb-1) =
c_st_enum1_vector_2(highb-1 to highb-1) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_enum1_vector(highb-1 to highb-1) =
c_st_enum1_vector_1(highb-1 to highb-1) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00345.P4" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_enum1_vector_select <= transport 2 ;
-- s_st_enum1_vector(highb-1 to highb-1) <= transport
-- c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns ,
-- c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns ,
-- c_st_enum1_vector_2(highb-1 to highb-1) after 30 ns ,
-- c_st_enum1_vector_1(highb-1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_enum1_vector(highb-1 to highb-1) =
c_st_enum1_vector_2(highb-1 to highb-1) and
(s_st_enum1_vector_savt + 10 ns) = Std.Standard.Now ;
st_enum1_vector_select <= transport 3 ;
-- s_st_enum1_vector(highb-1 to highb-1) <= transport
-- c_st_enum1_vector_1(highb-1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_enum1_vector(highb-1 to highb-1) =
c_st_enum1_vector_1(highb-1 to highb-1) and
(s_st_enum1_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00345" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00345" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00345" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_enum1_vector_savt <= transport Std.Standard.Now ;
chk_st_enum1_vector <= transport s_st_enum1_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_enum1_vector_cnt <= transport s_st_enum1_vector_cnt + 1 ;
--
end process CHG4 ;
--
PGEN_CHKP_4 :
process ( chk_st_enum1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Transport transactions completed entirely",
chk_st_enum1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
--
s_st_enum1_vector(highb-1 to highb-1) <= transport
c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns,
c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns
when st_enum1_vector_select = 1 else
--
c_st_enum1_vector_2(highb-1 to highb-1) after 10 ns ,
c_st_enum1_vector_1(highb-1 to highb-1) after 20 ns ,
c_st_enum1_vector_2(highb-1 to highb-1) after 30 ns ,
c_st_enum1_vector_1(highb-1 to highb-1) after 40 ns
when st_enum1_vector_select = 2 else
--
c_st_enum1_vector_1(highb-1 to highb-1) after 5 ns ;
--
CHG5 :
process ( s_st_integer_vector )
variable correct : boolean ;
begin
case s_st_integer_vector_cnt is
when 0
=> null ;
-- s_st_integer_vector(lowb to highb-1) <= transport
-- c_st_integer_vector_2(lowb to highb-1) after 10 ns,
-- c_st_integer_vector_1(lowb to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_integer_vector(lowb to highb-1) =
c_st_integer_vector_2(lowb to highb-1) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_integer_vector(lowb to highb-1) =
c_st_integer_vector_1(lowb to highb-1) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00345.P5" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_integer_vector_select <= transport 2 ;
-- s_st_integer_vector(lowb to highb-1) <= transport
-- c_st_integer_vector_2(lowb to highb-1) after 10 ns ,
-- c_st_integer_vector_1(lowb to highb-1) after 20 ns ,
-- c_st_integer_vector_2(lowb to highb-1) after 30 ns ,
-- c_st_integer_vector_1(lowb to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_integer_vector(lowb to highb-1) =
c_st_integer_vector_2(lowb to highb-1) and
(s_st_integer_vector_savt + 10 ns) = Std.Standard.Now ;
st_integer_vector_select <= transport 3 ;
-- s_st_integer_vector(lowb to highb-1) <= transport
-- c_st_integer_vector_1(lowb to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_integer_vector(lowb to highb-1) =
c_st_integer_vector_1(lowb to highb-1) and
(s_st_integer_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00345" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00345" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00345" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_integer_vector_savt <= transport Std.Standard.Now ;
chk_st_integer_vector <= transport s_st_integer_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_integer_vector_cnt <= transport s_st_integer_vector_cnt + 1 ;
--
end process CHG5 ;
--
PGEN_CHKP_5 :
process ( chk_st_integer_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Transport transactions completed entirely",
chk_st_integer_vector = 4 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
--
s_st_integer_vector(lowb to highb-1) <= transport
c_st_integer_vector_2(lowb to highb-1) after 10 ns,
c_st_integer_vector_1(lowb to highb-1) after 20 ns
when st_integer_vector_select = 1 else
--
c_st_integer_vector_2(lowb to highb-1) after 10 ns ,
c_st_integer_vector_1(lowb to highb-1) after 20 ns ,
c_st_integer_vector_2(lowb to highb-1) after 30 ns ,
c_st_integer_vector_1(lowb to highb-1) after 40 ns
when st_integer_vector_select = 2 else
--
c_st_integer_vector_1(lowb to highb-1) after 5 ns ;
--
CHG6 :
process ( s_st_time_vector )
variable correct : boolean ;
begin
case s_st_time_vector_cnt is
when 0
=> null ;
-- s_st_time_vector(lowb to highb-1) <= transport
-- c_st_time_vector_2(lowb to highb-1) after 10 ns,
-- c_st_time_vector_1(lowb to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_time_vector(lowb to highb-1) =
c_st_time_vector_2(lowb to highb-1) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_time_vector(lowb to highb-1) =
c_st_time_vector_1(lowb to highb-1) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00345.P6" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_time_vector_select <= transport 2 ;
-- s_st_time_vector(lowb to highb-1) <= transport
-- c_st_time_vector_2(lowb to highb-1) after 10 ns ,
-- c_st_time_vector_1(lowb to highb-1) after 20 ns ,
-- c_st_time_vector_2(lowb to highb-1) after 30 ns ,
-- c_st_time_vector_1(lowb to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_time_vector(lowb to highb-1) =
c_st_time_vector_2(lowb to highb-1) and
(s_st_time_vector_savt + 10 ns) = Std.Standard.Now ;
st_time_vector_select <= transport 3 ;
-- s_st_time_vector(lowb to highb-1) <= transport
-- c_st_time_vector_1(lowb to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_time_vector(lowb to highb-1) =
c_st_time_vector_1(lowb to highb-1) and
(s_st_time_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00345" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00345" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00345" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_time_vector_savt <= transport Std.Standard.Now ;
chk_st_time_vector <= transport s_st_time_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_time_vector_cnt <= transport s_st_time_vector_cnt + 1 ;
--
end process CHG6 ;
--
PGEN_CHKP_6 :
process ( chk_st_time_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Transport transactions completed entirely",
chk_st_time_vector = 4 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
--
s_st_time_vector(lowb to highb-1) <= transport
c_st_time_vector_2(lowb to highb-1) after 10 ns,
c_st_time_vector_1(lowb to highb-1) after 20 ns
when st_time_vector_select = 1 else
--
c_st_time_vector_2(lowb to highb-1) after 10 ns ,
c_st_time_vector_1(lowb to highb-1) after 20 ns ,
c_st_time_vector_2(lowb to highb-1) after 30 ns ,
c_st_time_vector_1(lowb to highb-1) after 40 ns
when st_time_vector_select = 2 else
--
c_st_time_vector_1(lowb to highb-1) after 5 ns ;
--
CHG7 :
process ( s_st_real_vector )
variable correct : boolean ;
begin
case s_st_real_vector_cnt is
when 0
=> null ;
-- s_st_real_vector(highb-1 to highb-1) <= transport
-- c_st_real_vector_2(highb-1 to highb-1) after 10 ns,
-- c_st_real_vector_1(highb-1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_real_vector(highb-1 to highb-1) =
c_st_real_vector_2(highb-1 to highb-1) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real_vector(highb-1 to highb-1) =
c_st_real_vector_1(highb-1 to highb-1) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00345.P7" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_real_vector_select <= transport 2 ;
-- s_st_real_vector(highb-1 to highb-1) <= transport
-- c_st_real_vector_2(highb-1 to highb-1) after 10 ns ,
-- c_st_real_vector_1(highb-1 to highb-1) after 20 ns ,
-- c_st_real_vector_2(highb-1 to highb-1) after 30 ns ,
-- c_st_real_vector_1(highb-1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_real_vector(highb-1 to highb-1) =
c_st_real_vector_2(highb-1 to highb-1) and
(s_st_real_vector_savt + 10 ns) = Std.Standard.Now ;
st_real_vector_select <= transport 3 ;
-- s_st_real_vector(highb-1 to highb-1) <= transport
-- c_st_real_vector_1(highb-1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real_vector(highb-1 to highb-1) =
c_st_real_vector_1(highb-1 to highb-1) and
(s_st_real_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00345" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00345" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00345" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_real_vector_savt <= transport Std.Standard.Now ;
chk_st_real_vector <= transport s_st_real_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_real_vector_cnt <= transport s_st_real_vector_cnt + 1 ;
--
end process CHG7 ;
--
PGEN_CHKP_7 :
process ( chk_st_real_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P7" ,
"Transport transactions completed entirely",
chk_st_real_vector = 4 ) ;
end if ;
end process PGEN_CHKP_7 ;
--
--
s_st_real_vector(highb-1 to highb-1) <= transport
c_st_real_vector_2(highb-1 to highb-1) after 10 ns,
c_st_real_vector_1(highb-1 to highb-1) after 20 ns
when st_real_vector_select = 1 else
--
c_st_real_vector_2(highb-1 to highb-1) after 10 ns ,
c_st_real_vector_1(highb-1 to highb-1) after 20 ns ,
c_st_real_vector_2(highb-1 to highb-1) after 30 ns ,
c_st_real_vector_1(highb-1 to highb-1) after 40 ns
when st_real_vector_select = 2 else
--
c_st_real_vector_1(highb-1 to highb-1) after 5 ns ;
--
CHG8 :
process ( s_st_rec1_vector )
variable correct : boolean ;
begin
case s_st_rec1_vector_cnt is
when 0
=> null ;
-- s_st_rec1_vector(highb-1 to highb-1) <= transport
-- c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns,
-- c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_rec1_vector(highb-1 to highb-1) =
c_st_rec1_vector_2(highb-1 to highb-1) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1_vector(highb-1 to highb-1) =
c_st_rec1_vector_1(highb-1 to highb-1) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00345.P8" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec1_vector_select <= transport 2 ;
-- s_st_rec1_vector(highb-1 to highb-1) <= transport
-- c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns ,
-- c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns ,
-- c_st_rec1_vector_2(highb-1 to highb-1) after 30 ns ,
-- c_st_rec1_vector_1(highb-1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_rec1_vector(highb-1 to highb-1) =
c_st_rec1_vector_2(highb-1 to highb-1) and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
st_rec1_vector_select <= transport 3 ;
-- s_st_rec1_vector(highb-1 to highb-1) <= transport
-- c_st_rec1_vector_1(highb-1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1_vector(highb-1 to highb-1) =
c_st_rec1_vector_1(highb-1 to highb-1) and
(s_st_rec1_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00345" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00345" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00345" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_rec1_vector_savt <= transport Std.Standard.Now ;
chk_st_rec1_vector <= transport s_st_rec1_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec1_vector_cnt <= transport s_st_rec1_vector_cnt + 1 ;
--
end process CHG8 ;
--
PGEN_CHKP_8 :
process ( chk_st_rec1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P8" ,
"Transport transactions completed entirely",
chk_st_rec1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_8 ;
--
--
s_st_rec1_vector(highb-1 to highb-1) <= transport
c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns,
c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns
when st_rec1_vector_select = 1 else
--
c_st_rec1_vector_2(highb-1 to highb-1) after 10 ns ,
c_st_rec1_vector_1(highb-1 to highb-1) after 20 ns ,
c_st_rec1_vector_2(highb-1 to highb-1) after 30 ns ,
c_st_rec1_vector_1(highb-1 to highb-1) after 40 ns
when st_rec1_vector_select = 2 else
--
c_st_rec1_vector_1(highb-1 to highb-1) after 5 ns ;
--
CHG9 :
process ( s_st_arr2_vector )
variable correct : boolean ;
begin
case s_st_arr2_vector_cnt is
when 0
=> null ;
-- s_st_arr2_vector(lowb to highb-1) <= transport
-- c_st_arr2_vector_2(lowb to highb-1) after 10 ns,
-- c_st_arr2_vector_1(lowb to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_arr2_vector(lowb to highb-1) =
c_st_arr2_vector_2(lowb to highb-1) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2_vector(lowb to highb-1) =
c_st_arr2_vector_1(lowb to highb-1) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00345.P9" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr2_vector_select <= transport 2 ;
-- s_st_arr2_vector(lowb to highb-1) <= transport
-- c_st_arr2_vector_2(lowb to highb-1) after 10 ns ,
-- c_st_arr2_vector_1(lowb to highb-1) after 20 ns ,
-- c_st_arr2_vector_2(lowb to highb-1) after 30 ns ,
-- c_st_arr2_vector_1(lowb to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_arr2_vector(lowb to highb-1) =
c_st_arr2_vector_2(lowb to highb-1) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
st_arr2_vector_select <= transport 3 ;
-- s_st_arr2_vector(lowb to highb-1) <= transport
-- c_st_arr2_vector_1(lowb to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2_vector(lowb to highb-1) =
c_st_arr2_vector_1(lowb to highb-1) and
(s_st_arr2_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00345" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00345" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00345" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_arr2_vector_savt <= transport Std.Standard.Now ;
chk_st_arr2_vector <= transport s_st_arr2_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr2_vector_cnt <= transport s_st_arr2_vector_cnt + 1 ;
--
end process CHG9 ;
--
PGEN_CHKP_9 :
process ( chk_st_arr2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P9" ,
"Transport transactions completed entirely",
chk_st_arr2_vector = 4 ) ;
end if ;
end process PGEN_CHKP_9 ;
--
--
s_st_arr2_vector(lowb to highb-1) <= transport
c_st_arr2_vector_2(lowb to highb-1) after 10 ns,
c_st_arr2_vector_1(lowb to highb-1) after 20 ns
when st_arr2_vector_select = 1 else
--
c_st_arr2_vector_2(lowb to highb-1) after 10 ns ,
c_st_arr2_vector_1(lowb to highb-1) after 20 ns ,
c_st_arr2_vector_2(lowb to highb-1) after 30 ns ,
c_st_arr2_vector_1(lowb to highb-1) after 40 ns
when st_arr2_vector_select = 2 else
--
c_st_arr2_vector_1(lowb to highb-1) after 5 ns ;
--
end ARCH00345 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00345_Test_Bench is
end ENT00345_Test_Bench ;
--
--
architecture ARCH00345_Test_Bench of ENT00345_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.ENT00345 ( ARCH00345 ) ;
begin
CIS1 : UUT
;
end block L1 ;
end ARCH00345_Test_Bench ;
|
--------------------------------------------------------------------------------
--
-- AM2901 Benchmark -- mem test vectors
--
-- Source: AMD data book
--
-- VHDL Benchmark author Indraneel Ghosh
-- University Of California, Irvine, CA 92717
--
-- Developed on Jan 1, 1992
--
-- Verification Information:
--
-- Verified By whom? Date Simulator
-- -------- ------------ -------- ------------
-- Syntax yes Champaka Ramachandran Sept 17, 92 ZYCAD
-- Functionality yes Champaka Ramachandran Sept 17, 92 ZYCAD
--------------------------------------------------------------------------------
--library ZYCAD;
use work.TYPES.all;
use work.MVL7_functions.all;
use work.synthesis_types.all;
entity E is
end;
architecture A of E is
component mem_inst
port (
RAM : inout Memory(15 downto 0);
F : in MVL7_vector(3 downto 0);
clk : in clock;
I : in MVL7_vector(8 downto 0);
RAM0, RAM3 : in MVL7;
Aadd, Badd : in integer range 15 downto 0
);
end component;
signal RAM : Memory(15 downto 0);
signal F : MVL7_vector(3 downto 0);
signal clk : clock;
signal I : MVL7_vector(8 downto 0);
signal RAM0, RAM3 : MVL7;
signal Aadd, Badd : integer range 15 downto 0;
for all : mem_inst use entity work.mem(mem);
begin
mem_inst1 : mem_inst port map(
RAM,
F ,
clk,
I ,
RAM0, RAM3 ,
Aadd, Badd
);
process
begin
----------------------------------------------------------
F <= "0111"; --#1
I <= "010000000";
RAM0 <= 'Z';
RAM3 <= 'Z';
Aadd <= 0; -- Load F into RAM(Badd) where Badd = 0
Badd <= 0;
wait for 1 ns;
clk <= '1';
wait for 1 ns;
clk <= '0';
wait for 1 ns;
assert (RAM(Aadd) = "0111")
report
"Assert 1 : < RAM(Aadd) /= '0111'> "
severity warning;
assert(RAM(Badd) = "0111")
report
"Assert 2 : < RAM(Badd) /= '0111'> "
severity warning;
wait for 1 ns;
----------------------------------------------------------
F <= "1001"; --#2
I <= "011000000";
RAM0 <= 'Z';
RAM3 <= 'Z';
Aadd <= 0; -- Load F into RAM(Badd) where Badd = 1
Badd <= 1;
wait for 1 ns;
clk <= '1';
wait for 1 ns;
clk <= '0';
wait for 1 ns;
assert (RAM(Aadd) = "0111")
report
"Assert a1 : < RAM(Aadd) /= '0111'> "
severity warning;
assert(RAM(Badd) = "1001")
report
"Assert a2 : < RAM(Badd) /= '1001'> "
severity warning;
wait for 1 ns;
----------------------------------------------------------
F <= "0000"; --#3
I <= "000000000";
RAM0 <= 'Z';
RAM3 <= 'Z';
Aadd <= 1; -- Do nothing
Badd <= 0;
wait for 1 ns;
clk <= '1';
wait for 1 ns;
clk <= '0';
wait for 1 ns;
assert (RAM(Aadd) = "1001")
report
"Assert b1 : < RAM(Aadd) /= '1001'> "
severity warning;
assert(RAM(Badd) = "0111")
report
"Assert b2 : < RAM(Badd) /= '0111'> "
severity warning;
wait for 1 ns;
----------------------------------------------------------
F <= "1111"; --#4
I <= "001000000";
RAM0 <= 'Z';
RAM3 <= 'Z'; -- Do nothing
Aadd <= 0;
Badd <= 1;
wait for 1 ns;
clk <= '1';
wait for 1 ns;
clk <= '0';
wait for 1 ns;
assert (RAM(Aadd) = "0111")
report
"Assert c1 : < RAM(Aadd) /= '0111'> "
severity warning;
assert(RAM(Badd) = "1001")
report
"Assert c2 : < RAM(Badd) /= '1001'> "
severity warning;
wait for 1 ns;
----------------------------------------------------------
F <= "1001"; --#5
I <= "100000000";
RAM0 <= 'Z';
RAM3 <= '0';
Aadd <= 1; -- Down shift F and load that into RAM(Badd)
Badd <= 2; -- with input 0. Badd = 2.
wait for 1 ns;
clk <= '1';
wait for 1 ns;
clk <= '0';
wait for 1 ns;
assert (RAM(Aadd) = "1001")
report
"Assert d1 : < RAM(Aadd) /= '1001'> "
severity warning;
assert(RAM(Badd) = "0100")
report
"Assert d2 : < RAM(Badd) /= '0100'> "
severity warning;
wait for 1 ns;
----------------------------------------------------------
F <= "0111"; --#6
I <= "100000000";
RAM0 <= 'Z';
RAM3 <= '1';
Aadd <= 0; -- Down shift F and load that into RAM(Badd)
Badd <= 3; -- with input 1. Badd = 3
wait for 1 ns;
clk <= '1';
wait for 1 ns;
clk <= '0';
wait for 1 ns;
assert (RAM(Aadd) = "0111")
report
"Assert e1 : < RAM(Aadd) /= '0111'> "
severity warning;
assert(RAM(Badd) = "1011")
report
"Assert e2 : < RAM(Badd) /= '1011'> "
severity warning;
wait for 1 ns;
----------------------------------------------------------
F <= "1101"; --#7
I <= "101000000";
RAM0 <= 'Z';
RAM3 <= '0';
Aadd <= 2; -- Down shift F and load that into RAM(Badd)
Badd <= 4; -- with input 0. Badd = 4
wait for 1 ns;
clk <= '1';
wait for 1 ns;
clk <= '0';
wait for 1 ns;
assert (RAM(Aadd) = "0100")
report
"Assert f1 : < RAM(Aadd) /= '0100'> "
severity warning;
assert(RAM(Badd) = "0110")
report
"Assert f2 : < RAM(Badd) /= '0110'> "
severity warning;
wait for 1 ns;
----------------------------------------------------------
F <= "1101"; --#8
I <= "101000000";
RAM0 <= 'Z';
RAM3 <= '1'; -- Down shift F and load that into RAM(Badd)
Aadd <= 3; -- with input 1. Badd = 5
Badd <= 5;
wait for 1 ns;
clk <= '1';
wait for 1 ns;
clk <= '0';
wait for 1 ns;
assert (RAM(Aadd) = "1011")
report
"Assert g1 : < RAM(Aadd) /= '1011'> "
severity warning;
assert(RAM(Badd) = "1110")
report
"Assert g2 : < RAM(Badd) /= '1110'> "
severity warning;
wait for 1 ns;
----------------------------------------------------------
F <= "0110"; --#9
I <= "110000000";
RAM0 <= '0';
RAM3 <= 'Z'; -- Up shift F and load that into RAM(Badd)
Aadd <= 4; -- with input 0. Badd = 2
Badd <= 2;
wait for 1 ns;
clk <= '1';
wait for 1 ns;
clk <= '0';
wait for 1 ns;
assert (RAM(Aadd) = "0110")
report
"Assert h1 : < RAM(Aadd) /= '0110'> "
severity warning;
assert(RAM(Badd) = "1100")
report
"Assert h2 : < RAM(Badd) /= '1100'> "
severity warning;
wait for 1 ns;
----------------------------------------------------------
F <= "0000"; --#10
I <= "110000000";
RAM0 <= '1';
RAM3 <= 'Z'; -- Up shift F and load that into RAM(Badd)
Aadd <= 2; -- with input 1. Badd = 6
Badd <= 6;
wait for 1 ns;
clk <= '1';
wait for 1 ns;
clk <= '0';
wait for 1 ns;
assert (RAM(Aadd) = "1100")
report
"Assert i1 : < RAM(Aadd) /= '1100'> "
severity warning;
assert(RAM(Badd) = "0001")
report
"Assert i2 : < RAM(Badd) /= '0001'> "
severity warning;
wait for 1 ns;
----------------------------------------------------------
F <= "1101"; --#11
I <= "111000000";
RAM0 <= '0';
RAM3 <= 'Z';
Aadd <= 5; -- Up shift F and load that into RAM(Badd)
Badd <= 7; -- with input 0. Badd = 7
wait for 1 ns;
clk <= '1';
wait for 1 ns;
clk <= '0';
wait for 1 ns;
assert (RAM(Aadd) = "1110")
report
"Assert j1 : < RAM(Aadd) /= '1110'> "
severity warning;
assert(RAM(Badd) = "1010")
report
"Assert j2 : < RAM(Badd) /= '1010'> "
severity warning;
wait for 1 ns;
----------------------------------------------------------
F <= "0010"; --#12
I <= "111000000";
RAM0 <= '1';
RAM3 <= 'Z';
Aadd <= 6; -- Up shift F and load that into RAM(Badd)
Badd <= 8; -- with input 1. Badd = 8
wait for 1 ns;
clk <= '1';
wait for 1 ns;
clk <= '0';
wait for 1 ns;
assert (RAM(Aadd) = "0001")
report
"Assert k1 : < RAM(Aadd) /= '0001'> "
severity warning;
assert(RAM(Badd) = "0101")
report
"Assert k2 : < RAM(Badd) /= '0101'> "
severity warning;
wait for 1 ns;
----------------------------------------------------------
end process;
end A; |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_314 is
port (
result : out std_logic_vector(26 downto 0);
in_a : in std_logic_vector(26 downto 0);
in_b : in std_logic_vector(26 downto 0)
);
end add_314;
architecture augh of add_314 is
signal carry_inA : std_logic_vector(28 downto 0);
signal carry_inB : std_logic_vector(28 downto 0);
signal carry_res : std_logic_vector(28 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(27 downto 1);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_314 is
port (
result : out std_logic_vector(26 downto 0);
in_a : in std_logic_vector(26 downto 0);
in_b : in std_logic_vector(26 downto 0)
);
end add_314;
architecture augh of add_314 is
signal carry_inA : std_logic_vector(28 downto 0);
signal carry_inB : std_logic_vector(28 downto 0);
signal carry_res : std_logic_vector(28 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(27 downto 1);
end architecture;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.all;
use work.procedures.all;
entity simple_alu is
port(
clk : in std_logic;
a : in t_data;
b : in t_data;
op : in std_logic_vector(2 downto 0);
c : out t_data
);
end simple_alu;
architecture Structural of simple_alu is
signal arith : t_data;
signal logic : t_data;
begin
ashift: entity work.shift_ra
port map(
a => a,
b => b,
c => arith
);
lshift: entity work.shift_rl
port map(
a => a,
b => b,
c => logic
);
alu: process(clk)
begin
if rising_edge(clk) then
case op is
when SALU_ADD => c <= std_logic_vector(unsigned(a) + unsigned(b));
when SALU_SUB => c <= std_logic_vector(unsigned(a) - unsigned(b));
when SALU_SAR => c <= arith;
when SALU_SLR => c <= logic;
when SALU_AND => c <= a and b;
when SALU_OR => c <= a or b;
when SALU_XOR => c <= a xor b;
when others =>
end case;
end if;
end process alu;
end Structural;
|
-- $Id: tb_tst_serloop.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2016 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_serloop - sim
-- Description: Generic test bench for sys_tst_serloop_xx
--
-- Dependencies: vlib/simlib/simclkcnt
-- vlib/serport/serport_uart_rxtx_tb
-- vlib/serport/serport_xontx_tb
--
-- To test: sys_tst_serloop_xx
--
-- Target Devices: generic
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-09-03 805 1.2.2 remove CLK_STOP logic (simstop via report)
-- 2016-08-18 799 1.2.1 remove 'assert false' from report statements
-- 2016-04-23 764 1.2 use serport/tb/serport_(uart_rxtx|xontx)_tb
-- use assert to halt simulation
-- 2011-12-23 444 1.1 use new simclkcnt
-- 2011-11-13 425 1.0 Initial version
-- 2011-11-06 420 0.5 First draft
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
use work.simbus.all;
use work.serportlib_tb.all;
entity tb_tst_serloop is
port (
CLKS : in slbit; -- clock for serport
CLKH : in slbit; -- clock for humanio
P0_RXD : out slbit; -- port 0 receive data (board view)
P0_TXD : in slbit; -- port 0 transmit data (board view)
P0_RTS_N : in slbit; -- port 0 rts_n
P0_CTS_N : out slbit; -- port 0 cts_n
P1_RXD : out slbit; -- port 1 receive data (board view)
P1_TXD : in slbit; -- port 1 transmit data (board view)
P1_RTS_N : in slbit; -- port 1 rts_n
P1_CTS_N : out slbit; -- port 1 cts_n
SWI : out slv8; -- hio switches
BTN : out slv4 -- hio buttons
);
end tb_tst_serloop;
architecture sim of tb_tst_serloop is
signal CLK_CYCLE : integer := 0;
signal UART_RESET : slbit := '0';
signal UART_RXD : slbit := '1';
signal UART_TXD : slbit := '1';
signal CTS_N : slbit := '0';
signal RTS_N : slbit := '0';
signal CLKDIV : slv13 := (others=>'0');
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal UART_TXDATA : slv8 := (others=>'0');
signal UART_TXENA : slbit := '0';
signal UART_TXBUSY : slbit := '0';
signal ACTPORT : slbit := '0';
signal BREAK : slbit := '0';
signal CTS_CYCLE : integer := 0;
signal CTS_FRACT : integer := 0;
signal XON_CYCLE : integer := 0;
signal XON_FRACT : integer := 0;
signal S2M_ACTIVE : slbit := '0';
signal S2M_SIZE : integer := 0;
signal S2M_ENAESC : slbit := '0';
signal S2M_ENAXON : slbit := '0';
signal M2S_XONSEEN : slbit := '0';
signal M2S_XOFFSEEN : slbit := '0';
signal R_XONRXOK : slbit := '1';
signal R_XONTXOK : slbit := '1';
begin
CLKCNT : simclkcnt port map (CLK => CLKS, CLK_CYCLE => CLK_CYCLE);
UART : entity work.serport_uart_rxtx_tb
generic map (
CDWIDTH => 13)
port map (
CLK => CLKS,
RESET => UART_RESET,
CLKDIV => CLKDIV,
RXSD => UART_RXD,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXACT => RXACT,
TXSD => UART_TXD,
TXDATA => UART_TXDATA,
TXENA => UART_TXENA,
TXBUSY => UART_TXBUSY
);
XONTX : entity work.serport_xontx_tb
port map (
CLK => CLKS,
RESET => UART_RESET,
ENAXON => S2M_ENAXON,
ENAESC => S2M_ENAESC,
UART_TXDATA => UART_TXDATA,
UART_TXENA => UART_TXENA,
UART_TXBUSY => UART_TXBUSY,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
RXOK => R_XONRXOK,
TXOK => R_XONTXOK
);
proc_port_mux: process (ACTPORT, BREAK, UART_TXD, CTS_N,
P0_TXD, P0_RTS_N, P1_TXD, P1_RTS_N)
variable eff_txd : slbit := '0';
begin
if BREAK = '0' then -- if no break active
eff_txd := UART_TXD; -- send uart
else -- otherwise
eff_txd := '0'; -- force '0'
end if;
if ACTPORT = '0' then -- use port 0
P0_RXD <= eff_txd; -- write port 0 inputs
P0_CTS_N <= CTS_N;
UART_RXD <= P0_TXD; -- get port 0 outputs
RTS_N <= P0_RTS_N;
P1_RXD <= '1'; -- port 1 inputs to idle state
P1_CTS_N <= '0';
else -- use port 1
P1_RXD <= eff_txd; -- write port 1 inputs
P1_CTS_N <= CTS_N;
UART_RXD <= P1_TXD; -- get port 1 outputs
RTS_N <= P1_RTS_N;
P0_RXD <= '1'; -- port 0 inputs to idle state
P0_CTS_N <= '0';
end if;
end process proc_port_mux;
proc_cts: process(CLKS)
variable cts_timer : integer := 0;
begin
if rising_edge(CLKS) then
if CTS_CYCLE = 0 then -- if cts throttle off
CTS_N <= '0'; -- cts permanently asserted
else -- otherwise determine throttling
if cts_timer>0 and cts_timer<CTS_CYCLE then -- unless beyond ends
cts_timer := cts_timer - 1; -- decrement
else
cts_timer := CTS_CYCLE-1; -- otherwise reload
end if;
if cts_timer < cts_fract then -- if in lower 'fract' counts
CTS_N <= '1'; -- throttle: deassert CTS
else -- otherwise
CTS_N <= '0'; -- let go: assert CTS
end if;
end if;
end if;
end process proc_cts;
proc_xonrxok: process(CLKS)
variable xon_timer : integer := 0;
begin
if rising_edge(CLKS) then
if XON_CYCLE = 0 then -- if xon throttle off
R_XONRXOK <= '1'; -- xonrxok permanently asserted
else -- otherwise determine throttling
if xon_timer>0 and xon_timer<XON_CYCLE then -- unless beyond ends
xon_timer := xon_timer - 1; -- decrement
else
xon_timer := XON_CYCLE-1; -- otherwise reload
end if;
if xon_timer < xon_fract then -- if in lower 'fract' counts
R_XONRXOK <= '0'; -- throttle: deassert xonrxok
else -- otherwise
R_XONRXOK <= '1'; -- let go: assert xonrxok
end if;
end if;
end if;
end process proc_xonrxok;
proc_xontxok: process(CLKS)
begin
if rising_edge(CLKS) then
if M2S_XONSEEN = '1' then
R_XONTXOK <= '1';
elsif M2S_XOFFSEEN = '1' then
R_XONTXOK <= '0';
end if;
end if;
end process proc_xontxok;
proc_stim: process
file fstim : text open read_mode is "tb_tst_serloop_stim";
variable iline : line;
variable oline : line;
variable idelta : integer := 0;
variable iactport : slbit := '0';
variable iswi : slv8 := (others=>'0');
variable btn_num : integer := 0;
variable i_cycle : integer := 0;
variable i_fract : integer := 0;
variable nbyte : integer := 0;
variable enaesc : slbit := '0';
variable enaxon : slbit := '0';
variable bcnt : integer := 0;
variable itxdata : slv8 := (others=>'0');
variable ok : boolean;
variable dname : string(1 to 6) := (others=>' ');
procedure waitclk(ncyc : in integer) is
begin
for i in 1 to ncyc loop
wait until rising_edge(CLKS);
end loop; -- i
end procedure waitclk;
begin
-- initialize some top level out signals
SWI <= (others=>'0');
BTN <= (others=>'0');
wait until rising_edge(CLKS);
file_loop: while not endfile(fstim) loop
readline (fstim, iline);
readcomment(iline, ok);
next file_loop when ok;
readword(iline, dname, ok);
if ok then
case dname is
when "wait " => -- wait
read_ea(iline, idelta);
writetimestamp(oline, CLK_CYCLE, ": wait ");
write(oline, idelta, right, 5);
writeline(output, oline);
waitclk(idelta);
when "port " => -- switch rs232 port
read_ea(iline, iactport);
ACTPORT <= iactport;
writetimestamp(oline, CLK_CYCLE, ": port ");
write(oline, iactport, right, 5);
writeline(output, oline);
when "cts " => -- setup cts throttling
read_ea(iline, i_cycle);
read_ea(iline, i_fract);
CTS_CYCLE <= i_cycle;
CTS_FRACT <= i_fract;
writetimestamp(oline, CLK_CYCLE, ": cts ");
write(oline, i_cycle, right, 5);
write(oline, i_fract, right, 5);
writeline(output, oline);
when "xon " => -- setup xon throttling
read_ea(iline, i_cycle);
read_ea(iline, i_fract);
XON_CYCLE <= i_cycle;
XON_FRACT <= i_fract;
writetimestamp(oline, CLK_CYCLE, ": cts ");
write(oline, i_cycle, right, 5);
write(oline, i_fract, right, 5);
writeline(output, oline);
when "swi " => -- new SWI settings
read_ea(iline, iswi);
read_ea(iline, idelta);
writetimestamp(oline, CLK_CYCLE, ": swi ");
write(oline, iswi, right, 10);
write(oline, idelta, right, 5);
writeline(output, oline);
wait until rising_edge(CLKH);
SWI <= iswi;
wait until rising_edge(CLKS);
waitclk(idelta);
when "btn " => -- BTN push (3 cyc down + 3 cyc wait)
read_ea(iline, btn_num);
read_ea(iline, idelta);
if btn_num>=0 and btn_num<=3 then
writetimestamp(oline, CLK_CYCLE, ": btn ");
write(oline, btn_num, right, 5);
write(oline, idelta, right, 5);
writeline(output, oline);
wait until rising_edge(CLKH);
BTN(btn_num) <= '1'; -- 3 cycle BTN pulse
wait until rising_edge(CLKH);
wait until rising_edge(CLKH);
wait until rising_edge(CLKH);
BTN(btn_num) <= '0';
wait until rising_edge(CLKH);
wait until rising_edge(CLKH);
wait until rising_edge(CLKH);
wait until rising_edge(CLKS);
waitclk(idelta);
else
write(oline, string'("!! btn: btn number out of range"));
writeline(output, oline);
end if;
when "expect" => -- expect n bytes data
read_ea(iline, nbyte);
read_ea(iline, enaesc);
read_ea(iline, enaxon);
writetimestamp(oline, CLK_CYCLE, ": expect");
write(oline, nbyte, right, 5);
write(oline, enaesc, right, 3);
write(oline, enaxon, right, 3);
writeline(output, oline);
if nbyte > 0 then
S2M_ACTIVE <= '1';
S2M_SIZE <= nbyte;
else
S2M_ACTIVE <= '0';
end if;
S2M_ENAESC <= enaesc;
S2M_ENAXON <= enaxon;
wait until rising_edge(CLKS);
when "send " => -- send n bytes data
read_ea(iline, nbyte);
read_ea(iline, enaesc);
read_ea(iline, enaxon);
writetimestamp(oline, CLK_CYCLE, ": send ");
write(oline, nbyte, right, 5);
write(oline, enaesc, right, 3);
write(oline, enaxon, right, 3);
writeline(output, oline);
bcnt := 0;
itxdata := (others=>'0');
wait until falling_edge(CLKS);
while bcnt < nbyte loop
while TXBUSY='1' or RTS_N='1' loop
wait until falling_edge(CLKS);
end loop;
TXDATA <= itxdata;
itxdata := slv(unsigned(itxdata) + 1);
bcnt := bcnt + 1;
TXENA <= '1';
wait until falling_edge(CLKS);
TXENA <= '0';
wait until falling_edge(CLKS);
end loop;
while TXBUSY='1' or RTS_N='1' loop -- wait till last char send...
wait until falling_edge(CLKS);
end loop;
wait until rising_edge(CLKS);
when "break " => -- send a break for n cycles
read_ea(iline, idelta);
writetimestamp(oline, CLK_CYCLE, ": break ");
write(oline, idelta, right, 5);
writeline(output, oline);
-- send break for n cycles
BREAK <= '1';
waitclk(idelta);
BREAK <= '0';
-- wait for 3 bit cell width
waitclk(3*to_integer(unsigned(CLKDIV)+1));
-- send 'sync' character
wait until falling_edge(CLKS);
TXDATA <= "10000000";
TXENA <= '1';
wait until falling_edge(CLKS);
TXENA <= '0';
wait until rising_edge(CLKS);
when "clkdiv" => -- set new clock divider
read_ea(iline, idelta);
writetimestamp(oline, CLK_CYCLE, ": clkdiv");
write(oline, idelta, right, 5);
writeline(output, oline);
CLKDIV <= slv(to_unsigned(idelta, CLKDIV'length));
UART_RESET <= '1';
wait until rising_edge(CLKS);
UART_RESET <= '0';
when others => -- unknown command
write(oline, string'("?? unknown command: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
else
report "failed to find command" severity failure;
end if;
testempty_ea(iline);
end loop; -- file_loop
-- extra wait for at least two character times (20 bit times)
-- to allow tx and rx of the last character
waitclk(20*(to_integer(unsigned(CLKDIV))+1));
writetimestamp(oline, CLK_CYCLE, ": DONE ");
writeline(output, oline);
SB_SIMSTOP <= '1'; -- signal simulation stop
wait for 100 ns; -- monitor grace time
report "Simulation Finished" severity failure; -- end simulation
end process proc_stim;
proc_moni: process
variable oline : line;
variable dclk : integer := 0;
variable active_1 : slbit := '0';
variable irxdata : slv8 := (others=>'0');
variable irxeff : slv8 := (others=>'0');
variable irxval : slbit := '0';
variable doesc : slbit := '0';
variable bcnt : integer := 0;
variable xseen : slbit := '0';
begin
loop
wait until falling_edge(CLKS);
M2S_XONSEEN <= '0';
M2S_XOFFSEEN <= '0';
if S2M_ACTIVE='1' and active_1='0' then -- start expect message
irxdata := (others=>'0');
bcnt := 0;
end if;
if S2M_ACTIVE='0' and active_1='1' then -- end expect message
if bcnt = S2M_SIZE then
writetimestamp(oline, CLK_CYCLE, ": OK: message seen");
else
writetimestamp(oline, CLK_CYCLE, ": FAIL: missing chars, seen=");
write(oline, bcnt, right, 5);
write(oline, string'(" expect="));
write(oline, S2M_SIZE, right, 5);
end if;
writeline(output, oline);
end if;
active_1 := S2M_ACTIVE;
if RXVAL = '1' then
writetimestamp(oline, CLK_CYCLE, ": char: ");
write(oline, RXDATA, right, 10);
write(oline, string'(" ("));
writeoct(oline, RXDATA, right, 3);
write(oline, string'(") dt="));
write(oline, dclk, right, 4);
irxeff := RXDATA;
irxval := '1';
if doesc = '1' then
irxeff := not RXDATA;
irxval := '1';
doesc := '0';
write(oline, string'(" eff="));
write(oline, irxeff, right, 10);
write(oline, string'(" ("));
writeoct(oline, irxeff, right, 3);
write(oline, string'(")"));
elsif S2M_ENAESC='1' and RXDATA=c_serport_xesc then
doesc := '1';
irxval := '0';
write(oline, string'(" XESC seen"));
end if;
xseen := '0';
if S2M_ENAXON = '1' then
if RXDATA = c_serport_xon then
write(oline, string'(" XON seen"));
M2S_XONSEEN <= '1';
xseen := '1';
elsif RXDATA = c_serport_xoff then
write(oline, string'(" XOFF seen"));
M2S_XOFFSEEN <= '1';
xseen := '1';
end if;
end if;
if S2M_ACTIVE='1' and irxval='1' and xseen='0' then
if irxeff = irxdata then
write(oline, string'(" OK"));
else
write(oline, string'(" FAIL: expect="));
write(oline, irxdata, right, 10);
end if;
irxdata := slv(unsigned(irxdata) + 1);
bcnt := bcnt + 1;
end if;
writeline(output, oline);
dclk := 0;
end if;
if RXERR = '1' then
writetimestamp(oline, CLK_CYCLE, ": FAIL: RXERR='1'");
writeline(output, oline);
end if;
dclk := dclk + 1;
end loop;
end process proc_moni;
end sim;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: memory_unisim.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Memory generators for Xilinx RAMs
------------------------------------------------------------------------------
-- parametrisable sync ram generator using UNISIM RAMB16 block rams
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
--pragma translate_off
library unisim;
use unisim.RAMB16_S36_S36;
use unisim.RAMB16_S36;
use unisim.RAMB16_S18;
use unisim.RAMB16_S9;
use unisim.RAMB16_S4;
use unisim.RAMB16_S2;
use unisim.RAMB16_S1;
--pragma translate_on
entity unisim_syncram is
generic ( abits : integer := 9; dbits : integer := 32);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (dbits -1 downto 0);
dataout : out std_logic_vector (dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end;
architecture behav of unisim_syncram is
component RAMB16_S36_S36
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
DOA : out std_logic_vector (31 downto 0);
DOB : out std_logic_vector (31 downto 0);
DOPA : out std_logic_vector (3 downto 0);
DOPB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (31 downto 0);
DIB : in std_logic_vector (31 downto 0);
DIPA : in std_logic_vector (3 downto 0);
DIPB : in std_logic_vector (3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic);
end component;
component RAMB16_S1
port (
DO : out std_logic_vector (0 downto 0);
ADDR : in std_logic_vector (13 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (0 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S2
port (
DO : out std_logic_vector (1 downto 0);
ADDR : in std_logic_vector (12 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (1 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S4
port (
DO : out std_logic_vector (3 downto 0);
ADDR : in std_logic_vector (11 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (3 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S9
port (
DO : out std_logic_vector (7 downto 0);
DOP : out std_logic_vector (0 downto 0);
ADDR : in std_logic_vector (10 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (7 downto 0);
DIP : in std_logic_vector (0 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S18
port (
DO : out std_logic_vector (15 downto 0);
DOP : out std_logic_vector (1 downto 0);
ADDR : in std_logic_vector (9 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (15 downto 0);
DIP : in std_logic_vector (1 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component RAMB16_S36
port (
DO : out std_logic_vector (31 downto 0);
DOP : out std_logic_vector (3 downto 0);
ADDR : in std_logic_vector (8 downto 0);
CLK : in std_ulogic;
DI : in std_logic_vector (31 downto 0);
DIP : in std_logic_vector (3 downto 0);
EN : in std_ulogic;
SSR : in std_ulogic;
WE : in std_ulogic
);
end component;
component generic_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
write : in std_ulogic);
end component;
signal gnd : std_ulogic;
signal do, di : std_logic_vector(dbits+72 downto 0);
signal xa, ya : std_logic_vector(19 downto 0);
begin
gnd <= '0'; dataout <= do(dbits-1 downto 0); di(dbits-1 downto 0) <= datain;
di(dbits+72 downto dbits) <= (others => '0'); xa(abits-1 downto 0) <= address;
xa(19 downto abits) <= (others => '0'); ya(abits-1 downto 0) <= address;
ya(19 downto abits) <= (others => '1');
a0 : if (abits <= 5) and (GRLIB_CONFIG_ARRAY(grlib_techmap_strict_ram) = 0) generate
r0 : generic_syncram generic map (abits, dbits)
port map (clk, address, datain, do(dbits-1 downto 0), write);
do(dbits+72 downto dbits) <= (others => '0');
end generate;
a8 : if ((abits > 5 or GRLIB_CONFIG_ARRAY(grlib_techmap_strict_ram) /= 0) and
(abits <= 8)) generate
x : for i in 0 to ((dbits-1)/72) generate
r0 : RAMB16_S36_S36
generic map (SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
do(i*72+36+31 downto i*72+36), do(i*72+31 downto i*72),
do(i*72+36+32+3 downto i*72+36+32), do(i*72+32+3 downto i*72+32),
xa(8 downto 0), ya(8 downto 0), clk, clk,
di(i*72+36+31 downto i*72+36), di(i*72+31 downto i*72),
di(i*72+36+32+3 downto i*72+36+32), di(i*72+32+3 downto i*72+32),
enable, enable, gnd, gnd, write, write);
end generate;
do(dbits+72 downto 72*(((dbits-1)/72)+1)) <= (others => '0');
end generate;
a9 : if (abits = 9) generate
x : for i in 0 to ((dbits-1)/36) generate
r : RAMB16_S36 port map ( do(((i+1)*36)-5 downto i*36),
do(((i+1)*36)-1 downto i*36+32), xa(8 downto 0), clk,
di(((i+1)*36)-5 downto i*36), di(((i+1)*36)-1 downto i*36+32),
enable, gnd, write);
end generate;
do(dbits+72 downto 36*(((dbits-1)/36)+1)) <= (others => '0');
end generate;
a10 : if (abits = 10) generate
x : for i in 0 to ((dbits-1)/18) generate
r : RAMB16_S18 port map ( do(((i+1)*18)-3 downto i*18),
do(((i+1)*18)-1 downto i*18+16), xa(9 downto 0), clk,
di(((i+1)*18)-3 downto i*18), di(((i+1)*18)-1 downto i*18+16),
enable, gnd, write);
end generate;
do(dbits+72 downto 18*(((dbits-1)/18)+1)) <= (others => '0');
end generate;
a11 : if abits = 11 generate
x : for i in 0 to ((dbits-1)/9) generate
r : RAMB16_S9 port map ( do(((i+1)*9)-2 downto i*9),
do(((i+1)*9)-1 downto i*9+8), xa(10 downto 0), clk,
di(((i+1)*9)-2 downto i*9), di(((i+1)*9)-1 downto i*9+8),
enable, gnd, write);
end generate;
do(dbits+72 downto 9*(((dbits-1)/9)+1)) <= (others => '0');
end generate;
a12 : if abits = 12 generate
x : for i in 0 to ((dbits-1)/4) generate
r : RAMB16_S4 port map ( do(((i+1)*4)-1 downto i*4), xa(11 downto 0),
clk, di(((i+1)*4)-1 downto i*4), enable, gnd, write);
end generate;
do(dbits+72 downto 4*(((dbits-1)/4)+1)) <= (others => '0');
end generate;
a13 : if abits = 13 generate
x : for i in 0 to ((dbits-1)/2) generate
r : RAMB16_S2 port map ( do(((i+1)*2)-1 downto i*2), xa(12 downto 0),
clk, di(((i+1)*2)-1 downto i*2), enable, gnd, write);
end generate;
do(dbits+72 downto 2*(((dbits-1)/2)+1)) <= (others => '0');
end generate;
a14 : if abits = 14 generate
x : for i in 0 to (dbits-1) generate
r : RAMB16_S1 port map ( do((i+1)-1 downto i), xa(13 downto 0),
clk, di((i+1)-1 downto i), enable, gnd, write);
end generate;
do(dbits+72 downto dbits) <= (others => '0');
end generate;
a15 : if abits > 14 generate
x: generic_syncram generic map (abits, dbits)
port map (clk, address, datain, do(dbits-1 downto 0), write);
do(dbits+72 downto dbits) <= (others => '0');
end generate;
-- pragma translate_off
-- a_to_high : if abits > 14 generate
-- x : process
-- begin
-- assert false
-- report "Address depth larger than 14 not supported for unisim_syncram"
-- severity failure;
-- wait;
-- end process;
-- end generate;
-- pragma translate_on
end;
LIBRARY ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.conv_integer;
--pragma translate_off
library unisim;
use unisim.RAMB16_S36_S36;
use unisim.RAMB16_S18_S18;
use unisim.RAMB16_S9_S9;
use unisim.RAMB16_S4_S4;
use unisim.RAMB16_S2_S2;
use unisim.RAMB16_S1_S1;
--pragma translate_on
entity unisim_syncram_dp is
generic (
abits : integer := 4; dbits : integer := 32
);
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic);
end;
architecture behav of unisim_syncram_dp is
component RAMB16_S4_S4
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
DOA : out std_logic_vector (3 downto 0);
DOB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (11 downto 0);
ADDRB : in std_logic_vector (11 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (3 downto 0);
DIB : in std_logic_vector (3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
component RAMB16_S1_S1
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
DOA : out std_logic_vector (0 downto 0);
DOB : out std_logic_vector (0 downto 0);
ADDRA : in std_logic_vector (13 downto 0);
ADDRB : in std_logic_vector (13 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (0 downto 0);
DIB : in std_logic_vector (0 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
component RAMB16_S2_S2
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
DOA : out std_logic_vector (1 downto 0);
DOB : out std_logic_vector (1 downto 0);
ADDRA : in std_logic_vector (12 downto 0);
ADDRB : in std_logic_vector (12 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (1 downto 0);
DIB : in std_logic_vector (1 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
component RAMB16_S9_S9
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0);
DOPA : out std_logic_vector (0 downto 0);
DOPB : out std_logic_vector (0 downto 0);
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
DIPA : in std_logic_vector (0 downto 0);
DIPB : in std_logic_vector (0 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
component RAMB16_S18_S18
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
DOA : out std_logic_vector (15 downto 0);
DOB : out std_logic_vector (15 downto 0);
DOPA : out std_logic_vector (1 downto 0);
DOPB : out std_logic_vector (1 downto 0);
ADDRA : in std_logic_vector (9 downto 0);
ADDRB : in std_logic_vector (9 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (15 downto 0);
DIB : in std_logic_vector (15 downto 0);
DIPA : in std_logic_vector (1 downto 0);
DIPB : in std_logic_vector (1 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic);
end component;
component RAMB16_S36_S36
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
DOA : out std_logic_vector (31 downto 0);
DOB : out std_logic_vector (31 downto 0);
DOPA : out std_logic_vector (3 downto 0);
DOPB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (31 downto 0);
DIB : in std_logic_vector (31 downto 0);
DIPA : in std_logic_vector (3 downto 0);
DIPB : in std_logic_vector (3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic);
end component;
signal gnd, vcc : std_ulogic;
signal do1, do2, di1, di2 : std_logic_vector(dbits+36 downto 0);
signal addr1, addr2 : std_logic_vector(19 downto 0);
subtype qword is std_logic_vector(dbits+36 downto 0);
type qqtype is array (0 to 3) of qword;
signal qq1 : qqtype;
signal qq2 : qqtype;
signal enable1_t, write1_t : std_logic_vector(3 downto 0);
signal enable2_t, write2_t : std_logic_vector(3 downto 0);
signal ra1, ra2 : std_logic_vector(15 downto 14);
begin
gnd <= '0'; vcc <= '1';
dataout1 <= do1(dbits-1 downto 0); dataout2 <= do2(dbits-1 downto 0);
di1(dbits-1 downto 0) <= datain1; di1(dbits+36 downto dbits) <= (others => '0');
di2(dbits-1 downto 0) <= datain2; di2(dbits+36 downto dbits) <= (others => '0');
addr1(abits-1 downto 0) <= address1; addr1(19 downto abits) <= (others => '0');
addr2(abits-1 downto 0) <= address2; addr2(19 downto abits) <= (others => '0');
a9 : if abits <= 9 generate
x : for i in 0 to ((dbits-1)/36) generate
r0 : RAMB16_S36_S36
generic map(SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
do1(((i+1)*36)-5 downto i*36), do2(((i+1)*36)-5 downto i*36),
do1(((i+1)*36)-1 downto i*36+32), do2(((i+1)*36)-1 downto i*36+32),
addr1(8 downto 0), addr2(8 downto 0), clk1, clk2,
di1(((i+1)*36)-5 downto i*36), di2(((i+1)*36)-5 downto i*36),
di1(((i+1)*36)-1 downto i*36+32), di2(((i+1)*36)-1 downto i*36+32),
enable1, enable2, gnd, gnd, write1, write2);
-- vcc, vcc, gnd, gnd, write1, write2);
end generate;
do1(dbits+36 downto 36*(((dbits-1)/36)+1)) <= (others => '0');
do2(dbits+36 downto 36*(((dbits-1)/36)+1)) <= (others => '0');
end generate;
a10 : if abits = 10 generate
x : for i in 0 to ((dbits-1)/18) generate
r0 : RAMB16_S18_S18
generic map(SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
do1(((i+1)*18)-3 downto i*18), do2(((i+1)*18)-3 downto i*18),
do1(((i+1)*18)-1 downto i*18+16), do2(((i+1)*18)-1 downto i*18+16),
addr1(9 downto 0), addr2(9 downto 0), clk1, clk2,
di1(((i+1)*18)-3 downto i*18), di2(((i+1)*18)-3 downto i*18),
di1(((i+1)*18)-1 downto i*18+16), di2(((i+1)*18)-1 downto i*18+16),
-- vcc, vcc, gnd, gnd, write1, write2);
enable1, enable2, gnd, gnd, write1, write2);
end generate;
do1(dbits+36 downto 18*(((dbits-1)/18)+1)) <= (others => '0');
do2(dbits+36 downto 18*(((dbits-1)/18)+1)) <= (others => '0');
end generate;
a11 : if abits = 11 generate
x : for i in 0 to ((dbits-1)/9) generate
r0 : RAMB16_S9_S9
generic map(SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
do1(((i+1)*9)-2 downto i*9), do2(((i+1)*9)-2 downto i*9),
do1(((i+1)*9)-1 downto i*9+8), do2(((i+1)*9)-1 downto i*9+8),
addr1(10 downto 0), addr2(10 downto 0), clk1, clk2,
di1(((i+1)*9)-2 downto i*9), di2(((i+1)*9)-2 downto i*9),
di1(((i+1)*9)-1 downto i*9+8), di2(((i+1)*9)-1 downto i*9+8),
-- vcc, vcc, gnd, gnd, write1, write2);
enable1, enable2, gnd, gnd, write1, write2);
end generate;
do1(dbits+36 downto 9*(((dbits-1)/9)+1)) <= (others => '0');
do2(dbits+36 downto 9*(((dbits-1)/9)+1)) <= (others => '0');
end generate;
a12 : if abits = 12 generate
x : for i in 0 to ((dbits-1)/4) generate
r0 : RAMB16_S4_S4
generic map(SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
do1(((i+1)*4)-1 downto i*4), do2(((i+1)*4)-1 downto i*4),
addr1(11 downto 0), addr2(11 downto 0), clk1, clk2,
di1(((i+1)*4)-1 downto i*4), di2(((i+1)*4)-1 downto i*4),
-- vcc, vcc, gnd, gnd, write1, write2);
enable1, enable2, gnd, gnd, write1, write2);
end generate;
do1(dbits+36 downto 4*(((dbits-1)/4)+1)) <= (others => '0');
do2(dbits+36 downto 4*(((dbits-1)/4)+1)) <= (others => '0');
end generate;
a13 : if abits = 13 generate
x : for i in 0 to ((dbits-1)/2) generate
r0 : RAMB16_S2_S2
generic map(SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
do1(((i+1)*2)-1 downto i*2), do2(((i+1)*2)-1 downto i*2),
addr1(12 downto 0), addr2(12 downto 0), clk1, clk2,
di1(((i+1)*2)-1 downto i*2), di2(((i+1)*2)-1 downto i*2),
-- vcc, vcc, gnd, gnd, write1, write2);
enable1, enable2, gnd, gnd, write1, write2);
end generate;
do1(dbits+36 downto 2*(((dbits-1)/2)+1)) <= (others => '0');
do2(dbits+36 downto 2*(((dbits-1)/2)+1)) <= (others => '0');
end generate;
a14 : if abits = 14 generate
x : for i in 0 to ((dbits-1)/1) generate
r0 : RAMB16_S1_S1
generic map(SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
do1(((i+1)*1)-1 downto i*1), do2(((i+1)*1)-1 downto i*1),
addr1(13 downto 0), addr2(13 downto 0), clk1, clk2,
di1(((i+1)*1)-1 downto i*1), di2(((i+1)*1)-1 downto i*1),
-- vcc, vcc, gnd, gnd, write1, write2);
enable1, enable2, gnd, gnd, write1, write2);
end generate;
do1(dbits+36 downto dbits) <= (others => '0');
do2(dbits+36 downto dbits) <= (others => '0');
end generate;
a15a16 : if abits >= 15 and abits <= 16 generate
y : for j in 0 to (2**(abits-14))-1 generate
enable1_t(j) <= '1' when ((enable1 = '1') and (conv_integer(addr1(15 downto 14)) = j)) else '0';
write1_t(j) <= '1' when ((write1 = '1') and (conv_integer(addr1(15 downto 14)) = j)) else '0';
enable2_t(j) <= '1' when ((enable2 = '1') and (conv_integer(addr2(15 downto 14)) = j)) else '0';
write2_t(j) <= '1' when ((write2 = '1') and (conv_integer(addr2(15 downto 14)) = j)) else '0';
x : for i in 0 to ((dbits-1)/1) generate
r0 : RAMB16_S1_S1
generic map(SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
qq1(j)(((i+1)*1)-1 downto i*1), qq2(j)(((i+1)*1)-1 downto i*1),
addr1(13 downto 0), addr2(13 downto 0), clk1, clk2,
di1(((i+1)*1)-1 downto i*1), di2(((i+1)*1)-1 downto i*1),
enable1_t(j), enable2_t(j), gnd, gnd, write1_t(j), write2_t(j));
end generate;
end generate;
do1(dbits-1 downto 0) <= qq1(conv_integer(ra1(15 downto 14)))(dbits-1 downto 0);
do2(dbits-1 downto 0) <= qq2(conv_integer(ra2(15 downto 14)))(dbits-1 downto 0);
regs1 : process(clk1)
begin
if rising_edge(clk1) then
ra1(15 downto 14) <= addr1(15 downto 14);
end if;
end process;
regs2 : process(clk2)
begin
if rising_edge(clk2) then
ra2(15 downto 14) <= addr2(15 downto 14);
end if;
end process;
do1(dbits+36 downto dbits) <= (others => '0');
do2(dbits+36 downto dbits) <= (others => '0');
end generate;
-- pragma translate_off
a_to_high : if abits > 16 generate
x : process
begin
assert false
report "Address depth larger than 16 not supported for unisim_syncram_dp"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
entity unisim_syncram_2p is
generic (abits : integer := 6; dbits : integer := 8; sepclk : integer := 0;
wrfst : integer := 0);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0));
end;
architecture behav of unisim_syncram_2p is
component unisim_syncram_dp
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic
);
end component;
component generic_syncram_2p
generic (abits : integer := 8; dbits : integer := 32; sepclk : integer := 0);
port (
rclk : in std_ulogic;
wclk : in std_ulogic;
rdaddress: in std_logic_vector (abits -1 downto 0);
wraddress: in std_logic_vector (abits -1 downto 0);
data: in std_logic_vector (dbits -1 downto 0);
wren : in std_ulogic;
q: out std_logic_vector (dbits -1 downto 0)
);
end component;
signal write2, renable2 : std_ulogic;
signal datain2 : std_logic_vector((dbits-1) downto 0);
begin
-- nowf: if wrfst = 0 generate
write2 <= '0'; renable2 <= renable; datain2 <= (others => '0');
-- end generate;
-- wf : if wrfst = 1 generate
-- write2 <= '0' when (waddress /= raddress) else write;
-- renable2 <= renable or write2; datain2 <= datain;
-- end generate;
a0 : if abits <= 5 and GRLIB_CONFIG_ARRAY(grlib_techmap_strict_ram) = 0 generate
x0 : generic_syncram_2p generic map (abits, dbits, sepclk)
port map (rclk, wclk, raddress, waddress, datain, write, dataout);
end generate;
a6 : if abits > 5 or GRLIB_CONFIG_ARRAY(grlib_techmap_strict_ram) /= 0 generate
x0 : unisim_syncram_dp generic map (abits, dbits)
port map (wclk, waddress, datain, open, write, write,
rclk, raddress, datain2, dataout, renable2, write2);
end generate;
end;
-- parametrisable sync ram generator using unisim block rams
library ieee;
use ieee.std_logic_1164.all;
--pragma translate_off
library unisim;
use unisim.RAMB16_S36_S36;
--pragma translate_on
entity unisim_syncram64 is
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (63 downto 0);
dataout : out std_logic_vector (63 downto 0);
enable : in std_logic_vector (1 downto 0);
write : in std_logic_vector (1 downto 0)
);
end;
architecture behav of unisim_syncram64 is
component unisim_syncram
generic ( abits : integer := 9; dbits : integer := 32);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (dbits -1 downto 0);
dataout : out std_logic_vector (dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end component;
component RAMB16_S36_S36
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
DOA : out std_logic_vector (31 downto 0);
DOB : out std_logic_vector (31 downto 0);
DOPA : out std_logic_vector (3 downto 0);
DOPB : out std_logic_vector (3 downto 0);
ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (31 downto 0);
DIB : in std_logic_vector (31 downto 0);
DIPA : in std_logic_vector (3 downto 0);
DIPB : in std_logic_vector (3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic);
end component;
signal gnd : std_logic_vector(3 downto 0);
signal xa, ya : std_logic_vector(19 downto 0);
begin
gnd <= "0000";
xa(abits-1 downto 0) <= address; xa(19 downto abits) <= (others => '0');
ya(abits-1 downto 0) <= address; ya(19 downto abits) <= (others => '1');
a8 : if abits <= 8 generate
r0 : RAMB16_S36_S36
generic map(SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
dataout(63 downto 32), dataout(31 downto 0), open, open,
xa(8 downto 0), ya(8 downto 0), clk, clk,
datain(63 downto 32), datain(31 downto 0), gnd, gnd,
enable(1), enable(0), gnd(0), gnd(0), write(1), write(0));
end generate;
a9 : if abits > 8 generate
x1 : unisim_syncram generic map ( abits, 32)
port map (clk, address, datain(63 downto 32), dataout(63 downto 32),
enable(1), write(1));
x2 : unisim_syncram generic map ( abits, 32)
port map (clk, address, datain(31 downto 0), dataout(31 downto 0),
enable(0), write(0));
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
entity unisim_syncram128 is
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (127 downto 0);
dataout : out std_logic_vector (127 downto 0);
enable : in std_logic_vector (3 downto 0);
write : in std_logic_vector (3 downto 0)
);
end;
architecture behav of unisim_syncram128 is
component unisim_syncram64 is
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (63 downto 0);
dataout : out std_logic_vector (63 downto 0);
enable : in std_logic_vector (1 downto 0);
write : in std_logic_vector (1 downto 0)
);
end component;
begin
x0 : unisim_syncram64 generic map (abits)
port map (clk, address, datain(127 downto 64), dataout(127 downto 64),
enable(3 downto 2), write(3 downto 2));
x1 : unisim_syncram64 generic map (abits)
port map (clk, address, datain(63 downto 0), dataout(63 downto 0),
enable(1 downto 0), write(1 downto 0));
end;
library ieee;
use ieee.std_logic_1164.all;
--pragma translate_off
library unisim;
use unisim.RAMB16_S36_S36;
--pragma translate_on
entity unisim_syncram128bw is
generic ( abits : integer := 9);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (127 downto 0);
dataout : out std_logic_vector (127 downto 0);
enable : in std_logic_vector (15 downto 0);
write : in std_logic_vector (15 downto 0)
);
end;
architecture behav of unisim_syncram128bw is
component unisim_syncram
generic ( abits : integer := 9; dbits : integer := 32);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (dbits -1 downto 0);
dataout : out std_logic_vector (dbits -1 downto 0);
enable : in std_ulogic;
write : in std_ulogic
);
end component;
component RAMB16_S9_S9
generic (SIM_COLLISION_CHECK : string := "ALL");
port (
DOA : out std_logic_vector (7 downto 0);
DOB : out std_logic_vector (7 downto 0);
DOPA : out std_logic_vector (0 downto 0);
DOPB : out std_logic_vector (0 downto 0);
ADDRA : in std_logic_vector (10 downto 0);
ADDRB : in std_logic_vector (10 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (7 downto 0);
DIPA : in std_logic_vector (0 downto 0);
DIPB : in std_logic_vector (0 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_ulogic;
WEB : in std_ulogic
);
end component;
signal gnd : std_logic_vector(3 downto 0);
signal xa, ya : std_logic_vector(19 downto 0);
begin
gnd <= "0000";
xa(abits-1 downto 0) <= address; xa(19 downto abits) <= (others => '0');
ya(abits-1 downto 0) <= address; ya(19 downto abits) <= (others => '1');
a11 : if abits <= 10 generate
x0 : for i in 0 to 7 generate
r0 : RAMB16_S9_S9
generic map(SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
dataout(i*8+7+64 downto i*8+64), dataout(i*8+7 downto i*8), open, open,
xa(10 downto 0), ya(10 downto 0), clk, clk,
datain(i*8+7+64 downto i*8+64), datain(i*8+7 downto i*8), gnd(0 downto 0), gnd(0 downto 0),
enable(i+8), enable(i), gnd(0), gnd(0), write(i+8), write(i));
end generate;
end generate;
a12 : if abits > 10 generate
x0 : for i in 0 to 15 generate
x2 : unisim_syncram generic map ( abits, 8)
port map (clk, address, datain(i*8+7 downto i*8),
dataout(i*8+7 downto i*8), enable(i), write(i));
end generate;
end generate;
end;
-------------------------
-- unisim_syncram with byte enable
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.orv;
use grlib.config_types.all;
use grlib.config.all;
--pragma translate_off
library unisim;
use unisim.RAMB36;
use unisim.RAMB18;
use unisim.RAMB18SDP;
--pragma translate_on
entity unisim_syncram_be is
generic ( abits : integer := 9; dbits : integer := 32; tech : integer := 0);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (dbits -1 downto 0);
dataout : out std_logic_vector (dbits -1 downto 0);
enable : in std_logic_vector (dbits/8-1 downto 0);
write : in std_logic_vector(dbits/8-1 downto 0)
);
end;
architecture behav of unisim_syncram_be is
-- Virtex5 primitives --
component RAMB36
generic (
READ_WIDTH_A : integer := 0;
READ_WIDTH_B : integer := 0;
SIM_COLLISION_CHECK : string := "ALL";
WRITE_WIDTH_A : integer := 0;
WRITE_WIDTH_B : integer := 0
);
port (
CASCADEOUTLATA : out std_ulogic;
CASCADEOUTLATB : out std_ulogic;
CASCADEOUTREGA : out std_ulogic;
CASCADEOUTREGB : out std_ulogic;
DOA : out std_logic_vector(31 downto 0);
DOB : out std_logic_vector(31 downto 0);
DOPA : out std_logic_vector(3 downto 0);
DOPB : out std_logic_vector(3 downto 0);
ADDRA : in std_logic_vector(15 downto 0);
ADDRB : in std_logic_vector(15 downto 0);
CASCADEINLATA : in std_ulogic;
CASCADEINLATB : in std_ulogic;
CASCADEINREGA : in std_ulogic;
CASCADEINREGB : in std_ulogic;
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector(31 downto 0);
DIB : in std_logic_vector(31 downto 0);
DIPA : in std_logic_vector(3 downto 0);
DIPB : in std_logic_vector(3 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
REGCEA : in std_ulogic;
REGCEB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_logic_vector(3 downto 0);
WEB : in std_logic_vector(3 downto 0)
);
end component;
component RAMB18
generic (
READ_WIDTH_A : integer := 0;
READ_WIDTH_B : integer := 0;
SIM_COLLISION_CHECK : string := "ALL";
WRITE_WIDTH_A : integer := 0;
WRITE_WIDTH_B : integer := 0
);
port (
DOA : out std_logic_vector(15 downto 0);
DOB : out std_logic_vector(15 downto 0);
DOPA : out std_logic_vector(1 downto 0);
DOPB : out std_logic_vector(1 downto 0);
ADDRA : in std_logic_vector(13 downto 0);
ADDRB : in std_logic_vector(13 downto 0);
CLKA : in std_ulogic;
CLKB : in std_ulogic;
DIA : in std_logic_vector(15 downto 0);
DIB : in std_logic_vector(15 downto 0);
DIPA : in std_logic_vector(1 downto 0);
DIPB : in std_logic_vector(1 downto 0);
ENA : in std_ulogic;
ENB : in std_ulogic;
REGCEA : in std_ulogic;
REGCEB : in std_ulogic;
SSRA : in std_ulogic;
SSRB : in std_ulogic;
WEA : in std_logic_vector(1 downto 0);
WEB : in std_logic_vector(1 downto 0)
);
end component;
component RAMB18SDP
generic (
DO_REG : integer := 0;
SIM_COLLISION_CHECK : string := "ALL";
SIM_MODE : string := "SAFE");
port (
DO : out std_logic_vector(31 downto 0);
DOP : out std_logic_vector(3 downto 0);
DI : in std_logic_vector(31 downto 0);
DIP : in std_logic_vector(3 downto 0);
RDADDR : in std_logic_vector(8 downto 0);
RDCLK : in std_ulogic;
RDEN : in std_ulogic;
REGCE : in std_ulogic;
SSR : in std_ulogic;
WE : in std_logic_vector(3 downto 0);
WRADDR : in std_logic_vector(8 downto 0);
WRCLK : in std_ulogic;
WREN : in std_ulogic
);
end component;
-----------------------
component generic_syncram
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
write : in std_ulogic);
end component;
signal gnd, xenable : std_ulogic;
signal do, di : std_logic_vector(dbits+32 downto 0);
signal xa : std_logic_vector(19 downto 0);
type xd_type is array (0 to 255) of std_logic_vector(15 downto 0);
signal xdi, xdo : xd_type;
type xd36_type is array (0 to 255) of std_logic_vector(31 downto 0);
signal xdi36, xdo36 : xd36_type;
signal xwen : std_logic;
type xwen_type is array (0 to 255) of std_logic_vector(1 downto 0);
signal xwen18 : xwen_type;
type xwen36_type is array (0 to 255) of std_logic_vector(3 downto 0);
signal xwen36 : xwen36_type;
begin
gnd <= '0';
dataout <= do(dbits-1 downto 0);
di(dbits-1 downto 0) <= datain;
di(dbits+32 downto dbits) <= (others => '0');
a0 : if (abits <= 5) and (GRLIB_CONFIG_ARRAY(grlib_techmap_strict_ram) = 0) generate
x : for i in 0 to ((dbits-1)/8) generate
r : generic_syncram generic map (abits, 8)
port map (clk, address, di(i*8+8-1 downto i*8), do(i*8+8-1 downto i*8), write(i));
end generate;
do(dbits+32 downto 8*(((dbits-1)/8)+1)) <= (others => '0');
end generate;
a8 : if ((abits > 5 or GRLIB_CONFIG_ARRAY(grlib_techmap_strict_ram) /= 0) and
(abits <= 9)) generate
xa(19 downto abits) <= (others => '0');
xa(abits-1 downto 0) <= address;
xenable <= orv(enable);
xwen <= orv(write);
x : for i in 0 to ((dbits-1)/32) generate
r0 : RAMB18SDP
generic map (SIM_COLLISION_CHECK => "GENERATE_X_ONLY")
port map (
DO => do(i*32+32-1 downto i*32),
DOP => open,
DI => di(i*32+32-1 downto i*32),
DIP => x"F",
RDADDR => xa(8 downto 0),
WRADDR => xa(8 downto 0),
RDCLK => clk,
WRCLK => clk,
RDEN => xenable,
REGCE => gnd,
SSR => gnd,
WE => write(i*4+4-1 downto i*4),
WREN => xwen);
end generate;
do(dbits+32 downto 32*(((dbits-1)/32)+1)) <= (others => '0');
end generate;
a10 : if (abits = 10) generate
xa(19 downto 14) <= (others => '0');
xa(3 downto 0) <= (others => '0');
xa(13 downto 4) <= address;
xenable <= orv(enable);
x : for i in 0 to ((dbits-1)/16) generate
r : RAMB18 generic map (READ_WIDTH_A => 18, READ_WIDTH_B => 18,
SIM_COLLISION_CHECK => "GENERATE_X_ONLY",
WRITE_WIDTH_A => 18, WRITE_WIDTH_B => 18)
port map(
DOA => open,
DOB => do(i*16+16-1 downto i*16),
DOPA => open,
DOPB => open,
ADDRA => xa(13 downto 0),
ADDRB => xa(13 downto 0),
CLKA => clk,
CLKB => clk,
DIA => di(i*16+16-1 downto i*16),
DIB => x"FFFF",
DIPA => "11",
DIPB => "11",
ENA => xenable,
ENB => xenable,
REGCEA => '0',
REGCEB => '0',
SSRA => '0',
SSRB => '0',
WEA => write(i*2+2-1 downto i*2),
WEB => "00");
end generate;
do(dbits+32 downto 16*(((dbits-1)/16)+1)) <= (others => '0');
end generate;
a11 : if abits = 11 generate
xa(19 downto 14) <= (others => '0');
xa(2 downto 0) <= (others => '0');
xa(13 downto 3) <= address;
xenable <= orv(enable);
x : for i in 0 to ((dbits-1)/8) generate
xwen18(i) <= '0'&write(i);
xdi(i) <= x"00"&di(i*8+8-1 downto i*8);
do(i*8+8-1 downto i*8) <= xdo(i)(7 downto 0);
r : RAMB18 generic map (READ_WIDTH_A => 9, READ_WIDTH_B => 9,
SIM_COLLISION_CHECK => "GENERATE_X_ONLY",
WRITE_WIDTH_A => 9, WRITE_WIDTH_B => 9)
port map(
DOA => open,
DOB => xdo(i),
DOPA => open,
DOPB => open,
ADDRA => xa(13 downto 0),
ADDRB => xa(13 downto 0),
CLKA => clk,
CLKB => clk,
DIA => xdi(i),
DIB => x"FFFF",
DIPA => "11",
DIPB => "11",
ENA => xenable,
ENB => xenable,
REGCEA => '0',
REGCEB => '0',
SSRA => '0',
SSRB => '0',
WEA => xwen18(i),
WEB => "00");
end generate;
do(dbits+32 downto 8*(((dbits-1)/8)+1)) <= (others => '0');
end generate;
a12 : if abits = 12 generate
xa(19 downto 14) <= (others => '0');
xa(1 downto 0) <= (others => '0');
xa(13 downto 2) <= address;
xenable <= orv(enable);
x : for i in 0 to ((dbits-1)/4) generate
xwen18(i) <= '0'&write(i/2);
xdi(i) <= x"000"&di(i*4+4-1 downto i*4);
do(i*4+4-1 downto i*4) <= xdo(i)(3 downto 0);
r : RAMB18 generic map (READ_WIDTH_A => 4, READ_WIDTH_B => 4,
SIM_COLLISION_CHECK => "GENERATE_X_ONLY",
WRITE_WIDTH_A => 4, WRITE_WIDTH_B => 4)
port map(
DOA => open,
DOB => xdo(i),
DOPA => open,
DOPB => open,
ADDRA => xa(13 downto 0),
ADDRB => xa(13 downto 0),
CLKA => clk,
CLKB => clk,
DIA => xdi(i),
DIB => x"FFFF",
DIPA => "11",
DIPB => "11",
ENA => xenable,
ENB => xenable,
REGCEA => '0',
REGCEB => '0',
SSRA => '0',
SSRB => '0',
WEA => xwen18(i),
WEB => "00");
end generate;
do(dbits+32 downto 4*(((dbits-1)/4)+1)) <= (others => '0');
end generate;
a13 : if abits = 13 generate
xa(19 downto 14) <= (others => '0');
xa(0) <= '0';
xa(13 downto 1) <= address;
xenable <= orv(enable);
x : for i in 0 to ((dbits-1)/2) generate
xwen18(i) <= '0'&write(i/4);
xdi(i)(15 downto 2) <= (others=>'0');
xdi(i)(1 downto 0) <= di(i*2+2-1 downto i*2);
do(i*2+2-1 downto i*2) <= xdo(i)(1 downto 0);
r : RAMB18 generic map (READ_WIDTH_A => 2, READ_WIDTH_B => 2,
SIM_COLLISION_CHECK => "GENERATE_X_ONLY",
WRITE_WIDTH_A => 2, WRITE_WIDTH_B => 2)
port map(
DOA => open,
DOB => xdo(i),
DOPA => open,
DOPB => open,
ADDRA => xa(13 downto 0),
ADDRB => xa(13 downto 0),
CLKA => clk,
CLKB => clk,
DIA => xdi(i),
DIB => x"FFFF",
DIPA => "11",
DIPB => "11",
ENA => xenable,
ENB => xenable,
REGCEA => '0',
REGCEB => '0',
SSRA => '0',
SSRB => '0',
WEA => xwen18(i),
WEB => "00");
end generate;
do(dbits+32 downto 2*(((dbits-1)/2)+1)) <= (others => '0');
end generate;
a14 : if abits = 14 generate
xa(19 downto 14) <= (others => '0');
xa(13 downto 0) <= address;
xenable <= orv(enable);
x : for i in 0 to (dbits-1) generate
xwen18(i) <= '0'&write(i/8);
xdi(i)(15 downto 1) <= (others=>'0');
xdi(i)(0) <= di(i);
do(i) <= xdo(i)(0);
r : RAMB18 generic map (READ_WIDTH_A => 1, READ_WIDTH_B => 1,
SIM_COLLISION_CHECK => "GENERATE_X_ONLY",
WRITE_WIDTH_A => 1, WRITE_WIDTH_B => 1)
port map(
DOA => open,
DOB => xdo(i),
DOPA => open,
DOPB => open,
ADDRA => xa(13 downto 0),
ADDRB => xa(13 downto 0),
CLKA => clk,
CLKB => clk,
DIA => xdi(i),
DIB => x"FFFF",
DIPA => "11",
DIPB => "11",
ENA => xenable,
ENB => xenable,
REGCEA => '0',
REGCEB => '0',
SSRA => '0',
SSRB => '0',
WEA => xwen18(i),
WEB => "00");
end generate;
do(dbits+32 downto dbits) <= (others => '0');
end generate;
a15 : if abits = 15 generate
xa(19 downto 15) <= (others => '0');
xa(14 downto 0) <= address;
xenable <= orv(enable);
x : for i in 0 to (dbits-1) generate
xwen36(i) <= "000"&write(i/8);
xdi36(i)(31 downto 1) <= (others=>'0');
xdi36(i)(0) <= di(i);
do(i) <= xdo36(i)(0);
r : RAMB36 generic map(READ_WIDTH_A => 1, READ_WIDTH_B => 1,
SIM_COLLISION_CHECK => "GENERATE_X_ONLY",
WRITE_WIDTH_A => 1, WRITE_WIDTH_B => 1)
port map(
CASCADEOUTLATA => open,
CASCADEOUTLATB => open,
CASCADEOUTREGA => open,
CASCADEOUTREGB => open,
CASCADEINLATA => '0',
CASCADEINLATB => '0',
CASCADEINREGA => '0',
CASCADEINREGB => '0',
DOA => open,
DOB => xdo36(i),
DOPA => open,
DOPB => open,
ADDRA => xa(15 downto 0),
ADDRB => xa(15 downto 0),
CLKA => clk,
CLKB => clk,
DIA => xdi36(i),
DIB => x"FFFFFFFF",
DIPA => "1111",
DIPB => "1111",
ENA => xenable,
ENB => xenable,
REGCEA => '0',
REGCEB => '0',
SSRA => '0',
SSRB => '0',
WEA => xwen36(i),
WEB => "0000");
end generate;
do(dbits+32 downto dbits) <= (others => '0');
end generate;
a16 : if (abits > 15) generate
x : for i in 0 to ((dbits-1)/8) generate
r : generic_syncram generic map (abits, 8)
port map (clk, address, di(i*8+8-1 downto i*8), do(i*8+8-1 downto i*8), write(i));
end generate;
do(dbits+32 downto 8*(((dbits-1)/8)+1)) <= (others => '0');
end generate;
--pragma translate_off
gen_sram : if abits > 15 generate
x : process
begin
report "Address depth larger than 15 not supported for unisim_syncram_be. It will be implemented using inferred syncram.";
wait;
end process;
end generate;
--pragma translate_on
end;
|
library ieee;
use ieee.std_logic_1164.all;
use work.memory_types.all;
entity test_vga_rom is
end test_vga_rom;
architecture behavioural of test_vga_rom is
component VGA_ROM is
generic (
contents: vga_memory
);
port (
clock : in std_logic;
enable : in std_logic;
address : in natural range vga_memory'range;
data : out std_logic_vector(7 downto 0)
);
end component;
signal clock : std_logic;
signal enable : std_logic;
signal address : natural range vga_memory'range;
signal output : std_logic_vector(7 downto 0);
constant test_storage : vga_memory := (
0 => "00000000",
1 => "00000001",
2 => "00000010",
3 => "00000011",
4 => "00000100",
5 => "11110000",
6 => "11110000",
7 => "11110000",
8 => "11110000",
9 => "11110000",
10 => "11110000",
11 => "11110000",
12 => "11110000",
13 => "11110000",
14 => "11110000",
15 => "11110000",
others => "00000000"
);
begin
ROMCELL : VGA_ROM generic map (test_storage)
port map (clock, enable, address, output);
process
begin
enable <= '1';
address <= 0;
clock <= '0';
wait for 1 ns;
clock <= '1';
wait for 1 ns;
assert output = "00000000"
report "result should be 0" severity error;
address <= 1;
clock <= '0';
wait for 1 ns;
clock <= '1';
wait for 1 ns;
assert output = "00000001"
report "result should be 1" severity error;
address <= 2000;
clock <= '0';
wait for 1 ns;
clock <= '1';
wait for 1 ns;
assert output = "00000000"
report "result should be zero" severity error;
enable <= '0';
address <= 1;
clock <= '0';
wait for 1 ns;
clock <= '1';
wait for 1 ns;
assert output = "00000000"
report "result should be 0 when disabled" severity error;
wait;
end process;
end behavioural;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_multiplier is
generic (
DEDICATED_MULTIPLIER_CIRCUITRY : string := "AUTO";
SIGNED : natural := 0;
OUTPUTMSB : integer := 8;
AWIDTH : natural := 8;
BWIDTH : natural := 8;
OUTPUTLSB : integer := 0;
PIPELINE : integer := 0
);
port (
user_aclr : in std_logic := '0';
result : out std_logic_vector(OutputMsb-OutputLsb+1-1 downto 0);
clock : in std_logic := '0';
dataa : in std_logic_vector(aWidth-1 downto 0) := (others=>'0');
datab : in std_logic_vector(bWidth-1 downto 0) := (others=>'0');
aclr : in std_logic := '0';
ena : in std_logic := '0'
);
end entity alt_dspbuilder_multiplier;
architecture rtl of alt_dspbuilder_multiplier is
component alt_dspbuilder_multiplier_GNEIWYOKUR is
generic (
DEDICATED_MULTIPLIER_CIRCUITRY : string := "YES";
SIGNED : natural := 0;
OUTPUTMSB : integer := 47;
AWIDTH : natural := 24;
BWIDTH : natural := 24;
OUTPUTLSB : integer := 0;
PIPELINE : integer := 0
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
dataa : in std_logic_vector(24-1 downto 0) := (others=>'0');
datab : in std_logic_vector(24-1 downto 0) := (others=>'0');
ena : in std_logic := '0';
result : out std_logic_vector(48-1 downto 0);
user_aclr : in std_logic := '0'
);
end component alt_dspbuilder_multiplier_GNEIWYOKUR;
begin
alt_dspbuilder_multiplier_GNEIWYOKUR_0: if ((DEDICATED_MULTIPLIER_CIRCUITRY = "YES") and (SIGNED = 0) and (OUTPUTMSB = 47) and (AWIDTH = 24) and (BWIDTH = 24) and (OUTPUTLSB = 0) and (PIPELINE = 0)) generate
inst_alt_dspbuilder_multiplier_GNEIWYOKUR_0: alt_dspbuilder_multiplier_GNEIWYOKUR
generic map(DEDICATED_MULTIPLIER_CIRCUITRY => "YES", SIGNED => 0, OUTPUTMSB => 47, AWIDTH => 24, BWIDTH => 24, OUTPUTLSB => 0, PIPELINE => 0)
port map(aclr => aclr, clock => clock, dataa => dataa, datab => datab, ena => ena, result => result, user_aclr => user_aclr);
end generate;
assert not (((DEDICATED_MULTIPLIER_CIRCUITRY = "YES") and (SIGNED = 0) and (OUTPUTMSB = 47) and (AWIDTH = 24) and (BWIDTH = 24) and (OUTPUTLSB = 0) and (PIPELINE = 0)))
report "Please run generate again" severity error;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_multiplier is
generic (
DEDICATED_MULTIPLIER_CIRCUITRY : string := "AUTO";
SIGNED : natural := 0;
OUTPUTMSB : integer := 8;
AWIDTH : natural := 8;
BWIDTH : natural := 8;
OUTPUTLSB : integer := 0;
PIPELINE : integer := 0
);
port (
user_aclr : in std_logic := '0';
result : out std_logic_vector(OutputMsb-OutputLsb+1-1 downto 0);
clock : in std_logic := '0';
dataa : in std_logic_vector(aWidth-1 downto 0) := (others=>'0');
datab : in std_logic_vector(bWidth-1 downto 0) := (others=>'0');
aclr : in std_logic := '0';
ena : in std_logic := '0'
);
end entity alt_dspbuilder_multiplier;
architecture rtl of alt_dspbuilder_multiplier is
component alt_dspbuilder_multiplier_GNEIWYOKUR is
generic (
DEDICATED_MULTIPLIER_CIRCUITRY : string := "YES";
SIGNED : natural := 0;
OUTPUTMSB : integer := 47;
AWIDTH : natural := 24;
BWIDTH : natural := 24;
OUTPUTLSB : integer := 0;
PIPELINE : integer := 0
);
port (
aclr : in std_logic := '0';
clock : in std_logic := '0';
dataa : in std_logic_vector(24-1 downto 0) := (others=>'0');
datab : in std_logic_vector(24-1 downto 0) := (others=>'0');
ena : in std_logic := '0';
result : out std_logic_vector(48-1 downto 0);
user_aclr : in std_logic := '0'
);
end component alt_dspbuilder_multiplier_GNEIWYOKUR;
begin
alt_dspbuilder_multiplier_GNEIWYOKUR_0: if ((DEDICATED_MULTIPLIER_CIRCUITRY = "YES") and (SIGNED = 0) and (OUTPUTMSB = 47) and (AWIDTH = 24) and (BWIDTH = 24) and (OUTPUTLSB = 0) and (PIPELINE = 0)) generate
inst_alt_dspbuilder_multiplier_GNEIWYOKUR_0: alt_dspbuilder_multiplier_GNEIWYOKUR
generic map(DEDICATED_MULTIPLIER_CIRCUITRY => "YES", SIGNED => 0, OUTPUTMSB => 47, AWIDTH => 24, BWIDTH => 24, OUTPUTLSB => 0, PIPELINE => 0)
port map(aclr => aclr, clock => clock, dataa => dataa, datab => datab, ena => ena, result => result, user_aclr => user_aclr);
end generate;
assert not (((DEDICATED_MULTIPLIER_CIRCUITRY = "YES") and (SIGNED = 0) and (OUTPUTMSB = 47) and (AWIDTH = 24) and (BWIDTH = 24) and (OUTPUTLSB = 0) and (PIPELINE = 0)))
report "Please run generate again" severity error;
end architecture rtl;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SPI_MasterTB is
end entity; --SPI_MasterTB
architecture tb of SPI_MasterTB is
constant G_CLOCK_FREQUENCY : integer := 100E6;
constant G_CLOCK_DIVIDER : integer := 100;
constant G_SPI_TRANSACTION_SIZE : integer := 32;
--declarations
signal clock : std_logic := '0';
signal clock_n : std_logic := '0';
signal enable : std_logic := '0';
signal clock_divider1 : integer := 1000;
signal clock_output1 : std_logic := '0';
begin
clock <= not clock after (1 sec / G_CLOCK_FREQUENCY) / 2;
clock_n <= not clock;
Test:process
begin
wait for 100 ns;
enable <= '1';
wait for 10 us;
enable <= '0';
wait for 1 ms;
end process; --Test
dut : entity work.SPI_Master
generic map
(
G_CLOCK_FREQUENCY => G_CLOCK_FREQUENCY,
G_SPI_FREQUENCY => G_SPI_FREQUENCY,
G_SPI_TRANSACTION_SIZE => G_SPI_TRANSACTION_SIZE
)
port map
(
clock => clock,
enable => enable
);
end architecture; -- tb |
library ieee;
use ieee.std_logic_1164.all;
use work.utils_pkg.all;
entity event_hold_stage_tb is
end event_hold_stage_tb;
architecture tb of event_hold_stage_tb is
signal dout : std_logic := '0';
signal din : std_logic := '0';
signal period : std_logic := '0';
signal clk : std_logic := '0';
begin
clk <= not clk after 10 NS; -- 50 Mhz clock
uut : event_hold_stage
port map (
dout_p => dout,
din_p => din,
period_p => period,
clk => clk);
process
begin
wait for 10 NS;
din <= '1';
wait for 20 NS;
din <= '0';
wait for 100 NS;
period <= '1';
wait for 20 NS;
period <= '0';
wait for 100 NS;
period <= '1';
wait for 20 NS;
period <= '0';
wait for 100 NS;
period <= '1';
din <= '1';
wait for 20 NS;
period <= '0';
din <= '0';
wait for 100 NS;
period <= '1';
wait for 20 NS;
period <= '0';
wait for 100 NS;
period <= '1';
wait for 20 NS;
period <= '0';
wait for 100 US;
end process;
end tb;
|
library ieee;
use ieee.std_logic_1164.all;
use work.utils_pkg.all;
entity event_hold_stage_tb is
end event_hold_stage_tb;
architecture tb of event_hold_stage_tb is
signal dout : std_logic := '0';
signal din : std_logic := '0';
signal period : std_logic := '0';
signal clk : std_logic := '0';
begin
clk <= not clk after 10 NS; -- 50 Mhz clock
uut : event_hold_stage
port map (
dout_p => dout,
din_p => din,
period_p => period,
clk => clk);
process
begin
wait for 10 NS;
din <= '1';
wait for 20 NS;
din <= '0';
wait for 100 NS;
period <= '1';
wait for 20 NS;
period <= '0';
wait for 100 NS;
period <= '1';
wait for 20 NS;
period <= '0';
wait for 100 NS;
period <= '1';
din <= '1';
wait for 20 NS;
period <= '0';
din <= '0';
wait for 100 NS;
period <= '1';
wait for 20 NS;
period <= '0';
wait for 100 NS;
period <= '1';
wait for 20 NS;
period <= '0';
wait for 100 US;
end process;
end tb;
|
--------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 28-03-2016
-- Module Name: p9.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity counter is
generic (N : integer := 4);
port (clk, reset : in std_logic;
count : out std_logic_vector (N - 1 downto 0));
end entity counter;
architecture behavioral of counter is
begin
process (clk, reset)
variable count_buff : std_logic_vector (N - 1 downto 0) := (others => '0');
begin
if clk'event and clk = '1' then
count <= count_buff;
count_buff := count_buff + '1';
end if;
if reset = '1' then
count_buff := (others => '0');
count <= count_buff;
end if;
end process;
end architecture behavioral;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_ch_03_16.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity ch_03_16 is
end entity ch_03_16;
architecture test of ch_03_16 is
begin
-- code from book:
hiding_example : process is
variable a, b : integer;
begin
a := 10;
for a in 0 to 7 loop
b := a;
end loop;
-- a = 10, and b = 7
-- . . .
-- not in book:
wait;
-- end not in book
end process hiding_example;
-- end of code from book
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_ch_03_16.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity ch_03_16 is
end entity ch_03_16;
architecture test of ch_03_16 is
begin
-- code from book:
hiding_example : process is
variable a, b : integer;
begin
a := 10;
for a in 0 to 7 loop
b := a;
end loop;
-- a = 10, and b = 7
-- . . .
-- not in book:
wait;
-- end not in book
end process hiding_example;
-- end of code from book
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_03_ch_03_16.vhd,v 1.3 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity ch_03_16 is
end entity ch_03_16;
architecture test of ch_03_16 is
begin
-- code from book:
hiding_example : process is
variable a, b : integer;
begin
a := 10;
for a in 0 to 7 loop
b := a;
end loop;
-- a = 10, and b = 7
-- . . .
-- not in book:
wait;
-- end not in book
end process hiding_example;
-- end of code from book
end architecture test;
|
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Solving_Key_Equation_1
-- Module Name: Solving_Key_Equation_1
-- Project Name: McEliece QD-Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The 2nd step in Goppa Code Decoding.
--
-- This circuit solves the polynomial key equation sigma with the polynomial syndrome.
-- To solve the key equation, this circuit employs a modified extended euclidean algorithm
-- The modification is made to stop the algorithm when polynomial, represented here as G, has
-- degree less or equal than the polynomial key equation sigma desired degree.
-- The syndrome is the input and expected to be of degree 2*final_degree, and after computations
-- polynomial C, will hold sigma with degree less or equal to final_degree.
--
-- This is the first circuit version. It is a non pipeline version of the algorithm,
-- each coefficient takes more than 1 cycle to be computed.
-- A more optimized version, still non pipeline was made called solving_key_equation_1_v2
-- This improved version, has new address resolution logic and internal degree counters.
--
-- Parameters
--
-- gf_2_m :
--
-- The size of the field used in this circuit. This parameter depends of the
-- Goppa code used.
--
-- final_degree :
--
-- The final degree size expected for polynomial sigma to have. This parameter depends
-- of the Goppa code used.
--
-- size_final_degree :
--
-- The number of bits necessary to hold the polynomial with degree of final_degree, which
-- has final_degree + 1 coefficients. This is ceil(log2(final_degree+1)).
--
-- Dependencies:
--
-- VHDL-93
--
-- controller_solving_key_equation_1 Rev 1.0
-- register_nbits Rev 1.0
-- register_rst_nbits Rev 1.0
-- counter_decrement_rst_nbits Rev 1.0
-- mult_gf_2_m Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity solving_key_equation_1 is
Generic(
-- GOPPA [2048, 1751, 27, 11] --
gf_2_m : integer range 1 to 20 := 11;
final_degree : integer := 27;
size_final_degree : integer := 5
-- GOPPA [2048, 1498, 50, 11] --
-- gf_2_m : integer range 1 to 20 := 11;
-- final_degree : integer := 50;
-- size_final_degree : integer := 6
-- GOPPA [3307, 2515, 66, 12] --
-- gf_2_m : integer range 1 to 20 := 11;
-- final_degree : integer := 50;
-- size_final_degree : integer := 6
-- QD-GOPPA [2528, 2144, 32, 12] --
-- gf_2_m : integer range 1 to 20 := 12;
-- final_degree : integer := 32;
-- size_final_degree : integer := 5
-- QD-GOPPA [2816, 2048, 64, 12] --
-- gf_2_m : integer range 1 to 20 := 12;
-- final_degree : integer := 64;
-- size_final_degree : integer := 6
-- QD-GOPPA [3328, 2560, 64, 12] --
-- gf_2_m : integer range 1 to 20 := 12;
-- final_degree : integer := 64;
-- size_final_degree : integer := 6
-- QD-GOPPA [7296, 5632, 128, 13] --
-- gf_2_m : integer range 1 to 20 := 13;
-- final_degree : integer := 128;
-- size_final_degree : integer := 7
);
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
ready_inv : in STD_LOGIC;
value_FB : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_GC : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_inv : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal_inv : out STD_LOGIC;
key_equation_found : out STD_LOGIC;
write_enable_FB : out STD_LOGIC;
write_enable_GC : out STD_LOGIC;
new_value_inv : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_FB : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_GC : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
address_FB : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_GC : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0)
);
end solving_key_equation_1;
architecture Behavioral of solving_key_equation_1 is
component controller_solving_key_equation_1
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
ready_inv : in STD_LOGIC;
FB_equal_zero : in STD_LOGIC;
i_equal_zero : in STD_LOGIC;
i_minus_j_less_than_zero : in STD_LOGIC;
degree_G_less_equal_final_degree : in STD_LOGIC;
degree_F_less_than_degree_G : in STD_LOGIC;
degree_B_equal_degree_C_plus_j : in STD_LOGIC;
degree_B_less_than_degree_C_plus_j : in STD_LOGIC;
reg_looking_degree_q : in STD_LOGIC_VECTOR(0 downto 0);
key_equation_found : out STD_LOGIC;
signal_inv : out STD_LOGIC;
write_enable_FB : out STD_LOGIC;
write_enable_GC : out STD_LOGIC;
sel_base_mul : out STD_LOGIC;
reg_h_ce : out STD_LOGIC;
ctr_i_ce : out STD_LOGIC;
ctr_i_rst : out STD_LOGIC;
sel_ctr_i_rst_value : out STD_LOGIC_VECTOR(1 downto 0);
reg_j_ce : out STD_LOGIC;
reg_FB_ce : out STD_LOGIC;
reg_FB_rst : out STD_LOGIC;
sel_reg_FB : out STD_LOGIC;
reg_GC_ce : out STD_LOGIC;
reg_GC_rst : out STD_LOGIC;
sel_reg_GC : out STD_LOGIC;
reg_degree_F_ce : out STD_LOGIC;
reg_degree_F_rst : out STD_LOGIC;
sel_reg_degree_F : out STD_LOGIC;
reg_degree_G_ce : out STD_LOGIC;
reg_degree_G_rst : out STD_LOGIC;
reg_degree_B_ce : out STD_LOGIC;
reg_degree_B_rst : out STD_LOGIC;
sel_reg_degree_B : out STD_LOGIC_VECTOR(1 downto 0);
reg_degree_C_ce : out STD_LOGIC;
reg_degree_C_rst : out STD_LOGIC;
reg_looking_degree_d : out STD_LOGIC_VECTOR(0 downto 0);
reg_looking_degree_ce : out STD_LOGIC;
reg_swap_ce : out STD_LOGIC;
reg_swap_rst : out STD_LOGIC;
sel_int_new_value_FB : out STD_LOGIC;
sel_address_FB : out STD_LOGIC;
sel_address_GC : out STD_LOGIC_VECTOR(1 downto 0);
BC_calculation : out STD_LOGIC;
enable_external_swap : out STD_LOGIC
);
end component;
component register_nbits
Generic (size : integer);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component register_rst_nbits
Generic (size : integer);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component counter_decrement_rst_nbits
Generic (
size : integer;
decrement_value : integer
);
Port (
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component mult_gf_2_m
Generic (gf_2_m : integer range 1 to 20 := 11);
Port (
a : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
b: in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
o : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end component;
signal base_mult_a : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal base_mult_b : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal base_mult_o : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal sel_base_mul : STD_LOGIC;
signal reg_h_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_h_ce : STD_LOGIC;
signal reg_h_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_inv_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_inv_ce : STD_LOGIC;
signal reg_inv_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal ctr_i_ce : STD_LOGIC;
signal ctr_i_rst : STD_LOGIC;
signal ctr_i_rst_value : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal ctr_i_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal sel_ctr_i_rst_value : STD_LOGIC_VECTOR(1 downto 0);
constant ctr_i_rst_value_F : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0) := std_logic_vector(to_unsigned(2*final_degree - 1,size_final_degree + 2));
constant ctr_i_rst_value_B : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0) := std_logic_vector(to_unsigned(final_degree,size_final_degree + 2));
signal reg_j_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_j_ce : STD_LOGIC;
signal reg_j_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_FB_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_FB_ce : STD_LOGIC;
signal reg_FB_rst : STD_LOGIC;
constant reg_FB_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := (others=> '0');
signal reg_FB_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal sel_reg_FB : STD_LOGIC;
signal reg_GC_d : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal reg_GC_ce : STD_LOGIC;
signal reg_GC_rst : STD_LOGIC;
constant reg_GC_rst_value : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0) := (others=> '0');
signal reg_GC_q : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal sel_reg_GC : STD_LOGIC;
signal reg_degree_F_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_degree_F_ce : STD_LOGIC;
signal reg_degree_F_rst : STD_LOGIC;
constant reg_degree_F_rst_value : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0) := std_logic_vector(to_unsigned(2*final_degree - 1,size_final_degree + 2));
signal reg_degree_F_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal sel_reg_degree_F : STD_LOGIC;
signal reg_degree_G_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_degree_G_ce : STD_LOGIC;
signal reg_degree_G_rst : STD_LOGIC;
constant reg_degree_G_rst_value : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0) := std_logic_vector(to_unsigned(2*final_degree,size_final_degree + 2));
signal reg_degree_G_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_degree_B_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_degree_B_ce : STD_LOGIC;
signal reg_degree_B_rst : STD_LOGIC;
constant reg_degree_B_rst_value : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0) := std_logic_vector(to_unsigned(0,size_final_degree + 2));
signal reg_degree_B_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal sel_reg_degree_B : STD_LOGIC_VECTOR(1 downto 0);
signal reg_degree_C_d : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_degree_C_ce : STD_LOGIC;
signal reg_degree_C_rst : STD_LOGIC;
constant reg_degree_C_rst_value : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0) := std_logic_vector(to_unsigned(0,size_final_degree + 2));
signal reg_degree_C_q : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal reg_looking_degree_d : STD_LOGIC_VECTOR(0 downto 0);
signal reg_looking_degree_ce : STD_LOGIC;
signal reg_looking_degree_q : STD_LOGIC_VECTOR(0 downto 0);
signal reg_swap_d : STD_LOGIC_VECTOR(0 downto 0);
signal reg_swap_ce : STD_LOGIC;
signal reg_swap_rst : STD_LOGIC;
constant reg_swap_rst_value : STD_LOGIC_VECTOR(0 downto 0) := "0";
signal reg_swap_q : STD_LOGIC_VECTOR(0 downto 0);
signal i_minus_j : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal degree_C_plus_j : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal int_value_FB : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal int_value_GC : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal sel_int_new_value_FB : STD_LOGIC;
signal int_new_value_FB : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal int_new_value_GC : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal int_write_enable_FB : STD_LOGIC;
signal int_write_enable_GC : STD_LOGIC;
signal int_address_FB : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal int_address_GC : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal address_i_FB : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal address_degree_FB_FB : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal address_i_GC : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal address_degree_GC_GC : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal address_i_minus_j_GC : STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
signal sel_address_FB : STD_LOGIC;
signal sel_address_GC : STD_LOGIC_VECTOR(1 downto 0);
signal BC_calculation : STD_LOGIC;
signal enable_external_swap : STD_LOGIC;
signal FB_equal_zero : STD_LOGIC;
signal i_equal_zero : STD_LOGIC;
signal i_minus_j_less_than_zero : STD_LOGIC;
signal degree_G_less_equal_final_degree : STD_LOGIC;
signal degree_F_less_than_degree_G : STD_LOGIC;
signal degree_B_equal_degree_C_plus_j : STD_LOGIC;
signal degree_B_less_than_degree_C_plus_j : STD_LOGIC;
begin
controller : controller_solving_key_equation_1
Port Map(
clk => clk,
rst => rst,
ready_inv => ready_inv,
FB_equal_zero => FB_equal_zero,
i_equal_zero => i_equal_zero,
i_minus_j_less_than_zero => i_minus_j_less_than_zero,
degree_G_less_equal_final_degree => degree_G_less_equal_final_degree,
degree_F_less_than_degree_G => degree_F_less_than_degree_G,
degree_B_equal_degree_C_plus_j => degree_B_equal_degree_C_plus_j,
degree_B_less_than_degree_C_plus_j => degree_B_less_than_degree_C_plus_j,
reg_looking_degree_q => reg_looking_degree_q,
key_equation_found => key_equation_found,
signal_inv => signal_inv,
write_enable_FB => int_write_enable_FB,
write_enable_GC => int_write_enable_GC,
sel_base_mul => sel_base_mul,
reg_h_ce => reg_h_ce,
ctr_i_ce => ctr_i_ce,
ctr_i_rst => ctr_i_rst,
sel_ctr_i_rst_value => sel_ctr_i_rst_value,
reg_j_ce => reg_j_ce,
reg_FB_ce => reg_FB_ce,
reg_FB_rst => reg_FB_rst,
sel_reg_FB => sel_reg_FB,
reg_GC_ce => reg_GC_ce,
reg_GC_rst => reg_GC_rst,
sel_reg_GC => sel_reg_GC,
reg_degree_F_ce => reg_degree_F_ce,
reg_degree_F_rst => reg_degree_F_rst,
sel_reg_degree_F => sel_reg_degree_F,
reg_degree_G_ce => reg_degree_G_ce,
reg_degree_G_rst => reg_degree_G_rst,
reg_degree_B_ce => reg_degree_B_ce,
reg_degree_B_rst => reg_degree_B_rst,
sel_reg_degree_B => sel_reg_degree_B,
reg_degree_C_ce => reg_degree_C_ce,
reg_degree_C_rst => reg_degree_C_rst,
reg_looking_degree_d => reg_looking_degree_d,
reg_looking_degree_ce => reg_looking_degree_ce,
reg_swap_ce => reg_swap_ce,
reg_swap_rst => reg_swap_rst,
sel_int_new_value_FB => sel_int_new_value_FB,
sel_address_FB => sel_address_FB,
sel_address_GC => sel_address_GC,
BC_calculation => BC_calculation,
enable_external_swap => enable_external_swap
);
base_mult : mult_gf_2_m
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => base_mult_a,
b => base_mult_b,
o => base_mult_o
);
reg_h : register_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_h_d,
clk => clk,
ce => reg_h_ce,
q => reg_h_q
);
reg_inv : register_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_inv_d,
clk => clk,
ce => reg_inv_ce,
q => reg_inv_q
);
ctr_i : counter_decrement_rst_nbits
Generic Map(
size => size_final_degree+2,
decrement_value => 1
)
Port Map(
clk => clk,
ce => ctr_i_ce,
rst => ctr_i_rst,
rst_value => ctr_i_rst_value,
q => ctr_i_q
);
reg_j : register_nbits
Generic Map(
size => size_final_degree+2
)
Port Map(
d => reg_j_d,
clk => clk,
ce => reg_j_ce,
q => reg_j_q
);
reg_FB : register_rst_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_FB_d,
clk => clk,
rst => reg_FB_rst,
rst_value => reg_FB_rst_value,
ce => reg_FB_ce,
q => reg_FB_q
);
reg_GC : register_rst_nbits
Generic Map(
size => gf_2_m
)
Port Map(
d => reg_GC_d,
clk => clk,
rst => reg_GC_rst,
rst_value => reg_GC_rst_value,
ce => reg_GC_ce,
q => reg_GC_q
);
reg_degree_F : register_rst_nbits
Generic Map(
size => size_final_degree+2
)
Port Map(
d => reg_degree_F_d,
clk => clk,
rst => reg_degree_F_rst,
rst_value => reg_degree_F_rst_value,
ce => reg_degree_F_ce,
q => reg_degree_F_q
);
reg_degree_G : register_rst_nbits
Generic Map(
size => size_final_degree+2
)
Port Map(
d => reg_degree_G_d,
clk => clk,
rst => reg_degree_G_rst,
rst_value => reg_degree_G_rst_value,
ce => reg_degree_G_ce,
q => reg_degree_G_q
);
reg_degree_B : register_rst_nbits
Generic Map(
size => size_final_degree+2
)
Port Map(
d => reg_degree_B_d,
clk => clk,
rst => reg_degree_B_rst,
rst_value => reg_degree_B_rst_value,
ce => reg_degree_B_ce,
q => reg_degree_B_q
);
reg_degree_C : register_rst_nbits
Generic Map(
size => size_final_degree+2
)
Port Map(
d => reg_degree_C_d,
clk => clk,
rst => reg_degree_C_rst,
rst_value => reg_degree_C_rst_value,
ce => reg_degree_C_ce,
q => reg_degree_C_q
);
reg_looking_degree : register_nbits
Generic Map(
size => 1
)
Port Map(
d => reg_looking_degree_d,
clk => clk,
ce => reg_looking_degree_ce,
q => reg_looking_degree_q
);
reg_swap : register_rst_nbits
Generic Map(
size => 1
)
Port Map(
d => reg_swap_d,
clk => clk,
ce => reg_swap_ce,
rst => reg_swap_rst,
rst_value => reg_swap_rst_value,
q => reg_swap_q
);
base_mult_a <= reg_inv_q when sel_base_mul = '1' else
reg_h_q;
base_mult_b <= reg_FB_q when sel_base_mul = '1' else
reg_GC_q;
reg_h_d <= base_mult_o;
reg_inv_d <= value_inv;
reg_inv_ce <= ready_inv;
ctr_i_rst_value <= reg_degree_F_q when sel_ctr_i_rst_value = "11" else
degree_C_plus_j when sel_ctr_i_rst_value = "10" else
ctr_i_rst_value_F when sel_ctr_i_rst_value = "01" else
ctr_i_rst_value_B;
reg_j_d <= std_logic_vector(unsigned(reg_degree_F_q) - unsigned(reg_degree_G_q));
reg_FB_d <= std_logic_vector(to_unsigned(1, reg_FB_d'length)) when sel_reg_FB = '1' else
int_value_FB;
reg_GC_d <= std_logic_vector(to_unsigned(1, reg_GC_d'length)) when sel_reg_GC = '1' else
int_value_GC;
reg_degree_F_d <= std_logic_vector((unsigned(reg_degree_F_q) - to_unsigned(1, reg_degree_F_q'length))) when sel_reg_degree_F = '1' else
reg_degree_G_q;
reg_degree_G_d <= reg_degree_F_q;
reg_degree_B_d <= degree_C_plus_j when sel_reg_degree_B = "10" else
std_logic_vector(unsigned(reg_degree_B_q) - to_unsigned(1, reg_degree_B_q'length)) when sel_reg_degree_B = "01" else
reg_degree_C_q when sel_reg_degree_B = "00" else
(others => '-');
degree_C_plus_j <= std_logic_vector(unsigned(reg_degree_C_q) + unsigned(reg_j_q));
i_minus_j <= std_logic_vector(unsigned(ctr_i_q) - unsigned(reg_j_q));
reg_degree_C_d <= reg_degree_B_q;
reg_swap_d <= not reg_swap_q;
int_new_value_FB <= (base_mult_o xor reg_FB_q) when sel_int_new_value_FB = '1' else
reg_FB_q;
int_new_value_GC <= reg_GC_q;
int_value_FB <= value_GC when reg_swap_q = "1" else value_FB;
int_value_GC <= value_FB when reg_swap_q = "1" else value_GC;
new_value_inv <= int_new_value_GC;
new_value_FB <= int_new_value_GC when (reg_swap_q(0) and enable_external_swap) = '1' else int_new_value_FB;
new_value_GC <= int_new_value_FB when (reg_swap_q(0) and enable_external_swap) = '1' else int_new_value_GC;
write_enable_FB <= int_write_enable_GC when (reg_swap_q(0) and enable_external_swap) = '1' else int_write_enable_FB;
write_enable_GC <= int_write_enable_FB when (reg_swap_q(0) and enable_external_swap) = '1' else int_write_enable_GC;
address_i_FB <= std_logic_vector(to_unsigned(2*final_degree + 1, address_i_FB'length) + unsigned(ctr_i_q)) when BC_calculation = '1' else
ctr_i_q;
address_degree_FB_FB <= std_logic_vector(to_unsigned(2*final_degree + 1, address_degree_FB_FB'length) + unsigned(reg_degree_B_q)) when BC_calculation = '1' else
reg_degree_F_q;
address_i_GC <= std_logic_vector(to_unsigned(2*final_degree + 1, address_i_GC'length) + unsigned(ctr_i_q)) when BC_calculation = '1' else
ctr_i_q;
address_degree_GC_GC <= std_logic_vector(to_unsigned(2*final_degree + 1, address_degree_GC_GC'length) + unsigned(reg_degree_C_q)) when BC_calculation = '1' else
reg_degree_G_q;
address_i_minus_j_GC <= std_logic_vector(to_unsigned(2*final_degree + 1, address_i_minus_j_GC'length) + unsigned(i_minus_j)) when BC_calculation = '1' else
i_minus_j;
int_address_FB <= address_degree_FB_FB when sel_address_FB = '1' else
address_i_FB;
int_address_GC <= address_i_minus_j_GC when sel_address_GC = "10" else
address_degree_GC_GC when sel_address_GC = "01" else
address_i_GC when sel_address_GC = "00" else
(others => '-');
address_FB <= int_address_GC when (reg_swap_q(0) and enable_external_swap) = '1' else int_address_FB;
address_GC <= int_address_FB when (reg_swap_q(0) and enable_external_swap) = '1' else int_address_GC;
FB_equal_zero <= '1' when (int_new_value_FB = std_logic_vector(to_unsigned(0,reg_FB_q'length))) else '0';
i_equal_zero <= '1' when (ctr_i_q = std_logic_vector(to_unsigned(0,ctr_i_q'length))) else '0';
i_minus_j_less_than_zero <= '1' when (signed(i_minus_j) < to_signed(0,i_minus_j'length)) else '0';
degree_G_less_equal_final_degree <= '1' when (unsigned(reg_degree_G_q) <= to_unsigned(final_degree-1,reg_degree_G_q'length)) else '0';
degree_F_less_than_degree_G <= '1' when (unsigned(reg_degree_F_q) < unsigned(reg_degree_G_q)) else '0';
degree_B_equal_degree_C_plus_j <= '1' when (reg_degree_B_q = degree_C_plus_j) else '0';
degree_B_less_than_degree_C_plus_j <= '1' when (unsigned(reg_degree_B_q) < unsigned(degree_C_plus_j)) else '0';
end Behavioral; |
-- library foo
package pack is
end package;
entity sub2 is
end entity;
architecture a of sub2 is
begin
end architecture;
use work.pack.all;
entity sub1 is
end entity;
architecture a of sub1 is
component sub2 is
end component;
begin
sub_i: component sub2;
end architecture;
-- library bar
library foo;
entity binding1 is
end entity;
architecture test of binding1 is
component sub1 is
end component;
begin
sub_i: component sub1;
end architecture;
|
-- library foo
package pack is
end package;
entity sub2 is
end entity;
architecture a of sub2 is
begin
end architecture;
use work.pack.all;
entity sub1 is
end entity;
architecture a of sub1 is
component sub2 is
end component;
begin
sub_i: component sub2;
end architecture;
-- library bar
library foo;
entity binding1 is
end entity;
architecture test of binding1 is
component sub1 is
end component;
begin
sub_i: component sub1;
end architecture;
|
-- library foo
package pack is
end package;
entity sub2 is
end entity;
architecture a of sub2 is
begin
end architecture;
use work.pack.all;
entity sub1 is
end entity;
architecture a of sub1 is
component sub2 is
end component;
begin
sub_i: component sub2;
end architecture;
-- library bar
library foo;
entity binding1 is
end entity;
architecture test of binding1 is
component sub1 is
end component;
begin
sub_i: component sub1;
end architecture;
|
-- library foo
package pack is
end package;
entity sub2 is
end entity;
architecture a of sub2 is
begin
end architecture;
use work.pack.all;
entity sub1 is
end entity;
architecture a of sub1 is
component sub2 is
end component;
begin
sub_i: component sub2;
end architecture;
-- library bar
library foo;
entity binding1 is
end entity;
architecture test of binding1 is
component sub1 is
end component;
begin
sub_i: component sub1;
end architecture;
|
-- library foo
package pack is
end package;
entity sub2 is
end entity;
architecture a of sub2 is
begin
end architecture;
use work.pack.all;
entity sub1 is
end entity;
architecture a of sub1 is
component sub2 is
end component;
begin
sub_i: component sub2;
end architecture;
-- library bar
library foo;
entity binding1 is
end entity;
architecture test of binding1 is
component sub1 is
end component;
begin
sub_i: component sub1;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity not00 is
port(
clkn: in std_logic ;
codopn: in std_logic_vector ( 3 downto 0 );
inFlagn: in std_logic;
portAn: in std_logic_vector ( 7 downto 0 );
outn: out std_logic_vector ( 7 downto 0 );
outFlagn: out std_logic );
end;
architecture not0 of not00 is
begin
pnot: process(codopn, portAn)
begin
if(codopn = "0011") then
outn <= not portAn;
outFlagn <= '1';
else
outn <= (others => 'Z');
outFlagn <= 'Z';
end if;
end process pnot;
-- pnot: process(clkn, codopn, inFlagn)
-- --variable auxn: bit:='0';
-- begin
-- if (clkn = '1') then
----clkn'event and
-- if (codopn = "0011") then
-- --if (inFlagn = '1') then
-- --if (auxn = '0') then
-- --auxn:= '1';
-- outn <= not(portAn);
-- outFlagn <= '1';
-- --end if;
-- --else
-- --outFlagn <= '0';
-- --end if;
-- else
-- outn <= (others => 'Z');
-- outFlagn <= 'Z';
-- --auxn:='0';
-- end if;
-- end if;
-- end process pnot;
end not0;
|
-------------------------------------------------------------------------------
--
-- SNESpad controller core
--
-- Copyright (c) 2004, Arnim Laeuger ([email protected])
--
-- $Id: snespad_comp-pack.vhd,v 1.1 2004-10-05 18:20:14 arniml Exp $
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package snespad_comp is
component snespad
generic (
num_pads_g : natural := 1;
reset_level_g : natural := 0;
button_level_g : natural := 0;
clocks_per_6us_g : natural := 6
);
port (
clk_i : in std_logic;
reset_i : in std_logic;
pad_clk_o : out std_logic;
pad_latch_o : out std_logic;
pad_data_i : in std_logic_vector(num_pads_g-1 downto 0);
but_a_o : out std_logic_vector(num_pads_g-1 downto 0);
but_b_o : out std_logic_vector(num_pads_g-1 downto 0);
but_x_o : out std_logic_vector(num_pads_g-1 downto 0);
but_y_o : out std_logic_vector(num_pads_g-1 downto 0);
but_start_o : out std_logic_vector(num_pads_g-1 downto 0);
but_sel_o : out std_logic_vector(num_pads_g-1 downto 0);
but_tl_o : out std_logic_vector(num_pads_g-1 downto 0);
but_tr_o : out std_logic_vector(num_pads_g-1 downto 0);
but_up_o : out std_logic_vector(num_pads_g-1 downto 0);
but_down_o : out std_logic_vector(num_pads_g-1 downto 0);
but_left_o : out std_logic_vector(num_pads_g-1 downto 0);
but_right_o : out std_logic_vector(num_pads_g-1 downto 0)
);
end component snespad;
end snespad_comp;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:30:45 03/28/2014
-- Design Name:
-- Module Name: sccpu_cpu - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity sccpu_cpu is
end sccpu_cpu;
architecture Behavioral of sccpu_cpu is
begin
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:21:35 05/08/2012
-- Design Name:
-- Module Name: instmemory - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity instmemory is
Port ( Address : in STD_LOGIC_VECTOR (31 downto 0);
Instruction : out STD_LOGIC_VECTOR (31 downto 0));
end instmemory;
architecture Behavioral of instmemory is
begin
process (Address)
begin
case Address is
-- Main program
when "00000000000000000000000000000000"=>Instruction<="00000000000000000000000000100101";
when "00000000000000000000000000000100"=>Instruction<="00000000000000000011100000100101";
when "00000000000000000000000000001000"=>Instruction<="00000000000000000011000000100101";
when "00000000000000000000000000001100"=>Instruction<="00000000000000000010100000100101";
when "00000000000000000000000000010000"=>Instruction<="00000000000000000010000000100101";
when "00000000000000000000000000010100"=>Instruction<="00000000000000000001100000100101";
when "00000000000000000000000000011000"=>Instruction<="00000000000000000001000000100101";
when "00000000000000000000000000011100"=>Instruction<="00000000000000000000100000100101";
when "00000000000000000000000000100000"=>Instruction<="10101100000000000000000000010000";
when "00000000000000000000000000100100"=>Instruction<="10101100000000000000000000110001";
when "00000000000000000000000000101000"=>Instruction<="10101100000000000000000000110010";
when "00000000000000000000000000101100"=>Instruction<="10101100000000000000000000110011";
when "00000000000000000000000000110000"=>Instruction<="00110100000001000000000000000011";
when "00000000000000000000000000110100"=>Instruction<="00001000000000000000000000101111";
when "00000000000000000000000000111000"=>Instruction<="00110100000000010000000000011001";
when "00000000000000000000000000111100"=>Instruction<="00010000000000010000000000001001";
when "00000000000000000000000001000000"=>Instruction<="00100000001000011111111111111111";
when "00000000000000000000000001000100"=>Instruction<="00000000000000000000000000100101";
when "00000000000000000000000001001000"=>Instruction<="00000000000000000000000000100101";
when "00000000000000000000000001001100"=>Instruction<="00000000000000000000000000100101";
when "00000000000000000000000001010000"=>Instruction<="00000000000000000000000000100101";
when "00000000000000000000000001010100"=>Instruction<="00000000000000000000000000100101";
when "00000000000000000000000001011000"=>Instruction<="00000000000000000000000000100101";
when "00000000000000000000000001011100"=>Instruction<="00000000000000000000000000100101";
when "00000000000000000000000001100000"=>Instruction<="00001000000000000000000000001111";
when "00000000000000000000000001100100"=>Instruction<="00010000000000110000000000000100";
when "00000000000000000000000001101000"=>Instruction<="00100000011000111111111111111111";
when "00000000000000000000000001101100"=>Instruction<="00110100000000010000000000000001";
when "00000000000000000000000001110000"=>Instruction<="10101100000000010000000000110001";
when "00000000000000000000000001110100"=>Instruction<="00001000000000000000000000001110";
when "00000000000000000000000001111000"=>Instruction<="10101100000000000000000000110001";
when "00000000000000000000000001111100"=>Instruction<="00010000100000001111111111111111";
when "00000000000000000000000010000000"=>Instruction<="10001100000000010000000000110100";
when "00000000000000000000000010000100"=>Instruction<="00110000001000010000000000111111";
when "00000000000000000000000010001000"=>Instruction<="00010000001000000000000000011000";
when "00000000000000000000000010001100"=>Instruction<="00100000100001001111111111111111";
when "00000000000000000000000010010000"=>Instruction<="00110100000000010000000000000011";
when "00000000000000000000000010010100"=>Instruction<="00010000001001000000000000001001";
when "00000000000000000000000010011000"=>Instruction<="00110100000000010000000000000010";
when "00000000000000000000000010011100"=>Instruction<="00010000001001000000000000001010";
when "00000000000000000000000010100000"=>Instruction<="00110100000000010000000000000001";
when "00000000000000000000000010100100"=>Instruction<="00010000001001000000000000001011";
when "00000000000000000000000010101000"=>Instruction<="00001000000000000000000000111000";
when "00000000000000000000000010101100"=>Instruction<="00110100000000010000000000000001";
when "00000000000000000000000010110000"=>Instruction<="10101100000000010000000000110001";
when "00000000000000000000000010110100"=>Instruction<="00110100000000110110000110101000";
when "00000000000000000000000010111000"=>Instruction<="00001000000000000000000000001110";
when "00000000000000000000000010111100"=>Instruction<="00110100000000010000000001001111";
when "00000000000000000000000011000000"=>Instruction<="10101100000000010000000000110010";
when "00000000000000000000000011000100"=>Instruction<="00001000000000000000000000101011";
when "00000000000000000000000011001000"=>Instruction<="00110100000000010000000001011011";
when "00000000000000000000000011001100"=>Instruction<="10101100000000010000000000110010";
when "00000000000000000000000011010000"=>Instruction<="00001000000000000000000000101011";
when "00000000000000000000000011010100"=>Instruction<="00110100000000010000000000000110";
when "00000000000000000000000011011000"=>Instruction<="10101100000000010000000000110010";
when "00000000000000000000000011011100"=>Instruction<="00001000000000000000000000101011";
when "00000000000000000000000011100000"=>Instruction<="00110100000000010000000000111111";
when "00000000000000000000000011100100"=>Instruction<="10101100000000010000000000110010";
when "00000000000000000000000011101000"=>Instruction<="00001000000000000000000000101011";
when "00000000000000000000000011101100"=>Instruction<="10001100000001010000000000110000";
when "00000000000000000000000011110000"=>Instruction<="00110000101000010000000000000001";
when "00000000000000000000000011110100"=>Instruction<="00010000001000000000000000000011";
when "00000000000000000000000011111000"=>Instruction<="00110100000000010000000000000111";
when "00000000000000000000000011111100"=>Instruction<="10101100000000010000000000110011";
when "00000000000000000000000100000000"=>Instruction<="00001000000000000000000001000010";
when "00000000000000000000000100000100"=>Instruction<="10101100000000000000000000110011";
when "00000000000000000000000100001000"=>Instruction<="00010000110000000000000000000010";
when "00000000000000000000000100001100"=>Instruction<="00100000110001101111111111111111";
when "00000000000000000000000100010000"=>Instruction<="00001000000000000000000000001110";
when "00000000000000000000000100010100"=>Instruction<="00110000101000010000000000000010";
when "00000000000000000000000100011000"=>Instruction<="00010000001000000000000000000001";
when "00000000000000000000000100011100"=>Instruction<="00001000000000000000000001100000";
when "00000000000000000000000100100000"=>Instruction<="00110000101000010000000000000100";
when "00000000000000000000000100100100"=>Instruction<="00010000001000000000000000000001";
when "00000000000000000000000100101000"=>Instruction<="00001000000000000000000001001110";
when "00000000000000000000000100101100"=>Instruction<="00110100000001100000000010100111";
when "00000000000000000000000100110000"=>Instruction<="10101100000001110000000000010000";
when "00000000000000000000000100110100"=>Instruction<="00001000000000000000000000001110";
when "00000000000000000000000100111000"=>Instruction<="00110000111000010000000000001111";
when "00000000000000000000000100111100"=>Instruction<="00110100000000100000000000000001";
when "00000000000000000000000101000000"=>Instruction<="00010000001000100000000000000110";
when "00000000000000000000000101000100"=>Instruction<="00110100000000100000000000000010";
when "00000000000000000000000101001000"=>Instruction<="00010000001000100000000000000110";
when "00000000000000000000000101001100"=>Instruction<="00110100000000100000000000000100";
when "00000000000000000000000101010000"=>Instruction<="00010000001000100000000000000110";
when "00000000000000000000000101010100"=>Instruction<="00110100000000010000000000000001";
when "00000000000000000000000101011000"=>Instruction<="00010000000000000000000000000110";
when "00000000000000000000000101011100"=>Instruction<="00110100000000010000000000000010";
when "00000000000000000000000101100000"=>Instruction<="00010000000000000000000000000100";
when "00000000000000000000000101100100"=>Instruction<="00110100000000010000000000000100";
when "00000000000000000000000101101000"=>Instruction<="00010000000000000000000000000010";
when "00000000000000000000000101101100"=>Instruction<="00110100000000010000000000001000";
when "00000000000000000000000101110000"=>Instruction<="00010000000000000000000000000000";
when "00000000000000000000000101110100"=>Instruction<="00110000111001111111111111110000";
when "00000000000000000000000101111000"=>Instruction<="00000000111000010011100000100101";
when "00000000000000000000000101111100"=>Instruction<="00010000000000001111111111101011";
when "00000000000000000000000110000000"=>Instruction<="00110000111000010000000011110000";
when "00000000000000000000000110000100"=>Instruction<="00110100000000100000000000010000";
when "00000000000000000000000110001000"=>Instruction<="00010000001000100000000000001100";
when "00000000000000000000000110001100"=>Instruction<="00110100000000100000000000100000";
when "00000000000000000000000110010000"=>Instruction<="00010000001000100000000000000100";
when "00000000000000000000000110010100"=>Instruction<="00110100000000100000000001000000";
when "00000000000000000000000110011000"=>Instruction<="00010000001000100000000000000100";
when "00000000000000000000000110011100"=>Instruction<="00110100000000100000000010000000";
when "00000000000000000000000110100000"=>Instruction<="00010000001000100000000000000100";
when "00000000000000000000000110100100"=>Instruction<="00110100000000010000000000010000";
when "00000000000000000000000110101000"=>Instruction<="00010000000000000000000000000110";
when "00000000000000000000000110101100"=>Instruction<="00110100000000010000000000100000";
when "00000000000000000000000110110000"=>Instruction<="00010000000000000000000000000100";
when "00000000000000000000000110110100"=>Instruction<="00110100000000010000000001000000";
when "00000000000000000000000110111000"=>Instruction<="00010000000000000000000000000010";
when "00000000000000000000000110111100"=>Instruction<="00110100000000010000000010000000";
when "00000000000000000000000111000000"=>Instruction<="00010000000000000000000000000000";
when "00000000000000000000000111000100"=>Instruction<="00110000111001111111111100001111";
when "00000000000000000000000111001000"=>Instruction<="00000000111000010011100000100101";
when "00000000000000000000000111001100"=>Instruction<="00010000000000001111111111010100";
when others => Instruction <= "00000000000000000000000000000000";
End case;
end process;
end Behavioral;
|
--
-- GPIOs on s6micro
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2017 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
entity Top is
port (
dips_i : in std_logic_vector(3 downto 0);
pbs_i : in std_logic;
leds_o : out std_logic_vector(3 downto 0)
);
end entity Top;
architecture RTL of Top is
begin
leds_o <= dips_i when pbs_i='0' else (others => '1');
end architecture RTL;
|
--
-- GPIOs on s6micro
--
-- Author(s):
-- * Rodrigo A. Melo
--
-- Copyright (c) 2017 Authors and INTI
-- Distributed under the BSD 3-Clause License
--
library IEEE;
use IEEE.std_logic_1164.all;
entity Top is
port (
dips_i : in std_logic_vector(3 downto 0);
pbs_i : in std_logic;
leds_o : out std_logic_vector(3 downto 0)
);
end entity Top;
architecture RTL of Top is
begin
leds_o <= dips_i when pbs_i='0' else (others => '1');
end architecture RTL;
|
---------------------------------------------------------------------
-- Standard Library bits
---------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- For Modelsim
--use ieee.fixed_pkg.all;
--use ieee.fixed_float_types.ALL;
-- For ISE
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.fixed_float_types.ALL;
use IEEE.numeric_std.all;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Entity Description
---------------------------------------------------------------------
entity synapsemodel is
Port (
clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model : in STD_LOGIC; --SYNCHRONOUS RESET
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
component_done : out STD_LOGIC;
eventport_in_in : in STD_LOGIC;
requirement_voltage_v : in sfixed (2 downto -22);
param_time_tauDecay : in sfixed (6 downto -18);
param_conductance_gbase : in sfixed (-22 downto -53);
param_voltage_erev : in sfixed (2 downto -22);
param_time_inv_tauDecay_inv : in sfixed (18 downto -6);
exposure_current_i : out sfixed (-28 downto -53);
exposure_conductance_g : out sfixed (-22 downto -53);
statevariable_conductance_g_out : out sfixed (-22 downto -53);
statevariable_conductance_g_in : in sfixed (-22 downto -53);
derivedvariable_current_i_out : out sfixed (-28 downto -53);
derivedvariable_current_i_in : in sfixed (-28 downto -53);
sysparam_time_timestep : in sfixed (-6 downto -22);
sysparam_time_simtime : in sfixed (6 downto -22)
);
end synapsemodel;
---------------------------------------------------------------------
-------------------------------------------------------------------------------------------
-- Architecture Begins
-------------------------------------------------------------------------------------------
architecture RTL of synapsemodel is
signal COUNT : unsigned(2 downto 0) := "000";
signal childrenCombined_Component_done_single_shot_fired : STD_LOGIC := '0';
signal childrenCombined_Component_done_single_shot : STD_LOGIC := '0';
signal childrenCombined_Component_done : STD_LOGIC := '0';
signal Component_done_int : STD_LOGIC := '0';
signal subprocess_der_int_pre_ready : STD_LOGIC := '0';
signal subprocess_der_int_ready : STD_LOGIC := '0';
signal subprocess_der_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_pre_ready : STD_LOGIC := '0';
signal subprocess_dyn_int_ready : STD_LOGIC := '0';
signal subprocess_dyn_ready : STD_LOGIC := '0';
signal subprocess_model_ready : STD_LOGIC := '1';
signal subprocess_all_ready_shotdone : STD_LOGIC := '1';
signal subprocess_all_ready_shot : STD_LOGIC := '0';
signal subprocess_all_ready : STD_LOGIC := '0';signal statevariable_conductance_noregime_g_temp_1 : sfixed (-22 downto -53);
signal statevariable_conductance_noregime_g_temp_1_next : sfixed (-22 downto -53);
---------------------------------------------------------------------
-- Derived Variables and parameters
---------------------------------------------------------------------
signal DerivedVariable_current_i : sfixed (-28 downto -53) := to_sfixed(0.0 ,-28,-53);
signal DerivedVariable_current_i_next : sfixed (-28 downto -53) := to_sfixed(0.0 ,-28,-53);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- EDState internal Variables
---------------------------------------------------------------------
signal statevariable_conductance_g_next : sfixed (-22 downto -53);
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Output Port internal Variables
---------------------------------------------------------------------
signal EventPort_in_in_internal : std_logic := '0';
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Child Components
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Begin Internal Processes
---------------------------------------------------------------------
begin
---------------------------------------------------------------------
-- Child EDComponent Instantiations and corresponding internal variables
---------------------------------------------------------------------
derived_variable_pre_process_comb :process ( sysparam_time_timestep, statevariable_conductance_g_in , requirement_voltage_v , param_voltage_erev )
begin
end process derived_variable_pre_process_comb;
derived_variable_pre_process_syn :process ( clk, init_model )
begin
subprocess_der_int_pre_ready <= '1';
end process derived_variable_pre_process_syn;
--no complex steps in derived variables
subprocess_der_int_ready <= '1';
derived_variable_process_comb :process ( sysparam_time_timestep, statevariable_conductance_g_in , requirement_voltage_v , param_voltage_erev )
begin
derivedvariable_current_i_next <= resize(( statevariable_conductance_g_in * ( param_voltage_erev - requirement_voltage_v ) ),-28,-53);
subprocess_der_ready <= '1';
end process derived_variable_process_comb;
derived_variable_process_syn :process ( clk,init_model )
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
derivedvariable_current_i <= derivedvariable_current_i_next;
end if;
end if;
end process derived_variable_process_syn;
---------------------------------------------------------------------
dynamics_pre_process_comb :process ( sysparam_time_timestep, param_time_tauDecay, statevariable_conductance_g_in ,param_time_inv_tauDecay_inv )
begin
end process dynamics_pre_process_comb;
dynamics_pre_process_syn :process ( clk, init_model )
begin
subprocess_dyn_int_pre_ready <= '1';
end process dynamics_pre_process_syn;
--No dynamics with complex equations found
subprocess_dyn_int_ready <= '1';
state_variable_process_dynamics_comb :process (sysparam_time_timestep, param_time_tauDecay, statevariable_conductance_g_in ,param_time_inv_tauDecay_inv ,statevariable_conductance_g_in)
begin
statevariable_conductance_noregime_g_temp_1_next <= resize(statevariable_conductance_g_in + ( - statevariable_conductance_g_in * param_time_inv_tauDecay_inv ) * sysparam_time_timestep,-22,-53);
subprocess_dyn_ready <= '1';
end process state_variable_process_dynamics_comb;
state_variable_process_dynamics_syn :process (CLK,init_model)
begin
if clk'event and clk = '1' then
if subprocess_all_ready_shot = '1' then
statevariable_conductance_noregime_g_temp_1 <= statevariable_conductance_noregime_g_temp_1_next;
end if;
end if;
end process state_variable_process_dynamics_syn;
------------------------------------------------------------------------------------------------------
-- EDState Variable Drivers
------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------
-- EDState variable: $par.name Driver Process
---------------------------------------------------------------------
state_variable_process_comb_0 :process (sysparam_time_timestep,init_model,eventport_in_in,statevariable_conductance_g_in,param_conductance_gbase,statevariable_conductance_noregime_g_temp_1,param_time_tauDecay,statevariable_conductance_g_in,param_time_inv_tauDecay_inv)
variable statevariable_conductance_g_temp_1 : sfixed (-22 downto -53);
variable statevariable_conductance_g_temp_2 : sfixed (-22 downto -53);
begin
statevariable_conductance_g_temp_1 := statevariable_conductance_noregime_g_temp_1; if eventport_in_in = '1' then
statevariable_conductance_g_temp_2 := resize( statevariable_conductance_g_in + param_conductance_gbase ,-22,-53);
else
statevariable_conductance_g_temp_2 := statevariable_conductance_g_temp_1;
end if;
statevariable_conductance_g_next <= statevariable_conductance_g_temp_2;
end process;
---------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to exposures
---------------------------------------------------------------------
exposure_conductance_g <= statevariable_conductance_g_in;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign state variables to output state variables
---------------------------------------------------------------------
statevariable_conductance_g_out <= statevariable_conductance_g_next;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Assign derived variables to exposures
---------------------------------------------------------------------
exposure_current_i <= derivedvariable_current_i_in;derivedvariable_current_i_out <= derivedvariable_current_i;
---------------------------------------------------------------------
---------------------------------------------------------------------
-- Subprocess ready process
---------------------------------------------------------------------
subprocess_all_ready_process: process(step_once_go,subprocess_der_int_ready,subprocess_der_int_pre_ready,subprocess_der_ready,subprocess_dyn_int_pre_ready,subprocess_dyn_int_ready,subprocess_dyn_ready,subprocess_model_ready)
begin
if step_once_go = '0' and subprocess_der_int_ready = '1' and subprocess_der_int_pre_ready = '1'and subprocess_der_ready ='1' and subprocess_dyn_int_ready = '1' and subprocess_dyn_int_pre_ready = '1' and subprocess_dyn_ready = '1' and subprocess_model_ready = '1' then
subprocess_all_ready <= '1';
else
subprocess_all_ready <= '0';
end if;
end process subprocess_all_ready_process;
subprocess_all_ready_shot_process : process(clk)
begin
if rising_edge(clk) then
if (init_model='1') then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '1';
else
if subprocess_all_ready = '1' and subprocess_all_ready_shotdone = '0' then
subprocess_all_ready_shot <= '1';
subprocess_all_ready_shotdone <= '1';
elsif subprocess_all_ready_shot = '1' then
subprocess_all_ready_shot <= '0';
elsif subprocess_all_ready = '0' then
subprocess_all_ready_shot <= '0';
subprocess_all_ready_shotdone <= '0';
end if;
end if;
end if;
end process subprocess_all_ready_shot_process;
---------------------------------------------------------------------
count_proc:process(clk)
begin
if (clk'EVENT AND clk = '1') then
if init_model = '1' then COUNT <= "001";
component_done_int <= '1';
else if step_once_go = '1' then
COUNT <= "000";
component_done_int <= '0';
elsif COUNT = "001" then
component_done_int <= '1';
elsif subprocess_all_ready_shot = '1' then
COUNT <= COUNT + 1;
component_done_int <= '0';
end if;
end if;
end if;
end process count_proc;
component_done <= component_done_int;
end RTL;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.types_pkg.all;
package robot_layer_2_pkg is
constant MOTOR_COUNT : natural := 6;
constant QEI_COUNT : natural := 4+1;
component robot_layer_2 is
generic (
CLK_FREQUENCY_HZ : positive;
RegCnt : positive
);
port (
clk : in std_logic;
reset : in std_logic;
regs_data_in_value : out std_logic_vector(RegCnt*32-1 downto 0) := (others => '0');
regs_data_in_read : in std_logic_vector(RegCnt-1 downto 0);
regs_data_out_value : in std_logic_vector(RegCnt*32-1 downto 0);
regs_data_out_write : in std_logic_vector(RegCnt-1 downto 0);
---------------------------------
-------- TO/FROM LAYER 1 --------
---------------------------------
--------- UART ----------
uart_tx : out std_logic_vector(4-1 downto 0);
uart_rx : in std_logic_vector(4-1 downto 0);
motor_value : out int16_t(MOTOR_COUNT-1 downto 0);
motor_current : in int24_t(MOTOR_COUNT-1 downto 0);
motor_fault : in std_logic_vector(MOTOR_COUNT-1 downto 0);
qei_value : in int16_t(QEI_COUNT-1 downto 0);
qei_ref : in std_logic_vector(QEI_COUNT-1 downto 0);
---------------------------------
-------- TO/FROM LAYER 3 --------
---------------------------------
sum_m_dist : out std_logic_vector(32-1 downto 0);
sum_m_angle : out std_logic_vector(32-1 downto 0);
sum_c_dist : out std_logic_vector(32-1 downto 0);
sum_c_angle : out std_logic_vector(32-1 downto 0);
pos_valid : out std_logic;
pos_id : out std_logic_vector(8-1 downto 0);
pos_teta : out std_logic_vector(16-1 downto 0);
pos_x : out std_logic_vector(16-1 downto 0);
pos_y : out std_logic_vector(16-1 downto 0);
pos_sum_dist : out std_logic_vector(32-1 downto 0);
pos_sum_angle : out std_logic_vector(32-1 downto 0);
dist_en : in std_logic;
dist_acc : in std_logic_vector(32-1 downto 0);
dist_speed : in std_logic_vector(32-1 downto 0);
dist_target : in std_logic_vector(32-1 downto 0);
angle_en : in std_logic;
angle_acc : in std_logic_vector(32-1 downto 0);
angle_speed : in std_logic_vector(32-1 downto 0);
angle_target : in std_logic_vector(32-1 downto 0)
);
end component;
end package;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:16:35 10/31/2006
-- Design Name: fast_queue
-- Module Name: C:/fast_queueProject/src/fast_queue_tb.vhd
-- Project Name: myProj
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: fast_queue
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY fast_queue_tb IS
END fast_queue_tb;
ARCHITECTURE behavior OF fast_queue_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT fast_queue
generic(
ADDRESS_BITS : integer := 2;
DATA_BITS : integer := 32
);
PORT(
clk : IN std_logic;
rst : IN std_logic;
add_busy : out std_logic;
remove_busy : out std_logic;
add : IN std_logic;
remove : IN std_logic;
entryToAdd : IN std_logic_vector(0 to 31);
headValid : INOUT std_logic;
full : INOUT std_logic;
empty : INOUT std_logic;
head : OUT std_logic_vector(0 to 31)
);
END COMPONENT;
--Inputs
SIGNAL clk : std_logic := '0';
SIGNAL rst : std_logic := '0';
SIGNAL add : std_logic := '0';
SIGNAL remove : std_logic := '0';
SIGNAL entryToAdd : std_logic_vector(0 to 31) := (others=>'0');
--BiDirs
SIGNAL headValid : std_logic;
SIGNAL full : std_logic;
SIGNAL empty : std_logic;
signal add_busy : std_logic;
signal remove_busy : std_logic;
--Outputs
SIGNAL head : std_logic_vector(0 to 31);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: fast_queue
GENERIC MAP(
ADDRESS_BITS => 2,
DATA_BITS => 32
)
PORT MAP(
clk => clk,
rst => rst,
add_busy => add_busy,
remove_busy => remove_busy,
add => add,
remove => remove,
entryToAdd => entryToAdd,
head => head,
headValid => headValid,
full => full,
empty => empty
);
tb : PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
wait for 100 ns;
-- Place stimulus here
rst <= '1'; -- Reset the FIFO
wait for 20 ns;
rst <= '0';
wait for 20 ns;
entryToAdd <= x"1111_1111"; -- Add an entry
wait for 10 ns;
add <= '1';
wait for 20 ns;
add <= '0';
wait for 100 ns;
entryToAdd <= x"2222_2222"; -- Add an entry
wait for 10 ns;
add <= '1';
wait for 20 ns;
add <= '0';
wait for 100 ns;
entryToAdd <= x"3333_3333"; -- Add an entry
wait for 10 ns;
add <= '1';
wait for 20 ns;
add <= '0';
wait for 100 ns;
entryToAdd <= x"4444_4444"; -- Add an entry
wait for 10 ns;
add <= '1';
wait for 20 ns;
add <= '0';
wait for 100 ns;
remove <= '1'; -- Remove an entry
wait for 20 ns;
remove <= '0';
wait for 100 ns;
remove <= '1'; -- Remove an entry
wait for 20 ns;
remove <= '0';
wait for 100 ns;
remove <= '1'; -- Remove an entry
wait for 20 ns;
remove <= '0';
wait for 100 ns;
remove <= '1'; -- Remove an entry
wait for 20 ns;
remove <= '0';
wait for 100 ns;
remove <= '1'; -- Remove an entry
wait for 20 ns;
remove <= '0';
wait for 100 ns;
entryToAdd <= x"5555_5555"; -- Add an entry
wait for 10 ns;
add <= '1';
wait for 20 ns;
add <= '0';
wait for 100 ns;
remove <= '1'; -- Remove an entry
wait for 20 ns;
remove <= '0';
wait for 100 ns;
wait; -- will wait forever
END PROCESS;
clockProcess : PROCESS
BEGIN
clk <= '1'; -- clock cycle 10 ns
wait for 5 ns;
clk <= '0';
wait for 5 ns;
END PROCESS;
END;
|
library ieee;
use ieee.std_logic_1164.all;
entity sub is
port ( x : inout std_logic );
end entity;
architecture test of sub is
begin
p1: process is
begin
x <= '1';
wait for 1 ns;
x <= '0';
wait for 0 ns;
assert x'active;
assert not x'event;
assert x = 'U';
x <= 'L';
wait for 0 ns;
assert x'active;
assert not x'event;
assert x = 'U';
assert x = x'last_value;
wait;
end process;
end architecture;
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity driver11 is
end entity;
architecture test of driver11 is
signal y : std_logic;
begin
u: entity work.sub port map ( y );
p2: process is
begin
y <= 'U';
wait;
end process;
end architecture;
|
entity tb_asgn05 is
end tb_asgn05;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_asgn05 is
signal s0 : std_logic;
signal s1 : std_logic;
signal r : std_logic_vector (5 downto 0);
begin
dut: entity work.asgn05
port map (s0 => s0, s1 => s1, r => r);
process
begin
s0 <= '0';
s1 <= '0';
wait for 1 ns;
assert r = "000000" severity failure;
s0 <= '1';
s1 <= '0';
wait for 1 ns;
assert r = "010110" severity failure;
wait;
end process;
end behav;
|
entity call6a is
end;
architecture behav of call6a is
procedure check (s : string) is
begin
wait for 1 ns;
assert s (2) = 'a';
end;
begin
process
variable c : character := 'a';
begin
check ("bac");
wait for 2 ns;
check ((1 => 'e', 2 => c, 3 => 'c'));
report "SUCCESS";
wait;
end process;
end behav;
|
entity call6a is
end;
architecture behav of call6a is
procedure check (s : string) is
begin
wait for 1 ns;
assert s (2) = 'a';
end;
begin
process
variable c : character := 'a';
begin
check ("bac");
wait for 2 ns;
check ((1 => 'e', 2 => c, 3 => 'c'));
report "SUCCESS";
wait;
end process;
end behav;
|
-------------------------------------------------------------------------------
--! @file convRmiiToMii-rtl-ea.vhd
--
--! @brief RMII-to-MII converter
--
--! @details This is an RMII-to-MII converter to convert MII phy traces to RMII.
--! Example: MII PHY <--> RMII-to-MII converter <--> RMII MAC
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
--! Work library
library work;
--! use openmac package
use work.openmacPkg.all;
entity convRmiiToMii is
port (
--! Reset
iRst : in std_logic;
--! RMII Clock
iClk : in std_logic;
--! RMII transmit path
iRmiiTx : in tRmiiPath;
--! RMII receive path
oRmiiRx : out tRmiiPath;
--! MII receive clock
iMiiRxClk : in std_logic;
--! MII receive path
iMiiRx : in tMiiPath;
--! MII receive error
iMiiRxError : in std_logic;
--! MII transmit clock
iMiiTxClk : in std_logic;
--! MII transmit path
oMiiTx : out tMiiPath
);
end convRmiiToMii;
architecture rtl of convRmiiToMii is
constant DIBIT_SIZE : integer := 2;
constant NIBBLE_SIZE : integer := 4;
begin
TX_BLOCK : block
--fifo size must not be larger than 2**5
constant FIFO_NIBBLES_LOG2 : integer := 5;
signal fifo_half, fifo_full, fifo_empty, fifo_valid, txEnable_reg : std_logic;
signal fifo_wr, fifo_rd : std_logic;
signal fifo_din : std_logic_vector(NIBBLE_SIZE-1 downto 0);
signal fifo_dout, txData_reg : std_logic_vector(NIBBLE_SIZE-1 downto 0);
signal fifo_rdUsedWord : std_logic_vector (FIFO_NIBBLES_LOG2-1 downto 0);
--necessary for clr fifo
signal aclr, rTxEn_l : std_logic;
--convert dibits to nibble
signal sel_dibit : std_logic;
signal fifo_din_reg : std_logic_vector(iRmiiTx.data'range);
begin
fifo_din <= iRmiiTx.data & fifo_din_reg;
fifo_wr <= sel_dibit;
--convert dibits to nibble (to fit to fifo)
process(iClk, iRst)
begin
if iRst = cActivated then
sel_dibit <= cInactivated;
fifo_din_reg <= (others => cInactivated);
elsif iClk = cActivated and iClk'event then
if iRmiiTx.enable = cActivated then
sel_dibit <= not sel_dibit;
if sel_dibit = cInactivated then
fifo_din_reg <= iRmiiTx.data;
end if;
else
sel_dibit <= cInactivated;
end if;
end if;
end process;
fifo_half <= fifo_rdUsedWord(fifo_rdUsedWord'left);
oMiiTx.data <= txData_reg;
oMiiTx.enable <= txEnable_reg;
process(iMiiTxClk, iRst)
begin
if iRst = cActivated then
fifo_rd <= cInactivated;
fifo_valid <= cInactivated;
txData_reg <= (others => cInactivated);
txEnable_reg <= cInactivated;
elsif iMiiTxClk = cActivated and iMiiTxClk'event then
txData_reg <= fifo_dout;
txEnable_reg <= fifo_valid;
if fifo_rd = cInactivated and fifo_half = cActivated then
fifo_rd <= cActivated;
elsif fifo_rd = cActivated and fifo_empty = cActivated then
fifo_rd <= cInactivated;
end if;
if fifo_rd = cActivated and fifo_rdUsedWord > std_logic_vector(to_unsigned(1, fifo_rdUsedWord'length)) then
fifo_valid <= cActivated;
else
fifo_valid <= cInactivated;
end if;
end if;
end process;
--! This is the asynchronous FIFO used to decouple RMII from MII.
TXFIFO : entity work.asyncFifo
generic map (
gDataWidth => NIBBLE_SIZE,
gWordSize => 2**FIFO_NIBBLES_LOG2,
gSyncStages => 2,
gMemRes => "ON"
)
port map (
iAclr => aclr,
iWrClk => iClk,
iWrReq => fifo_wr,
iWrData => fifo_din,
oWrEmpty => open,
oWrFull => fifo_full,
oWrUsedw => open,
iRdClk => iMiiTxClk,
iRdReq => fifo_rd,
oRdData => fifo_dout,
oRdEmpty => fifo_empty,
oRdFull => open,
oRdUsedw => fifo_rdUsedWord
);
--sync Mii Tx En (=fifo_valid) to wr clk
process(iClk, iRst)
begin
if iRst = cActivated then
aclr <= cActivated; --reset fifo
rTxEn_l <= cInactivated;
elsif iClk = cActivated and iClk'event then
rTxEn_l <= iRmiiTx.enable;
aclr <= cInactivated; --default
--clear the full fifo after TX on RMII side is done
if fifo_full = cActivated and rTxEn_l = cActivated and iRmiiTx.enable = cInactivated then
aclr <= cActivated;
end if;
end if;
end process;
end block;
RX_BLOCK : block
--fifo size must not be larger than 2**5
constant FIFO_NIBBLES_LOG2 : integer := 5;
signal fifo_half, fifo_empty, fifo_valid : std_logic;
signal rxDataValid_reg, fifo_rd : std_logic;
signal rxError_reg : std_logic;
signal fifo_wr : std_logic;
signal rxData_reg : std_logic_vector(NIBBLE_SIZE-1 downto 0);
signal fifo_dout : std_logic_vector(NIBBLE_SIZE-1 downto 0);
signal fifo_rdUsedWord : std_logic_vector(FIFO_NIBBLES_LOG2-1 downto 0);
signal fifo_wrUsedWord : std_logic_vector(FIFO_NIBBLES_LOG2-1 downto 0);
--convert nibble to dibits
signal sel_dibit : std_logic;
signal fifo_rd_s : std_logic;
begin
process(iMiiRxClk, iRst)
begin
if iRst = cActivated then
rxData_reg <= (others => cInactivated);
rxDataValid_reg <= cInactivated;
rxError_reg <= cInactivated;
elsif iMiiRxClk = cActivated and iMiiRxClk'event then
rxData_reg <= iMiiRx.data;
rxDataValid_reg <= iMiiRx.enable;
rxError_reg <= iMiiRxError;
end if;
end process;
fifo_wr <= rxDataValid_reg and not rxError_reg;
oRmiiRx.data <= fifo_dout(fifo_dout'right+1 downto 0) when sel_dibit = cActivated else
fifo_dout(fifo_dout'left downto fifo_dout'left-1);
oRmiiRx.enable <= fifo_valid;
fifo_rd <= fifo_rd_s and not sel_dibit;
process(iClk, iRst)
begin
if iRst = cActivated then
sel_dibit <= cInactivated;
elsif iClk = cActivated and iClk'event then
if fifo_rd_s = cActivated or fifo_valid = cActivated then
sel_dibit <= not sel_dibit;
else
sel_dibit <= cInactivated;
end if;
end if;
end process;
fifo_half <= fifo_rdUsedWord(fifo_rdUsedWord'left);
process(iClk, iRst)
begin
if iRst = cActivated then
fifo_rd_s <= cInactivated;
fifo_valid <= cInactivated;
elsif iClk = cActivated and iClk'event then
if fifo_rd_s = cInactivated and fifo_half = cActivated then
fifo_rd_s <= cActivated;
elsif fifo_rd_s = cActivated and fifo_empty = cActivated then
fifo_rd_s <= cInactivated;
end if;
if fifo_rd_s = cActivated then
fifo_valid <= cActivated;
else
fifo_valid <= cInactivated;
end if;
end if;
end process;
--! This is the asynchronous FIFO used to decouple RMII from MII.
RXFIFO : entity work.asyncFifo
generic map (
gDataWidth => NIBBLE_SIZE,
gWordSize => 2**FIFO_NIBBLES_LOG2,
gSyncStages => 2,
gMemRes => "ON"
)
port map (
iAclr => iRst,
iWrClk => iMiiRxClk,
iWrReq => fifo_wr,
iWrData => rxData_reg,
oWrEmpty => open,
oWrFull => open,
oWrUsedw => open,
iRdClk => iClk,
iRdReq => fifo_rd,
oRdData => fifo_dout,
oRdEmpty => fifo_empty,
oRdFull => open,
oRdUsedw => fifo_rdUsedWord
);
end block;
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity issue is
port (sub_uns : out unsigned (8-1 downto 0);
sub_sgn : out signed (8-1 downto 0));
end issue;
architecture beh of issue is
begin
sub_uns <= unsigned'(b"0000_0000") - 1; -- works
sub_sgn <= signed'(b"0000_0000") - 1; -- fails
end architecture beh;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_3_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 05:50:09 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../generic.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_3_e-rtl-a.vhd,v 1.4 2006/06/26 07:42:18 wig Exp $
-- $Date: 2006/06/26 07:42:18 $
-- $Log: inst_3_e-rtl-a.vhd,v $
-- Revision 1.4 2006/06/26 07:42:18 wig
-- Updated io, generic and mde_tests testcases
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_3_e
--
architecture rtl of inst_3_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1237.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s02b00x00p03n01i01237ent IS
END c08s02b00x00p03n01i01237ent;
ARCHITECTURE c08s02b00x00p03n01i01237arch OF c08s02b00x00p03n01i01237ent IS
BEGIN
TESTING: PROCESS
variable k : real;
BEGIN
assert k;
assert FALSE
report "***FAILED TEST: c08s02b00x00p03n01i01237 - The condition in the assert statement is not of type boolean"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s02b00x00p03n01i01237arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1237.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s02b00x00p03n01i01237ent IS
END c08s02b00x00p03n01i01237ent;
ARCHITECTURE c08s02b00x00p03n01i01237arch OF c08s02b00x00p03n01i01237ent IS
BEGIN
TESTING: PROCESS
variable k : real;
BEGIN
assert k;
assert FALSE
report "***FAILED TEST: c08s02b00x00p03n01i01237 - The condition in the assert statement is not of type boolean"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s02b00x00p03n01i01237arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1237.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s02b00x00p03n01i01237ent IS
END c08s02b00x00p03n01i01237ent;
ARCHITECTURE c08s02b00x00p03n01i01237arch OF c08s02b00x00p03n01i01237ent IS
BEGIN
TESTING: PROCESS
variable k : real;
BEGIN
assert k;
assert FALSE
report "***FAILED TEST: c08s02b00x00p03n01i01237 - The condition in the assert statement is not of type boolean"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s02b00x00p03n01i01237arch;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity globalmodereg is
port (
clk: in STD_LOGIC;
ibus: in STD_LOGIC_VECTOR (15 downto 0);
obus: out STD_LOGIC_VECTOR (15 downto 0);
reset: in STD_LOGIC;
loadglobalmode: in STD_LOGIC;
readglobalmode: in STD_LOGIC;
ctrena: out STD_LOGIC;
pwmena: out STD_LOGIC;
clearpwmena: in STD_LOGIC;
loi: out STD_LOGIC;
som: out STD_LOGIC;
sot: out STD_LOGIC;
miout: out STD_LOGIC;
miin: in STD_LOGIC;
irqmask: out STD_LOGIC;
irqstatus: in STD_LOGIC
);
end globalmodereg;
architecture behavioral of globalmodereg is
signal ctrenareg: STD_LOGIC;
signal pwmenareg: STD_LOGIC;
signal loireg: STD_LOGIC;
signal somreg: STD_LOGIC;
signal sotreg: STD_LOGIC;
signal mioutreg: STD_LOGIC;
signal irqmaskreg: STD_LOGIC;
begin
aglobalmodereg: process(
clk,
ibus,
loadglobalmode,
reset,
readglobalmode,
ctrenareg,
pwmenareg,
clearpwmena,
loireg,
somreg,
sotreg,
mioutreg,
miin
)
begin
if clk'event and clk = '1' then
if reset = '1' then
ctrenareg <= '0';
pwmenareg <= '0';
loireg <= '0';
somreg <= '0';
sotreg <= '0';
mioutreg <= '1';
irqmaskreg <= '0';
elsif loadglobalmode = '1' then
ctrenareg <= ibus(0);
pwmenareg <= ibus(1);
loireg <= ibus(2);
somreg <= ibus(3);
mioutreg <= not ibus(4);
irqmaskreg <= ibus(5);
sotreg <= ibus(7);
end if;
if mioutreg = '1' then
mioutreg <= '0';
end if;
end if;
if clearpwmena = '1' then
pwmenareg <= '0';
end if;
if readglobalmode = '1' then
obus(0) <= ctrenareg;
obus(1) <= pwmenareg;
obus(2) <= loireg;
obus(3) <= somreg;
obus(4) <= miin;
obus(5) <= irqmaskreg;
obus(6) <= irqstatus;
obus(7) <= sotreg;
obus(15 downto 8) <= "ZZZZZZZZ";
else
obus <= "ZZZZZZZZZZZZZZZZ";
end if;
ctrena <= ctrenareg;
pwmena <= pwmenareg;
loi <= loireg;
miout <= mioutreg or reset;
som <= somreg;
irqmask <= irqmaskreg;
sot <= sotreg;
end process;
end behavioral;
|
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Testbench Package
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: Instruction_Memory_tb_pkg.vhd
--
-- Description:
-- DMG Testbench Package files
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE Instruction_Memory_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE :STRING)
RETURN STRING;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE :STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER;
END Instruction_Memory_TB_PKG;
PACKAGE BODY Instruction_Memory_TB_PKG IS
FUNCTION DIVROUNDUP (
DATA_VALUE : INTEGER;
DIVISOR : INTEGER)
RETURN INTEGER IS
VARIABLE DIV : INTEGER;
BEGIN
DIV := DATA_VALUE/DIVISOR;
IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN
DIV := DIV+1;
END IF;
RETURN DIV;
END DIVROUNDUP;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC_VECTOR;
FALSE_CASE : STD_LOGIC_VECTOR)
RETURN STD_LOGIC_VECTOR IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STD_LOGIC;
FALSE_CASE : STD_LOGIC)
RETURN STD_LOGIC IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : INTEGER;
FALSE_CASE : INTEGER)
RETURN INTEGER IS
VARIABLE RETVAL : INTEGER := 0;
BEGIN
IF CONDITION=FALSE THEN
RETVAL:=FALSE_CASE;
ELSE
RETVAL:=TRUE_CASE;
END IF;
RETURN RETVAL;
END IF_THEN_ELSE;
---------------------------------
FUNCTION IF_THEN_ELSE (
CONDITION : BOOLEAN;
TRUE_CASE : STRING;
FALSE_CASE : STRING)
RETURN STRING IS
BEGIN
IF NOT CONDITION THEN
RETURN FALSE_CASE;
ELSE
RETURN TRUE_CASE;
END IF;
END IF_THEN_ELSE;
-------------------------------
FUNCTION LOG2ROUNDUP (
DATA_VALUE : INTEGER)
RETURN INTEGER IS
VARIABLE WIDTH : INTEGER := 0;
VARIABLE CNT : INTEGER := 1;
BEGIN
IF (DATA_VALUE <= 1) THEN
WIDTH := 1;
ELSE
WHILE (CNT < DATA_VALUE) LOOP
WIDTH := WIDTH + 1;
CNT := CNT *2;
END LOOP;
END IF;
RETURN WIDTH;
END LOG2ROUNDUP;
END Instruction_Memory_TB_PKG;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee;
use ieee.std_logic_1164.all;
entity syspll1 is
port (
refclk : in std_logic := 'X'; -- clk
rst : in std_logic := 'X'; -- reset
outclk_0 : out std_logic; -- clk
locked : out std_logic -- export
);
end;
architecture sim of syspll1 is
begin
p: process
variable vclk: std_logic := '0';
begin
outclk_0 <= vclk;
wait for 5.555 ns;
vclk := not vclk;
end process;
locked <= '0', '1' after 1 us;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fast_slave is
port(
clk_proc : in std_logic;
reset_n : in std_logic;
addr_rel_i : in std_logic_vector(1 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0);
enable_o : out std_logic
);
end fast_slave;
architecture rtl of fast_slave is
constant ENABLE_REG_ADDR : natural := 0;
signal enable_reg : std_logic;
begin
write_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
enable_reg <= '0';
elsif(rising_edge(clk_proc)) then
if(wr_i='1') then
case addr_rel_i is
when std_logic_vector(to_unsigned(ENABLE_REG_ADDR, 2)) => enable_reg <= datawr_i(0);
when others=>
end case;
end if;
end if;
end process;
enable_o <= enable_reg;
end rtl;
|
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:dds_compiler:6.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY dds_compiler_v6_0;
USE dds_compiler_v6_0.dds_compiler_v6_0;
ENTITY dds IS
PORT (
aclk : IN STD_LOGIC;
s_axis_phase_tvalid : IN STD_LOGIC;
s_axis_phase_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END dds;
ARCHITECTURE dds_arch OF dds IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF dds_arch: ARCHITECTURE IS "yes";
COMPONENT dds_compiler_v6_0 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_MODE_OF_OPERATION : INTEGER;
C_MODULUS : INTEGER;
C_ACCUMULATOR_WIDTH : INTEGER;
C_CHANNELS : INTEGER;
C_HAS_PHASE_OUT : INTEGER;
C_HAS_PHASEGEN : INTEGER;
C_HAS_SINCOS : INTEGER;
C_LATENCY : INTEGER;
C_MEM_TYPE : INTEGER;
C_NEGATIVE_COSINE : INTEGER;
C_NEGATIVE_SINE : INTEGER;
C_NOISE_SHAPING : INTEGER;
C_OUTPUTS_REQUIRED : INTEGER;
C_OUTPUT_FORM : INTEGER;
C_OUTPUT_WIDTH : INTEGER;
C_PHASE_ANGLE_WIDTH : INTEGER;
C_PHASE_INCREMENT : INTEGER;
C_PHASE_INCREMENT_VALUE : STRING;
C_RESYNC : INTEGER;
C_PHASE_OFFSET : INTEGER;
C_PHASE_OFFSET_VALUE : STRING;
C_OPTIMISE_GOAL : INTEGER;
C_USE_DSP48 : INTEGER;
C_POR_MODE : INTEGER;
C_AMPLITUDE : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_HAS_TLAST : INTEGER;
C_HAS_TREADY : INTEGER;
C_HAS_S_PHASE : INTEGER;
C_S_PHASE_TDATA_WIDTH : INTEGER;
C_S_PHASE_HAS_TUSER : INTEGER;
C_S_PHASE_TUSER_WIDTH : INTEGER;
C_HAS_S_CONFIG : INTEGER;
C_S_CONFIG_SYNC_MODE : INTEGER;
C_S_CONFIG_TDATA_WIDTH : INTEGER;
C_HAS_M_DATA : INTEGER;
C_M_DATA_TDATA_WIDTH : INTEGER;
C_M_DATA_HAS_TUSER : INTEGER;
C_M_DATA_TUSER_WIDTH : INTEGER;
C_HAS_M_PHASE : INTEGER;
C_M_PHASE_TDATA_WIDTH : INTEGER;
C_M_PHASE_HAS_TUSER : INTEGER;
C_M_PHASE_TUSER_WIDTH : INTEGER;
C_DEBUG_INTERFACE : INTEGER;
C_CHAN_WIDTH : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_phase_tvalid : IN STD_LOGIC;
s_axis_phase_tready : OUT STD_LOGIC;
s_axis_phase_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axis_phase_tlast : IN STD_LOGIC;
s_axis_phase_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_config_tlast : IN STD_LOGIC;
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tready : IN STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_data_tlast : OUT STD_LOGIC;
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_phase_tvalid : OUT STD_LOGIC;
m_axis_phase_tready : IN STD_LOGIC;
m_axis_phase_tdata : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_phase_tlast : OUT STD_LOGIC;
m_axis_phase_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
event_pinc_invalid : OUT STD_LOGIC;
event_poff_invalid : OUT STD_LOGIC;
event_phase_in_invalid : OUT STD_LOGIC;
event_s_phase_tlast_missing : OUT STD_LOGIC;
event_s_phase_tlast_unexpected : OUT STD_LOGIC;
event_s_phase_chanid_incorrect : OUT STD_LOGIC;
event_s_config_tlast_missing : OUT STD_LOGIC;
event_s_config_tlast_unexpected : OUT STD_LOGIC
);
END COMPONENT dds_compiler_v6_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF dds_arch: ARCHITECTURE IS "dds_compiler_v6_0,Vivado 2013.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF dds_arch : ARCHITECTURE IS "dds,dds_compiler_v6_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF dds_arch: ARCHITECTURE IS "dds,dds_compiler_v6_0,{x_ipProduct=Vivado 2013.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=dds_compiler,x_ipVersion=6.0,x_ipCoreRevision=3,x_ipLanguage=VHDL,C_XDEVICEFAMILY=zynq,C_MODE_OF_OPERATION=0,C_MODULUS=9,C_ACCUMULATOR_WIDTH=16,C_CHANNELS=1,C_HAS_PHASE_OUT=0,C_HAS_PHASEGEN=1,C_HAS_SINCOS=1,C_LATENCY=7,C_MEM_TYPE=1,C_NEGATIVE_COSINE=0,C_NEGATIVE_SINE=0,C_NOISE_SHAPING=0,C_OUTPUTS_REQUIRED=2,C_OUTPUT_FORM=0,C_OUTPUT_WIDTH=16,C_PHASE_ANGLE_WIDTH=16,C_PHASE_INCREMENT=3,C_PHASE_INCREMENT_VALUE=0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0,C_RESYNC=0,C_PHASE_OFFSET=0,C_PHASE_OFFSET_VALUE=0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0,C_OPTIMISE_GOAL=0,C_USE_DSP48=0,C_POR_MODE=0,C_AMPLITUDE=0,C_HAS_ACLKEN=0,C_HAS_ARESETN=0,C_HAS_TLAST=0,C_HAS_TREADY=0,C_HAS_S_PHASE=1,C_S_PHASE_TDATA_WIDTH=16,C_S_PHASE_HAS_TUSER=0,C_S_PHASE_TUSER_WIDTH=1,C_HAS_S_CONFIG=0,C_S_CONFIG_SYNC_MODE=0,C_S_CONFIG_TDATA_WIDTH=1,C_HAS_M_DATA=1,C_M_DATA_TDATA_WIDTH=32,C_M_DATA_HAS_TUSER=0,C_M_DATA_TUSER_WIDTH=1,C_HAS_M_PHASE=0,C_M_PHASE_TDATA_WIDTH=1,C_M_PHASE_HAS_TUSER=0,C_M_PHASE_TUSER_WIDTH=1,C_DEBUG_INTERFACE=0,C_CHAN_WIDTH=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_phase_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_PHASE TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_phase_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_PHASE TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
BEGIN
U0 : dds_compiler_v6_0
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_MODE_OF_OPERATION => 0,
C_MODULUS => 9,
C_ACCUMULATOR_WIDTH => 16,
C_CHANNELS => 1,
C_HAS_PHASE_OUT => 0,
C_HAS_PHASEGEN => 1,
C_HAS_SINCOS => 1,
C_LATENCY => 7,
C_MEM_TYPE => 1,
C_NEGATIVE_COSINE => 0,
C_NEGATIVE_SINE => 0,
C_NOISE_SHAPING => 0,
C_OUTPUTS_REQUIRED => 2,
C_OUTPUT_FORM => 0,
C_OUTPUT_WIDTH => 16,
C_PHASE_ANGLE_WIDTH => 16,
C_PHASE_INCREMENT => 3,
C_PHASE_INCREMENT_VALUE => "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0",
C_RESYNC => 0,
C_PHASE_OFFSET => 0,
C_PHASE_OFFSET_VALUE => "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0",
C_OPTIMISE_GOAL => 0,
C_USE_DSP48 => 0,
C_POR_MODE => 0,
C_AMPLITUDE => 0,
C_HAS_ACLKEN => 0,
C_HAS_ARESETN => 0,
C_HAS_TLAST => 0,
C_HAS_TREADY => 0,
C_HAS_S_PHASE => 1,
C_S_PHASE_TDATA_WIDTH => 16,
C_S_PHASE_HAS_TUSER => 0,
C_S_PHASE_TUSER_WIDTH => 1,
C_HAS_S_CONFIG => 0,
C_S_CONFIG_SYNC_MODE => 0,
C_S_CONFIG_TDATA_WIDTH => 1,
C_HAS_M_DATA => 1,
C_M_DATA_TDATA_WIDTH => 32,
C_M_DATA_HAS_TUSER => 0,
C_M_DATA_TUSER_WIDTH => 1,
C_HAS_M_PHASE => 0,
C_M_PHASE_TDATA_WIDTH => 1,
C_M_PHASE_HAS_TUSER => 0,
C_M_PHASE_TUSER_WIDTH => 1,
C_DEBUG_INTERFACE => 0,
C_CHAN_WIDTH => 1
)
PORT MAP (
aclk => aclk,
aclken => '1',
aresetn => '1',
s_axis_phase_tvalid => s_axis_phase_tvalid,
s_axis_phase_tdata => s_axis_phase_tdata,
s_axis_phase_tlast => '0',
s_axis_phase_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_config_tvalid => '0',
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_config_tlast => '0',
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tready => '0',
m_axis_data_tdata => m_axis_data_tdata,
m_axis_phase_tready => '0'
);
END dds_arch;
|
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:dds_compiler:6.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY dds_compiler_v6_0;
USE dds_compiler_v6_0.dds_compiler_v6_0;
ENTITY dds IS
PORT (
aclk : IN STD_LOGIC;
s_axis_phase_tvalid : IN STD_LOGIC;
s_axis_phase_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END dds;
ARCHITECTURE dds_arch OF dds IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF dds_arch: ARCHITECTURE IS "yes";
COMPONENT dds_compiler_v6_0 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_MODE_OF_OPERATION : INTEGER;
C_MODULUS : INTEGER;
C_ACCUMULATOR_WIDTH : INTEGER;
C_CHANNELS : INTEGER;
C_HAS_PHASE_OUT : INTEGER;
C_HAS_PHASEGEN : INTEGER;
C_HAS_SINCOS : INTEGER;
C_LATENCY : INTEGER;
C_MEM_TYPE : INTEGER;
C_NEGATIVE_COSINE : INTEGER;
C_NEGATIVE_SINE : INTEGER;
C_NOISE_SHAPING : INTEGER;
C_OUTPUTS_REQUIRED : INTEGER;
C_OUTPUT_FORM : INTEGER;
C_OUTPUT_WIDTH : INTEGER;
C_PHASE_ANGLE_WIDTH : INTEGER;
C_PHASE_INCREMENT : INTEGER;
C_PHASE_INCREMENT_VALUE : STRING;
C_RESYNC : INTEGER;
C_PHASE_OFFSET : INTEGER;
C_PHASE_OFFSET_VALUE : STRING;
C_OPTIMISE_GOAL : INTEGER;
C_USE_DSP48 : INTEGER;
C_POR_MODE : INTEGER;
C_AMPLITUDE : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_HAS_TLAST : INTEGER;
C_HAS_TREADY : INTEGER;
C_HAS_S_PHASE : INTEGER;
C_S_PHASE_TDATA_WIDTH : INTEGER;
C_S_PHASE_HAS_TUSER : INTEGER;
C_S_PHASE_TUSER_WIDTH : INTEGER;
C_HAS_S_CONFIG : INTEGER;
C_S_CONFIG_SYNC_MODE : INTEGER;
C_S_CONFIG_TDATA_WIDTH : INTEGER;
C_HAS_M_DATA : INTEGER;
C_M_DATA_TDATA_WIDTH : INTEGER;
C_M_DATA_HAS_TUSER : INTEGER;
C_M_DATA_TUSER_WIDTH : INTEGER;
C_HAS_M_PHASE : INTEGER;
C_M_PHASE_TDATA_WIDTH : INTEGER;
C_M_PHASE_HAS_TUSER : INTEGER;
C_M_PHASE_TUSER_WIDTH : INTEGER;
C_DEBUG_INTERFACE : INTEGER;
C_CHAN_WIDTH : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_phase_tvalid : IN STD_LOGIC;
s_axis_phase_tready : OUT STD_LOGIC;
s_axis_phase_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axis_phase_tlast : IN STD_LOGIC;
s_axis_phase_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_config_tlast : IN STD_LOGIC;
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tready : IN STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_data_tlast : OUT STD_LOGIC;
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_phase_tvalid : OUT STD_LOGIC;
m_axis_phase_tready : IN STD_LOGIC;
m_axis_phase_tdata : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_phase_tlast : OUT STD_LOGIC;
m_axis_phase_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
event_pinc_invalid : OUT STD_LOGIC;
event_poff_invalid : OUT STD_LOGIC;
event_phase_in_invalid : OUT STD_LOGIC;
event_s_phase_tlast_missing : OUT STD_LOGIC;
event_s_phase_tlast_unexpected : OUT STD_LOGIC;
event_s_phase_chanid_incorrect : OUT STD_LOGIC;
event_s_config_tlast_missing : OUT STD_LOGIC;
event_s_config_tlast_unexpected : OUT STD_LOGIC
);
END COMPONENT dds_compiler_v6_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF dds_arch: ARCHITECTURE IS "dds_compiler_v6_0,Vivado 2013.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF dds_arch : ARCHITECTURE IS "dds,dds_compiler_v6_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF dds_arch: ARCHITECTURE IS "dds,dds_compiler_v6_0,{x_ipProduct=Vivado 2013.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=dds_compiler,x_ipVersion=6.0,x_ipCoreRevision=3,x_ipLanguage=VHDL,C_XDEVICEFAMILY=zynq,C_MODE_OF_OPERATION=0,C_MODULUS=9,C_ACCUMULATOR_WIDTH=16,C_CHANNELS=1,C_HAS_PHASE_OUT=0,C_HAS_PHASEGEN=1,C_HAS_SINCOS=1,C_LATENCY=7,C_MEM_TYPE=1,C_NEGATIVE_COSINE=0,C_NEGATIVE_SINE=0,C_NOISE_SHAPING=0,C_OUTPUTS_REQUIRED=2,C_OUTPUT_FORM=0,C_OUTPUT_WIDTH=16,C_PHASE_ANGLE_WIDTH=16,C_PHASE_INCREMENT=3,C_PHASE_INCREMENT_VALUE=0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0,C_RESYNC=0,C_PHASE_OFFSET=0,C_PHASE_OFFSET_VALUE=0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0,C_OPTIMISE_GOAL=0,C_USE_DSP48=0,C_POR_MODE=0,C_AMPLITUDE=0,C_HAS_ACLKEN=0,C_HAS_ARESETN=0,C_HAS_TLAST=0,C_HAS_TREADY=0,C_HAS_S_PHASE=1,C_S_PHASE_TDATA_WIDTH=16,C_S_PHASE_HAS_TUSER=0,C_S_PHASE_TUSER_WIDTH=1,C_HAS_S_CONFIG=0,C_S_CONFIG_SYNC_MODE=0,C_S_CONFIG_TDATA_WIDTH=1,C_HAS_M_DATA=1,C_M_DATA_TDATA_WIDTH=32,C_M_DATA_HAS_TUSER=0,C_M_DATA_TUSER_WIDTH=1,C_HAS_M_PHASE=0,C_M_PHASE_TDATA_WIDTH=1,C_M_PHASE_HAS_TUSER=0,C_M_PHASE_TUSER_WIDTH=1,C_DEBUG_INTERFACE=0,C_CHAN_WIDTH=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_phase_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_PHASE TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_phase_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_PHASE TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
BEGIN
U0 : dds_compiler_v6_0
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_MODE_OF_OPERATION => 0,
C_MODULUS => 9,
C_ACCUMULATOR_WIDTH => 16,
C_CHANNELS => 1,
C_HAS_PHASE_OUT => 0,
C_HAS_PHASEGEN => 1,
C_HAS_SINCOS => 1,
C_LATENCY => 7,
C_MEM_TYPE => 1,
C_NEGATIVE_COSINE => 0,
C_NEGATIVE_SINE => 0,
C_NOISE_SHAPING => 0,
C_OUTPUTS_REQUIRED => 2,
C_OUTPUT_FORM => 0,
C_OUTPUT_WIDTH => 16,
C_PHASE_ANGLE_WIDTH => 16,
C_PHASE_INCREMENT => 3,
C_PHASE_INCREMENT_VALUE => "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0",
C_RESYNC => 0,
C_PHASE_OFFSET => 0,
C_PHASE_OFFSET_VALUE => "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0",
C_OPTIMISE_GOAL => 0,
C_USE_DSP48 => 0,
C_POR_MODE => 0,
C_AMPLITUDE => 0,
C_HAS_ACLKEN => 0,
C_HAS_ARESETN => 0,
C_HAS_TLAST => 0,
C_HAS_TREADY => 0,
C_HAS_S_PHASE => 1,
C_S_PHASE_TDATA_WIDTH => 16,
C_S_PHASE_HAS_TUSER => 0,
C_S_PHASE_TUSER_WIDTH => 1,
C_HAS_S_CONFIG => 0,
C_S_CONFIG_SYNC_MODE => 0,
C_S_CONFIG_TDATA_WIDTH => 1,
C_HAS_M_DATA => 1,
C_M_DATA_TDATA_WIDTH => 32,
C_M_DATA_HAS_TUSER => 0,
C_M_DATA_TUSER_WIDTH => 1,
C_HAS_M_PHASE => 0,
C_M_PHASE_TDATA_WIDTH => 1,
C_M_PHASE_HAS_TUSER => 0,
C_M_PHASE_TUSER_WIDTH => 1,
C_DEBUG_INTERFACE => 0,
C_CHAN_WIDTH => 1
)
PORT MAP (
aclk => aclk,
aclken => '1',
aresetn => '1',
s_axis_phase_tvalid => s_axis_phase_tvalid,
s_axis_phase_tdata => s_axis_phase_tdata,
s_axis_phase_tlast => '0',
s_axis_phase_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_config_tvalid => '0',
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_config_tlast => '0',
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tready => '0',
m_axis_data_tdata => m_axis_data_tdata,
m_axis_phase_tready => '0'
);
END dds_arch;
|
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:dds_compiler:6.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY dds_compiler_v6_0;
USE dds_compiler_v6_0.dds_compiler_v6_0;
ENTITY dds IS
PORT (
aclk : IN STD_LOGIC;
s_axis_phase_tvalid : IN STD_LOGIC;
s_axis_phase_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END dds;
ARCHITECTURE dds_arch OF dds IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF dds_arch: ARCHITECTURE IS "yes";
COMPONENT dds_compiler_v6_0 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_MODE_OF_OPERATION : INTEGER;
C_MODULUS : INTEGER;
C_ACCUMULATOR_WIDTH : INTEGER;
C_CHANNELS : INTEGER;
C_HAS_PHASE_OUT : INTEGER;
C_HAS_PHASEGEN : INTEGER;
C_HAS_SINCOS : INTEGER;
C_LATENCY : INTEGER;
C_MEM_TYPE : INTEGER;
C_NEGATIVE_COSINE : INTEGER;
C_NEGATIVE_SINE : INTEGER;
C_NOISE_SHAPING : INTEGER;
C_OUTPUTS_REQUIRED : INTEGER;
C_OUTPUT_FORM : INTEGER;
C_OUTPUT_WIDTH : INTEGER;
C_PHASE_ANGLE_WIDTH : INTEGER;
C_PHASE_INCREMENT : INTEGER;
C_PHASE_INCREMENT_VALUE : STRING;
C_RESYNC : INTEGER;
C_PHASE_OFFSET : INTEGER;
C_PHASE_OFFSET_VALUE : STRING;
C_OPTIMISE_GOAL : INTEGER;
C_USE_DSP48 : INTEGER;
C_POR_MODE : INTEGER;
C_AMPLITUDE : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_HAS_TLAST : INTEGER;
C_HAS_TREADY : INTEGER;
C_HAS_S_PHASE : INTEGER;
C_S_PHASE_TDATA_WIDTH : INTEGER;
C_S_PHASE_HAS_TUSER : INTEGER;
C_S_PHASE_TUSER_WIDTH : INTEGER;
C_HAS_S_CONFIG : INTEGER;
C_S_CONFIG_SYNC_MODE : INTEGER;
C_S_CONFIG_TDATA_WIDTH : INTEGER;
C_HAS_M_DATA : INTEGER;
C_M_DATA_TDATA_WIDTH : INTEGER;
C_M_DATA_HAS_TUSER : INTEGER;
C_M_DATA_TUSER_WIDTH : INTEGER;
C_HAS_M_PHASE : INTEGER;
C_M_PHASE_TDATA_WIDTH : INTEGER;
C_M_PHASE_HAS_TUSER : INTEGER;
C_M_PHASE_TUSER_WIDTH : INTEGER;
C_DEBUG_INTERFACE : INTEGER;
C_CHAN_WIDTH : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_phase_tvalid : IN STD_LOGIC;
s_axis_phase_tready : OUT STD_LOGIC;
s_axis_phase_tdata : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
s_axis_phase_tlast : IN STD_LOGIC;
s_axis_phase_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_config_tlast : IN STD_LOGIC;
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tready : IN STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_data_tlast : OUT STD_LOGIC;
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_phase_tvalid : OUT STD_LOGIC;
m_axis_phase_tready : IN STD_LOGIC;
m_axis_phase_tdata : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_phase_tlast : OUT STD_LOGIC;
m_axis_phase_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
event_pinc_invalid : OUT STD_LOGIC;
event_poff_invalid : OUT STD_LOGIC;
event_phase_in_invalid : OUT STD_LOGIC;
event_s_phase_tlast_missing : OUT STD_LOGIC;
event_s_phase_tlast_unexpected : OUT STD_LOGIC;
event_s_phase_chanid_incorrect : OUT STD_LOGIC;
event_s_config_tlast_missing : OUT STD_LOGIC;
event_s_config_tlast_unexpected : OUT STD_LOGIC
);
END COMPONENT dds_compiler_v6_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF dds_arch: ARCHITECTURE IS "dds_compiler_v6_0,Vivado 2013.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF dds_arch : ARCHITECTURE IS "dds,dds_compiler_v6_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF dds_arch: ARCHITECTURE IS "dds,dds_compiler_v6_0,{x_ipProduct=Vivado 2013.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=dds_compiler,x_ipVersion=6.0,x_ipCoreRevision=3,x_ipLanguage=VHDL,C_XDEVICEFAMILY=zynq,C_MODE_OF_OPERATION=0,C_MODULUS=9,C_ACCUMULATOR_WIDTH=16,C_CHANNELS=1,C_HAS_PHASE_OUT=0,C_HAS_PHASEGEN=1,C_HAS_SINCOS=1,C_LATENCY=7,C_MEM_TYPE=1,C_NEGATIVE_COSINE=0,C_NEGATIVE_SINE=0,C_NOISE_SHAPING=0,C_OUTPUTS_REQUIRED=2,C_OUTPUT_FORM=0,C_OUTPUT_WIDTH=16,C_PHASE_ANGLE_WIDTH=16,C_PHASE_INCREMENT=3,C_PHASE_INCREMENT_VALUE=0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0,C_RESYNC=0,C_PHASE_OFFSET=0,C_PHASE_OFFSET_VALUE=0_0_0_0_0_0_0_0_0_0_0_0_0_0_0_0,C_OPTIMISE_GOAL=0,C_USE_DSP48=0,C_POR_MODE=0,C_AMPLITUDE=0,C_HAS_ACLKEN=0,C_HAS_ARESETN=0,C_HAS_TLAST=0,C_HAS_TREADY=0,C_HAS_S_PHASE=1,C_S_PHASE_TDATA_WIDTH=16,C_S_PHASE_HAS_TUSER=0,C_S_PHASE_TUSER_WIDTH=1,C_HAS_S_CONFIG=0,C_S_CONFIG_SYNC_MODE=0,C_S_CONFIG_TDATA_WIDTH=1,C_HAS_M_DATA=1,C_M_DATA_TDATA_WIDTH=32,C_M_DATA_HAS_TUSER=0,C_M_DATA_TUSER_WIDTH=1,C_HAS_M_PHASE=0,C_M_PHASE_TDATA_WIDTH=1,C_M_PHASE_HAS_TUSER=0,C_M_PHASE_TUSER_WIDTH=1,C_DEBUG_INTERFACE=0,C_CHAN_WIDTH=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_phase_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_PHASE TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_phase_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_PHASE TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
BEGIN
U0 : dds_compiler_v6_0
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_MODE_OF_OPERATION => 0,
C_MODULUS => 9,
C_ACCUMULATOR_WIDTH => 16,
C_CHANNELS => 1,
C_HAS_PHASE_OUT => 0,
C_HAS_PHASEGEN => 1,
C_HAS_SINCOS => 1,
C_LATENCY => 7,
C_MEM_TYPE => 1,
C_NEGATIVE_COSINE => 0,
C_NEGATIVE_SINE => 0,
C_NOISE_SHAPING => 0,
C_OUTPUTS_REQUIRED => 2,
C_OUTPUT_FORM => 0,
C_OUTPUT_WIDTH => 16,
C_PHASE_ANGLE_WIDTH => 16,
C_PHASE_INCREMENT => 3,
C_PHASE_INCREMENT_VALUE => "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0",
C_RESYNC => 0,
C_PHASE_OFFSET => 0,
C_PHASE_OFFSET_VALUE => "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0",
C_OPTIMISE_GOAL => 0,
C_USE_DSP48 => 0,
C_POR_MODE => 0,
C_AMPLITUDE => 0,
C_HAS_ACLKEN => 0,
C_HAS_ARESETN => 0,
C_HAS_TLAST => 0,
C_HAS_TREADY => 0,
C_HAS_S_PHASE => 1,
C_S_PHASE_TDATA_WIDTH => 16,
C_S_PHASE_HAS_TUSER => 0,
C_S_PHASE_TUSER_WIDTH => 1,
C_HAS_S_CONFIG => 0,
C_S_CONFIG_SYNC_MODE => 0,
C_S_CONFIG_TDATA_WIDTH => 1,
C_HAS_M_DATA => 1,
C_M_DATA_TDATA_WIDTH => 32,
C_M_DATA_HAS_TUSER => 0,
C_M_DATA_TUSER_WIDTH => 1,
C_HAS_M_PHASE => 0,
C_M_PHASE_TDATA_WIDTH => 1,
C_M_PHASE_HAS_TUSER => 0,
C_M_PHASE_TUSER_WIDTH => 1,
C_DEBUG_INTERFACE => 0,
C_CHAN_WIDTH => 1
)
PORT MAP (
aclk => aclk,
aclken => '1',
aresetn => '1',
s_axis_phase_tvalid => s_axis_phase_tvalid,
s_axis_phase_tdata => s_axis_phase_tdata,
s_axis_phase_tlast => '0',
s_axis_phase_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_config_tvalid => '0',
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_config_tlast => '0',
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tready => '0',
m_axis_data_tdata => m_axis_data_tdata,
m_axis_phase_tready => '0'
);
END dds_arch;
|
use Std.Textio.all;
LIBRARY ieee;
use ieee.std_logic_1164.ALL;
LIBRARY WORK;
use WORK.ALL;
entity test_Signal is end;
architecture test_Signal of test_Signal is
component C_Signal
generic (width : INTEGER := 4);
port (Input : in std_logic_Vector((width - 1) downto 0);
Store, Update, Clear, clock : in std_logic;
Output : out std_logic_Vector((width + 1) downto 0));
end component;
for all : C_Signal use entity Work.C_Signal(Behavior);
signal INPUT : std_logic_vector(3 downto 0) ;
signal OUTPUT : std_logic_vector(5 downto 0) ;
signal CLEAR : std_logic ;
signal clock : std_logic ;
signal STORE : std_logic ;
signal UPDATE : std_logic ;
begin
Signal1 : C_Signal generic map (4)
port map( Clear => CLEAR , clock => clock, input(3) => INPUT(3),input(2) => INPUT(2),input(1) => INPUT(1),input(0) => INPUT(0), output(5)=>output(5),output(4)=>output(4),output(3) => OUTPUT(3),output(2) => OUTPUT(2),output(1) => OUTPUT(1),output(0) => OUTPUT(0), Store => STORE, Update => UPDATE);
test_process : process
begin
clear <= '0';
clock <= '1';
store <= '1';
update <= '0';
input <= "1001";
WAIT FOR 50 ns;
clock <= '0';
WAIT FOR 50 ns;
clear <= '0';
clock <= '1';
store <= '0';
update <= '1';
WAIT FOR 50 ns;
clock <= '0';
WAIT FOR 50 ns;
clear <= '0';
clock <= '1';
store <= '0';
update <= '1';
WAIT FOR 50 ns;
clock <= '0';
WAIT FOR 50 ns;
clear <= '0';
clock <= '1';
store <= '1';
update <= '1';
input <= "1111";
WAIT FOR 50 ns;
clock <= '0';
WAIT FOR 50 ns;
clear <= '1';
clock <= '1';
store <= '1';
update <= '1';
input <= "1111";
WAIT FOR 50 ns;
clock <= '0';
WAIT FOR 50 ns;
wait;
------------ end checking --------------
end process test_process ;
end test_Signal;
---------------------------------------------------------------------------
---------------------------------------------------------------------------
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc449.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00449ent IS
END c03s02b01x01p19n01i00449ent;
ARCHITECTURE c03s02b01x01p19n01i00449arch OF c03s02b01x01p19n01i00449ent IS
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
subtype boolean_vector_st is boolean_vector(0 to 15);
subtype severity_level_vector_st is severity_level_vector(0 to 15);
subtype integer_vector_st is integer_vector(0 to 15);
subtype real_vector_st is real_vector(0 to 15);
subtype time_vector_st is time_vector(0 to 15);
subtype natural_vector_st is natural_vector(0 to 15);
subtype positive_vector_st is positive_vector(0 to 15);
type record_array_st is record
a:boolean_vector_st;
b:severity_level_vector_st;
c:integer_vector_st;
d:real_vector_st;
e:time_vector_st;
f:natural_vector_st;
g:positive_vector_st;
end record;
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant C70 : boolean_vector_st :=(others => C1);
constant C71 : severity_level_vector_st :=(others => C4);
constant C72 : integer_vector_st :=(others => C5);
constant C73 : real_vector_st :=(others => C6);
constant C74 : time_vector_st :=(others => C7);
constant C75 : natural_vector_st :=(others => C8);
constant C76 : positive_vector_st :=(others => C9);
constant C77 : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
function complex_scalar(s : record_array_st) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return record_array_st is
begin
return C77;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : record_array_st;
signal S2 : record_array_st;
signal S3 : record_array_st := C77;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C77) and (S2 = C77))
report "***PASSED TEST: c03s02b01x01p19n01i00449"
severity NOTE;
assert ((S1 = C77) and (S2 = C77))
report "***FAILED TEST: c03s02b01x01p19n01i00449 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00449arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc449.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00449ent IS
END c03s02b01x01p19n01i00449ent;
ARCHITECTURE c03s02b01x01p19n01i00449arch OF c03s02b01x01p19n01i00449ent IS
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
subtype boolean_vector_st is boolean_vector(0 to 15);
subtype severity_level_vector_st is severity_level_vector(0 to 15);
subtype integer_vector_st is integer_vector(0 to 15);
subtype real_vector_st is real_vector(0 to 15);
subtype time_vector_st is time_vector(0 to 15);
subtype natural_vector_st is natural_vector(0 to 15);
subtype positive_vector_st is positive_vector(0 to 15);
type record_array_st is record
a:boolean_vector_st;
b:severity_level_vector_st;
c:integer_vector_st;
d:real_vector_st;
e:time_vector_st;
f:natural_vector_st;
g:positive_vector_st;
end record;
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant C70 : boolean_vector_st :=(others => C1);
constant C71 : severity_level_vector_st :=(others => C4);
constant C72 : integer_vector_st :=(others => C5);
constant C73 : real_vector_st :=(others => C6);
constant C74 : time_vector_st :=(others => C7);
constant C75 : natural_vector_st :=(others => C8);
constant C76 : positive_vector_st :=(others => C9);
constant C77 : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
function complex_scalar(s : record_array_st) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return record_array_st is
begin
return C77;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : record_array_st;
signal S2 : record_array_st;
signal S3 : record_array_st := C77;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C77) and (S2 = C77))
report "***PASSED TEST: c03s02b01x01p19n01i00449"
severity NOTE;
assert ((S1 = C77) and (S2 = C77))
report "***FAILED TEST: c03s02b01x01p19n01i00449 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00449arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc449.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00449ent IS
END c03s02b01x01p19n01i00449ent;
ARCHITECTURE c03s02b01x01p19n01i00449arch OF c03s02b01x01p19n01i00449ent IS
type boolean_vector is array (natural range <>) of boolean;
type severity_level_vector is array (natural range <>) of severity_level;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
type natural_vector is array (natural range <>) of natural;
type positive_vector is array (natural range <>) of positive;
subtype boolean_vector_st is boolean_vector(0 to 15);
subtype severity_level_vector_st is severity_level_vector(0 to 15);
subtype integer_vector_st is integer_vector(0 to 15);
subtype real_vector_st is real_vector(0 to 15);
subtype time_vector_st is time_vector(0 to 15);
subtype natural_vector_st is natural_vector(0 to 15);
subtype positive_vector_st is positive_vector(0 to 15);
type record_array_st is record
a:boolean_vector_st;
b:severity_level_vector_st;
c:integer_vector_st;
d:real_vector_st;
e:time_vector_st;
f:natural_vector_st;
g:positive_vector_st;
end record;
constant C1 : boolean := true;
constant C2 : bit := '1';
constant C3 : character := 's';
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 1;
constant C9 : positive := 1;
constant C70 : boolean_vector_st :=(others => C1);
constant C71 : severity_level_vector_st :=(others => C4);
constant C72 : integer_vector_st :=(others => C5);
constant C73 : real_vector_st :=(others => C6);
constant C74 : time_vector_st :=(others => C7);
constant C75 : natural_vector_st :=(others => C8);
constant C76 : positive_vector_st :=(others => C9);
constant C77 : record_array_st := (C70,C71,C72,C73,C74,C75,C76);
function complex_scalar(s : record_array_st) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return record_array_st is
begin
return C77;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : record_array_st;
signal S2 : record_array_st;
signal S3 : record_array_st := C77;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C77) and (S2 = C77))
report "***PASSED TEST: c03s02b01x01p19n01i00449"
severity NOTE;
assert ((S1 = C77) and (S2 = C77))
report "***FAILED TEST: c03s02b01x01p19n01i00449 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00449arch;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: DEBUG_RAM_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan3e
-- C_XDEVICEFAMILY : spartan3e
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 1
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 0
-- C_INIT_FILE_NAME : no_coe_file_loaded
-- C_USE_DEFAULT_DATA : 1
-- C_DEFAULT_DATA : 20
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 52
-- C_READ_WIDTH_A : 52
-- C_WRITE_DEPTH_A : 16
-- C_READ_DEPTH_A : 16
-- C_ADDRA_WIDTH : 4
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 52
-- C_READ_WIDTH_B : 52
-- C_WRITE_DEPTH_B : 16
-- C_READ_DEPTH_B : 16
-- C_ADDRB_WIDTH : 4
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY DEBUG_RAM_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(51 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(51 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(51 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(51 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(51 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(51 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END DEBUG_RAM_prod;
ARCHITECTURE xilinx OF DEBUG_RAM_prod IS
COMPONENT DEBUG_RAM_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(51 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
ADDRB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(51 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : DEBUG_RAM_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
CLKA => CLKA,
--Port B
ADDRB => ADDRB,
DOUTB => DOUTB,
CLKB => CLKB
);
END xilinx;
|
Subsets and Splits
No saved queries yet
Save your SQL queries to embed, download, and access them later. Queries will appear here once saved.