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-- -------------------------------------------------------------
--
-- File Name: hdl_prj\hdlsrc\lms\lms_pcore_axi_lite_module.vhd
-- Created: 2015-06-19 16:39:46
--
-- Generated by MATLAB 8.5 and HDL Coder 3.6
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: lms_pcore_axi_lite_module
-- Source Path: lms_pcore/lms_pcore_axi_lite/lms_pcore_axi_lite_module
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY lms_pcore_axi_lite_module IS
PORT( clk : IN std_logic;
AXI4_Lite_ARESETN : IN std_logic; -- ufix1
AXI4_Lite_AWADDR : IN std_logic_vector(15 DOWNTO 0); -- ufix16
AXI4_Lite_AWVALID : IN std_logic; -- ufix1
AXI4_Lite_WDATA : IN std_logic_vector(31 DOWNTO 0); -- ufix32
AXI4_Lite_WSTRB : IN std_logic_vector(3 DOWNTO 0); -- ufix4
AXI4_Lite_WVALID : IN std_logic; -- ufix1
AXI4_Lite_BREADY : IN std_logic; -- ufix1
AXI4_Lite_ARADDR : IN std_logic_vector(15 DOWNTO 0); -- ufix16
AXI4_Lite_ARVALID : IN std_logic; -- ufix1
AXI4_Lite_RREADY : IN std_logic; -- ufix1
data_read : IN std_logic_vector(31 DOWNTO 0); -- ufix32
AXI4_Lite_AWREADY : OUT std_logic; -- ufix1
AXI4_Lite_WREADY : OUT std_logic; -- ufix1
AXI4_Lite_BRESP : OUT std_logic_vector(1 DOWNTO 0); -- ufix2
AXI4_Lite_BVALID : OUT std_logic; -- ufix1
AXI4_Lite_ARREADY : OUT std_logic; -- ufix1
AXI4_Lite_RDATA : OUT std_logic_vector(31 DOWNTO 0); -- ufix32
AXI4_Lite_RRESP : OUT std_logic_vector(1 DOWNTO 0); -- ufix2
AXI4_Lite_RVALID : OUT std_logic; -- ufix1
data_write : OUT std_logic_vector(31 DOWNTO 0); -- ufix32
addr_sel : OUT std_logic_vector(13 DOWNTO 0); -- ufix14
wr_enb : OUT std_logic; -- ufix1
rd_enb : OUT std_logic; -- ufix1
reset_internal : OUT std_logic -- ufix1
);
END lms_pcore_axi_lite_module;
ARCHITECTURE rtl OF lms_pcore_axi_lite_module IS
-- Signals
SIGNAL reset : std_logic;
SIGNAL enb : std_logic;
SIGNAL const_1 : std_logic; -- ufix1
SIGNAL axi_lite_wstate : unsigned(7 DOWNTO 0); -- uint8
SIGNAL axi_lite_rstate : unsigned(7 DOWNTO 0); -- uint8
SIGNAL axi_lite_wstate_next : unsigned(7 DOWNTO 0); -- uint8
SIGNAL axi_lite_rstate_next : unsigned(7 DOWNTO 0); -- uint8
SIGNAL aw_transfer : std_logic; -- ufix1
SIGNAL w_transfer : std_logic; -- ufix1
SIGNAL ar_transfer : std_logic; -- ufix1
SIGNAL const_0_2 : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL data_read_unsigned : unsigned(31 DOWNTO 0); -- ufix32
SIGNAL AXI4_Lite_RDATA_tmp : unsigned(31 DOWNTO 0); -- ufix32
SIGNAL AXI4_Lite_WDATA_unsigned : unsigned(31 DOWNTO 0); -- ufix32
SIGNAL wdata : unsigned(31 DOWNTO 0); -- ufix32
SIGNAL AXI4_Lite_AWADDR_unsigned : unsigned(15 DOWNTO 0); -- ufix16
SIGNAL waddr : unsigned(15 DOWNTO 0); -- ufix16
SIGNAL waddr_sel : unsigned(13 DOWNTO 0); -- ufix14
SIGNAL AXI4_Lite_ARADDR_unsigned : unsigned(15 DOWNTO 0); -- ufix16
SIGNAL raddr_sel : unsigned(13 DOWNTO 0); -- ufix14
SIGNAL addr_sel_tmp : unsigned(13 DOWNTO 0); -- ufix14
SIGNAL wr_enb_1 : std_logic; -- ufix1
SIGNAL strobe_addr : std_logic; -- ufix1
SIGNAL strobe_sel : std_logic; -- ufix1
SIGNAL const_zero : std_logic; -- ufix1
SIGNAL strobe_in : std_logic; -- ufix1
SIGNAL strobe_sw : std_logic; -- ufix1
SIGNAL soft_reset : std_logic; -- ufix1
BEGIN
const_1 <= '1';
enb <= const_1;
reset <= NOT AXI4_Lite_ARESETN;
axi_lite_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
axi_lite_wstate <= to_unsigned(16#00#, 8);
axi_lite_rstate <= to_unsigned(16#00#, 8);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
axi_lite_wstate <= axi_lite_wstate_next;
axi_lite_rstate <= axi_lite_rstate_next;
END IF;
END IF;
END PROCESS axi_lite_process;
axi_lite_output : PROCESS (axi_lite_wstate, axi_lite_rstate, AXI4_Lite_AWVALID, AXI4_Lite_WVALID,
AXI4_Lite_BREADY, AXI4_Lite_ARVALID, AXI4_Lite_RREADY)
VARIABLE out0 : std_logic;
VARIABLE out1 : std_logic;
VARIABLE out3 : std_logic;
VARIABLE awvalid : std_logic;
VARIABLE wvalid : std_logic;
VARIABLE arvalid : std_logic;
BEGIN
axi_lite_wstate_next <= axi_lite_wstate;
axi_lite_rstate_next <= axi_lite_rstate;
IF AXI4_Lite_AWVALID /= '0' THEN
awvalid := '1';
ELSE
awvalid := '0';
END IF;
IF AXI4_Lite_WVALID /= '0' THEN
wvalid := '1';
ELSE
wvalid := '0';
END IF;
IF AXI4_Lite_ARVALID /= '0' THEN
arvalid := '1';
ELSE
arvalid := '0';
END IF;
CASE axi_lite_wstate IS
WHEN "00000000" =>
out0 := '1';
out1 := '0';
AXI4_Lite_BVALID <= '0';
IF awvalid = '1' THEN
axi_lite_wstate_next <= to_unsigned(16#01#, 8);
ELSE
axi_lite_wstate_next <= to_unsigned(16#00#, 8);
END IF;
WHEN "00000001" =>
out0 := '0';
out1 := '1';
AXI4_Lite_BVALID <= '0';
IF wvalid = '1' THEN
axi_lite_wstate_next <= to_unsigned(16#02#, 8);
ELSE
axi_lite_wstate_next <= to_unsigned(16#01#, 8);
END IF;
WHEN "00000010" =>
out0 := '0';
out1 := '0';
AXI4_Lite_BVALID <= '1';
IF AXI4_Lite_BREADY /= '0' THEN
axi_lite_wstate_next <= to_unsigned(16#00#, 8);
ELSE
axi_lite_wstate_next <= to_unsigned(16#02#, 8);
END IF;
WHEN OTHERS =>
out0 := '0';
out1 := '0';
AXI4_Lite_BVALID <= '0';
axi_lite_wstate_next <= to_unsigned(16#00#, 8);
END CASE;
CASE axi_lite_rstate IS
WHEN "00000000" =>
out3 := '1';
AXI4_Lite_RVALID <= '0';
IF arvalid = '1' THEN
axi_lite_rstate_next <= to_unsigned(16#01#, 8);
ELSE
axi_lite_rstate_next <= to_unsigned(16#00#, 8);
END IF;
WHEN "00000001" =>
out3 := '0';
AXI4_Lite_RVALID <= '1';
IF AXI4_Lite_RREADY /= '0' THEN
axi_lite_rstate_next <= to_unsigned(16#00#, 8);
ELSE
axi_lite_rstate_next <= to_unsigned(16#01#, 8);
END IF;
WHEN OTHERS =>
out3 := '0';
AXI4_Lite_RVALID <= '0';
axi_lite_rstate_next <= to_unsigned(16#00#, 8);
END CASE;
AXI4_Lite_AWREADY <= out0;
AXI4_Lite_WREADY <= out1;
AXI4_Lite_ARREADY <= out3;
aw_transfer <= awvalid AND out0;
w_transfer <= wvalid AND out1;
ar_transfer <= arvalid AND out3;
END PROCESS axi_lite_output;
const_0_2 <= to_unsigned(16#0#, 2);
AXI4_Lite_BRESP <= std_logic_vector(const_0_2);
data_read_unsigned <= unsigned(data_read);
reg_rdata_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
AXI4_Lite_RDATA_tmp <= to_unsigned(0, 32);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' AND ar_transfer = '1' THEN
AXI4_Lite_RDATA_tmp <= data_read_unsigned;
END IF;
END IF;
END PROCESS reg_rdata_process;
AXI4_Lite_RDATA <= std_logic_vector(AXI4_Lite_RDATA_tmp);
AXI4_Lite_RRESP <= std_logic_vector(const_0_2);
AXI4_Lite_WDATA_unsigned <= unsigned(AXI4_Lite_WDATA);
reg_wdata_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
wdata <= to_unsigned(0, 32);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' AND w_transfer = '1' THEN
wdata <= AXI4_Lite_WDATA_unsigned;
END IF;
END IF;
END PROCESS reg_wdata_process;
data_write <= std_logic_vector(wdata);
AXI4_Lite_AWADDR_unsigned <= unsigned(AXI4_Lite_AWADDR);
reg_waddr_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
waddr <= to_unsigned(16#0000#, 16);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' AND aw_transfer = '1' THEN
waddr <= AXI4_Lite_AWADDR_unsigned;
END IF;
END IF;
END PROCESS reg_waddr_process;
waddr_sel <= waddr(15 DOWNTO 2);
AXI4_Lite_ARADDR_unsigned <= unsigned(AXI4_Lite_ARADDR);
raddr_sel <= AXI4_Lite_ARADDR_unsigned(15 DOWNTO 2);
addr_sel_tmp <= waddr_sel WHEN AXI4_Lite_ARVALID = '0' ELSE
raddr_sel;
addr_sel <= std_logic_vector(addr_sel_tmp);
reg_wr_enb_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
wr_enb_1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
wr_enb_1 <= w_transfer;
END IF;
END IF;
END PROCESS reg_wr_enb_process;
rd_enb <= ar_transfer;
strobe_addr <= '1' WHEN waddr_sel = to_unsigned(16#0000#, 14) ELSE
'0';
strobe_sel <= strobe_addr AND wr_enb_1;
const_zero <= '0';
strobe_in <= wdata(0);
strobe_sw <= const_zero WHEN strobe_sel = '0' ELSE
strobe_in;
reg_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
soft_reset <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
soft_reset <= strobe_sw;
END IF;
END IF;
END PROCESS reg_process;
reset_internal <= reset OR soft_reset;
wr_enb <= wr_enb_1;
END rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test2 is
port (
d_in: in std_logic_vector(1 downto 0);
d_out: out std_logic_vector(1 downto 0)
);
end entity test2;
architecture rtl of test2 is
constant c : std_logic_vector (7 downto 0) := "10010000";
begin
d_out <= c(to_integer(unsigned(d_in))+1 downto to_integer(unsigned(d_in)));
end rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1926.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n02i01926ent IS
END c07s02b01x00p01n02i01926ent;
ARCHITECTURE c07s02b01x00p01n02i01926arch OF c07s02b01x00p01n02i01926ent IS
BEGIN
TESTING: PROCESS
type A is array ( 1 to 1, 1 to 1 ) of BOOLEAN;
variable A1 : A;
BEGIN
A1 := A'(1=>(1=>TRUE)) and A'(1=>(1=>FALSE)); -- Failure_here
-- SEMANTIC ERROR: "and" not defined for multi-dimensional arrays.
assert FALSE
report "***FAILED TEST: c07s02b01x00p01n02i01926 - Logical operators are not valid for multi-dimensional arrays."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n02i01926arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1926.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n02i01926ent IS
END c07s02b01x00p01n02i01926ent;
ARCHITECTURE c07s02b01x00p01n02i01926arch OF c07s02b01x00p01n02i01926ent IS
BEGIN
TESTING: PROCESS
type A is array ( 1 to 1, 1 to 1 ) of BOOLEAN;
variable A1 : A;
BEGIN
A1 := A'(1=>(1=>TRUE)) and A'(1=>(1=>FALSE)); -- Failure_here
-- SEMANTIC ERROR: "and" not defined for multi-dimensional arrays.
assert FALSE
report "***FAILED TEST: c07s02b01x00p01n02i01926 - Logical operators are not valid for multi-dimensional arrays."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n02i01926arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1926.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n02i01926ent IS
END c07s02b01x00p01n02i01926ent;
ARCHITECTURE c07s02b01x00p01n02i01926arch OF c07s02b01x00p01n02i01926ent IS
BEGIN
TESTING: PROCESS
type A is array ( 1 to 1, 1 to 1 ) of BOOLEAN;
variable A1 : A;
BEGIN
A1 := A'(1=>(1=>TRUE)) and A'(1=>(1=>FALSE)); -- Failure_here
-- SEMANTIC ERROR: "and" not defined for multi-dimensional arrays.
assert FALSE
report "***FAILED TEST: c07s02b01x00p01n02i01926 - Logical operators are not valid for multi-dimensional arrays."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n02i01926arch;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer: Gabbe
--
-- Create Date: 12:04:52 09/17/2014
-- Design Name:
-- Module Name: H:/embedded_labs/comp/tb_comp.vhd
-- Project Name: comp
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: comp
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
ENTITY tb_comp IS
END tb_comp;
ARCHITECTURE behavior OF tb_comp IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT comp
PORT(
clk : IN std_logic;
rstn : IN std_logic;
i_hash_0 : IN unsigned(31 downto 0);
i_hash_1 : IN unsigned(31 downto 0);
i_hash_2 : IN unsigned(31 downto 0);
i_hash_3 : IN unsigned(31 downto 0);
i_cmp_hash : IN std_logic_vector(127 downto 0);
i_start : IN std_logic;
o_equal : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal rstn : std_logic := '1';
signal i_hash_0 : unsigned(31 downto 0) := (others => '0');
signal i_hash_1 : unsigned(31 downto 0) := (others => '0');
signal i_hash_2 : unsigned(31 downto 0) := (others => '0');
signal i_hash_3 : unsigned(31 downto 0) := (others => '0');
signal i_cmp_hash : std_logic_vector(127 downto 0) := (others => '0');
signal i_start : std_logic := '0';
--Outputs
signal o_equal : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: comp PORT MAP (
clk => clk,
rstn => rstn,
i_hash_0 => i_hash_0,
i_hash_1 => i_hash_1,
i_hash_2 => i_hash_2,
i_hash_3 => i_hash_3,
i_cmp_hash => i_cmp_hash,
i_start => i_start,
o_equal => o_res
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for clk_period/2;
rstn <= '0';
wait for clk_period;
rstn <= '1';
i_cmp_hash <= x"13121110232221203332313043424140";
i_start <= '1';
wait for clk_period;
i_start <= '0';
i_hash_0 <= x"10111213";
i_hash_1 <= x"20212223";
i_hash_2 <= x"30313233";
i_hash_3 <= x"40414243";
assert o_equal = '1' report "correct hash compared wrong";
wait for clk_period*4;
i_hash_0 <= x"11111111";
i_hash_1 <= x"11111111";
i_hash_2 <= x"11111111";
i_hash_3 <= x"11111111";
wait for clk_period;
assert o_equal = '0' report "false hash compared wrong";
wait;
end process;
END;
|
entity driver13 is
end entity;
architecture test of driver13 is
constant MAX_NAME_LENGTH : positive := 20;
type t_channel is (NA, ALL_CHANNELS, RX, TX);
type t_record_unresolved is record
trigger : bit;
vvc_name : string(1 to MAX_NAME_LENGTH);
vvc_instance_idx : integer;
vvc_channel : t_channel;
end record;
constant C_VVC_TARGET_RECORD_DEFAULT : t_record_unresolved := (
trigger => '0',
vvc_name => (others => '?'),
vvc_instance_idx => -1,
vvc_channel => NA
); --
type t_record_drivers is array (natural range <> ) of t_record_unresolved;
function resolved ( input : t_record_drivers) return t_record_unresolved;
subtype t_record is resolved t_record_unresolved;
function resolved ( input : t_record_drivers) return t_record_unresolved is
variable v_result : t_record_unresolved := input(input'low);
begin
for i in input'range loop
report to_string(i) & ": trigger=" & to_string(input(i).trigger)
& " vvc_name=" & input(i).vvc_name;
assert input(i).vvc_name(1 to 5) = "hello"
or input(i).vvc_name(1 to 5) = "world"
or input(i).vvc_name(1 to 5) = (1 to 5 => NUL);
end loop;
return v_result;
end resolved;
signal s : t_record;
begin
p1: s <= ('0', ("hello", others => NUL), 1, RX);
p2: s <= ('1', ("world", others => NUL), 2, TX);
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1638.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s12b00x00p05n03i01638ent IS
END c08s12b00x00p05n03i01638ent;
ARCHITECTURE c08s12b00x00p05n03i01638arch OF c08s12b00x00p05n03i01638ent IS
BEGIN
TESTING: PROCESS
function f1(in1:real) return integer is
begin
exit;
end;
variable k : integer := 0;
BEGIN
k := f1(1.2);
assert FALSE
report "***FAILED TEST: c08s12b00x00p05n03i01638 - A function must be completed by a return statement"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s12b00x00p05n03i01638arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1638.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s12b00x00p05n03i01638ent IS
END c08s12b00x00p05n03i01638ent;
ARCHITECTURE c08s12b00x00p05n03i01638arch OF c08s12b00x00p05n03i01638ent IS
BEGIN
TESTING: PROCESS
function f1(in1:real) return integer is
begin
exit;
end;
variable k : integer := 0;
BEGIN
k := f1(1.2);
assert FALSE
report "***FAILED TEST: c08s12b00x00p05n03i01638 - A function must be completed by a return statement"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s12b00x00p05n03i01638arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1638.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s12b00x00p05n03i01638ent IS
END c08s12b00x00p05n03i01638ent;
ARCHITECTURE c08s12b00x00p05n03i01638arch OF c08s12b00x00p05n03i01638ent IS
BEGIN
TESTING: PROCESS
function f1(in1:real) return integer is
begin
exit;
end;
variable k : integer := 0;
BEGIN
k := f1(1.2);
assert FALSE
report "***FAILED TEST: c08s12b00x00p05n03i01638 - A function must be completed by a return statement"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s12b00x00p05n03i01638arch;
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
library uvvm_vvc_framework;
use uvvm_vvc_framework.ti_vvc_framework_support_pkg.all;
use work.vvc_cmd_pkg.all;
package td_target_support_pkg is
signal global_vvc_ack : std_logic; -- ACK on global triggers
signal global_vvc_busy : std_logic := 'L'; -- ACK on global triggers
shared variable protected_multicast_semaphore : t_protected_semaphore;
shared variable protected_acknowledge_index : t_protected_acknowledge_cmd_idx;
type t_vvc_target_record_unresolved is record -- VVC dedicated to assure signature differences between equal common methods
trigger : std_logic;
vvc_name : string(1 to C_VVC_NAME_MAX_LENGTH); -- as scope is vvc_name & ',' and number
vvc_instance_idx : integer;
vvc_channel : t_channel;
end record;
constant C_VVC_TARGET_RECORD_DEFAULT : t_vvc_target_record_unresolved := (
trigger => 'L',
vvc_name => (others => '?'),
vvc_instance_idx => -1,
vvc_channel => NA
); --
type t_vvc_target_record_drivers is array (natural range <> ) of t_vvc_target_record_unresolved;
function resolved ( input_vector : t_vvc_target_record_drivers) return t_vvc_target_record_unresolved;
subtype t_vvc_target_record is resolved t_vvc_target_record_unresolved;
constant C_VVC_INDEX_NOT_FOUND : integer := -1;
-------------------------------------------
-- to_string
-------------------------------------------
-- to_string method for VVC name, instance and channel
-- - If channel is set to NA, it will not be included in the string
function to_string(
value : t_vvc_target_record;
vvc_instance : integer := -1;
vvc_channel : t_channel := NA
) return string;
-------------------------------------------
-- format_command_idx
-------------------------------------------
-- Returns an encapsulated command index as string
impure function format_command_idx(
command : t_vvc_cmd_record -- VVC dedicated
) return string;
-------------------------------------------
-- send_command_to_vvc
-------------------------------------------
-- Sends command to VVC and waits for ACK or timeout
-- - Logs with ID_UVVM_SEND_CMD when sending to VVC
-- - Logs with ID_UVVM_CMD_ACK when ACK or timeout occurs
procedure send_command_to_vvc( -- VVC dedicated shared command used shared_vvc_cmd
signal vvc_target : inout t_vvc_target_record;
constant timeout : in time := std.env.resolution_limit;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel
);
-------------------------------------------
-- set_vvc_target_defaults
-------------------------------------------
-- Returns a vvc target record with vvc_name and values specified in C_VVC_TARGET_RECORD_DEFAULT
function set_vvc_target_defaults (
constant vvc_name : in string;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
) return t_vvc_target_record;
-------------------------------------------
-- set_general_target_and_command_fields
-------------------------------------------
-- Sets target index and channel, and updates shared_vvc_cmd
procedure set_general_target_and_command_fields ( -- VVC dedicated shared command used shared_vvc_cmd
signal target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant proc_call : in string;
constant msg : in string;
constant command_type : in t_immediate_or_queued;
constant operation : in t_operation
);
-------------------------------------------
-- set_general_target_and_command_fields
-------------------------------------------
-- Sets target index and channel, and updates shared_vvc_cmd
procedure set_general_target_and_command_fields ( -- VVC dedicated shared command used shared_vvc_cmd
signal target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant proc_call : in string;
constant msg : in string;
constant command_type : in t_immediate_or_queued;
constant operation : in t_operation
);
-------------------------------------------
-- acknowledge_cmd
-------------------------------------------
-- Drives global_vvc_ack signal (to '1') for 1 delta cycle, then sets it back to 'Z'.
procedure acknowledge_cmd (
signal vvc_ack : inout std_logic;
constant command_idx : in natural
);
--
-- Helper procedure for getting the VVC index in the VVC activity register
-- and the number of instances of this VVC.
--
procedure get_vvc_index_in_activity_register(
signal vvc_target : in t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
variable vvc_idx_in_activity_register : inout t_integer_array(0 to C_MAX_TB_VVC_NUM);
variable num_vvc_instances : inout natural range 0 to C_MAX_TB_VVC_NUM
);
end package td_target_support_pkg;
package body td_target_support_pkg is
function resolved ( input_vector : t_vvc_target_record_drivers) return t_vvc_target_record_unresolved is
-- if none of the drives want to drive the target return value of first driver (which we need to drive at least the target name)
constant C_LINE_LENGTH_MAX : natural := 100; -- VVC idx list string length
variable v_result : t_vvc_target_record_unresolved := input_vector(input_vector'low);
variable v_cnt : integer := 0;
variable v_instance_string : string(1 to C_LINE_LENGTH_MAX) := (others => NUL);
variable v_line : line;
variable v_width : integer := 0;
begin
if input_vector'length = 1 then
return input_vector(input_vector'low);
else
for i in input_vector'range loop
-- The VVC is used if instance_idx is not -1 (which is the default value)
if input_vector(i).vvc_instance_idx /= -1 then
-- count the number of sequencer trying to access the VVC
v_cnt := v_cnt + 1;
v_result := input_vector(i);
-- generating string with all instance_idx for report in case of failure
write(v_line, string'(" "));
write(v_line, input_vector(i).vvc_instance_idx);
-- Ensure there is room for the last item and dots
v_width := v_line'length;
if v_width > (C_LINE_LENGTH_MAX-15) then
write(v_line, string'("..."));
exit;
end if;
end if;
end loop;
if v_width > 0 then
v_instance_string(1 to v_width) := v_line.all;
end if;
deallocate(v_line);
check_value(v_cnt < 2, TB_FAILURE, "Arbitration mechanism failed. Check VVC " & to_string(v_result.vvc_name) & " implementation and semaphore handling. Crashing instances with numbers " & v_instance_string(1 to v_width), "Multiple scopes", ID_NEVER);
return v_result;
end if;
end resolved;
function to_string(
value : t_vvc_target_record;
vvc_instance : integer := -1;
vvc_channel : t_channel:= NA
) return string is
variable v_instance : integer;
variable v_channel : t_channel;
begin
if vvc_instance = -1 then
v_instance := value.vvc_instance_idx;
else
v_instance := vvc_instance;
end if;
if vvc_channel = NA then
v_channel := value.vvc_channel;
else
v_channel := vvc_channel;
end if;
if v_channel = NA then
if vvc_instance = -2 then
return to_string(value.vvc_name) & ",ALL_INSTANCES";
else
return to_string(value.vvc_name) & "," & to_string(v_instance);
end if;
else
if vvc_instance = -2 then
return to_string(value.vvc_name) & ",ALL_INSTANCES" & "," & to_string(v_channel);
else
return to_string(value.vvc_name) & "," & to_string(v_instance) & "," & to_string(v_channel);
end if;
end if;
end;
function set_vvc_target_defaults (
constant vvc_name : in string;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT
) return t_vvc_target_record is
variable v_rec : t_vvc_target_record := C_VVC_TARGET_RECORD_DEFAULT;
begin
if vvc_name'length > C_MAX_VVC_NAME_LENGTH then
alert(TB_FAILURE, "vvc_name is too long. Shorten name or set C_MAX_VVC_NAME_LENGTH in adaptation_pkg to desired length.", scope);
end if;
v_rec.vvc_name := (others => NUL);
v_rec.vvc_name(1 to vvc_name'length) := vvc_name;
return v_rec;
end function;
procedure set_general_target_and_command_fields (
signal target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
constant proc_call : in string;
constant msg : in string;
constant command_type : in t_immediate_or_queued;
constant operation : in t_operation
) is
begin
-- As shared_vvc_cmd is a shared variable we have to get exclusive access to it. Therefor we have to lock the protected_semaphore here.
-- It is unlocked again in await_cmd_from_sequencer after it is copied localy or in send_command_to_vvc if no VVC acknowledges the command.
-- It is guaranteed that no time delay occurs, only delta cycle delay.
await_semaphore_in_delta_cycles(protected_semaphore);
shared_vvc_cmd := C_VVC_CMD_DEFAULT;
target.vvc_instance_idx <= vvc_instance_idx;
target.vvc_channel <= vvc_channel;
shared_vvc_cmd.proc_call := pad_string(proc_call, NUL, shared_vvc_cmd.proc_call'length);
shared_vvc_cmd.msg := (others => NUL); -- default empty
shared_vvc_cmd.msg(1 to msg'length) := msg;
shared_vvc_cmd.command_type := command_type;
shared_vvc_cmd.operation := operation;
-- Wait a delta cycle for target signal values update
wait for 0 ns;
end procedure;
procedure set_general_target_and_command_fields (
signal target : inout t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant proc_call : in string;
constant msg : in string;
constant command_type : in t_immediate_or_queued;
constant operation : in t_operation
) is
begin
set_general_target_and_command_fields(target, vvc_instance_idx, NA, proc_call, msg, command_type, operation);
end procedure;
impure function format_command_idx(
command : t_vvc_cmd_record
) return string is
begin
return format_command_idx(command.cmd_idx);
end;
procedure send_command_to_vvc(
signal vvc_target : inout t_vvc_target_record;
constant timeout : in time := std.env.resolution_limit;
constant scope : in string := C_VVC_CMD_SCOPE_DEFAULT;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel
) is
constant C_CMD_INFO : string := "uvvm cmd " & format_command_idx(shared_cmd_idx+1) & ": ";
variable v_ack_cmd_idx : integer := -1;
variable v_start_time : time;
variable v_local_vvc_cmd : t_vvc_cmd_record;
variable v_local_cmd_idx : integer;
variable v_was_multicast : boolean := false;
variable v_vvc_idx_in_activity_register : t_integer_array(0 to C_MAX_TB_VVC_NUM) := (others => -1);
variable v_num_vvc_instances : natural range 0 to C_MAX_TB_VVC_NUM:= 0;
variable v_vvc_instance_idx : integer := vvc_target.vvc_instance_idx;
variable v_vvc_channel : t_channel := vvc_target.vvc_channel;
begin
check_value((shared_uvvm_state /= IDLE), TB_FAILURE, "UVVM will not work without uvvm_vvc_framework.ti_uvvm_engine instantiated in the test harness", scope, ID_NEVER, msg_id_panel);
-- Default to ALL_INSTANCES and/or ALL_CHANNELS if these are not set in vvc_target
if v_vvc_instance_idx = -1 then
v_vvc_instance_idx := ALL_INSTANCES;
end if;
if v_vvc_channel = NA then
v_vvc_channel := ALL_CHANNELS;
end if;
-- Get the corresponding index from the vvc activity register
get_vvc_index_in_activity_register(vvc_target,
v_vvc_instance_idx,
v_vvc_channel,
v_vvc_idx_in_activity_register,
v_num_vvc_instances);
-- increment shared_cmd_inx. It is protected by the protected_semaphore and only one sequencer can access the variable at a time.
shared_cmd_idx := shared_cmd_idx + 1;
shared_vvc_cmd.cmd_idx := shared_cmd_idx;
if global_show_msg_for_uvvm_cmd then
log(ID_UVVM_SEND_CMD, to_string(shared_vvc_cmd.proc_call) & ": " & add_msg_delimiter(to_string(shared_vvc_cmd.msg)) & "."
& format_command_idx(shared_cmd_idx), scope, msg_id_panel);
else
log(ID_UVVM_SEND_CMD, to_string(shared_vvc_cmd.proc_call)
& format_command_idx(shared_cmd_idx), scope, msg_id_panel);
end if;
wait for 0 ns;
if (vvc_target.vvc_instance_idx = ALL_INSTANCES) then
await_semaphore_in_delta_cycles(protected_multicast_semaphore);
if global_vvc_busy /= 'L' then
wait until global_vvc_busy = 'L';
end if;
v_was_multicast := true;
end if;
v_start_time := now;
-- semaphore "protected_semaphore" gets released after "wait for 0 ns" in await_cmd_from_sequencer
-- Before the semaphore is released copy shared_vvc_cmd to local variable, so that the shared_vvc_cmd can be used by other VVCs.
v_local_vvc_cmd := shared_vvc_cmd;
-- copy the shared_cmd_idx as it can be changed during this function after the semaphore is released
v_local_cmd_idx := shared_cmd_idx;
-- trigger the target -> vvc continues in await_cmd_from_sequencer
vvc_target.trigger <= '1';
wait for 0 ns;
-- the default value of vvc_target drives trigger to 'L' again
vvc_target <= set_vvc_target_defaults(vvc_target.vvc_name, scope);
while v_ack_cmd_idx /= v_local_cmd_idx loop
wait until global_vvc_ack = '1' for ((v_start_time + timeout) - now);
v_ack_cmd_idx := protected_acknowledge_index.get_index;
if not (global_vvc_ack'event) then
tb_error("Time out for " & C_CMD_INFO & " '" & to_string(v_local_vvc_cmd.proc_call) & "' while waiting for acknowledge from VVC", scope);
-- lock the sequencer for 5 delta cycles as it can take so long to get every VVC in normal mode again
wait for 0 ns;
wait for 0 ns;
wait for 0 ns;
wait for 0 ns;
wait for 0 ns;
-- release the semaphore as no VVC can do this
release_semaphore(protected_semaphore);
return;
end if;
end loop;
if (v_was_multicast = true) then
release_semaphore(protected_multicast_semaphore);
end if;
-- VVCs registered in the VVC activity register release semaphore now.
if v_num_vvc_instances > 0 then
release_semaphore(protected_semaphore);
end if;
-- VVCs registered in the VVC activity register release semaphore now.
if v_num_vvc_instances > 0 then
release_semaphore(protected_semaphore);
end if;
log(ID_UVVM_CMD_ACK, "ACK received. " & format_command_idx(v_local_cmd_idx), scope, msg_id_panel);
-- clean up and prepare for next
wait for 0 ns; -- wait for executor to stop driving global_vvc_ack
end procedure;
procedure acknowledge_cmd (
signal vvc_ack : inout std_logic;
constant command_idx : in natural
) is
begin
-- Drive ack signal for 1 delta cycle only one command index can be acknowledged simultaneously.
while(protected_acknowledge_index.set_index(command_idx) = false) loop
-- if it can't set the acknowledge_index wait for one delta cycle and try again
wait for 0 ns;
end loop;
vvc_ack <= '1';
wait until vvc_ack = '1';
vvc_ack <= 'Z';
wait for 0 ns;
protected_acknowledge_index.release_index;
end procedure;
--
-- Helper procedure for getting the VVC index in the VVC activity register
-- and the number of instances of this VVC.
--
procedure get_vvc_index_in_activity_register(
signal vvc_target : in t_vvc_target_record;
constant vvc_instance_idx : in integer;
constant vvc_channel : in t_channel;
variable vvc_idx_in_activity_register : inout t_integer_array(0 to C_MAX_TB_VVC_NUM);
variable num_vvc_instances : inout natural range 0 to C_MAX_TB_VVC_NUM
) is
begin
if vvc_instance_idx = ALL_INSTANCES or vvc_channel = ALL_CHANNELS then
-- Check how many instances or channels of this VVC are registered in the vvc activity register
num_vvc_instances := shared_vvc_activity_register.priv_get_num_registered_vvc_matches(vvc_target.vvc_name,
vvc_instance_idx, vvc_channel);
-- Get the index for every instance or channel of this VVC
for j in 0 to num_vvc_instances-1 loop
vvc_idx_in_activity_register(j) := shared_vvc_activity_register.priv_get_vvc_idx(j, vvc_target.vvc_name,
vvc_instance_idx, vvc_channel);
end loop;
else
-- Get the index for a specific VVC
vvc_idx_in_activity_register(0) := shared_vvc_activity_register.priv_get_vvc_idx(vvc_target.vvc_name,
vvc_instance_idx, vvc_channel);
num_vvc_instances := 0 when vvc_idx_in_activity_register(0) = C_VVC_INDEX_NOT_FOUND else 1;
end if;
end procedure;
end package body td_target_support_pkg;
|
library IEEE;
use IEEE.std_logic_1164.all;
entity contador_vector_tb is
end;
architecture contador_sim of contador_vector_tb is
signal rst_in: std_logic:='1';
signal enable_in: std_logic:='0';
signal clk_in: std_logic:='0';
signal Q_out: std_logic_vector(1 downto 0);
component contador_vector is
port(
rst_c: in std_logic;
clk_c: in std_logic;
enable_c: in std_logic;
Q: out std_logic_vector(1 downto 0)
);
end component;
begin
clk_in <= not clk_in after 20 ns;
enable_in <= '1' after 100 ns;
--enable_in <= not(enable_in)) after 100 ns; //Para probar que funciona el enable
rst_in <= '0' after 50 ns;
ContadorMap: contador_vector port map(
clk_c => clk_in,
rst_c => rst_in,
enable_c => enable_in,
Q => Q_out
);
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
entity contador_vector_tb is
end;
architecture contador_sim of contador_vector_tb is
signal rst_in: std_logic:='1';
signal enable_in: std_logic:='0';
signal clk_in: std_logic:='0';
signal Q_out: std_logic_vector(1 downto 0);
component contador_vector is
port(
rst_c: in std_logic;
clk_c: in std_logic;
enable_c: in std_logic;
Q: out std_logic_vector(1 downto 0)
);
end component;
begin
clk_in <= not clk_in after 20 ns;
enable_in <= '1' after 100 ns;
--enable_in <= not(enable_in)) after 100 ns; //Para probar que funciona el enable
rst_in <= '0' after 50 ns;
ContadorMap: contador_vector port map(
clk_c => clk_in,
rst_c => rst_in,
enable_c => enable_in,
Q => Q_out
);
end architecture;
|
-- Ian Roth
-- ECE 8455
-- control logic, final project
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE work.fixed_pkg.all;
ENTITY Control IS
PORT(
clk, rst :IN STD_LOGIC;
Zoom, ZoomX, ZoomY :IN STD_LOGIC;
x_const, y_const :OUT STD_LOGIC_VECTOR(35 downto 0);
x_addr, y_addr, w_addr :OUT STD_LOGIC_VECTOR(9 downto 0);
WE_const, WE :OUT STD_LOGIC
);
END ENTITY Control;
ARCHITECTURE Behavior OF Control IS
TYPE state_type IS (A,B,C,D,E,F,G);
SIGNAL cur_state :state_type;
SIGNAL x_counter :UNSIGNED(9 downto 0);
SIGNAL y_counter :UNSIGNED(9 downto 0);
SIGNAL w_counter :UNSIGNED(9 downto 0);
SIGNAL pixel_counter :UNSIGNED(19 downto 0);
SIGNAL x_com_min, x_com_max, y_com_min, y_com_max, x_span, y_span :sfixed(3 downto -32);
SIGNAL h_pixel, w_pixel, h_npixel, w_npixel, x_int_const, y_int_const :sfixed(3 downto -32);
SIGNAL iteration_counter :UNSIGNED(15 downto 0);
CONSTANT x_size :sfixed(10 downto 0) := "10000000000"; -- 1024
CONSTANT y_size :sfixed(10 downto 0) := "01100000000"; -- 768
BEGIN
x_const <= STD_LOGIC_VECTOR(x_int_const);
y_const <= STD_LOGIC_VECTOR(y_int_const);
x_addr <= STD_LOGIC_VECTOR(x_counter);
y_addr <= STD_LOGIC_VECTOR(y_counter);
w_addr <= STD_LOGIC_VECTOR(w_counter);
w_npixel <= resize((x_span sra 1) / x_size, w_npixel);
h_npixel <= resize((y_span sra 1) / y_size, h_npixel);
PROCESS(clk, rst)
BEGIN
IF (clk'EVENT and clk = '1') THEN
IF (rst = '1') THEN
x_com_min <= to_sfixed(-2, x_com_min);
x_com_max <= to_sfixed(1, x_com_max);
y_com_min <= to_sfixed(-1, y_com_min);
y_com_max <= to_sfixed(1, y_com_max);
x_int_const <= to_sfixed(-2, x_int_const);
y_int_const <= to_sfixed(1, y_int_const);
w_pixel <= to_sfixed(0.0029296875, w_pixel);
h_pixel <= to_sfixed(0.0026146667, h_pixel);
x_span <= to_sfixed(4, x_span);
y_span <= to_sfixed(2, y_span);
WE_const <= '1';
WE <= '0';
cur_state <= A;
ELSE
CASE cur_state IS
WHEN A =>
x_counter <= "0000000000";
y_counter <= "0000000000";
w_counter <= "0000000000";
pixel_counter <= X"00000";
WE_const <= '1';
WE <= '0';
cur_state <= B;
WHEN B => -- Load first constants for complex x y plane
x_int_const <= resize(x_int_const + w_pixel, x_int_const);
y_int_const <= resize(y_int_const - h_pixel, y_int_const);
w_counter <= w_counter + 1;
WE_const <= '1';
WE <= '0';
cur_state <= C;
WHEN C => -- Start Pipeline, 23 (pipeline length) cycles
x_int_const <= resize(x_int_const + w_pixel, x_int_const);
y_int_const <= resize(y_int_const - h_pixel, y_int_const);
w_counter <= w_counter + 1;
WE_const <= '1';
WE <= '0';
x_counter <= x_counter + 1;
IF (x_counter = 22) THEN
cur_state <= D;
END IF;
WHEN D => -- Write into memory
x_int_const <= resize(x_int_const + w_pixel, x_int_const);
y_int_const <= resize(y_int_const - h_pixel, y_int_const);
w_counter <= w_counter + 1;
WE_const <= '1';
WE <= '1';
x_counter <= x_counter + 1;
pixel_counter <= pixel_counter + 1; -- Actual written pixels
IF (w_counter = 1022) THEN
cur_state <= E;
END IF;
WHEN E => -- Stop constants
WE_const <= '0';
WE <= '1';
x_counter <= x_counter + 1;
pixel_counter <= pixel_counter + 1; -- Actual written pixels
IF (x_counter = 1023) THEN
y_counter <= y_counter + 1;
ELSE
y_counter <= y_counter;
END IF;
IF (pixel_counter = X"BFFFF") THEN
cur_state <= F;
END IF;
WHEN F => -- Stop writing to memory
WE_const <= '0';
WE <= '0';
IF (Zoom = '0') THEN
IF (ZoomX = '0') THEN -- Zoom in on right
x_com_min <= resize(x_com_min + (x_span sra 1), x_com_min);
ELSE
x_com_max <= resize(x_com_max - (x_span sra 1), x_com_max);
END IF;
IF (ZoomY = '0') THEN -- Zoom in on top
y_com_min <= resize(y_com_min + (y_span sra 1), x_com_min);
ELSE
y_com_max <= resize(y_com_max - (y_span sra 1), x_com_max);
END IF;
w_pixel <= w_npixel;
h_pixel <= h_npixel;
x_span <= x_span sra 1;
y_span <= y_span sra 1;
cur_state <= G;
END IF;
WHEN G =>
x_int_const <= x_com_min;
y_int_const <= y_com_max;
IF (Zoom = '1') THEN
cur_state <= A;
END IF;
END CASE;
END IF;
END IF;
END PROCESS;
END Behavior; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity PWM is
generic(
MAX_VAL : integer := 256;
CLOCK_DIVIDER : integer := 256
);
port(
CLK : in std_logic;
DATA : in std_logic_vector(31 downto 0);
DATA_STB : in std_logic;
DATA_ACK : out std_logic;
OUT_BIT : out std_logic
);
end entity PWM;
architecture RTL of PWM is
signal TIMER : integer range 0 to CLOCK_DIVIDER - 1 := CLOCK_DIVIDER - 1;
signal COUNT : integer range 0 to MAX_VAL - 1 := 0;
signal PWM_VAL : integer range 0 to MAX_VAL := 0;
begin
DATA_ACK <= '1';
process
begin
wait until rising_edge(CLK);
if DATA_STB = '1' then
PWM_VAL <= to_integer(unsigned(DATA));
end if;
if TIMER = 0 then
if COUNT = MAX_VAL - 1 then
COUNT <= 0;
else
COUNT <= COUNT + 1;
end if;
TIMER <= CLOCK_DIVIDER-1;
else
TIMER <= TIMER-1;
end if;
if COUNT >= PWM_VAL then
OUT_BIT <= '0';
else
OUT_BIT <= '1';
end if;
end process;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity PWM is
generic(
MAX_VAL : integer := 256;
CLOCK_DIVIDER : integer := 256
);
port(
CLK : in std_logic;
DATA : in std_logic_vector(31 downto 0);
DATA_STB : in std_logic;
DATA_ACK : out std_logic;
OUT_BIT : out std_logic
);
end entity PWM;
architecture RTL of PWM is
signal TIMER : integer range 0 to CLOCK_DIVIDER - 1 := CLOCK_DIVIDER - 1;
signal COUNT : integer range 0 to MAX_VAL - 1 := 0;
signal PWM_VAL : integer range 0 to MAX_VAL := 0;
begin
DATA_ACK <= '1';
process
begin
wait until rising_edge(CLK);
if DATA_STB = '1' then
PWM_VAL <= to_integer(unsigned(DATA));
end if;
if TIMER = 0 then
if COUNT = MAX_VAL - 1 then
COUNT <= 0;
else
COUNT <= COUNT + 1;
end if;
TIMER <= CLOCK_DIVIDER-1;
else
TIMER <= TIMER-1;
end if;
if COUNT >= PWM_VAL then
OUT_BIT <= '0';
else
OUT_BIT <= '1';
end if;
end process;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity PWM is
generic(
MAX_VAL : integer := 256;
CLOCK_DIVIDER : integer := 256
);
port(
CLK : in std_logic;
DATA : in std_logic_vector(31 downto 0);
DATA_STB : in std_logic;
DATA_ACK : out std_logic;
OUT_BIT : out std_logic
);
end entity PWM;
architecture RTL of PWM is
signal TIMER : integer range 0 to CLOCK_DIVIDER - 1 := CLOCK_DIVIDER - 1;
signal COUNT : integer range 0 to MAX_VAL - 1 := 0;
signal PWM_VAL : integer range 0 to MAX_VAL := 0;
begin
DATA_ACK <= '1';
process
begin
wait until rising_edge(CLK);
if DATA_STB = '1' then
PWM_VAL <= to_integer(unsigned(DATA));
end if;
if TIMER = 0 then
if COUNT = MAX_VAL - 1 then
COUNT <= 0;
else
COUNT <= COUNT + 1;
end if;
TIMER <= CLOCK_DIVIDER-1;
else
TIMER <= TIMER-1;
end if;
if COUNT >= PWM_VAL then
OUT_BIT <= '0';
else
OUT_BIT <= '1';
end if;
end process;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity PWM is
generic(
MAX_VAL : integer := 256;
CLOCK_DIVIDER : integer := 256
);
port(
CLK : in std_logic;
DATA : in std_logic_vector(31 downto 0);
DATA_STB : in std_logic;
DATA_ACK : out std_logic;
OUT_BIT : out std_logic
);
end entity PWM;
architecture RTL of PWM is
signal TIMER : integer range 0 to CLOCK_DIVIDER - 1 := CLOCK_DIVIDER - 1;
signal COUNT : integer range 0 to MAX_VAL - 1 := 0;
signal PWM_VAL : integer range 0 to MAX_VAL := 0;
begin
DATA_ACK <= '1';
process
begin
wait until rising_edge(CLK);
if DATA_STB = '1' then
PWM_VAL <= to_integer(unsigned(DATA));
end if;
if TIMER = 0 then
if COUNT = MAX_VAL - 1 then
COUNT <= 0;
else
COUNT <= COUNT + 1;
end if;
TIMER <= CLOCK_DIVIDER-1;
else
TIMER <= TIMER-1;
end if;
if COUNT >= PWM_VAL then
OUT_BIT <= '0';
else
OUT_BIT <= '1';
end if;
end process;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity PWM is
generic(
MAX_VAL : integer := 256;
CLOCK_DIVIDER : integer := 256
);
port(
CLK : in std_logic;
DATA : in std_logic_vector(31 downto 0);
DATA_STB : in std_logic;
DATA_ACK : out std_logic;
OUT_BIT : out std_logic
);
end entity PWM;
architecture RTL of PWM is
signal TIMER : integer range 0 to CLOCK_DIVIDER - 1 := CLOCK_DIVIDER - 1;
signal COUNT : integer range 0 to MAX_VAL - 1 := 0;
signal PWM_VAL : integer range 0 to MAX_VAL := 0;
begin
DATA_ACK <= '1';
process
begin
wait until rising_edge(CLK);
if DATA_STB = '1' then
PWM_VAL <= to_integer(unsigned(DATA));
end if;
if TIMER = 0 then
if COUNT = MAX_VAL - 1 then
COUNT <= 0;
else
COUNT <= COUNT + 1;
end if;
TIMER <= CLOCK_DIVIDER-1;
else
TIMER <= TIMER-1;
end if;
if COUNT >= PWM_VAL then
OUT_BIT <= '0';
else
OUT_BIT <= '1';
end if;
end process;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity PWM is
generic(
MAX_VAL : integer := 256;
CLOCK_DIVIDER : integer := 256
);
port(
CLK : in std_logic;
DATA : in std_logic_vector(31 downto 0);
DATA_STB : in std_logic;
DATA_ACK : out std_logic;
OUT_BIT : out std_logic
);
end entity PWM;
architecture RTL of PWM is
signal TIMER : integer range 0 to CLOCK_DIVIDER - 1 := CLOCK_DIVIDER - 1;
signal COUNT : integer range 0 to MAX_VAL - 1 := 0;
signal PWM_VAL : integer range 0 to MAX_VAL := 0;
begin
DATA_ACK <= '1';
process
begin
wait until rising_edge(CLK);
if DATA_STB = '1' then
PWM_VAL <= to_integer(unsigned(DATA));
end if;
if TIMER = 0 then
if COUNT = MAX_VAL - 1 then
COUNT <= 0;
else
COUNT <= COUNT + 1;
end if;
TIMER <= CLOCK_DIVIDER-1;
else
TIMER <= TIMER-1;
end if;
if COUNT >= PWM_VAL then
OUT_BIT <= '0';
else
OUT_BIT <= '1';
end if;
end process;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity PWM is
generic(
MAX_VAL : integer := 256;
CLOCK_DIVIDER : integer := 256
);
port(
CLK : in std_logic;
DATA : in std_logic_vector(31 downto 0);
DATA_STB : in std_logic;
DATA_ACK : out std_logic;
OUT_BIT : out std_logic
);
end entity PWM;
architecture RTL of PWM is
signal TIMER : integer range 0 to CLOCK_DIVIDER - 1 := CLOCK_DIVIDER - 1;
signal COUNT : integer range 0 to MAX_VAL - 1 := 0;
signal PWM_VAL : integer range 0 to MAX_VAL := 0;
begin
DATA_ACK <= '1';
process
begin
wait until rising_edge(CLK);
if DATA_STB = '1' then
PWM_VAL <= to_integer(unsigned(DATA));
end if;
if TIMER = 0 then
if COUNT = MAX_VAL - 1 then
COUNT <= 0;
else
COUNT <= COUNT + 1;
end if;
TIMER <= CLOCK_DIVIDER-1;
else
TIMER <= TIMER-1;
end if;
if COUNT >= PWM_VAL then
OUT_BIT <= '0';
else
OUT_BIT <= '1';
end if;
end process;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity PWM is
generic(
MAX_VAL : integer := 256;
CLOCK_DIVIDER : integer := 256
);
port(
CLK : in std_logic;
DATA : in std_logic_vector(31 downto 0);
DATA_STB : in std_logic;
DATA_ACK : out std_logic;
OUT_BIT : out std_logic
);
end entity PWM;
architecture RTL of PWM is
signal TIMER : integer range 0 to CLOCK_DIVIDER - 1 := CLOCK_DIVIDER - 1;
signal COUNT : integer range 0 to MAX_VAL - 1 := 0;
signal PWM_VAL : integer range 0 to MAX_VAL := 0;
begin
DATA_ACK <= '1';
process
begin
wait until rising_edge(CLK);
if DATA_STB = '1' then
PWM_VAL <= to_integer(unsigned(DATA));
end if;
if TIMER = 0 then
if COUNT = MAX_VAL - 1 then
COUNT <= 0;
else
COUNT <= COUNT + 1;
end if;
TIMER <= CLOCK_DIVIDER-1;
else
TIMER <= TIMER-1;
end if;
if COUNT >= PWM_VAL then
OUT_BIT <= '0';
else
OUT_BIT <= '1';
end if;
end process;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity PWM is
generic(
MAX_VAL : integer := 256;
CLOCK_DIVIDER : integer := 256
);
port(
CLK : in std_logic;
DATA : in std_logic_vector(31 downto 0);
DATA_STB : in std_logic;
DATA_ACK : out std_logic;
OUT_BIT : out std_logic
);
end entity PWM;
architecture RTL of PWM is
signal TIMER : integer range 0 to CLOCK_DIVIDER - 1 := CLOCK_DIVIDER - 1;
signal COUNT : integer range 0 to MAX_VAL - 1 := 0;
signal PWM_VAL : integer range 0 to MAX_VAL := 0;
begin
DATA_ACK <= '1';
process
begin
wait until rising_edge(CLK);
if DATA_STB = '1' then
PWM_VAL <= to_integer(unsigned(DATA));
end if;
if TIMER = 0 then
if COUNT = MAX_VAL - 1 then
COUNT <= 0;
else
COUNT <= COUNT + 1;
end if;
TIMER <= CLOCK_DIVIDER-1;
else
TIMER <= TIMER-1;
end if;
if COUNT >= PWM_VAL then
OUT_BIT <= '0';
else
OUT_BIT <= '1';
end if;
end process;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity PWM is
generic(
MAX_VAL : integer := 256;
CLOCK_DIVIDER : integer := 256
);
port(
CLK : in std_logic;
DATA : in std_logic_vector(31 downto 0);
DATA_STB : in std_logic;
DATA_ACK : out std_logic;
OUT_BIT : out std_logic
);
end entity PWM;
architecture RTL of PWM is
signal TIMER : integer range 0 to CLOCK_DIVIDER - 1 := CLOCK_DIVIDER - 1;
signal COUNT : integer range 0 to MAX_VAL - 1 := 0;
signal PWM_VAL : integer range 0 to MAX_VAL := 0;
begin
DATA_ACK <= '1';
process
begin
wait until rising_edge(CLK);
if DATA_STB = '1' then
PWM_VAL <= to_integer(unsigned(DATA));
end if;
if TIMER = 0 then
if COUNT = MAX_VAL - 1 then
COUNT <= 0;
else
COUNT <= COUNT + 1;
end if;
TIMER <= CLOCK_DIVIDER-1;
else
TIMER <= TIMER-1;
end if;
if COUNT >= PWM_VAL then
OUT_BIT <= '0';
else
OUT_BIT <= '1';
end if;
end process;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity PWM is
generic(
MAX_VAL : integer := 256;
CLOCK_DIVIDER : integer := 256
);
port(
CLK : in std_logic;
DATA : in std_logic_vector(31 downto 0);
DATA_STB : in std_logic;
DATA_ACK : out std_logic;
OUT_BIT : out std_logic
);
end entity PWM;
architecture RTL of PWM is
signal TIMER : integer range 0 to CLOCK_DIVIDER - 1 := CLOCK_DIVIDER - 1;
signal COUNT : integer range 0 to MAX_VAL - 1 := 0;
signal PWM_VAL : integer range 0 to MAX_VAL := 0;
begin
DATA_ACK <= '1';
process
begin
wait until rising_edge(CLK);
if DATA_STB = '1' then
PWM_VAL <= to_integer(unsigned(DATA));
end if;
if TIMER = 0 then
if COUNT = MAX_VAL - 1 then
COUNT <= 0;
else
COUNT <= COUNT + 1;
end if;
TIMER <= CLOCK_DIVIDER-1;
else
TIMER <= TIMER-1;
end if;
if COUNT >= PWM_VAL then
OUT_BIT <= '0';
else
OUT_BIT <= '1';
end if;
end process;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity PWM is
generic(
MAX_VAL : integer := 256;
CLOCK_DIVIDER : integer := 256
);
port(
CLK : in std_logic;
DATA : in std_logic_vector(31 downto 0);
DATA_STB : in std_logic;
DATA_ACK : out std_logic;
OUT_BIT : out std_logic
);
end entity PWM;
architecture RTL of PWM is
signal TIMER : integer range 0 to CLOCK_DIVIDER - 1 := CLOCK_DIVIDER - 1;
signal COUNT : integer range 0 to MAX_VAL - 1 := 0;
signal PWM_VAL : integer range 0 to MAX_VAL := 0;
begin
DATA_ACK <= '1';
process
begin
wait until rising_edge(CLK);
if DATA_STB = '1' then
PWM_VAL <= to_integer(unsigned(DATA));
end if;
if TIMER = 0 then
if COUNT = MAX_VAL - 1 then
COUNT <= 0;
else
COUNT <= COUNT + 1;
end if;
TIMER <= CLOCK_DIVIDER-1;
else
TIMER <= TIMER-1;
end if;
if COUNT >= PWM_VAL then
OUT_BIT <= '0';
else
OUT_BIT <= '1';
end if;
end process;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity PWM is
generic(
MAX_VAL : integer := 256;
CLOCK_DIVIDER : integer := 256
);
port(
CLK : in std_logic;
DATA : in std_logic_vector(31 downto 0);
DATA_STB : in std_logic;
DATA_ACK : out std_logic;
OUT_BIT : out std_logic
);
end entity PWM;
architecture RTL of PWM is
signal TIMER : integer range 0 to CLOCK_DIVIDER - 1 := CLOCK_DIVIDER - 1;
signal COUNT : integer range 0 to MAX_VAL - 1 := 0;
signal PWM_VAL : integer range 0 to MAX_VAL := 0;
begin
DATA_ACK <= '1';
process
begin
wait until rising_edge(CLK);
if DATA_STB = '1' then
PWM_VAL <= to_integer(unsigned(DATA));
end if;
if TIMER = 0 then
if COUNT = MAX_VAL - 1 then
COUNT <= 0;
else
COUNT <= COUNT + 1;
end if;
TIMER <= CLOCK_DIVIDER-1;
else
TIMER <= TIMER-1;
end if;
if COUNT >= PWM_VAL then
OUT_BIT <= '0';
else
OUT_BIT <= '1';
end if;
end process;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity PWM is
generic(
MAX_VAL : integer := 256;
CLOCK_DIVIDER : integer := 256
);
port(
CLK : in std_logic;
DATA : in std_logic_vector(31 downto 0);
DATA_STB : in std_logic;
DATA_ACK : out std_logic;
OUT_BIT : out std_logic
);
end entity PWM;
architecture RTL of PWM is
signal TIMER : integer range 0 to CLOCK_DIVIDER - 1 := CLOCK_DIVIDER - 1;
signal COUNT : integer range 0 to MAX_VAL - 1 := 0;
signal PWM_VAL : integer range 0 to MAX_VAL := 0;
begin
DATA_ACK <= '1';
process
begin
wait until rising_edge(CLK);
if DATA_STB = '1' then
PWM_VAL <= to_integer(unsigned(DATA));
end if;
if TIMER = 0 then
if COUNT = MAX_VAL - 1 then
COUNT <= 0;
else
COUNT <= COUNT + 1;
end if;
TIMER <= CLOCK_DIVIDER-1;
else
TIMER <= TIMER-1;
end if;
if COUNT >= PWM_VAL then
OUT_BIT <= '0';
else
OUT_BIT <= '1';
end if;
end process;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity PWM is
generic(
MAX_VAL : integer := 256;
CLOCK_DIVIDER : integer := 256
);
port(
CLK : in std_logic;
DATA : in std_logic_vector(31 downto 0);
DATA_STB : in std_logic;
DATA_ACK : out std_logic;
OUT_BIT : out std_logic
);
end entity PWM;
architecture RTL of PWM is
signal TIMER : integer range 0 to CLOCK_DIVIDER - 1 := CLOCK_DIVIDER - 1;
signal COUNT : integer range 0 to MAX_VAL - 1 := 0;
signal PWM_VAL : integer range 0 to MAX_VAL := 0;
begin
DATA_ACK <= '1';
process
begin
wait until rising_edge(CLK);
if DATA_STB = '1' then
PWM_VAL <= to_integer(unsigned(DATA));
end if;
if TIMER = 0 then
if COUNT = MAX_VAL - 1 then
COUNT <= 0;
else
COUNT <= COUNT + 1;
end if;
TIMER <= CLOCK_DIVIDER-1;
else
TIMER <= TIMER-1;
end if;
if COUNT >= PWM_VAL then
OUT_BIT <= '0';
else
OUT_BIT <= '1';
end if;
end process;
end architecture RTL;
|
-------------------------------------------------------------------------------
--
-- File: Protocol_Engine.vhd
-- Author: Gherman Tudor
-- Original Project: USB Device IP on 7-series Xilinx FPGA
-- Date: 2 May 2016
--
-------------------------------------------------------------------------------
-- (c) 2016 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module instantiates all the necessary modules to implement ULPI
-- communication, Speed negotiation , Reset and Suspend. Packet data is
-- sent/received over AXI Stream. Synchronization modules for registers
-- that corss the ULPI Clock domain to AXI clock domain is implemented
-- here
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity Protocol_Engine is
generic (
MAX_NR_ENDP : integer := 1
);
Port (
Axi_Clk : IN std_logic;
Axi_Resetn : IN STD_LOGIC;
Ulpi_Clk : in STD_LOGIC;
u_ResetN : in STD_LOGIC;
--ULPI Bus
Ulpi_Reset : out STD_LOGIC;
u_Ulpi_Data : INOUT std_logic_vector(7 downto 0);
u_Ulpi_Dir : IN std_logic;
u_Ulpi_Nxt : IN std_logic;
u_Ulpi_Stp : OUT std_logic;
led : out STD_LOGIC; --debug purposes
--Transmit FIFO write channel
a_Arb_Endpt_Nr : in std_logic_vector(4 downto 0);
Tx_Fifo_S_Aresetn : IN STD_LOGIC;
a_Tx_Fifo_S_Aclk : IN STD_LOGIC;
a_Tx_Fifo_S_Axis_Tvalid : IN STD_LOGIC;
a_Tx_Fifo_S_Axis_Tready : OUT STD_LOGIC;
a_Tx_Fifo_S_Axis_Tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
a_Tx_Fifo_S_Axis_Tlast : IN STD_LOGIC;
a_Tx_Fifo_S_Axis_Tkeep : IN std_logic_vector(3 downto 0);
a_Tx_Fifo_S_Axis_Tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
tx_fifo_axis_overflow : OUT STD_LOGIC;
tx_fifo_axis_underflow : OUT STD_LOGIC;
--Receive FIFO write channel
u_Rx_Fifo_s_Aclk : OUT std_logic;
u_Rx_Fifo_s_Axis_Tready : IN std_logic;
u_Rx_Fifo_s_Axis_Tvalid : OUT std_logic;
u_Rx_Fifo_s_Axis_Tdata : OUT std_logic_vector(31 downto 0);
u_Rx_Fifo_s_Axis_Tkeep : OUT std_logic_vector (3 downto 0);
u_Rx_Fifo_s_Axis_Tlast : OUT std_logic;
u_Rx_Fifo_Axis_Overflow : IN std_logic;
u_Rx_Fifo_Axis_Underflow : IN std_logic;
--Command FIFO; used to keep track of received OUT transactions
u_Command_Fifo_Rd_En : IN std_logic;
u_Command_Fifo_Dout : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
u_Command_Fifo_Empty : OUT std_logic;
u_Command_Fifo_Valid : OUT std_logic;
--control signals to/from DMA_Transfer_Manager
a_In_Packet_Complete_oData : OUT std_logic_vector(31 downto 0); --a bit is set when the corresponding endpoint has completed an IN transaction
a_In_Packet_Complete_Set_En : OUT std_logic; --a_In_Packet_Complete_oData strobe
u_Send_Zero_Length_Packet_Rd : IN STD_LOGIC_VECTOR(31 downto 0); --If a bit is set, the corresponding endpoint needs to send a Zero Length Packet
a_Send_Zero_Length_Packet_Clear_oData : OUT STD_LOGIC_VECTOR(31 downto 0); --ZLP Hanshake between Packet_Decoder and DMA_Transfer_Manager
a_Send_Zero_Length_Packet_Clear_En : OUT STD_LOGIC; --ZLP Hanshake between Packet_Decoder and DMA_Transfer_Manager
a_Send_Zero_Length_Packet_Ack_oData : OUT STD_LOGIC_VECTOR(31 downto 0); --ZLP Hanshake between Packet_Decoder and DMA_Transfer_Manager
a_Send_Zero_Length_Packet_Ack_Set_En : OUT STD_LOGIC; --ZLP Hanshake between Packet_Decoder and DMA_Transfer_Manager
a_Cnt_Bytes_Sent_oData : out std_logic_vector(12 downto 0); --number of bytes sent in response to an IN token
a_Cnt_Bytes_Sent_oValid : OUT std_logic; -- a_Cnt_Bytes_Sent_oData strobe
a_Resend_oData : OUT STD_LOGIC_VECTOR(31 downto 0); --indicates to the upper layers that the endpoint corresponding to set bits need to resend a packet
a_Resend_Wr_En : OUT std_logic; --a_Resend_oData
a_In_Token_Received_oData : OUT std_logic_vector(31 downto 0); -- a bit is set when the corresponding endpoint has received an IN token
a_In_Token_Received_Set_En : OUT std_logic; --a_In_Token_Received_oData strobe
a_Endpt_Nr : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); --endpoint accessed by the lower layers (ULPI, Packet_Decoder)
u_Endp_Nr : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
u_Endp_Nr_Arb : IN STD_LOGIC_VECTOR(4 DOWNTO 0); --endpoint accessed by the DMA_Transfer_Manager
u_Endp_Nr_Arb_Ack : OUT std_logic;
u_Endp_Nr_Arb_Valid : IN std_logic;
--Setup packets are stored in these registers before being copied into the dQH
a_Setup_Buffer_Bytes_3_0_oData : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
a_Setup_Buffer_Bytes_7_4_oData : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--Interface to Control_Registers block
u_Endp_Type : in STD_LOGIC_VECTOR(47 downto 0);
u_Endp_Stall : IN STD_LOGIC_VECTOR(23 downto 0);
u_USBADRA : in STD_LOGIC_VECTOR (7 downto 0);
a_FRINDEX_oData : out std_logic_vector(10 downto 0);
a_FRINDEX_Wr_En : out std_logic;
a_PORTSC1_PSPD_oData : out std_logic_vector(1 downto 0);
a_PORTSC1_PSPD_Wr_En : out std_logic;
a_ENDPTNAK_oData : out std_logic_vector(31 downto 0);
a_ENDPTNAK_Wr_En : out std_logic;
a_ENDPTSETUP_RECEIVED_oData : out std_logic_vector(31 downto 0);
a_ENDPTSETUP_RECEIVED_Wr_En : out std_logic;
a_USBSTS_NAKI_oData : out std_logic;
a_USBSTS_NAKI_Wr_En : out std_logic;
a_USBSTS_SLI_oData : out std_logic;
a_USBSTS_SLI_Wr_En : out std_logic;
a_USBSTS_SRI_oData : out std_logic;
a_USBSTS_SRI_Wr_En : out std_logic;
a_USBSTS_URI_oData : out std_logic;
a_USBSTS_URI_Wr_En : out std_logic;
a_USBSTS_PCI_oData : out std_logic;
a_USBSTS_PCI_Wr_En : out std_logic;
u_USBCMD_RS : in std_logic;
state_ind : out STD_LOGIC_VECTOR(5 downto 0);
state_ind_pd : out STD_LOGIC_VECTOR(6 downto 0);
state_ind_hs : out STD_LOGIC_VECTOR(4 downto 0)
);
end Protocol_Engine;
architecture Behavioral of Protocol_Engine is
COMPONENT ULPI
PORT(
Ulpi_Clk : IN std_logic;
reset : IN std_logic;
u_Ulpi_Data : INOUT std_logic_vector(7 downto 0);
u_Ulpi_Dir : IN std_logic;
u_Ulpi_Nxt : IN std_logic;
u_Ulpi_Stp : OUT std_logic;
u_Ulpi_Reset : OUT std_logic;
u_Send_NOOP_CMD : IN std_logic;
u_Send_NOPID_CMD : IN std_logic;
u_Send_PID_CMD : IN std_logic;
u_Send_EXTW_CMD : IN std_logic;
u_Send_REGW_CMD : IN std_logic;
u_Send_EXTR_CMD : IN std_logic;
u_Send_REGR_CMD : IN std_logic;
u_Send_STP_CMD : IN std_logic;
u_Send_Last : IN std_logic;
u_Send_Err : IN std_logic;
u_Tx_Data : IN std_logic_vector(7 downto 0);
u_Tx_Data_En : OUT std_logic;
u_Tx_Pid : IN std_logic_vector(3 downto 0);
u_Tx_Regw_Data : in STD_LOGIC_VECTOR (7 downto 0);
u_Tx_Reg_Addr : in STD_LOGIC_VECTOR (7 downto 0);
u_Tx_Cmd_Done : OUT STD_LOGIC;
u_USB_Mode : IN std_logic;
u_CRC16_En : out STD_LOGIC;
u_Tx_Pid_Phase_Done : out STD_LOGIC;
u_Rx_Data : OUT std_logic_vector(7 downto 0);
u_Rx_Packet_Received : OUT std_logic;
u_Ulpi_Dir_Out : out STD_LOGIC;
u_LineState : OUT std_logic_vector(1 downto 0);
u_Vbus : OUT std_logic_vector(1 downto 0);
u_RxEvent : OUT std_logic_vector(1 downto 0);
u_RxActive : out STD_LOGIC;
u_ID : OUT std_logic;
u_Alt_Int : OUT std_logic;
u_Rx_Cmd_Received : OUT std_logic;
state_ind : out STD_LOGIC_VECTOR(5 downto 0);
u_Rx_Register_Data : OUT std_logic_vector(7 downto 0);
u_Rx_Register_Data_Received : OUT std_logic
);
END COMPONENT;
COMPONENT HS_Negotiation
PORT(
u_Reset : IN std_logic;
Ulpi_Clk : IN std_logic;
u_Remote_Wake : IN std_logic;
u_LineState : IN std_logic_vector(1 downto 0);
u_Vbus : IN std_logic_vector(1 downto 0);
u_Rx_Cmd_Received : IN std_logic;
u_Send_NOPID_CMD : OUT std_logic;
u_Send_EXTW_CMD : OUT std_logic;
u_Send_REGW_CMD : OUT std_logic;
u_Send_EXTR_CMD : OUT std_logic;
u_Send_REGR_CMD : OUT std_logic;
u_Send_STP_CMD : OUT std_logic;
u_Send_Last : OUT std_logic;
u_Tx_Data : OUT std_logic_vector(7 downto 0);
u_Tx_Regw_Data : OUT STD_LOGIC_VECTOR (7 downto 0);
u_Tx_Cmd_Done : IN STD_LOGIC;
u_Tx_Reg_Addr : OUT STD_LOGIC_VECTOR (7 downto 0);
u_USB_Mode : OUT std_logic;
u_Not_Connected : OUT std_logic;
u_Set_Mode_HS : OUT std_logic;
u_Set_Mode_FS : OUT std_logic;
u_Wake : OUT std_logic;
u_USBCMD_RS : in std_logic;
state_ind_hs : out STD_LOGIC_VECTOR(4 downto 0);
u_Negociation_Done : out STD_LOGIC
);
END COMPONENT;
COMPONENT Packet_Decoder
PORT(
Ulpi_Clk : in STD_LOGIC;
reset : in STD_LOGIC;
Axi_Clk : IN std_logic;
Axi_Resetn : IN STD_LOGIC;
a_Arb_Endpt_Nr : in std_logic_vector(4 downto 0);
Tx_Fifo_S_Aresetn : IN STD_LOGIC;
a_Tx_Fifo_S_Aclk : IN STD_LOGIC;
a_Tx_Fifo_S_Axis_Tvalid : IN STD_LOGIC;
a_Tx_Fifo_S_Axis_Tready : OUT STD_LOGIC;
a_Tx_Fifo_S_Axis_Tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
a_Tx_Fifo_S_Axis_Tlast : IN STD_LOGIC;
a_Tx_Fifo_S_Axis_Tkeep : IN std_logic_vector(3 downto 0);
a_Tx_Fifo_S_Axis_Tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
tx_fifo_axis_overflow : OUT STD_LOGIC;
tx_fifo_axis_underflow : OUT STD_LOGIC;
--RX FIFO (write)
u_Rx_Fifo_s_Aclk : OUT std_logic;
u_Rx_Fifo_s_Axis_Tready : IN std_logic;
u_Rx_Fifo_s_Axis_Tvalid : OUT std_logic;
u_Rx_Fifo_s_Axis_Tdata : OUT std_logic_vector(31 downto 0);
u_Rx_Fifo_s_Axis_Tkeep : OUT std_logic_vector (3 downto 0);
u_Rx_Fifo_s_Axis_Tlast : OUT std_logic;
u_Rx_Fifo_Axis_Overflow : IN std_logic;
u_Rx_Fifo_Axis_Underflow : IN std_logic;
u_Command_Fifo_Rd_En : IN std_logic;
u_Command_Fifo_Dout : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
u_Command_Fifo_Empty : OUT std_logic;
u_Command_Fifo_Valid : OUT std_logic;
u_Setup_Buffer_Bytes_3_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
u_Setup_Buffer_Bytes_7_4 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
u_Send_PID_CMD : out STD_LOGIC;
u_Send_Last : out STD_LOGIC;
u_Tx_Data : out STD_LOGIC_VECTOR (7 downto 0);
u_Tx_Data_En : in STD_LOGIC;
u_Tx_Pid : out STD_LOGIC_VECTOR (3 downto 0);
u_Tx_Cmd_Done : in STD_LOGIC;
u_Tx_Pid_Phase_Done : in STD_LOGIC;
u_CRC16_En_Ulpi : in STD_LOGIC;
u_RxEvent : in STD_LOGIC_VECTOR(1 downto 0);
u_RxActive : in STD_LOGIC;
u_Rx_Packet_Received : in STD_LOGIC;
u_Ulpi_Dir_Out : in STD_LOGIC;
u_Rx_Data : in STD_LOGIC_VECTOR(7 downto 0);
u_USB_Mode : in STD_LOGIC;
u_Setup_Received : OUT std_logic;
u_Setup_Received_Rst : IN std_logic;
u_In_Token_Received : OUT std_logic;
u_In_Packet_Complete : OUT std_logic;
u_In_Packet_Complete_Rst : IN std_logic;
u_iPush_Endpt_Nr_PD : OUT STD_LOGIC;
-- endp_enable : IN STD_LOGIC(11 downto 0);
u_Send_Zero_Length_Packet : in STD_LOGIC;
u_Send_Zero_Length_Packet_Ack_Set : OUT STD_LOGIC;
u_Send_Zero_Length_Packet_Clear : OUT STD_LOGIC;
u_NAK_Sent : out STD_LOGIC;
u_Frame_Index : out STD_LOGIC_VECTOR (10 downto 0);
u_SOF_received : out STD_LOGIC;
u_Cnt_Bytes_Sent : out std_logic_vector(12 downto 0);
u_Cnt_Bytes_Sent_Latch : out STD_LOGIC;
u_Resend_Set : out STD_LOGIC;
u_Endp_Nr : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
u_Endp_Stall : IN STD_LOGIC;
u_Endp_Type : in STD_LOGIC_VECTOR(1 downto 0);
u_USBADRA : in STD_LOGIC_VECTOR (7 downto 0);
axis_32_to_8_latency_comp_out_port : out STD_LOGIC;
ulpi_latency_comp_out : in STD_LOGIC;
state_ind_pd : out STD_LOGIC_VECTOR(6 downto 0);
packet_err : out STD_LOGIC
);
END COMPONENT;
COMPONENT SyncBase
Generic (
kResetTo : std_logic := '0'; --value when reset and upon init
kStages : natural := 2); --double sync by default
PORT(
aReset : IN std_logic;
InClk : IN std_logic;
iIn : IN std_logic;
OutClk : IN std_logic;
oOut : OUT std_logic
);
END COMPONENT;
type state_type is (IDLE, SEND_ZERO_LENGTH_STATE, RESET_SETUP_RECEIVED);
signal state, next_state : state_type;
type PACKET_IN_BYTE_COUNT is array (11 downto 0) of std_logic_vector(12 downto 0);
signal u_Cnt_Bytes_Sent_Array : PACKET_IN_BYTE_COUNT;
signal reset : STD_LOGIC;
signal not_reset : STD_LOGIC;
signal not_axi_resetn : STD_LOGIC;
signal u_Send_NOPID_CMD : STD_LOGIC;
signal u_Send_PID_CMD : STD_LOGIC;
signal u_Send_EXTW_CMD : STD_LOGIC;
signal u_Send_REGW_CMD : STD_LOGIC;
signal u_Send_EXTR_CMD : STD_LOGIC;
signal u_Send_REGR_CMD : STD_LOGIC;
signal u_Send_STP_CMD : STD_LOGIC;
signal u_Send_Last : STD_LOGIC;
signal u_Send_Last_HSNegociation : STD_LOGIC;
signal u_Send_Last_PD : STD_LOGIC;
signal u_Tx_Pid : STD_LOGIC_VECTOR(3 downto 0);
signal u_Tx_Data : STD_LOGIC_VECTOR(7 downto 0);
signal u_Tx_Regw_Data : STD_LOGIC_VECTOR(7 downto 0);
signal u_Tx_Cmd_Done : STD_LOGIC;
signal u_Tx_Reg_Addr : STD_LOGIC_VECTOR(7 downto 0);
signal u_Tx_Data_HSNegociation : STD_LOGIC_VECTOR(7 downto 0);
signal u_Tx_Data_PD : STD_LOGIC_VECTOR(7 downto 0);
signal u_Tx_Data_En : STD_LOGIC;
signal u_Tx_Pid_Phase_Done : STD_LOGIC;
signal u_CRC16_En : STD_LOGIC;
signal u_Rx_Data : STD_LOGIC_VECTOR(7 downto 0);
signal u_Rx_Cmd_Received : STD_LOGIC;
signal u_RxEvent : STD_LOGIC_VECTOR(1 downto 0);
signal u_RxActive : STD_LOGIC;
signal u_Rx_Register_Data : STD_LOGIC_VECTOR(7 downto 0);
signal u_Rx_Register_Data_Received : STD_LOGIC;
signal u_Rx_Packet_Received : STD_LOGIC;
signal u_LineState : STD_LOGIC_VECTOR(1 downto 0);
signal u_Vbus : STD_LOGIC_VECTOR(1 downto 0);
signal u_Ulpi_Dir_Out : STD_LOGIC;
signal u_ID : STD_LOGIC;
signal u_Alt_Int : STD_LOGIC;
signal u_Negociation_Done : STD_LOGIC;
signal u_USB_Mode : STD_LOGIC;
signal packet_err : STD_LOGIC;
type u_Cnt_Bytes_Sent_iData_Array is array (MAX_NR_ENDP downto 0) of std_logic_vector(12 downto 0);
signal u_Cnt_Bytes_Sent_iData : u_Cnt_Bytes_Sent_iData_Array;
type a_Cnt_Bytes_Sent_oData_Array is array (MAX_NR_ENDP downto 0) of std_logic_vector(12 downto 0);
signal a_Cnt_Bytes_Sent_oData_Loc : a_Cnt_Bytes_Sent_oData_Array;
type u_Cnt_Bytes_Sent_iPush_Array is array (MAX_NR_ENDP downto 0) of std_logic;
signal u_Cnt_Bytes_Sent_iPush : u_Cnt_Bytes_Sent_iPush_Array;
type u_Cnt_Bytes_Sent_iRdy_Array is array (MAX_NR_ENDP downto 0) of std_logic;
signal u_Cnt_Bytes_Sent_iRdy : u_Cnt_Bytes_Sent_iRdy_Array;
type a_Cnt_Bytes_Sent_oValid_Array is array (MAX_NR_ENDP downto 0) of std_logic;
signal a_Cnt_Bytes_Sent_oValid_Loc : a_Cnt_Bytes_Sent_oValid_Array;
signal u_Cnt_Bytes_Sent : STD_LOGIC_VECTOR(12 downto 0);
signal u_Cnt_Bytes_Sent_Latch, u_Cnt_Bytes_Sent_Latch_q : STD_LOGIC;
signal u_ENDPTNAK_iData : std_logic_vector(31 downto 0);
signal a_ENDPTNAK_oValid : STD_LOGIC;
signal a_ENDPTNAK_Wr_En_q : STD_LOGIC;
signal u_ENDPTNAK_iPush : STD_LOGIC;
signal u_ENDPTNAK_iRdy : STD_LOGIC;
signal u_ENDPTSETUPSTAT_iData : std_logic_vector(31 downto 0);
signal a_ENDPTSETUPSTAT_Wr_En_q : std_logic;
signal u_ENDPTSETUPSTAT_iPush : STD_LOGIC;
signal u_ENDPTSETUPSTAT_iRdy : STD_LOGIC;
signal a_ENDPTSETUPSTAT_oValid : STD_LOGIC;
signal u_Setup_Received : STD_LOGIC;
signal u_Setup_Received_Rst : STD_LOGIC;
signal a_ENDPTSETUP_RECEIVED_Wr_En_qq, a_ENDPTSETUP_RECEIVED_Wr_En_q, a_ENDPTSETUP_RECEIVED_Wr_En_Loc : STD_LOGIC;
signal ENDPTSETUPSTAT_Hanshake_Rst, a_ENDPTSETUPSTAT_Hanshake_Rst : STD_LOGIC;
signal u_In_Packet_Complete_iData : std_logic_vector (31 downto 0);
signal u_In_Packet_Complete_iPush : std_logic;
signal u_In_Packet_Complete_iRdy : std_logic;
signal a_In_Packet_Complete_Set_En_q, a_In_Packet_Complete_Set_En_qq : std_logic;
signal a_Packet_In_Complete_Hanshake_Rst, Packet_In_Complete_Hanshake_Rst : std_logic;
signal a_In_Packet_Complete_Set_En_Loc : std_logic;
signal a_In_Packet_Complete_Wr_En_q : std_logic;
signal a_In_Packet_In_Complete_oValid : STD_LOGIC;
signal u_In_Packet_Complete : STD_LOGIC;
signal u_In_Packet_Complete_Rst : STD_LOGIC;
signal u_FRINDEX_iData : std_logic_vector(10 downto 0);
signal a_FRINDEX_Wr_En_q : std_logic;
signal a_FRINDEX_oValid : STD_LOGIC;
signal u_FRINDEX_iPush : STD_LOGIC;
signal u_FRINDEX_iRdy : STD_LOGIC;
signal u_SOF_Received : STD_LOGIC;
signal u_Frame_Index : STD_LOGIC_VECTOR(10 downto 0);
signal u_In_Token_Received : std_logic;
signal u_In_Token_Received_iData : std_logic_vector(31 downto 0);
signal a_In_Token_Received_Set_En_q, a_In_Token_Received_Set_En_qq, a_In_Token_Received_Set_En_Loc : STD_LOGIC;
signal u_In_Token_Received_iPush : STD_LOGIC;
signal u_In_Token_Received_iRdy : STD_LOGIC;
signal a_In_Token_Received_oValid : STD_LOGIC;
signal a_In_Token_Received_Hanshake_Rst, In_Token_Received_Hanshake_Rst : STD_LOGIC;
signal u_Send_Zero_Length_Packet_Clear_iData : std_logic_vector(31 downto 0);
signal u_Send_Zero_Length_Packet_Clear : std_logic;
signal u_Send_Zero_Length_Packet_Clear_iPush : std_logic;
signal u_Send_Zero_Length_Packet_Clear_iRdy : std_logic;
signal a_Send_Zero_Length_Packet_Clear_oValid : std_logic;
signal a_Send_Zero_Length_Packet_Clear_En_q, a_Send_Zero_Length_Packet_Clear_En_qq : std_logic;
signal a_Send_Zero_Length_Packet_Clear_En_Loc : std_logic;
signal Send_Zero_Length_Packet_Clear_Hanshake_Rst, a_Send_Zero_Length_Packet_Clear_Hanshake_Rst : std_logic;
signal u_Send_Zero_Length_Packet_Ack_iData, u_Send_Zero_Length_Packet_Ack_iData_q : std_logic_vector(31 downto 0);
signal u_Send_Zero_Length_Packet_Ack_iRdy : std_logic;
signal u_Send_Zero_Length_Packet_Ack_Set : STD_LOGIC;
signal u_Send_Zero_Length_Packet_Ack_iPush : std_logic;
signal a_Send_Zero_Length_Packet_Ack_oValid : STD_LOGIC;
signal a_Send_Zero_Length_Packet_Ack_Set_En_q, a_Send_Zero_Length_Packet_Ack_Set_En_qq : std_logic;
signal u_Send_Zero_Length_Packet : STD_LOGIC;
signal a_Send_Zero_Length_Packet_Ack_Set_En_Loc : std_logic;
signal a_Send_Zero_Length_Packet_Ack_Set_Hanshake_Rst, Send_Zero_Length_Packet_Ack_Set_Hanshake_Rst : std_logic;
signal u_Setup_Buffer_Bytes_3_0_iData : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal u_Setup_Buffer_Bytes_3_0_q : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal u_Setup_Buffer_Bytes_3_0_iPush : STD_LOGIC;
signal u_Setup_Buffer_Bytes_3_0_iRdy : STD_LOGIC;
signal a_Setup_Buffer_Bytes_3_0_oValid : STD_LOGIC;
signal u_Setup_Buffer_Bytes_7_4_iData : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal u_Setup_Buffer_Bytes_7_4_q : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal u_Setup_Buffer_Bytes_7_4_iPush : STD_LOGIC;
signal u_Setup_Buffer_Bytes_7_4_iRdy : STD_LOGIC;
signal a_Setup_Buffer_Bytes_7_4_oValid : STD_LOGIC;
signal u_NAK_Sent : STD_LOGIC;
signal u_USBSTS_NAKI_iData : std_logic_vector(0 downto 0);
signal a_USBSTS_NAKI_Wr_En_q : std_logic;
signal u_USBSTS_NAKI_iPush : std_logic;
signal u_USBSTS_NAKI_iRdy : std_logic;
signal a_USBSTS_NAKI_oValid : std_logic;
signal a_USBSTS_NAKI_Vector : STD_LOGIC_VECTOR(0 downto 0);
signal u_USBSTS_SLI_iData : std_logic_vector(0 downto 0);
signal u_USBSTS_SLI_iPush : std_logic;
signal u_USBSTS_SLI_iRdy : std_logic;
signal a_USBSTS_SLI_oValid : std_logic;
signal a_USBSTS_SLI_Vector : STD_LOGIC_VECTOR(0 downto 0);
signal a_USBSTS_SLI_Wr_En_q : std_logic;
signal u_Suspend_State, u_Suspend_State_q, u_Set_Suspend_State : STD_LOGIC;
signal u_Clear_Suspend_State, u_Set_Clear_Suspend_State, u_Set_Clear_Suspend_State_q : STD_LOGIC;
signal u_USBSTS_SRI_iData : std_logic_vector(0 downto 0);
signal u_USBSTS_SRI_iPush : std_logic;
signal u_USBSTS_SRI_iRdy : std_logic;
signal a_USBSTS_SRI_oValid : std_logic;
signal a_USBSTS_SRI_Vector : STD_LOGIC_VECTOR(0 downto 0);
signal a_USBSTS_SRI_Wr_En_q : std_logic;
signal u_USBSTS_URI_iData : std_logic_vector(0 downto 0);
signal u_USBSTS_URI_iPush : std_logic;
signal u_USBSTS_URI_iRdy : std_logic;
signal a_USBSTS_URI_oValid : std_logic;
signal a_USBSTS_URI_Vector : STD_LOGIC_VECTOR(0 downto 0);
signal a_USBSTS_URI_Wr_En_q : std_logic;
signal u_Reset_Received_Ulpi_q, u_Reset_Received, u_Reset_Received_Ulpi : STD_LOGIC;
signal u_USBSTS_PCI_iData : std_logic_vector(0 downto 0);
signal u_USBSTS_PCI_iPush : STD_LOGIC;
signal u_USBSTS_PCI_iRdy: STD_LOGIC;
signal a_USBSTS_PCI_oValid: STD_LOGIC;
signal a_USBSTS_PCI_Vector : STD_LOGIC_VECTOR(0 downto 0);
signal a_USBSTS_PCI_Wr_En_q : std_logic;
signal u_Port_Change_Detect : STD_LOGIC;
signal u_Wake : STD_LOGIC;
signal u_Set_Mode_FS : STD_LOGIC;
signal u_Set_Mode_HS : STD_LOGIC;
signal u_PORTSC1_iData : std_logic_vector(1 downto 0);
signal u_PORTSC1_iPush : STD_LOGIC;
signal u_PORTSC1_iRdy : STD_LOGIC;
signal a_PORTSC1_oValid : STD_LOGIC;
signal a_PORTSC1_PSPD_Wr_En_q : STD_LOGIC;
signal u_Not_Connected : STD_LOGIC;
signal u_Not_Connected_Pulse : STD_LOGIC;
signal u_Not_Connected_q : STD_LOGIC;
signal u_Resend_Set : STD_LOGIC;
signal u_Resend_iData : std_logic_vector (31 downto 0);
signal u_Resend_iPush : std_logic;
signal u_Resend_iRdy : std_logic;
signal a_Resend_Wr_En_q : std_logic;
signal a_Resend_oValid : STD_LOGIC;
signal u_Endpt_Nr_Loc : STD_LOGIC_VECTOR(4 downto 0);
signal u_iPush_Endpt_Nr, u_iPush_Endpt_Nr_PD, u_Endpt_Nr_oValid, u_Endpt_Nr_iRdy : STD_LOGIC;
signal pe_endpt_nr_int_4msb : integer range 0 to 12;
signal pe_endpt_nr_int : integer range 0 to 21;
signal pe_endpt_nr_index : integer range 0 to 27;
signal arb_endpt_nr_int_4msb : integer range 0 to 22;
signal a_Arb_Endpt_Nr_Int_4msb : integer range 0 to 22;
signal u_Arb_Endpt_Nr_Loc, a_Arb_Endpt_Nr_Loc: STD_LOGIC_VECTOR(4 downto 0);
signal u_Endp_Stall_PD : STD_LOGIC;
signal u_Endp_Type_PD : STD_LOGIC_VECTOR(1 downto 0);
signal state_ind_hs_loc : STD_LOGIC_VECTOR(4 downto 0);
signal ulpi_latency_comp_in, ulpi_latency_comp_out : STD_LOGIC;
-- attribute mark_debug : string;
-- attribute keep : string;
-- attribute mark_debug of u_Send_Zero_Length_Packet_Ack_iPush : signal is "true";
-- attribute keep of u_Send_Zero_Length_Packet_Ack_iPush : signal is "true";
--attribute mark_debug of u_In_Packet_Complete_iData : signal is "true";
--attribute keep of u_In_Packet_Complete_iData : signal is "true";
--attribute mark_debug of u_In_Packet_Complete_iPush : signal is "true";
--attribute keep of u_In_Packet_Complete_iPush : signal is "true";
--attribute mark_debug of u_In_Packet_Complete_iRdy : signal is "true";
--attribute keep of u_In_Packet_Complete_iRdy : signal is "true";
--attribute mark_debug of a_In_Packet_Complete_oData : signal is "true";
--attribute keep of a_In_Packet_Complete_oData : signal is "true";
--attribute mark_debug of a_In_Packet_Complete_Set_En : signal is "true";
--attribute keep of a_In_Packet_Complete_Set_En : signal is "true";
--attribute mark_debug of u_ENDPTSETUPSTAT_iData : signal is "true";
--attribute keep of u_ENDPTSETUPSTAT_iData : signal is "true";
--attribute mark_debug of a_ENDPTSETUP_RECEIVED_oData : signal is "true";
--attribute keep of a_ENDPTSETUP_RECEIVED_oData : signal is "true";
--attribute mark_debug of u_ENDPTSETUPSTAT_iPush : signal is "true";
--attribute keep of u_ENDPTSETUPSTAT_iPush : signal is "true";
--attribute mark_debug of ENDPTSETUPSTAT_Hanshake_Rst : signal is "true";
--attribute keep of ENDPTSETUPSTAT_Hanshake_Rst : signal is "true";
--attribute mark_debug of u_In_Token_Received_iData : signal is "true";
--attribute keep of u_In_Token_Received_iData : signal is "true";
--attribute mark_debug of u_In_Token_Received_iPush : signal is "true";
--attribute keep of u_In_Token_Received_iPush : signal is "true";
--attribute mark_debug of a_In_Token_Received_oValid : signal is "true";
--attribute keep of a_In_Token_Received_oValid : signal is "true";
--attribute mark_debug of a_In_Token_Received_oData : signal is "true";
--attribute keep of a_In_Token_Received_oData : signal is "true";
--attribute mark_debug of In_Token_Received_Hanshake_Rst : signal is "true";
--attribute keep of In_Token_Received_Hanshake_Rst : signal is "true";
--attribute mark_debug of u_Cnt_Bytes_Sent_iPush : signal is "true";
--attribute keep of u_Cnt_Bytes_Sent_iPush : signal is "true";
--attribute mark_debug of a_Cnt_Bytes_Sent_oData_Loc : signal is "true";
--attribute keep of a_Cnt_Bytes_Sent_oData_Loc : signal is "true";
begin
u_Endp_Nr <= u_Endpt_Nr_Loc;
not_reset <= not (reset);
reset <= u_ResetN;
not_axi_resetn <= not (axi_resetn);
u_Arb_Endpt_Nr_Loc <= u_Endp_Nr_Arb;
a_Arb_Endpt_Nr_Loc <= a_Arb_Endpt_Nr;
state_ind_hs <= state_ind_hs_loc;
led <= '1';
--Transmit data MUX. During speed negotiation HS_Negotiation controls the ULPI bus.
--Once negotiation is done, the Packet_Decoder controls the ULPI bus
u_Tx_Data <= u_Tx_Data_PD when u_Negociation_Done = '1'
else u_Tx_Data_HSNegociation;--reg_data;--
u_Send_Last <= u_Send_Last_PD when u_Negociation_Done = '1'
else u_Send_Last_HSNegociation;
-- This module handles ULPI transmissions (NOPID, PID, EXTW, REGW, EXTR, REGR)
-- and reception
Inst_ULPI: ULPI PORT MAP(
u_Ulpi_Data => u_Ulpi_Data,
Ulpi_Clk => Ulpi_Clk,
reset => reset,
u_Ulpi_Dir => u_Ulpi_Dir,
u_Ulpi_Nxt => u_Ulpi_Nxt,
u_Ulpi_Stp => u_Ulpi_Stp,
u_Ulpi_Reset => Ulpi_Reset,
u_Send_NOOP_CMD => '0',
u_Send_NOPID_CMD => u_Send_NOPID_CMD,
u_Send_PID_CMD => u_Send_PID_CMD,
u_Send_EXTW_CMD => u_Send_EXTW_CMD,
u_Send_REGW_CMD => u_Send_REGW_CMD,
u_Send_EXTR_CMD => u_Send_EXTR_CMD,
u_Send_REGR_CMD => u_Send_REGR_CMD,
u_Send_STP_CMD => u_Send_STP_CMD,
u_Send_Last => u_Send_Last,
u_Send_Err => '0',
u_Tx_Data => u_Tx_Data,
u_Tx_Data_En => u_Tx_Data_En,
u_Tx_Pid => u_Tx_Pid,
u_Tx_Regw_Data => u_Tx_Regw_Data,
u_Tx_Reg_Addr => u_Tx_Reg_Addr,
u_Tx_Cmd_Done => u_Tx_Cmd_Done,
u_CRC16_En => u_CRC16_En,
u_Tx_Pid_Phase_Done => u_Tx_Pid_Phase_Done,
u_Rx_Data => u_Rx_Data,
u_Rx_Packet_Received => u_Rx_Packet_Received,
u_Ulpi_Dir_Out => u_Ulpi_Dir_Out,
u_LineState => u_LineState,
u_Vbus => u_Vbus,
u_RxEvent => u_RxEvent,
u_RxActive => u_RxActive,
u_ID => u_ID,
u_Alt_Int => u_Alt_Int,
u_Rx_Cmd_Received => u_Rx_Cmd_Received,
state_ind => state_ind,
u_Rx_Register_Data => u_Rx_Register_Data,
u_Rx_Register_Data_Received => u_Rx_Register_Data_Received,
u_USB_Mode => u_USB_Mode
);
-- This module handles the USB speed negociatian, reset and suspend protocols
Inst_HS_Negotiation: HS_Negotiation PORT MAP(
u_Reset => reset,
Ulpi_Clk => Ulpi_Clk,
u_Send_NOPID_CMD => u_Send_NOPID_CMD,
u_Send_EXTW_CMD => u_Send_EXTW_CMD,
u_Send_REGW_CMD => u_Send_REGW_CMD,
u_Send_EXTR_CMD => u_Send_EXTR_CMD,
u_Send_REGR_CMD => u_Send_REGR_CMD,
u_Send_STP_CMD => u_Send_STP_CMD,
u_Send_Last => u_Send_Last_HSNegociation,
u_Remote_Wake => '0',
u_Rx_Cmd_Received => u_Rx_Cmd_Received,
u_LineState => u_LineState,
u_Vbus => u_Vbus,
u_Tx_Data => u_Tx_Data_HSNegociation,
u_Tx_Regw_Data => u_Tx_Regw_Data,
u_Tx_Cmd_Done => u_Tx_Cmd_Done,
u_Tx_Reg_Addr => u_Tx_Reg_Addr,
u_USB_Mode => u_USB_Mode,
u_Not_Connected => u_Not_Connected,
u_Set_Mode_HS => u_Set_Mode_HS,
u_Set_Mode_FS => u_Set_Mode_FS,
u_Wake => u_Wake,
u_USBCMD_RS => u_USBCMD_RS,
state_ind_hs => state_ind_hs_loc,
u_Negociation_Done => u_Negociation_Done
);
u_Endp_Stall_PD <= u_Endp_Stall(pe_endpt_nr_int);
u_Endp_Type_PD <= u_Endp_Type((pe_endpt_nr_int*2) + 1 downto pe_endpt_nr_int*2);
u_Send_Zero_Length_Packet <= u_Send_Zero_Length_Packet_Rd(pe_endpt_nr_index);
-- This module implements chapter 8 of the USB protocol
Inst_Packet_Decoder: Packet_Decoder PORT MAP(
Ulpi_Clk => Ulpi_Clk,
Axi_Clk => Axi_Clk,
reset => reset,
Axi_Resetn => Axi_Resetn,
a_Arb_Endpt_Nr => a_Arb_Endpt_Nr,
Tx_Fifo_S_Aresetn => Tx_Fifo_S_Aresetn,
a_Tx_Fifo_S_Aclk => a_Tx_Fifo_S_Aclk,
a_Tx_Fifo_S_Axis_Tvalid => a_Tx_Fifo_S_Axis_Tvalid,
a_Tx_Fifo_S_Axis_Tready => a_Tx_Fifo_S_Axis_Tready,
a_Tx_Fifo_S_Axis_Tdata => a_Tx_Fifo_S_Axis_Tdata,
a_Tx_Fifo_S_Axis_Tlast => a_Tx_Fifo_S_Axis_Tlast,
a_Tx_Fifo_S_Axis_Tkeep => a_Tx_Fifo_S_Axis_Tkeep,
a_Tx_Fifo_S_Axis_Tuser => a_Tx_Fifo_S_Axis_Tuser,
tx_fifo_axis_overflow => tx_fifo_axis_overflow,
tx_fifo_axis_underflow => tx_fifo_axis_underflow,
u_Rx_Fifo_s_Aclk => u_Rx_Fifo_s_Aclk,
u_Rx_Fifo_s_Axis_Tready => u_Rx_Fifo_s_Axis_Tready,
u_Rx_Fifo_s_Axis_Tvalid => u_Rx_Fifo_s_Axis_Tvalid,
u_Rx_Fifo_s_Axis_Tdata => u_Rx_Fifo_s_Axis_Tdata,
u_Rx_Fifo_s_Axis_Tkeep => u_Rx_Fifo_s_Axis_Tkeep,
u_Rx_Fifo_s_Axis_Tlast => u_Rx_Fifo_s_Axis_Tlast,
u_Rx_Fifo_Axis_Overflow => u_Rx_Fifo_Axis_Overflow,
u_Rx_Fifo_Axis_Underflow => u_Rx_Fifo_Axis_Underflow,
u_Command_Fifo_Rd_En => u_Command_Fifo_Rd_En,
u_Command_Fifo_Dout => u_Command_Fifo_Dout,
u_Command_Fifo_Empty => u_Command_Fifo_Empty,
u_Command_Fifo_Valid => u_Command_Fifo_Valid,
u_Setup_Buffer_Bytes_3_0 => u_Setup_Buffer_Bytes_3_0_iData,
u_Setup_Buffer_Bytes_7_4 => u_Setup_Buffer_Bytes_7_4_iData,
u_Send_PID_CMD => u_Send_PID_CMD,
u_Send_Last => u_Send_Last_PD,
u_Tx_Data => u_Tx_Data_PD,
u_Tx_Data_En => u_Tx_Data_En,
u_Tx_Pid => u_Tx_Pid,
u_Tx_Cmd_Done => u_Tx_Cmd_Done,
u_Tx_Pid_Phase_Done => u_Tx_Pid_Phase_Done,
u_CRC16_En_Ulpi => u_CRC16_En,
u_Rx_Data => u_Rx_Data,
u_Rx_Packet_Received => u_Rx_Packet_Received,
u_Ulpi_Dir_Out => u_Ulpi_Dir_Out,
u_RxEvent => u_RxEvent,
u_RxActive => u_RxActive,
u_USB_Mode => u_USB_Mode,
u_Setup_Received => u_Setup_Received,
u_Setup_Received_Rst => u_Setup_Received_Rst,
u_In_Token_Received => u_In_Token_Received,
u_In_Packet_Complete => u_In_Packet_Complete,
u_In_Packet_Complete_Rst => u_In_Packet_Complete_Rst,
u_Cnt_Bytes_Sent_Latch => u_Cnt_Bytes_Sent_Latch,
u_Cnt_Bytes_Sent => u_Cnt_Bytes_Sent,
u_Resend_Set => u_Resend_Set,
u_Endp_Nr => u_Endpt_Nr_Loc,
u_iPush_Endpt_Nr_PD => u_iPush_Endpt_Nr_PD,
u_Send_Zero_Length_Packet_Clear => u_Send_Zero_Length_Packet_Clear,
u_Send_Zero_Length_Packet => u_Send_Zero_Length_Packet,
u_Send_Zero_Length_Packet_Ack_Set => u_Send_Zero_Length_Packet_Ack_Set,
u_NAK_Sent => u_NAK_Sent,
u_Frame_Index => u_Frame_Index,
u_SOF_Received => u_SOF_Received,
u_USBADRA => u_USBADRA,
u_Endp_Type => u_Endp_Type_PD,
u_Endp_Stall => u_Endp_Stall_PD,
ulpi_latency_comp_out => ulpi_latency_comp_out,
state_ind_pd => state_ind_pd,
packet_err =>packet_err
);
--Synchronization modules for data that crosses the ULPI clock domain to AXI clock domain
u_iPush_Endpt_Nr <= u_iPush_Endpt_Nr_PD when (u_Endpt_Nr_iRdy = '1') else '0';
Inst_HandshakeData_pe_endpt_nr: entity work.HandshakeData
GENERIC MAP (
kDataWidth => 5)
PORT MAP(
InClk => Ulpi_Clk,
OutClk => Axi_Clk,
iData => u_Endpt_Nr_Loc,
oData => a_Endpt_Nr ,
iPush => u_iPush_Endpt_Nr,
iRdy => u_Endpt_Nr_iRdy,
oAck => u_Endpt_Nr_oValid,
oValid => u_Endpt_Nr_oValid,
aReset => not_axi_resetn
);
--------------------------------------------------------------------------------------------
pe_endpt_nr_int_4msb <= to_integer(unsigned(u_Endpt_Nr_Loc(4 downto 1)));
pe_endpt_nr_int <= to_integer(unsigned(u_Endpt_Nr_Loc));
arb_endpt_nr_int_4msb <= to_integer(unsigned(u_Arb_Endpt_Nr_Loc(4 downto 1)));
a_Arb_Endpt_Nr_Int_4msb <= to_integer(unsigned(a_Arb_Endpt_Nr_Loc(4 downto 1)));
DEFINE_INDEX_PROC: process (reset, u_Endpt_Nr_Loc, pe_endpt_nr_int_4msb)
begin
if (reset = '0') then
pe_endpt_nr_index <= 0;
else
if (u_Endpt_Nr_Loc(0) = '0') then
pe_endpt_nr_index <= pe_endpt_nr_int_4msb;
else
pe_endpt_nr_index <= pe_endpt_nr_int_4msb + 16;
end if;
end if;
end process;
MULTIPLE_HANDSHAKE : for i in 0 to MAX_NR_ENDP generate
Inst_HandshakeData_Count: entity work.HandshakeData
GENERIC MAP (
kDataWidth => 13)
PORT MAP(
InClk => Ulpi_Clk,
OutClk => Axi_Clk,
iData => u_Cnt_Bytes_Sent_iData(i),
oData => a_Cnt_Bytes_Sent_oData_Loc(i),
iPush => u_Cnt_Bytes_Sent_iPush(i),
iRdy => u_Cnt_Bytes_Sent_iRdy(i),
oAck => a_Cnt_Bytes_Sent_oValid_Loc(i),
oValid => a_Cnt_Bytes_Sent_oValid_Loc(i),
aReset => not_axi_resetn
);
end generate;
IN_PACKET_COUNTER_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Cnt_Bytes_Sent_iData <= (others => (others => '0'));
else
if (u_Cnt_Bytes_Sent_Latch = '1') then
u_Cnt_Bytes_Sent_iData(pe_endpt_nr_int_4msb) <= u_Cnt_Bytes_Sent;
end if;
end if;
end if;
end process;
IPUSH_COUNTER_PROC : process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Cnt_Bytes_Sent_iPush <= (others => '0');
u_Cnt_Bytes_Sent_Latch_q <= '0';
else
u_Cnt_Bytes_Sent_Latch_q <= u_Cnt_Bytes_Sent_Latch;
if ((u_Cnt_Bytes_Sent_Latch_q = '1') and (u_Cnt_Bytes_Sent_iRdy(pe_endpt_nr_int_4msb) = '1'))then
u_Cnt_Bytes_Sent_iPush(pe_endpt_nr_int_4msb) <= '1';
else
u_Cnt_Bytes_Sent_iPush(pe_endpt_nr_int_4msb) <= '0';
end if;
end if;
end if;
end process;
IN_TRANSF_CNT_OVALID_PROC : process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (axi_resetn = '0') then
a_Cnt_Bytes_Sent_oValid <= '0';
else
a_Cnt_Bytes_Sent_oValid <= a_Cnt_Bytes_Sent_oValid_Loc(a_Arb_Endpt_Nr_Int_4msb);
end if;
end if;
end process;
IN_TRANSF_CNT_ODATA_PROC : process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (axi_resetn = '0') then
a_Cnt_Bytes_Sent_oData <= (others => '0');
else
if (a_Cnt_Bytes_Sent_oValid_Loc(a_Arb_Endpt_Nr_Int_4msb) = '1') then
a_Cnt_Bytes_Sent_oData <= a_Cnt_Bytes_Sent_oData_Loc(a_Arb_Endpt_Nr_Int_4msb);
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------------
NAK_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_ENDPTNAK_iData <= (others => '0');
u_ENDPTNAK_iPush <= '0';
else
if (u_NAK_Sent = '1' and u_ENDPTNAK_iRdy = '1') then
u_ENDPTNAK_iData(pe_endpt_nr_index) <= '1';
u_ENDPTNAK_iPush <= '1';
else
u_ENDPTNAK_iData <= (others => '0');
u_ENDPTNAK_iPush <= '0';
end if;
end if;
end if;
end process;
ENDPTNAK_wr_en_PROC : process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (axi_resetn = '0') then
a_ENDPTNAK_Wr_En <= '0';
a_ENDPTNAK_Wr_En_q <= '0';
else
a_ENDPTNAK_Wr_En_q <= a_ENDPTNAK_oValid;
a_ENDPTNAK_Wr_En <= a_ENDPTNAK_oValid and (not a_ENDPTNAK_Wr_En_q);
end if;
end if;
end process;
Inst_HandshakeData_ENDPTNAK : entity work.HandshakeData
GENERIC MAP (
kDataWidth => 32)
PORT MAP(
InClk => Ulpi_Clk,
OutClk => Axi_Clk,
iData => u_ENDPTNAK_iData,
oData => a_ENDPTNAK_oData,
iPush => u_ENDPTNAK_iPush,
iRdy => u_ENDPTNAK_iRdy,
oAck => a_ENDPTNAK_oValid,
oValid => a_ENDPTNAK_oValid,
aReset => not_axi_resetn
);
-----------------------------------------------------------------------------------------------
ENDPTSETUPSTAT_PROC : process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Setup_Received_Rst <= '0';
u_ENDPTSETUPSTAT_iData <= (others => '0');
u_ENDPTSETUPSTAT_iPush <= '0';
else
if (u_Setup_Received = '1' and u_ENDPTSETUPSTAT_iRdy = '1') then
u_ENDPTSETUPSTAT_iData(pe_endpt_nr_index) <= '1';
u_ENDPTSETUPSTAT_iPush <= '1';
u_Setup_Received_Rst <= '0';
else
u_ENDPTSETUPSTAT_iData <= (others => '0');
u_Setup_Received_Rst <= '1';
u_ENDPTSETUPSTAT_iPush <= '0';
end if;
end if;
end if;
end process;
ENDPTSETUPSTAT_wr_en_PROC : process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (axi_resetn = '0') then
a_ENDPTSETUP_RECEIVED_Wr_En_Loc <= '0';
a_ENDPTSETUPSTAT_Wr_En_q <= '0';
a_ENDPTSETUP_RECEIVED_Wr_En_qq <= '0';
a_ENDPTSETUPSTAT_Hanshake_Rst <= '0';
a_ENDPTSETUP_RECEIVED_Wr_En_q <= '0';
else
a_ENDPTSETUPSTAT_Wr_En_q <= a_ENDPTSETUPSTAT_oValid;
a_ENDPTSETUP_RECEIVED_Wr_En_Loc <= a_ENDPTSETUPSTAT_oValid and (not a_ENDPTSETUPSTAT_Wr_En_q);
a_ENDPTSETUP_RECEIVED_Wr_En_q <= a_ENDPTSETUP_RECEIVED_Wr_En_Loc;
a_ENDPTSETUP_RECEIVED_Wr_En_qq <= a_ENDPTSETUP_RECEIVED_Wr_En_q;
a_ENDPTSETUPSTAT_Hanshake_Rst <= a_ENDPTSETUP_RECEIVED_Wr_En_qq;
end if;
end if;
end process;
ENDPTSETUPSTAT_Hanshake_Rst <= a_ENDPTSETUPSTAT_Hanshake_Rst or not_axi_resetn;
a_ENDPTSETUP_RECEIVED_Wr_En <= a_ENDPTSETUP_RECEIVED_Wr_En_Loc;
Inst_HandshakeData_ENDPTSETUPSTAT : entity work.HandshakeData
GENERIC MAP (
kDataWidth => 32)
PORT MAP(
InClk => Ulpi_Clk,
OutClk => Axi_Clk,
iData => u_ENDPTSETUPSTAT_iData,
oData => a_ENDPTSETUP_RECEIVED_oData,
iPush => u_ENDPTSETUPSTAT_iPush,
iRdy => u_ENDPTSETUPSTAT_iRdy,
oAck => a_ENDPTSETUPSTAT_oValid,
oValid => a_ENDPTSETUPSTAT_oValid,
aReset => ENDPTSETUPSTAT_Hanshake_Rst
);
------------------------------------------------------------------------------------------------
PACKET_IN_COMPLETE_PROC : process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_In_Packet_Complete_iData <= (others => '0');
u_In_Packet_Complete_iPush <= '0';
u_In_Packet_Complete_Rst <= '0';
else
if (u_In_Packet_Complete = '1' and u_In_Packet_Complete_iRdy = '1') then
u_In_Packet_Complete_iData(pe_endpt_nr_index) <= '1';
u_In_Packet_Complete_iPush <= '1';
u_In_Packet_Complete_Rst <= '0';
else
u_In_Packet_Complete_iData <= (others => '0');
u_In_Packet_Complete_Rst <= '1';
u_In_Packet_Complete_iPush <= '0';
end if;
end if;
end if;
end process;
packet_in_complete_wr_en_PROC : process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (axi_resetn = '0') then
a_In_Packet_Complete_Set_En_Loc <= '0';
a_In_Packet_Complete_Wr_En_q <= '0';
a_In_Packet_Complete_Set_En_q <= '0';
a_In_Packet_Complete_Set_En_qq <= '0';
a_Packet_In_Complete_Hanshake_Rst <= '0';
else
a_In_Packet_Complete_Wr_En_q <= a_In_Packet_In_Complete_oValid;
a_In_Packet_Complete_Set_En_Loc <= a_In_Packet_In_Complete_oValid and (not a_In_Packet_Complete_Wr_En_q);
a_In_Packet_Complete_Set_En_q <= a_In_Packet_Complete_Set_En_Loc;
a_In_Packet_Complete_Set_En_qq <= a_In_Packet_Complete_Set_En_q;
a_Packet_In_Complete_Hanshake_Rst <= a_In_Packet_Complete_Set_En_qq;
end if;
end if;
end process;
a_In_Packet_Complete_Set_En <= a_In_Packet_Complete_Set_En_Loc;
Packet_In_Complete_Hanshake_Rst <= a_Packet_In_Complete_Hanshake_Rst or not_axi_resetn;
Inst_HandshakeData_packet_in_complete : entity work.HandshakeData
GENERIC MAP (
kDataWidth => 32)
PORT MAP(
InClk => Ulpi_Clk,
OutClk => Axi_Clk,
iData => u_In_Packet_Complete_iData,
oData => a_In_Packet_Complete_oData,
iPush => (u_In_Packet_Complete_iPush and u_In_Packet_Complete_iRdy),
iRdy => u_In_Packet_Complete_iRdy,
oAck => a_In_Packet_In_Complete_oValid,
oValid => a_In_Packet_In_Complete_oValid,
aReset => Packet_In_Complete_Hanshake_Rst
);
-----------------------------------------------------------------------------------------------------
FRINDEX_PROC : process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_FRINDEX_iData <= (others => '0');
u_FRINDEX_iPush <= '0';
else
if (u_SOF_Received = '1' and u_FRINDEX_iRdy = '1') then
u_FRINDEX_iData(10 downto 0) <= u_Frame_Index;
u_FRINDEX_iPush <= '1';
else
u_FRINDEX_iPush <= '0';
end if;
end if;
end if;
end process;
FRINDEX_wr_en_PROC : process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (axi_resetn = '0') then
a_FRINDEX_Wr_En <= '0';
a_FRINDEX_Wr_En_q <= '0';
else
a_FRINDEX_Wr_En_q <= a_FRINDEX_oValid;
a_FRINDEX_Wr_En <= a_FRINDEX_oValid and (not a_FRINDEX_Wr_En_q);
end if;
end if;
end process;
Inst_HandshakeData_FRINDEX : entity work.HandshakeData
GENERIC MAP (
kDataWidth => 11)
PORT MAP(
InClk => Ulpi_Clk,
OutClk => Axi_Clk,
iData => u_FRINDEX_iData,
oData => a_FRINDEX_oData,
iPush => u_FRINDEX_iPush,
iRdy => u_FRINDEX_iRdy,
oAck => a_FRINDEX_oValid,
oValid => a_FRINDEX_oValid,
aReset => not_axi_resetn
);
---------------------------------------------------------------------------------------------------------
IN_TOKEN_RECEIVED_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_In_Token_Received_iData <= (others => '0');
u_In_Token_Received_iPush <= '0';
else
u_In_Token_Received_iPush <= u_In_Token_Received and u_In_Token_Received_iRdy;
if (u_In_Token_Received = '1') then
u_In_Token_Received_iData(pe_endpt_nr_index) <= '1';
else
u_In_Token_Received_iData <= (others => '0');
end if;
end if;
end if;
end process;
in_token_received_set_en_PROC : process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (axi_resetn = '0') then
a_In_Token_Received_Set_En_Loc <= '0';
a_In_Token_Received_Set_En_qq <= '0';
a_In_Token_Received_Set_En_q <= '0';
a_In_Token_Received_Hanshake_Rst <= '0';
else
a_In_Token_Received_Set_En_q <= a_In_Token_Received_oValid;
a_In_Token_Received_Set_En_Loc <= a_In_Token_Received_oValid and (not a_In_Token_Received_Set_En_q);
a_In_Token_Received_Set_En_qq <= a_In_Token_Received_Set_En_Loc;
a_In_Token_Received_Hanshake_Rst <= a_In_Token_Received_Set_En_qq;
end if;
end if;
end process;
a_In_Token_Received_Set_En <= a_In_Token_Received_Set_En_Loc;
In_Token_Received_Hanshake_Rst <= a_In_Token_Received_Hanshake_Rst or not_axi_resetn;
Inst_HandshakeData_in_token_received : entity work.HandshakeData
GENERIC MAP (
kDataWidth => 32)
PORT MAP(
InClk => Ulpi_Clk,
OutClk => Axi_Clk,
iData => u_In_Token_Received_iData,
oData => a_In_Token_Received_oData,
iPush => u_In_Token_Received_iPush,
iRdy => u_In_Token_Received_iRdy,
oAck => a_In_Token_Received_oValid,
oValid => a_In_Token_Received_oValid,
aReset => In_Token_Received_Hanshake_Rst
);
-----------------------------------------------------------------------------------------------------------
SEND_ZERO_LENGTH_PROC : process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Send_Zero_Length_Packet_Clear_iData <= (others => '1');
u_Send_Zero_Length_Packet_Clear_iPush <= '0';
else
if (u_Send_Zero_Length_Packet_Clear = '1') then
u_Send_Zero_Length_Packet_Clear_iData(pe_endpt_nr_index) <= '0';
u_Send_Zero_Length_Packet_Clear_iPush <= '1';
else
u_Send_Zero_Length_Packet_Clear_iData <= (others => '1');
u_Send_Zero_Length_Packet_Clear_iPush <= '0';
end if;
end if;
end if;
end process;
send_zero_length_packet_clear_en_PROC : process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (axi_resetn = '0') then
a_Send_Zero_Length_Packet_Clear_En_Loc <= '0';
a_Send_Zero_Length_Packet_Clear_En_qq <= '0';
a_Send_Zero_Length_Packet_Clear_En_q <= '0';
a_Send_Zero_Length_Packet_Clear_Hanshake_Rst <= '0';
else
a_Send_Zero_Length_Packet_Clear_En_q <= a_In_Token_Received_oValid;
a_Send_Zero_Length_Packet_Clear_En_Loc <= a_Send_Zero_Length_Packet_Clear_oValid and (not a_Send_Zero_Length_Packet_Clear_En_q);
a_Send_Zero_Length_Packet_Clear_En_qq <= a_Send_Zero_Length_Packet_Clear_En_Loc;
a_Send_Zero_Length_Packet_Clear_Hanshake_Rst <= a_Send_Zero_Length_Packet_Clear_Hanshake_Rst;
end if;
end if;
end process;
a_Send_Zero_Length_Packet_Clear_En <= a_Send_Zero_Length_Packet_Clear_En_Loc;
Send_Zero_Length_Packet_Clear_Hanshake_Rst <= a_Send_Zero_Length_Packet_Clear_Hanshake_Rst or not_axi_resetn;
Inst_HandshakeData_zero_length_clear: entity work.HandshakeData
GENERIC MAP (
kDataWidth => 32)
PORT MAP(
InClk => Ulpi_Clk,
OutClk => Axi_Clk,
iData => u_Send_Zero_Length_Packet_Clear_iData,
oData => a_Send_Zero_Length_Packet_Clear_oData ,
iPush => (u_Send_Zero_Length_Packet_Clear_iPush and u_Send_Zero_Length_Packet_Clear_iRdy),
iRdy => u_Send_Zero_Length_Packet_Clear_iRdy,
oAck => a_Send_Zero_Length_Packet_Clear_oValid,
oValid => a_Send_Zero_Length_Packet_Clear_oValid,
aReset => Send_Zero_Length_Packet_Clear_Hanshake_Rst
);
-------------------------------------------------------------------------------------------------------------
SEND_ZERO_LENGTH_ACK_PROC : process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Send_Zero_Length_Packet_Ack_iData <= (others => '0');
else
if (u_Send_Zero_Length_Packet_Ack_Set = '1') then
u_Send_Zero_Length_Packet_Ack_iData(pe_endpt_nr_index) <= '1';
else
u_Send_Zero_Length_Packet_Ack_iData <= (others => '0');
end if;
end if;
end if;
end process;
IPUSH_SEND_ZERO_LENGTH_ACK_PROC : process (Ulpi_Clk)
begin
if (Ulpi_Clk'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Send_Zero_Length_Packet_Ack_iPush <= '0';
u_Send_Zero_Length_Packet_Ack_iData_q <= (others => '0');
else
u_Send_Zero_Length_Packet_Ack_iData_q <= u_Send_Zero_Length_Packet_Ack_iData;
if (u_Send_Zero_Length_Packet_Ack_iData /= u_Send_Zero_Length_Packet_Ack_iData_q and u_Send_Zero_Length_Packet_Ack_iRdy = '1') then
u_Send_Zero_Length_Packet_Ack_iPush <= '1';
else
u_Send_Zero_Length_Packet_Ack_iPush <= '0';
end if;
end if;
end if;
end process;
Send_Zero_Length_Packet_Ack_Set_En_PROC : process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (axi_resetn = '0') then
a_Send_Zero_Length_Packet_Ack_Set_En_Loc <= '0';
a_Send_Zero_Length_Packet_Ack_Set_En_qq <= '0';
a_Send_Zero_Length_Packet_Ack_Set_En_q <= '0';
a_Send_Zero_Length_Packet_Ack_Set_Hanshake_Rst <= '0';
else
a_Send_Zero_Length_Packet_Ack_Set_En_q <= a_Send_Zero_Length_Packet_Ack_oValid;
a_Send_Zero_Length_Packet_Ack_Set_En_Loc <= a_Send_Zero_Length_Packet_Ack_oValid and (not a_Send_Zero_Length_Packet_Ack_Set_En_q);
a_Send_Zero_Length_Packet_Ack_Set_En_qq <= a_Send_Zero_Length_Packet_Ack_Set_En_Loc;
a_Send_Zero_Length_Packet_Ack_Set_Hanshake_Rst <= a_Send_Zero_Length_Packet_Ack_Set_En_qq;
end if;
end if;
end process;
a_Send_Zero_Length_Packet_Ack_Set_En <= a_Send_Zero_Length_Packet_Ack_Set_En_Loc;
Send_Zero_Length_Packet_Ack_Set_Hanshake_Rst <= a_Send_Zero_Length_Packet_Ack_Set_Hanshake_Rst or not_axi_resetn;
Inst_HandshakeData_zero_length_ack: entity work.HandshakeData
GENERIC MAP (
kDataWidth => 32)
PORT MAP(
InClk => Ulpi_Clk,
OutClk => Axi_Clk,
iData => u_Send_Zero_Length_Packet_Ack_iData,
oData => a_Send_Zero_Length_Packet_Ack_oData ,
iPush => u_Send_Zero_Length_Packet_Ack_iPush,
iRdy => u_Send_Zero_Length_Packet_Ack_iRdy,
oAck => a_Send_Zero_Length_Packet_Ack_oValid,
oValid => a_Send_Zero_Length_Packet_Ack_oValid,
aReset => Send_Zero_Length_Packet_Ack_Set_Hanshake_Rst
);
----------------------------------------------------------------------------------------------------------------
IPUSH_pe_SETUP_BUFFER_BYTES_3_0_PROC : process (Ulpi_Clk)
begin
if (Ulpi_Clk'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Setup_Buffer_Bytes_3_0_iPush <= '0';
u_Setup_Buffer_Bytes_3_0_q <= (others => '0');
else
u_Setup_Buffer_Bytes_3_0_q <= u_Setup_Buffer_Bytes_3_0_iData;
if (u_Setup_Buffer_Bytes_3_0_iData /= u_Setup_Buffer_Bytes_3_0_q and u_Setup_Buffer_Bytes_3_0_iRdy = '1') then
u_Setup_Buffer_Bytes_3_0_iPush <= '1';
else
u_Setup_Buffer_Bytes_3_0_iPush <= '0';
end if;
end if;
end if;
end process;
Inst_HandshakeData_SETUP_BUFFER_BYTES_3_0 : entity work.HandshakeData
GENERIC MAP (
kDataWidth => 32)
PORT MAP(
InClk => Ulpi_Clk,
OutClk => Axi_Clk,
iData => u_Setup_Buffer_Bytes_3_0_iData,
oData => a_Setup_Buffer_Bytes_3_0_oData,
iPush => u_Setup_Buffer_Bytes_3_0_iPush,
iRdy => u_Setup_Buffer_Bytes_3_0_iRdy,
oAck => a_Setup_Buffer_Bytes_3_0_oValid,
oValid => a_Setup_Buffer_Bytes_3_0_oValid,
aReset => not_axi_resetn
);
----------------------------------------------------------------------------------------------------------------
IPUSH_pe_SETUP_BUFFER_BYTES_7_4_PROC : process (Ulpi_Clk)
begin
if (Ulpi_Clk'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Setup_Buffer_Bytes_7_4_iPush <= '0';
u_Setup_Buffer_Bytes_7_4_q <= (others => '0');
else
u_Setup_Buffer_Bytes_7_4_q <= u_Setup_Buffer_Bytes_7_4_iData;
if (u_Setup_Buffer_Bytes_7_4_iData /= u_Setup_Buffer_Bytes_7_4_q and u_Setup_Buffer_Bytes_7_4_iRdy = '1') then
u_Setup_Buffer_Bytes_7_4_iPush <= '1';
else
u_Setup_Buffer_Bytes_7_4_iPush <= '0';
end if;
end if;
end if;
end process;
Inst_HandshakeData_pe_SETUP_BUFFER_BYTES_7_4 : entity work.HandshakeData
GENERIC MAP (
kDataWidth => 32)
PORT MAP(
InClk => Ulpi_Clk,
OutClk => Axi_Clk,
iData => u_Setup_Buffer_Bytes_7_4_iData,
oData => a_Setup_Buffer_Bytes_7_4_oData,
iPush => u_Setup_Buffer_Bytes_7_4_iPush,
iRdy => u_Setup_Buffer_Bytes_7_4_iRdy,
oAck => a_Setup_Buffer_Bytes_7_4_oValid,
oValid => a_Setup_Buffer_Bytes_7_4_oValid,
aReset => not_axi_resetn
);
----------------------------------------------------------------------------------------------------------------
USBSTS_NAKI_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_USBSTS_NAKI_iData <= "0";
u_USBSTS_NAKI_iPush <= '0';
else
if (u_NAK_Sent = '1' and u_USBSTS_NAKI_iRdy = '1') then
u_USBSTS_NAKI_iData <= "1";
u_USBSTS_NAKI_iPush <= '1';
else
u_USBSTS_NAKI_iPush <= '0';
end if;
end if;
end if;
end process;
USBSTS_wr_en_NAK_PROC : process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (axi_resetn = '0') then
a_USBSTS_NAKI_Wr_En <= '0';
a_USBSTS_NAKI_Wr_En_q <= '0';
else
a_USBSTS_NAKI_Wr_En_q <= a_USBSTS_NAKI_oValid;
a_USBSTS_NAKI_Wr_En <= a_USBSTS_NAKI_oValid and (not a_USBSTS_NAKI_Wr_En_q);
end if;
end if;
end process;
Inst_HandshakeData_NAKI : entity work.HandshakeData
GENERIC MAP (
kDataWidth => 1)
PORT MAP(
InClk => Ulpi_Clk,
OutClk => Axi_Clk,
iData => u_USBSTS_NAKI_iData,
oData => a_USBSTS_NAKI_Vector,
iPush => u_USBSTS_NAKI_iPush,
iRdy => u_USBSTS_NAKI_iRdy,
oAck => a_USBSTS_NAKI_oValid,
oValid => a_USBSTS_NAKI_oValid,
aReset => not_axi_resetn
);
a_USBSTS_NAKI_oData <= a_USBSTS_NAKI_Vector(0);
----------------------------------------------------------------------------------------------------------------
SET_CLEAR_SUSPEND_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Set_Suspend_State <= '0';
u_Set_Clear_Suspend_State <= '0';
u_Reset_Received_Ulpi <= '0';
else
if (state_ind_hs_loc = "10010") then
u_Set_Suspend_State <= '1';
u_Set_Clear_Suspend_State <= '0';
u_Reset_Received_Ulpi <= '0';
else
u_Set_Suspend_State <= '0';
u_Set_Clear_Suspend_State <= '1';
if(state_ind_hs_loc = "01000") then
u_Reset_Received_Ulpi <= '1';
else
u_Reset_Received_Ulpi <= '0';
end if;
end if;
end if;
end if;
end process;
SET_SUSPEND_PROC : process (Ulpi_Clk)
begin
if (Ulpi_Clk'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Suspend_State <= '0';
u_Suspend_State_q <= '0';
else
u_Suspend_State_q <= u_Set_Suspend_State;
u_Suspend_State <= u_Set_Suspend_State and (not u_Suspend_State_q);
end if;
end if;
end process;
CLEAR_SUSPEND_PROC : process (Ulpi_Clk)
begin
if (Ulpi_Clk'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Clear_Suspend_State <= '0';
u_Set_Clear_Suspend_State_q <= '0';
else
u_Set_Clear_Suspend_State_q <= u_Set_Clear_Suspend_State;
u_Clear_Suspend_State <= u_Set_Clear_Suspend_State and (not u_Set_Clear_Suspend_State_q);
end if;
end if;
end process;
USBSTS_SLI_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_USBSTS_SLI_iData <= "0";
u_USBSTS_SLI_iPush <= '0';
else
if (u_Suspend_State = '1' and u_USBSTS_SLI_iRdy = '1') then
u_USBSTS_SLI_iData <= "1";
u_USBSTS_SLI_iPush <= '1';
elsif (u_Clear_Suspend_State = '1' and u_USBSTS_SLI_iRdy = '1') then
u_USBSTS_SLI_iData <= "1";
u_USBSTS_SLI_iPush <= '1';
else
u_USBSTS_SLI_iPush <= '0';
end if;
end if;
end if;
end process;
USBSTS_wr_en_SLI_PROC : process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (axi_resetn = '0') then
a_USBSTS_SLI_Wr_En <= '0';
a_USBSTS_SLI_Wr_En_q <= '0';
else
a_USBSTS_SLI_Wr_En_q <= a_USBSTS_SLI_oValid;
a_USBSTS_SLI_Wr_En <= a_USBSTS_SLI_oValid and (not a_USBSTS_SLI_Wr_En_q);
end if;
end if;
end process;
Inst_HandshakeData_SLI: entity work.HandshakeData
GENERIC MAP (
kDataWidth => 1)
PORT MAP(
InClk => Ulpi_Clk,
OutClk => Axi_Clk,
iData => u_USBSTS_SLI_iData,
oData => a_USBSTS_SLI_Vector,
iPush => u_USBSTS_SLI_iPush,
iRdy => u_USBSTS_SLI_iRdy,
oAck => a_USBSTS_SLI_oValid,
oValid => a_USBSTS_SLI_oValid,
aReset => not_axi_resetn
);
a_USBSTS_SLI_oData <= a_USBSTS_SLI_Vector(0);
------------------------------------------------------------------------------------------------------------------------------------
USBSTS_SRI_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_USBSTS_SRI_iData <= "0";
u_USBSTS_SRI_iPush <= '0';
else
if (u_SOF_Received = '1' and u_USBSTS_SRI_iRdy = '1') then
u_USBSTS_SRI_iData <= "1";
u_USBSTS_SRI_iPush <= '1';
else
u_USBSTS_SRI_iPush <= '0';
end if;
end if;
end if;
end process;
USBSTS_wr_en_SRI_PROC : process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (axi_resetn = '0') then
a_USBSTS_SRI_Wr_En <= '0';
a_USBSTS_SRI_Wr_En_q <= '0';
else
a_USBSTS_SRI_Wr_En_q <= a_USBSTS_SRI_oValid;
a_USBSTS_SRI_Wr_En <= a_USBSTS_SRI_oValid and (not a_USBSTS_SRI_Wr_En_q);
end if;
end if;
end process;
Inst_HandshakeData_SRI: entity work.HandshakeData
GENERIC MAP (
kDataWidth => 1)
PORT MAP(
InClk => Ulpi_Clk,
OutClk => Axi_Clk,
iData => u_USBSTS_SRI_iData,
oData => a_USBSTS_SRI_Vector,
iPush => u_USBSTS_SRI_iPush,
iRdy => u_USBSTS_SRI_iRdy,
oAck => a_USBSTS_SRI_oValid,
oValid => a_USBSTS_SRI_oValid,
aReset => not_axi_resetn
);
a_USBSTS_SRI_oData <= a_USBSTS_SRI_Vector(0);
--------------------------------------------------------------------------------------------------------------------------------------
USBSTS_URI_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_USBSTS_URI_iData <= "0";
u_USBSTS_URI_iPush <= '0';
else
if (u_Reset_Received = '1' and u_USBSTS_URI_iRdy = '1') then
u_USBSTS_URI_iData <= "1";
u_USBSTS_URI_iPush <= '1';
else
u_USBSTS_URI_iPush <= '0';
end if;
end if;
end if;
end process;
RESET_RECEIVED_PROC : process (Ulpi_Clk)
begin
if (Ulpi_Clk'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Reset_Received <= '0';
u_Reset_Received_Ulpi_q <= '0';
else
u_Reset_Received_Ulpi_q <= u_Reset_Received_Ulpi;
u_Reset_Received <= u_Reset_Received_Ulpi and (not u_Reset_Received_Ulpi_q);
end if;
end if;
end process;
USBSTS_wr_en_URI_PROC : process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (axi_resetn = '0') then
a_USBSTS_URI_Wr_En <= '0';
a_USBSTS_URI_Wr_En_q <= '0';
else
a_USBSTS_URI_Wr_En_q <= a_USBSTS_URI_oValid;
a_USBSTS_URI_Wr_En <= a_USBSTS_URI_oValid and (not a_USBSTS_URI_Wr_En_q);
end if;
end if;
end process;
Inst_HandshakeData_URI: entity work.HandshakeData
GENERIC MAP (
kDataWidth => 1)
PORT MAP(
InClk => Ulpi_Clk,
OutClk => Axi_Clk,
iData => u_USBSTS_URI_iData,
oData => a_USBSTS_URI_Vector,
iPush => u_USBSTS_URI_iPush,
iRdy => u_USBSTS_URI_iRdy,
oAck => a_USBSTS_URI_oValid,
oValid => a_USBSTS_URI_oValid,
aReset => not_axi_resetn
);
a_USBSTS_URI_oData <= a_USBSTS_URI_Vector(0);
--------------------------------------------------------------------------------------------------------------------------------------
u_Port_Change_Detect <= u_Wake or u_Set_Mode_HS or u_Set_Mode_FS;
USBSTS_PCI_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_USBSTS_PCI_iData <= "0";
u_USBSTS_PCI_iPush <= '0';
else
if (u_Port_Change_Detect = '1' and u_USBSTS_PCI_iRdy = '1') then --resume signaling or port enters high speed or full speed mode
u_USBSTS_PCI_iData <= "1";
u_USBSTS_PCI_iPush <= '1';
else
u_USBSTS_PCI_iPush <= '0';
end if;
end if;
end if;
end process;
USBSTS_wr_en_PCI_PROC : process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (axi_resetn = '0') then
a_USBSTS_PCI_Wr_En <= '0';
a_USBSTS_PCI_Wr_En_q <= '0';
else
a_USBSTS_PCI_Wr_En_q <= a_USBSTS_PCI_oValid;
a_USBSTS_PCI_Wr_En <= a_USBSTS_PCI_oValid and (not a_USBSTS_PCI_Wr_En_q);
end if;
end if;
end process;
Inst_HandshakeData_PCI : entity work.HandshakeData
GENERIC MAP (
kDataWidth => 1)
PORT MAP(
InClk => Ulpi_Clk,
OutClk => Axi_Clk,
iData => u_USBSTS_PCI_iData,
oData => a_USBSTS_PCI_Vector,
iPush => u_USBSTS_PCI_iPush,
iRdy => u_USBSTS_PCI_iRdy,
oAck => a_USBSTS_PCI_oValid,
oValid => a_USBSTS_PCI_oValid,
aReset => not_axi_resetn
);
a_USBSTS_PCI_oData <= a_USBSTS_PCI_Vector(0);
------------------------------------------------------------------------------------------------------------------------------------------
URESEND_IDATA_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Resend_iData <= (others => '0');
u_Resend_iPush <= '0';
else
if (u_Resend_Set = '1' and u_Resend_iRdy = '1') then --resume signaling or port enters high speed or full speed mode
u_Resend_iData(pe_endpt_nr_index) <= '1';
u_Resend_iPush <= '1';
else
u_Resend_iPush <= '0';
u_Resend_iData <= (others => '0');
end if;
end if;
end if;
end process;
RESEND_WR_EN_PROC : process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (axi_resetn = '0') then
a_Resend_Wr_En <= '0';
a_Resend_Wr_En_q <= '0';
else
a_Resend_Wr_En_q <= a_Resend_oValid;
a_Resend_Wr_En <= a_Resend_oValid and (not a_Resend_Wr_En_q);
end if;
end if;
end process;
Inst_HandshakeData_Resend : entity work.HandshakeData
GENERIC MAP (
kDataWidth => 32)
PORT MAP(
InClk => Ulpi_Clk,
OutClk => Axi_Clk,
iData => u_Resend_iData,
oData => a_Resend_oData,
iPush => u_Resend_iPush,
iRdy => u_Resend_iRdy,
oAck => a_Resend_oValid,
oValid => a_Resend_oValid,
aReset => not_axi_resetn
);
------------------------------------------------------------------------------------------------------------------------------------------
PORTSC1_PSPD_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_PORTSC1_iData <= "00";
u_PORTSC1_iPush <= '0';
else
if (u_Not_Connected = '1') then
if (u_Not_Connected_Pulse = '1' and u_PORTSC1_iRdy = '1') then
u_PORTSC1_iData <= "11";
u_PORTSC1_iPush <= '1';
end if;
else
if (u_Set_Mode_HS = '1' and u_PORTSC1_iRdy = '1') then
u_PORTSC1_iData <= "10";
u_PORTSC1_iPush <= '1';
elsif (u_Set_Mode_FS = '0' and u_Not_Connected = '0' and u_PORTSC1_iRdy = '1')then
u_PORTSC1_iData <= "01";
u_PORTSC1_iPush <= '1';
else
u_PORTSC1_iPush <= '0';
end if;
end if;
end if;
end if;
end process;
PORTSC1_PSPD_wr_en_PROC : process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (axi_resetn = '0') then
a_PORTSC1_PSPD_Wr_En <= '0';
a_PORTSC1_PSPD_Wr_En_q <= '0';
else
a_PORTSC1_PSPD_Wr_En_q <= a_PORTSC1_oValid;
a_PORTSC1_PSPD_Wr_En <= a_PORTSC1_oValid and (not a_PORTSC1_PSPD_Wr_En_q);
end if;
end if;
end process;
Inst_HandshakeData_PORTSC1: entity work.HandshakeData
GENERIC MAP (
kDataWidth => 2)
PORT MAP(
InClk => Ulpi_Clk,
OutClk => Axi_Clk,
iData => u_PORTSC1_iData,
oData => a_PORTSC1_PSPD_oData,
iPush => u_PORTSC1_iPush,
iRdy => u_PORTSC1_iRdy,
oAck => a_PORTSC1_oValid,
oValid => a_PORTSC1_oValid,
aReset => not_axi_resetn
);
NOT_CONNECTED_PROC : process (Ulpi_Clk)
begin
if (Ulpi_Clk'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Not_Connected_Pulse <= '0';
u_Not_Connected_q <= '0';
else
u_Not_Connected_q <= u_Not_Connected;
u_Not_Connected_Pulse <= u_Not_Connected and (not u_Not_Connected_q);
end if;
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- File: Protocol_Engine.vhd
-- Author: Gherman Tudor
-- Original Project: USB Device IP on 7-series Xilinx FPGA
-- Date: 2 May 2016
--
-------------------------------------------------------------------------------
-- (c) 2016 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module instantiates all the necessary modules to implement ULPI
-- communication, Speed negotiation , Reset and Suspend. Packet data is
-- sent/received over AXI Stream. Synchronization modules for registers
-- that corss the ULPI Clock domain to AXI clock domain is implemented
-- here
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity Protocol_Engine is
generic (
MAX_NR_ENDP : integer := 1
);
Port (
Axi_Clk : IN std_logic;
Axi_Resetn : IN STD_LOGIC;
Ulpi_Clk : in STD_LOGIC;
u_ResetN : in STD_LOGIC;
--ULPI Bus
Ulpi_Reset : out STD_LOGIC;
u_Ulpi_Data : INOUT std_logic_vector(7 downto 0);
u_Ulpi_Dir : IN std_logic;
u_Ulpi_Nxt : IN std_logic;
u_Ulpi_Stp : OUT std_logic;
led : out STD_LOGIC; --debug purposes
--Transmit FIFO write channel
a_Arb_Endpt_Nr : in std_logic_vector(4 downto 0);
Tx_Fifo_S_Aresetn : IN STD_LOGIC;
a_Tx_Fifo_S_Aclk : IN STD_LOGIC;
a_Tx_Fifo_S_Axis_Tvalid : IN STD_LOGIC;
a_Tx_Fifo_S_Axis_Tready : OUT STD_LOGIC;
a_Tx_Fifo_S_Axis_Tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
a_Tx_Fifo_S_Axis_Tlast : IN STD_LOGIC;
a_Tx_Fifo_S_Axis_Tkeep : IN std_logic_vector(3 downto 0);
a_Tx_Fifo_S_Axis_Tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
tx_fifo_axis_overflow : OUT STD_LOGIC;
tx_fifo_axis_underflow : OUT STD_LOGIC;
--Receive FIFO write channel
u_Rx_Fifo_s_Aclk : OUT std_logic;
u_Rx_Fifo_s_Axis_Tready : IN std_logic;
u_Rx_Fifo_s_Axis_Tvalid : OUT std_logic;
u_Rx_Fifo_s_Axis_Tdata : OUT std_logic_vector(31 downto 0);
u_Rx_Fifo_s_Axis_Tkeep : OUT std_logic_vector (3 downto 0);
u_Rx_Fifo_s_Axis_Tlast : OUT std_logic;
u_Rx_Fifo_Axis_Overflow : IN std_logic;
u_Rx_Fifo_Axis_Underflow : IN std_logic;
--Command FIFO; used to keep track of received OUT transactions
u_Command_Fifo_Rd_En : IN std_logic;
u_Command_Fifo_Dout : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
u_Command_Fifo_Empty : OUT std_logic;
u_Command_Fifo_Valid : OUT std_logic;
--control signals to/from DMA_Transfer_Manager
a_In_Packet_Complete_oData : OUT std_logic_vector(31 downto 0); --a bit is set when the corresponding endpoint has completed an IN transaction
a_In_Packet_Complete_Set_En : OUT std_logic; --a_In_Packet_Complete_oData strobe
u_Send_Zero_Length_Packet_Rd : IN STD_LOGIC_VECTOR(31 downto 0); --If a bit is set, the corresponding endpoint needs to send a Zero Length Packet
a_Send_Zero_Length_Packet_Clear_oData : OUT STD_LOGIC_VECTOR(31 downto 0); --ZLP Hanshake between Packet_Decoder and DMA_Transfer_Manager
a_Send_Zero_Length_Packet_Clear_En : OUT STD_LOGIC; --ZLP Hanshake between Packet_Decoder and DMA_Transfer_Manager
a_Send_Zero_Length_Packet_Ack_oData : OUT STD_LOGIC_VECTOR(31 downto 0); --ZLP Hanshake between Packet_Decoder and DMA_Transfer_Manager
a_Send_Zero_Length_Packet_Ack_Set_En : OUT STD_LOGIC; --ZLP Hanshake between Packet_Decoder and DMA_Transfer_Manager
a_Cnt_Bytes_Sent_oData : out std_logic_vector(12 downto 0); --number of bytes sent in response to an IN token
a_Cnt_Bytes_Sent_oValid : OUT std_logic; -- a_Cnt_Bytes_Sent_oData strobe
a_Resend_oData : OUT STD_LOGIC_VECTOR(31 downto 0); --indicates to the upper layers that the endpoint corresponding to set bits need to resend a packet
a_Resend_Wr_En : OUT std_logic; --a_Resend_oData
a_In_Token_Received_oData : OUT std_logic_vector(31 downto 0); -- a bit is set when the corresponding endpoint has received an IN token
a_In_Token_Received_Set_En : OUT std_logic; --a_In_Token_Received_oData strobe
a_Endpt_Nr : OUT STD_LOGIC_VECTOR(4 DOWNTO 0); --endpoint accessed by the lower layers (ULPI, Packet_Decoder)
u_Endp_Nr : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
u_Endp_Nr_Arb : IN STD_LOGIC_VECTOR(4 DOWNTO 0); --endpoint accessed by the DMA_Transfer_Manager
u_Endp_Nr_Arb_Ack : OUT std_logic;
u_Endp_Nr_Arb_Valid : IN std_logic;
--Setup packets are stored in these registers before being copied into the dQH
a_Setup_Buffer_Bytes_3_0_oData : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
a_Setup_Buffer_Bytes_7_4_oData : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--Interface to Control_Registers block
u_Endp_Type : in STD_LOGIC_VECTOR(47 downto 0);
u_Endp_Stall : IN STD_LOGIC_VECTOR(23 downto 0);
u_USBADRA : in STD_LOGIC_VECTOR (7 downto 0);
a_FRINDEX_oData : out std_logic_vector(10 downto 0);
a_FRINDEX_Wr_En : out std_logic;
a_PORTSC1_PSPD_oData : out std_logic_vector(1 downto 0);
a_PORTSC1_PSPD_Wr_En : out std_logic;
a_ENDPTNAK_oData : out std_logic_vector(31 downto 0);
a_ENDPTNAK_Wr_En : out std_logic;
a_ENDPTSETUP_RECEIVED_oData : out std_logic_vector(31 downto 0);
a_ENDPTSETUP_RECEIVED_Wr_En : out std_logic;
a_USBSTS_NAKI_oData : out std_logic;
a_USBSTS_NAKI_Wr_En : out std_logic;
a_USBSTS_SLI_oData : out std_logic;
a_USBSTS_SLI_Wr_En : out std_logic;
a_USBSTS_SRI_oData : out std_logic;
a_USBSTS_SRI_Wr_En : out std_logic;
a_USBSTS_URI_oData : out std_logic;
a_USBSTS_URI_Wr_En : out std_logic;
a_USBSTS_PCI_oData : out std_logic;
a_USBSTS_PCI_Wr_En : out std_logic;
u_USBCMD_RS : in std_logic;
state_ind : out STD_LOGIC_VECTOR(5 downto 0);
state_ind_pd : out STD_LOGIC_VECTOR(6 downto 0);
state_ind_hs : out STD_LOGIC_VECTOR(4 downto 0)
);
end Protocol_Engine;
architecture Behavioral of Protocol_Engine is
COMPONENT ULPI
PORT(
Ulpi_Clk : IN std_logic;
reset : IN std_logic;
u_Ulpi_Data : INOUT std_logic_vector(7 downto 0);
u_Ulpi_Dir : IN std_logic;
u_Ulpi_Nxt : IN std_logic;
u_Ulpi_Stp : OUT std_logic;
u_Ulpi_Reset : OUT std_logic;
u_Send_NOOP_CMD : IN std_logic;
u_Send_NOPID_CMD : IN std_logic;
u_Send_PID_CMD : IN std_logic;
u_Send_EXTW_CMD : IN std_logic;
u_Send_REGW_CMD : IN std_logic;
u_Send_EXTR_CMD : IN std_logic;
u_Send_REGR_CMD : IN std_logic;
u_Send_STP_CMD : IN std_logic;
u_Send_Last : IN std_logic;
u_Send_Err : IN std_logic;
u_Tx_Data : IN std_logic_vector(7 downto 0);
u_Tx_Data_En : OUT std_logic;
u_Tx_Pid : IN std_logic_vector(3 downto 0);
u_Tx_Regw_Data : in STD_LOGIC_VECTOR (7 downto 0);
u_Tx_Reg_Addr : in STD_LOGIC_VECTOR (7 downto 0);
u_Tx_Cmd_Done : OUT STD_LOGIC;
u_USB_Mode : IN std_logic;
u_CRC16_En : out STD_LOGIC;
u_Tx_Pid_Phase_Done : out STD_LOGIC;
u_Rx_Data : OUT std_logic_vector(7 downto 0);
u_Rx_Packet_Received : OUT std_logic;
u_Ulpi_Dir_Out : out STD_LOGIC;
u_LineState : OUT std_logic_vector(1 downto 0);
u_Vbus : OUT std_logic_vector(1 downto 0);
u_RxEvent : OUT std_logic_vector(1 downto 0);
u_RxActive : out STD_LOGIC;
u_ID : OUT std_logic;
u_Alt_Int : OUT std_logic;
u_Rx_Cmd_Received : OUT std_logic;
state_ind : out STD_LOGIC_VECTOR(5 downto 0);
u_Rx_Register_Data : OUT std_logic_vector(7 downto 0);
u_Rx_Register_Data_Received : OUT std_logic
);
END COMPONENT;
COMPONENT HS_Negotiation
PORT(
u_Reset : IN std_logic;
Ulpi_Clk : IN std_logic;
u_Remote_Wake : IN std_logic;
u_LineState : IN std_logic_vector(1 downto 0);
u_Vbus : IN std_logic_vector(1 downto 0);
u_Rx_Cmd_Received : IN std_logic;
u_Send_NOPID_CMD : OUT std_logic;
u_Send_EXTW_CMD : OUT std_logic;
u_Send_REGW_CMD : OUT std_logic;
u_Send_EXTR_CMD : OUT std_logic;
u_Send_REGR_CMD : OUT std_logic;
u_Send_STP_CMD : OUT std_logic;
u_Send_Last : OUT std_logic;
u_Tx_Data : OUT std_logic_vector(7 downto 0);
u_Tx_Regw_Data : OUT STD_LOGIC_VECTOR (7 downto 0);
u_Tx_Cmd_Done : IN STD_LOGIC;
u_Tx_Reg_Addr : OUT STD_LOGIC_VECTOR (7 downto 0);
u_USB_Mode : OUT std_logic;
u_Not_Connected : OUT std_logic;
u_Set_Mode_HS : OUT std_logic;
u_Set_Mode_FS : OUT std_logic;
u_Wake : OUT std_logic;
u_USBCMD_RS : in std_logic;
state_ind_hs : out STD_LOGIC_VECTOR(4 downto 0);
u_Negociation_Done : out STD_LOGIC
);
END COMPONENT;
COMPONENT Packet_Decoder
PORT(
Ulpi_Clk : in STD_LOGIC;
reset : in STD_LOGIC;
Axi_Clk : IN std_logic;
Axi_Resetn : IN STD_LOGIC;
a_Arb_Endpt_Nr : in std_logic_vector(4 downto 0);
Tx_Fifo_S_Aresetn : IN STD_LOGIC;
a_Tx_Fifo_S_Aclk : IN STD_LOGIC;
a_Tx_Fifo_S_Axis_Tvalid : IN STD_LOGIC;
a_Tx_Fifo_S_Axis_Tready : OUT STD_LOGIC;
a_Tx_Fifo_S_Axis_Tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
a_Tx_Fifo_S_Axis_Tlast : IN STD_LOGIC;
a_Tx_Fifo_S_Axis_Tkeep : IN std_logic_vector(3 downto 0);
a_Tx_Fifo_S_Axis_Tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
tx_fifo_axis_overflow : OUT STD_LOGIC;
tx_fifo_axis_underflow : OUT STD_LOGIC;
--RX FIFO (write)
u_Rx_Fifo_s_Aclk : OUT std_logic;
u_Rx_Fifo_s_Axis_Tready : IN std_logic;
u_Rx_Fifo_s_Axis_Tvalid : OUT std_logic;
u_Rx_Fifo_s_Axis_Tdata : OUT std_logic_vector(31 downto 0);
u_Rx_Fifo_s_Axis_Tkeep : OUT std_logic_vector (3 downto 0);
u_Rx_Fifo_s_Axis_Tlast : OUT std_logic;
u_Rx_Fifo_Axis_Overflow : IN std_logic;
u_Rx_Fifo_Axis_Underflow : IN std_logic;
u_Command_Fifo_Rd_En : IN std_logic;
u_Command_Fifo_Dout : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
u_Command_Fifo_Empty : OUT std_logic;
u_Command_Fifo_Valid : OUT std_logic;
u_Setup_Buffer_Bytes_3_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
u_Setup_Buffer_Bytes_7_4 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
u_Send_PID_CMD : out STD_LOGIC;
u_Send_Last : out STD_LOGIC;
u_Tx_Data : out STD_LOGIC_VECTOR (7 downto 0);
u_Tx_Data_En : in STD_LOGIC;
u_Tx_Pid : out STD_LOGIC_VECTOR (3 downto 0);
u_Tx_Cmd_Done : in STD_LOGIC;
u_Tx_Pid_Phase_Done : in STD_LOGIC;
u_CRC16_En_Ulpi : in STD_LOGIC;
u_RxEvent : in STD_LOGIC_VECTOR(1 downto 0);
u_RxActive : in STD_LOGIC;
u_Rx_Packet_Received : in STD_LOGIC;
u_Ulpi_Dir_Out : in STD_LOGIC;
u_Rx_Data : in STD_LOGIC_VECTOR(7 downto 0);
u_USB_Mode : in STD_LOGIC;
u_Setup_Received : OUT std_logic;
u_Setup_Received_Rst : IN std_logic;
u_In_Token_Received : OUT std_logic;
u_In_Packet_Complete : OUT std_logic;
u_In_Packet_Complete_Rst : IN std_logic;
u_iPush_Endpt_Nr_PD : OUT STD_LOGIC;
-- endp_enable : IN STD_LOGIC(11 downto 0);
u_Send_Zero_Length_Packet : in STD_LOGIC;
u_Send_Zero_Length_Packet_Ack_Set : OUT STD_LOGIC;
u_Send_Zero_Length_Packet_Clear : OUT STD_LOGIC;
u_NAK_Sent : out STD_LOGIC;
u_Frame_Index : out STD_LOGIC_VECTOR (10 downto 0);
u_SOF_received : out STD_LOGIC;
u_Cnt_Bytes_Sent : out std_logic_vector(12 downto 0);
u_Cnt_Bytes_Sent_Latch : out STD_LOGIC;
u_Resend_Set : out STD_LOGIC;
u_Endp_Nr : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
u_Endp_Stall : IN STD_LOGIC;
u_Endp_Type : in STD_LOGIC_VECTOR(1 downto 0);
u_USBADRA : in STD_LOGIC_VECTOR (7 downto 0);
axis_32_to_8_latency_comp_out_port : out STD_LOGIC;
ulpi_latency_comp_out : in STD_LOGIC;
state_ind_pd : out STD_LOGIC_VECTOR(6 downto 0);
packet_err : out STD_LOGIC
);
END COMPONENT;
COMPONENT SyncBase
Generic (
kResetTo : std_logic := '0'; --value when reset and upon init
kStages : natural := 2); --double sync by default
PORT(
aReset : IN std_logic;
InClk : IN std_logic;
iIn : IN std_logic;
OutClk : IN std_logic;
oOut : OUT std_logic
);
END COMPONENT;
type state_type is (IDLE, SEND_ZERO_LENGTH_STATE, RESET_SETUP_RECEIVED);
signal state, next_state : state_type;
type PACKET_IN_BYTE_COUNT is array (11 downto 0) of std_logic_vector(12 downto 0);
signal u_Cnt_Bytes_Sent_Array : PACKET_IN_BYTE_COUNT;
signal reset : STD_LOGIC;
signal not_reset : STD_LOGIC;
signal not_axi_resetn : STD_LOGIC;
signal u_Send_NOPID_CMD : STD_LOGIC;
signal u_Send_PID_CMD : STD_LOGIC;
signal u_Send_EXTW_CMD : STD_LOGIC;
signal u_Send_REGW_CMD : STD_LOGIC;
signal u_Send_EXTR_CMD : STD_LOGIC;
signal u_Send_REGR_CMD : STD_LOGIC;
signal u_Send_STP_CMD : STD_LOGIC;
signal u_Send_Last : STD_LOGIC;
signal u_Send_Last_HSNegociation : STD_LOGIC;
signal u_Send_Last_PD : STD_LOGIC;
signal u_Tx_Pid : STD_LOGIC_VECTOR(3 downto 0);
signal u_Tx_Data : STD_LOGIC_VECTOR(7 downto 0);
signal u_Tx_Regw_Data : STD_LOGIC_VECTOR(7 downto 0);
signal u_Tx_Cmd_Done : STD_LOGIC;
signal u_Tx_Reg_Addr : STD_LOGIC_VECTOR(7 downto 0);
signal u_Tx_Data_HSNegociation : STD_LOGIC_VECTOR(7 downto 0);
signal u_Tx_Data_PD : STD_LOGIC_VECTOR(7 downto 0);
signal u_Tx_Data_En : STD_LOGIC;
signal u_Tx_Pid_Phase_Done : STD_LOGIC;
signal u_CRC16_En : STD_LOGIC;
signal u_Rx_Data : STD_LOGIC_VECTOR(7 downto 0);
signal u_Rx_Cmd_Received : STD_LOGIC;
signal u_RxEvent : STD_LOGIC_VECTOR(1 downto 0);
signal u_RxActive : STD_LOGIC;
signal u_Rx_Register_Data : STD_LOGIC_VECTOR(7 downto 0);
signal u_Rx_Register_Data_Received : STD_LOGIC;
signal u_Rx_Packet_Received : STD_LOGIC;
signal u_LineState : STD_LOGIC_VECTOR(1 downto 0);
signal u_Vbus : STD_LOGIC_VECTOR(1 downto 0);
signal u_Ulpi_Dir_Out : STD_LOGIC;
signal u_ID : STD_LOGIC;
signal u_Alt_Int : STD_LOGIC;
signal u_Negociation_Done : STD_LOGIC;
signal u_USB_Mode : STD_LOGIC;
signal packet_err : STD_LOGIC;
type u_Cnt_Bytes_Sent_iData_Array is array (MAX_NR_ENDP downto 0) of std_logic_vector(12 downto 0);
signal u_Cnt_Bytes_Sent_iData : u_Cnt_Bytes_Sent_iData_Array;
type a_Cnt_Bytes_Sent_oData_Array is array (MAX_NR_ENDP downto 0) of std_logic_vector(12 downto 0);
signal a_Cnt_Bytes_Sent_oData_Loc : a_Cnt_Bytes_Sent_oData_Array;
type u_Cnt_Bytes_Sent_iPush_Array is array (MAX_NR_ENDP downto 0) of std_logic;
signal u_Cnt_Bytes_Sent_iPush : u_Cnt_Bytes_Sent_iPush_Array;
type u_Cnt_Bytes_Sent_iRdy_Array is array (MAX_NR_ENDP downto 0) of std_logic;
signal u_Cnt_Bytes_Sent_iRdy : u_Cnt_Bytes_Sent_iRdy_Array;
type a_Cnt_Bytes_Sent_oValid_Array is array (MAX_NR_ENDP downto 0) of std_logic;
signal a_Cnt_Bytes_Sent_oValid_Loc : a_Cnt_Bytes_Sent_oValid_Array;
signal u_Cnt_Bytes_Sent : STD_LOGIC_VECTOR(12 downto 0);
signal u_Cnt_Bytes_Sent_Latch, u_Cnt_Bytes_Sent_Latch_q : STD_LOGIC;
signal u_ENDPTNAK_iData : std_logic_vector(31 downto 0);
signal a_ENDPTNAK_oValid : STD_LOGIC;
signal a_ENDPTNAK_Wr_En_q : STD_LOGIC;
signal u_ENDPTNAK_iPush : STD_LOGIC;
signal u_ENDPTNAK_iRdy : STD_LOGIC;
signal u_ENDPTSETUPSTAT_iData : std_logic_vector(31 downto 0);
signal a_ENDPTSETUPSTAT_Wr_En_q : std_logic;
signal u_ENDPTSETUPSTAT_iPush : STD_LOGIC;
signal u_ENDPTSETUPSTAT_iRdy : STD_LOGIC;
signal a_ENDPTSETUPSTAT_oValid : STD_LOGIC;
signal u_Setup_Received : STD_LOGIC;
signal u_Setup_Received_Rst : STD_LOGIC;
signal a_ENDPTSETUP_RECEIVED_Wr_En_qq, a_ENDPTSETUP_RECEIVED_Wr_En_q, a_ENDPTSETUP_RECEIVED_Wr_En_Loc : STD_LOGIC;
signal ENDPTSETUPSTAT_Hanshake_Rst, a_ENDPTSETUPSTAT_Hanshake_Rst : STD_LOGIC;
signal u_In_Packet_Complete_iData : std_logic_vector (31 downto 0);
signal u_In_Packet_Complete_iPush : std_logic;
signal u_In_Packet_Complete_iRdy : std_logic;
signal a_In_Packet_Complete_Set_En_q, a_In_Packet_Complete_Set_En_qq : std_logic;
signal a_Packet_In_Complete_Hanshake_Rst, Packet_In_Complete_Hanshake_Rst : std_logic;
signal a_In_Packet_Complete_Set_En_Loc : std_logic;
signal a_In_Packet_Complete_Wr_En_q : std_logic;
signal a_In_Packet_In_Complete_oValid : STD_LOGIC;
signal u_In_Packet_Complete : STD_LOGIC;
signal u_In_Packet_Complete_Rst : STD_LOGIC;
signal u_FRINDEX_iData : std_logic_vector(10 downto 0);
signal a_FRINDEX_Wr_En_q : std_logic;
signal a_FRINDEX_oValid : STD_LOGIC;
signal u_FRINDEX_iPush : STD_LOGIC;
signal u_FRINDEX_iRdy : STD_LOGIC;
signal u_SOF_Received : STD_LOGIC;
signal u_Frame_Index : STD_LOGIC_VECTOR(10 downto 0);
signal u_In_Token_Received : std_logic;
signal u_In_Token_Received_iData : std_logic_vector(31 downto 0);
signal a_In_Token_Received_Set_En_q, a_In_Token_Received_Set_En_qq, a_In_Token_Received_Set_En_Loc : STD_LOGIC;
signal u_In_Token_Received_iPush : STD_LOGIC;
signal u_In_Token_Received_iRdy : STD_LOGIC;
signal a_In_Token_Received_oValid : STD_LOGIC;
signal a_In_Token_Received_Hanshake_Rst, In_Token_Received_Hanshake_Rst : STD_LOGIC;
signal u_Send_Zero_Length_Packet_Clear_iData : std_logic_vector(31 downto 0);
signal u_Send_Zero_Length_Packet_Clear : std_logic;
signal u_Send_Zero_Length_Packet_Clear_iPush : std_logic;
signal u_Send_Zero_Length_Packet_Clear_iRdy : std_logic;
signal a_Send_Zero_Length_Packet_Clear_oValid : std_logic;
signal a_Send_Zero_Length_Packet_Clear_En_q, a_Send_Zero_Length_Packet_Clear_En_qq : std_logic;
signal a_Send_Zero_Length_Packet_Clear_En_Loc : std_logic;
signal Send_Zero_Length_Packet_Clear_Hanshake_Rst, a_Send_Zero_Length_Packet_Clear_Hanshake_Rst : std_logic;
signal u_Send_Zero_Length_Packet_Ack_iData, u_Send_Zero_Length_Packet_Ack_iData_q : std_logic_vector(31 downto 0);
signal u_Send_Zero_Length_Packet_Ack_iRdy : std_logic;
signal u_Send_Zero_Length_Packet_Ack_Set : STD_LOGIC;
signal u_Send_Zero_Length_Packet_Ack_iPush : std_logic;
signal a_Send_Zero_Length_Packet_Ack_oValid : STD_LOGIC;
signal a_Send_Zero_Length_Packet_Ack_Set_En_q, a_Send_Zero_Length_Packet_Ack_Set_En_qq : std_logic;
signal u_Send_Zero_Length_Packet : STD_LOGIC;
signal a_Send_Zero_Length_Packet_Ack_Set_En_Loc : std_logic;
signal a_Send_Zero_Length_Packet_Ack_Set_Hanshake_Rst, Send_Zero_Length_Packet_Ack_Set_Hanshake_Rst : std_logic;
signal u_Setup_Buffer_Bytes_3_0_iData : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal u_Setup_Buffer_Bytes_3_0_q : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal u_Setup_Buffer_Bytes_3_0_iPush : STD_LOGIC;
signal u_Setup_Buffer_Bytes_3_0_iRdy : STD_LOGIC;
signal a_Setup_Buffer_Bytes_3_0_oValid : STD_LOGIC;
signal u_Setup_Buffer_Bytes_7_4_iData : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal u_Setup_Buffer_Bytes_7_4_q : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal u_Setup_Buffer_Bytes_7_4_iPush : STD_LOGIC;
signal u_Setup_Buffer_Bytes_7_4_iRdy : STD_LOGIC;
signal a_Setup_Buffer_Bytes_7_4_oValid : STD_LOGIC;
signal u_NAK_Sent : STD_LOGIC;
signal u_USBSTS_NAKI_iData : std_logic_vector(0 downto 0);
signal a_USBSTS_NAKI_Wr_En_q : std_logic;
signal u_USBSTS_NAKI_iPush : std_logic;
signal u_USBSTS_NAKI_iRdy : std_logic;
signal a_USBSTS_NAKI_oValid : std_logic;
signal a_USBSTS_NAKI_Vector : STD_LOGIC_VECTOR(0 downto 0);
signal u_USBSTS_SLI_iData : std_logic_vector(0 downto 0);
signal u_USBSTS_SLI_iPush : std_logic;
signal u_USBSTS_SLI_iRdy : std_logic;
signal a_USBSTS_SLI_oValid : std_logic;
signal a_USBSTS_SLI_Vector : STD_LOGIC_VECTOR(0 downto 0);
signal a_USBSTS_SLI_Wr_En_q : std_logic;
signal u_Suspend_State, u_Suspend_State_q, u_Set_Suspend_State : STD_LOGIC;
signal u_Clear_Suspend_State, u_Set_Clear_Suspend_State, u_Set_Clear_Suspend_State_q : STD_LOGIC;
signal u_USBSTS_SRI_iData : std_logic_vector(0 downto 0);
signal u_USBSTS_SRI_iPush : std_logic;
signal u_USBSTS_SRI_iRdy : std_logic;
signal a_USBSTS_SRI_oValid : std_logic;
signal a_USBSTS_SRI_Vector : STD_LOGIC_VECTOR(0 downto 0);
signal a_USBSTS_SRI_Wr_En_q : std_logic;
signal u_USBSTS_URI_iData : std_logic_vector(0 downto 0);
signal u_USBSTS_URI_iPush : std_logic;
signal u_USBSTS_URI_iRdy : std_logic;
signal a_USBSTS_URI_oValid : std_logic;
signal a_USBSTS_URI_Vector : STD_LOGIC_VECTOR(0 downto 0);
signal a_USBSTS_URI_Wr_En_q : std_logic;
signal u_Reset_Received_Ulpi_q, u_Reset_Received, u_Reset_Received_Ulpi : STD_LOGIC;
signal u_USBSTS_PCI_iData : std_logic_vector(0 downto 0);
signal u_USBSTS_PCI_iPush : STD_LOGIC;
signal u_USBSTS_PCI_iRdy: STD_LOGIC;
signal a_USBSTS_PCI_oValid: STD_LOGIC;
signal a_USBSTS_PCI_Vector : STD_LOGIC_VECTOR(0 downto 0);
signal a_USBSTS_PCI_Wr_En_q : std_logic;
signal u_Port_Change_Detect : STD_LOGIC;
signal u_Wake : STD_LOGIC;
signal u_Set_Mode_FS : STD_LOGIC;
signal u_Set_Mode_HS : STD_LOGIC;
signal u_PORTSC1_iData : std_logic_vector(1 downto 0);
signal u_PORTSC1_iPush : STD_LOGIC;
signal u_PORTSC1_iRdy : STD_LOGIC;
signal a_PORTSC1_oValid : STD_LOGIC;
signal a_PORTSC1_PSPD_Wr_En_q : STD_LOGIC;
signal u_Not_Connected : STD_LOGIC;
signal u_Not_Connected_Pulse : STD_LOGIC;
signal u_Not_Connected_q : STD_LOGIC;
signal u_Resend_Set : STD_LOGIC;
signal u_Resend_iData : std_logic_vector (31 downto 0);
signal u_Resend_iPush : std_logic;
signal u_Resend_iRdy : std_logic;
signal a_Resend_Wr_En_q : std_logic;
signal a_Resend_oValid : STD_LOGIC;
signal u_Endpt_Nr_Loc : STD_LOGIC_VECTOR(4 downto 0);
signal u_iPush_Endpt_Nr, u_iPush_Endpt_Nr_PD, u_Endpt_Nr_oValid, u_Endpt_Nr_iRdy : STD_LOGIC;
signal pe_endpt_nr_int_4msb : integer range 0 to 12;
signal pe_endpt_nr_int : integer range 0 to 21;
signal pe_endpt_nr_index : integer range 0 to 27;
signal arb_endpt_nr_int_4msb : integer range 0 to 22;
signal a_Arb_Endpt_Nr_Int_4msb : integer range 0 to 22;
signal u_Arb_Endpt_Nr_Loc, a_Arb_Endpt_Nr_Loc: STD_LOGIC_VECTOR(4 downto 0);
signal u_Endp_Stall_PD : STD_LOGIC;
signal u_Endp_Type_PD : STD_LOGIC_VECTOR(1 downto 0);
signal state_ind_hs_loc : STD_LOGIC_VECTOR(4 downto 0);
signal ulpi_latency_comp_in, ulpi_latency_comp_out : STD_LOGIC;
-- attribute mark_debug : string;
-- attribute keep : string;
-- attribute mark_debug of u_Send_Zero_Length_Packet_Ack_iPush : signal is "true";
-- attribute keep of u_Send_Zero_Length_Packet_Ack_iPush : signal is "true";
--attribute mark_debug of u_In_Packet_Complete_iData : signal is "true";
--attribute keep of u_In_Packet_Complete_iData : signal is "true";
--attribute mark_debug of u_In_Packet_Complete_iPush : signal is "true";
--attribute keep of u_In_Packet_Complete_iPush : signal is "true";
--attribute mark_debug of u_In_Packet_Complete_iRdy : signal is "true";
--attribute keep of u_In_Packet_Complete_iRdy : signal is "true";
--attribute mark_debug of a_In_Packet_Complete_oData : signal is "true";
--attribute keep of a_In_Packet_Complete_oData : signal is "true";
--attribute mark_debug of a_In_Packet_Complete_Set_En : signal is "true";
--attribute keep of a_In_Packet_Complete_Set_En : signal is "true";
--attribute mark_debug of u_ENDPTSETUPSTAT_iData : signal is "true";
--attribute keep of u_ENDPTSETUPSTAT_iData : signal is "true";
--attribute mark_debug of a_ENDPTSETUP_RECEIVED_oData : signal is "true";
--attribute keep of a_ENDPTSETUP_RECEIVED_oData : signal is "true";
--attribute mark_debug of u_ENDPTSETUPSTAT_iPush : signal is "true";
--attribute keep of u_ENDPTSETUPSTAT_iPush : signal is "true";
--attribute mark_debug of ENDPTSETUPSTAT_Hanshake_Rst : signal is "true";
--attribute keep of ENDPTSETUPSTAT_Hanshake_Rst : signal is "true";
--attribute mark_debug of u_In_Token_Received_iData : signal is "true";
--attribute keep of u_In_Token_Received_iData : signal is "true";
--attribute mark_debug of u_In_Token_Received_iPush : signal is "true";
--attribute keep of u_In_Token_Received_iPush : signal is "true";
--attribute mark_debug of a_In_Token_Received_oValid : signal is "true";
--attribute keep of a_In_Token_Received_oValid : signal is "true";
--attribute mark_debug of a_In_Token_Received_oData : signal is "true";
--attribute keep of a_In_Token_Received_oData : signal is "true";
--attribute mark_debug of In_Token_Received_Hanshake_Rst : signal is "true";
--attribute keep of In_Token_Received_Hanshake_Rst : signal is "true";
--attribute mark_debug of u_Cnt_Bytes_Sent_iPush : signal is "true";
--attribute keep of u_Cnt_Bytes_Sent_iPush : signal is "true";
--attribute mark_debug of a_Cnt_Bytes_Sent_oData_Loc : signal is "true";
--attribute keep of a_Cnt_Bytes_Sent_oData_Loc : signal is "true";
begin
u_Endp_Nr <= u_Endpt_Nr_Loc;
not_reset <= not (reset);
reset <= u_ResetN;
not_axi_resetn <= not (axi_resetn);
u_Arb_Endpt_Nr_Loc <= u_Endp_Nr_Arb;
a_Arb_Endpt_Nr_Loc <= a_Arb_Endpt_Nr;
state_ind_hs <= state_ind_hs_loc;
led <= '1';
--Transmit data MUX. During speed negotiation HS_Negotiation controls the ULPI bus.
--Once negotiation is done, the Packet_Decoder controls the ULPI bus
u_Tx_Data <= u_Tx_Data_PD when u_Negociation_Done = '1'
else u_Tx_Data_HSNegociation;--reg_data;--
u_Send_Last <= u_Send_Last_PD when u_Negociation_Done = '1'
else u_Send_Last_HSNegociation;
-- This module handles ULPI transmissions (NOPID, PID, EXTW, REGW, EXTR, REGR)
-- and reception
Inst_ULPI: ULPI PORT MAP(
u_Ulpi_Data => u_Ulpi_Data,
Ulpi_Clk => Ulpi_Clk,
reset => reset,
u_Ulpi_Dir => u_Ulpi_Dir,
u_Ulpi_Nxt => u_Ulpi_Nxt,
u_Ulpi_Stp => u_Ulpi_Stp,
u_Ulpi_Reset => Ulpi_Reset,
u_Send_NOOP_CMD => '0',
u_Send_NOPID_CMD => u_Send_NOPID_CMD,
u_Send_PID_CMD => u_Send_PID_CMD,
u_Send_EXTW_CMD => u_Send_EXTW_CMD,
u_Send_REGW_CMD => u_Send_REGW_CMD,
u_Send_EXTR_CMD => u_Send_EXTR_CMD,
u_Send_REGR_CMD => u_Send_REGR_CMD,
u_Send_STP_CMD => u_Send_STP_CMD,
u_Send_Last => u_Send_Last,
u_Send_Err => '0',
u_Tx_Data => u_Tx_Data,
u_Tx_Data_En => u_Tx_Data_En,
u_Tx_Pid => u_Tx_Pid,
u_Tx_Regw_Data => u_Tx_Regw_Data,
u_Tx_Reg_Addr => u_Tx_Reg_Addr,
u_Tx_Cmd_Done => u_Tx_Cmd_Done,
u_CRC16_En => u_CRC16_En,
u_Tx_Pid_Phase_Done => u_Tx_Pid_Phase_Done,
u_Rx_Data => u_Rx_Data,
u_Rx_Packet_Received => u_Rx_Packet_Received,
u_Ulpi_Dir_Out => u_Ulpi_Dir_Out,
u_LineState => u_LineState,
u_Vbus => u_Vbus,
u_RxEvent => u_RxEvent,
u_RxActive => u_RxActive,
u_ID => u_ID,
u_Alt_Int => u_Alt_Int,
u_Rx_Cmd_Received => u_Rx_Cmd_Received,
state_ind => state_ind,
u_Rx_Register_Data => u_Rx_Register_Data,
u_Rx_Register_Data_Received => u_Rx_Register_Data_Received,
u_USB_Mode => u_USB_Mode
);
-- This module handles the USB speed negociatian, reset and suspend protocols
Inst_HS_Negotiation: HS_Negotiation PORT MAP(
u_Reset => reset,
Ulpi_Clk => Ulpi_Clk,
u_Send_NOPID_CMD => u_Send_NOPID_CMD,
u_Send_EXTW_CMD => u_Send_EXTW_CMD,
u_Send_REGW_CMD => u_Send_REGW_CMD,
u_Send_EXTR_CMD => u_Send_EXTR_CMD,
u_Send_REGR_CMD => u_Send_REGR_CMD,
u_Send_STP_CMD => u_Send_STP_CMD,
u_Send_Last => u_Send_Last_HSNegociation,
u_Remote_Wake => '0',
u_Rx_Cmd_Received => u_Rx_Cmd_Received,
u_LineState => u_LineState,
u_Vbus => u_Vbus,
u_Tx_Data => u_Tx_Data_HSNegociation,
u_Tx_Regw_Data => u_Tx_Regw_Data,
u_Tx_Cmd_Done => u_Tx_Cmd_Done,
u_Tx_Reg_Addr => u_Tx_Reg_Addr,
u_USB_Mode => u_USB_Mode,
u_Not_Connected => u_Not_Connected,
u_Set_Mode_HS => u_Set_Mode_HS,
u_Set_Mode_FS => u_Set_Mode_FS,
u_Wake => u_Wake,
u_USBCMD_RS => u_USBCMD_RS,
state_ind_hs => state_ind_hs_loc,
u_Negociation_Done => u_Negociation_Done
);
u_Endp_Stall_PD <= u_Endp_Stall(pe_endpt_nr_int);
u_Endp_Type_PD <= u_Endp_Type((pe_endpt_nr_int*2) + 1 downto pe_endpt_nr_int*2);
u_Send_Zero_Length_Packet <= u_Send_Zero_Length_Packet_Rd(pe_endpt_nr_index);
-- This module implements chapter 8 of the USB protocol
Inst_Packet_Decoder: Packet_Decoder PORT MAP(
Ulpi_Clk => Ulpi_Clk,
Axi_Clk => Axi_Clk,
reset => reset,
Axi_Resetn => Axi_Resetn,
a_Arb_Endpt_Nr => a_Arb_Endpt_Nr,
Tx_Fifo_S_Aresetn => Tx_Fifo_S_Aresetn,
a_Tx_Fifo_S_Aclk => a_Tx_Fifo_S_Aclk,
a_Tx_Fifo_S_Axis_Tvalid => a_Tx_Fifo_S_Axis_Tvalid,
a_Tx_Fifo_S_Axis_Tready => a_Tx_Fifo_S_Axis_Tready,
a_Tx_Fifo_S_Axis_Tdata => a_Tx_Fifo_S_Axis_Tdata,
a_Tx_Fifo_S_Axis_Tlast => a_Tx_Fifo_S_Axis_Tlast,
a_Tx_Fifo_S_Axis_Tkeep => a_Tx_Fifo_S_Axis_Tkeep,
a_Tx_Fifo_S_Axis_Tuser => a_Tx_Fifo_S_Axis_Tuser,
tx_fifo_axis_overflow => tx_fifo_axis_overflow,
tx_fifo_axis_underflow => tx_fifo_axis_underflow,
u_Rx_Fifo_s_Aclk => u_Rx_Fifo_s_Aclk,
u_Rx_Fifo_s_Axis_Tready => u_Rx_Fifo_s_Axis_Tready,
u_Rx_Fifo_s_Axis_Tvalid => u_Rx_Fifo_s_Axis_Tvalid,
u_Rx_Fifo_s_Axis_Tdata => u_Rx_Fifo_s_Axis_Tdata,
u_Rx_Fifo_s_Axis_Tkeep => u_Rx_Fifo_s_Axis_Tkeep,
u_Rx_Fifo_s_Axis_Tlast => u_Rx_Fifo_s_Axis_Tlast,
u_Rx_Fifo_Axis_Overflow => u_Rx_Fifo_Axis_Overflow,
u_Rx_Fifo_Axis_Underflow => u_Rx_Fifo_Axis_Underflow,
u_Command_Fifo_Rd_En => u_Command_Fifo_Rd_En,
u_Command_Fifo_Dout => u_Command_Fifo_Dout,
u_Command_Fifo_Empty => u_Command_Fifo_Empty,
u_Command_Fifo_Valid => u_Command_Fifo_Valid,
u_Setup_Buffer_Bytes_3_0 => u_Setup_Buffer_Bytes_3_0_iData,
u_Setup_Buffer_Bytes_7_4 => u_Setup_Buffer_Bytes_7_4_iData,
u_Send_PID_CMD => u_Send_PID_CMD,
u_Send_Last => u_Send_Last_PD,
u_Tx_Data => u_Tx_Data_PD,
u_Tx_Data_En => u_Tx_Data_En,
u_Tx_Pid => u_Tx_Pid,
u_Tx_Cmd_Done => u_Tx_Cmd_Done,
u_Tx_Pid_Phase_Done => u_Tx_Pid_Phase_Done,
u_CRC16_En_Ulpi => u_CRC16_En,
u_Rx_Data => u_Rx_Data,
u_Rx_Packet_Received => u_Rx_Packet_Received,
u_Ulpi_Dir_Out => u_Ulpi_Dir_Out,
u_RxEvent => u_RxEvent,
u_RxActive => u_RxActive,
u_USB_Mode => u_USB_Mode,
u_Setup_Received => u_Setup_Received,
u_Setup_Received_Rst => u_Setup_Received_Rst,
u_In_Token_Received => u_In_Token_Received,
u_In_Packet_Complete => u_In_Packet_Complete,
u_In_Packet_Complete_Rst => u_In_Packet_Complete_Rst,
u_Cnt_Bytes_Sent_Latch => u_Cnt_Bytes_Sent_Latch,
u_Cnt_Bytes_Sent => u_Cnt_Bytes_Sent,
u_Resend_Set => u_Resend_Set,
u_Endp_Nr => u_Endpt_Nr_Loc,
u_iPush_Endpt_Nr_PD => u_iPush_Endpt_Nr_PD,
u_Send_Zero_Length_Packet_Clear => u_Send_Zero_Length_Packet_Clear,
u_Send_Zero_Length_Packet => u_Send_Zero_Length_Packet,
u_Send_Zero_Length_Packet_Ack_Set => u_Send_Zero_Length_Packet_Ack_Set,
u_NAK_Sent => u_NAK_Sent,
u_Frame_Index => u_Frame_Index,
u_SOF_Received => u_SOF_Received,
u_USBADRA => u_USBADRA,
u_Endp_Type => u_Endp_Type_PD,
u_Endp_Stall => u_Endp_Stall_PD,
ulpi_latency_comp_out => ulpi_latency_comp_out,
state_ind_pd => state_ind_pd,
packet_err =>packet_err
);
--Synchronization modules for data that crosses the ULPI clock domain to AXI clock domain
u_iPush_Endpt_Nr <= u_iPush_Endpt_Nr_PD when (u_Endpt_Nr_iRdy = '1') else '0';
Inst_HandshakeData_pe_endpt_nr: entity work.HandshakeData
GENERIC MAP (
kDataWidth => 5)
PORT MAP(
InClk => Ulpi_Clk,
OutClk => Axi_Clk,
iData => u_Endpt_Nr_Loc,
oData => a_Endpt_Nr ,
iPush => u_iPush_Endpt_Nr,
iRdy => u_Endpt_Nr_iRdy,
oAck => u_Endpt_Nr_oValid,
oValid => u_Endpt_Nr_oValid,
aReset => not_axi_resetn
);
--------------------------------------------------------------------------------------------
pe_endpt_nr_int_4msb <= to_integer(unsigned(u_Endpt_Nr_Loc(4 downto 1)));
pe_endpt_nr_int <= to_integer(unsigned(u_Endpt_Nr_Loc));
arb_endpt_nr_int_4msb <= to_integer(unsigned(u_Arb_Endpt_Nr_Loc(4 downto 1)));
a_Arb_Endpt_Nr_Int_4msb <= to_integer(unsigned(a_Arb_Endpt_Nr_Loc(4 downto 1)));
DEFINE_INDEX_PROC: process (reset, u_Endpt_Nr_Loc, pe_endpt_nr_int_4msb)
begin
if (reset = '0') then
pe_endpt_nr_index <= 0;
else
if (u_Endpt_Nr_Loc(0) = '0') then
pe_endpt_nr_index <= pe_endpt_nr_int_4msb;
else
pe_endpt_nr_index <= pe_endpt_nr_int_4msb + 16;
end if;
end if;
end process;
MULTIPLE_HANDSHAKE : for i in 0 to MAX_NR_ENDP generate
Inst_HandshakeData_Count: entity work.HandshakeData
GENERIC MAP (
kDataWidth => 13)
PORT MAP(
InClk => Ulpi_Clk,
OutClk => Axi_Clk,
iData => u_Cnt_Bytes_Sent_iData(i),
oData => a_Cnt_Bytes_Sent_oData_Loc(i),
iPush => u_Cnt_Bytes_Sent_iPush(i),
iRdy => u_Cnt_Bytes_Sent_iRdy(i),
oAck => a_Cnt_Bytes_Sent_oValid_Loc(i),
oValid => a_Cnt_Bytes_Sent_oValid_Loc(i),
aReset => not_axi_resetn
);
end generate;
IN_PACKET_COUNTER_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Cnt_Bytes_Sent_iData <= (others => (others => '0'));
else
if (u_Cnt_Bytes_Sent_Latch = '1') then
u_Cnt_Bytes_Sent_iData(pe_endpt_nr_int_4msb) <= u_Cnt_Bytes_Sent;
end if;
end if;
end if;
end process;
IPUSH_COUNTER_PROC : process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Cnt_Bytes_Sent_iPush <= (others => '0');
u_Cnt_Bytes_Sent_Latch_q <= '0';
else
u_Cnt_Bytes_Sent_Latch_q <= u_Cnt_Bytes_Sent_Latch;
if ((u_Cnt_Bytes_Sent_Latch_q = '1') and (u_Cnt_Bytes_Sent_iRdy(pe_endpt_nr_int_4msb) = '1'))then
u_Cnt_Bytes_Sent_iPush(pe_endpt_nr_int_4msb) <= '1';
else
u_Cnt_Bytes_Sent_iPush(pe_endpt_nr_int_4msb) <= '0';
end if;
end if;
end if;
end process;
IN_TRANSF_CNT_OVALID_PROC : process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (axi_resetn = '0') then
a_Cnt_Bytes_Sent_oValid <= '0';
else
a_Cnt_Bytes_Sent_oValid <= a_Cnt_Bytes_Sent_oValid_Loc(a_Arb_Endpt_Nr_Int_4msb);
end if;
end if;
end process;
IN_TRANSF_CNT_ODATA_PROC : process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (axi_resetn = '0') then
a_Cnt_Bytes_Sent_oData <= (others => '0');
else
if (a_Cnt_Bytes_Sent_oValid_Loc(a_Arb_Endpt_Nr_Int_4msb) = '1') then
a_Cnt_Bytes_Sent_oData <= a_Cnt_Bytes_Sent_oData_Loc(a_Arb_Endpt_Nr_Int_4msb);
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------------
NAK_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_ENDPTNAK_iData <= (others => '0');
u_ENDPTNAK_iPush <= '0';
else
if (u_NAK_Sent = '1' and u_ENDPTNAK_iRdy = '1') then
u_ENDPTNAK_iData(pe_endpt_nr_index) <= '1';
u_ENDPTNAK_iPush <= '1';
else
u_ENDPTNAK_iData <= (others => '0');
u_ENDPTNAK_iPush <= '0';
end if;
end if;
end if;
end process;
ENDPTNAK_wr_en_PROC : process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (axi_resetn = '0') then
a_ENDPTNAK_Wr_En <= '0';
a_ENDPTNAK_Wr_En_q <= '0';
else
a_ENDPTNAK_Wr_En_q <= a_ENDPTNAK_oValid;
a_ENDPTNAK_Wr_En <= a_ENDPTNAK_oValid and (not a_ENDPTNAK_Wr_En_q);
end if;
end if;
end process;
Inst_HandshakeData_ENDPTNAK : entity work.HandshakeData
GENERIC MAP (
kDataWidth => 32)
PORT MAP(
InClk => Ulpi_Clk,
OutClk => Axi_Clk,
iData => u_ENDPTNAK_iData,
oData => a_ENDPTNAK_oData,
iPush => u_ENDPTNAK_iPush,
iRdy => u_ENDPTNAK_iRdy,
oAck => a_ENDPTNAK_oValid,
oValid => a_ENDPTNAK_oValid,
aReset => not_axi_resetn
);
-----------------------------------------------------------------------------------------------
ENDPTSETUPSTAT_PROC : process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Setup_Received_Rst <= '0';
u_ENDPTSETUPSTAT_iData <= (others => '0');
u_ENDPTSETUPSTAT_iPush <= '0';
else
if (u_Setup_Received = '1' and u_ENDPTSETUPSTAT_iRdy = '1') then
u_ENDPTSETUPSTAT_iData(pe_endpt_nr_index) <= '1';
u_ENDPTSETUPSTAT_iPush <= '1';
u_Setup_Received_Rst <= '0';
else
u_ENDPTSETUPSTAT_iData <= (others => '0');
u_Setup_Received_Rst <= '1';
u_ENDPTSETUPSTAT_iPush <= '0';
end if;
end if;
end if;
end process;
ENDPTSETUPSTAT_wr_en_PROC : process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (axi_resetn = '0') then
a_ENDPTSETUP_RECEIVED_Wr_En_Loc <= '0';
a_ENDPTSETUPSTAT_Wr_En_q <= '0';
a_ENDPTSETUP_RECEIVED_Wr_En_qq <= '0';
a_ENDPTSETUPSTAT_Hanshake_Rst <= '0';
a_ENDPTSETUP_RECEIVED_Wr_En_q <= '0';
else
a_ENDPTSETUPSTAT_Wr_En_q <= a_ENDPTSETUPSTAT_oValid;
a_ENDPTSETUP_RECEIVED_Wr_En_Loc <= a_ENDPTSETUPSTAT_oValid and (not a_ENDPTSETUPSTAT_Wr_En_q);
a_ENDPTSETUP_RECEIVED_Wr_En_q <= a_ENDPTSETUP_RECEIVED_Wr_En_Loc;
a_ENDPTSETUP_RECEIVED_Wr_En_qq <= a_ENDPTSETUP_RECEIVED_Wr_En_q;
a_ENDPTSETUPSTAT_Hanshake_Rst <= a_ENDPTSETUP_RECEIVED_Wr_En_qq;
end if;
end if;
end process;
ENDPTSETUPSTAT_Hanshake_Rst <= a_ENDPTSETUPSTAT_Hanshake_Rst or not_axi_resetn;
a_ENDPTSETUP_RECEIVED_Wr_En <= a_ENDPTSETUP_RECEIVED_Wr_En_Loc;
Inst_HandshakeData_ENDPTSETUPSTAT : entity work.HandshakeData
GENERIC MAP (
kDataWidth => 32)
PORT MAP(
InClk => Ulpi_Clk,
OutClk => Axi_Clk,
iData => u_ENDPTSETUPSTAT_iData,
oData => a_ENDPTSETUP_RECEIVED_oData,
iPush => u_ENDPTSETUPSTAT_iPush,
iRdy => u_ENDPTSETUPSTAT_iRdy,
oAck => a_ENDPTSETUPSTAT_oValid,
oValid => a_ENDPTSETUPSTAT_oValid,
aReset => ENDPTSETUPSTAT_Hanshake_Rst
);
------------------------------------------------------------------------------------------------
PACKET_IN_COMPLETE_PROC : process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_In_Packet_Complete_iData <= (others => '0');
u_In_Packet_Complete_iPush <= '0';
u_In_Packet_Complete_Rst <= '0';
else
if (u_In_Packet_Complete = '1' and u_In_Packet_Complete_iRdy = '1') then
u_In_Packet_Complete_iData(pe_endpt_nr_index) <= '1';
u_In_Packet_Complete_iPush <= '1';
u_In_Packet_Complete_Rst <= '0';
else
u_In_Packet_Complete_iData <= (others => '0');
u_In_Packet_Complete_Rst <= '1';
u_In_Packet_Complete_iPush <= '0';
end if;
end if;
end if;
end process;
packet_in_complete_wr_en_PROC : process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (axi_resetn = '0') then
a_In_Packet_Complete_Set_En_Loc <= '0';
a_In_Packet_Complete_Wr_En_q <= '0';
a_In_Packet_Complete_Set_En_q <= '0';
a_In_Packet_Complete_Set_En_qq <= '0';
a_Packet_In_Complete_Hanshake_Rst <= '0';
else
a_In_Packet_Complete_Wr_En_q <= a_In_Packet_In_Complete_oValid;
a_In_Packet_Complete_Set_En_Loc <= a_In_Packet_In_Complete_oValid and (not a_In_Packet_Complete_Wr_En_q);
a_In_Packet_Complete_Set_En_q <= a_In_Packet_Complete_Set_En_Loc;
a_In_Packet_Complete_Set_En_qq <= a_In_Packet_Complete_Set_En_q;
a_Packet_In_Complete_Hanshake_Rst <= a_In_Packet_Complete_Set_En_qq;
end if;
end if;
end process;
a_In_Packet_Complete_Set_En <= a_In_Packet_Complete_Set_En_Loc;
Packet_In_Complete_Hanshake_Rst <= a_Packet_In_Complete_Hanshake_Rst or not_axi_resetn;
Inst_HandshakeData_packet_in_complete : entity work.HandshakeData
GENERIC MAP (
kDataWidth => 32)
PORT MAP(
InClk => Ulpi_Clk,
OutClk => Axi_Clk,
iData => u_In_Packet_Complete_iData,
oData => a_In_Packet_Complete_oData,
iPush => (u_In_Packet_Complete_iPush and u_In_Packet_Complete_iRdy),
iRdy => u_In_Packet_Complete_iRdy,
oAck => a_In_Packet_In_Complete_oValid,
oValid => a_In_Packet_In_Complete_oValid,
aReset => Packet_In_Complete_Hanshake_Rst
);
-----------------------------------------------------------------------------------------------------
FRINDEX_PROC : process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_FRINDEX_iData <= (others => '0');
u_FRINDEX_iPush <= '0';
else
if (u_SOF_Received = '1' and u_FRINDEX_iRdy = '1') then
u_FRINDEX_iData(10 downto 0) <= u_Frame_Index;
u_FRINDEX_iPush <= '1';
else
u_FRINDEX_iPush <= '0';
end if;
end if;
end if;
end process;
FRINDEX_wr_en_PROC : process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (axi_resetn = '0') then
a_FRINDEX_Wr_En <= '0';
a_FRINDEX_Wr_En_q <= '0';
else
a_FRINDEX_Wr_En_q <= a_FRINDEX_oValid;
a_FRINDEX_Wr_En <= a_FRINDEX_oValid and (not a_FRINDEX_Wr_En_q);
end if;
end if;
end process;
Inst_HandshakeData_FRINDEX : entity work.HandshakeData
GENERIC MAP (
kDataWidth => 11)
PORT MAP(
InClk => Ulpi_Clk,
OutClk => Axi_Clk,
iData => u_FRINDEX_iData,
oData => a_FRINDEX_oData,
iPush => u_FRINDEX_iPush,
iRdy => u_FRINDEX_iRdy,
oAck => a_FRINDEX_oValid,
oValid => a_FRINDEX_oValid,
aReset => not_axi_resetn
);
---------------------------------------------------------------------------------------------------------
IN_TOKEN_RECEIVED_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_In_Token_Received_iData <= (others => '0');
u_In_Token_Received_iPush <= '0';
else
u_In_Token_Received_iPush <= u_In_Token_Received and u_In_Token_Received_iRdy;
if (u_In_Token_Received = '1') then
u_In_Token_Received_iData(pe_endpt_nr_index) <= '1';
else
u_In_Token_Received_iData <= (others => '0');
end if;
end if;
end if;
end process;
in_token_received_set_en_PROC : process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (axi_resetn = '0') then
a_In_Token_Received_Set_En_Loc <= '0';
a_In_Token_Received_Set_En_qq <= '0';
a_In_Token_Received_Set_En_q <= '0';
a_In_Token_Received_Hanshake_Rst <= '0';
else
a_In_Token_Received_Set_En_q <= a_In_Token_Received_oValid;
a_In_Token_Received_Set_En_Loc <= a_In_Token_Received_oValid and (not a_In_Token_Received_Set_En_q);
a_In_Token_Received_Set_En_qq <= a_In_Token_Received_Set_En_Loc;
a_In_Token_Received_Hanshake_Rst <= a_In_Token_Received_Set_En_qq;
end if;
end if;
end process;
a_In_Token_Received_Set_En <= a_In_Token_Received_Set_En_Loc;
In_Token_Received_Hanshake_Rst <= a_In_Token_Received_Hanshake_Rst or not_axi_resetn;
Inst_HandshakeData_in_token_received : entity work.HandshakeData
GENERIC MAP (
kDataWidth => 32)
PORT MAP(
InClk => Ulpi_Clk,
OutClk => Axi_Clk,
iData => u_In_Token_Received_iData,
oData => a_In_Token_Received_oData,
iPush => u_In_Token_Received_iPush,
iRdy => u_In_Token_Received_iRdy,
oAck => a_In_Token_Received_oValid,
oValid => a_In_Token_Received_oValid,
aReset => In_Token_Received_Hanshake_Rst
);
-----------------------------------------------------------------------------------------------------------
SEND_ZERO_LENGTH_PROC : process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Send_Zero_Length_Packet_Clear_iData <= (others => '1');
u_Send_Zero_Length_Packet_Clear_iPush <= '0';
else
if (u_Send_Zero_Length_Packet_Clear = '1') then
u_Send_Zero_Length_Packet_Clear_iData(pe_endpt_nr_index) <= '0';
u_Send_Zero_Length_Packet_Clear_iPush <= '1';
else
u_Send_Zero_Length_Packet_Clear_iData <= (others => '1');
u_Send_Zero_Length_Packet_Clear_iPush <= '0';
end if;
end if;
end if;
end process;
send_zero_length_packet_clear_en_PROC : process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (axi_resetn = '0') then
a_Send_Zero_Length_Packet_Clear_En_Loc <= '0';
a_Send_Zero_Length_Packet_Clear_En_qq <= '0';
a_Send_Zero_Length_Packet_Clear_En_q <= '0';
a_Send_Zero_Length_Packet_Clear_Hanshake_Rst <= '0';
else
a_Send_Zero_Length_Packet_Clear_En_q <= a_In_Token_Received_oValid;
a_Send_Zero_Length_Packet_Clear_En_Loc <= a_Send_Zero_Length_Packet_Clear_oValid and (not a_Send_Zero_Length_Packet_Clear_En_q);
a_Send_Zero_Length_Packet_Clear_En_qq <= a_Send_Zero_Length_Packet_Clear_En_Loc;
a_Send_Zero_Length_Packet_Clear_Hanshake_Rst <= a_Send_Zero_Length_Packet_Clear_Hanshake_Rst;
end if;
end if;
end process;
a_Send_Zero_Length_Packet_Clear_En <= a_Send_Zero_Length_Packet_Clear_En_Loc;
Send_Zero_Length_Packet_Clear_Hanshake_Rst <= a_Send_Zero_Length_Packet_Clear_Hanshake_Rst or not_axi_resetn;
Inst_HandshakeData_zero_length_clear: entity work.HandshakeData
GENERIC MAP (
kDataWidth => 32)
PORT MAP(
InClk => Ulpi_Clk,
OutClk => Axi_Clk,
iData => u_Send_Zero_Length_Packet_Clear_iData,
oData => a_Send_Zero_Length_Packet_Clear_oData ,
iPush => (u_Send_Zero_Length_Packet_Clear_iPush and u_Send_Zero_Length_Packet_Clear_iRdy),
iRdy => u_Send_Zero_Length_Packet_Clear_iRdy,
oAck => a_Send_Zero_Length_Packet_Clear_oValid,
oValid => a_Send_Zero_Length_Packet_Clear_oValid,
aReset => Send_Zero_Length_Packet_Clear_Hanshake_Rst
);
-------------------------------------------------------------------------------------------------------------
SEND_ZERO_LENGTH_ACK_PROC : process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Send_Zero_Length_Packet_Ack_iData <= (others => '0');
else
if (u_Send_Zero_Length_Packet_Ack_Set = '1') then
u_Send_Zero_Length_Packet_Ack_iData(pe_endpt_nr_index) <= '1';
else
u_Send_Zero_Length_Packet_Ack_iData <= (others => '0');
end if;
end if;
end if;
end process;
IPUSH_SEND_ZERO_LENGTH_ACK_PROC : process (Ulpi_Clk)
begin
if (Ulpi_Clk'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Send_Zero_Length_Packet_Ack_iPush <= '0';
u_Send_Zero_Length_Packet_Ack_iData_q <= (others => '0');
else
u_Send_Zero_Length_Packet_Ack_iData_q <= u_Send_Zero_Length_Packet_Ack_iData;
if (u_Send_Zero_Length_Packet_Ack_iData /= u_Send_Zero_Length_Packet_Ack_iData_q and u_Send_Zero_Length_Packet_Ack_iRdy = '1') then
u_Send_Zero_Length_Packet_Ack_iPush <= '1';
else
u_Send_Zero_Length_Packet_Ack_iPush <= '0';
end if;
end if;
end if;
end process;
Send_Zero_Length_Packet_Ack_Set_En_PROC : process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (axi_resetn = '0') then
a_Send_Zero_Length_Packet_Ack_Set_En_Loc <= '0';
a_Send_Zero_Length_Packet_Ack_Set_En_qq <= '0';
a_Send_Zero_Length_Packet_Ack_Set_En_q <= '0';
a_Send_Zero_Length_Packet_Ack_Set_Hanshake_Rst <= '0';
else
a_Send_Zero_Length_Packet_Ack_Set_En_q <= a_Send_Zero_Length_Packet_Ack_oValid;
a_Send_Zero_Length_Packet_Ack_Set_En_Loc <= a_Send_Zero_Length_Packet_Ack_oValid and (not a_Send_Zero_Length_Packet_Ack_Set_En_q);
a_Send_Zero_Length_Packet_Ack_Set_En_qq <= a_Send_Zero_Length_Packet_Ack_Set_En_Loc;
a_Send_Zero_Length_Packet_Ack_Set_Hanshake_Rst <= a_Send_Zero_Length_Packet_Ack_Set_En_qq;
end if;
end if;
end process;
a_Send_Zero_Length_Packet_Ack_Set_En <= a_Send_Zero_Length_Packet_Ack_Set_En_Loc;
Send_Zero_Length_Packet_Ack_Set_Hanshake_Rst <= a_Send_Zero_Length_Packet_Ack_Set_Hanshake_Rst or not_axi_resetn;
Inst_HandshakeData_zero_length_ack: entity work.HandshakeData
GENERIC MAP (
kDataWidth => 32)
PORT MAP(
InClk => Ulpi_Clk,
OutClk => Axi_Clk,
iData => u_Send_Zero_Length_Packet_Ack_iData,
oData => a_Send_Zero_Length_Packet_Ack_oData ,
iPush => u_Send_Zero_Length_Packet_Ack_iPush,
iRdy => u_Send_Zero_Length_Packet_Ack_iRdy,
oAck => a_Send_Zero_Length_Packet_Ack_oValid,
oValid => a_Send_Zero_Length_Packet_Ack_oValid,
aReset => Send_Zero_Length_Packet_Ack_Set_Hanshake_Rst
);
----------------------------------------------------------------------------------------------------------------
IPUSH_pe_SETUP_BUFFER_BYTES_3_0_PROC : process (Ulpi_Clk)
begin
if (Ulpi_Clk'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Setup_Buffer_Bytes_3_0_iPush <= '0';
u_Setup_Buffer_Bytes_3_0_q <= (others => '0');
else
u_Setup_Buffer_Bytes_3_0_q <= u_Setup_Buffer_Bytes_3_0_iData;
if (u_Setup_Buffer_Bytes_3_0_iData /= u_Setup_Buffer_Bytes_3_0_q and u_Setup_Buffer_Bytes_3_0_iRdy = '1') then
u_Setup_Buffer_Bytes_3_0_iPush <= '1';
else
u_Setup_Buffer_Bytes_3_0_iPush <= '0';
end if;
end if;
end if;
end process;
Inst_HandshakeData_SETUP_BUFFER_BYTES_3_0 : entity work.HandshakeData
GENERIC MAP (
kDataWidth => 32)
PORT MAP(
InClk => Ulpi_Clk,
OutClk => Axi_Clk,
iData => u_Setup_Buffer_Bytes_3_0_iData,
oData => a_Setup_Buffer_Bytes_3_0_oData,
iPush => u_Setup_Buffer_Bytes_3_0_iPush,
iRdy => u_Setup_Buffer_Bytes_3_0_iRdy,
oAck => a_Setup_Buffer_Bytes_3_0_oValid,
oValid => a_Setup_Buffer_Bytes_3_0_oValid,
aReset => not_axi_resetn
);
----------------------------------------------------------------------------------------------------------------
IPUSH_pe_SETUP_BUFFER_BYTES_7_4_PROC : process (Ulpi_Clk)
begin
if (Ulpi_Clk'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Setup_Buffer_Bytes_7_4_iPush <= '0';
u_Setup_Buffer_Bytes_7_4_q <= (others => '0');
else
u_Setup_Buffer_Bytes_7_4_q <= u_Setup_Buffer_Bytes_7_4_iData;
if (u_Setup_Buffer_Bytes_7_4_iData /= u_Setup_Buffer_Bytes_7_4_q and u_Setup_Buffer_Bytes_7_4_iRdy = '1') then
u_Setup_Buffer_Bytes_7_4_iPush <= '1';
else
u_Setup_Buffer_Bytes_7_4_iPush <= '0';
end if;
end if;
end if;
end process;
Inst_HandshakeData_pe_SETUP_BUFFER_BYTES_7_4 : entity work.HandshakeData
GENERIC MAP (
kDataWidth => 32)
PORT MAP(
InClk => Ulpi_Clk,
OutClk => Axi_Clk,
iData => u_Setup_Buffer_Bytes_7_4_iData,
oData => a_Setup_Buffer_Bytes_7_4_oData,
iPush => u_Setup_Buffer_Bytes_7_4_iPush,
iRdy => u_Setup_Buffer_Bytes_7_4_iRdy,
oAck => a_Setup_Buffer_Bytes_7_4_oValid,
oValid => a_Setup_Buffer_Bytes_7_4_oValid,
aReset => not_axi_resetn
);
----------------------------------------------------------------------------------------------------------------
USBSTS_NAKI_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_USBSTS_NAKI_iData <= "0";
u_USBSTS_NAKI_iPush <= '0';
else
if (u_NAK_Sent = '1' and u_USBSTS_NAKI_iRdy = '1') then
u_USBSTS_NAKI_iData <= "1";
u_USBSTS_NAKI_iPush <= '1';
else
u_USBSTS_NAKI_iPush <= '0';
end if;
end if;
end if;
end process;
USBSTS_wr_en_NAK_PROC : process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (axi_resetn = '0') then
a_USBSTS_NAKI_Wr_En <= '0';
a_USBSTS_NAKI_Wr_En_q <= '0';
else
a_USBSTS_NAKI_Wr_En_q <= a_USBSTS_NAKI_oValid;
a_USBSTS_NAKI_Wr_En <= a_USBSTS_NAKI_oValid and (not a_USBSTS_NAKI_Wr_En_q);
end if;
end if;
end process;
Inst_HandshakeData_NAKI : entity work.HandshakeData
GENERIC MAP (
kDataWidth => 1)
PORT MAP(
InClk => Ulpi_Clk,
OutClk => Axi_Clk,
iData => u_USBSTS_NAKI_iData,
oData => a_USBSTS_NAKI_Vector,
iPush => u_USBSTS_NAKI_iPush,
iRdy => u_USBSTS_NAKI_iRdy,
oAck => a_USBSTS_NAKI_oValid,
oValid => a_USBSTS_NAKI_oValid,
aReset => not_axi_resetn
);
a_USBSTS_NAKI_oData <= a_USBSTS_NAKI_Vector(0);
----------------------------------------------------------------------------------------------------------------
SET_CLEAR_SUSPEND_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Set_Suspend_State <= '0';
u_Set_Clear_Suspend_State <= '0';
u_Reset_Received_Ulpi <= '0';
else
if (state_ind_hs_loc = "10010") then
u_Set_Suspend_State <= '1';
u_Set_Clear_Suspend_State <= '0';
u_Reset_Received_Ulpi <= '0';
else
u_Set_Suspend_State <= '0';
u_Set_Clear_Suspend_State <= '1';
if(state_ind_hs_loc = "01000") then
u_Reset_Received_Ulpi <= '1';
else
u_Reset_Received_Ulpi <= '0';
end if;
end if;
end if;
end if;
end process;
SET_SUSPEND_PROC : process (Ulpi_Clk)
begin
if (Ulpi_Clk'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Suspend_State <= '0';
u_Suspend_State_q <= '0';
else
u_Suspend_State_q <= u_Set_Suspend_State;
u_Suspend_State <= u_Set_Suspend_State and (not u_Suspend_State_q);
end if;
end if;
end process;
CLEAR_SUSPEND_PROC : process (Ulpi_Clk)
begin
if (Ulpi_Clk'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Clear_Suspend_State <= '0';
u_Set_Clear_Suspend_State_q <= '0';
else
u_Set_Clear_Suspend_State_q <= u_Set_Clear_Suspend_State;
u_Clear_Suspend_State <= u_Set_Clear_Suspend_State and (not u_Set_Clear_Suspend_State_q);
end if;
end if;
end process;
USBSTS_SLI_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_USBSTS_SLI_iData <= "0";
u_USBSTS_SLI_iPush <= '0';
else
if (u_Suspend_State = '1' and u_USBSTS_SLI_iRdy = '1') then
u_USBSTS_SLI_iData <= "1";
u_USBSTS_SLI_iPush <= '1';
elsif (u_Clear_Suspend_State = '1' and u_USBSTS_SLI_iRdy = '1') then
u_USBSTS_SLI_iData <= "1";
u_USBSTS_SLI_iPush <= '1';
else
u_USBSTS_SLI_iPush <= '0';
end if;
end if;
end if;
end process;
USBSTS_wr_en_SLI_PROC : process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (axi_resetn = '0') then
a_USBSTS_SLI_Wr_En <= '0';
a_USBSTS_SLI_Wr_En_q <= '0';
else
a_USBSTS_SLI_Wr_En_q <= a_USBSTS_SLI_oValid;
a_USBSTS_SLI_Wr_En <= a_USBSTS_SLI_oValid and (not a_USBSTS_SLI_Wr_En_q);
end if;
end if;
end process;
Inst_HandshakeData_SLI: entity work.HandshakeData
GENERIC MAP (
kDataWidth => 1)
PORT MAP(
InClk => Ulpi_Clk,
OutClk => Axi_Clk,
iData => u_USBSTS_SLI_iData,
oData => a_USBSTS_SLI_Vector,
iPush => u_USBSTS_SLI_iPush,
iRdy => u_USBSTS_SLI_iRdy,
oAck => a_USBSTS_SLI_oValid,
oValid => a_USBSTS_SLI_oValid,
aReset => not_axi_resetn
);
a_USBSTS_SLI_oData <= a_USBSTS_SLI_Vector(0);
------------------------------------------------------------------------------------------------------------------------------------
USBSTS_SRI_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_USBSTS_SRI_iData <= "0";
u_USBSTS_SRI_iPush <= '0';
else
if (u_SOF_Received = '1' and u_USBSTS_SRI_iRdy = '1') then
u_USBSTS_SRI_iData <= "1";
u_USBSTS_SRI_iPush <= '1';
else
u_USBSTS_SRI_iPush <= '0';
end if;
end if;
end if;
end process;
USBSTS_wr_en_SRI_PROC : process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (axi_resetn = '0') then
a_USBSTS_SRI_Wr_En <= '0';
a_USBSTS_SRI_Wr_En_q <= '0';
else
a_USBSTS_SRI_Wr_En_q <= a_USBSTS_SRI_oValid;
a_USBSTS_SRI_Wr_En <= a_USBSTS_SRI_oValid and (not a_USBSTS_SRI_Wr_En_q);
end if;
end if;
end process;
Inst_HandshakeData_SRI: entity work.HandshakeData
GENERIC MAP (
kDataWidth => 1)
PORT MAP(
InClk => Ulpi_Clk,
OutClk => Axi_Clk,
iData => u_USBSTS_SRI_iData,
oData => a_USBSTS_SRI_Vector,
iPush => u_USBSTS_SRI_iPush,
iRdy => u_USBSTS_SRI_iRdy,
oAck => a_USBSTS_SRI_oValid,
oValid => a_USBSTS_SRI_oValid,
aReset => not_axi_resetn
);
a_USBSTS_SRI_oData <= a_USBSTS_SRI_Vector(0);
--------------------------------------------------------------------------------------------------------------------------------------
USBSTS_URI_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_USBSTS_URI_iData <= "0";
u_USBSTS_URI_iPush <= '0';
else
if (u_Reset_Received = '1' and u_USBSTS_URI_iRdy = '1') then
u_USBSTS_URI_iData <= "1";
u_USBSTS_URI_iPush <= '1';
else
u_USBSTS_URI_iPush <= '0';
end if;
end if;
end if;
end process;
RESET_RECEIVED_PROC : process (Ulpi_Clk)
begin
if (Ulpi_Clk'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Reset_Received <= '0';
u_Reset_Received_Ulpi_q <= '0';
else
u_Reset_Received_Ulpi_q <= u_Reset_Received_Ulpi;
u_Reset_Received <= u_Reset_Received_Ulpi and (not u_Reset_Received_Ulpi_q);
end if;
end if;
end process;
USBSTS_wr_en_URI_PROC : process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (axi_resetn = '0') then
a_USBSTS_URI_Wr_En <= '0';
a_USBSTS_URI_Wr_En_q <= '0';
else
a_USBSTS_URI_Wr_En_q <= a_USBSTS_URI_oValid;
a_USBSTS_URI_Wr_En <= a_USBSTS_URI_oValid and (not a_USBSTS_URI_Wr_En_q);
end if;
end if;
end process;
Inst_HandshakeData_URI: entity work.HandshakeData
GENERIC MAP (
kDataWidth => 1)
PORT MAP(
InClk => Ulpi_Clk,
OutClk => Axi_Clk,
iData => u_USBSTS_URI_iData,
oData => a_USBSTS_URI_Vector,
iPush => u_USBSTS_URI_iPush,
iRdy => u_USBSTS_URI_iRdy,
oAck => a_USBSTS_URI_oValid,
oValid => a_USBSTS_URI_oValid,
aReset => not_axi_resetn
);
a_USBSTS_URI_oData <= a_USBSTS_URI_Vector(0);
--------------------------------------------------------------------------------------------------------------------------------------
u_Port_Change_Detect <= u_Wake or u_Set_Mode_HS or u_Set_Mode_FS;
USBSTS_PCI_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_USBSTS_PCI_iData <= "0";
u_USBSTS_PCI_iPush <= '0';
else
if (u_Port_Change_Detect = '1' and u_USBSTS_PCI_iRdy = '1') then --resume signaling or port enters high speed or full speed mode
u_USBSTS_PCI_iData <= "1";
u_USBSTS_PCI_iPush <= '1';
else
u_USBSTS_PCI_iPush <= '0';
end if;
end if;
end if;
end process;
USBSTS_wr_en_PCI_PROC : process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (axi_resetn = '0') then
a_USBSTS_PCI_Wr_En <= '0';
a_USBSTS_PCI_Wr_En_q <= '0';
else
a_USBSTS_PCI_Wr_En_q <= a_USBSTS_PCI_oValid;
a_USBSTS_PCI_Wr_En <= a_USBSTS_PCI_oValid and (not a_USBSTS_PCI_Wr_En_q);
end if;
end if;
end process;
Inst_HandshakeData_PCI : entity work.HandshakeData
GENERIC MAP (
kDataWidth => 1)
PORT MAP(
InClk => Ulpi_Clk,
OutClk => Axi_Clk,
iData => u_USBSTS_PCI_iData,
oData => a_USBSTS_PCI_Vector,
iPush => u_USBSTS_PCI_iPush,
iRdy => u_USBSTS_PCI_iRdy,
oAck => a_USBSTS_PCI_oValid,
oValid => a_USBSTS_PCI_oValid,
aReset => not_axi_resetn
);
a_USBSTS_PCI_oData <= a_USBSTS_PCI_Vector(0);
------------------------------------------------------------------------------------------------------------------------------------------
URESEND_IDATA_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Resend_iData <= (others => '0');
u_Resend_iPush <= '0';
else
if (u_Resend_Set = '1' and u_Resend_iRdy = '1') then --resume signaling or port enters high speed or full speed mode
u_Resend_iData(pe_endpt_nr_index) <= '1';
u_Resend_iPush <= '1';
else
u_Resend_iPush <= '0';
u_Resend_iData <= (others => '0');
end if;
end if;
end if;
end process;
RESEND_WR_EN_PROC : process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (axi_resetn = '0') then
a_Resend_Wr_En <= '0';
a_Resend_Wr_En_q <= '0';
else
a_Resend_Wr_En_q <= a_Resend_oValid;
a_Resend_Wr_En <= a_Resend_oValid and (not a_Resend_Wr_En_q);
end if;
end if;
end process;
Inst_HandshakeData_Resend : entity work.HandshakeData
GENERIC MAP (
kDataWidth => 32)
PORT MAP(
InClk => Ulpi_Clk,
OutClk => Axi_Clk,
iData => u_Resend_iData,
oData => a_Resend_oData,
iPush => u_Resend_iPush,
iRdy => u_Resend_iRdy,
oAck => a_Resend_oValid,
oValid => a_Resend_oValid,
aReset => not_axi_resetn
);
------------------------------------------------------------------------------------------------------------------------------------------
PORTSC1_PSPD_PROC: process (Ulpi_Clk)
begin
if (Ulpi_Clk 'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_PORTSC1_iData <= "00";
u_PORTSC1_iPush <= '0';
else
if (u_Not_Connected = '1') then
if (u_Not_Connected_Pulse = '1' and u_PORTSC1_iRdy = '1') then
u_PORTSC1_iData <= "11";
u_PORTSC1_iPush <= '1';
end if;
else
if (u_Set_Mode_HS = '1' and u_PORTSC1_iRdy = '1') then
u_PORTSC1_iData <= "10";
u_PORTSC1_iPush <= '1';
elsif (u_Set_Mode_FS = '0' and u_Not_Connected = '0' and u_PORTSC1_iRdy = '1')then
u_PORTSC1_iData <= "01";
u_PORTSC1_iPush <= '1';
else
u_PORTSC1_iPush <= '0';
end if;
end if;
end if;
end if;
end process;
PORTSC1_PSPD_wr_en_PROC : process (Axi_Clk)
begin
if (Axi_Clk'event and Axi_Clk = '1') then
if (axi_resetn = '0') then
a_PORTSC1_PSPD_Wr_En <= '0';
a_PORTSC1_PSPD_Wr_En_q <= '0';
else
a_PORTSC1_PSPD_Wr_En_q <= a_PORTSC1_oValid;
a_PORTSC1_PSPD_Wr_En <= a_PORTSC1_oValid and (not a_PORTSC1_PSPD_Wr_En_q);
end if;
end if;
end process;
Inst_HandshakeData_PORTSC1: entity work.HandshakeData
GENERIC MAP (
kDataWidth => 2)
PORT MAP(
InClk => Ulpi_Clk,
OutClk => Axi_Clk,
iData => u_PORTSC1_iData,
oData => a_PORTSC1_PSPD_oData,
iPush => u_PORTSC1_iPush,
iRdy => u_PORTSC1_iRdy,
oAck => a_PORTSC1_oValid,
oValid => a_PORTSC1_oValid,
aReset => not_axi_resetn
);
NOT_CONNECTED_PROC : process (Ulpi_Clk)
begin
if (Ulpi_Clk'event and Ulpi_Clk = '1') then
if (reset = '0') then
u_Not_Connected_Pulse <= '0';
u_Not_Connected_q <= '0';
else
u_Not_Connected_q <= u_Not_Connected;
u_Not_Connected_Pulse <= u_Not_Connected and (not u_Not_Connected_q);
end if;
end if;
end process;
end Behavioral;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: various
-- File: memory_inferred.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: Behavioural memory generators
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity generic_syncram is
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
write : in std_ulogic
);
end;
architecture behavioral of generic_syncram is
type mem is array(0 to (2**abits -1))
of std_logic_vector((dbits -1) downto 0);
signal memarr : mem;
signal ra : std_logic_vector((abits -1) downto 0);
begin
main : process(clk)
begin
if rising_edge(clk) then
if write = '1' then
memarr(conv_integer(address)) <= datain;
end if;
ra <= address;
end if;
end process;
dataout <= memarr(conv_integer(ra));
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity generic_syncram_reg is
generic ( abits : integer := 10; dbits : integer := 8 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
write : in std_ulogic
);
end;
architecture behavioral of generic_syncram_reg is
type mem is array(0 to (2**abits -1))
of std_logic_vector((dbits -1) downto 0);
signal memarr : mem;
signal ra : std_logic_vector((abits -1) downto 0);
attribute syn_ramstyle : string;
attribute syn_ramstyle of memarr : signal is "registers";
begin
main : process(clk)
begin
if rising_edge(clk) then
if write = '1' then
memarr(conv_integer(address)) <= datain;
end if;
ra <= address;
end if;
end process;
dataout <= memarr(conv_integer(ra));
end;
-- synchronous 2-port ram, common clock
LIBRARY ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity generic_syncram_2p is
generic (
abits : integer := 8;
dbits : integer := 32;
sepclk: integer := 0
);
port (
rclk : in std_ulogic;
wclk : in std_ulogic;
rdaddress: in std_logic_vector (abits -1 downto 0);
wraddress: in std_logic_vector (abits -1 downto 0);
data: in std_logic_vector (dbits -1 downto 0);
wren : in std_ulogic;
q: out std_logic_vector (dbits -1 downto 0)
);
end;
architecture behav of generic_syncram_2p is
type dregtype is array (0 to 2**abits - 1)
of std_logic_vector(dbits -1 downto 0);
signal rfd : dregtype;
begin
wp : process(wclk)
begin
if rising_edge(wclk) then
if wren = '1' then rfd(conv_integer(wraddress)) <= data; end if;
end if;
end process;
oneclk : if sepclk = 0 generate
rp : process(wclk) begin
if rising_edge(wclk) then q <= rfd(conv_integer(rdaddress)); end if;
end process;
end generate;
twoclk : if sepclk = 1 generate
rp : process(rclk) begin
if rising_edge(rclk) then q <= rfd(conv_integer(rdaddress)); end if;
end process;
end generate;
end;
-- synchronous 2-port ram, common clock, flip-flops
LIBRARY ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity generic_syncram_2p_reg is
generic (
abits : integer := 8;
dbits : integer := 32;
sepclk: integer := 0
);
port (
rclk : in std_ulogic;
wclk : in std_ulogic;
rdaddress: in std_logic_vector (abits -1 downto 0);
wraddress: in std_logic_vector (abits -1 downto 0);
data: in std_logic_vector (dbits -1 downto 0);
wren : in std_ulogic;
q: out std_logic_vector (dbits -1 downto 0)
);
end;
architecture behav of generic_syncram_2p_reg is
type dregtype is array (0 to 2**abits - 1)
of std_logic_vector(dbits -1 downto 0);
signal rfd : dregtype;
signal wa, ra : std_logic_vector (abits -1 downto 0);
attribute syn_ramstyle : string;
attribute syn_ramstyle of rfd : signal is "registers";
begin
wp : process(wclk)
begin
if rising_edge(wclk) then
if wren = '1' then rfd(conv_integer(wraddress)) <= data; end if;
end if;
end process;
oneclk : if sepclk = 0 generate
rp : process(wclk) begin
if rising_edge(wclk) then ra <= rdaddress; end if;
end process;
end generate;
twoclk : if sepclk = 1 generate
rp : process(rclk) begin
if rising_edge(rclk) then ra <= rdaddress; end if;
end process;
end generate;
q <= rfd(conv_integer(ra));
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity generic_regfile_3p is
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 32;
wrfst : integer := 0; numregs : integer := 40; delout: integer := 0);
port (
wclk : in std_ulogic;
waddr : in std_logic_vector((abits -1) downto 0);
wdata : in std_logic_vector((dbits -1) downto 0);
we : in std_ulogic;
rclk : in std_ulogic;
raddr1 : in std_logic_vector((abits -1) downto 0);
re1 : in std_ulogic;
rdata1 : out std_logic_vector((dbits -1) downto 0);
raddr2 : in std_logic_vector((abits -1) downto 0);
re2 : in std_ulogic;
rdata2 : out std_logic_vector((dbits -1) downto 0);
pre1 : out std_ulogic;
pre2 : out std_ulogic;
prdata1 : out std_logic_vector((dbits -1) downto 0);
prdata2 : out std_logic_vector((dbits -1) downto 0)
);
end;
architecture rtl of generic_regfile_3p is
type mem is array(0 to numregs-1)
of std_logic_vector((dbits -1) downto 0);
signal memarr : mem;
signal ra1, ra2, wa : std_logic_vector((abits -1) downto 0);
signal din : std_logic_vector((dbits -1) downto 0);
signal wr : std_ulogic;
signal re1d,re1dd,re2d,re2dd: std_ulogic;
signal rdata1i,rdata2i,rdata1d,rdata2d: std_logic_vector(dbits-1 downto 0);
begin
main : process(wclk)
begin
if rising_edge(wclk) then
din <= wdata; wr <= we;
if (we = '1')
-- pragma translate_off
and (conv_integer(waddr) < numregs)
-- pragma translate_on
then wa <= waddr; end if;
if (re1 = '1')
-- pragma translate_off
and (conv_integer(raddr1) < numregs)
-- pragma translate_on
then ra1 <= raddr1; end if;
if (re2 = '1')
-- pragma translate_off
and (conv_integer(raddr2) < numregs)
-- pragma translate_on
then ra2 <= raddr2; end if;
if wr = '1' then
memarr(conv_integer(wa)) <= din;
end if;
end if;
end process;
rdata1i <= din when (wr = '1') and (wa = ra1) and (wrfst = 1)
else memarr(conv_integer(ra1));
rdata2i <= din when (wr = '1') and (wa = ra2) and (wrfst = 1)
else memarr(conv_integer(ra2));
rdata1 <= rdata1i;
rdata2 <= rdata2i;
delgen: if delout /= 0 generate
p: process(wclk)
begin
if rising_edge(wclk) then
re1d <= re1;
re2d <= re2;
re1dd <= re1d;
re2dd <= re2d;
rdata1d <= rdata1i;
rdata2d <= rdata2i;
end if;
end process;
end generate;
ndelgen: if delout=0 generate
re1d <= '0'; re2d <= '0';
re1dd <= '0'; re2dd <= '0';
rdata1d <= (others => '0');
rdata2d <= (others => '0');
end generate;
pre1 <= re1dd;
pre2 <= re2dd;
prdata1 <= rdata1d;
prdata2 <= rdata2d;
end;
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
entity generic_regfile_4p is
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 32;
wrfst : integer := 0; numregs : integer := 40; g0addr: integer := 0;
delout : integer := 0);
port (
wclk : in std_ulogic;
waddr : in std_logic_vector((abits -1) downto 0);
wdata : in std_logic_vector((dbits -1) downto 0);
we : in std_ulogic;
rclk : in std_ulogic;
raddr1 : in std_logic_vector((abits -1) downto 0);
re1 : in std_ulogic;
rdata1 : out std_logic_vector((dbits -1) downto 0);
raddr2 : in std_logic_vector((abits -1) downto 0);
re2 : in std_ulogic;
rdata2 : out std_logic_vector((dbits -1) downto 0);
raddr3 : in std_logic_vector((abits -1) downto 0);
re3 : in std_ulogic;
rdata3 : out std_logic_vector((dbits -1) downto 0);
pre1 : out std_ulogic;
pre2 : out std_ulogic;
pre3 : out std_ulogic;
prdata1 : out std_logic_vector((dbits -1) downto 0);
prdata2 : out std_logic_vector((dbits -1) downto 0);
prdata3 : out std_logic_vector((dbits -1) downto 0)
);
end;
architecture rtl of generic_regfile_4p is
type mem is array(0 to numregs-1)
of std_logic_vector((dbits -1) downto 0);
signal memarr : mem;
signal ra1, ra2, ra3, wa : std_logic_vector((abits -1) downto 0);
signal din : std_logic_vector((dbits -1) downto 0);
signal wr : std_ulogic;
signal re1d,re1dd,re2d,re2dd,re3d,re3dd: std_ulogic;
signal rdata1i,rdata2i,rdata3i,rdata1d,rdata2d,rdata3d: std_logic_vector(dbits-1 downto 0);
begin
main : process(wclk)
begin
if rising_edge(wclk) then
din <= wdata; wr <= we;
if (we = '1')
-- pragma translate_off
and (conv_integer(waddr) < numregs)
-- pragma translate_on
then wa <= waddr; end if;
if (re1 = '1')
-- pragma translate_off
and (conv_integer(raddr1) < numregs)
-- pragma translate_on
then ra1 <= raddr1; end if;
if (re2 = '1')
-- pragma translate_off
and (conv_integer(raddr2) < numregs)
-- pragma translate_on
then ra2 <= raddr2; end if;
if (re3 = '1')
-- pragma translate_off
and (conv_integer(raddr3) < numregs)
-- pragma translate_on
then ra3 <= raddr3; end if;
if wr = '1' then
memarr(conv_integer(wa)) <= din;
end if;
if g0addr > 0 and g0addr < numregs then
memarr(g0addr) <= (others => '0');
end if;
end if;
end process;
rdata1i <= din when (wr = '1') and (wa = ra1) and (wrfst = 1)
else memarr(conv_integer(ra1));
rdata2i <= din when (wr = '1') and (wa = ra2) and (wrfst = 1)
else memarr(conv_integer(ra2));
rdata3i <= din when (wr = '1') and (wa = ra3) and (wrfst = 1)
else memarr(conv_integer(ra3));
rdata1 <= rdata1i;
rdata2 <= rdata2i;
rdata3 <= rdata3i;
delgen: if delout /= 0 generate
p: process(wclk)
begin
if rising_edge(wclk) then
re1d <= re1;
re2d <= re2;
re3d <= re3;
re1dd <= re1d;
re2dd <= re2d;
re3dd <= re3d;
rdata1d <= rdata1i;
rdata2d <= rdata2i;
rdata3d <= rdata3i;
end if;
end process;
end generate;
ndelgen: if delout=0 generate
re1d <= '0'; re2d <= '0'; re3d <= '0';
re1dd <= '0'; re2dd <= '0'; re3dd <= '0';
rdata1d <= (others => '0');
rdata2d <= (others => '0');
rdata3d <= (others => '0');
end generate;
pre1 <= re1dd;
pre2 <= re2dd;
pre3 <= re3dd;
prdata1 <= rdata1d;
prdata2 <= rdata2d;
prdata3 <= rdata3d;
end;
|
library verilog;
use verilog.vl_types.all;
entity Threebit_BCD_counter_vlg_check_tst is
port(
Counter_Result : in vl_logic_vector(11 downto 0);
sampler_rx : in vl_logic
);
end Threebit_BCD_counter_vlg_check_tst;
|
-- HDLC_tb.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.All;
entity HDLC_tb is
end HDLC_tb;
architecture behavioural of HDLC_tb is
component HDLC
port (
-- microprocessor input
D : inout Std_Logic_Vector (7 downto 0);
E : in Std_Logic; -- system clock
nCS : in Std_Logic;
RS : in Std_Logic_Vector (1 downto 0);
RnW : in Std_Logic;
nRST : in Std_Logic;
nIRQ : out Std_Logic;
-- clock and data or transmitter and receiver
TxC : in Std_Logic;
RxC : in Std_Logic;
TxD : out Std_Logic;
RxD : in Std_Logic;
-- Peripheral/Modem control
nRTS : out Std_Logic;
nCTS : in Std_Logic;
nDCD : in Std_Logic;
nLOCnDTR : out Std_Logic;
-- DMA interface
RDSR : out Std_Logic; -- Rx FIFO requests service
TDSR : out Std_Logic -- Tx FIFO requests service
);
end component;
signal A, B : Std_Logic_Vector (7 downto 0);
signal R : Std_Logic;
begin
u0: HDLC PORT MAP (B, R);
A <= "00001000" after 0 ns, "00000000" after 10 ns, "00001111" after 20 ns, "00001010" after 30 ns, "00000000" after 50 ns, "00000000" after 60 ns;
end behavioural; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity control_unit is
Generic (
clock_frec : integer := 50 -- MHz
);
Port (
clock :in STD_LOGIC; -- 100MHz/50MHz
reset :in STD_LOGIC;
en :in STD_LOGIC;
);
end entity control_unit;
architecture behavioral of control_unit is
type state_t is (INIT, );
signal state: state_t := INIT;
begin
SYNC_PROC : process (clock, reset)
begin
if reset = '1' then
state <= INIT;
elsif (clk’event and clk=’l’) then
case state is
when INIT =>
when =>
end process; |
constant TRFSM1Length : integer := 1778;
constant TRFSM1Cfg : std_logic_vector(TRFSM1Length-1 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.siphash_package.all;
entity sipround is
port (
v0_in, v1_in, v2_in, v3_in : in std_logic_vector(V_WIDTH-1 downto 0);
v0_out, v1_out, v2_out, v3_out : out std_logic_vector(V_WIDTH-1 downto 0)
);
end entity;
architecture rtl of sipround is
begin
process(v0_in, v1_in, v2_in, v3_in)
variable v0, v1, v2, v3 : unsigned(V_WIDTH-1 downto 0);
begin
v0 := unsigned(v0_in);
v1 := unsigned(v1_in);
v2 := unsigned(v2_in);
v3 := unsigned(v3_in);
v0 := v0 + v1;
v2 := v2 + v3;
v1 := rotate_left(v1, 13);
v3 := rotate_left(v3, 16);
v1 := v1 xor v0;
v3 := v3 xor v2;
v0 := rotate_left(v0, 32);
v0 := v0 + v3;
v2 := v2 + v1;
v1 := rotate_left(v1, 17);
v3 := rotate_left(v3, 21);
v1 := v1 xor v2;
v3 := v3 xor v0;
v2 := rotate_left(v2, 32);
v0_out <= std_logic_vector(v0);
v1_out <= std_logic_vector(v1);
v2_out <= std_logic_vector(v2);
v3_out <= std_logic_vector(v3);
end process;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity VideoRam is
port (
clka : in std_logic;
wea : in std_logic;
addra : in std_logic_vector(15 downto 0);
dina : in std_logic_vector(3 downto 0);
clkb : in std_logic;
addrb : in std_logic_vector(15 downto 0);
doutb : out std_logic_vector(3 downto 0)
);
end VideoRam;
architecture BEHAVIORAL of VideoRam is
-- Shared memory
type ram_type is array (48*1024-1 downto 0) of std_logic_vector (3 downto 0);
shared variable RAM : ram_type;
--attribute RAM_STYLE : string;
--attribute RAM_STYLE of RAM: signal is "BLOCK";
begin
process (clka)
begin
if rising_edge(clka) then
if (wea = '1') then
RAM(conv_integer(addra)) := dina;
end if;
end if;
end process;
process (clkb)
begin
if rising_edge(clkb) then
doutb <= RAM(conv_integer(addrb));
end if;
end process;
end BEHAVIORAL;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
|
---------------------------------------------------------------------
-- TITLE: Pipeline
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 6/24/02
-- FILENAME: pipeline.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Controls the three stage pipeline by delaying the signals:
-- a_bus, b_bus, alu/shift/mult_func, c_source, and rs_index.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
--Note: sigD <= sig after rising_edge(clk)
entity pipeline is
port(clk : in std_logic;
reset : in std_logic;
a_bus : in std_logic_vector(31 downto 0);
a_busD : out std_logic_vector(31 downto 0);
b_bus : in std_logic_vector(31 downto 0);
b_busD : out std_logic_vector(31 downto 0);
alu_func : in alu_function_type;
alu_funcD : out alu_function_type;
shift_func : in shift_function_type;
shift_funcD : out shift_function_type;
mult_func : in mult_function_type;
mult_funcD : out mult_function_type;
reg_dest : in std_logic_vector(31 downto 0);
reg_destD : out std_logic_vector(31 downto 0);
rd_index : in std_logic_vector(5 downto 0);
rd_indexD : out std_logic_vector(5 downto 0);
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
pc_source : in pc_source_type;
mem_source : in mem_source_type;
a_source : in a_source_type;
b_source : in b_source_type;
c_source : in c_source_type;
c_bus : in std_logic_vector(31 downto 0);
pause_any : in std_logic;
pause_pipeline : out std_logic);
end; --entity pipeline
architecture logic of pipeline is
signal rd_index_reg : std_logic_vector(5 downto 0);
signal reg_dest_reg : std_logic_vector(31 downto 0);
signal reg_dest_delay : std_logic_vector(31 downto 0);
signal c_source_reg : c_source_type;
signal pause_enable_reg : std_logic;
begin
--When operating in three stage pipeline mode, the following signals
--are delayed by one clock cycle: a_bus, b_bus, alu/shift/mult_func,
--c_source, and rd_index.
pipeline3: process(clk, reset, a_bus, b_bus, alu_func, shift_func, mult_func,
rd_index, rd_index_reg, pause_any, pause_enable_reg,
rs_index, rt_index,
pc_source, mem_source, a_source, b_source, c_source, c_source_reg,
reg_dest, reg_dest_reg, reg_dest_delay, c_bus)
variable pause_mult_clock : std_logic;
variable freeze_pipeline : std_logic;
begin
if (pc_source /= FROM_INC4 and pc_source /= FROM_OPCODE25_0) or
mem_source /= MEM_FETCH or
(mult_func = MULT_READ_LO or mult_func = MULT_READ_HI) then
pause_mult_clock := '1';
else
pause_mult_clock := '0';
end if;
freeze_pipeline := not (pause_mult_clock and pause_enable_reg) and pause_any;
pause_pipeline <= pause_mult_clock and pause_enable_reg;
rd_indexD <= rd_index_reg;
-- The value written back into the register bank, signal reg_dest is tricky.
-- If reg_dest comes from the ALU via the signal c_bus, it is already delayed
-- into stage #3, because a_busD and b_busD are delayed. If reg_dest comes from
-- c_memory, pc_current, or pc_plus4 then reg_dest hasn't yet been delayed into
-- stage #3.
-- Instead of delaying c_memory, pc_current, and pc_plus4, these signals
-- are multiplexed into reg_dest which is then delayed. The decision to use
-- the already delayed c_bus or the delayed value of reg_dest (reg_dest_reg) is
-- based on a delayed value of c_source (c_source_reg).
if c_source_reg = C_FROM_ALU then
reg_dest_delay <= c_bus; --delayed by 1 clock cycle via a_busD & b_busD
else
reg_dest_delay <= reg_dest_reg; --need to delay 1 clock cycle from reg_dest
end if;
reg_destD <= reg_dest_delay;
if reset = '1' then
a_busD <= ZERO;
b_busD <= ZERO;
alu_funcD <= ALU_NOTHING;
shift_funcD <= SHIFT_NOTHING;
mult_funcD <= MULT_NOTHING;
reg_dest_reg <= ZERO;
c_source_reg <= "000";
rd_index_reg <= "000000";
pause_enable_reg <= '0';
elsif rising_edge(clk) then
if freeze_pipeline = '0' then
if (rs_index = "000000" or rs_index /= rd_index_reg) or
(a_source /= A_FROM_REG_SOURCE or pause_enable_reg = '0') then
a_busD <= a_bus;
else
a_busD <= reg_dest_delay; --rs from previous operation (bypass stage)
end if;
if (rt_index = "000000" or rt_index /= rd_index_reg) or
(b_source /= B_FROM_REG_TARGET or pause_enable_reg = '0') then
b_busD <= b_bus;
else
b_busD <= reg_dest_delay; --rt from previous operation
end if;
alu_funcD <= alu_func;
shift_funcD <= shift_func;
mult_funcD <= mult_func;
reg_dest_reg <= reg_dest;
c_source_reg <= c_source;
rd_index_reg <= rd_index;
end if;
if pause_enable_reg = '0' and pause_any = '0' then
pause_enable_reg <= '1'; --enable pause_pipeline
elsif pause_mult_clock = '1' then
pause_enable_reg <= '0'; --disable pause_pipeline
end if;
end if;
end process; --pipeline3
end; --logic
|
---------------------------------------------------------------------
-- TITLE: Pipeline
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 6/24/02
-- FILENAME: pipeline.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Controls the three stage pipeline by delaying the signals:
-- a_bus, b_bus, alu/shift/mult_func, c_source, and rs_index.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
--Note: sigD <= sig after rising_edge(clk)
entity pipeline is
port(clk : in std_logic;
reset : in std_logic;
a_bus : in std_logic_vector(31 downto 0);
a_busD : out std_logic_vector(31 downto 0);
b_bus : in std_logic_vector(31 downto 0);
b_busD : out std_logic_vector(31 downto 0);
alu_func : in alu_function_type;
alu_funcD : out alu_function_type;
shift_func : in shift_function_type;
shift_funcD : out shift_function_type;
mult_func : in mult_function_type;
mult_funcD : out mult_function_type;
reg_dest : in std_logic_vector(31 downto 0);
reg_destD : out std_logic_vector(31 downto 0);
rd_index : in std_logic_vector(5 downto 0);
rd_indexD : out std_logic_vector(5 downto 0);
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
pc_source : in pc_source_type;
mem_source : in mem_source_type;
a_source : in a_source_type;
b_source : in b_source_type;
c_source : in c_source_type;
c_bus : in std_logic_vector(31 downto 0);
pause_any : in std_logic;
pause_pipeline : out std_logic);
end; --entity pipeline
architecture logic of pipeline is
signal rd_index_reg : std_logic_vector(5 downto 0);
signal reg_dest_reg : std_logic_vector(31 downto 0);
signal reg_dest_delay : std_logic_vector(31 downto 0);
signal c_source_reg : c_source_type;
signal pause_enable_reg : std_logic;
begin
--When operating in three stage pipeline mode, the following signals
--are delayed by one clock cycle: a_bus, b_bus, alu/shift/mult_func,
--c_source, and rd_index.
pipeline3: process(clk, reset, a_bus, b_bus, alu_func, shift_func, mult_func,
rd_index, rd_index_reg, pause_any, pause_enable_reg,
rs_index, rt_index,
pc_source, mem_source, a_source, b_source, c_source, c_source_reg,
reg_dest, reg_dest_reg, reg_dest_delay, c_bus)
variable pause_mult_clock : std_logic;
variable freeze_pipeline : std_logic;
begin
if (pc_source /= FROM_INC4 and pc_source /= FROM_OPCODE25_0) or
mem_source /= MEM_FETCH or
(mult_func = MULT_READ_LO or mult_func = MULT_READ_HI) then
pause_mult_clock := '1';
else
pause_mult_clock := '0';
end if;
freeze_pipeline := not (pause_mult_clock and pause_enable_reg) and pause_any;
pause_pipeline <= pause_mult_clock and pause_enable_reg;
rd_indexD <= rd_index_reg;
-- The value written back into the register bank, signal reg_dest is tricky.
-- If reg_dest comes from the ALU via the signal c_bus, it is already delayed
-- into stage #3, because a_busD and b_busD are delayed. If reg_dest comes from
-- c_memory, pc_current, or pc_plus4 then reg_dest hasn't yet been delayed into
-- stage #3.
-- Instead of delaying c_memory, pc_current, and pc_plus4, these signals
-- are multiplexed into reg_dest which is then delayed. The decision to use
-- the already delayed c_bus or the delayed value of reg_dest (reg_dest_reg) is
-- based on a delayed value of c_source (c_source_reg).
if c_source_reg = C_FROM_ALU then
reg_dest_delay <= c_bus; --delayed by 1 clock cycle via a_busD & b_busD
else
reg_dest_delay <= reg_dest_reg; --need to delay 1 clock cycle from reg_dest
end if;
reg_destD <= reg_dest_delay;
if reset = '1' then
a_busD <= ZERO;
b_busD <= ZERO;
alu_funcD <= ALU_NOTHING;
shift_funcD <= SHIFT_NOTHING;
mult_funcD <= MULT_NOTHING;
reg_dest_reg <= ZERO;
c_source_reg <= "000";
rd_index_reg <= "000000";
pause_enable_reg <= '0';
elsif rising_edge(clk) then
if freeze_pipeline = '0' then
if (rs_index = "000000" or rs_index /= rd_index_reg) or
(a_source /= A_FROM_REG_SOURCE or pause_enable_reg = '0') then
a_busD <= a_bus;
else
a_busD <= reg_dest_delay; --rs from previous operation (bypass stage)
end if;
if (rt_index = "000000" or rt_index /= rd_index_reg) or
(b_source /= B_FROM_REG_TARGET or pause_enable_reg = '0') then
b_busD <= b_bus;
else
b_busD <= reg_dest_delay; --rt from previous operation
end if;
alu_funcD <= alu_func;
shift_funcD <= shift_func;
mult_funcD <= mult_func;
reg_dest_reg <= reg_dest;
c_source_reg <= c_source;
rd_index_reg <= rd_index;
end if;
if pause_enable_reg = '0' and pause_any = '0' then
pause_enable_reg <= '1'; --enable pause_pipeline
elsif pause_mult_clock = '1' then
pause_enable_reg <= '0'; --disable pause_pipeline
end if;
end if;
end process; --pipeline3
end; --logic
|
---------------------------------------------------------------------
-- TITLE: Pipeline
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 6/24/02
-- FILENAME: pipeline.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Controls the three stage pipeline by delaying the signals:
-- a_bus, b_bus, alu/shift/mult_func, c_source, and rs_index.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
--Note: sigD <= sig after rising_edge(clk)
entity pipeline is
port(clk : in std_logic;
reset : in std_logic;
a_bus : in std_logic_vector(31 downto 0);
a_busD : out std_logic_vector(31 downto 0);
b_bus : in std_logic_vector(31 downto 0);
b_busD : out std_logic_vector(31 downto 0);
alu_func : in alu_function_type;
alu_funcD : out alu_function_type;
shift_func : in shift_function_type;
shift_funcD : out shift_function_type;
mult_func : in mult_function_type;
mult_funcD : out mult_function_type;
reg_dest : in std_logic_vector(31 downto 0);
reg_destD : out std_logic_vector(31 downto 0);
rd_index : in std_logic_vector(5 downto 0);
rd_indexD : out std_logic_vector(5 downto 0);
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
pc_source : in pc_source_type;
mem_source : in mem_source_type;
a_source : in a_source_type;
b_source : in b_source_type;
c_source : in c_source_type;
c_bus : in std_logic_vector(31 downto 0);
pause_any : in std_logic;
pause_pipeline : out std_logic);
end; --entity pipeline
architecture logic of pipeline is
signal rd_index_reg : std_logic_vector(5 downto 0);
signal reg_dest_reg : std_logic_vector(31 downto 0);
signal reg_dest_delay : std_logic_vector(31 downto 0);
signal c_source_reg : c_source_type;
signal pause_enable_reg : std_logic;
begin
--When operating in three stage pipeline mode, the following signals
--are delayed by one clock cycle: a_bus, b_bus, alu/shift/mult_func,
--c_source, and rd_index.
pipeline3: process(clk, reset, a_bus, b_bus, alu_func, shift_func, mult_func,
rd_index, rd_index_reg, pause_any, pause_enable_reg,
rs_index, rt_index,
pc_source, mem_source, a_source, b_source, c_source, c_source_reg,
reg_dest, reg_dest_reg, reg_dest_delay, c_bus)
variable pause_mult_clock : std_logic;
variable freeze_pipeline : std_logic;
begin
if (pc_source /= FROM_INC4 and pc_source /= FROM_OPCODE25_0) or
mem_source /= MEM_FETCH or
(mult_func = MULT_READ_LO or mult_func = MULT_READ_HI) then
pause_mult_clock := '1';
else
pause_mult_clock := '0';
end if;
freeze_pipeline := not (pause_mult_clock and pause_enable_reg) and pause_any;
pause_pipeline <= pause_mult_clock and pause_enable_reg;
rd_indexD <= rd_index_reg;
-- The value written back into the register bank, signal reg_dest is tricky.
-- If reg_dest comes from the ALU via the signal c_bus, it is already delayed
-- into stage #3, because a_busD and b_busD are delayed. If reg_dest comes from
-- c_memory, pc_current, or pc_plus4 then reg_dest hasn't yet been delayed into
-- stage #3.
-- Instead of delaying c_memory, pc_current, and pc_plus4, these signals
-- are multiplexed into reg_dest which is then delayed. The decision to use
-- the already delayed c_bus or the delayed value of reg_dest (reg_dest_reg) is
-- based on a delayed value of c_source (c_source_reg).
if c_source_reg = C_FROM_ALU then
reg_dest_delay <= c_bus; --delayed by 1 clock cycle via a_busD & b_busD
else
reg_dest_delay <= reg_dest_reg; --need to delay 1 clock cycle from reg_dest
end if;
reg_destD <= reg_dest_delay;
if reset = '1' then
a_busD <= ZERO;
b_busD <= ZERO;
alu_funcD <= ALU_NOTHING;
shift_funcD <= SHIFT_NOTHING;
mult_funcD <= MULT_NOTHING;
reg_dest_reg <= ZERO;
c_source_reg <= "000";
rd_index_reg <= "000000";
pause_enable_reg <= '0';
elsif rising_edge(clk) then
if freeze_pipeline = '0' then
if (rs_index = "000000" or rs_index /= rd_index_reg) or
(a_source /= A_FROM_REG_SOURCE or pause_enable_reg = '0') then
a_busD <= a_bus;
else
a_busD <= reg_dest_delay; --rs from previous operation (bypass stage)
end if;
if (rt_index = "000000" or rt_index /= rd_index_reg) or
(b_source /= B_FROM_REG_TARGET or pause_enable_reg = '0') then
b_busD <= b_bus;
else
b_busD <= reg_dest_delay; --rt from previous operation
end if;
alu_funcD <= alu_func;
shift_funcD <= shift_func;
mult_funcD <= mult_func;
reg_dest_reg <= reg_dest;
c_source_reg <= c_source;
rd_index_reg <= rd_index;
end if;
if pause_enable_reg = '0' and pause_any = '0' then
pause_enable_reg <= '1'; --enable pause_pipeline
elsif pause_mult_clock = '1' then
pause_enable_reg <= '0'; --disable pause_pipeline
end if;
end if;
end process; --pipeline3
end; --logic
|
---------------------------------------------------------------------
-- TITLE: Pipeline
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 6/24/02
-- FILENAME: pipeline.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Controls the three stage pipeline by delaying the signals:
-- a_bus, b_bus, alu/shift/mult_func, c_source, and rs_index.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
--Note: sigD <= sig after rising_edge(clk)
entity pipeline is
port(clk : in std_logic;
reset : in std_logic;
a_bus : in std_logic_vector(31 downto 0);
a_busD : out std_logic_vector(31 downto 0);
b_bus : in std_logic_vector(31 downto 0);
b_busD : out std_logic_vector(31 downto 0);
alu_func : in alu_function_type;
alu_funcD : out alu_function_type;
shift_func : in shift_function_type;
shift_funcD : out shift_function_type;
mult_func : in mult_function_type;
mult_funcD : out mult_function_type;
reg_dest : in std_logic_vector(31 downto 0);
reg_destD : out std_logic_vector(31 downto 0);
rd_index : in std_logic_vector(5 downto 0);
rd_indexD : out std_logic_vector(5 downto 0);
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
pc_source : in pc_source_type;
mem_source : in mem_source_type;
a_source : in a_source_type;
b_source : in b_source_type;
c_source : in c_source_type;
c_bus : in std_logic_vector(31 downto 0);
pause_any : in std_logic;
pause_pipeline : out std_logic);
end; --entity pipeline
architecture logic of pipeline is
signal rd_index_reg : std_logic_vector(5 downto 0);
signal reg_dest_reg : std_logic_vector(31 downto 0);
signal reg_dest_delay : std_logic_vector(31 downto 0);
signal c_source_reg : c_source_type;
signal pause_enable_reg : std_logic;
begin
--When operating in three stage pipeline mode, the following signals
--are delayed by one clock cycle: a_bus, b_bus, alu/shift/mult_func,
--c_source, and rd_index.
pipeline3: process(clk, reset, a_bus, b_bus, alu_func, shift_func, mult_func,
rd_index, rd_index_reg, pause_any, pause_enable_reg,
rs_index, rt_index,
pc_source, mem_source, a_source, b_source, c_source, c_source_reg,
reg_dest, reg_dest_reg, reg_dest_delay, c_bus)
variable pause_mult_clock : std_logic;
variable freeze_pipeline : std_logic;
begin
if (pc_source /= FROM_INC4 and pc_source /= FROM_OPCODE25_0) or
mem_source /= MEM_FETCH or
(mult_func = MULT_READ_LO or mult_func = MULT_READ_HI) then
pause_mult_clock := '1';
else
pause_mult_clock := '0';
end if;
freeze_pipeline := not (pause_mult_clock and pause_enable_reg) and pause_any;
pause_pipeline <= pause_mult_clock and pause_enable_reg;
rd_indexD <= rd_index_reg;
-- The value written back into the register bank, signal reg_dest is tricky.
-- If reg_dest comes from the ALU via the signal c_bus, it is already delayed
-- into stage #3, because a_busD and b_busD are delayed. If reg_dest comes from
-- c_memory, pc_current, or pc_plus4 then reg_dest hasn't yet been delayed into
-- stage #3.
-- Instead of delaying c_memory, pc_current, and pc_plus4, these signals
-- are multiplexed into reg_dest which is then delayed. The decision to use
-- the already delayed c_bus or the delayed value of reg_dest (reg_dest_reg) is
-- based on a delayed value of c_source (c_source_reg).
if c_source_reg = C_FROM_ALU then
reg_dest_delay <= c_bus; --delayed by 1 clock cycle via a_busD & b_busD
else
reg_dest_delay <= reg_dest_reg; --need to delay 1 clock cycle from reg_dest
end if;
reg_destD <= reg_dest_delay;
if reset = '1' then
a_busD <= ZERO;
b_busD <= ZERO;
alu_funcD <= ALU_NOTHING;
shift_funcD <= SHIFT_NOTHING;
mult_funcD <= MULT_NOTHING;
reg_dest_reg <= ZERO;
c_source_reg <= "000";
rd_index_reg <= "000000";
pause_enable_reg <= '0';
elsif rising_edge(clk) then
if freeze_pipeline = '0' then
if (rs_index = "000000" or rs_index /= rd_index_reg) or
(a_source /= A_FROM_REG_SOURCE or pause_enable_reg = '0') then
a_busD <= a_bus;
else
a_busD <= reg_dest_delay; --rs from previous operation (bypass stage)
end if;
if (rt_index = "000000" or rt_index /= rd_index_reg) or
(b_source /= B_FROM_REG_TARGET or pause_enable_reg = '0') then
b_busD <= b_bus;
else
b_busD <= reg_dest_delay; --rt from previous operation
end if;
alu_funcD <= alu_func;
shift_funcD <= shift_func;
mult_funcD <= mult_func;
reg_dest_reg <= reg_dest;
c_source_reg <= c_source;
rd_index_reg <= rd_index;
end if;
if pause_enable_reg = '0' and pause_any = '0' then
pause_enable_reg <= '1'; --enable pause_pipeline
elsif pause_mult_clock = '1' then
pause_enable_reg <= '0'; --disable pause_pipeline
end if;
end if;
end process; --pipeline3
end; --logic
|
---------------------------------------------------------------------
-- TITLE: Pipeline
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 6/24/02
-- FILENAME: pipeline.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Controls the three stage pipeline by delaying the signals:
-- a_bus, b_bus, alu/shift/mult_func, c_source, and rs_index.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
--Note: sigD <= sig after rising_edge(clk)
entity pipeline is
port(clk : in std_logic;
reset : in std_logic;
a_bus : in std_logic_vector(31 downto 0);
a_busD : out std_logic_vector(31 downto 0);
b_bus : in std_logic_vector(31 downto 0);
b_busD : out std_logic_vector(31 downto 0);
alu_func : in alu_function_type;
alu_funcD : out alu_function_type;
shift_func : in shift_function_type;
shift_funcD : out shift_function_type;
mult_func : in mult_function_type;
mult_funcD : out mult_function_type;
reg_dest : in std_logic_vector(31 downto 0);
reg_destD : out std_logic_vector(31 downto 0);
rd_index : in std_logic_vector(5 downto 0);
rd_indexD : out std_logic_vector(5 downto 0);
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
pc_source : in pc_source_type;
mem_source : in mem_source_type;
a_source : in a_source_type;
b_source : in b_source_type;
c_source : in c_source_type;
c_bus : in std_logic_vector(31 downto 0);
pause_any : in std_logic;
pause_pipeline : out std_logic);
end; --entity pipeline
architecture logic of pipeline is
signal rd_index_reg : std_logic_vector(5 downto 0);
signal reg_dest_reg : std_logic_vector(31 downto 0);
signal reg_dest_delay : std_logic_vector(31 downto 0);
signal c_source_reg : c_source_type;
signal pause_enable_reg : std_logic;
begin
--When operating in three stage pipeline mode, the following signals
--are delayed by one clock cycle: a_bus, b_bus, alu/shift/mult_func,
--c_source, and rd_index.
pipeline3: process(clk, reset, a_bus, b_bus, alu_func, shift_func, mult_func,
rd_index, rd_index_reg, pause_any, pause_enable_reg,
rs_index, rt_index,
pc_source, mem_source, a_source, b_source, c_source, c_source_reg,
reg_dest, reg_dest_reg, reg_dest_delay, c_bus)
variable pause_mult_clock : std_logic;
variable freeze_pipeline : std_logic;
begin
if (pc_source /= FROM_INC4 and pc_source /= FROM_OPCODE25_0) or
mem_source /= MEM_FETCH or
(mult_func = MULT_READ_LO or mult_func = MULT_READ_HI) then
pause_mult_clock := '1';
else
pause_mult_clock := '0';
end if;
freeze_pipeline := not (pause_mult_clock and pause_enable_reg) and pause_any;
pause_pipeline <= pause_mult_clock and pause_enable_reg;
rd_indexD <= rd_index_reg;
-- The value written back into the register bank, signal reg_dest is tricky.
-- If reg_dest comes from the ALU via the signal c_bus, it is already delayed
-- into stage #3, because a_busD and b_busD are delayed. If reg_dest comes from
-- c_memory, pc_current, or pc_plus4 then reg_dest hasn't yet been delayed into
-- stage #3.
-- Instead of delaying c_memory, pc_current, and pc_plus4, these signals
-- are multiplexed into reg_dest which is then delayed. The decision to use
-- the already delayed c_bus or the delayed value of reg_dest (reg_dest_reg) is
-- based on a delayed value of c_source (c_source_reg).
if c_source_reg = C_FROM_ALU then
reg_dest_delay <= c_bus; --delayed by 1 clock cycle via a_busD & b_busD
else
reg_dest_delay <= reg_dest_reg; --need to delay 1 clock cycle from reg_dest
end if;
reg_destD <= reg_dest_delay;
if reset = '1' then
a_busD <= ZERO;
b_busD <= ZERO;
alu_funcD <= ALU_NOTHING;
shift_funcD <= SHIFT_NOTHING;
mult_funcD <= MULT_NOTHING;
reg_dest_reg <= ZERO;
c_source_reg <= "000";
rd_index_reg <= "000000";
pause_enable_reg <= '0';
elsif rising_edge(clk) then
if freeze_pipeline = '0' then
if (rs_index = "000000" or rs_index /= rd_index_reg) or
(a_source /= A_FROM_REG_SOURCE or pause_enable_reg = '0') then
a_busD <= a_bus;
else
a_busD <= reg_dest_delay; --rs from previous operation (bypass stage)
end if;
if (rt_index = "000000" or rt_index /= rd_index_reg) or
(b_source /= B_FROM_REG_TARGET or pause_enable_reg = '0') then
b_busD <= b_bus;
else
b_busD <= reg_dest_delay; --rt from previous operation
end if;
alu_funcD <= alu_func;
shift_funcD <= shift_func;
mult_funcD <= mult_func;
reg_dest_reg <= reg_dest;
c_source_reg <= c_source;
rd_index_reg <= rd_index;
end if;
if pause_enable_reg = '0' and pause_any = '0' then
pause_enable_reg <= '1'; --enable pause_pipeline
elsif pause_mult_clock = '1' then
pause_enable_reg <= '0'; --disable pause_pipeline
end if;
end if;
end process; --pipeline3
end; --logic
|
---------------------------------------------------------------------
-- TITLE: Pipeline
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 6/24/02
-- FILENAME: pipeline.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Controls the three stage pipeline by delaying the signals:
-- a_bus, b_bus, alu/shift/mult_func, c_source, and rs_index.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
--Note: sigD <= sig after rising_edge(clk)
entity pipeline is
port(clk : in std_logic;
reset : in std_logic;
a_bus : in std_logic_vector(31 downto 0);
a_busD : out std_logic_vector(31 downto 0);
b_bus : in std_logic_vector(31 downto 0);
b_busD : out std_logic_vector(31 downto 0);
alu_func : in alu_function_type;
alu_funcD : out alu_function_type;
shift_func : in shift_function_type;
shift_funcD : out shift_function_type;
mult_func : in mult_function_type;
mult_funcD : out mult_function_type;
reg_dest : in std_logic_vector(31 downto 0);
reg_destD : out std_logic_vector(31 downto 0);
rd_index : in std_logic_vector(5 downto 0);
rd_indexD : out std_logic_vector(5 downto 0);
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
pc_source : in pc_source_type;
mem_source : in mem_source_type;
a_source : in a_source_type;
b_source : in b_source_type;
c_source : in c_source_type;
c_bus : in std_logic_vector(31 downto 0);
pause_any : in std_logic;
pause_pipeline : out std_logic);
end; --entity pipeline
architecture logic of pipeline is
signal rd_index_reg : std_logic_vector(5 downto 0);
signal reg_dest_reg : std_logic_vector(31 downto 0);
signal reg_dest_delay : std_logic_vector(31 downto 0);
signal c_source_reg : c_source_type;
signal pause_enable_reg : std_logic;
begin
--When operating in three stage pipeline mode, the following signals
--are delayed by one clock cycle: a_bus, b_bus, alu/shift/mult_func,
--c_source, and rd_index.
pipeline3: process(clk, reset, a_bus, b_bus, alu_func, shift_func, mult_func,
rd_index, rd_index_reg, pause_any, pause_enable_reg,
rs_index, rt_index,
pc_source, mem_source, a_source, b_source, c_source, c_source_reg,
reg_dest, reg_dest_reg, reg_dest_delay, c_bus)
variable pause_mult_clock : std_logic;
variable freeze_pipeline : std_logic;
begin
if (pc_source /= FROM_INC4 and pc_source /= FROM_OPCODE25_0) or
mem_source /= MEM_FETCH or
(mult_func = MULT_READ_LO or mult_func = MULT_READ_HI) then
pause_mult_clock := '1';
else
pause_mult_clock := '0';
end if;
freeze_pipeline := not (pause_mult_clock and pause_enable_reg) and pause_any;
pause_pipeline <= pause_mult_clock and pause_enable_reg;
rd_indexD <= rd_index_reg;
-- The value written back into the register bank, signal reg_dest is tricky.
-- If reg_dest comes from the ALU via the signal c_bus, it is already delayed
-- into stage #3, because a_busD and b_busD are delayed. If reg_dest comes from
-- c_memory, pc_current, or pc_plus4 then reg_dest hasn't yet been delayed into
-- stage #3.
-- Instead of delaying c_memory, pc_current, and pc_plus4, these signals
-- are multiplexed into reg_dest which is then delayed. The decision to use
-- the already delayed c_bus or the delayed value of reg_dest (reg_dest_reg) is
-- based on a delayed value of c_source (c_source_reg).
if c_source_reg = C_FROM_ALU then
reg_dest_delay <= c_bus; --delayed by 1 clock cycle via a_busD & b_busD
else
reg_dest_delay <= reg_dest_reg; --need to delay 1 clock cycle from reg_dest
end if;
reg_destD <= reg_dest_delay;
if reset = '1' then
a_busD <= ZERO;
b_busD <= ZERO;
alu_funcD <= ALU_NOTHING;
shift_funcD <= SHIFT_NOTHING;
mult_funcD <= MULT_NOTHING;
reg_dest_reg <= ZERO;
c_source_reg <= "000";
rd_index_reg <= "000000";
pause_enable_reg <= '0';
elsif rising_edge(clk) then
if freeze_pipeline = '0' then
if (rs_index = "000000" or rs_index /= rd_index_reg) or
(a_source /= A_FROM_REG_SOURCE or pause_enable_reg = '0') then
a_busD <= a_bus;
else
a_busD <= reg_dest_delay; --rs from previous operation (bypass stage)
end if;
if (rt_index = "000000" or rt_index /= rd_index_reg) or
(b_source /= B_FROM_REG_TARGET or pause_enable_reg = '0') then
b_busD <= b_bus;
else
b_busD <= reg_dest_delay; --rt from previous operation
end if;
alu_funcD <= alu_func;
shift_funcD <= shift_func;
mult_funcD <= mult_func;
reg_dest_reg <= reg_dest;
c_source_reg <= c_source;
rd_index_reg <= rd_index;
end if;
if pause_enable_reg = '0' and pause_any = '0' then
pause_enable_reg <= '1'; --enable pause_pipeline
elsif pause_mult_clock = '1' then
pause_enable_reg <= '0'; --disable pause_pipeline
end if;
end if;
end process; --pipeline3
end; --logic
|
---------------------------------------------------------------------
-- TITLE: Pipeline
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 6/24/02
-- FILENAME: pipeline.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Controls the three stage pipeline by delaying the signals:
-- a_bus, b_bus, alu/shift/mult_func, c_source, and rs_index.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
--Note: sigD <= sig after rising_edge(clk)
entity pipeline is
port(clk : in std_logic;
reset : in std_logic;
a_bus : in std_logic_vector(31 downto 0);
a_busD : out std_logic_vector(31 downto 0);
b_bus : in std_logic_vector(31 downto 0);
b_busD : out std_logic_vector(31 downto 0);
alu_func : in alu_function_type;
alu_funcD : out alu_function_type;
shift_func : in shift_function_type;
shift_funcD : out shift_function_type;
mult_func : in mult_function_type;
mult_funcD : out mult_function_type;
reg_dest : in std_logic_vector(31 downto 0);
reg_destD : out std_logic_vector(31 downto 0);
rd_index : in std_logic_vector(5 downto 0);
rd_indexD : out std_logic_vector(5 downto 0);
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
pc_source : in pc_source_type;
mem_source : in mem_source_type;
a_source : in a_source_type;
b_source : in b_source_type;
c_source : in c_source_type;
c_bus : in std_logic_vector(31 downto 0);
pause_any : in std_logic;
pause_pipeline : out std_logic);
end; --entity pipeline
architecture logic of pipeline is
signal rd_index_reg : std_logic_vector(5 downto 0);
signal reg_dest_reg : std_logic_vector(31 downto 0);
signal reg_dest_delay : std_logic_vector(31 downto 0);
signal c_source_reg : c_source_type;
signal pause_enable_reg : std_logic;
begin
--When operating in three stage pipeline mode, the following signals
--are delayed by one clock cycle: a_bus, b_bus, alu/shift/mult_func,
--c_source, and rd_index.
pipeline3: process(clk, reset, a_bus, b_bus, alu_func, shift_func, mult_func,
rd_index, rd_index_reg, pause_any, pause_enable_reg,
rs_index, rt_index,
pc_source, mem_source, a_source, b_source, c_source, c_source_reg,
reg_dest, reg_dest_reg, reg_dest_delay, c_bus)
variable pause_mult_clock : std_logic;
variable freeze_pipeline : std_logic;
begin
if (pc_source /= FROM_INC4 and pc_source /= FROM_OPCODE25_0) or
mem_source /= MEM_FETCH or
(mult_func = MULT_READ_LO or mult_func = MULT_READ_HI) then
pause_mult_clock := '1';
else
pause_mult_clock := '0';
end if;
freeze_pipeline := not (pause_mult_clock and pause_enable_reg) and pause_any;
pause_pipeline <= pause_mult_clock and pause_enable_reg;
rd_indexD <= rd_index_reg;
-- The value written back into the register bank, signal reg_dest is tricky.
-- If reg_dest comes from the ALU via the signal c_bus, it is already delayed
-- into stage #3, because a_busD and b_busD are delayed. If reg_dest comes from
-- c_memory, pc_current, or pc_plus4 then reg_dest hasn't yet been delayed into
-- stage #3.
-- Instead of delaying c_memory, pc_current, and pc_plus4, these signals
-- are multiplexed into reg_dest which is then delayed. The decision to use
-- the already delayed c_bus or the delayed value of reg_dest (reg_dest_reg) is
-- based on a delayed value of c_source (c_source_reg).
if c_source_reg = C_FROM_ALU then
reg_dest_delay <= c_bus; --delayed by 1 clock cycle via a_busD & b_busD
else
reg_dest_delay <= reg_dest_reg; --need to delay 1 clock cycle from reg_dest
end if;
reg_destD <= reg_dest_delay;
if reset = '1' then
a_busD <= ZERO;
b_busD <= ZERO;
alu_funcD <= ALU_NOTHING;
shift_funcD <= SHIFT_NOTHING;
mult_funcD <= MULT_NOTHING;
reg_dest_reg <= ZERO;
c_source_reg <= "000";
rd_index_reg <= "000000";
pause_enable_reg <= '0';
elsif rising_edge(clk) then
if freeze_pipeline = '0' then
if (rs_index = "000000" or rs_index /= rd_index_reg) or
(a_source /= A_FROM_REG_SOURCE or pause_enable_reg = '0') then
a_busD <= a_bus;
else
a_busD <= reg_dest_delay; --rs from previous operation (bypass stage)
end if;
if (rt_index = "000000" or rt_index /= rd_index_reg) or
(b_source /= B_FROM_REG_TARGET or pause_enable_reg = '0') then
b_busD <= b_bus;
else
b_busD <= reg_dest_delay; --rt from previous operation
end if;
alu_funcD <= alu_func;
shift_funcD <= shift_func;
mult_funcD <= mult_func;
reg_dest_reg <= reg_dest;
c_source_reg <= c_source;
rd_index_reg <= rd_index;
end if;
if pause_enable_reg = '0' and pause_any = '0' then
pause_enable_reg <= '1'; --enable pause_pipeline
elsif pause_mult_clock = '1' then
pause_enable_reg <= '0'; --disable pause_pipeline
end if;
end if;
end process; --pipeline3
end; --logic
|
---------------------------------------------------------------------
-- TITLE: Pipeline
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 6/24/02
-- FILENAME: pipeline.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Controls the three stage pipeline by delaying the signals:
-- a_bus, b_bus, alu/shift/mult_func, c_source, and rs_index.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
--Note: sigD <= sig after rising_edge(clk)
entity pipeline is
port(clk : in std_logic;
reset : in std_logic;
a_bus : in std_logic_vector(31 downto 0);
a_busD : out std_logic_vector(31 downto 0);
b_bus : in std_logic_vector(31 downto 0);
b_busD : out std_logic_vector(31 downto 0);
alu_func : in alu_function_type;
alu_funcD : out alu_function_type;
shift_func : in shift_function_type;
shift_funcD : out shift_function_type;
mult_func : in mult_function_type;
mult_funcD : out mult_function_type;
reg_dest : in std_logic_vector(31 downto 0);
reg_destD : out std_logic_vector(31 downto 0);
rd_index : in std_logic_vector(5 downto 0);
rd_indexD : out std_logic_vector(5 downto 0);
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
pc_source : in pc_source_type;
mem_source : in mem_source_type;
a_source : in a_source_type;
b_source : in b_source_type;
c_source : in c_source_type;
c_bus : in std_logic_vector(31 downto 0);
pause_any : in std_logic;
pause_pipeline : out std_logic);
end; --entity pipeline
architecture logic of pipeline is
signal rd_index_reg : std_logic_vector(5 downto 0);
signal reg_dest_reg : std_logic_vector(31 downto 0);
signal reg_dest_delay : std_logic_vector(31 downto 0);
signal c_source_reg : c_source_type;
signal pause_enable_reg : std_logic;
begin
--When operating in three stage pipeline mode, the following signals
--are delayed by one clock cycle: a_bus, b_bus, alu/shift/mult_func,
--c_source, and rd_index.
pipeline3: process(clk, reset, a_bus, b_bus, alu_func, shift_func, mult_func,
rd_index, rd_index_reg, pause_any, pause_enable_reg,
rs_index, rt_index,
pc_source, mem_source, a_source, b_source, c_source, c_source_reg,
reg_dest, reg_dest_reg, reg_dest_delay, c_bus)
variable pause_mult_clock : std_logic;
variable freeze_pipeline : std_logic;
begin
if (pc_source /= FROM_INC4 and pc_source /= FROM_OPCODE25_0) or
mem_source /= MEM_FETCH or
(mult_func = MULT_READ_LO or mult_func = MULT_READ_HI) then
pause_mult_clock := '1';
else
pause_mult_clock := '0';
end if;
freeze_pipeline := not (pause_mult_clock and pause_enable_reg) and pause_any;
pause_pipeline <= pause_mult_clock and pause_enable_reg;
rd_indexD <= rd_index_reg;
-- The value written back into the register bank, signal reg_dest is tricky.
-- If reg_dest comes from the ALU via the signal c_bus, it is already delayed
-- into stage #3, because a_busD and b_busD are delayed. If reg_dest comes from
-- c_memory, pc_current, or pc_plus4 then reg_dest hasn't yet been delayed into
-- stage #3.
-- Instead of delaying c_memory, pc_current, and pc_plus4, these signals
-- are multiplexed into reg_dest which is then delayed. The decision to use
-- the already delayed c_bus or the delayed value of reg_dest (reg_dest_reg) is
-- based on a delayed value of c_source (c_source_reg).
if c_source_reg = C_FROM_ALU then
reg_dest_delay <= c_bus; --delayed by 1 clock cycle via a_busD & b_busD
else
reg_dest_delay <= reg_dest_reg; --need to delay 1 clock cycle from reg_dest
end if;
reg_destD <= reg_dest_delay;
if reset = '1' then
a_busD <= ZERO;
b_busD <= ZERO;
alu_funcD <= ALU_NOTHING;
shift_funcD <= SHIFT_NOTHING;
mult_funcD <= MULT_NOTHING;
reg_dest_reg <= ZERO;
c_source_reg <= "000";
rd_index_reg <= "000000";
pause_enable_reg <= '0';
elsif rising_edge(clk) then
if freeze_pipeline = '0' then
if (rs_index = "000000" or rs_index /= rd_index_reg) or
(a_source /= A_FROM_REG_SOURCE or pause_enable_reg = '0') then
a_busD <= a_bus;
else
a_busD <= reg_dest_delay; --rs from previous operation (bypass stage)
end if;
if (rt_index = "000000" or rt_index /= rd_index_reg) or
(b_source /= B_FROM_REG_TARGET or pause_enable_reg = '0') then
b_busD <= b_bus;
else
b_busD <= reg_dest_delay; --rt from previous operation
end if;
alu_funcD <= alu_func;
shift_funcD <= shift_func;
mult_funcD <= mult_func;
reg_dest_reg <= reg_dest;
c_source_reg <= c_source;
rd_index_reg <= rd_index;
end if;
if pause_enable_reg = '0' and pause_any = '0' then
pause_enable_reg <= '1'; --enable pause_pipeline
elsif pause_mult_clock = '1' then
pause_enable_reg <= '0'; --disable pause_pipeline
end if;
end if;
end process; --pipeline3
end; --logic
|
---------------------------------------------------------------------
-- TITLE: Pipeline
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 6/24/02
-- FILENAME: pipeline.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Controls the three stage pipeline by delaying the signals:
-- a_bus, b_bus, alu/shift/mult_func, c_source, and rs_index.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
--Note: sigD <= sig after rising_edge(clk)
entity pipeline is
port(clk : in std_logic;
reset : in std_logic;
a_bus : in std_logic_vector(31 downto 0);
a_busD : out std_logic_vector(31 downto 0);
b_bus : in std_logic_vector(31 downto 0);
b_busD : out std_logic_vector(31 downto 0);
alu_func : in alu_function_type;
alu_funcD : out alu_function_type;
shift_func : in shift_function_type;
shift_funcD : out shift_function_type;
mult_func : in mult_function_type;
mult_funcD : out mult_function_type;
reg_dest : in std_logic_vector(31 downto 0);
reg_destD : out std_logic_vector(31 downto 0);
rd_index : in std_logic_vector(5 downto 0);
rd_indexD : out std_logic_vector(5 downto 0);
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
pc_source : in pc_source_type;
mem_source : in mem_source_type;
a_source : in a_source_type;
b_source : in b_source_type;
c_source : in c_source_type;
c_bus : in std_logic_vector(31 downto 0);
pause_any : in std_logic;
pause_pipeline : out std_logic);
end; --entity pipeline
architecture logic of pipeline is
signal rd_index_reg : std_logic_vector(5 downto 0);
signal reg_dest_reg : std_logic_vector(31 downto 0);
signal reg_dest_delay : std_logic_vector(31 downto 0);
signal c_source_reg : c_source_type;
signal pause_enable_reg : std_logic;
begin
--When operating in three stage pipeline mode, the following signals
--are delayed by one clock cycle: a_bus, b_bus, alu/shift/mult_func,
--c_source, and rd_index.
pipeline3: process(clk, reset, a_bus, b_bus, alu_func, shift_func, mult_func,
rd_index, rd_index_reg, pause_any, pause_enable_reg,
rs_index, rt_index,
pc_source, mem_source, a_source, b_source, c_source, c_source_reg,
reg_dest, reg_dest_reg, reg_dest_delay, c_bus)
variable pause_mult_clock : std_logic;
variable freeze_pipeline : std_logic;
begin
if (pc_source /= FROM_INC4 and pc_source /= FROM_OPCODE25_0) or
mem_source /= MEM_FETCH or
(mult_func = MULT_READ_LO or mult_func = MULT_READ_HI) then
pause_mult_clock := '1';
else
pause_mult_clock := '0';
end if;
freeze_pipeline := not (pause_mult_clock and pause_enable_reg) and pause_any;
pause_pipeline <= pause_mult_clock and pause_enable_reg;
rd_indexD <= rd_index_reg;
-- The value written back into the register bank, signal reg_dest is tricky.
-- If reg_dest comes from the ALU via the signal c_bus, it is already delayed
-- into stage #3, because a_busD and b_busD are delayed. If reg_dest comes from
-- c_memory, pc_current, or pc_plus4 then reg_dest hasn't yet been delayed into
-- stage #3.
-- Instead of delaying c_memory, pc_current, and pc_plus4, these signals
-- are multiplexed into reg_dest which is then delayed. The decision to use
-- the already delayed c_bus or the delayed value of reg_dest (reg_dest_reg) is
-- based on a delayed value of c_source (c_source_reg).
if c_source_reg = C_FROM_ALU then
reg_dest_delay <= c_bus; --delayed by 1 clock cycle via a_busD & b_busD
else
reg_dest_delay <= reg_dest_reg; --need to delay 1 clock cycle from reg_dest
end if;
reg_destD <= reg_dest_delay;
if reset = '1' then
a_busD <= ZERO;
b_busD <= ZERO;
alu_funcD <= ALU_NOTHING;
shift_funcD <= SHIFT_NOTHING;
mult_funcD <= MULT_NOTHING;
reg_dest_reg <= ZERO;
c_source_reg <= "000";
rd_index_reg <= "000000";
pause_enable_reg <= '0';
elsif rising_edge(clk) then
if freeze_pipeline = '0' then
if (rs_index = "000000" or rs_index /= rd_index_reg) or
(a_source /= A_FROM_REG_SOURCE or pause_enable_reg = '0') then
a_busD <= a_bus;
else
a_busD <= reg_dest_delay; --rs from previous operation (bypass stage)
end if;
if (rt_index = "000000" or rt_index /= rd_index_reg) or
(b_source /= B_FROM_REG_TARGET or pause_enable_reg = '0') then
b_busD <= b_bus;
else
b_busD <= reg_dest_delay; --rt from previous operation
end if;
alu_funcD <= alu_func;
shift_funcD <= shift_func;
mult_funcD <= mult_func;
reg_dest_reg <= reg_dest;
c_source_reg <= c_source;
rd_index_reg <= rd_index;
end if;
if pause_enable_reg = '0' and pause_any = '0' then
pause_enable_reg <= '1'; --enable pause_pipeline
elsif pause_mult_clock = '1' then
pause_enable_reg <= '0'; --disable pause_pipeline
end if;
end if;
end process; --pipeline3
end; --logic
|
---------------------------------------------------------------------
-- TITLE: Pipeline
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 6/24/02
-- FILENAME: pipeline.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Controls the three stage pipeline by delaying the signals:
-- a_bus, b_bus, alu/shift/mult_func, c_source, and rs_index.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
--Note: sigD <= sig after rising_edge(clk)
entity pipeline is
port(clk : in std_logic;
reset : in std_logic;
a_bus : in std_logic_vector(31 downto 0);
a_busD : out std_logic_vector(31 downto 0);
b_bus : in std_logic_vector(31 downto 0);
b_busD : out std_logic_vector(31 downto 0);
alu_func : in alu_function_type;
alu_funcD : out alu_function_type;
shift_func : in shift_function_type;
shift_funcD : out shift_function_type;
mult_func : in mult_function_type;
mult_funcD : out mult_function_type;
reg_dest : in std_logic_vector(31 downto 0);
reg_destD : out std_logic_vector(31 downto 0);
rd_index : in std_logic_vector(5 downto 0);
rd_indexD : out std_logic_vector(5 downto 0);
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
pc_source : in pc_source_type;
mem_source : in mem_source_type;
a_source : in a_source_type;
b_source : in b_source_type;
c_source : in c_source_type;
c_bus : in std_logic_vector(31 downto 0);
pause_any : in std_logic;
pause_pipeline : out std_logic);
end; --entity pipeline
architecture logic of pipeline is
signal rd_index_reg : std_logic_vector(5 downto 0);
signal reg_dest_reg : std_logic_vector(31 downto 0);
signal reg_dest_delay : std_logic_vector(31 downto 0);
signal c_source_reg : c_source_type;
signal pause_enable_reg : std_logic;
begin
--When operating in three stage pipeline mode, the following signals
--are delayed by one clock cycle: a_bus, b_bus, alu/shift/mult_func,
--c_source, and rd_index.
pipeline3: process(clk, reset, a_bus, b_bus, alu_func, shift_func, mult_func,
rd_index, rd_index_reg, pause_any, pause_enable_reg,
rs_index, rt_index,
pc_source, mem_source, a_source, b_source, c_source, c_source_reg,
reg_dest, reg_dest_reg, reg_dest_delay, c_bus)
variable pause_mult_clock : std_logic;
variable freeze_pipeline : std_logic;
begin
if (pc_source /= FROM_INC4 and pc_source /= FROM_OPCODE25_0) or
mem_source /= MEM_FETCH or
(mult_func = MULT_READ_LO or mult_func = MULT_READ_HI) then
pause_mult_clock := '1';
else
pause_mult_clock := '0';
end if;
freeze_pipeline := not (pause_mult_clock and pause_enable_reg) and pause_any;
pause_pipeline <= pause_mult_clock and pause_enable_reg;
rd_indexD <= rd_index_reg;
-- The value written back into the register bank, signal reg_dest is tricky.
-- If reg_dest comes from the ALU via the signal c_bus, it is already delayed
-- into stage #3, because a_busD and b_busD are delayed. If reg_dest comes from
-- c_memory, pc_current, or pc_plus4 then reg_dest hasn't yet been delayed into
-- stage #3.
-- Instead of delaying c_memory, pc_current, and pc_plus4, these signals
-- are multiplexed into reg_dest which is then delayed. The decision to use
-- the already delayed c_bus or the delayed value of reg_dest (reg_dest_reg) is
-- based on a delayed value of c_source (c_source_reg).
if c_source_reg = C_FROM_ALU then
reg_dest_delay <= c_bus; --delayed by 1 clock cycle via a_busD & b_busD
else
reg_dest_delay <= reg_dest_reg; --need to delay 1 clock cycle from reg_dest
end if;
reg_destD <= reg_dest_delay;
if reset = '1' then
a_busD <= ZERO;
b_busD <= ZERO;
alu_funcD <= ALU_NOTHING;
shift_funcD <= SHIFT_NOTHING;
mult_funcD <= MULT_NOTHING;
reg_dest_reg <= ZERO;
c_source_reg <= "000";
rd_index_reg <= "000000";
pause_enable_reg <= '0';
elsif rising_edge(clk) then
if freeze_pipeline = '0' then
if (rs_index = "000000" or rs_index /= rd_index_reg) or
(a_source /= A_FROM_REG_SOURCE or pause_enable_reg = '0') then
a_busD <= a_bus;
else
a_busD <= reg_dest_delay; --rs from previous operation (bypass stage)
end if;
if (rt_index = "000000" or rt_index /= rd_index_reg) or
(b_source /= B_FROM_REG_TARGET or pause_enable_reg = '0') then
b_busD <= b_bus;
else
b_busD <= reg_dest_delay; --rt from previous operation
end if;
alu_funcD <= alu_func;
shift_funcD <= shift_func;
mult_funcD <= mult_func;
reg_dest_reg <= reg_dest;
c_source_reg <= c_source;
rd_index_reg <= rd_index;
end if;
if pause_enable_reg = '0' and pause_any = '0' then
pause_enable_reg <= '1'; --enable pause_pipeline
elsif pause_mult_clock = '1' then
pause_enable_reg <= '0'; --disable pause_pipeline
end if;
end if;
end process; --pipeline3
end; --logic
|
---------------------------------------------------------------------
-- TITLE: Pipeline
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 6/24/02
-- FILENAME: pipeline.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Controls the three stage pipeline by delaying the signals:
-- a_bus, b_bus, alu/shift/mult_func, c_source, and rs_index.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
--Note: sigD <= sig after rising_edge(clk)
entity pipeline is
port(clk : in std_logic;
reset : in std_logic;
a_bus : in std_logic_vector(31 downto 0);
a_busD : out std_logic_vector(31 downto 0);
b_bus : in std_logic_vector(31 downto 0);
b_busD : out std_logic_vector(31 downto 0);
alu_func : in alu_function_type;
alu_funcD : out alu_function_type;
shift_func : in shift_function_type;
shift_funcD : out shift_function_type;
mult_func : in mult_function_type;
mult_funcD : out mult_function_type;
reg_dest : in std_logic_vector(31 downto 0);
reg_destD : out std_logic_vector(31 downto 0);
rd_index : in std_logic_vector(5 downto 0);
rd_indexD : out std_logic_vector(5 downto 0);
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
pc_source : in pc_source_type;
mem_source : in mem_source_type;
a_source : in a_source_type;
b_source : in b_source_type;
c_source : in c_source_type;
c_bus : in std_logic_vector(31 downto 0);
pause_any : in std_logic;
pause_pipeline : out std_logic);
end; --entity pipeline
architecture logic of pipeline is
signal rd_index_reg : std_logic_vector(5 downto 0);
signal reg_dest_reg : std_logic_vector(31 downto 0);
signal reg_dest_delay : std_logic_vector(31 downto 0);
signal c_source_reg : c_source_type;
signal pause_enable_reg : std_logic;
begin
--When operating in three stage pipeline mode, the following signals
--are delayed by one clock cycle: a_bus, b_bus, alu/shift/mult_func,
--c_source, and rd_index.
pipeline3: process(clk, reset, a_bus, b_bus, alu_func, shift_func, mult_func,
rd_index, rd_index_reg, pause_any, pause_enable_reg,
rs_index, rt_index,
pc_source, mem_source, a_source, b_source, c_source, c_source_reg,
reg_dest, reg_dest_reg, reg_dest_delay, c_bus)
variable pause_mult_clock : std_logic;
variable freeze_pipeline : std_logic;
begin
if (pc_source /= FROM_INC4 and pc_source /= FROM_OPCODE25_0) or
mem_source /= MEM_FETCH or
(mult_func = MULT_READ_LO or mult_func = MULT_READ_HI) then
pause_mult_clock := '1';
else
pause_mult_clock := '0';
end if;
freeze_pipeline := not (pause_mult_clock and pause_enable_reg) and pause_any;
pause_pipeline <= pause_mult_clock and pause_enable_reg;
rd_indexD <= rd_index_reg;
-- The value written back into the register bank, signal reg_dest is tricky.
-- If reg_dest comes from the ALU via the signal c_bus, it is already delayed
-- into stage #3, because a_busD and b_busD are delayed. If reg_dest comes from
-- c_memory, pc_current, or pc_plus4 then reg_dest hasn't yet been delayed into
-- stage #3.
-- Instead of delaying c_memory, pc_current, and pc_plus4, these signals
-- are multiplexed into reg_dest which is then delayed. The decision to use
-- the already delayed c_bus or the delayed value of reg_dest (reg_dest_reg) is
-- based on a delayed value of c_source (c_source_reg).
if c_source_reg = C_FROM_ALU then
reg_dest_delay <= c_bus; --delayed by 1 clock cycle via a_busD & b_busD
else
reg_dest_delay <= reg_dest_reg; --need to delay 1 clock cycle from reg_dest
end if;
reg_destD <= reg_dest_delay;
if reset = '1' then
a_busD <= ZERO;
b_busD <= ZERO;
alu_funcD <= ALU_NOTHING;
shift_funcD <= SHIFT_NOTHING;
mult_funcD <= MULT_NOTHING;
reg_dest_reg <= ZERO;
c_source_reg <= "000";
rd_index_reg <= "000000";
pause_enable_reg <= '0';
elsif rising_edge(clk) then
if freeze_pipeline = '0' then
if (rs_index = "000000" or rs_index /= rd_index_reg) or
(a_source /= A_FROM_REG_SOURCE or pause_enable_reg = '0') then
a_busD <= a_bus;
else
a_busD <= reg_dest_delay; --rs from previous operation (bypass stage)
end if;
if (rt_index = "000000" or rt_index /= rd_index_reg) or
(b_source /= B_FROM_REG_TARGET or pause_enable_reg = '0') then
b_busD <= b_bus;
else
b_busD <= reg_dest_delay; --rt from previous operation
end if;
alu_funcD <= alu_func;
shift_funcD <= shift_func;
mult_funcD <= mult_func;
reg_dest_reg <= reg_dest;
c_source_reg <= c_source;
rd_index_reg <= rd_index;
end if;
if pause_enable_reg = '0' and pause_any = '0' then
pause_enable_reg <= '1'; --enable pause_pipeline
elsif pause_mult_clock = '1' then
pause_enable_reg <= '0'; --disable pause_pipeline
end if;
end if;
end process; --pipeline3
end; --logic
|
---------------------------------------------------------------------
-- TITLE: Pipeline
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 6/24/02
-- FILENAME: pipeline.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Controls the three stage pipeline by delaying the signals:
-- a_bus, b_bus, alu/shift/mult_func, c_source, and rs_index.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
--Note: sigD <= sig after rising_edge(clk)
entity pipeline is
port(clk : in std_logic;
reset : in std_logic;
a_bus : in std_logic_vector(31 downto 0);
a_busD : out std_logic_vector(31 downto 0);
b_bus : in std_logic_vector(31 downto 0);
b_busD : out std_logic_vector(31 downto 0);
alu_func : in alu_function_type;
alu_funcD : out alu_function_type;
shift_func : in shift_function_type;
shift_funcD : out shift_function_type;
mult_func : in mult_function_type;
mult_funcD : out mult_function_type;
reg_dest : in std_logic_vector(31 downto 0);
reg_destD : out std_logic_vector(31 downto 0);
rd_index : in std_logic_vector(5 downto 0);
rd_indexD : out std_logic_vector(5 downto 0);
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
pc_source : in pc_source_type;
mem_source : in mem_source_type;
a_source : in a_source_type;
b_source : in b_source_type;
c_source : in c_source_type;
c_bus : in std_logic_vector(31 downto 0);
pause_any : in std_logic;
pause_pipeline : out std_logic);
end; --entity pipeline
architecture logic of pipeline is
signal rd_index_reg : std_logic_vector(5 downto 0);
signal reg_dest_reg : std_logic_vector(31 downto 0);
signal reg_dest_delay : std_logic_vector(31 downto 0);
signal c_source_reg : c_source_type;
signal pause_enable_reg : std_logic;
begin
--When operating in three stage pipeline mode, the following signals
--are delayed by one clock cycle: a_bus, b_bus, alu/shift/mult_func,
--c_source, and rd_index.
pipeline3: process(clk, reset, a_bus, b_bus, alu_func, shift_func, mult_func,
rd_index, rd_index_reg, pause_any, pause_enable_reg,
rs_index, rt_index,
pc_source, mem_source, a_source, b_source, c_source, c_source_reg,
reg_dest, reg_dest_reg, reg_dest_delay, c_bus)
variable pause_mult_clock : std_logic;
variable freeze_pipeline : std_logic;
begin
if (pc_source /= FROM_INC4 and pc_source /= FROM_OPCODE25_0) or
mem_source /= MEM_FETCH or
(mult_func = MULT_READ_LO or mult_func = MULT_READ_HI) then
pause_mult_clock := '1';
else
pause_mult_clock := '0';
end if;
freeze_pipeline := not (pause_mult_clock and pause_enable_reg) and pause_any;
pause_pipeline <= pause_mult_clock and pause_enable_reg;
rd_indexD <= rd_index_reg;
-- The value written back into the register bank, signal reg_dest is tricky.
-- If reg_dest comes from the ALU via the signal c_bus, it is already delayed
-- into stage #3, because a_busD and b_busD are delayed. If reg_dest comes from
-- c_memory, pc_current, or pc_plus4 then reg_dest hasn't yet been delayed into
-- stage #3.
-- Instead of delaying c_memory, pc_current, and pc_plus4, these signals
-- are multiplexed into reg_dest which is then delayed. The decision to use
-- the already delayed c_bus or the delayed value of reg_dest (reg_dest_reg) is
-- based on a delayed value of c_source (c_source_reg).
if c_source_reg = C_FROM_ALU then
reg_dest_delay <= c_bus; --delayed by 1 clock cycle via a_busD & b_busD
else
reg_dest_delay <= reg_dest_reg; --need to delay 1 clock cycle from reg_dest
end if;
reg_destD <= reg_dest_delay;
if reset = '1' then
a_busD <= ZERO;
b_busD <= ZERO;
alu_funcD <= ALU_NOTHING;
shift_funcD <= SHIFT_NOTHING;
mult_funcD <= MULT_NOTHING;
reg_dest_reg <= ZERO;
c_source_reg <= "000";
rd_index_reg <= "000000";
pause_enable_reg <= '0';
elsif rising_edge(clk) then
if freeze_pipeline = '0' then
if (rs_index = "000000" or rs_index /= rd_index_reg) or
(a_source /= A_FROM_REG_SOURCE or pause_enable_reg = '0') then
a_busD <= a_bus;
else
a_busD <= reg_dest_delay; --rs from previous operation (bypass stage)
end if;
if (rt_index = "000000" or rt_index /= rd_index_reg) or
(b_source /= B_FROM_REG_TARGET or pause_enable_reg = '0') then
b_busD <= b_bus;
else
b_busD <= reg_dest_delay; --rt from previous operation
end if;
alu_funcD <= alu_func;
shift_funcD <= shift_func;
mult_funcD <= mult_func;
reg_dest_reg <= reg_dest;
c_source_reg <= c_source;
rd_index_reg <= rd_index;
end if;
if pause_enable_reg = '0' and pause_any = '0' then
pause_enable_reg <= '1'; --enable pause_pipeline
elsif pause_mult_clock = '1' then
pause_enable_reg <= '0'; --disable pause_pipeline
end if;
end if;
end process; --pipeline3
end; --logic
|
---------------------------------------------------------------------
-- TITLE: Pipeline
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 6/24/02
-- FILENAME: pipeline.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Controls the three stage pipeline by delaying the signals:
-- a_bus, b_bus, alu/shift/mult_func, c_source, and rs_index.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
--Note: sigD <= sig after rising_edge(clk)
entity pipeline is
port(clk : in std_logic;
reset : in std_logic;
a_bus : in std_logic_vector(31 downto 0);
a_busD : out std_logic_vector(31 downto 0);
b_bus : in std_logic_vector(31 downto 0);
b_busD : out std_logic_vector(31 downto 0);
alu_func : in alu_function_type;
alu_funcD : out alu_function_type;
shift_func : in shift_function_type;
shift_funcD : out shift_function_type;
mult_func : in mult_function_type;
mult_funcD : out mult_function_type;
reg_dest : in std_logic_vector(31 downto 0);
reg_destD : out std_logic_vector(31 downto 0);
rd_index : in std_logic_vector(5 downto 0);
rd_indexD : out std_logic_vector(5 downto 0);
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
pc_source : in pc_source_type;
mem_source : in mem_source_type;
a_source : in a_source_type;
b_source : in b_source_type;
c_source : in c_source_type;
c_bus : in std_logic_vector(31 downto 0);
pause_any : in std_logic;
pause_pipeline : out std_logic);
end; --entity pipeline
architecture logic of pipeline is
signal rd_index_reg : std_logic_vector(5 downto 0);
signal reg_dest_reg : std_logic_vector(31 downto 0);
signal reg_dest_delay : std_logic_vector(31 downto 0);
signal c_source_reg : c_source_type;
signal pause_enable_reg : std_logic;
begin
--When operating in three stage pipeline mode, the following signals
--are delayed by one clock cycle: a_bus, b_bus, alu/shift/mult_func,
--c_source, and rd_index.
pipeline3: process(clk, reset, a_bus, b_bus, alu_func, shift_func, mult_func,
rd_index, rd_index_reg, pause_any, pause_enable_reg,
rs_index, rt_index,
pc_source, mem_source, a_source, b_source, c_source, c_source_reg,
reg_dest, reg_dest_reg, reg_dest_delay, c_bus)
variable pause_mult_clock : std_logic;
variable freeze_pipeline : std_logic;
begin
if (pc_source /= FROM_INC4 and pc_source /= FROM_OPCODE25_0) or
mem_source /= MEM_FETCH or
(mult_func = MULT_READ_LO or mult_func = MULT_READ_HI) then
pause_mult_clock := '1';
else
pause_mult_clock := '0';
end if;
freeze_pipeline := not (pause_mult_clock and pause_enable_reg) and pause_any;
pause_pipeline <= pause_mult_clock and pause_enable_reg;
rd_indexD <= rd_index_reg;
-- The value written back into the register bank, signal reg_dest is tricky.
-- If reg_dest comes from the ALU via the signal c_bus, it is already delayed
-- into stage #3, because a_busD and b_busD are delayed. If reg_dest comes from
-- c_memory, pc_current, or pc_plus4 then reg_dest hasn't yet been delayed into
-- stage #3.
-- Instead of delaying c_memory, pc_current, and pc_plus4, these signals
-- are multiplexed into reg_dest which is then delayed. The decision to use
-- the already delayed c_bus or the delayed value of reg_dest (reg_dest_reg) is
-- based on a delayed value of c_source (c_source_reg).
if c_source_reg = C_FROM_ALU then
reg_dest_delay <= c_bus; --delayed by 1 clock cycle via a_busD & b_busD
else
reg_dest_delay <= reg_dest_reg; --need to delay 1 clock cycle from reg_dest
end if;
reg_destD <= reg_dest_delay;
if reset = '1' then
a_busD <= ZERO;
b_busD <= ZERO;
alu_funcD <= ALU_NOTHING;
shift_funcD <= SHIFT_NOTHING;
mult_funcD <= MULT_NOTHING;
reg_dest_reg <= ZERO;
c_source_reg <= "000";
rd_index_reg <= "000000";
pause_enable_reg <= '0';
elsif rising_edge(clk) then
if freeze_pipeline = '0' then
if (rs_index = "000000" or rs_index /= rd_index_reg) or
(a_source /= A_FROM_REG_SOURCE or pause_enable_reg = '0') then
a_busD <= a_bus;
else
a_busD <= reg_dest_delay; --rs from previous operation (bypass stage)
end if;
if (rt_index = "000000" or rt_index /= rd_index_reg) or
(b_source /= B_FROM_REG_TARGET or pause_enable_reg = '0') then
b_busD <= b_bus;
else
b_busD <= reg_dest_delay; --rt from previous operation
end if;
alu_funcD <= alu_func;
shift_funcD <= shift_func;
mult_funcD <= mult_func;
reg_dest_reg <= reg_dest;
c_source_reg <= c_source;
rd_index_reg <= rd_index;
end if;
if pause_enable_reg = '0' and pause_any = '0' then
pause_enable_reg <= '1'; --enable pause_pipeline
elsif pause_mult_clock = '1' then
pause_enable_reg <= '0'; --disable pause_pipeline
end if;
end if;
end process; --pipeline3
end; --logic
|
---------------------------------------------------------------------
-- TITLE: Pipeline
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 6/24/02
-- FILENAME: pipeline.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Controls the three stage pipeline by delaying the signals:
-- a_bus, b_bus, alu/shift/mult_func, c_source, and rs_index.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
--Note: sigD <= sig after rising_edge(clk)
entity pipeline is
port(clk : in std_logic;
reset : in std_logic;
a_bus : in std_logic_vector(31 downto 0);
a_busD : out std_logic_vector(31 downto 0);
b_bus : in std_logic_vector(31 downto 0);
b_busD : out std_logic_vector(31 downto 0);
alu_func : in alu_function_type;
alu_funcD : out alu_function_type;
shift_func : in shift_function_type;
shift_funcD : out shift_function_type;
mult_func : in mult_function_type;
mult_funcD : out mult_function_type;
reg_dest : in std_logic_vector(31 downto 0);
reg_destD : out std_logic_vector(31 downto 0);
rd_index : in std_logic_vector(5 downto 0);
rd_indexD : out std_logic_vector(5 downto 0);
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
pc_source : in pc_source_type;
mem_source : in mem_source_type;
a_source : in a_source_type;
b_source : in b_source_type;
c_source : in c_source_type;
c_bus : in std_logic_vector(31 downto 0);
pause_any : in std_logic;
pause_pipeline : out std_logic);
end; --entity pipeline
architecture logic of pipeline is
signal rd_index_reg : std_logic_vector(5 downto 0);
signal reg_dest_reg : std_logic_vector(31 downto 0);
signal reg_dest_delay : std_logic_vector(31 downto 0);
signal c_source_reg : c_source_type;
signal pause_enable_reg : std_logic;
begin
--When operating in three stage pipeline mode, the following signals
--are delayed by one clock cycle: a_bus, b_bus, alu/shift/mult_func,
--c_source, and rd_index.
pipeline3: process(clk, reset, a_bus, b_bus, alu_func, shift_func, mult_func,
rd_index, rd_index_reg, pause_any, pause_enable_reg,
rs_index, rt_index,
pc_source, mem_source, a_source, b_source, c_source, c_source_reg,
reg_dest, reg_dest_reg, reg_dest_delay, c_bus)
variable pause_mult_clock : std_logic;
variable freeze_pipeline : std_logic;
begin
if (pc_source /= FROM_INC4 and pc_source /= FROM_OPCODE25_0) or
mem_source /= MEM_FETCH or
(mult_func = MULT_READ_LO or mult_func = MULT_READ_HI) then
pause_mult_clock := '1';
else
pause_mult_clock := '0';
end if;
freeze_pipeline := not (pause_mult_clock and pause_enable_reg) and pause_any;
pause_pipeline <= pause_mult_clock and pause_enable_reg;
rd_indexD <= rd_index_reg;
-- The value written back into the register bank, signal reg_dest is tricky.
-- If reg_dest comes from the ALU via the signal c_bus, it is already delayed
-- into stage #3, because a_busD and b_busD are delayed. If reg_dest comes from
-- c_memory, pc_current, or pc_plus4 then reg_dest hasn't yet been delayed into
-- stage #3.
-- Instead of delaying c_memory, pc_current, and pc_plus4, these signals
-- are multiplexed into reg_dest which is then delayed. The decision to use
-- the already delayed c_bus or the delayed value of reg_dest (reg_dest_reg) is
-- based on a delayed value of c_source (c_source_reg).
if c_source_reg = C_FROM_ALU then
reg_dest_delay <= c_bus; --delayed by 1 clock cycle via a_busD & b_busD
else
reg_dest_delay <= reg_dest_reg; --need to delay 1 clock cycle from reg_dest
end if;
reg_destD <= reg_dest_delay;
if reset = '1' then
a_busD <= ZERO;
b_busD <= ZERO;
alu_funcD <= ALU_NOTHING;
shift_funcD <= SHIFT_NOTHING;
mult_funcD <= MULT_NOTHING;
reg_dest_reg <= ZERO;
c_source_reg <= "000";
rd_index_reg <= "000000";
pause_enable_reg <= '0';
elsif rising_edge(clk) then
if freeze_pipeline = '0' then
if (rs_index = "000000" or rs_index /= rd_index_reg) or
(a_source /= A_FROM_REG_SOURCE or pause_enable_reg = '0') then
a_busD <= a_bus;
else
a_busD <= reg_dest_delay; --rs from previous operation (bypass stage)
end if;
if (rt_index = "000000" or rt_index /= rd_index_reg) or
(b_source /= B_FROM_REG_TARGET or pause_enable_reg = '0') then
b_busD <= b_bus;
else
b_busD <= reg_dest_delay; --rt from previous operation
end if;
alu_funcD <= alu_func;
shift_funcD <= shift_func;
mult_funcD <= mult_func;
reg_dest_reg <= reg_dest;
c_source_reg <= c_source;
rd_index_reg <= rd_index;
end if;
if pause_enable_reg = '0' and pause_any = '0' then
pause_enable_reg <= '1'; --enable pause_pipeline
elsif pause_mult_clock = '1' then
pause_enable_reg <= '0'; --disable pause_pipeline
end if;
end if;
end process; --pipeline3
end; --logic
|
---------------------------------------------------------------------
-- TITLE: Pipeline
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 6/24/02
-- FILENAME: pipeline.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Controls the three stage pipeline by delaying the signals:
-- a_bus, b_bus, alu/shift/mult_func, c_source, and rs_index.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
--Note: sigD <= sig after rising_edge(clk)
entity pipeline is
port(clk : in std_logic;
reset : in std_logic;
a_bus : in std_logic_vector(31 downto 0);
a_busD : out std_logic_vector(31 downto 0);
b_bus : in std_logic_vector(31 downto 0);
b_busD : out std_logic_vector(31 downto 0);
alu_func : in alu_function_type;
alu_funcD : out alu_function_type;
shift_func : in shift_function_type;
shift_funcD : out shift_function_type;
mult_func : in mult_function_type;
mult_funcD : out mult_function_type;
reg_dest : in std_logic_vector(31 downto 0);
reg_destD : out std_logic_vector(31 downto 0);
rd_index : in std_logic_vector(5 downto 0);
rd_indexD : out std_logic_vector(5 downto 0);
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
pc_source : in pc_source_type;
mem_source : in mem_source_type;
a_source : in a_source_type;
b_source : in b_source_type;
c_source : in c_source_type;
c_bus : in std_logic_vector(31 downto 0);
pause_any : in std_logic;
pause_pipeline : out std_logic);
end; --entity pipeline
architecture logic of pipeline is
signal rd_index_reg : std_logic_vector(5 downto 0);
signal reg_dest_reg : std_logic_vector(31 downto 0);
signal reg_dest_delay : std_logic_vector(31 downto 0);
signal c_source_reg : c_source_type;
signal pause_enable_reg : std_logic;
begin
--When operating in three stage pipeline mode, the following signals
--are delayed by one clock cycle: a_bus, b_bus, alu/shift/mult_func,
--c_source, and rd_index.
pipeline3: process(clk, reset, a_bus, b_bus, alu_func, shift_func, mult_func,
rd_index, rd_index_reg, pause_any, pause_enable_reg,
rs_index, rt_index,
pc_source, mem_source, a_source, b_source, c_source, c_source_reg,
reg_dest, reg_dest_reg, reg_dest_delay, c_bus)
variable pause_mult_clock : std_logic;
variable freeze_pipeline : std_logic;
begin
if (pc_source /= FROM_INC4 and pc_source /= FROM_OPCODE25_0) or
mem_source /= MEM_FETCH or
(mult_func = MULT_READ_LO or mult_func = MULT_READ_HI) then
pause_mult_clock := '1';
else
pause_mult_clock := '0';
end if;
freeze_pipeline := not (pause_mult_clock and pause_enable_reg) and pause_any;
pause_pipeline <= pause_mult_clock and pause_enable_reg;
rd_indexD <= rd_index_reg;
-- The value written back into the register bank, signal reg_dest is tricky.
-- If reg_dest comes from the ALU via the signal c_bus, it is already delayed
-- into stage #3, because a_busD and b_busD are delayed. If reg_dest comes from
-- c_memory, pc_current, or pc_plus4 then reg_dest hasn't yet been delayed into
-- stage #3.
-- Instead of delaying c_memory, pc_current, and pc_plus4, these signals
-- are multiplexed into reg_dest which is then delayed. The decision to use
-- the already delayed c_bus or the delayed value of reg_dest (reg_dest_reg) is
-- based on a delayed value of c_source (c_source_reg).
if c_source_reg = C_FROM_ALU then
reg_dest_delay <= c_bus; --delayed by 1 clock cycle via a_busD & b_busD
else
reg_dest_delay <= reg_dest_reg; --need to delay 1 clock cycle from reg_dest
end if;
reg_destD <= reg_dest_delay;
if reset = '1' then
a_busD <= ZERO;
b_busD <= ZERO;
alu_funcD <= ALU_NOTHING;
shift_funcD <= SHIFT_NOTHING;
mult_funcD <= MULT_NOTHING;
reg_dest_reg <= ZERO;
c_source_reg <= "000";
rd_index_reg <= "000000";
pause_enable_reg <= '0';
elsif rising_edge(clk) then
if freeze_pipeline = '0' then
if (rs_index = "000000" or rs_index /= rd_index_reg) or
(a_source /= A_FROM_REG_SOURCE or pause_enable_reg = '0') then
a_busD <= a_bus;
else
a_busD <= reg_dest_delay; --rs from previous operation (bypass stage)
end if;
if (rt_index = "000000" or rt_index /= rd_index_reg) or
(b_source /= B_FROM_REG_TARGET or pause_enable_reg = '0') then
b_busD <= b_bus;
else
b_busD <= reg_dest_delay; --rt from previous operation
end if;
alu_funcD <= alu_func;
shift_funcD <= shift_func;
mult_funcD <= mult_func;
reg_dest_reg <= reg_dest;
c_source_reg <= c_source;
rd_index_reg <= rd_index;
end if;
if pause_enable_reg = '0' and pause_any = '0' then
pause_enable_reg <= '1'; --enable pause_pipeline
elsif pause_mult_clock = '1' then
pause_enable_reg <= '0'; --disable pause_pipeline
end if;
end if;
end process; --pipeline3
end; --logic
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity ANN is
generic (
C_S_AXI_AXILITES_ADDR_WIDTH : INTEGER := 7;
C_S_AXI_AXILITES_DATA_WIDTH : INTEGER := 32 );
port (
ap_clk : IN STD_LOGIC;
ap_rst_n : IN STD_LOGIC;
s_axi_AXILiteS_AWVALID : IN STD_LOGIC;
s_axi_AXILiteS_AWREADY : OUT STD_LOGIC;
s_axi_AXILiteS_AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_ADDR_WIDTH-1 downto 0);
s_axi_AXILiteS_WVALID : IN STD_LOGIC;
s_axi_AXILiteS_WREADY : OUT STD_LOGIC;
s_axi_AXILiteS_WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH-1 downto 0);
s_axi_AXILiteS_WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH/8-1 downto 0);
s_axi_AXILiteS_ARVALID : IN STD_LOGIC;
s_axi_AXILiteS_ARREADY : OUT STD_LOGIC;
s_axi_AXILiteS_ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_AXILITES_ADDR_WIDTH-1 downto 0);
s_axi_AXILiteS_RVALID : OUT STD_LOGIC;
s_axi_AXILiteS_RREADY : IN STD_LOGIC;
s_axi_AXILiteS_RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_AXILITES_DATA_WIDTH-1 downto 0);
s_axi_AXILiteS_RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
s_axi_AXILiteS_BVALID : OUT STD_LOGIC;
s_axi_AXILiteS_BREADY : IN STD_LOGIC;
s_axi_AXILiteS_BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
interrupt : OUT STD_LOGIC );
end;
architecture behav of ANN is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"ANN,hls_ip_2015_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=1,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z010clg400-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=8.621000,HLS_SYN_LAT=-1,HLS_SYN_TPT=none,HLS_SYN_MEM=18,HLS_SYN_DSP=37,HLS_SYN_FF=8607,HLS_SYN_LUT=12250}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000";
constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000";
constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000";
constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000";
constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000";
constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000";
constant ap_ST_st10_fsm_9 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000";
constant ap_ST_st11_fsm_10 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000";
constant ap_ST_st12_fsm_11 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000";
constant ap_ST_st13_fsm_12 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000";
constant ap_ST_st14_fsm_13 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000";
constant ap_ST_st15_fsm_14 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000";
constant ap_ST_st16_fsm_15 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000";
constant ap_ST_st17_fsm_16 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000";
constant ap_ST_st18_fsm_17 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000";
constant ap_ST_st19_fsm_18 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000";
constant ap_ST_st20_fsm_19 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000";
constant ap_ST_st21_fsm_20 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000";
constant ap_ST_st22_fsm_21 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000";
constant ap_ST_st23_fsm_22 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000";
constant ap_ST_st24_fsm_23 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000";
constant ap_ST_st25_fsm_24 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000";
constant ap_ST_st26_fsm_25 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000";
constant ap_ST_st27_fsm_26 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000";
constant ap_ST_st28_fsm_27 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000";
constant ap_ST_st29_fsm_28 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000";
constant ap_ST_st30_fsm_29 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000";
constant ap_ST_st31_fsm_30 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000";
constant ap_ST_st32_fsm_31 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000";
constant ap_ST_st33_fsm_32 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000";
constant ap_ST_st34_fsm_33 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000";
constant ap_ST_st35_fsm_34 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000";
constant ap_ST_st36_fsm_35 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000";
constant ap_ST_st37_fsm_36 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000";
constant ap_ST_st38_fsm_37 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000";
constant ap_ST_st39_fsm_38 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000";
constant ap_ST_st40_fsm_39 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000";
constant ap_ST_st41_fsm_40 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000";
constant ap_ST_st42_fsm_41 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000";
constant ap_ST_st43_fsm_42 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000";
constant ap_ST_st44_fsm_43 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000";
constant ap_ST_st45_fsm_44 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000";
constant ap_ST_st46_fsm_45 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000";
constant ap_ST_st47_fsm_46 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000";
constant ap_ST_st48_fsm_47 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000";
constant ap_ST_st49_fsm_48 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000";
constant ap_ST_st50_fsm_49 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000";
constant ap_ST_st51_fsm_50 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000";
constant ap_ST_st52_fsm_51 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000";
constant ap_ST_st53_fsm_52 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000";
constant ap_ST_st54_fsm_53 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000";
constant ap_ST_st55_fsm_54 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000";
constant ap_ST_st56_fsm_55 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000";
constant ap_ST_st57_fsm_56 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000";
constant ap_ST_st58_fsm_57 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st59_fsm_58 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st60_fsm_59 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st61_fsm_60 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st62_fsm_61 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st63_fsm_62 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st64_fsm_63 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st65_fsm_64 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st66_fsm_65 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st67_fsm_66 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st68_fsm_67 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st69_fsm_68 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st70_fsm_69 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st71_fsm_70 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st72_fsm_71 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st73_fsm_72 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st74_fsm_73 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st75_fsm_74 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st76_fsm_75 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st77_fsm_76 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st78_fsm_77 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st79_fsm_78 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st80_fsm_79 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st81_fsm_80 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st82_fsm_81 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st83_fsm_82 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st84_fsm_83 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st85_fsm_84 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st86_fsm_85 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st87_fsm_86 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st88_fsm_87 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st89_fsm_88 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st90_fsm_89 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st91_fsm_90 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st92_fsm_91 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st93_fsm_92 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st94_fsm_93 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st95_fsm_94 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st96_fsm_95 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st97_fsm_96 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st98_fsm_97 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st99_fsm_98 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st100_fsm_99 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st101_fsm_100 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st102_fsm_101 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st103_fsm_102 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st104_fsm_103 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st105_fsm_104 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st106_fsm_105 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st107_fsm_106 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st108_fsm_107 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st109_fsm_108 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st110_fsm_109 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st111_fsm_110 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st112_fsm_111 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st113_fsm_112 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st114_fsm_113 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st115_fsm_114 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st116_fsm_115 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st117_fsm_116 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st118_fsm_117 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st119_fsm_118 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st120_fsm_119 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st121_fsm_120 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st122_fsm_121 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st123_fsm_122 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st124_fsm_123 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st125_fsm_124 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st126_fsm_125 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st127_fsm_126 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st128_fsm_127 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st129_fsm_128 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st130_fsm_129 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st131_fsm_130 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st132_fsm_131 : STD_LOGIC_VECTOR (142 downto 0) := "00000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st133_fsm_132 : STD_LOGIC_VECTOR (142 downto 0) := "00000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st134_fsm_133 : STD_LOGIC_VECTOR (142 downto 0) := "00000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st135_fsm_134 : STD_LOGIC_VECTOR (142 downto 0) := "00000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st136_fsm_135 : STD_LOGIC_VECTOR (142 downto 0) := "00000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st137_fsm_136 : STD_LOGIC_VECTOR (142 downto 0) := "00000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st138_fsm_137 : STD_LOGIC_VECTOR (142 downto 0) := "00000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st139_fsm_138 : STD_LOGIC_VECTOR (142 downto 0) := "00001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st140_fsm_139 : STD_LOGIC_VECTOR (142 downto 0) := "00010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st141_fsm_140 : STD_LOGIC_VECTOR (142 downto 0) := "00100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st142_fsm_141 : STD_LOGIC_VECTOR (142 downto 0) := "01000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_ST_st143_fsm_142 : STD_LOGIC_VECTOR (142 downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv1_1 : STD_LOGIC_VECTOR (0 downto 0) := "1";
constant C_S_AXI_DATA_WIDTH : INTEGER range 63 downto 0 := 20;
constant ap_const_lv32_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000010";
constant ap_const_lv32_8 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001000";
constant ap_const_lv32_52 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010010";
constant ap_const_lv32_7B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111011";
constant ap_const_lv32_11 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010001";
constant ap_const_lv32_5B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011011";
constant ap_const_lv32_B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001011";
constant ap_const_lv32_55 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010101";
constant ap_const_lv32_10 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010000";
constant ap_const_lv32_5A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011010";
constant ap_const_lv32_16 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010110";
constant ap_const_lv32_60 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100000";
constant ap_const_lv32_17 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010111";
constant ap_const_lv32_61 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001100001";
constant ap_const_lv32_29 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101001";
constant ap_const_lv32_73 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001110011";
constant ap_const_lv32_4E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001110";
constant ap_const_lv32_74 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001110100";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000011";
constant ap_const_lv32_4 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000100";
constant ap_const_lv32_5 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000101";
constant ap_const_lv32_6 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000110";
constant ap_const_lv32_7 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000111";
constant ap_const_lv32_2E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000101110";
constant ap_const_lv32_4D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001101";
constant ap_const_lv32_50 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010000";
constant ap_const_lv32_51 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010001";
constant ap_const_lv32_79 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111001";
constant ap_const_lv32_7A : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001111010";
constant ap_const_lv32_8B : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001011";
constant ap_const_lv32_8D : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001101";
constant ap_const_lv31_1 : STD_LOGIC_VECTOR (30 downto 0) := "0000000000000000000000000000001";
constant ap_const_lv32_4F : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001001111";
constant ap_const_lv31_0 : STD_LOGIC_VECTOR (30 downto 0) := "0000000000000000000000000000000";
constant ap_const_lv32_8C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001100";
constant ap_const_lv32_8E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000010001110";
constant ap_const_lv2_0 : STD_LOGIC_VECTOR (1 downto 0) := "00";
constant ap_const_lv2_1 : STD_LOGIC_VECTOR (1 downto 0) := "01";
constant ap_const_lv2_2 : STD_LOGIC_VECTOR (1 downto 0) := "10";
constant ap_const_lv32_75 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001110101";
constant ap_const_lv32_C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000001100";
constant ap_const_lv32_12 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000010010";
constant ap_const_lv32_56 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001010110";
constant ap_const_lv32_5C : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000001011100";
constant ap_const_lv64_3FF0000000000000 : STD_LOGIC_VECTOR (63 downto 0) := "0011111111110000000000000000000000000000000000000000000000000000";
constant ap_const_lv32_FFFFFFFF : STD_LOGIC_VECTOR (31 downto 0) := "11111111111111111111111111111111";
constant ap_const_lv5_0 : STD_LOGIC_VECTOR (4 downto 0) := "00000";
constant ap_const_lv3_0 : STD_LOGIC_VECTOR (2 downto 0) := "000";
constant ap_const_lv32_1E : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000011110";
constant ap_const_lv8_FF : STD_LOGIC_VECTOR (7 downto 0) := "11111111";
constant ap_const_lv23_0 : STD_LOGIC_VECTOR (22 downto 0) := "00000000000000000000000";
constant ap_const_lv31_7FFFFFFF : STD_LOGIC_VECTOR (30 downto 0) := "1111111111111111111111111111111";
constant ap_const_lv32_FFFFFFFE : STD_LOGIC_VECTOR (31 downto 0) := "11111111111111111111111111111110";
constant ap_const_lv32_80000000 : STD_LOGIC_VECTOR (31 downto 0) := "10000000000000000000000000000000";
constant ap_const_lv14_29 : STD_LOGIC_VECTOR (13 downto 0) := "00000000101001";
constant ap_const_lv5_2 : STD_LOGIC_VECTOR (4 downto 0) := "00010";
constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
signal ap_rst_n_inv : STD_LOGIC;
signal ap_start : STD_LOGIC;
signal ap_done : STD_LOGIC;
signal ap_idle : STD_LOGIC;
signal ap_CS_fsm : STD_LOGIC_VECTOR (142 downto 0) := "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
attribute fsm_encoding : string;
attribute fsm_encoding of ap_CS_fsm : signal is "none";
signal ap_sig_cseq_ST_st1_fsm_0 : STD_LOGIC;
signal ap_sig_bdd_161 : BOOLEAN;
signal ap_ready : STD_LOGIC;
signal P_mode : STD_LOGIC_VECTOR (31 downto 0);
signal P_index1 : STD_LOGIC_VECTOR (31 downto 0);
signal P_index2 : STD_LOGIC_VECTOR (31 downto 0);
signal P_intIn_index3 : STD_LOGIC_VECTOR (31 downto 0);
signal P_floatIn : STD_LOGIC_VECTOR (31 downto 0);
signal P_floatOut : STD_LOGIC_VECTOR (31 downto 0);
signal P_floatOut_ap_vld : STD_LOGIC;
signal P_intOut : STD_LOGIC_VECTOR (31 downto 0);
signal P_intOut_ap_vld : STD_LOGIC;
signal ST_numLayer : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal ST_WandB_address0 : STD_LOGIC_VECTOR (12 downto 0);
signal ST_WandB_ce0 : STD_LOGIC;
signal ST_WandB_we0 : STD_LOGIC;
signal ST_WandB_d0 : STD_LOGIC_VECTOR (31 downto 0);
signal ST_WandB_q0 : STD_LOGIC_VECTOR (31 downto 0);
signal ST_uOut_address0 : STD_LOGIC_VECTOR (7 downto 0);
signal ST_uOut_ce0 : STD_LOGIC;
signal ST_uOut_we0 : STD_LOGIC;
signal ST_uOut_d0 : STD_LOGIC_VECTOR (31 downto 0);
signal ST_uOut_q0 : STD_LOGIC_VECTOR (31 downto 0);
signal ST_uOut_address1 : STD_LOGIC_VECTOR (7 downto 0);
signal ST_uOut_ce1 : STD_LOGIC;
signal ST_uOut_we1 : STD_LOGIC;
signal ST_uOut_d1 : STD_LOGIC_VECTOR (31 downto 0);
signal ST_uOut_q1 : STD_LOGIC_VECTOR (31 downto 0);
signal ST_layerSize_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal ST_layerSize_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal ST_layerSize_2 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal ST_layerSize_3 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal ANN_AXILiteS_s_axi_U_ap_dummy_ce : STD_LOGIC;
signal reg_479 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st3_fsm_2 : STD_LOGIC;
signal ap_sig_bdd_249 : BOOLEAN;
signal ap_sig_cseq_ST_st9_fsm_8 : STD_LOGIC;
signal ap_sig_bdd_256 : BOOLEAN;
signal ap_sig_cseq_ST_st83_fsm_82 : STD_LOGIC;
signal ap_sig_bdd_263 : BOOLEAN;
signal ap_sig_cseq_ST_st124_fsm_123 : STD_LOGIC;
signal ap_sig_bdd_271 : BOOLEAN;
signal reg_487 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st18_fsm_17 : STD_LOGIC;
signal ap_sig_bdd_280 : BOOLEAN;
signal ap_sig_cseq_ST_st92_fsm_91 : STD_LOGIC;
signal ap_sig_bdd_289 : BOOLEAN;
signal grp_fu_421_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_493 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st12_fsm_11 : STD_LOGIC;
signal ap_sig_bdd_299 : BOOLEAN;
signal ap_sig_cseq_ST_st86_fsm_85 : STD_LOGIC;
signal ap_sig_bdd_306 : BOOLEAN;
signal grp_fu_414_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st17_fsm_16 : STD_LOGIC;
signal ap_sig_bdd_316 : BOOLEAN;
signal ap_sig_cseq_ST_st91_fsm_90 : STD_LOGIC;
signal ap_sig_bdd_323 : BOOLEAN;
signal reg_504 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st23_fsm_22 : STD_LOGIC;
signal ap_sig_bdd_332 : BOOLEAN;
signal ap_sig_cseq_ST_st97_fsm_96 : STD_LOGIC;
signal ap_sig_bdd_339 : BOOLEAN;
signal grp_fu_436_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal reg_509 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st24_fsm_23 : STD_LOGIC;
signal ap_sig_bdd_349 : BOOLEAN;
signal ap_sig_cseq_ST_st98_fsm_97 : STD_LOGIC;
signal ap_sig_bdd_356 : BOOLEAN;
signal grp_fu_453_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal reg_514 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st42_fsm_41 : STD_LOGIC;
signal ap_sig_bdd_366 : BOOLEAN;
signal ap_sig_cseq_ST_st116_fsm_115 : STD_LOGIC;
signal ap_sig_bdd_373 : BOOLEAN;
signal grp_fu_433_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal reg_520 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st79_fsm_78 : STD_LOGIC;
signal ap_sig_bdd_383 : BOOLEAN;
signal ap_sig_cseq_ST_st117_fsm_116 : STD_LOGIC;
signal ap_sig_bdd_390 : BOOLEAN;
signal P_floatIn_read_reg_1333 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_1_fu_526_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_1_reg_1338 : STD_LOGIC_VECTOR (0 downto 0);
signal ST_numLayer_load_reg_1342 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_2_fu_537_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_2_reg_1349 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_4_fu_543_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_4_reg_1353 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_8_fu_549_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_8_reg_1357 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_s_fu_555_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_s_reg_1361 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_10_fu_561_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_10_reg_1365 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_14_fu_567_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_14_reg_1369 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_75_fu_597_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_75_reg_1373 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_31_fu_607_p6 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_31_reg_1379 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_6_fu_671_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_6_reg_1389 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_16_fu_709_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_16_reg_1394 : STD_LOGIC_VECTOR (13 downto 0);
signal max_2_cast_fu_749_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal max_2_cast_reg_1402 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st2_fsm_1 : STD_LOGIC;
signal ap_sig_bdd_459 : BOOLEAN;
signal tmp_24_fu_753_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal i_4_fu_786_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal i_4_reg_1420 : STD_LOGIC_VECTOR (30 downto 0);
signal ST_uOut_load_2_reg_1425 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_62_fu_869_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_62_reg_1431 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st4_fsm_3 : STD_LOGIC;
signal ap_sig_bdd_485 : BOOLEAN;
signal max_1_fu_875_p3 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st5_fsm_4 : STD_LOGIC;
signal ap_sig_bdd_494 : BOOLEAN;
signal tmp_28_fu_914_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_28_reg_1444 : STD_LOGIC_VECTOR (13 downto 0);
signal ap_sig_cseq_ST_st6_fsm_5 : STD_LOGIC;
signal ap_sig_bdd_503 : BOOLEAN;
signal tmp_3_fu_885_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_29_fu_920_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_29_reg_1449 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_37_fu_954_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_37_reg_1454 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_44_fu_960_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_44_reg_1459 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_55_fu_988_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_55_reg_1464 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_57_fu_994_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_57_reg_1469 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_63_fu_998_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_63_reg_1474 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_68_fu_1031_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_68_reg_1479 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_69_fu_1037_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_69_reg_1484 : STD_LOGIC_VECTOR (1 downto 0);
signal j_2_fu_1060_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal j_2_reg_1492 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st7_fsm_6 : STD_LOGIC;
signal ap_sig_bdd_533 : BOOLEAN;
signal tmp_52_fu_1066_p6 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_52_reg_1497 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_20_fu_1054_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ST_uOut_addr_5_reg_1503 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_79_fu_1327_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_79_reg_1508 : STD_LOGIC_VECTOR (13 downto 0);
signal i_3_fu_1093_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal k_1_fu_1108_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal k_1_reg_1522 : STD_LOGIC_VECTOR (30 downto 0);
signal ap_sig_cseq_ST_st8_fsm_7 : STD_LOGIC;
signal ap_sig_bdd_555 : BOOLEAN;
signal tmp_32_fu_1103_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_443_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_41_reg_1542 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st47_fsm_46 : STD_LOGIC;
signal ap_sig_bdd_575 : BOOLEAN;
signal grp_fu_448_p2 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_42_reg_1547 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st78_fsm_77 : STD_LOGIC;
signal ap_sig_bdd_584 : BOOLEAN;
signal tmp_27_fu_1170_p6 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_27_reg_1552 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st81_fsm_80 : STD_LOGIC;
signal ap_sig_bdd_593 : BOOLEAN;
signal i_5_fu_1189_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal i_5_reg_1560 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_53_fu_1195_p6 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_53_reg_1565 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_22_fu_1183_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ST_uOut_addr_7_reg_1571 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_82_fu_1321_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_82_reg_1576 : STD_LOGIC_VECTOR (13 downto 0);
signal j_3_fu_1231_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal j_3_reg_1585 : STD_LOGIC_VECTOR (30 downto 0);
signal ap_sig_cseq_ST_st82_fsm_81 : STD_LOGIC;
signal ap_sig_bdd_614 : BOOLEAN;
signal tmp_33_fu_1226_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_cseq_ST_st122_fsm_121 : STD_LOGIC;
signal ap_sig_bdd_633 : BOOLEAN;
signal i_6_fu_1287_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal i_6_reg_1613 : STD_LOGIC_VECTOR (30 downto 0);
signal ap_sig_cseq_ST_st123_fsm_122 : STD_LOGIC;
signal ap_sig_bdd_642 : BOOLEAN;
signal ST_uOut_addr_8_reg_1618 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_34_fu_1282_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_428_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_51_reg_1624 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st140_fsm_139 : STD_LOGIC;
signal ap_sig_bdd_669 : BOOLEAN;
signal tmp_21_fu_1312_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_21_reg_1629 : STD_LOGIC_VECTOR (13 downto 0);
signal ap_sig_cseq_ST_st142_fsm_141 : STD_LOGIC;
signal ap_sig_bdd_678 : BOOLEAN;
signal max_2_reg_287 : STD_LOGIC_VECTOR (30 downto 0);
signal max_reg_298 : STD_LOGIC_VECTOR (31 downto 0);
signal i_reg_311 : STD_LOGIC_VECTOR (30 downto 0);
signal j_reg_323 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st80_fsm_79 : STD_LOGIC;
signal ap_sig_bdd_700 : BOOLEAN;
signal sum_reg_334 : STD_LOGIC_VECTOR (31 downto 0);
signal k_reg_346 : STD_LOGIC_VECTOR (30 downto 0);
signal sumsoft_reg_357 : STD_LOGIC_VECTOR (31 downto 0);
signal i_1_reg_369 : STD_LOGIC_VECTOR (31 downto 0);
signal sum_1_reg_380 : STD_LOGIC_VECTOR (31 downto 0);
signal j_1_reg_392 : STD_LOGIC_VECTOR (30 downto 0);
signal i_2_reg_403 : STD_LOGIC_VECTOR (30 downto 0);
signal ap_sig_cseq_ST_st141_fsm_140 : STD_LOGIC;
signal ap_sig_bdd_722 : BOOLEAN;
signal tmp_65_cast_fu_661_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_9_fu_666_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_85_cast_fu_767_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_86_cast_fu_781_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_81_cast_fu_1088_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_87_cast_fu_1127_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_88_cast_fu_1137_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_89_cast_fu_1150_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_83_cast_fu_1217_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_90_cast_fu_1250_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_91_cast_fu_1260_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_92_cast_fu_1273_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_93_cast_fu_1302_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_21_cast_fu_1317_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sig_cseq_ST_st143_fsm_142 : STD_LOGIC;
signal ap_sig_bdd_750 : BOOLEAN;
signal tmp_5_fu_715_p1 : STD_LOGIC_VECTOR (1 downto 0);
signal ap_sig_cseq_ST_st118_fsm_117 : STD_LOGIC;
signal ap_sig_bdd_816 : BOOLEAN;
signal grp_fu_414_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_414_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ap_sig_cseq_ST_st13_fsm_12 : STD_LOGIC;
signal ap_sig_bdd_835 : BOOLEAN;
signal ap_sig_cseq_ST_st19_fsm_18 : STD_LOGIC;
signal ap_sig_bdd_842 : BOOLEAN;
signal ap_sig_cseq_ST_st87_fsm_86 : STD_LOGIC;
signal ap_sig_bdd_850 : BOOLEAN;
signal ap_sig_cseq_ST_st93_fsm_92 : STD_LOGIC;
signal ap_sig_bdd_857 : BOOLEAN;
signal grp_fu_421_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_433_p0 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_436_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_38_fu_1165_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_458_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_458_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_73_fu_573_p1 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_74_fu_585_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal p_shl12_cast_fu_577_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal p_shl13_cast_fu_589_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_31_fu_607_p5 : STD_LOGIC_VECTOR (1 downto 0);
signal tmp_71_fu_625_p1 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_72_fu_637_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal p_shl10_cast_fu_629_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal p_shl11_cast_fu_641_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_70_fu_621_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_64_fu_649_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_65_fu_655_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_11_fu_679_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_12_fu_691_p1 : STD_LOGIC_VECTOR (10 downto 0);
signal p_shl_cast_fu_683_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal p_shl1_cast_fu_695_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_7_fu_675_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_13_fu_703_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_93_fu_758_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_85_fu_762_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_94_fu_772_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_86_fu_776_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal ST_uOut_load_1_to_int_fu_792_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal ST_uOut_load_2_to_int_fu_810_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_54_fu_796_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_95_fu_806_p1 : STD_LOGIC_VECTOR (22 downto 0);
signal notrhs_fu_833_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal notlhs_fu_827_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_56_fu_813_p4 : STD_LOGIC_VECTOR (7 downto 0);
signal tmp_96_fu_823_p1 : STD_LOGIC_VECTOR (22 downto 0);
signal notrhs2_fu_851_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal notlhs1_fu_845_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_58_fu_839_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_59_fu_857_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_60_fu_863_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_61_fu_439_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal i_cast_fu_881_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_25_fu_890_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_26_fu_902_p1 : STD_LOGIC_VECTOR (10 downto 0);
signal p_shl8_cast_fu_894_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal p_shl9_cast_fu_906_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_15_fu_924_p2 : STD_LOGIC_VECTOR (30 downto 0);
signal tmp_30_fu_930_p1 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_35_fu_942_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal p_shl6_cast_fu_934_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal p_shl7_cast_fu_946_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_46_fu_964_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_50_fu_976_p1 : STD_LOGIC_VECTOR (10 downto 0);
signal p_shl4_cast_fu_968_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal p_shl5_cast_fu_980_p3 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_23_fu_1002_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_66_fu_1007_p1 : STD_LOGIC_VECTOR (3 downto 0);
signal tmp_67_fu_1019_p1 : STD_LOGIC_VECTOR (5 downto 0);
signal p_shl2_cast_fu_1011_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal p_shl3_cast_fu_1023_p3 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_fu_1041_p6 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_77_fu_1079_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_78_fu_1083_p2 : STD_LOGIC_VECTOR (13 downto 0);
attribute use_dsp48 : string;
attribute use_dsp48 of tmp_78_fu_1083_p2 : signal is "no";
signal k_cast_fu_1099_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_98_fu_1118_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_87_fu_1122_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_97_fu_1114_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_88_fu_1132_p2 : STD_LOGIC_VECTOR (13 downto 0);
attribute use_dsp48 of tmp_88_fu_1132_p2 : signal is "no";
signal tmp_99_fu_1142_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_89_fu_1145_p2 : STD_LOGIC_VECTOR (13 downto 0);
attribute use_dsp48 of tmp_89_fu_1145_p2 : signal is "no";
signal tmp_38_to_int_fu_1155_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_38_neg_fu_1159_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_80_fu_1208_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_81_fu_1212_p2 : STD_LOGIC_VECTOR (13 downto 0);
attribute use_dsp48 of tmp_81_fu_1212_p2 : signal is "no";
signal j_1_cast_fu_1222_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_101_fu_1241_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_90_fu_1245_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_100_fu_1237_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_91_fu_1255_p2 : STD_LOGIC_VECTOR (13 downto 0);
attribute use_dsp48 of tmp_91_fu_1255_p2 : signal is "no";
signal tmp_102_fu_1265_p1 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_92_fu_1268_p2 : STD_LOGIC_VECTOR (13 downto 0);
attribute use_dsp48 of tmp_92_fu_1268_p2 : signal is "no";
signal i_2_cast_fu_1278_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal tmp_83_fu_1293_p1 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_84_fu_1297_p2 : STD_LOGIC_VECTOR (8 downto 0);
signal tmp_19_fu_1307_p2 : STD_LOGIC_VECTOR (13 downto 0);
signal tmp_82_fu_1321_p0 : STD_LOGIC_VECTOR (6 downto 0);
signal tmp_79_fu_1327_p0 : STD_LOGIC_VECTOR (6 downto 0);
signal grp_fu_414_ce : STD_LOGIC;
signal grp_fu_421_ce : STD_LOGIC;
signal grp_fu_428_ce : STD_LOGIC;
signal tmp_61_fu_439_opcode : STD_LOGIC_VECTOR (4 downto 0);
signal grp_fu_443_ce : STD_LOGIC;
signal grp_fu_448_ce : STD_LOGIC;
signal grp_fu_453_ce : STD_LOGIC;
signal ap_NS_fsm : STD_LOGIC_VECTOR (142 downto 0);
component ANN_fadd_32ns_32ns_32_5_full_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component ANN_fmul_32ns_32ns_32_4_max_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component ANN_fdiv_32ns_32ns_32_16 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component ANN_fptrunc_64ns_32_1 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component ANN_fpext_32ns_64_1 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component ANN_fcmp_32ns_32ns_1_1 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
opcode : IN STD_LOGIC_VECTOR (4 downto 0);
dout : OUT STD_LOGIC_VECTOR (0 downto 0) );
end component;
component ANN_dadd_64ns_64ns_64_5_full_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component ANN_ddiv_64ns_64ns_64_31 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component ANN_dexp_64ns_64ns_64_18_full_dsp IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (63 downto 0);
din1 : IN STD_LOGIC_VECTOR (63 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component ANN_mux_4to1_sel2_32_1 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din1_WIDTH : INTEGER;
din2_WIDTH : INTEGER;
din3_WIDTH : INTEGER;
din4_WIDTH : INTEGER;
din5_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
din2 : IN STD_LOGIC_VECTOR (31 downto 0);
din3 : IN STD_LOGIC_VECTOR (31 downto 0);
din4 : IN STD_LOGIC_VECTOR (31 downto 0);
din5 : IN STD_LOGIC_VECTOR (1 downto 0);
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component ANN_mul_mul_7ns_14s_14_1 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
din0 : IN STD_LOGIC_VECTOR (6 downto 0);
din1 : IN STD_LOGIC_VECTOR (13 downto 0);
dout : OUT STD_LOGIC_VECTOR (13 downto 0) );
end component;
component ANN_ST_WandB IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (12 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (31 downto 0);
q0 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component ANN_ST_uOut IS
generic (
DataWidth : INTEGER;
AddressRange : INTEGER;
AddressWidth : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR (7 downto 0);
ce0 : IN STD_LOGIC;
we0 : IN STD_LOGIC;
d0 : IN STD_LOGIC_VECTOR (31 downto 0);
q0 : OUT STD_LOGIC_VECTOR (31 downto 0);
address1 : IN STD_LOGIC_VECTOR (7 downto 0);
ce1 : IN STD_LOGIC;
we1 : IN STD_LOGIC;
d1 : IN STD_LOGIC_VECTOR (31 downto 0);
q1 : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component ANN_AXILiteS_s_axi IS
generic (
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER );
port (
AWVALID : IN STD_LOGIC;
AWREADY : OUT STD_LOGIC;
AWADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
WVALID : IN STD_LOGIC;
WREADY : OUT STD_LOGIC;
WDATA : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB : IN STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH/8-1 downto 0);
ARVALID : IN STD_LOGIC;
ARREADY : OUT STD_LOGIC;
ARADDR : IN STD_LOGIC_VECTOR (C_S_AXI_ADDR_WIDTH-1 downto 0);
RVALID : OUT STD_LOGIC;
RREADY : IN STD_LOGIC;
RDATA : OUT STD_LOGIC_VECTOR (C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
BVALID : OUT STD_LOGIC;
BREADY : IN STD_LOGIC;
BRESP : OUT STD_LOGIC_VECTOR (1 downto 0);
ACLK : IN STD_LOGIC;
ARESET : IN STD_LOGIC;
ACLK_EN : IN STD_LOGIC;
ap_start : OUT STD_LOGIC;
interrupt : OUT STD_LOGIC;
ap_ready : IN STD_LOGIC;
ap_done : IN STD_LOGIC;
ap_idle : IN STD_LOGIC;
P_mode : OUT STD_LOGIC_VECTOR (31 downto 0);
P_index1 : OUT STD_LOGIC_VECTOR (31 downto 0);
P_index2 : OUT STD_LOGIC_VECTOR (31 downto 0);
P_intIn_index3 : OUT STD_LOGIC_VECTOR (31 downto 0);
P_floatIn : OUT STD_LOGIC_VECTOR (31 downto 0);
P_floatOut : IN STD_LOGIC_VECTOR (31 downto 0);
P_floatOut_ap_vld : IN STD_LOGIC;
P_intOut : IN STD_LOGIC_VECTOR (31 downto 0);
P_intOut_ap_vld : IN STD_LOGIC );
end component;
begin
ST_WandB_U : component ANN_ST_WandB
generic map (
DataWidth => 32,
AddressRange => 6560,
AddressWidth => 13)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
address0 => ST_WandB_address0,
ce0 => ST_WandB_ce0,
we0 => ST_WandB_we0,
d0 => ST_WandB_d0,
q0 => ST_WandB_q0);
ST_uOut_U : component ANN_ST_uOut
generic map (
DataWidth => 32,
AddressRange => 160,
AddressWidth => 8)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
address0 => ST_uOut_address0,
ce0 => ST_uOut_ce0,
we0 => ST_uOut_we0,
d0 => ST_uOut_d0,
q0 => ST_uOut_q0,
address1 => ST_uOut_address1,
ce1 => ST_uOut_ce1,
we1 => ST_uOut_we1,
d1 => ST_uOut_d1,
q1 => ST_uOut_q1);
ANN_AXILiteS_s_axi_U : component ANN_AXILiteS_s_axi
generic map (
C_S_AXI_ADDR_WIDTH => C_S_AXI_AXILITES_ADDR_WIDTH,
C_S_AXI_DATA_WIDTH => C_S_AXI_AXILITES_DATA_WIDTH)
port map (
AWVALID => s_axi_AXILiteS_AWVALID,
AWREADY => s_axi_AXILiteS_AWREADY,
AWADDR => s_axi_AXILiteS_AWADDR,
WVALID => s_axi_AXILiteS_WVALID,
WREADY => s_axi_AXILiteS_WREADY,
WDATA => s_axi_AXILiteS_WDATA,
WSTRB => s_axi_AXILiteS_WSTRB,
ARVALID => s_axi_AXILiteS_ARVALID,
ARREADY => s_axi_AXILiteS_ARREADY,
ARADDR => s_axi_AXILiteS_ARADDR,
RVALID => s_axi_AXILiteS_RVALID,
RREADY => s_axi_AXILiteS_RREADY,
RDATA => s_axi_AXILiteS_RDATA,
RRESP => s_axi_AXILiteS_RRESP,
BVALID => s_axi_AXILiteS_BVALID,
BREADY => s_axi_AXILiteS_BREADY,
BRESP => s_axi_AXILiteS_BRESP,
ACLK => ap_clk,
ARESET => ap_rst_n_inv,
ACLK_EN => ANN_AXILiteS_s_axi_U_ap_dummy_ce,
ap_start => ap_start,
interrupt => interrupt,
ap_ready => ap_ready,
ap_done => ap_done,
ap_idle => ap_idle,
P_mode => P_mode,
P_index1 => P_index1,
P_index2 => P_index2,
P_intIn_index3 => P_intIn_index3,
P_floatIn => P_floatIn,
P_floatOut => P_floatOut,
P_floatOut_ap_vld => P_floatOut_ap_vld,
P_intOut => P_intOut,
P_intOut_ap_vld => P_intOut_ap_vld);
ANN_fadd_32ns_32ns_32_5_full_dsp_U0 : component ANN_fadd_32ns_32ns_32_5_full_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_414_p0,
din1 => grp_fu_414_p1,
ce => grp_fu_414_ce,
dout => grp_fu_414_p2);
ANN_fmul_32ns_32ns_32_4_max_dsp_U1 : component ANN_fmul_32ns_32ns_32_4_max_dsp
generic map (
ID => 1,
NUM_STAGE => 4,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => grp_fu_421_p0,
din1 => ST_WandB_q0,
ce => grp_fu_421_ce,
dout => grp_fu_421_p2);
ANN_fdiv_32ns_32ns_32_16_U2 : component ANN_fdiv_32ns_32ns_32_16
generic map (
ID => 1,
NUM_STAGE => 16,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => reg_479,
din1 => sumsoft_reg_357,
ce => grp_fu_428_ce,
dout => grp_fu_428_p2);
ANN_fptrunc_64ns_32_1_U3 : component ANN_fptrunc_64ns_32_1
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 64,
dout_WIDTH => 32)
port map (
din0 => grp_fu_433_p0,
dout => grp_fu_433_p1);
ANN_fpext_32ns_64_1_U4 : component ANN_fpext_32ns_64_1
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 32,
dout_WIDTH => 64)
port map (
din0 => grp_fu_436_p0,
dout => grp_fu_436_p1);
ANN_fcmp_32ns_32ns_1_1_U5 : component ANN_fcmp_32ns_32ns_1_1
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 1)
port map (
din0 => reg_479,
din1 => ST_uOut_load_2_reg_1425,
opcode => tmp_61_fu_439_opcode,
dout => tmp_61_fu_439_p2);
ANN_dadd_64ns_64ns_64_5_full_dsp_U6 : component ANN_dadd_64ns_64ns_64_5_full_dsp
generic map (
ID => 1,
NUM_STAGE => 5,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => reg_514,
din1 => ap_const_lv64_3FF0000000000000,
ce => grp_fu_443_ce,
dout => grp_fu_443_p2);
ANN_ddiv_64ns_64ns_64_31_U7 : component ANN_ddiv_64ns_64ns_64_31
generic map (
ID => 1,
NUM_STAGE => 31,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => ap_const_lv64_3FF0000000000000,
din1 => tmp_41_reg_1542,
ce => grp_fu_448_ce,
dout => grp_fu_448_p2);
ANN_dexp_64ns_64ns_64_18_full_dsp_U8 : component ANN_dexp_64ns_64ns_64_18_full_dsp
generic map (
ID => 1,
NUM_STAGE => 18,
din0_WIDTH => 64,
din1_WIDTH => 64,
dout_WIDTH => 64)
port map (
clk => ap_clk,
reset => ap_rst_n_inv,
din0 => ap_const_lv64_0,
din1 => reg_509,
ce => grp_fu_453_ce,
dout => grp_fu_453_p2);
ANN_mux_4to1_sel2_32_1_U9 : component ANN_mux_4to1_sel2_32_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 32,
din2_WIDTH => 32,
din3_WIDTH => 32,
din4_WIDTH => 32,
din5_WIDTH => 2,
dout_WIDTH => 32)
port map (
din1 => ST_layerSize_0,
din2 => ST_layerSize_1,
din3 => ST_layerSize_2,
din4 => ST_layerSize_3,
din5 => tmp_31_fu_607_p5,
dout => tmp_31_fu_607_p6);
ANN_mux_4to1_sel2_32_1_U10 : component ANN_mux_4to1_sel2_32_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 32,
din2_WIDTH => 32,
din3_WIDTH => 32,
din4_WIDTH => 32,
din5_WIDTH => 2,
dout_WIDTH => 32)
port map (
din1 => ST_layerSize_0,
din2 => ST_layerSize_1,
din3 => ST_layerSize_2,
din4 => ST_layerSize_3,
din5 => tmp_29_reg_1449,
dout => tmp_fu_1041_p6);
ANN_mux_4to1_sel2_32_1_U11 : component ANN_mux_4to1_sel2_32_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 32,
din2_WIDTH => 32,
din3_WIDTH => 32,
din4_WIDTH => 32,
din5_WIDTH => 2,
dout_WIDTH => 32)
port map (
din1 => ST_layerSize_0,
din2 => ST_layerSize_1,
din3 => ST_layerSize_2,
din4 => ST_layerSize_3,
din5 => tmp_44_reg_1459,
dout => tmp_52_fu_1066_p6);
ANN_mux_4to1_sel2_32_1_U12 : component ANN_mux_4to1_sel2_32_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 32,
din2_WIDTH => 32,
din3_WIDTH => 32,
din4_WIDTH => 32,
din5_WIDTH => 2,
dout_WIDTH => 32)
port map (
din1 => ST_layerSize_0,
din2 => ST_layerSize_1,
din3 => ST_layerSize_2,
din4 => ST_layerSize_3,
din5 => tmp_63_reg_1474,
dout => tmp_27_fu_1170_p6);
ANN_mux_4to1_sel2_32_1_U13 : component ANN_mux_4to1_sel2_32_1
generic map (
ID => 1,
NUM_STAGE => 1,
din1_WIDTH => 32,
din2_WIDTH => 32,
din3_WIDTH => 32,
din4_WIDTH => 32,
din5_WIDTH => 2,
dout_WIDTH => 32)
port map (
din1 => ST_layerSize_0,
din2 => ST_layerSize_1,
din3 => ST_layerSize_2,
din4 => ST_layerSize_3,
din5 => tmp_69_reg_1484,
dout => tmp_53_fu_1195_p6);
ANN_mul_mul_7ns_14s_14_1_U14 : component ANN_mul_mul_7ns_14s_14_1
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 7,
din1_WIDTH => 14,
dout_WIDTH => 14)
port map (
din0 => tmp_82_fu_1321_p0,
din1 => tmp_81_fu_1212_p2,
dout => tmp_82_fu_1321_p2);
ANN_mul_mul_7ns_14s_14_1_U15 : component ANN_mul_mul_7ns_14s_14_1
generic map (
ID => 1,
NUM_STAGE => 1,
din0_WIDTH => 7,
din1_WIDTH => 14,
dout_WIDTH => 14)
port map (
din0 => tmp_79_fu_1327_p0,
din1 => tmp_78_fu_1083_p2,
dout => tmp_79_fu_1327_p2);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst_n_inv = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- i_1_reg_369 assign process. --
i_1_reg_369_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) and (ap_const_lv1_0 = tmp_3_fu_885_p2))) then
i_1_reg_369 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st122_fsm_121)) then
i_1_reg_369 <= i_5_reg_1560;
end if;
end if;
end process;
-- i_2_reg_403 assign process. --
i_2_reg_403_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st81_fsm_80) and (ap_const_lv1_0 = tmp_22_fu_1183_p2))) then
i_2_reg_403 <= ap_const_lv31_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st141_fsm_140)) then
i_2_reg_403 <= i_6_reg_1613;
end if;
end if;
end process;
-- i_reg_311 assign process. --
i_reg_311_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_526_p2 = ap_const_lv1_0) and (tmp_2_fu_537_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_4_fu_543_p2) and (ap_const_lv1_0 = tmp_8_fu_549_p2) and not((ap_const_lv1_0 = tmp_s_fu_555_p2)))) then
i_reg_311 <= ap_const_lv31_1;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6) and (ap_const_lv1_0 = tmp_20_fu_1054_p2))) then
i_reg_311 <= i_3_fu_1093_p2;
end if;
end if;
end process;
-- j_1_reg_392 assign process. --
j_1_reg_392_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st81_fsm_80) and not((ap_const_lv1_0 = tmp_22_fu_1183_p2)))) then
j_1_reg_392 <= ap_const_lv31_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st91_fsm_90)) then
j_1_reg_392 <= j_3_reg_1585;
end if;
end if;
end process;
-- j_reg_323 assign process. --
j_reg_323_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) and not((ap_const_lv1_0 = tmp_3_fu_885_p2)))) then
j_reg_323 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st80_fsm_79)) then
j_reg_323 <= j_2_reg_1492;
end if;
end if;
end process;
-- k_reg_346 assign process. --
k_reg_346_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6) and not((ap_const_lv1_0 = tmp_20_fu_1054_p2)))) then
k_reg_346 <= ap_const_lv31_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_16)) then
k_reg_346 <= k_1_reg_1522;
end if;
end if;
end process;
-- max_2_reg_287 assign process. --
max_2_reg_287_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_526_p2 = ap_const_lv1_0) and (tmp_2_fu_537_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_4_fu_543_p2) and (ap_const_lv1_0 = tmp_8_fu_549_p2) and (ap_const_lv1_0 = tmp_s_fu_555_p2) and (ap_const_lv1_0 = tmp_10_fu_561_p2) and not((ap_const_lv1_0 = tmp_14_fu_567_p2)))) then
max_2_reg_287 <= ap_const_lv31_1;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4)) then
max_2_reg_287 <= i_4_reg_1420;
end if;
end if;
end process;
-- max_reg_298 assign process. --
max_reg_298_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_526_p2 = ap_const_lv1_0) and (tmp_2_fu_537_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_4_fu_543_p2) and (ap_const_lv1_0 = tmp_8_fu_549_p2) and (ap_const_lv1_0 = tmp_s_fu_555_p2) and (ap_const_lv1_0 = tmp_10_fu_561_p2) and not((ap_const_lv1_0 = tmp_14_fu_567_p2)))) then
max_reg_298 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st5_fsm_4)) then
max_reg_298 <= max_1_fu_875_p3;
end if;
end if;
end process;
-- reg_479 assign process. --
reg_479_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
reg_479 <= ST_uOut_q1;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2) or (ap_const_logic_1 = ap_sig_cseq_ST_st83_fsm_82) or (ap_const_logic_1 = ap_sig_cseq_ST_st124_fsm_123))) then
reg_479 <= ST_uOut_q0;
end if;
end if;
end process;
-- sum_1_reg_380 assign process. --
sum_1_reg_380_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st81_fsm_80) and not((ap_const_lv1_0 = tmp_22_fu_1183_p2)))) then
sum_1_reg_380 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st91_fsm_90)) then
sum_1_reg_380 <= grp_fu_414_p2;
end if;
end if;
end process;
-- sum_reg_334 assign process. --
sum_reg_334_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6) and not((ap_const_lv1_0 = tmp_20_fu_1054_p2)))) then
sum_reg_334 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st17_fsm_16)) then
sum_reg_334 <= grp_fu_414_p2;
end if;
end if;
end process;
-- sumsoft_reg_357 assign process. --
sumsoft_reg_357_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) and (ap_const_lv1_0 = tmp_3_fu_885_p2))) then
sumsoft_reg_357 <= ap_const_lv32_0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st122_fsm_121)) then
sumsoft_reg_357 <= grp_fu_414_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)))) then
P_floatIn_read_reg_1333 <= P_floatIn;
ST_numLayer_load_reg_1342 <= ST_numLayer;
tmp_1_reg_1338 <= tmp_1_fu_526_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_526_p2 = ap_const_lv1_0) and not((tmp_2_fu_537_p2 = ap_const_lv1_0)) and (tmp_5_fu_715_p1 = ap_const_lv2_0))) then
ST_layerSize_0 <= P_intIn_index3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_526_p2 = ap_const_lv1_0) and not((tmp_2_fu_537_p2 = ap_const_lv1_0)) and (tmp_5_fu_715_p1 = ap_const_lv2_1))) then
ST_layerSize_1 <= P_intIn_index3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_526_p2 = ap_const_lv1_0) and not((tmp_2_fu_537_p2 = ap_const_lv1_0)) and (tmp_5_fu_715_p1 = ap_const_lv2_2))) then
ST_layerSize_2 <= P_intIn_index3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_526_p2 = ap_const_lv1_0) and not((tmp_2_fu_537_p2 = ap_const_lv1_0)) and not((tmp_5_fu_715_p1 = ap_const_lv2_2)) and not((tmp_5_fu_715_p1 = ap_const_lv2_1)) and not((tmp_5_fu_715_p1 = ap_const_lv2_0)))) then
ST_layerSize_3 <= P_intIn_index3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and not((tmp_1_fu_526_p2 = ap_const_lv1_0)))) then
ST_numLayer <= P_intIn_index3;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6) and not((ap_const_lv1_0 = tmp_20_fu_1054_p2)))) then
ST_uOut_addr_5_reg_1503 <= tmp_81_cast_fu_1088_p1(8 - 1 downto 0);
tmp_52_reg_1497 <= tmp_52_fu_1066_p6;
tmp_79_reg_1508 <= tmp_79_fu_1327_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st81_fsm_80) and not((ap_const_lv1_0 = tmp_22_fu_1183_p2)))) then
ST_uOut_addr_7_reg_1571 <= tmp_83_cast_fu_1217_p1(8 - 1 downto 0);
tmp_53_reg_1565 <= tmp_53_fu_1195_p6;
tmp_82_reg_1576 <= tmp_82_fu_1321_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st123_fsm_122) and (tmp_1_reg_1338 = ap_const_lv1_0) and (tmp_2_reg_1349 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_4_reg_1353) and (ap_const_lv1_0 = tmp_8_reg_1357) and not((ap_const_lv1_0 = tmp_s_reg_1361)) and not((ap_const_lv1_0 = tmp_34_fu_1282_p2)))) then
ST_uOut_addr_8_reg_1618 <= tmp_93_cast_fu_1302_p1(8 - 1 downto 0);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st3_fsm_2)) then
ST_uOut_load_2_reg_1425 <= ST_uOut_q1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (ap_const_lv1_0 = tmp_10_reg_1365) and not((ap_const_lv1_0 = tmp_14_reg_1369)) and not((ap_const_lv1_0 = tmp_24_fu_753_p2)))) then
i_4_reg_1420 <= i_4_fu_786_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st81_fsm_80)) then
i_5_reg_1560 <= i_5_fu_1189_p2;
tmp_27_reg_1552 <= tmp_27_fu_1170_p6;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st123_fsm_122) and (tmp_1_reg_1338 = ap_const_lv1_0) and (tmp_2_reg_1349 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_4_reg_1353) and (ap_const_lv1_0 = tmp_8_reg_1357) and not((ap_const_lv1_0 = tmp_s_reg_1361)))) then
i_6_reg_1613 <= i_6_fu_1287_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st7_fsm_6)) then
j_2_reg_1492 <= j_2_fu_1060_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st82_fsm_81)) then
j_3_reg_1585 <= j_3_fu_1231_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7)) then
k_1_reg_1522 <= k_1_fu_1108_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (ap_const_lv1_0 = tmp_10_reg_1365) and not((ap_const_lv1_0 = tmp_14_reg_1369)))) then
max_2_cast_reg_1402(30 downto 0) <= max_2_cast_fu_749_p1(30 downto 0);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8) or (ap_const_logic_1 = ap_sig_cseq_ST_st83_fsm_82) or (ap_const_logic_1 = ap_sig_cseq_ST_st18_fsm_17) or (ap_const_logic_1 = ap_sig_cseq_ST_st92_fsm_91))) then
reg_487 <= ST_WandB_q0;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st12_fsm_11) or (ap_const_logic_1 = ap_sig_cseq_ST_st86_fsm_85))) then
reg_493 <= grp_fu_421_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st23_fsm_22) or (ap_const_logic_1 = ap_sig_cseq_ST_st97_fsm_96))) then
reg_504 <= grp_fu_414_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st24_fsm_23) or (ap_const_logic_1 = ap_sig_cseq_ST_st98_fsm_97))) then
reg_509 <= grp_fu_436_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st42_fsm_41) or (ap_const_logic_1 = ap_sig_cseq_ST_st116_fsm_115))) then
reg_514 <= grp_fu_453_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st79_fsm_78) or (ap_const_logic_1 = ap_sig_cseq_ST_st117_fsm_116))) then
reg_520 <= grp_fu_433_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_526_p2 = ap_const_lv1_0) and (tmp_2_fu_537_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_4_fu_543_p2) and (ap_const_lv1_0 = tmp_8_fu_549_p2) and (ap_const_lv1_0 = tmp_s_fu_555_p2))) then
tmp_10_reg_1365 <= tmp_10_fu_561_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_526_p2 = ap_const_lv1_0) and (tmp_2_fu_537_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_4_fu_543_p2) and (ap_const_lv1_0 = tmp_8_fu_549_p2) and (ap_const_lv1_0 = tmp_s_fu_555_p2) and (ap_const_lv1_0 = tmp_10_fu_561_p2))) then
tmp_14_reg_1369 <= tmp_14_fu_567_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_526_p2 = ap_const_lv1_0) and (tmp_2_fu_537_p2 = ap_const_lv1_0) and not((ap_const_lv1_0 = tmp_4_fu_543_p2)))) then
tmp_16_reg_1394 <= tmp_16_fu_709_p2;
tmp_6_reg_1389 <= tmp_6_fu_671_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st142_fsm_141)) then
tmp_21_reg_1629 <= tmp_21_fu_1312_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) and not((ap_const_lv1_0 = tmp_3_fu_885_p2)))) then
tmp_28_reg_1444(13 downto 3) <= tmp_28_fu_914_p2(13 downto 3);
tmp_29_reg_1449 <= tmp_29_fu_920_p1;
tmp_37_reg_1454(8 downto 3) <= tmp_37_fu_954_p2(8 downto 3);
tmp_44_reg_1459 <= tmp_44_fu_960_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_526_p2 = ap_const_lv1_0))) then
tmp_2_reg_1349 <= tmp_2_fu_537_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_526_p2 = ap_const_lv1_0) and (tmp_2_fu_537_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_4_fu_543_p2) and (ap_const_lv1_0 = tmp_8_fu_549_p2) and (ap_const_lv1_0 = tmp_s_fu_555_p2) and (ap_const_lv1_0 = tmp_10_fu_561_p2) and not((ap_const_lv1_0 = tmp_14_fu_567_p2)))) then
tmp_31_reg_1379 <= tmp_31_fu_607_p6;
tmp_75_reg_1373(8 downto 3) <= tmp_75_fu_597_p2(8 downto 3);
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st47_fsm_46)) then
tmp_41_reg_1542 <= grp_fu_443_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st78_fsm_77)) then
tmp_42_reg_1547 <= grp_fu_448_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_526_p2 = ap_const_lv1_0) and (tmp_2_fu_537_p2 = ap_const_lv1_0))) then
tmp_4_reg_1353 <= tmp_4_fu_543_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st140_fsm_139)) then
tmp_51_reg_1624 <= grp_fu_428_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5) and (ap_const_lv1_0 = tmp_3_fu_885_p2))) then
tmp_55_reg_1464(13 downto 3) <= tmp_55_fu_988_p2(13 downto 3);
tmp_57_reg_1469(8 downto 3) <= tmp_57_fu_994_p1(8 downto 3);
tmp_63_reg_1474 <= tmp_63_fu_998_p1;
tmp_68_reg_1479(8 downto 3) <= tmp_68_fu_1031_p2(8 downto 3);
tmp_69_reg_1484 <= tmp_69_fu_1037_p1;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_const_logic_1 = ap_sig_cseq_ST_st4_fsm_3)) then
tmp_62_reg_1431 <= tmp_62_fu_869_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_526_p2 = ap_const_lv1_0) and (tmp_2_fu_537_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_4_fu_543_p2))) then
tmp_8_reg_1357 <= tmp_8_fu_549_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_526_p2 = ap_const_lv1_0) and (tmp_2_fu_537_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_4_fu_543_p2) and (ap_const_lv1_0 = tmp_8_fu_549_p2))) then
tmp_s_reg_1361 <= tmp_s_fu_555_p2;
end if;
end if;
end process;
tmp_75_reg_1373(2 downto 0) <= "000";
max_2_cast_reg_1402(31) <= '0';
tmp_28_reg_1444(2 downto 0) <= "000";
tmp_37_reg_1454(2 downto 0) <= "000";
tmp_55_reg_1464(2 downto 0) <= "000";
tmp_57_reg_1469(2 downto 0) <= "000";
tmp_68_reg_1479(2 downto 0) <= "000";
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start, ap_CS_fsm, tmp_1_fu_526_p2, tmp_1_reg_1338, tmp_2_fu_537_p2, tmp_2_reg_1349, tmp_4_fu_543_p2, tmp_4_reg_1353, tmp_8_fu_549_p2, tmp_8_reg_1357, tmp_s_fu_555_p2, tmp_s_reg_1361, tmp_10_reg_1365, tmp_14_reg_1369, tmp_24_fu_753_p2, tmp_3_fu_885_p2, tmp_20_fu_1054_p2, tmp_32_fu_1103_p2, tmp_22_fu_1183_p2, tmp_33_fu_1226_p2, tmp_34_fu_1282_p2)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if ((not((ap_start = ap_const_logic_0)) and (not((tmp_1_fu_526_p2 = ap_const_lv1_0)) or not((tmp_2_fu_537_p2 = ap_const_lv1_0)) or ((ap_const_lv1_0 = tmp_4_fu_543_p2) and not((ap_const_lv1_0 = tmp_8_fu_549_p2)))))) then
ap_NS_fsm <= ap_ST_st123_fsm_122;
elsif ((not((ap_start = ap_const_logic_0)) and (tmp_1_fu_526_p2 = ap_const_lv1_0) and (tmp_2_fu_537_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_4_fu_543_p2) and (ap_const_lv1_0 = tmp_8_fu_549_p2) and (ap_const_lv1_0 = tmp_s_fu_555_p2))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
elsif ((not((ap_start = ap_const_logic_0)) and (tmp_1_fu_526_p2 = ap_const_lv1_0) and (tmp_2_fu_537_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_4_fu_543_p2) and (ap_const_lv1_0 = tmp_8_fu_549_p2) and not((ap_const_lv1_0 = tmp_s_fu_555_p2)))) then
ap_NS_fsm <= ap_ST_st6_fsm_5;
elsif ((not((ap_start = ap_const_logic_0)) and (tmp_1_fu_526_p2 = ap_const_lv1_0) and (tmp_2_fu_537_p2 = ap_const_lv1_0) and not((ap_const_lv1_0 = tmp_4_fu_543_p2)))) then
ap_NS_fsm <= ap_ST_st142_fsm_141;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
if (((ap_const_lv1_0 = tmp_14_reg_1369) or (ap_const_lv1_0 = tmp_24_fu_753_p2) or not((ap_const_lv1_0 = tmp_10_reg_1365)))) then
ap_NS_fsm <= ap_ST_st123_fsm_122;
else
ap_NS_fsm <= ap_ST_st3_fsm_2;
end if;
when ap_ST_st3_fsm_2 =>
ap_NS_fsm <= ap_ST_st4_fsm_3;
when ap_ST_st4_fsm_3 =>
ap_NS_fsm <= ap_ST_st5_fsm_4;
when ap_ST_st5_fsm_4 =>
ap_NS_fsm <= ap_ST_st2_fsm_1;
when ap_ST_st6_fsm_5 =>
if ((ap_const_lv1_0 = tmp_3_fu_885_p2)) then
ap_NS_fsm <= ap_ST_st81_fsm_80;
else
ap_NS_fsm <= ap_ST_st7_fsm_6;
end if;
when ap_ST_st7_fsm_6 =>
if ((ap_const_lv1_0 = tmp_20_fu_1054_p2)) then
ap_NS_fsm <= ap_ST_st6_fsm_5;
else
ap_NS_fsm <= ap_ST_st8_fsm_7;
end if;
when ap_ST_st8_fsm_7 =>
if ((ap_const_lv1_0 = tmp_32_fu_1103_p2)) then
ap_NS_fsm <= ap_ST_st18_fsm_17;
else
ap_NS_fsm <= ap_ST_st9_fsm_8;
end if;
when ap_ST_st9_fsm_8 =>
ap_NS_fsm <= ap_ST_st10_fsm_9;
when ap_ST_st10_fsm_9 =>
ap_NS_fsm <= ap_ST_st11_fsm_10;
when ap_ST_st11_fsm_10 =>
ap_NS_fsm <= ap_ST_st12_fsm_11;
when ap_ST_st12_fsm_11 =>
ap_NS_fsm <= ap_ST_st13_fsm_12;
when ap_ST_st13_fsm_12 =>
ap_NS_fsm <= ap_ST_st14_fsm_13;
when ap_ST_st14_fsm_13 =>
ap_NS_fsm <= ap_ST_st15_fsm_14;
when ap_ST_st15_fsm_14 =>
ap_NS_fsm <= ap_ST_st16_fsm_15;
when ap_ST_st16_fsm_15 =>
ap_NS_fsm <= ap_ST_st17_fsm_16;
when ap_ST_st17_fsm_16 =>
ap_NS_fsm <= ap_ST_st8_fsm_7;
when ap_ST_st18_fsm_17 =>
ap_NS_fsm <= ap_ST_st19_fsm_18;
when ap_ST_st19_fsm_18 =>
ap_NS_fsm <= ap_ST_st20_fsm_19;
when ap_ST_st20_fsm_19 =>
ap_NS_fsm <= ap_ST_st21_fsm_20;
when ap_ST_st21_fsm_20 =>
ap_NS_fsm <= ap_ST_st22_fsm_21;
when ap_ST_st22_fsm_21 =>
ap_NS_fsm <= ap_ST_st23_fsm_22;
when ap_ST_st23_fsm_22 =>
ap_NS_fsm <= ap_ST_st24_fsm_23;
when ap_ST_st24_fsm_23 =>
ap_NS_fsm <= ap_ST_st25_fsm_24;
when ap_ST_st25_fsm_24 =>
ap_NS_fsm <= ap_ST_st26_fsm_25;
when ap_ST_st26_fsm_25 =>
ap_NS_fsm <= ap_ST_st27_fsm_26;
when ap_ST_st27_fsm_26 =>
ap_NS_fsm <= ap_ST_st28_fsm_27;
when ap_ST_st28_fsm_27 =>
ap_NS_fsm <= ap_ST_st29_fsm_28;
when ap_ST_st29_fsm_28 =>
ap_NS_fsm <= ap_ST_st30_fsm_29;
when ap_ST_st30_fsm_29 =>
ap_NS_fsm <= ap_ST_st31_fsm_30;
when ap_ST_st31_fsm_30 =>
ap_NS_fsm <= ap_ST_st32_fsm_31;
when ap_ST_st32_fsm_31 =>
ap_NS_fsm <= ap_ST_st33_fsm_32;
when ap_ST_st33_fsm_32 =>
ap_NS_fsm <= ap_ST_st34_fsm_33;
when ap_ST_st34_fsm_33 =>
ap_NS_fsm <= ap_ST_st35_fsm_34;
when ap_ST_st35_fsm_34 =>
ap_NS_fsm <= ap_ST_st36_fsm_35;
when ap_ST_st36_fsm_35 =>
ap_NS_fsm <= ap_ST_st37_fsm_36;
when ap_ST_st37_fsm_36 =>
ap_NS_fsm <= ap_ST_st38_fsm_37;
when ap_ST_st38_fsm_37 =>
ap_NS_fsm <= ap_ST_st39_fsm_38;
when ap_ST_st39_fsm_38 =>
ap_NS_fsm <= ap_ST_st40_fsm_39;
when ap_ST_st40_fsm_39 =>
ap_NS_fsm <= ap_ST_st41_fsm_40;
when ap_ST_st41_fsm_40 =>
ap_NS_fsm <= ap_ST_st42_fsm_41;
when ap_ST_st42_fsm_41 =>
ap_NS_fsm <= ap_ST_st43_fsm_42;
when ap_ST_st43_fsm_42 =>
ap_NS_fsm <= ap_ST_st44_fsm_43;
when ap_ST_st44_fsm_43 =>
ap_NS_fsm <= ap_ST_st45_fsm_44;
when ap_ST_st45_fsm_44 =>
ap_NS_fsm <= ap_ST_st46_fsm_45;
when ap_ST_st46_fsm_45 =>
ap_NS_fsm <= ap_ST_st47_fsm_46;
when ap_ST_st47_fsm_46 =>
ap_NS_fsm <= ap_ST_st48_fsm_47;
when ap_ST_st48_fsm_47 =>
ap_NS_fsm <= ap_ST_st49_fsm_48;
when ap_ST_st49_fsm_48 =>
ap_NS_fsm <= ap_ST_st50_fsm_49;
when ap_ST_st50_fsm_49 =>
ap_NS_fsm <= ap_ST_st51_fsm_50;
when ap_ST_st51_fsm_50 =>
ap_NS_fsm <= ap_ST_st52_fsm_51;
when ap_ST_st52_fsm_51 =>
ap_NS_fsm <= ap_ST_st53_fsm_52;
when ap_ST_st53_fsm_52 =>
ap_NS_fsm <= ap_ST_st54_fsm_53;
when ap_ST_st54_fsm_53 =>
ap_NS_fsm <= ap_ST_st55_fsm_54;
when ap_ST_st55_fsm_54 =>
ap_NS_fsm <= ap_ST_st56_fsm_55;
when ap_ST_st56_fsm_55 =>
ap_NS_fsm <= ap_ST_st57_fsm_56;
when ap_ST_st57_fsm_56 =>
ap_NS_fsm <= ap_ST_st58_fsm_57;
when ap_ST_st58_fsm_57 =>
ap_NS_fsm <= ap_ST_st59_fsm_58;
when ap_ST_st59_fsm_58 =>
ap_NS_fsm <= ap_ST_st60_fsm_59;
when ap_ST_st60_fsm_59 =>
ap_NS_fsm <= ap_ST_st61_fsm_60;
when ap_ST_st61_fsm_60 =>
ap_NS_fsm <= ap_ST_st62_fsm_61;
when ap_ST_st62_fsm_61 =>
ap_NS_fsm <= ap_ST_st63_fsm_62;
when ap_ST_st63_fsm_62 =>
ap_NS_fsm <= ap_ST_st64_fsm_63;
when ap_ST_st64_fsm_63 =>
ap_NS_fsm <= ap_ST_st65_fsm_64;
when ap_ST_st65_fsm_64 =>
ap_NS_fsm <= ap_ST_st66_fsm_65;
when ap_ST_st66_fsm_65 =>
ap_NS_fsm <= ap_ST_st67_fsm_66;
when ap_ST_st67_fsm_66 =>
ap_NS_fsm <= ap_ST_st68_fsm_67;
when ap_ST_st68_fsm_67 =>
ap_NS_fsm <= ap_ST_st69_fsm_68;
when ap_ST_st69_fsm_68 =>
ap_NS_fsm <= ap_ST_st70_fsm_69;
when ap_ST_st70_fsm_69 =>
ap_NS_fsm <= ap_ST_st71_fsm_70;
when ap_ST_st71_fsm_70 =>
ap_NS_fsm <= ap_ST_st72_fsm_71;
when ap_ST_st72_fsm_71 =>
ap_NS_fsm <= ap_ST_st73_fsm_72;
when ap_ST_st73_fsm_72 =>
ap_NS_fsm <= ap_ST_st74_fsm_73;
when ap_ST_st74_fsm_73 =>
ap_NS_fsm <= ap_ST_st75_fsm_74;
when ap_ST_st75_fsm_74 =>
ap_NS_fsm <= ap_ST_st76_fsm_75;
when ap_ST_st76_fsm_75 =>
ap_NS_fsm <= ap_ST_st77_fsm_76;
when ap_ST_st77_fsm_76 =>
ap_NS_fsm <= ap_ST_st78_fsm_77;
when ap_ST_st78_fsm_77 =>
ap_NS_fsm <= ap_ST_st79_fsm_78;
when ap_ST_st79_fsm_78 =>
ap_NS_fsm <= ap_ST_st80_fsm_79;
when ap_ST_st80_fsm_79 =>
ap_NS_fsm <= ap_ST_st7_fsm_6;
when ap_ST_st81_fsm_80 =>
if (not((ap_const_lv1_0 = tmp_22_fu_1183_p2))) then
ap_NS_fsm <= ap_ST_st82_fsm_81;
else
ap_NS_fsm <= ap_ST_st123_fsm_122;
end if;
when ap_ST_st82_fsm_81 =>
if ((ap_const_lv1_0 = tmp_33_fu_1226_p2)) then
ap_NS_fsm <= ap_ST_st92_fsm_91;
else
ap_NS_fsm <= ap_ST_st83_fsm_82;
end if;
when ap_ST_st83_fsm_82 =>
ap_NS_fsm <= ap_ST_st84_fsm_83;
when ap_ST_st84_fsm_83 =>
ap_NS_fsm <= ap_ST_st85_fsm_84;
when ap_ST_st85_fsm_84 =>
ap_NS_fsm <= ap_ST_st86_fsm_85;
when ap_ST_st86_fsm_85 =>
ap_NS_fsm <= ap_ST_st87_fsm_86;
when ap_ST_st87_fsm_86 =>
ap_NS_fsm <= ap_ST_st88_fsm_87;
when ap_ST_st88_fsm_87 =>
ap_NS_fsm <= ap_ST_st89_fsm_88;
when ap_ST_st89_fsm_88 =>
ap_NS_fsm <= ap_ST_st90_fsm_89;
when ap_ST_st90_fsm_89 =>
ap_NS_fsm <= ap_ST_st91_fsm_90;
when ap_ST_st91_fsm_90 =>
ap_NS_fsm <= ap_ST_st82_fsm_81;
when ap_ST_st92_fsm_91 =>
ap_NS_fsm <= ap_ST_st93_fsm_92;
when ap_ST_st93_fsm_92 =>
ap_NS_fsm <= ap_ST_st94_fsm_93;
when ap_ST_st94_fsm_93 =>
ap_NS_fsm <= ap_ST_st95_fsm_94;
when ap_ST_st95_fsm_94 =>
ap_NS_fsm <= ap_ST_st96_fsm_95;
when ap_ST_st96_fsm_95 =>
ap_NS_fsm <= ap_ST_st97_fsm_96;
when ap_ST_st97_fsm_96 =>
ap_NS_fsm <= ap_ST_st98_fsm_97;
when ap_ST_st98_fsm_97 =>
ap_NS_fsm <= ap_ST_st99_fsm_98;
when ap_ST_st99_fsm_98 =>
ap_NS_fsm <= ap_ST_st100_fsm_99;
when ap_ST_st100_fsm_99 =>
ap_NS_fsm <= ap_ST_st101_fsm_100;
when ap_ST_st101_fsm_100 =>
ap_NS_fsm <= ap_ST_st102_fsm_101;
when ap_ST_st102_fsm_101 =>
ap_NS_fsm <= ap_ST_st103_fsm_102;
when ap_ST_st103_fsm_102 =>
ap_NS_fsm <= ap_ST_st104_fsm_103;
when ap_ST_st104_fsm_103 =>
ap_NS_fsm <= ap_ST_st105_fsm_104;
when ap_ST_st105_fsm_104 =>
ap_NS_fsm <= ap_ST_st106_fsm_105;
when ap_ST_st106_fsm_105 =>
ap_NS_fsm <= ap_ST_st107_fsm_106;
when ap_ST_st107_fsm_106 =>
ap_NS_fsm <= ap_ST_st108_fsm_107;
when ap_ST_st108_fsm_107 =>
ap_NS_fsm <= ap_ST_st109_fsm_108;
when ap_ST_st109_fsm_108 =>
ap_NS_fsm <= ap_ST_st110_fsm_109;
when ap_ST_st110_fsm_109 =>
ap_NS_fsm <= ap_ST_st111_fsm_110;
when ap_ST_st111_fsm_110 =>
ap_NS_fsm <= ap_ST_st112_fsm_111;
when ap_ST_st112_fsm_111 =>
ap_NS_fsm <= ap_ST_st113_fsm_112;
when ap_ST_st113_fsm_112 =>
ap_NS_fsm <= ap_ST_st114_fsm_113;
when ap_ST_st114_fsm_113 =>
ap_NS_fsm <= ap_ST_st115_fsm_114;
when ap_ST_st115_fsm_114 =>
ap_NS_fsm <= ap_ST_st116_fsm_115;
when ap_ST_st116_fsm_115 =>
ap_NS_fsm <= ap_ST_st117_fsm_116;
when ap_ST_st117_fsm_116 =>
ap_NS_fsm <= ap_ST_st118_fsm_117;
when ap_ST_st118_fsm_117 =>
ap_NS_fsm <= ap_ST_st119_fsm_118;
when ap_ST_st119_fsm_118 =>
ap_NS_fsm <= ap_ST_st120_fsm_119;
when ap_ST_st120_fsm_119 =>
ap_NS_fsm <= ap_ST_st121_fsm_120;
when ap_ST_st121_fsm_120 =>
ap_NS_fsm <= ap_ST_st122_fsm_121;
when ap_ST_st122_fsm_121 =>
ap_NS_fsm <= ap_ST_st81_fsm_80;
when ap_ST_st123_fsm_122 =>
if (((ap_const_lv1_0 = tmp_s_reg_1361) or (ap_const_lv1_0 = tmp_34_fu_1282_p2) or not((tmp_1_reg_1338 = ap_const_lv1_0)) or not((tmp_2_reg_1349 = ap_const_lv1_0)) or not((ap_const_lv1_0 = tmp_4_reg_1353)) or not((ap_const_lv1_0 = tmp_8_reg_1357)))) then
ap_NS_fsm <= ap_ST_st1_fsm_0;
else
ap_NS_fsm <= ap_ST_st124_fsm_123;
end if;
when ap_ST_st124_fsm_123 =>
ap_NS_fsm <= ap_ST_st125_fsm_124;
when ap_ST_st125_fsm_124 =>
ap_NS_fsm <= ap_ST_st126_fsm_125;
when ap_ST_st126_fsm_125 =>
ap_NS_fsm <= ap_ST_st127_fsm_126;
when ap_ST_st127_fsm_126 =>
ap_NS_fsm <= ap_ST_st128_fsm_127;
when ap_ST_st128_fsm_127 =>
ap_NS_fsm <= ap_ST_st129_fsm_128;
when ap_ST_st129_fsm_128 =>
ap_NS_fsm <= ap_ST_st130_fsm_129;
when ap_ST_st130_fsm_129 =>
ap_NS_fsm <= ap_ST_st131_fsm_130;
when ap_ST_st131_fsm_130 =>
ap_NS_fsm <= ap_ST_st132_fsm_131;
when ap_ST_st132_fsm_131 =>
ap_NS_fsm <= ap_ST_st133_fsm_132;
when ap_ST_st133_fsm_132 =>
ap_NS_fsm <= ap_ST_st134_fsm_133;
when ap_ST_st134_fsm_133 =>
ap_NS_fsm <= ap_ST_st135_fsm_134;
when ap_ST_st135_fsm_134 =>
ap_NS_fsm <= ap_ST_st136_fsm_135;
when ap_ST_st136_fsm_135 =>
ap_NS_fsm <= ap_ST_st137_fsm_136;
when ap_ST_st137_fsm_136 =>
ap_NS_fsm <= ap_ST_st138_fsm_137;
when ap_ST_st138_fsm_137 =>
ap_NS_fsm <= ap_ST_st139_fsm_138;
when ap_ST_st139_fsm_138 =>
ap_NS_fsm <= ap_ST_st140_fsm_139;
when ap_ST_st140_fsm_139 =>
ap_NS_fsm <= ap_ST_st141_fsm_140;
when ap_ST_st141_fsm_140 =>
ap_NS_fsm <= ap_ST_st123_fsm_122;
when ap_ST_st142_fsm_141 =>
ap_NS_fsm <= ap_ST_st143_fsm_142;
when ap_ST_st143_fsm_142 =>
ap_NS_fsm <= ap_ST_st123_fsm_122;
when others =>
ap_NS_fsm <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end case;
end process;
ANN_AXILiteS_s_axi_U_ap_dummy_ce <= ap_const_logic_1;
P_floatOut <= ST_uOut_q0;
-- P_floatOut_ap_vld assign process. --
P_floatOut_ap_vld_assign_proc : process(tmp_10_reg_1365, ap_sig_cseq_ST_st2_fsm_1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and not((ap_const_lv1_0 = tmp_10_reg_1365)))) then
P_floatOut_ap_vld <= ap_const_logic_1;
else
P_floatOut_ap_vld <= ap_const_logic_0;
end if;
end process;
P_intOut <= max_reg_298;
-- P_intOut_ap_vld assign process. --
P_intOut_ap_vld_assign_proc : process(tmp_10_reg_1365, tmp_14_reg_1369, ap_sig_cseq_ST_st2_fsm_1, tmp_24_fu_753_p2)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) and (ap_const_lv1_0 = tmp_10_reg_1365) and not((ap_const_lv1_0 = tmp_14_reg_1369)) and (ap_const_lv1_0 = tmp_24_fu_753_p2))) then
P_intOut_ap_vld <= ap_const_logic_1;
else
P_intOut_ap_vld <= ap_const_logic_0;
end if;
end process;
-- ST_WandB_address0 assign process. --
ST_WandB_address0_assign_proc : process(ap_sig_cseq_ST_st8_fsm_7, tmp_32_fu_1103_p2, ap_sig_cseq_ST_st82_fsm_81, tmp_33_fu_1226_p2, tmp_88_cast_fu_1137_p1, tmp_89_cast_fu_1150_p1, tmp_91_cast_fu_1260_p1, tmp_92_cast_fu_1273_p1, tmp_21_cast_fu_1317_p1, ap_sig_cseq_ST_st143_fsm_142)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142)) then
ST_WandB_address0 <= tmp_21_cast_fu_1317_p1(13 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st82_fsm_81) and (ap_const_lv1_0 = tmp_33_fu_1226_p2))) then
ST_WandB_address0 <= tmp_92_cast_fu_1273_p1(13 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st82_fsm_81) and not((ap_const_lv1_0 = tmp_33_fu_1226_p2)))) then
ST_WandB_address0 <= tmp_91_cast_fu_1260_p1(13 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) and (ap_const_lv1_0 = tmp_32_fu_1103_p2))) then
ST_WandB_address0 <= tmp_89_cast_fu_1150_p1(13 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) and not((ap_const_lv1_0 = tmp_32_fu_1103_p2)))) then
ST_WandB_address0 <= tmp_88_cast_fu_1137_p1(13 - 1 downto 0);
else
ST_WandB_address0 <= "XXXXXXXXXXXXX";
end if;
end process;
-- ST_WandB_ce0 assign process. --
ST_WandB_ce0_assign_proc : process(ap_sig_cseq_ST_st8_fsm_7, tmp_32_fu_1103_p2, ap_sig_cseq_ST_st82_fsm_81, tmp_33_fu_1226_p2, ap_sig_cseq_ST_st143_fsm_142)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) and not((ap_const_lv1_0 = tmp_32_fu_1103_p2))) or ((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) and (ap_const_lv1_0 = tmp_32_fu_1103_p2)) or ((ap_const_logic_1 = ap_sig_cseq_ST_st82_fsm_81) and not((ap_const_lv1_0 = tmp_33_fu_1226_p2))) or ((ap_const_logic_1 = ap_sig_cseq_ST_st82_fsm_81) and (ap_const_lv1_0 = tmp_33_fu_1226_p2)) or (ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142))) then
ST_WandB_ce0 <= ap_const_logic_1;
else
ST_WandB_ce0 <= ap_const_logic_0;
end if;
end process;
ST_WandB_d0 <= P_floatIn_read_reg_1333;
-- ST_WandB_we0 assign process. --
ST_WandB_we0_assign_proc : process(ap_sig_cseq_ST_st143_fsm_142)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st143_fsm_142))) then
ST_WandB_we0 <= ap_const_logic_1;
else
ST_WandB_we0 <= ap_const_logic_0;
end if;
end process;
-- ST_uOut_address0 assign process. --
ST_uOut_address0_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, tmp_1_fu_526_p2, tmp_2_fu_537_p2, tmp_4_fu_543_p2, tmp_8_fu_549_p2, tmp_s_fu_555_p2, tmp_10_fu_561_p2, ap_sig_cseq_ST_st2_fsm_1, ap_sig_cseq_ST_st82_fsm_81, ap_sig_cseq_ST_st123_fsm_122, tmp_65_cast_fu_661_p1, tmp_9_fu_666_p1, tmp_85_cast_fu_767_p1, tmp_90_cast_fu_1250_p1, tmp_93_cast_fu_1302_p1)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and (tmp_1_fu_526_p2 = ap_const_lv1_0) and (tmp_2_fu_537_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_4_fu_543_p2) and not((ap_const_lv1_0 = tmp_8_fu_549_p2)))) then
ST_uOut_address0 <= tmp_9_fu_666_p1(8 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st123_fsm_122)) then
ST_uOut_address0 <= tmp_93_cast_fu_1302_p1(8 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st82_fsm_81)) then
ST_uOut_address0 <= tmp_90_cast_fu_1250_p1(8 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
ST_uOut_address0 <= tmp_85_cast_fu_767_p1(8 - 1 downto 0);
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and (tmp_1_fu_526_p2 = ap_const_lv1_0) and (tmp_2_fu_537_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_4_fu_543_p2) and (ap_const_lv1_0 = tmp_8_fu_549_p2) and (ap_const_lv1_0 = tmp_s_fu_555_p2) and not((ap_const_lv1_0 = tmp_10_fu_561_p2)))) then
ST_uOut_address0 <= tmp_65_cast_fu_661_p1(8 - 1 downto 0);
else
ST_uOut_address0 <= "XXXXXXXX";
end if;
end process;
-- ST_uOut_address1 assign process. --
ST_uOut_address1_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, ST_uOut_addr_5_reg_1503, ap_sig_cseq_ST_st8_fsm_7, ST_uOut_addr_7_reg_1571, ST_uOut_addr_8_reg_1618, ap_sig_cseq_ST_st80_fsm_79, ap_sig_cseq_ST_st141_fsm_140, tmp_86_cast_fu_781_p1, tmp_87_cast_fu_1127_p1, ap_sig_cseq_ST_st118_fsm_117)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st141_fsm_140)) then
ST_uOut_address1 <= ST_uOut_addr_8_reg_1618;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st118_fsm_117)) then
ST_uOut_address1 <= ST_uOut_addr_7_reg_1571;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st80_fsm_79)) then
ST_uOut_address1 <= ST_uOut_addr_5_reg_1503;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7)) then
ST_uOut_address1 <= tmp_87_cast_fu_1127_p1(8 - 1 downto 0);
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1)) then
ST_uOut_address1 <= tmp_86_cast_fu_781_p1(8 - 1 downto 0);
else
ST_uOut_address1 <= "XXXXXXXX";
end if;
end process;
-- ST_uOut_ce0 assign process. --
ST_uOut_ce0_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0, tmp_1_fu_526_p2, tmp_2_fu_537_p2, tmp_4_fu_543_p2, tmp_8_fu_549_p2, tmp_s_fu_555_p2, tmp_10_fu_561_p2, ap_sig_cseq_ST_st2_fsm_1, ap_sig_cseq_ST_st82_fsm_81, ap_sig_cseq_ST_st123_fsm_122)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_526_p2 = ap_const_lv1_0) and (tmp_2_fu_537_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_4_fu_543_p2) and (ap_const_lv1_0 = tmp_8_fu_549_p2) and (ap_const_lv1_0 = tmp_s_fu_555_p2) and not((ap_const_lv1_0 = tmp_10_fu_561_p2))) or (ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) or (ap_const_logic_1 = ap_sig_cseq_ST_st82_fsm_81) or (ap_const_logic_1 = ap_sig_cseq_ST_st123_fsm_122) or ((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_526_p2 = ap_const_lv1_0) and (tmp_2_fu_537_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_4_fu_543_p2) and not((ap_const_lv1_0 = tmp_8_fu_549_p2))))) then
ST_uOut_ce0 <= ap_const_logic_1;
else
ST_uOut_ce0 <= ap_const_logic_0;
end if;
end process;
-- ST_uOut_ce1 assign process. --
ST_uOut_ce1_assign_proc : process(ap_sig_cseq_ST_st2_fsm_1, ap_sig_cseq_ST_st8_fsm_7, ap_sig_cseq_ST_st80_fsm_79, ap_sig_cseq_ST_st141_fsm_140, ap_sig_cseq_ST_st118_fsm_117)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st2_fsm_1) or (ap_const_logic_1 = ap_sig_cseq_ST_st8_fsm_7) or (ap_const_logic_1 = ap_sig_cseq_ST_st80_fsm_79) or (ap_const_logic_1 = ap_sig_cseq_ST_st141_fsm_140) or (ap_const_logic_1 = ap_sig_cseq_ST_st118_fsm_117))) then
ST_uOut_ce1 <= ap_const_logic_1;
else
ST_uOut_ce1 <= ap_const_logic_0;
end if;
end process;
ST_uOut_d0 <= P_floatIn;
-- ST_uOut_d1 assign process. --
ST_uOut_d1_assign_proc : process(reg_520, tmp_51_reg_1624, ap_sig_cseq_ST_st80_fsm_79, ap_sig_cseq_ST_st141_fsm_140, ap_sig_cseq_ST_st118_fsm_117)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st141_fsm_140)) then
ST_uOut_d1 <= tmp_51_reg_1624;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st80_fsm_79) or (ap_const_logic_1 = ap_sig_cseq_ST_st118_fsm_117))) then
ST_uOut_d1 <= reg_520;
else
ST_uOut_d1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
ST_uOut_load_1_to_int_fu_792_p1 <= reg_479;
ST_uOut_load_2_to_int_fu_810_p1 <= ST_uOut_load_2_reg_1425;
-- ST_uOut_we0 assign process. --
ST_uOut_we0_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0, tmp_1_fu_526_p2, tmp_2_fu_537_p2, tmp_4_fu_543_p2, tmp_8_fu_549_p2)
begin
if ((((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0) and not((ap_start = ap_const_logic_0)) and (tmp_1_fu_526_p2 = ap_const_lv1_0) and (tmp_2_fu_537_p2 = ap_const_lv1_0) and (ap_const_lv1_0 = tmp_4_fu_543_p2) and not((ap_const_lv1_0 = tmp_8_fu_549_p2))))) then
ST_uOut_we0 <= ap_const_logic_1;
else
ST_uOut_we0 <= ap_const_logic_0;
end if;
end process;
-- ST_uOut_we1 assign process. --
ST_uOut_we1_assign_proc : process(ap_sig_cseq_ST_st80_fsm_79, ap_sig_cseq_ST_st141_fsm_140, ap_sig_cseq_ST_st118_fsm_117)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st80_fsm_79) or (ap_const_logic_1 = ap_sig_cseq_ST_st141_fsm_140) or (ap_const_logic_1 = ap_sig_cseq_ST_st118_fsm_117))) then
ST_uOut_we1 <= ap_const_logic_1;
else
ST_uOut_we1 <= ap_const_logic_0;
end if;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(tmp_1_reg_1338, tmp_2_reg_1349, tmp_4_reg_1353, tmp_8_reg_1357, tmp_s_reg_1361, ap_sig_cseq_ST_st123_fsm_122, tmp_34_fu_1282_p2)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st123_fsm_122) and ((ap_const_lv1_0 = tmp_s_reg_1361) or (ap_const_lv1_0 = tmp_34_fu_1282_p2) or not((tmp_1_reg_1338 = ap_const_lv1_0)) or not((tmp_2_reg_1349 = ap_const_lv1_0)) or not((ap_const_lv1_0 = tmp_4_reg_1353)) or not((ap_const_lv1_0 = tmp_8_reg_1357))))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_sig_cseq_ST_st1_fsm_0)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(tmp_1_reg_1338, tmp_2_reg_1349, tmp_4_reg_1353, tmp_8_reg_1357, tmp_s_reg_1361, ap_sig_cseq_ST_st123_fsm_122, tmp_34_fu_1282_p2)
begin
if (((ap_const_logic_1 = ap_sig_cseq_ST_st123_fsm_122) and ((ap_const_lv1_0 = tmp_s_reg_1361) or (ap_const_lv1_0 = tmp_34_fu_1282_p2) or not((tmp_1_reg_1338 = ap_const_lv1_0)) or not((tmp_2_reg_1349 = ap_const_lv1_0)) or not((ap_const_lv1_0 = tmp_4_reg_1353)) or not((ap_const_lv1_0 = tmp_8_reg_1357))))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
-- ap_rst_n_inv assign process. --
ap_rst_n_inv_assign_proc : process(ap_rst_n)
begin
ap_rst_n_inv <= not(ap_rst_n);
end process;
-- ap_sig_bdd_161 assign process. --
ap_sig_bdd_161_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_161 <= (ap_CS_fsm(0 downto 0) = ap_const_lv1_1);
end process;
-- ap_sig_bdd_249 assign process. --
ap_sig_bdd_249_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_249 <= (ap_const_lv1_1 = ap_CS_fsm(2 downto 2));
end process;
-- ap_sig_bdd_256 assign process. --
ap_sig_bdd_256_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_256 <= (ap_const_lv1_1 = ap_CS_fsm(8 downto 8));
end process;
-- ap_sig_bdd_263 assign process. --
ap_sig_bdd_263_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_263 <= (ap_const_lv1_1 = ap_CS_fsm(82 downto 82));
end process;
-- ap_sig_bdd_271 assign process. --
ap_sig_bdd_271_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_271 <= (ap_const_lv1_1 = ap_CS_fsm(123 downto 123));
end process;
-- ap_sig_bdd_280 assign process. --
ap_sig_bdd_280_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_280 <= (ap_const_lv1_1 = ap_CS_fsm(17 downto 17));
end process;
-- ap_sig_bdd_289 assign process. --
ap_sig_bdd_289_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_289 <= (ap_const_lv1_1 = ap_CS_fsm(91 downto 91));
end process;
-- ap_sig_bdd_299 assign process. --
ap_sig_bdd_299_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_299 <= (ap_const_lv1_1 = ap_CS_fsm(11 downto 11));
end process;
-- ap_sig_bdd_306 assign process. --
ap_sig_bdd_306_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_306 <= (ap_const_lv1_1 = ap_CS_fsm(85 downto 85));
end process;
-- ap_sig_bdd_316 assign process. --
ap_sig_bdd_316_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_316 <= (ap_const_lv1_1 = ap_CS_fsm(16 downto 16));
end process;
-- ap_sig_bdd_323 assign process. --
ap_sig_bdd_323_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_323 <= (ap_const_lv1_1 = ap_CS_fsm(90 downto 90));
end process;
-- ap_sig_bdd_332 assign process. --
ap_sig_bdd_332_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_332 <= (ap_const_lv1_1 = ap_CS_fsm(22 downto 22));
end process;
-- ap_sig_bdd_339 assign process. --
ap_sig_bdd_339_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_339 <= (ap_const_lv1_1 = ap_CS_fsm(96 downto 96));
end process;
-- ap_sig_bdd_349 assign process. --
ap_sig_bdd_349_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_349 <= (ap_const_lv1_1 = ap_CS_fsm(23 downto 23));
end process;
-- ap_sig_bdd_356 assign process. --
ap_sig_bdd_356_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_356 <= (ap_const_lv1_1 = ap_CS_fsm(97 downto 97));
end process;
-- ap_sig_bdd_366 assign process. --
ap_sig_bdd_366_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_366 <= (ap_const_lv1_1 = ap_CS_fsm(41 downto 41));
end process;
-- ap_sig_bdd_373 assign process. --
ap_sig_bdd_373_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_373 <= (ap_const_lv1_1 = ap_CS_fsm(115 downto 115));
end process;
-- ap_sig_bdd_383 assign process. --
ap_sig_bdd_383_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_383 <= (ap_const_lv1_1 = ap_CS_fsm(78 downto 78));
end process;
-- ap_sig_bdd_390 assign process. --
ap_sig_bdd_390_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_390 <= (ap_const_lv1_1 = ap_CS_fsm(116 downto 116));
end process;
-- ap_sig_bdd_459 assign process. --
ap_sig_bdd_459_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_459 <= (ap_const_lv1_1 = ap_CS_fsm(1 downto 1));
end process;
-- ap_sig_bdd_485 assign process. --
ap_sig_bdd_485_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_485 <= (ap_const_lv1_1 = ap_CS_fsm(3 downto 3));
end process;
-- ap_sig_bdd_494 assign process. --
ap_sig_bdd_494_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_494 <= (ap_const_lv1_1 = ap_CS_fsm(4 downto 4));
end process;
-- ap_sig_bdd_503 assign process. --
ap_sig_bdd_503_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_503 <= (ap_const_lv1_1 = ap_CS_fsm(5 downto 5));
end process;
-- ap_sig_bdd_533 assign process. --
ap_sig_bdd_533_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_533 <= (ap_const_lv1_1 = ap_CS_fsm(6 downto 6));
end process;
-- ap_sig_bdd_555 assign process. --
ap_sig_bdd_555_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_555 <= (ap_const_lv1_1 = ap_CS_fsm(7 downto 7));
end process;
-- ap_sig_bdd_575 assign process. --
ap_sig_bdd_575_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_575 <= (ap_const_lv1_1 = ap_CS_fsm(46 downto 46));
end process;
-- ap_sig_bdd_584 assign process. --
ap_sig_bdd_584_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_584 <= (ap_const_lv1_1 = ap_CS_fsm(77 downto 77));
end process;
-- ap_sig_bdd_593 assign process. --
ap_sig_bdd_593_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_593 <= (ap_const_lv1_1 = ap_CS_fsm(80 downto 80));
end process;
-- ap_sig_bdd_614 assign process. --
ap_sig_bdd_614_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_614 <= (ap_const_lv1_1 = ap_CS_fsm(81 downto 81));
end process;
-- ap_sig_bdd_633 assign process. --
ap_sig_bdd_633_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_633 <= (ap_const_lv1_1 = ap_CS_fsm(121 downto 121));
end process;
-- ap_sig_bdd_642 assign process. --
ap_sig_bdd_642_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_642 <= (ap_const_lv1_1 = ap_CS_fsm(122 downto 122));
end process;
-- ap_sig_bdd_669 assign process. --
ap_sig_bdd_669_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_669 <= (ap_const_lv1_1 = ap_CS_fsm(139 downto 139));
end process;
-- ap_sig_bdd_678 assign process. --
ap_sig_bdd_678_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_678 <= (ap_const_lv1_1 = ap_CS_fsm(141 downto 141));
end process;
-- ap_sig_bdd_700 assign process. --
ap_sig_bdd_700_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_700 <= (ap_const_lv1_1 = ap_CS_fsm(79 downto 79));
end process;
-- ap_sig_bdd_722 assign process. --
ap_sig_bdd_722_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_722 <= (ap_const_lv1_1 = ap_CS_fsm(140 downto 140));
end process;
-- ap_sig_bdd_750 assign process. --
ap_sig_bdd_750_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_750 <= (ap_const_lv1_1 = ap_CS_fsm(142 downto 142));
end process;
-- ap_sig_bdd_816 assign process. --
ap_sig_bdd_816_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_816 <= (ap_const_lv1_1 = ap_CS_fsm(117 downto 117));
end process;
-- ap_sig_bdd_835 assign process. --
ap_sig_bdd_835_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_835 <= (ap_const_lv1_1 = ap_CS_fsm(12 downto 12));
end process;
-- ap_sig_bdd_842 assign process. --
ap_sig_bdd_842_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_842 <= (ap_const_lv1_1 = ap_CS_fsm(18 downto 18));
end process;
-- ap_sig_bdd_850 assign process. --
ap_sig_bdd_850_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_850 <= (ap_const_lv1_1 = ap_CS_fsm(86 downto 86));
end process;
-- ap_sig_bdd_857 assign process. --
ap_sig_bdd_857_assign_proc : process(ap_CS_fsm)
begin
ap_sig_bdd_857 <= (ap_const_lv1_1 = ap_CS_fsm(92 downto 92));
end process;
-- ap_sig_cseq_ST_st116_fsm_115 assign process. --
ap_sig_cseq_ST_st116_fsm_115_assign_proc : process(ap_sig_bdd_373)
begin
if (ap_sig_bdd_373) then
ap_sig_cseq_ST_st116_fsm_115 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st116_fsm_115 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st117_fsm_116 assign process. --
ap_sig_cseq_ST_st117_fsm_116_assign_proc : process(ap_sig_bdd_390)
begin
if (ap_sig_bdd_390) then
ap_sig_cseq_ST_st117_fsm_116 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st117_fsm_116 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st118_fsm_117 assign process. --
ap_sig_cseq_ST_st118_fsm_117_assign_proc : process(ap_sig_bdd_816)
begin
if (ap_sig_bdd_816) then
ap_sig_cseq_ST_st118_fsm_117 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st118_fsm_117 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st122_fsm_121 assign process. --
ap_sig_cseq_ST_st122_fsm_121_assign_proc : process(ap_sig_bdd_633)
begin
if (ap_sig_bdd_633) then
ap_sig_cseq_ST_st122_fsm_121 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st122_fsm_121 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st123_fsm_122 assign process. --
ap_sig_cseq_ST_st123_fsm_122_assign_proc : process(ap_sig_bdd_642)
begin
if (ap_sig_bdd_642) then
ap_sig_cseq_ST_st123_fsm_122 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st123_fsm_122 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st124_fsm_123 assign process. --
ap_sig_cseq_ST_st124_fsm_123_assign_proc : process(ap_sig_bdd_271)
begin
if (ap_sig_bdd_271) then
ap_sig_cseq_ST_st124_fsm_123 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st124_fsm_123 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st12_fsm_11 assign process. --
ap_sig_cseq_ST_st12_fsm_11_assign_proc : process(ap_sig_bdd_299)
begin
if (ap_sig_bdd_299) then
ap_sig_cseq_ST_st12_fsm_11 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st12_fsm_11 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st13_fsm_12 assign process. --
ap_sig_cseq_ST_st13_fsm_12_assign_proc : process(ap_sig_bdd_835)
begin
if (ap_sig_bdd_835) then
ap_sig_cseq_ST_st13_fsm_12 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st13_fsm_12 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st140_fsm_139 assign process. --
ap_sig_cseq_ST_st140_fsm_139_assign_proc : process(ap_sig_bdd_669)
begin
if (ap_sig_bdd_669) then
ap_sig_cseq_ST_st140_fsm_139 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st140_fsm_139 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st141_fsm_140 assign process. --
ap_sig_cseq_ST_st141_fsm_140_assign_proc : process(ap_sig_bdd_722)
begin
if (ap_sig_bdd_722) then
ap_sig_cseq_ST_st141_fsm_140 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st141_fsm_140 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st142_fsm_141 assign process. --
ap_sig_cseq_ST_st142_fsm_141_assign_proc : process(ap_sig_bdd_678)
begin
if (ap_sig_bdd_678) then
ap_sig_cseq_ST_st142_fsm_141 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st142_fsm_141 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st143_fsm_142 assign process. --
ap_sig_cseq_ST_st143_fsm_142_assign_proc : process(ap_sig_bdd_750)
begin
if (ap_sig_bdd_750) then
ap_sig_cseq_ST_st143_fsm_142 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st143_fsm_142 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st17_fsm_16 assign process. --
ap_sig_cseq_ST_st17_fsm_16_assign_proc : process(ap_sig_bdd_316)
begin
if (ap_sig_bdd_316) then
ap_sig_cseq_ST_st17_fsm_16 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st17_fsm_16 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st18_fsm_17 assign process. --
ap_sig_cseq_ST_st18_fsm_17_assign_proc : process(ap_sig_bdd_280)
begin
if (ap_sig_bdd_280) then
ap_sig_cseq_ST_st18_fsm_17 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st18_fsm_17 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st19_fsm_18 assign process. --
ap_sig_cseq_ST_st19_fsm_18_assign_proc : process(ap_sig_bdd_842)
begin
if (ap_sig_bdd_842) then
ap_sig_cseq_ST_st19_fsm_18 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st19_fsm_18 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st1_fsm_0 assign process. --
ap_sig_cseq_ST_st1_fsm_0_assign_proc : process(ap_sig_bdd_161)
begin
if (ap_sig_bdd_161) then
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st1_fsm_0 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st23_fsm_22 assign process. --
ap_sig_cseq_ST_st23_fsm_22_assign_proc : process(ap_sig_bdd_332)
begin
if (ap_sig_bdd_332) then
ap_sig_cseq_ST_st23_fsm_22 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st23_fsm_22 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st24_fsm_23 assign process. --
ap_sig_cseq_ST_st24_fsm_23_assign_proc : process(ap_sig_bdd_349)
begin
if (ap_sig_bdd_349) then
ap_sig_cseq_ST_st24_fsm_23 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st24_fsm_23 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st2_fsm_1 assign process. --
ap_sig_cseq_ST_st2_fsm_1_assign_proc : process(ap_sig_bdd_459)
begin
if (ap_sig_bdd_459) then
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st2_fsm_1 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st3_fsm_2 assign process. --
ap_sig_cseq_ST_st3_fsm_2_assign_proc : process(ap_sig_bdd_249)
begin
if (ap_sig_bdd_249) then
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st3_fsm_2 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st42_fsm_41 assign process. --
ap_sig_cseq_ST_st42_fsm_41_assign_proc : process(ap_sig_bdd_366)
begin
if (ap_sig_bdd_366) then
ap_sig_cseq_ST_st42_fsm_41 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st42_fsm_41 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st47_fsm_46 assign process. --
ap_sig_cseq_ST_st47_fsm_46_assign_proc : process(ap_sig_bdd_575)
begin
if (ap_sig_bdd_575) then
ap_sig_cseq_ST_st47_fsm_46 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st47_fsm_46 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st4_fsm_3 assign process. --
ap_sig_cseq_ST_st4_fsm_3_assign_proc : process(ap_sig_bdd_485)
begin
if (ap_sig_bdd_485) then
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st4_fsm_3 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st5_fsm_4 assign process. --
ap_sig_cseq_ST_st5_fsm_4_assign_proc : process(ap_sig_bdd_494)
begin
if (ap_sig_bdd_494) then
ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st5_fsm_4 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st6_fsm_5 assign process. --
ap_sig_cseq_ST_st6_fsm_5_assign_proc : process(ap_sig_bdd_503)
begin
if (ap_sig_bdd_503) then
ap_sig_cseq_ST_st6_fsm_5 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st6_fsm_5 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st78_fsm_77 assign process. --
ap_sig_cseq_ST_st78_fsm_77_assign_proc : process(ap_sig_bdd_584)
begin
if (ap_sig_bdd_584) then
ap_sig_cseq_ST_st78_fsm_77 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st78_fsm_77 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st79_fsm_78 assign process. --
ap_sig_cseq_ST_st79_fsm_78_assign_proc : process(ap_sig_bdd_383)
begin
if (ap_sig_bdd_383) then
ap_sig_cseq_ST_st79_fsm_78 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st79_fsm_78 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st7_fsm_6 assign process. --
ap_sig_cseq_ST_st7_fsm_6_assign_proc : process(ap_sig_bdd_533)
begin
if (ap_sig_bdd_533) then
ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st7_fsm_6 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st80_fsm_79 assign process. --
ap_sig_cseq_ST_st80_fsm_79_assign_proc : process(ap_sig_bdd_700)
begin
if (ap_sig_bdd_700) then
ap_sig_cseq_ST_st80_fsm_79 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st80_fsm_79 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st81_fsm_80 assign process. --
ap_sig_cseq_ST_st81_fsm_80_assign_proc : process(ap_sig_bdd_593)
begin
if (ap_sig_bdd_593) then
ap_sig_cseq_ST_st81_fsm_80 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st81_fsm_80 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st82_fsm_81 assign process. --
ap_sig_cseq_ST_st82_fsm_81_assign_proc : process(ap_sig_bdd_614)
begin
if (ap_sig_bdd_614) then
ap_sig_cseq_ST_st82_fsm_81 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st82_fsm_81 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st83_fsm_82 assign process. --
ap_sig_cseq_ST_st83_fsm_82_assign_proc : process(ap_sig_bdd_263)
begin
if (ap_sig_bdd_263) then
ap_sig_cseq_ST_st83_fsm_82 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st83_fsm_82 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st86_fsm_85 assign process. --
ap_sig_cseq_ST_st86_fsm_85_assign_proc : process(ap_sig_bdd_306)
begin
if (ap_sig_bdd_306) then
ap_sig_cseq_ST_st86_fsm_85 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st86_fsm_85 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st87_fsm_86 assign process. --
ap_sig_cseq_ST_st87_fsm_86_assign_proc : process(ap_sig_bdd_850)
begin
if (ap_sig_bdd_850) then
ap_sig_cseq_ST_st87_fsm_86 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st87_fsm_86 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st8_fsm_7 assign process. --
ap_sig_cseq_ST_st8_fsm_7_assign_proc : process(ap_sig_bdd_555)
begin
if (ap_sig_bdd_555) then
ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st8_fsm_7 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st91_fsm_90 assign process. --
ap_sig_cseq_ST_st91_fsm_90_assign_proc : process(ap_sig_bdd_323)
begin
if (ap_sig_bdd_323) then
ap_sig_cseq_ST_st91_fsm_90 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st91_fsm_90 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st92_fsm_91 assign process. --
ap_sig_cseq_ST_st92_fsm_91_assign_proc : process(ap_sig_bdd_289)
begin
if (ap_sig_bdd_289) then
ap_sig_cseq_ST_st92_fsm_91 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st92_fsm_91 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st93_fsm_92 assign process. --
ap_sig_cseq_ST_st93_fsm_92_assign_proc : process(ap_sig_bdd_857)
begin
if (ap_sig_bdd_857) then
ap_sig_cseq_ST_st93_fsm_92 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st93_fsm_92 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st97_fsm_96 assign process. --
ap_sig_cseq_ST_st97_fsm_96_assign_proc : process(ap_sig_bdd_339)
begin
if (ap_sig_bdd_339) then
ap_sig_cseq_ST_st97_fsm_96 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st97_fsm_96 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st98_fsm_97 assign process. --
ap_sig_cseq_ST_st98_fsm_97_assign_proc : process(ap_sig_bdd_356)
begin
if (ap_sig_bdd_356) then
ap_sig_cseq_ST_st98_fsm_97 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st98_fsm_97 <= ap_const_logic_0;
end if;
end process;
-- ap_sig_cseq_ST_st9_fsm_8 assign process. --
ap_sig_cseq_ST_st9_fsm_8_assign_proc : process(ap_sig_bdd_256)
begin
if (ap_sig_bdd_256) then
ap_sig_cseq_ST_st9_fsm_8 <= ap_const_logic_1;
else
ap_sig_cseq_ST_st9_fsm_8 <= ap_const_logic_0;
end if;
end process;
grp_fu_414_ce <= ap_const_logic_1;
-- grp_fu_414_p0 assign process. --
grp_fu_414_p0_assign_proc : process(sum_reg_334, sumsoft_reg_357, sum_1_reg_380, ap_sig_cseq_ST_st118_fsm_117, ap_sig_cseq_ST_st13_fsm_12, ap_sig_cseq_ST_st19_fsm_18, ap_sig_cseq_ST_st87_fsm_86, ap_sig_cseq_ST_st93_fsm_92)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st118_fsm_117)) then
grp_fu_414_p0 <= sumsoft_reg_357;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st87_fsm_86) or (ap_const_logic_1 = ap_sig_cseq_ST_st93_fsm_92))) then
grp_fu_414_p0 <= sum_1_reg_380;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st13_fsm_12) or (ap_const_logic_1 = ap_sig_cseq_ST_st19_fsm_18))) then
grp_fu_414_p0 <= sum_reg_334;
else
grp_fu_414_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- grp_fu_414_p1 assign process. --
grp_fu_414_p1_assign_proc : process(reg_487, reg_493, reg_520, ap_sig_cseq_ST_st118_fsm_117, ap_sig_cseq_ST_st13_fsm_12, ap_sig_cseq_ST_st19_fsm_18, ap_sig_cseq_ST_st87_fsm_86, ap_sig_cseq_ST_st93_fsm_92)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st118_fsm_117)) then
grp_fu_414_p1 <= reg_520;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st19_fsm_18) or (ap_const_logic_1 = ap_sig_cseq_ST_st93_fsm_92))) then
grp_fu_414_p1 <= reg_487;
elsif (((ap_const_logic_1 = ap_sig_cseq_ST_st13_fsm_12) or (ap_const_logic_1 = ap_sig_cseq_ST_st87_fsm_86))) then
grp_fu_414_p1 <= reg_493;
else
grp_fu_414_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_421_ce <= ap_const_logic_1;
-- grp_fu_421_p0 assign process. --
grp_fu_421_p0_assign_proc : process(ST_uOut_q0, ST_uOut_q1, ap_sig_cseq_ST_st9_fsm_8, ap_sig_cseq_ST_st83_fsm_82)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st83_fsm_82)) then
grp_fu_421_p0 <= ST_uOut_q0;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st9_fsm_8)) then
grp_fu_421_p0 <= ST_uOut_q1;
else
grp_fu_421_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_428_ce <= ap_const_logic_1;
-- grp_fu_433_p0 assign process. --
grp_fu_433_p0_assign_proc : process(reg_514, ap_sig_cseq_ST_st79_fsm_78, ap_sig_cseq_ST_st117_fsm_116, tmp_42_reg_1547)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st117_fsm_116)) then
grp_fu_433_p0 <= reg_514;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st79_fsm_78)) then
grp_fu_433_p0 <= tmp_42_reg_1547;
else
grp_fu_433_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- grp_fu_436_p0 assign process. --
grp_fu_436_p0_assign_proc : process(reg_504, ap_sig_cseq_ST_st24_fsm_23, ap_sig_cseq_ST_st98_fsm_97, tmp_38_fu_1165_p1)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st98_fsm_97)) then
grp_fu_436_p0 <= reg_504;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st24_fsm_23)) then
grp_fu_436_p0 <= tmp_38_fu_1165_p1;
else
grp_fu_436_p0 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_443_ce <= ap_const_logic_1;
grp_fu_448_ce <= ap_const_logic_1;
grp_fu_453_ce <= ap_const_logic_1;
-- grp_fu_458_p1 assign process. --
grp_fu_458_p1_assign_proc : process(ap_sig_cseq_ST_st1_fsm_0, ST_numLayer, ST_numLayer_load_reg_1342, ap_sig_cseq_ST_st6_fsm_5)
begin
if ((ap_const_logic_1 = ap_sig_cseq_ST_st6_fsm_5)) then
grp_fu_458_p1 <= ST_numLayer_load_reg_1342;
elsif ((ap_const_logic_1 = ap_sig_cseq_ST_st1_fsm_0)) then
grp_fu_458_p1 <= ST_numLayer;
else
grp_fu_458_p1 <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
grp_fu_458_p2 <= std_logic_vector(signed(ap_const_lv32_FFFFFFFF) + signed(grp_fu_458_p1));
i_2_cast_fu_1278_p1 <= std_logic_vector(resize(unsigned(i_2_reg_403),32));
i_3_fu_1093_p2 <= std_logic_vector(unsigned(i_reg_311) + unsigned(ap_const_lv31_1));
i_4_fu_786_p2 <= std_logic_vector(unsigned(ap_const_lv31_1) + unsigned(max_2_reg_287));
i_5_fu_1189_p2 <= std_logic_vector(unsigned(i_1_reg_369) + unsigned(ap_const_lv32_1));
i_6_fu_1287_p2 <= std_logic_vector(unsigned(i_2_reg_403) + unsigned(ap_const_lv31_1));
i_cast_fu_881_p1 <= std_logic_vector(resize(unsigned(i_reg_311),32));
j_1_cast_fu_1222_p1 <= std_logic_vector(resize(unsigned(j_1_reg_392),32));
j_2_fu_1060_p2 <= std_logic_vector(unsigned(j_reg_323) + unsigned(ap_const_lv32_1));
j_3_fu_1231_p2 <= std_logic_vector(unsigned(j_1_reg_392) + unsigned(ap_const_lv31_1));
k_1_fu_1108_p2 <= std_logic_vector(unsigned(k_reg_346) + unsigned(ap_const_lv31_1));
k_cast_fu_1099_p1 <= std_logic_vector(resize(unsigned(k_reg_346),32));
max_1_fu_875_p3 <=
max_2_cast_reg_1402 when (tmp_62_reg_1431(0) = '1') else
max_reg_298;
max_2_cast_fu_749_p1 <= std_logic_vector(resize(unsigned(max_2_reg_287),32));
notlhs1_fu_845_p2 <= "0" when (tmp_56_fu_813_p4 = ap_const_lv8_FF) else "1";
notlhs_fu_827_p2 <= "0" when (tmp_54_fu_796_p4 = ap_const_lv8_FF) else "1";
notrhs2_fu_851_p2 <= "1" when (tmp_96_fu_823_p1 = ap_const_lv23_0) else "0";
notrhs_fu_833_p2 <= "1" when (tmp_95_fu_806_p1 = ap_const_lv23_0) else "0";
p_shl10_cast_fu_629_p3 <= (tmp_71_fu_625_p1 & ap_const_lv5_0);
p_shl11_cast_fu_641_p3 <= (tmp_72_fu_637_p1 & ap_const_lv3_0);
p_shl12_cast_fu_577_p3 <= (tmp_73_fu_573_p1 & ap_const_lv5_0);
p_shl13_cast_fu_589_p3 <= (tmp_74_fu_585_p1 & ap_const_lv3_0);
p_shl1_cast_fu_695_p3 <= (tmp_12_fu_691_p1 & ap_const_lv3_0);
p_shl2_cast_fu_1011_p3 <= (tmp_66_fu_1007_p1 & ap_const_lv5_0);
p_shl3_cast_fu_1023_p3 <= (tmp_67_fu_1019_p1 & ap_const_lv3_0);
p_shl4_cast_fu_968_p3 <= (tmp_46_fu_964_p1 & ap_const_lv5_0);
p_shl5_cast_fu_980_p3 <= (tmp_50_fu_976_p1 & ap_const_lv3_0);
p_shl6_cast_fu_934_p3 <= (tmp_30_fu_930_p1 & ap_const_lv5_0);
p_shl7_cast_fu_946_p3 <= (tmp_35_fu_942_p1 & ap_const_lv3_0);
p_shl8_cast_fu_894_p3 <= (tmp_25_fu_890_p1 & ap_const_lv5_0);
p_shl9_cast_fu_906_p3 <= (tmp_26_fu_902_p1 & ap_const_lv3_0);
p_shl_cast_fu_683_p3 <= (tmp_11_fu_679_p1 & ap_const_lv5_0);
tmp_100_fu_1237_p1 <= j_1_reg_392(14 - 1 downto 0);
tmp_101_fu_1241_p1 <= j_1_reg_392(9 - 1 downto 0);
tmp_102_fu_1265_p1 <= tmp_53_reg_1565(14 - 1 downto 0);
tmp_10_fu_561_p2 <= "1" when (P_mode = ap_const_lv32_6) else "0";
tmp_11_fu_679_p1 <= P_index1(9 - 1 downto 0);
tmp_12_fu_691_p1 <= P_index1(11 - 1 downto 0);
tmp_13_fu_703_p2 <= std_logic_vector(unsigned(p_shl_cast_fu_683_p3) + unsigned(p_shl1_cast_fu_695_p3));
tmp_14_fu_567_p2 <= "1" when (P_mode = ap_const_lv32_7) else "0";
tmp_15_fu_924_p2 <= std_logic_vector(signed(ap_const_lv31_7FFFFFFF) + signed(i_reg_311));
tmp_16_fu_709_p2 <= std_logic_vector(unsigned(tmp_7_fu_675_p1) + unsigned(tmp_13_fu_703_p2));
tmp_19_fu_1307_p2 <= std_logic_vector(resize(unsigned(std_logic_vector(signed('0' &ap_const_lv14_29) * signed(tmp_16_reg_1394))), 14));
tmp_1_fu_526_p2 <= "1" when (P_mode = ap_const_lv32_1) else "0";
tmp_20_fu_1054_p2 <= "1" when (signed(j_reg_323) < signed(tmp_fu_1041_p6)) else "0";
tmp_21_cast_fu_1317_p1 <= std_logic_vector(resize(signed(tmp_21_reg_1629),64));
tmp_21_fu_1312_p2 <= std_logic_vector(unsigned(tmp_6_reg_1389) + unsigned(tmp_19_fu_1307_p2));
tmp_22_fu_1183_p2 <= "1" when (signed(i_1_reg_369) < signed(tmp_27_fu_1170_p6)) else "0";
tmp_23_fu_1002_p2 <= std_logic_vector(signed(ap_const_lv32_FFFFFFFE) + signed(ST_numLayer_load_reg_1342));
tmp_24_fu_753_p2 <= "1" when (signed(max_2_cast_fu_749_p1) < signed(tmp_31_reg_1379)) else "0";
tmp_25_fu_890_p1 <= i_reg_311(9 - 1 downto 0);
tmp_26_fu_902_p1 <= i_reg_311(11 - 1 downto 0);
tmp_28_fu_914_p2 <= std_logic_vector(unsigned(p_shl8_cast_fu_894_p3) + unsigned(p_shl9_cast_fu_906_p3));
tmp_29_fu_920_p1 <= i_reg_311(2 - 1 downto 0);
tmp_2_fu_537_p2 <= "1" when (P_mode = ap_const_lv32_2) else "0";
tmp_30_fu_930_p1 <= tmp_15_fu_924_p2(4 - 1 downto 0);
tmp_31_fu_607_p5 <= grp_fu_458_p2(2 - 1 downto 0);
tmp_32_fu_1103_p2 <= "1" when (signed(k_cast_fu_1099_p1) < signed(tmp_52_reg_1497)) else "0";
tmp_33_fu_1226_p2 <= "1" when (signed(j_1_cast_fu_1222_p1) < signed(tmp_53_reg_1565)) else "0";
tmp_34_fu_1282_p2 <= "1" when (signed(i_2_cast_fu_1278_p1) < signed(tmp_27_reg_1552)) else "0";
tmp_35_fu_942_p1 <= tmp_15_fu_924_p2(6 - 1 downto 0);
tmp_37_fu_954_p2 <= std_logic_vector(unsigned(p_shl6_cast_fu_934_p3) + unsigned(p_shl7_cast_fu_946_p3));
tmp_38_fu_1165_p1 <= tmp_38_neg_fu_1159_p2;
tmp_38_neg_fu_1159_p2 <= (tmp_38_to_int_fu_1155_p1 xor ap_const_lv32_80000000);
tmp_38_to_int_fu_1155_p1 <= reg_504;
tmp_3_fu_885_p2 <= "1" when (signed(i_cast_fu_881_p1) < signed(ST_numLayer_load_reg_1342)) else "0";
tmp_44_fu_960_p1 <= tmp_15_fu_924_p2(2 - 1 downto 0);
tmp_46_fu_964_p1 <= grp_fu_458_p2(9 - 1 downto 0);
tmp_4_fu_543_p2 <= "1" when (P_mode = ap_const_lv32_3) else "0";
tmp_50_fu_976_p1 <= grp_fu_458_p2(11 - 1 downto 0);
tmp_54_fu_796_p4 <= ST_uOut_load_1_to_int_fu_792_p1(30 downto 23);
tmp_55_fu_988_p2 <= std_logic_vector(unsigned(p_shl4_cast_fu_968_p3) + unsigned(p_shl5_cast_fu_980_p3));
tmp_56_fu_813_p4 <= ST_uOut_load_2_to_int_fu_810_p1(30 downto 23);
tmp_57_fu_994_p1 <= tmp_55_fu_988_p2(9 - 1 downto 0);
tmp_58_fu_839_p2 <= (notrhs_fu_833_p2 or notlhs_fu_827_p2);
tmp_59_fu_857_p2 <= (notrhs2_fu_851_p2 or notlhs1_fu_845_p2);
tmp_5_fu_715_p1 <= P_index1(2 - 1 downto 0);
tmp_60_fu_863_p2 <= (tmp_58_fu_839_p2 and tmp_59_fu_857_p2);
tmp_61_fu_439_opcode <= ap_const_lv5_2;
tmp_62_fu_869_p2 <= (tmp_60_fu_863_p2 and tmp_61_fu_439_p2);
tmp_63_fu_998_p1 <= grp_fu_458_p2(2 - 1 downto 0);
tmp_64_fu_649_p2 <= std_logic_vector(unsigned(p_shl10_cast_fu_629_p3) + unsigned(p_shl11_cast_fu_641_p3));
tmp_65_cast_fu_661_p1 <= std_logic_vector(resize(signed(tmp_65_fu_655_p2),64));
tmp_65_fu_655_p2 <= std_logic_vector(unsigned(tmp_70_fu_621_p1) + unsigned(tmp_64_fu_649_p2));
tmp_66_fu_1007_p1 <= tmp_23_fu_1002_p2(4 - 1 downto 0);
tmp_67_fu_1019_p1 <= tmp_23_fu_1002_p2(6 - 1 downto 0);
tmp_68_fu_1031_p2 <= std_logic_vector(unsigned(p_shl2_cast_fu_1011_p3) + unsigned(p_shl3_cast_fu_1023_p3));
tmp_69_fu_1037_p1 <= tmp_23_fu_1002_p2(2 - 1 downto 0);
tmp_6_fu_671_p1 <= P_intIn_index3(14 - 1 downto 0);
tmp_70_fu_621_p1 <= P_index2(9 - 1 downto 0);
tmp_71_fu_625_p1 <= P_index1(4 - 1 downto 0);
tmp_72_fu_637_p1 <= P_index1(6 - 1 downto 0);
tmp_73_fu_573_p1 <= grp_fu_458_p2(4 - 1 downto 0);
tmp_74_fu_585_p1 <= grp_fu_458_p2(6 - 1 downto 0);
tmp_75_fu_597_p2 <= std_logic_vector(unsigned(p_shl12_cast_fu_577_p3) + unsigned(p_shl13_cast_fu_589_p3));
tmp_77_fu_1079_p1 <= j_reg_323(14 - 1 downto 0);
tmp_78_fu_1083_p2 <= std_logic_vector(unsigned(tmp_28_reg_1444) + unsigned(tmp_77_fu_1079_p1));
tmp_79_fu_1327_p0 <= ap_const_lv14_29(7 - 1 downto 0);
tmp_7_fu_675_p1 <= P_index2(14 - 1 downto 0);
tmp_80_fu_1208_p1 <= i_1_reg_369(14 - 1 downto 0);
tmp_81_cast_fu_1088_p1 <= std_logic_vector(resize(signed(tmp_78_fu_1083_p2),64));
tmp_81_fu_1212_p2 <= std_logic_vector(unsigned(tmp_55_reg_1464) + unsigned(tmp_80_fu_1208_p1));
tmp_82_fu_1321_p0 <= ap_const_lv14_29(7 - 1 downto 0);
tmp_83_cast_fu_1217_p1 <= std_logic_vector(resize(signed(tmp_81_fu_1212_p2),64));
tmp_83_fu_1293_p1 <= i_2_reg_403(9 - 1 downto 0);
tmp_84_fu_1297_p2 <= std_logic_vector(unsigned(tmp_57_reg_1469) + unsigned(tmp_83_fu_1293_p1));
tmp_85_cast_fu_767_p1 <= std_logic_vector(resize(signed(tmp_85_fu_762_p2),64));
tmp_85_fu_762_p2 <= std_logic_vector(unsigned(tmp_93_fu_758_p1) + unsigned(tmp_75_reg_1373));
tmp_86_cast_fu_781_p1 <= std_logic_vector(resize(signed(tmp_86_fu_776_p2),64));
tmp_86_fu_776_p2 <= std_logic_vector(unsigned(tmp_94_fu_772_p1) + unsigned(tmp_75_reg_1373));
tmp_87_cast_fu_1127_p1 <= std_logic_vector(resize(unsigned(tmp_87_fu_1122_p2),64));
tmp_87_fu_1122_p2 <= std_logic_vector(unsigned(tmp_37_reg_1454) + unsigned(tmp_98_fu_1118_p1));
tmp_88_cast_fu_1137_p1 <= std_logic_vector(resize(signed(tmp_88_fu_1132_p2),64));
tmp_88_fu_1132_p2 <= std_logic_vector(signed(tmp_79_reg_1508) + signed(tmp_97_fu_1114_p1));
tmp_89_cast_fu_1150_p1 <= std_logic_vector(resize(signed(tmp_89_fu_1145_p2),64));
tmp_89_fu_1145_p2 <= std_logic_vector(signed(tmp_79_reg_1508) + signed(tmp_99_fu_1142_p1));
tmp_8_fu_549_p2 <= "1" when (P_mode = ap_const_lv32_4) else "0";
tmp_90_cast_fu_1250_p1 <= std_logic_vector(resize(signed(tmp_90_fu_1245_p2),64));
tmp_90_fu_1245_p2 <= std_logic_vector(unsigned(tmp_68_reg_1479) + unsigned(tmp_101_fu_1241_p1));
tmp_91_cast_fu_1260_p1 <= std_logic_vector(resize(signed(tmp_91_fu_1255_p2),64));
tmp_91_fu_1255_p2 <= std_logic_vector(signed(tmp_82_reg_1576) + signed(tmp_100_fu_1237_p1));
tmp_92_cast_fu_1273_p1 <= std_logic_vector(resize(signed(tmp_92_fu_1268_p2),64));
tmp_92_fu_1268_p2 <= std_logic_vector(signed(tmp_82_reg_1576) + signed(tmp_102_fu_1265_p1));
tmp_93_cast_fu_1302_p1 <= std_logic_vector(resize(signed(tmp_84_fu_1297_p2),64));
tmp_93_fu_758_p1 <= max_2_reg_287(9 - 1 downto 0);
tmp_94_fu_772_p1 <= max_reg_298(9 - 1 downto 0);
tmp_95_fu_806_p1 <= ST_uOut_load_1_to_int_fu_792_p1(23 - 1 downto 0);
tmp_96_fu_823_p1 <= ST_uOut_load_2_to_int_fu_810_p1(23 - 1 downto 0);
tmp_97_fu_1114_p1 <= k_reg_346(14 - 1 downto 0);
tmp_98_fu_1118_p1 <= k_reg_346(9 - 1 downto 0);
tmp_99_fu_1142_p1 <= tmp_52_reg_1497(14 - 1 downto 0);
tmp_9_fu_666_p1 <= std_logic_vector(resize(signed(P_index1),64));
tmp_s_fu_555_p2 <= "1" when (P_mode = ap_const_lv32_5) else "0";
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity mem_bus_arbiter_pri is
generic (
g_registered: boolean := true;
g_ports : positive := 3 );
port (
clock : in std_logic;
reset : in std_logic;
reqs : in t_mem_req_array(0 to g_ports-1);
resps : out t_mem_resp_array(0 to g_ports-1);
req : out t_mem_req;
resp : in t_mem_resp );
end entity;
architecture rtl of mem_bus_arbiter_pri is
signal req_i : t_mem_req;
signal req_c : t_mem_req;
begin
-- prioritize the first request found onto output
process(reqs)
begin
req_i <= c_mem_req_init;
for i in reqs'range loop
if reqs(i).request='1' then
req_i <= reqs(i);
exit;
end if;
end loop;
end process;
-- send the reply to everyone (including tag)
process(resp)
begin
for i in resps'range loop
resps(i) <= resp;
end loop;
end process;
-- output register (will be eliminated when not used)
process(clock)
begin
if rising_edge(clock) then
req_c <= req_i;
if resp.rack = '1' and (resp.rack_tag = req_c.tag) then
req_c.request <= '0';
end if;
end if;
end process;
req <= req_c when g_registered else req_i;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity mem_bus_arbiter_pri is
generic (
g_registered: boolean := true;
g_ports : positive := 3 );
port (
clock : in std_logic;
reset : in std_logic;
reqs : in t_mem_req_array(0 to g_ports-1);
resps : out t_mem_resp_array(0 to g_ports-1);
req : out t_mem_req;
resp : in t_mem_resp );
end entity;
architecture rtl of mem_bus_arbiter_pri is
signal req_i : t_mem_req;
signal req_c : t_mem_req;
begin
-- prioritize the first request found onto output
process(reqs)
begin
req_i <= c_mem_req_init;
for i in reqs'range loop
if reqs(i).request='1' then
req_i <= reqs(i);
exit;
end if;
end loop;
end process;
-- send the reply to everyone (including tag)
process(resp)
begin
for i in resps'range loop
resps(i) <= resp;
end loop;
end process;
-- output register (will be eliminated when not used)
process(clock)
begin
if rising_edge(clock) then
req_c <= req_i;
if resp.rack = '1' and (resp.rack_tag = req_c.tag) then
req_c.request <= '0';
end if;
end if;
end process;
req <= req_c when g_registered else req_i;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity mem_bus_arbiter_pri is
generic (
g_registered: boolean := true;
g_ports : positive := 3 );
port (
clock : in std_logic;
reset : in std_logic;
reqs : in t_mem_req_array(0 to g_ports-1);
resps : out t_mem_resp_array(0 to g_ports-1);
req : out t_mem_req;
resp : in t_mem_resp );
end entity;
architecture rtl of mem_bus_arbiter_pri is
signal req_i : t_mem_req;
signal req_c : t_mem_req;
begin
-- prioritize the first request found onto output
process(reqs)
begin
req_i <= c_mem_req_init;
for i in reqs'range loop
if reqs(i).request='1' then
req_i <= reqs(i);
exit;
end if;
end loop;
end process;
-- send the reply to everyone (including tag)
process(resp)
begin
for i in resps'range loop
resps(i) <= resp;
end loop;
end process;
-- output register (will be eliminated when not used)
process(clock)
begin
if rising_edge(clock) then
req_c <= req_i;
if resp.rack = '1' and (resp.rack_tag = req_c.tag) then
req_c.request <= '0';
end if;
end if;
end process;
req <= req_c when g_registered else req_i;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity mem_bus_arbiter_pri is
generic (
g_registered: boolean := true;
g_ports : positive := 3 );
port (
clock : in std_logic;
reset : in std_logic;
reqs : in t_mem_req_array(0 to g_ports-1);
resps : out t_mem_resp_array(0 to g_ports-1);
req : out t_mem_req;
resp : in t_mem_resp );
end entity;
architecture rtl of mem_bus_arbiter_pri is
signal req_i : t_mem_req;
signal req_c : t_mem_req;
begin
-- prioritize the first request found onto output
process(reqs)
begin
req_i <= c_mem_req_init;
for i in reqs'range loop
if reqs(i).request='1' then
req_i <= reqs(i);
exit;
end if;
end loop;
end process;
-- send the reply to everyone (including tag)
process(resp)
begin
for i in resps'range loop
resps(i) <= resp;
end loop;
end process;
-- output register (will be eliminated when not used)
process(clock)
begin
if rising_edge(clock) then
req_c <= req_i;
if resp.rack = '1' and (resp.rack_tag = req_c.tag) then
req_c.request <= '0';
end if;
end if;
end process;
req <= req_c when g_registered else req_i;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity mem_bus_arbiter_pri is
generic (
g_registered: boolean := true;
g_ports : positive := 3 );
port (
clock : in std_logic;
reset : in std_logic;
reqs : in t_mem_req_array(0 to g_ports-1);
resps : out t_mem_resp_array(0 to g_ports-1);
req : out t_mem_req;
resp : in t_mem_resp );
end entity;
architecture rtl of mem_bus_arbiter_pri is
signal req_i : t_mem_req;
signal req_c : t_mem_req;
begin
-- prioritize the first request found onto output
process(reqs)
begin
req_i <= c_mem_req_init;
for i in reqs'range loop
if reqs(i).request='1' then
req_i <= reqs(i);
exit;
end if;
end loop;
end process;
-- send the reply to everyone (including tag)
process(resp)
begin
for i in resps'range loop
resps(i) <= resp;
end loop;
end process;
-- output register (will be eliminated when not used)
process(clock)
begin
if rising_edge(clock) then
req_c <= req_i;
if resp.rack = '1' and (resp.rack_tag = req_c.tag) then
req_c.request <= '0';
end if;
end if;
end process;
req <= req_c when g_registered else req_i;
end architecture;
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
library util;
use util.logic_pkg.all;
use util.types_pkg.all;
library sys;
use sys.sys_pkg.all;
library mem;
library tech;
use work.cpu_types_pkg.all;
use work.cpu_l1mem_data_types_pkg.all;
use work.cpu_l1mem_data_cache_pkg.all;
use work.cpu_l1mem_data_cache_config_pkg.all;
use work.cpu_l1mem_data_cache_replace_pkg.all;
architecture rtl of cpu_l1mem_data_cache is
type comb_type is record
cpu_l1mem_data_cache_ctrl_out_vram : cpu_l1mem_data_cache_ctrl_out_vram_type;
cpu_l1mem_data_cache_ctrl_in_vram : cpu_l1mem_data_cache_ctrl_in_vram_type;
cpu_l1mem_data_cache_dp_out_vram : cpu_l1mem_data_cache_dp_out_vram_type;
cpu_l1mem_data_cache_ctrl_out_mram : cpu_l1mem_data_cache_ctrl_out_mram_type;
cpu_l1mem_data_cache_ctrl_in_mram : cpu_l1mem_data_cache_ctrl_in_mram_type;
cpu_l1mem_data_cache_dp_out_mram : cpu_l1mem_data_cache_dp_out_mram_type;
cpu_l1mem_data_cache_ctrl_out_tram : cpu_l1mem_data_cache_ctrl_out_tram_type;
cpu_l1mem_data_cache_dp_in_tram : cpu_l1mem_data_cache_dp_in_tram_type;
cpu_l1mem_data_cache_dp_out_tram : cpu_l1mem_data_cache_dp_out_tram_type;
cpu_l1mem_data_cache_ctrl_out_dram : cpu_l1mem_data_cache_ctrl_out_dram_type;
cpu_l1mem_data_cache_dp_in_dram : cpu_l1mem_data_cache_dp_in_dram_type;
cpu_l1mem_data_cache_dp_out_dram : cpu_l1mem_data_cache_dp_out_dram_type;
cpu_l1mem_data_cache_dp_in_ctrl : cpu_l1mem_data_cache_dp_in_ctrl_type;
cpu_l1mem_data_cache_dp_out_ctrl : cpu_l1mem_data_cache_dp_out_ctrl_type;
cpu_l1mem_data_cache_replace_ctrl_out : cpu_l1mem_data_cache_replace_ctrl_out_type;
cpu_l1mem_data_cache_replace_ctrl_in : cpu_l1mem_data_cache_replace_ctrl_in_type;
cpu_l1mem_data_cache_replace_dp_in : cpu_l1mem_data_cache_replace_dp_in_type;
cpu_l1mem_data_cache_replace_dp_out : cpu_l1mem_data_cache_replace_dp_out_type;
cpu_l1mem_data_cache_ctrl_out : cpu_l1mem_data_cache_ctrl_out_type;
cpu_l1mem_data_cache_dp_out : cpu_l1mem_data_cache_dp_out_type;
sys_master_ctrl_out : sys_master_ctrl_out_type;
sys_master_dp_out : sys_master_dp_out_type;
end record;
signal c : comb_type;
begin
-- pragma translate_off
process (clk) is
begin
if rising_edge(clk) and rstn = '1' then
case cpu_l1mem_data_cache_ctrl_in.request is
when cpu_l1mem_data_request_code_none |
cpu_l1mem_data_request_code_load |
cpu_l1mem_data_request_code_store |
cpu_l1mem_data_request_code_invalidate |
cpu_l1mem_data_request_code_flush |
cpu_l1mem_data_request_code_writeback |
cpu_l1mem_data_request_code_sync =>
null;
when others =>
assert false
report "cpu_l1mem_data_cache_ctrl_in.request invalid"
severity failure;
end case;
case cpu_l1mem_data_cache_ctrl_in.request is
when cpu_l1mem_data_request_code_load |
cpu_l1mem_data_request_code_store =>
assert not is_x(cpu_l1mem_data_cache_ctrl_in.cacheen)
report "cpu_l1mem_data_cache_ctrl_in.cacheen invalid"
severity failure;
when others =>
null;
end case;
case cpu_l1mem_data_cache_ctrl_in.request is
when cpu_l1mem_data_request_code_load |
cpu_l1mem_data_request_code_store |
cpu_l1mem_data_request_code_invalidate |
cpu_l1mem_data_request_code_flush |
cpu_l1mem_data_request_code_writeback =>
assert not is_x(cpu_l1mem_data_cache_ctrl_in.mmuen)
report "cpu_l1mem_data_cache_ctrl_in.mmuen invalid"
severity failure;
when others =>
null;
end case;
if cpu_l1mem_data_cache_ctrl_in.cacheen = '1' then
case cpu_l1mem_data_cache_ctrl_in.request is
when cpu_l1mem_data_request_code_load |
cpu_l1mem_data_request_code_store =>
assert not is_x(cpu_l1mem_data_cache_ctrl_in.be)
report "cpu_l1mem_data_cache_ctrl_in.alloc invalid"
severity failure;
assert not is_x(cpu_l1mem_data_cache_ctrl_in.alloc)
report "cpu_l1mem_data_cache_ctrl_in.alloc invalid"
severity failure;
assert not is_x(cpu_l1mem_data_cache_ctrl_in.writethrough)
report "cpu_l1mem_data_cache_ctrl_in.writethrough invalid"
severity failure;
when others =>
null;
end case;
end if;
end if;
end process;
-- pragma translate_on
ctrl : entity work.cpu_l1mem_data_cache_ctrl(rtl)
port map (
clk => clk,
rstn => rstn,
cpu_mmu_data_ctrl_in => cpu_mmu_data_ctrl_in,
cpu_mmu_data_ctrl_out => cpu_mmu_data_ctrl_out,
cpu_l1mem_data_cache_ctrl_out => c.cpu_l1mem_data_cache_ctrl_out,
cpu_l1mem_data_cache_ctrl_in => cpu_l1mem_data_cache_ctrl_in,
sys_master_ctrl_out => c.sys_master_ctrl_out,
sys_slave_ctrl_out => sys_slave_ctrl_out,
cpu_l1mem_data_cache_ctrl_out_vram => c.cpu_l1mem_data_cache_ctrl_out_vram,
cpu_l1mem_data_cache_ctrl_in_vram => c.cpu_l1mem_data_cache_ctrl_in_vram,
cpu_l1mem_data_cache_ctrl_out_mram => c.cpu_l1mem_data_cache_ctrl_out_mram,
cpu_l1mem_data_cache_ctrl_in_mram => c.cpu_l1mem_data_cache_ctrl_in_mram,
cpu_l1mem_data_cache_ctrl_out_tram => c.cpu_l1mem_data_cache_ctrl_out_tram,
cpu_l1mem_data_cache_ctrl_out_dram => c.cpu_l1mem_data_cache_ctrl_out_dram,
cpu_l1mem_data_cache_dp_in_ctrl => c.cpu_l1mem_data_cache_dp_in_ctrl,
cpu_l1mem_data_cache_dp_out_ctrl => c.cpu_l1mem_data_cache_dp_out_ctrl,
cpu_l1mem_data_cache_replace_ctrl_in => c.cpu_l1mem_data_cache_replace_ctrl_in,
cpu_l1mem_data_cache_replace_ctrl_out => c.cpu_l1mem_data_cache_replace_ctrl_out
);
cpu_l1mem_data_cache_ctrl_out <= c.cpu_l1mem_data_cache_ctrl_out;
sys_master_ctrl_out <= c.sys_master_ctrl_out;
dp : entity work.cpu_l1mem_data_cache_dp(rtl)
port map (
clk => clk,
rstn => rstn,
cpu_mmu_data_dp_in => cpu_mmu_data_dp_in,
cpu_mmu_data_dp_out => cpu_mmu_data_dp_out,
cpu_l1mem_data_cache_dp_out => c.cpu_l1mem_data_cache_dp_out,
cpu_l1mem_data_cache_dp_in => cpu_l1mem_data_cache_dp_in,
sys_master_dp_out => c.sys_master_dp_out,
sys_slave_dp_out => sys_slave_dp_out,
cpu_l1mem_data_cache_dp_out_vram => c.cpu_l1mem_data_cache_dp_out_vram,
cpu_l1mem_data_cache_dp_out_mram => c.cpu_l1mem_data_cache_dp_out_mram,
cpu_l1mem_data_cache_dp_out_tram => c.cpu_l1mem_data_cache_dp_out_tram,
cpu_l1mem_data_cache_dp_in_tram => c.cpu_l1mem_data_cache_dp_in_tram,
cpu_l1mem_data_cache_dp_out_dram => c.cpu_l1mem_data_cache_dp_out_dram,
cpu_l1mem_data_cache_dp_in_dram => c.cpu_l1mem_data_cache_dp_in_dram,
cpu_l1mem_data_cache_dp_in_ctrl => c.cpu_l1mem_data_cache_dp_in_ctrl,
cpu_l1mem_data_cache_dp_out_ctrl => c.cpu_l1mem_data_cache_dp_out_ctrl,
cpu_l1mem_data_cache_replace_dp_in => c.cpu_l1mem_data_cache_replace_dp_in,
cpu_l1mem_data_cache_replace_dp_out => c.cpu_l1mem_data_cache_replace_dp_out
);
cpu_l1mem_data_cache_dp_out <= c.cpu_l1mem_data_cache_dp_out;
sys_master_dp_out <= c.sys_master_dp_out;
replace : entity work.cpu_l1mem_data_cache_replace(rtl)
port map (
clk => clk,
rstn => rstn,
cpu_l1mem_data_cache_replace_ctrl_out => c.cpu_l1mem_data_cache_replace_ctrl_out,
cpu_l1mem_data_cache_replace_ctrl_in => c.cpu_l1mem_data_cache_replace_ctrl_in,
cpu_l1mem_data_cache_replace_dp_in => c.cpu_l1mem_data_cache_replace_dp_in,
cpu_l1mem_data_cache_replace_dp_out => c.cpu_l1mem_data_cache_replace_dp_out
);
-- pragma translate_off
process (clk) is
begin
if rising_edge(clk) and rstn = '1' then
assert not is_x(c.cpu_l1mem_data_cache_replace_ctrl_in.re)
report "replace re is invalid"
severity failure;
assert not is_x(c.cpu_l1mem_data_cache_replace_ctrl_in.we)
report "replace we is invalid"
severity failure;
if c.cpu_l1mem_data_cache_replace_ctrl_in.re = '1' then
assert not is_x(c.cpu_l1mem_data_cache_replace_dp_in.rindex)
report "replace rindex is invalid"
severity failure;
end if;
if c.cpu_l1mem_data_cache_replace_ctrl_in.we = '1' then
assert not is_x(c.cpu_l1mem_data_cache_replace_dp_in.windex)
report "replace windex is invalid"
severity failure;
assert not is_x(c.cpu_l1mem_data_cache_replace_dp_in.wstate)
report "replace wstate is invalid"
severity failure;
end if;
end if;
end process;
-- pragma translate_on
vram : entity tech.syncram_1r1w(rtl)
generic map (
addr_bits => cpu_l1mem_data_cache_index_bits,
data_bits => cpu_l1mem_data_cache_assoc
)
port map (
clk => clk,
re => c.cpu_l1mem_data_cache_ctrl_out_vram.re,
we => c.cpu_l1mem_data_cache_ctrl_out_vram.we,
raddr => c.cpu_l1mem_data_cache_dp_out_vram.raddr,
rdata => c.cpu_l1mem_data_cache_ctrl_in_vram.rdata,
waddr => c.cpu_l1mem_data_cache_dp_out_vram.waddr,
wdata => c.cpu_l1mem_data_cache_ctrl_out_vram.wdata
);
-- pragma translate_off
process (clk) is
begin
if rising_edge(clk) and rstn = '1' then
assert not is_x(c.cpu_l1mem_data_cache_ctrl_out_vram.re)
report "vram re is invalid"
severity failure;
assert not is_x(c.cpu_l1mem_data_cache_ctrl_out_vram.we)
report "vram we is invalid"
severity failure;
if c.cpu_l1mem_data_cache_ctrl_out_vram.re = '1' then
assert not is_x(c.cpu_l1mem_data_cache_dp_out_vram.raddr)
report "vram raddr is invalid"
severity failure;
end if;
if c.cpu_l1mem_data_cache_ctrl_out_vram.we = '1' then
assert not is_x(c.cpu_l1mem_data_cache_ctrl_out_vram.wdata)
report "vram wdata is invalid"
severity failure;
assert not is_x(c.cpu_l1mem_data_cache_dp_out_vram.waddr)
report "vram waddr is invalid"
severity failure;
end if;
end if;
end process;
-- pragma translate_on
mram : entity tech.syncram_1r1w(rtl)
generic map (
addr_bits => cpu_l1mem_data_cache_index_bits,
data_bits => cpu_l1mem_data_cache_assoc
)
port map (
clk => clk,
re => c.cpu_l1mem_data_cache_ctrl_out_mram.re,
we => c.cpu_l1mem_data_cache_ctrl_out_mram.we,
raddr => c.cpu_l1mem_data_cache_dp_out_mram.raddr,
rdata => c.cpu_l1mem_data_cache_ctrl_in_mram.rdata,
waddr => c.cpu_l1mem_data_cache_dp_out_mram.waddr,
wdata => c.cpu_l1mem_data_cache_ctrl_out_mram.wdata
);
-- pragma translate_off
process (clk) is
begin
if rising_edge(clk) and rstn = '1' then
assert not is_x(c.cpu_l1mem_data_cache_ctrl_out_mram.re)
report "mram re is invalid"
severity failure;
assert not is_x(c.cpu_l1mem_data_cache_ctrl_out_mram.we)
report "mram we is invalid"
severity failure;
if c.cpu_l1mem_data_cache_ctrl_out_mram.re = '1' then
assert not is_x(c.cpu_l1mem_data_cache_dp_out_mram.raddr)
report "mram raddr is invalid"
severity failure;
end if;
if c.cpu_l1mem_data_cache_ctrl_out_mram.we = '1' then
assert not is_x(c.cpu_l1mem_data_cache_ctrl_out_mram.wdata)
report "mram wdata is invalid"
severity failure;
assert not is_x(c.cpu_l1mem_data_cache_dp_out_mram.waddr)
report "mram waddr is invalid"
severity failure;
end if;
end if;
end process;
-- pragma translate_on
tram : entity tech.syncram_banked_1rw(rtl)
generic map (
addr_bits => cpu_l1mem_data_cache_index_bits,
word_bits => cpu_l1mem_data_cache_tag_bits,
log2_banks => cpu_l1mem_data_cache_log2_assoc
)
port map (
clk => clk,
en => c.cpu_l1mem_data_cache_ctrl_out_tram.en,
we => c.cpu_l1mem_data_cache_ctrl_out_tram.we,
banken => c.cpu_l1mem_data_cache_ctrl_out_tram.banken,
addr => c.cpu_l1mem_data_cache_dp_out_tram.addr,
rdata => c.cpu_l1mem_data_cache_dp_in_tram.rdata,
wdata => c.cpu_l1mem_data_cache_dp_out_tram.wdata
);
-- pragma translate_on
process (clk) is
begin
if rising_edge(clk) and rstn = '1' then
assert not is_x(c.cpu_l1mem_data_cache_ctrl_out_tram.en)
report "tram en is invalid"
severity failure;
if c.cpu_l1mem_data_cache_ctrl_out_tram.en = '1' then
assert not is_x(c.cpu_l1mem_data_cache_dp_out_tram.addr)
report "tram addr is invalid"
severity failure;
assert not is_x(c.cpu_l1mem_data_cache_ctrl_out_tram.banken)
report "tram banken is invalid"
severity failure;
assert not is_x(c.cpu_l1mem_data_cache_ctrl_out_tram.we)
report "tram we is invalid"
severity failure;
if c.cpu_l1mem_data_cache_ctrl_out_tram.we = '1' then
for n in cpu_l1mem_data_cache_assoc-1 downto 0 loop
if c.cpu_l1mem_data_cache_ctrl_out_tram.banken(n) = '1' then
assert not is_x(std_ulogic_vector2_slice2(c.cpu_l1mem_data_cache_dp_out_tram.wdata, n))
report "tram wdata " & integer'image(n) & " is invalid"
severity failure;
end if;
end loop;
end if;
end if;
end if;
end process;
-- pragma translate_on
dram : entity tech.syncram_banked_1rw(rtl)
generic map (
addr_bits => cpu_l1mem_data_cache_index_bits + cpu_l1mem_data_cache_offset_bits - cpu_log2_word_bytes,
word_bits => byte_bits,
log2_banks => cpu_l1mem_data_cache_log2_assoc + cpu_log2_word_bytes
)
port map (
clk => clk,
en => c.cpu_l1mem_data_cache_ctrl_out_dram.en,
we => c.cpu_l1mem_data_cache_ctrl_out_dram.we,
banken => c.cpu_l1mem_data_cache_dp_out_dram.banken,
addr => c.cpu_l1mem_data_cache_dp_out_dram.addr,
rdata => c.cpu_l1mem_data_cache_dp_in_dram.rdata,
wdata => c.cpu_l1mem_data_cache_dp_out_dram.wdata
);
-- pragma translate_off
process (clk) is
begin
if rising_edge(clk) and rstn = '1' then
assert not is_x(c.cpu_l1mem_data_cache_ctrl_out_dram.en)
report "dram en is invalid"
severity failure;
if c.cpu_l1mem_data_cache_ctrl_out_dram.en = '1' then
assert not is_x(c.cpu_l1mem_data_cache_dp_out_dram.addr)
report "dram addr is invalid"
severity failure;
assert not is_x(c.cpu_l1mem_data_cache_dp_out_dram.banken)
report "dram banken is invalid"
severity failure;
assert not is_x(c.cpu_l1mem_data_cache_ctrl_out_dram.we)
report "dram we is invalid"
severity failure;
--if c.cpu_l1mem_data_cache_ctrl_out_dram.we = '1' then
-- for n in cpu_l1mem_data_cache_assoc-1 downto 0 loop
-- if c.cpu_l1mem_data_cache_ctrl_out_tram.banken(n) = '1' then
-- assert not is_x(std_ulogic_vector2_slice2(c.cpu_l1mem_data_cache_dp_out_dram.wdata, n))
-- report "dram wdata " & integer'image(n) & " is invalid"
-- severity failure;
-- end if;
-- end loop;
--end if;
end if;
end if;
end process;
-- pragma translate_on
-- pragma translate_off
process (clk) is
begin
if rising_edge(clk) and rstn = '1' then
assert not is_x(sys_slave_ctrl_out.ready)
report "sys_slave_ctrl_out.ready invalid"
severity failure;
if sys_slave_ctrl_out.ready = '1' then
assert not is_x(sys_slave_ctrl_out.error)
report "sys_slave_ctrl_out.error invalid"
severity failure;
end if;
assert not is_x(c.sys_master_ctrl_out.request)
report "sys_master_ctrl_out.request invalid"
severity failure;
if c.sys_master_ctrl_out.request = '1' then
assert not is_x(c.sys_master_ctrl_out.be)
report "sys_master_ctrl_out.be invalid"
severity failure;
assert not is_x(c.sys_master_ctrl_out.write)
report "sys_master_ctrl_out.write invalid"
severity failure;
assert not is_x(c.sys_master_ctrl_out.cacheable)
report "sys_master_ctrl_out.cacheable invalid"
severity failure;
assert not is_x(c.sys_master_ctrl_out.inst)
report "sys_master_ctrl_out.inst invalid"
severity failure;
assert not is_x(c.sys_master_ctrl_out.burst)
report "sys_master_ctrl_out.burst invalid"
severity failure;
if c.sys_master_ctrl_out.burst = '1' then
assert not is_x(c.sys_master_ctrl_out.bwrap)
report "sys_master_ctrl_out.bwrap invalid"
severity failure;
assert not is_x(c.sys_master_ctrl_out.bcycles)
report "sys_master_ctrl_out.bcycles invalid"
severity failure;
end if;
assert not is_x(c.sys_master_dp_out.paddr)
report "sys_master_dp_out.paddr invalid"
severity failure;
assert not is_x(c.sys_master_dp_out.size)
report "sys_master_dp_out.size invalid"
severity failure;
end if;
end if;
end process;
-- pragma translate_on
end;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.all;
use work.procedures.all;
entity complex_alu is
port(
clk : in std_logic;
a : in t_data;
b : in t_data;
op : in std_logic_vector(2 downto 0);
point : in std_logic_vector(2 downto 0);
c : out t_data
);
end complex_alu;
architecture Structural of complex_alu is
signal imm_c : t_data;
signal umul_c : t_data;
signal smul_c : t_data;
signal umul : std_logic_vector(t_data'high*2+1 downto 0);
signal smul : std_logic_vector(t_data'high*2+1 downto 0);
signal umulshift : std_logic_vector(t_data'high*2+1 downto 0);
signal smulshift : std_logic_vector(t_data'high*2+1 downto 0);
signal point_1 : std_logic_vector(2 downto 0);
signal op_1 : std_logic_vector(2 downto 0);
signal umul_p : unsigned(0 downto 0);
signal smul_p : unsigned(0 downto 0);
begin
p: process(clk)
begin
if rising_edge(clk) then
point_1 <= point;
op_1 <= op;
end if;
end process p;
ashift: entity work.shift_ra
port map(
a => smul,
b => point_1,
c => smulshift
);
lshift: entity work.shift_rl
port map(
a => umul,
b => point_1,
c => umulshift
);
umul_p(0) <= umul(6) when point_1 = "111" else
umul(5) when point_1 = "110" else
umul(4) when point_1 = "101" else
umul(3) when point_1 = "100" else
umul(2) when point_1 = "011" else
umul(1) when point_1 = "010" else
umul(0) when point_1 = "001" else
'0';
smul_p(0) <= smul(6) when point_1 = "111" else
smul(5) when point_1 = "110" else
smul(4) when point_1 = "101" else
smul(3) when point_1 = "100" else
smul(2) when point_1 = "011" else
smul(1) when point_1 = "010" else
smul(0) when point_1 = "001" else
'0';
umul_c <= std_logic_vector(unsigned(umulshift(t_data'range)) + umul_p);
smul_c <= std_logic_vector(unsigned(smulshift(t_data'range)) + smul_p);
alu: process(clk)
begin
if rising_edge(clk) then
umul <= std_logic_vector(unsigned(a) * unsigned(b));
smul <= std_logic_vector(signed(a) * signed(b));
case op is
when CALU_ADD =>
imm_c <= std_logic_vector(unsigned(a) + unsigned(b));
when CALU_SUB =>
imm_c <= std_logic_vector(unsigned(a) - unsigned(b));
when CALU_AND =>
imm_c <= a and b;
when CALU_OR =>
imm_c <= a or b;
when CALU_XOR =>
imm_c <= a xor b;
when others =>
imm_c <= (others => '0');
end case;
case op_1 is
when CALU_ADD | CALU_SUB | CALU_AND | CALU_OR | CALU_XOR =>
c <= imm_c;
when CALU_UMUL =>
c <= umul_c;
when CALU_SMUL =>
c <= smul_c;
when others =>
c <= (others => '0');
end case;
end if;
end process alu;
end Structural;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity datapath is
port (
input : in std_logic_vector(1 downto 0);
clk : in std_logic;
output : out std_logic_vector(2 downto 0)
);
end datapath;
architecture behave of datapath is
component state_machine
port(
input: in std_logic;
reset: in std_logic;
state : out std_logic_vector(2 downto 0);
clk : in std_logic
);
end component;
signal stin: std_logic := '0';
signal streset: std_logic := '1';
begin -- behave
st: state_machine port map (
input => stin,
reset => streset,
clk => clk,
state => output);
streset <= input(1);
stin <= input(0);
end behave;
|
--
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity comm_fpga_epp is
port(
clk_in : in std_logic; -- clock input (asynchronous with EPP signals)
reset_in : in std_logic; -- synchronous active-high reset input
reset_out : out std_logic; -- synchronous active-high reset output
-- EPP interface -----------------------------------------------------------------------------
eppData_io : inout std_logic_vector(7 downto 0); -- bidirectional 8-bit data bus
eppAddrStb_in : in std_logic; -- active-low asynchronous address strobe
eppDataStb_in : in std_logic; -- active-low asynchronous data strobe
eppWrite_in : in std_logic; -- read='1'; write='0'
eppWait_out : out std_logic; -- active-low asynchronous wait signal
-- Channel read/write interface --------------------------------------------------------------
chanAddr_out : out std_logic_vector(6 downto 0); -- the selected channel (0-127)
-- Host >> FPGA pipe:
h2fData_out : out std_logic_vector(7 downto 0); -- data lines used when the host writes to a channel
h2fValid_out : out std_logic; -- '1' means "on the next clock rising edge, please accept the data on h2fData_out"
h2fReady_in : in std_logic; -- channel logic can drive this low to say "I'm not ready for more data yet"
-- Host << FPGA pipe:
f2hData_in : in std_logic_vector(7 downto 0); -- data lines used when the host reads from a channel
f2hValid_in : in std_logic; -- channel logic can drive this low to say "I don't have data ready for you"
f2hReady_out : out std_logic -- '1' means "on the next clock rising edge, put your next byte of data on f2hData_in"
);
end entity;
architecture rtl of comm_fpga_epp is
type StateType is (
S_RESET,
S_IDLE,
S_ADDR_WRITE_WAIT,
S_DATA_WRITE_EXEC,
S_DATA_WRITE_WAIT,
S_DATA_READ_EXEC,
S_DATA_READ_WAIT
);
-- State and next-state
signal state : StateType := S_RESET;
signal state_next : StateType;
-- Synchronised versions of asynchronous inputs
signal eppAddrStb_sync : std_logic := '1';
signal eppDataStb_sync : std_logic := '1';
signal eppWrite_sync : std_logic := '1';
-- Registers
signal eppWait : std_logic := '1';
signal eppWait_next : std_logic;
signal chanAddr : std_logic_vector(6 downto 0) := (others => '0');
signal chanAddr_next : std_logic_vector(6 downto 0);
signal eppData : std_logic_vector(7 downto 0) := (others => '0');
signal eppData_next : std_logic_vector(7 downto 0);
-- Other signals
signal driveBus : std_logic := '0'; -- whether or not to drive eppData_io
begin
-- Infer registers
process(clk_in)
begin
if ( rising_edge(clk_in) ) then
if ( reset_in = '1' ) then
state <= S_RESET;
chanAddr <= (others => '0');
eppData <= (others => '0');
eppWait <= '1';
eppAddrStb_sync <= '1';
eppDataStb_sync <= '1';
eppWrite_sync <= '1';
else
state <= state_next;
chanAddr <= chanAddr_next;
eppData <= eppData_next;
eppWait <= eppWait_next;
eppAddrStb_sync <= eppAddrStb_in;
eppDataStb_sync <= eppDataStb_in;
eppWrite_sync <= eppWrite_in;
end if;
end if;
end process;
-- Next state logic
process(
state, eppData_io, eppAddrStb_sync, eppDataStb_sync, eppWrite_sync, chanAddr, eppWait, eppData,
f2hData_in, f2hValid_in, h2fReady_in)
begin
state_next <= state;
chanAddr_next <= chanAddr;
eppWait_next <= eppWait;
eppData_next <= eppData;
h2fData_out <= (others => '0');
f2hReady_out <= '0';
h2fValid_out <= '0';
reset_out <= '0';
driveBus <= eppWrite_sync;
case state is
-- Finish the address update cycle
when S_ADDR_WRITE_WAIT =>
if ( eppAddrStb_sync = '1' ) then
eppWait_next <= '0';
state_next <= S_IDLE;
end if;
-- Host writes a byte to the FPGA
when S_DATA_WRITE_EXEC =>
h2fData_out <= eppData_io;
h2fValid_out <= '1';
if ( h2fReady_in = '1') then
eppWait_next <= '1';
state_next <= S_DATA_WRITE_WAIT;
end if;
when S_DATA_WRITE_WAIT =>
if ( eppDataStb_sync = '1' ) then
eppWait_next <= '0';
state_next <= S_IDLE;
end if;
-- Host reads a byte from the FPGA
when S_DATA_READ_EXEC =>
eppData_next <= f2hData_in;
f2hReady_out <= '1';
if ( f2hValid_in = '1' ) then
eppWait_next <= '1';
state_next <= S_DATA_READ_WAIT;
end if;
when S_DATA_READ_WAIT =>
if ( eppDataStb_sync = '1' ) then
eppWait_next <= '0';
state_next <= S_IDLE;
end if;
-- S_RESET - tri-state everything
when S_RESET =>
reset_out <= '1';
driveBus <= '0';
if ( eppWrite_sync = '0' ) then
state_next <= S_IDLE;
end if;
-- S_IDLE and others
when others =>
eppWait_next <= '0';
if ( eppAddrStb_sync = '0' ) then
-- Address can only be written, not read
if ( eppWrite_sync = '0' ) then
eppWait_next <= '1';
chanAddr_next <= eppData_io(6 downto 0);
state_next <= S_ADDR_WRITE_WAIT;
end if;
elsif ( eppDataStb_sync = '0' ) then
-- Register read or write
if ( eppWrite_sync = '0' ) then
state_next <= S_DATA_WRITE_EXEC;
else
state_next <= S_DATA_READ_EXEC;
end if;
end if;
end case;
end process;
-- Drive stateless signals
chanAddr_out <= chanAddr;
eppWait_out <= eppWait;
eppData_io <=
eppData when ( driveBus = '1' ) else
"ZZZZZZZZ";
end architecture;
|
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12384)
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12384)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12384)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12384)
`protect data_block
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`protect end_protected
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:40:13 07/21/2014
-- Design Name:
-- Module Name: aes_module_cu - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.types.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity aes_module_cu is
port (clk : in std_logic;
reset : in std_logic;
x_start : in std_logic;
x_mode : in aes_mode;
x_end_enc : in std_logic;
x_end_dec : in std_logic;
x_end_exp : in std_logic;
y_end : out std_logic;
y_done : out std_logic;
y_start_enc : out std_logic;
y_start_dec : out std_logic;
y_start_exp : out std_logic;
y_mux_ctrl : out aes_mode
);
end aes_module_cu;
architecture Behavioral of aes_module_cu is
type States is (S_READY, S_ENC, S_DEC, S_EXP, S_DONE);
signal S, S_next : States;
begin
delta : process (S, x_start, x_mode, x_end_enc, x_end_dec, x_end_exp)
begin
case S is
when S_READY => y_done <= '0';
y_end <= '0';
y_start_enc <= '0';
y_start_dec <= '0';
y_start_exp <= '0';
if x_start = '1' then
case x_mode is
when ENCRYPT => y_start_enc <= '1';
S_next <= S_ENC;
when DECRYPT => y_start_dec <= '1';
S_next <= S_DEC;
when EXPAND_KEY => y_start_exp <= '1';
S_next <= S_EXP;
when others => S_next <= S_READY;
end case;
else
S_next <= S_READY;
end if;
when S_ENC => y_done <= '0';
y_end <= '0';
y_start_enc <= '0';
y_start_dec <= '0';
y_start_exp <= '0';
y_mux_ctrl <= ENCRYPT;
if x_end_enc = '1' then
y_end <= '1';
S_next <= S_DONE;
else
S_next <= S_ENC;
end if;
when S_DEC => y_done <= '0';
y_end <= '0';
y_start_enc <= '0';
y_start_dec <= '0';
y_start_exp <= '0';
y_mux_ctrl <= DECRYPT;
if x_end_dec = '1' then
y_end <= '1';
S_next <= S_DONE;
else
S_next <= S_DEC;
end if;
when S_EXP => y_done <= '0';
y_end <= '0';
y_start_enc <= '0';
y_start_dec <= '0';
y_start_exp <= '0';
if x_end_exp = '1' then
y_end <= '1';
S_next <= S_DONE;
else
S_next <= S_EXP;
end if;
when S_DONE => y_done <= '1';
y_end <= '0';
y_start_enc <= '0';
y_start_dec <= '0';
y_start_exp <= '0';
if x_start = '1' then
case x_mode is
when ENCRYPT => y_start_enc <= '1';
S_next <= S_ENC;
when DECRYPT => y_start_dec <= '1';
S_next <= S_DEC;
when EXPAND_KEY => y_start_exp <= '1';
S_next <= S_EXP;
when others => S_next <= S_DONE;
end case;
else
S_next <= S_DONE;
end if;
end case;
end process delta;
feedback_loop : process (clk, reset, S_next)
begin
if reset = '1' then
S <= S_READY;
elsif rising_edge(clk) then
S <= S_next;
end if;
end process feedback_loop;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
package apkg is
component acomp is
port (x: in std_ulogic; y: out std_ulogic);
end component;
end apkg;
|
library ieee;
use ieee.std_logic_1164.all;
package apkg is
component acomp is
port (x: in std_ulogic; y: out std_ulogic);
end component;
end apkg;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;
--openMixR top level design
--Copyright (C) 2017 David Shah
--Licensed under the MIT License
entity ov13850_demo is
Port (
--Core signals
clock_p : in std_logic;
clock_n : in std_logic;
aux_clock_p : in std_logic;
aux_clock_n : in std_logic;
--User interface
btn_miso : in std_logic;
btn_clk : out std_logic;
btn_ld_n : out std_logic;
rgb_led : out std_logic_vector(2 downto 0);
imu_mosi : out std_logic;
imu_miso : in std_logic;
imu_sclk : out std_logic;
imu_cs_n : out std_logic;
imu_fsync : out std_logic;
--FTDI interface
ftdi_data : inout std_logic_vector(7 downto 0);
ftdi_rd_n : out std_logic;
ftdi_wr_n : out std_logic;
ftdi_siwu_n : out std_logic;
ftdi_rxf_n : in std_logic;
ftdi_txf_n : in std_logic;
--USB-C and DP interface
ccg_io0 : inout std_logic;
ccg_io1 : inout std_logic;
dp_aux_p : inout std_logic;
dp_aux_n : inout std_logic;
dp_hpd : inout std_logic;
dprt_en : out std_logic;
dprt_sda : inout std_logic;
dprt_scl : inout std_logic;
--Camera CSI port
csi0_clk : in std_logic_vector(1 downto 0);
csi0_d0 : in std_logic_vector(1 downto 0);
csi0_d1 : in std_logic_vector(1 downto 0);
csi0_d2 : in std_logic_vector(1 downto 0);
csi0_d3 : in std_logic_vector(1 downto 0);
csi1_clk : in std_logic_vector(1 downto 0);
csi1_d0 : in std_logic_vector(1 downto 0);
csi1_d1 : in std_logic_vector(1 downto 0);
csi1_d2 : in std_logic_vector(1 downto 0);
csi1_d3 : in std_logic_vector(1 downto 0);
--Camera control port
cam0_mclk : out std_logic;
cam_rstn : out std_logic;
cam0_i2c_sda : inout std_logic;
cam0_i2c_sck : inout std_logic;
cam0_led : out std_logic;
cam0_gpio : inout std_logic;
cam1_mclk : out std_logic;
cam1_i2c_sda : inout std_logic;
cam1_i2c_sck : inout std_logic;
cam1_led : out std_logic;
cam1_gpio : inout std_logic;
--LCD control interface
vddd_en : out std_logic;
vdda_en : out std_logic;
lcd_reset_b : out std_logic;
bl_pwm_b : out std_logic;
lcd_te : in std_logic;
lcd_id : in std_logic_vector(3 downto 0);
lcd_gpio : inout std_logic_vector(2 downto 0);
lcd_psu_sda : inout std_logic_vector;
lcd_psu_scl : inout std_logic_vector;
--DSI port 0 (master, left)
dphy0_hs_clk : inout STD_LOGIC_VECTOR (1 downto 0); --DSI lanes; hs is high speed and lp is low power for resistor network
dphy0_lp_clk : inout STD_LOGIC_VECTOR (1 downto 0); -- In each case 1 is P and 0 is N
dphy0_hs_d0 : inout STD_LOGIC_VECTOR (1 downto 0);
dphy0_lp_d0 : inout STD_LOGIC_VECTOR (1 downto 0);
dphy0_hs_d1 : inout STD_LOGIC_VECTOR (1 downto 0);
dphy0_lp_d1 : inout STD_LOGIC_VECTOR (1 downto 0);
dphy0_hs_d2 : inout STD_LOGIC_VECTOR (1 downto 0);
dphy0_lp_d2 : inout STD_LOGIC_VECTOR (1 downto 0);
dphy0_hs_d3 : inout STD_LOGIC_VECTOR (1 downto 0);
dphy0_lp_d3 : inout STD_LOGIC_VECTOR (1 downto 0);
--DSI port 1 (slave, right)
dphy1_hs_clk : inout STD_LOGIC_VECTOR (1 downto 0); --DSI lanes; hs is high speed and lp is low power for resistor network
dphy1_lp_clk : inout STD_LOGIC_VECTOR (1 downto 0); -- In each case 1 is P and 0 is N
dphy1_hs_d0 : inout STD_LOGIC_VECTOR (1 downto 0);
dphy1_lp_d0 : inout STD_LOGIC_VECTOR (1 downto 0);
dphy1_hs_d1 : inout STD_LOGIC_VECTOR (1 downto 0);
dphy1_lp_d1 : inout STD_LOGIC_VECTOR (1 downto 0);
dphy1_hs_d2 : inout STD_LOGIC_VECTOR (1 downto 0);
dphy1_lp_d2 : inout STD_LOGIC_VECTOR (1 downto 0);
dphy1_hs_d3 : inout STD_LOGIC_VECTOR (1 downto 0);
dphy1_lp_d3 : inout STD_LOGIC_VECTOR (1 downto 0);
--A64 control interface
a64_boot_ctl : out std_logic;
a64_reset_ctl : out std_logic;
a64_fpga_oe : in std_logic;
a64_mosi : in std_logic;
a64_miso : inout std_logic;
a64_sck : in std_logic;
a64_csn : in std_logic;
a64_io0 : inout std_logic;
--A64 vLCD interface
a64_lcd_pixclk : in std_logic;
a64_lcd_data : in std_logic_vector(17 downto 0);
a64_lcd_hsync : in std_logic;
a64_lcd_vsync : in std_logic;
a64_lcd_den : in std_logic;
--A64 vCamera interface
a64_cam_pixclk : inout std_logic;
a64_cam_mclk : in std_logic;
a64_cam_data : inout std_logic_vector(7 downto 0);
a64_cam_vsync : inout std_logic;
a64_cam_hsync : inout std_logic;
--DDR3 interface
ddr3_addr : out std_logic_vector(14 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_cas_n : out std_logic;
ddr3_ck_n : out std_logic_vector(0 downto 0);
ddr3_ck_p : out std_logic_vector(0 downto 0);
ddr3_cke : out std_logic_vector(0 downto 0);
ddr3_ras_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_we_n : out std_logic;
ddr3_dq : inout std_logic_vector(31 downto 0);
ddr3_dqs_n : inout std_logic_vector(3 downto 0);
ddr3_dqs_p : inout std_logic_vector(3 downto 0);
ddr3_cs_n : out std_logic_vector(0 downto 0);
ddr3_dm : out std_logic_vector(3 downto 0);
ddr3_odt : out std_logic_vector(0 downto 0)
);
end ov13850_demo;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_afifo_autord.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- asynchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_fifo_v1_0_4;
use lib_fifo_v1_0_4.async_fifo_fg;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity axi_sg_afifo_autord is
generic (
C_DWIDTH : integer := 32;
C_DEPTH : integer := 16;
C_CNT_WIDTH : Integer := 5;
C_USE_BLKMEM : Integer := 0 ;
C_USE_AUTORD : Integer := 1;
C_FAMILY : String := "virtex7"
);
port (
-- Inputs
AFIFO_Ainit : In std_logic; --
AFIFO_Wr_clk : In std_logic; --
AFIFO_Wr_en : In std_logic; --
AFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Rd_clk : In std_logic; --
AFIFO_Rd_en : In std_logic; --
AFIFO_Clr_Rd_Data_Valid : In std_logic; --
--
-- Outputs --
AFIFO_DValid : Out std_logic; --
AFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Full : Out std_logic; --
AFIFO_Empty : Out std_logic; --
AFIFO_Almost_full : Out std_logic; --
AFIFO_Almost_empty : Out std_logic; --
AFIFO_Wr_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Rd_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Corr_Rd_count : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Corr_Rd_count_minus1 : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Rd_ack : Out std_logic --
);
end entity axi_sg_afifo_autord;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_sg_afifo_autord is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- Constant declarations
-- Signal declarations
signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal wr_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_int : integer range 0 to C_DEPTH+1 := 0;
signal rd_count_int_corr : integer range 0 to C_DEPTH+1 := 0;
signal rd_count_int_corr_minus1 : integer range 0 to C_DEPTH+1 := 0;
Signal corrected_empty : std_logic := '0';
Signal corrected_almost_empty : std_logic := '0';
Signal sig_afifo_empty : std_logic := '0';
Signal sig_afifo_almost_empty : std_logic := '0';
-- backend fifo read ack sample and hold
Signal sig_rddata_valid : std_logic := '0';
Signal hold_ff_q : std_logic := '0';
Signal ored_ack_ff_reset : std_logic := '0';
Signal autoread : std_logic := '0';
Signal sig_wrfifo_rdack : std_logic := '0';
Signal fifo_read_enable : std_logic := '0';
Signal first_write : std_logic := '0';
Signal first_read : std_logic := '0';
Signal first_read1 : std_logic := '0';
-- Component declarations
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-- Bit ordering translations
write_data_lil_end <= AFIFO_Din; -- translate from Big Endian to little
-- endian.
AFIFO_Rd_ack <= sig_wrfifo_rdack;
AFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to
-- Big endian.
AFIFO_Almost_empty <= corrected_almost_empty;
GEN_EMPTY : if (C_USE_AUTORD = 1) generate
begin
AFIFO_Empty <= corrected_empty;
end generate GEN_EMPTY;
GEN_EMPTY1 : if (C_USE_AUTORD = 0) generate
begin
AFIFO_Empty <= sig_afifo_empty;
end generate GEN_EMPTY1;
AFIFO_Wr_count <= wr_count_lil_end;
AFIFO_Rd_count <= rd_count_lil_end;
AFIFO_Corr_Rd_count <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr,
C_CNT_WIDTH+1);
AFIFO_Corr_Rd_count_minus1 <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr_minus1,
C_CNT_WIDTH+1);
AFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator
fifo_read_enable <= AFIFO_Rd_en or autoread;
-------------------------------------------------------------------------------
-- Instantiate the CoreGen FIFO
--
-- NOTE:
-- This instance refers to a wrapper file that interm will use the
-- CoreGen FIFO Generator Async FIFO utility.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0_4.async_fifo_fg
generic map (
-- C_ALLOW_2N_DEPTH => 1,
C_ALLOW_2N_DEPTH => 0,
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DWIDTH,
C_ENABLE_RLOCS => 0,
C_FIFO_DEPTH => C_DEPTH,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_COUNT => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_COUNT => 1,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_COUNT_WIDTH => C_CNT_WIDTH,
C_RD_ERR_LOW => 0,
C_USE_BLOCKMEM => C_USE_BLKMEM,
C_WR_ACK_LOW => 0,
C_WR_COUNT_WIDTH => C_CNT_WIDTH,
C_WR_ERR_LOW => 0
-- C_USE_EMBEDDED_REG => 1, -- 0 ;
-- C_PRELOAD_REGS => 0, -- 0 ;
-- C_PRELOAD_LATENCY => 1 -- 1 ;
)
port Map (
Din => write_data_lil_end,
Wr_en => AFIFO_Wr_en,
Wr_clk => AFIFO_Wr_clk,
Rd_en => fifo_read_enable,
Rd_clk => AFIFO_Rd_clk,
Ainit => AFIFO_Ainit,
Dout => read_data_lil_end,
Full => AFIFO_Full,
Empty => sig_afifo_empty,
Almost_full => AFIFO_Almost_full,
Almost_empty => sig_afifo_almost_empty,
Wr_count => wr_count_lil_end,
Rd_count => rd_count_lil_end,
Rd_ack => sig_wrfifo_rdack,
Rd_err => open, -- Not used by axi_dma
Wr_ack => open, -- Not used by axi_dma
Wr_err => open -- Not used by axi_dma
);
----------------------------------------------------------------------------
-- Read Ack assert & hold logic (needed because:
-- 1) The Async FIFO has to be read once to get valid
-- data to the read data port (data is discarded).
-- 2) The Read ack from the fifo is only asserted for 1 clock.
-- 3) A signal is needed that indicates valid data is at the read
-- port of the FIFO and has not yet been read. This signal needs
-- to be held until the next read operation occurs or a clear
-- signal is received.
ored_ack_ff_reset <= fifo_read_enable or
AFIFO_Ainit or
AFIFO_Clr_Rd_Data_Valid;
sig_rddata_valid <= hold_ff_q or
sig_wrfifo_rdack;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ACK_HOLD_FLOP
--
-- Process Description:
-- Flop for registering the hold flag
--
-------------------------------------------------------------
IMP_ACK_HOLD_FLOP : process (AFIFO_Rd_clk)
begin
if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
if (ored_ack_ff_reset = '1') then
hold_ff_q <= '0';
else
hold_ff_q <= sig_rddata_valid;
end if;
end if;
end process IMP_ACK_HOLD_FLOP;
-- I_ACK_HOLD_FF : FDRE
-- port map(
-- Q => hold_ff_q,
-- C => AFIFO_Rd_clk,
-- CE => '1',
-- D => sig_rddata_valid,
-- R => ored_ack_ff_reset
-- );
-- generate auto-read enable. This keeps fresh data at the output
-- of the FIFO whenever it is available.
GEN_AUTORD1 : if C_USE_AUTORD = 1 generate
autoread <= '1' -- create a read strobe when the
when (sig_rddata_valid = '0' and -- output data is NOT valid
sig_afifo_empty = '0') -- and the FIFO is not empty
Else '0';
end generate GEN_AUTORD1;
GEN_AUTORD2 : if C_USE_AUTORD = 0 generate
process (AFIFO_Wr_clk, AFIFO_Ainit)
begin
if (AFIFO_Ainit = '0') then
first_write <= '0';
elsif (AFIFO_Wr_clk'event and AFIFO_Wr_clk = '1') then
if (AFIFO_Wr_en = '1') then
first_write <= '1';
end if;
end if;
end process;
process (AFIFO_Rd_clk, AFIFO_Ainit)
begin
if (AFIFO_Ainit = '0') then
first_read <= '0';
first_read1 <= '0';
elsif (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
if (sig_afifo_empty = '0') then
first_read <= first_write;
first_read1 <= first_read;
end if;
end if;
end process;
autoread <= first_read xor first_read1;
end generate GEN_AUTORD2;
rd_count_int <= CONV_INTEGER(rd_count_lil_end);
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function.
--
-------------------------------------------------------------
CORRECT_RD_CNT : process (sig_rddata_valid,
sig_afifo_empty,
sig_afifo_almost_empty,
rd_count_int)
begin
if (sig_rddata_valid = '0') then
rd_count_int_corr <= 0;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '1';
corrected_almost_empty <= '0';
elsif (sig_afifo_empty = '1') then -- rddata valid and fifo empty
rd_count_int_corr <= 1;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '0';
corrected_almost_empty <= '1';
Elsif (sig_afifo_almost_empty = '1') Then -- rddata valid and fifo almost empty
rd_count_int_corr <= 2;
rd_count_int_corr_minus1 <= 1;
corrected_empty <= '0';
corrected_almost_empty <= '0';
else -- rddata valid and modify rd count from FIFO
rd_count_int_corr <= rd_count_int+1;
rd_count_int_corr_minus1 <= rd_count_int;
corrected_empty <= '0';
corrected_almost_empty <= '0';
end if;
end process CORRECT_RD_CNT;
end imp;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_afifo_autord.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- asynchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_fifo_v1_0_4;
use lib_fifo_v1_0_4.async_fifo_fg;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity axi_sg_afifo_autord is
generic (
C_DWIDTH : integer := 32;
C_DEPTH : integer := 16;
C_CNT_WIDTH : Integer := 5;
C_USE_BLKMEM : Integer := 0 ;
C_USE_AUTORD : Integer := 1;
C_FAMILY : String := "virtex7"
);
port (
-- Inputs
AFIFO_Ainit : In std_logic; --
AFIFO_Wr_clk : In std_logic; --
AFIFO_Wr_en : In std_logic; --
AFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Rd_clk : In std_logic; --
AFIFO_Rd_en : In std_logic; --
AFIFO_Clr_Rd_Data_Valid : In std_logic; --
--
-- Outputs --
AFIFO_DValid : Out std_logic; --
AFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Full : Out std_logic; --
AFIFO_Empty : Out std_logic; --
AFIFO_Almost_full : Out std_logic; --
AFIFO_Almost_empty : Out std_logic; --
AFIFO_Wr_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Rd_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Corr_Rd_count : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Corr_Rd_count_minus1 : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Rd_ack : Out std_logic --
);
end entity axi_sg_afifo_autord;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_sg_afifo_autord is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- Constant declarations
-- Signal declarations
signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal wr_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_int : integer range 0 to C_DEPTH+1 := 0;
signal rd_count_int_corr : integer range 0 to C_DEPTH+1 := 0;
signal rd_count_int_corr_minus1 : integer range 0 to C_DEPTH+1 := 0;
Signal corrected_empty : std_logic := '0';
Signal corrected_almost_empty : std_logic := '0';
Signal sig_afifo_empty : std_logic := '0';
Signal sig_afifo_almost_empty : std_logic := '0';
-- backend fifo read ack sample and hold
Signal sig_rddata_valid : std_logic := '0';
Signal hold_ff_q : std_logic := '0';
Signal ored_ack_ff_reset : std_logic := '0';
Signal autoread : std_logic := '0';
Signal sig_wrfifo_rdack : std_logic := '0';
Signal fifo_read_enable : std_logic := '0';
Signal first_write : std_logic := '0';
Signal first_read : std_logic := '0';
Signal first_read1 : std_logic := '0';
-- Component declarations
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-- Bit ordering translations
write_data_lil_end <= AFIFO_Din; -- translate from Big Endian to little
-- endian.
AFIFO_Rd_ack <= sig_wrfifo_rdack;
AFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to
-- Big endian.
AFIFO_Almost_empty <= corrected_almost_empty;
GEN_EMPTY : if (C_USE_AUTORD = 1) generate
begin
AFIFO_Empty <= corrected_empty;
end generate GEN_EMPTY;
GEN_EMPTY1 : if (C_USE_AUTORD = 0) generate
begin
AFIFO_Empty <= sig_afifo_empty;
end generate GEN_EMPTY1;
AFIFO_Wr_count <= wr_count_lil_end;
AFIFO_Rd_count <= rd_count_lil_end;
AFIFO_Corr_Rd_count <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr,
C_CNT_WIDTH+1);
AFIFO_Corr_Rd_count_minus1 <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr_minus1,
C_CNT_WIDTH+1);
AFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator
fifo_read_enable <= AFIFO_Rd_en or autoread;
-------------------------------------------------------------------------------
-- Instantiate the CoreGen FIFO
--
-- NOTE:
-- This instance refers to a wrapper file that interm will use the
-- CoreGen FIFO Generator Async FIFO utility.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0_4.async_fifo_fg
generic map (
-- C_ALLOW_2N_DEPTH => 1,
C_ALLOW_2N_DEPTH => 0,
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DWIDTH,
C_ENABLE_RLOCS => 0,
C_FIFO_DEPTH => C_DEPTH,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_COUNT => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_COUNT => 1,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_COUNT_WIDTH => C_CNT_WIDTH,
C_RD_ERR_LOW => 0,
C_USE_BLOCKMEM => C_USE_BLKMEM,
C_WR_ACK_LOW => 0,
C_WR_COUNT_WIDTH => C_CNT_WIDTH,
C_WR_ERR_LOW => 0
-- C_USE_EMBEDDED_REG => 1, -- 0 ;
-- C_PRELOAD_REGS => 0, -- 0 ;
-- C_PRELOAD_LATENCY => 1 -- 1 ;
)
port Map (
Din => write_data_lil_end,
Wr_en => AFIFO_Wr_en,
Wr_clk => AFIFO_Wr_clk,
Rd_en => fifo_read_enable,
Rd_clk => AFIFO_Rd_clk,
Ainit => AFIFO_Ainit,
Dout => read_data_lil_end,
Full => AFIFO_Full,
Empty => sig_afifo_empty,
Almost_full => AFIFO_Almost_full,
Almost_empty => sig_afifo_almost_empty,
Wr_count => wr_count_lil_end,
Rd_count => rd_count_lil_end,
Rd_ack => sig_wrfifo_rdack,
Rd_err => open, -- Not used by axi_dma
Wr_ack => open, -- Not used by axi_dma
Wr_err => open -- Not used by axi_dma
);
----------------------------------------------------------------------------
-- Read Ack assert & hold logic (needed because:
-- 1) The Async FIFO has to be read once to get valid
-- data to the read data port (data is discarded).
-- 2) The Read ack from the fifo is only asserted for 1 clock.
-- 3) A signal is needed that indicates valid data is at the read
-- port of the FIFO and has not yet been read. This signal needs
-- to be held until the next read operation occurs or a clear
-- signal is received.
ored_ack_ff_reset <= fifo_read_enable or
AFIFO_Ainit or
AFIFO_Clr_Rd_Data_Valid;
sig_rddata_valid <= hold_ff_q or
sig_wrfifo_rdack;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ACK_HOLD_FLOP
--
-- Process Description:
-- Flop for registering the hold flag
--
-------------------------------------------------------------
IMP_ACK_HOLD_FLOP : process (AFIFO_Rd_clk)
begin
if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
if (ored_ack_ff_reset = '1') then
hold_ff_q <= '0';
else
hold_ff_q <= sig_rddata_valid;
end if;
end if;
end process IMP_ACK_HOLD_FLOP;
-- I_ACK_HOLD_FF : FDRE
-- port map(
-- Q => hold_ff_q,
-- C => AFIFO_Rd_clk,
-- CE => '1',
-- D => sig_rddata_valid,
-- R => ored_ack_ff_reset
-- );
-- generate auto-read enable. This keeps fresh data at the output
-- of the FIFO whenever it is available.
GEN_AUTORD1 : if C_USE_AUTORD = 1 generate
autoread <= '1' -- create a read strobe when the
when (sig_rddata_valid = '0' and -- output data is NOT valid
sig_afifo_empty = '0') -- and the FIFO is not empty
Else '0';
end generate GEN_AUTORD1;
GEN_AUTORD2 : if C_USE_AUTORD = 0 generate
process (AFIFO_Wr_clk, AFIFO_Ainit)
begin
if (AFIFO_Ainit = '0') then
first_write <= '0';
elsif (AFIFO_Wr_clk'event and AFIFO_Wr_clk = '1') then
if (AFIFO_Wr_en = '1') then
first_write <= '1';
end if;
end if;
end process;
process (AFIFO_Rd_clk, AFIFO_Ainit)
begin
if (AFIFO_Ainit = '0') then
first_read <= '0';
first_read1 <= '0';
elsif (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
if (sig_afifo_empty = '0') then
first_read <= first_write;
first_read1 <= first_read;
end if;
end if;
end process;
autoread <= first_read xor first_read1;
end generate GEN_AUTORD2;
rd_count_int <= CONV_INTEGER(rd_count_lil_end);
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function.
--
-------------------------------------------------------------
CORRECT_RD_CNT : process (sig_rddata_valid,
sig_afifo_empty,
sig_afifo_almost_empty,
rd_count_int)
begin
if (sig_rddata_valid = '0') then
rd_count_int_corr <= 0;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '1';
corrected_almost_empty <= '0';
elsif (sig_afifo_empty = '1') then -- rddata valid and fifo empty
rd_count_int_corr <= 1;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '0';
corrected_almost_empty <= '1';
Elsif (sig_afifo_almost_empty = '1') Then -- rddata valid and fifo almost empty
rd_count_int_corr <= 2;
rd_count_int_corr_minus1 <= 1;
corrected_empty <= '0';
corrected_almost_empty <= '0';
else -- rddata valid and modify rd count from FIFO
rd_count_int_corr <= rd_count_int+1;
rd_count_int_corr_minus1 <= rd_count_int;
corrected_empty <= '0';
corrected_almost_empty <= '0';
end if;
end process CORRECT_RD_CNT;
end imp;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_afifo_autord.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- asynchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_fifo_v1_0_4;
use lib_fifo_v1_0_4.async_fifo_fg;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity axi_sg_afifo_autord is
generic (
C_DWIDTH : integer := 32;
C_DEPTH : integer := 16;
C_CNT_WIDTH : Integer := 5;
C_USE_BLKMEM : Integer := 0 ;
C_USE_AUTORD : Integer := 1;
C_FAMILY : String := "virtex7"
);
port (
-- Inputs
AFIFO_Ainit : In std_logic; --
AFIFO_Wr_clk : In std_logic; --
AFIFO_Wr_en : In std_logic; --
AFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Rd_clk : In std_logic; --
AFIFO_Rd_en : In std_logic; --
AFIFO_Clr_Rd_Data_Valid : In std_logic; --
--
-- Outputs --
AFIFO_DValid : Out std_logic; --
AFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Full : Out std_logic; --
AFIFO_Empty : Out std_logic; --
AFIFO_Almost_full : Out std_logic; --
AFIFO_Almost_empty : Out std_logic; --
AFIFO_Wr_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Rd_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Corr_Rd_count : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Corr_Rd_count_minus1 : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Rd_ack : Out std_logic --
);
end entity axi_sg_afifo_autord;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_sg_afifo_autord is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- Constant declarations
-- Signal declarations
signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal wr_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_int : integer range 0 to C_DEPTH+1 := 0;
signal rd_count_int_corr : integer range 0 to C_DEPTH+1 := 0;
signal rd_count_int_corr_minus1 : integer range 0 to C_DEPTH+1 := 0;
Signal corrected_empty : std_logic := '0';
Signal corrected_almost_empty : std_logic := '0';
Signal sig_afifo_empty : std_logic := '0';
Signal sig_afifo_almost_empty : std_logic := '0';
-- backend fifo read ack sample and hold
Signal sig_rddata_valid : std_logic := '0';
Signal hold_ff_q : std_logic := '0';
Signal ored_ack_ff_reset : std_logic := '0';
Signal autoread : std_logic := '0';
Signal sig_wrfifo_rdack : std_logic := '0';
Signal fifo_read_enable : std_logic := '0';
Signal first_write : std_logic := '0';
Signal first_read : std_logic := '0';
Signal first_read1 : std_logic := '0';
-- Component declarations
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-- Bit ordering translations
write_data_lil_end <= AFIFO_Din; -- translate from Big Endian to little
-- endian.
AFIFO_Rd_ack <= sig_wrfifo_rdack;
AFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to
-- Big endian.
AFIFO_Almost_empty <= corrected_almost_empty;
GEN_EMPTY : if (C_USE_AUTORD = 1) generate
begin
AFIFO_Empty <= corrected_empty;
end generate GEN_EMPTY;
GEN_EMPTY1 : if (C_USE_AUTORD = 0) generate
begin
AFIFO_Empty <= sig_afifo_empty;
end generate GEN_EMPTY1;
AFIFO_Wr_count <= wr_count_lil_end;
AFIFO_Rd_count <= rd_count_lil_end;
AFIFO_Corr_Rd_count <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr,
C_CNT_WIDTH+1);
AFIFO_Corr_Rd_count_minus1 <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr_minus1,
C_CNT_WIDTH+1);
AFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator
fifo_read_enable <= AFIFO_Rd_en or autoread;
-------------------------------------------------------------------------------
-- Instantiate the CoreGen FIFO
--
-- NOTE:
-- This instance refers to a wrapper file that interm will use the
-- CoreGen FIFO Generator Async FIFO utility.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0_4.async_fifo_fg
generic map (
-- C_ALLOW_2N_DEPTH => 1,
C_ALLOW_2N_DEPTH => 0,
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DWIDTH,
C_ENABLE_RLOCS => 0,
C_FIFO_DEPTH => C_DEPTH,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_COUNT => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_COUNT => 1,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_COUNT_WIDTH => C_CNT_WIDTH,
C_RD_ERR_LOW => 0,
C_USE_BLOCKMEM => C_USE_BLKMEM,
C_WR_ACK_LOW => 0,
C_WR_COUNT_WIDTH => C_CNT_WIDTH,
C_WR_ERR_LOW => 0
-- C_USE_EMBEDDED_REG => 1, -- 0 ;
-- C_PRELOAD_REGS => 0, -- 0 ;
-- C_PRELOAD_LATENCY => 1 -- 1 ;
)
port Map (
Din => write_data_lil_end,
Wr_en => AFIFO_Wr_en,
Wr_clk => AFIFO_Wr_clk,
Rd_en => fifo_read_enable,
Rd_clk => AFIFO_Rd_clk,
Ainit => AFIFO_Ainit,
Dout => read_data_lil_end,
Full => AFIFO_Full,
Empty => sig_afifo_empty,
Almost_full => AFIFO_Almost_full,
Almost_empty => sig_afifo_almost_empty,
Wr_count => wr_count_lil_end,
Rd_count => rd_count_lil_end,
Rd_ack => sig_wrfifo_rdack,
Rd_err => open, -- Not used by axi_dma
Wr_ack => open, -- Not used by axi_dma
Wr_err => open -- Not used by axi_dma
);
----------------------------------------------------------------------------
-- Read Ack assert & hold logic (needed because:
-- 1) The Async FIFO has to be read once to get valid
-- data to the read data port (data is discarded).
-- 2) The Read ack from the fifo is only asserted for 1 clock.
-- 3) A signal is needed that indicates valid data is at the read
-- port of the FIFO and has not yet been read. This signal needs
-- to be held until the next read operation occurs or a clear
-- signal is received.
ored_ack_ff_reset <= fifo_read_enable or
AFIFO_Ainit or
AFIFO_Clr_Rd_Data_Valid;
sig_rddata_valid <= hold_ff_q or
sig_wrfifo_rdack;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ACK_HOLD_FLOP
--
-- Process Description:
-- Flop for registering the hold flag
--
-------------------------------------------------------------
IMP_ACK_HOLD_FLOP : process (AFIFO_Rd_clk)
begin
if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
if (ored_ack_ff_reset = '1') then
hold_ff_q <= '0';
else
hold_ff_q <= sig_rddata_valid;
end if;
end if;
end process IMP_ACK_HOLD_FLOP;
-- I_ACK_HOLD_FF : FDRE
-- port map(
-- Q => hold_ff_q,
-- C => AFIFO_Rd_clk,
-- CE => '1',
-- D => sig_rddata_valid,
-- R => ored_ack_ff_reset
-- );
-- generate auto-read enable. This keeps fresh data at the output
-- of the FIFO whenever it is available.
GEN_AUTORD1 : if C_USE_AUTORD = 1 generate
autoread <= '1' -- create a read strobe when the
when (sig_rddata_valid = '0' and -- output data is NOT valid
sig_afifo_empty = '0') -- and the FIFO is not empty
Else '0';
end generate GEN_AUTORD1;
GEN_AUTORD2 : if C_USE_AUTORD = 0 generate
process (AFIFO_Wr_clk, AFIFO_Ainit)
begin
if (AFIFO_Ainit = '0') then
first_write <= '0';
elsif (AFIFO_Wr_clk'event and AFIFO_Wr_clk = '1') then
if (AFIFO_Wr_en = '1') then
first_write <= '1';
end if;
end if;
end process;
process (AFIFO_Rd_clk, AFIFO_Ainit)
begin
if (AFIFO_Ainit = '0') then
first_read <= '0';
first_read1 <= '0';
elsif (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
if (sig_afifo_empty = '0') then
first_read <= first_write;
first_read1 <= first_read;
end if;
end if;
end process;
autoread <= first_read xor first_read1;
end generate GEN_AUTORD2;
rd_count_int <= CONV_INTEGER(rd_count_lil_end);
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function.
--
-------------------------------------------------------------
CORRECT_RD_CNT : process (sig_rddata_valid,
sig_afifo_empty,
sig_afifo_almost_empty,
rd_count_int)
begin
if (sig_rddata_valid = '0') then
rd_count_int_corr <= 0;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '1';
corrected_almost_empty <= '0';
elsif (sig_afifo_empty = '1') then -- rddata valid and fifo empty
rd_count_int_corr <= 1;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '0';
corrected_almost_empty <= '1';
Elsif (sig_afifo_almost_empty = '1') Then -- rddata valid and fifo almost empty
rd_count_int_corr <= 2;
rd_count_int_corr_minus1 <= 1;
corrected_empty <= '0';
corrected_almost_empty <= '0';
else -- rddata valid and modify rd count from FIFO
rd_count_int_corr <= rd_count_int+1;
rd_count_int_corr_minus1 <= rd_count_int;
corrected_empty <= '0';
corrected_almost_empty <= '0';
end if;
end process CORRECT_RD_CNT;
end imp;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_afifo_autord.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- asynchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_fifo_v1_0_4;
use lib_fifo_v1_0_4.async_fifo_fg;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity axi_sg_afifo_autord is
generic (
C_DWIDTH : integer := 32;
C_DEPTH : integer := 16;
C_CNT_WIDTH : Integer := 5;
C_USE_BLKMEM : Integer := 0 ;
C_USE_AUTORD : Integer := 1;
C_FAMILY : String := "virtex7"
);
port (
-- Inputs
AFIFO_Ainit : In std_logic; --
AFIFO_Wr_clk : In std_logic; --
AFIFO_Wr_en : In std_logic; --
AFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Rd_clk : In std_logic; --
AFIFO_Rd_en : In std_logic; --
AFIFO_Clr_Rd_Data_Valid : In std_logic; --
--
-- Outputs --
AFIFO_DValid : Out std_logic; --
AFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Full : Out std_logic; --
AFIFO_Empty : Out std_logic; --
AFIFO_Almost_full : Out std_logic; --
AFIFO_Almost_empty : Out std_logic; --
AFIFO_Wr_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Rd_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Corr_Rd_count : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Corr_Rd_count_minus1 : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Rd_ack : Out std_logic --
);
end entity axi_sg_afifo_autord;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_sg_afifo_autord is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- Constant declarations
-- Signal declarations
signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal wr_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_int : integer range 0 to C_DEPTH+1 := 0;
signal rd_count_int_corr : integer range 0 to C_DEPTH+1 := 0;
signal rd_count_int_corr_minus1 : integer range 0 to C_DEPTH+1 := 0;
Signal corrected_empty : std_logic := '0';
Signal corrected_almost_empty : std_logic := '0';
Signal sig_afifo_empty : std_logic := '0';
Signal sig_afifo_almost_empty : std_logic := '0';
-- backend fifo read ack sample and hold
Signal sig_rddata_valid : std_logic := '0';
Signal hold_ff_q : std_logic := '0';
Signal ored_ack_ff_reset : std_logic := '0';
Signal autoread : std_logic := '0';
Signal sig_wrfifo_rdack : std_logic := '0';
Signal fifo_read_enable : std_logic := '0';
Signal first_write : std_logic := '0';
Signal first_read : std_logic := '0';
Signal first_read1 : std_logic := '0';
-- Component declarations
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-- Bit ordering translations
write_data_lil_end <= AFIFO_Din; -- translate from Big Endian to little
-- endian.
AFIFO_Rd_ack <= sig_wrfifo_rdack;
AFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to
-- Big endian.
AFIFO_Almost_empty <= corrected_almost_empty;
GEN_EMPTY : if (C_USE_AUTORD = 1) generate
begin
AFIFO_Empty <= corrected_empty;
end generate GEN_EMPTY;
GEN_EMPTY1 : if (C_USE_AUTORD = 0) generate
begin
AFIFO_Empty <= sig_afifo_empty;
end generate GEN_EMPTY1;
AFIFO_Wr_count <= wr_count_lil_end;
AFIFO_Rd_count <= rd_count_lil_end;
AFIFO_Corr_Rd_count <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr,
C_CNT_WIDTH+1);
AFIFO_Corr_Rd_count_minus1 <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr_minus1,
C_CNT_WIDTH+1);
AFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator
fifo_read_enable <= AFIFO_Rd_en or autoread;
-------------------------------------------------------------------------------
-- Instantiate the CoreGen FIFO
--
-- NOTE:
-- This instance refers to a wrapper file that interm will use the
-- CoreGen FIFO Generator Async FIFO utility.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0_4.async_fifo_fg
generic map (
-- C_ALLOW_2N_DEPTH => 1,
C_ALLOW_2N_DEPTH => 0,
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DWIDTH,
C_ENABLE_RLOCS => 0,
C_FIFO_DEPTH => C_DEPTH,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_COUNT => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_COUNT => 1,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_COUNT_WIDTH => C_CNT_WIDTH,
C_RD_ERR_LOW => 0,
C_USE_BLOCKMEM => C_USE_BLKMEM,
C_WR_ACK_LOW => 0,
C_WR_COUNT_WIDTH => C_CNT_WIDTH,
C_WR_ERR_LOW => 0
-- C_USE_EMBEDDED_REG => 1, -- 0 ;
-- C_PRELOAD_REGS => 0, -- 0 ;
-- C_PRELOAD_LATENCY => 1 -- 1 ;
)
port Map (
Din => write_data_lil_end,
Wr_en => AFIFO_Wr_en,
Wr_clk => AFIFO_Wr_clk,
Rd_en => fifo_read_enable,
Rd_clk => AFIFO_Rd_clk,
Ainit => AFIFO_Ainit,
Dout => read_data_lil_end,
Full => AFIFO_Full,
Empty => sig_afifo_empty,
Almost_full => AFIFO_Almost_full,
Almost_empty => sig_afifo_almost_empty,
Wr_count => wr_count_lil_end,
Rd_count => rd_count_lil_end,
Rd_ack => sig_wrfifo_rdack,
Rd_err => open, -- Not used by axi_dma
Wr_ack => open, -- Not used by axi_dma
Wr_err => open -- Not used by axi_dma
);
----------------------------------------------------------------------------
-- Read Ack assert & hold logic (needed because:
-- 1) The Async FIFO has to be read once to get valid
-- data to the read data port (data is discarded).
-- 2) The Read ack from the fifo is only asserted for 1 clock.
-- 3) A signal is needed that indicates valid data is at the read
-- port of the FIFO and has not yet been read. This signal needs
-- to be held until the next read operation occurs or a clear
-- signal is received.
ored_ack_ff_reset <= fifo_read_enable or
AFIFO_Ainit or
AFIFO_Clr_Rd_Data_Valid;
sig_rddata_valid <= hold_ff_q or
sig_wrfifo_rdack;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ACK_HOLD_FLOP
--
-- Process Description:
-- Flop for registering the hold flag
--
-------------------------------------------------------------
IMP_ACK_HOLD_FLOP : process (AFIFO_Rd_clk)
begin
if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
if (ored_ack_ff_reset = '1') then
hold_ff_q <= '0';
else
hold_ff_q <= sig_rddata_valid;
end if;
end if;
end process IMP_ACK_HOLD_FLOP;
-- I_ACK_HOLD_FF : FDRE
-- port map(
-- Q => hold_ff_q,
-- C => AFIFO_Rd_clk,
-- CE => '1',
-- D => sig_rddata_valid,
-- R => ored_ack_ff_reset
-- );
-- generate auto-read enable. This keeps fresh data at the output
-- of the FIFO whenever it is available.
GEN_AUTORD1 : if C_USE_AUTORD = 1 generate
autoread <= '1' -- create a read strobe when the
when (sig_rddata_valid = '0' and -- output data is NOT valid
sig_afifo_empty = '0') -- and the FIFO is not empty
Else '0';
end generate GEN_AUTORD1;
GEN_AUTORD2 : if C_USE_AUTORD = 0 generate
process (AFIFO_Wr_clk, AFIFO_Ainit)
begin
if (AFIFO_Ainit = '0') then
first_write <= '0';
elsif (AFIFO_Wr_clk'event and AFIFO_Wr_clk = '1') then
if (AFIFO_Wr_en = '1') then
first_write <= '1';
end if;
end if;
end process;
process (AFIFO_Rd_clk, AFIFO_Ainit)
begin
if (AFIFO_Ainit = '0') then
first_read <= '0';
first_read1 <= '0';
elsif (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
if (sig_afifo_empty = '0') then
first_read <= first_write;
first_read1 <= first_read;
end if;
end if;
end process;
autoread <= first_read xor first_read1;
end generate GEN_AUTORD2;
rd_count_int <= CONV_INTEGER(rd_count_lil_end);
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function.
--
-------------------------------------------------------------
CORRECT_RD_CNT : process (sig_rddata_valid,
sig_afifo_empty,
sig_afifo_almost_empty,
rd_count_int)
begin
if (sig_rddata_valid = '0') then
rd_count_int_corr <= 0;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '1';
corrected_almost_empty <= '0';
elsif (sig_afifo_empty = '1') then -- rddata valid and fifo empty
rd_count_int_corr <= 1;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '0';
corrected_almost_empty <= '1';
Elsif (sig_afifo_almost_empty = '1') Then -- rddata valid and fifo almost empty
rd_count_int_corr <= 2;
rd_count_int_corr_minus1 <= 1;
corrected_empty <= '0';
corrected_almost_empty <= '0';
else -- rddata valid and modify rd count from FIFO
rd_count_int_corr <= rd_count_int+1;
rd_count_int_corr_minus1 <= rd_count_int;
corrected_empty <= '0';
corrected_almost_empty <= '0';
end if;
end process CORRECT_RD_CNT;
end imp;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_afifo_autord.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- asynchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_fifo_v1_0_4;
use lib_fifo_v1_0_4.async_fifo_fg;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity axi_sg_afifo_autord is
generic (
C_DWIDTH : integer := 32;
C_DEPTH : integer := 16;
C_CNT_WIDTH : Integer := 5;
C_USE_BLKMEM : Integer := 0 ;
C_USE_AUTORD : Integer := 1;
C_FAMILY : String := "virtex7"
);
port (
-- Inputs
AFIFO_Ainit : In std_logic; --
AFIFO_Wr_clk : In std_logic; --
AFIFO_Wr_en : In std_logic; --
AFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Rd_clk : In std_logic; --
AFIFO_Rd_en : In std_logic; --
AFIFO_Clr_Rd_Data_Valid : In std_logic; --
--
-- Outputs --
AFIFO_DValid : Out std_logic; --
AFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Full : Out std_logic; --
AFIFO_Empty : Out std_logic; --
AFIFO_Almost_full : Out std_logic; --
AFIFO_Almost_empty : Out std_logic; --
AFIFO_Wr_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Rd_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Corr_Rd_count : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Corr_Rd_count_minus1 : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Rd_ack : Out std_logic --
);
end entity axi_sg_afifo_autord;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_sg_afifo_autord is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- Constant declarations
-- Signal declarations
signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal wr_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_int : integer range 0 to C_DEPTH+1 := 0;
signal rd_count_int_corr : integer range 0 to C_DEPTH+1 := 0;
signal rd_count_int_corr_minus1 : integer range 0 to C_DEPTH+1 := 0;
Signal corrected_empty : std_logic := '0';
Signal corrected_almost_empty : std_logic := '0';
Signal sig_afifo_empty : std_logic := '0';
Signal sig_afifo_almost_empty : std_logic := '0';
-- backend fifo read ack sample and hold
Signal sig_rddata_valid : std_logic := '0';
Signal hold_ff_q : std_logic := '0';
Signal ored_ack_ff_reset : std_logic := '0';
Signal autoread : std_logic := '0';
Signal sig_wrfifo_rdack : std_logic := '0';
Signal fifo_read_enable : std_logic := '0';
Signal first_write : std_logic := '0';
Signal first_read : std_logic := '0';
Signal first_read1 : std_logic := '0';
-- Component declarations
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-- Bit ordering translations
write_data_lil_end <= AFIFO_Din; -- translate from Big Endian to little
-- endian.
AFIFO_Rd_ack <= sig_wrfifo_rdack;
AFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to
-- Big endian.
AFIFO_Almost_empty <= corrected_almost_empty;
GEN_EMPTY : if (C_USE_AUTORD = 1) generate
begin
AFIFO_Empty <= corrected_empty;
end generate GEN_EMPTY;
GEN_EMPTY1 : if (C_USE_AUTORD = 0) generate
begin
AFIFO_Empty <= sig_afifo_empty;
end generate GEN_EMPTY1;
AFIFO_Wr_count <= wr_count_lil_end;
AFIFO_Rd_count <= rd_count_lil_end;
AFIFO_Corr_Rd_count <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr,
C_CNT_WIDTH+1);
AFIFO_Corr_Rd_count_minus1 <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr_minus1,
C_CNT_WIDTH+1);
AFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator
fifo_read_enable <= AFIFO_Rd_en or autoread;
-------------------------------------------------------------------------------
-- Instantiate the CoreGen FIFO
--
-- NOTE:
-- This instance refers to a wrapper file that interm will use the
-- CoreGen FIFO Generator Async FIFO utility.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0_4.async_fifo_fg
generic map (
-- C_ALLOW_2N_DEPTH => 1,
C_ALLOW_2N_DEPTH => 0,
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DWIDTH,
C_ENABLE_RLOCS => 0,
C_FIFO_DEPTH => C_DEPTH,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_COUNT => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_COUNT => 1,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_COUNT_WIDTH => C_CNT_WIDTH,
C_RD_ERR_LOW => 0,
C_USE_BLOCKMEM => C_USE_BLKMEM,
C_WR_ACK_LOW => 0,
C_WR_COUNT_WIDTH => C_CNT_WIDTH,
C_WR_ERR_LOW => 0
-- C_USE_EMBEDDED_REG => 1, -- 0 ;
-- C_PRELOAD_REGS => 0, -- 0 ;
-- C_PRELOAD_LATENCY => 1 -- 1 ;
)
port Map (
Din => write_data_lil_end,
Wr_en => AFIFO_Wr_en,
Wr_clk => AFIFO_Wr_clk,
Rd_en => fifo_read_enable,
Rd_clk => AFIFO_Rd_clk,
Ainit => AFIFO_Ainit,
Dout => read_data_lil_end,
Full => AFIFO_Full,
Empty => sig_afifo_empty,
Almost_full => AFIFO_Almost_full,
Almost_empty => sig_afifo_almost_empty,
Wr_count => wr_count_lil_end,
Rd_count => rd_count_lil_end,
Rd_ack => sig_wrfifo_rdack,
Rd_err => open, -- Not used by axi_dma
Wr_ack => open, -- Not used by axi_dma
Wr_err => open -- Not used by axi_dma
);
----------------------------------------------------------------------------
-- Read Ack assert & hold logic (needed because:
-- 1) The Async FIFO has to be read once to get valid
-- data to the read data port (data is discarded).
-- 2) The Read ack from the fifo is only asserted for 1 clock.
-- 3) A signal is needed that indicates valid data is at the read
-- port of the FIFO and has not yet been read. This signal needs
-- to be held until the next read operation occurs or a clear
-- signal is received.
ored_ack_ff_reset <= fifo_read_enable or
AFIFO_Ainit or
AFIFO_Clr_Rd_Data_Valid;
sig_rddata_valid <= hold_ff_q or
sig_wrfifo_rdack;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ACK_HOLD_FLOP
--
-- Process Description:
-- Flop for registering the hold flag
--
-------------------------------------------------------------
IMP_ACK_HOLD_FLOP : process (AFIFO_Rd_clk)
begin
if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
if (ored_ack_ff_reset = '1') then
hold_ff_q <= '0';
else
hold_ff_q <= sig_rddata_valid;
end if;
end if;
end process IMP_ACK_HOLD_FLOP;
-- I_ACK_HOLD_FF : FDRE
-- port map(
-- Q => hold_ff_q,
-- C => AFIFO_Rd_clk,
-- CE => '1',
-- D => sig_rddata_valid,
-- R => ored_ack_ff_reset
-- );
-- generate auto-read enable. This keeps fresh data at the output
-- of the FIFO whenever it is available.
GEN_AUTORD1 : if C_USE_AUTORD = 1 generate
autoread <= '1' -- create a read strobe when the
when (sig_rddata_valid = '0' and -- output data is NOT valid
sig_afifo_empty = '0') -- and the FIFO is not empty
Else '0';
end generate GEN_AUTORD1;
GEN_AUTORD2 : if C_USE_AUTORD = 0 generate
process (AFIFO_Wr_clk, AFIFO_Ainit)
begin
if (AFIFO_Ainit = '0') then
first_write <= '0';
elsif (AFIFO_Wr_clk'event and AFIFO_Wr_clk = '1') then
if (AFIFO_Wr_en = '1') then
first_write <= '1';
end if;
end if;
end process;
process (AFIFO_Rd_clk, AFIFO_Ainit)
begin
if (AFIFO_Ainit = '0') then
first_read <= '0';
first_read1 <= '0';
elsif (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
if (sig_afifo_empty = '0') then
first_read <= first_write;
first_read1 <= first_read;
end if;
end if;
end process;
autoread <= first_read xor first_read1;
end generate GEN_AUTORD2;
rd_count_int <= CONV_INTEGER(rd_count_lil_end);
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function.
--
-------------------------------------------------------------
CORRECT_RD_CNT : process (sig_rddata_valid,
sig_afifo_empty,
sig_afifo_almost_empty,
rd_count_int)
begin
if (sig_rddata_valid = '0') then
rd_count_int_corr <= 0;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '1';
corrected_almost_empty <= '0';
elsif (sig_afifo_empty = '1') then -- rddata valid and fifo empty
rd_count_int_corr <= 1;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '0';
corrected_almost_empty <= '1';
Elsif (sig_afifo_almost_empty = '1') Then -- rddata valid and fifo almost empty
rd_count_int_corr <= 2;
rd_count_int_corr_minus1 <= 1;
corrected_empty <= '0';
corrected_almost_empty <= '0';
else -- rddata valid and modify rd count from FIFO
rd_count_int_corr <= rd_count_int+1;
rd_count_int_corr_minus1 <= rd_count_int;
corrected_empty <= '0';
corrected_almost_empty <= '0';
end if;
end process CORRECT_RD_CNT;
end imp;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_afifo_autord.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- asynchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_fifo_v1_0_4;
use lib_fifo_v1_0_4.async_fifo_fg;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity axi_sg_afifo_autord is
generic (
C_DWIDTH : integer := 32;
C_DEPTH : integer := 16;
C_CNT_WIDTH : Integer := 5;
C_USE_BLKMEM : Integer := 0 ;
C_USE_AUTORD : Integer := 1;
C_FAMILY : String := "virtex7"
);
port (
-- Inputs
AFIFO_Ainit : In std_logic; --
AFIFO_Wr_clk : In std_logic; --
AFIFO_Wr_en : In std_logic; --
AFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Rd_clk : In std_logic; --
AFIFO_Rd_en : In std_logic; --
AFIFO_Clr_Rd_Data_Valid : In std_logic; --
--
-- Outputs --
AFIFO_DValid : Out std_logic; --
AFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Full : Out std_logic; --
AFIFO_Empty : Out std_logic; --
AFIFO_Almost_full : Out std_logic; --
AFIFO_Almost_empty : Out std_logic; --
AFIFO_Wr_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Rd_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Corr_Rd_count : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Corr_Rd_count_minus1 : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Rd_ack : Out std_logic --
);
end entity axi_sg_afifo_autord;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_sg_afifo_autord is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- Constant declarations
-- Signal declarations
signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal wr_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_int : integer range 0 to C_DEPTH+1 := 0;
signal rd_count_int_corr : integer range 0 to C_DEPTH+1 := 0;
signal rd_count_int_corr_minus1 : integer range 0 to C_DEPTH+1 := 0;
Signal corrected_empty : std_logic := '0';
Signal corrected_almost_empty : std_logic := '0';
Signal sig_afifo_empty : std_logic := '0';
Signal sig_afifo_almost_empty : std_logic := '0';
-- backend fifo read ack sample and hold
Signal sig_rddata_valid : std_logic := '0';
Signal hold_ff_q : std_logic := '0';
Signal ored_ack_ff_reset : std_logic := '0';
Signal autoread : std_logic := '0';
Signal sig_wrfifo_rdack : std_logic := '0';
Signal fifo_read_enable : std_logic := '0';
Signal first_write : std_logic := '0';
Signal first_read : std_logic := '0';
Signal first_read1 : std_logic := '0';
-- Component declarations
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-- Bit ordering translations
write_data_lil_end <= AFIFO_Din; -- translate from Big Endian to little
-- endian.
AFIFO_Rd_ack <= sig_wrfifo_rdack;
AFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to
-- Big endian.
AFIFO_Almost_empty <= corrected_almost_empty;
GEN_EMPTY : if (C_USE_AUTORD = 1) generate
begin
AFIFO_Empty <= corrected_empty;
end generate GEN_EMPTY;
GEN_EMPTY1 : if (C_USE_AUTORD = 0) generate
begin
AFIFO_Empty <= sig_afifo_empty;
end generate GEN_EMPTY1;
AFIFO_Wr_count <= wr_count_lil_end;
AFIFO_Rd_count <= rd_count_lil_end;
AFIFO_Corr_Rd_count <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr,
C_CNT_WIDTH+1);
AFIFO_Corr_Rd_count_minus1 <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr_minus1,
C_CNT_WIDTH+1);
AFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator
fifo_read_enable <= AFIFO_Rd_en or autoread;
-------------------------------------------------------------------------------
-- Instantiate the CoreGen FIFO
--
-- NOTE:
-- This instance refers to a wrapper file that interm will use the
-- CoreGen FIFO Generator Async FIFO utility.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0_4.async_fifo_fg
generic map (
-- C_ALLOW_2N_DEPTH => 1,
C_ALLOW_2N_DEPTH => 0,
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DWIDTH,
C_ENABLE_RLOCS => 0,
C_FIFO_DEPTH => C_DEPTH,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_COUNT => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_COUNT => 1,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_COUNT_WIDTH => C_CNT_WIDTH,
C_RD_ERR_LOW => 0,
C_USE_BLOCKMEM => C_USE_BLKMEM,
C_WR_ACK_LOW => 0,
C_WR_COUNT_WIDTH => C_CNT_WIDTH,
C_WR_ERR_LOW => 0
-- C_USE_EMBEDDED_REG => 1, -- 0 ;
-- C_PRELOAD_REGS => 0, -- 0 ;
-- C_PRELOAD_LATENCY => 1 -- 1 ;
)
port Map (
Din => write_data_lil_end,
Wr_en => AFIFO_Wr_en,
Wr_clk => AFIFO_Wr_clk,
Rd_en => fifo_read_enable,
Rd_clk => AFIFO_Rd_clk,
Ainit => AFIFO_Ainit,
Dout => read_data_lil_end,
Full => AFIFO_Full,
Empty => sig_afifo_empty,
Almost_full => AFIFO_Almost_full,
Almost_empty => sig_afifo_almost_empty,
Wr_count => wr_count_lil_end,
Rd_count => rd_count_lil_end,
Rd_ack => sig_wrfifo_rdack,
Rd_err => open, -- Not used by axi_dma
Wr_ack => open, -- Not used by axi_dma
Wr_err => open -- Not used by axi_dma
);
----------------------------------------------------------------------------
-- Read Ack assert & hold logic (needed because:
-- 1) The Async FIFO has to be read once to get valid
-- data to the read data port (data is discarded).
-- 2) The Read ack from the fifo is only asserted for 1 clock.
-- 3) A signal is needed that indicates valid data is at the read
-- port of the FIFO and has not yet been read. This signal needs
-- to be held until the next read operation occurs or a clear
-- signal is received.
ored_ack_ff_reset <= fifo_read_enable or
AFIFO_Ainit or
AFIFO_Clr_Rd_Data_Valid;
sig_rddata_valid <= hold_ff_q or
sig_wrfifo_rdack;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ACK_HOLD_FLOP
--
-- Process Description:
-- Flop for registering the hold flag
--
-------------------------------------------------------------
IMP_ACK_HOLD_FLOP : process (AFIFO_Rd_clk)
begin
if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
if (ored_ack_ff_reset = '1') then
hold_ff_q <= '0';
else
hold_ff_q <= sig_rddata_valid;
end if;
end if;
end process IMP_ACK_HOLD_FLOP;
-- I_ACK_HOLD_FF : FDRE
-- port map(
-- Q => hold_ff_q,
-- C => AFIFO_Rd_clk,
-- CE => '1',
-- D => sig_rddata_valid,
-- R => ored_ack_ff_reset
-- );
-- generate auto-read enable. This keeps fresh data at the output
-- of the FIFO whenever it is available.
GEN_AUTORD1 : if C_USE_AUTORD = 1 generate
autoread <= '1' -- create a read strobe when the
when (sig_rddata_valid = '0' and -- output data is NOT valid
sig_afifo_empty = '0') -- and the FIFO is not empty
Else '0';
end generate GEN_AUTORD1;
GEN_AUTORD2 : if C_USE_AUTORD = 0 generate
process (AFIFO_Wr_clk, AFIFO_Ainit)
begin
if (AFIFO_Ainit = '0') then
first_write <= '0';
elsif (AFIFO_Wr_clk'event and AFIFO_Wr_clk = '1') then
if (AFIFO_Wr_en = '1') then
first_write <= '1';
end if;
end if;
end process;
process (AFIFO_Rd_clk, AFIFO_Ainit)
begin
if (AFIFO_Ainit = '0') then
first_read <= '0';
first_read1 <= '0';
elsif (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
if (sig_afifo_empty = '0') then
first_read <= first_write;
first_read1 <= first_read;
end if;
end if;
end process;
autoread <= first_read xor first_read1;
end generate GEN_AUTORD2;
rd_count_int <= CONV_INTEGER(rd_count_lil_end);
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function.
--
-------------------------------------------------------------
CORRECT_RD_CNT : process (sig_rddata_valid,
sig_afifo_empty,
sig_afifo_almost_empty,
rd_count_int)
begin
if (sig_rddata_valid = '0') then
rd_count_int_corr <= 0;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '1';
corrected_almost_empty <= '0';
elsif (sig_afifo_empty = '1') then -- rddata valid and fifo empty
rd_count_int_corr <= 1;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '0';
corrected_almost_empty <= '1';
Elsif (sig_afifo_almost_empty = '1') Then -- rddata valid and fifo almost empty
rd_count_int_corr <= 2;
rd_count_int_corr_minus1 <= 1;
corrected_empty <= '0';
corrected_almost_empty <= '0';
else -- rddata valid and modify rd count from FIFO
rd_count_int_corr <= rd_count_int+1;
rd_count_int_corr_minus1 <= rd_count_int;
corrected_empty <= '0';
corrected_almost_empty <= '0';
end if;
end process CORRECT_RD_CNT;
end imp;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_afifo_autord.vhd
-- Version: initial
-- Description:
-- This file contains the logic to generate a CoreGen call to create a
-- asynchronous FIFO as part of the synthesis process of XST. This eliminates
-- the need for multiple fixed netlists for various sizes and widths of FIFOs.
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library lib_fifo_v1_0_4;
use lib_fifo_v1_0_4.async_fifo_fg;
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity axi_sg_afifo_autord is
generic (
C_DWIDTH : integer := 32;
C_DEPTH : integer := 16;
C_CNT_WIDTH : Integer := 5;
C_USE_BLKMEM : Integer := 0 ;
C_USE_AUTORD : Integer := 1;
C_FAMILY : String := "virtex7"
);
port (
-- Inputs
AFIFO_Ainit : In std_logic; --
AFIFO_Wr_clk : In std_logic; --
AFIFO_Wr_en : In std_logic; --
AFIFO_Din : In std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Rd_clk : In std_logic; --
AFIFO_Rd_en : In std_logic; --
AFIFO_Clr_Rd_Data_Valid : In std_logic; --
--
-- Outputs --
AFIFO_DValid : Out std_logic; --
AFIFO_Dout : Out std_logic_vector(C_DWIDTH-1 downto 0); --
AFIFO_Full : Out std_logic; --
AFIFO_Empty : Out std_logic; --
AFIFO_Almost_full : Out std_logic; --
AFIFO_Almost_empty : Out std_logic; --
AFIFO_Wr_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Rd_count : Out std_logic_vector(C_CNT_WIDTH-1 downto 0); --
AFIFO_Corr_Rd_count : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Corr_Rd_count_minus1 : Out std_logic_vector(C_CNT_WIDTH downto 0); --
AFIFO_Rd_ack : Out std_logic --
);
end entity axi_sg_afifo_autord;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of axi_sg_afifo_autord is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-- Constant declarations
-- Signal declarations
signal write_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal read_data_lil_end : std_logic_vector(C_DWIDTH-1 downto 0) := (others => '0');
signal wr_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_lil_end : std_logic_vector(C_CNT_WIDTH-1 downto 0) := (others => '0');
signal rd_count_int : integer range 0 to C_DEPTH+1 := 0;
signal rd_count_int_corr : integer range 0 to C_DEPTH+1 := 0;
signal rd_count_int_corr_minus1 : integer range 0 to C_DEPTH+1 := 0;
Signal corrected_empty : std_logic := '0';
Signal corrected_almost_empty : std_logic := '0';
Signal sig_afifo_empty : std_logic := '0';
Signal sig_afifo_almost_empty : std_logic := '0';
-- backend fifo read ack sample and hold
Signal sig_rddata_valid : std_logic := '0';
Signal hold_ff_q : std_logic := '0';
Signal ored_ack_ff_reset : std_logic := '0';
Signal autoread : std_logic := '0';
Signal sig_wrfifo_rdack : std_logic := '0';
Signal fifo_read_enable : std_logic := '0';
Signal first_write : std_logic := '0';
Signal first_read : std_logic := '0';
Signal first_read1 : std_logic := '0';
-- Component declarations
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin
-- Bit ordering translations
write_data_lil_end <= AFIFO_Din; -- translate from Big Endian to little
-- endian.
AFIFO_Rd_ack <= sig_wrfifo_rdack;
AFIFO_Dout <= read_data_lil_end; -- translate from Little Endian to
-- Big endian.
AFIFO_Almost_empty <= corrected_almost_empty;
GEN_EMPTY : if (C_USE_AUTORD = 1) generate
begin
AFIFO_Empty <= corrected_empty;
end generate GEN_EMPTY;
GEN_EMPTY1 : if (C_USE_AUTORD = 0) generate
begin
AFIFO_Empty <= sig_afifo_empty;
end generate GEN_EMPTY1;
AFIFO_Wr_count <= wr_count_lil_end;
AFIFO_Rd_count <= rd_count_lil_end;
AFIFO_Corr_Rd_count <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr,
C_CNT_WIDTH+1);
AFIFO_Corr_Rd_count_minus1 <= CONV_STD_LOGIC_VECTOR(rd_count_int_corr_minus1,
C_CNT_WIDTH+1);
AFIFO_DValid <= sig_rddata_valid; -- Output data valid indicator
fifo_read_enable <= AFIFO_Rd_en or autoread;
-------------------------------------------------------------------------------
-- Instantiate the CoreGen FIFO
--
-- NOTE:
-- This instance refers to a wrapper file that interm will use the
-- CoreGen FIFO Generator Async FIFO utility.
--
-------------------------------------------------------------------------------
I_ASYNC_FIFOGEN_FIFO : entity lib_fifo_v1_0_4.async_fifo_fg
generic map (
-- C_ALLOW_2N_DEPTH => 1,
C_ALLOW_2N_DEPTH => 0,
C_FAMILY => C_FAMILY,
C_DATA_WIDTH => C_DWIDTH,
C_ENABLE_RLOCS => 0,
C_FIFO_DEPTH => C_DEPTH,
C_HAS_ALMOST_EMPTY => 1,
C_HAS_ALMOST_FULL => 1,
C_HAS_RD_ACK => 1,
C_HAS_RD_COUNT => 1,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_COUNT => 1,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_COUNT_WIDTH => C_CNT_WIDTH,
C_RD_ERR_LOW => 0,
C_USE_BLOCKMEM => C_USE_BLKMEM,
C_WR_ACK_LOW => 0,
C_WR_COUNT_WIDTH => C_CNT_WIDTH,
C_WR_ERR_LOW => 0
-- C_USE_EMBEDDED_REG => 1, -- 0 ;
-- C_PRELOAD_REGS => 0, -- 0 ;
-- C_PRELOAD_LATENCY => 1 -- 1 ;
)
port Map (
Din => write_data_lil_end,
Wr_en => AFIFO_Wr_en,
Wr_clk => AFIFO_Wr_clk,
Rd_en => fifo_read_enable,
Rd_clk => AFIFO_Rd_clk,
Ainit => AFIFO_Ainit,
Dout => read_data_lil_end,
Full => AFIFO_Full,
Empty => sig_afifo_empty,
Almost_full => AFIFO_Almost_full,
Almost_empty => sig_afifo_almost_empty,
Wr_count => wr_count_lil_end,
Rd_count => rd_count_lil_end,
Rd_ack => sig_wrfifo_rdack,
Rd_err => open, -- Not used by axi_dma
Wr_ack => open, -- Not used by axi_dma
Wr_err => open -- Not used by axi_dma
);
----------------------------------------------------------------------------
-- Read Ack assert & hold logic (needed because:
-- 1) The Async FIFO has to be read once to get valid
-- data to the read data port (data is discarded).
-- 2) The Read ack from the fifo is only asserted for 1 clock.
-- 3) A signal is needed that indicates valid data is at the read
-- port of the FIFO and has not yet been read. This signal needs
-- to be held until the next read operation occurs or a clear
-- signal is received.
ored_ack_ff_reset <= fifo_read_enable or
AFIFO_Ainit or
AFIFO_Clr_Rd_Data_Valid;
sig_rddata_valid <= hold_ff_q or
sig_wrfifo_rdack;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ACK_HOLD_FLOP
--
-- Process Description:
-- Flop for registering the hold flag
--
-------------------------------------------------------------
IMP_ACK_HOLD_FLOP : process (AFIFO_Rd_clk)
begin
if (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
if (ored_ack_ff_reset = '1') then
hold_ff_q <= '0';
else
hold_ff_q <= sig_rddata_valid;
end if;
end if;
end process IMP_ACK_HOLD_FLOP;
-- I_ACK_HOLD_FF : FDRE
-- port map(
-- Q => hold_ff_q,
-- C => AFIFO_Rd_clk,
-- CE => '1',
-- D => sig_rddata_valid,
-- R => ored_ack_ff_reset
-- );
-- generate auto-read enable. This keeps fresh data at the output
-- of the FIFO whenever it is available.
GEN_AUTORD1 : if C_USE_AUTORD = 1 generate
autoread <= '1' -- create a read strobe when the
when (sig_rddata_valid = '0' and -- output data is NOT valid
sig_afifo_empty = '0') -- and the FIFO is not empty
Else '0';
end generate GEN_AUTORD1;
GEN_AUTORD2 : if C_USE_AUTORD = 0 generate
process (AFIFO_Wr_clk, AFIFO_Ainit)
begin
if (AFIFO_Ainit = '0') then
first_write <= '0';
elsif (AFIFO_Wr_clk'event and AFIFO_Wr_clk = '1') then
if (AFIFO_Wr_en = '1') then
first_write <= '1';
end if;
end if;
end process;
process (AFIFO_Rd_clk, AFIFO_Ainit)
begin
if (AFIFO_Ainit = '0') then
first_read <= '0';
first_read1 <= '0';
elsif (AFIFO_Rd_clk'event and AFIFO_Rd_clk = '1') then
if (sig_afifo_empty = '0') then
first_read <= first_write;
first_read1 <= first_read;
end if;
end if;
end process;
autoread <= first_read xor first_read1;
end generate GEN_AUTORD2;
rd_count_int <= CONV_INTEGER(rd_count_lil_end);
-------------------------------------------------------------
-- Combinational Process
--
-- Label: CORRECT_RD_CNT
--
-- Process Description:
-- This process corrects the FIFO Read Count output for the
-- auto read function.
--
-------------------------------------------------------------
CORRECT_RD_CNT : process (sig_rddata_valid,
sig_afifo_empty,
sig_afifo_almost_empty,
rd_count_int)
begin
if (sig_rddata_valid = '0') then
rd_count_int_corr <= 0;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '1';
corrected_almost_empty <= '0';
elsif (sig_afifo_empty = '1') then -- rddata valid and fifo empty
rd_count_int_corr <= 1;
rd_count_int_corr_minus1 <= 0;
corrected_empty <= '0';
corrected_almost_empty <= '1';
Elsif (sig_afifo_almost_empty = '1') Then -- rddata valid and fifo almost empty
rd_count_int_corr <= 2;
rd_count_int_corr_minus1 <= 1;
corrected_empty <= '0';
corrected_almost_empty <= '0';
else -- rddata valid and modify rd count from FIFO
rd_count_int_corr <= rd_count_int+1;
rd_count_int_corr_minus1 <= rd_count_int;
corrected_empty <= '0';
corrected_almost_empty <= '0';
end if;
end process CORRECT_RD_CNT;
end imp;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_14 is
end entity inline_14;
----------------------------------------------------------------
architecture test of inline_14 is
-- code from book:
type controller_state is (initial, idle, active, error);
-- end of code from book
signal current_state : controller_state := initial;
begin
process_4_c : process is
begin
-- code from book:
for state in controller_state loop
-- . . .
-- not in book:
current_state <= state;
wait for 10 ns;
-- end not in book
end loop;
-- end of code from book
wait;
end process process_4_c;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_14 is
end entity inline_14;
----------------------------------------------------------------
architecture test of inline_14 is
-- code from book:
type controller_state is (initial, idle, active, error);
-- end of code from book
signal current_state : controller_state := initial;
begin
process_4_c : process is
begin
-- code from book:
for state in controller_state loop
-- . . .
-- not in book:
current_state <= state;
wait for 10 ns;
-- end not in book
end loop;
-- end of code from book
wait;
end process process_4_c;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_14 is
end entity inline_14;
----------------------------------------------------------------
architecture test of inline_14 is
-- code from book:
type controller_state is (initial, idle, active, error);
-- end of code from book
signal current_state : controller_state := initial;
begin
process_4_c : process is
begin
-- code from book:
for state in controller_state loop
-- . . .
-- not in book:
current_state <= state;
wait for 10 ns;
-- end not in book
end loop;
-- end of code from book
wait;
end process process_4_c;
end architecture test;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Entity: fifo_shift
--
-- Module: FIFO, common clock, pipelined interface
--
-- Authors: Thomas B. Preusser
--
-- Description:
-- ------------------------------------
-- This FIFO implementation is based on an internal shift register. This is
-- especially useful for smaller FIFO sizes, which can be implemented in LUT
-- storage on some devices (e.g. Xilinx' SRLs). Only a single read pointer is
-- maintained, which determines the number of valid entries within the
-- underlying shift register.
-- The specified depth (MIN_DEPTH) is rounded up to the next suitable value.
--
--
-- License:
-- ============================================================================
-- Copyright 2007-2014 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
library PoC;
use Poc.utils.all;
entity fifo_shift is
generic (
D_BITS : positive; -- Data Width
MIN_DEPTH : positive -- Minimum FIFO Size in Words
);
port (
-- Global Control
clk : in std_logic;
rst : in std_logic;
-- Writing Interface
put : in std_logic; -- Write Request
din : in std_logic_vector(D_BITS-1 downto 0); -- Input Data
ful : out std_logic; -- Capacity Exhausted
-- Reading Interface
got : in std_logic; -- Read Done Strobe
dout : out std_logic_vector(D_BITS-1 downto 0); -- Output Data
vld : out std_logic -- Data Valid
);
end fifo_shift;
library IEEE;
use IEEE.numeric_std.all;
library poc;
use poc.utils.all;
architecture rtl of fifo_shift is
-- Data Register
type tData is array(natural range<>) of std_logic_vector(D_BITS-1 downto 0);
signal Dat : tData(0 to MIN_DEPTH-1);
signal Ptr : unsigned(log2ceilnz(MIN_DEPTH) downto 0);
begin
-- Data anf Pointer Registers
process(clk)
begin
if clk'event and clk = '1' then
if put = '1' then
Dat <= din & Dat(0 to MIN_DEPTH-2);
end if;
end if;
end process;
process(clk)
begin
if clk'event and clk = '1' then
if rst = '1' then
Ptr <= (others => '0');
else
if put /= got then
if put = '1' then
Ptr <= Ptr - 1;
else
Ptr <= Ptr + 1;
end if;
end if;
end if;
end if;
end process;
-- Outputs
dout <= Dat(to_integer(not Ptr(Ptr'left-1 downto 0)));
vld <= Ptr(Ptr'left);
ful <= '1' when ((not Ptr(Ptr'left-1 downto 0)) and to_unsigned(MIN_DEPTH-1, Ptr'length-1)) = MIN_DEPTH-1 else '0';
end rtl;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Entity: fifo_shift
--
-- Module: FIFO, common clock, pipelined interface
--
-- Authors: Thomas B. Preusser
--
-- Description:
-- ------------------------------------
-- This FIFO implementation is based on an internal shift register. This is
-- especially useful for smaller FIFO sizes, which can be implemented in LUT
-- storage on some devices (e.g. Xilinx' SRLs). Only a single read pointer is
-- maintained, which determines the number of valid entries within the
-- underlying shift register.
-- The specified depth (MIN_DEPTH) is rounded up to the next suitable value.
--
--
-- License:
-- ============================================================================
-- Copyright 2007-2014 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.std_logic_1164.all;
library PoC;
use Poc.utils.all;
entity fifo_shift is
generic (
D_BITS : positive; -- Data Width
MIN_DEPTH : positive -- Minimum FIFO Size in Words
);
port (
-- Global Control
clk : in std_logic;
rst : in std_logic;
-- Writing Interface
put : in std_logic; -- Write Request
din : in std_logic_vector(D_BITS-1 downto 0); -- Input Data
ful : out std_logic; -- Capacity Exhausted
-- Reading Interface
got : in std_logic; -- Read Done Strobe
dout : out std_logic_vector(D_BITS-1 downto 0); -- Output Data
vld : out std_logic -- Data Valid
);
end fifo_shift;
library IEEE;
use IEEE.numeric_std.all;
library poc;
use poc.utils.all;
architecture rtl of fifo_shift is
-- Data Register
type tData is array(natural range<>) of std_logic_vector(D_BITS-1 downto 0);
signal Dat : tData(0 to MIN_DEPTH-1);
signal Ptr : unsigned(log2ceilnz(MIN_DEPTH) downto 0);
begin
-- Data anf Pointer Registers
process(clk)
begin
if clk'event and clk = '1' then
if put = '1' then
Dat <= din & Dat(0 to MIN_DEPTH-2);
end if;
end if;
end process;
process(clk)
begin
if clk'event and clk = '1' then
if rst = '1' then
Ptr <= (others => '0');
else
if put /= got then
if put = '1' then
Ptr <= Ptr - 1;
else
Ptr <= Ptr + 1;
end if;
end if;
end if;
end if;
end process;
-- Outputs
dout <= Dat(to_integer(not Ptr(Ptr'left-1 downto 0)));
vld <= Ptr(Ptr'left);
ful <= '1' when ((not Ptr(Ptr'left-1 downto 0)) and to_unsigned(MIN_DEPTH-1, Ptr'length-1)) = MIN_DEPTH-1 else '0';
end rtl;
|
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