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----------------------------------------------------------------------------------
-- Company:LAAS-CNRS
-- Author:Jonathan Piat <[email protected]>
--
-- Create Date: 15:37:36 06/18/2012
-- Design Name:
-- Module Name: dp_fifo - Behavioral
-- Project Name:
-- Target Devices: Spartan 6
-- Tool versions: ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
library work ;
use work.logi_primitive_pack.all ;
use work.logi_utils_pack.all ;
--! dual port ram based fifo for fast logic to logic communication
entity dp_fifo is
generic(N : natural := 128 ; --! depth of the fifo
W : positive := 16; --! width of the fifo
SYNC_WR : boolean := false;
SYNC_RD : boolean := false
);
port(
clk, resetn, sraz : in std_logic; --! system clock, asynchronous and synchronous reset
wr, rd : in std_logic; --! fifo write and read signal
empty, full : out std_logic ; --! fifo stat signals
data_out : out std_logic_vector((W - 1) downto 0 ); --! data output of fifo
data_in : in std_logic_vector((W - 1) downto 0 ); --! data input of fifo
nb_available : out unsigned(nbit(N) downto 0 ) --! number of available tokens in fifo
);
end dp_fifo;
architecture Behavioral of dp_fifo is
constant std_fifo_size : std_logic_vector(nbit(N) downto 0 ) := std_logic_vector(to_unsigned(N, nbit(N) + 1));
signal rd_addr, rd_addr_adv, wr_addr: std_logic_vector((nbit(N) - 1) downto 0) ;
signal nb_free_t, nb_available_t : unsigned(nbit(N) downto 0 ) ;
signal slv_nb_available_t : std_logic_vector(nbit(N) downto 0 ) ;
signal fifo_out, fifo_in : std_logic_vector((W - 1 ) downto 0) ;
signal rd_old, wr_old, wr_data, rd_data, one_turn, latch_data : std_logic ;
signal rd_rising_edge, wr_rising_edge : std_logic ;
signal rd_falling_edge, wr_falling_edge : std_logic ;
signal en_available_counter, up_downn_available_counter : std_logic ;
signal en_free_counter, up_downn_free_counter, counter_load : std_logic ;
signal fifo_wr, fifo_rd : std_logic ;
begin
dp_ram0 : dpram_NxN
generic map(SIZE => N , NBIT => W, ADDR_WIDTH => nbit(N))
port map(
clk => clk ,
we => wr_data ,
di => data_in ,
a => wr_addr,
dpra => rd_addr_adv ,
dpo => fifo_out
);
data_out <= fifo_out ;
gen_async_rd : if NOT SYNC_RD generate
process(resetn, clk)
begin
if resetn = '0' then
rd_old <= '0' ;
elsif clk'event and clk = '1' then
rd_old <= rd ;
end if ;
end process ;
rd_falling_edge <= ((NOT rd) AND rd_old);
fifo_rd <= rd_falling_edge ;
rd_addr_adv <= rd_addr ;
end generate ;
gen_sync_rd : if SYNC_RD generate
fifo_rd <= rd;
rd_addr_adv <= (rd_addr + 1) when fifo_rd = '1' else
rd_addr ;
end generate ;
gen_async_wr : if NOT SYNC_WR generate
process(resetn, clk)
begin
if resetn = '0' then
wr_old <= '0' ;
elsif clk'event and clk = '1' then
wr_old <= wr ;
end if ;
end process ;
wr_falling_edge <= ((NOT wr) AND wr_old) ;
fifo_wr <= wr_falling_edge ;
end generate ;
gen_sync_wr : if SYNC_WR generate
fifo_wr <= wr ;
end generate ;
--rd process
process(clk, resetn)
begin
if resetn = '0' then
rd_addr <= (others => '0') ;
elsif clk'event and clk = '1' then
if sraz = '1' then
rd_addr <= (others => '0');
elsif fifo_rd = '1' and nb_available_t /= 0 then
rd_addr <= rd_addr + 1;
end if ;
end if ;
end process ;
-- wr process
process(clk, resetn)
begin
if resetn = '0' then
wr_addr <= (others => '0') ;
elsif clk'event and clk = '1' then
if sraz = '1' then
wr_addr <= (others => '0');
elsif fifo_wr = '1' and nb_available_t /= N then
wr_addr <= wr_addr + 1;
end if ;
end if ;
end process ;
-- nb available process
process(clk, resetn)
begin
if resetn = '0' then
nb_available_t <= (others => '0') ;
elsif clk'event and clk = '1' then
if sraz = '1' then
nb_available_t <= (others => '0') ;
elsif fifo_wr = '1' and fifo_rd = '0' and nb_available_t /= N then
nb_available_t <= nb_available_t + 1 ;
elsif fifo_rd = '1' and fifo_wr = '0' and nb_available_t /= 0 then
nb_available_t <= nb_available_t - 1 ;
end if ;
end if ;
end process ;
nb_available <= nb_available_t ;
empty <= '1' when nb_available_t = 0 else
'1' when nb_available_t = 1 and fifo_rd = '1' else -- must check if its useful ...
'0' ;
full <= '1' when nb_available_t = N else
'1' when nb_available_t = N - 1 and fifo_wr = '1' else -- must check if its useful ...
'0' ;
wr_data <= fifo_wr ;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:LAAS-CNRS
-- Author:Jonathan Piat <[email protected]>
--
-- Create Date: 15:37:36 06/18/2012
-- Design Name:
-- Module Name: dp_fifo - Behavioral
-- Project Name:
-- Target Devices: Spartan 6
-- Tool versions: ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
library work ;
use work.logi_primitive_pack.all ;
use work.logi_utils_pack.all ;
--! dual port ram based fifo for fast logic to logic communication
entity dp_fifo is
generic(N : natural := 128 ; --! depth of the fifo
W : positive := 16; --! width of the fifo
SYNC_WR : boolean := false;
SYNC_RD : boolean := false
);
port(
clk, resetn, sraz : in std_logic; --! system clock, asynchronous and synchronous reset
wr, rd : in std_logic; --! fifo write and read signal
empty, full : out std_logic ; --! fifo stat signals
data_out : out std_logic_vector((W - 1) downto 0 ); --! data output of fifo
data_in : in std_logic_vector((W - 1) downto 0 ); --! data input of fifo
nb_available : out unsigned(nbit(N) downto 0 ) --! number of available tokens in fifo
);
end dp_fifo;
architecture Behavioral of dp_fifo is
constant std_fifo_size : std_logic_vector(nbit(N) downto 0 ) := std_logic_vector(to_unsigned(N, nbit(N) + 1));
signal rd_addr, rd_addr_adv, wr_addr: std_logic_vector((nbit(N) - 1) downto 0) ;
signal nb_free_t, nb_available_t : unsigned(nbit(N) downto 0 ) ;
signal slv_nb_available_t : std_logic_vector(nbit(N) downto 0 ) ;
signal fifo_out, fifo_in : std_logic_vector((W - 1 ) downto 0) ;
signal rd_old, wr_old, wr_data, rd_data, one_turn, latch_data : std_logic ;
signal rd_rising_edge, wr_rising_edge : std_logic ;
signal rd_falling_edge, wr_falling_edge : std_logic ;
signal en_available_counter, up_downn_available_counter : std_logic ;
signal en_free_counter, up_downn_free_counter, counter_load : std_logic ;
signal fifo_wr, fifo_rd : std_logic ;
begin
dp_ram0 : dpram_NxN
generic map(SIZE => N , NBIT => W, ADDR_WIDTH => nbit(N))
port map(
clk => clk ,
we => wr_data ,
di => data_in ,
a => wr_addr,
dpra => rd_addr_adv ,
dpo => fifo_out
);
data_out <= fifo_out ;
gen_async_rd : if NOT SYNC_RD generate
process(resetn, clk)
begin
if resetn = '0' then
rd_old <= '0' ;
elsif clk'event and clk = '1' then
rd_old <= rd ;
end if ;
end process ;
rd_falling_edge <= ((NOT rd) AND rd_old);
fifo_rd <= rd_falling_edge ;
rd_addr_adv <= rd_addr ;
end generate ;
gen_sync_rd : if SYNC_RD generate
fifo_rd <= rd;
rd_addr_adv <= (rd_addr + 1) when fifo_rd = '1' else
rd_addr ;
end generate ;
gen_async_wr : if NOT SYNC_WR generate
process(resetn, clk)
begin
if resetn = '0' then
wr_old <= '0' ;
elsif clk'event and clk = '1' then
wr_old <= wr ;
end if ;
end process ;
wr_falling_edge <= ((NOT wr) AND wr_old) ;
fifo_wr <= wr_falling_edge ;
end generate ;
gen_sync_wr : if SYNC_WR generate
fifo_wr <= wr ;
end generate ;
--rd process
process(clk, resetn)
begin
if resetn = '0' then
rd_addr <= (others => '0') ;
elsif clk'event and clk = '1' then
if sraz = '1' then
rd_addr <= (others => '0');
elsif fifo_rd = '1' and nb_available_t /= 0 then
rd_addr <= rd_addr + 1;
end if ;
end if ;
end process ;
-- wr process
process(clk, resetn)
begin
if resetn = '0' then
wr_addr <= (others => '0') ;
elsif clk'event and clk = '1' then
if sraz = '1' then
wr_addr <= (others => '0');
elsif fifo_wr = '1' and nb_available_t /= N then
wr_addr <= wr_addr + 1;
end if ;
end if ;
end process ;
-- nb available process
process(clk, resetn)
begin
if resetn = '0' then
nb_available_t <= (others => '0') ;
elsif clk'event and clk = '1' then
if sraz = '1' then
nb_available_t <= (others => '0') ;
elsif fifo_wr = '1' and fifo_rd = '0' and nb_available_t /= N then
nb_available_t <= nb_available_t + 1 ;
elsif fifo_rd = '1' and fifo_wr = '0' and nb_available_t /= 0 then
nb_available_t <= nb_available_t - 1 ;
end if ;
end if ;
end process ;
nb_available <= nb_available_t ;
empty <= '1' when nb_available_t = 0 else
'1' when nb_available_t = 1 and fifo_rd = '1' else -- must check if its useful ...
'0' ;
full <= '1' when nb_available_t = N else
'1' when nb_available_t = N - 1 and fifo_wr = '1' else -- must check if its useful ...
'0' ;
wr_data <= fifo_wr ;
end Behavioral;
|
--------------------------------------------------------------------
-- Entity: MultiIO_APB
-- File: MultiIO_APB.vhd
-- Author: Thomas Ameseder, Gleichmann Electronics
-- Based on an orginal version by [email protected]
--
-- Description: APB Multiple digital I/O for minimal User Interface
--------------------------------------------------------------------
-- Functionality:
-- 8 LEDs, active low or high, r/w
-- dual 7Segment, active low or high, w only
-- 8 DIL Switches, active low or high, r only
-- 8 Buttons, active low or high, r only, with IRQ enables
--------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gleichmann;
use gleichmann.spi.all;
use gleichmann.i2c.all;
use gleichmann.miscellaneous.all;
use gleichmann.multiio.all;
-- pragma translate_off
use std.textio.all;
-- pragma translate_on
entity MultiIO_APB is
generic (
hpe_version: integer := 0; -- adapt multiplexing for different boards
pindex : integer := 0; -- Leon-Index
paddr : integer := 0; -- Leon-Address
pmask : integer := 16#FFF#; -- Leon-Mask
pirq : integer := 0; -- Leon-IRQ
clk_freq_in : integer := 25_000_000; -- Leons clock to calculate timings
led7act : std_logic := '0'; -- active level for 7Segment
ledact : std_logic := '0'; -- active level for LEDs
switchact : std_logic := '1'; -- active level for LED's
buttonact : std_logic := '1'; -- active level for LED's
n_switches : integer := 8; -- number of switches that are driven
n_leds : integer := 8 -- number of LEDs that are driven
);
port (
rst_n : in std_ulogic; -- global Reset, active low
clk : in std_ulogic; -- global Clock
apbi : in apb_slv_in_type; -- APB-Input
apbo : out apb_slv_out_type; -- APB-Output
MultiIO_in : in MultiIO_in_type; -- MultIO-Inputs
MultiIO_out : out MultiIO_out_type -- MultiIO-Outputs
);
end entity;
architecture Implementation of MultiIO_APB is ----------------------
constant VERSION : std_logic_vector(31 downto 0) := x"EA_07_12_06";
constant REVISION : integer := 1;
constant MUXMAX : integer := 7;
constant VCC : std_logic_vector(31 downto 0) := (others => '1');
constant GND : std_logic_vector(31 downto 0) := (others => '0');
signal Enable1ms : boolean;
signal MUXCounter : integer range 0 to MUXMAX-1;
signal clkgen_mclk : std_ulogic;
signal clkgen_bclk : std_ulogic;
signal clkgen_sclk : std_ulogic;
signal clkgen_lrclk : std_ulogic;
type state_t is (WAIT_FOR_SYNC,READY,WAIT_FOR_ACK);
signal state,next_state : state_t;
signal Strobe,next_Strobe : std_ulogic;
-- status signals of the i2s core for upper-level state machine
signal SampleAck, WaitForSample : std_ulogic;
signal samplereg : std_ulogic_vector(N_CODECI2SBITS-1 downto 0);
constant pconfig : apb_config_type := (
0 => ahb_device_reg (VENDOR_GLEICHMANN, GLEICHMANN_HIFC, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask)
);
type MultiIOregisters is
record
ledreg : std_logic_vector(31 downto 0); -- LEDs
led7reg : std_logic_vector(31 downto 0); -- Dual 7Segment LEDs
codecreg : std_logic_vector(31 downto 0);
codecreg2 : std_logic_vector(31 downto 0);
-- Switches in
sw_inreg : std_logic_vector(31 downto 0);
-- ASCII value of input button
btn_inreg : std_logic_vector(31 downto 0);
irqenareg : std_logic_vector(31 downto 0); -- IRQ enables for Buttons
btn_irqs : std_logic_vector(31 downto 0); -- IRQs from each Button
new_data : std_ulogic;
-- new_data_valid : std_ulogic;
lcdreg : std_logic_vector(31 downto 0); -- LCD instruction
--cb1_in_reg : std_logic_vector(31 downto 0);
--cb1_out_reg : std_logic_vector(31 downto 0);
-- cb3_in_reg : std_logic_vector(31 downto 0);
--cb4_in2_reg : std_logic_vector(31 downto 0);
-- cb3_out_reg : std_logic_vector(31 downto 0);
--cb4_out2_reg : std_logic_vector(31 downto 0);
exp_in_reg : std_logic_vector(31 downto 0);
exp_out_reg : std_logic_vector(31 downto 0);
hsc_out_reg : std_logic_vector(31 downto 0);
hsc_in_reg : std_logic_vector(31 downto 0);
end record;
signal r, rin : MultiIOregisters; -- register sets
signal Key : std_logic_vector(7 downto 0); -- ASCII value of button
-- character representation of the key (for simulation purposes)
signal KeyVal : character;
signal OldColumnRow1 : std_logic_vector(6 downto 0); -- for key debounce
signal OldColumnRow2 : std_logic_vector(6 downto 0); -- for key debounce
begin
reg_rw : process(MUXCounter, MultiIO_in, apbi, key, r, rst_n)
variable readdata : std_logic_vector(31 downto 0); -- system bus width
variable irqs : std_logic_vector(31 downto 0); -- system IRQs width
variable v : MultiIOregisters; -- register set
begin
v := r;
-- reset registers
if rst_n = '0' then
-- lower half of LEDs on
v.ledreg := (others => '0');
v.ledreg(3 downto 0) := "1111";
v.led7reg := (others => '0');
v.led7reg(15 downto 0) := X"38_4F"; -- show "L3" Leon3 on 7Segments
v.codecreg := (others => '0');
v.codecreg2 := (others => '0');
v.irqenareg := (others => '0'); -- IRQs disable
v.btn_inreg := (others => '0');
v.sw_inreg := (others => '0');
-- new data flag off
v.new_data := '0';
-- v.new_data_valid := '0';
v.lcdreg := (others => '0');
-- v.cb3_in_reg := (others => '0');
--v.cb4_in2_reg := (others => '0');
-- v.cb3_out_reg := (others => '0');
--v.cb4_out2_reg := (others => '0');
v.exp_in_reg := (others => '0');
v.exp_out_reg := (others => '0');
v.hsc_in_reg := (others => '0');
v.hsc_out_reg := (others => '0');
end if;
-- get switches and buttons
if switchact = '1' then
v.sw_inreg(N_SWITCHES-1 downto 0) := MultiIO_in.switch_in;
else
v.sw_inreg(N_SWITCHES-1 downto 0) := not MultiIO_in.switch_in;
end if;
v.btn_inreg(7 downto 0) := key;
v.btn_irqs := (others => '0');
---------------------------------------------------------------------------
-- TO BE ALTERED
---------------------------------------------------------------------------
-- set local button-IRQs
for i in 0 to v.btn_irqs'left loop
-- detect low-to-high transition
if (v.btn_inreg(i) = '1') and (r.btn_inreg(i) = '0') then
-- set local IRQs if IRQ enabled
v.btn_irqs(i) := v.btn_inreg(i) and r.irqenareg(i);
else
-- clear local IRQs
v.btn_irqs(i) := '0';
end if;
end loop;
---------------------------------------------------------------------------
-- read registers
readdata := (others => 'X');
case conv_integer(apbi.paddr(6 downto 2)) is
when 0 => readdata := r.ledreg; -- LEDs
when 1 => readdata := r.led7reg; -- seven segment
when 2 => readdata := r.codecreg; -- codec command register
when 3 => readdata := r.codecreg2; -- codec i2s register
when 4 => readdata := r.sw_inreg; -- switches
when 5 => readdata := r.btn_inreg; -- buttons
when 6 => readdata := r.irqenareg; -- IRQ enables
when 7 => readdata := conv_std_logic_vector(pirq, 32); -- IRQ#
when 8 => readdata := version; -- version
when 9 => readdata := r.lcdreg; -- LCD data
when 10 => readdata := r.exp_out_reg; -- expansion connector out
when 11 => readdata := r.exp_in_reg; -- expansion connector in
when 12 => readdata := r.hsc_out_reg;
when 13 => readdata := r.hsc_in_reg;
--when 14 => readdata := r.cb4_out1_reg; -- childboard4 connector out
--when 15 => readdata := r.cb4_out2_reg; -- childboard4 connector out
-- when 14 => readdata := r.cb3_in_reg; -- childboard3 connector in
-- when 15 => readdata := r.cb3_out_reg; -- childboard3 connector out
--when 14 => readdata := r.cb1_out_reg; -- childboard1 connector out
--when 15 => readdata := r.cb1_in_reg; -- childboard1 connector in
when others => null;
end case;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case conv_integer(apbi.paddr(6 downto 2)) is
when 0 => v.ledreg :=
GND(31 downto N_LEDS) &
apbi.pwdata(N_LEDS-1 downto 0); -- write LEDs
when 1 => v.led7reg :=
GND(31 downto N_SEVSEGBITS) &
apbi.pwdata(N_SEVSEGBITS-1 downto 0); -- write 7Segment
when 2 => v.codecreg :=
GND(31 downto N_CODECBITS) &
apbi.pwdata(N_CODECBITS-1 downto 0);
when 3 => v.codecreg2 :=
GND(31 downto N_CODECI2SBITS) &
apbi.pwdata(N_CODECI2SBITS-1 downto 0);
when 6 => v.irqenareg :=
GND(31 downto N_BUTTONS) &
apbi.pwdata(N_BUTTONS-1 downto 0);
when 9 => v.lcdreg :=
GND(31 downto N_LCDBITS) &
apbi.pwdata(N_LCDBITS-1 downto 0);
-- signal that new data has arrived
-- v.new_data_valid := '0';
v.new_data := '1';
when 10 => v.exp_out_reg :=
GND(31 downto N_EXPBITS/2) &
-- bit(N_EXPBITS) holds enable signal
apbi.pwdata(N_EXPBITS/2-1 downto 0);
when 12 => v.hsc_out_reg :=
GND(31 downto N_HSCBITS) &
apbi.pwdata(N_HSCBITS-1 downto 0);
--when 14 => v.cb4_out1_reg :=
-- apbi.pwdata(31 downto 0);
-- when 15 => v.cb3_out_reg :=
-- apbi.pwdata(31 downto 0);
--when 14 => v.exp_out_reg :=
-- GND(31 downto 13) &
-- -- bit(N_EXPBITS) holds enable signal
-- apbi.pwdata(12 downto 0);
when others => null;
end case;
end if;
-- set PIRQ
irqs := (others => '0');
for i in 0 to v.btn_irqs'left loop
-- set IRQ if button-i pressed and IRQ enabled
irqs(pirq) := irqs(pirq) or r.btn_irqs(i);
end loop;
if ledact = '1' then
MultiIO_out.led_out <= r.ledreg(N_LEDS-1 downto 0); -- not inverted
else
MultiIO_out.led_out <= not r.ledreg(N_LEDS-1 downto 0); -- inverted
end if;
-- disable seven segment and LC display by default
-- MultiIO_out.lcd_enable <= '0';
MultiIO_out.lcd_rw <= r.lcdreg(8);
MultiIO_out.lcd_regsel <= r.lcdreg(9);
-- reset new lcd data flag
-- will be enabled when new data are written to the LCD register
if MUXCounter = 4 then
v.new_data := '0';
-- v.serviced := '1';
end if;
-- register inputs from expansion connector
v.exp_in_reg(N_EXPBITS/2-1 downto 0) := MultiIO_in.exp_in;
MultiIO_out.exp_out <= r.exp_out_reg(N_EXPBITS/2-1 downto 0);
-- high-speed connector
v.hsc_in_reg(N_HSCBITS-1 downto 0) := MultiIO_in.hsc_in;
MultiIO_out.hsc_out <= r.hsc_out_reg(N_HSCBITS-1 downto 0);
-- configure control port of audio codec for SPI mode
MultiIO_out.codec_mode <= '1';
apbo.prdata <= readdata; -- output data to Leon
apbo.pirq <= irqs; -- output IRQs to Leon
apbo.pindex <= pindex; -- output index to Leon
rin <= v; -- update registers
end process;
apbo.pconfig <= pconfig; -- output config to Leon
regs : process(clk) -- update registers
begin
if rising_edge(clk) then
r <= rin;
end if;
end process;
KeyBoard : process(clk, rst_n)
variable ColumnStrobe : std_logic_vector(2 downto 0);
variable FirstTime : boolean;
variable NewColumnRow : std_logic_vector(6 downto 0);
begin
if rst_n = '0' then
MultiIO_out.column_out <= (others => '0'); -- all column off
Key <= X"40"; -- default '@' after Reset and no key pressed
OldColumnRow1 <= "1111111";
OldColumnRow2 <= "1110011";
ColumnStrobe := "001";
FirstTime := true;
elsif rising_edge(clk) then
if Enable1ms then
if MultiIO_in.row_in = "0000" then -- no key pressed
ColumnStrobe := ColumnStrobe(1) & ColumnStrobe(0) & ColumnStrobe(2); -- rotate column
MultiIO_out.column_out <= ColumnStrobe;
if not FirstTime then
Key <= X"3F"; -- no key pressed '?'
end if;
else -- key pressed
OldColumnRow2 <= OldColumnRow1;
-- check whether button inputs produce a high or a
-- low level, then assign these inputs in order that
-- they can be decoded into ASCII format
if buttonact = '1' then
NewColumnRow := ColumnStrobe & MultiIO_in.row_in;
else
NewColumnRow := ColumnStrobe & not MultiIO_in.row_in;
end if;
OldColumnRow1 <= NewColumnRow;
if (ColumnStrobe & MultiIO_in.row_in = OldColumnRow1) and
(OldColumnRow1 = OldColumnRow2)
then -- debounced
FirstTime := false; -- 1st valid key pressed
case OldColumnRow2 is -- decode keys into ascii characters
when "0010001" => Key <= x"31"; -- 1
when "0010010" => Key <= x"34"; -- 4
when "0010100" => Key <= x"37"; -- 7
when "0011000" => Key <= x"43"; -- C
when "0100001" => Key <= x"32"; -- 2
when "0100010" => Key <= x"35"; -- 5
when "0100100" => Key <= x"38"; -- 8
when "0101000" => Key <= x"30"; -- 0
when "1000001" => Key <= x"33"; -- 3
when "1000010" => Key <= x"36"; -- 6
when "1000100" => Key <= x"39"; -- 9
when "1001000" => Key <= x"45"; -- E
when others => Key <= x"39"; -- ? -- more than one key pressed
end case;
else
Key <= x"3D"; -- '=' -- bouncing
end if; -- debounce
end if; -- MultiIO_in.row_in
end if; -- Enable1ms
end if; -- rst_n
end process KeyBoard;
Multiplex3Sources : if hpe_version = midi generate
Multiplex : process(MUXCounter, r)
begin
-- disable LED output by default
MultiIO_out.led_enable <= '0' xnor ledact;
-- disable 7-segment display by default
MultiIO_out.led_ca_out <= "00" xnor (led7act & led7act);
-- set enable signal in the middle of LCD timeslots
if MUXCounter = 3 then
MultiIO_out.lcd_enable <= '1';
else
MultiIO_out.lcd_enable <= '0';
end if;
case MUXCounter is
when 0 | 1 =>
-- output logical value according to active level of the 7segment display
MultiIO_out.led_a_out <= r.led7reg(MUXCounter*8 + 0) xnor led7act;
MultiIO_out.led_b_out <= r.led7reg(MUXCounter*8 + 1) xnor led7act;
MultiIO_out.led_c_out <= r.led7reg(MUXCounter*8 + 2) xnor led7act;
MultiIO_out.led_d_out <= r.led7reg(MUXCounter*8 + 3) xnor led7act;
MultiIO_out.led_e_out <= r.led7reg(MUXCounter*8 + 4) xnor led7act;
MultiIO_out.led_f_out <= r.led7reg(MUXCounter*8 + 5) xnor led7act;
MultiIO_out.led_g_out <= r.led7reg(MUXCounter*8 + 6) xnor led7act;
MultiIO_out.led_dp_out <= r.led7reg(MUXCounter*8 + 7) xnor led7act;
-- selectively enable the current digit
for i in 0 to 1 loop
if i = MUXCounter then
MultiIO_out.led_ca_out(i) <= '1' xnor led7act;
else
MultiIO_out.led_ca_out(i) <= '0' xnor led7act;
end if;
end loop; -- i
when 2 | 3 | 4 =>
MultiIO_out.led_a_out <= r.lcdreg(0);
MultiIO_out.led_b_out <= r.lcdreg(1);
MultiIO_out.led_c_out <= r.lcdreg(2);
MultiIO_out.led_d_out <= r.lcdreg(3);
MultiIO_out.led_e_out <= r.lcdreg(4);
MultiIO_out.led_f_out <= r.lcdreg(5);
MultiIO_out.led_g_out <= r.lcdreg(6);
MultiIO_out.led_dp_out <= r.lcdreg(7);
when 5 | 6 =>
MultiIO_out.led_enable <= '1' xnor ledact;
MultiIO_out.led_a_out <= r.ledreg(0) xnor ledact;
MultiIO_out.led_b_out <= r.ledreg(1) xnor ledact;
MultiIO_out.led_c_out <= r.ledreg(2) xnor ledact;
MultiIO_out.led_d_out <= r.ledreg(3) xnor ledact;
MultiIO_out.led_e_out <= r.ledreg(4) xnor ledact;
MultiIO_out.led_f_out <= r.ledreg(5) xnor ledact;
MultiIO_out.led_g_out <= r.ledreg(6) xnor ledact;
MultiIO_out.led_dp_out <= r.ledreg(7) xnor ledact;
when others =>
null;
end case;
end process Multiplex;
end generate Multiplex3Sources;
Multiplex2Sources : if hpe_version /= midi generate
Multiplex : process(MUXCounter, r)
begin
-- disable LED output by default
MultiIO_out.led_enable <= '0' xnor ledact;
-- disable 7-segment display by default
MultiIO_out.led_ca_out <= "00" xnor (led7act & led7act);
-- set enable signal in the middle of LCD timeslots
if MUXCounter = 3 then
MultiIO_out.lcd_enable <= '1';
else
MultiIO_out.lcd_enable <= '0';
end if;
case MUXCounter is
when 0 | 1 =>
-- output logical value according to active level of the 7segment display
MultiIO_out.led_a_out <= r.led7reg(MUXCounter*8 + 0) xnor led7act;
MultiIO_out.led_b_out <= r.led7reg(MUXCounter*8 + 1) xnor led7act;
MultiIO_out.led_c_out <= r.led7reg(MUXCounter*8 + 2) xnor led7act;
MultiIO_out.led_d_out <= r.led7reg(MUXCounter*8 + 3) xnor led7act;
MultiIO_out.led_e_out <= r.led7reg(MUXCounter*8 + 4) xnor led7act;
MultiIO_out.led_f_out <= r.led7reg(MUXCounter*8 + 5) xnor led7act;
MultiIO_out.led_g_out <= r.led7reg(MUXCounter*8 + 6) xnor led7act;
MultiIO_out.led_dp_out <= r.led7reg(MUXCounter*8 + 7) xnor led7act;
-- selectively enable the current digit
for i in 0 to 1 loop
if i = MUXCounter then
MultiIO_out.led_ca_out(i) <= '1' xnor led7act;
else
MultiIO_out.led_ca_out(i) <= '0' xnor led7act;
end if;
end loop; -- i
when others =>
MultiIO_out.led_a_out <= r.lcdreg(0);
MultiIO_out.led_b_out <= r.lcdreg(1);
MultiIO_out.led_c_out <= r.lcdreg(2);
MultiIO_out.led_d_out <= r.lcdreg(3);
MultiIO_out.led_e_out <= r.lcdreg(4);
MultiIO_out.led_f_out <= r.lcdreg(5);
MultiIO_out.led_g_out <= r.lcdreg(6);
MultiIO_out.led_dp_out <= r.lcdreg(7);
end case;
end process Multiplex;
end generate Multiplex2Sources;
-- generate prescaler signal every 100 ms
-- control MUXCounter according to input and board type
Count1ms : process(clk, rst_n)
constant divider100ms : integer := clk_freq_in / 10_000;
variable frequency_counter : integer range 0 to Divider100ms;
begin
if rst_n = '0' then
frequency_counter := Divider100ms;
Enable1ms <= false;
MUXCounter <= 0;
elsif rising_edge(clk) then
if frequency_counter = 0 then -- 1-ms counter has expired
frequency_counter := Divider100ms;
Enable1ms <= true;
if (hpe_version = midi) then
-- skip LCD control sequence and go to
-- LED control
if (MUXCounter = 1 and r.new_data = '0') then
MUXCounter <= 5;
-- overflow at maximum counter value for Hpe_midi
elsif MUXCounter = MUXMAX-1 then
MUXCounter <= 0;
else
MUXCounter <= MUXCounter + 1;
end if;
elsif (hpe_version /= midi) then
-- skip LCD control sequence and go back to
-- 7-segment control
if (MUXCounter = 1 and r.new_data = '0') then
MUXCounter <= 0;
-- overflow at maximum counter value for Hpe_mini
elsif MUXCounter = MUXMAX-3 then
MUXCounter <= 0;
else
MUXCounter <= MUXCounter + 1;
end if;
end if;
else
frequency_counter := frequency_counter - 1;
Enable1ms <= false;
end if;
end if;
end process;
---------------------------------------------------------------------------------------
-- AUDIO CODEC SECTION
---------------------------------------------------------------------------------------
tlv320aic23b_audio : if hpe_version = mini_altera generate
-- audio clock generation
clk_gen : ClockGenerator
port map (
Clk => clk,
Reset => rst_n,
omclk => clkgen_mclk,
obclk => clkgen_bclk,
osclk => clkgen_sclk,
olrcout => clkgen_lrclk);
-- drive clock signals by clock generator
MultiIO_out.CODEC_SCLK <= clkgen_sclk;
MultiIO_out.CODEC_MCLK <= clkgen_mclk;
MultiIO_out.CODEC_BCLK <= clkgen_bclk;
MultiIO_out.CODEC_LRCIN <= clkgen_lrclk;
MultiIO_out.CODEC_LRCOUT <= clkgen_lrclk;
-- SPI control interface
spi_xmit_1 : spi_xmit
generic map (
data_width => N_CODECBITS)
port map (
clk_i => clkgen_SCLK,
rst_i => rst_n,
data_i => r.codecreg(N_CODECBITS-1 downto 0),
CODEC_SDIN => MultiIO_out.CODEC_SDIN,
CODEC_CS => MultiIO_out.CODEC_CS);
-- I2C data interface
ParToI2s_1 : ParToI2s
generic map (
SampleSize_g => N_CODECI2SBITS)
port map (
Clk_i => clk,
Reset_i => rst_n,
SampleLeft_i => SampleReg,
SampleRight_i => SampleReg,
StrobeLeft_i => Strobe,
StrobeRight_i => Strobe,
SampleAck_o => SampleAck,
WaitForSample_o => WaitForSample,
SClk_i => clkgen_sclk,
LRClk_i => clkgen_lrclk,
SdnyData_o => MultiIO_out.CODEC_DIN);
audio_ctrl_sm : process(SampleAck, WaitForSample, state)
begin
next_state <= state;
next_Strobe <= '0';
case state is
when WAIT_FOR_SYNC =>
if WaitForSample = '1' then
next_state <= READY;
end if;
when READY =>
next_state <= WAIT_FOR_ACK;
next_Strobe <= '1';
when WAIT_FOR_ACK =>
if SampleAck = '1' then
next_state <= READY;
end if;
when others =>
next_state <= WAIT_FOR_SYNC;
end case;
end process;
audio_ctrl_reg : process(clk, rst_n)
begin
if rst_n = '0' then -- asynchronous reset
state <= WAIT_FOR_SYNC;
Strobe <= '0';
SampleReg <= (others => '0');
elsif clk'event and clk = '1' then
state <= next_state;
Strobe <= next_Strobe;
if (next_Strobe) = '1' then
-- if Mode = '0' then
-- SampleReg <= std_ulogic_vector(unsigned(AudioSample)- X"80");
-- else
-- SampleReg <= AudioSample;
-- end if;
SampleReg <= std_ulogic_vector(r.codecreg2(N_CODECI2SBITS-1 downto 0));
end if;
end if;
end process;
end generate tlv320aic23b_audio;
---------------------------------------------------------------------------------------
-- DEBUG SECTION
---------------------------------------------------------------------------------------
-- pragma translate_off
KeyVal <=
ascii2char(conv_integer(Key)) when
(conv_integer(Key) >= 16#30#) and (conv_integer(Key) <= 16#46#)
else 'U';
bootmsg : report_version
generic map ("MultiIO_APB6:" & tost(pindex) &
", Human Interface Controller rev " & tost(REVISION) &
", IRQ " & tost(pirq));
-- pragma translate_on
end architecture;
|
--------------------------------------------------------------------
-- Entity: MultiIO_APB
-- File: MultiIO_APB.vhd
-- Author: Thomas Ameseder, Gleichmann Electronics
-- Based on an orginal version by [email protected]
--
-- Description: APB Multiple digital I/O for minimal User Interface
--------------------------------------------------------------------
-- Functionality:
-- 8 LEDs, active low or high, r/w
-- dual 7Segment, active low or high, w only
-- 8 DIL Switches, active low or high, r only
-- 8 Buttons, active low or high, r only, with IRQ enables
--------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gleichmann;
use gleichmann.spi.all;
use gleichmann.i2c.all;
use gleichmann.miscellaneous.all;
use gleichmann.multiio.all;
-- pragma translate_off
use std.textio.all;
-- pragma translate_on
entity MultiIO_APB is
generic (
hpe_version: integer := 0; -- adapt multiplexing for different boards
pindex : integer := 0; -- Leon-Index
paddr : integer := 0; -- Leon-Address
pmask : integer := 16#FFF#; -- Leon-Mask
pirq : integer := 0; -- Leon-IRQ
clk_freq_in : integer := 25_000_000; -- Leons clock to calculate timings
led7act : std_logic := '0'; -- active level for 7Segment
ledact : std_logic := '0'; -- active level for LEDs
switchact : std_logic := '1'; -- active level for LED's
buttonact : std_logic := '1'; -- active level for LED's
n_switches : integer := 8; -- number of switches that are driven
n_leds : integer := 8 -- number of LEDs that are driven
);
port (
rst_n : in std_ulogic; -- global Reset, active low
clk : in std_ulogic; -- global Clock
apbi : in apb_slv_in_type; -- APB-Input
apbo : out apb_slv_out_type; -- APB-Output
MultiIO_in : in MultiIO_in_type; -- MultIO-Inputs
MultiIO_out : out MultiIO_out_type -- MultiIO-Outputs
);
end entity;
architecture Implementation of MultiIO_APB is ----------------------
constant VERSION : std_logic_vector(31 downto 0) := x"EA_07_12_06";
constant REVISION : integer := 1;
constant MUXMAX : integer := 7;
constant VCC : std_logic_vector(31 downto 0) := (others => '1');
constant GND : std_logic_vector(31 downto 0) := (others => '0');
signal Enable1ms : boolean;
signal MUXCounter : integer range 0 to MUXMAX-1;
signal clkgen_mclk : std_ulogic;
signal clkgen_bclk : std_ulogic;
signal clkgen_sclk : std_ulogic;
signal clkgen_lrclk : std_ulogic;
type state_t is (WAIT_FOR_SYNC,READY,WAIT_FOR_ACK);
signal state,next_state : state_t;
signal Strobe,next_Strobe : std_ulogic;
-- status signals of the i2s core for upper-level state machine
signal SampleAck, WaitForSample : std_ulogic;
signal samplereg : std_ulogic_vector(N_CODECI2SBITS-1 downto 0);
constant pconfig : apb_config_type := (
0 => ahb_device_reg (VENDOR_GLEICHMANN, GLEICHMANN_HIFC, 0, REVISION, pirq),
1 => apb_iobar(paddr, pmask)
);
type MultiIOregisters is
record
ledreg : std_logic_vector(31 downto 0); -- LEDs
led7reg : std_logic_vector(31 downto 0); -- Dual 7Segment LEDs
codecreg : std_logic_vector(31 downto 0);
codecreg2 : std_logic_vector(31 downto 0);
-- Switches in
sw_inreg : std_logic_vector(31 downto 0);
-- ASCII value of input button
btn_inreg : std_logic_vector(31 downto 0);
irqenareg : std_logic_vector(31 downto 0); -- IRQ enables for Buttons
btn_irqs : std_logic_vector(31 downto 0); -- IRQs from each Button
new_data : std_ulogic;
-- new_data_valid : std_ulogic;
lcdreg : std_logic_vector(31 downto 0); -- LCD instruction
--cb1_in_reg : std_logic_vector(31 downto 0);
--cb1_out_reg : std_logic_vector(31 downto 0);
-- cb3_in_reg : std_logic_vector(31 downto 0);
--cb4_in2_reg : std_logic_vector(31 downto 0);
-- cb3_out_reg : std_logic_vector(31 downto 0);
--cb4_out2_reg : std_logic_vector(31 downto 0);
exp_in_reg : std_logic_vector(31 downto 0);
exp_out_reg : std_logic_vector(31 downto 0);
hsc_out_reg : std_logic_vector(31 downto 0);
hsc_in_reg : std_logic_vector(31 downto 0);
end record;
signal r, rin : MultiIOregisters; -- register sets
signal Key : std_logic_vector(7 downto 0); -- ASCII value of button
-- character representation of the key (for simulation purposes)
signal KeyVal : character;
signal OldColumnRow1 : std_logic_vector(6 downto 0); -- for key debounce
signal OldColumnRow2 : std_logic_vector(6 downto 0); -- for key debounce
begin
reg_rw : process(MUXCounter, MultiIO_in, apbi, key, r, rst_n)
variable readdata : std_logic_vector(31 downto 0); -- system bus width
variable irqs : std_logic_vector(31 downto 0); -- system IRQs width
variable v : MultiIOregisters; -- register set
begin
v := r;
-- reset registers
if rst_n = '0' then
-- lower half of LEDs on
v.ledreg := (others => '0');
v.ledreg(3 downto 0) := "1111";
v.led7reg := (others => '0');
v.led7reg(15 downto 0) := X"38_4F"; -- show "L3" Leon3 on 7Segments
v.codecreg := (others => '0');
v.codecreg2 := (others => '0');
v.irqenareg := (others => '0'); -- IRQs disable
v.btn_inreg := (others => '0');
v.sw_inreg := (others => '0');
-- new data flag off
v.new_data := '0';
-- v.new_data_valid := '0';
v.lcdreg := (others => '0');
-- v.cb3_in_reg := (others => '0');
--v.cb4_in2_reg := (others => '0');
-- v.cb3_out_reg := (others => '0');
--v.cb4_out2_reg := (others => '0');
v.exp_in_reg := (others => '0');
v.exp_out_reg := (others => '0');
v.hsc_in_reg := (others => '0');
v.hsc_out_reg := (others => '0');
end if;
-- get switches and buttons
if switchact = '1' then
v.sw_inreg(N_SWITCHES-1 downto 0) := MultiIO_in.switch_in;
else
v.sw_inreg(N_SWITCHES-1 downto 0) := not MultiIO_in.switch_in;
end if;
v.btn_inreg(7 downto 0) := key;
v.btn_irqs := (others => '0');
---------------------------------------------------------------------------
-- TO BE ALTERED
---------------------------------------------------------------------------
-- set local button-IRQs
for i in 0 to v.btn_irqs'left loop
-- detect low-to-high transition
if (v.btn_inreg(i) = '1') and (r.btn_inreg(i) = '0') then
-- set local IRQs if IRQ enabled
v.btn_irqs(i) := v.btn_inreg(i) and r.irqenareg(i);
else
-- clear local IRQs
v.btn_irqs(i) := '0';
end if;
end loop;
---------------------------------------------------------------------------
-- read registers
readdata := (others => 'X');
case conv_integer(apbi.paddr(6 downto 2)) is
when 0 => readdata := r.ledreg; -- LEDs
when 1 => readdata := r.led7reg; -- seven segment
when 2 => readdata := r.codecreg; -- codec command register
when 3 => readdata := r.codecreg2; -- codec i2s register
when 4 => readdata := r.sw_inreg; -- switches
when 5 => readdata := r.btn_inreg; -- buttons
when 6 => readdata := r.irqenareg; -- IRQ enables
when 7 => readdata := conv_std_logic_vector(pirq, 32); -- IRQ#
when 8 => readdata := version; -- version
when 9 => readdata := r.lcdreg; -- LCD data
when 10 => readdata := r.exp_out_reg; -- expansion connector out
when 11 => readdata := r.exp_in_reg; -- expansion connector in
when 12 => readdata := r.hsc_out_reg;
when 13 => readdata := r.hsc_in_reg;
--when 14 => readdata := r.cb4_out1_reg; -- childboard4 connector out
--when 15 => readdata := r.cb4_out2_reg; -- childboard4 connector out
-- when 14 => readdata := r.cb3_in_reg; -- childboard3 connector in
-- when 15 => readdata := r.cb3_out_reg; -- childboard3 connector out
--when 14 => readdata := r.cb1_out_reg; -- childboard1 connector out
--when 15 => readdata := r.cb1_in_reg; -- childboard1 connector in
when others => null;
end case;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case conv_integer(apbi.paddr(6 downto 2)) is
when 0 => v.ledreg :=
GND(31 downto N_LEDS) &
apbi.pwdata(N_LEDS-1 downto 0); -- write LEDs
when 1 => v.led7reg :=
GND(31 downto N_SEVSEGBITS) &
apbi.pwdata(N_SEVSEGBITS-1 downto 0); -- write 7Segment
when 2 => v.codecreg :=
GND(31 downto N_CODECBITS) &
apbi.pwdata(N_CODECBITS-1 downto 0);
when 3 => v.codecreg2 :=
GND(31 downto N_CODECI2SBITS) &
apbi.pwdata(N_CODECI2SBITS-1 downto 0);
when 6 => v.irqenareg :=
GND(31 downto N_BUTTONS) &
apbi.pwdata(N_BUTTONS-1 downto 0);
when 9 => v.lcdreg :=
GND(31 downto N_LCDBITS) &
apbi.pwdata(N_LCDBITS-1 downto 0);
-- signal that new data has arrived
-- v.new_data_valid := '0';
v.new_data := '1';
when 10 => v.exp_out_reg :=
GND(31 downto N_EXPBITS/2) &
-- bit(N_EXPBITS) holds enable signal
apbi.pwdata(N_EXPBITS/2-1 downto 0);
when 12 => v.hsc_out_reg :=
GND(31 downto N_HSCBITS) &
apbi.pwdata(N_HSCBITS-1 downto 0);
--when 14 => v.cb4_out1_reg :=
-- apbi.pwdata(31 downto 0);
-- when 15 => v.cb3_out_reg :=
-- apbi.pwdata(31 downto 0);
--when 14 => v.exp_out_reg :=
-- GND(31 downto 13) &
-- -- bit(N_EXPBITS) holds enable signal
-- apbi.pwdata(12 downto 0);
when others => null;
end case;
end if;
-- set PIRQ
irqs := (others => '0');
for i in 0 to v.btn_irqs'left loop
-- set IRQ if button-i pressed and IRQ enabled
irqs(pirq) := irqs(pirq) or r.btn_irqs(i);
end loop;
if ledact = '1' then
MultiIO_out.led_out <= r.ledreg(N_LEDS-1 downto 0); -- not inverted
else
MultiIO_out.led_out <= not r.ledreg(N_LEDS-1 downto 0); -- inverted
end if;
-- disable seven segment and LC display by default
-- MultiIO_out.lcd_enable <= '0';
MultiIO_out.lcd_rw <= r.lcdreg(8);
MultiIO_out.lcd_regsel <= r.lcdreg(9);
-- reset new lcd data flag
-- will be enabled when new data are written to the LCD register
if MUXCounter = 4 then
v.new_data := '0';
-- v.serviced := '1';
end if;
-- register inputs from expansion connector
v.exp_in_reg(N_EXPBITS/2-1 downto 0) := MultiIO_in.exp_in;
MultiIO_out.exp_out <= r.exp_out_reg(N_EXPBITS/2-1 downto 0);
-- high-speed connector
v.hsc_in_reg(N_HSCBITS-1 downto 0) := MultiIO_in.hsc_in;
MultiIO_out.hsc_out <= r.hsc_out_reg(N_HSCBITS-1 downto 0);
-- configure control port of audio codec for SPI mode
MultiIO_out.codec_mode <= '1';
apbo.prdata <= readdata; -- output data to Leon
apbo.pirq <= irqs; -- output IRQs to Leon
apbo.pindex <= pindex; -- output index to Leon
rin <= v; -- update registers
end process;
apbo.pconfig <= pconfig; -- output config to Leon
regs : process(clk) -- update registers
begin
if rising_edge(clk) then
r <= rin;
end if;
end process;
KeyBoard : process(clk, rst_n)
variable ColumnStrobe : std_logic_vector(2 downto 0);
variable FirstTime : boolean;
variable NewColumnRow : std_logic_vector(6 downto 0);
begin
if rst_n = '0' then
MultiIO_out.column_out <= (others => '0'); -- all column off
Key <= X"40"; -- default '@' after Reset and no key pressed
OldColumnRow1 <= "1111111";
OldColumnRow2 <= "1110011";
ColumnStrobe := "001";
FirstTime := true;
elsif rising_edge(clk) then
if Enable1ms then
if MultiIO_in.row_in = "0000" then -- no key pressed
ColumnStrobe := ColumnStrobe(1) & ColumnStrobe(0) & ColumnStrobe(2); -- rotate column
MultiIO_out.column_out <= ColumnStrobe;
if not FirstTime then
Key <= X"3F"; -- no key pressed '?'
end if;
else -- key pressed
OldColumnRow2 <= OldColumnRow1;
-- check whether button inputs produce a high or a
-- low level, then assign these inputs in order that
-- they can be decoded into ASCII format
if buttonact = '1' then
NewColumnRow := ColumnStrobe & MultiIO_in.row_in;
else
NewColumnRow := ColumnStrobe & not MultiIO_in.row_in;
end if;
OldColumnRow1 <= NewColumnRow;
if (ColumnStrobe & MultiIO_in.row_in = OldColumnRow1) and
(OldColumnRow1 = OldColumnRow2)
then -- debounced
FirstTime := false; -- 1st valid key pressed
case OldColumnRow2 is -- decode keys into ascii characters
when "0010001" => Key <= x"31"; -- 1
when "0010010" => Key <= x"34"; -- 4
when "0010100" => Key <= x"37"; -- 7
when "0011000" => Key <= x"43"; -- C
when "0100001" => Key <= x"32"; -- 2
when "0100010" => Key <= x"35"; -- 5
when "0100100" => Key <= x"38"; -- 8
when "0101000" => Key <= x"30"; -- 0
when "1000001" => Key <= x"33"; -- 3
when "1000010" => Key <= x"36"; -- 6
when "1000100" => Key <= x"39"; -- 9
when "1001000" => Key <= x"45"; -- E
when others => Key <= x"39"; -- ? -- more than one key pressed
end case;
else
Key <= x"3D"; -- '=' -- bouncing
end if; -- debounce
end if; -- MultiIO_in.row_in
end if; -- Enable1ms
end if; -- rst_n
end process KeyBoard;
Multiplex3Sources : if hpe_version = midi generate
Multiplex : process(MUXCounter, r)
begin
-- disable LED output by default
MultiIO_out.led_enable <= '0' xnor ledact;
-- disable 7-segment display by default
MultiIO_out.led_ca_out <= "00" xnor (led7act & led7act);
-- set enable signal in the middle of LCD timeslots
if MUXCounter = 3 then
MultiIO_out.lcd_enable <= '1';
else
MultiIO_out.lcd_enable <= '0';
end if;
case MUXCounter is
when 0 | 1 =>
-- output logical value according to active level of the 7segment display
MultiIO_out.led_a_out <= r.led7reg(MUXCounter*8 + 0) xnor led7act;
MultiIO_out.led_b_out <= r.led7reg(MUXCounter*8 + 1) xnor led7act;
MultiIO_out.led_c_out <= r.led7reg(MUXCounter*8 + 2) xnor led7act;
MultiIO_out.led_d_out <= r.led7reg(MUXCounter*8 + 3) xnor led7act;
MultiIO_out.led_e_out <= r.led7reg(MUXCounter*8 + 4) xnor led7act;
MultiIO_out.led_f_out <= r.led7reg(MUXCounter*8 + 5) xnor led7act;
MultiIO_out.led_g_out <= r.led7reg(MUXCounter*8 + 6) xnor led7act;
MultiIO_out.led_dp_out <= r.led7reg(MUXCounter*8 + 7) xnor led7act;
-- selectively enable the current digit
for i in 0 to 1 loop
if i = MUXCounter then
MultiIO_out.led_ca_out(i) <= '1' xnor led7act;
else
MultiIO_out.led_ca_out(i) <= '0' xnor led7act;
end if;
end loop; -- i
when 2 | 3 | 4 =>
MultiIO_out.led_a_out <= r.lcdreg(0);
MultiIO_out.led_b_out <= r.lcdreg(1);
MultiIO_out.led_c_out <= r.lcdreg(2);
MultiIO_out.led_d_out <= r.lcdreg(3);
MultiIO_out.led_e_out <= r.lcdreg(4);
MultiIO_out.led_f_out <= r.lcdreg(5);
MultiIO_out.led_g_out <= r.lcdreg(6);
MultiIO_out.led_dp_out <= r.lcdreg(7);
when 5 | 6 =>
MultiIO_out.led_enable <= '1' xnor ledact;
MultiIO_out.led_a_out <= r.ledreg(0) xnor ledact;
MultiIO_out.led_b_out <= r.ledreg(1) xnor ledact;
MultiIO_out.led_c_out <= r.ledreg(2) xnor ledact;
MultiIO_out.led_d_out <= r.ledreg(3) xnor ledact;
MultiIO_out.led_e_out <= r.ledreg(4) xnor ledact;
MultiIO_out.led_f_out <= r.ledreg(5) xnor ledact;
MultiIO_out.led_g_out <= r.ledreg(6) xnor ledact;
MultiIO_out.led_dp_out <= r.ledreg(7) xnor ledact;
when others =>
null;
end case;
end process Multiplex;
end generate Multiplex3Sources;
Multiplex2Sources : if hpe_version /= midi generate
Multiplex : process(MUXCounter, r)
begin
-- disable LED output by default
MultiIO_out.led_enable <= '0' xnor ledact;
-- disable 7-segment display by default
MultiIO_out.led_ca_out <= "00" xnor (led7act & led7act);
-- set enable signal in the middle of LCD timeslots
if MUXCounter = 3 then
MultiIO_out.lcd_enable <= '1';
else
MultiIO_out.lcd_enable <= '0';
end if;
case MUXCounter is
when 0 | 1 =>
-- output logical value according to active level of the 7segment display
MultiIO_out.led_a_out <= r.led7reg(MUXCounter*8 + 0) xnor led7act;
MultiIO_out.led_b_out <= r.led7reg(MUXCounter*8 + 1) xnor led7act;
MultiIO_out.led_c_out <= r.led7reg(MUXCounter*8 + 2) xnor led7act;
MultiIO_out.led_d_out <= r.led7reg(MUXCounter*8 + 3) xnor led7act;
MultiIO_out.led_e_out <= r.led7reg(MUXCounter*8 + 4) xnor led7act;
MultiIO_out.led_f_out <= r.led7reg(MUXCounter*8 + 5) xnor led7act;
MultiIO_out.led_g_out <= r.led7reg(MUXCounter*8 + 6) xnor led7act;
MultiIO_out.led_dp_out <= r.led7reg(MUXCounter*8 + 7) xnor led7act;
-- selectively enable the current digit
for i in 0 to 1 loop
if i = MUXCounter then
MultiIO_out.led_ca_out(i) <= '1' xnor led7act;
else
MultiIO_out.led_ca_out(i) <= '0' xnor led7act;
end if;
end loop; -- i
when others =>
MultiIO_out.led_a_out <= r.lcdreg(0);
MultiIO_out.led_b_out <= r.lcdreg(1);
MultiIO_out.led_c_out <= r.lcdreg(2);
MultiIO_out.led_d_out <= r.lcdreg(3);
MultiIO_out.led_e_out <= r.lcdreg(4);
MultiIO_out.led_f_out <= r.lcdreg(5);
MultiIO_out.led_g_out <= r.lcdreg(6);
MultiIO_out.led_dp_out <= r.lcdreg(7);
end case;
end process Multiplex;
end generate Multiplex2Sources;
-- generate prescaler signal every 100 ms
-- control MUXCounter according to input and board type
Count1ms : process(clk, rst_n)
constant divider100ms : integer := clk_freq_in / 10_000;
variable frequency_counter : integer range 0 to Divider100ms;
begin
if rst_n = '0' then
frequency_counter := Divider100ms;
Enable1ms <= false;
MUXCounter <= 0;
elsif rising_edge(clk) then
if frequency_counter = 0 then -- 1-ms counter has expired
frequency_counter := Divider100ms;
Enable1ms <= true;
if (hpe_version = midi) then
-- skip LCD control sequence and go to
-- LED control
if (MUXCounter = 1 and r.new_data = '0') then
MUXCounter <= 5;
-- overflow at maximum counter value for Hpe_midi
elsif MUXCounter = MUXMAX-1 then
MUXCounter <= 0;
else
MUXCounter <= MUXCounter + 1;
end if;
elsif (hpe_version /= midi) then
-- skip LCD control sequence and go back to
-- 7-segment control
if (MUXCounter = 1 and r.new_data = '0') then
MUXCounter <= 0;
-- overflow at maximum counter value for Hpe_mini
elsif MUXCounter = MUXMAX-3 then
MUXCounter <= 0;
else
MUXCounter <= MUXCounter + 1;
end if;
end if;
else
frequency_counter := frequency_counter - 1;
Enable1ms <= false;
end if;
end if;
end process;
---------------------------------------------------------------------------------------
-- AUDIO CODEC SECTION
---------------------------------------------------------------------------------------
tlv320aic23b_audio : if hpe_version = mini_altera generate
-- audio clock generation
clk_gen : ClockGenerator
port map (
Clk => clk,
Reset => rst_n,
omclk => clkgen_mclk,
obclk => clkgen_bclk,
osclk => clkgen_sclk,
olrcout => clkgen_lrclk);
-- drive clock signals by clock generator
MultiIO_out.CODEC_SCLK <= clkgen_sclk;
MultiIO_out.CODEC_MCLK <= clkgen_mclk;
MultiIO_out.CODEC_BCLK <= clkgen_bclk;
MultiIO_out.CODEC_LRCIN <= clkgen_lrclk;
MultiIO_out.CODEC_LRCOUT <= clkgen_lrclk;
-- SPI control interface
spi_xmit_1 : spi_xmit
generic map (
data_width => N_CODECBITS)
port map (
clk_i => clkgen_SCLK,
rst_i => rst_n,
data_i => r.codecreg(N_CODECBITS-1 downto 0),
CODEC_SDIN => MultiIO_out.CODEC_SDIN,
CODEC_CS => MultiIO_out.CODEC_CS);
-- I2C data interface
ParToI2s_1 : ParToI2s
generic map (
SampleSize_g => N_CODECI2SBITS)
port map (
Clk_i => clk,
Reset_i => rst_n,
SampleLeft_i => SampleReg,
SampleRight_i => SampleReg,
StrobeLeft_i => Strobe,
StrobeRight_i => Strobe,
SampleAck_o => SampleAck,
WaitForSample_o => WaitForSample,
SClk_i => clkgen_sclk,
LRClk_i => clkgen_lrclk,
SdnyData_o => MultiIO_out.CODEC_DIN);
audio_ctrl_sm : process(SampleAck, WaitForSample, state)
begin
next_state <= state;
next_Strobe <= '0';
case state is
when WAIT_FOR_SYNC =>
if WaitForSample = '1' then
next_state <= READY;
end if;
when READY =>
next_state <= WAIT_FOR_ACK;
next_Strobe <= '1';
when WAIT_FOR_ACK =>
if SampleAck = '1' then
next_state <= READY;
end if;
when others =>
next_state <= WAIT_FOR_SYNC;
end case;
end process;
audio_ctrl_reg : process(clk, rst_n)
begin
if rst_n = '0' then -- asynchronous reset
state <= WAIT_FOR_SYNC;
Strobe <= '0';
SampleReg <= (others => '0');
elsif clk'event and clk = '1' then
state <= next_state;
Strobe <= next_Strobe;
if (next_Strobe) = '1' then
-- if Mode = '0' then
-- SampleReg <= std_ulogic_vector(unsigned(AudioSample)- X"80");
-- else
-- SampleReg <= AudioSample;
-- end if;
SampleReg <= std_ulogic_vector(r.codecreg2(N_CODECI2SBITS-1 downto 0));
end if;
end if;
end process;
end generate tlv320aic23b_audio;
---------------------------------------------------------------------------------------
-- DEBUG SECTION
---------------------------------------------------------------------------------------
-- pragma translate_off
KeyVal <=
ascii2char(conv_integer(Key)) when
(conv_integer(Key) >= 16#30#) and (conv_integer(Key) <= 16#46#)
else 'U';
bootmsg : report_version
generic map ("MultiIO_APB6:" & tost(pindex) &
", Human Interface Controller rev " & tost(REVISION) &
", IRQ " & tost(pirq));
-- pragma translate_on
end architecture;
|
entity tb_repro_rng1 is
end tb_repro_rng1;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_repro_rng1 is
signal clk : std_logic;
signal a : natural range 0 to 7;
signal b : natural range 0 to 7;
begin
dut: entity work.repro_rng1
port map (
clk => clk, a => a, b => b);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
a <= 1;
pulse;
assert b = 1 severity failure;
a <= 6;
pulse;
assert b = 6 severity failure;
wait;
end process;
end behav;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: FiFo512Core32W32R_tb.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.FiFo512Core32W32R_pkg.ALL;
ENTITY FiFo512Core32W32R_tb IS
END ENTITY;
ARCHITECTURE FiFo512Core32W32R_arch OF FiFo512Core32W32R_tb IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL rd_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 100 ns;
CONSTANT rd_clk_period_by_2 : TIME := 200 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 200 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
PROCESS BEGIN
WAIT FOR 400 ns;-- Wait for global reset
WHILE 1 = 1 LOOP
rd_clk <= '0';
WAIT FOR rd_clk_period_by_2;
rd_clk <= '1';
WAIT FOR rd_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 4200 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from FiFo512Core32W32R_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Test Completed Successfully"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 400 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of FiFo512Core32W32R_synth
FiFo512Core32W32R_synth_inst:FiFo512Core32W32R_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 32
)
PORT MAP(
WR_CLK => wr_clk,
RD_CLK => rd_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity U232CRecv is
generic (
wTime : std_logic_vector(15 downto 0) := x"1B17");
port (
clk : in std_logic;
ok : in std_logic;
rx_pin : in std_logic;
data : out std_logic_vector (7 downto 0);
recf : out std_logic);
end U232CRecv;
architecture statemachine of U232CRecv is
signal countdown : std_logic_vector(15 downto 0);
signal buf : std_logic_vector(8 downto 0) := (others => '0');
signal state : integer range 0 to 11 := 11;
signal recf_i : std_logic;
begin
recf <= recf_i;
recf_i <= '1' when state = 0 else '0';
buf(8) <= rx_pin;
everyClock : process(clk)
begin
if rising_edge(clk) then
case state is
when 11 =>
if buf(8) = '1' then
-- read start bit at half of wTime
countdown <= "0"&wTime(15 downto 1);
state <= 10;
end if;
when 10 =>
if buf(8) = '0' then
if countdown = 0 then
countdown <= wTime;
state <= state-1;
else
countdown <= countdown-1;
end if;
else
countdown <= "0"&wTime(15 downto 1);
end if;
when 1 =>
if countdown = 0 then
if buf(8) = '1' then
state <= 0;
data <= buf(7 downto 0);
else
state <= 11;
end if;
else
countdown <= countdown-1;
end if;
when 0 =>
if ok = '1' then
state <= 11;
end if;
when others =>
if countdown = 0 then
buf(7 downto 0) <= buf(8 downto 1);
countdown <= wTime;
state <= state-1;
else
countdown <= countdown-1;
end if;
end case;
end if;
end process;
end statemachine;
|
-- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 2; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 1;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 8;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant LMEM_IMPLEMENT : natural := 1;
-- implement local scratchpad
constant N_TAG_MANAGERS_W : natural := N_CU_W+1; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant RD_CACHE_N_WORDS_W : natural := 0;
constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6;
constant FLOAT_IMPLEMENT : natural := 0;
constant FADD_IMPLEMENT : integer := 1;
constant FMUL_IMPLEMENT : integer := 1;
constant FDIV_IMPLEMENT : integer := 0;
constant FSQRT_IMPLEMENT : integer := 1;
constant UITOFP_IMPLEMENT : integer := 1;
constant FSLT_IMPLEMENT : integer := 0;
constant FRSQRT_IMPLEMENT : integer := 0;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant FRSQRT_DELAY : integer := 28;
constant FSLT_DELAY : integer := 2;
constant MAX_FPU_DELAY : integer := FDIV_DELAY;
constant CACHE_N_BANKS_W : natural := 3;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_rx_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.fifo_rx_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fifo_rx_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fifo_rx_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL srst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(9-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(9-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(9-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(9-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
SIGNAL rst_sync_rd1 : STD_LOGIC := '0';
SIGNAL rst_sync_rd2 : STD_LOGIC := '0';
SIGNAL rst_sync_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Synchronous reset generation for FIFO core
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_sync_rd1 <= RESET;
rst_sync_rd2 <= rst_sync_rd1;
rst_sync_rd3 <= rst_sync_rd2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
clk_i <= CLK;
------------------
srst <= rst_sync_rd3 OR rst_s_rd AFTER 100 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fifo_rx_dgen
GENERIC MAP (
C_DIN_WIDTH => 9,
C_DOUT_WIDTH => 9,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fifo_rx_dverif
GENERIC MAP (
C_DOUT_WIDTH => 9,
C_DIN_WIDTH => 9,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fifo_rx_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 9,
C_DIN_WIDTH => 9,
C_WR_PNTR_WIDTH => 4,
C_RD_PNTR_WIDTH => 4,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fifo_rx_inst : fifo_rx_exdes
PORT MAP (
CLK => clk_i,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
--*****************************************************************************
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 3.92
-- \ \ Application: MIG
-- / / Filename: rd_bitslip.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/06/02 07:18:13 $
-- \ \ / \ Date Created: Aug 03 2009
-- \___\/\___\
--
--Device: Virtex-6
--Design Name: DDR3 SDRAM
--Purpose:
-- Shifts and delays data from ISERDES, in both memory clock and internal
-- clock cycles. Used to uniquely shift/delay each byte to align all bytes
-- in data word
--Reference:
--Revision History:
--*****************************************************************************
--******************************************************************************
--**$Id: rd_bitslip.vhd,v 1.1 2011/06/02 07:18:13 mishra Exp $
--**$Date: 2011/06/02 07:18:13 $
--**$Author: mishra $
--**$Revision: 1.1 $
--**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_v3_9/data/dlib/virtex6/ddr3_sdram/vhdl/rtl/phy/rd_bitslip.vhd,v $
--******************************************************************************
library unisim;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity rd_bitslip is
generic (
TCQ : integer := 100
);
port (
clk : in std_logic;
bitslip_cnt : in std_logic_vector(1 downto 0);
clkdly_cnt : in std_logic_vector(1 downto 0);
din : in std_logic_vector(5 downto 0);
qout : out std_logic_vector(3 downto 0)
);
end rd_bitslip;
architecture trans_rd_bitslip of rd_bitslip is
signal din2_r : std_logic;
signal slip_out : std_logic_vector(3 downto 0);
signal slip_out_r : std_logic_vector(3 downto 0);
signal slip_out_r2 : std_logic_vector(3 downto 0);
signal slip_out_r3 : std_logic_vector(3 downto 0);
begin
--***************************************************************************
process (clk)
begin
if (clk'event and clk = '1') then
din2_r <= din(2) after (TCQ)*1 ps;
end if;
end process;
--Can shift data from ISERDES from 0-3 fast clock cycles
--NOTE: This is coded combinationally, in order to allow register to
--occur after MUXing of delayed outputs. Timing may be difficult to
--meet on this logic, if necessary, the register may need to be moved
--here instead, or another register added.
process (bitslip_cnt, din, din2_r)
begin
case bitslip_cnt is
when "00" => -- No slip
slip_out <= (din(3) & din(2) & din(1) & din(0));
when "01" => -- Slip = 0.5 cycle
slip_out <= (din(4) & din(3) & din(2) & din(1));
when "10" => -- Slip = 1 cycle
slip_out <= (din(5) & din(4) & din(3) & din(2));
when "11" => -- Slip = 1.5 cycle
slip_out <= (din2_r & din(5) & din(4) & din(3));
when others =>
null;
end case;
end process;
--Can delay up to 3 additional internal clock cycles - this accounts
--not only for delays due to DRAM, PCB routing between different bytes,
--but also differences within the FPGA - e.g. clock skew between different
--I/O columns, and differences in latency between different circular
--buffers or whatever synchronization method (FIFO) is used to get the
--data into the global clock domain
process (clk)
begin
if (clk'event and clk = '1') then
slip_out_r <= slip_out after TCQ*1 ps;
slip_out_r2 <= slip_out_r after TCQ*1 ps;
slip_out_r3 <= slip_out_r2 after TCQ*1 ps;
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
case clkdly_cnt is
when "00" =>
qout <= slip_out after (TCQ)*1 ps;
when "01" =>
qout <= slip_out_r after (TCQ)*1 ps;
when "10" =>
qout <= slip_out_r2 after (TCQ)*1 ps;
when "11" =>
qout <= slip_out_r3 after (TCQ)*1 ps;
when others =>
null;
end case;
end if;
end process;
end trans_rd_bitslip;
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_bus_build is
end entity alt_dspbuilder_bus_build;
architecture rtl of alt_dspbuilder_bus_build is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
-- This file is not intended for synthesis. The entity described in this file
-- is not directly instantiatable from HDL because its port list changes in a
-- way which is too complex to describe in VHDL or Verilog. Please use a tool
-- such as SOPC builder, DSP builder or the Megawizard plug-in manager to
-- instantiate this entity.
--altera translate_off
entity alt_dspbuilder_bus_build is
end entity alt_dspbuilder_bus_build;
architecture rtl of alt_dspbuilder_bus_build is
begin
assert false report "This file is not intended for synthesis. Please remove it from your project" severity error;
end architecture rtl;
--altera translate_on
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.pkg_6502_defs.all;
use work.tl_flat_memory_model_pkg.all;
use work.pkg_6502_decode.all;
entity tb_proc_core is
generic (
test_file : string := "opcode_test";
test_base : integer := 16#02FE# );
end tb_proc_core;
architecture tb of tb_proc_core is
signal clock : std_logic := '0';
signal clock_en : std_logic;
signal reset : std_logic;
signal addr_out : std_logic_vector(19 downto 0) := X"00000";
signal data_in : std_logic_vector(7 downto 0) := X"AA";
signal data_out : std_logic_vector(7 downto 0);
signal i_reg : std_logic_vector(7 downto 0);
signal read_write_n : std_logic;
signal nmi_n : std_logic := '1';
signal irq_n : std_logic := '1';
signal stop_clock : boolean := false;
shared variable ram : h_mem_object;
signal brk : std_logic := '0';
signal cmd : std_logic := '0';
signal s_is_absolute : boolean;
signal s_is_abs_jump : boolean;
signal s_is_immediate : boolean;
signal s_is_implied : boolean;
signal s_is_stack : boolean;
signal s_is_push : boolean;
signal s_is_zeropage : boolean;
signal s_is_indirect : boolean;
signal s_is_relative : boolean;
signal s_is_load : boolean;
signal s_is_store : boolean;
signal s_is_shift : boolean;
signal s_is_alu : boolean;
signal s_is_rmw : boolean;
signal s_is_jump : boolean;
signal s_is_postindexed : boolean;
signal s_is_illegal : boolean;
signal s_select_index_y : boolean;
signal s_store_a_from_alu : boolean;
signal s_load_a : boolean;
signal s_load_x : boolean;
signal s_load_y : boolean;
begin
clock <= not clock after 50 ns when not stop_clock;
clock_en <= '1';
reset <= '1', '0' after 300 ns;
core: entity work.proc_core
generic map (
support_bcd => true )
port map (
clock => clock,
clock_en => clock_en,
reset => reset,
irq_n => irq_n,
nmi_n => nmi_n,
addr_out => addr_out(16 downto 0),
inst_out => i_reg,
data_in => data_in,
data_out => data_out,
read_write_n => read_write_n );
cmd <= '1' when addr_out = X"10391" else '0';
process(clock)
variable addr : std_logic_vector(31 downto 0) := (others => '0');
begin
if falling_edge(clock) then
addr(15 downto 0) := addr_out(15 downto 0);
data_in <= read_memory_8(ram, addr);
if read_write_n = '0' then
write_memory_8(ram, addr, data_out);
-- if addr_out(15 downto 0) = X"FFF8" then
-- stop_clock <= true;
-- if data_out = X"55" then
-- report "Test program completed successfully." severity note;
-- else
-- report "Test program failed." severity error;
-- end if;
-- elsif addr_out(15 downto 0) = X"FFF9" then
-- case data_out is
-- when X"01" => report "Break IRQ service routine." severity note;
-- when X"02" => report "External IRQ service routine." severity note;
-- when X"03" => report "NMI service routine." severity note;
-- when others => report "Unknown event message." severity warning;
-- end case;
-- end if;
else -- read
if addr_out = X"1FFFE" then -- vector for BRK
brk <= '1';
end if;
end if;
end if;
end process;
test: process
begin
register_mem_model(tb_proc_core'path_name, "6502 ram", ram);
load_memory("bootstrap", ram, X"0000FFEE");
load_memory(test_file, ram, std_logic_vector(to_unsigned(test_base, 32)));
wait until brk = '1';
save_memory("result", ram, X"00000000", 2048);
stop_clock <= true;
-- wait for 30 us;
-- irq_n <= '0';
-- wait for 10 us;
-- irq_n <= '1';
-- wait for 10 us;
-- nmi_n <= '0';
-- wait for 10 us;
-- nmi_n <= '1';
wait;
end process;
s_is_absolute <= is_absolute(i_reg);
s_is_abs_jump <= is_abs_jump(i_reg);
s_is_immediate <= is_immediate(i_reg);
s_is_implied <= is_implied(i_reg);
s_is_stack <= is_stack(i_reg);
s_is_push <= is_push(i_reg);
s_is_zeropage <= is_zeropage(i_reg);
s_is_indirect <= is_indirect(i_reg);
s_is_relative <= is_relative(i_reg);
s_is_load <= is_load(i_reg);
s_is_store <= is_store(i_reg);
s_is_shift <= is_shift(i_reg);
s_is_alu <= is_alu(i_reg);
s_is_rmw <= is_rmw(i_reg);
s_is_jump <= is_jump(i_reg);
s_is_postindexed <= is_postindexed(i_reg);
s_is_illegal <= is_illegal(i_reg);
s_select_index_y <= select_index_y(i_reg);
s_store_a_from_alu <= store_a_from_alu(i_reg);
s_load_a <= load_a(i_reg);
s_load_x <= load_x(i_reg);
s_load_y <= load_y(i_reg);
end tb;
|
----------------------------------------------------------------------------------
-- Engineer: [email protected]
--
-- Create Date: 21:43:14 02/02/2015
-- Design Name: SPI driver for WS2801 led strings
-- Module Name: spiout - Behavioral
-- Project Name: Neppielight
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity spiout is
Port ( clk50 : in STD_LOGIC;
data : in std_logic_vector(0 to 24*25-1); -- MSB first
MOSI : out STD_LOGIC;
SCK : out STD_LOGIC);
end spiout;
architecture Behavioral of spiout is
signal sck_counter : std_logic_vector(15 downto 0);
signal sck_s : std_logic;
signal sck_enable : std_logic := '1';
signal wrcnt: std_logic_vector(9 downto 0) := (others => '0');
begin
process(clk50,sck_counter,sck_enable)
begin
if (rising_edge(clk50)) then
sck_counter <= sck_counter + 1;
end if;
sck_s <= sck_counter(11);
end process;
process(sck_s, sck_enable)
begin
-- Assert MOSI on the falling edge
-- So it can be sampled by the WS2801 on the rising edge.
if (falling_edge(sck_s)) then
if wrcnt <= 599 then
MOSI <= data(to_integer(unsigned(wrcnt)));
wrcnt <= (wrcnt + 1);
sck_enable <= '1'; -- this will let the clock go high on the next rising edge.
elsif wrcnt = 600 then
MOSI <= '0';
sck_enable <= '0';
wrcnt <= (wrcnt + 1);
elsif wrcnt = 640 then
sck_enable <= '0';
MOSI <= '0';
wrcnt <= (others =>'0');
else
sck_enable <= '0';
MOSI <= '0';
wrcnt <= (wrcnt + 1);
end if;
end if;
if sck_enable = '1' then
SCK <= sck_s;
else
SCK <= '0';
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Engineer: [email protected]
--
-- Create Date: 21:43:14 02/02/2015
-- Design Name: SPI driver for WS2801 led strings
-- Module Name: spiout - Behavioral
-- Project Name: Neppielight
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity spiout is
Port ( clk50 : in STD_LOGIC;
data : in std_logic_vector(0 to 24*25-1); -- MSB first
MOSI : out STD_LOGIC;
SCK : out STD_LOGIC);
end spiout;
architecture Behavioral of spiout is
signal sck_counter : std_logic_vector(15 downto 0);
signal sck_s : std_logic;
signal sck_enable : std_logic := '1';
signal wrcnt: std_logic_vector(9 downto 0) := (others => '0');
begin
process(clk50,sck_counter,sck_enable)
begin
if (rising_edge(clk50)) then
sck_counter <= sck_counter + 1;
end if;
sck_s <= sck_counter(11);
end process;
process(sck_s, sck_enable)
begin
-- Assert MOSI on the falling edge
-- So it can be sampled by the WS2801 on the rising edge.
if (falling_edge(sck_s)) then
if wrcnt <= 599 then
MOSI <= data(to_integer(unsigned(wrcnt)));
wrcnt <= (wrcnt + 1);
sck_enable <= '1'; -- this will let the clock go high on the next rising edge.
elsif wrcnt = 600 then
MOSI <= '0';
sck_enable <= '0';
wrcnt <= (wrcnt + 1);
elsif wrcnt = 640 then
sck_enable <= '0';
MOSI <= '0';
wrcnt <= (others =>'0');
else
sck_enable <= '0';
MOSI <= '0';
wrcnt <= (wrcnt + 1);
end if;
end if;
if sck_enable = '1' then
SCK <= sck_s;
else
SCK <= '0';
end if;
end process;
end Behavioral;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.types.all;
use work.interfaces.all;
entity load_logic is
port( clk : in std_logic;
reset : in std_logic;
input : in load_logic_in_if;
output : out load_logic_out_if);
end entity;
architecture rtl of load_logic is
type state_t is (load_idle, load_n_0, load_nn_0, load_r_0, load_indirect, load_have_b, load_n_1, load_nn_1, load_r_1, load_have_a);
signal state : state_t := load_idle;
signal a16 : word_t := (others => '0'); -- write address
begin
main: process(clk)
variable d16 : word_t; -- write data
begin
if reset = '1' then
output.mem.address <= (others => '0');
state <= load_idle;
elsif rising_edge(clk) then
output.mem.we <= '0';
output.reg.we <= '0';
output.done <= '0';
case state is
when load_idle =>
if input.en = '1' then
if input.r1 = register_d8 or input.r1 = register_d16 then
state <= load_n_0;
output.mem.address <= std_logic_vector(unsigned(input.reg.pc) + 1);
else
state <= load_r_0;
output.reg.rsel0 <= input.r1;
end if;
else
state <= load_idle;
end if;
when load_n_0 =>
d16(LO_BYTE) := input.mem.data;
if input.r1 = register_d16 then
state <= load_nn_0;
output.mem.address <= std_logic_vector(unsigned(input.reg.pc) + 2);
elsif input.indirect = "10" then
state <= load_indirect;
output.mem.address <= x"ff" & input.mem.data;
else
state <= load_have_b;
end if;
when load_nn_0 =>
d16(HI_BYTE) := input.mem.data;
if input.indirect = "10" then
state <= load_indirect;
output.mem.address <= d16;
else
state <= load_have_b;
end if;
when load_r_0 =>
if input.indirect = "10" then
state <= load_indirect;
if input.r0(3) = '1' then -- 16bit register
output.mem.address <= input.reg.d0;
else
output.mem.address <= x"ff" & input.reg.d0(LO_BYTE);
end if;
else
state <= load_have_b;
d16 := input.reg.d0;
end if;
when load_indirect =>
state <= load_have_b;
d16(LO_BYTE) := input.mem.data;
when load_have_b =>
if input.r0 = register_d8 or input.r0 = register_d16 then
state <= load_n_1;
output.mem.address <= std_logic_vector(unsigned(input.reg.pc) + 1);
else
state <= load_r_1;
output.reg.rsel0 <= input.r0;
end if;
when load_n_1 =>
if input.r0 = register_d16 then
state <= load_have_a;
output.mem.address <= x"ff" & input.mem.data;
else
state <= load_nn_1;
a16(LO_BYTE) <= input.mem.data;
output.mem.address <= std_logic_vector(unsigned(input.reg.pc) + 2);
end if;
when load_nn_1 =>
state <= load_have_a;
a16(HI_BYTE) <= input.mem.data;
when load_r_1 =>
if input.indirect = "01" then
state <= load_have_a;
if input.r0(3) = '1' then -- 16bit
output.mem.address <= input.reg.d0;
else
output.mem.address <= x"ff" & input.reg.d0(LO_BYTE);
end if;
else
state <= load_idle;
output.reg.we <= '1';
output.reg.wsel <= input.r0;
output.reg.data <= d16;
output.done <= '1';
end if;
when load_have_a =>
state <= load_idle;
output.mem.we <= '1';
output.mem.address <= a16;
output.mem.data <= d16(LO_BYTE);
output.done <= '1';
if input.inc_dec = "01" then
output.reg.we <= '1';
output.reg.wsel <= input.r0;
output.reg.data <= std_logic_vector(unsigned(input.reg.hl) + 1);
elsif input.inc_dec = "10" then
output.reg.we <= '1';
output.reg.wsel <= input.r0;
output.reg.data <= std_logic_vector(unsigned(input.reg.hl) - 1);
end if;
end case;
end if;
end process;
end architecture;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
-- Steffen Koehler
--
-- Module: Synchronizes a command signal across clock-domain boundaries
--
-- Description:
-- ------------------------------------
-- This module synchronizes a vector of bits from clock-domain 'Clock1' to
-- clock-domain 'Clock2'. The clock-domain boundary crossing is done by a
-- change comparator, a T-FF, two synchronizer D-FFs and a reconstructive
-- XOR indicating a value change on the input. This changed signal is used
-- to capture the input for the new output. A busy flag is additionally
-- calculated for the input clock-domain. The output has strobe character
-- and is reset to it's INIT value after one clock cycle.
--
-- CONSTRAINTS:
-- General:
-- This module uses sub modules which need to be constrained. Please
-- attend to the notes of the instantiated sub modules.
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.utils.all;
entity sync_Command IS
generic (
BITS : POSITIVE := 8; -- number of bit to be synchronized
INIT : STD_LOGIC_VECTOR := x"00000000" --
);
PORT (
Clock1 : in STD_LOGIC; -- <Clock> input clock
Clock2 : in STD_LOGIC; -- <Clock> output clock
Input : in STD_LOGIC_VECTOR(BITS - 1 downto 0); -- @Clock1: input vector
Output : out STD_LOGIC_VECTOR(BITS - 1 downto 0); -- @Clock2: output vector
Busy : out STD_LOGIC; -- @Clock1: busy bit
Changed : out STD_LOGIC -- @Clock2: changed bit
);
end;
architecture rtl OF sync_Command is
attribute SHREG_EXTRACT : STRING;
constant INIT_I : STD_LOGIC_VECTOR := descend(INIT)(BITS - 1 downto 0);
signal D0 : STD_LOGIC := '0';
signal D1 : STD_LOGIC_VECTOR(BITS - 1 downto 0) := INIT_I;
signal T2 : STD_LOGIC := '0';
signal D3 : STD_LOGIC := '0';
signal D4 : STD_LOGIC := '0';
signal D5 : STD_LOGIC_VECTOR(BITS - 1 downto 0) := INIT_I;
signal IsCommand_Clk1 : STD_LOGIC;
signal Changed_Clk1 : STD_LOGIC;
signal Changed_Clk2 : STD_LOGIC;
signal Busy_i : STD_LOGIC;
-- Prevent XST from translating two FFs into SRL plus FF
attribute SHREG_EXTRACT of D0 : signal IS "NO";
attribute SHREG_EXTRACT of T2 : signal IS "NO";
attribute SHREG_EXTRACT of D3 : signal IS "NO";
attribute SHREG_EXTRACT of D4 : signal IS "NO";
attribute SHREG_EXTRACT of D5 : signal IS "NO";
signal syncClk1_In : STD_LOGIC;
signal syncClk1_Out : STD_LOGIC;
signal syncClk2_In : STD_LOGIC;
signal syncClk2_Out : STD_LOGIC;
begin
-- input D-FF @Clock1 -> changed detection
process(Clock1)
begin
if rising_edge(Clock1) then
if (Busy_i = '0') then
D0 <= IsCommand_Clk1; -- delay detected IsCommand signal for rising edge detection; gated by busy flag
D1 <= Input;
T2 <= T2 xor Changed_Clk1; -- toggle T2 if input vector has changed
end if;
end if;
end process;
-- D-FF for level change detection (both edges)
process(Clock2)
begin
if rising_edge(Clock2) then
D3 <= syncClk2_Out;
D4 <= Changed_Clk2;
if (D4 = '1') then
D5 <= INIT_I;
elsif (Changed_Clk2 = '1') then
D5 <= D1;
end if;
end if;
end process;
-- assign syncClk*_In signals
syncClk2_In <= T2;
syncClk1_In <= D3;
IsCommand_Clk1 <= to_sl(Input /= INIT_I); -- input command detection
Changed_Clk1 <= not D0 and IsCommand_Clk1; -- input rising edge detection
Changed_Clk2 <= syncClk2_Out xor D3; -- level change detection; restore strobe signal from flag
Busy_i <= T2 xor syncClk1_Out; -- calculate busy signal
-- output signals
Output <= D5;
Busy <= Busy_i;
Changed <= D4;
syncClk2 : entity PoC.sync_Bits
generic map (
BITS => 1 -- number of bit to be synchronized
)
port map (
Clock => Clock2, -- <Clock> output clock domain
Input(0) => syncClk2_In, -- @async: input bits
Output(0) => syncClk2_Out -- @Clock: output bits
);
syncClk1 : entity PoC.sync_Bits
generic map (
BITS => 1 -- number of bit to be synchronized
)
port map (
Clock => Clock1, -- <Clock> output clock domain
Input(0) => syncClk1_In, -- @async: input bits
Output(0) => syncClk1_Out -- @Clock: output bits
);
end;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
-- Steffen Koehler
--
-- Module: Synchronizes a command signal across clock-domain boundaries
--
-- Description:
-- ------------------------------------
-- This module synchronizes a vector of bits from clock-domain 'Clock1' to
-- clock-domain 'Clock2'. The clock-domain boundary crossing is done by a
-- change comparator, a T-FF, two synchronizer D-FFs and a reconstructive
-- XOR indicating a value change on the input. This changed signal is used
-- to capture the input for the new output. A busy flag is additionally
-- calculated for the input clock-domain. The output has strobe character
-- and is reset to it's INIT value after one clock cycle.
--
-- CONSTRAINTS:
-- General:
-- This module uses sub modules which need to be constrained. Please
-- attend to the notes of the instantiated sub modules.
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.utils.all;
entity sync_Command IS
generic (
BITS : POSITIVE := 8; -- number of bit to be synchronized
INIT : STD_LOGIC_VECTOR := x"00000000" --
);
PORT (
Clock1 : in STD_LOGIC; -- <Clock> input clock
Clock2 : in STD_LOGIC; -- <Clock> output clock
Input : in STD_LOGIC_VECTOR(BITS - 1 downto 0); -- @Clock1: input vector
Output : out STD_LOGIC_VECTOR(BITS - 1 downto 0); -- @Clock2: output vector
Busy : out STD_LOGIC; -- @Clock1: busy bit
Changed : out STD_LOGIC -- @Clock2: changed bit
);
end;
architecture rtl OF sync_Command is
attribute SHREG_EXTRACT : STRING;
constant INIT_I : STD_LOGIC_VECTOR := descend(INIT)(BITS - 1 downto 0);
signal D0 : STD_LOGIC := '0';
signal D1 : STD_LOGIC_VECTOR(BITS - 1 downto 0) := INIT_I;
signal T2 : STD_LOGIC := '0';
signal D3 : STD_LOGIC := '0';
signal D4 : STD_LOGIC := '0';
signal D5 : STD_LOGIC_VECTOR(BITS - 1 downto 0) := INIT_I;
signal IsCommand_Clk1 : STD_LOGIC;
signal Changed_Clk1 : STD_LOGIC;
signal Changed_Clk2 : STD_LOGIC;
signal Busy_i : STD_LOGIC;
-- Prevent XST from translating two FFs into SRL plus FF
attribute SHREG_EXTRACT of D0 : signal IS "NO";
attribute SHREG_EXTRACT of T2 : signal IS "NO";
attribute SHREG_EXTRACT of D3 : signal IS "NO";
attribute SHREG_EXTRACT of D4 : signal IS "NO";
attribute SHREG_EXTRACT of D5 : signal IS "NO";
signal syncClk1_In : STD_LOGIC;
signal syncClk1_Out : STD_LOGIC;
signal syncClk2_In : STD_LOGIC;
signal syncClk2_Out : STD_LOGIC;
begin
-- input D-FF @Clock1 -> changed detection
process(Clock1)
begin
if rising_edge(Clock1) then
if (Busy_i = '0') then
D0 <= IsCommand_Clk1; -- delay detected IsCommand signal for rising edge detection; gated by busy flag
D1 <= Input;
T2 <= T2 xor Changed_Clk1; -- toggle T2 if input vector has changed
end if;
end if;
end process;
-- D-FF for level change detection (both edges)
process(Clock2)
begin
if rising_edge(Clock2) then
D3 <= syncClk2_Out;
D4 <= Changed_Clk2;
if (D4 = '1') then
D5 <= INIT_I;
elsif (Changed_Clk2 = '1') then
D5 <= D1;
end if;
end if;
end process;
-- assign syncClk*_In signals
syncClk2_In <= T2;
syncClk1_In <= D3;
IsCommand_Clk1 <= to_sl(Input /= INIT_I); -- input command detection
Changed_Clk1 <= not D0 and IsCommand_Clk1; -- input rising edge detection
Changed_Clk2 <= syncClk2_Out xor D3; -- level change detection; restore strobe signal from flag
Busy_i <= T2 xor syncClk1_Out; -- calculate busy signal
-- output signals
Output <= D5;
Busy <= Busy_i;
Changed <= D4;
syncClk2 : entity PoC.sync_Bits
generic map (
BITS => 1 -- number of bit to be synchronized
)
port map (
Clock => Clock2, -- <Clock> output clock domain
Input(0) => syncClk2_In, -- @async: input bits
Output(0) => syncClk2_Out -- @Clock: output bits
);
syncClk1 : entity PoC.sync_Bits
generic map (
BITS => 1 -- number of bit to be synchronized
)
port map (
Clock => Clock1, -- <Clock> output clock domain
Input(0) => syncClk1_In, -- @async: input bits
Output(0) => syncClk1_Out -- @Clock: output bits
);
end;
|
architecture rtl of fifo is
constant c_zeros : std_logic_vector(7 downto 0) := (others => '0');
constant c_one : std_logic_vector(7 downto 0) := (0 => '1', (others => '0'));
constant c_two : std_logic_vector(7 downto 0) := (1 => '1', (others => '0'));
constant c_stimulus : t_stimulus_array := ((name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00"));
constant c_stimulus : t_stimulus_array :=
(
(name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00"));
constant c_stimulus : t_stimulus_array :=
((name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00"));
constant c_stimulus : t_stimulus_array :=
((name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00")
);
constant c_stimulus : t_stimulus_array :=
(
(name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"),
(name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00")
);
constant c_stimulus : t_stimulus_array :=
(
(name => "Hold in reset",
clk_in => "01",
rst_in => "11",
cnt_en_in => "00",
cnt_out => "00"),
(name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00")
);
constant c_stimulus : t_stimulus_array :=
(
(
name => "Hold in reset",
clk_in => "01",
rst_in => "11",
cnt_en_in => "00",
cnt_out => "00"),
(
name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00")
);
constant c_stimulus : t_stimulus_array :=
(
(
name => "Hold in reset",
clk_in => "01",
rst_in => "11",
cnt_en_in => "00",
cnt_out => "00"
),
(
name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00"
)
);
constant c_stimulus : t_stimulus_array :=
(
name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00"); -- Comment
begin
end architecture rtl;
|
--!-----------------------------------------------------------------------------
--! --
--! Weizmann Institute of Science --
--! Electronics & Data Acquisition Group --
--! --
--!-----------------------------------------------------------------------------
--!
--! unit name: centralRouter package
--!
--! author: [email protected]
--!
--! date: $10/12/2014 $: created
--!
--! version: $Rev 0 $:
--!
--! description: package file for the centralRouter interface
--!
--!-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
package centralRouter_package is
-------------------------------------------------------------------
-- general use type definitions
-------------------------------------------------------------------
type array7_std_logic_vector_15 is array (0 to 6) of std_logic_vector(14 downto 0);
type array8_std_logic_vector_15 is array (0 to 7) of std_logic_vector(14 downto 0);
type array8_std_logic_vector_16 is array (0 to 7) of std_logic_vector(15 downto 0);
type array7_std_logic_vector_8 is array (0 to 6) of std_logic_vector(7 downto 0);
type array8_std_logic_vector_8 is array (0 to 7) of std_logic_vector(7 downto 0);
type array15_std_logic_vector_7 is array (0 to 14) of std_logic_vector(6 downto 0);
type array15_std_logic_vector_8 is array (0 to 14) of std_logic_vector(7 downto 0);
type array15_std_logic_vector_6 is array (0 to 14) of std_logic_vector(5 downto 0);
type array15_std_logic_vector_3 is array (0 to 14) of std_logic_vector(2 downto 0);
-------------------------------------------------------------------
-- EPROC internal type definitions
-------------------------------------------------------------------
type isk_2array_type is array (0 to 1) of std_logic_vector(1 downto 0); -- 2 words of 2bit
type word8b_2array_type is array (0 to 1) of std_logic_vector(7 downto 0); -- 2 words of 8bit
type word10b_2array_type is array (0 to 1) of std_logic_vector(9 downto 0); -- 2 words of 10bit
type word10b_2array_4array_type is array (0 to 3) of word10b_2array_type; -- 4 groups of {2 words of 10bit}, one group per alignment
--
type isk_4array_type is array (0 to 3) of std_logic_vector(1 downto 0); -- 4 words of 2bit
type word8b_4array_type is array (0 to 3) of std_logic_vector(7 downto 0); -- 4 words of 8bit
type word10b_4array_type is array (0 to 3) of std_logic_vector(9 downto 0); -- 4 words of 10bit
type word10b_4array_8array_type is array (0 to 7) of word10b_4array_type; -- 8 groups of {4 words of 10bit}, one group per alignment
--
type isk_8array_type is array (0 to 7) of std_logic_vector(1 downto 0); -- 8 words of 2bit
type word8b_8array_type is array (0 to 7) of std_logic_vector(7 downto 0); -- 8 words of 8bit
type word10b_8array_type is array (0 to 7) of std_logic_vector(9 downto 0); -- 8 words of 10bit
type word10b_8array_16array_type is array (0 to 15) of word10b_8array_type; -- 16 groups of {8 words of 10bit}, one group per alignment
-------------------------------------------------------------------
-- 7 and 5 entry arrays of 16 input lines, 16bit line per EGROUP
-------------------------------------------------------------------
type from1GBTdata_array_type is array (0 to 6) of std_logic_vector(15 downto 0);
type to1GBTdata_array_type is array (0 to 4) of std_logic_vector(15 downto 0);
type to1GBTdataNcode_array_type is array (0 to 4) of std_logic_vector(17 downto 0);
-------------------------------------------------------------------
-- N entry array of 16 output lines, 16bit output line per EGROUP
-------------------------------------------------------------------
type GBTdata_array_type is array ( NATURAL RANGE <>) of std_logic_vector(15 downto 0);
-------------------------------------------------------------------
-- GBT_NUM entry arrays
-------------------------------------------------------------------
type ic_data_array_type is array ( NATURAL RANGE <>) of std_logic_vector(7 downto 0);
type cr_DIN_array_type is array ( NATURAL RANGE <>) of from1GBTdata_array_type;
type cr_DOUT_array_type is array ( NATURAL RANGE <>) of to1GBTdata_array_type;
type cr_8MSbs_array_type is array ( NATURAL RANGE <>) of std_logic_vector(7 downto 0);
type cr_4bit_array_type is array ( NATURAL RANGE <>) of std_logic_vector(3 downto 0);
type TTCin_array_type is array ( NATURAL RANGE <>) of std_logic_vector(9 downto 0);
type DownFifoFull_mon_array_type is array ( NATURAL RANGE <>) of std_logic_vector(58 downto 0);
type fmch_monitor_array_type is array ( NATURAL RANGE <>) of std_logic_vector(7 downto 0);
type busyOut_array_type is array ( NATURAL RANGE <>) of std_logic_vector(56 downto 0);
-------------------------------------------------------------------
-- Central Router configuration register arrays
-------------------------------------------------------------------
type crDownstreamConfig_type is array (0 to 7) of std_logic_vector(63 downto 0);
type crUpstreamConfig_type is array (0 to 5) of std_logic_vector(63 downto 0);
-------------------------------------------------------------------
-- 256-bit fifo out, one per GBT
-------------------------------------------------------------------
type d256b_array_type is array (natural range <>) of std_logic_vector(255 downto 0);
type txrx33b_type is array (natural range <>) of std_logic_vector(32 downto 0);
type GBTdm_data_array_type is array ( NATURAL RANGE <>) of std_logic_vector(255 downto 0);
type GBTdm_dsdata_array_type is array ( NATURAL RANGE <>) of std_logic_vector(31 downto 0);
type d32bit_array_type is array (0 to 255) of std_logic_vector(31 downto 0);
type d32bit_array32_type is array (0 to 31) of std_logic_vector(31 downto 0);
-------------------------------------------------------------------
-- 8 entry array of 8bit input
-------------------------------------------------------------------
type EPROC_FIFO_DIN_array_type is array (0 to 7) of std_logic_vector(7 downto 0);
type EPROC_FIFO_DIN_CODE_array_type is array (0 to 7) of std_logic_vector(1 downto 0);
-------------------------------------------------------------------
-- BLOCK size definition [in 16bit words]
-- chunck can span on part of a BLOCK or on several BLOCKs
-------------------------------------------------------------------
constant BLOCK_WORDn : std_logic_vector(9 downto 0) := "1000000000"; -- = 512 (number of 16-bit words in a block)
constant BLOCK_WORD32n : std_logic_vector(8 downto 0) := "100000000"; -- = 256 (number of 32-bit words in a block)
-------------------------------------------------------------------
-- 8b10b encoding / decoding parameters
-------------------------------------------------------------------
constant COMMAp : std_logic_vector (9 downto 0) := "0011111010"; -- +K.28.5
constant COMMAn : std_logic_vector (9 downto 0) := "1100000101"; -- -K.28.5
--- start-of-chunk and end-of-chunk characters
constant EOCp : std_logic_vector (9 downto 0) := "0011110110"; -- +K.28.6
constant EOCn : std_logic_vector (9 downto 0) := "1100001001"; -- -K.28.6
--constant SOCp : std_logic_vector (9 downto 0) := "0011111000"; -- +K.28.7 <---- discontinued
--constant SOCn : std_logic_vector (9 downto 0) := "1100000111"; -- -K.28.7 <---- discontinued
constant SOCp : std_logic_vector (9 downto 0) := "0011111001"; -- +K.28.1
constant SOCn : std_logic_vector (9 downto 0) := "1100000110"; -- -K.28.1
--- start-of-busy and end-of-busy characters
constant SOBp : std_logic_vector (9 downto 0) := "0011110101"; -- +K.28.2
constant SOBn : std_logic_vector (9 downto 0) := "1100001010"; -- -K.28.2
constant EOBp : std_logic_vector (9 downto 0) := "0011110011"; -- +K.28.3
constant EOBn : std_logic_vector (9 downto 0) := "1100001100"; -- -K.28.3
constant Kchar_comma : std_logic_vector (7 downto 0) := "10111100"; -- K28.5
constant Kchar_eop : std_logic_vector (7 downto 0) := "11011100"; -- K28.6
--constant Kchar_sop : std_logic_vector (7 downto 0) := "11111100"; -- K28.7 <---- discontinued
constant Kchar_sop : std_logic_vector (7 downto 0) := "00111100"; -- K28.1
constant Kchar_sob : std_logic_vector (7 downto 0) := "01011100"; -- K28.2
constant Kchar_eob : std_logic_vector (7 downto 0) := "01111100"; -- K28.3
-------------------------------------------------------------------
-- HDLC encoding / decoding parameters
-------------------------------------------------------------------
constant HDLC_flag : std_logic_vector(7 downto 0) := "01111110";
----------------------------------------------------------------------------------
-- 7 EGROUPs configuration parameters:
----------------------------------------------------------------------------------
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- MATLAB generated parameters, consistent with GBT LINK DATA EMULATOR .coe files
--<< begin
--
-- 1. EPROC_ENA_bits 15 bit vector per EGROUP (15 EPROCs in one EGROUP)
-- [EPROC_IN2 EPROC_IN2 EPROC_IN2 EPROC_IN2 EPROC_IN2 EPROC_IN2 EPROC_IN2 EPROC_IN2 EPROC_IN4 EPROC_IN4 EPROC_IN4 EPROC_IN4 EPROC_IN8 EPROC_IN8 EPROC_IN16]
--
type EPROC_ENA_bits_array_type is array (0 to 7) of std_logic_vector(14 downto 0);
constant EPROC_ENA_bits_array : EPROC_ENA_bits_array_type :=(
"111111110000000",
"000000000000110",
"000000000000110",
"000011110000100",
"111111110000000",
"000000000000000",
"000000000000000",
"100000000000000");
--
-- 2. PATH_ENCODING, 16 bit vector per EGROUP (2 bits per PATH, 8 PATHs in one EGROUP)
-- for each of 8 output paths: "00"=non, "01"=8b10b, "10"=HDLC
--
type EPROC_ENCODING_array_type is array (0 to 7) of std_logic_vector(15 downto 0);
constant PATH_ENCODING_array : EPROC_ENCODING_array_type :=(
"0101010101010101",
"0101010101010101",
"0101010101010101",
"0101010101010101",
"0101010101010101",
"0101010101010101",
"0101010101010101",
"1000000000000000");
--
-- 3. Maximal valid CHUNK length for data truncation
-- per GBT channel, 3MSBs per Eproc type
--
constant MAX_CHUNK_LEN_array : std_logic_vector(11 downto 0) := "000000000000";
--<< end
-- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-- 10 MS bits are used as an Egroup address in serial CR configuration mode (otherwise unused)
constant broadcast17bits : std_logic_vector(16 downto 0) := (16=>'1', 15=>'1', others=>'0');
constant broadcast21bits : std_logic_vector(20 downto 0) := (20=>'1', 19=>'1', others => '0');
-------------------------------------------------------------------
-- initial conf. constants for the case of {TTC_test_mode = false}
--
-- NOT a TTC test, initial configuration is generated using Matlab,
-- according to the selected options in a gui.
-------------------------------------------------------------------
constant CR_TH_EGROUP0_CTRL_C :std_logic_vector(63 downto 0) :=(
broadcast21bits & -- 17 + 4 bit: (63 downto 43)
MAX_CHUNK_LEN_array & -- 12 bit: (42 downto 31)
PATH_ENCODING_array(0) & -- 16 bit: (30 downto 15)
EPROC_ENA_bits_array(0)); -- 15 bit: (14 downto 0)
constant CR_TH_EGROUP1_CTRL_C :std_logic_vector(63 downto 0) :=(
broadcast21bits & -- 17 + 4 bit: (63 downto 43)
MAX_CHUNK_LEN_array & -- 12 bit: (42 downto 31)
PATH_ENCODING_array(1) & -- 16 bit: (30 downto 15)
EPROC_ENA_bits_array(1)); -- 15 bit: (14 downto 0)
constant CR_TH_EGROUP2_CTRL_C :std_logic_vector(63 downto 0) :=(
broadcast21bits & -- 17 + 4 bit: (63 downto 43)
MAX_CHUNK_LEN_array & -- 12 bit: (42 downto 31)
PATH_ENCODING_array(2) & -- 16 bit: (30 downto 15)
EPROC_ENA_bits_array(2)); -- 15 bit: (14 downto 0)
constant CR_TH_EGROUP3_CTRL_C :std_logic_vector(63 downto 0) :=(
broadcast21bits & -- 17 + 4 bit: (63 downto 43)
MAX_CHUNK_LEN_array & -- 12 bit: (42 downto 31)
PATH_ENCODING_array(3) & -- 16 bit: (30 downto 15)
EPROC_ENA_bits_array(3)); -- 15 bit: (14 downto 0)
constant CR_TH_EGROUP4_CTRL_C :std_logic_vector(63 downto 0) :=(
broadcast21bits & -- 17 + 4 bit: (63 downto 43)
MAX_CHUNK_LEN_array & -- 12 bit: (42 downto 31)
PATH_ENCODING_array(4) & -- 16 bit: (30 downto 15)
EPROC_ENA_bits_array(4)); -- 15 bit: (14 downto 0)
constant CR_TH_EGROUP5_CTRL_C :std_logic_vector(63 downto 0) :=(
broadcast21bits & -- 17 + 4 bit: (63 downto 43)
MAX_CHUNK_LEN_array & -- 12 bit: (42 downto 31)
PATH_ENCODING_array(5) & -- 16 bit: (30 downto 15)
EPROC_ENA_bits_array(5)); -- 15 bit: (14 downto 0)
constant CR_TH_EGROUP6_CTRL_C :std_logic_vector(63 downto 0) :=(
broadcast21bits & -- 17 + 4 bit: (63 downto 43)
MAX_CHUNK_LEN_array & -- 12 bit: (42 downto 31)
PATH_ENCODING_array(6) & -- 16 bit: (30 downto 15)
EPROC_ENA_bits_array(6)); -- 15 bit: (14 downto 0)
constant CR_TH_EGROUP7_CTRL_C :std_logic_vector(63 downto 0) :=(
broadcast21bits & -- 17 + 4 bit: (63 downto 43)
MAX_CHUNK_LEN_array & -- 12 bit: (42 downto 31)
PATH_ENCODING_array(7) & -- 16 bit: (30 downto 15)
EPROC_ENA_bits_array(7)); -- 15 bit: (14 downto 0)
-------------------------------------------------------------------
-- Initial configuration of the from-host path:
-- matched the initial configuration of the to-host path
-- (and the initial contents of the GBT data emulators)
-- this allows for the loop-back test without reconfiguration
-------------------------------------------------------------------
constant CR_FH_EGROUP0_CTRL_C : std_logic_vector(63 downto 0) := (broadcast17bits &
"00" & PATH_ENCODING_array(0)(15 downto 14) &
"00" & PATH_ENCODING_array(0)(13 downto 12) &
"00" & PATH_ENCODING_array(0)(11 downto 10) &
"00" & PATH_ENCODING_array(0)(9 downto 8) &
"00" & PATH_ENCODING_array(0)(7 downto 6) &
"00" & PATH_ENCODING_array(0)(5 downto 4) &
"00" & PATH_ENCODING_array(0)(3 downto 2) &
"00" & PATH_ENCODING_array(0)(1 downto 0) &
EPROC_ENA_bits_array(0));
constant CR_FH_EGROUP1_CTRL_C : std_logic_vector(63 downto 0) := (broadcast17bits &
"00" & PATH_ENCODING_array(1)(15 downto 14) &
"00" & PATH_ENCODING_array(1)(13 downto 12) &
"00" & PATH_ENCODING_array(1)(11 downto 10) &
"00" & PATH_ENCODING_array(1)(9 downto 8) &
"00" & PATH_ENCODING_array(1)(7 downto 6) &
"00" & PATH_ENCODING_array(1)(5 downto 4) &
"00" & PATH_ENCODING_array(1)(3 downto 2) &
"00" & PATH_ENCODING_array(1)(1 downto 0) &
EPROC_ENA_bits_array(1));
constant CR_FH_EGROUP2_CTRL_C : std_logic_vector(63 downto 0) := (broadcast17bits &
"00" & PATH_ENCODING_array(2)(15 downto 14) &
"00" & PATH_ENCODING_array(2)(13 downto 12) &
"00" & PATH_ENCODING_array(2)(11 downto 10) &
"00" & PATH_ENCODING_array(2)(9 downto 8) &
"00" & PATH_ENCODING_array(2)(7 downto 6) &
"00" & PATH_ENCODING_array(2)(5 downto 4) &
"00" & PATH_ENCODING_array(2)(3 downto 2) &
"00" & PATH_ENCODING_array(2)(1 downto 0) &
EPROC_ENA_bits_array(2));
constant CR_FH_EGROUP3_CTRL_C : std_logic_vector(63 downto 0) := (broadcast17bits &
"00" & PATH_ENCODING_array(3)(15 downto 14) &
"00" & PATH_ENCODING_array(3)(13 downto 12) &
"00" & PATH_ENCODING_array(3)(11 downto 10) &
"00" & PATH_ENCODING_array(3)(9 downto 8) &
"00" & PATH_ENCODING_array(3)(7 downto 6) &
"00" & PATH_ENCODING_array(3)(5 downto 4) &
"00" & PATH_ENCODING_array(3)(3 downto 2) &
"00" & PATH_ENCODING_array(3)(1 downto 0) &
EPROC_ENA_bits_array(3));
constant CR_FH_EGROUP4_CTRL_C : std_logic_vector(63 downto 0) := (broadcast17bits &
"00" & PATH_ENCODING_array(4)(15 downto 14) &
"00" & PATH_ENCODING_array(4)(13 downto 12) &
"00" & PATH_ENCODING_array(4)(11 downto 10) &
"00" & PATH_ENCODING_array(4)(9 downto 8) &
"00" & PATH_ENCODING_array(4)(7 downto 6) &
"00" & PATH_ENCODING_array(4)(5 downto 4) &
"00" & PATH_ENCODING_array(4)(3 downto 2) &
"00" & PATH_ENCODING_array(4)(1 downto 0) &
EPROC_ENA_bits_array(4));
constant CR_FH_EGROUP5_CTRL_C : std_logic_vector(63 downto 0) := (broadcast17bits &
"00" & PATH_ENCODING_array(7)(15 downto 14) &
"00" & PATH_ENCODING_array(7)(13 downto 12) &
"00" & PATH_ENCODING_array(7)(11 downto 10) &
"00" & PATH_ENCODING_array(7)(9 downto 8) &
"00" & PATH_ENCODING_array(7)(7 downto 6) &
"00" & PATH_ENCODING_array(7)(5 downto 4) &
"00" & PATH_ENCODING_array(7)(3 downto 2) &
"00" & PATH_ENCODING_array(7)(1 downto 0) &
EPROC_ENA_bits_array(7));
-------------------------------------------------------------------
-- initial configuration of the from- and to-host paths
-- for the case of {TTC_test_mode = true}
-- TTC test mode, normal GBT mode only!
-- Central Router generic 'wideMode' has to be set false.
-- Congifuration of TTC-from-host matches
-- the direct-to-host congifuration.
-- Trom-Host is TTC, to-Host is direct data.
-------------------------------------------------------------------
--
-- egroup0: 8 x EPROCx2s. direct data: TTC-0 (2bit) [B-chan L1A]
constant CR_FH_EGROUP0_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := broadcast17bits & x"33333333" & "111111110000000"; -- TTC-0
constant CR_TH_EGROUP0_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := broadcast21bits & "000000000000" & "0000000000000000" & "111111110000000";
-- egroup1: 4 x EPROCx4s. direct data: TTC-1 (4bit) [B-chan ECR BCR L1A]
constant CR_FH_EGROUP1_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := broadcast17bits & x"03030303" & "000000001111000"; -- TTC-1
constant CR_TH_EGROUP1_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := broadcast21bits & "000000000000" & "0000000000000000" & "000000001111000";
-- egroup2: 4 x EPROCx4s. direct data: TTC-2 (4bit) [Brcst[2] ECR BCR L1A]
constant CR_FH_EGROUP2_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := broadcast17bits & x"04040404" & "000000001111000"; -- TTC-2
constant CR_TH_EGROUP2_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := broadcast21bits & "000000000000" & "0000000000000000" & "000000001111000";
-- egroup3: 2 x EPROCx8s. direct data: TTC-3 (8bit) [B-chan Brcst[5] Brcst[4] Brcst[3] Brcst[2] ECR BCR L1A]
constant CR_FH_EGROUP3_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := broadcast17bits & x"00300030" & "000000000000110"; -- TTC-3
constant CR_TH_EGROUP3_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := broadcast21bits & "000000000000" & "0000000000000000" & "000000000000110";
-- egroup4: 2 x EPROCx8s. direct data: TTC-4 (8bit) [Brcst[6] Brcst[5] Brcst[4] Brcst[3] Brcst[2] ECR BCR L1A]
constant CR_FH_EGROUP4_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := broadcast17bits & x"00400040" & "000000000000110"; -- TTC-4
constant CR_TH_EGROUP4_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := broadcast21bits & "000000000000" & "0000000000000000" & "000000000000110";
-- egroup7: 8 x EPROCx2s. direct data: TTC-0 (2bit) [B-chan L1A]
constant CR_FH_EGROUP5_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := broadcast17bits & x"33333333" & "111111110000000"; -- TTC-0
constant CR_TH_EGROUP7_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := broadcast21bits & "000000000000" & "0000000000000000" & "000000000000110";
--
--
constant CR_TH_EGROUP5_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := (others=>'0');
constant CR_TH_EGROUP6_CTRL_C_TTC_test : std_logic_vector(63 downto 0) := (others=>'0');
--
--
end package centralRouter_package ;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mult IS
GENERIC(N:POSITIVE := 8);
PORT(
a,b : IN std_logic_vector(N-1 DOWNTO 0);
S : OUT std_logic_vector((2*N)-1 DOWNTO 0)
);
END mult;
ARCHITECTURE behavior OF mult IS
TYPE mem_ET IS array(0 TO N-1) OF std_logic_vector(N-1 DOWNTO 0);
TYPE mem_S IS ARRAY(0 TO N-1) OF std_logic_vector(N DOWNTO 0);
TYPE mem_C IS ARRAY(0 TO N-1) OF std_logic_vector(N DOWNTO 0);
SIGNAL memS : mem_S;
SIGNAL memET : mem_ET;
SIGNAL memC : mem_C;
COMPONENT fa IS
PORT(
a,b,Cin : IN std_logic;
S,Cout : OUT std_logic
);
END COMPONENT;
BEGIN
ligne : for i in 0 TO N GENERATE
memC(i)(0) <= '0';
colonne : for j IN 0 TO N GENERATE
memET(i)(j) <= (a(j) AND b(i));
prem_1 : IF i = 0 GENERATE
memS(0)(j) <= memET(0)(j);
memC(0)(4) <= '0';
END GENERATE prem_1;
prem_2 : IF i > 0 GENERATE
addN : fa PORT MAP(a => memS(i-1)(j), s => memS(i)(j),b => memET(i)(j),Cin => memC(i)(j),Cout => memC(i)(j+1));
END GENERATE prem_2;
END GENERATE colonne;
memS(i)(4) <= memC(i)(4);
END GENERATE ligne;
fin : FOR k in 0 TO N GENERATE
S(k) <= memS(k)(0);
END GENERATE fin;
fin2 : FOR l IN 1 TO N+1 GENERATE
S(N+l) <= memS(N)(l);
END GENERATE fin2;
END ARCHITECTURE;
|
library ieee;
use ieee.std_logic_1164.all;
entity arr01 is
port (
a : std_logic_vector (31 downto 0);
sel : natural range 0 to 3;
clk : std_logic;
res : out std_logic_vector (7 downto 0));
end arr01;
architecture behav of arr01 is
type t_mem is array (0 to 3) of std_logic_vector (7 downto 0);
type t_stage is record
sel : natural range 0 to 3;
val : t_mem;
end record;
signal s : t_stage;
begin
process (clk) is
begin
if rising_edge (clk) then
s.sel <= sel;
s.val <= (a (31 downto 24),
a (23 downto 16),
a (15 downto 8),
a (7 downto 0));
end if;
end process;
process (clk) is
begin
if rising_edge (clk) then
res <= s.val (s.sel);
end if;
end process;
end behav;
|
-- The Potato Processor - A simple processor for FPGAs
-- (c) Kristian Klomsten Skordal 2014 - 2016 <[email protected]>
-- Report bugs and issues on <https://github.com/skordal/potato/issues>
library ieee;
use ieee.std_logic_1164.all;
entity tb_soc_timer is
end entity tb_soc_timer;
architecture behaviour of tb_soc_timer is
-- Clock signal:
signal clk : std_logic := '0';
constant clk_period : time := 10 ns;
-- Reset signal:
signal reset : std_logic := '1';
-- IRQ signal:
signal irq : std_logic;
-- Wishbone interface:
signal wb_adr_in : std_logic_vector(11 downto 0) := (others => '0');
signal wb_dat_in : std_logic_vector(31 downto 0) := (others => '0');
signal wb_dat_out : std_logic_vector(31 downto 0);
signal wb_cyc_in : std_logic := '0';
signal wb_stb_in : std_logic := '0';
signal wb_we_in : std_logic := '0';
signal wb_ack_out : std_logic;
begin
uut: entity work.pp_soc_timer
port map(
clk => clk,
reset => reset,
irq => irq,
wb_adr_in => wb_adr_in,
wb_dat_in => wb_dat_in,
wb_dat_out => wb_dat_out,
wb_cyc_in => wb_cyc_in,
wb_stb_in => wb_stb_in,
wb_we_in => wb_we_in,
wb_ack_out => wb_ack_out
);
clock: process
begin
clk <= '1';
wait for clk_period / 2;
clk <= '0';
wait for clk_period / 2;
end process clock;
stimulus: process
begin
wait for clk_period * 2;
reset <= '0';
wait for clk_period;
-- Set the compare register to 50:
wb_cyc_in <= '1';
wb_stb_in <= '1';
wb_adr_in <= x"004";
wb_dat_in <= x"00000032";
wb_we_in <= '1';
wait until wb_ack_out = '1';
wait for clk_period;
wb_stb_in <= '0';
wait for clk_period;
-- Start the timer:
wb_stb_in <= '1';
wb_adr_in <= x"000";
wb_dat_in <= x"00000003";
wait until wb_ack_out = '1';
wait for clk_period;
wb_stb_in <= '0';
wb_cyc_in <= '0';
wb_we_in <= '0';
wait for clk_period;
-- Wait for the interrupt:
wait until irq = '1';
wait for clk_period;
-- Reset the interrupt:
wb_cyc_in <= '1';
wb_stb_in <= '1';
wb_we_in <= '1';
wb_adr_in <= x"000";
wb_dat_in <= x"00000003";
wait until wb_ack_out = '1';
wait for clk_period;
wb_stb_in <= '0';
wb_cyc_in <= '0';
wb_we_in <= '0';
wait for clk_period;
wait;
end process stimulus;
end architecture behaviour;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.usb_pkg.all;
entity usb_host_interface is
generic (
g_simulation : boolean := false );
port (
clock : in std_logic;
reset : in std_logic;
usb_rx : out t_usb_rx;
usb_tx_req : in t_usb_tx_req;
usb_tx_resp : out t_usb_tx_resp;
-- low level ulpi interfacing
reg_read : in std_logic := '0';
reg_write : in std_logic;
reg_address : in std_logic_vector(5 downto 0);
reg_wdata : in std_logic_vector(7 downto 0);
reg_rdata : out std_logic_vector(7 downto 0);
reg_ack : out std_logic;
do_chirp : in std_logic := '0';
chirp_data : in std_logic := '0';
status : out std_logic_vector(7 downto 0);
speed : in std_logic_vector(1 downto 0);
ulpi_nxt : in std_logic;
ulpi_stp : out std_logic;
ulpi_dir : in std_logic;
ulpi_data : inout std_logic_vector(7 downto 0) );
end entity;
architecture structural of usb_host_interface is
signal status_i : std_logic_vector(7 downto 0);
signal tx_data : std_logic_vector(7 downto 0) := X"00";
signal tx_last : std_logic := '0';
signal tx_valid : std_logic := '0';
signal tx_start : std_logic := '0';
signal tx_next : std_logic := '0';
signal rx_data : std_logic_vector(7 downto 0) := X"00";
signal rx_register : std_logic := '0';
signal rx_last : std_logic := '0';
signal rx_valid : std_logic := '0';
signal rx_store : std_logic := '0';
signal rx_crc_sync : std_logic;
signal rx_crc_dvalid : std_logic;
signal tx_crc_sync : std_logic;
signal tx_crc_dvalid : std_logic;
signal crc_sync : std_logic;
signal crc_dvalid : std_logic;
signal tx_data_to_crc: std_logic_vector(7 downto 0);
signal crc_data_in : std_logic_vector(7 downto 0);
signal data_crc : std_logic_vector(15 downto 0);
begin
i_ulpi: entity work.ulpi_bus
port map (
clock => clock,
reset => reset,
ULPI_DATA => ulpi_data,
ULPI_DIR => ulpi_dir,
ULPI_NXT => ulpi_nxt,
ULPI_STP => ulpi_stp,
-- status
status => status_i,
operational => '1',
-- chirp interface
do_chirp => do_chirp,
chirp_data => chirp_data,
-- register interface
reg_read => reg_read,
reg_write => reg_write,
reg_address => reg_address,
reg_wdata => reg_wdata,
reg_ack => reg_ack,
-- stream interface
tx_data => tx_data,
tx_last => tx_last,
tx_valid => tx_valid,
tx_start => tx_start,
tx_next => tx_next,
rx_data => rx_data,
rx_register => rx_register,
rx_last => rx_last,
rx_valid => rx_valid,
rx_store => rx_store );
i_rx: entity work.ulpi_rx
generic map (
g_support_split => false,
g_support_token => false ) -- hosts do not receive tokens
port map (
clock => clock,
reset => reset,
rx_data => rx_data,
rx_last => rx_last,
rx_valid => rx_valid,
rx_store => rx_store,
status => status_i,
-- interface to DATA CRC (shared resource)
crc_sync => rx_crc_sync,
crc_dvalid => rx_crc_dvalid,
data_crc => data_crc,
usb_rx => usb_rx );
crc_sync <= rx_crc_sync or tx_crc_sync;
crc_dvalid <= rx_crc_dvalid or tx_crc_dvalid;
crc_data_in <= rx_data when rx_crc_dvalid='1' else tx_data_to_crc;
i_data_crc: entity work.data_crc
port map (
clock => clock,
sync => crc_sync,
valid => crc_dvalid,
data_in => crc_data_in,
crc => data_crc );
i_tx: entity work.ulpi_tx
generic map (
g_simulation => g_simulation,
g_support_split => true,
g_support_token => true ) -- hosts do send tokens
port map (
clock => clock,
reset => reset,
-- Bus Interface
tx_start => tx_start,
tx_last => tx_last,
tx_valid => tx_valid,
tx_next => tx_next,
tx_data => tx_data,
rx_busy => rx_store,
-- interface to DATA CRC (shared resource)
crc_sync => tx_crc_sync,
crc_dvalid => tx_crc_dvalid,
data_crc => data_crc,
data_to_crc => tx_data_to_crc,
-- Status
status => status_i,
speed => speed,
-- Interface to send tokens and handshakes
usb_tx_req => usb_tx_req,
usb_tx_resp => usb_tx_resp );
status <= status_i;
reg_rdata <= rx_data;
end architecture;
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/ifft_16_bit/TWDLROM_3_15.vhd
-- Created: 2017-03-28 01:00:37
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: TWDLROM_3_15
-- Source Path: ifft_16_bit/IFFT HDL Optimized/TWDLROM_3_15
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.ifft_16_bit_pkg.ALL;
ENTITY TWDLROM_3_15 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
dout_2_vld : IN std_logic;
softReset : IN std_logic;
twdl_3_15_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_15_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_15_vld : OUT std_logic
);
END TWDLROM_3_15;
ARCHITECTURE rtl OF TWDLROM_3_15 IS
-- Constants
CONSTANT Twiddle_re_table_data : vector_of_signed17(0 TO 1) :=
(to_signed(16#08000#, 17), to_signed(16#07642#, 17)); -- sfix17 [2]
CONSTANT Twiddle_im_table_data : vector_of_signed17(0 TO 1) :=
(to_signed(16#00000#, 17), to_signed(-16#030FC#, 17)); -- sfix17 [2]
-- Signals
SIGNAL Radix22TwdlMapping_cnt : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_phase : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_octantReg1 : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL Radix22TwdlMapping_twdlAddr_raw : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL Radix22TwdlMapping_twdlAddrMap : std_logic; -- ufix1
SIGNAL Radix22TwdlMapping_twdl45Reg : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg1 : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg2 : std_logic;
SIGNAL Radix22TwdlMapping_cnt_next : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_phase_next : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_octantReg1_next : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL Radix22TwdlMapping_twdlAddr_raw_next : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL Radix22TwdlMapping_twdlAddrMap_next : std_logic; -- ufix1
SIGNAL Radix22TwdlMapping_twdl45Reg_next : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg1_next : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg2_next : std_logic;
SIGNAL twdlAddr : std_logic; -- ufix1
SIGNAL twdlAddrVld : std_logic;
SIGNAL twdlOctant : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL twdl45 : std_logic;
SIGNAL Twiddle_re_cast : signed(31 DOWNTO 0); -- int32
SIGNAL twiddleS_re : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twiddleReg_re : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL Twiddle_im_cast : signed(31 DOWNTO 0); -- int32
SIGNAL twiddleS_im : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twiddleReg_im : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdlOctantReg : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL twdl45Reg : std_logic;
SIGNAL twdl_3_15_re_tmp : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdl_3_15_im_tmp : signed(16 DOWNTO 0); -- sfix17_En15
BEGIN
-- Radix22TwdlMapping
Radix22TwdlMapping_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22TwdlMapping_octantReg1 <= to_unsigned(16#0#, 3);
Radix22TwdlMapping_twdlAddr_raw <= to_unsigned(16#0#, 4);
Radix22TwdlMapping_twdlAddrMap <= '0';
Radix22TwdlMapping_twdl45Reg <= '0';
Radix22TwdlMapping_dvldReg1 <= '0';
Radix22TwdlMapping_dvldReg2 <= '0';
Radix22TwdlMapping_cnt <= to_unsigned(16#2#, 2);
Radix22TwdlMapping_phase <= to_unsigned(16#3#, 2);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Radix22TwdlMapping_cnt <= Radix22TwdlMapping_cnt_next;
Radix22TwdlMapping_phase <= Radix22TwdlMapping_phase_next;
Radix22TwdlMapping_octantReg1 <= Radix22TwdlMapping_octantReg1_next;
Radix22TwdlMapping_twdlAddr_raw <= Radix22TwdlMapping_twdlAddr_raw_next;
Radix22TwdlMapping_twdlAddrMap <= Radix22TwdlMapping_twdlAddrMap_next;
Radix22TwdlMapping_twdl45Reg <= Radix22TwdlMapping_twdl45Reg_next;
Radix22TwdlMapping_dvldReg1 <= Radix22TwdlMapping_dvldReg1_next;
Radix22TwdlMapping_dvldReg2 <= Radix22TwdlMapping_dvldReg2_next;
END IF;
END IF;
END PROCESS Radix22TwdlMapping_process;
Radix22TwdlMapping_output : PROCESS (Radix22TwdlMapping_cnt, Radix22TwdlMapping_phase,
Radix22TwdlMapping_octantReg1, Radix22TwdlMapping_twdlAddr_raw,
Radix22TwdlMapping_twdlAddrMap, Radix22TwdlMapping_twdl45Reg,
Radix22TwdlMapping_dvldReg1, Radix22TwdlMapping_dvldReg2, dout_2_vld)
VARIABLE octant : unsigned(2 DOWNTO 0);
VARIABLE cnt_cast : unsigned(3 DOWNTO 0);
VARIABLE sub_cast : signed(9 DOWNTO 0);
VARIABLE sub_temp : signed(9 DOWNTO 0);
VARIABLE sub_cast_0 : signed(5 DOWNTO 0);
VARIABLE sub_temp_0 : signed(5 DOWNTO 0);
VARIABLE sub_cast_1 : signed(5 DOWNTO 0);
VARIABLE sub_temp_1 : signed(5 DOWNTO 0);
VARIABLE sub_cast_2 : signed(9 DOWNTO 0);
VARIABLE sub_temp_2 : signed(9 DOWNTO 0);
VARIABLE sub_cast_3 : signed(9 DOWNTO 0);
VARIABLE sub_temp_3 : signed(9 DOWNTO 0);
BEGIN
Radix22TwdlMapping_twdlAddr_raw_next <= Radix22TwdlMapping_twdlAddr_raw;
Radix22TwdlMapping_twdlAddrMap_next <= Radix22TwdlMapping_twdlAddrMap;
Radix22TwdlMapping_twdl45Reg_next <= Radix22TwdlMapping_twdl45Reg;
Radix22TwdlMapping_dvldReg2_next <= Radix22TwdlMapping_dvldReg1;
Radix22TwdlMapping_dvldReg1_next <= dout_2_vld;
CASE Radix22TwdlMapping_twdlAddr_raw IS
WHEN "0010" =>
octant := to_unsigned(16#0#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN "0100" =>
octant := to_unsigned(16#1#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '0';
WHEN "0110" =>
octant := to_unsigned(16#2#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN "1000" =>
octant := to_unsigned(16#3#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '0';
WHEN "1010" =>
octant := to_unsigned(16#4#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN OTHERS =>
octant := Radix22TwdlMapping_twdlAddr_raw(3 DOWNTO 1);
Radix22TwdlMapping_twdl45Reg_next <= '0';
END CASE;
Radix22TwdlMapping_octantReg1_next <= octant;
CASE octant IS
WHEN "000" =>
Radix22TwdlMapping_twdlAddrMap_next <= Radix22TwdlMapping_twdlAddr_raw(0);
WHEN "001" =>
sub_cast_0 := signed(resize(Radix22TwdlMapping_twdlAddr_raw, 6));
sub_temp_0 := to_signed(16#04#, 6) - sub_cast_0;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_0(0);
WHEN "010" =>
sub_cast_1 := signed(resize(Radix22TwdlMapping_twdlAddr_raw, 6));
sub_temp_1 := sub_cast_1 - to_signed(16#04#, 6);
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_1(0);
WHEN "011" =>
sub_cast_2 := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp_2 := to_signed(16#010#, 10) - sub_cast_2;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_2(1);
WHEN "100" =>
sub_cast_3 := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp_3 := sub_cast_3 - to_signed(16#010#, 10);
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_3(1);
WHEN OTHERS =>
sub_cast := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp := to_signed(16#018#, 10) - sub_cast;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp(1);
END CASE;
IF Radix22TwdlMapping_phase = to_unsigned(16#0#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= to_unsigned(16#0#, 4);
ELSIF Radix22TwdlMapping_phase = to_unsigned(16#1#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= resize(Radix22TwdlMapping_cnt, 4) sll 1;
ELSIF Radix22TwdlMapping_phase = to_unsigned(16#2#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= resize(Radix22TwdlMapping_cnt, 4);
ELSE
cnt_cast := resize(Radix22TwdlMapping_cnt, 4);
Radix22TwdlMapping_twdlAddr_raw_next <= (cnt_cast sll 1) + cnt_cast;
END IF;
Radix22TwdlMapping_phase_next <= to_unsigned(16#3#, 2);
Radix22TwdlMapping_cnt_next <= Radix22TwdlMapping_cnt + to_unsigned(16#000000010#, 2);
twdlAddr <= Radix22TwdlMapping_twdlAddrMap;
twdlAddrVld <= Radix22TwdlMapping_dvldReg2;
twdlOctant <= Radix22TwdlMapping_octantReg1;
twdl45 <= Radix22TwdlMapping_twdl45Reg;
END PROCESS Radix22TwdlMapping_output;
-- Twiddle ROM1
Twiddle_re_cast <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & twdlAddr;
twiddleS_re <= Twiddle_re_table_data(to_integer(Twiddle_re_cast));
TWIDDLEROM_RE_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twiddleReg_re <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twiddleReg_re <= twiddleS_re;
END IF;
END IF;
END PROCESS TWIDDLEROM_RE_process;
-- Twiddle ROM2
Twiddle_im_cast <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & twdlAddr;
twiddleS_im <= Twiddle_im_table_data(to_integer(Twiddle_im_cast));
TWIDDLEROM_IM_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twiddleReg_im <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twiddleReg_im <= twiddleS_im;
END IF;
END IF;
END PROCESS TWIDDLEROM_IM_process;
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdlOctantReg <= to_unsigned(16#0#, 3);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twdlOctantReg <= twdlOctant;
END IF;
END IF;
END PROCESS intdelay_process;
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl45Reg <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twdl45Reg <= twdl45;
END IF;
END IF;
END PROCESS intdelay_1_process;
-- Radix22TwdlOctCorr
Radix22TwdlOctCorr_output : PROCESS (twiddleReg_re, twiddleReg_im, twdlOctantReg, twdl45Reg)
VARIABLE twdlIn_re : signed(16 DOWNTO 0);
VARIABLE twdlIn_im : signed(16 DOWNTO 0);
VARIABLE cast : signed(17 DOWNTO 0);
VARIABLE cast_0 : signed(17 DOWNTO 0);
VARIABLE cast_1 : signed(17 DOWNTO 0);
VARIABLE cast_2 : signed(17 DOWNTO 0);
VARIABLE cast_3 : signed(17 DOWNTO 0);
VARIABLE cast_4 : signed(17 DOWNTO 0);
VARIABLE cast_5 : signed(17 DOWNTO 0);
VARIABLE cast_6 : signed(17 DOWNTO 0);
VARIABLE cast_7 : signed(17 DOWNTO 0);
VARIABLE cast_8 : signed(17 DOWNTO 0);
VARIABLE cast_9 : signed(17 DOWNTO 0);
VARIABLE cast_10 : signed(17 DOWNTO 0);
BEGIN
twdlIn_re := twiddleReg_re;
twdlIn_im := twiddleReg_im;
IF twdl45Reg = '1' THEN
CASE twdlOctantReg IS
WHEN "000" =>
twdlIn_re := to_signed(16#05A82#, 17);
twdlIn_im := to_signed(-16#05A82#, 17);
WHEN "010" =>
twdlIn_re := to_signed(-16#05A82#, 17);
twdlIn_im := to_signed(-16#05A82#, 17);
WHEN "100" =>
twdlIn_re := to_signed(-16#05A82#, 17);
twdlIn_im := to_signed(16#05A82#, 17);
WHEN OTHERS =>
twdlIn_re := to_signed(16#05A82#, 17);
twdlIn_im := to_signed(-16#05A82#, 17);
END CASE;
ELSE
CASE twdlOctantReg IS
WHEN "000" =>
NULL;
WHEN "001" =>
cast := resize(twiddleReg_im, 18);
cast_0 := - (cast);
twdlIn_re := cast_0(16 DOWNTO 0);
cast_5 := resize(twiddleReg_re, 18);
cast_6 := - (cast_5);
twdlIn_im := cast_6(16 DOWNTO 0);
WHEN "010" =>
twdlIn_re := twiddleReg_im;
cast_7 := resize(twiddleReg_re, 18);
cast_8 := - (cast_7);
twdlIn_im := cast_8(16 DOWNTO 0);
WHEN "011" =>
cast_1 := resize(twiddleReg_re, 18);
cast_2 := - (cast_1);
twdlIn_re := cast_2(16 DOWNTO 0);
twdlIn_im := twiddleReg_im;
WHEN "100" =>
cast_3 := resize(twiddleReg_re, 18);
cast_4 := - (cast_3);
twdlIn_re := cast_4(16 DOWNTO 0);
cast_9 := resize(twiddleReg_im, 18);
cast_10 := - (cast_9);
twdlIn_im := cast_10(16 DOWNTO 0);
WHEN OTHERS =>
twdlIn_re := twiddleReg_im;
twdlIn_im := twiddleReg_re;
END CASE;
END IF;
twdl_3_15_re_tmp <= twdlIn_re;
twdl_3_15_im_tmp <= twdlIn_im;
END PROCESS Radix22TwdlOctCorr_output;
twdl_3_15_re <= std_logic_vector(twdl_3_15_re_tmp);
twdl_3_15_im <= std_logic_vector(twdl_3_15_im_tmp);
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_3_15_vld <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twdl_3_15_vld <= twdlAddrVld;
END IF;
END IF;
END PROCESS intdelay_2_process;
END rtl;
|
-- megafunction wizard: %FIFO%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: dcfifo_mixed_widths
-- ============================================================
-- File Name: rgmi2gmii_fifo.vhd
-- Megafunction Name(s):
-- dcfifo_mixed_widths
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 13.1.0 Build 162 10/23/2013 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2013 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY rgmii2gmii_fifo IS
PORT
(
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
rdempty : OUT STD_LOGIC
);
END rgmii2gmii_fifo;
ARCHITECTURE SYN OF rgmii2gmii_fifo IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
COMPONENT dcfifo_mixed_widths
GENERIC (
intended_device_family : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
lpm_widthu_r : NATURAL;
lpm_width_r : NATURAL;
overflow_checking : STRING;
rdsync_delaypipe : NATURAL;
underflow_checking : STRING;
use_eab : STRING;
wrsync_delaypipe : NATURAL
);
PORT (
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
rdempty : OUT STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC
);
END COMPONENT;
BEGIN
q <= sub_wire0(7 DOWNTO 0);
rdempty <= sub_wire1;
dcfifo_mixed_widths_component : dcfifo_mixed_widths
GENERIC MAP (
intended_device_family => "Cyclone III",
lpm_numwords => 32,
lpm_showahead => "OFF",
lpm_type => "dcfifo_mixed_widths",
lpm_width => 4,
lpm_widthu => 5,
lpm_widthu_r => 4,
lpm_width_r => 8,
overflow_checking => "ON",
rdsync_delaypipe => 4,
underflow_checking => "ON",
use_eab => "ON",
wrsync_delaypipe => 4
)
PORT MAP (
data => data,
rdclk => rdclk,
rdreq => rdreq,
wrclk => wrclk,
wrreq => wrreq,
q => sub_wire0,
rdempty => sub_wire1
);
END SYN;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inline_01a is
end entity inline_01a;
----------------------------------------------------------------
-- code from book:
library widget_parts, wasp_lib;
use widget_parts.capacitor;
-- end of code from book
architecture test of inline_01a is
terminal node3 : electrical;
begin
-- code from book:
C1 : entity capacitor
port map ( node1 => node3, node2 => ground );
-- end of code from book
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inline_01a is
end entity inline_01a;
----------------------------------------------------------------
-- code from book:
library widget_parts, wasp_lib;
use widget_parts.capacitor;
-- end of code from book
architecture test of inline_01a is
terminal node3 : electrical;
begin
-- code from book:
C1 : entity capacitor
port map ( node1 => node3, node2 => ground );
-- end of code from book
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inline_01a is
end entity inline_01a;
----------------------------------------------------------------
-- code from book:
library widget_parts, wasp_lib;
use widget_parts.capacitor;
-- end of code from book
architecture test of inline_01a is
terminal node3 : electrical;
begin
-- code from book:
C1 : entity capacitor
port map ( node1 => node3, node2 => ground );
-- end of code from book
end architecture test;
|
-------------------------------------------------------------------------------
-- File Name : HostIF.vhd
--
-- Project : JPEG_ENC
--
-- Module : HostIF
--
-- Content : Host Interface (Xilinx OPB v2.1)
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090301: (MK): Initial Creation.
-------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity HostIF is
port
(
CLK : in std_logic;
RST : in std_logic;
-- OPB
OPB_ABus : in std_logic_vector(11 downto 0);
OPB_BE : in std_logic_vector(3 downto 0);
OPB_DBus_in : in std_logic_vector(31 downto 0);
OPB_RNW : in std_logic;
OPB_select : in std_logic;
OPB_DBus_out : out std_logic_vector(31 downto 0);
OPB_XferAck : out std_logic;
OPB_retry : out std_logic;
OPB_toutSup : out std_logic;
OPB_errAck : out std_logic;
-- Quantizer RAM
qdata : out std_logic_vector(7 downto 0);
qaddr : out std_logic_vector(6 downto 0);
qwren : out std_logic;
-- CTRL
jpeg_ready : in std_logic;
jpeg_busy : in std_logic;
-- ByteStuffer
outram_base_addr : out std_logic_vector(9 downto 0);
num_enc_bytes : in std_logic_vector(23 downto 0);
-- others
img_size_x : out std_logic_vector(15 downto 0);
img_size_y : out std_logic_vector(15 downto 0);
img_size_wr : out std_logic;
sof : out std_logic
);
end entity HostIF;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of HostIF is
constant C_ENC_START_REG : std_logic_vector(11 downto 0) := X"000";
constant C_IMAGE_SIZE_REG : std_logic_vector(11 downto 0) := X"004";
constant C_IMAGE_RAM_ACCESS_REG : std_logic_vector(11 downto 0) := X"008";
constant C_ENC_STS_REG : std_logic_vector(11 downto 0) := X"00C";
constant C_COD_DATA_ADDR_REG : std_logic_vector(11 downto 0) := X"010";
constant C_ENC_LENGTH_REG : std_logic_vector(11 downto 0) := X"014";
constant C_QUANTIZER_RAM_LUM_BASE : std_logic_vector(11 downto 0) := X"100";
constant C_QUANTIZER_RAM_CHR_BASE : std_logic_vector(11 downto 0) := X"200";
signal enc_start_reg : std_logic_vector(31 downto 0);
signal image_size_reg : std_logic_vector(31 downto 0);
signal image_ram_access_reg : std_logic_vector(31 downto 0);
signal enc_sts_reg : std_logic_vector(31 downto 0);
signal cod_data_addr_reg : std_logic_vector(31 downto 0);
signal read_ack : std_logic;
signal write_ack : std_logic;
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
OPB_retry <= '0';
OPB_toutSup <= '0';
OPB_errAck <= '0';
img_size_x <= image_size_reg(31 downto 16);
img_size_y <= image_size_reg(15 downto 0);
outram_base_addr <= cod_data_addr_reg(outram_base_addr'range);
-------------------------------------------------------------------
-- OPB read
-------------------------------------------------------------------
p_read : process(CLK, RST)
begin
if RST = '1' then
read_ack <= '0';
OPB_DBus_out <= (others => '0');
elsif CLK'event and CLK = '1' then
read_ack <= '0';
if OPB_select = '1' and read_ack = '0' then
-- only double word transactions are be supported
if OPB_RNW = '1' and OPB_BE = X"F" then
read_ack <= '1';
case OPB_ABus is
when C_ENC_START_REG =>
OPB_DBus_out <= enc_start_reg;
when C_IMAGE_SIZE_REG =>
OPB_DBus_out <= image_size_reg;
when C_IMAGE_RAM_ACCESS_REG =>
OPB_DBus_out <= image_ram_access_reg;
when C_ENC_STS_REG =>
OPB_DBus_out <= enc_sts_reg;
when C_COD_DATA_ADDR_REG =>
OPB_DBus_out <= cod_data_addr_reg;
when C_ENC_LENGTH_REG =>
OPB_DBus_out(31 downto 24) <= (others => '0');
OPB_DBus_out(23 downto 0) <= num_enc_bytes;
when others =>
OPB_DBus_out <= (others => '0');
end case;
end if;
end if;
end if;
end process;
-------------------------------------------------------------------
-- OPB write
-------------------------------------------------------------------
p_write : process(CLK, RST)
begin
if RST = '1' then
qwren <= '0';
write_ack <= '0';
enc_start_reg <= (others => '0');
image_size_reg <= (others => '0');
image_ram_access_reg <= (others => '0');
enc_sts_reg <= (others => '0');
cod_data_addr_reg <= (others => '0');
qdata <= (others => '0');
qaddr <= (others => '0');
sof <= '0';
img_size_wr <= '0';
elsif CLK'event and CLK = '1' then
qwren <= '0';
write_ack <= '0';
sof <= '0';
img_size_wr <= '0';
if OPB_select = '1' and write_ack = '0' then
-- only double word transactions are be supported
if OPB_RNW = '0' and OPB_BE = X"F" then
write_ack <= '1';
case OPB_ABus is
when C_ENC_START_REG =>
enc_start_reg <= OPB_DBus_in;
if OPB_DBus_in(0) = '1' then
sof <= '1';
end if;
when C_IMAGE_SIZE_REG =>
image_size_reg <= OPB_DBus_in;
img_size_wr <= '1';
when C_IMAGE_RAM_ACCESS_REG =>
image_ram_access_reg <= OPB_DBus_in;
when C_ENC_STS_REG =>
enc_sts_reg <= (others => '0');
when C_COD_DATA_ADDR_REG =>
cod_data_addr_reg <= OPB_DBus_in;
when C_ENC_LENGTH_REG =>
--enc_length_reg <= OPB_DBus_in;
when others =>
if OPB_ABus(11 downto 8) = C_QUANTIZER_RAM_LUM_BASE(11 downto 8) then
qwren <= '1';
qaddr <= '0' & OPB_ABus(qaddr'high+2-1 downto 2);
elsif OPB_ABus(11 downto 8) = C_QUANTIZER_RAM_CHR_BASE(11 downto 8) then
qwren <= '1';
qaddr <= '1' & OPB_ABus(qaddr'high+2-1 downto 2);
end if;
end case;
end if;
qdata <= OPB_DBus_in(qdata'range);
end if;
-- special handling of status reg
if jpeg_ready = '1' then
-- set jpeg done flag
enc_sts_reg(1) <= '1';
end if;
enc_sts_reg(0) <= jpeg_busy;
end if;
end process;
-------------------------------------------------------------------
-- transfer ACK
-------------------------------------------------------------------
OPB_XferAck <= read_ack or write_ack;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- |
-------------------------------------------------------------------------------
-- File Name : HostIF.vhd
--
-- Project : JPEG_ENC
--
-- Module : HostIF
--
-- Content : Host Interface (Xilinx OPB v2.1)
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090301: (MK): Initial Creation.
-------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity HostIF is
port
(
CLK : in std_logic;
RST : in std_logic;
-- OPB
OPB_ABus : in std_logic_vector(11 downto 0);
OPB_BE : in std_logic_vector(3 downto 0);
OPB_DBus_in : in std_logic_vector(31 downto 0);
OPB_RNW : in std_logic;
OPB_select : in std_logic;
OPB_DBus_out : out std_logic_vector(31 downto 0);
OPB_XferAck : out std_logic;
OPB_retry : out std_logic;
OPB_toutSup : out std_logic;
OPB_errAck : out std_logic;
-- Quantizer RAM
qdata : out std_logic_vector(7 downto 0);
qaddr : out std_logic_vector(6 downto 0);
qwren : out std_logic;
-- CTRL
jpeg_ready : in std_logic;
jpeg_busy : in std_logic;
-- ByteStuffer
outram_base_addr : out std_logic_vector(9 downto 0);
num_enc_bytes : in std_logic_vector(23 downto 0);
-- others
img_size_x : out std_logic_vector(15 downto 0);
img_size_y : out std_logic_vector(15 downto 0);
img_size_wr : out std_logic;
sof : out std_logic
);
end entity HostIF;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of HostIF is
constant C_ENC_START_REG : std_logic_vector(11 downto 0) := X"000";
constant C_IMAGE_SIZE_REG : std_logic_vector(11 downto 0) := X"004";
constant C_IMAGE_RAM_ACCESS_REG : std_logic_vector(11 downto 0) := X"008";
constant C_ENC_STS_REG : std_logic_vector(11 downto 0) := X"00C";
constant C_COD_DATA_ADDR_REG : std_logic_vector(11 downto 0) := X"010";
constant C_ENC_LENGTH_REG : std_logic_vector(11 downto 0) := X"014";
constant C_QUANTIZER_RAM_LUM_BASE : std_logic_vector(11 downto 0) := X"100";
constant C_QUANTIZER_RAM_CHR_BASE : std_logic_vector(11 downto 0) := X"200";
signal enc_start_reg : std_logic_vector(31 downto 0);
signal image_size_reg : std_logic_vector(31 downto 0);
signal image_ram_access_reg : std_logic_vector(31 downto 0);
signal enc_sts_reg : std_logic_vector(31 downto 0);
signal cod_data_addr_reg : std_logic_vector(31 downto 0);
signal read_ack : std_logic;
signal write_ack : std_logic;
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
OPB_retry <= '0';
OPB_toutSup <= '0';
OPB_errAck <= '0';
img_size_x <= image_size_reg(31 downto 16);
img_size_y <= image_size_reg(15 downto 0);
outram_base_addr <= cod_data_addr_reg(outram_base_addr'range);
-------------------------------------------------------------------
-- OPB read
-------------------------------------------------------------------
p_read : process(CLK, RST)
begin
if RST = '1' then
read_ack <= '0';
OPB_DBus_out <= (others => '0');
elsif CLK'event and CLK = '1' then
read_ack <= '0';
if OPB_select = '1' and read_ack = '0' then
-- only double word transactions are be supported
if OPB_RNW = '1' and OPB_BE = X"F" then
read_ack <= '1';
case OPB_ABus is
when C_ENC_START_REG =>
OPB_DBus_out <= enc_start_reg;
when C_IMAGE_SIZE_REG =>
OPB_DBus_out <= image_size_reg;
when C_IMAGE_RAM_ACCESS_REG =>
OPB_DBus_out <= image_ram_access_reg;
when C_ENC_STS_REG =>
OPB_DBus_out <= enc_sts_reg;
when C_COD_DATA_ADDR_REG =>
OPB_DBus_out <= cod_data_addr_reg;
when C_ENC_LENGTH_REG =>
OPB_DBus_out(31 downto 24) <= (others => '0');
OPB_DBus_out(23 downto 0) <= num_enc_bytes;
when others =>
OPB_DBus_out <= (others => '0');
end case;
end if;
end if;
end if;
end process;
-------------------------------------------------------------------
-- OPB write
-------------------------------------------------------------------
p_write : process(CLK, RST)
begin
if RST = '1' then
qwren <= '0';
write_ack <= '0';
enc_start_reg <= (others => '0');
image_size_reg <= (others => '0');
image_ram_access_reg <= (others => '0');
enc_sts_reg <= (others => '0');
cod_data_addr_reg <= (others => '0');
qdata <= (others => '0');
qaddr <= (others => '0');
sof <= '0';
img_size_wr <= '0';
elsif CLK'event and CLK = '1' then
qwren <= '0';
write_ack <= '0';
sof <= '0';
img_size_wr <= '0';
if OPB_select = '1' and write_ack = '0' then
-- only double word transactions are be supported
if OPB_RNW = '0' and OPB_BE = X"F" then
write_ack <= '1';
case OPB_ABus is
when C_ENC_START_REG =>
enc_start_reg <= OPB_DBus_in;
if OPB_DBus_in(0) = '1' then
sof <= '1';
end if;
when C_IMAGE_SIZE_REG =>
image_size_reg <= OPB_DBus_in;
img_size_wr <= '1';
when C_IMAGE_RAM_ACCESS_REG =>
image_ram_access_reg <= OPB_DBus_in;
when C_ENC_STS_REG =>
enc_sts_reg <= (others => '0');
when C_COD_DATA_ADDR_REG =>
cod_data_addr_reg <= OPB_DBus_in;
when C_ENC_LENGTH_REG =>
--enc_length_reg <= OPB_DBus_in;
when others =>
if OPB_ABus(11 downto 8) = C_QUANTIZER_RAM_LUM_BASE(11 downto 8) then
qwren <= '1';
qaddr <= '0' & OPB_ABus(qaddr'high+2-1 downto 2);
elsif OPB_ABus(11 downto 8) = C_QUANTIZER_RAM_CHR_BASE(11 downto 8) then
qwren <= '1';
qaddr <= '1' & OPB_ABus(qaddr'high+2-1 downto 2);
end if;
end case;
end if;
qdata <= OPB_DBus_in(qdata'range);
end if;
-- special handling of status reg
if jpeg_ready = '1' then
-- set jpeg done flag
enc_sts_reg(1) <= '1';
end if;
enc_sts_reg(0) <= jpeg_busy;
end if;
end process;
-------------------------------------------------------------------
-- transfer ACK
-------------------------------------------------------------------
OPB_XferAck <= read_ack or write_ack;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2162.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p22n01i02162ent IS
END c07s02b04x00p22n01i02162ent;
ARCHITECTURE c07s02b04x00p22n01i02162arch OF c07s02b04x00p22n01i02162ent IS
TYPE simple_record is record
data_1 : integer;
data_2 : integer;
end record;
TYPE record_v is array (integer range <>) of simple_record;
SUBTYPE record_2 is record_v (1 to 2);
BEGIN
TESTING: PROCESS
variable result : record_2;
variable l_operand : simple_record := (12,34) ;
variable r_operand : simple_record := (56,78) ;
BEGIN
--
-- The element is treated as an implicit single element array !
--
result := l_operand & r_operand;
wait for 5 ns;
assert NOT(result = ( (12,34), (56,78) ))
report "***PASSED TEST: c07s02b04x00p22n01i02162"
severity NOTE;
assert (result = ( (12,34), (56,78) ))
report "***FAILED TEST: c07s02b04x00p22n01i02162 - Concatenation of record element and element failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p22n01i02162arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2162.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p22n01i02162ent IS
END c07s02b04x00p22n01i02162ent;
ARCHITECTURE c07s02b04x00p22n01i02162arch OF c07s02b04x00p22n01i02162ent IS
TYPE simple_record is record
data_1 : integer;
data_2 : integer;
end record;
TYPE record_v is array (integer range <>) of simple_record;
SUBTYPE record_2 is record_v (1 to 2);
BEGIN
TESTING: PROCESS
variable result : record_2;
variable l_operand : simple_record := (12,34) ;
variable r_operand : simple_record := (56,78) ;
BEGIN
--
-- The element is treated as an implicit single element array !
--
result := l_operand & r_operand;
wait for 5 ns;
assert NOT(result = ( (12,34), (56,78) ))
report "***PASSED TEST: c07s02b04x00p22n01i02162"
severity NOTE;
assert (result = ( (12,34), (56,78) ))
report "***FAILED TEST: c07s02b04x00p22n01i02162 - Concatenation of record element and element failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p22n01i02162arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2162.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p22n01i02162ent IS
END c07s02b04x00p22n01i02162ent;
ARCHITECTURE c07s02b04x00p22n01i02162arch OF c07s02b04x00p22n01i02162ent IS
TYPE simple_record is record
data_1 : integer;
data_2 : integer;
end record;
TYPE record_v is array (integer range <>) of simple_record;
SUBTYPE record_2 is record_v (1 to 2);
BEGIN
TESTING: PROCESS
variable result : record_2;
variable l_operand : simple_record := (12,34) ;
variable r_operand : simple_record := (56,78) ;
BEGIN
--
-- The element is treated as an implicit single element array !
--
result := l_operand & r_operand;
wait for 5 ns;
assert NOT(result = ( (12,34), (56,78) ))
report "***PASSED TEST: c07s02b04x00p22n01i02162"
severity NOTE;
assert (result = ( (12,34), (56,78) ))
report "***FAILED TEST: c07s02b04x00p22n01i02162 - Concatenation of record element and element failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p22n01i02162arch;
|
-- $Id: pdp11_dmscnt.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_dmscnt - syn
-- Description: pdp11: debug&moni: state counter
--
-- Dependencies: memlib/ram_2swsr_rfirst_gen
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: ise 14.7; viv 2014.4-2019.1; ghdl 0.31-0.35
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2015-06-26 695 14.7 131013 xc6slx16-2 91 107 0 41 s 5.4
--
-- Revision History: -
-- Date Rev Version Comment
-- 2019-06-02 1159 1.1.2 use rbaddr_ constants
-- 2016-05-22 767 1.1.1 don't init N_REGS (vivado fix for fsm inference)
-- 2015-12-28 721 1.1 use laddr/waddr; use ena instead of cnt;
-- 2015-07-19 702 1.0 Initial version
-- 2015-06-26 695 0.1 First draft
------------------------------------------------------------------------------
--
-- rbus registers:
--
-- Addr Bits Name r/w/f Function
--
-- 00 cntl r/w/- control
-- 01 clr r/w/- if 1 starts mem clear
-- 00 ena r/w/- if 1 enables counting
-- 01 addr r/w/- memory address
-- 10:02 laddr r/w/- line address (state number)
-- 01:00 waddr r/-/- word address (cleared on write)
-- 10 15:00 data r/-/- memory data
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.rblib.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_dmscnt is -- debug&moni: state counter
generic (
RB_ADDR : slv16 := rbaddr_dmscnt_off);
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
DM_STAT_SE : in dm_stat_se_type; -- debug and monitor status - sequencer
DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status - data path
DM_STAT_CO : in dm_stat_co_type -- debug and monitor status - core
);
end pdp11_dmscnt;
architecture syn of pdp11_dmscnt is
constant rbaddr_cntl : slv2 := "00"; -- cntl address offset
constant rbaddr_addr : slv2 := "01"; -- addr address offset
constant rbaddr_data : slv2 := "10"; -- data address offset
constant cntl_rbf_clr : integer := 1;
constant cntl_rbf_ena : integer := 0;
subtype addr_rbf_mem is integer range 10 downto 2;
subtype addr_rbf_word is integer range 1 downto 0;
type state_type is (
s_idle, -- s_idle: rbus access or count
s_mread -- s_mread: memory read
);
type regs_type is record
state : state_type; -- state
rbsel : slbit; -- rbus select
clr : slbit; -- clr flag
ena0 : slbit; -- ena flag
ena1 : slbit; -- ena flag (delayed)
snum0 : slv9; -- snum stage 0
snum1 : slv9; -- snum stage 1
same : slbit; -- same snum flag
laddr : slv9; -- line addr
waddr : slv2; -- word addr
scnt : slv(35 downto 0); -- scnt buffer
mbuf : slv20; -- lsb memory buffer
end record regs_type;
constant regs_init : regs_type := (
s_idle, -- state
'0', -- rbsel
'0','0','0', -- clr,ena0,ena1
(others=>'0'), -- snum0
(others=>'0'), -- snum1
'0', -- same
(others=>'0'), -- laddr
(others=>'0'), -- waddr
(others=>'0'), -- scnt
(others=>'0') -- mbuf
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type; -- don't init (vivado fix for fsm infer)
signal CMEM_CEA : slbit := '0';
signal CMEM_CEB : slbit := '0';
signal CMEM_WEA : slbit := '0';
signal CMEM_WEB : slbit := '0';
signal CMEM_ADDRA : slv9 := (others=>'0');
signal CMEM_DIB : slv(35 downto 0) := (others=>'0');
signal CMEM_DOA : slv(35 downto 0) := (others=>'0');
constant cmem_data_zero : slv(35 downto 0) := (others=>'0');
begin
CMEM : ram_2swsr_rfirst_gen
generic map (
AWIDTH => 9,
DWIDTH => 36)
port map (
CLKA => CLK,
CLKB => CLK,
ENA => CMEM_CEA,
ENB => CMEM_CEB,
WEA => CMEM_WEA,
WEB => CMEM_WEB,
ADDRA => CMEM_ADDRA,
ADDRB => R_REGS.snum1,
DIA => cmem_data_zero,
DIB => CMEM_DIB,
DOA => CMEM_DOA,
DOB => open
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next: process (R_REGS, RB_MREQ, DM_STAT_SE,
DM_STAT_DP, DM_STAT_DP.psw, -- xst needs sub-records
DM_STAT_CO, CMEM_DOA)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable irb_ack : slbit := '0';
variable irb_busy : slbit := '0';
variable irb_err : slbit := '0';
variable irb_dout : slv16 := (others=>'0');
variable irbena : slbit := '0';
variable icea : slbit := '0';
variable iwea : slbit := '0';
variable iweb : slbit := '0';
variable iaddra : slv9 := (others=>'0');
variable iscnt0 : slv(35 downto 0) := (others=>'0');
variable iscnt1 : slv(35 downto 0) := (others=>'0');
begin
r := R_REGS;
n := R_REGS;
irb_ack := '0';
irb_busy := '0';
irb_err := '0';
irb_dout := (others=>'0');
irbena := RB_MREQ.re or RB_MREQ.we;
icea := '0';
iwea := '0';
iweb := '0';
iaddra := r.snum0;
-- rbus address decoder
n.rbsel := '0';
if RB_MREQ.aval='1' then
if RB_MREQ.addr(15 downto 2)=RB_ADDR(15 downto 2) then
n.rbsel := '1';
end if;
end if;
case r.state is
when s_idle => -- s_idle: rbus access or count ------
-- rbus transactions
if r.rbsel = '1' then
irb_ack := irbena; -- ack all accesses
case RB_MREQ.addr(1 downto 0) is
when rbaddr_cntl => -- cntl ------------------
if RB_MREQ.we = '1' then
n.clr := RB_MREQ.din(cntl_rbf_clr);
if RB_MREQ.din(cntl_rbf_clr) = '1' then -- if clr set
n.laddr := (others=>'0'); -- reset mem addr
end if;
n.ena0 := RB_MREQ.din(cntl_rbf_ena);
end if;
when rbaddr_addr => -- addr ------------------
if RB_MREQ.we = '1' then
if r.clr = '1' then -- if clr active
irb_err := '1'; -- block addr writes
else -- otherwise
n.laddr := RB_MREQ.din(addr_rbf_mem); -- set mem addr
n.waddr := (others=>'0'); -- clr word addr
end if;
end if;
when rbaddr_data => -- data ------------------
if RB_MREQ.we = '1' then -- writes not allowed
irb_err := '1';
end if;
if RB_MREQ.re = '1' then
if r.clr = '1' then -- if clr active
irb_err := '1'; -- block data reads
else -- otherwise
case r.waddr is -- handle word addr
when "00" => -- 1st access
icea := '1'; -- enable mem read
iaddra := r.laddr; -- of current line
irb_busy := '1';
n.state := s_mread;
when "01" => -- 2nd part
n.waddr := "10"; -- inc word addr
when "10" => -- 3rd part
n.waddr := "00"; -- wrap to next line
n.laddr := slv(unsigned(r.laddr) + 1);
when others => null;
end case;
end if;
end if;
when others => -- <> --------------------
irb_err := '1';
end case;
end if;
when s_mread => --s_mread: memory read ---------------
irb_ack := irbena; -- ack access
n.waddr := "01"; -- inc word addr
n.mbuf := CMEM_DOA(35 downto 16); -- capture msb part
n.state := s_idle;
when others => null;
end case;
-- rbus output driver
if r.rbsel = '1' then
case RB_MREQ.addr(1 downto 0) is
when rbaddr_cntl => -- cntl ------------------
irb_dout(cntl_rbf_clr) := r.clr;
irb_dout(cntl_rbf_ena) := r.ena0;
when rbaddr_addr => -- addr ------------------
irb_dout(addr_rbf_mem) := r.laddr;
irb_dout(addr_rbf_word) := r.waddr;
when rbaddr_data => -- data ------------------
case r.waddr is
when "00" => irb_dout := CMEM_DOA(15 downto 0);
when "01" => irb_dout := r.mbuf(15 downto 0);
when "10" => irb_dout(3 downto 0) := r.mbuf(19 downto 16);
when others => null;
end case;
when others => null;
end case;
end if;
-- latch state number
-- 1 msb determined from cpu mode: 0 if kernel and 1 when user or super
-- 8 lsb taken from sequencer snum
n.snum0(8) := '0';
if DM_STAT_DP.psw.cmode /= c_psw_kmode then
n.snum0(8) := '1';
end if;
n.snum0(7 downto 0) := DM_STAT_SE.snum;
n.snum1 := r.snum0;
-- incrementer pipeline
n.same := '0';
if r.snum0=r.snum1 and r.ena1 ='1' then -- in same state ?
n.same := '1'; -- don't read mem and remember
else -- otherwise
icea := '1'; -- enable mem read
end if;
-- increment state count
if r.same = '0' then -- was mem read ?
iscnt0 := CMEM_DOA; -- take memory value
else -- otherwise
iscnt0 := r.scnt; -- use scnt reg
end if;
iscnt1 := slv(unsigned(iscnt0) + 1); -- increment
n.scnt := iscnt1; -- and store
-- finally setup memory access
n.ena1 := r.ena0;
if r.clr = '1' then -- mem clear action
icea := '1';
iwea := '1';
iaddra := r.laddr;
n.laddr := slv(unsigned(r.laddr) + 1);
if r.laddr = "111111111" then
n.clr := '0';
end if;
elsif r.ena1 = '1' then -- state count action
iweb := '1';
end if;
N_REGS <= n;
CMEM_CEA <= icea;
CMEM_CEB <= iweb;
CMEM_WEA <= iwea;
CMEM_WEB <= iweb;
CMEM_ADDRA <= iaddra;
CMEM_DIB <= iscnt1;
RB_SRES.ack <= irb_ack;
RB_SRES.err <= irb_err;
RB_SRES.busy <= irb_busy;
RB_SRES.dout <= irb_dout;
end process proc_next;
end syn;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
Bds85+dGMeCsD7hcir1yMlD7vI3TxE/REkPnx8PwdLXDvto8RvBWcd2kdr6GYLOjf4YCuyZymrYJ
5GH7YkzIwQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
C6h1CCNWEgO7EUKAL/CRgXRzcW+RA97RWjh/l30pdyXuP1Xh05NFvOimQ4WrD4pBnDcaF8Hj+jOF
QbJOmFWQUyqCbK7gf8QDLcLapOMJv98IuE3h1+EI8TgktIn5/kUDGyhwEaZ0GVA2ssADSiwedB09
BugvAqGcFiYjbWTkwYY=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
nV+3dfcQQtizCD4IvxWM+E2x1KiaejJmvBiJRPCc/Gr+d6qGz6skRXcO4PVrsIJUFbMrIvGRnAJj
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 117312)
`protect data_block
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AFhXIB9h
`protect end_protected
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 48 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 960 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(3) = '1') THEN
assert false
report "Almost Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(4) = '1') THEN
assert false
report "Almost Full flag Mismatch/timeout"
severity error;
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 101
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_top.vhd
--
-- Description:
-- This is the demo testbench top file for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
LIBRARY std;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_misc.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_textio.ALL;
USE std.textio.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_top IS
END ENTITY;
ARCHITECTURE fg_tb_arch OF fg_tb_top IS
SIGNAL status : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
SIGNAL wr_clk : STD_LOGIC;
SIGNAL reset : STD_LOGIC;
SIGNAL sim_done : STD_LOGIC := '0';
SIGNAL end_of_sim : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '0');
-- Write and Read clock periods
CONSTANT wr_clk_period_by_2 : TIME := 48 ns;
-- Procedures to display strings
PROCEDURE disp_str(CONSTANT str:IN STRING) IS
variable dp_l : line := null;
BEGIN
write(dp_l,str);
writeline(output,dp_l);
END PROCEDURE;
PROCEDURE disp_hex(signal hex:IN STD_LOGIC_VECTOR(7 DOWNTO 0)) IS
variable dp_lx : line := null;
BEGIN
hwrite(dp_lx,hex);
writeline(output,dp_lx);
END PROCEDURE;
BEGIN
-- Generation of clock
PROCESS BEGIN
WAIT FOR 110 ns; -- Wait for global reset
WHILE 1 = 1 LOOP
wr_clk <= '0';
WAIT FOR wr_clk_period_by_2;
wr_clk <= '1';
WAIT FOR wr_clk_period_by_2;
END LOOP;
END PROCESS;
-- Generation of Reset
PROCESS BEGIN
reset <= '1';
WAIT FOR 960 ns;
reset <= '0';
WAIT;
END PROCESS;
-- Error message printing based on STATUS signal from fg_tb_synth
PROCESS(status)
BEGIN
IF(status /= "0" AND status /= "1") THEN
disp_str("STATUS:");
disp_hex(status);
END IF;
IF(status(7) = '1') THEN
assert false
report "Data mismatch found"
severity error;
END IF;
IF(status(1) = '1') THEN
END IF;
IF(status(3) = '1') THEN
assert false
report "Almost Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(4) = '1') THEN
assert false
report "Almost Full flag Mismatch/timeout"
severity error;
END IF;
IF(status(5) = '1') THEN
assert false
report "Empty flag Mismatch/timeout"
severity error;
END IF;
IF(status(6) = '1') THEN
assert false
report "Full Flag Mismatch/timeout"
severity error;
END IF;
END PROCESS;
PROCESS
BEGIN
wait until sim_done = '1';
IF(status /= "0" AND status /= "1") THEN
assert false
report "Simulation failed"
severity failure;
ELSE
assert false
report "Simulation Complete"
severity failure;
END IF;
END PROCESS;
PROCESS
BEGIN
wait for 100 ms;
assert false
report "Test bench timed out"
severity failure;
END PROCESS;
-- Instance of fg_tb_synth
fg_tb_synth_inst:fg_tb_synth
GENERIC MAP(
FREEZEON_ERROR => 0,
TB_STOP_CNT => 2,
TB_SEED => 101
)
PORT MAP(
CLK => wr_clk,
RESET => reset,
SIM_DONE => sim_done,
STATUS => status
);
END ARCHITECTURE;
|
library verilog;
use verilog.vl_types.all;
entity BFM_AHBSLAVEEXT is
generic(
AWIDTH : integer := 10;
DEPTH : integer := 256;
EXT_SIZE : integer := 2;
INITFILE : string := " ";
ID : integer := 0;
ENFUNC : integer := 0;
ENFIFO : integer := 0;
TPD : integer := 1;
DEBUG : integer := -1
);
port(
HCLK : in vl_logic;
HRESETN : in vl_logic;
HSEL : in vl_logic;
HWRITE : in vl_logic;
HADDR : in vl_logic_vector;
HWDATA : in vl_logic_vector(31 downto 0);
HRDATA : out vl_logic_vector(31 downto 0);
HREADYIN : in vl_logic;
HREADYOUT : out vl_logic;
HTRANS : in vl_logic_vector(1 downto 0);
HSIZE : in vl_logic_vector(2 downto 0);
HBURST : in vl_logic_vector(2 downto 0);
HMASTLOCK : in vl_logic;
HPROT : in vl_logic_vector(3 downto 0);
HRESP : out vl_logic;
EXT_EN : in vl_logic;
EXT_WR : in vl_logic;
EXT_RD : in vl_logic;
EXT_ADDR : in vl_logic_vector;
EXT_DATA : inout vl_logic_vector(31 downto 0);
TXREADY : out vl_logic;
RXREADY : out vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of AWIDTH : constant is 1;
attribute mti_svvh_generic_type of DEPTH : constant is 1;
attribute mti_svvh_generic_type of EXT_SIZE : constant is 1;
attribute mti_svvh_generic_type of INITFILE : constant is 1;
attribute mti_svvh_generic_type of ID : constant is 1;
attribute mti_svvh_generic_type of ENFUNC : constant is 1;
attribute mti_svvh_generic_type of ENFIFO : constant is 1;
attribute mti_svvh_generic_type of TPD : constant is 1;
attribute mti_svvh_generic_type of DEBUG : constant is 1;
end BFM_AHBSLAVEEXT;
|
library verilog;
use verilog.vl_types.all;
entity BFM_AHBSLAVEEXT is
generic(
AWIDTH : integer := 10;
DEPTH : integer := 256;
EXT_SIZE : integer := 2;
INITFILE : string := " ";
ID : integer := 0;
ENFUNC : integer := 0;
ENFIFO : integer := 0;
TPD : integer := 1;
DEBUG : integer := -1
);
port(
HCLK : in vl_logic;
HRESETN : in vl_logic;
HSEL : in vl_logic;
HWRITE : in vl_logic;
HADDR : in vl_logic_vector;
HWDATA : in vl_logic_vector(31 downto 0);
HRDATA : out vl_logic_vector(31 downto 0);
HREADYIN : in vl_logic;
HREADYOUT : out vl_logic;
HTRANS : in vl_logic_vector(1 downto 0);
HSIZE : in vl_logic_vector(2 downto 0);
HBURST : in vl_logic_vector(2 downto 0);
HMASTLOCK : in vl_logic;
HPROT : in vl_logic_vector(3 downto 0);
HRESP : out vl_logic;
EXT_EN : in vl_logic;
EXT_WR : in vl_logic;
EXT_RD : in vl_logic;
EXT_ADDR : in vl_logic_vector;
EXT_DATA : inout vl_logic_vector(31 downto 0);
TXREADY : out vl_logic;
RXREADY : out vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of AWIDTH : constant is 1;
attribute mti_svvh_generic_type of DEPTH : constant is 1;
attribute mti_svvh_generic_type of EXT_SIZE : constant is 1;
attribute mti_svvh_generic_type of INITFILE : constant is 1;
attribute mti_svvh_generic_type of ID : constant is 1;
attribute mti_svvh_generic_type of ENFUNC : constant is 1;
attribute mti_svvh_generic_type of ENFIFO : constant is 1;
attribute mti_svvh_generic_type of TPD : constant is 1;
attribute mti_svvh_generic_type of DEBUG : constant is 1;
end BFM_AHBSLAVEEXT;
|
-- File: gray_inc_reg.vhd
-- Generated by MyHDL 1.0dev
-- Date: Thu Jun 23 19:06:43 2016
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_10.all;
entity gray_inc_reg is
port (
graycnt: out unsigned(7 downto 0);
enable: in std_logic;
clock: in std_logic;
reset: in std_logic
);
end entity gray_inc_reg;
architecture MyHDL of gray_inc_reg is
signal graycnt_comb: unsigned(7 downto 0);
signal gray_inc_1_bincnt: unsigned(7 downto 0);
begin
GRAY_INC_REG_GRAY_INC_1_INC_1_SEQ: process (clock, reset) is
begin
if (reset = '0') then
gray_inc_1_bincnt <= to_unsigned(0, 8);
elsif rising_edge(clock) then
if bool(enable) then
gray_inc_1_bincnt <= (gray_inc_1_bincnt + 1);
end if;
end if;
end process GRAY_INC_REG_GRAY_INC_1_INC_1_SEQ;
graycnt_comb <= (shift_right(gray_inc_1_bincnt, 1) xor gray_inc_1_bincnt);
GRAY_INC_REG_REG_0: process (clock, reset) is
begin
if (reset = '0') then
graycnt <= to_unsigned(0, 8);
elsif rising_edge(clock) then
graycnt <= graycnt_comb;
end if;
end process GRAY_INC_REG_REG_0;
end architecture MyHDL;
|
-- File: gray_inc_reg.vhd
-- Generated by MyHDL 1.0dev
-- Date: Thu Jun 23 19:06:43 2016
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_10.all;
entity gray_inc_reg is
port (
graycnt: out unsigned(7 downto 0);
enable: in std_logic;
clock: in std_logic;
reset: in std_logic
);
end entity gray_inc_reg;
architecture MyHDL of gray_inc_reg is
signal graycnt_comb: unsigned(7 downto 0);
signal gray_inc_1_bincnt: unsigned(7 downto 0);
begin
GRAY_INC_REG_GRAY_INC_1_INC_1_SEQ: process (clock, reset) is
begin
if (reset = '0') then
gray_inc_1_bincnt <= to_unsigned(0, 8);
elsif rising_edge(clock) then
if bool(enable) then
gray_inc_1_bincnt <= (gray_inc_1_bincnt + 1);
end if;
end if;
end process GRAY_INC_REG_GRAY_INC_1_INC_1_SEQ;
graycnt_comb <= (shift_right(gray_inc_1_bincnt, 1) xor gray_inc_1_bincnt);
GRAY_INC_REG_REG_0: process (clock, reset) is
begin
if (reset = '0') then
graycnt <= to_unsigned(0, 8);
elsif rising_edge(clock) then
graycnt <= graycnt_comb;
end if;
end process GRAY_INC_REG_REG_0;
end architecture MyHDL;
|
-- File: gray_inc_reg.vhd
-- Generated by MyHDL 1.0dev
-- Date: Thu Jun 23 19:06:43 2016
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_10.all;
entity gray_inc_reg is
port (
graycnt: out unsigned(7 downto 0);
enable: in std_logic;
clock: in std_logic;
reset: in std_logic
);
end entity gray_inc_reg;
architecture MyHDL of gray_inc_reg is
signal graycnt_comb: unsigned(7 downto 0);
signal gray_inc_1_bincnt: unsigned(7 downto 0);
begin
GRAY_INC_REG_GRAY_INC_1_INC_1_SEQ: process (clock, reset) is
begin
if (reset = '0') then
gray_inc_1_bincnt <= to_unsigned(0, 8);
elsif rising_edge(clock) then
if bool(enable) then
gray_inc_1_bincnt <= (gray_inc_1_bincnt + 1);
end if;
end if;
end process GRAY_INC_REG_GRAY_INC_1_INC_1_SEQ;
graycnt_comb <= (shift_right(gray_inc_1_bincnt, 1) xor gray_inc_1_bincnt);
GRAY_INC_REG_REG_0: process (clock, reset) is
begin
if (reset = '0') then
graycnt <= to_unsigned(0, 8);
elsif rising_edge(clock) then
graycnt <= graycnt_comb;
end if;
end process GRAY_INC_REG_REG_0;
end architecture MyHDL;
|
-- File: gray_inc_reg.vhd
-- Generated by MyHDL 1.0dev
-- Date: Thu Jun 23 19:06:43 2016
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_10.all;
entity gray_inc_reg is
port (
graycnt: out unsigned(7 downto 0);
enable: in std_logic;
clock: in std_logic;
reset: in std_logic
);
end entity gray_inc_reg;
architecture MyHDL of gray_inc_reg is
signal graycnt_comb: unsigned(7 downto 0);
signal gray_inc_1_bincnt: unsigned(7 downto 0);
begin
GRAY_INC_REG_GRAY_INC_1_INC_1_SEQ: process (clock, reset) is
begin
if (reset = '0') then
gray_inc_1_bincnt <= to_unsigned(0, 8);
elsif rising_edge(clock) then
if bool(enable) then
gray_inc_1_bincnt <= (gray_inc_1_bincnt + 1);
end if;
end if;
end process GRAY_INC_REG_GRAY_INC_1_INC_1_SEQ;
graycnt_comb <= (shift_right(gray_inc_1_bincnt, 1) xor gray_inc_1_bincnt);
GRAY_INC_REG_REG_0: process (clock, reset) is
begin
if (reset = '0') then
graycnt <= to_unsigned(0, 8);
elsif rising_edge(clock) then
graycnt <= graycnt_comb;
end if;
end process GRAY_INC_REG_REG_0;
end architecture MyHDL;
|
-- File: gray_inc_reg.vhd
-- Generated by MyHDL 1.0dev
-- Date: Thu Jun 23 19:06:43 2016
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_10.all;
entity gray_inc_reg is
port (
graycnt: out unsigned(7 downto 0);
enable: in std_logic;
clock: in std_logic;
reset: in std_logic
);
end entity gray_inc_reg;
architecture MyHDL of gray_inc_reg is
signal graycnt_comb: unsigned(7 downto 0);
signal gray_inc_1_bincnt: unsigned(7 downto 0);
begin
GRAY_INC_REG_GRAY_INC_1_INC_1_SEQ: process (clock, reset) is
begin
if (reset = '0') then
gray_inc_1_bincnt <= to_unsigned(0, 8);
elsif rising_edge(clock) then
if bool(enable) then
gray_inc_1_bincnt <= (gray_inc_1_bincnt + 1);
end if;
end if;
end process GRAY_INC_REG_GRAY_INC_1_INC_1_SEQ;
graycnt_comb <= (shift_right(gray_inc_1_bincnt, 1) xor gray_inc_1_bincnt);
GRAY_INC_REG_REG_0: process (clock, reset) is
begin
if (reset = '0') then
graycnt <= to_unsigned(0, 8);
elsif rising_edge(clock) then
graycnt <= graycnt_comb;
end if;
end process GRAY_INC_REG_REG_0;
end architecture MyHDL;
|
-- File: gray_inc_reg.vhd
-- Generated by MyHDL 1.0dev
-- Date: Thu Jun 23 19:06:43 2016
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_10.all;
entity gray_inc_reg is
port (
graycnt: out unsigned(7 downto 0);
enable: in std_logic;
clock: in std_logic;
reset: in std_logic
);
end entity gray_inc_reg;
architecture MyHDL of gray_inc_reg is
signal graycnt_comb: unsigned(7 downto 0);
signal gray_inc_1_bincnt: unsigned(7 downto 0);
begin
GRAY_INC_REG_GRAY_INC_1_INC_1_SEQ: process (clock, reset) is
begin
if (reset = '0') then
gray_inc_1_bincnt <= to_unsigned(0, 8);
elsif rising_edge(clock) then
if bool(enable) then
gray_inc_1_bincnt <= (gray_inc_1_bincnt + 1);
end if;
end if;
end process GRAY_INC_REG_GRAY_INC_1_INC_1_SEQ;
graycnt_comb <= (shift_right(gray_inc_1_bincnt, 1) xor gray_inc_1_bincnt);
GRAY_INC_REG_REG_0: process (clock, reset) is
begin
if (reset = '0') then
graycnt <= to_unsigned(0, 8);
elsif rising_edge(clock) then
graycnt <= graycnt_comb;
end if;
end process GRAY_INC_REG_REG_0;
end architecture MyHDL;
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- cMIPS, a VHDL model of the classical five stage MIPS pipeline.
-- Copyright (C) 2013 Roberto Andre Hexsel
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- These components are replacements for Altera's Megafunctions.
-- They are meant to be used only in simulation; for synthesis, the
-- real Megafunctions must be used instead of these 'fakes'.
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity mf_alt_add_4 is
port(datab : in std_logic_vector (31 downto 0);
result : out std_logic_vector (31 downto 0) );
end mf_alt_add_4;
architecture functional of mf_alt_add_4 is
begin
result <= std_logic_vector( 4 + signed(datab) );
end architecture functional;
-- -----------------------------------------------------------------------
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity mf_alt_adder is
port(dataa : in std_logic_vector (31 downto 0);
datab : in std_logic_vector (31 downto 0);
result : out std_logic_vector (31 downto 0));
end mf_alt_adder;
architecture functional of mf_alt_adder is
begin
result <= std_logic_vector( signed(dataa) + signed(datab) );
end architecture functional;
-- -----------------------------------------------------------------------
-- -----------------------------------------------------------------------
-- add/subtract SIGNED numbers
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity mf_alt_add_sub is
port(add_sub : IN STD_LOGIC; -- add=1, sub=0
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
overflow : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0));
end mf_alt_add_sub;
architecture functional of mf_alt_add_sub is
signal ext_a,ext_b, ext_add_C,ext_sub_C : STD_LOGIC_VECTOR (32 DOWNTO 0);
signal ovfl_add,ovfl_sub : std_logic;
begin
ext_A <= dataa(31) & dataa;
ext_B <= datab(31) & datab;
ext_add_C <= std_logic_vector(signed(ext_A) + signed(ext_B));
ovfl_add <= '1' when (ext_add_C(32) /= ext_add_C(31)) else '0';
ext_sub_C <= std_logic_vector(signed(ext_A)+signed(signed(not ext_B)+1));
ovfl_sub <= '1' when (ext_sub_C(32) /= ext_sub_C(31)) else '0';
result <= ext_add_C(31 downto 0) when add_sub='1' else
ext_sub_C(31 downto 0);
overflow <= ovfl_add when add_sub='1' else
ovfl_sub;
end architecture functional;
-- -----------------------------------------------------------------------
-- -----------------------------------------------------------------------
-- add/subtract UN-SIGNED numbers, does not signal overflow
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity mf_alt_add_sub_u is
port(add_sub : IN STD_LOGIC; -- add=1, sub=0
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0));
end mf_alt_add_sub_u;
architecture functional of mf_alt_add_sub_u is
signal add_C, sub_C : STD_LOGIC_VECTOR (31 DOWNTO 0);
begin
add_C <= std_logic_vector(unsigned(dataa) + unsigned(datab));
sub_C <= std_logic_vector(unsigned(dataa)+unsigned(unsigned(not datab)+1));
result <= add_C(31 downto 0) when add_sub='1' else
sub_C(31 downto 0);
end architecture functional;
-- -----------------------------------------------------------------------
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
entity mf_ram1port is
generic (N_WORDS : integer; ADDRS_BITS : integer);
port (address : in std_logic_vector (ADDRS_BITS-1 downto 0);
clken : in std_logic;
clock : in std_logic;
data : in std_logic_vector (7 downto 0);
wren : in std_logic;
q : out std_logic_vector (7 downto 0));
end mf_ram1port;
architecture rtl of mf_ram1port is
-- Build a 2-D array type for the RAM
subtype word_t is std_logic_vector(7 downto 0);
type memory_t is array(0 to N_WORDS - 1) of word_t;
-- Declare the RAM signal.
signal ram : memory_t;
-- Register to hold the address
signal addr, addr_reg : natural range 0 to N_WORDS - 1;
begin
addr <= to_integer(unsigned(address));
U_addr: process(clock)
begin
if rising_edge(clock) then
-- Register the address for reading
addr_reg <= addr;
end if;
end process U_addr;
U_write: process(clock)
begin
if (clken = '1') and rising_edge(clock) then
if (wren = '1') then
ram(addr) <= data;
end if;
end if;
end process U_write;
q <= ram(addr_reg);
end architecture rtl;
-- -----------------------------------------------------------------------
-- fake ROM megafunction = not used in simulation, only on the FPGA ------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
use work.p_memory.all;
entity alt_mf_rom is port (
address : IN STD_LOGIC_VECTOR ((INST_ADDRS_BITS-1) DOWNTO 0);
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0));
end alt_mf_rom;
architecture fake of alt_mf_rom is
begin -- fake
q <= (others => 'X');
end fake;
-- -----------------------------------------------------------------------
-- PLL for CPU clocks ----------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.p_wires.all;
entity mf_altpll is port (
areset : IN STD_LOGIC;
inclk0 : IN STD_LOGIC; -- 50MHz input
c0 : OUT STD_LOGIC; -- 50MHz, 25% duty cycle, phase 0
c1 : OUT STD_LOGIC; -- 50MHz, 25% duty cycle, phase 120
c2 : OUT STD_LOGIC; -- 50MHz, 25% duty cycle, phase 180
c3 : OUT STD_LOGIC; -- 50MHz, 25% duty cycle, phase 270
c4 : OUT STD_LOGIC); -- 50MHz, 50% duty cycle, phase 0
end mf_altpll;
architecture functional of mf_altpll is
component count4phases is
port(clk, rst : in std_logic;
p0,p1,p2,p3 : out std_logic);
end component count4phases;
component FFD is
port(clk, rst, set, D : in std_logic; Q : out std_logic);
end component FFD;
signal clk4x, phi0,phi1,phi2,phi3, phi2_dlyd : std_logic;
begin
U_clock4x: process -- clk and clk4x MUST start in opposite phases
begin
clk4x <= '0';
wait for CLOCK_PER / 8;
clk4x <= '1';
wait for CLOCK_PER / 8;
end process;
U_4PHASE_CLOCK: count4phases
port map (clk4x, areset, phi0,phi1,phi2,phi3);
-- U_DELAY_PHI2: FFD port map (clk4x, areset, '1', phi2, phi2_dlyd);
c0 <= phi3;
c1 <= phi0;
c2 <= phi1;
c3 <= phi2;
c4 <= inclk0;
end architecture functional;
-- -----------------------------------------------------------------------
-- PLL for I/O devices ---------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.p_wires.all;
entity mf_altpll_io is port (
areset : IN STD_LOGIC;
inclk0 : IN STD_LOGIC; -- 50 MHz
c0 : OUT STD_LOGIC; -- 100MHz, in phase
c1 : OUT STD_LOGIC; -- 200MHz, in phase
c2 : OUT STD_LOGIC); -- 200MHz, opposite phase
end mf_altpll_io;
architecture functional of mf_altpll_io is
signal clk2x, clk4x0, clk4x180 : std_logic;
begin
U_clock2x: process -- in phase with inclk0
begin
clk2x <= '1';
wait for CLOCK_PER / 4;
clk2x <= '0';
wait for CLOCK_PER / 4;
end process;
U_clock4x: process -- clk and clk4x180 MUST start in opposite phases
begin
clk4x180 <= '0';
wait for CLOCK_PER / 8;
clk4x180 <= '1';
wait for CLOCK_PER / 8;
end process;
clk4x0 <= not(clk4x180);
c0 <= clk2x;
c1 <= clk4x0;
c2 <= clk4x180;
end architecture functional;
-- -----------------------------------------------------------------------
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity mf_altclkctrl is port (
inclk : IN STD_LOGIC;
outclk : OUT STD_LOGIC);
end mf_altclkctrl;
architecture functional of mf_altclkctrl is
begin
outclk <= inclk;
end architecture functional;
-- -----------------------------------------------------------------------
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- cMIPS, a VHDL model of the classical five stage MIPS pipeline.
-- Copyright (C) 2013 Roberto Andre Hexsel
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- These components are replacements for Altera's Megafunctions.
-- They are meant to be used only in simulation; for synthesis, the
-- real Megafunctions must be used instead of these 'fakes'.
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity mf_alt_add_4 is
port(datab : in std_logic_vector (31 downto 0);
result : out std_logic_vector (31 downto 0) );
end mf_alt_add_4;
architecture functional of mf_alt_add_4 is
begin
result <= std_logic_vector( 4 + signed(datab) );
end architecture functional;
-- -----------------------------------------------------------------------
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity mf_alt_adder is
port(dataa : in std_logic_vector (31 downto 0);
datab : in std_logic_vector (31 downto 0);
result : out std_logic_vector (31 downto 0));
end mf_alt_adder;
architecture functional of mf_alt_adder is
begin
result <= std_logic_vector( signed(dataa) + signed(datab) );
end architecture functional;
-- -----------------------------------------------------------------------
-- -----------------------------------------------------------------------
-- add/subtract SIGNED numbers
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity mf_alt_add_sub is
port(add_sub : IN STD_LOGIC; -- add=1, sub=0
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
overflow : OUT STD_LOGIC;
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0));
end mf_alt_add_sub;
architecture functional of mf_alt_add_sub is
signal ext_a,ext_b, ext_add_C,ext_sub_C : STD_LOGIC_VECTOR (32 DOWNTO 0);
signal ovfl_add,ovfl_sub : std_logic;
begin
ext_A <= dataa(31) & dataa;
ext_B <= datab(31) & datab;
ext_add_C <= std_logic_vector(signed(ext_A) + signed(ext_B));
ovfl_add <= '1' when (ext_add_C(32) /= ext_add_C(31)) else '0';
ext_sub_C <= std_logic_vector(signed(ext_A)+signed(signed(not ext_B)+1));
ovfl_sub <= '1' when (ext_sub_C(32) /= ext_sub_C(31)) else '0';
result <= ext_add_C(31 downto 0) when add_sub='1' else
ext_sub_C(31 downto 0);
overflow <= ovfl_add when add_sub='1' else
ovfl_sub;
end architecture functional;
-- -----------------------------------------------------------------------
-- -----------------------------------------------------------------------
-- add/subtract UN-SIGNED numbers, does not signal overflow
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity mf_alt_add_sub_u is
port(add_sub : IN STD_LOGIC; -- add=1, sub=0
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0));
end mf_alt_add_sub_u;
architecture functional of mf_alt_add_sub_u is
signal add_C, sub_C : STD_LOGIC_VECTOR (31 DOWNTO 0);
begin
add_C <= std_logic_vector(unsigned(dataa) + unsigned(datab));
sub_C <= std_logic_vector(unsigned(dataa)+unsigned(unsigned(not datab)+1));
result <= add_C(31 downto 0) when add_sub='1' else
sub_C(31 downto 0);
end architecture functional;
-- -----------------------------------------------------------------------
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
entity mf_ram1port is
generic (N_WORDS : integer; ADDRS_BITS : integer);
port (address : in std_logic_vector (ADDRS_BITS-1 downto 0);
clken : in std_logic;
clock : in std_logic;
data : in std_logic_vector (7 downto 0);
wren : in std_logic;
q : out std_logic_vector (7 downto 0));
end mf_ram1port;
architecture rtl of mf_ram1port is
-- Build a 2-D array type for the RAM
subtype word_t is std_logic_vector(7 downto 0);
type memory_t is array(0 to N_WORDS - 1) of word_t;
-- Declare the RAM signal.
signal ram : memory_t;
-- Register to hold the address
signal addr, addr_reg : natural range 0 to N_WORDS - 1;
begin
addr <= to_integer(unsigned(address));
U_addr: process(clock)
begin
if rising_edge(clock) then
-- Register the address for reading
addr_reg <= addr;
end if;
end process U_addr;
U_write: process(clock)
begin
if (clken = '1') and rising_edge(clock) then
if (wren = '1') then
ram(addr) <= data;
end if;
end if;
end process U_write;
q <= ram(addr_reg);
end architecture rtl;
-- -----------------------------------------------------------------------
-- fake ROM megafunction = not used in simulation, only on the FPGA ------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
use work.p_memory.all;
entity alt_mf_rom is port (
address : IN STD_LOGIC_VECTOR ((INST_ADDRS_BITS-1) DOWNTO 0);
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '1';
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0));
end alt_mf_rom;
architecture fake of alt_mf_rom is
begin -- fake
q <= (others => 'X');
end fake;
-- -----------------------------------------------------------------------
-- PLL for CPU clocks ----------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.p_wires.all;
entity mf_altpll is port (
areset : IN STD_LOGIC;
inclk0 : IN STD_LOGIC; -- 50MHz input
c0 : OUT STD_LOGIC; -- 50MHz, 25% duty cycle, phase 0
c1 : OUT STD_LOGIC; -- 50MHz, 25% duty cycle, phase 120
c2 : OUT STD_LOGIC; -- 50MHz, 25% duty cycle, phase 180
c3 : OUT STD_LOGIC; -- 50MHz, 25% duty cycle, phase 270
c4 : OUT STD_LOGIC); -- 50MHz, 50% duty cycle, phase 0
end mf_altpll;
architecture functional of mf_altpll is
component count4phases is
port(clk, rst : in std_logic;
p0,p1,p2,p3 : out std_logic);
end component count4phases;
component FFD is
port(clk, rst, set, D : in std_logic; Q : out std_logic);
end component FFD;
signal clk4x, phi0,phi1,phi2,phi3, phi2_dlyd : std_logic;
begin
U_clock4x: process -- clk and clk4x MUST start in opposite phases
begin
clk4x <= '0';
wait for CLOCK_PER / 8;
clk4x <= '1';
wait for CLOCK_PER / 8;
end process;
U_4PHASE_CLOCK: count4phases
port map (clk4x, areset, phi0,phi1,phi2,phi3);
-- U_DELAY_PHI2: FFD port map (clk4x, areset, '1', phi2, phi2_dlyd);
c0 <= phi3;
c1 <= phi0;
c2 <= phi1;
c3 <= phi2;
c4 <= inclk0;
end architecture functional;
-- -----------------------------------------------------------------------
-- PLL for I/O devices ---------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.p_wires.all;
entity mf_altpll_io is port (
areset : IN STD_LOGIC;
inclk0 : IN STD_LOGIC; -- 50 MHz
c0 : OUT STD_LOGIC; -- 100MHz, in phase
c1 : OUT STD_LOGIC; -- 200MHz, in phase
c2 : OUT STD_LOGIC); -- 200MHz, opposite phase
end mf_altpll_io;
architecture functional of mf_altpll_io is
signal clk2x, clk4x0, clk4x180 : std_logic;
begin
U_clock2x: process -- in phase with inclk0
begin
clk2x <= '1';
wait for CLOCK_PER / 4;
clk2x <= '0';
wait for CLOCK_PER / 4;
end process;
U_clock4x: process -- clk and clk4x180 MUST start in opposite phases
begin
clk4x180 <= '0';
wait for CLOCK_PER / 8;
clk4x180 <= '1';
wait for CLOCK_PER / 8;
end process;
clk4x0 <= not(clk4x180);
c0 <= clk2x;
c1 <= clk4x0;
c2 <= clk4x180;
end architecture functional;
-- -----------------------------------------------------------------------
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity mf_altclkctrl is port (
inclk : IN STD_LOGIC;
outclk : OUT STD_LOGIC);
end mf_altclkctrl;
architecture functional of mf_altclkctrl is
begin
outclk <= inclk;
end architecture functional;
-- -----------------------------------------------------------------------
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file RxTstFIFO2K.vhd when simulating
-- the core, RxTstFIFO2K. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY RxTstFIFO2K IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END RxTstFIFO2K;
ARCHITECTURE RxTstFIFO2K_a OF RxTstFIFO2K IS
-- synthesis translate_off
COMPONENT wrapped_RxTstFIFO2K
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_RxTstFIFO2K USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 0,
c_count_type => 0,
c_data_count_width => 11,
c_default_value => "BlankString",
c_din_width => 8,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "BB",
c_dout_width => 16,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "spartan6",
c_full_flags_rst_val => 1,
c_has_almost_empty => 0,
c_has_almost_full => 0,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 0,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 0,
c_has_rd_rst => 0,
c_has_rst => 1,
c_has_slave_ce => 0,
c_has_srst => 0,
c_has_underflow => 0,
c_has_valid => 0,
c_has_wr_ack => 0,
c_has_wr_data_count => 0,
c_has_wr_rst => 0,
c_implementation_type => 2,
c_implementation_type_axis => 11,
c_implementation_type_rach => 12,
c_implementation_type_rdch => 11,
c_implementation_type_wach => 12,
c_implementation_type_wdch => 11,
c_implementation_type_wrch => 12,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 1,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 0,
c_preload_regs => 1,
c_prim_fifo_type => "2kx9",
c_prog_empty_thresh_assert_val => 4,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 5,
c_prog_empty_type => 0,
c_prog_empty_type_axis => 0,
c_prog_empty_type_rach => 0,
c_prog_empty_type_rdch => 0,
c_prog_empty_type_wach => 0,
c_prog_empty_type_wdch => 0,
c_prog_empty_type_wrch => 0,
c_prog_full_thresh_assert_val => 2047,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 2046,
c_prog_full_type => 0,
c_prog_full_type_axis => 0,
c_prog_full_type_rach => 0,
c_prog_full_type_rdch => 0,
c_prog_full_type_wach => 0,
c_prog_full_type_wdch => 0,
c_prog_full_type_wrch => 0,
c_rach_type => 0,
c_rd_data_count_width => 10,
c_rd_depth => 1024,
c_rd_freq => 1,
c_rd_pntr_width => 10,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_synchronizer_stage => 2,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 1,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 0,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 11,
c_wr_depth => 2048,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 11,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_RxTstFIFO2K
PORT MAP (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty
);
-- synthesis translate_on
END RxTstFIFO2K_a;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file RxTstFIFO2K.vhd when simulating
-- the core, RxTstFIFO2K. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY RxTstFIFO2K IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END RxTstFIFO2K;
ARCHITECTURE RxTstFIFO2K_a OF RxTstFIFO2K IS
-- synthesis translate_off
COMPONENT wrapped_RxTstFIFO2K
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_RxTstFIFO2K USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 0,
c_count_type => 0,
c_data_count_width => 11,
c_default_value => "BlankString",
c_din_width => 8,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "BB",
c_dout_width => 16,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "spartan6",
c_full_flags_rst_val => 1,
c_has_almost_empty => 0,
c_has_almost_full => 0,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 0,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 0,
c_has_rd_rst => 0,
c_has_rst => 1,
c_has_slave_ce => 0,
c_has_srst => 0,
c_has_underflow => 0,
c_has_valid => 0,
c_has_wr_ack => 0,
c_has_wr_data_count => 0,
c_has_wr_rst => 0,
c_implementation_type => 2,
c_implementation_type_axis => 11,
c_implementation_type_rach => 12,
c_implementation_type_rdch => 11,
c_implementation_type_wach => 12,
c_implementation_type_wdch => 11,
c_implementation_type_wrch => 12,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 1,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 0,
c_preload_regs => 1,
c_prim_fifo_type => "2kx9",
c_prog_empty_thresh_assert_val => 4,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 5,
c_prog_empty_type => 0,
c_prog_empty_type_axis => 0,
c_prog_empty_type_rach => 0,
c_prog_empty_type_rdch => 0,
c_prog_empty_type_wach => 0,
c_prog_empty_type_wdch => 0,
c_prog_empty_type_wrch => 0,
c_prog_full_thresh_assert_val => 2047,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 2046,
c_prog_full_type => 0,
c_prog_full_type_axis => 0,
c_prog_full_type_rach => 0,
c_prog_full_type_rdch => 0,
c_prog_full_type_wach => 0,
c_prog_full_type_wdch => 0,
c_prog_full_type_wrch => 0,
c_rach_type => 0,
c_rd_data_count_width => 10,
c_rd_depth => 1024,
c_rd_freq => 1,
c_rd_pntr_width => 10,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_synchronizer_stage => 2,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 1,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 0,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 11,
c_wr_depth => 2048,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 11,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_RxTstFIFO2K
PORT MAP (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty
);
-- synthesis translate_on
END RxTstFIFO2K_a;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file RxTstFIFO2K.vhd when simulating
-- the core, RxTstFIFO2K. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY RxTstFIFO2K IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END RxTstFIFO2K;
ARCHITECTURE RxTstFIFO2K_a OF RxTstFIFO2K IS
-- synthesis translate_off
COMPONENT wrapped_RxTstFIFO2K
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_RxTstFIFO2K USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 0,
c_count_type => 0,
c_data_count_width => 11,
c_default_value => "BlankString",
c_din_width => 8,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "BB",
c_dout_width => 16,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "spartan6",
c_full_flags_rst_val => 1,
c_has_almost_empty => 0,
c_has_almost_full => 0,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 0,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 0,
c_has_rd_rst => 0,
c_has_rst => 1,
c_has_slave_ce => 0,
c_has_srst => 0,
c_has_underflow => 0,
c_has_valid => 0,
c_has_wr_ack => 0,
c_has_wr_data_count => 0,
c_has_wr_rst => 0,
c_implementation_type => 2,
c_implementation_type_axis => 11,
c_implementation_type_rach => 12,
c_implementation_type_rdch => 11,
c_implementation_type_wach => 12,
c_implementation_type_wdch => 11,
c_implementation_type_wrch => 12,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 1,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 0,
c_preload_regs => 1,
c_prim_fifo_type => "2kx9",
c_prog_empty_thresh_assert_val => 4,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 5,
c_prog_empty_type => 0,
c_prog_empty_type_axis => 0,
c_prog_empty_type_rach => 0,
c_prog_empty_type_rdch => 0,
c_prog_empty_type_wach => 0,
c_prog_empty_type_wdch => 0,
c_prog_empty_type_wrch => 0,
c_prog_full_thresh_assert_val => 2047,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 2046,
c_prog_full_type => 0,
c_prog_full_type_axis => 0,
c_prog_full_type_rach => 0,
c_prog_full_type_rdch => 0,
c_prog_full_type_wach => 0,
c_prog_full_type_wdch => 0,
c_prog_full_type_wrch => 0,
c_rach_type => 0,
c_rd_data_count_width => 10,
c_rd_depth => 1024,
c_rd_freq => 1,
c_rd_pntr_width => 10,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_synchronizer_stage => 2,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 1,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 0,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 11,
c_wr_depth => 2048,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 11,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_RxTstFIFO2K
PORT MAP (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty
);
-- synthesis translate_on
END RxTstFIFO2K_a;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file RxTstFIFO2K.vhd when simulating
-- the core, RxTstFIFO2K. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY RxTstFIFO2K IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END RxTstFIFO2K;
ARCHITECTURE RxTstFIFO2K_a OF RxTstFIFO2K IS
-- synthesis translate_off
COMPONENT wrapped_RxTstFIFO2K
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_RxTstFIFO2K USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 0,
c_count_type => 0,
c_data_count_width => 11,
c_default_value => "BlankString",
c_din_width => 8,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "BB",
c_dout_width => 16,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "spartan6",
c_full_flags_rst_val => 1,
c_has_almost_empty => 0,
c_has_almost_full => 0,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 0,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 0,
c_has_rd_rst => 0,
c_has_rst => 1,
c_has_slave_ce => 0,
c_has_srst => 0,
c_has_underflow => 0,
c_has_valid => 0,
c_has_wr_ack => 0,
c_has_wr_data_count => 0,
c_has_wr_rst => 0,
c_implementation_type => 2,
c_implementation_type_axis => 11,
c_implementation_type_rach => 12,
c_implementation_type_rdch => 11,
c_implementation_type_wach => 12,
c_implementation_type_wdch => 11,
c_implementation_type_wrch => 12,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 1,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 0,
c_preload_regs => 1,
c_prim_fifo_type => "2kx9",
c_prog_empty_thresh_assert_val => 4,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 5,
c_prog_empty_type => 0,
c_prog_empty_type_axis => 0,
c_prog_empty_type_rach => 0,
c_prog_empty_type_rdch => 0,
c_prog_empty_type_wach => 0,
c_prog_empty_type_wdch => 0,
c_prog_empty_type_wrch => 0,
c_prog_full_thresh_assert_val => 2047,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 2046,
c_prog_full_type => 0,
c_prog_full_type_axis => 0,
c_prog_full_type_rach => 0,
c_prog_full_type_rdch => 0,
c_prog_full_type_wach => 0,
c_prog_full_type_wdch => 0,
c_prog_full_type_wrch => 0,
c_rach_type => 0,
c_rd_data_count_width => 10,
c_rd_depth => 1024,
c_rd_freq => 1,
c_rd_pntr_width => 10,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_synchronizer_stage => 2,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 1,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 0,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 11,
c_wr_depth => 2048,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 11,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_RxTstFIFO2K
PORT MAP (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty
);
-- synthesis translate_on
END RxTstFIFO2K_a;
|
------------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2006 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.net.all;
use gaisler.jtag.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
reset : in std_ulogic;
reset_o1 : out std_ulogic;
reset_o2 : out std_ulogic;
clk_in : in std_ulogic;
clk_vga : in std_ulogic;
errorn : out std_ulogic;
-- PROM interface
address : out std_logic_vector(23 downto 0);
data : inout std_logic_vector(7 downto 0);
romsn : out std_ulogic;
oen : out std_ulogic;
writen : out std_ulogic;
-- pragma translate_off
iosn : out std_ulogic;
testdata : inout std_logic_vector(23 downto 0);
-- pragma translate_on
-- DDR2 memory
ddr_clk : out std_logic_vector(1 downto 0);
ddr_clkb : out std_logic_vector(1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic;
ddr_csb : out std_logic;
ddr_we : out std_ulogic; -- write enable
ddr_ras : out std_ulogic; -- ras
ddr_cas : out std_ulogic; -- cas
ddr_dm : out std_logic_vector(3 downto 0); -- dm
ddr_dqs : inout std_logic_vector(3 downto 0); -- dqs
ddr_dqsn : inout std_logic_vector(3 downto 0); -- dqsn
ddr_ad : out std_logic_vector(12 downto 0); -- address
ddr_ba : out std_logic_vector(1 downto 0); -- bank address
ddr_dq : inout std_logic_vector(31 downto 0); -- data
ddr_odt : out std_logic;
-- Debug support unit
dsubre : in std_ulogic; -- Debug Unit break (connect to button)
-- AHB Uart
dsurx : in std_ulogic;
dsutx : out std_ulogic;
-- Ethernet signals
etx_clk : in std_ulogic;
erx_clk : in std_ulogic;
erxd : in std_logic_vector(3 downto 0);
erx_dv : in std_ulogic;
erx_er : in std_ulogic;
erx_col : in std_ulogic;
erx_crs : in std_ulogic;
etxd : out std_logic_vector(3 downto 0);
etx_en : out std_ulogic;
etx_er : out std_ulogic;
emdc : out std_ulogic;
emdio : inout std_logic;
-- SVGA
vid_hsync : out std_logic;
vid_vsync : out std_logic;
vid_r : out std_logic_vector(3 downto 0);
vid_g : out std_logic_vector(3 downto 0);
vid_b : out std_logic_vector(3 downto 0);
-- SPI flash
spi_sel_n : inout std_ulogic;
spi_clk : out std_ulogic;
spi_mosi : out std_ulogic;
-- Output signals to LEDs
led : out std_logic_vector(2 downto 0)
);
end;
architecture rtl of leon3mp is
signal vcc : std_logic;
signal gnd : std_logic;
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal gpti : gptimer_in_type;
signal vgao : apbvga_out_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
signal spmi : spimctrl_in_type;
signal spmo : spimctrl_out_type;
signal lclk : std_ulogic;
signal lclk_vga : std_ulogic;
signal clkm, rstn, clkml : std_ulogic;
signal tck, tms, tdi, tdo : std_ulogic;
signal rstraw : std_logic;
signal lock : std_logic;
-- RS232 APB Uart
signal rxd1 : std_logic;
signal txd1 : std_logic;
-- Used for connecting input/output signals to the DDR2 controller
signal core_ddr_clk : std_logic_vector(2 downto 0);
signal core_ddr_clkb : std_logic_vector(2 downto 0);
signal core_ddr_cke : std_logic_vector(1 downto 0);
signal core_ddr_csb : std_logic_vector(1 downto 0);
signal core_ddr_ad : std_logic_vector(13 downto 0);
signal core_ddr_odt : std_logic_vector(1 downto 0);
attribute keep : boolean;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of lock : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_keep of clkm : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute syn_keep of lclk_vga : signal is true;
attribute syn_preserve of lclk_vga : signal is true;
attribute keep of lock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
constant BOARD_FREQ : integer := 125000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1';
gnd <= '0';
cgi.pllctrl <= "00";
cgi.pllrst <= rstraw;
-- Glitch free reset that can be used for the Eth Phy and flash memory
reset_o1 <= rstn;
reset_o2 <= rstn;
rst0 : rstgen generic map (acthigh => 1)
port map (reset, clkm, lock, rstn, rstraw);
clk_pad : clkpad generic map (tech => padtech) port map (clk_in, lclk);
-- clock generator
clkgen0 : clkgen
generic map (fabtech, CFG_CLKMUL, CFG_CLKDIV, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd, clkm, open, open, open, open, cgi, cgo, open, open, open);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => 1,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE,
nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
-- LEON3 processor
leon3gen : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR,
CFG_NCPU-1, CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso, irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
error_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
-- LEON3 Debug Support Unit
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsui.enable <= '1';
led(2) <= dsuo.active;
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
-- Debug UART
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart
generic map (hindex => CFG_NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(CFG_NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (dsurx, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (dsutx, duo.txd);
led(0) <= not dui.rxd;
led(1) <= not duo.txd;
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(4) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd);
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mg2 : if CFG_MCTRL_LEON2 = 1 generate -- LEON2 memory controller
sr1 : mctrl generic map (hindex => 5, pindex => 0, paddr => 0,
ram8 => CFG_MCTRL_RAM8BIT, ram16 => CFG_MCTRL_RAM16BIT, rammask => 0)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(5), apbi, apbo(0), wpo, open);
end generate;
memi.brdyn <= '1';
memi.bexcn <= '1';
memi.writen <= '1';
memi.wrn <= "1111";
memi.bwidth <= "00";
mg0 : if (CFG_MCTRL_LEON2 = 0) generate
apbo(0) <= apb_none;
ahbso(5) <= ahbs_none;
roms_pad : outpad generic map (tech => padtech)
port map (romsn, vcc);
memo.bdrive(0) <= '1';
end generate;
mgpads : if (CFG_MCTRL_LEON2 /= 0) generate
addr_pad : outpadv generic map (tech => padtech, width => 24)
port map (address, memo.address(23 downto 0));
roms_pad : outpad generic map (tech => padtech)
port map (romsn, memo.romsn(0));
oen_pad : outpad generic map (tech => padtech)
port map (oen, memo.oen);
wri_pad : outpad generic map (tech => padtech)
port map (writen, memo.writen);
-- pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
tbdr : iopadv generic map (tech => padtech, width => 24)
port map (testdata(23 downto 0), memo.data(23 downto 0),
memo.bdrive(1), memi.data(23 downto 0));
-- pragma translate_on
end generate;
bdr : iopadv generic map (tech => padtech, width => 8)
port map (data(7 downto 0), memo.data(31 downto 24),
memo.bdrive(0), memi.data(31 downto 24));
----------------------------------------------------------------------
--- DDR2 memory controller ------------------------------------------
----------------------------------------------------------------------
ddr2sp0 : if (CFG_DDR2SP /= 0) generate
ddrc0 : ddr2spa generic map ( fabtech => spartan3, memtech => memtech,
hindex => 4, haddr => 16#400#, hmask => 16#F00#, ioaddr => 1,
pwron => CFG_DDR2SP_INIT, MHz => BOARD_FREQ/1000, clkmul => 2, clkdiv => 2,
TRFC => CFG_DDR2SP_TRFC,
-- readdly must be 0 for simulation, but 1 for hardware
--pragma translate_off
readdly => 0,
--pragma translate_on
ahbfreq => CPU_FREQ/1000, col => CFG_DDR2SP_COL, Mbyte => CFG_DDR2SP_SIZE,
ddrbits => CFG_DDR2SP_DATAWIDTH, odten => 0)
port map ( cgo.clklock, rstn, lclk, clkm, vcc, lock, clkml, clkml, ahbsi, ahbso(4),
core_ddr_clk, core_ddr_clkb, ddr_clk_fb_out, ddr_clk_fb, core_ddr_cke,
core_ddr_csb, ddr_we, ddr_ras, ddr_cas, ddr_dm, ddr_dqs, ddr_dqsn,
core_ddr_ad, ddr_ba, ddr_dq, core_ddr_odt);
ddr_clk(1 downto 0) <= core_ddr_clk(1 downto 0);
ddr_clkb(1 downto 0) <= core_ddr_clkb(1 downto 0);
ddr_cke <= core_ddr_cke(0);
ddr_csb <= core_ddr_csb(0);
ddr_ad <= core_ddr_ad(12 downto 0);
ddr_odt <= core_ddr_odt(0);
end generate;
noddr : if (CFG_DDR2SP = 0) generate lock <= '1'; end generate;
----------------------------------------------------------------------
--- SPI Memory Controller--------------------------------------------
----------------------------------------------------------------------
spimc: if CFG_SPICTRL_ENABLE = 0 and CFG_SPIMCTRL = 1 generate
spimctrl0 : spimctrl -- SPI Memory Controller
generic map (hindex => 7, hirq => 11, faddr => 16#e00#, fmask => 16#ff8#,
ioaddr => 16#002#, iomask => 16#fff#,
spliten => CFG_SPLIT, oepol => 0,
sdcard => CFG_SPIMCTRL_SDCARD,
readcmd => CFG_SPIMCTRL_READCMD,
dummybyte => CFG_SPIMCTRL_DUMMYBYTE,
dualoutput => CFG_SPIMCTRL_DUALOUTPUT,
scaler => CFG_SPIMCTRL_SCALER,
altscaler => CFG_SPIMCTRL_ASCALER,
pwrupcnt => CFG_SPIMCTRL_PWRUPCNT)
port map (rstn, clkm, ahbsi, ahbso(7), spmi, spmo);
-- MISO is shared with Flash data 0
spmi.miso <= memi.data(24);
mosi_pad : outpad generic map (tech => padtech)
port map (spi_mosi, spmo.mosi);
sck_pad : outpad generic map (tech => padtech)
port map (spi_clk, spmo.sck);
slvsel0_pad : odpad generic map (tech => padtech)
port map (spi_sel_n, spmo.csn);
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
-- APB Bridge
apb0 : apbctrl
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
-- Interrupt controller
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
-- Time Unit
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW,
ntimers => CFG_GPT_NTIM, nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop;
gpti.extclk <= '0';
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
-- GPIO Unit
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate
grgpio0: grgpio
generic map(pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 12)
port map(rstn, clkm, apbi, apbo(11), gpioi, gpioo);
end generate;
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart, fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1;
u1i.ctsn <= '0';
u1i.extclk <= '0';
txd1 <= u1o.txd;
serrx_pad : inpad generic map (tech => padtech) port map (dsurx, rxd1);
sertx_pad : outpad generic map (tech => padtech) port map (dsutx, txd1);
led(0) <= not rxd1;
led(1) <= not txd1;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
-- There is no PS/2 port
apbo(5) <= apb_none;
spic: if CFG_SPICTRL_ENABLE = 1 generate -- SPI controller
spi1 : spictrl
generic map (pindex => 7, paddr => 7, pmask => 16#fff#, pirq => 11,
fdepth => CFG_SPICTRL_FIFO, slvselen => CFG_SPICTRL_SLVREG,
slvselsz => CFG_SPICTRL_SLVS, odmode => 0, netlist => 0,
syncram => CFG_SPICTRL_SYNCRAM, ft => CFG_SPICTRL_FT)
port map (rstn, clkm, apbi, apbo(7), spii, spio, slvsel);
spii.spisel <= '1'; -- Master only
-- MISO is shared with Flash data 0
spii.miso <= memi.data(24);
mosi_pad : outpad generic map (tech => padtech)
port map (spi_mosi, spio.mosi);
sck_pad : outpad generic map (tech => padtech)
port map (spi_clk, spio.sck);
slvsel_pad : odpad generic map (tech => padtech)
port map (spi_sel_n, slvsel(0));
end generate spic;
nospi: if CFG_SPICTRL_ENABLE = 0 and CFG_SPIMCTRL = 0 generate
apbo(7) <= apb_none;
mosi_pad : outpad generic map (tech => padtech)
port map (spi_mosi, gnd);
sck_pad : outpad generic map (tech => padtech)
port map (spi_clk, gnd);
slvsel_pad : odpad generic map (tech => padtech)
port map (spi_sel_n, vcc);
end generate;
-----------------------------------------------------------------------
--- SVGA -------------------------------------------------------------
-----------------------------------------------------------------------
svga : if CFG_SVGA_ENABLE /= 0 generate
clk_vga_pad : clkpad generic map (tech => padtech) port map (clk_vga, lclk_vga);
svga0 : svgactrl
generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
clk0 => 40000,clk1 => 0, clk2 => 0, burstlen => 5)
port map(rstn, clkm, lclk_vga, apbi, apbo(6), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), open);
vert_sync_pad : outpad generic map (tech => padtech)
port map (vid_vsync, vgao.vsync);
horiz_sync_pad : outpad generic map (tech => padtech)
port map (vid_hsync, vgao.hsync);
video_out_r_pad : outpadv generic map (tech => padtech, width => 4)
port map (vid_r, vgao.video_out_r(7 downto 4));
video_out_g_pad : outpadv generic map (tech => padtech, width => 4)
port map (vid_g, vgao.video_out_g(7 downto 4));
video_out_b_pad : outpadv generic map (tech => padtech, width => 4)
port map (vid_b, vgao.video_out_b(7 downto 4));
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth0 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm
generic map(hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 15, paddr => 15, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G)
port map(rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
apbi => apbi, apbo => apbo(15), ethi => ethi, etho => etho);
end generate;
ethpads : if (CFG_GRETH = 1) generate -- eth pads
emdio_pad : iopad generic map (tech => padtech)
port map (emdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (etx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (erx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (erxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (erx_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (erx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (erx_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (erx_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (etxd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (etx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (etx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (emdc, etho.mdc);
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram
generic map (hindex => 3, haddr => CFG_AHBRADDR, tech => CFG_MEMTECH,
kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(3));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(3) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH+CFG_SVGA_ENABLE+1) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Demonstration design for Xilinx Spartan3A DSP 1800A board",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end rtl;
|
------------------------------------------------------------------
-- _____
-- / \
-- /____ \____
-- / \===\ \==/
-- /___\===\___\/ AVNET
-- \======/
-- \====/
-----------------------------------------------------------------
--
-- This design is the property of Avnet. Publication of this
-- design is not authorized without written consent from Avnet.
--
-- Please direct any questions to: [email protected]
--
-- Disclaimer:
-- Avnet, Inc. makes no warranty for the use of this code or design.
-- This code is provided "As Is". Avnet, Inc assumes no responsibility for
-- any errors, which may appear in this code, nor does it make a commitment
-- to update the information contained herein. Avnet, Inc specifically
-- disclaims any implied warranties of fitness for a particular purpose.
-- Copyright(c) 2011 Avnet, Inc.
-- All rights reserved.
--
------------------------------------------------------------------
--
-- Create Date: Sep 15, 2011
-- Design Name: FMC-IMAGEON
-- Module Name: fmc_imageon_vita_core.vhd
-- Project Name: FMC-IMAGEON
-- Target Devices: Virtex-6
-- Kintex-7, Zynq
-- Avnet Boards: FMC-IMAGEON
--
-- Tool versions: ISE 14.1
--
-- Description: FMC-IMAGEON VITA receiver - Core Logic.
--
-- Dependencies:
--
-- Revision: Sep 15, 2011: 1.00 Initial version:
-- - VITA SPI controller
-- Sep 22, 2011: 1.01 Added:
-- - ISERDES interface
-- Sep 28, 2011: 1.02 Added:
-- - sync channel decoder
-- - crc checker
-- - data remapper
-- Oct 20, 2011: 1.03 Modify:
-- - iserdes (use BUFR)
-- Oct 21, 2011: 1.04 Added:
-- - fpn prnu correction
-- Nov 03, 2011: 1.05 Added:
-- - trigger generator
-- Dec 19, 2011: 1.06 Modified:
-- - port to Kintex-7
-- Jan 12, 2012: 1.07 Added:
-- - new fsync output port
-- Modify:
-- - syncgen
-- Feb 06, 2012: 1.08 Modify:
-- - triggergenerator
-- (new version with debounce logic)
-- - new C_XSVI_DIRECT_OUTPUT option
-- Feb 22, 2012: 1.09 Modified
-- - port to Zynq
-- - new C_XSVI_USE_SYNCGEN option
-- May 28, 2012: 1.11 Added:
-- - host_triggen_cnt_update
-- (for simultaneous update of high/low values)
-- - host_triggen_gen_polarity
-- Jun 01, 2012: 1.12 Modify:
-- - Move syncgen after demux_fifo
-- - Increase size of demux_fifo
-- (to tolerate jitter in video timing from sensor)
-- - Add programmable delay on framestart for syncgen
-- Jul 31, 2012: 1.13 Modify:
-- - define clk200, clk, clk4x with SIGIS = CLK
-- - define reset with SIGIS = RST
-- - port to Spartan-6
--
------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity fmc_imageon_vita_core is
Generic
(
C_XSVI_DATA_WIDTH : integer := 10;
C_XSVI_DIRECT_OUTPUT : integer := 0;
C_XSVI_USE_SYNCGEN : integer := 1;
C_FAMILY : string := "virtex6"
);
Port
(
clk200 : in std_logic;
clk : in std_logic;
clk4x : in std_logic;
reset : in std_logic;
oe : in std_logic;
-- HOST Interface - VITA
host_vita_reset : in std_logic;
-- HOST Interface - SPI
host_spi_clk : in std_logic;
host_spi_reset : in std_logic;
host_spi_timing : in std_logic_vector(15 downto 0);
host_spi_status_busy : out std_logic;
host_spi_status_error : out std_logic;
host_spi_txfifo_clk : in std_logic;
host_spi_txfifo_wen : in std_logic;
host_spi_txfifo_din : in std_logic_vector(31 downto 0);
host_spi_txfifo_full : out std_logic;
host_spi_rxfifo_clk : in std_logic;
host_spi_rxfifo_ren : in std_logic;
host_spi_rxfifo_dout : out std_logic_vector(31 downto 0);
host_spi_rxfifo_empty : out std_logic;
-- HOST Interface - ISERDES
host_iserdes_reset : in std_logic;
host_iserdes_auto_align : in std_logic;
host_iserdes_align_start : in std_logic;
host_iserdes_fifo_enable : in std_logic;
host_iserdes_manual_tap : in std_logic_vector(9 downto 0);
host_iserdes_training : in std_logic_vector(9 downto 0);
host_iserdes_clk_ready : out std_logic;
host_iserdes_clk_status : out std_logic_vector(15 downto 0);
host_iserdes_align_busy : out std_logic;
host_iserdes_aligned : out std_logic;
-- HOST Interface - Sync Channel Decoder
host_decoder_reset : in std_logic;
host_decoder_enable : in std_logic;
host_decoder_startoddeven : in std_logic_vector(31 downto 0);
host_decoder_code_ls : in std_logic_vector(9 downto 0);
host_decoder_code_le : in std_logic_vector(9 downto 0);
host_decoder_code_fs : in std_logic_vector(9 downto 0);
host_decoder_code_fe : in std_logic_vector(9 downto 0);
host_decoder_code_bl : in std_logic_vector(9 downto 0);
host_decoder_code_img : in std_logic_vector(9 downto 0);
host_decoder_code_tr : in std_logic_vector(9 downto 0);
host_decoder_code_crc : in std_logic_vector(9 downto 0);
host_decoder_frame_start : out std_logic;
host_decoder_cnt_black_lines : out std_logic_vector(31 downto 0);
host_decoder_cnt_image_lines : out std_logic_vector(31 downto 0);
host_decoder_cnt_black_pixels : out std_logic_vector(31 downto 0);
host_decoder_cnt_image_pixels : out std_logic_vector(31 downto 0);
host_decoder_cnt_frames : out std_logic_vector(31 downto 0);
host_decoder_cnt_windows : out std_logic_vector(31 downto 0);
host_decoder_cnt_clocks : out std_logic_vector(31 downto 0);
host_decoder_cnt_start_lines : out std_logic_vector(31 downto 0);
host_decoder_cnt_end_lines : out std_logic_vector(31 downto 0);
host_decoder_cnt_monitor0high : out std_logic_vector(31 downto 0);
host_decoder_cnt_monitor0low : out std_logic_vector(31 downto 0);
host_decoder_cnt_monitor1high : out std_logic_vector(31 downto 0);
host_decoder_cnt_monitor1low : out std_logic_vector(31 downto 0);
-- HOST Interface - CRC Checker
host_crc_reset : in std_logic;
host_crc_initvalue : in std_logic;
host_crc_status : out std_logic_vector(31 downto 0);
-- HOST Interface - Data Channel Remapper
host_remapper_write_cfg : in std_logic_vector(2 downto 0);
host_remapper_mode : in std_logic_vector(2 downto 0);
-- HOST Interface - Trigger Generator
host_triggen_enable : in std_logic_vector(2 downto 0);
host_triggen_sync2readout : in std_logic_vector(2 downto 0);
host_triggen_readouttrigger : in std_logic;
host_triggen_default_freq : in std_logic_vector(31 downto 0);
host_triggen_cnt_trigger0high : in std_logic_vector(31 downto 0);
host_triggen_cnt_trigger0low : in std_logic_vector(31 downto 0);
host_triggen_cnt_trigger1high : in std_logic_vector(31 downto 0);
host_triggen_cnt_trigger1low : in std_logic_vector(31 downto 0);
host_triggen_cnt_trigger2high : in std_logic_vector(31 downto 0);
host_triggen_cnt_trigger2low : in std_logic_vector(31 downto 0);
host_triggen_ext_debounce : in std_logic_vector(31 downto 0);
host_triggen_ext_polarity : in std_logic;
host_triggen_gen_polarity : in std_logic_vector(2 downto 0);
-- HOST Interface - FPN/PRNU Correction
host_fpn_prnu_values : in std_logic_vector((16*16)-1 downto 0);
-- HOST Interface - Sync Generator
host_syncgen_delay : in std_logic_vector(15 downto 0);
host_syncgen_hactive : in std_logic_vector(15 downto 0);
host_syncgen_hfporch : in std_logic_vector(15 downto 0);
host_syncgen_hsync : in std_logic_vector(15 downto 0);
host_syncgen_hbporch : in std_logic_vector(15 downto 0);
host_syncgen_vactive : in std_logic_vector(15 downto 0);
host_syncgen_vfporch : in std_logic_vector(15 downto 0);
host_syncgen_vsync : in std_logic_vector(15 downto 0);
host_syncgen_vbporch : in std_logic_vector(15 downto 0);
-- I/O pins
io_vita_clk_pll : out std_logic;
io_vita_reset_n : out std_logic;
io_vita_trigger : out std_logic_vector(2 downto 0);
io_vita_monitor : in std_logic_vector(1 downto 0);
io_vita_spi_sclk : out std_logic;
io_vita_spi_ssel_n : out std_logic;
io_vita_spi_mosi : out std_logic;
io_vita_spi_miso : in std_logic;
io_vita_clk_out_p : in std_logic;
io_vita_clk_out_n : in std_logic;
io_vita_sync_p : in std_logic;
io_vita_sync_n : in std_logic;
io_vita_data_p : in std_logic_vector(7 downto 0);
io_vita_data_n : in std_logic_vector(7 downto 0);
-- Trigger Port
trigger1 : in std_logic;
-- Frame Sync Port
fsync : out std_logic;
-- XSVI Port
xsvi_vsync_o : out std_logic;
xsvi_hsync_o : out std_logic;
xsvi_vblank_o : out std_logic;
xsvi_hblank_o : out std_logic;
xsvi_active_video_o : out std_logic;
xsvi_video_data_o : out std_logic_vector((C_XSVI_DATA_WIDTH-1) downto 0);
-- Debug Ports
debug_spi_o : out std_logic_vector( 95 downto 0);
debug_iserdes_o : out std_logic_vector(229 downto 0);
debug_decoder_o : out std_logic_vector(186 downto 0);
debug_crc_o : out std_logic_vector( 87 downto 0);
debug_triggen_o : out std_logic_vector( 9 downto 0);
debug_video_o : out std_logic_vector( 31 downto 0)
);
end fmc_imageon_vita_core;
architecture rtl of fmc_imageon_vita_core is
signal host_iserdes_reset_n : std_logic;
--
-- VITA SPI Controller
--
component spi_top is
generic
(
gSIMULATION : integer := 0;
gSysClkSpeed : integer := 50;
--LowLevel SPI settings
gSpiClkSpeed : integer := 1000; -- SPI Clock Speed in kHz
gUseFixedSpeed : integer := 1; -- 0: use timing input
-- 1: use SysClkSpeed/SpiClkSpeed generics
gDATA_WIDTH : integer := 26;
gTxMSB_FIRST : integer := 1;
gRxMSB_FIRST : integer := 1;
gSCLK_POLARITY : std_logic := '0'; --'0': idle low, '1': idle high
gCS_POLARITY : std_logic := '1'; --'0': active high, '1': active low
gEN_POLARITY : std_logic := '0'; --'0': normal, '1': invert
gMOSI_POLARITY : std_logic := '0'; --'0': normal, '1': invert
gMISO_POLARITY : std_logic := '0'; --'0': normal, '1': invert
gMISO_SAMPLE : std_logic := '1'; --'0': sample on rising edge
--'1': sample on falling edge
gMOSI_CLK : std_logic := '0'; --'0': clock out on rising edge
--'1': clock out on falling edge
--Seq SPI settings
gSyncTriggerWidth : integer; -- min 1, max 15
gRWbitposition : integer := 0 --seen from LSB
);
Port
(
CLOCK : in std_logic;
RESET : in std_logic;
TIMING : in std_logic_vector(15 downto 0);
BUSY : out std_logic;
--synchro signals
synctriggers : in std_logic_vector(gSyncTriggerWidth-1 downto 0);
sync1_select : in std_logic_vector(3 downto 0);
sync2_select : in std_logic_vector(3 downto 0);
-- Fifo signals
-- read fifo interface (SPI write path/SPI read address path)
APP_RDFIFO_CLK : out std_logic;
APP_RDFIFO_EN : out std_logic;
APP_RDFIFO_DATA_OUT : in std_logic_vector( 31 downto 0);
APP_RDFIFO_EMPTY : in std_logic;
-- write fifo interface (SPI read data path)
APP_WRFIFO_CLK : out std_logic;
APP_WRFIFO_EN : out std_logic;
APP_WRFIFO_DATA_IN : out std_logic_vector( 31 downto 0);
APP_WRFIFO_FULL : in std_logic;
ERROR : out std_logic;
--
-- SPI
--
SCLK : out std_logic;
MOSI : out std_logic;
MISO : in std_logic;
CS : out std_logic;
EN : out std_logic
);
end component spi_top;
signal vita_spi_status_busy : std_logic;
signal vita_spi_status_error : std_logic;
--
-- VITA SPI FIFOs
--
component afifo_32 is
generic
(
C_FAMILY : string := "virtex6"
);
port
(
rst : IN std_logic;
wr_clk : IN std_logic;
wr_en : IN std_logic;
din : IN std_logic_VECTOR(31 downto 0);
rd_clk : IN std_logic;
rd_en : IN std_logic;
dout : OUT std_logic_VECTOR(31 downto 0);
empty : OUT std_logic;
full : OUT std_logic
);
end component afifo_32;
signal vita_spi_txfifo_clk : std_logic;
signal vita_spi_txfifo_ren : std_logic;
signal vita_spi_txfifo_dout : std_logic_vector(31 downto 0);
signal vita_spi_txfifo_empty : std_logic;
signal vita_spi_rxfifo_clk : std_logic;
signal vita_spi_rxfifo_wen : std_logic;
signal vita_spi_rxfifo_din : std_logic_vector(31 downto 0);
signal vita_spi_rxfifo_full : std_logic;
--
-- VITA Serial LVDS Receiver
--
constant gSIMULATION : integer := 0;
constant NROF_CONN : integer := 5;
constant NROF_CONTR_CONN : integer := 5;
constant NROF_CLOCKCOMP : integer := 1;
constant NROF_WINDOWS : integer := 8;
constant DATAWIDTH : integer := 10;
constant CLKSPEED : integer := 62;
constant INVBOOL : boolean := FALSE;
constant NROF_DELAYCTRLS : integer := 1;
-- usedatapathfunc(gEngineering, gLVDS_OUT) ?
-- APP_CFG_REG.Sysmode(5) ? = ??
-- APP_CFG_REG.Sysmode(6) ? = ??
-- APP_CFG_REG.Sysmode(7) ? = INITVALUE = '0'
component iserdes_interface is
generic (
SIMULATION : integer := 0;
NROF_CONN : integer := 4; --16 bits
NROF_CONTR_CONN : integer := 4;
NROF_CLOCKCOMP : integer := 1;
DATAWIDTH : integer := 10; -- can be 4, 6, 8 or 10 for DDR, can be 2, 3, 4, 5, 6, 7, or 8 for SDR.
RETRY_MAX : integer := 32767; --16 bits, global
STABLE_COUNT : integer := 16;
TAP_COUNT_MAX : integer := 64;
DATA_RATE : string := "DDR"; -- DDR/SDR
DIFF_TERM : boolean := TRUE;
USE_FIFO : boolean := FALSE;
USE_BLOCKRAMFIFO : boolean := TRUE;
INVERT_OUTPUT : boolean := FALSE;
INVERSE_BITORDER : boolean := FALSE;
CLKSPEED : integer := 50; -- APPCLK speed in MHz. Everything is generated from Appclk to be as sync as possible
--DATAWIDTH, DATARATE, and clockspeed are used to calculate high speed clk speed.
--SIM_DEVICE : string := "VIRTEX5"; --VIRTEX4/VIRTEX5, for BUFR
C_FAMILY : string := "virtex6";
NROF_DELAYCTRLS : integer := 1;
IDELAYCLK_MULT : integer := 4;
IDELAYCLK_DIV : integer := 1;
GENIDELAYCLK : boolean := FALSE; -- generate own idelayrefclk based on mult and div parameters or use external clk
-- ext clk can come from common part and thus always be in spec regardless of clkspeed
USE_OUTPLL : boolean := TRUE; --use output/multiplieng PLL instead of DCM
USE_INPLL : boolean := TRUE; --use input/dividing PLL instead of DCM
USE_HS_EXT_CLK_IN : boolean := FALSE; -- use external clock high speed clock in
-- YES -> use as CLK source, either via BUFG or BUFIO/BUFR,
-- -> when USE_HS_REGIONAL_CLK = YES
-- use BUFIO (only IOblock can be clocked)
-- -> when USE_HS_REGIONAL_CLK = NO
-- use BUFG
--
-- NO -> when use USE_LS_EXT_CLK_IN = YES
-- not supported
-- when use USE_LS_EXT_CLK_IN = NO
-- appclk combined with DCM as CLK source
-- use BUFG as CLK source
USE_LS_EXT_CLK_IN : boolean := FALSE; -- use external clock low speed clock in
-- YES -> use as CLKDIV source, either via BUFG or BUFIO/BUFR,
-- -> when USE_LS_REGIONAL_CLK = YES
-- use BUFR
-- -> when USE_LS_REGIONAL_CLK = NO
-- use BUFG
--
--
-- NO -> when USE_HS_EXT_CLK_IN = YES
-- -> when USE_HS_REGIONAL_CLK =YES and BUFR can divide
-- use BUFIO/BUFR to divide HS
-- -> when USE_HS_REGIONAL_CLK =YES and BUFR can not divide
-- use BUFIO/BUFR + DCM to divide HS
-- -> when USE_HS_EXT_CLK_IN = NO
-- use DCM (same as HS_EXT_CLK_IN) as clk source, sync with appclk
--
--
USE_DIFF_HS_CLK_IN : boolean := FALSE; -- differential mode, automatically instantiates the correct buffer
USE_DIFF_LS_CLK_IN : boolean := FALSE; -- differential mode, automatically instantiates the correct buffer
USE_HS_REGIONAL_CLK : boolean := FALSE; -- only used when USE_HS_EXT_CLK_IN = yes
USE_LS_REGIONAL_CLK : boolean := FALSE; -- only used when USE_LS_EXT_CLK_IN = yes
USE_HS_EXT_CLK_OUT : boolean := FALSE; -- use external clock high speed clock out
USE_LS_EXT_CLK_OUT : boolean := FALSE; -- use external clock low speed clock out
USE_DIFF_HS_CLK_OUT : boolean := FALSE; -- differential mode, automatically instantiates the correct buffer
USE_DIFF_LS_CLK_OUT : boolean := FALSE; -- differential mode, automatically instantiates the correct buffer
USE_DATAPATH : boolean := TRUE
);
port(
CLOCK : in std_logic;
RESET : in std_logic;
CLK_RDY : out std_logic;
CLK_STATUS : out std_logic_vector((16*NROF_CLOCKCOMP)-1 downto 0);
CLK200 : in std_logic; -- optional 200MHz refclk
-- to sensor (external)
LS_OUT_CLK : out std_logic_vector(NROF_CLOCKCOMP-1 downto 0);
LS_OUT_CLKb : out std_logic_vector(NROF_CLOCKCOMP-1 downto 0); -- only used in differential mode
HS_OUT_CLK : out std_logic_vector(NROF_CLOCKCOMP-1 downto 0);
HS_OUT_CLKb : out std_logic_vector(NROF_CLOCKCOMP-1 downto 0);
-- from sensor (only used when USED_EXT_CLK = YES)
LS_IN_CLK : in std_logic_vector(NROF_CLOCKCOMP-1 downto 0);
LS_IN_CLKb : in std_logic_vector(NROF_CLOCKCOMP-1 downto 0);
HS_IN_CLK : in std_logic_vector(NROF_CLOCKCOMP-1 downto 0);
HS_IN_CLKb : in std_logic_vector(NROF_CLOCKCOMP-1 downto 0);
--serdes data, directly connected to bondpads
SDATAP : in std_logic_vector(NROF_CONN-1 downto 0);
SDATAN : in std_logic_vector(NROF_CONN-1 downto 0);
-- status info
EDGE_DETECT : out std_logic_vector(NROF_CONN-1 downto 0);
TRAINING_DETECT : out std_logic_vector(NROF_CONN-1 downto 0);
STABLE_DETECT : out std_logic_vector(NROF_CONN-1 downto 0);
FIRST_EDGE_FOUND : out std_logic_vector(NROF_CONN-1 downto 0);
SECOND_EDGE_FOUND : out std_logic_vector(NROF_CONN-1 downto 0);
NROF_RETRIES : out std_logic_vector((16*NROF_CONN)-1 downto 0);
TAP_SETTING : out std_logic_vector((10*NROF_CONN)-1 downto 0);
WINDOW_WIDTH : out std_logic_vector((10*NROF_CONN)-1 downto 0);
WORD_ALIGN : out std_logic_vector(NROF_CONN-1 downto 0);
TIMEOUTONACK : out std_logic_vector(NROF_CONTR_CONN-1 downto 0);
-- control
ALIGN_START : in std_logic;
ALIGN_BUSY : out std_logic;
ALIGNED : out std_logic;
FIFO_EN : in std_logic;
AUTOALIGN : in std_logic;
TRAINING : in std_logic_vector(DATAWIDTH-1 downto 0);
MANUAL_TAP : in std_logic_vector(9 downto 0);
EN_LS_CLK_OUT : in std_logic;
EN_HS_CLK_OUT : in std_logic;
-- parallel data out
FIFO_RDEN : in std_logic;
FIFO_EMPTY : out std_logic;
FIFO_DATAOUT : out std_logic_vector((NROF_CONN*DATAWIDTH)-1 downto 0)
);
end component iserdes_interface;
component iserdes_interface_s6 is
port (
CLOCK : in std_logic;
RESET : in std_logic;
-- serdes clock, directly connected to bondpads
SCLKP : in std_logic;
SCLKN : in std_logic;
-- serdes data, directly connected to bondpads
SDATAP : in std_logic_vector(4 downto 0);
SDATAN : in std_logic_vector(4 downto 0);
-- control
ALIGN_START : in std_logic;
FIFO_EN : in std_logic;
TRAINING : in std_logic_vector(DATAWIDTH-1 downto 0);
MANUAL_TAP : in std_logic_vector(9 downto 0);
-- status
PLL_LOCKED : out std_logic;
ALIGN_BUSY : out std_logic;
ALIGNED : out std_logic;
-- parallel data out
FIFO_RDEN : in std_logic;
FIFO_EMPTY : out std_logic;
FIFO_DATAOUT : out std_logic_vector((NROF_CONN*DATAWIDTH)-1 downto 0)
);
end component iserdes_interface_s6;
signal CLK_RDY : std_logic;
signal CLK_STATUS : std_logic_vector((16*NROF_CLOCKCOMP)-1 downto 0);
signal EDGE_DETECT : std_logic_vector(NROF_CONN-1 downto 0);
signal TRAINING_DETECT : std_logic_vector(NROF_CONN-1 downto 0);
signal STABLE_DETECT : std_logic_vector(NROF_CONN-1 downto 0);
signal FIRST_EDGE_FOUND : std_logic_vector(NROF_CONN-1 downto 0);
signal SECOND_EDGE_FOUND : std_logic_vector(NROF_CONN-1 downto 0);
signal NROF_RETRIES : std_logic_vector((16*NROF_CONN)-1 downto 0);
signal TAP_SETTING : std_logic_vector((10*NROF_CONN)-1 downto 0);
signal WINDOW_WIDTH : std_logic_vector((10*NROF_CONN)-1 downto 0);
signal WORD_ALIGN : std_logic_vector(NROF_CONN-1 downto 0);
signal TIMEOUTONACK : std_logic_vector(NROF_CONTR_CONN-1 downto 0);
-- control
--signal ALIGN_START : std_logic;
signal ALIGN_BUSY : std_logic;
signal ALIGNED : std_logic;
--signal FIFO_EN : std_logic;
--signal AUTOALIGN : std_logic;
--signal TRAINING : std_logic_vector(DATAWIDTH-1 downto 0);
--signal MANUAL_TAP : std_logic_vector(9 downto 0);
--signal EN_LS_CLK_OUT : std_logic;
--signal EN_HS_CLK_OUT : std_logic;
-- parallel data out
signal FIFO_RDEN : std_logic;
signal FIFO_EMPTY : std_logic;
signal FIFO_DATAOUT : std_logic_vector((NROF_CONN*DATAWIDTH)-1 downto 0);
--
-- Sync Channel Decoder
--
component syncchanneldecoder
generic (
NROF_CONN : integer;
DATAWIDTH : integer;
NROF_WINDOWS : integer
);
port (
-- Control signals
CLOCK : in std_logic;
RESET : in std_logic;
-- Internal signaling
en_decoder : in std_logic;
--busy_decoder : out std_logic;
PAR_DATA_RDEN : out std_logic;
PAR_DATA_EMPTY : in std_logic;
PAR_DATAIN : in std_logic_vector((NROF_CONN*DATAWIDTH)-1 downto 0);
PAR_SYNCOUT : out std_logic_vector((DATAWIDTH)-1 downto 0);
PAR_DATAOUT : out std_logic_vector(((NROF_CONN-1)*DATAWIDTH)-1 downto 0);
PAR_DATA_IMGVALID : out std_logic;
PAR_DATA_BLACKVALID : out std_logic;
PAR_DATA_LINE : out std_logic;
PAR_DATA_FRAME : out std_logic;
KERNEL_ODD_EVEN : out std_logic;
START_KERNEL : out std_logic;
StartOddEven : in std_logic_vector(31 downto 0);
LS_value : in std_logic_vector(9 downto 0);
LE_value : in std_logic_vector(9 downto 0);
FS_value : in std_logic_vector(9 downto 0);
FE_value : in std_logic_vector(9 downto 0);
BL_value : in std_logic_vector(9 downto 0);
IMG_value : in std_logic_vector(9 downto 0);
TR_value : in std_logic_vector(9 downto 0);
CRC_value : in std_logic_vector(9 downto 0);
-- synchro signals
framestart : out std_logic;
windowstart : out std_logic;
windowend : out std_logic;
linestart : out std_logic;
lineend : out std_logic;
blacklinestart : out std_logic;
blacklineend : out std_logic;
imagelinestart : out std_logic;
imagelineend : out std_logic;
validcrc : out std_logic;
-- counters
FramesCnt : out std_logic_vector(31 downto 0);
-- lines/frame counter
BlackLinesCnt : out std_logic_vector(31 downto 0);
ImgLinesCnt : out std_logic_vector(31 downto 0);
-- pixels/frame counter
BlackPixelCnt : out std_logic_vector(31 downto 0);
ImgPixelCnt : out std_logic_vector(31 downto 0);
-- windows/frame counter
WindowsCnt : out std_logic_vector(31 downto 0);
-- clocks/frame counter -> fps
ClocksCnt : out std_logic_vector(31 downto 0);
StartLineCnt : out std_logic_vector(31 downto 0);
EndLineCnt : out std_logic_vector(31 downto 0);
-- monitors
MONITOR : in std_logic_vector(1 downto 0);
Monitor0HighCnt : out std_logic_vector(31 downto 0);
Monitor0LowCnt : out std_logic_vector(31 downto 0);
Monitor1HighCnt : out std_logic_vector(31 downto 0);
Monitor1LowCnt : out std_logic_vector(31 downto 0)
);
end component;
--signal SYNC_PAR_DATA_RDEN : std_logic;
--signal SYNC_PAR_DATAIN : std_logic_vector((NROF_CONN*DATAWIDTH)-1 downto 0);
signal SYNC_PAR_SYNCOUT : std_logic_vector(DATAWIDTH-1 downto 0);
signal SYNC_PAR_DATAOUT : std_logic_vector(((NROF_CONN-1)*DATAWIDTH)-1 downto 0);
signal SYNC_PAR_DATA_IMGVALID : std_logic;
signal SYNC_PAR_DATA_BLACKVALID : std_logic;
signal SYNC_PAR_DATA_LINE : std_logic;
signal SYNC_PAR_DATA_FRAME : std_logic;
signal SYNC_KERNEL_ODD_EVEN : std_logic;
signal SYNC_START_KERNEL : std_logic;
--signal SYNC_VIDEO_SYNC : std_logic_vector(4 downto 0);
-- synchro signals
signal framestart : std_logic;
signal windowstart : std_logic;
signal windowend : std_logic;
signal linestart : std_logic;
signal lineend : std_logic;
signal blacklinestart : std_logic;
signal blacklineend : std_logic;
signal imagelinestart : std_logic;
signal imagelineend : std_logic;
signal validcrc : std_logic;
--
-- CRC Checker
--
constant POLYNOMIAL : std_logic_vector(10 downto 0) := "11001001111";
component crc_checker is
generic (
NROF_DATACONN : integer;
DATAWIDTH : integer;
NROF_WINDOWS : integer;
POLYNOMIAL : std_logic_vector
);
port (
-- Control signals
CLOCK : in std_logic;
RESET : in std_logic;
-- APP_CFG_REG : in AppCfgRegTp;
INITVALUE : in std_logic;
en_decoder : in std_logic;
-- Data input
PAR_SYNC_IN : in std_logic_vector(DATAWIDTH-1 downto 0);
PAR_DATA_IN : in std_logic_vector((NROF_DATACONN*DATAWIDTH)-1 downto 0);
PAR_DATA_IMGVALID_IN : in std_logic;
PAR_DATA_BLACKVALID_IN : in std_logic;
PAR_DATA_CRCVALID_IN : in std_logic;
PAR_DATA_LINE_IN : in std_logic;
PAR_DATA_FRAME_IN : in std_logic;
START_KERNEL_IN : in std_logic;
KERNEL_ODD_EVEN_IN : in std_logic;
VIDEO_SYNC_IN : in std_logic_vector(4 downto 0);
-- Data out
PAR_SYNC_OUT : out std_logic_vector(DATAWIDTH-1 downto 0);
PAR_DATA_OUT : out std_logic_vector((NROF_DATACONN*DATAWIDTH)-1 downto 0);
PAR_DATA_IMGVALID_OUT : out std_logic;
PAR_DATA_BLACKVALID_OUT : out std_logic;
PAR_DATA_CRCVALID_OUT : out std_logic;
PAR_DATA_LINE_OUT : out std_logic;
PAR_DATA_FRAME_OUT : out std_logic;
START_KERNEL_OUT : out std_logic;
KERNEL_ODD_EVEN_OUT : out std_logic;
VIDEO_SYNC_OUT : out std_logic_vector(4 downto 0);
--status
CRC_STATUS : out std_logic_vector(NROF_DATACONN-1 downto 0)
);
end component;
signal CRC_PAR_SYNC_OUT : std_logic_vector(DATAWIDTH-1 downto 0);
signal CRC_PAR_DATA_OUT : std_logic_vector(((NROF_CONN-1)*DATAWIDTH)-1 downto 0);
signal CRC_PAR_DATA_IMGVALID_OUT : std_logic;
signal CRC_PAR_DATA_BLACKVALID_OUT : std_logic;
signal CRC_PAR_DATA_CRCVALID_OUT : std_logic;
signal CRC_PAR_DATA_LINE_OUT : std_logic;
signal CRC_PAR_DATA_FRAME_OUT : std_logic;
signal CRC_START_KERNEL : std_logic;
signal CRC_KERNEL_ODD_EVEN : std_logic;
signal CRC_VIDEO_SYNC : std_logic_vector(4 downto 0);
signal CRC_STATUS : std_logic_vector(NROF_CONN - 2 downto 0);
signal CRC_DEBUG : std_logic_vector(((NROF_CONN-1)*(2*DATAWIDTH+1))-1 downto 0);
--
-- Data Channel Re-Mapper
--
component remapper
generic (
NROF_DATACONN : integer;
DATAWIDTH : integer;
NROF_WINDOWS : integer
);
port (
-- Control signals
CLOCK : in std_logic;
RESET : in std_logic;
WriteCfg : in std_logic_vector(2 downto 0);
RemapMode : in std_logic_vector(2 downto 0);
-- Data input
--from serial
PAR_SYNC : in std_logic_vector((DATAWIDTH)-1 downto 0);
PAR_DATA : in std_logic_vector((NROF_DATACONN*DATAWIDTH)-1 downto 0);
PAR_DATA_IMGVALID : in std_logic;
PAR_DATA_BLACKVALID : in std_logic;
PAR_DATA_CRCVALID : in std_logic;
PAR_DATA_LINE : in std_logic;
PAR_DATA_FRAME : in std_logic;
-- kernel odd/even control
START_KERNEL : in std_logic;
KERNEL_ODD_EVEN : in std_logic;
VIDEO_SYNC_IN : in std_logic_vector(4 downto 0);
VIDEO_SYNC_OUT : out std_logic_vector(4 downto 0);
en_decoder : in std_logic;
-- Data output
PAR_DATA_OUT : out std_logic_vector((NROF_DATACONN*DATAWIDTH)-1 downto 0);
PAR_DATA_VALID_OUT : out std_logic;
PAR_DATA_LINE_OUT : out std_logic;
PAR_DATA_FRAME_OUT : out std_logic;
PAR_DATA_WINDOW_OUT : out std_logic
);
end component;
signal REMAP_PAR_DATA_OUT : std_logic_vector(((NROF_CONN-1)*DATAWIDTH)-1 downto 0);
signal REMAP_PAR_DATA_VALID_OUT : std_logic;
signal REMAP_PAR_DATA_LINE_OUT : std_logic;
signal REMAP_PAR_DATA_FRAME_OUT : std_logic;
signal REMAP_PAR_DATA_WINDOW_OUT : std_logic;
signal REMAP_VIDEO_SYNC : std_logic_vector(4 downto 0);
--
-- FPN/PRNU Correction
--
component correct_column_fpn_prnu_dsp48e is
generic (
NROF_DATACONN : integer;
DATAWIDTH : integer;
ENABLECORRECT : boolean;
C_FAMILY : string
);
port (
-- Control signals
CLOCK : in std_logic;
RESET : in std_logic;
CorrectValues : in std_logic_vector((NROF_DATACONN*4*16)-1 downto 0);
WR_DATA_in : in std_logic_vector((NROF_DATACONN*DATAWIDTH)-1 downto 0);
WR_NEXT_in : in std_logic;
WR_FRAME_in : in std_logic;
WR_LINE_in : in std_logic;
WR_WINDOW_in : in std_logic;
WR_DATA_out : out std_logic_vector((NROF_DATACONN*DATAWIDTH)-1 downto 0);
WR_NEXT_out : out std_logic;
WR_FRAME_out : out std_logic;
WR_LINE_out : out std_logic;
WR_WINDOW_out : out std_logic;
VIDEO_SYNC_IN : in std_logic_vector(4 downto 0);
VIDEO_SYNC_OUT : out std_logic_vector(4 downto 0)
);
end component;
signal BLC_CORRECT_VALUES : std_logic_vector(((NROF_CONN-1)*4*16)-1 downto 0);
signal BLC_PAR_DATA_OUT : std_logic_vector(((NROF_CONN-1)*DATAWIDTH)-1 downto 0);
signal BLC_PAR_DATA_VALID_OUT : std_logic;
signal BLC_PAR_DATA_LINE_OUT : std_logic;
signal BLC_PAR_DATA_FRAME_OUT : std_logic;
signal BLC_PAR_DATA_WINDOW_OUT : std_logic;
signal BLC_VIDEO_SYNC : std_logic_vector(4 downto 0);
--
-- Trigger Generator
--
component triggergenerator
port (
-- Control signals
csi_clockreset_clk : in std_logic;
csi_clockreset_reset_n : in std_logic;
coe_external_trigger_in : in std_logic;
readouttrigger : in std_logic;
ENABLETRIGGER : in std_logic_vector(2 downto 0);
SYNCTOREADOUT_OR_EXT : in std_logic_vector(2 downto 0); --(0): enable timeout default frequency
--(1): trigger on readout input trigger
--(2): trigger on external input trigger
--Note: (0) can be combined with (1) xor (2), (1) and (2) can be combined but it is prob not usefull
DEFAULTFREQ : in std_logic_vector(31 downto 0); --acutally an interval
TRIGGERLENGTHLOW0 : in std_logic_vector(31 downto 0);
TRIGGERLENGTHHIGH0 : in std_logic_vector(31 downto 0);
TRIGGERLENGTHLOW1 : in std_logic_vector(31 downto 0);
TRIGGERLENGTHHIGH1 : in std_logic_vector(31 downto 0);
TRIGGERLENGTHLOW2 : in std_logic_vector(31 downto 0);
TRIGGERLENGTHHIGH2 : in std_logic_vector(31 downto 0);
EXTERNAL_TRIGGER_DEB : in std_logic_vector(31 downto 0);
EXTERNAL_TRIGGER_POL : in std_logic; --0 is active low 1 is active high
coe_vita_TRIGGER : out std_logic_vector(2 downto 0)
);
end component;
-- signal readouttrigger : std_logic;
-- signal readouttrigger_d1 : std_logic;
-- signal readouttrigger_d2 : std_logic;
signal triggen_vita_trigger : std_logic_vector(2 downto 0);
--
-- Delayed Start Frame signal
--
component pulse_regen is
generic
(
C_FAMILY : string := "kintex7"
);
port
(
rst : IN std_logic;
clk1 : IN std_logic;
pulse1 : IN std_logic;
clk2 : IN std_logic;
pulse2 : OUT std_logic
);
end component;
signal framestart_cnt : unsigned(15 downto 0) := (others => '0');
signal framestart_active : std_logic := '0';
signal framestart2 : std_logic;
signal framestart2_regen : std_logic;
--
-- Video Sync Generator
--
component VideoSyncGen is
generic (
HWidth_g : integer := 16;
VWidth_g : integer := 16
);
port (
-- Global Reset
i_Clk_p : in std_logic;
i_Reset_p : in std_logic;
--
i_Restart_p : in std_logic;
-- Video Configuration
iv16_VidHActive_p : in std_logic_vector(15 downto 0);
iv16_VidHFPorch_p : in std_logic_vector(15 downto 0);
iv16_VidHSync_p : in std_logic_vector(15 downto 0);
iv16_VidHBPorch_p : in std_logic_vector(15 downto 0);
--
iv16_VidVActive_p : in std_logic_vector(15 downto 0);
iv16_VidVFPorch_p : in std_logic_vector(15 downto 0);
iv16_VidVSync_p : in std_logic_vector(15 downto 0);
iv16_VidVBPorch_p : in std_logic_vector(15 downto 0);
-- Video Synchronization Signals
o_HSync_p : out std_logic;
o_VSync_p : out std_logic;
o_De_p : out std_logic;
o_HBlank_p : out std_logic;
o_VBlank_p : out std_logic;
-- Data Request strobe (1 cycle in advance of synchronization signals)
ov_HCount_p : out std_logic_vector(HWidth_g-1 downto 0);
ov_VCount_p : out std_logic_vector(VWidth_g-1 downto 0);
o_PixelRequest_p : out std_logic
);
end component VideoSyncGen;
signal syncgen_hsync : std_logic;
signal syncgen_vsync : std_logic;
signal syncgen_de : std_logic;
signal syncgen_hblank : std_logic;
signal syncgen_vblank : std_logic;
--signal syncgen_pixelrequest : std_logic;
--
-- De-Multiplexer
--
component afifo_64i_16o is
generic
(
C_FAMILY : string := "virtex6"
);
port
(
rst : IN std_logic;
wr_clk : IN std_logic;
wr_en : IN std_logic;
din : IN std_logic_VECTOR(63 downto 0);
rd_clk : IN std_logic;
rd_en : IN std_logic;
dout : OUT std_logic_VECTOR(15 downto 0);
empty : OUT std_logic;
full : OUT std_logic
);
end component;
signal demux_din : std_logic_vector(63 downto 0);
signal demux_dout : std_logic_vector(15 downto 0);
signal demux_empty : std_logic;
signal demux_full : std_logic;
--
-- I/O registers & buffers
--
signal clk_n : std_logic;
signal net0 : std_logic;
signal net1 : std_logic;
signal oe_n : std_logic;
signal vita_clk_pll_o : std_logic;
signal vita_reset_n_o : std_logic;
signal vita_trigger_o : std_logic_vector(2 downto 0);
signal vita_spi_sclk_o : std_logic;
signal vita_spi_ssel_n_o : std_logic;
signal vita_spi_mosi_o : std_logic;
signal vita_clk_pll_t : std_logic;
signal vita_reset_n_t : std_logic;
signal vita_trigger_t : std_logic_vector(2 downto 0);
signal vita_spi_sclk_t : std_logic;
signal vita_spi_ssel_n_t : std_logic;
signal vita_spi_mosi_t : std_logic;
begin
host_iserdes_reset_n <= not host_iserdes_reset;
--
-- SPI Controller
--
vita_spi: spi_top
generic map
(
gSIMULATION => 0, --gSIMULATION,
gSysClkSpeed => 50, -- 50MHz --gSysClkSpeed,
--LowLevel SPI settings
gSpiClkSpeed => 1000, -- 1000KHz (or 1MHz)
gUseFixedSpeed => 0,
gDATA_WIDTH => 26,
gTxMSB_FIRST => 1,
gRxMSB_FIRST => 1,
gSCLK_POLARITY => '0',
gCS_POLARITY => '1',
gEN_POLARITY => '0',
gMOSI_POLARITY => '0',
gMISO_POLARITY => '0',
gMISO_SAMPLE => '0',
gMOSI_CLK => '0',
--Seq SPI settings
gSyncTriggerWidth => 10,
gRWbitposition => 16
)
port map
(
CLOCK => host_spi_clk,
RESET => host_spi_reset,
TIMING => host_spi_timing, --TIMING,
BUSY => vita_spi_status_busy,
--synchro signals
synctriggers => (others => '0'), --synctriggers,
sync1_select => (others => '0'), --sync1_select,
sync2_select => (others => '0'), --sync2_select,
-- Fifo signals
-- read fifo interface (SPI write path/SPI read address path)
APP_RDFIFO_CLK => vita_spi_txfifo_clk,
APP_RDFIFO_EN => vita_spi_txfifo_ren,
APP_RDFIFO_DATA_OUT => vita_spi_txfifo_dout,
APP_RDFIFO_EMPTY => vita_spi_txfifo_empty,
-- write fifo interface (SPI read data path)
APP_WRFIFO_CLK => vita_spi_rxfifo_clk,
APP_WRFIFO_EN => vita_spi_rxfifo_wen,
APP_WRFIFO_DATA_IN => vita_spi_rxfifo_din,
APP_WRFIFO_FULL => vita_spi_rxfifo_full,
ERROR => vita_spi_status_error,
--
-- SPI
--
SCLK => vita_spi_sclk_o,
MOSI => vita_spi_mosi_o,
MISO => io_vita_spi_miso,
CS => vita_spi_ssel_n_o,
EN => open
);
host_spi_status_busy <= vita_spi_status_busy;
host_spi_status_error <= vita_spi_status_error;
--
-- VITA SPI FIFOs
--
vita_spi_txfifo_l : afifo_32
generic map
(
C_FAMILY => C_FAMILY
)
port map
(
rst => host_spi_reset,
wr_clk => host_spi_txfifo_clk,
wr_en => host_spi_txfifo_wen,
din => host_spi_txfifo_din,
rd_clk => vita_spi_txfifo_clk,
rd_en => vita_spi_txfifo_ren,
dout => vita_spi_txfifo_dout,
empty => vita_spi_txfifo_empty,
full => host_spi_txfifo_full
);
vita_spi_rxfifo_l : afifo_32
generic map
(
C_FAMILY => C_FAMILY
)
port map
(
rst => host_spi_reset,
wr_clk => vita_spi_rxfifo_clk,
wr_en => vita_spi_rxfifo_wen,
din => vita_spi_rxfifo_din,
rd_clk => host_spi_rxfifo_clk,
rd_en => host_spi_rxfifo_ren,
dout => host_spi_rxfifo_dout,
empty => host_spi_rxfifo_empty,
full => vita_spi_rxfifo_full
);
--
-- VITA Serial LVDS Receiver
--
vita_iserdes_s6 : if ( C_FAMILY = "spartan6" ) generate
vita_iserdes : iserdes_interface_s6
port map (
CLOCK => clk ,
RESET => host_iserdes_reset ,
-- serdes clock, directly connected to bondpads
SCLKP => io_vita_clk_out_p ,
SCLKN => io_vita_clk_out_n ,
-- serdes data, directly connected to bondpads
SDATAP(4 downto 1) => io_vita_data_p(3 downto 0) ,
SDATAP(0) => io_vita_sync_p ,
SDATAN(4 downto 1) => io_vita_data_n(3 downto 0) ,
SDATAN(0) => io_vita_sync_n ,
-- control
ALIGN_START => host_iserdes_align_start ,
FIFO_EN => host_iserdes_fifo_enable ,
TRAINING => host_iserdes_training ,
MANUAL_TAP => host_iserdes_manual_tap ,
-- status
PLL_LOCKED => CLK_RDY ,
ALIGN_BUSY => ALIGN_BUSY ,
ALIGNED => ALIGNED ,
-- parallel data out
FIFO_RDEN => FIFO_RDEN ,
FIFO_EMPTY => FIFO_EMPTY ,
FIFO_DATAOUT => FIFO_DATAOUT
);
host_iserdes_clk_ready <= CLK_RDY;
host_iserdes_clk_status <= CLK_STATUS;
host_iserdes_align_busy <= ALIGN_BUSY;
host_iserdes_aligned <= ALIGNED;
end generate;
vita_iserdes_v5 : if not ( C_FAMILY = "spartan6" ) generate
vita_iserdes : iserdes_interface
generic map (
SIMULATION => gSIMULATION ,
NROF_CONN => NROF_CONN ,
NROF_CONTR_CONN => NROF_CONN ,
NROF_CLOCKCOMP => 1 ,
DATAWIDTH => DATAWIDTH ,
RETRY_MAX => 32767 ,
STABLE_COUNT => 16 ,
--TAP_COUNT_MAX => 64 , -- for Virtex-5 IODELAY
TAP_COUNT_MAX => 32 , -- for Virtex-6 IODELAYE1
DATA_RATE => "DDR" ,
DIFF_TERM => TRUE ,
USE_FIFO => TRUE ,
USE_BLOCKRAMFIFO => TRUE ,
INVERT_OUTPUT => INVBOOL , --change back for final system !!!!!
INVERSE_BITORDER => FALSE ,
CLKSPEED => CLKSPEED ,
--SIM_DEVICE => "VIRTEX5" ,
C_FAMILY => C_FAMILY ,
NROF_DELAYCTRLS => NROF_DELAYCTRLS, --should be 2 for 'correct' char board, change when required
IDELAYCLK_MULT => 3 ,
IDELAYCLK_DIV => 1 ,
GENIDELAYCLK => FALSE ,
USE_OUTPLL => FALSE , --use output/multiplieng PLL instead of DCM
USE_INPLL => FALSE ,
USE_HS_EXT_CLK_IN => TRUE,--useLVDSclocks(gEngineering, gLVDS_OUT) ,
USE_LS_EXT_CLK_IN => FALSE ,
USE_DIFF_HS_CLK_IN => TRUE,--useLVDSclocks(gEngineering, gLVDS_OUT) , -- differential mode, automatically instantiates the correct buffer
USE_DIFF_LS_CLK_IN => FALSE , -- differential mode, automatically instantiates the correct buffer
USE_HS_REGIONAL_CLK => TRUE,--useLVDSclocks(gEngineering, gLVDS_OUT) , -- only used when USE_HS_EXT_CLK_IN = yes
USE_LS_REGIONAL_CLK => FALSE , --
USE_HS_EXT_CLK_OUT => FALSE , -- use external clock high speed clock out
USE_LS_EXT_CLK_OUT => FALSE , -- use external clock low speed clock out
USE_DIFF_HS_CLK_OUT => TRUE , -- differential mode, automatically instantiates the correct buffer
USE_DIFF_LS_CLK_OUT => FALSE , -- differential mode, automatically instantiates the correct buffer
USE_DATAPATH => TRUE--usedatapathfunc(gEngineering, gLVDS_OUT)
)
port map(
CLOCK => clk ,
RESET => host_iserdes_reset,
CLK200 => clk200 ,
CLK_RDY => CLK_RDY ,
CLK_STATUS => CLK_STATUS ,
-- to sensor (external)
--LS_OUT_CLK(0) => open, --CLK_PLL ,
--LS_OUT_CLKb(0) => open, --CLK_PLL_n ,
--HS_OUT_CLK(0) => open, --ClockIn_P ,
--HS_OUT_CLKb(0) => open, --ClockIn_N ,
-- from sensor (only used when USED_EXT_CLK = YES)
LS_IN_CLK(0) => '0',
LS_IN_CLKb(0) => '0',
HS_IN_CLK(0) => io_vita_clk_out_p,
HS_IN_CLKb(0) => io_vita_clk_out_n,
--serdes data, directly connected to bondpads
SDATAP(4 downto 1) => io_vita_data_p(3 downto 0),
SDATAP(0) => io_vita_sync_p ,
SDATAN(4 downto 1) => io_vita_data_n(3 downto 0),
SDATAN(0) => io_vita_sync_n ,
-- status info
EDGE_DETECT => EDGE_DETECT ,
TRAINING_DETECT => TRAINING_DETECT ,
STABLE_DETECT => STABLE_DETECT ,
FIRST_EDGE_FOUND => FIRST_EDGE_FOUND ,
SECOND_EDGE_FOUND => SECOND_EDGE_FOUND ,
NROF_RETRIES => NROF_RETRIES ,
TAP_SETTING => TAP_SETTING ,
WINDOW_WIDTH => WINDOW_WIDTH ,
WORD_ALIGN => WORD_ALIGN ,
-- control
ALIGN_START => host_iserdes_align_start,
ALIGN_BUSY => ALIGN_BUSY ,
ALIGNED => ALIGNED ,
FIFO_EN => host_iserdes_fifo_enable,
AUTOALIGN => host_iserdes_auto_align,
TRAINING => host_iserdes_training,
MANUAL_TAP => host_iserdes_manual_tap,
EN_LS_CLK_OUT => '0' ,--APP_CFG_REG.Sysmode(5),
EN_HS_CLK_OUT => '0' ,--APP_CFG_REG.Sysmode(6),
TIMEOUTONACK => open ,
-- parallel data out
FIFO_RDEN => FIFO_RDEN ,
FIFO_EMPTY => FIFO_EMPTY ,
FIFO_DATAOUT => FIFO_DATAOUT
);
host_iserdes_clk_ready <= CLK_RDY;
host_iserdes_clk_status <= CLK_STATUS;
host_iserdes_align_busy <= ALIGN_BUSY;
host_iserdes_aligned <= ALIGNED;
end generate;
--
-- Sync Channel Decoder
--
vita_syncchanneldecoder: syncchanneldecoder
generic map (
NROF_CONN => NROF_CONN ,
DATAWIDTH => DATAWIDTH ,
NROF_WINDOWS => 8
)
port map (
-- Control signals
CLOCK => clk ,
RESET => host_decoder_reset ,
-- Internal signaling
en_decoder => host_decoder_enable ,
PAR_DATA_RDEN => FIFO_RDEN ,
PAR_DATA_EMPTY => FIFO_EMPTY ,
PAR_DATAIN => FIFO_DATAOUT ,
PAR_SYNCOUT => SYNC_PAR_SYNCOUT ,
PAR_DATAOUT => SYNC_PAR_DATAOUT ,
PAR_DATA_IMGVALID => SYNC_PAR_DATA_IMGVALID ,
PAR_DATA_BLACKVALID => SYNC_PAR_DATA_BLACKVALID ,
PAR_DATA_LINE => SYNC_PAR_DATA_LINE ,
PAR_DATA_FRAME => SYNC_PAR_DATA_FRAME ,
KERNEL_ODD_EVEN => SYNC_KERNEL_ODD_EVEN ,
START_KERNEL => SYNC_START_KERNEL ,
StartOddEven => host_decoder_startoddeven,
LS_value => host_decoder_code_ls ,
LE_value => host_decoder_code_le ,
FS_value => host_decoder_code_fs ,
FE_value => host_decoder_code_fe ,
BL_value => host_decoder_code_bl ,
IMG_value => host_decoder_code_img ,
TR_value => host_decoder_code_tr ,
CRC_value => host_decoder_code_crc ,
-- synchro signals
framestart => framestart ,
windowstart => windowstart ,
windowend => windowend ,
linestart => linestart ,
lineend => lineend ,
blacklinestart => blacklinestart ,
blacklineend => blacklineend ,
imagelinestart => imagelinestart ,
imagelineend => imagelineend ,
validcrc => validcrc ,
-- counters
FramesCnt => host_decoder_cnt_frames,
-- lines/frame counter
BlackLinesCnt => host_decoder_cnt_black_lines,
ImgLinesCnt => host_decoder_cnt_image_lines,
-- pixels/frame counter
BlackPixelCnt => host_decoder_cnt_black_pixels,
ImgPixelCnt => host_decoder_cnt_image_pixels,
-- windows/frame counter
WindowsCnt => host_decoder_cnt_windows,
-- clocks/frame counter -> fps
ClocksCnt => host_decoder_cnt_clocks,
StartLineCnt => host_decoder_cnt_start_lines,
EndLineCnt => host_decoder_cnt_end_lines,
-- monitors
MONITOR => io_vita_monitor,
Monitor0HighCnt => host_decoder_cnt_monitor0high,
Monitor0LowCnt => host_decoder_cnt_monitor0low,
Monitor1HighCnt => host_decoder_cnt_monitor1high,
Monitor1LowCnt => host_decoder_cnt_monitor1low
);
host_decoder_frame_start <= framestart;
--
-- CRC Checker
--
vita_crc_checker: crc_checker
generic map (
NROF_DATACONN => NROF_CONN - 1 ,
DATAWIDTH => DATAWIDTH ,
NROF_WINDOWS => NROF_WINDOWS ,
POLYNOMIAL => POLYNOMIAL
)
port map (
-- Control signals
CLOCK => clk ,
RESET => host_decoder_reset ,
INITVALUE => host_crc_initvalue ,
en_decoder => host_decoder_enable ,
-- Data input
PAR_SYNC_IN => SYNC_PAR_SYNCOUT ,
PAR_DATA_IN => SYNC_PAR_DATAOUT ,
PAR_DATA_IMGVALID_IN => SYNC_PAR_DATA_IMGVALID ,
PAR_DATA_BLACKVALID_IN => SYNC_PAR_DATA_BLACKVALID ,
PAR_DATA_CRCVALID_IN => validcrc ,
PAR_DATA_LINE_IN => SYNC_PAR_DATA_LINE ,
PAR_DATA_FRAME_IN => SYNC_PAR_DATA_FRAME ,
START_KERNEL_IN => SYNC_START_KERNEL ,
KERNEL_ODD_EVEN_IN => SYNC_KERNEL_ODD_EVEN ,
VIDEO_SYNC_IN => "00000", --SYNC_VIDEO_SYNC ,
-- Data out
PAR_SYNC_OUT => CRC_PAR_SYNC_OUT ,
PAR_DATA_OUT => CRC_PAR_DATA_OUT ,
PAR_DATA_IMGVALID_OUT => CRC_PAR_DATA_IMGVALID_OUT ,
PAR_DATA_BLACKVALID_OUT => CRC_PAR_DATA_BLACKVALID_OUT ,
PAR_DATA_CRCVALID_OUT => CRC_PAR_DATA_CRCVALID_OUT ,
PAR_DATA_LINE_OUT => CRC_PAR_DATA_LINE_OUT ,
PAR_DATA_FRAME_OUT => CRC_PAR_DATA_FRAME_OUT ,
START_KERNEL_OUT => CRC_START_KERNEL ,
KERNEL_ODD_EVEN_OUT => CRC_KERNEL_ODD_EVEN ,
VIDEO_SYNC_OUT => open, --CRC_VIDEO_SYNC ,
--status
CRC_STATUS => CRC_STATUS
-- CRC_DEBUG => CRC_DEBUG
);
host_crc_status(31 downto (NROF_CONN - 1)) <= (others => '0');
host_crc_status((NROF_CONN - 2) downto 0) <= CRC_STATUS;
--
-- Data Channel Re-Mapper
--
vita_remapper: remapper
generic map (
NROF_DATACONN => NROF_CONN - 1 ,
DATAWIDTH => DATAWIDTH ,
NROF_WINDOWS => 8
)
port map (
-- Control signals
CLOCK => clk ,
RESET => host_decoder_reset ,
WriteCfg => host_remapper_write_cfg ,
RemapMode => host_remapper_mode ,
-- Data input
--from serial
PAR_SYNC => CRC_PAR_SYNC_OUT ,
PAR_DATA => CRC_PAR_DATA_OUT ,
PAR_DATA_IMGVALID => CRC_PAR_DATA_IMGVALID_OUT ,
PAR_DATA_BLACKVALID => CRC_PAR_DATA_BLACKVALID_OUT ,
PAR_DATA_CRCVALID => CRC_PAR_DATA_CRCVALID_OUT ,
PAR_DATA_LINE => CRC_PAR_DATA_LINE_OUT ,
PAR_DATA_FRAME => CRC_PAR_DATA_FRAME_OUT ,
-- kernel odd/even control
START_KERNEL => CRC_KERNEL_ODD_EVEN ,
KERNEL_ODD_EVEN => CRC_START_KERNEL ,
VIDEO_SYNC_IN => CRC_VIDEO_SYNC ,
VIDEO_SYNC_OUT => REMAP_VIDEO_SYNC ,
en_decoder => host_decoder_enable ,
-- Data output
PAR_DATA_OUT => REMAP_PAR_DATA_OUT ,
PAR_DATA_VALID_OUT => REMAP_PAR_DATA_VALID_OUT ,
PAR_DATA_LINE_OUT => REMAP_PAR_DATA_LINE_OUT ,
PAR_DATA_FRAME_OUT => REMAP_PAR_DATA_FRAME_OUT ,
PAR_DATA_WINDOW_OUT => REMAP_PAR_DATA_WINDOW_OUT
);
--
-- FPN/PRNU Correction
--
vita_blc: correct_column_fpn_prnu_dsp48e
generic map (
NROF_DATACONN => NROF_CONN - 1 ,
DATAWIDTH => DATAWIDTH ,
ENABLECORRECT => true ,
C_FAMILY => C_FAMILY
)
port map (
-- Control signals
CLOCK => clk,
RESET => host_decoder_reset,
CorrectValues => host_fpn_prnu_values,
WR_DATA_in => REMAP_PAR_DATA_OUT,
WR_NEXT_in => REMAP_PAR_DATA_VALID_OUT,
WR_FRAME_in => REMAP_PAR_DATA_LINE_OUT,
WR_LINE_in => REMAP_PAR_DATA_FRAME_OUT,
WR_WINDOW_in => REMAP_PAR_DATA_WINDOW_OUT,
WR_DATA_out => BLC_PAR_DATA_OUT,
WR_NEXT_out => BLC_PAR_DATA_VALID_OUT,
WR_FRAME_out => BLC_PAR_DATA_LINE_OUT,
WR_LINE_out => BLC_PAR_DATA_FRAME_OUT,
WR_WINDOW_out => BLC_PAR_DATA_WINDOW_OUT,
VIDEO_SYNC_IN => REMAP_VIDEO_SYNC,
VIDEO_SYNC_OUT => BLC_VIDEO_SYNC
);
--
-- Trigger Generator
--
-- readouttrigger <= host_triggen_readouttrigger or trigger1;
-- triggen_readouttrigger_l : process (clk)
-- begin
-- if rising_edge( clk ) then
-- readouttrigger_d1 <= readouttrigger;
-- readouttrigger_d2 <= readouttrigger_d1;
-- end if;
-- end process;
vita_triggergenerator: triggergenerator
port map (
-- Control signals
csi_clockreset_clk => clk ,
csi_clockreset_reset_n => host_iserdes_reset_n ,
-- readouttrigger => readouttrigger_d2 ,
coe_external_trigger_in => trigger1 ,
readouttrigger => host_triggen_readouttrigger ,
ENABLETRIGGER => host_triggen_enable ,
SYNCTOREADOUT_OR_EXT => host_triggen_sync2readout ,
DEFAULTFREQ => host_triggen_default_freq ,
TRIGGERLENGTHLOW0 => host_triggen_cnt_trigger0low ,
TRIGGERLENGTHHIGH0 => host_triggen_cnt_trigger0high,
TRIGGERLENGTHLOW1 => host_triggen_cnt_trigger1low ,
TRIGGERLENGTHHIGH1 => host_triggen_cnt_trigger1high,
TRIGGERLENGTHLOW2 => host_triggen_cnt_trigger2low ,
TRIGGERLENGTHHIGH2 => host_triggen_cnt_trigger2high,
EXTERNAL_TRIGGER_DEB => host_triggen_ext_debounce ,
EXTERNAL_TRIGGER_POL => host_triggen_ext_polarity ,
coe_vita_TRIGGER => triggen_vita_trigger
);
triggen_gen_polarity_l : process (clk)
begin
if rising_edge( clk ) then
-- TRIGGER0
if ( host_triggen_gen_polarity(0) = '0' ) then
vita_trigger_o(0) <= triggen_vita_trigger(0);
else
vita_trigger_o(0) <= not triggen_vita_trigger(0);
end if;
-- TRIGGER1
if ( host_triggen_gen_polarity(1) = '0' ) then
vita_trigger_o(1) <= triggen_vita_trigger(1);
else
vita_trigger_o(1) <= not triggen_vita_trigger(1);
end if;
-- TRIGGER2
if ( host_triggen_gen_polarity(2) = '0' ) then
vita_trigger_o(2) <= triggen_vita_trigger(2);
else
vita_trigger_o(2) <= not triggen_vita_trigger(2);
end if;
end if;
end process;
--
-- Delayed Start Frame signal
--
framestart2_l : process (reset, clk)
begin
if ( reset = '1' ) then
framestart_active <= '0';
framestart_cnt <= (others => '0');
framestart2 <= '0';
elsif rising_edge( clk ) then
-- default values
framestart2 <= '0';
-- detect incoming framestart
if ( framestart = '1' ) then
framestart_active <= '1';
framestart_cnt <= (others => '0');
end if;
-- create delayed framestart2
if ( framestart_active = '1' ) then
framestart_cnt <= framestart_cnt + 1;
if ( framestart_cnt = unsigned(host_syncgen_delay)-1 ) then
framestart_active <= '0';
framestart2 <= '1';
end if;
end if;
end if;
end process framestart2_l;
-- regenerate framestart2 to clk4x clock
framestart2_regen_l : pulse_regen
generic map
(
C_FAMILY => C_FAMILY
)
port map
(
rst => reset,
clk1 => clk,
pulse1 => framestart2,
clk2 => clk4x,
pulse2 => framestart2_regen
);
--
-- Video Sync Generator
--
--XSVI_WITH_SYNCGEN : if (C_XSVI_USE_SYNCGEN = 1) generate
syncgen_l : VideoSyncGen
generic map (
HWidth_g => 16,
VWidth_g => 16
)
port map (
-- Global Reset
i_Clk_p => clk4x,
i_Reset_p => reset,
i_Restart_p => framestart2_regen,
-- Video Configuration
iv16_VidHActive_p => host_syncgen_hactive,
iv16_VidHFPorch_p => host_syncgen_hfporch,
iv16_VidHSync_p => host_syncgen_hsync,
iv16_VidHBPorch_p => host_syncgen_hbporch,
--
iv16_VidVActive_p => host_syncgen_vactive,
iv16_VidVFPorch_p => host_syncgen_vfporch,
iv16_VidVSync_p => host_syncgen_vsync,
iv16_VidVBPorch_p => host_syncgen_vbporch,
-- Video Synchronization Signals
o_HSync_p => syncgen_hsync,
o_VSync_p => syncgen_vsync,
o_De_p => syncgen_de,
o_HBlank_p => syncgen_hblank,
o_VBlank_p => syncgen_vblank,
-- Data Request strobe (1 cycle in advance of synchronization signals)
ov_HCount_p => open,
ov_VCount_p => open,
o_PixelRequest_p => open --syncgen_pixelrequest
);
-- syncgen_delay_l : process (clk)
-- begin
-- if rising_edge( clk ) then
---- SYNC_VIDEO_SYNC(4) <= syncgen_vsync;
---- SYNC_VIDEO_SYNC(3) <= syncgen_hsync;
---- SYNC_VIDEO_SYNC(2) <= syncgen_vblank;
---- SYNC_VIDEO_SYNC(1) <= syncgen_hblank;
---- SYNC_VIDEO_SYNC(0) <= syncgen_de;
-- CRC_VIDEO_SYNC(4) <= syncgen_vsync;
-- CRC_VIDEO_SYNC(3) <= syncgen_hsync;
-- CRC_VIDEO_SYNC(2) <= syncgen_vblank;
-- CRC_VIDEO_SYNC(1) <= syncgen_hblank;
-- CRC_VIDEO_SYNC(0) <= syncgen_de;
-- end if;
-- end process;
--
--end generate XSVI_WITH_SYNCGEN;
--XSVI_WITHOUT_SYNCGEN : if (C_XSVI_USE_SYNCGEN = 0) generate
-- Without the VideoSynGen module,
-- only the DE signal is availabel via IMGVALID
CRC_VIDEO_SYNC(4) <= '0'; -- vsync
CRC_VIDEO_SYNC(3) <= '0'; -- hsync
CRC_VIDEO_SYNC(2) <= '0'; -- vblank
CRC_VIDEO_SYNC(1) <= '0'; -- hblank
CRC_VIDEO_SYNC(0) <= CRC_PAR_DATA_IMGVALID_OUT; -- de
--end generate XSVI_WITHOUT_SYNCGEN;
DEMUX_GEN : if (C_XSVI_DIRECT_OUTPUT = 0) generate
--
-- De-Multiplexer
--
demux_fifo_l : afifo_64i_16o
generic map
(
C_FAMILY => C_FAMILY
)
port map
(
rst => framestart,
wr_clk => clk,
wr_en => BLC_VIDEO_SYNC(0), -- delayed version of CRC_PAR_DATA_IMGVALID_OUT
din => demux_din,
rd_clk => clk4x,
rd_en => syncgen_de, --syncgen_pixelrequest,
dout => demux_dout,
empty => demux_empty,
full => demux_full
);
demux_din(63 downto 58) <= BLC_VIDEO_SYNC & framestart;
demux_din(57 downto 48) <= BLC_PAR_DATA_OUT( 9 downto 0);
demux_din(47 downto 42) <= BLC_VIDEO_SYNC & '0';
demux_din(41 downto 32) <= BLC_PAR_DATA_OUT(19 downto 10);
demux_din(31 downto 26) <= BLC_VIDEO_SYNC & '0';
demux_din(25 downto 16) <= BLC_PAR_DATA_OUT(29 downto 20);
demux_din(15 downto 10) <= BLC_VIDEO_SYNC & '0';
demux_din( 9 downto 0) <= BLC_PAR_DATA_OUT(39 downto 30);
--
-- XSVI Interface
--
XSVI_8BIT_GEN : if (C_XSVI_DATA_WIDTH = 8) generate
xsvi_8bit_oregs_l : process (clk4x)
begin
if rising_edge( clk4x ) then
-- xsvi_vsync_o <= demux_dout(15);
-- xsvi_hsync_o <= demux_dout(14);
-- xsvi_vblank_o <= demux_dout(13);
-- xsvi_hblank_o <= demux_dout(12);
-- xsvi_active_video_o <= demux_dout(11);
-- fsync <= demux_dout(10);
xsvi_vsync_o <= syncgen_vsync;
xsvi_hsync_o <= syncgen_hsync;
xsvi_vblank_o <= syncgen_vblank;
xsvi_hblank_o <= syncgen_hblank;
xsvi_active_video_o <= syncgen_de;
fsync <= framestart2_regen;
xsvi_video_data_o <= demux_dout(9 downto 2);
end if;
end process;
end generate XSVI_8BIT_GEN;
XSVI_10BIT_GEN : if (C_XSVI_DATA_WIDTH = 10) generate
xsvi_10bit_oregs_l : process (clk4x)
begin
if rising_edge( clk4x ) then
-- xsvi_vsync_o <= demux_dout(15);
-- xsvi_hsync_o <= demux_dout(14);
-- xsvi_vblank_o <= demux_dout(13);
-- xsvi_hblank_o <= demux_dout(12);
-- xsvi_active_video_o <= demux_dout(11);
-- fsync <= demux_dout(10);
xsvi_vsync_o <= syncgen_vsync;
xsvi_hsync_o <= syncgen_hsync;
xsvi_vblank_o <= syncgen_vblank;
xsvi_hblank_o <= syncgen_hblank;
xsvi_active_video_o <= syncgen_de;
fsync <= framestart2_regen;
xsvi_video_data_o <= demux_dout(9 downto 0);
end if;
end process;
end generate XSVI_10BIT_GEN;
XSVI_16BIT_GEN : if (C_XSVI_DATA_WIDTH = 16) generate
xsvi_16bit_oregs_l : process (clk4x)
begin
if rising_edge( clk4x ) then
-- xsvi_vsync_o <= demux_dout(15);
-- xsvi_hsync_o <= demux_dout(14);
-- xsvi_vblank_o <= demux_dout(13);
-- xsvi_hblank_o <= demux_dout(12);
-- xsvi_active_video_o <= demux_dout(11);
-- fsync <= demux_dout(10);
xsvi_vsync_o <= syncgen_vsync;
xsvi_hsync_o <= syncgen_hsync;
xsvi_vblank_o <= syncgen_vblank;
xsvi_hblank_o <= syncgen_hblank;
xsvi_active_video_o <= syncgen_de;
fsync <= framestart2_regen;
xsvi_video_data_o <= X"80" & demux_dout(9 downto 2);
end if;
end process;
end generate XSVI_16BIT_GEN;
XSVI_24BIT_GEN : if (C_XSVI_DATA_WIDTH = 24) generate
xsvi_24bit_oregs_l : process (clk4x)
begin
if rising_edge( clk4x ) then
-- xsvi_vsync_o <= demux_dout(15);
-- xsvi_hsync_o <= demux_dout(14);
-- xsvi_vblank_o <= demux_dout(13);
-- xsvi_hblank_o <= demux_dout(12);
-- xsvi_active_video_o <= demux_dout(11);
-- fsync <= demux_dout(10);
xsvi_vsync_o <= syncgen_vsync;
xsvi_hsync_o <= syncgen_hsync;
xsvi_vblank_o <= syncgen_vblank;
xsvi_hblank_o <= syncgen_hblank;
xsvi_active_video_o <= syncgen_de;
fsync <= framestart2_regen;
xsvi_video_data_o <= demux_dout(9 downto 2) & demux_dout(9 downto 2) & demux_dout(9 downto 2);
end if;
end process;
end generate XSVI_24BIT_GEN;
end generate DEMUX_GEN;
DIRECT_OUTPUT_GEN : if (C_XSVI_DIRECT_OUTPUT = 1) generate
--
-- XSVI Interface
--
XSVI_40BIT_GEN : if (C_XSVI_DATA_WIDTH = 40) generate
xsvi_40bit_oregs_l : process (clk)
begin
if rising_edge( clk ) then
xsvi_vsync_o <= BLC_VIDEO_SYNC(4);
xsvi_hsync_o <= BLC_VIDEO_SYNC(3);
xsvi_vblank_o <= BLC_VIDEO_SYNC(2);
xsvi_hblank_o <= BLC_VIDEO_SYNC(1);
xsvi_active_video_o <= BLC_VIDEO_SYNC(0);
fsync <= framestart;
xsvi_video_data_o <= BLC_PAR_DATA_OUT(39 downto 30)
& BLC_PAR_DATA_OUT(29 downto 20)
& BLC_PAR_DATA_OUT(19 downto 10)
& BLC_PAR_DATA_OUT( 9 downto 0)
;
end if;
end process;
end generate XSVI_40BIT_GEN;
XSVI_64BIT_GEN : if (C_XSVI_DATA_WIDTH = 64) generate
xsvi_64bit_oregs_l : process (clk)
begin
if rising_edge( clk ) then
xsvi_vsync_o <= BLC_VIDEO_SYNC(4);
xsvi_hsync_o <= BLC_VIDEO_SYNC(3);
xsvi_vblank_o <= BLC_VIDEO_SYNC(2);
xsvi_hblank_o <= BLC_VIDEO_SYNC(1);
xsvi_active_video_o <= BLC_VIDEO_SYNC(0);
fsync <= framestart;
xsvi_video_data_o <= "000000" & BLC_PAR_DATA_OUT(39 downto 30)
& "000000" & BLC_PAR_DATA_OUT(29 downto 20)
& "000000" & BLC_PAR_DATA_OUT(19 downto 10)
& "000000" & BLC_PAR_DATA_OUT( 9 downto 0)
;
end if;
end process;
end generate XSVI_64BIT_GEN;
end generate DIRECT_OUTPUT_GEN;
--
-- I/O registers & buffers
--
clk_n <= not clk;
oe_n <= not oe;
net0 <= '0';
net1 <= '1';
--io_oregs1_l : process (clk)
--begin
-- if Rising_Edge(clk) then
vita_reset_n_o <= not host_vita_reset;
-- vita_trigger_o <= (others => '0');
--
vita_reset_n_t <= oe_n;
vita_trigger_t <= (others => oe_n);
-- end if;
--end process;
--io_oregs2_l : process (host_spi_clk)
--begin
-- if Rising_Edge(host_spi_clk) then
vita_spi_sclk_t <= oe_n;
vita_spi_ssel_n_t <= oe_n;
vita_spi_mosi_t <= oe_n;
-- end if;
--end process;
S6_GEN : if (C_FAMILY = "spartan6") generate
ODDR_vita_clk_pll_o : ODDR2
generic map (
DDR_ALIGNMENT => "C0", -- "NONE", "C0" or "C1"
INIT => '1', -- Sets initial state of Q
SRTYPE => "ASYNC") -- Reset type
port map (
Q => vita_clk_pll_o,
C0 => clk,
C1 => clk_n,
CE => net1,
D0 => net0,
D1 => net1,
R => net0,
S => net0);
ODDR_vita_clk_pll_t : ODDR2
generic map (
DDR_ALIGNMENT => "C0", -- "NONE", "C0" or "C1"
INIT => '1', -- Sets initial state of Q
SRTYPE => "ASYNC") -- Reset type
port map (
Q => vita_clk_pll_t,
C0 => clk,
C1 => clk_n,
CE => net1,
D0 => oe_n,
D1 => oe_n,
R => net0,
S => net0);
end generate S6_GEN;
V6_GEN : if (C_FAMILY = "virtex6" or C_FAMILY = "kintex7" or C_FAMILY = "zynq" or C_FAMILY = "artix7" or C_FAMILY = "virtex7") generate
ODDR_vita_clk_pll_o : ODDR
generic map (
DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
INIT => '1', -- Sets initial state of Q
SRTYPE => "ASYNC") -- Reset type
port map (
Q => vita_clk_pll_o,
C => clk,
CE => net1,
D1 => net0,
D2 => net1,
R => net0,
S => net0);
ODDR_vita_clk_pll_t : ODDR
generic map (
DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
INIT => '1', -- Sets initial state of Q
SRTYPE => "ASYNC") -- Reset type
port map (
Q => vita_clk_pll_t,
C => clk,
CE => net1,
D1 => oe_n,
D2 => oe_n,
R => net0,
S => net0);
end generate V6_GEN;
--
-- Tri-stateable outputs
-- Can be used to disable outputs to FMC connector
-- until FMC module is correctly identified.
--
OBUFT_vita_reset_n : OBUFT
port map (
O => io_vita_reset_n,
I => vita_reset_n_o,
T => vita_reset_n_t
);
IO1: for I in 0 to 2 generate
OBUFT_vita_trigger : OBUFT
port map (
O => io_vita_trigger(I),
I => vita_trigger_o(I),
T => vita_trigger_t(I)
);
end generate IO1;
OBUFT_vita_clk_pll : OBUFT
port map (
O => io_vita_clk_pll,
I => vita_clk_pll_o,
T => vita_clk_pll_t
);
OBUFT_vita_spi_sclk : OBUFT
port map (
O => io_vita_spi_sclk,
I => vita_spi_sclk_o,
T => vita_spi_sclk_t
);
OBUFT_vita_spi_ssel_n : OBUFT
port map (
O => io_vita_spi_ssel_n,
I => vita_spi_ssel_n_o,
T => vita_spi_ssel_n_t
);
OBUFT_vita_spi_mosi : OBUFT
port map (
O => io_vita_spi_mosi,
I => vita_spi_mosi_o,
T => vita_spi_mosi_t
);
--
-- Debug Ports
-- Can be used to connect to ChipScope for debugging.
-- Having a port makes these signals accessible for debug via EDK.
--
debug_spi_l : process (host_spi_clk)
begin
if Rising_Edge(host_spi_clk) then
debug_spi_o(15 downto 0) <= host_spi_timing;
debug_spi_o( 16) <= vita_spi_sclk_o;
debug_spi_o( 17) <= vita_spi_ssel_n_o;
debug_spi_o( 18) <= vita_spi_mosi_o;
debug_spi_o( 19) <= io_vita_spi_miso;
debug_spi_o( 20) <= host_vita_reset;
debug_spi_o( 21) <= host_spi_txfifo_wen;
debug_spi_o( 22) <= host_spi_rxfifo_ren;
debug_spi_o( 23) <= '0';
debug_spi_o( 24) <= '0';
debug_spi_o( 25) <= host_spi_reset;
debug_spi_o( 26) <= vita_spi_status_busy;
debug_spi_o( 27) <= vita_spi_status_error;
debug_spi_o( 28) <= vita_spi_rxfifo_wen;
debug_spi_o( 29) <= vita_spi_txfifo_ren;
debug_spi_o( 30) <= vita_spi_rxfifo_full;
debug_spi_o( 31) <= vita_spi_txfifo_empty;
debug_spi_o(63 downto 32) <= vita_spi_rxfifo_din;
debug_spi_o(95 downto 64) <= vita_spi_txfifo_dout;
end if;
end process;
debug_iserdes_l : process (clk)
begin
if Rising_Edge(clk) then
debug_iserdes_o( 49 downto 0) <= FIFO_DATAOUT;
debug_iserdes_o( 50) <= FIFO_EMPTY;
debug_iserdes_o( 51) <= host_iserdes_fifo_enable;
debug_iserdes_o( 52) <= host_iserdes_auto_align;
debug_iserdes_o( 53) <= host_iserdes_align_start;
debug_iserdes_o( 54) <= host_iserdes_reset;
debug_iserdes_o( 59 downto 55) <= EDGE_DETECT;
debug_iserdes_o( 64 downto 60) <= TRAINING_DETECT;
debug_iserdes_o( 69 downto 65) <= STABLE_DETECT;
debug_iserdes_o( 74 downto 70) <= FIRST_EDGE_FOUND;
debug_iserdes_o( 79 downto 75) <= SECOND_EDGE_FOUND;
debug_iserdes_o( 89 downto 80) <= host_iserdes_training;
debug_iserdes_o( 99 downto 90) <= host_iserdes_manual_tap;
debug_iserdes_o(115 downto 100) <= CLK_STATUS;
debug_iserdes_o( 116) <= CLK_RDY;
debug_iserdes_o( 117) <= ALIGN_BUSY;
debug_iserdes_o( 118) <= ALIGNED;
debug_iserdes_o( 119) <= '0';
debug_iserdes_o(124 downto 120) <= WORD_ALIGN;
debug_iserdes_o(129 downto 125) <= TIMEOUTONACK;
debug_iserdes_o(179 downto 130) <= TAP_SETTING;
debug_iserdes_o(229 downto 180) <= WINDOW_WIDTH;
--debug_iserdes_o(309 downto 230) <= NROF_RETRIES;
end if;
end process;
debug_decoder_l : process (clk)
begin
if Rising_Edge(clk) then
debug_decoder_o( 49 downto 0) <= FIFO_DATAOUT;
debug_decoder_o( 50) <= FIFO_EMPTY;
debug_decoder_o( 51) <= FIFO_RDEN;
debug_decoder_o( 52) <= host_iserdes_fifo_enable;
debug_decoder_o( 53) <= host_decoder_enable;
debug_decoder_o( 54) <= framestart;
debug_decoder_o( 55) <= windowstart;
debug_decoder_o( 56) <= windowend;
debug_decoder_o( 57) <= linestart;
debug_decoder_o( 58) <= lineend;
debug_decoder_o( 59) <= blacklinestart;
debug_decoder_o( 60) <= blacklineend;
debug_decoder_o( 61) <= imagelinestart;
debug_decoder_o( 62) <= imagelineend;
debug_decoder_o( 63) <= validcrc;
debug_decoder_o( 67 downto 64) <= CRC_STATUS(NROF_CONN - 2 downto 0);
debug_decoder_o( 77 downto 68) <= SYNC_PAR_SYNCOUT;
debug_decoder_o(117 downto 78) <= SYNC_PAR_DATAOUT;
debug_decoder_o( 118) <= SYNC_PAR_DATA_IMGVALID;
debug_decoder_o( 119) <= SYNC_PAR_DATA_BLACKVALID;
debug_decoder_o( 120) <= validcrc;
debug_decoder_o( 121) <= SYNC_PAR_DATA_LINE;
debug_decoder_o( 122) <= SYNC_PAR_DATA_FRAME;
debug_decoder_o( 123) <= SYNC_START_KERNEL;
debug_decoder_o( 124) <= SYNC_KERNEL_ODD_EVEN;
-- debug_decoder_o(134 downto 125) <= CRC_PAR_SYNC_OUT;
-- debug_decoder_o(174 downto 135) <= CRC_PAR_DATA_OUT;
-- debug_decoder_o( 175) <= CRC_PAR_DATA_IMGVALID_OUT;
-- debug_decoder_o( 176) <= CRC_PAR_DATA_BLACKVALID_OUT;
-- debug_decoder_o( 177) <= CRC_PAR_DATA_CRCVALID_OUT;
-- debug_decoder_o( 178) <= CRC_PAR_DATA_LINE_OUT;
-- debug_decoder_o( 179) <= CRC_PAR_DATA_FRAME_OUT;
-- debug_decoder_o( 180) <= CRC_START_KERNEL;
-- debug_decoder_o( 181) <= CRC_KERNEL_ODD_EVEN;
-- debug_decoder_o(134 downto 125) <= (others => '0');
debug_decoder_o( 125) <= CRC_PAR_DATA_FRAME_OUT;
debug_decoder_o( 126) <= CRC_PAR_DATA_LINE_OUT;
debug_decoder_o( 127) <= CRC_PAR_DATA_CRCVALID_OUT;
debug_decoder_o( 128) <= CRC_PAR_DATA_BLACKVALID_OUT;
debug_decoder_o( 129) <= CRC_PAR_DATA_IMGVALID_OUT;
debug_decoder_o( 130) <= syncgen_de;
debug_decoder_o( 131) <= syncgen_hblank;
debug_decoder_o( 132) <= syncgen_vblank;
debug_decoder_o( 133) <= syncgen_hsync;
debug_decoder_o( 134) <= syncgen_vsync;
debug_decoder_o(174 downto 135) <= REMAP_PAR_DATA_OUT;
debug_decoder_o( 175) <= REMAP_PAR_DATA_VALID_OUT;
debug_decoder_o( 176) <= REMAP_PAR_DATA_LINE_OUT;
debug_decoder_o( 177) <= REMAP_PAR_DATA_FRAME_OUT;
debug_decoder_o( 178) <= REMAP_PAR_DATA_WINDOW_OUT;
debug_decoder_o( 179) <= host_remapper_write_cfg(0);
debug_decoder_o( 180) <= host_remapper_write_cfg(1);
debug_decoder_o( 181) <= host_remapper_write_cfg(2);
debug_decoder_o( 182) <= REMAP_VIDEO_SYNC(3); -- hsync
debug_decoder_o( 183) <= REMAP_VIDEO_SYNC(4); -- vsync
debug_decoder_o( 184) <= REMAP_VIDEO_SYNC(0); -- de
debug_decoder_o( 185) <= REMAP_VIDEO_SYNC(1); -- hblank
debug_decoder_o( 186) <= REMAP_VIDEO_SYNC(2); -- vblank
end if;
end process;
debug_crc_l : process (clk)
begin
if Rising_Edge(clk) then
debug_crc_o( 3 downto 0) <= CRC_STATUS;
debug_crc_o(87 downto 4) <= (others => '0'); --CRC_DEBUG;
end if;
end process;
debug_video_l : process (clk4x)
begin
if Rising_Edge(clk4x) then
debug_video_o(10 downto 0) <= demux_dout(10 downto 0);
debug_video_o( 11) <= syncgen_de;
debug_video_o( 12) <= syncgen_hblank;
debug_video_o( 13) <= syncgen_vblank;
debug_video_o( 14) <= syncgen_hsync;
debug_video_o( 15) <= syncgen_vsync;
debug_video_o( 16) <= demux_empty;
debug_video_o( 17) <= demux_full;
debug_video_o( 18) <= syncgen_de; --syncgen_pixelrequest;
debug_video_o( 19) <= framestart2_regen;
debug_video_o( 20) <= framestart2;
debug_video_o( 21) <= framestart;
debug_video_o( 22) <= BLC_VIDEO_SYNC(0);
debug_video_o( 23) <= CRC_PAR_DATA_IMGVALID_OUT;
debug_video_o( 24) <= CRC_PAR_DATA_BLACKVALID_OUT;
debug_video_o( 25) <= CRC_PAR_DATA_CRCVALID_OUT;
debug_video_o( 26) <= CRC_PAR_DATA_LINE_OUT;
debug_video_o( 27) <= CRC_PAR_DATA_FRAME_OUT;
debug_video_o( 28) <= CRC_START_KERNEL;
debug_video_o( 29) <= CRC_KERNEL_ODD_EVEN;
debug_video_o( 30) <= clk;
debug_video_o( 31) <= '0';
end if;
end process;
debug_triggen_l : process (clk)
begin
if Rising_Edge(clk) then
debug_triggen_o( 2 downto 0) <= host_triggen_enable;
debug_triggen_o( 3) <= host_triggen_sync2readout(0);
debug_triggen_o( 4) <= host_triggen_readouttrigger;
debug_triggen_o( 5) <= trigger1;
debug_triggen_o( 6) <= '0'; --readouttrigger_d2;
debug_triggen_o( 9 downto 7) <= vita_trigger_o;
end if;
end process;
end rtl;
|
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-16.08:47:50)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY ewf_random_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2: IN unsigned(0 TO 3);
output1, output2, output3, output4, output5: OUT unsigned(0 TO 4));
END ewf_random_entity;
ARCHITECTURE ewf_random_description OF ewf_random_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register7: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register8: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 + 1;
register2 := input2 + 2;
WHEN "00000010" =>
register3 := register2 + 4;
WHEN "00000011" =>
register4 := register3 + 6;
WHEN "00000100" =>
register4 := register1 + register4;
WHEN "00000101" =>
register5 := register4 * 8;
register6 := register4 * 10;
WHEN "00000110" =>
register5 := register3 + register5;
WHEN "00000111" =>
register4 := register4 + register5;
register6 := register1 + register6;
register3 := register3 + register5;
WHEN "00001000" =>
register1 := register1 + register6;
register3 := register3 * 12;
WHEN "00001001" =>
register1 := register1 * 14;
WHEN "00001010" =>
register1 := register1 + 16;
register3 := register2 + register3;
WHEN "00001011" =>
register7 := register6 + register1;
register2 := register2 + register3;
WHEN "00001100" =>
register7 := register7 + 18;
register5 := register5 + register3;
WHEN "00001101" =>
register8 := register7 * 20;
output1 <= register6 + register4;
WHEN "00001110" =>
register4 := register8 + 23;
register6 := register1 + 25;
register2 := register2 * 27;
WHEN "00001111" =>
register6 := register6 * 29;
output2 <= register7 + register4;
register4 := register5 + 32;
register2 := register2 + 34;
WHEN "00010000" =>
output3 <= register3 + register2;
output4 <= register1 + register6;
register1 := register4 * 38;
WHEN "00010001" =>
register1 := register1 + 40;
WHEN "00010010" =>
output5 <= register4 + register1;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END ewf_random_description; |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_alu IS
END tb_alu;
ARCHITECTURE tb OF tb_alu IS
constant data_width : integer := 8;
constant sel_width : integer := 4;
COMPONENT alu
PORT (
A : IN std_logic_vector (data_width - 1 DOWNTO 0);
B : IN std_logic_vector (data_width - 1 DOWNTO 0);
C_IN : IN std_logic;
Sel : IN std_logic_vector (sel_width - 1 DOWNTO 0);
SUM : OUT std_logic_vector (data_width - 1 DOWNTO 0);
C_FLAG : OUT std_logic;
Z_FLAG : OUT std_logic
);
END COMPONENT;
SIGNAL A_tb : std_logic_vector (data_width - 1 DOWNTO 0);
SIGNAL B_tb : std_logic_vector (data_width - 1 DOWNTO 0);
SIGNAL C_IN_tb : std_logic;
SIGNAL Sel_tb : std_logic_vector (sel_width - 1 DOWNTO 0);
SIGNAL SUM_tb : std_logic_vector (data_width - 1 DOWNTO 0);
SIGNAL C_FLAG_tb : std_logic;
SIGNAL Z_FLAG_tb : std_logic;
CONSTANT TbPeriod : TIME := 1000 ns; -- EDIT Put right period here
SIGNAL TbClock : std_logic := '0';
SIGNAL TbSimEnded : std_logic := '0';
BEGIN
dut : alu
PORT MAP(
A => A_tb,
B => B_tb,
C_IN => C_IN_tb,
Sel => Sel_tb,
SUM => SUM_tb,
C_FLAG => C_FLAG_tb,
Z_FLAG => Z_FLAG_tb
);
-- Clock generation
TbClock <= NOT TbClock AFTER TbPeriod/2 WHEN TbSimEnded /= '1' ELSE '0';
-- EDIT: Replace YOURCLOCKSIGNAL below by the name of your clock as I haven't guessed it
-- YOURCLOCKSIGNAL <= TbClock;
stimuli : PROCESS
BEGIN
-- EDIT Adapt initialization as needed
A_tb <= (OTHERS => '0');
B_tb <= (OTHERS => '0');
C_IN_tb <= '0';
Sel_tb <= (OTHERS => '0');
--Test Case #1: add
WAIT FOR 10ns;
Sel_tb <= x"0";
A_tb <= x"AA";
B_tb <= x"AA";
C_IN_tb <= '0';
WAIT FOR 10ns;
--Test Case #2: addc
WAIT FOR 10ns;
Sel_tb <= x"1";
A_tb <= x"C8";
B_tb <= x"37";
C_IN_tb <= '1';
WAIT FOR 10ns;
--Test Case #3: sub
WAIT FOR 10ns;
Sel_tb <= x"2";
A_tb <= x"C8";
B_tb <= x"64";
C_IN_tb <= '0';
WAIT FOR 10ns;
--Test Case #4: subc
WAIT FOR 10ns;
Sel_tb <= x"3";
A_tb <= x"C8";
B_tb <= x"C8";
C_IN_tb <= '1';
WAIT FOR 10ns;
--Test Case #5: COMP
WAIT FOR 10ns;
Sel_tb <= x"4";
A_tb <= x"AA";
B_tb <= x"FF";
C_IN_tb <= '0';
WAIT FOR 10ns;
--Test Case #6: COMP
WAIT FOR 10ns;
Sel_tb <= x"4";
A_tb <= x"AA";
B_tb <= x"AA";
C_IN_tb <= '0';
WAIT FOR 10ns;
--Test Case #7: AND
WAIT FOR 10ns;
Sel_tb <= x"5";
A_tb <= x"AA";
B_tb <= x"CC";
C_IN_tb <= '0';
WAIT FOR 10ns;
--Test Case #7: OR
WAIT FOR 10ns;
Sel_tb <= x"6";
A_tb <= x"AA";
B_tb <= x"AA";
C_IN_tb <= '0';
WAIT FOR 10ns;
--Test Case #8: XOR
WAIT FOR 10ns;
Sel_tb <= x"7";
A_tb <= x"AA";
B_tb <= x"AA";
C_IN_tb <= '0';
WAIT FOR 10ns;
--Test Case #9: TEST
WAIT FOR 10ns;
Sel_tb <= x"8";
A_tb <= x"AA";
B_tb <= x"55";
C_IN_tb <= '0';
WAIT FOR 10ns;
--Test Case #10: LSL
WAIT FOR 10ns;
Sel_tb <= x"9";
A_tb <= x"01";
B_tb <= x"12";
C_IN_tb <= '1';
WAIT FOR 10ns;
--Test Case #11: LSR
WAIT FOR 10ns;
Sel_tb <= x"A";
A_tb <= x"81";
B_tb <= x"33";
C_IN_tb <= '0';
WAIT FOR 10ns;
--Test Case #12: ROL
WAIT FOR 10ns;
Sel_tb <= x"B";
A_tb <= x"01";
B_tb <= x"AB";
C_IN_tb <= '1';
WAIT FOR 10ns;
--Test Case #13: ROR
WAIT FOR 10ns;
Sel_tb <= x"C";
A_tb <= x"81";
B_tb <= x"3C";
C_IN_tb <= '0';
WAIT FOR 10ns;
--Test Case #14: ASR
WAIT FOR 10ns;
Sel_tb <= x"D";
A_tb <= x"81";
B_tb <= x"81";
C_IN_tb <= '0';
WAIT FOR 10ns;
--Test Case #15: MOV
WAIT FOR 10ns;
Sel_tb <= x"E";
A_tb <= x"50";
B_tb <= x"30";
C_IN_tb <= '0';
WAIT FOR 10ns;
WAIT FOR 100 * TbPeriod;
-- Stop the clock and hence terminate the simulation
TbSimEnded <= '1';
WAIT;
END PROCESS;
END tb;
|
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
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`protect key_block
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`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4016)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4016)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect key_block
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`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
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`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4016)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4016)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4016)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
|
------------------------------------------------------------------------------
-- Context multiplexer (behavioral)
--
-- Project :
-- File : $URL: svn+ssh://[email protected]/home/plessl/SVN/simzippy/trunk/vhdl/contextmux.vhd $
-- Authors : Rolf Enzler <[email protected]>
-- Christian Plessl <[email protected]>
-- Company : Swiss Federal Institute of Technology (ETH) Zurich
-- Created : 2003/01/15
-- $Id: contextmux.vhd 241 2005-04-07 08:50:55Z plessl $
------------------------------------------------------------------------------
-- The context multiplexer is used to select one particular
-- configuration (context) from the configuration memory.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.ConfigPkg.all;
use work.AuxPkg.all;
entity ContextMux is
generic (
NINP : integer); -- no. of inputs
port (
SelxSI : in std_logic_vector(log2(NINP)-1 downto 0);
InpxI : in contextArray;
OutxDO : out contextType);
end ContextMux;
architecture behav of ContextMux is
begin -- behav
OutxDO <= InpxI(to_integer(unsigned(SelxSI)));
end behav;
|
----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Virtual simple input buffer.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity ibuf_tech is
generic
(
generic_tech : integer := 0
);
port (
o : out std_logic;
i : in std_logic
);
end;
architecture rtl of ibuf_tech is
component ibuf_inferred is
port (
o : out std_logic;
i : in std_logic
);
end component;
component ibuf_micron180 is
port (
o : out std_logic;
i : in std_logic
);
end component;
begin
m180 : if generic_tech = micron180 generate
bufm : ibuf_micron180 port map
(
o => o,
i => i
);
end generate;
inf0 : if generic_tech /= micron180 generate
bufinf : ibuf_inferred port map
(
o => o,
i => i
);
end generate;
end;
|
----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Virtual simple input buffer.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
entity ibuf_tech is
generic
(
generic_tech : integer := 0
);
port (
o : out std_logic;
i : in std_logic
);
end;
architecture rtl of ibuf_tech is
component ibuf_inferred is
port (
o : out std_logic;
i : in std_logic
);
end component;
component ibuf_micron180 is
port (
o : out std_logic;
i : in std_logic
);
end component;
begin
m180 : if generic_tech = micron180 generate
bufm : ibuf_micron180 port map
(
o => o,
i => i
);
end generate;
inf0 : if generic_tech /= micron180 generate
bufinf : ibuf_inferred port map
(
o => o,
i => i
);
end generate;
end;
|
architecture ARCH of ENTITY is
begin
-- Component instantiation without component keyword.
U_INST1 : INST1
generic map (
GEN_1 => c_gen_1,
GEN_2 => c_gen_2,
GEN_3 => c_gen_3
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST1 : INST1
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST1 : INST1
generic map (
GEN_1 => c_gen_1,
GEN_2 => c_gen_2,
GEN_3 => c_gen_3
);
U_INST1 : INST1;
-- Component instantiation with component keyword.
U_INST1 : component INST1
generic map (
GEN_1 => c_gen_1,
GEN_2 => c_gen_2,
GEN_3 => c_gen_3
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST1 : component INST1
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST1 : component INST1
generic map (
GEN_1 => c_gen_1,
GEN_2 => c_gen_2,
GEN_3 => c_gen_3
);
U_INST1 : component INST1;
-- entity without architecture identifier
U_INST1 : entity INST1
generic map (
GEN_1 => c_gen_1,
GEN_2 => c_gen_2,
GEN_3 => c_gen_3
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST1 : entity INST1
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST1 : entity INST1
generic map (
GEN_1 => c_gen_1,
GEN_2 => c_gen_2,
GEN_3 => c_gen_3
);
U_INST1 : entity INST1;
-- entity without architecture identifier and with library identifier
U_INST1 : entity my_lib.INST1
generic map (
GEN_1 => c_gen_1,
GEN_2 => c_gen_2,
GEN_3 => c_gen_3
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST1 : entity my_lib.INST1
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST1 : entity my_lib.INST1
generic map (
GEN_1 => c_gen_1,
GEN_2 => c_gen_2,
GEN_3 => c_gen_3
);
U_INST1 : entity my_lib.INST1;
-- entity with architecture identifier
U_INST1 : entity INST1 (rtl)
generic map (
GEN_1 => c_gen_1,
GEN_2 => c_gen_2,
GEN_3 => c_gen_3
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST1 : entity INST1 (rtl)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST1 : entity INST1 (rtl)
generic map (
GEN_1 => c_gen_1,
GEN_2 => c_gen_2,
GEN_3 => c_gen_3
);
U_INST1 : entity INST1 (rtl);
-- configuration
U_INST1 : configuration INST1
generic map (
GEN_1 => c_gen_1,
GEN_2 => c_gen_2,
GEN_3 => c_gen_3
)
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST1 : configuration INST1
port map (
PORT_1 => w_port_1,
PORT_2 => w_port_2,
PORT_3 => w_port_3
);
U_INST1 : configuration INST1
generic map (
GEN_1 => c_gen_1,
GEN_2 => c_gen_2,
GEN_3 => c_gen_3
);
U_INST1 : configuration INST1;
end architecture ARCH;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_cmd_status.vhd
--
-- Description:
-- This file implements the DataMover Command and Status interfaces.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_sg_v4_1_2;
Use axi_sg_v4_1_2.axi_sg_fifo;
-------------------------------------------------------------------------------
entity axi_sg_cmd_status is
generic (
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Indictes the width of the DataMover Address bus
C_INCLUDE_STSFIFO : Integer range 0 to 1 := 1;
-- Indicates if a Stus FIFO is to be included or omitted
-- 0 = Omit
-- 1 = Include
C_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Sets the depth of the Command and Status FIFOs
C_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Indicates if the Command and Status Stream Channels are clocked with
-- a different clock than the Main dataMover Clock
-- 0 = Same Clock
-- 1 = Different clocks
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command
C_STS_WIDTH : Integer := 8;
-- Sets the width of the output status
C_FAMILY : string := "virtex7"
-- Sets the target FPGA family
);
port (
-- Clock inputs ----------------------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
secondary_awclk : in std_logic; --
-- Clock used for the Command and Status User Interface --
-- when the User Command and Status interface is Async --
-- to the MMap interface. Async mode is set by the assigned --
-- value to C_STSCMD_IS_ASYNC = 1. --
--------------------------------------------------------------------
-- Reset inputs ----------------------------------------------------
user_reset : in std_logic; --
-- Reset used for the User Stream interface logic --
--
internal_reset : in std_logic; --
-- Reset used for the internal master interface logic --
--------------------------------------------------------------------
-- User Command Stream Ports (AXI Stream) -------------------------------
cmd_wvalid : in std_logic; --
cmd_wready : out std_logic; --
cmd_wdata : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
cache_data : in std_logic_vector(7 downto 0); --
-------------------------------------------------------------------------
-- User Status Stream Ports (AXI Stream) ------------------------------------
sts_wvalid : out std_logic; --
sts_wready : in std_logic; --
sts_wdata : out std_logic_vector(C_STS_WIDTH-1 downto 0); --
sts_wstrb : out std_logic_vector((C_STS_WIDTH/8)-1 downto 0); --
sts_wlast : out std_logic; --
-----------------------------------------------------------------------------
-- Internal Command Out Interface -----------------------------------------------
cmd2mstr_command : Out std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
cache2mstr_command : Out std_logic_vector(7 downto 0); --
-- The cache value available from the FIFO/Register --
--
mst2cmd_cmd_valid : Out std_logic; --
-- Handshake bit indicating the Command FIFO/Register has at least 1 valid --
-- command entry --
--
cmd2mstr_cmd_ready : in std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
---------------------------------------------------------------------------------
-- Internal Status In Interface -----------------------------------------------------
mstr2stat_status : in std_logic_vector(C_STS_WIDTH-1 downto 0); --
-- The input for writing the status value to the Status FIFO/Register --
--
stat2mstr_status_ready : Out std_logic; --
-- Handshake bit indicating that the Status FIFO/Register is ready for transfer --
--
mst2stst_status_valid : In std_logic --
-- Handshake bit for writing the Status value into the Status FIFO/Register --
--------------------------------------------------------------------------------------
);
end entity axi_sg_cmd_status;
architecture implementation of axi_sg_cmd_status is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_fifo_prim_type
--
-- Function Description:
-- Returns the fifo primitiver type to use for the given input
-- conditions.
--
-- 0 = Not used or allowed here
-- 1 = BRAM Primitives (Block Memory)
-- 2 = Distributed memory
--
-------------------------------------------------------------------
function get_fifo_prim_type (is_async : integer;
depth : integer) return integer is
Variable var_temp_prim_type : Integer := 1;
begin
-- coverage off
if (is_async = 1) then -- Async FIFOs always use Blk Mem (BRAM)
var_temp_prim_type := 1;
elsif (depth <= 64) then -- (use srls or distrubuted)
var_temp_prim_type := 2;
else -- depth is too big for SRLs so use Blk Memory (BRAM)
var_temp_prim_type := 1;
end if;
-- coverage on
Return (var_temp_prim_type);
end function get_fifo_prim_type;
-- Constants
Constant REGISTER_TYPE : integer := 0;
Constant BRAM_TYPE : integer := 1;
--Constant SRL_TYPE : integer := 2;
--Constant FIFO_PRIM_TYPE : integer := SRL_TYPE;
Constant FIFO_PRIM_TYPE : integer := get_fifo_prim_type(C_STSCMD_IS_ASYNC,
C_STSCMD_FIFO_DEPTH);
-- Signals
signal sig_cmd_fifo_wr_clk : std_logic := '0';
signal sig_cmd_fifo_wr_rst : std_logic := '0';
signal sig_cmd_fifo_rd_clk : std_logic := '0';
signal sig_cmd_fifo_rd_rst : std_logic := '0';
signal sig_sts_fifo_wr_clk : std_logic := '0';
signal sig_sts_fifo_wr_rst : std_logic := '0';
signal sig_sts_fifo_rd_clk : std_logic := '0';
signal sig_sts_fifo_rd_rst : std_logic := '0';
signal sig_reset_mstr : std_logic := '0';
signal sig_reset_user : std_logic := '0';
begin --(architecture implementation)
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_SYNC_RESET
--
-- If Generate Description:
-- This IfGen assigns the clock and reset signals for the
-- synchronous User interface case
--
------------------------------------------------------------
GEN_SYNC_RESET : if (C_STSCMD_IS_ASYNC = 0) generate
begin
sig_reset_mstr <= internal_reset ;
sig_reset_user <= internal_reset ;
sig_cmd_fifo_wr_clk <= primary_aclk ;
sig_cmd_fifo_wr_rst <= sig_reset_user;
sig_cmd_fifo_rd_clk <= primary_aclk ;
sig_cmd_fifo_rd_rst <= sig_reset_mstr;
sig_sts_fifo_wr_clk <= primary_aclk ;
sig_sts_fifo_wr_rst <= sig_reset_mstr;
sig_sts_fifo_rd_clk <= primary_aclk ;
sig_sts_fifo_rd_rst <= sig_reset_user;
end generate GEN_SYNC_RESET;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ASYNC_RESET
--
-- If Generate Description:
-- This IfGen assigns the clock and reset signals for the
-- Asynchronous User interface case
--
------------------------------------------------------------
GEN_ASYNC_RESET : if (C_STSCMD_IS_ASYNC = 1) generate
begin
sig_reset_mstr <= internal_reset ;
sig_reset_user <= user_reset ;
sig_cmd_fifo_wr_clk <= secondary_awclk;
sig_cmd_fifo_wr_rst <= sig_reset_user ;
sig_cmd_fifo_rd_clk <= primary_aclk ;
sig_cmd_fifo_rd_rst <= sig_reset_mstr ;
sig_sts_fifo_wr_clk <= primary_aclk ;
sig_sts_fifo_wr_rst <= sig_reset_mstr ;
sig_sts_fifo_rd_clk <= secondary_awclk;
sig_sts_fifo_rd_rst <= sig_reset_user ;
end generate GEN_ASYNC_RESET;
------------------------------------------------------------
-- Instance: I_CMD_FIFO
--
-- Description:
-- Instance for the Command FIFO
-- The User Interface is the Write Side
-- The Internal Interface is the Read side
--
------------------------------------------------------------
I_CMD_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
generic map (
C_DWIDTH => C_CMD_WIDTH ,
C_DEPTH => C_STSCMD_FIFO_DEPTH ,
C_IS_ASYNC => C_STSCMD_IS_ASYNC ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => sig_cmd_fifo_wr_rst ,
fifo_wr_clk => sig_cmd_fifo_wr_clk ,
-- Write Side
fifo_wr_tvalid => cmd_wvalid ,
fifo_wr_tready => cmd_wready ,
fifo_wr_tdata => cmd_wdata ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => sig_cmd_fifo_rd_rst ,
fifo_async_rd_clk => sig_cmd_fifo_rd_clk ,
-- Read Side
fifo_rd_tvalid => mst2cmd_cmd_valid ,
fifo_rd_tready => cmd2mstr_cmd_ready ,
fifo_rd_tdata => cmd2mstr_command ,
fifo_rd_empty => open
);
I_CACHE_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
generic map (
C_DWIDTH => 8 ,
C_DEPTH => C_STSCMD_FIFO_DEPTH ,
C_IS_ASYNC => C_STSCMD_IS_ASYNC ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => sig_cmd_fifo_wr_rst ,
fifo_wr_clk => sig_cmd_fifo_wr_clk ,
-- Write Side
fifo_wr_tvalid => cmd_wvalid ,
fifo_wr_tready => open ,--cmd_wready ,
fifo_wr_tdata => cache_data ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => sig_cmd_fifo_rd_rst ,
fifo_async_rd_clk => sig_cmd_fifo_rd_clk ,
-- Read Side
fifo_rd_tvalid => open ,--mst2cmd_cmd_valid ,
fifo_rd_tready => cmd2mstr_cmd_ready ,
fifo_rd_tdata => cache2mstr_command ,
fifo_rd_empty => open
);
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_STATUS_FIFO
--
-- If Generate Description:
-- Instantiates a Status FIFO
--
--
------------------------------------------------------------
GEN_INCLUDE_STATUS_FIFO : if (C_INCLUDE_STSFIFO = 1) generate
begin
-- Set constant outputs for Status Interface
sts_wstrb <= (others => '1');
sts_wlast <= '1';
------------------------------------------------------------
-- Instance: I_STS_FIFO
--
-- Description:
-- Instance for the Status FIFO
-- The Internal Interface is the Write Side
-- The User Interface is the Read side
--
------------------------------------------------------------
I_STS_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
generic map (
C_DWIDTH => C_STS_WIDTH ,
C_DEPTH => C_STSCMD_FIFO_DEPTH ,
C_IS_ASYNC => C_STSCMD_IS_ASYNC ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => sig_sts_fifo_wr_rst ,
fifo_wr_clk => sig_sts_fifo_wr_clk ,
-- Write Side
fifo_wr_tvalid => mst2stst_status_valid ,
fifo_wr_tready => stat2mstr_status_ready,
fifo_wr_tdata => mstr2stat_status ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => sig_sts_fifo_rd_rst ,
fifo_async_rd_clk => sig_sts_fifo_rd_clk ,
-- Read Side
fifo_rd_tvalid => sts_wvalid ,
fifo_rd_tready => sts_wready ,
fifo_rd_tdata => sts_wdata ,
fifo_rd_empty => open
);
end generate GEN_INCLUDE_STATUS_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_STATUS_FIFO
--
-- If Generate Description:
-- Omits the Status FIFO
--
--
------------------------------------------------------------
GEN_OMIT_STATUS_FIFO : if (C_INCLUDE_STSFIFO = 0) generate
begin
-- Status FIFO User interface housekeeping
sts_wvalid <= '0';
-- sts_wready -- ignored
sts_wdata <= (others => '0');
sts_wstrb <= (others => '0');
sts_wlast <= '0';
-- Status FIFO Internal interface housekeeping
stat2mstr_status_ready <= '1';
-- mstr2stat_status -- ignored
-- mst2stst_status_valid -- ignored
end generate GEN_OMIT_STATUS_FIFO;
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_cmd_status.vhd
--
-- Description:
-- This file implements the DataMover Command and Status interfaces.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_sg_v4_1_2;
Use axi_sg_v4_1_2.axi_sg_fifo;
-------------------------------------------------------------------------------
entity axi_sg_cmd_status is
generic (
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Indictes the width of the DataMover Address bus
C_INCLUDE_STSFIFO : Integer range 0 to 1 := 1;
-- Indicates if a Stus FIFO is to be included or omitted
-- 0 = Omit
-- 1 = Include
C_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Sets the depth of the Command and Status FIFOs
C_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Indicates if the Command and Status Stream Channels are clocked with
-- a different clock than the Main dataMover Clock
-- 0 = Same Clock
-- 1 = Different clocks
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command
C_STS_WIDTH : Integer := 8;
-- Sets the width of the output status
C_FAMILY : string := "virtex7"
-- Sets the target FPGA family
);
port (
-- Clock inputs ----------------------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
secondary_awclk : in std_logic; --
-- Clock used for the Command and Status User Interface --
-- when the User Command and Status interface is Async --
-- to the MMap interface. Async mode is set by the assigned --
-- value to C_STSCMD_IS_ASYNC = 1. --
--------------------------------------------------------------------
-- Reset inputs ----------------------------------------------------
user_reset : in std_logic; --
-- Reset used for the User Stream interface logic --
--
internal_reset : in std_logic; --
-- Reset used for the internal master interface logic --
--------------------------------------------------------------------
-- User Command Stream Ports (AXI Stream) -------------------------------
cmd_wvalid : in std_logic; --
cmd_wready : out std_logic; --
cmd_wdata : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
cache_data : in std_logic_vector(7 downto 0); --
-------------------------------------------------------------------------
-- User Status Stream Ports (AXI Stream) ------------------------------------
sts_wvalid : out std_logic; --
sts_wready : in std_logic; --
sts_wdata : out std_logic_vector(C_STS_WIDTH-1 downto 0); --
sts_wstrb : out std_logic_vector((C_STS_WIDTH/8)-1 downto 0); --
sts_wlast : out std_logic; --
-----------------------------------------------------------------------------
-- Internal Command Out Interface -----------------------------------------------
cmd2mstr_command : Out std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
cache2mstr_command : Out std_logic_vector(7 downto 0); --
-- The cache value available from the FIFO/Register --
--
mst2cmd_cmd_valid : Out std_logic; --
-- Handshake bit indicating the Command FIFO/Register has at least 1 valid --
-- command entry --
--
cmd2mstr_cmd_ready : in std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
---------------------------------------------------------------------------------
-- Internal Status In Interface -----------------------------------------------------
mstr2stat_status : in std_logic_vector(C_STS_WIDTH-1 downto 0); --
-- The input for writing the status value to the Status FIFO/Register --
--
stat2mstr_status_ready : Out std_logic; --
-- Handshake bit indicating that the Status FIFO/Register is ready for transfer --
--
mst2stst_status_valid : In std_logic --
-- Handshake bit for writing the Status value into the Status FIFO/Register --
--------------------------------------------------------------------------------------
);
end entity axi_sg_cmd_status;
architecture implementation of axi_sg_cmd_status is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_fifo_prim_type
--
-- Function Description:
-- Returns the fifo primitiver type to use for the given input
-- conditions.
--
-- 0 = Not used or allowed here
-- 1 = BRAM Primitives (Block Memory)
-- 2 = Distributed memory
--
-------------------------------------------------------------------
function get_fifo_prim_type (is_async : integer;
depth : integer) return integer is
Variable var_temp_prim_type : Integer := 1;
begin
-- coverage off
if (is_async = 1) then -- Async FIFOs always use Blk Mem (BRAM)
var_temp_prim_type := 1;
elsif (depth <= 64) then -- (use srls or distrubuted)
var_temp_prim_type := 2;
else -- depth is too big for SRLs so use Blk Memory (BRAM)
var_temp_prim_type := 1;
end if;
-- coverage on
Return (var_temp_prim_type);
end function get_fifo_prim_type;
-- Constants
Constant REGISTER_TYPE : integer := 0;
Constant BRAM_TYPE : integer := 1;
--Constant SRL_TYPE : integer := 2;
--Constant FIFO_PRIM_TYPE : integer := SRL_TYPE;
Constant FIFO_PRIM_TYPE : integer := get_fifo_prim_type(C_STSCMD_IS_ASYNC,
C_STSCMD_FIFO_DEPTH);
-- Signals
signal sig_cmd_fifo_wr_clk : std_logic := '0';
signal sig_cmd_fifo_wr_rst : std_logic := '0';
signal sig_cmd_fifo_rd_clk : std_logic := '0';
signal sig_cmd_fifo_rd_rst : std_logic := '0';
signal sig_sts_fifo_wr_clk : std_logic := '0';
signal sig_sts_fifo_wr_rst : std_logic := '0';
signal sig_sts_fifo_rd_clk : std_logic := '0';
signal sig_sts_fifo_rd_rst : std_logic := '0';
signal sig_reset_mstr : std_logic := '0';
signal sig_reset_user : std_logic := '0';
begin --(architecture implementation)
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_SYNC_RESET
--
-- If Generate Description:
-- This IfGen assigns the clock and reset signals for the
-- synchronous User interface case
--
------------------------------------------------------------
GEN_SYNC_RESET : if (C_STSCMD_IS_ASYNC = 0) generate
begin
sig_reset_mstr <= internal_reset ;
sig_reset_user <= internal_reset ;
sig_cmd_fifo_wr_clk <= primary_aclk ;
sig_cmd_fifo_wr_rst <= sig_reset_user;
sig_cmd_fifo_rd_clk <= primary_aclk ;
sig_cmd_fifo_rd_rst <= sig_reset_mstr;
sig_sts_fifo_wr_clk <= primary_aclk ;
sig_sts_fifo_wr_rst <= sig_reset_mstr;
sig_sts_fifo_rd_clk <= primary_aclk ;
sig_sts_fifo_rd_rst <= sig_reset_user;
end generate GEN_SYNC_RESET;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ASYNC_RESET
--
-- If Generate Description:
-- This IfGen assigns the clock and reset signals for the
-- Asynchronous User interface case
--
------------------------------------------------------------
GEN_ASYNC_RESET : if (C_STSCMD_IS_ASYNC = 1) generate
begin
sig_reset_mstr <= internal_reset ;
sig_reset_user <= user_reset ;
sig_cmd_fifo_wr_clk <= secondary_awclk;
sig_cmd_fifo_wr_rst <= sig_reset_user ;
sig_cmd_fifo_rd_clk <= primary_aclk ;
sig_cmd_fifo_rd_rst <= sig_reset_mstr ;
sig_sts_fifo_wr_clk <= primary_aclk ;
sig_sts_fifo_wr_rst <= sig_reset_mstr ;
sig_sts_fifo_rd_clk <= secondary_awclk;
sig_sts_fifo_rd_rst <= sig_reset_user ;
end generate GEN_ASYNC_RESET;
------------------------------------------------------------
-- Instance: I_CMD_FIFO
--
-- Description:
-- Instance for the Command FIFO
-- The User Interface is the Write Side
-- The Internal Interface is the Read side
--
------------------------------------------------------------
I_CMD_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
generic map (
C_DWIDTH => C_CMD_WIDTH ,
C_DEPTH => C_STSCMD_FIFO_DEPTH ,
C_IS_ASYNC => C_STSCMD_IS_ASYNC ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => sig_cmd_fifo_wr_rst ,
fifo_wr_clk => sig_cmd_fifo_wr_clk ,
-- Write Side
fifo_wr_tvalid => cmd_wvalid ,
fifo_wr_tready => cmd_wready ,
fifo_wr_tdata => cmd_wdata ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => sig_cmd_fifo_rd_rst ,
fifo_async_rd_clk => sig_cmd_fifo_rd_clk ,
-- Read Side
fifo_rd_tvalid => mst2cmd_cmd_valid ,
fifo_rd_tready => cmd2mstr_cmd_ready ,
fifo_rd_tdata => cmd2mstr_command ,
fifo_rd_empty => open
);
I_CACHE_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
generic map (
C_DWIDTH => 8 ,
C_DEPTH => C_STSCMD_FIFO_DEPTH ,
C_IS_ASYNC => C_STSCMD_IS_ASYNC ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => sig_cmd_fifo_wr_rst ,
fifo_wr_clk => sig_cmd_fifo_wr_clk ,
-- Write Side
fifo_wr_tvalid => cmd_wvalid ,
fifo_wr_tready => open ,--cmd_wready ,
fifo_wr_tdata => cache_data ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => sig_cmd_fifo_rd_rst ,
fifo_async_rd_clk => sig_cmd_fifo_rd_clk ,
-- Read Side
fifo_rd_tvalid => open ,--mst2cmd_cmd_valid ,
fifo_rd_tready => cmd2mstr_cmd_ready ,
fifo_rd_tdata => cache2mstr_command ,
fifo_rd_empty => open
);
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_STATUS_FIFO
--
-- If Generate Description:
-- Instantiates a Status FIFO
--
--
------------------------------------------------------------
GEN_INCLUDE_STATUS_FIFO : if (C_INCLUDE_STSFIFO = 1) generate
begin
-- Set constant outputs for Status Interface
sts_wstrb <= (others => '1');
sts_wlast <= '1';
------------------------------------------------------------
-- Instance: I_STS_FIFO
--
-- Description:
-- Instance for the Status FIFO
-- The Internal Interface is the Write Side
-- The User Interface is the Read side
--
------------------------------------------------------------
I_STS_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
generic map (
C_DWIDTH => C_STS_WIDTH ,
C_DEPTH => C_STSCMD_FIFO_DEPTH ,
C_IS_ASYNC => C_STSCMD_IS_ASYNC ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => sig_sts_fifo_wr_rst ,
fifo_wr_clk => sig_sts_fifo_wr_clk ,
-- Write Side
fifo_wr_tvalid => mst2stst_status_valid ,
fifo_wr_tready => stat2mstr_status_ready,
fifo_wr_tdata => mstr2stat_status ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => sig_sts_fifo_rd_rst ,
fifo_async_rd_clk => sig_sts_fifo_rd_clk ,
-- Read Side
fifo_rd_tvalid => sts_wvalid ,
fifo_rd_tready => sts_wready ,
fifo_rd_tdata => sts_wdata ,
fifo_rd_empty => open
);
end generate GEN_INCLUDE_STATUS_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_STATUS_FIFO
--
-- If Generate Description:
-- Omits the Status FIFO
--
--
------------------------------------------------------------
GEN_OMIT_STATUS_FIFO : if (C_INCLUDE_STSFIFO = 0) generate
begin
-- Status FIFO User interface housekeeping
sts_wvalid <= '0';
-- sts_wready -- ignored
sts_wdata <= (others => '0');
sts_wstrb <= (others => '0');
sts_wlast <= '0';
-- Status FIFO Internal interface housekeeping
stat2mstr_status_ready <= '1';
-- mstr2stat_status -- ignored
-- mst2stst_status_valid -- ignored
end generate GEN_OMIT_STATUS_FIFO;
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_cmd_status.vhd
--
-- Description:
-- This file implements the DataMover Command and Status interfaces.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_sg_v4_1_2;
Use axi_sg_v4_1_2.axi_sg_fifo;
-------------------------------------------------------------------------------
entity axi_sg_cmd_status is
generic (
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Indictes the width of the DataMover Address bus
C_INCLUDE_STSFIFO : Integer range 0 to 1 := 1;
-- Indicates if a Stus FIFO is to be included or omitted
-- 0 = Omit
-- 1 = Include
C_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Sets the depth of the Command and Status FIFOs
C_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Indicates if the Command and Status Stream Channels are clocked with
-- a different clock than the Main dataMover Clock
-- 0 = Same Clock
-- 1 = Different clocks
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command
C_STS_WIDTH : Integer := 8;
-- Sets the width of the output status
C_FAMILY : string := "virtex7"
-- Sets the target FPGA family
);
port (
-- Clock inputs ----------------------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
secondary_awclk : in std_logic; --
-- Clock used for the Command and Status User Interface --
-- when the User Command and Status interface is Async --
-- to the MMap interface. Async mode is set by the assigned --
-- value to C_STSCMD_IS_ASYNC = 1. --
--------------------------------------------------------------------
-- Reset inputs ----------------------------------------------------
user_reset : in std_logic; --
-- Reset used for the User Stream interface logic --
--
internal_reset : in std_logic; --
-- Reset used for the internal master interface logic --
--------------------------------------------------------------------
-- User Command Stream Ports (AXI Stream) -------------------------------
cmd_wvalid : in std_logic; --
cmd_wready : out std_logic; --
cmd_wdata : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
cache_data : in std_logic_vector(7 downto 0); --
-------------------------------------------------------------------------
-- User Status Stream Ports (AXI Stream) ------------------------------------
sts_wvalid : out std_logic; --
sts_wready : in std_logic; --
sts_wdata : out std_logic_vector(C_STS_WIDTH-1 downto 0); --
sts_wstrb : out std_logic_vector((C_STS_WIDTH/8)-1 downto 0); --
sts_wlast : out std_logic; --
-----------------------------------------------------------------------------
-- Internal Command Out Interface -----------------------------------------------
cmd2mstr_command : Out std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
cache2mstr_command : Out std_logic_vector(7 downto 0); --
-- The cache value available from the FIFO/Register --
--
mst2cmd_cmd_valid : Out std_logic; --
-- Handshake bit indicating the Command FIFO/Register has at least 1 valid --
-- command entry --
--
cmd2mstr_cmd_ready : in std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
---------------------------------------------------------------------------------
-- Internal Status In Interface -----------------------------------------------------
mstr2stat_status : in std_logic_vector(C_STS_WIDTH-1 downto 0); --
-- The input for writing the status value to the Status FIFO/Register --
--
stat2mstr_status_ready : Out std_logic; --
-- Handshake bit indicating that the Status FIFO/Register is ready for transfer --
--
mst2stst_status_valid : In std_logic --
-- Handshake bit for writing the Status value into the Status FIFO/Register --
--------------------------------------------------------------------------------------
);
end entity axi_sg_cmd_status;
architecture implementation of axi_sg_cmd_status is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_fifo_prim_type
--
-- Function Description:
-- Returns the fifo primitiver type to use for the given input
-- conditions.
--
-- 0 = Not used or allowed here
-- 1 = BRAM Primitives (Block Memory)
-- 2 = Distributed memory
--
-------------------------------------------------------------------
function get_fifo_prim_type (is_async : integer;
depth : integer) return integer is
Variable var_temp_prim_type : Integer := 1;
begin
-- coverage off
if (is_async = 1) then -- Async FIFOs always use Blk Mem (BRAM)
var_temp_prim_type := 1;
elsif (depth <= 64) then -- (use srls or distrubuted)
var_temp_prim_type := 2;
else -- depth is too big for SRLs so use Blk Memory (BRAM)
var_temp_prim_type := 1;
end if;
-- coverage on
Return (var_temp_prim_type);
end function get_fifo_prim_type;
-- Constants
Constant REGISTER_TYPE : integer := 0;
Constant BRAM_TYPE : integer := 1;
--Constant SRL_TYPE : integer := 2;
--Constant FIFO_PRIM_TYPE : integer := SRL_TYPE;
Constant FIFO_PRIM_TYPE : integer := get_fifo_prim_type(C_STSCMD_IS_ASYNC,
C_STSCMD_FIFO_DEPTH);
-- Signals
signal sig_cmd_fifo_wr_clk : std_logic := '0';
signal sig_cmd_fifo_wr_rst : std_logic := '0';
signal sig_cmd_fifo_rd_clk : std_logic := '0';
signal sig_cmd_fifo_rd_rst : std_logic := '0';
signal sig_sts_fifo_wr_clk : std_logic := '0';
signal sig_sts_fifo_wr_rst : std_logic := '0';
signal sig_sts_fifo_rd_clk : std_logic := '0';
signal sig_sts_fifo_rd_rst : std_logic := '0';
signal sig_reset_mstr : std_logic := '0';
signal sig_reset_user : std_logic := '0';
begin --(architecture implementation)
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_SYNC_RESET
--
-- If Generate Description:
-- This IfGen assigns the clock and reset signals for the
-- synchronous User interface case
--
------------------------------------------------------------
GEN_SYNC_RESET : if (C_STSCMD_IS_ASYNC = 0) generate
begin
sig_reset_mstr <= internal_reset ;
sig_reset_user <= internal_reset ;
sig_cmd_fifo_wr_clk <= primary_aclk ;
sig_cmd_fifo_wr_rst <= sig_reset_user;
sig_cmd_fifo_rd_clk <= primary_aclk ;
sig_cmd_fifo_rd_rst <= sig_reset_mstr;
sig_sts_fifo_wr_clk <= primary_aclk ;
sig_sts_fifo_wr_rst <= sig_reset_mstr;
sig_sts_fifo_rd_clk <= primary_aclk ;
sig_sts_fifo_rd_rst <= sig_reset_user;
end generate GEN_SYNC_RESET;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ASYNC_RESET
--
-- If Generate Description:
-- This IfGen assigns the clock and reset signals for the
-- Asynchronous User interface case
--
------------------------------------------------------------
GEN_ASYNC_RESET : if (C_STSCMD_IS_ASYNC = 1) generate
begin
sig_reset_mstr <= internal_reset ;
sig_reset_user <= user_reset ;
sig_cmd_fifo_wr_clk <= secondary_awclk;
sig_cmd_fifo_wr_rst <= sig_reset_user ;
sig_cmd_fifo_rd_clk <= primary_aclk ;
sig_cmd_fifo_rd_rst <= sig_reset_mstr ;
sig_sts_fifo_wr_clk <= primary_aclk ;
sig_sts_fifo_wr_rst <= sig_reset_mstr ;
sig_sts_fifo_rd_clk <= secondary_awclk;
sig_sts_fifo_rd_rst <= sig_reset_user ;
end generate GEN_ASYNC_RESET;
------------------------------------------------------------
-- Instance: I_CMD_FIFO
--
-- Description:
-- Instance for the Command FIFO
-- The User Interface is the Write Side
-- The Internal Interface is the Read side
--
------------------------------------------------------------
I_CMD_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
generic map (
C_DWIDTH => C_CMD_WIDTH ,
C_DEPTH => C_STSCMD_FIFO_DEPTH ,
C_IS_ASYNC => C_STSCMD_IS_ASYNC ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => sig_cmd_fifo_wr_rst ,
fifo_wr_clk => sig_cmd_fifo_wr_clk ,
-- Write Side
fifo_wr_tvalid => cmd_wvalid ,
fifo_wr_tready => cmd_wready ,
fifo_wr_tdata => cmd_wdata ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => sig_cmd_fifo_rd_rst ,
fifo_async_rd_clk => sig_cmd_fifo_rd_clk ,
-- Read Side
fifo_rd_tvalid => mst2cmd_cmd_valid ,
fifo_rd_tready => cmd2mstr_cmd_ready ,
fifo_rd_tdata => cmd2mstr_command ,
fifo_rd_empty => open
);
I_CACHE_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
generic map (
C_DWIDTH => 8 ,
C_DEPTH => C_STSCMD_FIFO_DEPTH ,
C_IS_ASYNC => C_STSCMD_IS_ASYNC ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => sig_cmd_fifo_wr_rst ,
fifo_wr_clk => sig_cmd_fifo_wr_clk ,
-- Write Side
fifo_wr_tvalid => cmd_wvalid ,
fifo_wr_tready => open ,--cmd_wready ,
fifo_wr_tdata => cache_data ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => sig_cmd_fifo_rd_rst ,
fifo_async_rd_clk => sig_cmd_fifo_rd_clk ,
-- Read Side
fifo_rd_tvalid => open ,--mst2cmd_cmd_valid ,
fifo_rd_tready => cmd2mstr_cmd_ready ,
fifo_rd_tdata => cache2mstr_command ,
fifo_rd_empty => open
);
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_STATUS_FIFO
--
-- If Generate Description:
-- Instantiates a Status FIFO
--
--
------------------------------------------------------------
GEN_INCLUDE_STATUS_FIFO : if (C_INCLUDE_STSFIFO = 1) generate
begin
-- Set constant outputs for Status Interface
sts_wstrb <= (others => '1');
sts_wlast <= '1';
------------------------------------------------------------
-- Instance: I_STS_FIFO
--
-- Description:
-- Instance for the Status FIFO
-- The Internal Interface is the Write Side
-- The User Interface is the Read side
--
------------------------------------------------------------
I_STS_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
generic map (
C_DWIDTH => C_STS_WIDTH ,
C_DEPTH => C_STSCMD_FIFO_DEPTH ,
C_IS_ASYNC => C_STSCMD_IS_ASYNC ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => sig_sts_fifo_wr_rst ,
fifo_wr_clk => sig_sts_fifo_wr_clk ,
-- Write Side
fifo_wr_tvalid => mst2stst_status_valid ,
fifo_wr_tready => stat2mstr_status_ready,
fifo_wr_tdata => mstr2stat_status ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => sig_sts_fifo_rd_rst ,
fifo_async_rd_clk => sig_sts_fifo_rd_clk ,
-- Read Side
fifo_rd_tvalid => sts_wvalid ,
fifo_rd_tready => sts_wready ,
fifo_rd_tdata => sts_wdata ,
fifo_rd_empty => open
);
end generate GEN_INCLUDE_STATUS_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_STATUS_FIFO
--
-- If Generate Description:
-- Omits the Status FIFO
--
--
------------------------------------------------------------
GEN_OMIT_STATUS_FIFO : if (C_INCLUDE_STSFIFO = 0) generate
begin
-- Status FIFO User interface housekeeping
sts_wvalid <= '0';
-- sts_wready -- ignored
sts_wdata <= (others => '0');
sts_wstrb <= (others => '0');
sts_wlast <= '0';
-- Status FIFO Internal interface housekeeping
stat2mstr_status_ready <= '1';
-- mstr2stat_status -- ignored
-- mst2stst_status_valid -- ignored
end generate GEN_OMIT_STATUS_FIFO;
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_cmd_status.vhd
--
-- Description:
-- This file implements the DataMover Command and Status interfaces.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_sg_v4_1_2;
Use axi_sg_v4_1_2.axi_sg_fifo;
-------------------------------------------------------------------------------
entity axi_sg_cmd_status is
generic (
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Indictes the width of the DataMover Address bus
C_INCLUDE_STSFIFO : Integer range 0 to 1 := 1;
-- Indicates if a Stus FIFO is to be included or omitted
-- 0 = Omit
-- 1 = Include
C_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Sets the depth of the Command and Status FIFOs
C_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Indicates if the Command and Status Stream Channels are clocked with
-- a different clock than the Main dataMover Clock
-- 0 = Same Clock
-- 1 = Different clocks
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command
C_STS_WIDTH : Integer := 8;
-- Sets the width of the output status
C_FAMILY : string := "virtex7"
-- Sets the target FPGA family
);
port (
-- Clock inputs ----------------------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
secondary_awclk : in std_logic; --
-- Clock used for the Command and Status User Interface --
-- when the User Command and Status interface is Async --
-- to the MMap interface. Async mode is set by the assigned --
-- value to C_STSCMD_IS_ASYNC = 1. --
--------------------------------------------------------------------
-- Reset inputs ----------------------------------------------------
user_reset : in std_logic; --
-- Reset used for the User Stream interface logic --
--
internal_reset : in std_logic; --
-- Reset used for the internal master interface logic --
--------------------------------------------------------------------
-- User Command Stream Ports (AXI Stream) -------------------------------
cmd_wvalid : in std_logic; --
cmd_wready : out std_logic; --
cmd_wdata : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
cache_data : in std_logic_vector(7 downto 0); --
-------------------------------------------------------------------------
-- User Status Stream Ports (AXI Stream) ------------------------------------
sts_wvalid : out std_logic; --
sts_wready : in std_logic; --
sts_wdata : out std_logic_vector(C_STS_WIDTH-1 downto 0); --
sts_wstrb : out std_logic_vector((C_STS_WIDTH/8)-1 downto 0); --
sts_wlast : out std_logic; --
-----------------------------------------------------------------------------
-- Internal Command Out Interface -----------------------------------------------
cmd2mstr_command : Out std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
cache2mstr_command : Out std_logic_vector(7 downto 0); --
-- The cache value available from the FIFO/Register --
--
mst2cmd_cmd_valid : Out std_logic; --
-- Handshake bit indicating the Command FIFO/Register has at least 1 valid --
-- command entry --
--
cmd2mstr_cmd_ready : in std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
---------------------------------------------------------------------------------
-- Internal Status In Interface -----------------------------------------------------
mstr2stat_status : in std_logic_vector(C_STS_WIDTH-1 downto 0); --
-- The input for writing the status value to the Status FIFO/Register --
--
stat2mstr_status_ready : Out std_logic; --
-- Handshake bit indicating that the Status FIFO/Register is ready for transfer --
--
mst2stst_status_valid : In std_logic --
-- Handshake bit for writing the Status value into the Status FIFO/Register --
--------------------------------------------------------------------------------------
);
end entity axi_sg_cmd_status;
architecture implementation of axi_sg_cmd_status is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_fifo_prim_type
--
-- Function Description:
-- Returns the fifo primitiver type to use for the given input
-- conditions.
--
-- 0 = Not used or allowed here
-- 1 = BRAM Primitives (Block Memory)
-- 2 = Distributed memory
--
-------------------------------------------------------------------
function get_fifo_prim_type (is_async : integer;
depth : integer) return integer is
Variable var_temp_prim_type : Integer := 1;
begin
-- coverage off
if (is_async = 1) then -- Async FIFOs always use Blk Mem (BRAM)
var_temp_prim_type := 1;
elsif (depth <= 64) then -- (use srls or distrubuted)
var_temp_prim_type := 2;
else -- depth is too big for SRLs so use Blk Memory (BRAM)
var_temp_prim_type := 1;
end if;
-- coverage on
Return (var_temp_prim_type);
end function get_fifo_prim_type;
-- Constants
Constant REGISTER_TYPE : integer := 0;
Constant BRAM_TYPE : integer := 1;
--Constant SRL_TYPE : integer := 2;
--Constant FIFO_PRIM_TYPE : integer := SRL_TYPE;
Constant FIFO_PRIM_TYPE : integer := get_fifo_prim_type(C_STSCMD_IS_ASYNC,
C_STSCMD_FIFO_DEPTH);
-- Signals
signal sig_cmd_fifo_wr_clk : std_logic := '0';
signal sig_cmd_fifo_wr_rst : std_logic := '0';
signal sig_cmd_fifo_rd_clk : std_logic := '0';
signal sig_cmd_fifo_rd_rst : std_logic := '0';
signal sig_sts_fifo_wr_clk : std_logic := '0';
signal sig_sts_fifo_wr_rst : std_logic := '0';
signal sig_sts_fifo_rd_clk : std_logic := '0';
signal sig_sts_fifo_rd_rst : std_logic := '0';
signal sig_reset_mstr : std_logic := '0';
signal sig_reset_user : std_logic := '0';
begin --(architecture implementation)
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_SYNC_RESET
--
-- If Generate Description:
-- This IfGen assigns the clock and reset signals for the
-- synchronous User interface case
--
------------------------------------------------------------
GEN_SYNC_RESET : if (C_STSCMD_IS_ASYNC = 0) generate
begin
sig_reset_mstr <= internal_reset ;
sig_reset_user <= internal_reset ;
sig_cmd_fifo_wr_clk <= primary_aclk ;
sig_cmd_fifo_wr_rst <= sig_reset_user;
sig_cmd_fifo_rd_clk <= primary_aclk ;
sig_cmd_fifo_rd_rst <= sig_reset_mstr;
sig_sts_fifo_wr_clk <= primary_aclk ;
sig_sts_fifo_wr_rst <= sig_reset_mstr;
sig_sts_fifo_rd_clk <= primary_aclk ;
sig_sts_fifo_rd_rst <= sig_reset_user;
end generate GEN_SYNC_RESET;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ASYNC_RESET
--
-- If Generate Description:
-- This IfGen assigns the clock and reset signals for the
-- Asynchronous User interface case
--
------------------------------------------------------------
GEN_ASYNC_RESET : if (C_STSCMD_IS_ASYNC = 1) generate
begin
sig_reset_mstr <= internal_reset ;
sig_reset_user <= user_reset ;
sig_cmd_fifo_wr_clk <= secondary_awclk;
sig_cmd_fifo_wr_rst <= sig_reset_user ;
sig_cmd_fifo_rd_clk <= primary_aclk ;
sig_cmd_fifo_rd_rst <= sig_reset_mstr ;
sig_sts_fifo_wr_clk <= primary_aclk ;
sig_sts_fifo_wr_rst <= sig_reset_mstr ;
sig_sts_fifo_rd_clk <= secondary_awclk;
sig_sts_fifo_rd_rst <= sig_reset_user ;
end generate GEN_ASYNC_RESET;
------------------------------------------------------------
-- Instance: I_CMD_FIFO
--
-- Description:
-- Instance for the Command FIFO
-- The User Interface is the Write Side
-- The Internal Interface is the Read side
--
------------------------------------------------------------
I_CMD_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
generic map (
C_DWIDTH => C_CMD_WIDTH ,
C_DEPTH => C_STSCMD_FIFO_DEPTH ,
C_IS_ASYNC => C_STSCMD_IS_ASYNC ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => sig_cmd_fifo_wr_rst ,
fifo_wr_clk => sig_cmd_fifo_wr_clk ,
-- Write Side
fifo_wr_tvalid => cmd_wvalid ,
fifo_wr_tready => cmd_wready ,
fifo_wr_tdata => cmd_wdata ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => sig_cmd_fifo_rd_rst ,
fifo_async_rd_clk => sig_cmd_fifo_rd_clk ,
-- Read Side
fifo_rd_tvalid => mst2cmd_cmd_valid ,
fifo_rd_tready => cmd2mstr_cmd_ready ,
fifo_rd_tdata => cmd2mstr_command ,
fifo_rd_empty => open
);
I_CACHE_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
generic map (
C_DWIDTH => 8 ,
C_DEPTH => C_STSCMD_FIFO_DEPTH ,
C_IS_ASYNC => C_STSCMD_IS_ASYNC ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => sig_cmd_fifo_wr_rst ,
fifo_wr_clk => sig_cmd_fifo_wr_clk ,
-- Write Side
fifo_wr_tvalid => cmd_wvalid ,
fifo_wr_tready => open ,--cmd_wready ,
fifo_wr_tdata => cache_data ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => sig_cmd_fifo_rd_rst ,
fifo_async_rd_clk => sig_cmd_fifo_rd_clk ,
-- Read Side
fifo_rd_tvalid => open ,--mst2cmd_cmd_valid ,
fifo_rd_tready => cmd2mstr_cmd_ready ,
fifo_rd_tdata => cache2mstr_command ,
fifo_rd_empty => open
);
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_STATUS_FIFO
--
-- If Generate Description:
-- Instantiates a Status FIFO
--
--
------------------------------------------------------------
GEN_INCLUDE_STATUS_FIFO : if (C_INCLUDE_STSFIFO = 1) generate
begin
-- Set constant outputs for Status Interface
sts_wstrb <= (others => '1');
sts_wlast <= '1';
------------------------------------------------------------
-- Instance: I_STS_FIFO
--
-- Description:
-- Instance for the Status FIFO
-- The Internal Interface is the Write Side
-- The User Interface is the Read side
--
------------------------------------------------------------
I_STS_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
generic map (
C_DWIDTH => C_STS_WIDTH ,
C_DEPTH => C_STSCMD_FIFO_DEPTH ,
C_IS_ASYNC => C_STSCMD_IS_ASYNC ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => sig_sts_fifo_wr_rst ,
fifo_wr_clk => sig_sts_fifo_wr_clk ,
-- Write Side
fifo_wr_tvalid => mst2stst_status_valid ,
fifo_wr_tready => stat2mstr_status_ready,
fifo_wr_tdata => mstr2stat_status ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => sig_sts_fifo_rd_rst ,
fifo_async_rd_clk => sig_sts_fifo_rd_clk ,
-- Read Side
fifo_rd_tvalid => sts_wvalid ,
fifo_rd_tready => sts_wready ,
fifo_rd_tdata => sts_wdata ,
fifo_rd_empty => open
);
end generate GEN_INCLUDE_STATUS_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_STATUS_FIFO
--
-- If Generate Description:
-- Omits the Status FIFO
--
--
------------------------------------------------------------
GEN_OMIT_STATUS_FIFO : if (C_INCLUDE_STSFIFO = 0) generate
begin
-- Status FIFO User interface housekeeping
sts_wvalid <= '0';
-- sts_wready -- ignored
sts_wdata <= (others => '0');
sts_wstrb <= (others => '0');
sts_wlast <= '0';
-- Status FIFO Internal interface housekeeping
stat2mstr_status_ready <= '1';
-- mstr2stat_status -- ignored
-- mst2stst_status_valid -- ignored
end generate GEN_OMIT_STATUS_FIFO;
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_cmd_status.vhd
--
-- Description:
-- This file implements the DataMover Command and Status interfaces.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_sg_v4_1_2;
Use axi_sg_v4_1_2.axi_sg_fifo;
-------------------------------------------------------------------------------
entity axi_sg_cmd_status is
generic (
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Indictes the width of the DataMover Address bus
C_INCLUDE_STSFIFO : Integer range 0 to 1 := 1;
-- Indicates if a Stus FIFO is to be included or omitted
-- 0 = Omit
-- 1 = Include
C_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Sets the depth of the Command and Status FIFOs
C_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Indicates if the Command and Status Stream Channels are clocked with
-- a different clock than the Main dataMover Clock
-- 0 = Same Clock
-- 1 = Different clocks
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command
C_STS_WIDTH : Integer := 8;
-- Sets the width of the output status
C_FAMILY : string := "virtex7"
-- Sets the target FPGA family
);
port (
-- Clock inputs ----------------------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
secondary_awclk : in std_logic; --
-- Clock used for the Command and Status User Interface --
-- when the User Command and Status interface is Async --
-- to the MMap interface. Async mode is set by the assigned --
-- value to C_STSCMD_IS_ASYNC = 1. --
--------------------------------------------------------------------
-- Reset inputs ----------------------------------------------------
user_reset : in std_logic; --
-- Reset used for the User Stream interface logic --
--
internal_reset : in std_logic; --
-- Reset used for the internal master interface logic --
--------------------------------------------------------------------
-- User Command Stream Ports (AXI Stream) -------------------------------
cmd_wvalid : in std_logic; --
cmd_wready : out std_logic; --
cmd_wdata : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
cache_data : in std_logic_vector(7 downto 0); --
-------------------------------------------------------------------------
-- User Status Stream Ports (AXI Stream) ------------------------------------
sts_wvalid : out std_logic; --
sts_wready : in std_logic; --
sts_wdata : out std_logic_vector(C_STS_WIDTH-1 downto 0); --
sts_wstrb : out std_logic_vector((C_STS_WIDTH/8)-1 downto 0); --
sts_wlast : out std_logic; --
-----------------------------------------------------------------------------
-- Internal Command Out Interface -----------------------------------------------
cmd2mstr_command : Out std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
cache2mstr_command : Out std_logic_vector(7 downto 0); --
-- The cache value available from the FIFO/Register --
--
mst2cmd_cmd_valid : Out std_logic; --
-- Handshake bit indicating the Command FIFO/Register has at least 1 valid --
-- command entry --
--
cmd2mstr_cmd_ready : in std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
---------------------------------------------------------------------------------
-- Internal Status In Interface -----------------------------------------------------
mstr2stat_status : in std_logic_vector(C_STS_WIDTH-1 downto 0); --
-- The input for writing the status value to the Status FIFO/Register --
--
stat2mstr_status_ready : Out std_logic; --
-- Handshake bit indicating that the Status FIFO/Register is ready for transfer --
--
mst2stst_status_valid : In std_logic --
-- Handshake bit for writing the Status value into the Status FIFO/Register --
--------------------------------------------------------------------------------------
);
end entity axi_sg_cmd_status;
architecture implementation of axi_sg_cmd_status is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_fifo_prim_type
--
-- Function Description:
-- Returns the fifo primitiver type to use for the given input
-- conditions.
--
-- 0 = Not used or allowed here
-- 1 = BRAM Primitives (Block Memory)
-- 2 = Distributed memory
--
-------------------------------------------------------------------
function get_fifo_prim_type (is_async : integer;
depth : integer) return integer is
Variable var_temp_prim_type : Integer := 1;
begin
-- coverage off
if (is_async = 1) then -- Async FIFOs always use Blk Mem (BRAM)
var_temp_prim_type := 1;
elsif (depth <= 64) then -- (use srls or distrubuted)
var_temp_prim_type := 2;
else -- depth is too big for SRLs so use Blk Memory (BRAM)
var_temp_prim_type := 1;
end if;
-- coverage on
Return (var_temp_prim_type);
end function get_fifo_prim_type;
-- Constants
Constant REGISTER_TYPE : integer := 0;
Constant BRAM_TYPE : integer := 1;
--Constant SRL_TYPE : integer := 2;
--Constant FIFO_PRIM_TYPE : integer := SRL_TYPE;
Constant FIFO_PRIM_TYPE : integer := get_fifo_prim_type(C_STSCMD_IS_ASYNC,
C_STSCMD_FIFO_DEPTH);
-- Signals
signal sig_cmd_fifo_wr_clk : std_logic := '0';
signal sig_cmd_fifo_wr_rst : std_logic := '0';
signal sig_cmd_fifo_rd_clk : std_logic := '0';
signal sig_cmd_fifo_rd_rst : std_logic := '0';
signal sig_sts_fifo_wr_clk : std_logic := '0';
signal sig_sts_fifo_wr_rst : std_logic := '0';
signal sig_sts_fifo_rd_clk : std_logic := '0';
signal sig_sts_fifo_rd_rst : std_logic := '0';
signal sig_reset_mstr : std_logic := '0';
signal sig_reset_user : std_logic := '0';
begin --(architecture implementation)
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_SYNC_RESET
--
-- If Generate Description:
-- This IfGen assigns the clock and reset signals for the
-- synchronous User interface case
--
------------------------------------------------------------
GEN_SYNC_RESET : if (C_STSCMD_IS_ASYNC = 0) generate
begin
sig_reset_mstr <= internal_reset ;
sig_reset_user <= internal_reset ;
sig_cmd_fifo_wr_clk <= primary_aclk ;
sig_cmd_fifo_wr_rst <= sig_reset_user;
sig_cmd_fifo_rd_clk <= primary_aclk ;
sig_cmd_fifo_rd_rst <= sig_reset_mstr;
sig_sts_fifo_wr_clk <= primary_aclk ;
sig_sts_fifo_wr_rst <= sig_reset_mstr;
sig_sts_fifo_rd_clk <= primary_aclk ;
sig_sts_fifo_rd_rst <= sig_reset_user;
end generate GEN_SYNC_RESET;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ASYNC_RESET
--
-- If Generate Description:
-- This IfGen assigns the clock and reset signals for the
-- Asynchronous User interface case
--
------------------------------------------------------------
GEN_ASYNC_RESET : if (C_STSCMD_IS_ASYNC = 1) generate
begin
sig_reset_mstr <= internal_reset ;
sig_reset_user <= user_reset ;
sig_cmd_fifo_wr_clk <= secondary_awclk;
sig_cmd_fifo_wr_rst <= sig_reset_user ;
sig_cmd_fifo_rd_clk <= primary_aclk ;
sig_cmd_fifo_rd_rst <= sig_reset_mstr ;
sig_sts_fifo_wr_clk <= primary_aclk ;
sig_sts_fifo_wr_rst <= sig_reset_mstr ;
sig_sts_fifo_rd_clk <= secondary_awclk;
sig_sts_fifo_rd_rst <= sig_reset_user ;
end generate GEN_ASYNC_RESET;
------------------------------------------------------------
-- Instance: I_CMD_FIFO
--
-- Description:
-- Instance for the Command FIFO
-- The User Interface is the Write Side
-- The Internal Interface is the Read side
--
------------------------------------------------------------
I_CMD_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
generic map (
C_DWIDTH => C_CMD_WIDTH ,
C_DEPTH => C_STSCMD_FIFO_DEPTH ,
C_IS_ASYNC => C_STSCMD_IS_ASYNC ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => sig_cmd_fifo_wr_rst ,
fifo_wr_clk => sig_cmd_fifo_wr_clk ,
-- Write Side
fifo_wr_tvalid => cmd_wvalid ,
fifo_wr_tready => cmd_wready ,
fifo_wr_tdata => cmd_wdata ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => sig_cmd_fifo_rd_rst ,
fifo_async_rd_clk => sig_cmd_fifo_rd_clk ,
-- Read Side
fifo_rd_tvalid => mst2cmd_cmd_valid ,
fifo_rd_tready => cmd2mstr_cmd_ready ,
fifo_rd_tdata => cmd2mstr_command ,
fifo_rd_empty => open
);
I_CACHE_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
generic map (
C_DWIDTH => 8 ,
C_DEPTH => C_STSCMD_FIFO_DEPTH ,
C_IS_ASYNC => C_STSCMD_IS_ASYNC ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => sig_cmd_fifo_wr_rst ,
fifo_wr_clk => sig_cmd_fifo_wr_clk ,
-- Write Side
fifo_wr_tvalid => cmd_wvalid ,
fifo_wr_tready => open ,--cmd_wready ,
fifo_wr_tdata => cache_data ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => sig_cmd_fifo_rd_rst ,
fifo_async_rd_clk => sig_cmd_fifo_rd_clk ,
-- Read Side
fifo_rd_tvalid => open ,--mst2cmd_cmd_valid ,
fifo_rd_tready => cmd2mstr_cmd_ready ,
fifo_rd_tdata => cache2mstr_command ,
fifo_rd_empty => open
);
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_STATUS_FIFO
--
-- If Generate Description:
-- Instantiates a Status FIFO
--
--
------------------------------------------------------------
GEN_INCLUDE_STATUS_FIFO : if (C_INCLUDE_STSFIFO = 1) generate
begin
-- Set constant outputs for Status Interface
sts_wstrb <= (others => '1');
sts_wlast <= '1';
------------------------------------------------------------
-- Instance: I_STS_FIFO
--
-- Description:
-- Instance for the Status FIFO
-- The Internal Interface is the Write Side
-- The User Interface is the Read side
--
------------------------------------------------------------
I_STS_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
generic map (
C_DWIDTH => C_STS_WIDTH ,
C_DEPTH => C_STSCMD_FIFO_DEPTH ,
C_IS_ASYNC => C_STSCMD_IS_ASYNC ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => sig_sts_fifo_wr_rst ,
fifo_wr_clk => sig_sts_fifo_wr_clk ,
-- Write Side
fifo_wr_tvalid => mst2stst_status_valid ,
fifo_wr_tready => stat2mstr_status_ready,
fifo_wr_tdata => mstr2stat_status ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => sig_sts_fifo_rd_rst ,
fifo_async_rd_clk => sig_sts_fifo_rd_clk ,
-- Read Side
fifo_rd_tvalid => sts_wvalid ,
fifo_rd_tready => sts_wready ,
fifo_rd_tdata => sts_wdata ,
fifo_rd_empty => open
);
end generate GEN_INCLUDE_STATUS_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_STATUS_FIFO
--
-- If Generate Description:
-- Omits the Status FIFO
--
--
------------------------------------------------------------
GEN_OMIT_STATUS_FIFO : if (C_INCLUDE_STSFIFO = 0) generate
begin
-- Status FIFO User interface housekeeping
sts_wvalid <= '0';
-- sts_wready -- ignored
sts_wdata <= (others => '0');
sts_wstrb <= (others => '0');
sts_wlast <= '0';
-- Status FIFO Internal interface housekeeping
stat2mstr_status_ready <= '1';
-- mstr2stat_status -- ignored
-- mst2stst_status_valid -- ignored
end generate GEN_OMIT_STATUS_FIFO;
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_cmd_status.vhd
--
-- Description:
-- This file implements the DataMover Command and Status interfaces.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_sg_v4_1_2;
Use axi_sg_v4_1_2.axi_sg_fifo;
-------------------------------------------------------------------------------
entity axi_sg_cmd_status is
generic (
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Indictes the width of the DataMover Address bus
C_INCLUDE_STSFIFO : Integer range 0 to 1 := 1;
-- Indicates if a Stus FIFO is to be included or omitted
-- 0 = Omit
-- 1 = Include
C_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Sets the depth of the Command and Status FIFOs
C_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Indicates if the Command and Status Stream Channels are clocked with
-- a different clock than the Main dataMover Clock
-- 0 = Same Clock
-- 1 = Different clocks
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command
C_STS_WIDTH : Integer := 8;
-- Sets the width of the output status
C_FAMILY : string := "virtex7"
-- Sets the target FPGA family
);
port (
-- Clock inputs ----------------------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
secondary_awclk : in std_logic; --
-- Clock used for the Command and Status User Interface --
-- when the User Command and Status interface is Async --
-- to the MMap interface. Async mode is set by the assigned --
-- value to C_STSCMD_IS_ASYNC = 1. --
--------------------------------------------------------------------
-- Reset inputs ----------------------------------------------------
user_reset : in std_logic; --
-- Reset used for the User Stream interface logic --
--
internal_reset : in std_logic; --
-- Reset used for the internal master interface logic --
--------------------------------------------------------------------
-- User Command Stream Ports (AXI Stream) -------------------------------
cmd_wvalid : in std_logic; --
cmd_wready : out std_logic; --
cmd_wdata : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
cache_data : in std_logic_vector(7 downto 0); --
-------------------------------------------------------------------------
-- User Status Stream Ports (AXI Stream) ------------------------------------
sts_wvalid : out std_logic; --
sts_wready : in std_logic; --
sts_wdata : out std_logic_vector(C_STS_WIDTH-1 downto 0); --
sts_wstrb : out std_logic_vector((C_STS_WIDTH/8)-1 downto 0); --
sts_wlast : out std_logic; --
-----------------------------------------------------------------------------
-- Internal Command Out Interface -----------------------------------------------
cmd2mstr_command : Out std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
cache2mstr_command : Out std_logic_vector(7 downto 0); --
-- The cache value available from the FIFO/Register --
--
mst2cmd_cmd_valid : Out std_logic; --
-- Handshake bit indicating the Command FIFO/Register has at least 1 valid --
-- command entry --
--
cmd2mstr_cmd_ready : in std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
---------------------------------------------------------------------------------
-- Internal Status In Interface -----------------------------------------------------
mstr2stat_status : in std_logic_vector(C_STS_WIDTH-1 downto 0); --
-- The input for writing the status value to the Status FIFO/Register --
--
stat2mstr_status_ready : Out std_logic; --
-- Handshake bit indicating that the Status FIFO/Register is ready for transfer --
--
mst2stst_status_valid : In std_logic --
-- Handshake bit for writing the Status value into the Status FIFO/Register --
--------------------------------------------------------------------------------------
);
end entity axi_sg_cmd_status;
architecture implementation of axi_sg_cmd_status is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_fifo_prim_type
--
-- Function Description:
-- Returns the fifo primitiver type to use for the given input
-- conditions.
--
-- 0 = Not used or allowed here
-- 1 = BRAM Primitives (Block Memory)
-- 2 = Distributed memory
--
-------------------------------------------------------------------
function get_fifo_prim_type (is_async : integer;
depth : integer) return integer is
Variable var_temp_prim_type : Integer := 1;
begin
-- coverage off
if (is_async = 1) then -- Async FIFOs always use Blk Mem (BRAM)
var_temp_prim_type := 1;
elsif (depth <= 64) then -- (use srls or distrubuted)
var_temp_prim_type := 2;
else -- depth is too big for SRLs so use Blk Memory (BRAM)
var_temp_prim_type := 1;
end if;
-- coverage on
Return (var_temp_prim_type);
end function get_fifo_prim_type;
-- Constants
Constant REGISTER_TYPE : integer := 0;
Constant BRAM_TYPE : integer := 1;
--Constant SRL_TYPE : integer := 2;
--Constant FIFO_PRIM_TYPE : integer := SRL_TYPE;
Constant FIFO_PRIM_TYPE : integer := get_fifo_prim_type(C_STSCMD_IS_ASYNC,
C_STSCMD_FIFO_DEPTH);
-- Signals
signal sig_cmd_fifo_wr_clk : std_logic := '0';
signal sig_cmd_fifo_wr_rst : std_logic := '0';
signal sig_cmd_fifo_rd_clk : std_logic := '0';
signal sig_cmd_fifo_rd_rst : std_logic := '0';
signal sig_sts_fifo_wr_clk : std_logic := '0';
signal sig_sts_fifo_wr_rst : std_logic := '0';
signal sig_sts_fifo_rd_clk : std_logic := '0';
signal sig_sts_fifo_rd_rst : std_logic := '0';
signal sig_reset_mstr : std_logic := '0';
signal sig_reset_user : std_logic := '0';
begin --(architecture implementation)
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_SYNC_RESET
--
-- If Generate Description:
-- This IfGen assigns the clock and reset signals for the
-- synchronous User interface case
--
------------------------------------------------------------
GEN_SYNC_RESET : if (C_STSCMD_IS_ASYNC = 0) generate
begin
sig_reset_mstr <= internal_reset ;
sig_reset_user <= internal_reset ;
sig_cmd_fifo_wr_clk <= primary_aclk ;
sig_cmd_fifo_wr_rst <= sig_reset_user;
sig_cmd_fifo_rd_clk <= primary_aclk ;
sig_cmd_fifo_rd_rst <= sig_reset_mstr;
sig_sts_fifo_wr_clk <= primary_aclk ;
sig_sts_fifo_wr_rst <= sig_reset_mstr;
sig_sts_fifo_rd_clk <= primary_aclk ;
sig_sts_fifo_rd_rst <= sig_reset_user;
end generate GEN_SYNC_RESET;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ASYNC_RESET
--
-- If Generate Description:
-- This IfGen assigns the clock and reset signals for the
-- Asynchronous User interface case
--
------------------------------------------------------------
GEN_ASYNC_RESET : if (C_STSCMD_IS_ASYNC = 1) generate
begin
sig_reset_mstr <= internal_reset ;
sig_reset_user <= user_reset ;
sig_cmd_fifo_wr_clk <= secondary_awclk;
sig_cmd_fifo_wr_rst <= sig_reset_user ;
sig_cmd_fifo_rd_clk <= primary_aclk ;
sig_cmd_fifo_rd_rst <= sig_reset_mstr ;
sig_sts_fifo_wr_clk <= primary_aclk ;
sig_sts_fifo_wr_rst <= sig_reset_mstr ;
sig_sts_fifo_rd_clk <= secondary_awclk;
sig_sts_fifo_rd_rst <= sig_reset_user ;
end generate GEN_ASYNC_RESET;
------------------------------------------------------------
-- Instance: I_CMD_FIFO
--
-- Description:
-- Instance for the Command FIFO
-- The User Interface is the Write Side
-- The Internal Interface is the Read side
--
------------------------------------------------------------
I_CMD_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
generic map (
C_DWIDTH => C_CMD_WIDTH ,
C_DEPTH => C_STSCMD_FIFO_DEPTH ,
C_IS_ASYNC => C_STSCMD_IS_ASYNC ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => sig_cmd_fifo_wr_rst ,
fifo_wr_clk => sig_cmd_fifo_wr_clk ,
-- Write Side
fifo_wr_tvalid => cmd_wvalid ,
fifo_wr_tready => cmd_wready ,
fifo_wr_tdata => cmd_wdata ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => sig_cmd_fifo_rd_rst ,
fifo_async_rd_clk => sig_cmd_fifo_rd_clk ,
-- Read Side
fifo_rd_tvalid => mst2cmd_cmd_valid ,
fifo_rd_tready => cmd2mstr_cmd_ready ,
fifo_rd_tdata => cmd2mstr_command ,
fifo_rd_empty => open
);
I_CACHE_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
generic map (
C_DWIDTH => 8 ,
C_DEPTH => C_STSCMD_FIFO_DEPTH ,
C_IS_ASYNC => C_STSCMD_IS_ASYNC ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => sig_cmd_fifo_wr_rst ,
fifo_wr_clk => sig_cmd_fifo_wr_clk ,
-- Write Side
fifo_wr_tvalid => cmd_wvalid ,
fifo_wr_tready => open ,--cmd_wready ,
fifo_wr_tdata => cache_data ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => sig_cmd_fifo_rd_rst ,
fifo_async_rd_clk => sig_cmd_fifo_rd_clk ,
-- Read Side
fifo_rd_tvalid => open ,--mst2cmd_cmd_valid ,
fifo_rd_tready => cmd2mstr_cmd_ready ,
fifo_rd_tdata => cache2mstr_command ,
fifo_rd_empty => open
);
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_STATUS_FIFO
--
-- If Generate Description:
-- Instantiates a Status FIFO
--
--
------------------------------------------------------------
GEN_INCLUDE_STATUS_FIFO : if (C_INCLUDE_STSFIFO = 1) generate
begin
-- Set constant outputs for Status Interface
sts_wstrb <= (others => '1');
sts_wlast <= '1';
------------------------------------------------------------
-- Instance: I_STS_FIFO
--
-- Description:
-- Instance for the Status FIFO
-- The Internal Interface is the Write Side
-- The User Interface is the Read side
--
------------------------------------------------------------
I_STS_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
generic map (
C_DWIDTH => C_STS_WIDTH ,
C_DEPTH => C_STSCMD_FIFO_DEPTH ,
C_IS_ASYNC => C_STSCMD_IS_ASYNC ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => sig_sts_fifo_wr_rst ,
fifo_wr_clk => sig_sts_fifo_wr_clk ,
-- Write Side
fifo_wr_tvalid => mst2stst_status_valid ,
fifo_wr_tready => stat2mstr_status_ready,
fifo_wr_tdata => mstr2stat_status ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => sig_sts_fifo_rd_rst ,
fifo_async_rd_clk => sig_sts_fifo_rd_clk ,
-- Read Side
fifo_rd_tvalid => sts_wvalid ,
fifo_rd_tready => sts_wready ,
fifo_rd_tdata => sts_wdata ,
fifo_rd_empty => open
);
end generate GEN_INCLUDE_STATUS_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_STATUS_FIFO
--
-- If Generate Description:
-- Omits the Status FIFO
--
--
------------------------------------------------------------
GEN_OMIT_STATUS_FIFO : if (C_INCLUDE_STSFIFO = 0) generate
begin
-- Status FIFO User interface housekeeping
sts_wvalid <= '0';
-- sts_wready -- ignored
sts_wdata <= (others => '0');
sts_wstrb <= (others => '0');
sts_wlast <= '0';
-- Status FIFO Internal interface housekeeping
stat2mstr_status_ready <= '1';
-- mstr2stat_status -- ignored
-- mst2stst_status_valid -- ignored
end generate GEN_OMIT_STATUS_FIFO;
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_cmd_status.vhd
--
-- Description:
-- This file implements the DataMover Command and Status interfaces.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_sg_v4_1_2;
Use axi_sg_v4_1_2.axi_sg_fifo;
-------------------------------------------------------------------------------
entity axi_sg_cmd_status is
generic (
C_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Indictes the width of the DataMover Address bus
C_INCLUDE_STSFIFO : Integer range 0 to 1 := 1;
-- Indicates if a Stus FIFO is to be included or omitted
-- 0 = Omit
-- 1 = Include
C_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Sets the depth of the Command and Status FIFOs
C_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Indicates if the Command and Status Stream Channels are clocked with
-- a different clock than the Main dataMover Clock
-- 0 = Same Clock
-- 1 = Different clocks
C_CMD_WIDTH : Integer := 68;
-- Sets the width of the input command
C_STS_WIDTH : Integer := 8;
-- Sets the width of the output status
C_FAMILY : string := "virtex7"
-- Sets the target FPGA family
);
port (
-- Clock inputs ----------------------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
secondary_awclk : in std_logic; --
-- Clock used for the Command and Status User Interface --
-- when the User Command and Status interface is Async --
-- to the MMap interface. Async mode is set by the assigned --
-- value to C_STSCMD_IS_ASYNC = 1. --
--------------------------------------------------------------------
-- Reset inputs ----------------------------------------------------
user_reset : in std_logic; --
-- Reset used for the User Stream interface logic --
--
internal_reset : in std_logic; --
-- Reset used for the internal master interface logic --
--------------------------------------------------------------------
-- User Command Stream Ports (AXI Stream) -------------------------------
cmd_wvalid : in std_logic; --
cmd_wready : out std_logic; --
cmd_wdata : in std_logic_vector(C_CMD_WIDTH-1 downto 0); --
cache_data : in std_logic_vector(7 downto 0); --
-------------------------------------------------------------------------
-- User Status Stream Ports (AXI Stream) ------------------------------------
sts_wvalid : out std_logic; --
sts_wready : in std_logic; --
sts_wdata : out std_logic_vector(C_STS_WIDTH-1 downto 0); --
sts_wstrb : out std_logic_vector((C_STS_WIDTH/8)-1 downto 0); --
sts_wlast : out std_logic; --
-----------------------------------------------------------------------------
-- Internal Command Out Interface -----------------------------------------------
cmd2mstr_command : Out std_logic_vector(C_CMD_WIDTH-1 downto 0); --
-- The next command value available from the Command FIFO/Register --
cache2mstr_command : Out std_logic_vector(7 downto 0); --
-- The cache value available from the FIFO/Register --
--
mst2cmd_cmd_valid : Out std_logic; --
-- Handshake bit indicating the Command FIFO/Register has at least 1 valid --
-- command entry --
--
cmd2mstr_cmd_ready : in std_logic; --
-- Handshake bit indicating the Command Calculator is ready to accept --
-- another command --
---------------------------------------------------------------------------------
-- Internal Status In Interface -----------------------------------------------------
mstr2stat_status : in std_logic_vector(C_STS_WIDTH-1 downto 0); --
-- The input for writing the status value to the Status FIFO/Register --
--
stat2mstr_status_ready : Out std_logic; --
-- Handshake bit indicating that the Status FIFO/Register is ready for transfer --
--
mst2stst_status_valid : In std_logic --
-- Handshake bit for writing the Status value into the Status FIFO/Register --
--------------------------------------------------------------------------------------
);
end entity axi_sg_cmd_status;
architecture implementation of axi_sg_cmd_status is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function
-------------------------------------------------------------------
-- Function
--
-- Function Name: get_fifo_prim_type
--
-- Function Description:
-- Returns the fifo primitiver type to use for the given input
-- conditions.
--
-- 0 = Not used or allowed here
-- 1 = BRAM Primitives (Block Memory)
-- 2 = Distributed memory
--
-------------------------------------------------------------------
function get_fifo_prim_type (is_async : integer;
depth : integer) return integer is
Variable var_temp_prim_type : Integer := 1;
begin
-- coverage off
if (is_async = 1) then -- Async FIFOs always use Blk Mem (BRAM)
var_temp_prim_type := 1;
elsif (depth <= 64) then -- (use srls or distrubuted)
var_temp_prim_type := 2;
else -- depth is too big for SRLs so use Blk Memory (BRAM)
var_temp_prim_type := 1;
end if;
-- coverage on
Return (var_temp_prim_type);
end function get_fifo_prim_type;
-- Constants
Constant REGISTER_TYPE : integer := 0;
Constant BRAM_TYPE : integer := 1;
--Constant SRL_TYPE : integer := 2;
--Constant FIFO_PRIM_TYPE : integer := SRL_TYPE;
Constant FIFO_PRIM_TYPE : integer := get_fifo_prim_type(C_STSCMD_IS_ASYNC,
C_STSCMD_FIFO_DEPTH);
-- Signals
signal sig_cmd_fifo_wr_clk : std_logic := '0';
signal sig_cmd_fifo_wr_rst : std_logic := '0';
signal sig_cmd_fifo_rd_clk : std_logic := '0';
signal sig_cmd_fifo_rd_rst : std_logic := '0';
signal sig_sts_fifo_wr_clk : std_logic := '0';
signal sig_sts_fifo_wr_rst : std_logic := '0';
signal sig_sts_fifo_rd_clk : std_logic := '0';
signal sig_sts_fifo_rd_rst : std_logic := '0';
signal sig_reset_mstr : std_logic := '0';
signal sig_reset_user : std_logic := '0';
begin --(architecture implementation)
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_SYNC_RESET
--
-- If Generate Description:
-- This IfGen assigns the clock and reset signals for the
-- synchronous User interface case
--
------------------------------------------------------------
GEN_SYNC_RESET : if (C_STSCMD_IS_ASYNC = 0) generate
begin
sig_reset_mstr <= internal_reset ;
sig_reset_user <= internal_reset ;
sig_cmd_fifo_wr_clk <= primary_aclk ;
sig_cmd_fifo_wr_rst <= sig_reset_user;
sig_cmd_fifo_rd_clk <= primary_aclk ;
sig_cmd_fifo_rd_rst <= sig_reset_mstr;
sig_sts_fifo_wr_clk <= primary_aclk ;
sig_sts_fifo_wr_rst <= sig_reset_mstr;
sig_sts_fifo_rd_clk <= primary_aclk ;
sig_sts_fifo_rd_rst <= sig_reset_user;
end generate GEN_SYNC_RESET;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ASYNC_RESET
--
-- If Generate Description:
-- This IfGen assigns the clock and reset signals for the
-- Asynchronous User interface case
--
------------------------------------------------------------
GEN_ASYNC_RESET : if (C_STSCMD_IS_ASYNC = 1) generate
begin
sig_reset_mstr <= internal_reset ;
sig_reset_user <= user_reset ;
sig_cmd_fifo_wr_clk <= secondary_awclk;
sig_cmd_fifo_wr_rst <= sig_reset_user ;
sig_cmd_fifo_rd_clk <= primary_aclk ;
sig_cmd_fifo_rd_rst <= sig_reset_mstr ;
sig_sts_fifo_wr_clk <= primary_aclk ;
sig_sts_fifo_wr_rst <= sig_reset_mstr ;
sig_sts_fifo_rd_clk <= secondary_awclk;
sig_sts_fifo_rd_rst <= sig_reset_user ;
end generate GEN_ASYNC_RESET;
------------------------------------------------------------
-- Instance: I_CMD_FIFO
--
-- Description:
-- Instance for the Command FIFO
-- The User Interface is the Write Side
-- The Internal Interface is the Read side
--
------------------------------------------------------------
I_CMD_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
generic map (
C_DWIDTH => C_CMD_WIDTH ,
C_DEPTH => C_STSCMD_FIFO_DEPTH ,
C_IS_ASYNC => C_STSCMD_IS_ASYNC ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => sig_cmd_fifo_wr_rst ,
fifo_wr_clk => sig_cmd_fifo_wr_clk ,
-- Write Side
fifo_wr_tvalid => cmd_wvalid ,
fifo_wr_tready => cmd_wready ,
fifo_wr_tdata => cmd_wdata ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => sig_cmd_fifo_rd_rst ,
fifo_async_rd_clk => sig_cmd_fifo_rd_clk ,
-- Read Side
fifo_rd_tvalid => mst2cmd_cmd_valid ,
fifo_rd_tready => cmd2mstr_cmd_ready ,
fifo_rd_tdata => cmd2mstr_command ,
fifo_rd_empty => open
);
I_CACHE_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
generic map (
C_DWIDTH => 8 ,
C_DEPTH => C_STSCMD_FIFO_DEPTH ,
C_IS_ASYNC => C_STSCMD_IS_ASYNC ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => sig_cmd_fifo_wr_rst ,
fifo_wr_clk => sig_cmd_fifo_wr_clk ,
-- Write Side
fifo_wr_tvalid => cmd_wvalid ,
fifo_wr_tready => open ,--cmd_wready ,
fifo_wr_tdata => cache_data ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => sig_cmd_fifo_rd_rst ,
fifo_async_rd_clk => sig_cmd_fifo_rd_clk ,
-- Read Side
fifo_rd_tvalid => open ,--mst2cmd_cmd_valid ,
fifo_rd_tready => cmd2mstr_cmd_ready ,
fifo_rd_tdata => cache2mstr_command ,
fifo_rd_empty => open
);
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INCLUDE_STATUS_FIFO
--
-- If Generate Description:
-- Instantiates a Status FIFO
--
--
------------------------------------------------------------
GEN_INCLUDE_STATUS_FIFO : if (C_INCLUDE_STSFIFO = 1) generate
begin
-- Set constant outputs for Status Interface
sts_wstrb <= (others => '1');
sts_wlast <= '1';
------------------------------------------------------------
-- Instance: I_STS_FIFO
--
-- Description:
-- Instance for the Status FIFO
-- The Internal Interface is the Write Side
-- The User Interface is the Read side
--
------------------------------------------------------------
I_STS_FIFO : entity axi_sg_v4_1_2.axi_sg_fifo
generic map (
C_DWIDTH => C_STS_WIDTH ,
C_DEPTH => C_STSCMD_FIFO_DEPTH ,
C_IS_ASYNC => C_STSCMD_IS_ASYNC ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => sig_sts_fifo_wr_rst ,
fifo_wr_clk => sig_sts_fifo_wr_clk ,
-- Write Side
fifo_wr_tvalid => mst2stst_status_valid ,
fifo_wr_tready => stat2mstr_status_ready,
fifo_wr_tdata => mstr2stat_status ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => sig_sts_fifo_rd_rst ,
fifo_async_rd_clk => sig_sts_fifo_rd_clk ,
-- Read Side
fifo_rd_tvalid => sts_wvalid ,
fifo_rd_tready => sts_wready ,
fifo_rd_tdata => sts_wdata ,
fifo_rd_empty => open
);
end generate GEN_INCLUDE_STATUS_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_STATUS_FIFO
--
-- If Generate Description:
-- Omits the Status FIFO
--
--
------------------------------------------------------------
GEN_OMIT_STATUS_FIFO : if (C_INCLUDE_STSFIFO = 0) generate
begin
-- Status FIFO User interface housekeeping
sts_wvalid <= '0';
-- sts_wready -- ignored
sts_wdata <= (others => '0');
sts_wstrb <= (others => '0');
sts_wlast <= '0';
-- Status FIFO Internal interface housekeeping
stat2mstr_status_ready <= '1';
-- mstr2stat_status -- ignored
-- mst2stst_status_valid -- ignored
end generate GEN_OMIT_STATUS_FIFO;
end implementation;
|
package body fifo is
end package body fifo;
package body fifo is
end;
package body fifo is
end package body;
|
------------------------------------------------------------------------------------------------------------------------
-- OpenMAC DMA FIFO
--
-- Copyright (C) 2011 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2011-06-06 V0.01 added generic and export fifo word vector
-- 2011-08-03 V0.10 changed to dual clocked fifo (DCFIFO)
------------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library altera_mf;
use altera_mf.all;
entity openMAC_DMAfifo is
generic (
fifo_data_width_g : natural := 16;
fifo_word_size_g : natural := 32;
fifo_word_size_log2_g : natural := 5
);
port
(
aclr : in std_logic;
rd_clk : in std_logic;
wr_clk : in std_logic;
--read port
rd_req : in std_logic;
rd_data : out std_logic_vector(fifo_data_width_g-1 downto 0);
rd_empty : out std_logic;
rd_full : out std_logic;
rd_usedw : out std_logic_vector(fifo_word_size_log2_g-1 downto 0);
--write port
wr_req : in std_logic;
wr_data : in std_logic_vector(fifo_data_width_g-1 downto 0);
wr_empty : out std_logic;
wr_full : out std_logic;
wr_usedw : out std_logic_vector(fifo_word_size_log2_g-1 downto 0)
);
end openmac_dmafifo;
architecture struct of openMAC_DMAfifo is
component dcfifo
generic (
lpm_width : natural; --width of data and q ports (input/output)
lpm_widthu : natural; --width of wrusedw and rdusedw
lpm_numwords : natural; --depth of fifo
lpm_showahead : string; --fifo showahead off/on (rdreq works as req/ack)
lpm_type : string; --SCFIFO or DCFIFO (single/dual clocked)
overflow_checking : string; --protection circuit for wrreq
underflow_checking : string; --protection circuit for rdreq
rdsync_delaypipe : natural; --number of sync from wr to rd
wrsync_delaypipe : natural; --number of sync from rd to wr
use_eab : string; --construct fifo as LE/RAM (off/on)
write_aclr_synch : string; --sync async. clear to wr clk (avoids race cond.)
intended_device_family : string --specifies the intended device for functional simulation
);
port (
wrclk : in std_logic; --clock for wr port
rdclk : in std_logic; --clock for rd port
data : in std_logic_vector(fifo_data_width_g-1 downto 0); --data to be written
wrreq : in std_logic; --write request
rdreq : in std_logic; --read request
aclr : in std_logic; --asynchronous clear fifo
q : out std_logic_vector(fifo_data_width_g-1 downto 0); --read data
wrfull : out std_logic; --fifo is full on wr port
rdfull : out std_logic; --fifo is full on rd port
wrempty : out std_logic; --fifo is empty on wr port
rdempty : out std_logic; --fifo is empty on rd port
wrusedw : out std_logic_vector(fifo_word_size_log2_g-1 downto 0); --number of words stored on wr port
rdusedw : out std_logic_vector(fifo_word_size_log2_g-1 downto 0) --number of words stored on rd port
);
end component;
constant fifo_useRam_c : string := "ON";
constant fifo_words_c : natural := fifo_word_size_g; --e.g. 32
constant fifo_usedw_c : natural := fifo_word_size_log2_g; --e.g. log2(32) = 5
--constant fifo_rd_usedw_c : natural := 5;
--constant fifo_wr_usedw_c : natural := 5;
constant fifo_data_width_c : natural := fifo_data_width_g;
--constant fifo_rd_data_width_c : natural := 16;
--constant fifo_wr_data_width_c : natural := 16;
begin
dcfifo_inst : dcfifo
generic map (
lpm_width => fifo_data_width_c, --width of data and q ports (input/output)
lpm_widthu => fifo_usedw_c, --width of wrusedw and rdusedw
lpm_numwords => fifo_words_c, --depth of fifo
lpm_showahead => "OFF", --fifo showahead off/on (rdreq works as req/ack)
lpm_type => "DCFIFO", --SCFIFO or DCFIFO (single/dual clocked)
overflow_checking => "ON", --protection circuit for wrreq
underflow_checking => "ON", --protection circuit for rdreq
rdsync_delaypipe => 4, --number of sync from wr to rd
wrsync_delaypipe => 4, --number of sync from rd to wr
use_eab => fifo_useRam_c, --construct fifo as LE/RAM (off/on)
write_aclr_synch => "ON", --sync async. clear to wr clk (avoids race cond.)
intended_device_family => "Cyclone IV" --specifies the intended device for functional simulation
)
port map (
wrclk => wr_clk, --clock for wr port
rdclk => rd_clk, --clock for rd port
data => wr_data, --data to be written
wrreq => wr_req, --write request
rdreq => rd_req, --read request
aclr => aclr, --asynchronous clear fifo
q => rd_data, --read data
wrfull => wr_full, --fifo is full on wr port
rdfull => rd_full, --fifo is full on rd port
wrempty => wr_empty, --fifo is empty on wr port
rdempty => rd_empty, --fifo is empty on rd port
wrusedw => wr_usedw, --number of words stored on wr port
rdusedw => rd_usedw --number of words stored on rd port
);
end struct;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity memtable is
port (
clk : in std_logic;
rst : in std_logic;
instaddr: in std_logic_vector(31 downto 0);
instout : out std_logic_vector(31 downto 0);
wen : in std_logic;
addr : in std_logic_vector(31 downto 0);
din : in std_logic_vector(31 downto 0);
dout : out std_logic_vector(31 downto 0);
extwen : in std_logic;
extaddr : in std_logic_vector(31 downto 0);
extdin : in std_logic_vector(31 downto 0);
extdout : out std_logic_vector(31 downto 0)
);
end memtable;
architecture arch_memtable of memtable is
constant msize: natural := 16383; --word size
type memdata is array (0 to msize) of std_logic_vector(31 downto 0);
signal MT : memdata;
begin
process(clk, rst)
variable addri, extaddri : integer;
begin
if rst = '1' then
for i in 0 to msize loop
MT(i) <= (others => '0');
end loop;
elsif clk'event and clk = '1' then
if wen = '1' then
addri := conv_integer(addr(31 downto 2));
if addri >= 0 and addri <= msize then
MT(addri) <= din;
end if;
end if;
if extwen = '1' then
extaddri := conv_integer(extaddr(31 downto 2));
if extaddri >= 0 and extaddri <= msize then
MT(extaddri) <= extdin;
end if;
end if;
end if;
end process;
process(addr, MT)
variable addri: integer;
begin
dout <= (others => '0');
addri := conv_integer(addr(31 downto 2));
if addri >= 0 and addri <= msize then
dout <= MT(addri);
end if;
end process;
process(instaddr, MT)
variable addri: integer;
begin
instout <= (others => '0');
addri := conv_integer(instaddr(31 downto 2));
if addri >= 0 and addri <= msize then
instout <= MT(addri);
end if;
end process;
process(extaddr, MT)
variable extaddri: integer;
begin
extdout <= (others => '0');
extaddri := conv_integer(extaddr(31 downto 2));
if extaddri >= 0 and extaddri <= msize then
extdout <= MT(extaddri);
end if;
end process;
end arch_memtable;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ioblock1_e
--
-- Generated
-- by: wig
-- on: Wed Jul 5 07:04:19 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ioblock1_e-rtl-a.vhd,v 1.5 2006/07/05 10:01:23 wig Exp $
-- $Date: 2006/07/05 10:01:23 $
-- $Log: ioblock1_e-rtl-a.vhd,v $
-- Revision 1.5 2006/07/05 10:01:23 wig
-- Updated padio testcase.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.91 2006/07/04 12:22:35 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ioblock1_e
--
architecture rtl of ioblock1_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component ioc_r_io
-- No Generated Generics
port (
-- Generated Port for Entity ioc_r_io
di : out std_ulogic; -- __I_AUTO_REDUCED_BUS2SIGNAL
do : in std_ulogic_vector(4 downto 0);
en : in std_ulogic_vector(4 downto 0);
nand_dir : in std_ulogic; -- Direction
nand_in : in std_ulogic; -- out to in
nand_out : out std_ulogic; -- Last is open
p_di : in std_ulogic; -- data in from pad
p_do : out std_ulogic; -- data out to pad
p_en : out std_ulogic; -- pad output enable
sel : in std_ulogic_vector(4 downto 0)
-- End of Generated Port for Entity ioc_r_io
);
end component;
-- ---------
--
-- Generated Signal List
--
signal di2 : std_ulogic_vector(8 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal disp2 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal disp2_en : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ls_en : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal display_ls_hr : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ls_min : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_en : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_hr : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_min : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_disp : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_ls_hr : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_ls_min : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_ms_hr : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_ms_min : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal nand_dir : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal nand_out_12 : std_ulogic;
signal nand_out_13 : std_ulogic;
signal nand_out_14 : std_ulogic;
signal nand_out_15 : std_ulogic;
signal nand_out_16 : std_ulogic;
signal nand_out_17 : std_ulogic;
signal nand_out_2 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_di_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_do_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_16 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_17 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal pad_en_18 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
p_mix_di2_1_0_go(1 downto 0) <= di2(1 downto 0); -- __I_O_SLICE_PORT
p_mix_di2_7_3_go(4 downto 0) <= di2(7 downto 3); -- __I_O_SLICE_PORT
disp2(1 downto 0) <= p_mix_disp2_1_0_gi(1 downto 0); -- __I_I_SLICE_PORT
disp2(7 downto 3) <= p_mix_disp2_7_3_gi(4 downto 0); -- __I_I_SLICE_PORT
disp2_en(7 downto 3) <= p_mix_disp2_en_7_3_gi(4 downto 0); -- __I_I_SLICE_PORT
disp2_en(1 downto 0) <= p_mix_disp2_en_1_0_gi(1 downto 0); -- __I_I_SLICE_PORT
display_ls_en <= p_mix_display_ls_en_gi; -- __I_I_BIT_PORT
display_ls_hr <= p_mix_display_ls_hr_gi; -- __I_I_BUS_PORT
display_ls_min <= p_mix_display_ls_min_gi; -- __I_I_BUS_PORT
display_ms_en <= p_mix_display_ms_en_gi; -- __I_I_BIT_PORT
display_ms_hr <= p_mix_display_ms_hr_gi; -- __I_I_BUS_PORT
display_ms_min <= p_mix_display_ms_min_gi; -- __I_I_BUS_PORT
iosel_disp <= p_mix_iosel_disp_gi; -- __I_I_BIT_PORT
iosel_ls_hr <= p_mix_iosel_ls_hr_gi; -- __I_I_BIT_PORT
iosel_ls_min <= p_mix_iosel_ls_min_gi; -- __I_I_BIT_PORT
iosel_ms_hr <= p_mix_iosel_ms_hr_gi; -- __I_I_BIT_PORT
iosel_ms_min <= p_mix_iosel_ms_min_gi; -- __I_I_BIT_PORT
nand_dir <= p_mix_nand_dir_gi; -- __I_I_BIT_PORT
nand_out_2 <= p_mix_nand_out_2_gi; -- __I_I_BIT_PORT
pad_di_12 <= p_mix_pad_di_12_gi; -- __I_I_BIT_PORT
pad_di_13 <= p_mix_pad_di_13_gi; -- __I_I_BIT_PORT
pad_di_14 <= p_mix_pad_di_14_gi; -- __I_I_BIT_PORT
pad_di_15 <= p_mix_pad_di_15_gi; -- __I_I_BIT_PORT
pad_di_16 <= p_mix_pad_di_16_gi; -- __I_I_BIT_PORT
pad_di_17 <= p_mix_pad_di_17_gi; -- __I_I_BIT_PORT
pad_di_18 <= p_mix_pad_di_18_gi; -- __I_I_BIT_PORT
p_mix_pad_do_12_go <= pad_do_12; -- __I_O_BIT_PORT
p_mix_pad_do_13_go <= pad_do_13; -- __I_O_BIT_PORT
p_mix_pad_do_14_go <= pad_do_14; -- __I_O_BIT_PORT
p_mix_pad_do_15_go <= pad_do_15; -- __I_O_BIT_PORT
p_mix_pad_do_16_go <= pad_do_16; -- __I_O_BIT_PORT
p_mix_pad_do_17_go <= pad_do_17; -- __I_O_BIT_PORT
p_mix_pad_do_18_go <= pad_do_18; -- __I_O_BIT_PORT
p_mix_pad_en_12_go <= pad_en_12; -- __I_O_BIT_PORT
p_mix_pad_en_13_go <= pad_en_13; -- __I_O_BIT_PORT
p_mix_pad_en_14_go <= pad_en_14; -- __I_O_BIT_PORT
p_mix_pad_en_15_go <= pad_en_15; -- __I_O_BIT_PORT
p_mix_pad_en_16_go <= pad_en_16; -- __I_O_BIT_PORT
p_mix_pad_en_17_go <= pad_en_17; -- __I_O_BIT_PORT
p_mix_pad_en_18_go <= pad_en_18; -- __I_O_BIT_PORT
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for ioc_r_io_12
ioc_r_io_12: ioc_r_io
port map (
di => di2(0), -- io data
do(0) => disp2(0), -- io data
do(1) => display_ls_min(0), -- Display storage buffer 0 ls_min
do(2) => display_ls_hr(0), -- Display storage buffer 2 ls_hr
do(3) => display_ms_hr(0), -- Display storage buffer 3 ms_hr
do(4) => display_ms_min(0), -- Display storage buffer 1 ms_min
en(0) => disp2_en(0), -- io data
en(1) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(2) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(3) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(4) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
nand_dir => nand_dir, -- Direction (X17)
nand_in => nand_out_2, -- Links ...
nand_out => nand_out_12, -- out to in
p_di => pad_di_12, -- data in from pad
p_do => pad_do_12, -- data out to pad
p_en => pad_en_12, -- pad output enable
sel(0) => iosel_disp, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(1) => iosel_ls_min, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(2) => iosel_ls_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(3) => iosel_ms_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(4) => iosel_ms_min -- __I_BIT_TO_BUSPORT -- IO_Select
);
-- End of Generated Instance Port Map for ioc_r_io_12
-- Generated Instance Port Map for ioc_r_io_13
ioc_r_io_13: ioc_r_io
port map (
di => di2(1), -- io data
do(0) => disp2(1), -- io data
do(1) => display_ls_min(1), -- Display storage buffer 0 ls_min
do(2) => display_ls_hr(1), -- Display storage buffer 2 ls_hr
do(3) => display_ms_hr(1), -- Display storage buffer 3 ms_hr
do(4) => display_ms_min(1), -- Display storage buffer 1 ms_min
en(0) => disp2_en(1), -- io data
en(1) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(2) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(3) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(4) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
nand_dir => nand_dir, -- Direction (X17)
nand_in => nand_out_12, -- out to in
nand_out => nand_out_13, -- out to in
p_di => pad_di_13, -- data in from pad
p_do => pad_do_13, -- data out to pad
p_en => pad_en_13, -- pad output enable
sel(0) => iosel_disp, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(1) => iosel_ls_min, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(2) => iosel_ls_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(3) => iosel_ms_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(4) => iosel_ms_min -- __I_BIT_TO_BUSPORT -- IO_Select
);
-- End of Generated Instance Port Map for ioc_r_io_13
-- Generated Instance Port Map for ioc_r_io_14
ioc_r_io_14: ioc_r_io
port map (
di => di2(3), -- io data
do(0) => disp2(3), -- io data
do(1) => display_ls_min(2), -- Display storage buffer 0 ls_min
do(2) => display_ls_hr(2), -- Display storage buffer 2 ls_hr
do(3) => display_ms_hr(2), -- Display storage buffer 3 ms_hr
do(4) => display_ms_min(2), -- Display storage buffer 1 ms_min
en(0) => disp2_en(3), -- io data
en(1) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(2) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(3) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(4) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
nand_dir => nand_dir, -- Direction (X17)
nand_in => nand_out_13, -- out to in
nand_out => nand_out_14, -- out to in
p_di => pad_di_14, -- data in from pad
p_do => pad_do_14, -- data out to pad
p_en => pad_en_14, -- pad output enable
sel(0) => iosel_disp, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(1) => iosel_ls_min, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(2) => iosel_ls_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(3) => iosel_ms_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(4) => iosel_ms_min -- __I_BIT_TO_BUSPORT -- IO_Select
);
-- End of Generated Instance Port Map for ioc_r_io_14
-- Generated Instance Port Map for ioc_r_io_15
ioc_r_io_15: ioc_r_io
port map (
di => di2(4), -- io data
do(0) => disp2(4), -- io data
do(1) => display_ls_min(3), -- Display storage buffer 0 ls_min
do(2) => display_ls_hr(3), -- Display storage buffer 2 ls_hr
do(3) => display_ms_hr(3), -- Display storage buffer 3 ms_hr
do(4) => display_ms_min(3), -- Display storage buffer 1 ms_min
en(0) => disp2_en(4), -- io data
en(1) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(2) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(3) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(4) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
nand_dir => nand_dir, -- Direction (X17)
nand_in => nand_out_14, -- out to in
nand_out => nand_out_15, -- out to in
p_di => pad_di_15, -- data in from pad
p_do => pad_do_15, -- data out to pad
p_en => pad_en_15, -- pad output enable
sel(0) => iosel_disp, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(1) => iosel_ls_min, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(2) => iosel_ls_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(3) => iosel_ms_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(4) => iosel_ms_min -- __I_BIT_TO_BUSPORT -- IO_Select
);
-- End of Generated Instance Port Map for ioc_r_io_15
-- Generated Instance Port Map for ioc_r_io_16
ioc_r_io_16: ioc_r_io
port map (
di => di2(5), -- io data
do(0) => disp2(5), -- io data
do(1) => display_ls_min(4), -- Display storage buffer 0 ls_min
do(2) => display_ls_hr(4), -- Display storage buffer 2 ls_hr
do(3) => display_ms_hr(4), -- Display storage buffer 3 ms_hr
do(4) => display_ms_min(4), -- Display storage buffer 1 ms_min
en(0) => disp2_en(5), -- io data
en(1) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(2) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(3) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(4) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
nand_dir => nand_dir, -- Direction (X17)
nand_in => nand_out_15, -- out to in
nand_out => nand_out_16, -- out to in
p_di => pad_di_16, -- data in from pad
p_do => pad_do_16, -- data out to pad
p_en => pad_en_16, -- pad output enable
sel(0) => iosel_disp, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(1) => iosel_ls_min, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(2) => iosel_ls_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(3) => iosel_ms_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(4) => iosel_ms_min -- __I_BIT_TO_BUSPORT -- IO_Select
);
-- End of Generated Instance Port Map for ioc_r_io_16
-- Generated Instance Port Map for ioc_r_io_17
ioc_r_io_17: ioc_r_io
port map (
di => di2(6), -- io data
do(0) => disp2(6), -- io data
do(1) => display_ls_min(5), -- Display storage buffer 0 ls_min
do(2) => display_ls_hr(5), -- Display storage buffer 2 ls_hr
do(3) => display_ms_hr(5), -- Display storage buffer 3 ms_hr
do(4) => display_ms_min(5), -- Display storage buffer 1 ms_min
en(0) => disp2_en(6), -- io data
en(1) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(2) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(3) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(4) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
nand_dir => nand_dir, -- Direction (X17)
nand_in => nand_out_16, -- out to in
nand_out => nand_out_17, -- out to in
p_di => pad_di_17, -- data in from pad
p_do => pad_do_17, -- data out to pad
p_en => pad_en_17, -- pad output enable
sel(0) => iosel_disp, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(1) => iosel_ls_min, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(2) => iosel_ls_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(3) => iosel_ms_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(4) => iosel_ms_min -- __I_BIT_TO_BUSPORT -- IO_Select
);
-- End of Generated Instance Port Map for ioc_r_io_17
-- Generated Instance Port Map for ioc_r_io_18
ioc_r_io_18: ioc_r_io
port map (
di => di2(7), -- io data
do(0) => disp2(7), -- io data
do(1) => display_ls_min(6), -- Display storage buffer 0 ls_min
do(2) => display_ls_hr(6), -- Display storage buffer 2 ls_hr
do(3) => display_ms_hr(6), -- Display storage buffer 3 ms_hr
do(4) => display_ms_min(6), -- Display storage buffer 1 ms_min
en(0) => disp2_en(7), -- io data
en(1) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(2) => display_ls_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(3) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
en(4) => display_ms_en, -- __I_BIT_TO_BUSPORT -- io_enable
nand_dir => nand_dir, -- Direction (X17)
nand_in => nand_out_17, -- out to in
nand_out => open, -- Last is open
p_di => pad_di_18, -- data in from pad
p_do => pad_do_18, -- data out to pad
p_en => pad_en_18, -- pad output enable
sel(0) => iosel_disp, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(1) => iosel_ls_min, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(2) => iosel_ls_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(3) => iosel_ms_hr, -- __I_BIT_TO_BUSPORT -- IO_Select
sel(4) => iosel_ms_min -- __I_BIT_TO_BUSPORT -- IO_Select
);
-- End of Generated Instance Port Map for ioc_r_io_18
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
architecture Struct of TbdFIR is
component Audio is
port (
reset_reset_n : in std_logic := 'X'; -- reset_n
clk_clk : in std_logic := 'X'; -- clk
audio_clk_clk : out std_logic; -- clk
i2s_adcdat : in std_logic := 'X'; -- adcdat
i2s_adclrck : in std_logic := 'X'; -- adclrck
i2s_bclk : in std_logic := 'X'; -- bclk
i2s_dacdat : out std_logic; -- dacdat
i2s_daclrck : in std_logic := 'X'; -- daclrck
i2c_SDAT : inout std_logic := 'X'; -- SDAT
i2c_SCLK : out std_logic -- SCLK
);
end component Audio;
begin -- architecture Struct
u0 : component Audio
port map (
reset_reset_n => KEY(0), -- reset.reset_n
clk_clk => CLOCK_50, -- clk.clk
audio_clk_clk => AUD_XCK, -- audio_clk.clk
i2s_adcdat => AUD_ADCDAT, -- i2s.adcdat
i2s_adclrck => AUD_ADCLRCK, -- .adclrck
i2s_bclk => AUD_BCLK, -- .bclk
i2s_dacdat => AUD_DACDAT, -- .dacdat
i2s_daclrck => AUD_DACLRCK, -- .daclrck
i2c_SDAT => FPGA_I2C_SDAT, -- i2c.SDAT
i2c_SCLK => FPGA_I2C_SCLK -- .SCLK
);
end architecture Struct;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity node_port is
generic (WIDTH: integer := 8);
port ( I_clk : in STD_LOGIC;
I_reset : in STD_LOGIC;
I_writeEnable: in STD_LOGIC;
I_readEnable: in STD_LOGIC;
I_dataIn : in STD_LOGIC_VECTOR (WIDTH-1 downto 0);
O_dataOut : out STD_LOGIC_VECTOR (WIDTH-1 downto 0);
O_dataOutValid : out STD_LOGIC); -- TODO: Check if this is actually needed. We can reset the O_dataOut(0) to Z or U instead.
end node_port;
architecture Behavioral of node_port is
type state_type is (S_EMPTY, S_WAITING_READ, S_WAITING_WRITE);
signal state: state_type;
signal data: STD_LOGIC_VECTOR (WIDTH - 1 downto 0);
begin
state_proc: process (I_clk, I_reset) begin
if (I_reset = '1') then
state <= S_EMPTY;
O_dataOut <= (others => '0');
O_dataOutValid <= '0';
elsif (rising_edge(I_clk)) then
-- Always reset the O_dataOutValid output. The reading node had its chance for a whole clock cycle.
-- Hope it's enough :)
O_dataOutValid <= '0';
case state is
when S_EMPTY =>
report "PORT is EMPTY " & std_logic'image(I_writeEnable) & " " & std_logic'image(I_readEnable);
-- Port is EMPTY. The worst case scenario at this point is one node to write
-- and the other to read, at the same time. Favor writes over reads (1 cycle less to complete the transaction).
if (I_writeEnable = '1') then
data <= I_dataIn;
state <= S_WAITING_READ;
elsif (I_readEnable = '1') then
state <= S_WAITING_WRITE;
end if;
when S_WAITING_READ =>
-- There are 2 ways to end up here.
-- 1) The port was EMPTY and the first request was for a write.
-- In this case the data is valid (already stored in the EMPTY state) so if there's a pending read
-- we can safely output the data (and set the valid bit to 1).
-- 2) The port was EMPTY and the first request was for a read.
-- In this case the port already got through S_WAITING_WRITE, the data is valid, so if there's still
-- a pending read request, we can output the data and set the valid bit to 1).
if (I_readEnable = '1') then
O_dataOut <= data;
O_dataOutValid <= '1';
state <= S_EMPTY;
end if;
when S_WAITING_WRITE =>
-- The only way to end up here is if a port was empty, and a node tried to read from it.
-- It might be possible to do everything in one cycle, but in order to keep things simple
-- I decided to delegate (is this the right word?) the read request to the corresponding state.
-- There's a chance the reader lowered the I_readEnable bit in the meantime (it's not correct
-- behaviour but it might happen).
if (I_writeEnable = '1') then
data <= I_dataIn;
state <= S_WAITING_READ;
end if;
end case;
end if;
end process;
end Behavioral;
|
------------------------------------------------------------------------------
---- ----
---- gmzpu interrupt line component testbench ----
---- ----
---- http://github.com/sonologic/gmzpu ----
---- ----
---- Description: ----
---- This is the testbench for the gmZPU core ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author: ----
---- - Salvador E. Tropea, salvador inti.gob.ar ----
---- - "Koen Martens" <gmc sonologic.nl> ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar> ----
---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial ----
---- Copyright (c) 2014 Koen Martens ----
---- ----
---- Distributed under the BSD license ----
---- ----
------------------------------------------------------------------------------
---- ----
---- Design unit: zwishbone_TB ----
---- File name: gmzpu_tb.vhdl ----
---- Note: None ----
---- Limitations: None known ----
---- Errors: None known ----
---- Library: zpu ----
---- Dependencies: IEEE.std_logic_1164 ----
---- IEEE.numeric_std ----
---- Target FPGA: n/a ----
---- Language: VHDL ----
---- Wishbone: No ----
---- Synthesis tools: Modelsim ----
---- Simulation tools: Modelsim ----
---- Text editor: vim ----
---- ----
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library gmzpu;
use gmzpu.pic;
entity interrupt_line_TB is
end entity interrupt_line_TB;
architecture Behave of interrupt_line_TB is
constant CLK_FREQ : positive:=50; -- 50 MHz clock
constant CLK_S_PER : time:=1 us/(2.0*real(CLK_FREQ)); -- Clock semi period
component interrupt_line is
port (
clk_i : in std_logic;
int_i : in std_logic;
irq_o : out std_logic;
icr_o : out std_logic;
icr_i : in std_logic;
imr_i : in std_logic;
ier_i : in std_logic;
itr_i : in std_logic;
we_i : in std_logic
);
end component interrupt_line;
type sample is record
-- inputs
int_i : std_logic;
icr_i : std_logic;
imr_i : std_logic;
ier_i : std_logic;
itr_i : std_logic;
we_i : std_logic;
-- outputs
irq_o : std_logic;
icr_o : std_logic;
end record;
type sample_array is array(natural range <>) of sample;
constant test_data : sample_array :=
(
-- int icr imr ier itr we irq icr
-- reset
('0','0','0','0','0','1', '0','0'),
('0','0','0','0','0','0', '0','0'),
('0','0','0','0','0','0', '0','0'),
-- assert imr, then int_i
('0','0','1','0','0','0', '0','0'),
('1','0','1','0','0','0', '1','1'),
('0','0','1','0','0','0', '1','1'),
('0','0','1','0','0','0', '1','1'),
('0','0','0','0','0','1', '0','0'),
('0','0','0','0','0','0', '0','0'),
-- rising edge
('0','0','0','0','0','0', '0','0'),
('0','0','0','0','0','0', '0','0'),
('1','0','0','0','0','0', '0','1'),
('1','0','0','0','0','0', '0','1'),
('1','0','0','0','0','0', '0','1'),
('1','0','0','0','0','0', '0','1'),
('1','0','0','0','0','1', '0','0'),
('1','0','0','0','0','0', '0','0'),
('1','0','0','0','0','0', '0','0'),
('0','0','0','0','0','0', '0','0'),
('0','0','0','0','0','0', '0','0'),
-- falling edge
('0','0','0','1','0','0', '0','0'),
('0','0','0','1','0','0', '0','0'),
('1','0','0','1','0','0', '0','0'),
('1','0','0','1','0','0', '0','0'),
('1','0','0','1','0','0', '0','0'),
('1','0','0','1','0','0', '0','0'),
('1','0','0','1','0','0', '0','0'),
('0','0','0','1','0','0', '0','1'),
('0','0','0','1','0','0', '0','1'),
('0','0','0','1','0','1', '0','0'),
('0','0','0','1','0','0', '0','0'),
('0','0','0','1','0','0', '0','0'),
-- int icr imr ier itr we irq icr
-- level trig
('0','0','0','0','1','0', '0','0'),
('0','0','0','0','1','0', '0','0'),
('1','0','0','0','1','0', '0','1'),
('1','0','0','0','1','0', '0','1'),
('1','0','0','0','1','0', '0','1'),
('0','0','0','0','1','0', '0','0'),
('0','0','0','0','1','0', '0','0'),
-- terminate
('0','0','0','0','0','0', '0','0')
);
signal clk : std_logic;
signal int_i : std_logic;
signal icr_i : std_logic;
signal imr_i : std_logic;
signal ier_i : std_logic;
signal itr_i : std_logic;
signal we_i : std_logic;
signal irq_o : std_logic;
signal icr_o : std_logic;
signal valid : std_logic;
begin
line : interrupt_line
port map(int_i => int_i, icr_i => icr_i, imr_i => imr_i, ier_i => ier_i, itr_i => itr_i, we_i => we_i,
irq_o => irq_o, icr_o => icr_o,
clk_i => clk);
process
variable cycle_count : integer:=0;
begin
for i in test_data'range loop
int_i <= test_data(i).int_i;
icr_i <= test_data(i).icr_i;
imr_i <= test_data(i).imr_i;
ier_i <= test_data(i).ier_i;
itr_i <= test_data(i).itr_i;
we_i <= test_data(i).we_i;
clk <= '1';
wait for CLK_S_PER;
clk <= '0';
wait for CLK_S_PER;
valid <= '1';
if irq_o/=test_data(i).irq_o then
valid <= 'Z';
end if;
if icr_o/=test_data(i).icr_o then
valid <= 'Z';
end if;
assert (irq_o = test_data(i).irq_o) report "irq_o output mismatch" severity error;
assert (icr_o = test_data(i).icr_o) report "icr_o output mismatch" severity error;
end loop;
clk <= '0';
wait;
end process;
end architecture Behave;
|
------------------------------------------------------------------------------------------------------------------------
-- OpenHUB
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Note: RxDv, RxDat0 and RxDat1 have to be synchron to CLK
-- ReceivePort return currently active Port
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2009-08-07 V0.01 Converted from V3.1 to first official version.
-- 2011-11-28 V0.02 zelenkaj Changed reset level to high-active
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
ENTITY OpenHUB IS
GENERIC ( Ports : integer := 3 );
PORT ( Rst : IN std_logic;
Clk : IN std_logic;
RxDv : IN std_logic_vector(Ports DOWNTO 1);
RxDat0, RxDat1 : IN std_logic_vector(Ports DOWNTO 1);
TxEn : OUT std_logic_vector(Ports DOWNTO 1);
TxDat0, TxDat1 : OUT std_logic_vector(Ports DOWNTO 1);
internPort : IN integer RANGE 1 TO Ports := 1;
TransmitMask : IN std_logic_vector(Ports DOWNTO 1) := (OTHERS => '1');
ReceivePort : OUT integer RANGE 0 TO Ports
);
END ENTITY OpenHUB;
ARCHITECTURE struct OF OpenHUB IS
SIGNAL RxDvI, RxDvL : std_logic_vector(Ports DOWNTO 0);
SIGNAL RxDatI0, RxDatL0 : std_logic_vector(Ports DOWNTO 0);
SIGNAL RxDatI1, RxDatL1 : std_logic_vector(Ports DOWNTO 0);
SIGNAL TxEnI : std_logic_vector(Ports DOWNTO 0);
SIGNAL TxDatI0 : std_logic_vector(Ports DOWNTO 0);
SIGNAL TxDatI1 : std_logic_vector(Ports DOWNTO 0);
SIGNAL MasterAtCollNumber : integer RANGE 0 TO Ports;
SIGNAL HubActive : boolean;
SIGNAL CollStatus : boolean;
SIGNAL TransmitMask_L : std_logic_vector(Ports DOWNTO 1);
BEGIN
RxDvI(Ports DOWNTO 0) <= RxDv(Ports DOWNTO 1) & '0';
RxDatI0(Ports DOWNTO 0) <= RxDat0(Ports DOWNTO 1) & '0';
RxDatI1(Ports DOWNTO 0) <= RxDat1(Ports DOWNTO 1) & '0';
TxEn(Ports DOWNTO 1) <= TxEnI(Ports DOWNTO 1);
TxDat0(Ports DOWNTO 1) <= TxDatI0(Ports DOWNTO 1);
TxDat1(Ports DOWNTO 1) <= TxDatI1(Ports DOWNTO 1);
do: PROCESS (Rst, Clk)
VARIABLE Active : boolean;
VARIABLE Master : integer RANGE 0 TO Ports;
VARIABLE Master_at_Coll : integer RANGE 0 TO Ports;
VARIABLE Coll : boolean;
VARIABLE RxDvM : std_logic_vector(Ports DOWNTO 0);
BEGIN
IF Rst = '1' THEN
RxDvL <= (OTHERS => '0'); RxDatL0 <= (OTHERS => '0'); RxDatL1 <= (OTHERS => '0');
TxEnI <= (OTHERS => '0'); TxDatI0 <= (OTHERS => '0'); TxDatI1 <= (OTHERS => '0');
Active := false;
Master := 0;
Master_at_Coll := 0;
Coll := false;
TransmitMask_L <= (OTHERS => '1');
ELSIF rising_edge(Clk) THEN
RxDvL <= RxDvI; RxDatL0 <= RxDatI0; RxDatL1 <= RxDatI1;
IF Active = false THEN
IF RxDvL /= 0 THEN
FOR i IN 1 TO Ports LOOP
IF RxDvL(i) = '1' AND (RxDatL0(i) = '1' OR RxDatL1(i) = '1') THEN
Master := i;
Active := true;
EXIT;
END IF;
END LOOP;
END IF;
ELSE
IF RxDvL(Master) = '0' AND RxDvI(Master) = '0' THEN
Master := 0;
END IF;
IF RxDvL = 0 AND RxDvI = 0 THEN
Active := false;
END IF;
END IF;
IF Master = 0 THEN
TxEnI <= (OTHERS => '0'); TxDatI0 <= (OTHERS => '0'); TxDatI1 <= (OTHERS => '0');
-- Overtake new TransmitMask only, when there is no active frame.
TransmitMask_L <= TransmitMask;
ELSE
FOR i IN 1 TO Ports LOOP -- output received frame to every port
IF i /= Master THEN -- but not to the port where it is coming from - "eh kloar!"
-- only send data to active ports (=> TransmitMask is set to '1') or the internal Port (Mac)
IF TransmitMask_L(i) = '1' OR Master = internPort THEN
TxEnI(i) <= '1';
TxDatI0(i) <= RxDatL0(Master);
TxDatI1(i) <= RxDatL1(Master);
END IF;
-- If there is a frame received and another is sent => collision!
IF RxDvL(i) = '1' THEN
Coll := true;
Master_at_Coll := Master;
END IF;
END IF;
END LOOP;
END IF;
IF Coll = true THEN
TxEnI(Master_at_Coll) <= '1'; TxDatI0(Master_at_Coll) <= '1'; TxDatI1(Master_at_Coll) <= '0';
RxDvM := RxDvL;
RxDvM(Master_at_Coll) := '0';
IF RxDvM = 0 THEN
TxEnI(Master_at_Coll) <= '0'; TxDatI0(Master_at_Coll) <= '0'; TxDatI1(Master_at_Coll) <= '0';
Coll := false;
Master_at_Coll := 0;
END IF;
END IF;
END IF;
HubActive <= Active;
MasterAtCollNumber <= Master_at_Coll;
CollStatus <= Coll;
-- Output the Master Port - identifies the port (1...n) which has received the packet.
-- If Master is 0, the Hub is inactive.
ReceivePort <= Master;
END PROCESS do;
END struct;
|
------------------------------------------------------------------------------------------------------------------------
-- OpenHUB
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Note: RxDv, RxDat0 and RxDat1 have to be synchron to CLK
-- ReceivePort return currently active Port
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2009-08-07 V0.01 Converted from V3.1 to first official version.
-- 2011-11-28 V0.02 zelenkaj Changed reset level to high-active
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
ENTITY OpenHUB IS
GENERIC ( Ports : integer := 3 );
PORT ( Rst : IN std_logic;
Clk : IN std_logic;
RxDv : IN std_logic_vector(Ports DOWNTO 1);
RxDat0, RxDat1 : IN std_logic_vector(Ports DOWNTO 1);
TxEn : OUT std_logic_vector(Ports DOWNTO 1);
TxDat0, TxDat1 : OUT std_logic_vector(Ports DOWNTO 1);
internPort : IN integer RANGE 1 TO Ports := 1;
TransmitMask : IN std_logic_vector(Ports DOWNTO 1) := (OTHERS => '1');
ReceivePort : OUT integer RANGE 0 TO Ports
);
END ENTITY OpenHUB;
ARCHITECTURE struct OF OpenHUB IS
SIGNAL RxDvI, RxDvL : std_logic_vector(Ports DOWNTO 0);
SIGNAL RxDatI0, RxDatL0 : std_logic_vector(Ports DOWNTO 0);
SIGNAL RxDatI1, RxDatL1 : std_logic_vector(Ports DOWNTO 0);
SIGNAL TxEnI : std_logic_vector(Ports DOWNTO 0);
SIGNAL TxDatI0 : std_logic_vector(Ports DOWNTO 0);
SIGNAL TxDatI1 : std_logic_vector(Ports DOWNTO 0);
SIGNAL MasterAtCollNumber : integer RANGE 0 TO Ports;
SIGNAL HubActive : boolean;
SIGNAL CollStatus : boolean;
SIGNAL TransmitMask_L : std_logic_vector(Ports DOWNTO 1);
BEGIN
RxDvI(Ports DOWNTO 0) <= RxDv(Ports DOWNTO 1) & '0';
RxDatI0(Ports DOWNTO 0) <= RxDat0(Ports DOWNTO 1) & '0';
RxDatI1(Ports DOWNTO 0) <= RxDat1(Ports DOWNTO 1) & '0';
TxEn(Ports DOWNTO 1) <= TxEnI(Ports DOWNTO 1);
TxDat0(Ports DOWNTO 1) <= TxDatI0(Ports DOWNTO 1);
TxDat1(Ports DOWNTO 1) <= TxDatI1(Ports DOWNTO 1);
do: PROCESS (Rst, Clk)
VARIABLE Active : boolean;
VARIABLE Master : integer RANGE 0 TO Ports;
VARIABLE Master_at_Coll : integer RANGE 0 TO Ports;
VARIABLE Coll : boolean;
VARIABLE RxDvM : std_logic_vector(Ports DOWNTO 0);
BEGIN
IF Rst = '1' THEN
RxDvL <= (OTHERS => '0'); RxDatL0 <= (OTHERS => '0'); RxDatL1 <= (OTHERS => '0');
TxEnI <= (OTHERS => '0'); TxDatI0 <= (OTHERS => '0'); TxDatI1 <= (OTHERS => '0');
Active := false;
Master := 0;
Master_at_Coll := 0;
Coll := false;
TransmitMask_L <= (OTHERS => '1');
ELSIF rising_edge(Clk) THEN
RxDvL <= RxDvI; RxDatL0 <= RxDatI0; RxDatL1 <= RxDatI1;
IF Active = false THEN
IF RxDvL /= 0 THEN
FOR i IN 1 TO Ports LOOP
IF RxDvL(i) = '1' AND (RxDatL0(i) = '1' OR RxDatL1(i) = '1') THEN
Master := i;
Active := true;
EXIT;
END IF;
END LOOP;
END IF;
ELSE
IF RxDvL(Master) = '0' AND RxDvI(Master) = '0' THEN
Master := 0;
END IF;
IF RxDvL = 0 AND RxDvI = 0 THEN
Active := false;
END IF;
END IF;
IF Master = 0 THEN
TxEnI <= (OTHERS => '0'); TxDatI0 <= (OTHERS => '0'); TxDatI1 <= (OTHERS => '0');
-- Overtake new TransmitMask only, when there is no active frame.
TransmitMask_L <= TransmitMask;
ELSE
FOR i IN 1 TO Ports LOOP -- output received frame to every port
IF i /= Master THEN -- but not to the port where it is coming from - "eh kloar!"
-- only send data to active ports (=> TransmitMask is set to '1') or the internal Port (Mac)
IF TransmitMask_L(i) = '1' OR Master = internPort THEN
TxEnI(i) <= '1';
TxDatI0(i) <= RxDatL0(Master);
TxDatI1(i) <= RxDatL1(Master);
END IF;
-- If there is a frame received and another is sent => collision!
IF RxDvL(i) = '1' THEN
Coll := true;
Master_at_Coll := Master;
END IF;
END IF;
END LOOP;
END IF;
IF Coll = true THEN
TxEnI(Master_at_Coll) <= '1'; TxDatI0(Master_at_Coll) <= '1'; TxDatI1(Master_at_Coll) <= '0';
RxDvM := RxDvL;
RxDvM(Master_at_Coll) := '0';
IF RxDvM = 0 THEN
TxEnI(Master_at_Coll) <= '0'; TxDatI0(Master_at_Coll) <= '0'; TxDatI1(Master_at_Coll) <= '0';
Coll := false;
Master_at_Coll := 0;
END IF;
END IF;
END IF;
HubActive <= Active;
MasterAtCollNumber <= Master_at_Coll;
CollStatus <= Coll;
-- Output the Master Port - identifies the port (1...n) which has received the packet.
-- If Master is 0, the Hub is inactive.
ReceivePort <= Master;
END PROCESS do;
END struct;
|
------------------------------------------------------------------------------------------------------------------------
-- OpenHUB
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Note: RxDv, RxDat0 and RxDat1 have to be synchron to CLK
-- ReceivePort return currently active Port
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2009-08-07 V0.01 Converted from V3.1 to first official version.
-- 2011-11-28 V0.02 zelenkaj Changed reset level to high-active
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
ENTITY OpenHUB IS
GENERIC ( Ports : integer := 3 );
PORT ( Rst : IN std_logic;
Clk : IN std_logic;
RxDv : IN std_logic_vector(Ports DOWNTO 1);
RxDat0, RxDat1 : IN std_logic_vector(Ports DOWNTO 1);
TxEn : OUT std_logic_vector(Ports DOWNTO 1);
TxDat0, TxDat1 : OUT std_logic_vector(Ports DOWNTO 1);
internPort : IN integer RANGE 1 TO Ports := 1;
TransmitMask : IN std_logic_vector(Ports DOWNTO 1) := (OTHERS => '1');
ReceivePort : OUT integer RANGE 0 TO Ports
);
END ENTITY OpenHUB;
ARCHITECTURE struct OF OpenHUB IS
SIGNAL RxDvI, RxDvL : std_logic_vector(Ports DOWNTO 0);
SIGNAL RxDatI0, RxDatL0 : std_logic_vector(Ports DOWNTO 0);
SIGNAL RxDatI1, RxDatL1 : std_logic_vector(Ports DOWNTO 0);
SIGNAL TxEnI : std_logic_vector(Ports DOWNTO 0);
SIGNAL TxDatI0 : std_logic_vector(Ports DOWNTO 0);
SIGNAL TxDatI1 : std_logic_vector(Ports DOWNTO 0);
SIGNAL MasterAtCollNumber : integer RANGE 0 TO Ports;
SIGNAL HubActive : boolean;
SIGNAL CollStatus : boolean;
SIGNAL TransmitMask_L : std_logic_vector(Ports DOWNTO 1);
BEGIN
RxDvI(Ports DOWNTO 0) <= RxDv(Ports DOWNTO 1) & '0';
RxDatI0(Ports DOWNTO 0) <= RxDat0(Ports DOWNTO 1) & '0';
RxDatI1(Ports DOWNTO 0) <= RxDat1(Ports DOWNTO 1) & '0';
TxEn(Ports DOWNTO 1) <= TxEnI(Ports DOWNTO 1);
TxDat0(Ports DOWNTO 1) <= TxDatI0(Ports DOWNTO 1);
TxDat1(Ports DOWNTO 1) <= TxDatI1(Ports DOWNTO 1);
do: PROCESS (Rst, Clk)
VARIABLE Active : boolean;
VARIABLE Master : integer RANGE 0 TO Ports;
VARIABLE Master_at_Coll : integer RANGE 0 TO Ports;
VARIABLE Coll : boolean;
VARIABLE RxDvM : std_logic_vector(Ports DOWNTO 0);
BEGIN
IF Rst = '1' THEN
RxDvL <= (OTHERS => '0'); RxDatL0 <= (OTHERS => '0'); RxDatL1 <= (OTHERS => '0');
TxEnI <= (OTHERS => '0'); TxDatI0 <= (OTHERS => '0'); TxDatI1 <= (OTHERS => '0');
Active := false;
Master := 0;
Master_at_Coll := 0;
Coll := false;
TransmitMask_L <= (OTHERS => '1');
ELSIF rising_edge(Clk) THEN
RxDvL <= RxDvI; RxDatL0 <= RxDatI0; RxDatL1 <= RxDatI1;
IF Active = false THEN
IF RxDvL /= 0 THEN
FOR i IN 1 TO Ports LOOP
IF RxDvL(i) = '1' AND (RxDatL0(i) = '1' OR RxDatL1(i) = '1') THEN
Master := i;
Active := true;
EXIT;
END IF;
END LOOP;
END IF;
ELSE
IF RxDvL(Master) = '0' AND RxDvI(Master) = '0' THEN
Master := 0;
END IF;
IF RxDvL = 0 AND RxDvI = 0 THEN
Active := false;
END IF;
END IF;
IF Master = 0 THEN
TxEnI <= (OTHERS => '0'); TxDatI0 <= (OTHERS => '0'); TxDatI1 <= (OTHERS => '0');
-- Overtake new TransmitMask only, when there is no active frame.
TransmitMask_L <= TransmitMask;
ELSE
FOR i IN 1 TO Ports LOOP -- output received frame to every port
IF i /= Master THEN -- but not to the port where it is coming from - "eh kloar!"
-- only send data to active ports (=> TransmitMask is set to '1') or the internal Port (Mac)
IF TransmitMask_L(i) = '1' OR Master = internPort THEN
TxEnI(i) <= '1';
TxDatI0(i) <= RxDatL0(Master);
TxDatI1(i) <= RxDatL1(Master);
END IF;
-- If there is a frame received and another is sent => collision!
IF RxDvL(i) = '1' THEN
Coll := true;
Master_at_Coll := Master;
END IF;
END IF;
END LOOP;
END IF;
IF Coll = true THEN
TxEnI(Master_at_Coll) <= '1'; TxDatI0(Master_at_Coll) <= '1'; TxDatI1(Master_at_Coll) <= '0';
RxDvM := RxDvL;
RxDvM(Master_at_Coll) := '0';
IF RxDvM = 0 THEN
TxEnI(Master_at_Coll) <= '0'; TxDatI0(Master_at_Coll) <= '0'; TxDatI1(Master_at_Coll) <= '0';
Coll := false;
Master_at_Coll := 0;
END IF;
END IF;
END IF;
HubActive <= Active;
MasterAtCollNumber <= Master_at_Coll;
CollStatus <= Coll;
-- Output the Master Port - identifies the port (1...n) which has received the packet.
-- If Master is 0, the Hub is inactive.
ReceivePort <= Master;
END PROCESS do;
END struct;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_dlxstsv.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
configuration dlx_test_verifier of dlx_test is
for verifier
for cg : clock_gen
use entity work.clock_gen(behavior)
generic map ( Tpw => 8 ns, Tps => 2 ns );
end for;
for mem : memory
use entity work.memory(preloaded)
generic map ( mem_size => 65536,
Tac_first => 95 ns, Tac_burst => 35 ns, Tpd_clk_out => 2 ns );
end for;
for proc_behav : dlx
use entity work.dlx(behavior)
generic map ( Tpd_clk_out => 2 ns, debug => trace_each_step );
end for;
for proc_rtl : dlx
use configuration work.dlx_rtl
generic map ( Tpd_clk_out => 2 ns, debug => trace_each_step );
end for;
end for; -- verifier of dlx_test
end configuration dlx_test_verifier;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_dlxstsv.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
configuration dlx_test_verifier of dlx_test is
for verifier
for cg : clock_gen
use entity work.clock_gen(behavior)
generic map ( Tpw => 8 ns, Tps => 2 ns );
end for;
for mem : memory
use entity work.memory(preloaded)
generic map ( mem_size => 65536,
Tac_first => 95 ns, Tac_burst => 35 ns, Tpd_clk_out => 2 ns );
end for;
for proc_behav : dlx
use entity work.dlx(behavior)
generic map ( Tpd_clk_out => 2 ns, debug => trace_each_step );
end for;
for proc_rtl : dlx
use configuration work.dlx_rtl
generic map ( Tpd_clk_out => 2 ns, debug => trace_each_step );
end for;
end for; -- verifier of dlx_test
end configuration dlx_test_verifier;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_dlxstsv.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
configuration dlx_test_verifier of dlx_test is
for verifier
for cg : clock_gen
use entity work.clock_gen(behavior)
generic map ( Tpw => 8 ns, Tps => 2 ns );
end for;
for mem : memory
use entity work.memory(preloaded)
generic map ( mem_size => 65536,
Tac_first => 95 ns, Tac_burst => 35 ns, Tpd_clk_out => 2 ns );
end for;
for proc_behav : dlx
use entity work.dlx(behavior)
generic map ( Tpd_clk_out => 2 ns, debug => trace_each_step );
end for;
for proc_rtl : dlx
use configuration work.dlx_rtl
generic map ( Tpd_clk_out => 2 ns, debug => trace_each_step );
end for;
end for; -- verifier of dlx_test
end configuration dlx_test_verifier;
|
-- **************************************************************************
-- ComFlowFifo
-- **************************************************************************
--
-- 16/10/2014 - creation
--------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity com_flow_fifo_rx is
generic (
FIFO_DEPTH : POSITIVE := 1024;
FLOW_ID : INTEGER := 1;
IN_SIZE : POSITIVE := 16;
OUT_SIZE : POSITIVE := 16
);
port (
clk_hal : in std_logic;
clk_proc : in std_logic;
rst_n : in std_logic;
data_wr_i : in std_logic;
data_i : in std_logic_vector(IN_SIZE-1 downto 0);
rdreq_i : in std_logic;
pktend_i : in std_logic;
enable_i : in std_logic;
data_o : out std_logic_vector(OUT_SIZE-1 downto 0);
flow_rdy_o : out std_logic;
f_empty_o : out std_logic;
fifos_f_o : out std_logic;
flag_o : out std_logic_vector(7 downto 0)
);
end com_flow_fifo_rx;
architecture rtl of com_flow_fifo_rx is
---------------------------------------------------------
-- COMPONENT DECLARATION
---------------------------------------------------------
component fifo_com_rx IS
generic (
DEPTH : POSITIVE := FIFO_DEPTH;
IN_SIZE : POSITIVE;
OUT_SIZE : POSITIVE
);
port (
aclr : in std_logic := '0';
data : in std_logic_vector(IN_SIZE-1 downto 0);
rdclk : in std_logic;
rdreq : in std_logic;
wrclk : in std_logic;
wrreq : in std_logic;
q : out std_logic_vector(OUT_SIZE-1 downto 0);
rdempty : out std_logic;
wrfull : out std_logic
);
end component;
component synchronizer
generic (
CDC_SYNC_FF_CHAIN_DEPTH: integer := 2 -- CDC Flip flop Chain depth
);
port (
signal_i : in std_logic;
signal_o : out std_logic;
clk_i : in std_logic;
clk_o : in std_logic
);
end component;
---------------------------------------------------------
-- SIGNALS
---------------------------------------------------------
-------------
-- FIFO 1 SIGNALS
-------------
signal fifo_1_data_s : std_logic_vector(IN_SIZE-1 downto 0) := (others=>'0');
signal fifo_1_wrclk_s : std_logic := '0';
signal fifo_1_wrreq_s : std_logic := '0';
signal fifo_1_wrfull_s : std_logic := '0';
signal fifo_1_q_s : std_logic_vector(OUT_SIZE-1 downto 0) := (others=>'0');
signal fifo_1_rdclk_s : std_logic := '0';
signal fifo_1_rdreq_s : std_logic := '0';
signal fifo_1_rdempty_s : std_logic := '0';
-- registers
signal fifo_1_readable : std_logic := '0';
signal fifo_1_rdempty_r : std_logic := '0';
signal fifo_1_rdempty_rr : std_logic := '0';
signal flag_fifo1 : std_logic_vector(7 downto 0) := (others=>'0');
signal fifo_1_aclr_s : std_logic :='0';
-------------
-- FIFO 2 SIGNALS
-------------
signal fifo_2_data_s : std_logic_vector(IN_SIZE-1 downto 0) := (others=>'0');
signal fifo_2_wrclk_s : std_logic := '0';
signal fifo_2_wrreq_s : std_logic := '0';
signal fifo_2_wrfull_s : std_logic := '0';
signal fifo_2_q_s : std_logic_vector(OUT_SIZE-1 downto 0) := (others=>'0');
signal fifo_2_rdclk_s : std_logic := '0';
signal fifo_2_rdreq_s : std_logic := '0';
signal fifo_2_rdempty_s : std_logic := '0';
signal fifo_2_aclr_s : std_logic := '0';
-- registers
signal fifo_2_readable : std_logic := '0';
signal fifo_2_rdempty_r : std_logic := '0';
signal fifo_2_rdempty_rr : std_logic := '0';
signal flag_fifo2 : std_logic_vector(7 downto 0) := (others=>'0');
-------------
-- FSM Signal
-------------
type fsm_state_t is (Idle, Flag8, DecodeFN, DecodeFN8, DecodeFN8_low, ReceivePacket, SwapFifos, Full, tmp);
signal fsm_state : fsm_state_t := Idle;
-- mux/demux fifos
signal fifo_sel : std_logic:= '0';
-- flag
signal data_wr_r : std_logic:= '0';
signal data_wr_r2 : std_logic:= '0';
signal frame_number : std_logic_vector(15 downto 0) := (others=>'0');
signal cur_fifo_wrreq_s : std_logic := '0';
signal cur_fifo_data_s : std_logic_vector(IN_SIZE-1 downto 0) := (others=>'0');
signal cur_fifo_readable : std_logic := '0';
signal cur_fifo_readable_r : std_logic := '0';
signal other_fifo_readable : std_logic := '0';
signal cur_fifo_full_s : std_logic := '0';
signal flow_rdy_s : std_logic := '0';
begin
-------
-- MAP CLK
-------
fifo_1_wrclk_s <= clk_hal;
fifo_2_wrclk_s <= clk_hal;
fifo_1_rdclk_s <= clk_proc;
fifo_2_rdclk_s <= clk_proc;
flow_rdy_s <= fifo_1_readable or fifo_2_readable;
FIFO_1 : fifo_com_rx
generic map (
DEPTH => FIFO_DEPTH,
IN_SIZE => IN_SIZE,
OUT_SIZE => OUT_SIZE
)
port map (
aclr => fifo_1_aclr_s,
data => fifo_1_data_s,
rdclk => fifo_1_rdclk_s,
rdreq => fifo_1_rdreq_s,
wrclk => fifo_1_wrclk_s,
wrreq => fifo_1_wrreq_s,
q => fifo_1_q_s,
rdempty => fifo_1_rdempty_s,
wrfull => fifo_1_wrfull_s
);
FIFO_2 : fifo_com_rx
generic map (
DEPTH => FIFO_DEPTH,
IN_SIZE => IN_SIZE,
OUT_SIZE => OUT_SIZE
)
port map (
aclr => fifo_2_aclr_s,
data => fifo_2_data_s,
rdclk => fifo_2_rdclk_s,
rdreq => fifo_2_rdreq_s,
wrclk => fifo_2_wrclk_s,
wrreq => fifo_2_wrreq_s,
q => fifo_2_q_s,
rdempty => fifo_2_rdempty_s,
wrfull => fifo_2_wrfull_s
);
-- CDC Synchronizer
Sync_inst : component synchronizer
generic map (
CDC_SYNC_FF_CHAIN_DEPTH => 2
)
port map (
clk_i => clk_hal,
clk_o => clk_proc,
signal_i => flow_rdy_s,
signal_o => flow_rdy_o
);
fifo_1_aclr_s <= not(rst_n or enable_i);
fifo_2_aclr_s <= not(rst_n or enable_i);
FSM : process (clk_hal, rst_n)
begin
if (rst_n = '0') then
cur_fifo_wrreq_s <= '0';
fifos_f_o <='0';
cur_fifo_readable <= '0';
fifo_sel <= '0';
fsm_state <= Idle;
-- flag_s <= (others=>'0');
-- data_wr_r <='0';
frame_number <= (others=>'0');
elsif (rising_edge(clk_hal)) then
data_wr_r <= data_wr_i;
data_wr_r2 <= data_wr_r;
case fsm_state is
when Idle =>
-- si un packet vient de l USB
if (enable_i='1' and data_wr_r ='0' and data_wr_i ='1') then
-- flag_s <= data_i; le flag est gere dans un process specifique
-- on check si le paquet est pour nous
if (data_i(IN_SIZE-1 downto IN_SIZE-8) = std_logic_vector(to_unsigned(FLOW_ID,8)) ) then
if(IN_SIZE = 16) then
fsm_state <= DecodeFN;
else
fsm_state <= Flag8;
end if;
else
fsm_state <= Idle;
end if;
end if;
when Flag8 =>
fsm_state <= DecodeFN8;
-- on lit le frane number
when DecodeFN =>
frame_number(IN_SIZE-1 downto 0) <= data_i;
fsm_state <= ReceivePacket;
when DecodeFN8 =>
frame_number(15 downto 8) <= data_i(7 downto 0);
fsm_state <= DecodeFN8_low;
when DecodeFN8_low =>
frame_number(7 downto 0) <= data_i(7 downto 0);
fsm_state <= ReceivePacket;
-- reception du packet USB
when ReceivePacket =>
cur_fifo_wrreq_s <= '1'; -- on ecrit la fifo courante
cur_fifo_data_s <= data_i;
if (cur_fifo_full_s = '1' or pktend_i = '1') then
-- si le paquet est arrive on indique que
-- la fifo courante est disponible à la lecture en sortie
cur_fifo_readable <= '1';
cur_fifo_wrreq_s <= '0'; -- deassert cur_fifo_wrreq
-- si les deux fifos sont full => etat FULL
if (other_fifo_readable ='1') then
fsm_state <= Full;
else -- sinon on swap les deux fifos
-- fifo_sel <= not (fifo_sel);
-- fsm_state <= Idle;
fsm_state <= SwapFifos;
end if;
end if;
when SwapFifos =>
cur_fifo_readable <= '0';
fifo_sel <= not (fifo_sel);
fsm_state <= Idle;
when Full =>
fifos_f_o <= '1';
if (other_fifo_readable='0') then
-- fifo_sel <= not (fifo_sel);
-- fsm_state <= tmp;
fifos_f_o <= '0';
cur_fifo_readable <= '0';
fifo_sel <= not (fifo_sel);
fsm_state <= Idle;
end if;
-- TODO A enlever: creer un coup d'horloge d'attente apres une fin de full
when tmp =>
fifos_f_o <='0';
cur_fifo_readable <= '0';
fifo_sel <= not (fifo_sel);
fsm_state <= Idle;
end case;
end if;
end process;
-- Gere l'etat des flags fifos pretes a etre lues
READABLE_PROCESS : process(clk_hal, rst_n)
begin
if (rst_n = '0') then
fifo_1_readable <='0';
fifo_2_readable <='0';
elsif rising_edge(clk_hal) then
-- register values for rising/falling edge detection on signals
fifo_1_rdempty_r <= fifo_1_rdempty_s;
fifo_1_rdempty_rr <= fifo_1_rdempty_r; -- double registert to prevent for CDC metastability
fifo_2_rdempty_r <= fifo_2_rdempty_s;
fifo_2_rdempty_rr <= fifo_2_rdempty_r;
--~ if (fifo_1_rdempty_r ='0' and fifo_1_rdempty_s='1') then
if (fifo_1_rdempty_rr ='0' and fifo_1_rdempty_r='1') then
fifo_1_readable <= '0';
end if;
--~ if (fifo_2_rdempty_r ='0' and fifo_2_rdempty_s='1') then
if (fifo_2_rdempty_rr ='0' and fifo_2_rdempty_r='1') then
fifo_2_readable <= '0';
end if;
case (fifo_sel) is -- mise a jour
when '0' =>
fifo_1_readable <= cur_fifo_readable;
-- fifo_2_readable <= fifo_2_readable;
when '1' =>
-- fifo_1_readable <= fifo_1_readable;
fifo_2_readable <= cur_fifo_readable;
when others =>
fifo_1_readable <= '0';
fifo_2_readable <= '0';
end case;
end if;
end process;
--
FLAG_PROCESS : process(clk_hal, rst_n)
begin
if (rst_n = '0') then
flag_fifo1 <= (others=>'0');
flag_fifo2 <= (others=>'0');
elsif rising_edge(clk_hal) then
--data_wr_r <= data_wr_i; -- deja fait dans le FSM Process
if ((data_wr_r ='0' and data_wr_i = '1' and IN_SIZE=16) or (data_wr_r2 ='0' and data_wr_i = '1' and IN_SIZE=8)) then
case (fifo_sel) is -- mise a jour
when '0' =>
-- le flag est situé dans les 8 LSB du premier mot qui arrive dans l'USB
flag_fifo1 <= data_i(7 downto 0);
when '1' =>
flag_fifo2 <= data_i(7 downto 0);
when others =>
flag_fifo1 <= (others=>'0');
flag_fifo2 <= (others=>'0');
end case;
else
flag_fifo1 <= flag_fifo1;
flag_fifo2 <= flag_fifo2;
end if;
end if;
end process;
-- en cas de dysfonctionnement, gerer le flag_o dans le process FLAG_PROCESS
-- utiliser le signal de lecture pour mettre àjour le registre flag_o
with fifo_sel select
flag_o <= flag_fifo1 when '1',
flag_fifo2 when '0',
(others=>'0') when others;
-- fifos connection according to sel position
FIFO_SEL_MUX : process (fifo_sel,cur_fifo_data_s,cur_fifo_wrreq_s,fifo_1_readable,fifo_2_readable,fifo_1_wrfull_s,fifo_2_wrfull_s,rdreq_i,fifo_1_q_s,fifo_2_q_s,fifo_1_rdempty_s,fifo_2_rdempty_s)
begin
case (fifo_sel) is
when '0' =>
fifo_1_wrreq_s <= cur_fifo_wrreq_s;
fifo_1_data_s <= cur_fifo_data_s;
fifo_2_data_s <= (others=>'0');
fifo_2_wrreq_s <= '0';
other_fifo_readable <= fifo_2_readable;
cur_fifo_full_s <= fifo_1_wrfull_s;
-- Flag et signaux pour lecture dans fifos
fifo_1_rdreq_s <= '0';
fifo_2_rdreq_s <= rdreq_i;
data_o <= fifo_2_q_s;
f_empty_o <= fifo_2_rdempty_s;
when '1' =>
fifo_1_wrreq_s <= '0';
fifo_2_wrreq_s <= cur_fifo_wrreq_s;
fifo_1_data_s <= (others=>'0');
fifo_2_data_s <= cur_fifo_data_s;
other_fifo_readable <= fifo_1_readable;
cur_fifo_full_s <= fifo_2_wrfull_s;
-- Flag et signaux pour lecture dans fifos
fifo_1_rdreq_s <= rdreq_i;
fifo_2_rdreq_s <= '0';
data_o <= fifo_1_q_s;
f_empty_o <= fifo_1_rdempty_s;
when others =>
fifo_1_wrreq_s <= cur_fifo_wrreq_s;
fifo_2_wrreq_s <= '0';
end case;
end process;
end rtl;
|
------------------------------
library ieee;
use ieee.std_logic_1164.all;
------------------------------
entity circuit is
--generic declarations
port (
x: in std_logic_vector(1 downto 0) ;
y: out std_logic_vector(1 downto 0) );
end entity;
------------------------------
architecture circuit of circuit is
--signals and declarations
begin
y <= "00" when x = "00" else
"10" when x = "01" else
"01" when x = "10" else
"00";
end architecture;
------------------------------
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:xlslice:1.0
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY work;
USE work.xlslice;
ENTITY RAT_slice_17_13_0 IS
PORT (
Din : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
Dout : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END RAT_slice_17_13_0;
ARCHITECTURE RAT_slice_17_13_0_arch OF RAT_slice_17_13_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_slice_17_13_0_arch: ARCHITECTURE IS "yes";
COMPONENT xlslice IS
GENERIC (
DIN_WIDTH : INTEGER;
DIN_FROM : INTEGER;
DIN_TO : INTEGER
);
PORT (
Din : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
Dout : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT xlslice;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF RAT_slice_17_13_0_arch: ARCHITECTURE IS "xlslice,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF RAT_slice_17_13_0_arch : ARCHITECTURE IS "RAT_slice_17_13_0,xlslice,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF RAT_slice_17_13_0_arch: ARCHITECTURE IS "RAT_slice_17_13_0,xlslice,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlslice,x_ipVersion=1.0,x_ipCoreRevision=0,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,DIN_WIDTH=18,DIN_FROM=1,DIN_TO=0}";
BEGIN
U0 : xlslice
GENERIC MAP (
DIN_WIDTH => 18,
DIN_FROM => 1,
DIN_TO => 0
)
PORT MAP (
Din => Din,
Dout => Dout
);
END RAT_slice_17_13_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:xlslice:1.0
-- IP Revision: 0
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY work;
USE work.xlslice;
ENTITY RAT_slice_17_13_0 IS
PORT (
Din : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
Dout : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END RAT_slice_17_13_0;
ARCHITECTURE RAT_slice_17_13_0_arch OF RAT_slice_17_13_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF RAT_slice_17_13_0_arch: ARCHITECTURE IS "yes";
COMPONENT xlslice IS
GENERIC (
DIN_WIDTH : INTEGER;
DIN_FROM : INTEGER;
DIN_TO : INTEGER
);
PORT (
Din : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
Dout : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT xlslice;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF RAT_slice_17_13_0_arch: ARCHITECTURE IS "xlslice,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF RAT_slice_17_13_0_arch : ARCHITECTURE IS "RAT_slice_17_13_0,xlslice,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF RAT_slice_17_13_0_arch: ARCHITECTURE IS "RAT_slice_17_13_0,xlslice,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xlslice,x_ipVersion=1.0,x_ipCoreRevision=0,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,DIN_WIDTH=18,DIN_FROM=1,DIN_TO=0}";
BEGIN
U0 : xlslice
GENERIC MAP (
DIN_WIDTH => 18,
DIN_FROM => 1,
DIN_TO => 0
)
PORT MAP (
Din => Din,
Dout => Dout
);
END RAT_slice_17_13_0_arch;
|
-- NEED RESULT: ARCH00265: An architecture body need not contain concurrent statements passed
--
-- TEST NAME:
--
-- CT00265
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 1.2.2 (2)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00265)
-- ENT00265_Test_Bench(ARCH00265_Test_Bench)
--
-- REVISION HISTORY:
--
-- 17-JUL-1987 - initial revision
-- 11-DEC-1989 - GDT: added wait stmt to process
--
-- NOTES:
--
-- self-checking
--
use WORK.all ;
use STANDARD_TYPES.all ;
architecture ARCH00265 of E00000 is
begin
end ARCH00265 ;
use WORK.all ;
use STANDARD_TYPES.all ;
entity ENT00265_Test_Bench is
end ENT00265_Test_Bench ;
use WORK.all;
architecture ARCH00265_Test_Bench of ENT00265_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity E00000 ( ARCH00265 ) ;
begin
CIS1 : UUT ;
process
begin
test_report ( "ARCH00265" ,
"An architecture body need not contain concurrent"
& " statements" ,
true ) ;
wait ; -- GDT 12-7-89
end process ;
end block L1 ;
end ARCH00265_Test_Bench ;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2947.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s02b00x00p08n02i02947ent IS
END c02s02b00x00p08n02i02947ent;
ARCHITECTURE c02s02b00x00p08n02i02947arch OF c02s02b00x00p08n02i02947ent IS
procedure proc1 (A:bit; B: out boolean) is
begin
if A = '1' then
B := TRUE;
else
B := FALSE;
end if;
-- Failure_here : label must be the same as subprogram identifier
end proc;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s02b00x00p08n02i02947 - Designator at the end of subprogram body is not the same as the designator of the subprogram."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s02b00x00p08n02i02947arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2947.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s02b00x00p08n02i02947ent IS
END c02s02b00x00p08n02i02947ent;
ARCHITECTURE c02s02b00x00p08n02i02947arch OF c02s02b00x00p08n02i02947ent IS
procedure proc1 (A:bit; B: out boolean) is
begin
if A = '1' then
B := TRUE;
else
B := FALSE;
end if;
-- Failure_here : label must be the same as subprogram identifier
end proc;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s02b00x00p08n02i02947 - Designator at the end of subprogram body is not the same as the designator of the subprogram."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s02b00x00p08n02i02947arch;
|
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