content
stringlengths 1
1.04M
⌀ |
|---|
library verilog;
use verilog.vl_types.all;
entity generic_m10k is
generic(
operation_mode : string := "single_port";
mixed_port_feed_through_mode: string := "dont_care";
ram_block_type : string := "auto";
logical_ram_name: string := "ram_name";
init_file : string := "init_file.hex";
init_file_layout: string := "none";
ecc_pipeline_stage_enabled: string := "false";
enable_ecc : string := "false";
width_eccstatus : integer := 2;
data_interleave_width_in_bits: integer := 1;
data_interleave_offset_in_bits: integer := 1;
port_a_logical_ram_depth: integer := 0;
port_a_logical_ram_width: integer := 0;
port_a_first_address: integer := 0;
port_a_last_address: integer := 0;
port_a_first_bit_number: integer := 0;
port_a_data_out_clear: string := "none";
port_a_data_out_clock: string := "none";
port_a_data_width: integer := 1;
port_a_address_width: integer := 1;
port_a_byte_enable_mask_width: integer := 1;
port_b_logical_ram_depth: integer := 0;
port_b_logical_ram_width: integer := 0;
port_b_first_address: integer := 0;
port_b_last_address: integer := 0;
port_b_first_bit_number: integer := 0;
port_b_address_clear: string := "none";
port_b_data_out_clear: string := "none";
port_b_data_in_clock: string := "clock1";
port_b_address_clock: string := "clock1";
port_b_write_enable_clock: string := "clock1";
port_b_read_enable_clock: string := "clock1";
port_b_byte_enable_clock: string := "clock1";
port_b_data_out_clock: string := "none";
port_b_data_width: integer := 1;
port_b_address_width: integer := 1;
port_b_byte_enable_mask_width: integer := 1;
port_a_read_during_write_mode: string := "new_data_no_nbe_read";
port_b_read_during_write_mode: string := "new_data_no_nbe_read";
power_up_uninitialized: string := "false";
lpm_type : string := "arriav_ram_block";
lpm_hint : string := "true";
connectivity_checking: string := "off";
mem_init0 : string := "";
mem_init1 : string := "";
mem_init2 : string := "";
mem_init3 : string := "";
mem_init4 : string := "";
port_a_byte_size: integer := 0;
port_b_byte_size: integer := 0;
clk0_input_clock_enable: string := "none";
clk0_core_clock_enable: string := "none";
clk0_output_clock_enable: string := "none";
clk1_input_clock_enable: string := "none";
clk1_core_clock_enable: string := "none";
clk1_output_clock_enable: string := "none";
bist_ena : string := "false";
port_a_address_clear: string := "none";
port_a_data_in_clock: string := "clock0";
port_a_address_clock: string := "clock0";
port_a_write_enable_clock: string := "clock0";
port_a_byte_enable_clock: string := "clock0";
port_a_read_enable_clock: string := "clock0"
);
port(
portadatain : in vl_logic_vector;
portaaddr : in vl_logic_vector;
portawe : in vl_logic;
portare : in vl_logic;
portbdatain : in vl_logic_vector;
portbaddr : in vl_logic_vector;
portbwe : in vl_logic;
portbre : in vl_logic;
clk0 : in vl_logic;
clk1 : in vl_logic;
ena0 : in vl_logic;
ena1 : in vl_logic;
ena2 : in vl_logic;
ena3 : in vl_logic;
clr0 : in vl_logic;
clr1 : in vl_logic;
nerror : in vl_logic;
portabyteenamasks: in vl_logic_vector;
portbbyteenamasks: in vl_logic_vector;
portaaddrstall : in vl_logic;
portbaddrstall : in vl_logic;
devclrn : in vl_logic;
devpor : in vl_logic;
eccstatus : out vl_logic_vector;
portadataout : out vl_logic_vector;
portbdataout : out vl_logic_vector;
dftout : out vl_logic_vector(8 downto 0)
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of operation_mode : constant is 1;
attribute mti_svvh_generic_type of mixed_port_feed_through_mode : constant is 1;
attribute mti_svvh_generic_type of ram_block_type : constant is 1;
attribute mti_svvh_generic_type of logical_ram_name : constant is 1;
attribute mti_svvh_generic_type of init_file : constant is 1;
attribute mti_svvh_generic_type of init_file_layout : constant is 1;
attribute mti_svvh_generic_type of ecc_pipeline_stage_enabled : constant is 1;
attribute mti_svvh_generic_type of enable_ecc : constant is 1;
attribute mti_svvh_generic_type of width_eccstatus : constant is 1;
attribute mti_svvh_generic_type of data_interleave_width_in_bits : constant is 1;
attribute mti_svvh_generic_type of data_interleave_offset_in_bits : constant is 1;
attribute mti_svvh_generic_type of port_a_logical_ram_depth : constant is 1;
attribute mti_svvh_generic_type of port_a_logical_ram_width : constant is 1;
attribute mti_svvh_generic_type of port_a_first_address : constant is 1;
attribute mti_svvh_generic_type of port_a_last_address : constant is 1;
attribute mti_svvh_generic_type of port_a_first_bit_number : constant is 1;
attribute mti_svvh_generic_type of port_a_data_out_clear : constant is 1;
attribute mti_svvh_generic_type of port_a_data_out_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_data_width : constant is 1;
attribute mti_svvh_generic_type of port_a_address_width : constant is 1;
attribute mti_svvh_generic_type of port_a_byte_enable_mask_width : constant is 1;
attribute mti_svvh_generic_type of port_b_logical_ram_depth : constant is 1;
attribute mti_svvh_generic_type of port_b_logical_ram_width : constant is 1;
attribute mti_svvh_generic_type of port_b_first_address : constant is 1;
attribute mti_svvh_generic_type of port_b_last_address : constant is 1;
attribute mti_svvh_generic_type of port_b_first_bit_number : constant is 1;
attribute mti_svvh_generic_type of port_b_address_clear : constant is 1;
attribute mti_svvh_generic_type of port_b_data_out_clear : constant is 1;
attribute mti_svvh_generic_type of port_b_data_in_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_address_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_write_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_read_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_byte_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_data_out_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_data_width : constant is 1;
attribute mti_svvh_generic_type of port_b_address_width : constant is 1;
attribute mti_svvh_generic_type of port_b_byte_enable_mask_width : constant is 1;
attribute mti_svvh_generic_type of port_a_read_during_write_mode : constant is 1;
attribute mti_svvh_generic_type of port_b_read_during_write_mode : constant is 1;
attribute mti_svvh_generic_type of power_up_uninitialized : constant is 1;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
attribute mti_svvh_generic_type of lpm_hint : constant is 1;
attribute mti_svvh_generic_type of connectivity_checking : constant is 1;
attribute mti_svvh_generic_type of mem_init0 : constant is 1;
attribute mti_svvh_generic_type of mem_init1 : constant is 1;
attribute mti_svvh_generic_type of mem_init2 : constant is 1;
attribute mti_svvh_generic_type of mem_init3 : constant is 1;
attribute mti_svvh_generic_type of mem_init4 : constant is 1;
attribute mti_svvh_generic_type of port_a_byte_size : constant is 1;
attribute mti_svvh_generic_type of port_b_byte_size : constant is 1;
attribute mti_svvh_generic_type of clk0_input_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk0_core_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk0_output_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk1_input_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk1_core_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk1_output_clock_enable : constant is 1;
attribute mti_svvh_generic_type of bist_ena : constant is 1;
attribute mti_svvh_generic_type of port_a_address_clear : constant is 1;
attribute mti_svvh_generic_type of port_a_data_in_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_address_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_write_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_byte_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_read_enable_clock : constant is 1;
end generic_m10k;
|
library verilog;
use verilog.vl_types.all;
entity generic_m10k is
generic(
operation_mode : string := "single_port";
mixed_port_feed_through_mode: string := "dont_care";
ram_block_type : string := "auto";
logical_ram_name: string := "ram_name";
init_file : string := "init_file.hex";
init_file_layout: string := "none";
ecc_pipeline_stage_enabled: string := "false";
enable_ecc : string := "false";
width_eccstatus : integer := 2;
data_interleave_width_in_bits: integer := 1;
data_interleave_offset_in_bits: integer := 1;
port_a_logical_ram_depth: integer := 0;
port_a_logical_ram_width: integer := 0;
port_a_first_address: integer := 0;
port_a_last_address: integer := 0;
port_a_first_bit_number: integer := 0;
port_a_data_out_clear: string := "none";
port_a_data_out_clock: string := "none";
port_a_data_width: integer := 1;
port_a_address_width: integer := 1;
port_a_byte_enable_mask_width: integer := 1;
port_b_logical_ram_depth: integer := 0;
port_b_logical_ram_width: integer := 0;
port_b_first_address: integer := 0;
port_b_last_address: integer := 0;
port_b_first_bit_number: integer := 0;
port_b_address_clear: string := "none";
port_b_data_out_clear: string := "none";
port_b_data_in_clock: string := "clock1";
port_b_address_clock: string := "clock1";
port_b_write_enable_clock: string := "clock1";
port_b_read_enable_clock: string := "clock1";
port_b_byte_enable_clock: string := "clock1";
port_b_data_out_clock: string := "none";
port_b_data_width: integer := 1;
port_b_address_width: integer := 1;
port_b_byte_enable_mask_width: integer := 1;
port_a_read_during_write_mode: string := "new_data_no_nbe_read";
port_b_read_during_write_mode: string := "new_data_no_nbe_read";
power_up_uninitialized: string := "false";
lpm_type : string := "arriav_ram_block";
lpm_hint : string := "true";
connectivity_checking: string := "off";
mem_init0 : string := "";
mem_init1 : string := "";
mem_init2 : string := "";
mem_init3 : string := "";
mem_init4 : string := "";
port_a_byte_size: integer := 0;
port_b_byte_size: integer := 0;
clk0_input_clock_enable: string := "none";
clk0_core_clock_enable: string := "none";
clk0_output_clock_enable: string := "none";
clk1_input_clock_enable: string := "none";
clk1_core_clock_enable: string := "none";
clk1_output_clock_enable: string := "none";
bist_ena : string := "false";
port_a_address_clear: string := "none";
port_a_data_in_clock: string := "clock0";
port_a_address_clock: string := "clock0";
port_a_write_enable_clock: string := "clock0";
port_a_byte_enable_clock: string := "clock0";
port_a_read_enable_clock: string := "clock0"
);
port(
portadatain : in vl_logic_vector;
portaaddr : in vl_logic_vector;
portawe : in vl_logic;
portare : in vl_logic;
portbdatain : in vl_logic_vector;
portbaddr : in vl_logic_vector;
portbwe : in vl_logic;
portbre : in vl_logic;
clk0 : in vl_logic;
clk1 : in vl_logic;
ena0 : in vl_logic;
ena1 : in vl_logic;
ena2 : in vl_logic;
ena3 : in vl_logic;
clr0 : in vl_logic;
clr1 : in vl_logic;
nerror : in vl_logic;
portabyteenamasks: in vl_logic_vector;
portbbyteenamasks: in vl_logic_vector;
portaaddrstall : in vl_logic;
portbaddrstall : in vl_logic;
devclrn : in vl_logic;
devpor : in vl_logic;
eccstatus : out vl_logic_vector;
portadataout : out vl_logic_vector;
portbdataout : out vl_logic_vector;
dftout : out vl_logic_vector(8 downto 0)
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of operation_mode : constant is 1;
attribute mti_svvh_generic_type of mixed_port_feed_through_mode : constant is 1;
attribute mti_svvh_generic_type of ram_block_type : constant is 1;
attribute mti_svvh_generic_type of logical_ram_name : constant is 1;
attribute mti_svvh_generic_type of init_file : constant is 1;
attribute mti_svvh_generic_type of init_file_layout : constant is 1;
attribute mti_svvh_generic_type of ecc_pipeline_stage_enabled : constant is 1;
attribute mti_svvh_generic_type of enable_ecc : constant is 1;
attribute mti_svvh_generic_type of width_eccstatus : constant is 1;
attribute mti_svvh_generic_type of data_interleave_width_in_bits : constant is 1;
attribute mti_svvh_generic_type of data_interleave_offset_in_bits : constant is 1;
attribute mti_svvh_generic_type of port_a_logical_ram_depth : constant is 1;
attribute mti_svvh_generic_type of port_a_logical_ram_width : constant is 1;
attribute mti_svvh_generic_type of port_a_first_address : constant is 1;
attribute mti_svvh_generic_type of port_a_last_address : constant is 1;
attribute mti_svvh_generic_type of port_a_first_bit_number : constant is 1;
attribute mti_svvh_generic_type of port_a_data_out_clear : constant is 1;
attribute mti_svvh_generic_type of port_a_data_out_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_data_width : constant is 1;
attribute mti_svvh_generic_type of port_a_address_width : constant is 1;
attribute mti_svvh_generic_type of port_a_byte_enable_mask_width : constant is 1;
attribute mti_svvh_generic_type of port_b_logical_ram_depth : constant is 1;
attribute mti_svvh_generic_type of port_b_logical_ram_width : constant is 1;
attribute mti_svvh_generic_type of port_b_first_address : constant is 1;
attribute mti_svvh_generic_type of port_b_last_address : constant is 1;
attribute mti_svvh_generic_type of port_b_first_bit_number : constant is 1;
attribute mti_svvh_generic_type of port_b_address_clear : constant is 1;
attribute mti_svvh_generic_type of port_b_data_out_clear : constant is 1;
attribute mti_svvh_generic_type of port_b_data_in_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_address_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_write_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_read_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_byte_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_data_out_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_data_width : constant is 1;
attribute mti_svvh_generic_type of port_b_address_width : constant is 1;
attribute mti_svvh_generic_type of port_b_byte_enable_mask_width : constant is 1;
attribute mti_svvh_generic_type of port_a_read_during_write_mode : constant is 1;
attribute mti_svvh_generic_type of port_b_read_during_write_mode : constant is 1;
attribute mti_svvh_generic_type of power_up_uninitialized : constant is 1;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
attribute mti_svvh_generic_type of lpm_hint : constant is 1;
attribute mti_svvh_generic_type of connectivity_checking : constant is 1;
attribute mti_svvh_generic_type of mem_init0 : constant is 1;
attribute mti_svvh_generic_type of mem_init1 : constant is 1;
attribute mti_svvh_generic_type of mem_init2 : constant is 1;
attribute mti_svvh_generic_type of mem_init3 : constant is 1;
attribute mti_svvh_generic_type of mem_init4 : constant is 1;
attribute mti_svvh_generic_type of port_a_byte_size : constant is 1;
attribute mti_svvh_generic_type of port_b_byte_size : constant is 1;
attribute mti_svvh_generic_type of clk0_input_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk0_core_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk0_output_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk1_input_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk1_core_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk1_output_clock_enable : constant is 1;
attribute mti_svvh_generic_type of bist_ena : constant is 1;
attribute mti_svvh_generic_type of port_a_address_clear : constant is 1;
attribute mti_svvh_generic_type of port_a_data_in_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_address_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_write_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_byte_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_read_enable_clock : constant is 1;
end generic_m10k;
|
library verilog;
use verilog.vl_types.all;
entity generic_m10k is
generic(
operation_mode : string := "single_port";
mixed_port_feed_through_mode: string := "dont_care";
ram_block_type : string := "auto";
logical_ram_name: string := "ram_name";
init_file : string := "init_file.hex";
init_file_layout: string := "none";
ecc_pipeline_stage_enabled: string := "false";
enable_ecc : string := "false";
width_eccstatus : integer := 2;
data_interleave_width_in_bits: integer := 1;
data_interleave_offset_in_bits: integer := 1;
port_a_logical_ram_depth: integer := 0;
port_a_logical_ram_width: integer := 0;
port_a_first_address: integer := 0;
port_a_last_address: integer := 0;
port_a_first_bit_number: integer := 0;
port_a_data_out_clear: string := "none";
port_a_data_out_clock: string := "none";
port_a_data_width: integer := 1;
port_a_address_width: integer := 1;
port_a_byte_enable_mask_width: integer := 1;
port_b_logical_ram_depth: integer := 0;
port_b_logical_ram_width: integer := 0;
port_b_first_address: integer := 0;
port_b_last_address: integer := 0;
port_b_first_bit_number: integer := 0;
port_b_address_clear: string := "none";
port_b_data_out_clear: string := "none";
port_b_data_in_clock: string := "clock1";
port_b_address_clock: string := "clock1";
port_b_write_enable_clock: string := "clock1";
port_b_read_enable_clock: string := "clock1";
port_b_byte_enable_clock: string := "clock1";
port_b_data_out_clock: string := "none";
port_b_data_width: integer := 1;
port_b_address_width: integer := 1;
port_b_byte_enable_mask_width: integer := 1;
port_a_read_during_write_mode: string := "new_data_no_nbe_read";
port_b_read_during_write_mode: string := "new_data_no_nbe_read";
power_up_uninitialized: string := "false";
lpm_type : string := "arriav_ram_block";
lpm_hint : string := "true";
connectivity_checking: string := "off";
mem_init0 : string := "";
mem_init1 : string := "";
mem_init2 : string := "";
mem_init3 : string := "";
mem_init4 : string := "";
port_a_byte_size: integer := 0;
port_b_byte_size: integer := 0;
clk0_input_clock_enable: string := "none";
clk0_core_clock_enable: string := "none";
clk0_output_clock_enable: string := "none";
clk1_input_clock_enable: string := "none";
clk1_core_clock_enable: string := "none";
clk1_output_clock_enable: string := "none";
bist_ena : string := "false";
port_a_address_clear: string := "none";
port_a_data_in_clock: string := "clock0";
port_a_address_clock: string := "clock0";
port_a_write_enable_clock: string := "clock0";
port_a_byte_enable_clock: string := "clock0";
port_a_read_enable_clock: string := "clock0"
);
port(
portadatain : in vl_logic_vector;
portaaddr : in vl_logic_vector;
portawe : in vl_logic;
portare : in vl_logic;
portbdatain : in vl_logic_vector;
portbaddr : in vl_logic_vector;
portbwe : in vl_logic;
portbre : in vl_logic;
clk0 : in vl_logic;
clk1 : in vl_logic;
ena0 : in vl_logic;
ena1 : in vl_logic;
ena2 : in vl_logic;
ena3 : in vl_logic;
clr0 : in vl_logic;
clr1 : in vl_logic;
nerror : in vl_logic;
portabyteenamasks: in vl_logic_vector;
portbbyteenamasks: in vl_logic_vector;
portaaddrstall : in vl_logic;
portbaddrstall : in vl_logic;
devclrn : in vl_logic;
devpor : in vl_logic;
eccstatus : out vl_logic_vector;
portadataout : out vl_logic_vector;
portbdataout : out vl_logic_vector;
dftout : out vl_logic_vector(8 downto 0)
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of operation_mode : constant is 1;
attribute mti_svvh_generic_type of mixed_port_feed_through_mode : constant is 1;
attribute mti_svvh_generic_type of ram_block_type : constant is 1;
attribute mti_svvh_generic_type of logical_ram_name : constant is 1;
attribute mti_svvh_generic_type of init_file : constant is 1;
attribute mti_svvh_generic_type of init_file_layout : constant is 1;
attribute mti_svvh_generic_type of ecc_pipeline_stage_enabled : constant is 1;
attribute mti_svvh_generic_type of enable_ecc : constant is 1;
attribute mti_svvh_generic_type of width_eccstatus : constant is 1;
attribute mti_svvh_generic_type of data_interleave_width_in_bits : constant is 1;
attribute mti_svvh_generic_type of data_interleave_offset_in_bits : constant is 1;
attribute mti_svvh_generic_type of port_a_logical_ram_depth : constant is 1;
attribute mti_svvh_generic_type of port_a_logical_ram_width : constant is 1;
attribute mti_svvh_generic_type of port_a_first_address : constant is 1;
attribute mti_svvh_generic_type of port_a_last_address : constant is 1;
attribute mti_svvh_generic_type of port_a_first_bit_number : constant is 1;
attribute mti_svvh_generic_type of port_a_data_out_clear : constant is 1;
attribute mti_svvh_generic_type of port_a_data_out_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_data_width : constant is 1;
attribute mti_svvh_generic_type of port_a_address_width : constant is 1;
attribute mti_svvh_generic_type of port_a_byte_enable_mask_width : constant is 1;
attribute mti_svvh_generic_type of port_b_logical_ram_depth : constant is 1;
attribute mti_svvh_generic_type of port_b_logical_ram_width : constant is 1;
attribute mti_svvh_generic_type of port_b_first_address : constant is 1;
attribute mti_svvh_generic_type of port_b_last_address : constant is 1;
attribute mti_svvh_generic_type of port_b_first_bit_number : constant is 1;
attribute mti_svvh_generic_type of port_b_address_clear : constant is 1;
attribute mti_svvh_generic_type of port_b_data_out_clear : constant is 1;
attribute mti_svvh_generic_type of port_b_data_in_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_address_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_write_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_read_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_byte_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_data_out_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_data_width : constant is 1;
attribute mti_svvh_generic_type of port_b_address_width : constant is 1;
attribute mti_svvh_generic_type of port_b_byte_enable_mask_width : constant is 1;
attribute mti_svvh_generic_type of port_a_read_during_write_mode : constant is 1;
attribute mti_svvh_generic_type of port_b_read_during_write_mode : constant is 1;
attribute mti_svvh_generic_type of power_up_uninitialized : constant is 1;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
attribute mti_svvh_generic_type of lpm_hint : constant is 1;
attribute mti_svvh_generic_type of connectivity_checking : constant is 1;
attribute mti_svvh_generic_type of mem_init0 : constant is 1;
attribute mti_svvh_generic_type of mem_init1 : constant is 1;
attribute mti_svvh_generic_type of mem_init2 : constant is 1;
attribute mti_svvh_generic_type of mem_init3 : constant is 1;
attribute mti_svvh_generic_type of mem_init4 : constant is 1;
attribute mti_svvh_generic_type of port_a_byte_size : constant is 1;
attribute mti_svvh_generic_type of port_b_byte_size : constant is 1;
attribute mti_svvh_generic_type of clk0_input_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk0_core_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk0_output_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk1_input_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk1_core_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk1_output_clock_enable : constant is 1;
attribute mti_svvh_generic_type of bist_ena : constant is 1;
attribute mti_svvh_generic_type of port_a_address_clear : constant is 1;
attribute mti_svvh_generic_type of port_a_data_in_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_address_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_write_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_byte_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_read_enable_clock : constant is 1;
end generic_m10k;
|
library verilog;
use verilog.vl_types.all;
entity generic_m10k is
generic(
operation_mode : string := "single_port";
mixed_port_feed_through_mode: string := "dont_care";
ram_block_type : string := "auto";
logical_ram_name: string := "ram_name";
init_file : string := "init_file.hex";
init_file_layout: string := "none";
ecc_pipeline_stage_enabled: string := "false";
enable_ecc : string := "false";
width_eccstatus : integer := 2;
data_interleave_width_in_bits: integer := 1;
data_interleave_offset_in_bits: integer := 1;
port_a_logical_ram_depth: integer := 0;
port_a_logical_ram_width: integer := 0;
port_a_first_address: integer := 0;
port_a_last_address: integer := 0;
port_a_first_bit_number: integer := 0;
port_a_data_out_clear: string := "none";
port_a_data_out_clock: string := "none";
port_a_data_width: integer := 1;
port_a_address_width: integer := 1;
port_a_byte_enable_mask_width: integer := 1;
port_b_logical_ram_depth: integer := 0;
port_b_logical_ram_width: integer := 0;
port_b_first_address: integer := 0;
port_b_last_address: integer := 0;
port_b_first_bit_number: integer := 0;
port_b_address_clear: string := "none";
port_b_data_out_clear: string := "none";
port_b_data_in_clock: string := "clock1";
port_b_address_clock: string := "clock1";
port_b_write_enable_clock: string := "clock1";
port_b_read_enable_clock: string := "clock1";
port_b_byte_enable_clock: string := "clock1";
port_b_data_out_clock: string := "none";
port_b_data_width: integer := 1;
port_b_address_width: integer := 1;
port_b_byte_enable_mask_width: integer := 1;
port_a_read_during_write_mode: string := "new_data_no_nbe_read";
port_b_read_during_write_mode: string := "new_data_no_nbe_read";
power_up_uninitialized: string := "false";
lpm_type : string := "arriav_ram_block";
lpm_hint : string := "true";
connectivity_checking: string := "off";
mem_init0 : string := "";
mem_init1 : string := "";
mem_init2 : string := "";
mem_init3 : string := "";
mem_init4 : string := "";
port_a_byte_size: integer := 0;
port_b_byte_size: integer := 0;
clk0_input_clock_enable: string := "none";
clk0_core_clock_enable: string := "none";
clk0_output_clock_enable: string := "none";
clk1_input_clock_enable: string := "none";
clk1_core_clock_enable: string := "none";
clk1_output_clock_enable: string := "none";
bist_ena : string := "false";
port_a_address_clear: string := "none";
port_a_data_in_clock: string := "clock0";
port_a_address_clock: string := "clock0";
port_a_write_enable_clock: string := "clock0";
port_a_byte_enable_clock: string := "clock0";
port_a_read_enable_clock: string := "clock0"
);
port(
portadatain : in vl_logic_vector;
portaaddr : in vl_logic_vector;
portawe : in vl_logic;
portare : in vl_logic;
portbdatain : in vl_logic_vector;
portbaddr : in vl_logic_vector;
portbwe : in vl_logic;
portbre : in vl_logic;
clk0 : in vl_logic;
clk1 : in vl_logic;
ena0 : in vl_logic;
ena1 : in vl_logic;
ena2 : in vl_logic;
ena3 : in vl_logic;
clr0 : in vl_logic;
clr1 : in vl_logic;
nerror : in vl_logic;
portabyteenamasks: in vl_logic_vector;
portbbyteenamasks: in vl_logic_vector;
portaaddrstall : in vl_logic;
portbaddrstall : in vl_logic;
devclrn : in vl_logic;
devpor : in vl_logic;
eccstatus : out vl_logic_vector;
portadataout : out vl_logic_vector;
portbdataout : out vl_logic_vector;
dftout : out vl_logic_vector(8 downto 0)
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of operation_mode : constant is 1;
attribute mti_svvh_generic_type of mixed_port_feed_through_mode : constant is 1;
attribute mti_svvh_generic_type of ram_block_type : constant is 1;
attribute mti_svvh_generic_type of logical_ram_name : constant is 1;
attribute mti_svvh_generic_type of init_file : constant is 1;
attribute mti_svvh_generic_type of init_file_layout : constant is 1;
attribute mti_svvh_generic_type of ecc_pipeline_stage_enabled : constant is 1;
attribute mti_svvh_generic_type of enable_ecc : constant is 1;
attribute mti_svvh_generic_type of width_eccstatus : constant is 1;
attribute mti_svvh_generic_type of data_interleave_width_in_bits : constant is 1;
attribute mti_svvh_generic_type of data_interleave_offset_in_bits : constant is 1;
attribute mti_svvh_generic_type of port_a_logical_ram_depth : constant is 1;
attribute mti_svvh_generic_type of port_a_logical_ram_width : constant is 1;
attribute mti_svvh_generic_type of port_a_first_address : constant is 1;
attribute mti_svvh_generic_type of port_a_last_address : constant is 1;
attribute mti_svvh_generic_type of port_a_first_bit_number : constant is 1;
attribute mti_svvh_generic_type of port_a_data_out_clear : constant is 1;
attribute mti_svvh_generic_type of port_a_data_out_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_data_width : constant is 1;
attribute mti_svvh_generic_type of port_a_address_width : constant is 1;
attribute mti_svvh_generic_type of port_a_byte_enable_mask_width : constant is 1;
attribute mti_svvh_generic_type of port_b_logical_ram_depth : constant is 1;
attribute mti_svvh_generic_type of port_b_logical_ram_width : constant is 1;
attribute mti_svvh_generic_type of port_b_first_address : constant is 1;
attribute mti_svvh_generic_type of port_b_last_address : constant is 1;
attribute mti_svvh_generic_type of port_b_first_bit_number : constant is 1;
attribute mti_svvh_generic_type of port_b_address_clear : constant is 1;
attribute mti_svvh_generic_type of port_b_data_out_clear : constant is 1;
attribute mti_svvh_generic_type of port_b_data_in_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_address_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_write_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_read_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_byte_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_data_out_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_data_width : constant is 1;
attribute mti_svvh_generic_type of port_b_address_width : constant is 1;
attribute mti_svvh_generic_type of port_b_byte_enable_mask_width : constant is 1;
attribute mti_svvh_generic_type of port_a_read_during_write_mode : constant is 1;
attribute mti_svvh_generic_type of port_b_read_during_write_mode : constant is 1;
attribute mti_svvh_generic_type of power_up_uninitialized : constant is 1;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
attribute mti_svvh_generic_type of lpm_hint : constant is 1;
attribute mti_svvh_generic_type of connectivity_checking : constant is 1;
attribute mti_svvh_generic_type of mem_init0 : constant is 1;
attribute mti_svvh_generic_type of mem_init1 : constant is 1;
attribute mti_svvh_generic_type of mem_init2 : constant is 1;
attribute mti_svvh_generic_type of mem_init3 : constant is 1;
attribute mti_svvh_generic_type of mem_init4 : constant is 1;
attribute mti_svvh_generic_type of port_a_byte_size : constant is 1;
attribute mti_svvh_generic_type of port_b_byte_size : constant is 1;
attribute mti_svvh_generic_type of clk0_input_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk0_core_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk0_output_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk1_input_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk1_core_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk1_output_clock_enable : constant is 1;
attribute mti_svvh_generic_type of bist_ena : constant is 1;
attribute mti_svvh_generic_type of port_a_address_clear : constant is 1;
attribute mti_svvh_generic_type of port_a_data_in_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_address_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_write_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_byte_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_read_enable_clock : constant is 1;
end generic_m10k;
|
library verilog;
use verilog.vl_types.all;
entity generic_m10k is
generic(
operation_mode : string := "single_port";
mixed_port_feed_through_mode: string := "dont_care";
ram_block_type : string := "auto";
logical_ram_name: string := "ram_name";
init_file : string := "init_file.hex";
init_file_layout: string := "none";
ecc_pipeline_stage_enabled: string := "false";
enable_ecc : string := "false";
width_eccstatus : integer := 2;
data_interleave_width_in_bits: integer := 1;
data_interleave_offset_in_bits: integer := 1;
port_a_logical_ram_depth: integer := 0;
port_a_logical_ram_width: integer := 0;
port_a_first_address: integer := 0;
port_a_last_address: integer := 0;
port_a_first_bit_number: integer := 0;
port_a_data_out_clear: string := "none";
port_a_data_out_clock: string := "none";
port_a_data_width: integer := 1;
port_a_address_width: integer := 1;
port_a_byte_enable_mask_width: integer := 1;
port_b_logical_ram_depth: integer := 0;
port_b_logical_ram_width: integer := 0;
port_b_first_address: integer := 0;
port_b_last_address: integer := 0;
port_b_first_bit_number: integer := 0;
port_b_address_clear: string := "none";
port_b_data_out_clear: string := "none";
port_b_data_in_clock: string := "clock1";
port_b_address_clock: string := "clock1";
port_b_write_enable_clock: string := "clock1";
port_b_read_enable_clock: string := "clock1";
port_b_byte_enable_clock: string := "clock1";
port_b_data_out_clock: string := "none";
port_b_data_width: integer := 1;
port_b_address_width: integer := 1;
port_b_byte_enable_mask_width: integer := 1;
port_a_read_during_write_mode: string := "new_data_no_nbe_read";
port_b_read_during_write_mode: string := "new_data_no_nbe_read";
power_up_uninitialized: string := "false";
lpm_type : string := "arriav_ram_block";
lpm_hint : string := "true";
connectivity_checking: string := "off";
mem_init0 : string := "";
mem_init1 : string := "";
mem_init2 : string := "";
mem_init3 : string := "";
mem_init4 : string := "";
port_a_byte_size: integer := 0;
port_b_byte_size: integer := 0;
clk0_input_clock_enable: string := "none";
clk0_core_clock_enable: string := "none";
clk0_output_clock_enable: string := "none";
clk1_input_clock_enable: string := "none";
clk1_core_clock_enable: string := "none";
clk1_output_clock_enable: string := "none";
bist_ena : string := "false";
port_a_address_clear: string := "none";
port_a_data_in_clock: string := "clock0";
port_a_address_clock: string := "clock0";
port_a_write_enable_clock: string := "clock0";
port_a_byte_enable_clock: string := "clock0";
port_a_read_enable_clock: string := "clock0"
);
port(
portadatain : in vl_logic_vector;
portaaddr : in vl_logic_vector;
portawe : in vl_logic;
portare : in vl_logic;
portbdatain : in vl_logic_vector;
portbaddr : in vl_logic_vector;
portbwe : in vl_logic;
portbre : in vl_logic;
clk0 : in vl_logic;
clk1 : in vl_logic;
ena0 : in vl_logic;
ena1 : in vl_logic;
ena2 : in vl_logic;
ena3 : in vl_logic;
clr0 : in vl_logic;
clr1 : in vl_logic;
nerror : in vl_logic;
portabyteenamasks: in vl_logic_vector;
portbbyteenamasks: in vl_logic_vector;
portaaddrstall : in vl_logic;
portbaddrstall : in vl_logic;
devclrn : in vl_logic;
devpor : in vl_logic;
eccstatus : out vl_logic_vector;
portadataout : out vl_logic_vector;
portbdataout : out vl_logic_vector;
dftout : out vl_logic_vector(8 downto 0)
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of operation_mode : constant is 1;
attribute mti_svvh_generic_type of mixed_port_feed_through_mode : constant is 1;
attribute mti_svvh_generic_type of ram_block_type : constant is 1;
attribute mti_svvh_generic_type of logical_ram_name : constant is 1;
attribute mti_svvh_generic_type of init_file : constant is 1;
attribute mti_svvh_generic_type of init_file_layout : constant is 1;
attribute mti_svvh_generic_type of ecc_pipeline_stage_enabled : constant is 1;
attribute mti_svvh_generic_type of enable_ecc : constant is 1;
attribute mti_svvh_generic_type of width_eccstatus : constant is 1;
attribute mti_svvh_generic_type of data_interleave_width_in_bits : constant is 1;
attribute mti_svvh_generic_type of data_interleave_offset_in_bits : constant is 1;
attribute mti_svvh_generic_type of port_a_logical_ram_depth : constant is 1;
attribute mti_svvh_generic_type of port_a_logical_ram_width : constant is 1;
attribute mti_svvh_generic_type of port_a_first_address : constant is 1;
attribute mti_svvh_generic_type of port_a_last_address : constant is 1;
attribute mti_svvh_generic_type of port_a_first_bit_number : constant is 1;
attribute mti_svvh_generic_type of port_a_data_out_clear : constant is 1;
attribute mti_svvh_generic_type of port_a_data_out_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_data_width : constant is 1;
attribute mti_svvh_generic_type of port_a_address_width : constant is 1;
attribute mti_svvh_generic_type of port_a_byte_enable_mask_width : constant is 1;
attribute mti_svvh_generic_type of port_b_logical_ram_depth : constant is 1;
attribute mti_svvh_generic_type of port_b_logical_ram_width : constant is 1;
attribute mti_svvh_generic_type of port_b_first_address : constant is 1;
attribute mti_svvh_generic_type of port_b_last_address : constant is 1;
attribute mti_svvh_generic_type of port_b_first_bit_number : constant is 1;
attribute mti_svvh_generic_type of port_b_address_clear : constant is 1;
attribute mti_svvh_generic_type of port_b_data_out_clear : constant is 1;
attribute mti_svvh_generic_type of port_b_data_in_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_address_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_write_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_read_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_byte_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_data_out_clock : constant is 1;
attribute mti_svvh_generic_type of port_b_data_width : constant is 1;
attribute mti_svvh_generic_type of port_b_address_width : constant is 1;
attribute mti_svvh_generic_type of port_b_byte_enable_mask_width : constant is 1;
attribute mti_svvh_generic_type of port_a_read_during_write_mode : constant is 1;
attribute mti_svvh_generic_type of port_b_read_during_write_mode : constant is 1;
attribute mti_svvh_generic_type of power_up_uninitialized : constant is 1;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
attribute mti_svvh_generic_type of lpm_hint : constant is 1;
attribute mti_svvh_generic_type of connectivity_checking : constant is 1;
attribute mti_svvh_generic_type of mem_init0 : constant is 1;
attribute mti_svvh_generic_type of mem_init1 : constant is 1;
attribute mti_svvh_generic_type of mem_init2 : constant is 1;
attribute mti_svvh_generic_type of mem_init3 : constant is 1;
attribute mti_svvh_generic_type of mem_init4 : constant is 1;
attribute mti_svvh_generic_type of port_a_byte_size : constant is 1;
attribute mti_svvh_generic_type of port_b_byte_size : constant is 1;
attribute mti_svvh_generic_type of clk0_input_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk0_core_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk0_output_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk1_input_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk1_core_clock_enable : constant is 1;
attribute mti_svvh_generic_type of clk1_output_clock_enable : constant is 1;
attribute mti_svvh_generic_type of bist_ena : constant is 1;
attribute mti_svvh_generic_type of port_a_address_clear : constant is 1;
attribute mti_svvh_generic_type of port_a_data_in_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_address_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_write_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_byte_enable_clock : constant is 1;
attribute mti_svvh_generic_type of port_a_read_enable_clock : constant is 1;
end generic_m10k;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: config
-- File: config.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: GRLIB Global configuration package. Can be overriden
-- by local config packages in template designs.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
package config is
-- AHBDW - AHB data with
--
-- Valid values are 32, 64, 128 and 256
--
-- The value here sets the width of the AMBA AHB data vectors for all
-- cores in the library.
--
constant CFG_AHBDW : integer := 64;
-- CORE_ACDM - Enable AMBA Compliant Data Muxing in cores
--
-- Valid values are 0 and 1
--
-- 0: All GRLIB cores that use the ahbread* programs defined in this package
-- will read their data from the low part of the AHB data vector.
--
-- 1: All GRLIB cores that use the ahbread* programs defined in this package
-- will select valid data, as defined in the AMBA AHB standard, from the
-- AHB data vectors based on the address input. If a core uses a function
-- that does not have the address input, a failure will be asserted.
--
constant CFG_AHB_ACDM : integer := 0;
-- GRLIB_CONFIG_ARRAY - Array of configuration values
--
-- The length of this array and the meaning of different positions is defined
-- in the grlib.config_types package.
constant GRLIB_CONFIG_ARRAY : grlib_config_array_type := (
grlib_debug_level => 0,
grlib_debug_mask => 0,
grlib_techmap_strict_ram => 0,
others => 0);
end;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_mm2s_basic_wrap.vhd
--
-- Description:
-- This file implements the DataMover MM2S Basic Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- axi_sg Library Modules
library axi_sg_v4_1_3;
use axi_sg_v4_1_3.axi_sg_reset;
use axi_sg_v4_1_3.axi_sg_cmd_status;
use axi_sg_v4_1_3.axi_sg_scc;
use axi_sg_v4_1_3.axi_sg_addr_cntl;
use axi_sg_v4_1_3.axi_sg_rddata_cntl;
use axi_sg_v4_1_3.axi_sg_rd_status_cntl;
use axi_sg_v4_1_3.axi_sg_skid_buf;
-------------------------------------------------------------------------------
entity axi_sg_mm2s_basic_wrap is
generic (
C_INCLUDE_MM2S : Integer range 0 to 2 := 2;
-- Specifies the type of MM2S function to include
-- 0 = Omit MM2S functionality
-- 1 = Full MM2S Functionality
-- 2 = Basic MM2S functionality
C_MM2S_ARID : Integer range 0 to 255 := 8;
-- Specifies the constant value to output on
-- the ARID output port
C_MM2S_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the MM2S ID port
C_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_MM2S_MDATA_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_MM2S_SDATA_WIDTH : Integer range 8 to 64 := 32;
-- Specifies the width of the MM2S Master Stream Data
-- Channel data bus
C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit MM2S Status FIFO
-- 1 = Include MM2S Status FIFO
C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 1;
-- Specifies the depth of the MM2S Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the MM2S function
-- 0 = Omit DRE
-- 1 = Include DRE
C_MM2S_BURST_SIZE : Integer range 16 to 64 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the MM2S function
C_MM2S_BTT_USED : Integer range 8 to 23 := 16;
-- Specifies the number of bits used from the BTT field
-- of the input Command Word of the MM2S Command Interface
C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1;
-- This parameter specifies the depth of the MM2S internal
-- child command queues in the Read Address Controller and
-- the Read Data Controller. Increasing this value will
-- allow more Read Addresses to be issued to the AXI4 Read
-- Address Channel before receipt of the associated read
-- data on the Read Data Channel.
C_ENABLE_MULTI_CHANNEL : Integer range 0 to 1 := 1;
C_ENABLE_EXTRA_FIELD : integer range 0 to 1 := 0;
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- MM2S Primary Clock and Reset inputs -----------------------
mm2s_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- MM2S Primary Reset input --
mm2s_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
sg_ctl : in std_logic_vector (7 downto 0);
-- MM2S Halt request input control ---------------------------
mm2s_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- MM2S Halt Complete status flag --
mm2s_halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
--------------------------------------------------------------
-- Error discrete output -------------------------------------
mm2s_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------------------
-- Optional MM2S Command and Status Clock and Reset ----------
-- These are used when C_MM2S_STSCMD_IS_ASYNC = 1 --
mm2s_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
mm2s_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -------------------------------------------------
mm2s_cmd_wvalid : in std_logic; --
mm2s_cmd_wready : out std_logic; --
mm2s_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(1+C_ENABLE_MULTI_CHANNEL)*C_MM2S_ADDR_WIDTH+36)-1 downto 0); --
----------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) -----------------
mm2s_sts_wvalid : out std_logic; --
mm2s_sts_wready : in std_logic; --
mm2s_sts_wdata : out std_logic_vector(7 downto 0); --
mm2s_sts_wstrb : out std_logic_vector(0 downto 0); --
mm2s_sts_wlast : out std_logic; --
-------------------------------------------------------------
-- Address Posting contols ----------------------------------
mm2s_allow_addr_req : in std_logic; --
mm2s_addr_req_posted : out std_logic; --
mm2s_rd_xfer_cmplt : out std_logic; --
-------------------------------------------------------------
-- MM2S AXI Address Channel I/O --------------------------------------
mm2s_arid : out std_logic_vector(C_MM2S_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
mm2s_araddr : out std_logic_vector(C_MM2S_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
mm2s_arlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
mm2s_arsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
mm2s_arburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
mm2s_arprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
mm2s_arcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel CACHE output --
mm2s_aruser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel USER output --
--
mm2s_arvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
mm2s_arready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -------
-- addr2axi_alock : out std_logic_vector(2 downto 0); --
-- addr2axi_acache : out std_logic_vector(4 downto 0); --
-- addr2axi_aqos : out std_logic_vector(3 downto 0); --
-- addr2axi_aregion : out std_logic_vector(3 downto 0); --
-------------------------------------------------------------------
-- MM2S AXI MMap Read Data Channel I/O ------------------------------------------
mm2s_rdata : In std_logic_vector(C_MM2S_MDATA_WIDTH-1 downto 0); --
mm2s_rresp : In std_logic_vector(1 downto 0); --
mm2s_rlast : In std_logic; --
mm2s_rvalid : In std_logic; --
mm2s_rready : Out std_logic; --
----------------------------------------------------------------------------------
-- MM2S AXI Master Stream Channel I/O -----------------------------------------------
mm2s_strm_wdata : Out std_logic_vector(C_MM2S_SDATA_WIDTH-1 downto 0); --
mm2s_strm_wstrb : Out std_logic_vector((C_MM2S_SDATA_WIDTH/8)-1 downto 0); --
mm2s_strm_wlast : Out std_logic; --
mm2s_strm_wvalid : Out std_logic; --
mm2s_strm_wready : In std_logic; --
--------------------------------------------------------------------------------------
-- Testing Support I/O --------------------------------------------
mm2s_dbg_sel : in std_logic_vector( 3 downto 0); --
mm2s_dbg_data : out std_logic_vector(31 downto 0) --
-------------------------------------------------------------------
);
end entity axi_sg_mm2s_basic_wrap;
architecture implementation of axi_sg_mm2s_basic_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function Declarations ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: func_calc_rdmux_sel_bits
--
-- Function Description:
-- This function calculates the number of address bits needed for
-- the Read data mux select control.
--
-------------------------------------------------------------------
function func_calc_rdmux_sel_bits (mmap_dwidth_value : integer) return integer is
Variable num_addr_bits_needed : Integer range 1 to 5 := 1;
begin
case mmap_dwidth_value is
when 32 =>
num_addr_bits_needed := 2;
-- coverage off
when 64 =>
num_addr_bits_needed := 3;
when 128 =>
num_addr_bits_needed := 4;
when others => -- 256 bits
num_addr_bits_needed := 5;
-- coverage on
end case;
Return (num_addr_bits_needed);
end function func_calc_rdmux_sel_bits;
-- Constant Declarations ----------------------------------------
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant INCLUDE_MM2S : integer range 0 to 2 := 2;
Constant MM2S_ARID_VALUE : integer range 0 to 255 := C_MM2S_ARID;
Constant MM2S_ARID_WIDTH : integer range 1 to 8 := C_MM2S_ID_WIDTH;
Constant MM2S_ADDR_WIDTH : integer range 32 to 64 := C_MM2S_ADDR_WIDTH;
Constant MM2S_MDATA_WIDTH : integer range 32 to 256 := C_MM2S_MDATA_WIDTH;
Constant MM2S_SDATA_WIDTH : integer range 8 to 256 := C_MM2S_SDATA_WIDTH;
Constant MM2S_CMD_WIDTH : integer := (C_TAG_WIDTH+C_MM2S_ADDR_WIDTH+32);
Constant MM2S_STS_WIDTH : integer := 8; -- always 8 for MM2S
Constant INCLUDE_MM2S_STSFIFO : integer range 0 to 1 := 1;
Constant MM2S_STSCMD_FIFO_DEPTH : integer range 1 to 64 := 1;
Constant MM2S_STSCMD_IS_ASYNC : integer range 0 to 1 := 0;
Constant INCLUDE_MM2S_DRE : integer range 0 to 1 := 0;
Constant DRE_ALIGN_WIDTH : integer range 1 to 3 := 2;
Constant MM2S_BURST_SIZE : integer range 16 to 256 := 16;
Constant RD_ADDR_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH;
Constant RD_DATA_CNTL_FIFO_DEPTH : integer range 1 to 30 := C_MM2S_ADDR_PIPE_DEPTH;
Constant SEL_ADDR_WIDTH : integer := func_calc_rdmux_sel_bits(MM2S_MDATA_WIDTH);
Constant DRE_ALIGN_ZEROS : std_logic_vector(DRE_ALIGN_WIDTH-1 downto 0) := (others => '0');
-- obsoleted Constant DISABLE_WAIT_FOR_DATA : integer := 0;
-- Signal Declarations ------------------------------------------
signal sig_cmd_stat_rst_user : std_logic := '0';
signal sig_cmd_stat_rst_int : std_logic := '0';
signal sig_mmap_rst : std_logic := '0';
signal sig_stream_rst : std_logic := '0';
signal sig_mm2s_cmd_wdata : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0);
signal sig_mm2s_cache_data : std_logic_vector(7 downto 0);
signal sig_cmd2mstr_command : std_logic_vector(MM2S_CMD_WIDTH-1 downto 0) := (others => '0');
signal sig_cmd2mstr_cmd_valid : std_logic := '0';
signal sig_mst2cmd_cmd_ready : std_logic := '0';
signal sig_mstr2addr_addr : std_logic_vector(MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2addr_size : std_logic_vector(2 downto 0) := (others => '0');
signal sig_mstr2addr_burst : std_logic_vector(1 downto 0) := (others => '0');
signal sig_mstr2addr_cache : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_user : std_logic_vector(3 downto 0) := (others => '0');
signal sig_mstr2addr_cmd_cmplt : std_logic := '0';
signal sig_mstr2addr_calc_error : std_logic := '0';
signal sig_mstr2addr_cmd_valid : std_logic := '0';
signal sig_addr2mstr_cmd_ready : std_logic := '0';
signal sig_mstr2data_saddr_lsb : std_logic_vector(SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2data_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_mstr2data_strt_strb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_last_strb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_mstr2data_drr : std_logic := '0';
signal sig_mstr2data_eof : std_logic := '0';
signal sig_mstr2data_sequential : std_logic := '0';
signal sig_mstr2data_calc_error : std_logic := '0';
signal sig_mstr2data_cmd_cmplt : std_logic := '0';
signal sig_mstr2data_cmd_valid : std_logic := '0';
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_addr2data_addr_posted : std_logic := '0';
signal sig_data2all_dcntlr_halted : std_logic := '0';
signal sig_addr2rsc_calc_error : std_logic := '0';
signal sig_addr2rsc_cmd_fifo_empty : std_logic := '0';
signal sig_data2rsc_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2rsc_calc_err : std_logic := '0';
signal sig_data2rsc_okay : std_logic := '0';
signal sig_data2rsc_decerr : std_logic := '0';
signal sig_data2rsc_slverr : std_logic := '0';
signal sig_data2rsc_cmd_cmplt : std_logic := '0';
signal sig_rsc2data_ready : std_logic := '0';
signal sig_data2rsc_valid : std_logic := '0';
signal sig_calc2dm_calc_err : std_logic := '0';
signal sig_data2skid_wvalid : std_logic := '0';
signal sig_data2skid_wready : std_logic := '0';
signal sig_data2skid_wdata : std_logic_vector(MM2S_SDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_data2skid_wstrb : std_logic_vector((MM2S_SDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_data2skid_wlast : std_logic := '0';
signal sig_rsc2stat_status : std_logic_vector(MM2S_STS_WIDTH-1 downto 0) := (others => '0');
signal sig_stat2rsc_status_ready : std_logic := '0';
signal sig_rsc2stat_status_valid : std_logic := '0';
signal sig_rsc2mstr_halt_pipe : std_logic := '0';
signal sig_mstr2data_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_mstr2addr_tag : std_logic_vector(C_TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_dbg_data_mux_out : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_0 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_dbg_data_1 : std_logic_vector(31 downto 0) := (others => '0');
signal sig_rst2all_stop_request : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_addr2rst_stop_cmplt : std_logic := '0';
signal sig_data2addr_stop_req : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_cache2mstr_command : std_logic_vector (7 downto 0) := (others => '0');
signal mm2s_arcache_int : std_logic_vector (3 downto 0);
begin --(architecture implementation)
-- Debug Support ------------------------------------------
mm2s_dbg_data <= sig_dbg_data_mux_out;
-- Note that only the mm2s_dbg_sel(0) is used at this time
sig_dbg_data_mux_out <= sig_dbg_data_1
When (mm2s_dbg_sel(0) = '1')
else sig_dbg_data_0 ;
sig_dbg_data_0 <= X"BEEF2222" ; -- 32 bit Constant indicating MM2S Basic type
sig_dbg_data_1(0) <= sig_cmd_stat_rst_user ;
sig_dbg_data_1(1) <= sig_cmd_stat_rst_int ;
sig_dbg_data_1(2) <= sig_mmap_rst ;
sig_dbg_data_1(3) <= sig_stream_rst ;
sig_dbg_data_1(4) <= sig_cmd2mstr_cmd_valid ;
sig_dbg_data_1(5) <= sig_mst2cmd_cmd_ready ;
sig_dbg_data_1(6) <= sig_stat2rsc_status_ready;
sig_dbg_data_1(7) <= sig_rsc2stat_status_valid;
sig_dbg_data_1(11 downto 8) <= sig_data2rsc_tag ; -- Current TAG of active data transfer
sig_dbg_data_1(15 downto 12) <= sig_rsc2stat_status(3 downto 0); -- Internal status tag field
sig_dbg_data_1(16) <= sig_rsc2stat_status(4) ; -- Internal error
sig_dbg_data_1(17) <= sig_rsc2stat_status(5) ; -- Decode Error
sig_dbg_data_1(18) <= sig_rsc2stat_status(6) ; -- Slave Error
sig_dbg_data_1(19) <= sig_rsc2stat_status(7) ; -- OKAY
sig_dbg_data_1(20) <= sig_stat2rsc_status_ready ; -- Status Ready Handshake
sig_dbg_data_1(21) <= sig_rsc2stat_status_valid ; -- Status Valid Handshake
-- Spare bits in debug1
sig_dbg_data_1(31 downto 22) <= (others => '0') ; -- spare bits
GEN_CACHE : if (C_ENABLE_MULTI_CHANNEL = 0) generate
begin
-- Cache signal tie-off
mm2s_arcache <= "0011"; -- Per Interface-X guidelines for Masters
mm2s_aruser <= "0000"; -- Per Interface-X guidelines for Masters
sig_mm2s_cache_data <= (others => '0'); --mm2s_cmd_wdata(103 downto 96);
end generate GEN_CACHE;
GEN_CACHE2 : if (C_ENABLE_MULTI_CHANNEL = 1) generate
begin
-- Cache signal tie-off
mm2s_arcache <= sg_ctl (3 downto 0); -- SG Cache from register
mm2s_aruser <= sg_ctl (7 downto 4); -- Per Interface-X guidelines for Masters
sig_mm2s_cache_data <= mm2s_cmd_wdata(103 downto 96);
end generate GEN_CACHE2;
-- Cache signal tie-off
-- Internal error output discrete ------------------------------
mm2s_err <= sig_calc2dm_calc_err;
-- Rip the used portion of the Command Interface Command Data
-- and throw away the padding
sig_mm2s_cmd_wdata <= mm2s_cmd_wdata(MM2S_CMD_WIDTH-1 downto 0);
------------------------------------------------------------
-- Instance: I_RESET
--
-- Description:
-- Reset Block
--
------------------------------------------------------------
I_RESET : entity axi_sg_v4_1_3.axi_sg_reset
generic map (
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC
)
port map (
primary_aclk => mm2s_aclk ,
primary_aresetn => mm2s_aresetn ,
secondary_awclk => mm2s_cmdsts_awclk ,
secondary_aresetn => mm2s_cmdsts_aresetn ,
halt_req => mm2s_halt ,
halt_cmplt => mm2s_halt_cmplt ,
flush_stop_request => sig_rst2all_stop_request ,
data_cntlr_stopped => sig_data2rst_stop_cmplt ,
addr_cntlr_stopped => sig_addr2rst_stop_cmplt ,
aux1_stopped => LOGIC_HIGH ,
aux2_stopped => LOGIC_HIGH ,
cmd_stat_rst_user => sig_cmd_stat_rst_user ,
cmd_stat_rst_int => sig_cmd_stat_rst_int ,
mmap_rst => sig_mmap_rst ,
stream_rst => sig_stream_rst
);
------------------------------------------------------------
-- Instance: I_CMD_STATUS
--
-- Description:
-- Command and Status Interface Block
--
------------------------------------------------------------
I_CMD_STATUS : entity axi_sg_v4_1_3.axi_sg_cmd_status
generic map (
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_INCLUDE_STSFIFO => INCLUDE_MM2S_STSFIFO ,
C_STSCMD_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH ,
C_STSCMD_IS_ASYNC => MM2S_STSCMD_IS_ASYNC ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
primary_aclk => mm2s_aclk ,
secondary_awclk => mm2s_cmdsts_awclk ,
user_reset => sig_cmd_stat_rst_user ,
internal_reset => sig_cmd_stat_rst_int ,
cmd_wvalid => mm2s_cmd_wvalid ,
cmd_wready => mm2s_cmd_wready ,
cmd_wdata => sig_mm2s_cmd_wdata ,
cache_data => sig_mm2s_cache_data ,
sts_wvalid => mm2s_sts_wvalid ,
sts_wready => mm2s_sts_wready ,
sts_wdata => mm2s_sts_wdata ,
sts_wstrb => mm2s_sts_wstrb ,
sts_wlast => mm2s_sts_wlast ,
cmd2mstr_command => sig_cmd2mstr_command ,
mst2cmd_cmd_valid => sig_cmd2mstr_cmd_valid ,
cmd2mstr_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2stat_status => sig_rsc2stat_status ,
stat2mstr_status_ready => sig_stat2rsc_status_ready ,
mst2stst_status_valid => sig_rsc2stat_status_valid
);
------------------------------------------------------------
-- Instance: I_RD_STATUS_CNTLR
--
-- Description:
-- Read Status Controller Block
--
------------------------------------------------------------
I_RD_STATUS_CNTLR : entity axi_sg_v4_1_3.axi_sg_rd_status_cntl
generic map (
C_STS_WIDTH => MM2S_STS_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
calc2rsc_calc_error => sig_calc2dm_calc_err ,
addr2rsc_calc_error => sig_addr2rsc_calc_error ,
addr2rsc_fifo_empty => sig_addr2rsc_cmd_fifo_empty ,
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_error => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2stat_status => sig_rsc2stat_status ,
stat2rsc_status_ready => sig_stat2rsc_status_ready ,
rsc2stat_status_valid => sig_rsc2stat_status_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_MSTR_SCC
--
-- Description:
-- Simple Command Calculator Block
--
------------------------------------------------------------
I_MSTR_SCC : entity axi_sg_v4_1_3.axi_sg_scc
generic map (
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_MAX_BURST_LEN => C_MM2S_BURST_SIZE ,
C_CMD_WIDTH => MM2S_CMD_WIDTH ,
C_ENABLE_EXTRA_FIELD => C_ENABLE_EXTRA_FIELD ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
-- Clock input
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
cmd2mstr_command => sig_cmd2mstr_command ,
cache2mstr_command => sig_cache2mstr_command ,
cmd2mstr_cmd_valid => sig_cmd2mstr_cmd_valid ,
mst2cmd_cmd_ready => sig_mst2cmd_cmd_ready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_sof => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
calc_error => sig_calc2dm_calc_err
);
------------------------------------------------------------
-- Instance: I_ADDR_CNTL
--
-- Description:
-- Address Controller Block
--
------------------------------------------------------------
I_ADDR_CNTL : entity axi_sg_v4_1_3.axi_sg_addr_cntl
generic map (
-- obsoleted C_ENABlE_WAIT_FOR_DATA => DISABLE_WAIT_FOR_DATA ,
--C_ADDR_FIFO_DEPTH => MM2S_STSCMD_FIFO_DEPTH ,
C_ADDR_FIFO_DEPTH => RD_ADDR_CNTL_FIFO_DEPTH ,
C_ADDR_WIDTH => MM2S_ADDR_WIDTH ,
C_ADDR_ID => MM2S_ARID_VALUE ,
C_ADDR_ID_WIDTH => MM2S_ARID_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH
)
port map (
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
addr2axi_aid => mm2s_arid ,
addr2axi_aaddr => mm2s_araddr ,
addr2axi_alen => mm2s_arlen ,
addr2axi_asize => mm2s_arsize ,
addr2axi_aburst => mm2s_arburst ,
addr2axi_aprot => mm2s_arprot ,
addr2axi_avalid => mm2s_arvalid ,
addr2axi_acache => open ,
addr2axi_auser => open ,
axi2addr_aready => mm2s_arready ,
mstr2addr_tag => sig_mstr2addr_tag ,
mstr2addr_addr => sig_mstr2addr_addr ,
mstr2addr_len => sig_mstr2addr_len ,
mstr2addr_size => sig_mstr2addr_size ,
mstr2addr_burst => sig_mstr2addr_burst ,
mstr2addr_cache => sig_mstr2addr_cache ,
mstr2addr_user => sig_mstr2addr_user ,
mstr2addr_cmd_cmplt => sig_mstr2addr_cmd_cmplt ,
mstr2addr_calc_error => sig_mstr2addr_calc_error ,
mstr2addr_cmd_valid => sig_mstr2addr_cmd_valid ,
addr2mstr_cmd_ready => sig_addr2mstr_cmd_ready ,
addr2rst_stop_cmplt => sig_addr2rst_stop_cmplt ,
allow_addr_req => mm2s_allow_addr_req ,
addr_req_posted => mm2s_addr_req_posted ,
addr2data_addr_posted => sig_addr2data_addr_posted ,
data2addr_data_rdy => LOGIC_LOW ,
data2addr_stop_req => sig_data2addr_stop_req ,
addr2stat_calc_error => sig_addr2rsc_calc_error ,
addr2stat_cmd_fifo_empty => sig_addr2rsc_cmd_fifo_empty
);
------------------------------------------------------------
-- Instance: I_RD_DATA_CNTL
--
-- Description:
-- Read Data Controller Block
--
------------------------------------------------------------
I_RD_DATA_CNTL : entity axi_sg_v4_1_3.axi_sg_rddata_cntl
generic map (
C_INCLUDE_DRE => INCLUDE_MM2S_DRE ,
C_ALIGN_WIDTH => DRE_ALIGN_WIDTH ,
C_SEL_ADDR_WIDTH => SEL_ADDR_WIDTH ,
C_DATA_CNTL_FIFO_DEPTH => RD_DATA_CNTL_FIFO_DEPTH ,
C_MMAP_DWIDTH => MM2S_MDATA_WIDTH ,
C_STREAM_DWIDTH => MM2S_SDATA_WIDTH ,
C_TAG_WIDTH => C_TAG_WIDTH ,
C_FAMILY => C_FAMILY
)
port map (
-- Clock and Reset -----------------------------------
primary_aclk => mm2s_aclk ,
mmap_reset => sig_mmap_rst ,
-- Soft Shutdown Interface -----------------------------
rst2data_stop_request => sig_rst2all_stop_request ,
data2addr_stop_req => sig_data2addr_stop_req ,
data2rst_stop_cmplt => sig_data2rst_stop_cmplt ,
-- External Address Pipelining Contol support
mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt ,
-- AXI Read Data Channel I/O -------------------------------
mm2s_rdata => mm2s_rdata ,
mm2s_rresp => mm2s_rresp ,
mm2s_rlast => mm2s_rlast ,
mm2s_rvalid => mm2s_rvalid ,
mm2s_rready => mm2s_rready ,
-- MM2S DRE Control -----------------------------------
mm2s_dre_new_align => open ,
mm2s_dre_use_autodest => open ,
mm2s_dre_src_align => open ,
mm2s_dre_dest_align => open ,
mm2s_dre_flush => open ,
-- AXI Master Stream -----------------------------------
mm2s_strm_wvalid => mm2s_strm_wvalid ,
mm2s_strm_wready => mm2s_strm_wready ,
mm2s_strm_wdata => mm2s_strm_wdata ,
mm2s_strm_wstrb => mm2s_strm_wstrb ,
mm2s_strm_wlast => mm2s_strm_wlast ,
-- MM2S Store and Forward Supplimental Control -----------
mm2s_data2sf_cmd_cmplt => open ,
-- Command Calculator Interface --------------------------
mstr2data_tag => sig_mstr2data_tag ,
mstr2data_saddr_lsb => sig_mstr2data_saddr_lsb ,
mstr2data_len => sig_mstr2data_len ,
mstr2data_strt_strb => sig_mstr2data_strt_strb ,
mstr2data_last_strb => sig_mstr2data_last_strb ,
mstr2data_drr => sig_mstr2data_drr ,
mstr2data_eof => sig_mstr2data_eof ,
mstr2data_sequential => LOGIC_LOW ,
mstr2data_calc_error => sig_mstr2data_calc_error ,
mstr2data_cmd_cmplt => sig_mstr2data_cmd_cmplt ,
mstr2data_cmd_valid => sig_mstr2data_cmd_valid ,
data2mstr_cmd_ready => sig_data2mstr_cmd_ready ,
mstr2data_dre_src_align => DRE_ALIGN_ZEROS ,
mstr2data_dre_dest_align => DRE_ALIGN_ZEROS ,
-- Address Controller Interface --------------------------
addr2data_addr_posted => sig_addr2data_addr_posted ,
-- Data Controller Halted Status
data2all_dcntlr_halted => sig_data2all_dcntlr_halted,
-- Output Stream Skid Buffer Halt control
data2skid_halt => sig_data2skid_halt ,
-- Read Status Controller Interface --------------------------
data2rsc_tag => sig_data2rsc_tag ,
data2rsc_calc_err => sig_data2rsc_calc_err ,
data2rsc_okay => sig_data2rsc_okay ,
data2rsc_decerr => sig_data2rsc_decerr ,
data2rsc_slverr => sig_data2rsc_slverr ,
data2rsc_cmd_cmplt => sig_data2rsc_cmd_cmplt ,
rsc2data_ready => sig_rsc2data_ready ,
data2rsc_valid => sig_data2rsc_valid ,
rsc2mstr_halt_pipe => sig_rsc2mstr_halt_pipe
);
------------------------------------------------------------
-- Instance: I_MM2S_SKID_BUF
--
-- Description:
-- Instance for the MM2S Skid Buffer which provides for
-- registerd Master Stream outputs and supports bi-dir
-- throttling.
--
------------------------------------------------------------
-- I_MM2S_SKID_BUF : entity axi_sg_v4_1_3.axi_sg_skid_buf
-- generic map (
--
-- C_WDATA_WIDTH => MM2S_SDATA_WIDTH
--
-- )
-- port map (
--
-- -- System Ports
-- aclk => mm2s_aclk ,
-- arst => sig_stream_rst ,
--
-- -- Shutdown control (assert for 1 clk pulse)
-- skid_stop => sig_data2skid_halt ,
--
-- -- Slave Side (Stream Data Input)
-- s_valid => sig_data2skid_wvalid ,
-- s_ready => sig_data2skid_wready ,
-- s_data => sig_data2skid_wdata ,
-- s_strb => sig_data2skid_wstrb ,
-- s_last => sig_data2skid_wlast ,
--
-- -- Master Side (Stream Data Output
-- m_valid => mm2s_strm_wvalid ,
-- m_ready => mm2s_strm_wready ,
-- m_data => mm2s_strm_wdata ,
-- m_strb => mm2s_strm_wstrb ,
-- m_last => mm2s_strm_wlast
--
-- );
--
end implementation;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:52:24 10/03/2014
-- Design Name:
-- Module Name: /home/m1/dubiez/Documents/AEO_TP/TP_Bonus/L3TP5/fsm_tb.vhd
-- Project Name: L3TP5
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: fsm
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY fsm_tb IS
END fsm_tb;
ARCHITECTURE behavior OF fsm_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT fsm
PORT(
clk : IN std_logic;
Led_i : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
--Outputs
signal led : std_logic_vector(7 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: fsm PORT MAP (
clk => clk,
led => led
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
|
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
G_GEN_1(3 downto 0) => 3,
G_GEN_2(2 downto 1) => 4,
G_GEN_3 => 5
)
port map (
port_1(3 downto 0) => w_port_1,
port_2 => w_port_2,
port_3(2 downto 1) => w_port_3
);
-- Violations below
U_INST1 : INST1
generic map (
g_gen_1(3 downto 0) => 3,
g_gen_2(2 downto 1) => 4,
g_gen_3 => 5
)
port map (
port_1(3 downto 0) => w_port_1,
port_2 => w_port_2,
port_3(2 downto 1) => w_port_3
);
end architecture ARCH;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2018.2
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity video_scaler_mul_kbM_MulnS_1 is
port (
clk: in std_logic;
ce: in std_logic;
a: in std_logic_vector(28 - 1 downto 0);
b: in std_logic_vector(20 - 1 downto 0);
p: out std_logic_vector(48 - 1 downto 0));
end entity;
architecture behav of video_scaler_mul_kbM_MulnS_1 is
signal tmp_product : std_logic_vector(48 - 1 downto 0);
signal a_i : std_logic_vector(28 - 1 downto 0);
signal b_i : std_logic_vector(20 - 1 downto 0);
signal p_tmp : std_logic_vector(48 - 1 downto 0);
signal a_reg0 : std_logic_vector(28 - 1 downto 0);
signal b_reg0 : std_logic_vector(20 - 1 downto 0);
signal buff0 : std_logic_vector(48 - 1 downto 0);
signal buff1 : std_logic_vector(48 - 1 downto 0);
signal buff2 : std_logic_vector(48 - 1 downto 0);
begin
a_i <= a;
b_i <= b;
p <= p_tmp;
p_tmp <= buff2;
tmp_product <= std_logic_vector(resize(unsigned(std_logic_vector(signed(a_reg0) * signed(b_reg0))), 48));
process(clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
a_reg0 <= a_i;
b_reg0 <= b_i;
buff0 <= tmp_product;
buff1 <= buff0;
buff2 <= buff1;
end if;
end if;
end process;
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity video_scaler_mul_kbM is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of video_scaler_mul_kbM is
component video_scaler_mul_kbM_MulnS_1 is
port (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
p : OUT STD_LOGIC_VECTOR);
end component;
begin
video_scaler_mul_kbM_MulnS_1_U : component video_scaler_mul_kbM_MulnS_1
port map (
clk => clk,
ce => ce,
a => din0,
b => din1,
p => dout);
end architecture;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:59:24 12/02/2017
-- Design Name:
-- Module Name: C:/Users/Kalugy/Documents/xilinx/jummmmmmmm/unionntb.vhd
-- Project Name: jummmmmmmm
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Union
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY unionntb IS
END unionntb;
ARCHITECTURE behavior OF unionntb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Union
PORT(
Clk : IN std_logic;
reset : IN std_logic;
Salidaunion : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal Clk : std_logic := '0';
signal reset : std_logic := '0';
--Outputs
signal Salidaunion : std_logic_vector(31 downto 0);
-- Clock period definitions
constant Clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Union PORT MAP (
Clk => Clk,
reset => reset,
Salidaunion => Salidaunion
);
-- Clock process definitions
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
reset <= '1';
wait for 15 ns;
reset <= '0';
wait for 15 ns;
-- insert stimulus here
wait;
end process;
END;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
Gicn0ANpbkQLuZVExUrJihnUXPAxa1ImeWmqTzxIH62mdjSVlulvhi48IH3C4qAyQlx7nyrTGnKO
aZrh92ceqg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Ykp2msmA/Pi9SGpAkhHXp+LWvGL5x4WDWSZ3GOLqcsxi6Xuib7rImM0SpgG6UKY3bIMMKeu9xjcf
/eelPldDxHIyaoxj1+ITRuMUALLcjvj6WP7HDDwPLZ5krRznXm8lxxwV82spiF+b0EqzDwg6KWwf
bSIPUC3YC5ZK35YlEIQ=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
V+o5jgOQhjvfAyP/f09hwvOp9BBAnkU5DaRefEqWs6cG/XT9KsXqKuruvTFyukXJ+RjJMq0hLekA
tUxfhmOSc98JuhaOXJahe3iMzgk9KyPgZAPFGKi5COTcDjWm1HVb9D7yLmNZ2U2O3HzM7qFErxIW
kTtfGgXX25XMsC54xhIXA1xxePG7UjWYrdWhcrbAshA9LeLH9r3pTVDzdrrPJaaMoceJXiFtM4HD
Tr97ZAUxjQoi+LqwVuedrCCQzKi/0LIc6fcjScm+qdxeH0BnmhiInaIjkFZS7hRsb3RwdUWfKTCt
vBuB6RxyxQ6Jq5iOjRDGitvA0sIQvdKXGrmdxA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
q3Wo4n4K1Lemi+bOQODE3aX0dwXbNN5kPkzkx71l+r4YOt3RTgObzTyasyqCY0foeabUljrdxAJk
gng6IIin0DmDWlag8E83uFutRHF+NyGjn2kPA5q+k9l4h3R7jxuDCYVAsIjCVc/KP0aL+guwX2Y4
csmg4gg3wPr9N+sTkHY=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
e1I9CbotAQ7p4P1/G35hRa5mT0GeD+iuAyp848uYw4w6L3I+8I5Njpc22t2kZB2E1+sN1rTrPH0r
XBiBRmirIkkyeYdCmUt1U9X6ZVtvN4UN0HK28Gc5LLfN/Coas4/NUjcJuINl1XHan1yoQ0sic2m2
9mntBdFVXbnhfQ9FpkMR3RBFm9J6BV0Wou/fclhTcttQLYUmcN+cA8RBen5m1cZmHptDChv7Yd3e
FnjnXLj3civ4pcIJsBAtHS5iGvP42N5ojj8K14ShZI002eGMQLx6tXCi1ISYqebs/F9RkWRNpqDV
MGjJ8Wn2CD3tJDbK0V8JPDSZ/sR1gEiAU4bAqw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 35984)
`protect data_block
vxu1HEy3xhRN+v990cktOAlMDTxFOxwwDTP6OrQWKtVZUrGbwcoq35x7q+RlqT0KWJPpAaqNyGeo
Kc8aju0A35+DhDhFTml2h71m8Skb1V7Xvl0JiwfXZ8mb8MCDL+46jCROTd6t2ywgDJp/I6Kb9xbL
3lXI4E1bLnNiaY9daESA30YWieWFJ8OTK1ENAYPwyioheb+wf429YQWtYPJJRzMHW0UcWmfE6EGe
Ykwk7YFSscZbiPCkVQXVn/lKG3oablcXIOlpN1wuEhwza1xtGuHETUZCL2r9UcB7s5UtB4aJdpVW
bT+aWqI2bKPqnfZEhhOoDMLxLKfDCGohm1E4c5m9Au4WQ5bHEuM7nAh96yNdRyEuy2QuV90TQwpq
MmyOKlyroMei/8rbbtZHRkF5TXnFECsLgs70yaPLDWg4iuRG2YoIMGuqN+Uci8L86bASevdWe74p
ogZk7tEcHtb+N2LWhM7QQQpXwhqtHFJT3V7wvHV6jtYyxmuVGy5eOkM0uDAw/0FLut6mSobbBT1U
L/TD4XM6yJ4asHQDGrbSXGzYOQkwQeTyY3ZufAT+d/NiUf8J3rPPoxEXLxCzzmgaig6q5All5EV5
AuHp68HAqS224ATzpHKxLghWY/Aeg7TUUg8W+3vzrvlSdpfG7F4Gsu+BV36QA3Y1fLFDBupBAHUR
GLb+hBYzk0w0PShBcKxFJFKucl2Elnp+rmgF+L4JohQE2JGx3RkapNkn0VElcHqQKmDfxyt07TMD
4Q0KMpm2//3SxKqW10t5IXRJ00EOivvq/AdLmbIzqeaguJPm1vIYVtr384n051iE/UUkyQMHapXd
Rp+XyLQk39t8bMmXtFnxKtFtBUXHJAi0bVn7WQHpoHlj1lSaaa2S79JoerxTeZPnRNWJ8FFw4Cod
t1MtrvbZHxRIpl43to5scawcr8jJ7rkbruzn88/NkptguoKFzA5gMYgnDeqLU64O6NHrmWo3cndi
zqcMyMEBnFC09SWMSAZ0FoS+5jnNXerijdqQjrWFkMHEHAabOpv5d30IUSG4udbDgNk93WmHsQbX
9KufVVSgSfb9ryNTsR3jGqh8ldE6iaKk7peVGiDOEO1EmrrjZ2CiarSEx1wPkQ5X3sWUW2hirodB
9N8qJQcfBQ2JngMEW75ukXm0HV9FkIscxPYsvlBeZ/xnrPPclyTu6Fc+qfNmzCk06ktFa7jFd17P
23QcNiSucIt5f6r87hqtds63rOCe9+MZXJI8rroVWA6D7XpAt5iQbXmHItuu9qtlpV1YR1XDFF1O
iREn4YCjDJZoh6BAfNd233F36AwtyWz+UEGhPMDll/U5uX/sx3mtr+BB2MtXtBzOGaEh7WYw6lmb
8X8W8O8BU0blJPBL0GDtVxW5jLk8GuHClpcKFBv/8eINkhusJlm5UgcWBN9p1fa3/UQMpj5B6ID8
lVCioY55Qw5i18VzS8BGMNsHn+83upxRvX8oKHHbEavMBg97KHnrVoKf6YlKlKjAOTssfI++pVzq
K3kz4wED4jsp+owQPcgA2VDfc9vRIQrHPH+pCjCrrX9xNz0zpUK0ne2E/dacpVlW+zruvyowGVpL
yKJU7nOUd7y4OHCZb0Ot+jS2sFRGdLHV/+4H9a3Kcn5YWzM8OY2naCsWABxM9KmQHiEwL4pVLypk
oIDFonrFIYDD+y/BSAP81jkUYvW20Z8XUz6SeUzHVLDsGSlzRQwEGOeH3M1cZZgnbrzSrqerZ6di
uXKdEuuY4j/iqN2QNov0z4h4m70mVTOgzQCrnm13A6s06KolmoG++nnPSCbGTvur/KHuDPUZmhCq
NWRtgQ1ccGjBc1vnn67xNeHmsRBljOFosAHSKbhGuGtWN75gaWK62w/SqRu3jCG7e51OQJ2YQAE+
7ip2R14GuKkUNYiHE/8+YLCSJqOzccTnFBtlrrmgP2vYkvVAv+Oi27IUVCufHcL9cU9w8HfCIais
BH68UH48Wc+7BDKEwWimWvbMYCL5LJA/6znB+KWkkz11lzBL4v9nN/0EPYJpGJyNhWERDHl8qQY2
a9JKhkq9ZEJ47LetdoUxNLYz8fVF557l2RuIPVWkpCSA902Lj56yK+8wTVhw3Z1DpTQLYCBPNJxi
2jJgRWLf8JaNTc19Au/TTtoyukZhuGWlnE4sU/+I3ZzPxV6s1exSQ3G1ZZylc9Qxq2FNJR9hKQWM
NDb2XOZZqCC7okXw78B+izuc6oonrH2j1PNiFlJbtaPwtqfhMGQRzvQZ8MMQH23oRvGhslPJzppT
OgZ4zqyL/JDE37kuFyxTCW2B1VzI5e4A20dOslWNEKcRPaWcjySKb/YOxp9fBjyZbTN3IaRK37ki
e028OzM73UUDBV6XtiaMm3sY8CKlJ2AV2f0+kuAIWscZOltS9TlYaJO7VtFaja/AH8YjYn9jRP3V
JYCIWuViY0c0HTdpdWjTE355TIwBo2ZJhuWIaSqK/+on65VnksNuXsvxw3q5UrBzESSqGVxCSv6R
px2mxrTEFxK7XVqC5laNqw2S+Pl21YoGmB6rXYK6fdysT5ku6mmxvfQnHSi8AKWIWyzvOGm3+R7E
wJdEyCsqZo0lot1yeNDu2Yv7UgOEDNL7BFiR9JvcYXzET43gexT+blMewugh6wtnnjxw3DfI3wg2
ByBGzBv/FBno3KegFUMrwtXEKTTr5U9QcIk4btRGKkVFDTW1zjdpeTXdCXNWedCLHmYNP/cYNhTO
p/ymarQE77XVu7wXs5xBMM6+rGzlqBJ2hcgnsU5snEljEcfbdRujrtFrxNrC/xXU2ZoMXYdL/rMz
jxcwc5S0FCUY2NURUrlSVMAXHZ5buuuqvGzfNkekQmkytPQddM1ME5RTLzp97eiHIFABDcqJsy3F
INiTOmvUZ75RVfLBKMG/l41gEVOCsMNhC3cHDMdqyTVefv5/beSsgidkzWBO1XfIknxH2sPpd6iA
kmjhy77C04G6CoADitPz03zV2j+U2OS0Z70p12Ltu04Y5L2HV4R6oYQjYF0u4WA+Z37YfxZhf1qd
+/WuOhNNJT0I3x/FS/u54y2GafCFx2I/zExH5vY3DguwSRJP6LoS1IAY2FBm3wnyOGIB21AnSvzN
VWXQ0XsIwMLBXNEWks7lMzlzkAWLTE+toBuuZVSlEOxHNLm7JNhlevFNchXB3b/vH0IXyOToozhR
EXVipB+UKe6wuupfO7vh4/FoiJnafXUzapAUqFUxcD8tuESCVecJAJNOMiE41AWTYDcdP8rGIvFu
4hUfNl9/XWiiMJKpKh0VF61Rt06t6SwrIc7yByyN0rgnB+a9Dhzi3JJWT3nVNozIYZgDEgqQH0Th
e66F9jtlc96hSM+0RIxuDTPdvVaqY7Lle0DKRNhC59z8vxMBmRzGO559K/N8owttMFK+f5+Yoau3
oPlx67sBNa45grvLqyOnLKHKM7P/p/j6eHXTxJtWkg4vOakVNFtxejA1gVXgOy+R9nkBIcqw72ka
iFEpVRMrQwIuvz7h/0SX7JTmN9NTbOJq+q42akCOg0nVjKSAI11HBtesHtsRba/CiAYS7kKvm+oj
Kcr4jB7RUKa0nn+eeiL56J5GbZCKHYL9bj9Clso9E379SJ39xtCWyH8St/Kx5hmJe+4XHFc9VVBO
xrbuzCKRBpkYsgcHx06/GhIf2XB80nYjUgq4y5R2xxR+u6OiUYaNJfVzt42WcUwKbwllh76+OtwW
UplX7H+wskczmo5E/SXZzJ1QPxTkjITzz5uXOhoJ9sdnm0I50w1Msvt89FmRH/+KzVEUutzXqpY9
nLBBG7r7Pn+fsAmVU3y8fvVT7Yqcji5D59lU+KaIaMslc/OxwY0d6+64ec/2iaSk/0P2GOGA7AzP
RpCtFvyd8+wOLoyJVxrDByA/DoQ/qapZQpTHed/rWaRKYP0krD3KkA3CPkBu/rHG62MkV9oqKbuv
zEPjmVtzRd6EApygoelwF72bAOOSgcYEvadduHHpH8fSR1XQcQ5cv+xQDbvYLTVjSLIoF2fordxR
L3xKTuDyOze1a49tASUOFRJeqZCDFiRw3wW9J5ODOhKgoOWRenG6u0Yk/rJ5TNMsuriBkGfimW8C
WOtcg9itTIhJgjGAOJ1Xxcd2TYrPa3RQ7B3a7VGw+Rboh23NxK4C623KOxWBfvGmwjk78nq/hE1C
CKL7/kJG2aWcLzmLvrIYJU9EjTg6YLA7g74jA13y05SqlgiCZ2EvoI3euR640Roc9SA5Q2jKDhDj
4cUJ78066Ze8tn/42ukE+ff6ROyHBPNC/FFzidElVqkeD+TBZ0sEwNztOAq6tB8bAKUm1vKShwPb
9QsBm+ihrhPGaISOyGe9KcJhC53g+a1Jq/FyyRPtnThkrvUJ+W2g5lZJoypAnos62zcVH23RIZIJ
HQGxq6zYp/S63OIyA6IwdnNXJ7Hhgo1zHKoDM5MOWlYHielaccNGsO4jfkLvXTDrURgGScejst5c
9fuKLYL3w5E7JzNqXEX+/Nt7FZ29We+Q6S6kYHo3HhalXS+N0T8safejIWQLg7IPbB1FToUf+9Z6
AspzTpaPtpMKfZHlu9D3OcMNEvTkDlR1RSNZJ5qDIEsScG/IU/4csG9IczAamLRsGvUNy5FGT+2b
2Y+X2ZH744kv3Cz6d7IynapBTqahs34dANGmR4cCX9qRnLguOBKbxpFOs6lZQtQuYmIO5Hr2ke27
1MbCHq5g9uhGTTaxjuVvK7LOgo8CBCA2/z2R52K9e2HjAIsHY8ESxDD0bnI8oPZVG0BUWPBClFsu
NW3/EGQk6kXNRCz8FgRXArHHMXiCil30Z3Qm1LFwR7Nrutla21E57Xm9MOaOnh6j8sQjFh1DgWNc
ol1lFFRzbpT6qhgovpH9++so3qPWm6ccVKgQnUKyzaJYfPC7yRJNE3IVKdmgD1ARpbeNU3QKWB8M
BJ88locnBikw6N2JW83ul8xU+u/j/G0saC9dUYrgIRRWZJ3HkzF3rH7fCfpvL3Sqhyp0Kh51sAOn
vnsMYnec84nxYaMEfdKEu/8lGVaWDN10ACzXiU2y1oR9rHJWL1Q2BGR3On076sgcE0xpzYE3GX4+
OBvDBZUOnEDd53WAYhC1X24gk8oJbzmKXkrso/XObsCv6Oehy/n4r/PDxEkahxIz70In4Q80kc2V
vbtp5BDO0JhwB2Q8PLc2DXwMMlU8NKriHnpxXRfiO/hIgiFDUJhZm66VAotZMFh65PpDFOWaMeLc
PXIMejxWWbFq1W9DdWo9dVNWltVfW9hnbz3uv/R3L0LGtr+f3P8j0fAyk8rlkNWD91HbLwAxfoYd
h0DkuZD9lNmUdMp8pfyd7qyiR4lq7YuLo1sojeRQljsAWOwUcKQzqtSh90XL3a+zz4XKnyT3EMIE
WCP3+7Ka0keFLzpTn+Aeo9MjvmqFF9oAwxuLD6Eg5TVzA7PWgc3AymrM+x2XHzmQkiO7aj0DXBke
Al4+TXlJHHlhMpixFkczdGfhfMIfHllCYcfFq4AgwM15yNoT7sq0A9ApsOtO7Rmh+43JaT7IVWtj
5yNTwdwopoPfUt8LwZp11Vz0HHuwiqr40W3h8FEp8KxZOgjF5kFOiPwBptcq9ocl+vhqMplqe1jJ
hSiZa1pGfyrFC/aVVpju0qVFPHDGau4XKPnV57aXSilmdUCk3+TYNrFFWBiyEwsI2zHJuwiNjJQK
bcQrvOg25vwQeBkrdtfm+eT0EBh7ckpiIWkmOJIZlH3ypTYbpoa6hGtAbF4bSGk8BEYBiA3QLCPQ
5PQzERZVgwdwPRc6AfxkNle/3Ygu92dF9IhPSUg62g6aGuJFtCvbojSYTRKyAm+OVeef1uAbUxX7
iY3IDkkaZ9CkGFh/R6H28T7NWFjmgoC+vsZfVV38Swoj5a0H8oIiORTZQUKTSJGGmHbM8vIJK8/Z
9IlZapnfMq1KjBZkricRdE/pOaqRWBEY/0mmySiQOi3XqjqSE+9T1sAWG7isYYisu18Br68q696n
tdKQWsEtO04qjZXFu3Mmyln/NXs+7aW2FDaDZ4o8uuLA+IS6aQS1PdMzabcSjcrHebWRwpY3KCv1
kdXzLnJF/dtLvXRFRbYeTiYv/Uh3ivlYd7+D3IjiHIvWdMJ6I7Kcvw9Hy/J8avdtYUX8SdkC0N9A
snw4y6oDOX1Nk1Lf93llIgYJfz+0vzyW4KCVfjFuRUe2HlbPlNH0Qevf+tGgHtG4/Wifetsbc3QE
ryxJJsmBzJJVtI65QCSptTIBiRUT0binxL5t85CIoKyY621S13f6VM0wZharyFd9+vk2y640O1U0
sL3FgKMRyfa8A6Qqz+COTOy6e+ra2ucLqNOXrMr5utE1zGp0P9sWNOj777m3EHXIC+xKMCdCIe5a
IOQ4v6tqOgZtRZe6TTAo8g2rJD69HRuPuJ7jLHb7+za7bYybOW+6bqvGQ4/xc0Jq6szkO2PxSMxJ
dsNhZGAxmD/ySNGMGzChOS+tIStfjRU2UOyMDVxOGbimZl6RSIKZW0KOnbADKY0mQHRV0PkLfKtq
pwi1VpQa0CLaETPFI0rbV1YqZfaedHU618RDLPCcpbnrJclKy5mcY9i9IYqwjbdMyYZSVtQ7KQQP
qX0ZwQCX01Akxvzj0W5jsFXBTwqZ5Pg8QlaKTpP93YDwNdcv5HClvowhOIGPSanaXXg2mnDTEXx1
92wPOGVEQhQm+YCkQ6DY49QIDas68PTR+HR7Erkux4SyRfrSH5ttnHcusua7nlSZzafyj5oWYh0H
6z/+ZeX1W96DRjTJeqqmPOKpVOn0+MgwufmihTuxvVQqxK5sWulkjeRpdoMFbDLHrYtnhB+VJEyh
dlxLsVu6RXw2pR5iQOKUSaxgIhLTBL5cRPDnRiIQUXkMMPEo6j5F8ZneKsC23lvudQCTLGQ0jAHL
K+h5b2tasQzAk5YFSa2s5haSi9MJEXD0HGH8AUkfahjSpk9jnV5Z3+DO5JKenFh0e02avNW1SWou
laZchn5KhA6I920oGBAvXfxkyu/O/Jv6DGJubBTuNq5wyVlrWPWJwxH2bYc85uSUUYoTpCTGa1PO
+HmvSUFHXwEkonY+rpFR8MwoDc2Qo3AiR1iMKyhppqFj6VKaqDJXDGTeBbDwWwgqw+XQnL0ktdki
Q6l0t3pJ0GZi2obhlK7YfFqZl97Phwj4jVfA0J4KM1rczFLHU2sAUlBKrpSX7m2HEbqIpfX447Yl
+cpVESnOU8eqXZ27BYUcTMavAjyuFNov6hje4lKmtD7db8P8jl6UQ1qWcgugq4PgcDFYPvMri7Ih
ibm8nRZkZxrH+ca97We5zBW+m/zBHIs9orq4R1L4P7aNgjB8r8Q4MseKlWyJ2bCebsC570I+xsYF
+yX2joEApqD78I0sCYFpdWgTb6i0XSne5zJtJj63Dh2r8gtUsGzkVZX1FK2ULRvnjtn+Y3YT41Tk
TW2Ohhab/XHLbz8tIaVZmjCNimIxzFOj+fXnEIz5q2KhDM2NpaYNeTbc20CRLwq+jkN9ZYSLVQKq
44pZP2HzcXzd3M+JajLy7FYc3ky4cjtVqVUeVwB10bH9TAfM0oITSgYooAJ5S3D0wL6jqG3AUK13
PN4OfYNZveSmNe3aS4/Xzu/unq+5iW5/4umjIPRC74MrvZ4YxHBAOuDh+Skj3pPyddnnK0lrhJ9c
PuPwT2pOJ6PEeWH6GND2m/piCfN3JhgZtiGWTRIF+5AvUYSXkChSHrf4RFxBtB34iF17BI81M9sp
g5+UjFUditXlYku+cIPtJwb3YC/dRlDWlVsYLmi8cs4azHFTGIW7Rq1tpb+lwv6q+Y09V4vdYAji
yV227wpyCZwNS9waSDNcYcvKLjaa7l21zJyDi+ZGkf/jmybKAi4ppVSLrPlTw03FVZAN6PhOtuDR
BQjBtr/HXjbIcFtXMRSbRucJfTBzEdzWDdUQ8vRHl2tDdr/LNw0VZBAm4dgkdgpcLfsMWx+F+H36
2P7yXZYhFlnCGipg6S9r6gv+DwvWKz8vio9K//zgPRZaltM2X9zEyadX5PEQ3KTxqdUayIs0MVvj
3Bo+HyFClLF7EAVYgGGzVJYqE1SQSTdcoaRhCtTUqf+rZvE5Naz0D/mK3gTfk4dEU3WwvceMwpbh
toaodUTYcZENTEJG0T6sP/AAsBcFo/6GDd6t7ZQE3fUC3bx+8RgiRluIEetfuSJ6yFkWfM/8xKEP
807ZaJ4xNvw24MDkFPcGQqGRMJy9dC0q/8h+IUAnIWvPxylchODTZVGpDo20wCrRlEbhF5FHMtkq
S2OhnnVxJDOhWqfnNFj3q62Pn/vvBfAmef1PPjX57X2oHrMtTjG272rkqY7EBM9GMYqunhnviWX3
RQuD/c8v6Y4SDnwWcAMcZ3AUKNwbvzpY+1Q+VV4GWnsaPLz0kiw+RHBRlMEeCcNX2WJx9HwU2Pyq
UXIsif/fX+nmxrubmHBicP5AfVOanVkGa5kXopXWGoO87CVdfQ31JjIB738QARZ+b4KUmXp33VOb
wKZN6FrruEJMipNenL3UHaR3Hf9BNin+7OtI+GJCiEA51mDtgV4aVNUj3xrJ9JgtiqyJNZ/GNvE7
op3qVk9ZHQgrErrjTznFZI6nKraRmdDSbgrEHXObTP+v1PflA+P52cmUcWLhpvPidd+/KQDtwQuQ
SqDjs4KV+IK2V0eJsV2meOcDXmb03xOhK4AFxrdit/Ebz3xuNut+kngQRHsJqMPtsNCe0QLZcnRM
Wprb4vBygJbbKNO0i3GrsfYesPpRZ1ZDKabfc8ArUEWNOpKmAjfbEirCgGVP5kwWIOFvR56tNbP7
YSLfUWkkXe20+RHCQkgQYbhXN2zTv8IQV4zGDis39LnOsEPzagnw79p6o0ZOBbxXtw1Tb+DUiTFX
DsCsI3v/djv1UUsYAasfK+EPO4tBdWPDWWYgRaBXb4qchMG+aeTJfWnkOoVgRmCjNDdI4j5BtSKN
ZFq6ifVqdjQ+SHXlYdxOSJx7+zYjfWbtsQd6HaCCq4P/7a/+elv31Di2+q+hYnU4WHpCQOYifdZD
ZK9U+JfCYuploZSHm0dJYIFyMVS0Dnswlb/HoZQvRCWCKfw7Si7ml49pL4OvmmMyFe5gb4DIlDOB
h+fxXAlutkBz5UBsZWqguzzMXCJzkJQR20u9UKZ96o/KesogCVRPvQczW3OavCOPcmo1jrTmjPhq
bvwcrrIXSfErSxKKod0otBK9BRI4dBdACuwLjMst+hqmDzCwBxi6f2tYh2xCJFF3KjNR//NggLk3
ZMLIUZO+jBkFCG0ZS9avrKSmEXV7YIGvn4Bw4KFG2qnpZG1zXbloN7OOTIXa7J4mVIHdO/65vXrr
nbheQKw17l1SWSurXUebyrsHb8tZDunPBQlsYVSGgyxXkkWZV4u4q/6mq9ODEUZpCa2Nsz0qPlNZ
3LWrrz1cfrWedNk6aXX31nlJnQ7WYYp7IB9mBjDY3cmgXl2Bs4CaxLcEaXUOLGhyqJsVc3bdaly9
5pDBvWNnF/eLLMHJfqLkSUrSIhLbkdrIpl8LGM+bc+8+dQEhptpXmWdKXXjaWhlhLuhvjpfKNJb/
XBuyWB/7uwFEQaWcwuxheH6PIpWsYshtSqwzX25v1qzOxipIqdmIsPMKipgDiDqtrHkegOuGY3cX
eZHuvr6wyHZHrkuA7FpNCgjRUkilXNG/tFdiF2O33TiX2QlT66jHA/8jrswfn/HDv4vXm3CVo4mU
mRk2jeq5mdCOQvGwWvWvmjryFRDofpc5xCQyzFwxv2+MQnABjvHzWUTqvbYrfphleK9SHwu1DStt
d71b8Dgv7KbteWhdxMjgJK7gXLvRg3MxJ19yxMjM5ChXCoZEWPH4lQpHRSHHHU0IlnU6gbpOxRJb
oehR4FwV/wARidXuNN/NdGIADum5S+h5VgHfRs2Bi9O379rX5404fIcKaEe54m4aRB7Cjro6l3po
2qtoivW/dPmFjXAGJvGb4IKna1jjWI3HuseIYrUEVxnYjP4Ngv8xVIlkrD/v2XCkhOvuIOgBg58d
G94bWrznhUG2WFcDy7Eep98dvsuBfB7/kMmAzcxh2x0TyV5VXYmnJQRxT9H8fSBZ4KhrzScQcgA3
sbFOWaZQu4P6Jz+N6Hoez5bTQjiUfZu2AG9NhDb4cNXcNI8VNa1R0U6HYd4Dd0aNUmoGeB+9kkn9
ENGKJ20gmSdXdgMvGQf+DrnS/O4NtptckO6RQ2n3n/NeDVnzXxKJ7tZXWEpkChmnQ8e1lErd37gd
52ZWoIUlmKU9N5wLLFQvSvUG5MwwZO5BU9k5OiucSXbIzkdiSw9pCKvftt+cCF7KCLYOV3b1n1Jd
G5ILGMu+YtoKEYc2ZC+ArxDldyk3do8c1EjZsSnitxsl4Po9Im5QSstt5VhpnRi4CTRYzfGOFK58
uyRFgVDq6Gv7sxfRlo0OPwdji8JBvTDoU2yvk5xuve5Ivgjqmvj1ZDuL53buv2aQmp2zqizmmpHV
ILm5N7ghlrV6nsRyDrVC3MlP9SWG8WQ12JJ6Q1fM1DkYk+IhywbYWSfMoQdauxHHzbQVyOdIhWTS
/pwwBHeiitFI5cMFoa1lwKr+F5Ydmm4/xPpcyTXXsaA77Bi6uCODkcQNKXmOshzU3xNCsVujz406
o6vJfPXhJv/ERBzhwpxg/jVguE1J7FQpPrI/SqXV1qqecidD20hSrU5i327SIuLbGLkfX79kn3eD
8vGZwsqvFxxv9nEtDPNb+i4fvaRnP1td4/zB1e3ioMr3C4w7AwyEnWn+BwotbOTsZ0IaYPZXPBe2
FH6MBJZzhu73KNJol6lR/sC781RqNvvQMOCd2NuyCx1klJ27aIM5OPSCQmCeSo81RAEXMsBxBLxO
WCTwc6M++FoKrsYHFQamjB6/BbvrK/oqOFuUTaKroXYCX8Jc65EySim+8xwGpaYbzRkoB0k2MbFP
E2hnugikCRHFubxLF5bHZQ/M5oYgFTHj5s8Z7IiZNsR/+4+wl/T6dEnnHuVvzzVzUJ8FOxvN9Y5z
7ODbJbWDbwdWJiKO/MP66erub2jHIDMhy0hrF9LGg7AvGgdVkf9nLOqmvKMH2VRDtxE7ccqFdGcr
L4MWFlYo9n5adTVHTqASTdDp07guvhXMVV2aKM9arNx4DPnleDhupA33jeYfbwhcmD6TSwwUeTOw
cZPC01qLDNYR1OPkqfnzeB086DZN+Akx7Ro6MfQlVG/iIeUKoap8GSnoluHQNgaa/zMQLxwozf9n
nfq9WOtMdhZFW2CJvOS9AFS7FpCmde39lifPnDnamZv8D4g3CR+7BODd6x9gIa46jOlPZV6+EkYj
OhsjyLrti3azU26cvDS1iDEFpzF1x6ZOSVgIzsWpGAZqm2KXR+kWODEbc2kK6810H6YvbuceVwXX
zTtVep3SrMyEQwEEKfU2zNv5LR1YYhAlcsB0TC1GeLhHXu2spuHtrhOXY2Yu8PJ8O5mpE5J9hciy
Jgv9kxjs6V8/VOpySoc+DK6RqWF+1LBHI14Mcc+WTgH2LZifAwuAc4TdLXOnt8Ftm7toeK0GzuSR
n6T+OPDTUNkGZo/TxiHJf92SGdgLQUEhsav25/7sKnYRHXxLyqkOM6Vc4MSuQNbisLbVhx4lGxBh
FZplG3KNyOXk8i8uBsv/q84LzmSJXKwEh9+8icb9v3c9ZHGV9fvkR8Ufs9ZKHPv0eQObFk7rDe7h
vZJVlbN+q2yZKM016zB6QeFHEyxnRfxWQpOEYz3OX1UQzlm0GzfzoInIq6w9EhQe8h9mmZHwFPUz
F54h0Q/34PAsFPUBiL3Dl9tZ/3xn977shr8ZN6vMYO0YYwrsz2lg5mt4npk6mm9N/djIiCoXr1vb
RfmtO/HTXG3r+5vpOfO1eZgppaPgzjpoY+HvUMFul5tI4fwOJczwUS3LAqKHjwSnq0EXsyJ978fO
N24zFPYt0VhaQvePshnGuv+zrHfRaTgPduzyi/qFmwdOhNq6i/IaJXz0zmyjqJcdvXeqe1t70Go4
C0t1jFr3Z/X08PTz5h/sE6mShw6eONf4E5wxQLFzZ27t3nvwq8dMLekzOwWNLgLTu+N0Wv3j4XF+
rvPiXqn8C+PH+qoeWY66jronBiyVRqe4dfLzSYsGRoi+bXI9W8h7P0Hh9eZsxj67AGKylVwhgMMa
GjcyZ3cQCTXtcixdBpTFWskhob2smrY80uKLqleJ8o2E8z7Y2DmhwG5UdYh3yI2mjngfXa6QCdxh
60mUkO1QX1TLKXoA1PfTyCIw+XTkRDUoJkZVh87aZ6NLIvxEcNMKFhN04+T6mVr5m53+syIV8p9B
9x6I+prng4d8Vv/F+iLRl6vy5JJjTIFfN6T7ziZrYnkhhvsCfgRpzJ/WMwCmGOc904GwDj2K+0vv
/vj1P+md1vuAsS1/ylhMIo3c7PTPtNtHLFmHwmRo/Ny5R6zi4+5POftaF4l2xHtjaW2TB+b3/X4Z
hgN0HerPD3uDmzhh+YVWEpOZhKH95p8WOlw6Ah0aq4NRSlDsp+jjlGpBGsvA9UW3LYHnkwCvi7T/
obi6l9V4KEtXZNScKGN86t2wPXS/xPkokKEOKt4/YWspxj45n8GZUHLPbMrsmZZ2xaMZYhxYe1gb
Cdfc+cngj2c1OBKqRCdbD0kh2g8xOv+DtQNAZNSogyrKFM+74UqSKYvtbIoofSsnQrCeVV9CJM9O
ZqVB9JGmmMXgrFgzblDEdkJVWw/zW3qm28m3LtW3b/Pdgmz8BFsAdfAc+tLR+NxLF7wWRhMsU+G6
WW9/gePovVgUl8Z/5Iy055HrU2bBs3uRCNwaOiV8kvGl5vUFFzfY4eZ66kZSORFgUQycZ3vAZa5z
C1SpM2eCayvUL9cJDLu90aeSmHo7Tsk/GsHJyWNkCCqnf0SZxI1dJ2jtbhOO/j4ofcWbxfpEbHQf
y69in0J9xPpdbgqPSRzUp3sFLgJWtgYmi8ChN0BWak5zqJyPSwn9y2jkkd3H9wpjePNRnFsixmIS
GDGUaFRk+DpxxRzElyk0UYQiuRD0M+aaIWWb8m9ZhUhhcZKw5UMBFESu1sxhclBwX6hl1gwSoSBo
CdOjChsOS9sNJoPqoq86ijViriVyD2T3vWbrr35McPMzSvHRs6nAvXaJT4+WrjJOnBK7IMM99KLZ
j0MswSXaibk/bpDKBgJsNsePIRqOQK2UM6RRSFLsE3R+7O6infInPBQIVTKjHDJg/IetPbYnlBXc
f/q2HoFVXxKKNL7MfMjYKfzgIOo7zC4XAPpe//FcknP+77Rmn34/gFskCKHw1gs4a6oSXl9jJFau
hDuKieIUcFkC5FWEH3RgbE8tybIIDzZGzHWF6bmyAukwM+k9i86hB2DshbSYdun5JHJO/T7g1cea
9/apBAEJ5HcINLunq219F5ucVXaOFbAaUA+LpRWJh2PN4U/rz4n1/S45k3merVqxlAG8QRLl7YV9
ocu2s+I3ROf85SMsvOrNjdSWmPAa1IZ+3niuLFYIgyVIldgiX+MpogA3sgdBwucPwd2rtqVJG4rW
GvlQ1eM9Jow7XpsiXE6EEe9Mh44AmgLtrCXZFZYqZdqsxcXVxHbg7CXrhoWw90uW06u08E0s7j3q
mqgJkIetI2v8O740k40Z1bagE4XDG0EmMdAmqbNPfqQNV/zrDFPnjAmODLzKwgibnrxKrdz+mJ/g
0An4ZgHu0EbjCn4/Ae+Cvqyq5hhT2ppACBbKJrm4+MEhJRYJWh+Bq5PsTWjvKcQyQwUtZ+SmKYYv
9loF7My7ejZuzXe3aRDThkhpfdS351Zg4lBdiRZjUPD+pnaGJgfo6XXbo7hI2wWlPJCAQ8HR4chU
lkVnQG9Rooz+U5zg1tmiumT6A+PWWhzs7UcIQYZnmj/crDc/rh1rF3YA7vci1bufuZ6AnLXgyTRV
jL1yjGPxC7AvI1CWnl2zIpcrJMqk67I57muxrZ80bVldUOAGOn3WGA/osOnr1brzTvezRdVZnL/8
lxk9EiSPllAa/rNpaJF+xVZNCe+blb0osNtwlyvfOHJgtA4ijTTjHIpi2Qba3yyQlDvhg4olIC/T
IG7ikgRSq7I3XgMFZa8mSQbTQnvISHzwb2K/VRvIzlzDursENZZ8PEYTuCGnYxNc26bNanqHfiRu
BN3wgs25P5aVe1t7WV7n9ahXzTSoUsrDLbxrR8lD/f/3kK5/C18SPRsh3NDZo23z741z5pWbrXJy
tMS4k6S3rE7dBeLt6AC2JhQI/TXDF6jrFI4MjcZdpYi7Dh4TIQnL1LbbKHp/OuHQV1xnLKU+95DU
ar2eq/tzoxZFlYv2/+Mge/Wi/SIMZWlS8s9wdHbRge8ikrv6RUR8zowqzuQYTIiSvpoFRXCtH0JJ
+HOwbIox/sJ7gfo3FApVLEGT/O4xrjxbF7AwEupkmZpnjKrAum1/vTeM1BQtwrn7jNiYqA5pllFT
WhXpDZq5OMDEXQ2sRxnjnKbiTsZ13w1AhQQonWB+Qg31nQsQUEc4u/nSaQVpl9Vcaf5jPaAl1bsY
Xrc9ATmUsY2LYLHg2ASt5GQ07BsJGjnotNenMYPnO/BOBN1XanK20tGoexKCU8bPFhWD6QstDh03
XgnqCIEp0sO2t1maw5rnhm55Cu/KBRoXnzo/19I9vtf8sRTpTn4UlEiN+2+c583538iv5X8sb14G
daZfCR4BQF54gei0Q4uA2yx62SoA6epIJcXlra3wAe+wCbNdQ9fr16SJyn2NAo46+7sJfuNp9qTi
GziRrymj36HlFZJDQnhgHFYckd6U5rMkBZWi067IdeHJRGX3CDL8x3LkhMwGP7fIo4agbuj4u0cp
1sbhaUjoHfNcEVdKJ7Dk7zt3N5cynxAcZwCt7+6P6CrnD50SO2eZv6vLLZk3ju8uZm7riVAffwke
bMBsOaO5XkC5nr0DCHi6ZJZ5M1ubwjxgNKPF9kWbjD2XKXm5gSS1Y9kXrSxYTfe3FLWbmHpxBTtf
0Vi/fWA2uAWyXLHNSAkWQLfY6OgU1b7RG68T8ZAvE7PYtHx50xwmepB3P7e4wLyXQ8/N5CSq8a95
BGkg+oKHYw9uGi3t2LzEYjnacS7enzup8xNTsgUYNH2iNY6KhWB55ZOz+Gum30EM54yU9jCANg6y
ZLEWPBG8aDFxta+IdfUfN5Q9M6lvKSWY+JiR2/XevswIva9XZC+4axDajDbYpmy59cKGAIlzKNu1
Ds4i5s6L0CVKP/md5ibsj7c4EH3pc9yCjvI79fVTU/svni/hw7mzjEHGdreguTuctePDovY2YwcG
UpCaWbc6Qi1GNPjHRSEFilVOiEyW4HO4GmSigy3BcjEpUIRsoOXN82eQfOvf2+fj1BNu4E4eqkIf
flwSG/TnHzr8MmZN1twpMr5g2iuTtjekQ36S+I6nUzJvrdpboH8sIkADwqhMzMTBMArbsFyIbIG5
DXrmsOpda1vR3mn9BmWJRGFQYqNCjaNjImzDUVbfIbg4fqO4i9oizGrKM1DLAy2LvtpvxDAWvM44
dDlMn92yY0WIKB5ib285dOfGGtm3tBr2h/JCUtl4FtY7aDCWar7xsPOgyrsyTsp2idZFtJzcQxF2
MJjSZ2nVg3vCNsfBBC2UT7ZKSaF0oO7hAKrnlE257hxtYOAYYv8RdOyNQsy8x0yImte5ilWALC7E
LPkvEbr28ftLMiBSZWhqWF2CyVfL0vC9ElUO6ThGSbLHQ9xxhnbSJ2sKr1euB5q7vH7dHGkOYTHP
6pz4Ien0io+31J/JyKGeEkKi/DrHZp9JSOh8V0cRrUXn1PYfvmca4JO5OF9VqqIiZCPwYxYDFyzp
oWitGn7zfZpG+FpmEOltTyRFnomdWOSV2F3F2aBX7DWS+eNcVrWNyB9V52feCHs5Z10+2nOcldrr
3r7ZjjCzw2wHZHSY9G+wntKyY71zEqCyTDdmL3/Sk52k3WrkMgv6m6d6WMgwwr0bU4a3XADvrfkO
I+Ydr6kfqCaMT0tJMfho1U85+zpTJb+9VAWarL+GVWPq+3DmfgyQspS3dT+P3MgDxZZN/W4Gj0q+
9KXEc78KQizRp1Pr6aJ9pPP/3Hqi57VgoPlKv3t/yOI5R2YaUAMvK+upcANqdonw1o5iEdukKEOq
zjYwULOIZJdRuVpmNzJ5y3yY94I793wvgqVi56GscywjEmmRUcjb8cE8X5QxOyq9cNbGazASkyev
5vL23YzfX9Aqb9pa4Ltlr3xSK+Y7mFFLOo2QKXViXhAub3nwEvm6/1+omMQjhMvO2rJz5lZ9sX+B
kq7rIepVvTcRN4IcUR23VK8XUSx1ShMaEtnaUcI4hkaKSK7dfiKLKGRWmH0puKHm8LBzdM+apZHK
udIpkuj6MaF2lGTOoAvqW804HfgrBGUnyq5IO6uNi8SXnowyX6nhHsAWDr14Oob2q84+85Fwdtmd
U3uN0oqO2d2Dpu54WQbRSCLDE5sSaLqhclftuQOLQ+S3mxwQlwKz0DDFbfHbI14cp6vV3729sEq1
0fjOX2F1NMnP+Kp5P8gNQhuomJ/iorjzUZ1+rH/y27wOkVbBnxOg2KJuRVa9Brn+3IlKtWotONOA
8SUw9hh7/c5lM8fsAa/JXEBKJ5U7DkXeib++nu6CJuy5XAnLoM4TGuUyIPF2HGYsjouQ5z0dhHFn
S0wolnJu7Jy4NF7R5/mK1EzrRssw+3QD9yWl3V0OrGuSAGlX1Eo2EsOZVF3YGIfZD1iH/ZFSMPy3
w8PG8o09EziXX6xfFZZ5g+WrY6GZxO9DfWZeSLWUTiAm40BUFMRbJqTnc3CT4VaaOZ6ae81v5hu5
Rl1KR4CHlMKLXrP/MlSc6AOFSScXegZMNP5gk2oLgEoJJgS/1Z0sKmcG8Fen2EL00esflMmQS7Wt
rz2W4pGV5AiO8AJYnhib+aS/GxJGZzcwRPc1sqM3H7FnIXh5d2GYDF4kIPokePUWzAU8nhiYm6mp
ffAWsNg2sk86Zx0e7bMfCU6jrSEnidIK2hr2qu7De0rg54u6wKICYf3oiz0VbH9MoX7n3p78VX29
kubVF0FkeHOc8XbO63v3Z0XuF7hhueUODh7XxJ7nLUY3G9s1vTF5STPPt6ZiXkGWst/ja2MRih4w
zQ0EWXUvkiko4c7SbxIbVLgD08JVNqRXKywDhUII0Yk3SGCsnGpg8yoi7UNoWYEkEatFaALStNRe
0Apk6eZBXgvEfUHN2YKN+5YRdGDPbnPGpvBikUzAfdbi9CyymNoGlob0q71AKDJt5IZFq1COypsM
2pCDHG8+A28z0D4+pty52C2qn9QKxZjaWdYbMnbOwnZPpns2gTFBPTA/km2poVQXc6zv3LcVoNRQ
w+2tZtI4ii2RvnHRZlOJOLge4J70mylCfmNFQ61i27hluKiNe9kQ2eqjcX+y0DVPa8NiCRT2BsoS
Ay85RJdaAIjj2rexYS3H/HWL0wWcDYg/s/a/Zt3vaarMmsP2fbmJ4Bt0HOaIslqSE0tUU37GJh+j
dMnS4Upi/VTTjij3BID19x+B8z8MPPLP4tTI3Ii0VhRCXmTjpIhFq8ytj974Fh9jT7fUinNEZrS6
JDhuQELgXOBhCfGkgPcBaf5KeLLon3qA1ZG9WCSasn21sZQTAyy740XkpUtXJPmvWTSKoETNi52+
/LhYXEw4pV6XtZbpyHgbNlt+WwU/fSwPJiLGHr0+AvtqZ2FOtT91iPWjD0Sc2OQE1UmhCcMBxInK
rKJ44x79CZK7p8r7lXyg5muGcoPas7YL13k1tEW7DbGxkrBHayPu6sE+/Hk5Dt2/U2umcFqLEWf8
bvWwZrBKj8NvUP3kp8yu+D9aDiBX6lTkhf33kd0fLhUCK3kKBx3yMLTqUCKsALfIODriJDkPTIBN
N0iknX6g+CSYFwNgAFj9vu9zrsmx7oYRXYbPSvL67XR5UI7mJmOMjwPEvHzUbiw7AqH0Ym2x4eg3
YBPsWtadhEX50awCXiIOWycpRAe9EJA0BvdAzNrl1pIyS9KAng34xnHPur7J7ZjmCZs7UIfAsGXX
z0eY86F+v6awXbkfIrNk0Iw7NPbdKDQpwXt7YICQJCJmAwK3Km9Y3+SdhrvHtN4kB/L4NxS2l/8h
iktAkbgy2+ANiWz9OFwzMB4GYhK0S5mCLa0N1s/mT/s/2XcZSyIL7ZKo8Zfmwh30yMFaO0nQ238B
KdsXacy+rl67wWzfsaLB1YgYo8fwYoUecFsICpRlEmtTDVUE728g53rNCgp7pPkg/x/6OA2a7jDS
z/ycnTieAOtW0DuxjMyXWTYeT5OE5p5/WtfX8dSbOzwgKKNH6L2riSoe3QqfAfFCd02SmNnmzgnA
vUH3V2VaEJckXJHA7MVCESL0CbDS1JXIHU1P2FRSMLTIf13hdP8zsJU/cvD099gc0+L4j4W8fZqc
dcgsPNPnPQrmmC4JeCsxuusYUSPWQI0xHmtawZzuqFmVfX1upPGnTbwvrKd9lr7pMpG5cPLSWCx0
CqIIz3ZN82zY4MWtqPJipas97JMhLt0KM6vXPGb9apE+MT4Kzygv71VlmGx3WLZYcK49vWYSa5xL
Y1UcKEKJ4ADHbWBOS1WcmMrmBmXcY9En/LZrMWi/iLBthd31Snz+wEiCaRZUTsjpcMXB1Ai/vHJS
R10//kk8qm5Jj+ZcrRjBGCeeHX4bS4Qk3wFcMuQk0hVf8El8Z14BMWkJK2O4dQJK07qxguDjqsLf
hpSUdCtepxSlcxdM3sBSdra+GZJZe8R7kZshVtjHqngMdyEu3AaxzPibl0q9Cjp0mkY9UjhWvYCV
5joc3o4Uiq+3doaGUvbDp3qkaMJRi319R77L/QxyEYrUFF3qHz4bOjFjFndMK71ITPH+0QRbKOLB
tIes+3Fc/U5SceFF6kOcvoIvegbJSEsVZ31PFNdx1ySQhSAUYqfjymQS0Kl0NVWSDlGFl8Z84sDB
pnJaURejLAor6VtYuP2ff8honn3cyuzZLdolyp6usefaJhyLFhNGAKKm+m3Ge326DaedV73ZiFNJ
VCgSYLrePn5Ioi0UPvZUKjVc1ulXJ8c4kp/Q59ZN+5m1r3warv0OA52r/pXWQQyWz785kyje0oCP
8AfgHgvBMfxc2T85XydFx6c+sqmR1fyT+e8/PJEPaDzKfHphudO0PXuTpBcHtmMpp51qiAxjGTJ5
F57+KHw4dTHoecrCDePC8NAOAgv7cdn4WgyNsbo766Vsy5PENw1P5SbmmuCtORDRKPVMWkhflply
bxviJ+UPYpF9TDGjjSq1tsVijp/V3zFfImf2BKz1UBXQtWBXuSsFrQo4OXLnrel6Ywwre33XsJyr
If1M5LhBKT4aub58l0/DEdcUABo1/sCJhoPyMyVDgoUobEd23rgKnfVPsO00Y3zI3/v2AVoBAnPt
vOWsG05D2y3LKyG3FB5yaOLw+9bCGW22+EVO1/FF4cMSNz0SwYeFJoOQW+HTXTljw2mF7lOkZ0Yg
tNyGq3nLxEka5eUNCULUj7Gtfi9wYCUdcsnJCr5F+3TW4FCoQoeQSRANFHrRBkUul4/wiWNF9Zqc
G31izJwCd3UkDv4IYbnKS+h5/hn0kEH2sfVnFAOUuOTgh640Ex/stF2V+hOvp6Mo/snqJ/gPOBG0
wYO97QOP/684i6VG/qNYxSEGcHIDzmZaqP1ddu+C+dDbb++nCbjA9Zy/oqV/qN8FGzXTtXFSsY2n
OjQFieo7mvzoyi30sUdQ6iODUbXc9s3fJQQ8nmsNPj31/HmGBxcWY1qloYBxQH8JGQvdcbVOWkpr
9oz4lmis8y9SVE2/AyPVycBlEecLu1JmX1oIPVdJMtOKfR7QE+U8FEtq/ay7InkWPf+HS3BYGpwX
zaQsDFKcgb9NtO/U6G3lf4H64hKg7wZMejANUgQPWJJhGPS/y+s33ipoaoMTcC/Yu6HI10rzGwYw
ccgHx3pegPAyluXd/x7hlvPHnX9TIfazJu4hrEXFJbqYr//HMMu7+L2kqNdkb2SfxdLuuzcicSa3
9ROq+Hwb9cc3OPNKZRohzthud1KlhWZJNC1FFielDxSDPXYv+8TDWAyLHR3Oc5ckU09XxAhCjrWi
tdWPcncd+OuU4dQvuJ/Taojt5JVQ2clv8TmE/PJxsnaCnRFOxGwhjXHaBImkYtozyyy4WI6N05sU
rpwbpu1S8Ky6CY04BtjmIb3H2mVSSr//G3EOq6VwWmeQrEuNpNEG+VdsFNzIsty/65JsGmr+s+oS
Z92vo7DWY8NilP3iJcaz0lg3AyJbR08pY/XMcXgiVBDF/1dsBlGP9WZAUzTEfq1uHzTWQXHb32ql
k0JQDbwA+8oAZkVztjxt6c1FZihD20nuQPcXLXXY0y5fztTtKu0Gk6dBUYcqPI0kOr6FtOk9e7Nr
wSYcu++NeWHq781rp+GU4K7MpAXmsakgFi7CxOpGKYxNQQegqQu7YefyhgZKogzySv2b+lvp8xJt
7SbQk/fYQg+/SRuQoB4JTZ7AFOuPjsTeuVAqUOhj0clfmzouAXIIE/arREuk5bdRC7zF7t19BopO
YMmMxLVkOsH6+7vFeVsB9Xx0tfrohdmqqqTR8ODLvoKHXSY1NqtXUqEnhiTg536KQrGhE59Dx7RM
YXWhSpL6er32FTSxfd44O/kK0KABWNEMa6pQCfoDhB+XboaEJHEKzBio3a0l6n6OOeMu/+HLXOsw
lt20rV8fDoNPI4oFFG0RW4SH/YF9mGJlBWHpT5Nr9fyOFrJhMQqeahdnAuzzN9gfSQGTBUDixK4q
ZlB3Eb25JEKYrnpXDeHIGCfFp7WY0GI7vZywLZr01l+1rU1GUkpZcgKH/MPugvBiyJh4TY8pPToT
ogx18F4wJi36VvmOCrAOkvknVKpknfHd8Q+rTvKaAE7Au6ktIF0+K6SxhN6sjNUbUunsR9adIBfs
QkfN6uf17Z/aIo1Eqi5aVhFcqgku7Pe4okpUb0AqvHh1FNZvNaaU2jjCCCwSgwJXzE1o8D0EY4Vy
jSMx7WFg/mheexHvn9uBfWL/Ct8bqu+qPiXOPd2q0GJ3Y2sHdACzmSgZo4XnVFzkyMuV4o8BsmCM
4vNbl9t2kw46J6BNWSs6iQo3m9tdyAsoDCk5z6cQ27I+UrzL/dL8blJyKLt+9vibgqhWPjtKHZ42
GRp9920VyJESe/5+/Wo5DYNsl8lLZblzx8hK6OYLTvkmuBHPDz9Zm+lXJgsQuBQNCgXVDZIsTYil
EWv63Fek2WmDBRHu0vySSHb7A37EZFhKKS5s4pLlG5QAJUk7jNdm+inJrRy8OMRJl1heFxIgNq4E
4z7L9/SB0wVLCqull0zQ6fCi03dML7VVLqR/BAzN8l1F+H6KHbyTXMxh3+0J0DlPF4rfSU1w5Pbs
ARPzCchEGxk0A91DD1zQAXmvhl3wm/LfzMP9ZYkctmBkvH62bJQd0/+qSj0zqcjilj1r8s0g4pRf
2pB9KIMlzSLH8xCMC1DBK4HB8WErBPgMwv4Ivcv9dykQR6P/qf4UThfNIXDWz/NU64oPcEL9rWBL
6HHdONXYOfHHyjP+6yVgCbXKpWOdWnlTIWTsrMJRmOCurkvmTsjW75d8O4td76sqx7UgEfkIlsZW
i9zaXJu8j9sWcBImA7GRbEFgh/TEx2BzRv0Uvo2TtA92v2+8go26v3r7msIn8wzv0qBOOmfMkXG7
5OWuaUwwTtT06NgQOl1w9b7jXcJq1mkNugp793g8D7TXZELaZwq/FLeiu4Go+qXNroIKEy09bjCO
IxfkjN85NlP1jbiKnuNpg/yyEzZVRFj6w9L11hrNMZpfeyXDJm5ICZ7YAzAZ8DU/X4M8xflXjj+8
WmVOemlTBiNv2WyQVfCsyG/vMok8kCD75XV7fOTO86TrpsDZOU1/3iZCJZvSTNfaABkwdmIRsuxP
j+CaV9bgCNSX7pypS/6rFG74IWQhKSg4qGDEqmk9l9lHAoy4jLRXIlIiY79nw/OmHpd/fosw+kNO
Tbekusmm70QBJk6djdE9OatpFHDO0BgRsuaZagQ9QcLCQbUkhW2k/mV+oh/HNoqZoXkedRkgABgB
fKdmmSx2VONDowsh9NgsSoSvM2rWMJAEaD28E89vKXIqNitC7hY8HfmVjJNkIUmgD/iOmlcZZ1hI
7Q/cqBvK6ZLuOCZXUx9zbBmKeOWuuC7KTqSIwDqIbUqqaSlQ4i3pHHeYnNyIKmVDwg00AXu/tgsP
m6iEzgaipoOk6irF3HK85I9R77+dZKx0U9gQz7ANX+XbBAXkGdSXop+PbSQ0Z+WrcwroQ0miSFoL
sX75Jgl0SsYXZxsJZK+OjaqVFBwK0kew1nxskbxRblNwOKWRAsLLcsbSIg6oaxA8aBQkj5lH4e0w
Y/IDImwT576kTxnBXexF5arVYJC98XJG/R4BKUi7x9X2ERiurjmKvOj7sJzspNLtOpOkocwr3WXw
j01SBlB14zv3wzKWaiCHhuqnH0z6LnXvTRMN7tOTk3m04gurRwumSM9jUb4EL3FMnsKqYsQ6Qf16
sCZcfWO3uS4KJV2iXbJlo2JdlymSPof71PnwWMHpxDsyYaaG3qAX+ePEytSAxdHdv2WjhPcYv5zS
SvRMMRjshDdVpeDqAo4dprZNq0+FOCFsfXWzYj4aVomtnG+kXI4r5fYDXiU66QaXWF65RIzhNjod
UbZv/ZpYctO7Psrdi25uRWYgu0CYvBx7ejZCrERaFk6GMmuLXGuc5eGXOD90apNUegWGJ/HlThBy
fPAsD9Gk/ZVxKAWXIYazg7e7OODdkwqxkKAWb0BdqbbatljUnMYDA9MYhxiutIOPqlSwaeXH7W57
ghC8qWVueJ4T3uV0l0DhVQ+2GYl4XlmFrMSl74q5Aj1yjN61X7X2zMEyztOwN0UxJit/iIJGnywS
kMbWhZRb+gqiCMGZ1oTFqd0Uq8P9pffO3vOVkhG1Go9jEvYvwswT4VsznP0BINMjhYBOxsdkvaAY
qXFPuXI07WnV7L1PZchRh2rJ7f0neWn3VNktrVw6ALpKHEvfaGSEGCrqpwB9/44rqK76bZHNaLYR
jVBk+X0BeXRCZRSViFNKRFmxYHYfMBYaiQaeqRKG/p7v++YRr3bjSh50BLLaXajxjMNCHSA2g09F
ytLHtA2xgYKjkOYVN/zbeMhVFPTHsTCAlBJ63EV7d7vIC/pQRcj8omFUAklOJPahthp8JeaqW6le
HEeOFVv2Z2l0vvdga/6yvV8JcsMhNhwSxpszgw5SfR7xowkgvApzq6r6hvoNSNpUhRT8SVz9tvyI
4cxQvkID6uTcO4rHvNMY5ofVldWsDtVB4/RG4ipX9DbOCg4YomdxzA2+s05O0yFWTdnuEB6BV6el
3UXxZRFxQXBiYcRLOCLBj+R5N/eqaWeUc9o1YDOgBajfXWbxLakvTvX5Q8jUZm0WnB0nKiHksHNK
bo13ka9TFZp4WkeJuo/fG2NIOLqZnu3gYX94euIJQWLb7fHfEV6idTdZaWRnw/X3XRFeRvFnmo6P
qUq8eCB4rFXMj6Wq2gabs/hYIDfrsSJwL3PBZf0C/VqmrG9al8QXmFmAppgTjE1Ro9J3tSR4c/sH
qRVJPABlCpDC49Mn7xMk1Is9Ff8L4IkDCFuwqRNu6sKOfn7I1NYe7kdJm3GcXq7BeS1uHL3K8j49
Nfeg699IJAOGqOfk2fOm3HYN34XbBbrc0UAhWcsMobS6mJvKV5RUqs6txkTj3ZjeEQN/iAB1w17K
KMepVavAMD4HjeLKYFjmpvullUTaVxnZ1DmHMyYDOOZiIBrEZ4slYTEortJ2sNbYuPibFZ3FlzY3
uq1dlwZyPx0F90oAz7ktJYkQiDgKlJriVuzneK2WH+B7KJMioETcytdoM9Zq2o1Cyn2p8mhbxxWv
TfdGO86qjoYTqtXqPDOlIWTcA1gA5bvJP+OYka5W7iO01uOlyaCSagnsxZNmXNihNGXZcUzWRQyU
YldwtsNkgTjeErpgc3N9q0ZntiEOVvk7Qsq/SKpH9ZUBJFVQJOSGIY/xifCudtDPUJ71hLULy1QM
wf8KKulpgpPbs0HTHNduC6eneXNhsewClKi3M9nXgSVBl0eixZ2XauFfY1wri/aSEln6y348iFum
lO3v4Q9UFoHlu6HsB/QHudVs0haSbwdicENwSsYlsZNJ3YXxEqjBA5JREduuJp6IRQ/F1qhJ4iaS
1DIrNEU0cKPsSbzNT6zYTmngGjwLm/8/OGTu2V58wBso3fCNr9gNO9Nff4cmmPh9oV+Rkqj0YTIU
/Lc3Sh2YdC624UGExTQ0Uc0JkOT89i2BnnSdxqN6DP1AVpp4AUWnN0zYsUDhdm45bGxeCcyqeFwK
SdoEHVWmewMYXIATZdL2Ef8uIEkrJSljdOs2PY5a02HALC1mg1BINwG2Dqsn5nTOTorNoPx4lVkE
gM/MW5xnf4HC86s/5icFFNa6npHUKJvo8iMdp1fYrfWDmfICTBaFIIY2UPHRuGa/8oHFW8zapJqe
do63GyWdRzwPVHCYfEAAshasSOxBUYstgx494YPCKjx8mJA2FTB1JfwdCaxiZuhdq9J22czKNWWr
QUQR6vQ+VTjJL3/5AREDCVv9/bZo3NpWaSf9cTPFi0fmykQ5A0B63eX+QTQ1FCBfrOBowF3Lrwbd
qzh4V9vkm3GrJsnhzCSwoJwU+7FHHqO0na6MRvAcCmSoWqY2aFtFrEDb7o9EHNh6ZNuOYR0/uN2J
TXHFQRAxjyMuMyrmrS6mUjnpY8ukNOZUdpcGpfmCsB1vmMY/5HQohb9alB91MgFoXpz6U7wkaNQq
0sDlmOMvfJGeSkJXkUr/YpN1wV1jzk31posaLRAm8zNWW3ITBgiwC7lRhtppmSfx/OgZYeW0pH9j
dP/3Y6LJWnIi8vhrgAGzmYTMeO4K6UERyu/hRT6kckVuNbs9jgBt0hfRytSoT86eYM15FjSg1TIU
Sfp2UTgci0pIOsSJOXfMlvdcVvt26Wp5CWcumuRZssbfDIpIpdN1BTbeiHs9Z2L9q4lTraDEbTMN
VglRpeE5/xBavv/LIs+WvEPJchEVlER/lpDBW6InZLlADCE9T9XFWVgD+efrg2d8xOKM2KPzhE7k
sfz1+w8GKRkpLln663tXLtv0dhosQBxBdM0qFe0qsvz3TbWSjrboEFgJtg85ApYt1it3LCAskOJb
81I/BFKCJiPCQS6zxI58zIUEbfgZXQzrbQ+gwpCLa63UjeAIgqwxwdjtNeLWRbjWt+ZgvwBhNiAU
yxEMDxv9HBWBGx1qc6y1BntQz3Kq3/J6pr0/0a6/dtjeSvwUlg4K/lxtsuorrAO0DG7ge6NMw0Vs
FRKheZojzbILCJA6zWNdRcYbVWitpGqykx3FiODCHayd8LgJ3UvtmkTXL9P3PkOPdSRXvVXyI6zf
y7PgYXKd9gJQ0dza/Bf/IRHT76oLBo81iDVnWUEIS4vDh1rtTZado+lmLCKdInOCrC5vRcSbfvus
Zzwn7eQT/+wdj4MoFmpfdglrjieZxAusXF2pgX1lBTlVGLdTVDLuNIkGwSALueKNl0UhMrINPYBz
uI5tylU4s/IGgr7kWanSSHyjoj4e6jl0B4b4Ilu4vlPJ8E9zX8V8Iaqphpyz756xr3pR9z4XJOcm
5XXo6h/0UkwvfEbQ8n3MoMpvpszTgumNmQVyqx7v7KA/GXce875ewHXoYzLRcYQopGVTfpUHCvL3
H0nU1O2HGA42nEz0a3dDnVg4CAeyWwjJ3ZFr3jhceftkQsrXeS9wa0LT3RnjAVsi3tv+mOrgvNOd
5zK12RwQ7/ifdrBeuz3o2yYznfyvEyppEIM3l4W7WdUiML3ljNPJDkNck2W7c8tKz1TR895H/gpj
t7XgyCfUi0YIBRoOJvUrwFE2eV0K41ZyehfSFkAjN5j/x+RzjSRC+zf0ndiHaUtgtaysg+DxT3WC
1kOFqKLxP+1FymSqrNEfplWuFlZb6mYsEVam0TSlJsWWsuR8ogNNcVyXADMd89RyyX+Zi05Z1+A8
v2Zk2lclu9m+RnaXOknh6AxhoTfGnqE5K5RxW8u03eQ94R2+no92aOWMY5kopq4wAaqgweyVTIzi
e6YpbEjCXtHsJHI6h2w8h9TFD76dfF+iiGZrlmuX8GfDSpgNcMJwILKjUfxXEO8ioZWkdvPHO9aw
oQ8ZEHtl6+pQZquHJaXV9eWL5Rjx4SdIBI22d6IDmkrWyFrlmmE/k6HKRzvn8PZJVLsvKvzGCFYt
HNmkmBJmPHDf0qBKGkDSUMdHJwtrp4+Oo3UvslbzibW8QHN8KPZRCTp5CpAc6BR8b5sBBqgwKsH2
tk8/T22c4p5vsrn9dTLoV11kjdjItGs659S/EdiHSVfoAJu7gpPLl0zFxAFofunOnIMHhhZ5nyue
pwCH32gIz9PrGOdyuSEMVm90qtgl1GDNduePmel1PlzqQlfKerXgZvpICY6sdQXPkFo6Wa5/6fn0
imM0rhG4CbpJVnOyw5ktQ3DGSkPeHDvd/TJj+ADdvAiaeVtlxmd5vhBpIxVCTsh84Y5y5kQQwh+t
JejDGCnAm452OiE4yNCS4x1BqKp/p/Jp5RzXxjb1bV+FOHv5nb25P2NG+sKmsgJM+PChid96aoaa
9PSje8BO77/VhkVnZP1zIWE6y3RD68GnWeGQsF0027s/y2Wpg/q/1uu8oeIU2vPc3uKrXDr0+Wxe
0gMwjfyd52GZlNVKNE/Dr9ftLM9sevb86Cic0cAXV9gf4BJwXdL7FqKJJhQamL8gY2De1vssGytz
ExG/nuIECABDW1DOIvEverI1H4VV4/5B2LhTmrbIrKhFYj0feUfUxkR7wmCSlupPckl1ZWC4JaxC
kvUQunSIRYpe9pGaW/yWekd5lLClh77eeKmhz1qeH8r2uP2ODcPWvgwAOUQfxgNLfY04Ko6owPPe
BN0iDwIr9klY3bCm05qIX2YSMfBPc1wvTxsh0RZDUrtF6+jHS42q0alyy68pk+Ek7emyBwZ0JVvY
lTbV6T7F0/AcWkFzkYwqmIXldctuq7Rc3Z4zFEQ4kamSyqhCIfU4uN+CCcAzmMa+gudzWPUiZBX2
PkyWO2OYOYkMydhiv0BEpHc8BBtXIzdm+7eRPMWbQzBUtm2aIh5BqnybgoY2KOrrqgYtH0IJFD11
pGgHEVr9vIfpJDguPkfbX5MO6/RS9XnTUsYTxfcD/uzLOKaUk+m3RGDvy+2A3s+Mnzy8T96Ru1Go
uieM18+jNiFfqBtfjmPEH7jYqNB6rPuS0pJPa16SBTuN8HM1vD2omrBCKLsTMdSc9j19LOPSl0+C
8gs7uajkznULEvsCzyPWgxt4im66JuJerbw1AHNAFSDyGLSGYDKku3NbpuY0LAKq/7dqTWd3eSOW
prw3QmUylZundrRnv3X3b0Vx2lckU2vWz8TFlobX5ITLscobcqgRSOoqAqJTGg73bfceRdbwFFWl
NTp96oDHmUZbFxa54NVpMoeYYqD05zg/aqXlfr0S/G9jUDm2fqqYKJ1vvzTqtMrPJ19/hVRJ9839
Pwn1PFLoJnMkxcs0pqD0hjP43yzuUzUkr7ajBWXKaHtt9Dqr/RRblVDHJ/wxZ3yMwRfS0gSZJCvk
78VcwQg+6pVtK7KItdzpnJDglW27gbFCFNqqIahVeJfCSZ9caIefBQBQSchFK0nShXlVU106DRc5
LyIs7ZQsbK5M0iPF2LSep3gOrNCL/3OyywpqdazgNedrVjz6ZqYK5VnA6T2noIlYUrGWVKGXFwCq
nDcl8KoIgAwaCVU7zmaWVo0RcANu8+2IqKbGrC2iCRa+7BETiUqt0c2MILxZO0JneZD5v0bkh01M
y41DVlR3cIq+xrkbbeoyxkhDGDVqjkCumGM++eD/f+XQrXtp5Qkq1nNm4lUDk35LhkcGI1DHfv+n
IalBzqgvyx8SnofHrfG9e+w1Y6SEwLAyZY4AIadNYP7YaP1yW3W+UyXpS+a+BwZWaIZ5it1LhuxM
gmYYIUxbZSHreXyvlcAyshBHHkZJsIt9xRoEGWeyGqAiKMJ5zuZ2DaxLUWY8HzWG3kYcscZX3GB2
dbkRcMxWvb1xHSUiXwtu5gJ70KrtnKhTQPPt1Ei4C3lO/CYS2SLE+wSSPCXf++wYQnWW27nKioeY
pX4l7JnttssaOf0ZT9tPun+51sTRSe19X+bEODxl2fK7Q+snV3CVEtwaVAQYmKpo3c9qwtWkmGJ4
mW79xhkYGUew+qWHyTuUtyjmMZ6iirWVmbmOe3gViGlmyzSKftGn8cL5V+OHiwKcBq3O2XN+ApWe
co0xh70DJdg1lO1FHKAUx7N+dEY3IymboyoTrLsbGLvQyKPdfLWP87caR9rQkVEGojyg+fzcgWn4
Uvi2fhX1mNhffdXwzHdvYrZbsjTbKBIj3QtQxo73stCYZKJ/JUv+LpvzvFaM+UbAJ97upzrHkp7U
3a2fRzhQAZ/m3tACdjXYjPYgRo4HjxWzLZnjna8C0b6kCT40oowjzzlWcBjKWDL7ubcrvkT47i8p
x3rj+3kTQFGXb1eY4W8NuKwF51X/ueZ3Y/mgnb1AqOm5oaGwc43GcQNy+Dyw6dRDAGxKD5Nl58Jt
6+dFg8Dk/L1K22wdfOXss7V+zNPEKons9lQhMqXsidr/zOiH9Ayi2Tu34rMI4d1/AiTBOCdec2AZ
dhBoPAO+cNyIvUoi8JzDsEHM56A75mZuDv/XSxCIHq56i8BaJ93/LTSrqe2x/5/xIWAMz3BGt5u9
+ruLCji6UOSBCT8NJIO6zz7dyV/rFEbwQHvsSt5+eRZqCxHJqhjj+LdkxdQe08wPJkvG+C61Vwd0
lrp72+tHETsoUzHiVO4MIvSPpK78XEzm/CVuoqWGR7oJlHFs/JsUdsdbVxnJgFluLqmolSft3rPX
knqKeHD3PSY2/UddPOiEnoI4CMu6F4r7hR7loZJoMjDXFRl2eJzLLDxdacMqx6AC6BaakDLH7n8v
DB8tnZ/yhgFcXuile3oXlsVCOckdWS/TSoSK8XB0SucKU/wtO5AidWlGtJk6bud9GPNKRqZULUgy
hSbGUv3Xu7ZiGOn+HNuTSXj0VtvBC2UY1FDl2XIhMsoO7MB/0u6lt3sqLDKTp3FnT3vOze/PiPLD
eFxmf7uKgQ0Kv6TUoNixH+LtdmTEIUZr1/QqtT2NkO8CCu032Z6X5jdRhybfs4fJLNPj+ABGgclA
zNTBMrQsQUYnBDag8R3UC8xaqNCWMqAaphrlQ4BP/1UbDQGESf5dvu6lodHUShBWayBzDqrvMnwU
VfeSgczkBGZnr3T6IDhJcaWyAT7zUNS9BWGARYii3A4f91ryS/nvmJX8IyYAbQExh+2F4tKXDZq7
ZmVUbfrKj0GGM31kxQr/PWXUtIKtPj1CdzlpjhmGfJzNyzERXkgLogsDxOsMjsjYzBYm1GCkMAAq
9K+LpXb7OGJ1QDcYdM/yCJv1I8isX1aV+8ak1Oi1N2vKV9c+W3/y6u7mszFUiYzCzNhJEBtHMajL
RUIGxalB5r4a/96W7Mku8Hg/sakwH+7XaWTjNUbdUCfFI1jT0aw+/zm0nTDStls+okCBYfIS6TUJ
Qb74y1w9Mw9430umWU8PGFRT6f0FbVrq7QTA/x1kFxpOZqZEkwc+RKun7P5+X9c5BYSyOb6Dk6rA
mTUlJYQgPKmJldhN6LZJRRqC/4kM+OoL30jJYHmD/xNatH2/uL9qoOfZDPDuWQNKstkKIRT/fN83
+pYJmb9IQuARnDyJmJRko03355B8EBw4WgW0dXDb/gGJkXEeqOWtAM4AwreuIAxVvos8DyoAl0Rf
uu6w5DQbMTD2rg8vHKifdQq6S2A1PQtjBJx+BLSahykbmxs9esR8n2NTp33q/TrD3mmV4NR6sivm
wFU+JgMuSwPP8elAjRAzTbZ8eUOa9AvPPQ8fhMej0XRh1gv87BKPRWGCYlTkWz+7CzivQzlUbWcN
OEbDzD/bG0+ZHd2Z9BInRqcbQSAF3T27pX53VoNByYRVTevupGIcQnTIZnvydy2MITMZ4LStvHUQ
eNiJkw0uLSmDkmpb/zPRgggEQCi5ZGhUxmrEpKFEjxEOQJUd60Q1uARiWBxUjp5j30F8a6C4YBW5
S/3wkWhxDZgMQqK3e/sbecHy/a465XyDO9A/GlRd19I5uR2lqfV6zDcAzQyhX2ngr9j3Gn7lq8FL
c1FqbkbKFTpsW1c6aACbkC0i3xs/RHUrz/bWoi+a36jHz9bj65f31HODks4kqKgVLsz2IbZtdHOM
f7QaBFxDf8B/ZAQ5x8CFyjli8QGCGnrnGw7u/KFSnZeQCqVmahHan3e5PiRSPb+oo92wHftj2Xb6
rEDHsvNPMs5QtkNoOOchi0orn9RAAlmXhH1dzhv5MZelvhWL1hN+80Db2NfMgy3GxPFvOwVPLHt1
viDM+PGTL48RyRK28V5+Fkd7DGBHBnP/8kL/4F78GTpKHmVk3pcjyEKbYcITryqavV4D9cxuWirN
7Iv/CkSCFYzLx5g2X2+FCzLb5h21cYjYUaWh9dQ5L6+wCaOAcrMS9H6Nmi9nP8lqlZXXuw4RsIq5
LeQu28ckQVeofoYeaKfgE8UuHR0OVHcvUb6NsV52F1oYWL6gUmrfaBjUHjIonbq+rKhxMT7ujOY6
xpZ4GuB0JJd8NeOUfluT4t+OwoAymTxtGrAYIrR/38a64qOn3s5+Sed6MdtjIUlJECOxJRf5GF3i
47SzY7ct6S0KGi4KPV/ljI40JBpT/qsqq11ZdCsvq/yG1OzVCaxnZHMUgUQ0RBWgsYwNowo1sVzL
n+pvIsilVsb6aOd5q5mIM8iNUwBLu/jYD3n+C9j2nuphJzbHzSXi4iW2cfPbSHYdflM5NnBKn5cX
sKZQAkV4IURm8KlH3FYdb4xeomD63c9cXkt4nXJiiG8JCS+6UbyJQg4Xw2Ro6wWyiyyYbuf8xR8J
3mbtZ2i6sGVMrNNW0LdZZ3nuW8qSGQPWOMoLPAMsUeOIqpYLjVODtM6Ex41UpNCKuAIKQpdNM94q
5g+MmVW6IwfPc/o+C/u/ClmC70IZa1WGOT7dQldExMBPMSClanEgz6Ka5gzmhkWC4wlvHqdIdAgQ
a6fUlafmt+PueQLVrKpsPZc9kdQc9qaWMIzmfB0wKlafKWqebVi5aPNW19SAX7n5J7WfN6+NyPSx
bvkzyPbIvGD/DudC15mxwgUcUZeqPsXgh5lq+LLzgQFG0XfhOWbEbjO7YerJmTLBJXXtR3C9kbJN
trsbSz8ds/J4lg2/+kuir++ls+SdwtWskY/aiz3rdXFlz7dgxWFGlUinTPPdyYX1qnzl1XTRuXpc
JhctCxAwFexcZPz6c93BKpvsFLrs/eF739w0YEl4pCYnw3KIYl/d/JlS4Z6nYaLE2mYMqvpET5Lh
wfkdmWWwTyyLFXAAPq0Dm516Z2mY1YRSewGlWCfJMoQqwByMo7werrmUJfl3GMOVyVsC2J7FD+9Z
ZhweeBo6FP2Hd/od1DgatasiXZWk1dNbYzpAtPMlKFOvUYJPXMK6iABC0J5AZairSHAyz/0rNW13
mEOFmZjD+jwI2upnq3OOsOhdCdJh1P6Gt93IknDdAgsZmL9AGH+D+LZXrlSxzhufi9zwt8Og7GgX
1yAZAVtzXfCYsAnh93aVxCBz3sOfpJ/0jVhWb1B8sK01nsvQBgPQRBBM3YhGs2bG4RhWZOUUJYSp
X0yMwZxOG2oKvZFkjiWE9h9XKjty3Lq9v7SbCyKHH/ojGydzZ2H84q02yQNQyjX+3AghQdD5IHSr
qzJZxap/ZxjoQHhmcY5lLxA2GTeLmXVHTmnBYi52W6BYga3LhSrKb+U1HntmTIhYUTmZtTKNpX9r
e0gTCxDMTiDRlsVwpIFNn47myZwLYc6d0osog48ZXuSx25sl4MCKKOf9BLf77/nPIsProLPvs736
sEyvP6lW2jvvixjz6juA+hFfK0wjSY/2g1MLIsaBeF3T/zGuc2MrHQSW55ZdtdvJhs3QN8Nvi2yn
eq8vfH0KKcDDK/wp0pk5dHAzpVJ0+pW6TieLM1z0OCNdqWD6DRLJ/pWh4tWMF8Kwp7ipBt3xN8x+
TdtTNxD9eOMGfWq/XG8cG5BrpKA7bW2Lbi+fV5JXIhlV5vzFkDXm38AfKEpIsbcbeRSWK7I6+Pqp
jls5l/KmH44uujs9Xfqd31JMPSKnrUjZU6xJGdJ08yoJSrxn/qWNd2gQSW23pWSBQvji0SIQ8QXu
CibE1mXNnbGLFapAQYJmVLUu081G5E6Bof8X5SOZ6LEzyVCE65tVRQxTfBMs4u+K4ahUQ0I2g8VC
AJbyVaEXxI5817iTOEZdMvzOqCEarFs8/jXtN68wAF2DI+Kc581eDV40K2ex1tuVS95NfCq6SX7k
r2Ng80vB+OcXiLPK4RlKSOW8ezuJV2VmdZq+TKrcHKvsaDwa3NnhnkpwcpyangKOZI0bmS2w3o/F
pKr0yAjyZe/B7tKyTi9EmpejDp43dWRmjr8QtwTiXW89n1+7LHXYVrQKBOfRryvZzFKR9lYQ2x9R
eal++bgqckDyJjsAeOLLS8RXgIBl0c9qscCBNFZW2WwA0mx0QdiGcq0/kkKNA4GQPD9d1sX+b50w
y5Ewr8ohCz26c8fpgaTUDjCYvHXAzJomWtMso829+036Vbni/GQmPGDTljeWKiWHiB+cibH/xMGw
U7pt9w3AfZxUjXybA+uhiXAIMEvrnbbmFOjB4olpooP9EfyFd3rkFPx2bu86J9Il5KE4W9BDn67W
8FWnPy7+ogc60Yvk0Uw5clEgc6pzGgLtSqQAjLgfxjWLK6+S0JeaMWcAHU4vMrjyG+uZRBEfjaTg
ibLegwDSFAZdvcFOWa7d+Q1NDdFFl727gnSk7Lyv6UEcz+5BqXp+wtKAEd+RLymZVUknK14RfAo2
kzQKIlK6p55ptmlt+eFvv5bLPXm5sUYjZEkr6uIrI3Q1ZM4+I37jP6zUQQvf7Exxt9/Ifs/DcrWh
quAqFm5fTUafT0a3VutlwUSxXKvI8Cq3/7/OIrRL4W8ckk36cAuA8doZi5nrjJvo/qjMiuNjrx8x
Z46WvA8rOFm2NBVIaYja5Te7PyqOpRVogfgM54eUm8OXrGF25if0loMX8g1RPceb69Ny+blBXfFZ
5cTY9EmnXAtdUuvL4yuyuOzlMr59gvUwEC15M59tKQQ7r3NnBxdiWPe3IWB0Ib52XT0HCugKHPoQ
u3eX+fwmHVH889kx5Ywl2DK7/p7Gg1Ay+HVt8Jmz/BZBBS2usGDuJEFp02vzU93Tz0LEaNPoGfXq
qUHqSg3SjEVEJpEjbmnidCXpJKsmYp7ihvlX1GF7qWZ1rDkkbV2mcJGk74boMQ3HtF1ylanZ+2qy
mBT7whqNJII0X8nIzyQncf/O5SGMJ0MCrB+KOIloRb2HVWG0YBzaQpEI7uFBEt1DidO0ui0+YUsn
/E0mWGnzvCAg/OfdKeTKSWIK6QYSSAWohK68WunN5D5RP3dc8PxH1rmcf0SwT4NP67Oj+oLGhLDO
5rKAWyatFLZpRkNPSnh4UefqN4TZ0cv+F9SKH1o3827cLXnb99EAUrx0ym8FXOiMLhjirJVKs5Y1
4j35ZGjEHiPPUGOZ+p0oZdCy+gZc5QYS/MO/HqQnBRAqAMdPAXTB1yBU91HRvu/zwkRxweBcMQ1P
E/+IHZB4oFg9qrW6Vj+QfG1Ur2aGe4B1dA021ENqsOCA+mW/cV19/3+qMNz8kP0Ynz+eZ7lMoZ7h
UNRRwcMca8hhCbc13cXctb8xQ4DyXcrDpjCXyxjz6wvdB6bfuC4WLYD4OoZP3bbulEfO/mqaAsi0
OwAK5wHh/q5r6yfbjLWPelJDxOuen7wzM2xAdbAKorrfp5o64Ob0KBcgAsW8EeoO9vJ3tDOnrBf4
efv1+PLpqRY7EVzxFgPUvVQxqD5w2b5+CRjP07wldV7Ts96ecv3m9WHC/RQzVg1QdVU22uZmzWvm
rq+AzChdXKW0vxQ0tpZ0NNqUQ4fiU0UCRRDPuEuW6+v/He5ZW/T3k9httJqVxSRJKv1n565d4lyI
m+DmGvJyHYSx8DgjrANiMuPtAAJ2Ld9OmkDwIiVYW0TCM0kLUfO9PhBa0DHSAGPaOL8eelK9niwB
gIf6g3SCcJplQkpdXeJZkJq8YdkX0I08XMe/3+C/tCz44VZKrmEtSpwGPQO6VmDn6kEuqItTjjTl
hGMdvx3o9U8b/sFSaERMRJSKyF8BcTQqpW87YCPdAvOw8k/kqBWJhTLpzbh+2WlW/Rh/md/N1P+M
ZUpbri4T0/ww4GhS8TzahBmB//Q3p3nkjmyej3Z7tIgxyoVCk0Gcn4IpnbXayXqK8NPFatUO8TPZ
LWvPy9idx5++Mjar2t03rM787uK8ukWE1Octn8eRGxdrIT75dWWcJidBd/+i3cTTI8EWYhGDtRA4
xOa93LYLA4I/biNgJiEU8ufoyCfAivXYeNFWMGOja/1cIW9j0S2V4r+TYWia+i+QoX3Iqqe4AtZC
UZie2XQICYpaD0t3npcxDQlQ+uCzFHPiACXopjvXio96uth+7oYz5CGZyf6yWvIExbqQtWneTlsl
8SxslGBPM+VkmfMHiOV9tpMwdB+BEuKqhK3GpbP40nKSksE2BoWpASck6qunLn+IDb/biRLlHY/a
BPpiZ/bFPSLDSiXv/11ukiani6q/aQaHiDMVXOfEXSFVOh1LZl3Db7J2KakexHUwzfQuCbFR5XUz
vQPxizEuOw64YvokCE5bsoJMnbCreV3zh0PxPbuFGJkF9oObXdvDak+HD9ZccUySVi/9gen/NOB2
GvVkR+4ksN1i3ZDVlgvd0GBXImPwXAwaZsy6IRmLFpmdskezMo8v3pVnnkfX6B9EFERwIeIrnVPv
X1OUPyFtMgZbRNmZjoyMbFsnXK+0fktqI3JaSqTZGsnO/kE8MxzCNA1I0kTTS35Se5Doz10Z9vRr
YfXvnVZlTzE1kJ8QLDXAav6YoW7kv1hkytdNJ8kvsHg7bn/79GEzhcYhfp4qeRQk316u2B5PJq7s
a1FAklFF/grv4NMHF84yyW6IsLeDCH2Dd9U1HWwR04r2r9xnoo1DfxaLB5PErFfdXG+UiBCdtBjb
yV90/mltahPXBAsEA8T4NEsuBx5zAVr654gD3MhIslcUSn6AZkJ7imU5PaSKPWKZTXPwqtjbsPXf
pyGIxqGOK5xfi9L9JlZ1iMLnM3EbYUlNk3JVjdbaUVbEKxpGhx25X5gGW6K4ST7O0gCXgg8GwKcX
VxP0eJ7iLNUv/0SpS2toW/0fZJIjtWUpcY4wd46jvKp8m1A/lipZHLjfS1+R3f3KgpmcGvHAf4JX
Kqk8J87hjx2oQ8xztxjQoc30sdkJ7s5ttW19XY8RoujWDLFXJ0hnfqnl7WfVmVPlOVKaQCOv0Z0z
0P1ENdnn95OjsxH+e0dZyP4nSXF8Uj7++mh/KusoO9DqMDQIStb8Dv3iqEy0yOfSN2bEi9zfNu70
n+FFNaCkDLS7IEMCPAq3W0ZG04+GZGn6Nl+JNrQs7fFpQDCrnwPx542JeSbJyrvJi8NoNS/KCCTf
u6xyBqAnUGWv8OKUQvx3x3OG14cFVLvjMREyc36PzbEZHpssVq9N7a2vPn6wmBkMOO6J5FYbHoG9
kGajwFuNFsMLaolQWXLDDLuthPMJY6Op3Nh9f/lFRjC/4oqbXwEx2Z8hycnqckyKpXnfJnav3Tza
PRY9egwKdBC8XbyGBf5aX14z+WOBN21tiOfsQrEjx1mTTTKvWLou8ONC70Ciufb/kR0mVjShxKTn
mOTwJncAl18sQr2C3GGlNdPtvbUuPJKqqbVNUmUBryZ37M37pyJuzMHgcI82kaq1fXe07egaFeg3
PNxfyp9wsw9xzsCsBKGipEYnpFzKCSTJYZtjABn0VpznQmLlEYoDVPDgd4IOytSBnvfnTTi1yptK
H9vgppz8ekEE94ByHBoq8nMOTitVtg2+77oZqypOCwup64aGcOVQuR1WxVwrt1lpgxy0PnzBEO1r
NjKZGw0wTVC+JtyWulzzVgoGxBFdVOj4fzwlCAKEaok3sG4WLZrcRzn756YBIWNbwiPehMoFb4wH
wXxstGrbUTRjClOa3+GGj22AVgJotVp9vmzDEgV4UwXJidIFg4jiKMdw4s9rA20DKrDnlbNJeF1b
TqmlypOpgs9dN5XoeCYDwzJ30mbmCeaAeO0BiUrwG6tYtCh0YZzY3MrHgXLVPzfHsEGgVlh14o2i
ghT1Tl8XnoZAgmG7MxV1ybW/7CEXCa+OfmJxJLsK3acNFrY1Cvv2fvcEIfIUWrRZKDKPWBXfXysF
jn2NqA9ZmZGJLV5oygh83jFpEHDXp4iRlw7SigKGbu3MxBVxuW1MFF/B37zzr4oVgt2mwe9bXPsX
4q4J9bMO81Rqes9F+AOtqhhvxnY0MQUKFYS1kNAz9XxvdY3G8ehmlsbrmHQEJqnGiHodoAJI9QLr
qh7UJKdHkb8LqopvNzmJJh8PzEAPhhYQG8jwnW3PxXnb8IIQMeBxm2Ty8C05JyI/mdtvwXATsCjO
hVSqF5ab2euYtm9OYNRBb38hIUvEHA1wRAu07czAK3BLQbS2oUwYJSkSgZlDi/rLzapoe8UyFiCm
Amx3tgl0VlvOeY3mdYdICzuo42LRl4IYFrpaJnLoQlwFEkE7Z0PP/r7tV3y0+zQIzpd7BrX7Qr2E
wgT3fROOZ24Q/LiGsnVQ3KmNt0+tGZtsLaO6dZx2nI8GTkYiLO0L2XAig2aZ5VHha3TWXNhTLyny
Grt9tKf9A2VQDqOfg35iHvMjZ6/iIuuXmgsnRwEtkG7+F0cDeZ+m+d/ZikFd/wozcP/Cl8DCT8GS
UZHd/Pkla7qv1y63ZfHw11jKSFbzFeUrsIFv3GjZywMleYWGoNo/72S2lH1KhajJMpcH705zvWzY
UsmNnm7ApFQfp0J+rY5K2SdG3ZEeUDOb+PmMhRyJhRUOTvW6l3SLrYt8AzKns8HKaY9VM+l4KZ3A
3GC75xrQFjLGAW2cY3aK7+vSYUVNOmfp+trHMVVMY7jA+nvU3frquWy6B7dTR3FzgUH5JFqhYKMV
iI68cFcGg21wmrrkEi/OJUp5j4zD+A5DN683Qb7vtUmYumlozSEd34pq6x+TTTnoHa8e7LmIkAJE
TR+naYKKNWtjIGDTVcjBznQpo7AN87v+mH2MBHKJfcHKHUcWsLZ2rCabqmwe3dRbL1OEQ67xzPKI
Wpl2H1ZuQbie/2fxwKA7nnJ33fKahFO5xW6IsJdcfJJ9Qfx+sI5B7mEUjB4KoPimhX7CyoWaZN+Q
esqitBIJik6PKByjNYnkEmRv1h9tTpECPcWbVxoTaVG+o79NdB+WQNmf9dAc0pkYoBWYbb4xsk+4
XjJdFspF7ag0NbTXDKST/itc6MN4J0LLii/bZPvTtduDTpWlEd6YqvDhmIeCtloeIcvQVjXPHZyq
Ke7z8GMUNSkvorQXWUYDAqil6GJeIRsZIdH5FnVw6pokxUckvfch1QPEDhic7G12E/3HoXZCTH7p
rgSj8Rb+9oWdKUv733j3VbnYsX9xkc2SYoZThp3coOQg1Xc/3PdhzaUCG5xnjMUuDQvNDej+5/S9
3S7UdcN0y7GZQ5GVNW8s02H0KW2CS8r3UTiL7c01OLHCXytKcLQryG3yM8bR2s3vvDmwm3KQCDOx
q44LHNPaXg/nQkx1qjcb9dg3STqBDWoAg6ArHvPkZrg6fe3xzBUx/JdmETrfEmr2d9G5QCKVwfrd
RW9ng8/d5BW7TxIWlrV62q8Hwxf2HleL0/9fKFsUjw6lZOA4d24Px27H5gcPfgy5MjAZcgJTbdyn
CBFeO7et1+5poDcolw8A3Cd+9P14dEr8gxI5dFVY4Zmx69YH/uVRsWLEfYYlH3bNb1RD1EFGXG1y
jtZjl3Ss7E6tTLqAs/gUEMbzQ5opa3bP9hh/cag+rL0NzQHZf/S19HspvR/ELREzWx6/quVKRzsj
SXufhSDgY8V572XbFZKRRV56YyJgVwx2qL8tsvJtVQkmCWK6OjaI9Ox+K6efQOTqj77c/9Yj+et1
J1DVFgBg+lkCOw/tHxuFlIs/iZBTjiSStsgfyjdT/W4nLlXiv1tJlxlulOVpk82+65k1gPZiJN79
iy7iD6Km+YDEb6gTBEBg/JiJ9m/zfYyPJxoXmH/DhjQcXnSB8apC2IwEQto7VIvryd+gOE3ZlYtn
pFGNfaEuZsnA7Pft4eplVemWmkSbKXW1A+qtKeBx69oD4jzPzTkPh4dr1Ogm4Mf5XJU2lU8X0Ivf
gB6DujTrts6NT81u2FD3SFiOaVM5X+fION+us6owDZF3rFyjBmDj/jISM9ocvk93e3xPsZijhf/V
8LdapzDxivkFDGTyLsUkC/c/dOddz0gu5r8yiuVd30WMcC3Pc+QpBdYsKYvbuD7sbvBR9Hg4US1O
CwJabgk06hGMXS/tnzXgyNapeuRDGRCqJ9NuaeJGJ42FeM7yHP5X0u68X8k0NEq0yFzCA5L3zhu5
iAwrnp2awOLwU8405Bejbj25DLJb/cEqDQa3XMF02iMZ0nEgg1TrRKz2FDNOAxM/Czevlsl7ieAu
9N0C41mM4c6icUhKB8XJukVa5dxlCFKHZXpotpTlUeeBGAI9FZgW9gOY/ESDivVuwE2QGQBoFh9D
TVGuj/qXMdoixBGoIB1UJey6HkoMo0oZdtNKfpDNlG43Lr3HSdTIADGf4whLXO2cCAD6npBguv4n
0II9WQ7WEB8okFEWvuI+s5QqqmKuFifcz7lq1rTPLjIWK541EIcfQONeG/r538cp1B4KnQsBTtwc
SZ+4OY1z7jPb32ZQQihrxJAvUfoHVXg0nmRMY6d6nGfxk0RPOQySNZGUP9/YnfBewJ67TRbuqyzP
OrrZpEBsprda6QuTWVNc1yjOINUno/uHxIRNJhCPwEyPwjtDwdsyhFLpcR4WVJVhTS279vftXqzq
zpBXzDE+qQdx8PEsTF9GmXuNG/Hk/866IT4xOZtzwFj68WwTV+hhQZQ8qlLk2zwMo4eLwv1r9FLI
35eDXtzlpDqT/H7yirNbpPoz0M9xhu8UELXeGz2uJ7vY3zNms4fttGggvyfcmWLs+tEtsHf9F0LA
0qijY9XXaiDAfTHUhK/TYFztf/Zxkwk2I7QWXQ+0sY1KSrYfZmNLOgipSOWQmfUPhOJx8NaMMvq7
8D6l3rZVzkvEl6QXsJfyddo80a+bF8HnHnxVPJ+Y11hJTfrxysiUSGOq/cJYM20nfQhP6KnAQDuL
vZJrUZmdu6S/nuKdntx4V+86JOjiBJCB1OyTyh2h4y7ztgyXKLPw/59aEjBz+vpilODmF6RWQqIR
XtunT3KN7E5CAYXSfoGq6anZHmICw4gNMMAo74Q6S1MSvUck2D8wYt9+A7AIZ3uuED7qfDffnFVe
2N4Z/uRunqGtJabyILb3dgs7y6dEBrSDPSM1bMdamMgHHTn8FmWuCMoOFETwTFUMCpR9DcrHTkto
leV4im5ncVTWZMXCUO23GfBX3KL5aLpIk+UWWGJ/Fo7sFBynwPy5VHewUysGpABJWyd1ms50lndF
TN10R2tEL57ShbLltWbRBEUBWwLMYeHbKzIPF2Kd+OYNGD3PNV2v6F1x8DpSyumLxTiyMtjiugAu
D9+rNnIgDNDlw8nsUle11wFybHwcv4KJvTXmxJn+Kxa/e/f21PQkYf6WIN88q4TXHKiD49bcCjjr
1qFpDVbRebra47xiREgIZe+p/9R/G11WmMILwlxRXX9ZmaHWl6k1G1gYfmvxB5YouUEFozI5bGpP
SDI8XMRGtVpx4xq1YvnRDDrp0oR1wLfLTGzE3Nnkk7EzGJUTjCiFkwr0B30F35+mkk7Q3/mU3BS/
owuASDfDvN6KX9Ui1AgbofvXRCQzVpGpi4XcXSd8CqvAkCdH4x6cq4i4HChf/a2Lf6VcmU8/v8Pk
m4K3q7bTzgXcLH/gFQG8YcpYDMIwl1BK3J0z//M+dZA5hkRnBaAablLT2iudFGeBffLioc5NPQ+R
dvbehr+lvX+7Z9gtQZrHz9phMweW1MDCQQ9NAmStINwBeaa1lLNYOdN7P+b1Pw1QiMxxyAAzNZI/
VJXG7ScSSjHIScUOPLZ6lXAomeoZpl1EBwiKlyN34RBRBpolJhx/0KGKHibmYByT5bLWV9miei+v
XhFtSs0ngOqylQ3eFd4o0z8CcfEhgttAWFB+jkumMZTsrt+ez/SjZcPVox0/ngXftlWR9XGtdWw2
dJj6LpP8PoCBJ9U1eJGv41SK/mDQAV4gNaMt8jdI249Ht2bdmKi8lWmYoE/Xdj+8S7Wq+RcDnSQ6
nzbdDc85wle7WzxP4JBUW8OOF3WIv8zs20QyIylzZLnKoNipoOzKyFEg9ouBJTpr+0AruwYISxBl
OeV90tj0z+cUvH1e6k9qBhHjTGgW8xj+KMIAwEtjLtgepfqnh24188fdwtA5uPSmRrbX2I9Xf9eB
LZ/xvE8No/jthB0zVk4oObLlzFxFThN3PCNrCTzD/5bii/MUsvC5l5RTF2oqtsZ04Qz9qvAaRfxM
ko8BGRKV7FknRQJ4f52hWkxYD7R+z+LYWB1vDbFalUtgGbIpxDx2xvjtOyuSQBpaZpgObXWyjwx8
IGb6U24vLqwL15beMzzbpO6qer7bY+n9nn7QvDnxhQvEq653cdIwGZFh1RgQf4+0hLY1BlwDTgVq
VgrF5mJps1uAz2ruCHHe9vtAtm3EFztj+fv5T/NpG6S42LMjkosQ/Zba/QNUE07WIT1iOOUfQ0q0
MTsQuHWrgwq5WrUA/B8f3sAEgSgPDxYPfSXYfyyrHaS/Ion2D+NG9TJNhB8VvHw7oLlrDxpkmr4T
CBieQDIOr5f4zpkkPgt4fIcM3VnCz7f3ejcidOOkXrW3zop/xHLZeND/vRk638udlibhZ0D4Rg0E
81GkEa/X03kcgTJEQtsM9fqslZyrqMEB8yGeKhMGg/dnwxWPs0a4tKMArG98RCTQYheIKJ27e/FR
YbGnKAzNAkfESfzgBvaPq4nckfjQRrYkGZAc/N+PFaOz5Dzp6i81UpMrienfl/QsuR66go/sioQ0
5xKnFVzYwcu5K2PE7L0ylff29QwHQ7FbioLMcYLm2wXc3zT51NNus02PkVQdYHbtVyaL6sP8R6Bx
smKYV9yIFmToBy32vJEkarDKvjbKizaX6ojIZadaCuNGPMi7UbbshjBIIIKo38Ry9rO3hNLxNatF
MZPQTbehLzyWhH0/WMfSyxmT65fDuVDnp/1Uv2nTTmKKwO5HrxD2egNwP8CPX/eN3CGPlYeh6upg
83+CqpzCKg+Os71J4nkXONcxYC0rP116xzOj23qUj9tBnpwPJ8SYiXaKMaBWi46ZUS3O7+JdHP72
iLRQQmPj0I90tdRvPzBm1kYjQ5tG1pJvNtUkttsJrhx3RP4XSIinCvm1pBTXD0rT5xtyTQPCfwPv
EaAz5d4whxlgiVkb3hqx8RCpS96Vak3pF9QyuCrBSIzAUpsaQ83KAMSMuGqlPUnwX6wYe3Em6Ofp
05Qae6QRMYjYkUYO1nMhZ/u3SpINu3lQtnn4nlG3ux0oFSkLvWbEX96Y+7Pi7cmWMtM6rJEctxNo
5Prkc0t+Lqzb1JV9V7nygoKYcKi7kHgnAvys5saeNaLi/Y8FJsX1jfxHENF/1homwsNXXq24JVzN
n/WKCXOk5Jkovarz7ZPXB9s1ycOMMLL/YLuhZ9fQg5r9OMWgTLrPf/svRbtsQW4Wx0zIuW5+j6uX
C+/sebKpZdt8VW0on9+d1eHFxdNHhBV0GOMT0HTEZB+r0UHruVNRh1w0QBbF1Q77zOYHnhXN8bL5
WzSYs8Rc468fpgOG3D8TRH5tfpsvSQrV0wMjfAmEnCeCQFN1ad27w1eyBRDDYBh+d4gjl6cfkocO
DRtTRuJCKbf9OBpXRf6tzZ5BkMWahYUSgY/WkmEsy4VzlVnuL2RkU4+rb5Xv+m9nYv6VBsWxX0dU
ZChED1GqBIfy5HdfjDHWys1rr7PeoOu8BJUXefllJjj7angLxj+vNqckKMIPCwQOWb2XShI5Jv7i
GhB+vVleC2EBkHh8Eedd5l8wN0jA9BuohND5VAZM+mUCEIYGm5Pwx68rILey40KYplsw6GQt+2Oc
/Ijb2tG1NF2+XJ0tSnrn7CZJgvRp9seNHn6zK4Rj5YoHJNHLtgkUvhOAdUqjNNYBDtDgEXtsNtj1
dbDKob9LImX1R/97cWCzfJUietqvlNUw/HPfZn1jBpW217aOeFKWWRD6ewwmwKHLqkYh0VJmBQoc
TiFeI7TpQSXk+Q+VTvu59Z4ftmmHKG3a1XYvitw6yFoQeQWLVjlzW6WYbk8RFy2eOR3t+e6LlcJe
gIM5yW3HY8h0bEYSTtDw3RKL5OEghBNV27OYl3UF9y9q8/Kcin3gmPFQtes1FjEN9YEIyq/aoLlQ
I99DA48x57iclAzE70qPRIz+AP5VPUpwlIMtw45vw+HT6XQEpgEb2/1A6hphx79eSiUZveaf9MXA
OCDlzo4vsb3EFOTrMQeCz+Lgf4y+BUzrKRnB8HXGh7ffGVVUfRNfdByuj8RJCgElxSCxUkmyWuTk
6zpPlaQEa3CN53v0XhAFffxelDbq63VXINQ4WYZgrKseaQv0A1XUEBA53OoYT2/qlYTXuxCzzVli
pSjlxoXVyp7wYF9tOZhP+WKbSHbK9isOJa6Ry3F9S5RqaZkLDpUJFQSw6VqVYAY0b+s7DjX8SP04
ilDZhpZPJ1l9XKbZtAik2XovrIjrh3xxoccL8HsjJ0EZXwqewyDiFzgyWeiwOwLjrAJtJ6UNjISI
34BxS46tmf0jOFTGrG7XrnLI5B6AV3nrkC9X6H+KQAYxie+SJpIV72Sl+z1yK9WwVl5MNmEho9RI
IpgGISAaxzj8ZI9RboIt/inTYh3wUOi64GTZl606H1epwxbdRa9v+avsyGFybE2QscwXGEiX0x+Q
e07Rlae1MyDAlu9AC8VmeK31vuBvQM3lPxnFkmFYhWhXo7o/H9VqpWlvZUGIrhDc5pBLxPFB0zwV
ooQwnS8NT0L39ZvcP1gE9nYbD81Ionf/RmBSejV0fThf0NC7qMeXmR1l9jnJz5skdm/IAaRHlG0G
IFPqBBqhHQrhuDDfJ41q7HMDWvOzQuFuG45o2UzfWcCPj6qWWKGw3KuCHLk/ByGylig1z4C1Dop8
JmR/qZYi4ym7Vzhl/0+yp1YkysRet185TQPm9RB80AiJgrM049DT9LFOaWSAkaQzEEksLKi9j6Mp
pVW6+27VD7oX2rTRL/fYvUPXknh62llMDUqvLkpJKNpitCZB3zaq/98G24sba3ouPGSB9r6+WEgK
XpWYLlDTq+IIM8hIU9eu5rFxUazcMCxj9crU6jHuHbDnUZuMIeToUCwM+ccYJ0P4sYSMXQAP+cis
o2O29OGOKC7FUzqOur6lNEn3O+XkXLL3rj50fDZe8YSCAuAjWFfZ4N13dWXBQZx/iJ/5UywRYGDo
88PTYWn7yatncrwN9Iu38lGWdsZ96aB6iA7J+93BiGIoKWLgZsSI2Li+PHlNA8xBmA27v0BbnjXs
UXR5mj9rB0VzFkSrHas413Y8UzPn0VYyO5jCf8ki4XxYDNSIbfJ4id3f1Pt8uPYLXKXIva1PcfLe
Akc8vE3FL3QcdYkNVsQy8g4cBrlYn6GbnZ6fQlMFcoF/hqfP0XZuAwByA3U71doEpD6+zMLLHI2y
STbAwa/G6WLIz4VX4F3ZHE7jlPCbFK6B2tsjxH9AGZotKrIVr+KYCsW0EvCfTm4uibOZzC9qjk75
UEBfK2yzSqpeV3i6Foq94BDHGwZliaQSUi/fzVKiL9qvztjhC5t+N5QDKJzzj9jS9/8IPNwyQewq
1wtHJQDrbWpukxAiNnVavC+uoGbjgkGA7ZXODBNAvn5cqe0kRxnz3BViMuSyO4qUyFWk2LOD20y4
+l+FDOF4LInt5gk2eeVuiyOMXpHssWHq5qYdOl5c/yxRcPTVVv7lFgOb+gphsQ0Ik74nCR9zMUK6
JE/3BximEL7ub7qSyVsLQNpcqRDU77gnXNvRl/6VB6CSMGoR9CxNdkxfbeMAAorb5G7ioRxkiPHQ
5PyYg1N36aBHk7kllCgtZexwYdrlTCToPPAHenhvBoaVtJhIbU/DPc15+Bh4KvizwcagHW1NhVqt
jmtf9N8YZEV8kyKW1FBcn4h155a/hQaLddSPL9PJoq3K3Tj+LeGAcPD0nGpiB3jGGdJFDZi1GlNq
n0KfpCJQzEAImRzSdxCe/caO5WYO1DkXyjhOLtJre9H5oQfI+ACCj0hKWAJabJwtnDl7ADXu4+0p
NyixtocXQvmz61ZfL9aW1SN4ec7RQcd94YHDvlvekQIhIroDibzfqqJuwc2qjDrKsG27XTPeeoTn
F0lFknUl8eQ4kDFbHznDPWSVjHfv3Jm2X5xWK6Q53YohtxyP+uWmK/BhFcjqYIwSatDZ3nsJlqGa
vNoFGbRQMTZBRBxXCe8ZB7Iegoke/4JUuuodIqxxPmVHdGKJsjWu8GjkdE+Y11CsX4ChTTt6rDDx
AvytOt7Z7run9xdyPA4UCDrDjcqVslG+JS625Fxi9Klbp3nzElPKNUiOrkMOjxdxFTGOEyIkr5ol
MfXlXpt6OFJO1t0HTAhDjUFfulAEm91DEZWAF0LjH8Sk0MZQy6xvvUHfY95DxsHg9WwTvZIWfvxi
E7UokGXWX6sk43B+RRvXsmLKJLCxuGW5u1uT60s8Uk68AHf825bWr0MLaJyJ5rfgX0DLPZ6U/+yf
RJJTwpvmpSrKjPuRLF46tKA0De8i1w5ff6Mnq9YZyDnmUMDWp3xW3KQ6cTvFRUWNiho5iblupbAW
TpAoB0c9WancQ/sJpVDym9fWpX2NLk6l37G4kuwXTHmXBX3ozwqvYjZWgKOZfY4tYHDYjN3AKgXz
Omnjq0J9xkreSwnfSFsTDTnOLqYkzsCAEBNxJ5mb/Ts5+8Yeurx4QT0bZlJygLIMLZ6AiZpeQfN7
iS7VX7Bl+WHwAFAh0rN74TiT4gt6fzQiTI88ym3ri2u5agExjVRZ1ysB5dAA41D3HR3Ce25w9V6F
wuzhLlbLvBdZ/5yyGDJueiYkfKYFnhPU2m2WjFBhDxGyjb2T6AQIEQoVCIMQCIUCrf1WP77kprMR
howAD4YPBcuaZGzPjmLSbzTcO1KIjXfOM50j6YJ0lPo4a0RUswQUYrmr2cphDC1Xzq4FBT37Th9M
VPGWkX8qMHhDL0BXfj4Zm7oUZ1uVcPKRReXCUtmszAyxETp8DQx/BgG4pQcypDPI2eQlf7Vm0aTU
vBozCllP/KdLKuOwwhsp29a/YYqWmbSbN9MU34NIH4VULD2cEr9khZawf2PPLE3nqajRJV1F8uDB
yBlsiRGY4715Tw7DsE8ZeygxS5RQyb0S5JEu6hOOVMZ1iUcz2pmHIWyiLNnC707NVjH6pXwDAdih
TfoA4i5yHYu+S4l7dHXFkZGDKeWUcWI7chtrT3muZUQKcYzBOEqumWgSqP67Nvre0YX/i23S27Iu
fplxr+HfpRXRjF0ZbGFpHAgYYh2HJ3ci8luuqU0ZxbY7TsPw02jVP6c6hVRCoqbHuGaJV52jUckO
9qRVIkayGz5gesS+0/kfOo6u1a3aeu7mf6qPi+NUBf3zbJ6J9Mv0tp0XUlntjG/i2+aOibH3U7DV
X9SAqEidecW+yNDeQzTJ/pXW1A1einFXSMab9ZBYV/LR5xk/B7vvFVMVEF//hgJcplEtA+U0rpqu
jgwCHyQ0S8ogN3nYvU7ofkA5FUSsnZM2YYWoG10T5WeUMaSvAp+1n/+tmB0USI7iQzyvVabexIsX
/SIdyj3k7+iC8yqyErmrXJldogtBoEFa//bVT9jsZp3avyuHIgth0S4A+4SgMpADcm5t2lG1iNtn
hvwwAaohEd/9iGZCasM8LsjVudFB87sR3BmOCT+thysccH9lKLSAaQOHAcBdVLkS+XdMMAaTYZ+s
R1HzhdvDLaAncC42t/JF5kxfWK/BmGyef/lxQRxTSb8AGbt/6swNdd3jmUSoxDbO8APwLEYkaXMq
rNG9ULLhJMuyox788e1tw/QKZqrLvZ8QjII5qPEAbjiPZ6Rq2hUTYWNdNtA+CNTOmOeoLDTmQNK4
s3c0RpWZYZnBPtd6ybzZQfuyiTcVycNdm8tOGoRsr3p0gD7rFFdznV/8cwyS+mgqHr5xi5kLB9Fa
0GtqNmu2vPkuzJ4+BTWIsYXbpx43ekamvpGaUDOoKbmYb0ycuGjSyOpDCw11w387jIpNuxAjQr20
BMHHLqwFAiab7gVrXao6hya1WPXCPtbTO22XE59m9l3BkKc2o6XJSn2/h9zp0ceJCcIb7fT+6zuZ
jBQXhwWhHzsrWzJ696iEOFQOR38itYQCLtaMWhUBPeHnuCZo10mRmlKgh7M1xJG//AUwoZ6L818p
DtMTr39ht3I2HbOmSC9fzv5Eet3BYMQA869B9fjfml9sTyZ4Y0gslMw0zlc2WWjVyf+nb2LP2p16
FwHUtSO0DV0cwoWn0clVQPC20JEHkoUZdEXA0xr60n0J1RpaYQxta5P5xohRvNbpGA672kS3Orl0
o0You75PbSVUPB1gkLoIn1QPPimFGIMqxLYMe4l9Eqk0KgeU0vaVJqN15BLCkysSNxwSUjcDOhWQ
/U85nmKr5v0zoHPU39qqWO0THdMkEOhPFj0sYKaAAjXdi3TUtjm552WO8tIcQIydv+dIwBJGVxYP
oMo1z7oj9VhWn1WpxbpdoaznMHojemQfCAviYijNCTgWyH2gTtax+IG4rT87+Xu+H0s8GW2PlWzj
D+/Q/OUg+jYkZeb4TfpHwP4zMp6kC44LbAzvshgvIE+6izROjgeJZQA8IIl6cV47eBAOPTGGtOPH
qMrzV8N/wSKbNXtl7R5aMMWBby+jRvkVVhBSbwMQpBg2twYaR1cZDcKucF5XzuvRwF+rWTGp9oXK
qqgqLC9wvJ37r29F1ogqaITobeM2rWhyiGRG8xEX6kLJBBGwRbjrJj/98gQugKe0j6680QAXoZUy
LgUvpH6/CL8MXMygScQu9bIlPP42pwg1AmX+tGAlaqTHe5UXeugNPuXTnmR7UbsgvsM/EV4+vy0f
xz9EA8BdLixW4p0k18dPbkEmL15LNuVxEhutpLQDfcQF/H9u8g7DReU2lBIFGlVxx7EDQBX6IMuo
acnDTFRUOdHZRFw4eCZYYrOgrQXkjFcY31aZ2YW2wOKylUruFOaP6EjVPTMmwynNo9/9FbGNOg/f
8uMg6l9fFuUanFVeixFDyOPmgNXx3phmUISEUyizxbR2M8e4QZK33zvciHXtJKcgMexfnK+hZRkQ
dsXk68W+eAZiIcSIRU1IDaJoHgpApPlPwRkTxLTYjG61J/743Zx3kV+ISoJJtpL2jMGrbVlSheE5
FE4VZAsAAQGmXfN7fEPiAUQB3aWG0q1xjq0rl3w9ibv8PafARN6mw+1SdtdFnjLfjzlcaiABXZZQ
kwC2j0F0ZFaInwSQdENyS7IzcpbiQ912JRIA52KXPPH3JtRZ+woJr6jH6Y4khAMFrXJYFyJnepFb
9fboqillX04eao+F2ps7kH7HoyzHNHsZBBenluHheqjBgLewSs0vUP2lsgpLmm+Vi+/jJ/tz1tzm
IHWOBZC+CykaILO3NC7ApRo2VibYUIXxEhxY4u3DoxgQPABS9FmEhnm5Z7dahAof4iSDfBDsuIN1
7hk9Me52xo+AvQtg2bavnvleXXBOS1VxkMwv/1qD9MjIPdl9QAd0o6seYnlm1wkg4hR5bdrAMLDK
40f53yNnNOoPch1AHuNFLygfSjQghNPrDZN68166cbKND5swI3+7sp68ZPZG356IN6KXotjcTw2A
CiEjuD0+sItCbX17yJ71GnQ=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
Gicn0ANpbkQLuZVExUrJihnUXPAxa1ImeWmqTzxIH62mdjSVlulvhi48IH3C4qAyQlx7nyrTGnKO
aZrh92ceqg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Ykp2msmA/Pi9SGpAkhHXp+LWvGL5x4WDWSZ3GOLqcsxi6Xuib7rImM0SpgG6UKY3bIMMKeu9xjcf
/eelPldDxHIyaoxj1+ITRuMUALLcjvj6WP7HDDwPLZ5krRznXm8lxxwV82spiF+b0EqzDwg6KWwf
bSIPUC3YC5ZK35YlEIQ=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
V+o5jgOQhjvfAyP/f09hwvOp9BBAnkU5DaRefEqWs6cG/XT9KsXqKuruvTFyukXJ+RjJMq0hLekA
tUxfhmOSc98JuhaOXJahe3iMzgk9KyPgZAPFGKi5COTcDjWm1HVb9D7yLmNZ2U2O3HzM7qFErxIW
kTtfGgXX25XMsC54xhIXA1xxePG7UjWYrdWhcrbAshA9LeLH9r3pTVDzdrrPJaaMoceJXiFtM4HD
Tr97ZAUxjQoi+LqwVuedrCCQzKi/0LIc6fcjScm+qdxeH0BnmhiInaIjkFZS7hRsb3RwdUWfKTCt
vBuB6RxyxQ6Jq5iOjRDGitvA0sIQvdKXGrmdxA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
q3Wo4n4K1Lemi+bOQODE3aX0dwXbNN5kPkzkx71l+r4YOt3RTgObzTyasyqCY0foeabUljrdxAJk
gng6IIin0DmDWlag8E83uFutRHF+NyGjn2kPA5q+k9l4h3R7jxuDCYVAsIjCVc/KP0aL+guwX2Y4
csmg4gg3wPr9N+sTkHY=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
e1I9CbotAQ7p4P1/G35hRa5mT0GeD+iuAyp848uYw4w6L3I+8I5Njpc22t2kZB2E1+sN1rTrPH0r
XBiBRmirIkkyeYdCmUt1U9X6ZVtvN4UN0HK28Gc5LLfN/Coas4/NUjcJuINl1XHan1yoQ0sic2m2
9mntBdFVXbnhfQ9FpkMR3RBFm9J6BV0Wou/fclhTcttQLYUmcN+cA8RBen5m1cZmHptDChv7Yd3e
FnjnXLj3civ4pcIJsBAtHS5iGvP42N5ojj8K14ShZI002eGMQLx6tXCi1ISYqebs/F9RkWRNpqDV
MGjJ8Wn2CD3tJDbK0V8JPDSZ/sR1gEiAU4bAqw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 35984)
`protect data_block
vxu1HEy3xhRN+v990cktOAlMDTxFOxwwDTP6OrQWKtVZUrGbwcoq35x7q+RlqT0KWJPpAaqNyGeo
Kc8aju0A35+DhDhFTml2h71m8Skb1V7Xvl0JiwfXZ8mb8MCDL+46jCROTd6t2ywgDJp/I6Kb9xbL
3lXI4E1bLnNiaY9daESA30YWieWFJ8OTK1ENAYPwyioheb+wf429YQWtYPJJRzMHW0UcWmfE6EGe
Ykwk7YFSscZbiPCkVQXVn/lKG3oablcXIOlpN1wuEhwza1xtGuHETUZCL2r9UcB7s5UtB4aJdpVW
bT+aWqI2bKPqnfZEhhOoDMLxLKfDCGohm1E4c5m9Au4WQ5bHEuM7nAh96yNdRyEuy2QuV90TQwpq
MmyOKlyroMei/8rbbtZHRkF5TXnFECsLgs70yaPLDWg4iuRG2YoIMGuqN+Uci8L86bASevdWe74p
ogZk7tEcHtb+N2LWhM7QQQpXwhqtHFJT3V7wvHV6jtYyxmuVGy5eOkM0uDAw/0FLut6mSobbBT1U
L/TD4XM6yJ4asHQDGrbSXGzYOQkwQeTyY3ZufAT+d/NiUf8J3rPPoxEXLxCzzmgaig6q5All5EV5
AuHp68HAqS224ATzpHKxLghWY/Aeg7TUUg8W+3vzrvlSdpfG7F4Gsu+BV36QA3Y1fLFDBupBAHUR
GLb+hBYzk0w0PShBcKxFJFKucl2Elnp+rmgF+L4JohQE2JGx3RkapNkn0VElcHqQKmDfxyt07TMD
4Q0KMpm2//3SxKqW10t5IXRJ00EOivvq/AdLmbIzqeaguJPm1vIYVtr384n051iE/UUkyQMHapXd
Rp+XyLQk39t8bMmXtFnxKtFtBUXHJAi0bVn7WQHpoHlj1lSaaa2S79JoerxTeZPnRNWJ8FFw4Cod
t1MtrvbZHxRIpl43to5scawcr8jJ7rkbruzn88/NkptguoKFzA5gMYgnDeqLU64O6NHrmWo3cndi
zqcMyMEBnFC09SWMSAZ0FoS+5jnNXerijdqQjrWFkMHEHAabOpv5d30IUSG4udbDgNk93WmHsQbX
9KufVVSgSfb9ryNTsR3jGqh8ldE6iaKk7peVGiDOEO1EmrrjZ2CiarSEx1wPkQ5X3sWUW2hirodB
9N8qJQcfBQ2JngMEW75ukXm0HV9FkIscxPYsvlBeZ/xnrPPclyTu6Fc+qfNmzCk06ktFa7jFd17P
23QcNiSucIt5f6r87hqtds63rOCe9+MZXJI8rroVWA6D7XpAt5iQbXmHItuu9qtlpV1YR1XDFF1O
iREn4YCjDJZoh6BAfNd233F36AwtyWz+UEGhPMDll/U5uX/sx3mtr+BB2MtXtBzOGaEh7WYw6lmb
8X8W8O8BU0blJPBL0GDtVxW5jLk8GuHClpcKFBv/8eINkhusJlm5UgcWBN9p1fa3/UQMpj5B6ID8
lVCioY55Qw5i18VzS8BGMNsHn+83upxRvX8oKHHbEavMBg97KHnrVoKf6YlKlKjAOTssfI++pVzq
K3kz4wED4jsp+owQPcgA2VDfc9vRIQrHPH+pCjCrrX9xNz0zpUK0ne2E/dacpVlW+zruvyowGVpL
yKJU7nOUd7y4OHCZb0Ot+jS2sFRGdLHV/+4H9a3Kcn5YWzM8OY2naCsWABxM9KmQHiEwL4pVLypk
oIDFonrFIYDD+y/BSAP81jkUYvW20Z8XUz6SeUzHVLDsGSlzRQwEGOeH3M1cZZgnbrzSrqerZ6di
uXKdEuuY4j/iqN2QNov0z4h4m70mVTOgzQCrnm13A6s06KolmoG++nnPSCbGTvur/KHuDPUZmhCq
NWRtgQ1ccGjBc1vnn67xNeHmsRBljOFosAHSKbhGuGtWN75gaWK62w/SqRu3jCG7e51OQJ2YQAE+
7ip2R14GuKkUNYiHE/8+YLCSJqOzccTnFBtlrrmgP2vYkvVAv+Oi27IUVCufHcL9cU9w8HfCIais
BH68UH48Wc+7BDKEwWimWvbMYCL5LJA/6znB+KWkkz11lzBL4v9nN/0EPYJpGJyNhWERDHl8qQY2
a9JKhkq9ZEJ47LetdoUxNLYz8fVF557l2RuIPVWkpCSA902Lj56yK+8wTVhw3Z1DpTQLYCBPNJxi
2jJgRWLf8JaNTc19Au/TTtoyukZhuGWlnE4sU/+I3ZzPxV6s1exSQ3G1ZZylc9Qxq2FNJR9hKQWM
NDb2XOZZqCC7okXw78B+izuc6oonrH2j1PNiFlJbtaPwtqfhMGQRzvQZ8MMQH23oRvGhslPJzppT
OgZ4zqyL/JDE37kuFyxTCW2B1VzI5e4A20dOslWNEKcRPaWcjySKb/YOxp9fBjyZbTN3IaRK37ki
e028OzM73UUDBV6XtiaMm3sY8CKlJ2AV2f0+kuAIWscZOltS9TlYaJO7VtFaja/AH8YjYn9jRP3V
JYCIWuViY0c0HTdpdWjTE355TIwBo2ZJhuWIaSqK/+on65VnksNuXsvxw3q5UrBzESSqGVxCSv6R
px2mxrTEFxK7XVqC5laNqw2S+Pl21YoGmB6rXYK6fdysT5ku6mmxvfQnHSi8AKWIWyzvOGm3+R7E
wJdEyCsqZo0lot1yeNDu2Yv7UgOEDNL7BFiR9JvcYXzET43gexT+blMewugh6wtnnjxw3DfI3wg2
ByBGzBv/FBno3KegFUMrwtXEKTTr5U9QcIk4btRGKkVFDTW1zjdpeTXdCXNWedCLHmYNP/cYNhTO
p/ymarQE77XVu7wXs5xBMM6+rGzlqBJ2hcgnsU5snEljEcfbdRujrtFrxNrC/xXU2ZoMXYdL/rMz
jxcwc5S0FCUY2NURUrlSVMAXHZ5buuuqvGzfNkekQmkytPQddM1ME5RTLzp97eiHIFABDcqJsy3F
INiTOmvUZ75RVfLBKMG/l41gEVOCsMNhC3cHDMdqyTVefv5/beSsgidkzWBO1XfIknxH2sPpd6iA
kmjhy77C04G6CoADitPz03zV2j+U2OS0Z70p12Ltu04Y5L2HV4R6oYQjYF0u4WA+Z37YfxZhf1qd
+/WuOhNNJT0I3x/FS/u54y2GafCFx2I/zExH5vY3DguwSRJP6LoS1IAY2FBm3wnyOGIB21AnSvzN
VWXQ0XsIwMLBXNEWks7lMzlzkAWLTE+toBuuZVSlEOxHNLm7JNhlevFNchXB3b/vH0IXyOToozhR
EXVipB+UKe6wuupfO7vh4/FoiJnafXUzapAUqFUxcD8tuESCVecJAJNOMiE41AWTYDcdP8rGIvFu
4hUfNl9/XWiiMJKpKh0VF61Rt06t6SwrIc7yByyN0rgnB+a9Dhzi3JJWT3nVNozIYZgDEgqQH0Th
e66F9jtlc96hSM+0RIxuDTPdvVaqY7Lle0DKRNhC59z8vxMBmRzGO559K/N8owttMFK+f5+Yoau3
oPlx67sBNa45grvLqyOnLKHKM7P/p/j6eHXTxJtWkg4vOakVNFtxejA1gVXgOy+R9nkBIcqw72ka
iFEpVRMrQwIuvz7h/0SX7JTmN9NTbOJq+q42akCOg0nVjKSAI11HBtesHtsRba/CiAYS7kKvm+oj
Kcr4jB7RUKa0nn+eeiL56J5GbZCKHYL9bj9Clso9E379SJ39xtCWyH8St/Kx5hmJe+4XHFc9VVBO
xrbuzCKRBpkYsgcHx06/GhIf2XB80nYjUgq4y5R2xxR+u6OiUYaNJfVzt42WcUwKbwllh76+OtwW
UplX7H+wskczmo5E/SXZzJ1QPxTkjITzz5uXOhoJ9sdnm0I50w1Msvt89FmRH/+KzVEUutzXqpY9
nLBBG7r7Pn+fsAmVU3y8fvVT7Yqcji5D59lU+KaIaMslc/OxwY0d6+64ec/2iaSk/0P2GOGA7AzP
RpCtFvyd8+wOLoyJVxrDByA/DoQ/qapZQpTHed/rWaRKYP0krD3KkA3CPkBu/rHG62MkV9oqKbuv
zEPjmVtzRd6EApygoelwF72bAOOSgcYEvadduHHpH8fSR1XQcQ5cv+xQDbvYLTVjSLIoF2fordxR
L3xKTuDyOze1a49tASUOFRJeqZCDFiRw3wW9J5ODOhKgoOWRenG6u0Yk/rJ5TNMsuriBkGfimW8C
WOtcg9itTIhJgjGAOJ1Xxcd2TYrPa3RQ7B3a7VGw+Rboh23NxK4C623KOxWBfvGmwjk78nq/hE1C
CKL7/kJG2aWcLzmLvrIYJU9EjTg6YLA7g74jA13y05SqlgiCZ2EvoI3euR640Roc9SA5Q2jKDhDj
4cUJ78066Ze8tn/42ukE+ff6ROyHBPNC/FFzidElVqkeD+TBZ0sEwNztOAq6tB8bAKUm1vKShwPb
9QsBm+ihrhPGaISOyGe9KcJhC53g+a1Jq/FyyRPtnThkrvUJ+W2g5lZJoypAnos62zcVH23RIZIJ
HQGxq6zYp/S63OIyA6IwdnNXJ7Hhgo1zHKoDM5MOWlYHielaccNGsO4jfkLvXTDrURgGScejst5c
9fuKLYL3w5E7JzNqXEX+/Nt7FZ29We+Q6S6kYHo3HhalXS+N0T8safejIWQLg7IPbB1FToUf+9Z6
AspzTpaPtpMKfZHlu9D3OcMNEvTkDlR1RSNZJ5qDIEsScG/IU/4csG9IczAamLRsGvUNy5FGT+2b
2Y+X2ZH744kv3Cz6d7IynapBTqahs34dANGmR4cCX9qRnLguOBKbxpFOs6lZQtQuYmIO5Hr2ke27
1MbCHq5g9uhGTTaxjuVvK7LOgo8CBCA2/z2R52K9e2HjAIsHY8ESxDD0bnI8oPZVG0BUWPBClFsu
NW3/EGQk6kXNRCz8FgRXArHHMXiCil30Z3Qm1LFwR7Nrutla21E57Xm9MOaOnh6j8sQjFh1DgWNc
ol1lFFRzbpT6qhgovpH9++so3qPWm6ccVKgQnUKyzaJYfPC7yRJNE3IVKdmgD1ARpbeNU3QKWB8M
BJ88locnBikw6N2JW83ul8xU+u/j/G0saC9dUYrgIRRWZJ3HkzF3rH7fCfpvL3Sqhyp0Kh51sAOn
vnsMYnec84nxYaMEfdKEu/8lGVaWDN10ACzXiU2y1oR9rHJWL1Q2BGR3On076sgcE0xpzYE3GX4+
OBvDBZUOnEDd53WAYhC1X24gk8oJbzmKXkrso/XObsCv6Oehy/n4r/PDxEkahxIz70In4Q80kc2V
vbtp5BDO0JhwB2Q8PLc2DXwMMlU8NKriHnpxXRfiO/hIgiFDUJhZm66VAotZMFh65PpDFOWaMeLc
PXIMejxWWbFq1W9DdWo9dVNWltVfW9hnbz3uv/R3L0LGtr+f3P8j0fAyk8rlkNWD91HbLwAxfoYd
h0DkuZD9lNmUdMp8pfyd7qyiR4lq7YuLo1sojeRQljsAWOwUcKQzqtSh90XL3a+zz4XKnyT3EMIE
WCP3+7Ka0keFLzpTn+Aeo9MjvmqFF9oAwxuLD6Eg5TVzA7PWgc3AymrM+x2XHzmQkiO7aj0DXBke
Al4+TXlJHHlhMpixFkczdGfhfMIfHllCYcfFq4AgwM15yNoT7sq0A9ApsOtO7Rmh+43JaT7IVWtj
5yNTwdwopoPfUt8LwZp11Vz0HHuwiqr40W3h8FEp8KxZOgjF5kFOiPwBptcq9ocl+vhqMplqe1jJ
hSiZa1pGfyrFC/aVVpju0qVFPHDGau4XKPnV57aXSilmdUCk3+TYNrFFWBiyEwsI2zHJuwiNjJQK
bcQrvOg25vwQeBkrdtfm+eT0EBh7ckpiIWkmOJIZlH3ypTYbpoa6hGtAbF4bSGk8BEYBiA3QLCPQ
5PQzERZVgwdwPRc6AfxkNle/3Ygu92dF9IhPSUg62g6aGuJFtCvbojSYTRKyAm+OVeef1uAbUxX7
iY3IDkkaZ9CkGFh/R6H28T7NWFjmgoC+vsZfVV38Swoj5a0H8oIiORTZQUKTSJGGmHbM8vIJK8/Z
9IlZapnfMq1KjBZkricRdE/pOaqRWBEY/0mmySiQOi3XqjqSE+9T1sAWG7isYYisu18Br68q696n
tdKQWsEtO04qjZXFu3Mmyln/NXs+7aW2FDaDZ4o8uuLA+IS6aQS1PdMzabcSjcrHebWRwpY3KCv1
kdXzLnJF/dtLvXRFRbYeTiYv/Uh3ivlYd7+D3IjiHIvWdMJ6I7Kcvw9Hy/J8avdtYUX8SdkC0N9A
snw4y6oDOX1Nk1Lf93llIgYJfz+0vzyW4KCVfjFuRUe2HlbPlNH0Qevf+tGgHtG4/Wifetsbc3QE
ryxJJsmBzJJVtI65QCSptTIBiRUT0binxL5t85CIoKyY621S13f6VM0wZharyFd9+vk2y640O1U0
sL3FgKMRyfa8A6Qqz+COTOy6e+ra2ucLqNOXrMr5utE1zGp0P9sWNOj777m3EHXIC+xKMCdCIe5a
IOQ4v6tqOgZtRZe6TTAo8g2rJD69HRuPuJ7jLHb7+za7bYybOW+6bqvGQ4/xc0Jq6szkO2PxSMxJ
dsNhZGAxmD/ySNGMGzChOS+tIStfjRU2UOyMDVxOGbimZl6RSIKZW0KOnbADKY0mQHRV0PkLfKtq
pwi1VpQa0CLaETPFI0rbV1YqZfaedHU618RDLPCcpbnrJclKy5mcY9i9IYqwjbdMyYZSVtQ7KQQP
qX0ZwQCX01Akxvzj0W5jsFXBTwqZ5Pg8QlaKTpP93YDwNdcv5HClvowhOIGPSanaXXg2mnDTEXx1
92wPOGVEQhQm+YCkQ6DY49QIDas68PTR+HR7Erkux4SyRfrSH5ttnHcusua7nlSZzafyj5oWYh0H
6z/+ZeX1W96DRjTJeqqmPOKpVOn0+MgwufmihTuxvVQqxK5sWulkjeRpdoMFbDLHrYtnhB+VJEyh
dlxLsVu6RXw2pR5iQOKUSaxgIhLTBL5cRPDnRiIQUXkMMPEo6j5F8ZneKsC23lvudQCTLGQ0jAHL
K+h5b2tasQzAk5YFSa2s5haSi9MJEXD0HGH8AUkfahjSpk9jnV5Z3+DO5JKenFh0e02avNW1SWou
laZchn5KhA6I920oGBAvXfxkyu/O/Jv6DGJubBTuNq5wyVlrWPWJwxH2bYc85uSUUYoTpCTGa1PO
+HmvSUFHXwEkonY+rpFR8MwoDc2Qo3AiR1iMKyhppqFj6VKaqDJXDGTeBbDwWwgqw+XQnL0ktdki
Q6l0t3pJ0GZi2obhlK7YfFqZl97Phwj4jVfA0J4KM1rczFLHU2sAUlBKrpSX7m2HEbqIpfX447Yl
+cpVESnOU8eqXZ27BYUcTMavAjyuFNov6hje4lKmtD7db8P8jl6UQ1qWcgugq4PgcDFYPvMri7Ih
ibm8nRZkZxrH+ca97We5zBW+m/zBHIs9orq4R1L4P7aNgjB8r8Q4MseKlWyJ2bCebsC570I+xsYF
+yX2joEApqD78I0sCYFpdWgTb6i0XSne5zJtJj63Dh2r8gtUsGzkVZX1FK2ULRvnjtn+Y3YT41Tk
TW2Ohhab/XHLbz8tIaVZmjCNimIxzFOj+fXnEIz5q2KhDM2NpaYNeTbc20CRLwq+jkN9ZYSLVQKq
44pZP2HzcXzd3M+JajLy7FYc3ky4cjtVqVUeVwB10bH9TAfM0oITSgYooAJ5S3D0wL6jqG3AUK13
PN4OfYNZveSmNe3aS4/Xzu/unq+5iW5/4umjIPRC74MrvZ4YxHBAOuDh+Skj3pPyddnnK0lrhJ9c
PuPwT2pOJ6PEeWH6GND2m/piCfN3JhgZtiGWTRIF+5AvUYSXkChSHrf4RFxBtB34iF17BI81M9sp
g5+UjFUditXlYku+cIPtJwb3YC/dRlDWlVsYLmi8cs4azHFTGIW7Rq1tpb+lwv6q+Y09V4vdYAji
yV227wpyCZwNS9waSDNcYcvKLjaa7l21zJyDi+ZGkf/jmybKAi4ppVSLrPlTw03FVZAN6PhOtuDR
BQjBtr/HXjbIcFtXMRSbRucJfTBzEdzWDdUQ8vRHl2tDdr/LNw0VZBAm4dgkdgpcLfsMWx+F+H36
2P7yXZYhFlnCGipg6S9r6gv+DwvWKz8vio9K//zgPRZaltM2X9zEyadX5PEQ3KTxqdUayIs0MVvj
3Bo+HyFClLF7EAVYgGGzVJYqE1SQSTdcoaRhCtTUqf+rZvE5Naz0D/mK3gTfk4dEU3WwvceMwpbh
toaodUTYcZENTEJG0T6sP/AAsBcFo/6GDd6t7ZQE3fUC3bx+8RgiRluIEetfuSJ6yFkWfM/8xKEP
807ZaJ4xNvw24MDkFPcGQqGRMJy9dC0q/8h+IUAnIWvPxylchODTZVGpDo20wCrRlEbhF5FHMtkq
S2OhnnVxJDOhWqfnNFj3q62Pn/vvBfAmef1PPjX57X2oHrMtTjG272rkqY7EBM9GMYqunhnviWX3
RQuD/c8v6Y4SDnwWcAMcZ3AUKNwbvzpY+1Q+VV4GWnsaPLz0kiw+RHBRlMEeCcNX2WJx9HwU2Pyq
UXIsif/fX+nmxrubmHBicP5AfVOanVkGa5kXopXWGoO87CVdfQ31JjIB738QARZ+b4KUmXp33VOb
wKZN6FrruEJMipNenL3UHaR3Hf9BNin+7OtI+GJCiEA51mDtgV4aVNUj3xrJ9JgtiqyJNZ/GNvE7
op3qVk9ZHQgrErrjTznFZI6nKraRmdDSbgrEHXObTP+v1PflA+P52cmUcWLhpvPidd+/KQDtwQuQ
SqDjs4KV+IK2V0eJsV2meOcDXmb03xOhK4AFxrdit/Ebz3xuNut+kngQRHsJqMPtsNCe0QLZcnRM
Wprb4vBygJbbKNO0i3GrsfYesPpRZ1ZDKabfc8ArUEWNOpKmAjfbEirCgGVP5kwWIOFvR56tNbP7
YSLfUWkkXe20+RHCQkgQYbhXN2zTv8IQV4zGDis39LnOsEPzagnw79p6o0ZOBbxXtw1Tb+DUiTFX
DsCsI3v/djv1UUsYAasfK+EPO4tBdWPDWWYgRaBXb4qchMG+aeTJfWnkOoVgRmCjNDdI4j5BtSKN
ZFq6ifVqdjQ+SHXlYdxOSJx7+zYjfWbtsQd6HaCCq4P/7a/+elv31Di2+q+hYnU4WHpCQOYifdZD
ZK9U+JfCYuploZSHm0dJYIFyMVS0Dnswlb/HoZQvRCWCKfw7Si7ml49pL4OvmmMyFe5gb4DIlDOB
h+fxXAlutkBz5UBsZWqguzzMXCJzkJQR20u9UKZ96o/KesogCVRPvQczW3OavCOPcmo1jrTmjPhq
bvwcrrIXSfErSxKKod0otBK9BRI4dBdACuwLjMst+hqmDzCwBxi6f2tYh2xCJFF3KjNR//NggLk3
ZMLIUZO+jBkFCG0ZS9avrKSmEXV7YIGvn4Bw4KFG2qnpZG1zXbloN7OOTIXa7J4mVIHdO/65vXrr
nbheQKw17l1SWSurXUebyrsHb8tZDunPBQlsYVSGgyxXkkWZV4u4q/6mq9ODEUZpCa2Nsz0qPlNZ
3LWrrz1cfrWedNk6aXX31nlJnQ7WYYp7IB9mBjDY3cmgXl2Bs4CaxLcEaXUOLGhyqJsVc3bdaly9
5pDBvWNnF/eLLMHJfqLkSUrSIhLbkdrIpl8LGM+bc+8+dQEhptpXmWdKXXjaWhlhLuhvjpfKNJb/
XBuyWB/7uwFEQaWcwuxheH6PIpWsYshtSqwzX25v1qzOxipIqdmIsPMKipgDiDqtrHkegOuGY3cX
eZHuvr6wyHZHrkuA7FpNCgjRUkilXNG/tFdiF2O33TiX2QlT66jHA/8jrswfn/HDv4vXm3CVo4mU
mRk2jeq5mdCOQvGwWvWvmjryFRDofpc5xCQyzFwxv2+MQnABjvHzWUTqvbYrfphleK9SHwu1DStt
d71b8Dgv7KbteWhdxMjgJK7gXLvRg3MxJ19yxMjM5ChXCoZEWPH4lQpHRSHHHU0IlnU6gbpOxRJb
oehR4FwV/wARidXuNN/NdGIADum5S+h5VgHfRs2Bi9O379rX5404fIcKaEe54m4aRB7Cjro6l3po
2qtoivW/dPmFjXAGJvGb4IKna1jjWI3HuseIYrUEVxnYjP4Ngv8xVIlkrD/v2XCkhOvuIOgBg58d
G94bWrznhUG2WFcDy7Eep98dvsuBfB7/kMmAzcxh2x0TyV5VXYmnJQRxT9H8fSBZ4KhrzScQcgA3
sbFOWaZQu4P6Jz+N6Hoez5bTQjiUfZu2AG9NhDb4cNXcNI8VNa1R0U6HYd4Dd0aNUmoGeB+9kkn9
ENGKJ20gmSdXdgMvGQf+DrnS/O4NtptckO6RQ2n3n/NeDVnzXxKJ7tZXWEpkChmnQ8e1lErd37gd
52ZWoIUlmKU9N5wLLFQvSvUG5MwwZO5BU9k5OiucSXbIzkdiSw9pCKvftt+cCF7KCLYOV3b1n1Jd
G5ILGMu+YtoKEYc2ZC+ArxDldyk3do8c1EjZsSnitxsl4Po9Im5QSstt5VhpnRi4CTRYzfGOFK58
uyRFgVDq6Gv7sxfRlo0OPwdji8JBvTDoU2yvk5xuve5Ivgjqmvj1ZDuL53buv2aQmp2zqizmmpHV
ILm5N7ghlrV6nsRyDrVC3MlP9SWG8WQ12JJ6Q1fM1DkYk+IhywbYWSfMoQdauxHHzbQVyOdIhWTS
/pwwBHeiitFI5cMFoa1lwKr+F5Ydmm4/xPpcyTXXsaA77Bi6uCODkcQNKXmOshzU3xNCsVujz406
o6vJfPXhJv/ERBzhwpxg/jVguE1J7FQpPrI/SqXV1qqecidD20hSrU5i327SIuLbGLkfX79kn3eD
8vGZwsqvFxxv9nEtDPNb+i4fvaRnP1td4/zB1e3ioMr3C4w7AwyEnWn+BwotbOTsZ0IaYPZXPBe2
FH6MBJZzhu73KNJol6lR/sC781RqNvvQMOCd2NuyCx1klJ27aIM5OPSCQmCeSo81RAEXMsBxBLxO
WCTwc6M++FoKrsYHFQamjB6/BbvrK/oqOFuUTaKroXYCX8Jc65EySim+8xwGpaYbzRkoB0k2MbFP
E2hnugikCRHFubxLF5bHZQ/M5oYgFTHj5s8Z7IiZNsR/+4+wl/T6dEnnHuVvzzVzUJ8FOxvN9Y5z
7ODbJbWDbwdWJiKO/MP66erub2jHIDMhy0hrF9LGg7AvGgdVkf9nLOqmvKMH2VRDtxE7ccqFdGcr
L4MWFlYo9n5adTVHTqASTdDp07guvhXMVV2aKM9arNx4DPnleDhupA33jeYfbwhcmD6TSwwUeTOw
cZPC01qLDNYR1OPkqfnzeB086DZN+Akx7Ro6MfQlVG/iIeUKoap8GSnoluHQNgaa/zMQLxwozf9n
nfq9WOtMdhZFW2CJvOS9AFS7FpCmde39lifPnDnamZv8D4g3CR+7BODd6x9gIa46jOlPZV6+EkYj
OhsjyLrti3azU26cvDS1iDEFpzF1x6ZOSVgIzsWpGAZqm2KXR+kWODEbc2kK6810H6YvbuceVwXX
zTtVep3SrMyEQwEEKfU2zNv5LR1YYhAlcsB0TC1GeLhHXu2spuHtrhOXY2Yu8PJ8O5mpE5J9hciy
Jgv9kxjs6V8/VOpySoc+DK6RqWF+1LBHI14Mcc+WTgH2LZifAwuAc4TdLXOnt8Ftm7toeK0GzuSR
n6T+OPDTUNkGZo/TxiHJf92SGdgLQUEhsav25/7sKnYRHXxLyqkOM6Vc4MSuQNbisLbVhx4lGxBh
FZplG3KNyOXk8i8uBsv/q84LzmSJXKwEh9+8icb9v3c9ZHGV9fvkR8Ufs9ZKHPv0eQObFk7rDe7h
vZJVlbN+q2yZKM016zB6QeFHEyxnRfxWQpOEYz3OX1UQzlm0GzfzoInIq6w9EhQe8h9mmZHwFPUz
F54h0Q/34PAsFPUBiL3Dl9tZ/3xn977shr8ZN6vMYO0YYwrsz2lg5mt4npk6mm9N/djIiCoXr1vb
RfmtO/HTXG3r+5vpOfO1eZgppaPgzjpoY+HvUMFul5tI4fwOJczwUS3LAqKHjwSnq0EXsyJ978fO
N24zFPYt0VhaQvePshnGuv+zrHfRaTgPduzyi/qFmwdOhNq6i/IaJXz0zmyjqJcdvXeqe1t70Go4
C0t1jFr3Z/X08PTz5h/sE6mShw6eONf4E5wxQLFzZ27t3nvwq8dMLekzOwWNLgLTu+N0Wv3j4XF+
rvPiXqn8C+PH+qoeWY66jronBiyVRqe4dfLzSYsGRoi+bXI9W8h7P0Hh9eZsxj67AGKylVwhgMMa
GjcyZ3cQCTXtcixdBpTFWskhob2smrY80uKLqleJ8o2E8z7Y2DmhwG5UdYh3yI2mjngfXa6QCdxh
60mUkO1QX1TLKXoA1PfTyCIw+XTkRDUoJkZVh87aZ6NLIvxEcNMKFhN04+T6mVr5m53+syIV8p9B
9x6I+prng4d8Vv/F+iLRl6vy5JJjTIFfN6T7ziZrYnkhhvsCfgRpzJ/WMwCmGOc904GwDj2K+0vv
/vj1P+md1vuAsS1/ylhMIo3c7PTPtNtHLFmHwmRo/Ny5R6zi4+5POftaF4l2xHtjaW2TB+b3/X4Z
hgN0HerPD3uDmzhh+YVWEpOZhKH95p8WOlw6Ah0aq4NRSlDsp+jjlGpBGsvA9UW3LYHnkwCvi7T/
obi6l9V4KEtXZNScKGN86t2wPXS/xPkokKEOKt4/YWspxj45n8GZUHLPbMrsmZZ2xaMZYhxYe1gb
Cdfc+cngj2c1OBKqRCdbD0kh2g8xOv+DtQNAZNSogyrKFM+74UqSKYvtbIoofSsnQrCeVV9CJM9O
ZqVB9JGmmMXgrFgzblDEdkJVWw/zW3qm28m3LtW3b/Pdgmz8BFsAdfAc+tLR+NxLF7wWRhMsU+G6
WW9/gePovVgUl8Z/5Iy055HrU2bBs3uRCNwaOiV8kvGl5vUFFzfY4eZ66kZSORFgUQycZ3vAZa5z
C1SpM2eCayvUL9cJDLu90aeSmHo7Tsk/GsHJyWNkCCqnf0SZxI1dJ2jtbhOO/j4ofcWbxfpEbHQf
y69in0J9xPpdbgqPSRzUp3sFLgJWtgYmi8ChN0BWak5zqJyPSwn9y2jkkd3H9wpjePNRnFsixmIS
GDGUaFRk+DpxxRzElyk0UYQiuRD0M+aaIWWb8m9ZhUhhcZKw5UMBFESu1sxhclBwX6hl1gwSoSBo
CdOjChsOS9sNJoPqoq86ijViriVyD2T3vWbrr35McPMzSvHRs6nAvXaJT4+WrjJOnBK7IMM99KLZ
j0MswSXaibk/bpDKBgJsNsePIRqOQK2UM6RRSFLsE3R+7O6infInPBQIVTKjHDJg/IetPbYnlBXc
f/q2HoFVXxKKNL7MfMjYKfzgIOo7zC4XAPpe//FcknP+77Rmn34/gFskCKHw1gs4a6oSXl9jJFau
hDuKieIUcFkC5FWEH3RgbE8tybIIDzZGzHWF6bmyAukwM+k9i86hB2DshbSYdun5JHJO/T7g1cea
9/apBAEJ5HcINLunq219F5ucVXaOFbAaUA+LpRWJh2PN4U/rz4n1/S45k3merVqxlAG8QRLl7YV9
ocu2s+I3ROf85SMsvOrNjdSWmPAa1IZ+3niuLFYIgyVIldgiX+MpogA3sgdBwucPwd2rtqVJG4rW
GvlQ1eM9Jow7XpsiXE6EEe9Mh44AmgLtrCXZFZYqZdqsxcXVxHbg7CXrhoWw90uW06u08E0s7j3q
mqgJkIetI2v8O740k40Z1bagE4XDG0EmMdAmqbNPfqQNV/zrDFPnjAmODLzKwgibnrxKrdz+mJ/g
0An4ZgHu0EbjCn4/Ae+Cvqyq5hhT2ppACBbKJrm4+MEhJRYJWh+Bq5PsTWjvKcQyQwUtZ+SmKYYv
9loF7My7ejZuzXe3aRDThkhpfdS351Zg4lBdiRZjUPD+pnaGJgfo6XXbo7hI2wWlPJCAQ8HR4chU
lkVnQG9Rooz+U5zg1tmiumT6A+PWWhzs7UcIQYZnmj/crDc/rh1rF3YA7vci1bufuZ6AnLXgyTRV
jL1yjGPxC7AvI1CWnl2zIpcrJMqk67I57muxrZ80bVldUOAGOn3WGA/osOnr1brzTvezRdVZnL/8
lxk9EiSPllAa/rNpaJF+xVZNCe+blb0osNtwlyvfOHJgtA4ijTTjHIpi2Qba3yyQlDvhg4olIC/T
IG7ikgRSq7I3XgMFZa8mSQbTQnvISHzwb2K/VRvIzlzDursENZZ8PEYTuCGnYxNc26bNanqHfiRu
BN3wgs25P5aVe1t7WV7n9ahXzTSoUsrDLbxrR8lD/f/3kK5/C18SPRsh3NDZo23z741z5pWbrXJy
tMS4k6S3rE7dBeLt6AC2JhQI/TXDF6jrFI4MjcZdpYi7Dh4TIQnL1LbbKHp/OuHQV1xnLKU+95DU
ar2eq/tzoxZFlYv2/+Mge/Wi/SIMZWlS8s9wdHbRge8ikrv6RUR8zowqzuQYTIiSvpoFRXCtH0JJ
+HOwbIox/sJ7gfo3FApVLEGT/O4xrjxbF7AwEupkmZpnjKrAum1/vTeM1BQtwrn7jNiYqA5pllFT
WhXpDZq5OMDEXQ2sRxnjnKbiTsZ13w1AhQQonWB+Qg31nQsQUEc4u/nSaQVpl9Vcaf5jPaAl1bsY
Xrc9ATmUsY2LYLHg2ASt5GQ07BsJGjnotNenMYPnO/BOBN1XanK20tGoexKCU8bPFhWD6QstDh03
XgnqCIEp0sO2t1maw5rnhm55Cu/KBRoXnzo/19I9vtf8sRTpTn4UlEiN+2+c583538iv5X8sb14G
daZfCR4BQF54gei0Q4uA2yx62SoA6epIJcXlra3wAe+wCbNdQ9fr16SJyn2NAo46+7sJfuNp9qTi
GziRrymj36HlFZJDQnhgHFYckd6U5rMkBZWi067IdeHJRGX3CDL8x3LkhMwGP7fIo4agbuj4u0cp
1sbhaUjoHfNcEVdKJ7Dk7zt3N5cynxAcZwCt7+6P6CrnD50SO2eZv6vLLZk3ju8uZm7riVAffwke
bMBsOaO5XkC5nr0DCHi6ZJZ5M1ubwjxgNKPF9kWbjD2XKXm5gSS1Y9kXrSxYTfe3FLWbmHpxBTtf
0Vi/fWA2uAWyXLHNSAkWQLfY6OgU1b7RG68T8ZAvE7PYtHx50xwmepB3P7e4wLyXQ8/N5CSq8a95
BGkg+oKHYw9uGi3t2LzEYjnacS7enzup8xNTsgUYNH2iNY6KhWB55ZOz+Gum30EM54yU9jCANg6y
ZLEWPBG8aDFxta+IdfUfN5Q9M6lvKSWY+JiR2/XevswIva9XZC+4axDajDbYpmy59cKGAIlzKNu1
Ds4i5s6L0CVKP/md5ibsj7c4EH3pc9yCjvI79fVTU/svni/hw7mzjEHGdreguTuctePDovY2YwcG
UpCaWbc6Qi1GNPjHRSEFilVOiEyW4HO4GmSigy3BcjEpUIRsoOXN82eQfOvf2+fj1BNu4E4eqkIf
flwSG/TnHzr8MmZN1twpMr5g2iuTtjekQ36S+I6nUzJvrdpboH8sIkADwqhMzMTBMArbsFyIbIG5
DXrmsOpda1vR3mn9BmWJRGFQYqNCjaNjImzDUVbfIbg4fqO4i9oizGrKM1DLAy2LvtpvxDAWvM44
dDlMn92yY0WIKB5ib285dOfGGtm3tBr2h/JCUtl4FtY7aDCWar7xsPOgyrsyTsp2idZFtJzcQxF2
MJjSZ2nVg3vCNsfBBC2UT7ZKSaF0oO7hAKrnlE257hxtYOAYYv8RdOyNQsy8x0yImte5ilWALC7E
LPkvEbr28ftLMiBSZWhqWF2CyVfL0vC9ElUO6ThGSbLHQ9xxhnbSJ2sKr1euB5q7vH7dHGkOYTHP
6pz4Ien0io+31J/JyKGeEkKi/DrHZp9JSOh8V0cRrUXn1PYfvmca4JO5OF9VqqIiZCPwYxYDFyzp
oWitGn7zfZpG+FpmEOltTyRFnomdWOSV2F3F2aBX7DWS+eNcVrWNyB9V52feCHs5Z10+2nOcldrr
3r7ZjjCzw2wHZHSY9G+wntKyY71zEqCyTDdmL3/Sk52k3WrkMgv6m6d6WMgwwr0bU4a3XADvrfkO
I+Ydr6kfqCaMT0tJMfho1U85+zpTJb+9VAWarL+GVWPq+3DmfgyQspS3dT+P3MgDxZZN/W4Gj0q+
9KXEc78KQizRp1Pr6aJ9pPP/3Hqi57VgoPlKv3t/yOI5R2YaUAMvK+upcANqdonw1o5iEdukKEOq
zjYwULOIZJdRuVpmNzJ5y3yY94I793wvgqVi56GscywjEmmRUcjb8cE8X5QxOyq9cNbGazASkyev
5vL23YzfX9Aqb9pa4Ltlr3xSK+Y7mFFLOo2QKXViXhAub3nwEvm6/1+omMQjhMvO2rJz5lZ9sX+B
kq7rIepVvTcRN4IcUR23VK8XUSx1ShMaEtnaUcI4hkaKSK7dfiKLKGRWmH0puKHm8LBzdM+apZHK
udIpkuj6MaF2lGTOoAvqW804HfgrBGUnyq5IO6uNi8SXnowyX6nhHsAWDr14Oob2q84+85Fwdtmd
U3uN0oqO2d2Dpu54WQbRSCLDE5sSaLqhclftuQOLQ+S3mxwQlwKz0DDFbfHbI14cp6vV3729sEq1
0fjOX2F1NMnP+Kp5P8gNQhuomJ/iorjzUZ1+rH/y27wOkVbBnxOg2KJuRVa9Brn+3IlKtWotONOA
8SUw9hh7/c5lM8fsAa/JXEBKJ5U7DkXeib++nu6CJuy5XAnLoM4TGuUyIPF2HGYsjouQ5z0dhHFn
S0wolnJu7Jy4NF7R5/mK1EzrRssw+3QD9yWl3V0OrGuSAGlX1Eo2EsOZVF3YGIfZD1iH/ZFSMPy3
w8PG8o09EziXX6xfFZZ5g+WrY6GZxO9DfWZeSLWUTiAm40BUFMRbJqTnc3CT4VaaOZ6ae81v5hu5
Rl1KR4CHlMKLXrP/MlSc6AOFSScXegZMNP5gk2oLgEoJJgS/1Z0sKmcG8Fen2EL00esflMmQS7Wt
rz2W4pGV5AiO8AJYnhib+aS/GxJGZzcwRPc1sqM3H7FnIXh5d2GYDF4kIPokePUWzAU8nhiYm6mp
ffAWsNg2sk86Zx0e7bMfCU6jrSEnidIK2hr2qu7De0rg54u6wKICYf3oiz0VbH9MoX7n3p78VX29
kubVF0FkeHOc8XbO63v3Z0XuF7hhueUODh7XxJ7nLUY3G9s1vTF5STPPt6ZiXkGWst/ja2MRih4w
zQ0EWXUvkiko4c7SbxIbVLgD08JVNqRXKywDhUII0Yk3SGCsnGpg8yoi7UNoWYEkEatFaALStNRe
0Apk6eZBXgvEfUHN2YKN+5YRdGDPbnPGpvBikUzAfdbi9CyymNoGlob0q71AKDJt5IZFq1COypsM
2pCDHG8+A28z0D4+pty52C2qn9QKxZjaWdYbMnbOwnZPpns2gTFBPTA/km2poVQXc6zv3LcVoNRQ
w+2tZtI4ii2RvnHRZlOJOLge4J70mylCfmNFQ61i27hluKiNe9kQ2eqjcX+y0DVPa8NiCRT2BsoS
Ay85RJdaAIjj2rexYS3H/HWL0wWcDYg/s/a/Zt3vaarMmsP2fbmJ4Bt0HOaIslqSE0tUU37GJh+j
dMnS4Upi/VTTjij3BID19x+B8z8MPPLP4tTI3Ii0VhRCXmTjpIhFq8ytj974Fh9jT7fUinNEZrS6
JDhuQELgXOBhCfGkgPcBaf5KeLLon3qA1ZG9WCSasn21sZQTAyy740XkpUtXJPmvWTSKoETNi52+
/LhYXEw4pV6XtZbpyHgbNlt+WwU/fSwPJiLGHr0+AvtqZ2FOtT91iPWjD0Sc2OQE1UmhCcMBxInK
rKJ44x79CZK7p8r7lXyg5muGcoPas7YL13k1tEW7DbGxkrBHayPu6sE+/Hk5Dt2/U2umcFqLEWf8
bvWwZrBKj8NvUP3kp8yu+D9aDiBX6lTkhf33kd0fLhUCK3kKBx3yMLTqUCKsALfIODriJDkPTIBN
N0iknX6g+CSYFwNgAFj9vu9zrsmx7oYRXYbPSvL67XR5UI7mJmOMjwPEvHzUbiw7AqH0Ym2x4eg3
YBPsWtadhEX50awCXiIOWycpRAe9EJA0BvdAzNrl1pIyS9KAng34xnHPur7J7ZjmCZs7UIfAsGXX
z0eY86F+v6awXbkfIrNk0Iw7NPbdKDQpwXt7YICQJCJmAwK3Km9Y3+SdhrvHtN4kB/L4NxS2l/8h
iktAkbgy2+ANiWz9OFwzMB4GYhK0S5mCLa0N1s/mT/s/2XcZSyIL7ZKo8Zfmwh30yMFaO0nQ238B
KdsXacy+rl67wWzfsaLB1YgYo8fwYoUecFsICpRlEmtTDVUE728g53rNCgp7pPkg/x/6OA2a7jDS
z/ycnTieAOtW0DuxjMyXWTYeT5OE5p5/WtfX8dSbOzwgKKNH6L2riSoe3QqfAfFCd02SmNnmzgnA
vUH3V2VaEJckXJHA7MVCESL0CbDS1JXIHU1P2FRSMLTIf13hdP8zsJU/cvD099gc0+L4j4W8fZqc
dcgsPNPnPQrmmC4JeCsxuusYUSPWQI0xHmtawZzuqFmVfX1upPGnTbwvrKd9lr7pMpG5cPLSWCx0
CqIIz3ZN82zY4MWtqPJipas97JMhLt0KM6vXPGb9apE+MT4Kzygv71VlmGx3WLZYcK49vWYSa5xL
Y1UcKEKJ4ADHbWBOS1WcmMrmBmXcY9En/LZrMWi/iLBthd31Snz+wEiCaRZUTsjpcMXB1Ai/vHJS
R10//kk8qm5Jj+ZcrRjBGCeeHX4bS4Qk3wFcMuQk0hVf8El8Z14BMWkJK2O4dQJK07qxguDjqsLf
hpSUdCtepxSlcxdM3sBSdra+GZJZe8R7kZshVtjHqngMdyEu3AaxzPibl0q9Cjp0mkY9UjhWvYCV
5joc3o4Uiq+3doaGUvbDp3qkaMJRi319R77L/QxyEYrUFF3qHz4bOjFjFndMK71ITPH+0QRbKOLB
tIes+3Fc/U5SceFF6kOcvoIvegbJSEsVZ31PFNdx1ySQhSAUYqfjymQS0Kl0NVWSDlGFl8Z84sDB
pnJaURejLAor6VtYuP2ff8honn3cyuzZLdolyp6usefaJhyLFhNGAKKm+m3Ge326DaedV73ZiFNJ
VCgSYLrePn5Ioi0UPvZUKjVc1ulXJ8c4kp/Q59ZN+5m1r3warv0OA52r/pXWQQyWz785kyje0oCP
8AfgHgvBMfxc2T85XydFx6c+sqmR1fyT+e8/PJEPaDzKfHphudO0PXuTpBcHtmMpp51qiAxjGTJ5
F57+KHw4dTHoecrCDePC8NAOAgv7cdn4WgyNsbo766Vsy5PENw1P5SbmmuCtORDRKPVMWkhflply
bxviJ+UPYpF9TDGjjSq1tsVijp/V3zFfImf2BKz1UBXQtWBXuSsFrQo4OXLnrel6Ywwre33XsJyr
If1M5LhBKT4aub58l0/DEdcUABo1/sCJhoPyMyVDgoUobEd23rgKnfVPsO00Y3zI3/v2AVoBAnPt
vOWsG05D2y3LKyG3FB5yaOLw+9bCGW22+EVO1/FF4cMSNz0SwYeFJoOQW+HTXTljw2mF7lOkZ0Yg
tNyGq3nLxEka5eUNCULUj7Gtfi9wYCUdcsnJCr5F+3TW4FCoQoeQSRANFHrRBkUul4/wiWNF9Zqc
G31izJwCd3UkDv4IYbnKS+h5/hn0kEH2sfVnFAOUuOTgh640Ex/stF2V+hOvp6Mo/snqJ/gPOBG0
wYO97QOP/684i6VG/qNYxSEGcHIDzmZaqP1ddu+C+dDbb++nCbjA9Zy/oqV/qN8FGzXTtXFSsY2n
OjQFieo7mvzoyi30sUdQ6iODUbXc9s3fJQQ8nmsNPj31/HmGBxcWY1qloYBxQH8JGQvdcbVOWkpr
9oz4lmis8y9SVE2/AyPVycBlEecLu1JmX1oIPVdJMtOKfR7QE+U8FEtq/ay7InkWPf+HS3BYGpwX
zaQsDFKcgb9NtO/U6G3lf4H64hKg7wZMejANUgQPWJJhGPS/y+s33ipoaoMTcC/Yu6HI10rzGwYw
ccgHx3pegPAyluXd/x7hlvPHnX9TIfazJu4hrEXFJbqYr//HMMu7+L2kqNdkb2SfxdLuuzcicSa3
9ROq+Hwb9cc3OPNKZRohzthud1KlhWZJNC1FFielDxSDPXYv+8TDWAyLHR3Oc5ckU09XxAhCjrWi
tdWPcncd+OuU4dQvuJ/Taojt5JVQ2clv8TmE/PJxsnaCnRFOxGwhjXHaBImkYtozyyy4WI6N05sU
rpwbpu1S8Ky6CY04BtjmIb3H2mVSSr//G3EOq6VwWmeQrEuNpNEG+VdsFNzIsty/65JsGmr+s+oS
Z92vo7DWY8NilP3iJcaz0lg3AyJbR08pY/XMcXgiVBDF/1dsBlGP9WZAUzTEfq1uHzTWQXHb32ql
k0JQDbwA+8oAZkVztjxt6c1FZihD20nuQPcXLXXY0y5fztTtKu0Gk6dBUYcqPI0kOr6FtOk9e7Nr
wSYcu++NeWHq781rp+GU4K7MpAXmsakgFi7CxOpGKYxNQQegqQu7YefyhgZKogzySv2b+lvp8xJt
7SbQk/fYQg+/SRuQoB4JTZ7AFOuPjsTeuVAqUOhj0clfmzouAXIIE/arREuk5bdRC7zF7t19BopO
YMmMxLVkOsH6+7vFeVsB9Xx0tfrohdmqqqTR8ODLvoKHXSY1NqtXUqEnhiTg536KQrGhE59Dx7RM
YXWhSpL6er32FTSxfd44O/kK0KABWNEMa6pQCfoDhB+XboaEJHEKzBio3a0l6n6OOeMu/+HLXOsw
lt20rV8fDoNPI4oFFG0RW4SH/YF9mGJlBWHpT5Nr9fyOFrJhMQqeahdnAuzzN9gfSQGTBUDixK4q
ZlB3Eb25JEKYrnpXDeHIGCfFp7WY0GI7vZywLZr01l+1rU1GUkpZcgKH/MPugvBiyJh4TY8pPToT
ogx18F4wJi36VvmOCrAOkvknVKpknfHd8Q+rTvKaAE7Au6ktIF0+K6SxhN6sjNUbUunsR9adIBfs
QkfN6uf17Z/aIo1Eqi5aVhFcqgku7Pe4okpUb0AqvHh1FNZvNaaU2jjCCCwSgwJXzE1o8D0EY4Vy
jSMx7WFg/mheexHvn9uBfWL/Ct8bqu+qPiXOPd2q0GJ3Y2sHdACzmSgZo4XnVFzkyMuV4o8BsmCM
4vNbl9t2kw46J6BNWSs6iQo3m9tdyAsoDCk5z6cQ27I+UrzL/dL8blJyKLt+9vibgqhWPjtKHZ42
GRp9920VyJESe/5+/Wo5DYNsl8lLZblzx8hK6OYLTvkmuBHPDz9Zm+lXJgsQuBQNCgXVDZIsTYil
EWv63Fek2WmDBRHu0vySSHb7A37EZFhKKS5s4pLlG5QAJUk7jNdm+inJrRy8OMRJl1heFxIgNq4E
4z7L9/SB0wVLCqull0zQ6fCi03dML7VVLqR/BAzN8l1F+H6KHbyTXMxh3+0J0DlPF4rfSU1w5Pbs
ARPzCchEGxk0A91DD1zQAXmvhl3wm/LfzMP9ZYkctmBkvH62bJQd0/+qSj0zqcjilj1r8s0g4pRf
2pB9KIMlzSLH8xCMC1DBK4HB8WErBPgMwv4Ivcv9dykQR6P/qf4UThfNIXDWz/NU64oPcEL9rWBL
6HHdONXYOfHHyjP+6yVgCbXKpWOdWnlTIWTsrMJRmOCurkvmTsjW75d8O4td76sqx7UgEfkIlsZW
i9zaXJu8j9sWcBImA7GRbEFgh/TEx2BzRv0Uvo2TtA92v2+8go26v3r7msIn8wzv0qBOOmfMkXG7
5OWuaUwwTtT06NgQOl1w9b7jXcJq1mkNugp793g8D7TXZELaZwq/FLeiu4Go+qXNroIKEy09bjCO
IxfkjN85NlP1jbiKnuNpg/yyEzZVRFj6w9L11hrNMZpfeyXDJm5ICZ7YAzAZ8DU/X4M8xflXjj+8
WmVOemlTBiNv2WyQVfCsyG/vMok8kCD75XV7fOTO86TrpsDZOU1/3iZCJZvSTNfaABkwdmIRsuxP
j+CaV9bgCNSX7pypS/6rFG74IWQhKSg4qGDEqmk9l9lHAoy4jLRXIlIiY79nw/OmHpd/fosw+kNO
Tbekusmm70QBJk6djdE9OatpFHDO0BgRsuaZagQ9QcLCQbUkhW2k/mV+oh/HNoqZoXkedRkgABgB
fKdmmSx2VONDowsh9NgsSoSvM2rWMJAEaD28E89vKXIqNitC7hY8HfmVjJNkIUmgD/iOmlcZZ1hI
7Q/cqBvK6ZLuOCZXUx9zbBmKeOWuuC7KTqSIwDqIbUqqaSlQ4i3pHHeYnNyIKmVDwg00AXu/tgsP
m6iEzgaipoOk6irF3HK85I9R77+dZKx0U9gQz7ANX+XbBAXkGdSXop+PbSQ0Z+WrcwroQ0miSFoL
sX75Jgl0SsYXZxsJZK+OjaqVFBwK0kew1nxskbxRblNwOKWRAsLLcsbSIg6oaxA8aBQkj5lH4e0w
Y/IDImwT576kTxnBXexF5arVYJC98XJG/R4BKUi7x9X2ERiurjmKvOj7sJzspNLtOpOkocwr3WXw
j01SBlB14zv3wzKWaiCHhuqnH0z6LnXvTRMN7tOTk3m04gurRwumSM9jUb4EL3FMnsKqYsQ6Qf16
sCZcfWO3uS4KJV2iXbJlo2JdlymSPof71PnwWMHpxDsyYaaG3qAX+ePEytSAxdHdv2WjhPcYv5zS
SvRMMRjshDdVpeDqAo4dprZNq0+FOCFsfXWzYj4aVomtnG+kXI4r5fYDXiU66QaXWF65RIzhNjod
UbZv/ZpYctO7Psrdi25uRWYgu0CYvBx7ejZCrERaFk6GMmuLXGuc5eGXOD90apNUegWGJ/HlThBy
fPAsD9Gk/ZVxKAWXIYazg7e7OODdkwqxkKAWb0BdqbbatljUnMYDA9MYhxiutIOPqlSwaeXH7W57
ghC8qWVueJ4T3uV0l0DhVQ+2GYl4XlmFrMSl74q5Aj1yjN61X7X2zMEyztOwN0UxJit/iIJGnywS
kMbWhZRb+gqiCMGZ1oTFqd0Uq8P9pffO3vOVkhG1Go9jEvYvwswT4VsznP0BINMjhYBOxsdkvaAY
qXFPuXI07WnV7L1PZchRh2rJ7f0neWn3VNktrVw6ALpKHEvfaGSEGCrqpwB9/44rqK76bZHNaLYR
jVBk+X0BeXRCZRSViFNKRFmxYHYfMBYaiQaeqRKG/p7v++YRr3bjSh50BLLaXajxjMNCHSA2g09F
ytLHtA2xgYKjkOYVN/zbeMhVFPTHsTCAlBJ63EV7d7vIC/pQRcj8omFUAklOJPahthp8JeaqW6le
HEeOFVv2Z2l0vvdga/6yvV8JcsMhNhwSxpszgw5SfR7xowkgvApzq6r6hvoNSNpUhRT8SVz9tvyI
4cxQvkID6uTcO4rHvNMY5ofVldWsDtVB4/RG4ipX9DbOCg4YomdxzA2+s05O0yFWTdnuEB6BV6el
3UXxZRFxQXBiYcRLOCLBj+R5N/eqaWeUc9o1YDOgBajfXWbxLakvTvX5Q8jUZm0WnB0nKiHksHNK
bo13ka9TFZp4WkeJuo/fG2NIOLqZnu3gYX94euIJQWLb7fHfEV6idTdZaWRnw/X3XRFeRvFnmo6P
qUq8eCB4rFXMj6Wq2gabs/hYIDfrsSJwL3PBZf0C/VqmrG9al8QXmFmAppgTjE1Ro9J3tSR4c/sH
qRVJPABlCpDC49Mn7xMk1Is9Ff8L4IkDCFuwqRNu6sKOfn7I1NYe7kdJm3GcXq7BeS1uHL3K8j49
Nfeg699IJAOGqOfk2fOm3HYN34XbBbrc0UAhWcsMobS6mJvKV5RUqs6txkTj3ZjeEQN/iAB1w17K
KMepVavAMD4HjeLKYFjmpvullUTaVxnZ1DmHMyYDOOZiIBrEZ4slYTEortJ2sNbYuPibFZ3FlzY3
uq1dlwZyPx0F90oAz7ktJYkQiDgKlJriVuzneK2WH+B7KJMioETcytdoM9Zq2o1Cyn2p8mhbxxWv
TfdGO86qjoYTqtXqPDOlIWTcA1gA5bvJP+OYka5W7iO01uOlyaCSagnsxZNmXNihNGXZcUzWRQyU
YldwtsNkgTjeErpgc3N9q0ZntiEOVvk7Qsq/SKpH9ZUBJFVQJOSGIY/xifCudtDPUJ71hLULy1QM
wf8KKulpgpPbs0HTHNduC6eneXNhsewClKi3M9nXgSVBl0eixZ2XauFfY1wri/aSEln6y348iFum
lO3v4Q9UFoHlu6HsB/QHudVs0haSbwdicENwSsYlsZNJ3YXxEqjBA5JREduuJp6IRQ/F1qhJ4iaS
1DIrNEU0cKPsSbzNT6zYTmngGjwLm/8/OGTu2V58wBso3fCNr9gNO9Nff4cmmPh9oV+Rkqj0YTIU
/Lc3Sh2YdC624UGExTQ0Uc0JkOT89i2BnnSdxqN6DP1AVpp4AUWnN0zYsUDhdm45bGxeCcyqeFwK
SdoEHVWmewMYXIATZdL2Ef8uIEkrJSljdOs2PY5a02HALC1mg1BINwG2Dqsn5nTOTorNoPx4lVkE
gM/MW5xnf4HC86s/5icFFNa6npHUKJvo8iMdp1fYrfWDmfICTBaFIIY2UPHRuGa/8oHFW8zapJqe
do63GyWdRzwPVHCYfEAAshasSOxBUYstgx494YPCKjx8mJA2FTB1JfwdCaxiZuhdq9J22czKNWWr
QUQR6vQ+VTjJL3/5AREDCVv9/bZo3NpWaSf9cTPFi0fmykQ5A0B63eX+QTQ1FCBfrOBowF3Lrwbd
qzh4V9vkm3GrJsnhzCSwoJwU+7FHHqO0na6MRvAcCmSoWqY2aFtFrEDb7o9EHNh6ZNuOYR0/uN2J
TXHFQRAxjyMuMyrmrS6mUjnpY8ukNOZUdpcGpfmCsB1vmMY/5HQohb9alB91MgFoXpz6U7wkaNQq
0sDlmOMvfJGeSkJXkUr/YpN1wV1jzk31posaLRAm8zNWW3ITBgiwC7lRhtppmSfx/OgZYeW0pH9j
dP/3Y6LJWnIi8vhrgAGzmYTMeO4K6UERyu/hRT6kckVuNbs9jgBt0hfRytSoT86eYM15FjSg1TIU
Sfp2UTgci0pIOsSJOXfMlvdcVvt26Wp5CWcumuRZssbfDIpIpdN1BTbeiHs9Z2L9q4lTraDEbTMN
VglRpeE5/xBavv/LIs+WvEPJchEVlER/lpDBW6InZLlADCE9T9XFWVgD+efrg2d8xOKM2KPzhE7k
sfz1+w8GKRkpLln663tXLtv0dhosQBxBdM0qFe0qsvz3TbWSjrboEFgJtg85ApYt1it3LCAskOJb
81I/BFKCJiPCQS6zxI58zIUEbfgZXQzrbQ+gwpCLa63UjeAIgqwxwdjtNeLWRbjWt+ZgvwBhNiAU
yxEMDxv9HBWBGx1qc6y1BntQz3Kq3/J6pr0/0a6/dtjeSvwUlg4K/lxtsuorrAO0DG7ge6NMw0Vs
FRKheZojzbILCJA6zWNdRcYbVWitpGqykx3FiODCHayd8LgJ3UvtmkTXL9P3PkOPdSRXvVXyI6zf
y7PgYXKd9gJQ0dza/Bf/IRHT76oLBo81iDVnWUEIS4vDh1rtTZado+lmLCKdInOCrC5vRcSbfvus
Zzwn7eQT/+wdj4MoFmpfdglrjieZxAusXF2pgX1lBTlVGLdTVDLuNIkGwSALueKNl0UhMrINPYBz
uI5tylU4s/IGgr7kWanSSHyjoj4e6jl0B4b4Ilu4vlPJ8E9zX8V8Iaqphpyz756xr3pR9z4XJOcm
5XXo6h/0UkwvfEbQ8n3MoMpvpszTgumNmQVyqx7v7KA/GXce875ewHXoYzLRcYQopGVTfpUHCvL3
H0nU1O2HGA42nEz0a3dDnVg4CAeyWwjJ3ZFr3jhceftkQsrXeS9wa0LT3RnjAVsi3tv+mOrgvNOd
5zK12RwQ7/ifdrBeuz3o2yYznfyvEyppEIM3l4W7WdUiML3ljNPJDkNck2W7c8tKz1TR895H/gpj
t7XgyCfUi0YIBRoOJvUrwFE2eV0K41ZyehfSFkAjN5j/x+RzjSRC+zf0ndiHaUtgtaysg+DxT3WC
1kOFqKLxP+1FymSqrNEfplWuFlZb6mYsEVam0TSlJsWWsuR8ogNNcVyXADMd89RyyX+Zi05Z1+A8
v2Zk2lclu9m+RnaXOknh6AxhoTfGnqE5K5RxW8u03eQ94R2+no92aOWMY5kopq4wAaqgweyVTIzi
e6YpbEjCXtHsJHI6h2w8h9TFD76dfF+iiGZrlmuX8GfDSpgNcMJwILKjUfxXEO8ioZWkdvPHO9aw
oQ8ZEHtl6+pQZquHJaXV9eWL5Rjx4SdIBI22d6IDmkrWyFrlmmE/k6HKRzvn8PZJVLsvKvzGCFYt
HNmkmBJmPHDf0qBKGkDSUMdHJwtrp4+Oo3UvslbzibW8QHN8KPZRCTp5CpAc6BR8b5sBBqgwKsH2
tk8/T22c4p5vsrn9dTLoV11kjdjItGs659S/EdiHSVfoAJu7gpPLl0zFxAFofunOnIMHhhZ5nyue
pwCH32gIz9PrGOdyuSEMVm90qtgl1GDNduePmel1PlzqQlfKerXgZvpICY6sdQXPkFo6Wa5/6fn0
imM0rhG4CbpJVnOyw5ktQ3DGSkPeHDvd/TJj+ADdvAiaeVtlxmd5vhBpIxVCTsh84Y5y5kQQwh+t
JejDGCnAm452OiE4yNCS4x1BqKp/p/Jp5RzXxjb1bV+FOHv5nb25P2NG+sKmsgJM+PChid96aoaa
9PSje8BO77/VhkVnZP1zIWE6y3RD68GnWeGQsF0027s/y2Wpg/q/1uu8oeIU2vPc3uKrXDr0+Wxe
0gMwjfyd52GZlNVKNE/Dr9ftLM9sevb86Cic0cAXV9gf4BJwXdL7FqKJJhQamL8gY2De1vssGytz
ExG/nuIECABDW1DOIvEverI1H4VV4/5B2LhTmrbIrKhFYj0feUfUxkR7wmCSlupPckl1ZWC4JaxC
kvUQunSIRYpe9pGaW/yWekd5lLClh77eeKmhz1qeH8r2uP2ODcPWvgwAOUQfxgNLfY04Ko6owPPe
BN0iDwIr9klY3bCm05qIX2YSMfBPc1wvTxsh0RZDUrtF6+jHS42q0alyy68pk+Ek7emyBwZ0JVvY
lTbV6T7F0/AcWkFzkYwqmIXldctuq7Rc3Z4zFEQ4kamSyqhCIfU4uN+CCcAzmMa+gudzWPUiZBX2
PkyWO2OYOYkMydhiv0BEpHc8BBtXIzdm+7eRPMWbQzBUtm2aIh5BqnybgoY2KOrrqgYtH0IJFD11
pGgHEVr9vIfpJDguPkfbX5MO6/RS9XnTUsYTxfcD/uzLOKaUk+m3RGDvy+2A3s+Mnzy8T96Ru1Go
uieM18+jNiFfqBtfjmPEH7jYqNB6rPuS0pJPa16SBTuN8HM1vD2omrBCKLsTMdSc9j19LOPSl0+C
8gs7uajkznULEvsCzyPWgxt4im66JuJerbw1AHNAFSDyGLSGYDKku3NbpuY0LAKq/7dqTWd3eSOW
prw3QmUylZundrRnv3X3b0Vx2lckU2vWz8TFlobX5ITLscobcqgRSOoqAqJTGg73bfceRdbwFFWl
NTp96oDHmUZbFxa54NVpMoeYYqD05zg/aqXlfr0S/G9jUDm2fqqYKJ1vvzTqtMrPJ19/hVRJ9839
Pwn1PFLoJnMkxcs0pqD0hjP43yzuUzUkr7ajBWXKaHtt9Dqr/RRblVDHJ/wxZ3yMwRfS0gSZJCvk
78VcwQg+6pVtK7KItdzpnJDglW27gbFCFNqqIahVeJfCSZ9caIefBQBQSchFK0nShXlVU106DRc5
LyIs7ZQsbK5M0iPF2LSep3gOrNCL/3OyywpqdazgNedrVjz6ZqYK5VnA6T2noIlYUrGWVKGXFwCq
nDcl8KoIgAwaCVU7zmaWVo0RcANu8+2IqKbGrC2iCRa+7BETiUqt0c2MILxZO0JneZD5v0bkh01M
y41DVlR3cIq+xrkbbeoyxkhDGDVqjkCumGM++eD/f+XQrXtp5Qkq1nNm4lUDk35LhkcGI1DHfv+n
IalBzqgvyx8SnofHrfG9e+w1Y6SEwLAyZY4AIadNYP7YaP1yW3W+UyXpS+a+BwZWaIZ5it1LhuxM
gmYYIUxbZSHreXyvlcAyshBHHkZJsIt9xRoEGWeyGqAiKMJ5zuZ2DaxLUWY8HzWG3kYcscZX3GB2
dbkRcMxWvb1xHSUiXwtu5gJ70KrtnKhTQPPt1Ei4C3lO/CYS2SLE+wSSPCXf++wYQnWW27nKioeY
pX4l7JnttssaOf0ZT9tPun+51sTRSe19X+bEODxl2fK7Q+snV3CVEtwaVAQYmKpo3c9qwtWkmGJ4
mW79xhkYGUew+qWHyTuUtyjmMZ6iirWVmbmOe3gViGlmyzSKftGn8cL5V+OHiwKcBq3O2XN+ApWe
co0xh70DJdg1lO1FHKAUx7N+dEY3IymboyoTrLsbGLvQyKPdfLWP87caR9rQkVEGojyg+fzcgWn4
Uvi2fhX1mNhffdXwzHdvYrZbsjTbKBIj3QtQxo73stCYZKJ/JUv+LpvzvFaM+UbAJ97upzrHkp7U
3a2fRzhQAZ/m3tACdjXYjPYgRo4HjxWzLZnjna8C0b6kCT40oowjzzlWcBjKWDL7ubcrvkT47i8p
x3rj+3kTQFGXb1eY4W8NuKwF51X/ueZ3Y/mgnb1AqOm5oaGwc43GcQNy+Dyw6dRDAGxKD5Nl58Jt
6+dFg8Dk/L1K22wdfOXss7V+zNPEKons9lQhMqXsidr/zOiH9Ayi2Tu34rMI4d1/AiTBOCdec2AZ
dhBoPAO+cNyIvUoi8JzDsEHM56A75mZuDv/XSxCIHq56i8BaJ93/LTSrqe2x/5/xIWAMz3BGt5u9
+ruLCji6UOSBCT8NJIO6zz7dyV/rFEbwQHvsSt5+eRZqCxHJqhjj+LdkxdQe08wPJkvG+C61Vwd0
lrp72+tHETsoUzHiVO4MIvSPpK78XEzm/CVuoqWGR7oJlHFs/JsUdsdbVxnJgFluLqmolSft3rPX
knqKeHD3PSY2/UddPOiEnoI4CMu6F4r7hR7loZJoMjDXFRl2eJzLLDxdacMqx6AC6BaakDLH7n8v
DB8tnZ/yhgFcXuile3oXlsVCOckdWS/TSoSK8XB0SucKU/wtO5AidWlGtJk6bud9GPNKRqZULUgy
hSbGUv3Xu7ZiGOn+HNuTSXj0VtvBC2UY1FDl2XIhMsoO7MB/0u6lt3sqLDKTp3FnT3vOze/PiPLD
eFxmf7uKgQ0Kv6TUoNixH+LtdmTEIUZr1/QqtT2NkO8CCu032Z6X5jdRhybfs4fJLNPj+ABGgclA
zNTBMrQsQUYnBDag8R3UC8xaqNCWMqAaphrlQ4BP/1UbDQGESf5dvu6lodHUShBWayBzDqrvMnwU
VfeSgczkBGZnr3T6IDhJcaWyAT7zUNS9BWGARYii3A4f91ryS/nvmJX8IyYAbQExh+2F4tKXDZq7
ZmVUbfrKj0GGM31kxQr/PWXUtIKtPj1CdzlpjhmGfJzNyzERXkgLogsDxOsMjsjYzBYm1GCkMAAq
9K+LpXb7OGJ1QDcYdM/yCJv1I8isX1aV+8ak1Oi1N2vKV9c+W3/y6u7mszFUiYzCzNhJEBtHMajL
RUIGxalB5r4a/96W7Mku8Hg/sakwH+7XaWTjNUbdUCfFI1jT0aw+/zm0nTDStls+okCBYfIS6TUJ
Qb74y1w9Mw9430umWU8PGFRT6f0FbVrq7QTA/x1kFxpOZqZEkwc+RKun7P5+X9c5BYSyOb6Dk6rA
mTUlJYQgPKmJldhN6LZJRRqC/4kM+OoL30jJYHmD/xNatH2/uL9qoOfZDPDuWQNKstkKIRT/fN83
+pYJmb9IQuARnDyJmJRko03355B8EBw4WgW0dXDb/gGJkXEeqOWtAM4AwreuIAxVvos8DyoAl0Rf
uu6w5DQbMTD2rg8vHKifdQq6S2A1PQtjBJx+BLSahykbmxs9esR8n2NTp33q/TrD3mmV4NR6sivm
wFU+JgMuSwPP8elAjRAzTbZ8eUOa9AvPPQ8fhMej0XRh1gv87BKPRWGCYlTkWz+7CzivQzlUbWcN
OEbDzD/bG0+ZHd2Z9BInRqcbQSAF3T27pX53VoNByYRVTevupGIcQnTIZnvydy2MITMZ4LStvHUQ
eNiJkw0uLSmDkmpb/zPRgggEQCi5ZGhUxmrEpKFEjxEOQJUd60Q1uARiWBxUjp5j30F8a6C4YBW5
S/3wkWhxDZgMQqK3e/sbecHy/a465XyDO9A/GlRd19I5uR2lqfV6zDcAzQyhX2ngr9j3Gn7lq8FL
c1FqbkbKFTpsW1c6aACbkC0i3xs/RHUrz/bWoi+a36jHz9bj65f31HODks4kqKgVLsz2IbZtdHOM
f7QaBFxDf8B/ZAQ5x8CFyjli8QGCGnrnGw7u/KFSnZeQCqVmahHan3e5PiRSPb+oo92wHftj2Xb6
rEDHsvNPMs5QtkNoOOchi0orn9RAAlmXhH1dzhv5MZelvhWL1hN+80Db2NfMgy3GxPFvOwVPLHt1
viDM+PGTL48RyRK28V5+Fkd7DGBHBnP/8kL/4F78GTpKHmVk3pcjyEKbYcITryqavV4D9cxuWirN
7Iv/CkSCFYzLx5g2X2+FCzLb5h21cYjYUaWh9dQ5L6+wCaOAcrMS9H6Nmi9nP8lqlZXXuw4RsIq5
LeQu28ckQVeofoYeaKfgE8UuHR0OVHcvUb6NsV52F1oYWL6gUmrfaBjUHjIonbq+rKhxMT7ujOY6
xpZ4GuB0JJd8NeOUfluT4t+OwoAymTxtGrAYIrR/38a64qOn3s5+Sed6MdtjIUlJECOxJRf5GF3i
47SzY7ct6S0KGi4KPV/ljI40JBpT/qsqq11ZdCsvq/yG1OzVCaxnZHMUgUQ0RBWgsYwNowo1sVzL
n+pvIsilVsb6aOd5q5mIM8iNUwBLu/jYD3n+C9j2nuphJzbHzSXi4iW2cfPbSHYdflM5NnBKn5cX
sKZQAkV4IURm8KlH3FYdb4xeomD63c9cXkt4nXJiiG8JCS+6UbyJQg4Xw2Ro6wWyiyyYbuf8xR8J
3mbtZ2i6sGVMrNNW0LdZZ3nuW8qSGQPWOMoLPAMsUeOIqpYLjVODtM6Ex41UpNCKuAIKQpdNM94q
5g+MmVW6IwfPc/o+C/u/ClmC70IZa1WGOT7dQldExMBPMSClanEgz6Ka5gzmhkWC4wlvHqdIdAgQ
a6fUlafmt+PueQLVrKpsPZc9kdQc9qaWMIzmfB0wKlafKWqebVi5aPNW19SAX7n5J7WfN6+NyPSx
bvkzyPbIvGD/DudC15mxwgUcUZeqPsXgh5lq+LLzgQFG0XfhOWbEbjO7YerJmTLBJXXtR3C9kbJN
trsbSz8ds/J4lg2/+kuir++ls+SdwtWskY/aiz3rdXFlz7dgxWFGlUinTPPdyYX1qnzl1XTRuXpc
JhctCxAwFexcZPz6c93BKpvsFLrs/eF739w0YEl4pCYnw3KIYl/d/JlS4Z6nYaLE2mYMqvpET5Lh
wfkdmWWwTyyLFXAAPq0Dm516Z2mY1YRSewGlWCfJMoQqwByMo7werrmUJfl3GMOVyVsC2J7FD+9Z
ZhweeBo6FP2Hd/od1DgatasiXZWk1dNbYzpAtPMlKFOvUYJPXMK6iABC0J5AZairSHAyz/0rNW13
mEOFmZjD+jwI2upnq3OOsOhdCdJh1P6Gt93IknDdAgsZmL9AGH+D+LZXrlSxzhufi9zwt8Og7GgX
1yAZAVtzXfCYsAnh93aVxCBz3sOfpJ/0jVhWb1B8sK01nsvQBgPQRBBM3YhGs2bG4RhWZOUUJYSp
X0yMwZxOG2oKvZFkjiWE9h9XKjty3Lq9v7SbCyKHH/ojGydzZ2H84q02yQNQyjX+3AghQdD5IHSr
qzJZxap/ZxjoQHhmcY5lLxA2GTeLmXVHTmnBYi52W6BYga3LhSrKb+U1HntmTIhYUTmZtTKNpX9r
e0gTCxDMTiDRlsVwpIFNn47myZwLYc6d0osog48ZXuSx25sl4MCKKOf9BLf77/nPIsProLPvs736
sEyvP6lW2jvvixjz6juA+hFfK0wjSY/2g1MLIsaBeF3T/zGuc2MrHQSW55ZdtdvJhs3QN8Nvi2yn
eq8vfH0KKcDDK/wp0pk5dHAzpVJ0+pW6TieLM1z0OCNdqWD6DRLJ/pWh4tWMF8Kwp7ipBt3xN8x+
TdtTNxD9eOMGfWq/XG8cG5BrpKA7bW2Lbi+fV5JXIhlV5vzFkDXm38AfKEpIsbcbeRSWK7I6+Pqp
jls5l/KmH44uujs9Xfqd31JMPSKnrUjZU6xJGdJ08yoJSrxn/qWNd2gQSW23pWSBQvji0SIQ8QXu
CibE1mXNnbGLFapAQYJmVLUu081G5E6Bof8X5SOZ6LEzyVCE65tVRQxTfBMs4u+K4ahUQ0I2g8VC
AJbyVaEXxI5817iTOEZdMvzOqCEarFs8/jXtN68wAF2DI+Kc581eDV40K2ex1tuVS95NfCq6SX7k
r2Ng80vB+OcXiLPK4RlKSOW8ezuJV2VmdZq+TKrcHKvsaDwa3NnhnkpwcpyangKOZI0bmS2w3o/F
pKr0yAjyZe/B7tKyTi9EmpejDp43dWRmjr8QtwTiXW89n1+7LHXYVrQKBOfRryvZzFKR9lYQ2x9R
eal++bgqckDyJjsAeOLLS8RXgIBl0c9qscCBNFZW2WwA0mx0QdiGcq0/kkKNA4GQPD9d1sX+b50w
y5Ewr8ohCz26c8fpgaTUDjCYvHXAzJomWtMso829+036Vbni/GQmPGDTljeWKiWHiB+cibH/xMGw
U7pt9w3AfZxUjXybA+uhiXAIMEvrnbbmFOjB4olpooP9EfyFd3rkFPx2bu86J9Il5KE4W9BDn67W
8FWnPy7+ogc60Yvk0Uw5clEgc6pzGgLtSqQAjLgfxjWLK6+S0JeaMWcAHU4vMrjyG+uZRBEfjaTg
ibLegwDSFAZdvcFOWa7d+Q1NDdFFl727gnSk7Lyv6UEcz+5BqXp+wtKAEd+RLymZVUknK14RfAo2
kzQKIlK6p55ptmlt+eFvv5bLPXm5sUYjZEkr6uIrI3Q1ZM4+I37jP6zUQQvf7Exxt9/Ifs/DcrWh
quAqFm5fTUafT0a3VutlwUSxXKvI8Cq3/7/OIrRL4W8ckk36cAuA8doZi5nrjJvo/qjMiuNjrx8x
Z46WvA8rOFm2NBVIaYja5Te7PyqOpRVogfgM54eUm8OXrGF25if0loMX8g1RPceb69Ny+blBXfFZ
5cTY9EmnXAtdUuvL4yuyuOzlMr59gvUwEC15M59tKQQ7r3NnBxdiWPe3IWB0Ib52XT0HCugKHPoQ
u3eX+fwmHVH889kx5Ywl2DK7/p7Gg1Ay+HVt8Jmz/BZBBS2usGDuJEFp02vzU93Tz0LEaNPoGfXq
qUHqSg3SjEVEJpEjbmnidCXpJKsmYp7ihvlX1GF7qWZ1rDkkbV2mcJGk74boMQ3HtF1ylanZ+2qy
mBT7whqNJII0X8nIzyQncf/O5SGMJ0MCrB+KOIloRb2HVWG0YBzaQpEI7uFBEt1DidO0ui0+YUsn
/E0mWGnzvCAg/OfdKeTKSWIK6QYSSAWohK68WunN5D5RP3dc8PxH1rmcf0SwT4NP67Oj+oLGhLDO
5rKAWyatFLZpRkNPSnh4UefqN4TZ0cv+F9SKH1o3827cLXnb99EAUrx0ym8FXOiMLhjirJVKs5Y1
4j35ZGjEHiPPUGOZ+p0oZdCy+gZc5QYS/MO/HqQnBRAqAMdPAXTB1yBU91HRvu/zwkRxweBcMQ1P
E/+IHZB4oFg9qrW6Vj+QfG1Ur2aGe4B1dA021ENqsOCA+mW/cV19/3+qMNz8kP0Ynz+eZ7lMoZ7h
UNRRwcMca8hhCbc13cXctb8xQ4DyXcrDpjCXyxjz6wvdB6bfuC4WLYD4OoZP3bbulEfO/mqaAsi0
OwAK5wHh/q5r6yfbjLWPelJDxOuen7wzM2xAdbAKorrfp5o64Ob0KBcgAsW8EeoO9vJ3tDOnrBf4
efv1+PLpqRY7EVzxFgPUvVQxqD5w2b5+CRjP07wldV7Ts96ecv3m9WHC/RQzVg1QdVU22uZmzWvm
rq+AzChdXKW0vxQ0tpZ0NNqUQ4fiU0UCRRDPuEuW6+v/He5ZW/T3k9httJqVxSRJKv1n565d4lyI
m+DmGvJyHYSx8DgjrANiMuPtAAJ2Ld9OmkDwIiVYW0TCM0kLUfO9PhBa0DHSAGPaOL8eelK9niwB
gIf6g3SCcJplQkpdXeJZkJq8YdkX0I08XMe/3+C/tCz44VZKrmEtSpwGPQO6VmDn6kEuqItTjjTl
hGMdvx3o9U8b/sFSaERMRJSKyF8BcTQqpW87YCPdAvOw8k/kqBWJhTLpzbh+2WlW/Rh/md/N1P+M
ZUpbri4T0/ww4GhS8TzahBmB//Q3p3nkjmyej3Z7tIgxyoVCk0Gcn4IpnbXayXqK8NPFatUO8TPZ
LWvPy9idx5++Mjar2t03rM787uK8ukWE1Octn8eRGxdrIT75dWWcJidBd/+i3cTTI8EWYhGDtRA4
xOa93LYLA4I/biNgJiEU8ufoyCfAivXYeNFWMGOja/1cIW9j0S2V4r+TYWia+i+QoX3Iqqe4AtZC
UZie2XQICYpaD0t3npcxDQlQ+uCzFHPiACXopjvXio96uth+7oYz5CGZyf6yWvIExbqQtWneTlsl
8SxslGBPM+VkmfMHiOV9tpMwdB+BEuKqhK3GpbP40nKSksE2BoWpASck6qunLn+IDb/biRLlHY/a
BPpiZ/bFPSLDSiXv/11ukiani6q/aQaHiDMVXOfEXSFVOh1LZl3Db7J2KakexHUwzfQuCbFR5XUz
vQPxizEuOw64YvokCE5bsoJMnbCreV3zh0PxPbuFGJkF9oObXdvDak+HD9ZccUySVi/9gen/NOB2
GvVkR+4ksN1i3ZDVlgvd0GBXImPwXAwaZsy6IRmLFpmdskezMo8v3pVnnkfX6B9EFERwIeIrnVPv
X1OUPyFtMgZbRNmZjoyMbFsnXK+0fktqI3JaSqTZGsnO/kE8MxzCNA1I0kTTS35Se5Doz10Z9vRr
YfXvnVZlTzE1kJ8QLDXAav6YoW7kv1hkytdNJ8kvsHg7bn/79GEzhcYhfp4qeRQk316u2B5PJq7s
a1FAklFF/grv4NMHF84yyW6IsLeDCH2Dd9U1HWwR04r2r9xnoo1DfxaLB5PErFfdXG+UiBCdtBjb
yV90/mltahPXBAsEA8T4NEsuBx5zAVr654gD3MhIslcUSn6AZkJ7imU5PaSKPWKZTXPwqtjbsPXf
pyGIxqGOK5xfi9L9JlZ1iMLnM3EbYUlNk3JVjdbaUVbEKxpGhx25X5gGW6K4ST7O0gCXgg8GwKcX
VxP0eJ7iLNUv/0SpS2toW/0fZJIjtWUpcY4wd46jvKp8m1A/lipZHLjfS1+R3f3KgpmcGvHAf4JX
Kqk8J87hjx2oQ8xztxjQoc30sdkJ7s5ttW19XY8RoujWDLFXJ0hnfqnl7WfVmVPlOVKaQCOv0Z0z
0P1ENdnn95OjsxH+e0dZyP4nSXF8Uj7++mh/KusoO9DqMDQIStb8Dv3iqEy0yOfSN2bEi9zfNu70
n+FFNaCkDLS7IEMCPAq3W0ZG04+GZGn6Nl+JNrQs7fFpQDCrnwPx542JeSbJyrvJi8NoNS/KCCTf
u6xyBqAnUGWv8OKUQvx3x3OG14cFVLvjMREyc36PzbEZHpssVq9N7a2vPn6wmBkMOO6J5FYbHoG9
kGajwFuNFsMLaolQWXLDDLuthPMJY6Op3Nh9f/lFRjC/4oqbXwEx2Z8hycnqckyKpXnfJnav3Tza
PRY9egwKdBC8XbyGBf5aX14z+WOBN21tiOfsQrEjx1mTTTKvWLou8ONC70Ciufb/kR0mVjShxKTn
mOTwJncAl18sQr2C3GGlNdPtvbUuPJKqqbVNUmUBryZ37M37pyJuzMHgcI82kaq1fXe07egaFeg3
PNxfyp9wsw9xzsCsBKGipEYnpFzKCSTJYZtjABn0VpznQmLlEYoDVPDgd4IOytSBnvfnTTi1yptK
H9vgppz8ekEE94ByHBoq8nMOTitVtg2+77oZqypOCwup64aGcOVQuR1WxVwrt1lpgxy0PnzBEO1r
NjKZGw0wTVC+JtyWulzzVgoGxBFdVOj4fzwlCAKEaok3sG4WLZrcRzn756YBIWNbwiPehMoFb4wH
wXxstGrbUTRjClOa3+GGj22AVgJotVp9vmzDEgV4UwXJidIFg4jiKMdw4s9rA20DKrDnlbNJeF1b
TqmlypOpgs9dN5XoeCYDwzJ30mbmCeaAeO0BiUrwG6tYtCh0YZzY3MrHgXLVPzfHsEGgVlh14o2i
ghT1Tl8XnoZAgmG7MxV1ybW/7CEXCa+OfmJxJLsK3acNFrY1Cvv2fvcEIfIUWrRZKDKPWBXfXysF
jn2NqA9ZmZGJLV5oygh83jFpEHDXp4iRlw7SigKGbu3MxBVxuW1MFF/B37zzr4oVgt2mwe9bXPsX
4q4J9bMO81Rqes9F+AOtqhhvxnY0MQUKFYS1kNAz9XxvdY3G8ehmlsbrmHQEJqnGiHodoAJI9QLr
qh7UJKdHkb8LqopvNzmJJh8PzEAPhhYQG8jwnW3PxXnb8IIQMeBxm2Ty8C05JyI/mdtvwXATsCjO
hVSqF5ab2euYtm9OYNRBb38hIUvEHA1wRAu07czAK3BLQbS2oUwYJSkSgZlDi/rLzapoe8UyFiCm
Amx3tgl0VlvOeY3mdYdICzuo42LRl4IYFrpaJnLoQlwFEkE7Z0PP/r7tV3y0+zQIzpd7BrX7Qr2E
wgT3fROOZ24Q/LiGsnVQ3KmNt0+tGZtsLaO6dZx2nI8GTkYiLO0L2XAig2aZ5VHha3TWXNhTLyny
Grt9tKf9A2VQDqOfg35iHvMjZ6/iIuuXmgsnRwEtkG7+F0cDeZ+m+d/ZikFd/wozcP/Cl8DCT8GS
UZHd/Pkla7qv1y63ZfHw11jKSFbzFeUrsIFv3GjZywMleYWGoNo/72S2lH1KhajJMpcH705zvWzY
UsmNnm7ApFQfp0J+rY5K2SdG3ZEeUDOb+PmMhRyJhRUOTvW6l3SLrYt8AzKns8HKaY9VM+l4KZ3A
3GC75xrQFjLGAW2cY3aK7+vSYUVNOmfp+trHMVVMY7jA+nvU3frquWy6B7dTR3FzgUH5JFqhYKMV
iI68cFcGg21wmrrkEi/OJUp5j4zD+A5DN683Qb7vtUmYumlozSEd34pq6x+TTTnoHa8e7LmIkAJE
TR+naYKKNWtjIGDTVcjBznQpo7AN87v+mH2MBHKJfcHKHUcWsLZ2rCabqmwe3dRbL1OEQ67xzPKI
Wpl2H1ZuQbie/2fxwKA7nnJ33fKahFO5xW6IsJdcfJJ9Qfx+sI5B7mEUjB4KoPimhX7CyoWaZN+Q
esqitBIJik6PKByjNYnkEmRv1h9tTpECPcWbVxoTaVG+o79NdB+WQNmf9dAc0pkYoBWYbb4xsk+4
XjJdFspF7ag0NbTXDKST/itc6MN4J0LLii/bZPvTtduDTpWlEd6YqvDhmIeCtloeIcvQVjXPHZyq
Ke7z8GMUNSkvorQXWUYDAqil6GJeIRsZIdH5FnVw6pokxUckvfch1QPEDhic7G12E/3HoXZCTH7p
rgSj8Rb+9oWdKUv733j3VbnYsX9xkc2SYoZThp3coOQg1Xc/3PdhzaUCG5xnjMUuDQvNDej+5/S9
3S7UdcN0y7GZQ5GVNW8s02H0KW2CS8r3UTiL7c01OLHCXytKcLQryG3yM8bR2s3vvDmwm3KQCDOx
q44LHNPaXg/nQkx1qjcb9dg3STqBDWoAg6ArHvPkZrg6fe3xzBUx/JdmETrfEmr2d9G5QCKVwfrd
RW9ng8/d5BW7TxIWlrV62q8Hwxf2HleL0/9fKFsUjw6lZOA4d24Px27H5gcPfgy5MjAZcgJTbdyn
CBFeO7et1+5poDcolw8A3Cd+9P14dEr8gxI5dFVY4Zmx69YH/uVRsWLEfYYlH3bNb1RD1EFGXG1y
jtZjl3Ss7E6tTLqAs/gUEMbzQ5opa3bP9hh/cag+rL0NzQHZf/S19HspvR/ELREzWx6/quVKRzsj
SXufhSDgY8V572XbFZKRRV56YyJgVwx2qL8tsvJtVQkmCWK6OjaI9Ox+K6efQOTqj77c/9Yj+et1
J1DVFgBg+lkCOw/tHxuFlIs/iZBTjiSStsgfyjdT/W4nLlXiv1tJlxlulOVpk82+65k1gPZiJN79
iy7iD6Km+YDEb6gTBEBg/JiJ9m/zfYyPJxoXmH/DhjQcXnSB8apC2IwEQto7VIvryd+gOE3ZlYtn
pFGNfaEuZsnA7Pft4eplVemWmkSbKXW1A+qtKeBx69oD4jzPzTkPh4dr1Ogm4Mf5XJU2lU8X0Ivf
gB6DujTrts6NT81u2FD3SFiOaVM5X+fION+us6owDZF3rFyjBmDj/jISM9ocvk93e3xPsZijhf/V
8LdapzDxivkFDGTyLsUkC/c/dOddz0gu5r8yiuVd30WMcC3Pc+QpBdYsKYvbuD7sbvBR9Hg4US1O
CwJabgk06hGMXS/tnzXgyNapeuRDGRCqJ9NuaeJGJ42FeM7yHP5X0u68X8k0NEq0yFzCA5L3zhu5
iAwrnp2awOLwU8405Bejbj25DLJb/cEqDQa3XMF02iMZ0nEgg1TrRKz2FDNOAxM/Czevlsl7ieAu
9N0C41mM4c6icUhKB8XJukVa5dxlCFKHZXpotpTlUeeBGAI9FZgW9gOY/ESDivVuwE2QGQBoFh9D
TVGuj/qXMdoixBGoIB1UJey6HkoMo0oZdtNKfpDNlG43Lr3HSdTIADGf4whLXO2cCAD6npBguv4n
0II9WQ7WEB8okFEWvuI+s5QqqmKuFifcz7lq1rTPLjIWK541EIcfQONeG/r538cp1B4KnQsBTtwc
SZ+4OY1z7jPb32ZQQihrxJAvUfoHVXg0nmRMY6d6nGfxk0RPOQySNZGUP9/YnfBewJ67TRbuqyzP
OrrZpEBsprda6QuTWVNc1yjOINUno/uHxIRNJhCPwEyPwjtDwdsyhFLpcR4WVJVhTS279vftXqzq
zpBXzDE+qQdx8PEsTF9GmXuNG/Hk/866IT4xOZtzwFj68WwTV+hhQZQ8qlLk2zwMo4eLwv1r9FLI
35eDXtzlpDqT/H7yirNbpPoz0M9xhu8UELXeGz2uJ7vY3zNms4fttGggvyfcmWLs+tEtsHf9F0LA
0qijY9XXaiDAfTHUhK/TYFztf/Zxkwk2I7QWXQ+0sY1KSrYfZmNLOgipSOWQmfUPhOJx8NaMMvq7
8D6l3rZVzkvEl6QXsJfyddo80a+bF8HnHnxVPJ+Y11hJTfrxysiUSGOq/cJYM20nfQhP6KnAQDuL
vZJrUZmdu6S/nuKdntx4V+86JOjiBJCB1OyTyh2h4y7ztgyXKLPw/59aEjBz+vpilODmF6RWQqIR
XtunT3KN7E5CAYXSfoGq6anZHmICw4gNMMAo74Q6S1MSvUck2D8wYt9+A7AIZ3uuED7qfDffnFVe
2N4Z/uRunqGtJabyILb3dgs7y6dEBrSDPSM1bMdamMgHHTn8FmWuCMoOFETwTFUMCpR9DcrHTkto
leV4im5ncVTWZMXCUO23GfBX3KL5aLpIk+UWWGJ/Fo7sFBynwPy5VHewUysGpABJWyd1ms50lndF
TN10R2tEL57ShbLltWbRBEUBWwLMYeHbKzIPF2Kd+OYNGD3PNV2v6F1x8DpSyumLxTiyMtjiugAu
D9+rNnIgDNDlw8nsUle11wFybHwcv4KJvTXmxJn+Kxa/e/f21PQkYf6WIN88q4TXHKiD49bcCjjr
1qFpDVbRebra47xiREgIZe+p/9R/G11WmMILwlxRXX9ZmaHWl6k1G1gYfmvxB5YouUEFozI5bGpP
SDI8XMRGtVpx4xq1YvnRDDrp0oR1wLfLTGzE3Nnkk7EzGJUTjCiFkwr0B30F35+mkk7Q3/mU3BS/
owuASDfDvN6KX9Ui1AgbofvXRCQzVpGpi4XcXSd8CqvAkCdH4x6cq4i4HChf/a2Lf6VcmU8/v8Pk
m4K3q7bTzgXcLH/gFQG8YcpYDMIwl1BK3J0z//M+dZA5hkRnBaAablLT2iudFGeBffLioc5NPQ+R
dvbehr+lvX+7Z9gtQZrHz9phMweW1MDCQQ9NAmStINwBeaa1lLNYOdN7P+b1Pw1QiMxxyAAzNZI/
VJXG7ScSSjHIScUOPLZ6lXAomeoZpl1EBwiKlyN34RBRBpolJhx/0KGKHibmYByT5bLWV9miei+v
XhFtSs0ngOqylQ3eFd4o0z8CcfEhgttAWFB+jkumMZTsrt+ez/SjZcPVox0/ngXftlWR9XGtdWw2
dJj6LpP8PoCBJ9U1eJGv41SK/mDQAV4gNaMt8jdI249Ht2bdmKi8lWmYoE/Xdj+8S7Wq+RcDnSQ6
nzbdDc85wle7WzxP4JBUW8OOF3WIv8zs20QyIylzZLnKoNipoOzKyFEg9ouBJTpr+0AruwYISxBl
OeV90tj0z+cUvH1e6k9qBhHjTGgW8xj+KMIAwEtjLtgepfqnh24188fdwtA5uPSmRrbX2I9Xf9eB
LZ/xvE8No/jthB0zVk4oObLlzFxFThN3PCNrCTzD/5bii/MUsvC5l5RTF2oqtsZ04Qz9qvAaRfxM
ko8BGRKV7FknRQJ4f52hWkxYD7R+z+LYWB1vDbFalUtgGbIpxDx2xvjtOyuSQBpaZpgObXWyjwx8
IGb6U24vLqwL15beMzzbpO6qer7bY+n9nn7QvDnxhQvEq653cdIwGZFh1RgQf4+0hLY1BlwDTgVq
VgrF5mJps1uAz2ruCHHe9vtAtm3EFztj+fv5T/NpG6S42LMjkosQ/Zba/QNUE07WIT1iOOUfQ0q0
MTsQuHWrgwq5WrUA/B8f3sAEgSgPDxYPfSXYfyyrHaS/Ion2D+NG9TJNhB8VvHw7oLlrDxpkmr4T
CBieQDIOr5f4zpkkPgt4fIcM3VnCz7f3ejcidOOkXrW3zop/xHLZeND/vRk638udlibhZ0D4Rg0E
81GkEa/X03kcgTJEQtsM9fqslZyrqMEB8yGeKhMGg/dnwxWPs0a4tKMArG98RCTQYheIKJ27e/FR
YbGnKAzNAkfESfzgBvaPq4nckfjQRrYkGZAc/N+PFaOz5Dzp6i81UpMrienfl/QsuR66go/sioQ0
5xKnFVzYwcu5K2PE7L0ylff29QwHQ7FbioLMcYLm2wXc3zT51NNus02PkVQdYHbtVyaL6sP8R6Bx
smKYV9yIFmToBy32vJEkarDKvjbKizaX6ojIZadaCuNGPMi7UbbshjBIIIKo38Ry9rO3hNLxNatF
MZPQTbehLzyWhH0/WMfSyxmT65fDuVDnp/1Uv2nTTmKKwO5HrxD2egNwP8CPX/eN3CGPlYeh6upg
83+CqpzCKg+Os71J4nkXONcxYC0rP116xzOj23qUj9tBnpwPJ8SYiXaKMaBWi46ZUS3O7+JdHP72
iLRQQmPj0I90tdRvPzBm1kYjQ5tG1pJvNtUkttsJrhx3RP4XSIinCvm1pBTXD0rT5xtyTQPCfwPv
EaAz5d4whxlgiVkb3hqx8RCpS96Vak3pF9QyuCrBSIzAUpsaQ83KAMSMuGqlPUnwX6wYe3Em6Ofp
05Qae6QRMYjYkUYO1nMhZ/u3SpINu3lQtnn4nlG3ux0oFSkLvWbEX96Y+7Pi7cmWMtM6rJEctxNo
5Prkc0t+Lqzb1JV9V7nygoKYcKi7kHgnAvys5saeNaLi/Y8FJsX1jfxHENF/1homwsNXXq24JVzN
n/WKCXOk5Jkovarz7ZPXB9s1ycOMMLL/YLuhZ9fQg5r9OMWgTLrPf/svRbtsQW4Wx0zIuW5+j6uX
C+/sebKpZdt8VW0on9+d1eHFxdNHhBV0GOMT0HTEZB+r0UHruVNRh1w0QBbF1Q77zOYHnhXN8bL5
WzSYs8Rc468fpgOG3D8TRH5tfpsvSQrV0wMjfAmEnCeCQFN1ad27w1eyBRDDYBh+d4gjl6cfkocO
DRtTRuJCKbf9OBpXRf6tzZ5BkMWahYUSgY/WkmEsy4VzlVnuL2RkU4+rb5Xv+m9nYv6VBsWxX0dU
ZChED1GqBIfy5HdfjDHWys1rr7PeoOu8BJUXefllJjj7angLxj+vNqckKMIPCwQOWb2XShI5Jv7i
GhB+vVleC2EBkHh8Eedd5l8wN0jA9BuohND5VAZM+mUCEIYGm5Pwx68rILey40KYplsw6GQt+2Oc
/Ijb2tG1NF2+XJ0tSnrn7CZJgvRp9seNHn6zK4Rj5YoHJNHLtgkUvhOAdUqjNNYBDtDgEXtsNtj1
dbDKob9LImX1R/97cWCzfJUietqvlNUw/HPfZn1jBpW217aOeFKWWRD6ewwmwKHLqkYh0VJmBQoc
TiFeI7TpQSXk+Q+VTvu59Z4ftmmHKG3a1XYvitw6yFoQeQWLVjlzW6WYbk8RFy2eOR3t+e6LlcJe
gIM5yW3HY8h0bEYSTtDw3RKL5OEghBNV27OYl3UF9y9q8/Kcin3gmPFQtes1FjEN9YEIyq/aoLlQ
I99DA48x57iclAzE70qPRIz+AP5VPUpwlIMtw45vw+HT6XQEpgEb2/1A6hphx79eSiUZveaf9MXA
OCDlzo4vsb3EFOTrMQeCz+Lgf4y+BUzrKRnB8HXGh7ffGVVUfRNfdByuj8RJCgElxSCxUkmyWuTk
6zpPlaQEa3CN53v0XhAFffxelDbq63VXINQ4WYZgrKseaQv0A1XUEBA53OoYT2/qlYTXuxCzzVli
pSjlxoXVyp7wYF9tOZhP+WKbSHbK9isOJa6Ry3F9S5RqaZkLDpUJFQSw6VqVYAY0b+s7DjX8SP04
ilDZhpZPJ1l9XKbZtAik2XovrIjrh3xxoccL8HsjJ0EZXwqewyDiFzgyWeiwOwLjrAJtJ6UNjISI
34BxS46tmf0jOFTGrG7XrnLI5B6AV3nrkC9X6H+KQAYxie+SJpIV72Sl+z1yK9WwVl5MNmEho9RI
IpgGISAaxzj8ZI9RboIt/inTYh3wUOi64GTZl606H1epwxbdRa9v+avsyGFybE2QscwXGEiX0x+Q
e07Rlae1MyDAlu9AC8VmeK31vuBvQM3lPxnFkmFYhWhXo7o/H9VqpWlvZUGIrhDc5pBLxPFB0zwV
ooQwnS8NT0L39ZvcP1gE9nYbD81Ionf/RmBSejV0fThf0NC7qMeXmR1l9jnJz5skdm/IAaRHlG0G
IFPqBBqhHQrhuDDfJ41q7HMDWvOzQuFuG45o2UzfWcCPj6qWWKGw3KuCHLk/ByGylig1z4C1Dop8
JmR/qZYi4ym7Vzhl/0+yp1YkysRet185TQPm9RB80AiJgrM049DT9LFOaWSAkaQzEEksLKi9j6Mp
pVW6+27VD7oX2rTRL/fYvUPXknh62llMDUqvLkpJKNpitCZB3zaq/98G24sba3ouPGSB9r6+WEgK
XpWYLlDTq+IIM8hIU9eu5rFxUazcMCxj9crU6jHuHbDnUZuMIeToUCwM+ccYJ0P4sYSMXQAP+cis
o2O29OGOKC7FUzqOur6lNEn3O+XkXLL3rj50fDZe8YSCAuAjWFfZ4N13dWXBQZx/iJ/5UywRYGDo
88PTYWn7yatncrwN9Iu38lGWdsZ96aB6iA7J+93BiGIoKWLgZsSI2Li+PHlNA8xBmA27v0BbnjXs
UXR5mj9rB0VzFkSrHas413Y8UzPn0VYyO5jCf8ki4XxYDNSIbfJ4id3f1Pt8uPYLXKXIva1PcfLe
Akc8vE3FL3QcdYkNVsQy8g4cBrlYn6GbnZ6fQlMFcoF/hqfP0XZuAwByA3U71doEpD6+zMLLHI2y
STbAwa/G6WLIz4VX4F3ZHE7jlPCbFK6B2tsjxH9AGZotKrIVr+KYCsW0EvCfTm4uibOZzC9qjk75
UEBfK2yzSqpeV3i6Foq94BDHGwZliaQSUi/fzVKiL9qvztjhC5t+N5QDKJzzj9jS9/8IPNwyQewq
1wtHJQDrbWpukxAiNnVavC+uoGbjgkGA7ZXODBNAvn5cqe0kRxnz3BViMuSyO4qUyFWk2LOD20y4
+l+FDOF4LInt5gk2eeVuiyOMXpHssWHq5qYdOl5c/yxRcPTVVv7lFgOb+gphsQ0Ik74nCR9zMUK6
JE/3BximEL7ub7qSyVsLQNpcqRDU77gnXNvRl/6VB6CSMGoR9CxNdkxfbeMAAorb5G7ioRxkiPHQ
5PyYg1N36aBHk7kllCgtZexwYdrlTCToPPAHenhvBoaVtJhIbU/DPc15+Bh4KvizwcagHW1NhVqt
jmtf9N8YZEV8kyKW1FBcn4h155a/hQaLddSPL9PJoq3K3Tj+LeGAcPD0nGpiB3jGGdJFDZi1GlNq
n0KfpCJQzEAImRzSdxCe/caO5WYO1DkXyjhOLtJre9H5oQfI+ACCj0hKWAJabJwtnDl7ADXu4+0p
NyixtocXQvmz61ZfL9aW1SN4ec7RQcd94YHDvlvekQIhIroDibzfqqJuwc2qjDrKsG27XTPeeoTn
F0lFknUl8eQ4kDFbHznDPWSVjHfv3Jm2X5xWK6Q53YohtxyP+uWmK/BhFcjqYIwSatDZ3nsJlqGa
vNoFGbRQMTZBRBxXCe8ZB7Iegoke/4JUuuodIqxxPmVHdGKJsjWu8GjkdE+Y11CsX4ChTTt6rDDx
AvytOt7Z7run9xdyPA4UCDrDjcqVslG+JS625Fxi9Klbp3nzElPKNUiOrkMOjxdxFTGOEyIkr5ol
MfXlXpt6OFJO1t0HTAhDjUFfulAEm91DEZWAF0LjH8Sk0MZQy6xvvUHfY95DxsHg9WwTvZIWfvxi
E7UokGXWX6sk43B+RRvXsmLKJLCxuGW5u1uT60s8Uk68AHf825bWr0MLaJyJ5rfgX0DLPZ6U/+yf
RJJTwpvmpSrKjPuRLF46tKA0De8i1w5ff6Mnq9YZyDnmUMDWp3xW3KQ6cTvFRUWNiho5iblupbAW
TpAoB0c9WancQ/sJpVDym9fWpX2NLk6l37G4kuwXTHmXBX3ozwqvYjZWgKOZfY4tYHDYjN3AKgXz
Omnjq0J9xkreSwnfSFsTDTnOLqYkzsCAEBNxJ5mb/Ts5+8Yeurx4QT0bZlJygLIMLZ6AiZpeQfN7
iS7VX7Bl+WHwAFAh0rN74TiT4gt6fzQiTI88ym3ri2u5agExjVRZ1ysB5dAA41D3HR3Ce25w9V6F
wuzhLlbLvBdZ/5yyGDJueiYkfKYFnhPU2m2WjFBhDxGyjb2T6AQIEQoVCIMQCIUCrf1WP77kprMR
howAD4YPBcuaZGzPjmLSbzTcO1KIjXfOM50j6YJ0lPo4a0RUswQUYrmr2cphDC1Xzq4FBT37Th9M
VPGWkX8qMHhDL0BXfj4Zm7oUZ1uVcPKRReXCUtmszAyxETp8DQx/BgG4pQcypDPI2eQlf7Vm0aTU
vBozCllP/KdLKuOwwhsp29a/YYqWmbSbN9MU34NIH4VULD2cEr9khZawf2PPLE3nqajRJV1F8uDB
yBlsiRGY4715Tw7DsE8ZeygxS5RQyb0S5JEu6hOOVMZ1iUcz2pmHIWyiLNnC707NVjH6pXwDAdih
TfoA4i5yHYu+S4l7dHXFkZGDKeWUcWI7chtrT3muZUQKcYzBOEqumWgSqP67Nvre0YX/i23S27Iu
fplxr+HfpRXRjF0ZbGFpHAgYYh2HJ3ci8luuqU0ZxbY7TsPw02jVP6c6hVRCoqbHuGaJV52jUckO
9qRVIkayGz5gesS+0/kfOo6u1a3aeu7mf6qPi+NUBf3zbJ6J9Mv0tp0XUlntjG/i2+aOibH3U7DV
X9SAqEidecW+yNDeQzTJ/pXW1A1einFXSMab9ZBYV/LR5xk/B7vvFVMVEF//hgJcplEtA+U0rpqu
jgwCHyQ0S8ogN3nYvU7ofkA5FUSsnZM2YYWoG10T5WeUMaSvAp+1n/+tmB0USI7iQzyvVabexIsX
/SIdyj3k7+iC8yqyErmrXJldogtBoEFa//bVT9jsZp3avyuHIgth0S4A+4SgMpADcm5t2lG1iNtn
hvwwAaohEd/9iGZCasM8LsjVudFB87sR3BmOCT+thysccH9lKLSAaQOHAcBdVLkS+XdMMAaTYZ+s
R1HzhdvDLaAncC42t/JF5kxfWK/BmGyef/lxQRxTSb8AGbt/6swNdd3jmUSoxDbO8APwLEYkaXMq
rNG9ULLhJMuyox788e1tw/QKZqrLvZ8QjII5qPEAbjiPZ6Rq2hUTYWNdNtA+CNTOmOeoLDTmQNK4
s3c0RpWZYZnBPtd6ybzZQfuyiTcVycNdm8tOGoRsr3p0gD7rFFdznV/8cwyS+mgqHr5xi5kLB9Fa
0GtqNmu2vPkuzJ4+BTWIsYXbpx43ekamvpGaUDOoKbmYb0ycuGjSyOpDCw11w387jIpNuxAjQr20
BMHHLqwFAiab7gVrXao6hya1WPXCPtbTO22XE59m9l3BkKc2o6XJSn2/h9zp0ceJCcIb7fT+6zuZ
jBQXhwWhHzsrWzJ696iEOFQOR38itYQCLtaMWhUBPeHnuCZo10mRmlKgh7M1xJG//AUwoZ6L818p
DtMTr39ht3I2HbOmSC9fzv5Eet3BYMQA869B9fjfml9sTyZ4Y0gslMw0zlc2WWjVyf+nb2LP2p16
FwHUtSO0DV0cwoWn0clVQPC20JEHkoUZdEXA0xr60n0J1RpaYQxta5P5xohRvNbpGA672kS3Orl0
o0You75PbSVUPB1gkLoIn1QPPimFGIMqxLYMe4l9Eqk0KgeU0vaVJqN15BLCkysSNxwSUjcDOhWQ
/U85nmKr5v0zoHPU39qqWO0THdMkEOhPFj0sYKaAAjXdi3TUtjm552WO8tIcQIydv+dIwBJGVxYP
oMo1z7oj9VhWn1WpxbpdoaznMHojemQfCAviYijNCTgWyH2gTtax+IG4rT87+Xu+H0s8GW2PlWzj
D+/Q/OUg+jYkZeb4TfpHwP4zMp6kC44LbAzvshgvIE+6izROjgeJZQA8IIl6cV47eBAOPTGGtOPH
qMrzV8N/wSKbNXtl7R5aMMWBby+jRvkVVhBSbwMQpBg2twYaR1cZDcKucF5XzuvRwF+rWTGp9oXK
qqgqLC9wvJ37r29F1ogqaITobeM2rWhyiGRG8xEX6kLJBBGwRbjrJj/98gQugKe0j6680QAXoZUy
LgUvpH6/CL8MXMygScQu9bIlPP42pwg1AmX+tGAlaqTHe5UXeugNPuXTnmR7UbsgvsM/EV4+vy0f
xz9EA8BdLixW4p0k18dPbkEmL15LNuVxEhutpLQDfcQF/H9u8g7DReU2lBIFGlVxx7EDQBX6IMuo
acnDTFRUOdHZRFw4eCZYYrOgrQXkjFcY31aZ2YW2wOKylUruFOaP6EjVPTMmwynNo9/9FbGNOg/f
8uMg6l9fFuUanFVeixFDyOPmgNXx3phmUISEUyizxbR2M8e4QZK33zvciHXtJKcgMexfnK+hZRkQ
dsXk68W+eAZiIcSIRU1IDaJoHgpApPlPwRkTxLTYjG61J/743Zx3kV+ISoJJtpL2jMGrbVlSheE5
FE4VZAsAAQGmXfN7fEPiAUQB3aWG0q1xjq0rl3w9ibv8PafARN6mw+1SdtdFnjLfjzlcaiABXZZQ
kwC2j0F0ZFaInwSQdENyS7IzcpbiQ912JRIA52KXPPH3JtRZ+woJr6jH6Y4khAMFrXJYFyJnepFb
9fboqillX04eao+F2ps7kH7HoyzHNHsZBBenluHheqjBgLewSs0vUP2lsgpLmm+Vi+/jJ/tz1tzm
IHWOBZC+CykaILO3NC7ApRo2VibYUIXxEhxY4u3DoxgQPABS9FmEhnm5Z7dahAof4iSDfBDsuIN1
7hk9Me52xo+AvQtg2bavnvleXXBOS1VxkMwv/1qD9MjIPdl9QAd0o6seYnlm1wkg4hR5bdrAMLDK
40f53yNnNOoPch1AHuNFLygfSjQghNPrDZN68166cbKND5swI3+7sp68ZPZG356IN6KXotjcTw2A
CiEjuD0+sItCbX17yJ71GnQ=
`protect end_protected
|
--
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top_level is
port(
-- FX2LP interface ---------------------------------------------------------------------------
fx2Clk_in : in std_logic; -- 48MHz clock from FX2LP
fx2Addr_out : out std_logic_vector(1 downto 0); -- select FIFO: "00" for EP2OUT, "10" for EP6IN
fx2Data_io : inout std_logic_vector(7 downto 0); -- 8-bit data to/from FX2LP
-- When EP2OUT selected:
fx2Read_out : out std_logic; -- asserted (active-low) when reading from FX2LP
fx2OE_out : out std_logic; -- asserted (active-low) to tell FX2LP to drive bus
fx2GotData_in : in std_logic; -- asserted (active-high) when FX2LP has data for us
-- When EP6IN selected:
fx2Write_out : out std_logic; -- asserted (active-low) when writing to FX2LP
fx2GotRoom_in : in std_logic; -- asserted (active-high) when FX2LP has room for more data from us
fx2PktEnd_out : out std_logic; -- asserted (active-low) when a host read needs to be committed early
-- Onboard peripherals -----------------------------------------------------------------------
sseg_out : out std_logic_vector(7 downto 0); -- seven-segment display cathodes (one for each segment)
anode_out : out std_logic_vector(3 downto 0); -- seven-segment display anodes (one for each digit)
led_out : out std_logic_vector(7 downto 0); -- eight LEDs
sw_in : in std_logic_vector(7 downto 0) -- eight switches
);
end entity;
architecture structural of top_level is
-- Channel read/write interface -----------------------------------------------------------------
signal chanAddr : std_logic_vector(6 downto 0); -- the selected channel (0-127)
-- Host >> FPGA pipe:
signal h2fData : std_logic_vector(7 downto 0); -- data lines used when the host writes to a channel
signal h2fValid : std_logic; -- '1' means "on the next clock rising edge, please accept the data on h2fData"
signal h2fReady : std_logic; -- channel logic can drive this low to say "I'm not ready for more data yet"
-- Host << FPGA pipe:
signal f2hData : std_logic_vector(7 downto 0); -- data lines used when the host reads from a channel
signal f2hValid : std_logic; -- channel logic can drive this low to say "I don't have data ready for you"
signal f2hReady : std_logic; -- '1' means "on the next clock rising edge, put your next byte of data on f2hData"
-- ----------------------------------------------------------------------------------------------
-- Needed so that the comm_fpga_fx2 module can drive both fx2Read_out and fx2OE_out
signal fx2Read : std_logic;
-- Reset signal so host can delay startup
signal fx2Reset : std_logic;
begin
-- CommFPGA module
fx2Read_out <= fx2Read;
fx2OE_out <= fx2Read;
fx2Addr_out(0) <= -- So fx2Addr_out(1)='0' selects EP2OUT, fx2Addr_out(1)='1' selects EP6IN
'0' when fx2Reset = '0'
else 'Z';
comm_fpga_fx2 : entity work.comm_fpga_fx2
port map(
clk_in => fx2Clk_in,
reset_in => '0',
reset_out => fx2Reset,
-- FX2LP interface
fx2FifoSel_out => fx2Addr_out(1),
fx2Data_io => fx2Data_io,
fx2Read_out => fx2Read,
fx2GotData_in => fx2GotData_in,
fx2Write_out => fx2Write_out,
fx2GotRoom_in => fx2GotRoom_in,
fx2PktEnd_out => fx2PktEnd_out,
-- DVR interface -> Connects to application module
chanAddr_out => chanAddr,
h2fData_out => h2fData,
h2fValid_out => h2fValid,
h2fReady_in => h2fReady,
f2hData_in => f2hData,
f2hValid_in => f2hValid,
f2hReady_out => f2hReady
);
-- Switches & LEDs application
swled_app : entity work.swled
port map(
clk_in => fx2Clk_in,
reset_in => '0',
-- DVR interface -> Connects to comm_fpga module
chanAddr_in => chanAddr,
h2fData_in => h2fData,
h2fValid_in => h2fValid,
h2fReady_out => h2fReady,
f2hData_out => f2hData,
f2hValid_out => f2hValid,
f2hReady_in => f2hReady,
-- External interface
sseg_out => sseg_out,
anode_out => anode_out,
led_out => led_out,
sw_in => sw_in
);
end architecture;
|
entity test is
package a is new b generic map(c => foo(0 to 2)(open)(bar'baz));
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1414.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b01x00p01n01i01414ent IS
END c08s05b01x00p01n01i01414ent;
ARCHITECTURE c08s05b01x00p01n01i01414arch OF c08s05b01x00p01n01i01414ent IS
BEGIN
TESTING: PROCESS
type array_type is array (1 to 10) of integer;
variable v1 : array_type;
BEGIN
v1 (1) := integer'(12);
assert NOT(v1(1)=12)
report "***PASSED TEST: c08s05b01x00p01n01i01414"
severity NOTE;
assert (v1(1)=12)
report "***FAILED TEST: c08s05b01x00p01n01i01414 - Each element of the array variable there is a matching element on the right hand side."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b01x00p01n01i01414arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1414.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b01x00p01n01i01414ent IS
END c08s05b01x00p01n01i01414ent;
ARCHITECTURE c08s05b01x00p01n01i01414arch OF c08s05b01x00p01n01i01414ent IS
BEGIN
TESTING: PROCESS
type array_type is array (1 to 10) of integer;
variable v1 : array_type;
BEGIN
v1 (1) := integer'(12);
assert NOT(v1(1)=12)
report "***PASSED TEST: c08s05b01x00p01n01i01414"
severity NOTE;
assert (v1(1)=12)
report "***FAILED TEST: c08s05b01x00p01n01i01414 - Each element of the array variable there is a matching element on the right hand side."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b01x00p01n01i01414arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1414.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b01x00p01n01i01414ent IS
END c08s05b01x00p01n01i01414ent;
ARCHITECTURE c08s05b01x00p01n01i01414arch OF c08s05b01x00p01n01i01414ent IS
BEGIN
TESTING: PROCESS
type array_type is array (1 to 10) of integer;
variable v1 : array_type;
BEGIN
v1 (1) := integer'(12);
assert NOT(v1(1)=12)
report "***PASSED TEST: c08s05b01x00p01n01i01414"
severity NOTE;
assert (v1(1)=12)
report "***FAILED TEST: c08s05b01x00p01n01i01414 - Each element of the array variable there is a matching element on the right hand side."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b01x00p01n01i01414arch;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: system_axi_vdma_0_wrapper_fifo_generator_v9_3_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for FIFO Generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE system_axi_vdma_0_wrapper_fifo_generator_v9_3_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT system_axi_vdma_0_wrapper_fifo_generator_v9_3_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_vdma_0_wrapper_fifo_generator_v9_3_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_vdma_0_wrapper_fifo_generator_v9_3_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT system_axi_vdma_0_wrapper_fifo_generator_v9_3_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_vdma_0_wrapper_fifo_generator_v9_3_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT system_axi_vdma_0_wrapper_fifo_generator_v9_3_exdes IS
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(7-1 DOWNTO 0);
WR_ACK : OUT std_logic;
VALID : OUT std_logic;
ALMOST_EMPTY : OUT std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(35-1 DOWNTO 0);
DOUT : OUT std_logic_vector(35-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END system_axi_vdma_0_wrapper_fifo_generator_v9_3_pkg;
PACKAGE BODY system_axi_vdma_0_wrapper_fifo_generator_v9_3_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END system_axi_vdma_0_wrapper_fifo_generator_v9_3_pkg;
|
-- Btrace 448
-- Dot Product Unit
--
-- Bradley Boccuzzi
-- 2016
library ieee;
library ieee_proposed;
use ieee.std_logic_1164.all;
use ieee_proposed.fixed_pkg.all;
use ieee.std_logic_signed.all;
use work.btrace_pack.all;
entity dot is
generic(int, frac: integer := 16);
port(v1, v2: in vector;
result: out sfixed((2*int)-1 downto -(2*frac)));
end dot;
architecture arch of dot is
signal r1, r2, r3: sfixed((2*int)-1 downto -(2*frac));
signal cr: sfixed((2*int)+1 downto -(2*frac));
begin
r1 <= v1.m_x * v2.m_x;
r2 <= v1.m_y * v2.m_y;
r3 <= v1.m_z * v2.m_z;
cr <= r1 + r2 + r3;
result <= cr((2*int)-1 downto -(2*frac));
end arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_4;
USE floating_point_v7_1_4.floating_point_v7_1_4;
ENTITY sin_taylor_series_ap_dsub_3_full_dsp_64 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END sin_taylor_series_ap_dsub_3_full_dsp_64;
ARCHITECTURE sin_taylor_series_ap_dsub_3_full_dsp_64_arch OF sin_taylor_series_ap_dsub_3_full_dsp_64 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF sin_taylor_series_ap_dsub_3_full_dsp_64_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_4 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_4;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF sin_taylor_series_ap_dsub_3_full_dsp_64_arch: ARCHITECTURE IS "floating_point_v7_1_4,Vivado 2017.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF sin_taylor_series_ap_dsub_3_full_dsp_64_arch : ARCHITECTURE IS "sin_taylor_series_ap_dsub_3_full_dsp_64,floating_point_v7_1_4,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF sin_taylor_series_ap_dsub_3_full_dsp_64_arch: ARCHITECTURE IS "sin_taylor_series_ap_dsub_3_full_dsp_64,floating_point_v7_1_4,{x_ipProduct=Vivado 2017.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=4,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_HAS_ADD=0,C_HAS_SUBTRACT=1,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_F" &
"MS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=64,C_A_FRACTION_WIDTH=53,C_B_WIDTH=64,C_B_FRACTION_WIDTH=53,C_C_WIDTH=64,C_C_FRACTION_WIDTH=53,C_RESULT_WIDTH=64,C_RESULT_FRACTION_WIDTH=53,C_COMPARE_OPERATION=8,C_LATENCY=3,C_OPTIMIZATION=1,C_MULT_USAGE=2,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0" &
",C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=64,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=64,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=64,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=64,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_4
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 1,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 64,
C_A_FRACTION_WIDTH => 53,
C_B_WIDTH => 64,
C_B_FRACTION_WIDTH => 53,
C_C_WIDTH => 64,
C_C_FRACTION_WIDTH => 53,
C_RESULT_WIDTH => 64,
C_RESULT_FRACTION_WIDTH => 53,
C_COMPARE_OPERATION => 8,
C_LATENCY => 3,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 2,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 64,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 64,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 64,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 64,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END sin_taylor_series_ap_dsub_3_full_dsp_64_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_4;
USE floating_point_v7_1_4.floating_point_v7_1_4;
ENTITY sin_taylor_series_ap_dsub_3_full_dsp_64 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END sin_taylor_series_ap_dsub_3_full_dsp_64;
ARCHITECTURE sin_taylor_series_ap_dsub_3_full_dsp_64_arch OF sin_taylor_series_ap_dsub_3_full_dsp_64 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF sin_taylor_series_ap_dsub_3_full_dsp_64_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_4 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_4;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF sin_taylor_series_ap_dsub_3_full_dsp_64_arch: ARCHITECTURE IS "floating_point_v7_1_4,Vivado 2017.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF sin_taylor_series_ap_dsub_3_full_dsp_64_arch : ARCHITECTURE IS "sin_taylor_series_ap_dsub_3_full_dsp_64,floating_point_v7_1_4,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF sin_taylor_series_ap_dsub_3_full_dsp_64_arch: ARCHITECTURE IS "sin_taylor_series_ap_dsub_3_full_dsp_64,floating_point_v7_1_4,{x_ipProduct=Vivado 2017.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=4,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_HAS_ADD=0,C_HAS_SUBTRACT=1,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_F" &
"MS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=64,C_A_FRACTION_WIDTH=53,C_B_WIDTH=64,C_B_FRACTION_WIDTH=53,C_C_WIDTH=64,C_C_FRACTION_WIDTH=53,C_RESULT_WIDTH=64,C_RESULT_FRACTION_WIDTH=53,C_COMPARE_OPERATION=8,C_LATENCY=3,C_OPTIMIZATION=1,C_MULT_USAGE=2,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0" &
",C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=64,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=64,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=64,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=64,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_4
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 1,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 64,
C_A_FRACTION_WIDTH => 53,
C_B_WIDTH => 64,
C_B_FRACTION_WIDTH => 53,
C_C_WIDTH => 64,
C_C_FRACTION_WIDTH => 53,
C_RESULT_WIDTH => 64,
C_RESULT_FRACTION_WIDTH => 53,
C_COMPARE_OPERATION => 8,
C_LATENCY => 3,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 2,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 64,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 64,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 64,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 64,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END sin_taylor_series_ap_dsub_3_full_dsp_64_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_4;
USE floating_point_v7_1_4.floating_point_v7_1_4;
ENTITY sin_taylor_series_ap_dsub_3_full_dsp_64 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END sin_taylor_series_ap_dsub_3_full_dsp_64;
ARCHITECTURE sin_taylor_series_ap_dsub_3_full_dsp_64_arch OF sin_taylor_series_ap_dsub_3_full_dsp_64 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF sin_taylor_series_ap_dsub_3_full_dsp_64_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_4 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_4;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF sin_taylor_series_ap_dsub_3_full_dsp_64_arch: ARCHITECTURE IS "floating_point_v7_1_4,Vivado 2017.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF sin_taylor_series_ap_dsub_3_full_dsp_64_arch : ARCHITECTURE IS "sin_taylor_series_ap_dsub_3_full_dsp_64,floating_point_v7_1_4,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF sin_taylor_series_ap_dsub_3_full_dsp_64_arch: ARCHITECTURE IS "sin_taylor_series_ap_dsub_3_full_dsp_64,floating_point_v7_1_4,{x_ipProduct=Vivado 2017.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=4,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_HAS_ADD=0,C_HAS_SUBTRACT=1,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_F" &
"MS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=64,C_A_FRACTION_WIDTH=53,C_B_WIDTH=64,C_B_FRACTION_WIDTH=53,C_C_WIDTH=64,C_C_FRACTION_WIDTH=53,C_RESULT_WIDTH=64,C_RESULT_FRACTION_WIDTH=53,C_COMPARE_OPERATION=8,C_LATENCY=3,C_OPTIMIZATION=1,C_MULT_USAGE=2,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0" &
",C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=64,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=64,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=64,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=64,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_4
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 1,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 64,
C_A_FRACTION_WIDTH => 53,
C_B_WIDTH => 64,
C_B_FRACTION_WIDTH => 53,
C_C_WIDTH => 64,
C_C_FRACTION_WIDTH => 53,
C_RESULT_WIDTH => 64,
C_RESULT_FRACTION_WIDTH => 53,
C_COMPARE_OPERATION => 8,
C_LATENCY => 3,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 2,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 64,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 64,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 64,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 64,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END sin_taylor_series_ap_dsub_3_full_dsp_64_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 4
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_4;
USE floating_point_v7_1_4.floating_point_v7_1_4;
ENTITY sin_taylor_series_ap_dsub_3_full_dsp_64 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0)
);
END sin_taylor_series_ap_dsub_3_full_dsp_64;
ARCHITECTURE sin_taylor_series_ap_dsub_3_full_dsp_64_arch OF sin_taylor_series_ap_dsub_3_full_dsp_64 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF sin_taylor_series_ap_dsub_3_full_dsp_64_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_4 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_4;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF sin_taylor_series_ap_dsub_3_full_dsp_64_arch: ARCHITECTURE IS "floating_point_v7_1_4,Vivado 2017.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF sin_taylor_series_ap_dsub_3_full_dsp_64_arch : ARCHITECTURE IS "sin_taylor_series_ap_dsub_3_full_dsp_64,floating_point_v7_1_4,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF sin_taylor_series_ap_dsub_3_full_dsp_64_arch: ARCHITECTURE IS "sin_taylor_series_ap_dsub_3_full_dsp_64,floating_point_v7_1_4,{x_ipProduct=Vivado 2017.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=4,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_HAS_ADD=0,C_HAS_SUBTRACT=1,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_F" &
"MS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=64,C_A_FRACTION_WIDTH=53,C_B_WIDTH=64,C_B_FRACTION_WIDTH=53,C_C_WIDTH=64,C_C_FRACTION_WIDTH=53,C_RESULT_WIDTH=64,C_RESULT_FRACTION_WIDTH=53,C_COMPARE_OPERATION=8,C_LATENCY=3,C_OPTIMIZATION=1,C_MULT_USAGE=2,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0" &
",C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=64,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=64,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=64,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=64,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_4
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 1,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 64,
C_A_FRACTION_WIDTH => 53,
C_B_WIDTH => 64,
C_B_FRACTION_WIDTH => 53,
C_C_WIDTH => 64,
C_C_FRACTION_WIDTH => 53,
C_RESULT_WIDTH => 64,
C_RESULT_FRACTION_WIDTH => 53,
C_COMPARE_OPERATION => 8,
C_LATENCY => 3,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 2,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 64,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 64,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 64,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 64,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END sin_taylor_series_ap_dsub_3_full_dsp_64_arch;
|
----------------------------------------------------------------------------------------------------
-- ACS unit calculate path metric value at each clock cycles.
-- it takes previous path metrics and branch metrics of the branches converging to a particular node.
-- New path metric will be lowest of the two path metric calculated.
-- when both path metrics are same, upper path will be selected.
-- Decision - gives 0 when new path metric calculated is sum of PMD and BMD.
-- gives 1 when new path metric calculated is sum of PMU and BMU.
-- gives one when both are equal.
-- --------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ACS is
port (PMU,PMD:in std_logic_vector (2 downto 0); -- previous path metric values
BMU,BMD:in std_logic_vector (1 downto 0); -- branch metric values
DECISION:OUT std_logic; -- decision
RESET,CLK:IN std_logic;
PM:OUT std_logic_vector (2 downto 0)); -- new path metric calculated
END ACS;
architecture archi of ACS is
begin
PROCESS (CLK,RESET)
variable sum1,sum2,pmVar:std_logic_vector(2 downto 0);
variable decisionSig:std_logic;
BEGIN
if (reset = '1')then
pm <= "000";
decision <= '1';
elsif(clk'event and clk = '1')then
sum1 := pmu + bmu;
sum2 := pmd + bmd;
if (sum1 <= sum2)then
pmVar := sum1;
decisionSig :='1';
else
pmVar := sum2;
decisionSig := '0';
end if;
decision <= decisionSig;
pm <= pmVar;
end if;
END PROCESS;
END archi; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package reproducer_pkg is
-- Functions
function MIN(LEFT, RIGHT: unsigned) return unsigned;
function MIN(LEFT, RIGHT: integer) return integer;
end reproducer_pkg;
package body reproducer_pkg is
function MIN(LEFT, RIGHT: unsigned) return unsigned is
begin
if LEFT < RIGHT then
return LEFT;
else
return RIGHT;
end if;
end;
function MIN(LEFT, RIGHT: integer) return integer is
begin
if LEFT < RIGHT then
return LEFT;
else
return RIGHT;
end if;
end;
end reproducer_pkg;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.reproducer_pkg.all;
entity reproducer is
port(
inputA : in unsigned(7 downto 0);
inputB : in unsigned(7 downto 0);
inputC : in integer;
inputD : in integer;
OutputA : out unsigned(7 downto 0);
OutputB : out integer
);
end reproducer;
architecture rtl of reproducer is
begin
OutputA <= min(inputA, inputB);
OutputB <= min(inputC, inputD);
end rtl;
|
-- $Id: tb_cmoda7_core.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: tb_cmoda7_core - sim
-- Description: Test bench for cmoda7 - core device handling
--
-- Dependencies: -
--
-- To test: generic, any cmoda7 target
--
-- Target Devices: generic
-- Tool versions: viv 2016.4; ghdl 0.34
-- Revision History:
-- Date Rev Version Comment
-- 2017-06-04 906 1.0 Initial version (derived from tb_arty_core)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simbus.all;
entity tb_cmoda7_core is
port (
I_BTN : out slv2 -- c7 buttons
);
end tb_cmoda7_core;
architecture sim of tb_cmoda7_core is
signal R_BTN : slv2 := (others=>'0');
constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8));
begin
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_btn then
R_BTN <= to_x01(SB_DATA(R_BTN'range));
end if;
end if;
end process proc_simbus;
I_BTN <= R_BTN;
end sim;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity D11_C2 is
port(
clk:in std_logic;
s0,s1 : out STD_LOGIC
);
end D11_C2;
architecture D11_C2 of D11_C2 is
begin
process(clk)
begin
if(clk='1') then s0<='1';s1<='1';
else s0<='0';s1<='0';
end if;
end process;
end D11_C2;
-- clk=0.5hz |
--
-- Copyright (C) 2011, 2013 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.hex_util.all;
entity spi_master_tb is
end entity;
architecture behavioural of spi_master_tb is
-- Clocks, etc
signal sysClk : std_logic; -- main system clock
signal dispClk : std_logic; -- display version of sysClk, which transitions 4ns before it
signal reset : std_logic;
-- Client interface
signal sendData : std_logic_vector(7 downto 0); -- data to send
signal sendValid : std_logic;
signal sendReady : std_logic;
signal recvData : std_logic_vector(7 downto 0); -- data we receive
signal recvValid : std_logic;
signal recvReady : std_logic;
-- External interface
signal spiClk : std_logic; -- serial clock
signal spiDataOut : std_logic; -- send serial data
signal spiDataIn : std_logic; -- receive serial data
begin
-- Instantiate the unit under test
uut: entity work.spi_master
generic map(
--FAST_COUNT => "000011"
FAST_COUNT => "000000",
BIT_ORDER => '0'
)
port map(
reset_in => reset,
clk_in => sysClk,
turbo_in => '1',
suppress_in => '0',
sendData_in => sendData,
sendValid_in => sendValid,
sendReady_out => sendReady,
recvData_out => recvData,
recvValid_out => recvValid,
recvReady_in => recvReady,
spiClk_out => spiClk,
spiData_out => spiDataOut,
spiData_in => spiDataIn
);
-- Drive the clocks. In simulation, sysClk lags 4ns behind dispClk, to give a visual hold time
-- for signals in GTKWave.
process
begin
sysClk <= '0';
dispClk <= '0';
wait for 16 ns;
loop
dispClk <= not(dispClk); -- first dispClk transitions
wait for 4 ns;
sysClk <= not(sysClk); -- then sysClk transitions, 4ns later
wait for 6 ns;
end loop;
end process;
-- Deassert the synchronous reset a couple of cycles after startup.
--
process
begin
reset <= '1';
wait until rising_edge(sysClk);
wait until rising_edge(sysClk);
reset <= '0';
wait;
end process;
-- Drive the unit under test. Read stimulus from stimulus.sim and write results to results.sim
process
variable inLine : line;
variable outLine : line;
file inFile : text open read_mode is "stimulus/send.sim";
file outFile : text open write_mode is "results/recv.sim";
begin
sendData <= (others => 'X');
sendValid <= '0';
wait until falling_edge(reset);
wait until rising_edge(sysClk);
while ( not endfile(inFile) ) loop
readline(inFile, inLine);
while ( inLine.all'length = 0 or inLine.all(1) = '#' or inLine.all(1) = ht or inLine.all(1) = ' ' ) loop
readline(inFile, inLine);
end loop;
sendData <= to_4(inLine.all(1)) & to_4(inLine.all(2));
sendValid <= to_1(inLine.all(4));
recvReady <= to_1(inLine.all(6));
wait for 10 ns;
write(outLine, from_4(sendData(7 downto 4)) & from_4(sendData(3 downto 0)));
write(outLine, ' ');
write(outLine, sendValid);
write(outLine, ' ');
write(outLine, sendReady);
writeline(outFile, outLine);
wait for 10 ns;
end loop;
sendData <= (others => 'X');
sendValid <= '0';
wait;
end process;
-- Mock the serial interface's interlocutor: send from s/recv.sim and receive into r/send.sim
process
variable inLine, outLine : line;
variable inData, outData : std_logic_vector(7 downto 0);
file inFile : text open read_mode is "stimulus/recv.sim";
file outFile : text open write_mode is "results/send.sim";
begin
spiDataIn <= 'X';
loop
exit when endfile(inFile);
readline(inFile, inLine);
read(inLine, inData);
wait until spiClk = '0';
spiDataIn <= inData(0);
wait until spiClk = '1';
outData(0) := spiDataOut;
wait until spiClk = '0';
spiDataIn <= inData(1);
wait until spiClk = '1';
outData(1) := spiDataOut;
wait until spiClk = '0';
spiDataIn <= inData(2);
wait until spiClk = '1';
outData(2) := spiDataOut;
wait until spiClk = '0';
spiDataIn <= inData(3);
wait until spiClk = '1';
outData(3) := spiDataOut;
wait until spiClk = '0';
spiDataIn <= inData(4);
wait until spiClk = '1';
outData(4) := spiDataOut;
wait until spiClk = '0';
spiDataIn <= inData(5);
wait until spiClk = '1';
outData(5) := spiDataOut;
wait until spiClk = '0';
spiDataIn <= inData(6);
wait until spiClk = '1';
outData(6) := spiDataOut;
wait until spiClk = '0';
spiDataIn <= inData(7);
wait until spiClk = '1';
outData(7) := spiDataOut;
write(outLine, outData);
writeline(outFile, outLine);
end loop;
wait for 10 ns;
spiDataIn <= 'X';
wait;
end process;
end architecture;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Button Controller
-- Project Name: Button Controller
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Switch Controller
-- Maintain input from the four buttons on Nexys
-- Built in debouncer for buttons
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.all;
entity buttoncontrol is
Port ( CLK : in STD_LOGIC;
SW : in STD_LOGIC;
BTN : in STD_LOGIC_VECTOR (3 downto 0);
LED : out STD_LOGIC_VECTOR (3 downto 0));
end buttoncontrol;
architecture Structural of buttoncontrol is
begin
----- Structural Components: -----
BTN_0: entity work.debounce
port map( CLK => CLK,
EN => SW,
INPUT => BTN(0),
OUTPUT => LED(0));
BTN_1: entity work.debounce
port map( CLK => CLK,
EN => SW,
INPUT => BTN(1),
OUTPUT => LED(1));
BTN_2: entity work.debounce
port map( CLK => CLK,
EN => SW,
INPUT => BTN(2),
OUTPUT => LED(2));
BTN_3: entity work.debounce
port map( CLK => CLK,
EN => SW,
INPUT => BTN(3),
OUTPUT => LED(3));
----- End Structural Components -----
end Structural;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: Button Controller
-- Project Name: Button Controller
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: Switch Controller
-- Maintain input from the four buttons on Nexys
-- Built in debouncer for buttons
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.all;
entity buttoncontrol is
Port ( CLK : in STD_LOGIC;
SW : in STD_LOGIC;
BTN : in STD_LOGIC_VECTOR (3 downto 0);
LED : out STD_LOGIC_VECTOR (3 downto 0));
end buttoncontrol;
architecture Structural of buttoncontrol is
begin
----- Structural Components: -----
BTN_0: entity work.debounce
port map( CLK => CLK,
EN => SW,
INPUT => BTN(0),
OUTPUT => LED(0));
BTN_1: entity work.debounce
port map( CLK => CLK,
EN => SW,
INPUT => BTN(1),
OUTPUT => LED(1));
BTN_2: entity work.debounce
port map( CLK => CLK,
EN => SW,
INPUT => BTN(2),
OUTPUT => LED(2));
BTN_3: entity work.debounce
port map( CLK => CLK,
EN => SW,
INPUT => BTN(3),
OUTPUT => LED(3));
----- End Structural Components -----
end Structural;
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj\hdlsrc\lms\LMS.vhd
-- Created: 2015-06-19 16:39:42
--
-- Generated by MATLAB 8.5 and HDL Coder 3.6
--
--
-- -------------------------------------------------------------
-- Rate and Clocking Details
-- -------------------------------------------------------------
-- Model base rate: 2.26757e-05
-- Target subsystem base rate: 2.26757e-05
--
--
-- Clock Enable Sample Time
-- -------------------------------------------------------------
-- ce_out 2.26757e-05
-- -------------------------------------------------------------
--
--
-- Output Signal Clock Enable Sample Time
-- -------------------------------------------------------------
-- e_k ce_out 2.26757e-05
-- -------------------------------------------------------------
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: LMS
-- Source Path: lms/LMS
-- Hierarchy Level: 0
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.LMS_pkg.ALL;
ENTITY LMS IS
PORT( clk : IN std_logic;
reset : IN std_logic;
clk_enable : IN std_logic;
x_k : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
d_k : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
ce_out : OUT std_logic;
e_k : OUT std_logic_vector(15 DOWNTO 0) -- sfix16_En14
);
END LMS;
ARCHITECTURE rtl OF LMS IS
-- Constants
CONSTANT C_LMS_FILTER_STEP_SIZE : signed(15 DOWNTO 0) := "0100000000000000"; -- sfix16_En17
-- Signals
SIGNAL enb : std_logic;
SIGNAL x_k_signed : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL d_k_signed : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL LMS_Filter_out1 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL LMS_Filter_out2 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL weight : vector_of_signed16(0 TO 15); -- sfix16_En14 [16]
SIGNAL filter_sum : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL data_pipeline : vector_of_signed16(0 TO 15); -- sfix16_En14 [16]
SIGNAL data_pipeline_tmp : vector_of_signed16(0 TO 14); -- sfix16_En14 [15]
SIGNAL filter_products : vector_of_signed16(0 TO 15); -- sfix16_En14 [16]
SIGNAL mul_temp : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_1 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_2 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_3 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_4 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_5 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_6 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_7 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_8 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_9 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_10 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_11 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_12 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_13 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_14 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_15 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL sum_1 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_1 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL sum_2 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_2 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_3 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_1 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL sum_3 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_4 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_5 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_2 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL sum_4 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_6 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_7 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_3 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL sum_5 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_8 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_9 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_4 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL sum_6 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_10 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_11 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_5 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL sum_7 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_12 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_13 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_6 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL sum_8 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_14 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_15 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_7 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL sum_9 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_16 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_17 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_8 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL sum_10 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_18 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_19 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_9 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL sum_11 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_20 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_21 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_10 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL sum_12 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_22 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_23 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_11 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL sum_13 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_24 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_25 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_12 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL sum_14 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_26 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_27 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_13 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL add_cast_28 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_29 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_14 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL sub_cast : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL sub_cast_1 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL sub_temp : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL mu_err : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL mul_temp_16 : signed(31 DOWNTO 0); -- sfix32_En31
SIGNAL mu_err_data_prod : vector_of_signed16(0 TO 15); -- sfix16_En14 [16]
SIGNAL mul_temp_17 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_18 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_19 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_20 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_21 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_22 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_23 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_24 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_25 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_26 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_27 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_28 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_29 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_30 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_31 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_32 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL weight_adder_output : vector_of_signed16(0 TO 15); -- sfix16_En14 [16]
SIGNAL add_cast_30 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_31 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_15 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL add_cast_32 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_33 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_16 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL add_cast_34 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_35 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_17 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL add_cast_36 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_37 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_18 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL add_cast_38 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_39 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_19 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL add_cast_40 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_41 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_20 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL add_cast_42 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_43 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_21 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL add_cast_44 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_45 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_22 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL add_cast_46 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_47 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_23 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL add_cast_48 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_49 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_24 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL add_cast_50 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_51 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_25 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL add_cast_52 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_53 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_26 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL add_cast_54 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_55 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_27 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL add_cast_56 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_57 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_28 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL add_cast_58 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_59 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_29 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL add_cast_60 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_61 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_30 : signed(16 DOWNTO 0); -- sfix17_En14
BEGIN
x_k_signed <= signed(x_k);
d_k_signed <= signed(d_k);
enb <= clk_enable;
-- ***********************
-- ********* LMS *********
-- ***********************
-- * LMS: FIR section
LMS_Filter_del_temp_process1 : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
data_pipeline_tmp <= (OTHERS => (OTHERS => '0'));
ELSIF clk'event AND clk = '1' THEN
IF enb = '1' THEN
data_pipeline_tmp(0 TO 13) <= data_pipeline_tmp(1 TO 14);
data_pipeline_tmp(14) <= x_k_signed;
END IF;
END IF;
END PROCESS LMS_Filter_del_temp_process1;
data_pipeline(0 TO 14) <= data_pipeline_tmp(0 TO 14);
data_pipeline(15) <= x_k_signed;
mul_temp <= data_pipeline(0) * weight(0);
filter_products(0) <= resize(shift_right(mul_temp(29 DOWNTO 0) + ( "0" & (mul_temp(14) & NOT mul_temp(14) & NOT mul_temp(14) & NOT mul_temp(14) & NOT mul_temp(14) & NOT mul_temp(14) & NOT mul_temp(14) & NOT mul_temp(14) & NOT mul_temp(14) & NOT mul_temp(14) & NOT mul_temp(14) & NOT mul_temp(14) & NOT mul_temp(14) & NOT mul_temp(14))), 14), 16);
mul_temp_1 <= data_pipeline(1) * weight(1);
filter_products(1) <= resize(shift_right(mul_temp_1(29 DOWNTO 0) + ( "0" & (mul_temp_1(14) & NOT mul_temp_1(14) & NOT mul_temp_1(14) & NOT mul_temp_1(14) & NOT mul_temp_1(14) & NOT mul_temp_1(14) & NOT mul_temp_1(14) & NOT mul_temp_1(14) & NOT mul_temp_1(14) & NOT mul_temp_1(14) & NOT mul_temp_1(14) & NOT mul_temp_1(14) & NOT mul_temp_1(14) & NOT mul_temp_1(14))), 14), 16);
mul_temp_2 <= data_pipeline(2) * weight(2);
filter_products(2) <= resize(shift_right(mul_temp_2(29 DOWNTO 0) + ( "0" & (mul_temp_2(14) & NOT mul_temp_2(14) & NOT mul_temp_2(14) & NOT mul_temp_2(14) & NOT mul_temp_2(14) & NOT mul_temp_2(14) & NOT mul_temp_2(14) & NOT mul_temp_2(14) & NOT mul_temp_2(14) & NOT mul_temp_2(14) & NOT mul_temp_2(14) & NOT mul_temp_2(14) & NOT mul_temp_2(14) & NOT mul_temp_2(14))), 14), 16);
mul_temp_3 <= data_pipeline(3) * weight(3);
filter_products(3) <= resize(shift_right(mul_temp_3(29 DOWNTO 0) + ( "0" & (mul_temp_3(14) & NOT mul_temp_3(14) & NOT mul_temp_3(14) & NOT mul_temp_3(14) & NOT mul_temp_3(14) & NOT mul_temp_3(14) & NOT mul_temp_3(14) & NOT mul_temp_3(14) & NOT mul_temp_3(14) & NOT mul_temp_3(14) & NOT mul_temp_3(14) & NOT mul_temp_3(14) & NOT mul_temp_3(14) & NOT mul_temp_3(14))), 14), 16);
mul_temp_4 <= data_pipeline(4) * weight(4);
filter_products(4) <= resize(shift_right(mul_temp_4(29 DOWNTO 0) + ( "0" & (mul_temp_4(14) & NOT mul_temp_4(14) & NOT mul_temp_4(14) & NOT mul_temp_4(14) & NOT mul_temp_4(14) & NOT mul_temp_4(14) & NOT mul_temp_4(14) & NOT mul_temp_4(14) & NOT mul_temp_4(14) & NOT mul_temp_4(14) & NOT mul_temp_4(14) & NOT mul_temp_4(14) & NOT mul_temp_4(14) & NOT mul_temp_4(14))), 14), 16);
mul_temp_5 <= data_pipeline(5) * weight(5);
filter_products(5) <= resize(shift_right(mul_temp_5(29 DOWNTO 0) + ( "0" & (mul_temp_5(14) & NOT mul_temp_5(14) & NOT mul_temp_5(14) & NOT mul_temp_5(14) & NOT mul_temp_5(14) & NOT mul_temp_5(14) & NOT mul_temp_5(14) & NOT mul_temp_5(14) & NOT mul_temp_5(14) & NOT mul_temp_5(14) & NOT mul_temp_5(14) & NOT mul_temp_5(14) & NOT mul_temp_5(14) & NOT mul_temp_5(14))), 14), 16);
mul_temp_6 <= data_pipeline(6) * weight(6);
filter_products(6) <= resize(shift_right(mul_temp_6(29 DOWNTO 0) + ( "0" & (mul_temp_6(14) & NOT mul_temp_6(14) & NOT mul_temp_6(14) & NOT mul_temp_6(14) & NOT mul_temp_6(14) & NOT mul_temp_6(14) & NOT mul_temp_6(14) & NOT mul_temp_6(14) & NOT mul_temp_6(14) & NOT mul_temp_6(14) & NOT mul_temp_6(14) & NOT mul_temp_6(14) & NOT mul_temp_6(14) & NOT mul_temp_6(14))), 14), 16);
mul_temp_7 <= data_pipeline(7) * weight(7);
filter_products(7) <= resize(shift_right(mul_temp_7(29 DOWNTO 0) + ( "0" & (mul_temp_7(14) & NOT mul_temp_7(14) & NOT mul_temp_7(14) & NOT mul_temp_7(14) & NOT mul_temp_7(14) & NOT mul_temp_7(14) & NOT mul_temp_7(14) & NOT mul_temp_7(14) & NOT mul_temp_7(14) & NOT mul_temp_7(14) & NOT mul_temp_7(14) & NOT mul_temp_7(14) & NOT mul_temp_7(14) & NOT mul_temp_7(14))), 14), 16);
mul_temp_8 <= data_pipeline(8) * weight(8);
filter_products(8) <= resize(shift_right(mul_temp_8(29 DOWNTO 0) + ( "0" & (mul_temp_8(14) & NOT mul_temp_8(14) & NOT mul_temp_8(14) & NOT mul_temp_8(14) & NOT mul_temp_8(14) & NOT mul_temp_8(14) & NOT mul_temp_8(14) & NOT mul_temp_8(14) & NOT mul_temp_8(14) & NOT mul_temp_8(14) & NOT mul_temp_8(14) & NOT mul_temp_8(14) & NOT mul_temp_8(14) & NOT mul_temp_8(14))), 14), 16);
mul_temp_9 <= data_pipeline(9) * weight(9);
filter_products(9) <= resize(shift_right(mul_temp_9(29 DOWNTO 0) + ( "0" & (mul_temp_9(14) & NOT mul_temp_9(14) & NOT mul_temp_9(14) & NOT mul_temp_9(14) & NOT mul_temp_9(14) & NOT mul_temp_9(14) & NOT mul_temp_9(14) & NOT mul_temp_9(14) & NOT mul_temp_9(14) & NOT mul_temp_9(14) & NOT mul_temp_9(14) & NOT mul_temp_9(14) & NOT mul_temp_9(14) & NOT mul_temp_9(14))), 14), 16);
mul_temp_10 <= data_pipeline(10) * weight(10);
filter_products(10) <= resize(shift_right(mul_temp_10(29 DOWNTO 0) + ( "0" & (mul_temp_10(14) & NOT mul_temp_10(14) & NOT mul_temp_10(14) & NOT mul_temp_10(14) & NOT mul_temp_10(14) & NOT mul_temp_10(14) & NOT mul_temp_10(14) & NOT mul_temp_10(14) & NOT mul_temp_10(14) & NOT mul_temp_10(14) & NOT mul_temp_10(14) & NOT mul_temp_10(14) & NOT mul_temp_10(14) & NOT mul_temp_10(14))), 14), 16);
mul_temp_11 <= data_pipeline(11) * weight(11);
filter_products(11) <= resize(shift_right(mul_temp_11(29 DOWNTO 0) + ( "0" & (mul_temp_11(14) & NOT mul_temp_11(14) & NOT mul_temp_11(14) & NOT mul_temp_11(14) & NOT mul_temp_11(14) & NOT mul_temp_11(14) & NOT mul_temp_11(14) & NOT mul_temp_11(14) & NOT mul_temp_11(14) & NOT mul_temp_11(14) & NOT mul_temp_11(14) & NOT mul_temp_11(14) & NOT mul_temp_11(14) & NOT mul_temp_11(14))), 14), 16);
mul_temp_12 <= data_pipeline(12) * weight(12);
filter_products(12) <= resize(shift_right(mul_temp_12(29 DOWNTO 0) + ( "0" & (mul_temp_12(14) & NOT mul_temp_12(14) & NOT mul_temp_12(14) & NOT mul_temp_12(14) & NOT mul_temp_12(14) & NOT mul_temp_12(14) & NOT mul_temp_12(14) & NOT mul_temp_12(14) & NOT mul_temp_12(14) & NOT mul_temp_12(14) & NOT mul_temp_12(14) & NOT mul_temp_12(14) & NOT mul_temp_12(14) & NOT mul_temp_12(14))), 14), 16);
mul_temp_13 <= data_pipeline(13) * weight(13);
filter_products(13) <= resize(shift_right(mul_temp_13(29 DOWNTO 0) + ( "0" & (mul_temp_13(14) & NOT mul_temp_13(14) & NOT mul_temp_13(14) & NOT mul_temp_13(14) & NOT mul_temp_13(14) & NOT mul_temp_13(14) & NOT mul_temp_13(14) & NOT mul_temp_13(14) & NOT mul_temp_13(14) & NOT mul_temp_13(14) & NOT mul_temp_13(14) & NOT mul_temp_13(14) & NOT mul_temp_13(14) & NOT mul_temp_13(14))), 14), 16);
mul_temp_14 <= data_pipeline(14) * weight(14);
filter_products(14) <= resize(shift_right(mul_temp_14(29 DOWNTO 0) + ( "0" & (mul_temp_14(14) & NOT mul_temp_14(14) & NOT mul_temp_14(14) & NOT mul_temp_14(14) & NOT mul_temp_14(14) & NOT mul_temp_14(14) & NOT mul_temp_14(14) & NOT mul_temp_14(14) & NOT mul_temp_14(14) & NOT mul_temp_14(14) & NOT mul_temp_14(14) & NOT mul_temp_14(14) & NOT mul_temp_14(14) & NOT mul_temp_14(14))), 14), 16);
mul_temp_15 <= data_pipeline(15) * weight(15);
filter_products(15) <= resize(shift_right(mul_temp_15(29 DOWNTO 0) + ( "0" & (mul_temp_15(14) & NOT mul_temp_15(14) & NOT mul_temp_15(14) & NOT mul_temp_15(14) & NOT mul_temp_15(14) & NOT mul_temp_15(14) & NOT mul_temp_15(14) & NOT mul_temp_15(14) & NOT mul_temp_15(14) & NOT mul_temp_15(14) & NOT mul_temp_15(14) & NOT mul_temp_15(14) & NOT mul_temp_15(14) & NOT mul_temp_15(14))), 14), 16);
-- linear sum of filter products
add_cast <= filter_products(0);
add_cast_1 <= filter_products(1);
add_temp <= resize(add_cast, 17) + resize(add_cast_1, 17);
sum_1 <= add_temp(15 DOWNTO 0);
add_cast_2 <= sum_1;
add_cast_3 <= filter_products(2);
add_temp_1 <= resize(add_cast_2, 17) + resize(add_cast_3, 17);
sum_2 <= add_temp_1(15 DOWNTO 0);
add_cast_4 <= sum_2;
add_cast_5 <= filter_products(3);
add_temp_2 <= resize(add_cast_4, 17) + resize(add_cast_5, 17);
sum_3 <= add_temp_2(15 DOWNTO 0);
add_cast_6 <= sum_3;
add_cast_7 <= filter_products(4);
add_temp_3 <= resize(add_cast_6, 17) + resize(add_cast_7, 17);
sum_4 <= add_temp_3(15 DOWNTO 0);
add_cast_8 <= sum_4;
add_cast_9 <= filter_products(5);
add_temp_4 <= resize(add_cast_8, 17) + resize(add_cast_9, 17);
sum_5 <= add_temp_4(15 DOWNTO 0);
add_cast_10 <= sum_5;
add_cast_11 <= filter_products(6);
add_temp_5 <= resize(add_cast_10, 17) + resize(add_cast_11, 17);
sum_6 <= add_temp_5(15 DOWNTO 0);
add_cast_12 <= sum_6;
add_cast_13 <= filter_products(7);
add_temp_6 <= resize(add_cast_12, 17) + resize(add_cast_13, 17);
sum_7 <= add_temp_6(15 DOWNTO 0);
add_cast_14 <= sum_7;
add_cast_15 <= filter_products(8);
add_temp_7 <= resize(add_cast_14, 17) + resize(add_cast_15, 17);
sum_8 <= add_temp_7(15 DOWNTO 0);
add_cast_16 <= sum_8;
add_cast_17 <= filter_products(9);
add_temp_8 <= resize(add_cast_16, 17) + resize(add_cast_17, 17);
sum_9 <= add_temp_8(15 DOWNTO 0);
add_cast_18 <= sum_9;
add_cast_19 <= filter_products(10);
add_temp_9 <= resize(add_cast_18, 17) + resize(add_cast_19, 17);
sum_10 <= add_temp_9(15 DOWNTO 0);
add_cast_20 <= sum_10;
add_cast_21 <= filter_products(11);
add_temp_10 <= resize(add_cast_20, 17) + resize(add_cast_21, 17);
sum_11 <= add_temp_10(15 DOWNTO 0);
add_cast_22 <= sum_11;
add_cast_23 <= filter_products(12);
add_temp_11 <= resize(add_cast_22, 17) + resize(add_cast_23, 17);
sum_12 <= add_temp_11(15 DOWNTO 0);
add_cast_24 <= sum_12;
add_cast_25 <= filter_products(13);
add_temp_12 <= resize(add_cast_24, 17) + resize(add_cast_25, 17);
sum_13 <= add_temp_12(15 DOWNTO 0);
add_cast_26 <= sum_13;
add_cast_27 <= filter_products(14);
add_temp_13 <= resize(add_cast_26, 17) + resize(add_cast_27, 17);
sum_14 <= add_temp_13(15 DOWNTO 0);
add_cast_28 <= sum_14;
add_cast_29 <= filter_products(15);
add_temp_14 <= resize(add_cast_28, 17) + resize(add_cast_29, 17);
filter_sum <= add_temp_14(15 DOWNTO 0);
LMS_Filter_out1 <= filter_sum;
-- * Calculate Filter Error
sub_cast <= d_k_signed;
sub_cast_1 <= filter_sum;
sub_temp <= resize(sub_cast, 17) - resize(sub_cast_1, 17);
LMS_Filter_out2 <= sub_temp(15 DOWNTO 0);
-- ***** LMS Weight Update Function *****
mul_temp_16 <= C_LMS_FILTER_STEP_SIZE * LMS_Filter_out2;
mu_err <= resize(shift_right(mul_temp_16(31) & mul_temp_16(31 DOWNTO 0) + ( "0" & (mul_temp_16(17) & NOT mul_temp_16(17) & NOT mul_temp_16(17) & NOT mul_temp_16(17) & NOT mul_temp_16(17) & NOT mul_temp_16(17) & NOT mul_temp_16(17) & NOT mul_temp_16(17) & NOT mul_temp_16(17) & NOT mul_temp_16(17) & NOT mul_temp_16(17) & NOT mul_temp_16(17) & NOT mul_temp_16(17) & NOT mul_temp_16(17) & NOT mul_temp_16(17) & NOT mul_temp_16(17) & NOT mul_temp_16(17))), 17), 16);
mul_temp_17 <= data_pipeline(0) * mu_err;
mu_err_data_prod(0) <= resize(shift_right(mul_temp_17(29 DOWNTO 0) + ( "0" & (mul_temp_17(14) & NOT mul_temp_17(14) & NOT mul_temp_17(14) & NOT mul_temp_17(14) & NOT mul_temp_17(14) & NOT mul_temp_17(14) & NOT mul_temp_17(14) & NOT mul_temp_17(14) & NOT mul_temp_17(14) & NOT mul_temp_17(14) & NOT mul_temp_17(14) & NOT mul_temp_17(14) & NOT mul_temp_17(14) & NOT mul_temp_17(14))), 14), 16);
mul_temp_18 <= data_pipeline(1) * mu_err;
mu_err_data_prod(1) <= resize(shift_right(mul_temp_18(29 DOWNTO 0) + ( "0" & (mul_temp_18(14) & NOT mul_temp_18(14) & NOT mul_temp_18(14) & NOT mul_temp_18(14) & NOT mul_temp_18(14) & NOT mul_temp_18(14) & NOT mul_temp_18(14) & NOT mul_temp_18(14) & NOT mul_temp_18(14) & NOT mul_temp_18(14) & NOT mul_temp_18(14) & NOT mul_temp_18(14) & NOT mul_temp_18(14) & NOT mul_temp_18(14))), 14), 16);
mul_temp_19 <= data_pipeline(2) * mu_err;
mu_err_data_prod(2) <= resize(shift_right(mul_temp_19(29 DOWNTO 0) + ( "0" & (mul_temp_19(14) & NOT mul_temp_19(14) & NOT mul_temp_19(14) & NOT mul_temp_19(14) & NOT mul_temp_19(14) & NOT mul_temp_19(14) & NOT mul_temp_19(14) & NOT mul_temp_19(14) & NOT mul_temp_19(14) & NOT mul_temp_19(14) & NOT mul_temp_19(14) & NOT mul_temp_19(14) & NOT mul_temp_19(14) & NOT mul_temp_19(14))), 14), 16);
mul_temp_20 <= data_pipeline(3) * mu_err;
mu_err_data_prod(3) <= resize(shift_right(mul_temp_20(29 DOWNTO 0) + ( "0" & (mul_temp_20(14) & NOT mul_temp_20(14) & NOT mul_temp_20(14) & NOT mul_temp_20(14) & NOT mul_temp_20(14) & NOT mul_temp_20(14) & NOT mul_temp_20(14) & NOT mul_temp_20(14) & NOT mul_temp_20(14) & NOT mul_temp_20(14) & NOT mul_temp_20(14) & NOT mul_temp_20(14) & NOT mul_temp_20(14) & NOT mul_temp_20(14))), 14), 16);
mul_temp_21 <= data_pipeline(4) * mu_err;
mu_err_data_prod(4) <= resize(shift_right(mul_temp_21(29 DOWNTO 0) + ( "0" & (mul_temp_21(14) & NOT mul_temp_21(14) & NOT mul_temp_21(14) & NOT mul_temp_21(14) & NOT mul_temp_21(14) & NOT mul_temp_21(14) & NOT mul_temp_21(14) & NOT mul_temp_21(14) & NOT mul_temp_21(14) & NOT mul_temp_21(14) & NOT mul_temp_21(14) & NOT mul_temp_21(14) & NOT mul_temp_21(14) & NOT mul_temp_21(14))), 14), 16);
mul_temp_22 <= data_pipeline(5) * mu_err;
mu_err_data_prod(5) <= resize(shift_right(mul_temp_22(29 DOWNTO 0) + ( "0" & (mul_temp_22(14) & NOT mul_temp_22(14) & NOT mul_temp_22(14) & NOT mul_temp_22(14) & NOT mul_temp_22(14) & NOT mul_temp_22(14) & NOT mul_temp_22(14) & NOT mul_temp_22(14) & NOT mul_temp_22(14) & NOT mul_temp_22(14) & NOT mul_temp_22(14) & NOT mul_temp_22(14) & NOT mul_temp_22(14) & NOT mul_temp_22(14))), 14), 16);
mul_temp_23 <= data_pipeline(6) * mu_err;
mu_err_data_prod(6) <= resize(shift_right(mul_temp_23(29 DOWNTO 0) + ( "0" & (mul_temp_23(14) & NOT mul_temp_23(14) & NOT mul_temp_23(14) & NOT mul_temp_23(14) & NOT mul_temp_23(14) & NOT mul_temp_23(14) & NOT mul_temp_23(14) & NOT mul_temp_23(14) & NOT mul_temp_23(14) & NOT mul_temp_23(14) & NOT mul_temp_23(14) & NOT mul_temp_23(14) & NOT mul_temp_23(14) & NOT mul_temp_23(14))), 14), 16);
mul_temp_24 <= data_pipeline(7) * mu_err;
mu_err_data_prod(7) <= resize(shift_right(mul_temp_24(29 DOWNTO 0) + ( "0" & (mul_temp_24(14) & NOT mul_temp_24(14) & NOT mul_temp_24(14) & NOT mul_temp_24(14) & NOT mul_temp_24(14) & NOT mul_temp_24(14) & NOT mul_temp_24(14) & NOT mul_temp_24(14) & NOT mul_temp_24(14) & NOT mul_temp_24(14) & NOT mul_temp_24(14) & NOT mul_temp_24(14) & NOT mul_temp_24(14) & NOT mul_temp_24(14))), 14), 16);
mul_temp_25 <= data_pipeline(8) * mu_err;
mu_err_data_prod(8) <= resize(shift_right(mul_temp_25(29 DOWNTO 0) + ( "0" & (mul_temp_25(14) & NOT mul_temp_25(14) & NOT mul_temp_25(14) & NOT mul_temp_25(14) & NOT mul_temp_25(14) & NOT mul_temp_25(14) & NOT mul_temp_25(14) & NOT mul_temp_25(14) & NOT mul_temp_25(14) & NOT mul_temp_25(14) & NOT mul_temp_25(14) & NOT mul_temp_25(14) & NOT mul_temp_25(14) & NOT mul_temp_25(14))), 14), 16);
mul_temp_26 <= data_pipeline(9) * mu_err;
mu_err_data_prod(9) <= resize(shift_right(mul_temp_26(29 DOWNTO 0) + ( "0" & (mul_temp_26(14) & NOT mul_temp_26(14) & NOT mul_temp_26(14) & NOT mul_temp_26(14) & NOT mul_temp_26(14) & NOT mul_temp_26(14) & NOT mul_temp_26(14) & NOT mul_temp_26(14) & NOT mul_temp_26(14) & NOT mul_temp_26(14) & NOT mul_temp_26(14) & NOT mul_temp_26(14) & NOT mul_temp_26(14) & NOT mul_temp_26(14))), 14), 16);
mul_temp_27 <= data_pipeline(10) * mu_err;
mu_err_data_prod(10) <= resize(shift_right(mul_temp_27(29 DOWNTO 0) + ( "0" & (mul_temp_27(14) & NOT mul_temp_27(14) & NOT mul_temp_27(14) & NOT mul_temp_27(14) & NOT mul_temp_27(14) & NOT mul_temp_27(14) & NOT mul_temp_27(14) & NOT mul_temp_27(14) & NOT mul_temp_27(14) & NOT mul_temp_27(14) & NOT mul_temp_27(14) & NOT mul_temp_27(14) & NOT mul_temp_27(14) & NOT mul_temp_27(14))), 14), 16);
mul_temp_28 <= data_pipeline(11) * mu_err;
mu_err_data_prod(11) <= resize(shift_right(mul_temp_28(29 DOWNTO 0) + ( "0" & (mul_temp_28(14) & NOT mul_temp_28(14) & NOT mul_temp_28(14) & NOT mul_temp_28(14) & NOT mul_temp_28(14) & NOT mul_temp_28(14) & NOT mul_temp_28(14) & NOT mul_temp_28(14) & NOT mul_temp_28(14) & NOT mul_temp_28(14) & NOT mul_temp_28(14) & NOT mul_temp_28(14) & NOT mul_temp_28(14) & NOT mul_temp_28(14))), 14), 16);
mul_temp_29 <= data_pipeline(12) * mu_err;
mu_err_data_prod(12) <= resize(shift_right(mul_temp_29(29 DOWNTO 0) + ( "0" & (mul_temp_29(14) & NOT mul_temp_29(14) & NOT mul_temp_29(14) & NOT mul_temp_29(14) & NOT mul_temp_29(14) & NOT mul_temp_29(14) & NOT mul_temp_29(14) & NOT mul_temp_29(14) & NOT mul_temp_29(14) & NOT mul_temp_29(14) & NOT mul_temp_29(14) & NOT mul_temp_29(14) & NOT mul_temp_29(14) & NOT mul_temp_29(14))), 14), 16);
mul_temp_30 <= data_pipeline(13) * mu_err;
mu_err_data_prod(13) <= resize(shift_right(mul_temp_30(29 DOWNTO 0) + ( "0" & (mul_temp_30(14) & NOT mul_temp_30(14) & NOT mul_temp_30(14) & NOT mul_temp_30(14) & NOT mul_temp_30(14) & NOT mul_temp_30(14) & NOT mul_temp_30(14) & NOT mul_temp_30(14) & NOT mul_temp_30(14) & NOT mul_temp_30(14) & NOT mul_temp_30(14) & NOT mul_temp_30(14) & NOT mul_temp_30(14) & NOT mul_temp_30(14))), 14), 16);
mul_temp_31 <= data_pipeline(14) * mu_err;
mu_err_data_prod(14) <= resize(shift_right(mul_temp_31(29 DOWNTO 0) + ( "0" & (mul_temp_31(14) & NOT mul_temp_31(14) & NOT mul_temp_31(14) & NOT mul_temp_31(14) & NOT mul_temp_31(14) & NOT mul_temp_31(14) & NOT mul_temp_31(14) & NOT mul_temp_31(14) & NOT mul_temp_31(14) & NOT mul_temp_31(14) & NOT mul_temp_31(14) & NOT mul_temp_31(14) & NOT mul_temp_31(14) & NOT mul_temp_31(14))), 14), 16);
mul_temp_32 <= data_pipeline(15) * mu_err;
mu_err_data_prod(15) <= resize(shift_right(mul_temp_32(29 DOWNTO 0) + ( "0" & (mul_temp_32(14) & NOT mul_temp_32(14) & NOT mul_temp_32(14) & NOT mul_temp_32(14) & NOT mul_temp_32(14) & NOT mul_temp_32(14) & NOT mul_temp_32(14) & NOT mul_temp_32(14) & NOT mul_temp_32(14) & NOT mul_temp_32(14) & NOT mul_temp_32(14) & NOT mul_temp_32(14) & NOT mul_temp_32(14) & NOT mul_temp_32(14))), 14), 16);
-- * LMS_Filter Weight Accumulator
add_cast_30 <= weight(0);
add_cast_31 <= mu_err_data_prod(0);
add_temp_15 <= resize(add_cast_30, 17) + resize(add_cast_31, 17);
weight_adder_output(0) <= add_temp_15(15 DOWNTO 0);
add_cast_32 <= weight(1);
add_cast_33 <= mu_err_data_prod(1);
add_temp_16 <= resize(add_cast_32, 17) + resize(add_cast_33, 17);
weight_adder_output(1) <= add_temp_16(15 DOWNTO 0);
add_cast_34 <= weight(2);
add_cast_35 <= mu_err_data_prod(2);
add_temp_17 <= resize(add_cast_34, 17) + resize(add_cast_35, 17);
weight_adder_output(2) <= add_temp_17(15 DOWNTO 0);
add_cast_36 <= weight(3);
add_cast_37 <= mu_err_data_prod(3);
add_temp_18 <= resize(add_cast_36, 17) + resize(add_cast_37, 17);
weight_adder_output(3) <= add_temp_18(15 DOWNTO 0);
add_cast_38 <= weight(4);
add_cast_39 <= mu_err_data_prod(4);
add_temp_19 <= resize(add_cast_38, 17) + resize(add_cast_39, 17);
weight_adder_output(4) <= add_temp_19(15 DOWNTO 0);
add_cast_40 <= weight(5);
add_cast_41 <= mu_err_data_prod(5);
add_temp_20 <= resize(add_cast_40, 17) + resize(add_cast_41, 17);
weight_adder_output(5) <= add_temp_20(15 DOWNTO 0);
add_cast_42 <= weight(6);
add_cast_43 <= mu_err_data_prod(6);
add_temp_21 <= resize(add_cast_42, 17) + resize(add_cast_43, 17);
weight_adder_output(6) <= add_temp_21(15 DOWNTO 0);
add_cast_44 <= weight(7);
add_cast_45 <= mu_err_data_prod(7);
add_temp_22 <= resize(add_cast_44, 17) + resize(add_cast_45, 17);
weight_adder_output(7) <= add_temp_22(15 DOWNTO 0);
add_cast_46 <= weight(8);
add_cast_47 <= mu_err_data_prod(8);
add_temp_23 <= resize(add_cast_46, 17) + resize(add_cast_47, 17);
weight_adder_output(8) <= add_temp_23(15 DOWNTO 0);
add_cast_48 <= weight(9);
add_cast_49 <= mu_err_data_prod(9);
add_temp_24 <= resize(add_cast_48, 17) + resize(add_cast_49, 17);
weight_adder_output(9) <= add_temp_24(15 DOWNTO 0);
add_cast_50 <= weight(10);
add_cast_51 <= mu_err_data_prod(10);
add_temp_25 <= resize(add_cast_50, 17) + resize(add_cast_51, 17);
weight_adder_output(10) <= add_temp_25(15 DOWNTO 0);
add_cast_52 <= weight(11);
add_cast_53 <= mu_err_data_prod(11);
add_temp_26 <= resize(add_cast_52, 17) + resize(add_cast_53, 17);
weight_adder_output(11) <= add_temp_26(15 DOWNTO 0);
add_cast_54 <= weight(12);
add_cast_55 <= mu_err_data_prod(12);
add_temp_27 <= resize(add_cast_54, 17) + resize(add_cast_55, 17);
weight_adder_output(12) <= add_temp_27(15 DOWNTO 0);
add_cast_56 <= weight(13);
add_cast_57 <= mu_err_data_prod(13);
add_temp_28 <= resize(add_cast_56, 17) + resize(add_cast_57, 17);
weight_adder_output(13) <= add_temp_28(15 DOWNTO 0);
add_cast_58 <= weight(14);
add_cast_59 <= mu_err_data_prod(14);
add_temp_29 <= resize(add_cast_58, 17) + resize(add_cast_59, 17);
weight_adder_output(14) <= add_temp_29(15 DOWNTO 0);
add_cast_60 <= weight(15);
add_cast_61 <= mu_err_data_prod(15);
add_temp_30 <= resize(add_cast_60, 17) + resize(add_cast_61, 17);
weight_adder_output(15) <= add_temp_30(15 DOWNTO 0);
LMS_Filter_acc_temp_process2 : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
weight <= (OTHERS => (OTHERS => '0'));
ELSIF clk'event AND clk = '1' THEN
IF enb = '1' THEN
weight(0 TO 15) <= weight_adder_output(0 TO 15);
END IF;
END IF;
END PROCESS LMS_Filter_acc_temp_process2;
e_k <= std_logic_vector(LMS_Filter_out2);
ce_out <= clk_enable;
END rtl;
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj\hdlsrc\lms\LMS.vhd
-- Created: 2015-06-19 16:39:42
--
-- Generated by MATLAB 8.5 and HDL Coder 3.6
--
--
-- -------------------------------------------------------------
-- Rate and Clocking Details
-- -------------------------------------------------------------
-- Model base rate: 2.26757e-05
-- Target subsystem base rate: 2.26757e-05
--
--
-- Clock Enable Sample Time
-- -------------------------------------------------------------
-- ce_out 2.26757e-05
-- -------------------------------------------------------------
--
--
-- Output Signal Clock Enable Sample Time
-- -------------------------------------------------------------
-- e_k ce_out 2.26757e-05
-- -------------------------------------------------------------
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: LMS
-- Source Path: lms/LMS
-- Hierarchy Level: 0
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.LMS_pkg.ALL;
ENTITY LMS IS
PORT( clk : IN std_logic;
reset : IN std_logic;
clk_enable : IN std_logic;
x_k : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
d_k : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En14
ce_out : OUT std_logic;
e_k : OUT std_logic_vector(15 DOWNTO 0) -- sfix16_En14
);
END LMS;
ARCHITECTURE rtl OF LMS IS
-- Constants
CONSTANT C_LMS_FILTER_STEP_SIZE : signed(15 DOWNTO 0) := "0100000000000000"; -- sfix16_En17
-- Signals
SIGNAL enb : std_logic;
SIGNAL x_k_signed : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL d_k_signed : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL LMS_Filter_out1 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL LMS_Filter_out2 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL weight : vector_of_signed16(0 TO 15); -- sfix16_En14 [16]
SIGNAL filter_sum : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL data_pipeline : vector_of_signed16(0 TO 15); -- sfix16_En14 [16]
SIGNAL data_pipeline_tmp : vector_of_signed16(0 TO 14); -- sfix16_En14 [15]
SIGNAL filter_products : vector_of_signed16(0 TO 15); -- sfix16_En14 [16]
SIGNAL mul_temp : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_1 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_2 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_3 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_4 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_5 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_6 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_7 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_8 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_9 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_10 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_11 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_12 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_13 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_14 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_15 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL sum_1 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_1 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL sum_2 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_2 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_3 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_1 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL sum_3 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_4 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_5 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_2 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL sum_4 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_6 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_7 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_3 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL sum_5 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_8 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_9 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_4 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL sum_6 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_10 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_11 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_5 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL sum_7 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_12 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_13 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_6 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL sum_8 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_14 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_15 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_7 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL sum_9 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_16 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_17 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_8 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL sum_10 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_18 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_19 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_9 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL sum_11 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_20 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_21 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_10 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL sum_12 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_22 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_23 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_11 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL sum_13 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_24 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_25 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_12 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL sum_14 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_26 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_27 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_13 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL add_cast_28 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_29 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_14 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL sub_cast : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL sub_cast_1 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL sub_temp : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL mu_err : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL mul_temp_16 : signed(31 DOWNTO 0); -- sfix32_En31
SIGNAL mu_err_data_prod : vector_of_signed16(0 TO 15); -- sfix16_En14 [16]
SIGNAL mul_temp_17 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_18 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_19 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_20 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_21 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_22 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_23 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_24 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_25 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_26 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_27 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_28 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_29 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_30 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_31 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL mul_temp_32 : signed(31 DOWNTO 0); -- sfix32_En28
SIGNAL weight_adder_output : vector_of_signed16(0 TO 15); -- sfix16_En14 [16]
SIGNAL add_cast_30 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_31 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_15 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL add_cast_32 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_33 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_16 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL add_cast_34 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_35 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_17 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL add_cast_36 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_37 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_18 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL add_cast_38 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_39 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_19 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL add_cast_40 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_41 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_20 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL add_cast_42 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_43 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_21 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL add_cast_44 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_45 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_22 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL add_cast_46 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_47 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_23 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL add_cast_48 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_49 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_24 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL add_cast_50 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_51 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_25 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL add_cast_52 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_53 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_26 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL add_cast_54 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_55 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_27 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL add_cast_56 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_57 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_28 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL add_cast_58 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_59 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_29 : signed(16 DOWNTO 0); -- sfix17_En14
SIGNAL add_cast_60 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_cast_61 : signed(15 DOWNTO 0); -- sfix16_En14
SIGNAL add_temp_30 : signed(16 DOWNTO 0); -- sfix17_En14
BEGIN
x_k_signed <= signed(x_k);
d_k_signed <= signed(d_k);
enb <= clk_enable;
-- ***********************
-- ********* LMS *********
-- ***********************
-- * LMS: FIR section
LMS_Filter_del_temp_process1 : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
data_pipeline_tmp <= (OTHERS => (OTHERS => '0'));
ELSIF clk'event AND clk = '1' THEN
IF enb = '1' THEN
data_pipeline_tmp(0 TO 13) <= data_pipeline_tmp(1 TO 14);
data_pipeline_tmp(14) <= x_k_signed;
END IF;
END IF;
END PROCESS LMS_Filter_del_temp_process1;
data_pipeline(0 TO 14) <= data_pipeline_tmp(0 TO 14);
data_pipeline(15) <= x_k_signed;
mul_temp <= data_pipeline(0) * weight(0);
filter_products(0) <= resize(shift_right(mul_temp(29 DOWNTO 0) + ( "0" & (mul_temp(14) & NOT mul_temp(14) & NOT mul_temp(14) & NOT mul_temp(14) & NOT mul_temp(14) & NOT mul_temp(14) & NOT mul_temp(14) & NOT mul_temp(14) & NOT mul_temp(14) & NOT mul_temp(14) & NOT mul_temp(14) & NOT mul_temp(14) & NOT mul_temp(14) & NOT mul_temp(14))), 14), 16);
mul_temp_1 <= data_pipeline(1) * weight(1);
filter_products(1) <= resize(shift_right(mul_temp_1(29 DOWNTO 0) + ( "0" & (mul_temp_1(14) & NOT mul_temp_1(14) & NOT mul_temp_1(14) & NOT mul_temp_1(14) & NOT mul_temp_1(14) & NOT mul_temp_1(14) & NOT mul_temp_1(14) & NOT mul_temp_1(14) & NOT mul_temp_1(14) & NOT mul_temp_1(14) & NOT mul_temp_1(14) & NOT mul_temp_1(14) & NOT mul_temp_1(14) & NOT mul_temp_1(14))), 14), 16);
mul_temp_2 <= data_pipeline(2) * weight(2);
filter_products(2) <= resize(shift_right(mul_temp_2(29 DOWNTO 0) + ( "0" & (mul_temp_2(14) & NOT mul_temp_2(14) & NOT mul_temp_2(14) & NOT mul_temp_2(14) & NOT mul_temp_2(14) & NOT mul_temp_2(14) & NOT mul_temp_2(14) & NOT mul_temp_2(14) & NOT mul_temp_2(14) & NOT mul_temp_2(14) & NOT mul_temp_2(14) & NOT mul_temp_2(14) & NOT mul_temp_2(14) & NOT mul_temp_2(14))), 14), 16);
mul_temp_3 <= data_pipeline(3) * weight(3);
filter_products(3) <= resize(shift_right(mul_temp_3(29 DOWNTO 0) + ( "0" & (mul_temp_3(14) & NOT mul_temp_3(14) & NOT mul_temp_3(14) & NOT mul_temp_3(14) & NOT mul_temp_3(14) & NOT mul_temp_3(14) & NOT mul_temp_3(14) & NOT mul_temp_3(14) & NOT mul_temp_3(14) & NOT mul_temp_3(14) & NOT mul_temp_3(14) & NOT mul_temp_3(14) & NOT mul_temp_3(14) & NOT mul_temp_3(14))), 14), 16);
mul_temp_4 <= data_pipeline(4) * weight(4);
filter_products(4) <= resize(shift_right(mul_temp_4(29 DOWNTO 0) + ( "0" & (mul_temp_4(14) & NOT mul_temp_4(14) & NOT mul_temp_4(14) & NOT mul_temp_4(14) & NOT mul_temp_4(14) & NOT mul_temp_4(14) & NOT mul_temp_4(14) & NOT mul_temp_4(14) & NOT mul_temp_4(14) & NOT mul_temp_4(14) & NOT mul_temp_4(14) & NOT mul_temp_4(14) & NOT mul_temp_4(14) & NOT mul_temp_4(14))), 14), 16);
mul_temp_5 <= data_pipeline(5) * weight(5);
filter_products(5) <= resize(shift_right(mul_temp_5(29 DOWNTO 0) + ( "0" & (mul_temp_5(14) & NOT mul_temp_5(14) & NOT mul_temp_5(14) & NOT mul_temp_5(14) & NOT mul_temp_5(14) & NOT mul_temp_5(14) & NOT mul_temp_5(14) & NOT mul_temp_5(14) & NOT mul_temp_5(14) & NOT mul_temp_5(14) & NOT mul_temp_5(14) & NOT mul_temp_5(14) & NOT mul_temp_5(14) & NOT mul_temp_5(14))), 14), 16);
mul_temp_6 <= data_pipeline(6) * weight(6);
filter_products(6) <= resize(shift_right(mul_temp_6(29 DOWNTO 0) + ( "0" & (mul_temp_6(14) & NOT mul_temp_6(14) & NOT mul_temp_6(14) & NOT mul_temp_6(14) & NOT mul_temp_6(14) & NOT mul_temp_6(14) & NOT mul_temp_6(14) & NOT mul_temp_6(14) & NOT mul_temp_6(14) & NOT mul_temp_6(14) & NOT mul_temp_6(14) & NOT mul_temp_6(14) & NOT mul_temp_6(14) & NOT mul_temp_6(14))), 14), 16);
mul_temp_7 <= data_pipeline(7) * weight(7);
filter_products(7) <= resize(shift_right(mul_temp_7(29 DOWNTO 0) + ( "0" & (mul_temp_7(14) & NOT mul_temp_7(14) & NOT mul_temp_7(14) & NOT mul_temp_7(14) & NOT mul_temp_7(14) & NOT mul_temp_7(14) & NOT mul_temp_7(14) & NOT mul_temp_7(14) & NOT mul_temp_7(14) & NOT mul_temp_7(14) & NOT mul_temp_7(14) & NOT mul_temp_7(14) & NOT mul_temp_7(14) & NOT mul_temp_7(14))), 14), 16);
mul_temp_8 <= data_pipeline(8) * weight(8);
filter_products(8) <= resize(shift_right(mul_temp_8(29 DOWNTO 0) + ( "0" & (mul_temp_8(14) & NOT mul_temp_8(14) & NOT mul_temp_8(14) & NOT mul_temp_8(14) & NOT mul_temp_8(14) & NOT mul_temp_8(14) & NOT mul_temp_8(14) & NOT mul_temp_8(14) & NOT mul_temp_8(14) & NOT mul_temp_8(14) & NOT mul_temp_8(14) & NOT mul_temp_8(14) & NOT mul_temp_8(14) & NOT mul_temp_8(14))), 14), 16);
mul_temp_9 <= data_pipeline(9) * weight(9);
filter_products(9) <= resize(shift_right(mul_temp_9(29 DOWNTO 0) + ( "0" & (mul_temp_9(14) & NOT mul_temp_9(14) & NOT mul_temp_9(14) & NOT mul_temp_9(14) & NOT mul_temp_9(14) & NOT mul_temp_9(14) & NOT mul_temp_9(14) & NOT mul_temp_9(14) & NOT mul_temp_9(14) & NOT mul_temp_9(14) & NOT mul_temp_9(14) & NOT mul_temp_9(14) & NOT mul_temp_9(14) & NOT mul_temp_9(14))), 14), 16);
mul_temp_10 <= data_pipeline(10) * weight(10);
filter_products(10) <= resize(shift_right(mul_temp_10(29 DOWNTO 0) + ( "0" & (mul_temp_10(14) & NOT mul_temp_10(14) & NOT mul_temp_10(14) & NOT mul_temp_10(14) & NOT mul_temp_10(14) & NOT mul_temp_10(14) & NOT mul_temp_10(14) & NOT mul_temp_10(14) & NOT mul_temp_10(14) & NOT mul_temp_10(14) & NOT mul_temp_10(14) & NOT mul_temp_10(14) & NOT mul_temp_10(14) & NOT mul_temp_10(14))), 14), 16);
mul_temp_11 <= data_pipeline(11) * weight(11);
filter_products(11) <= resize(shift_right(mul_temp_11(29 DOWNTO 0) + ( "0" & (mul_temp_11(14) & NOT mul_temp_11(14) & NOT mul_temp_11(14) & NOT mul_temp_11(14) & NOT mul_temp_11(14) & NOT mul_temp_11(14) & NOT mul_temp_11(14) & NOT mul_temp_11(14) & NOT mul_temp_11(14) & NOT mul_temp_11(14) & NOT mul_temp_11(14) & NOT mul_temp_11(14) & NOT mul_temp_11(14) & NOT mul_temp_11(14))), 14), 16);
mul_temp_12 <= data_pipeline(12) * weight(12);
filter_products(12) <= resize(shift_right(mul_temp_12(29 DOWNTO 0) + ( "0" & (mul_temp_12(14) & NOT mul_temp_12(14) & NOT mul_temp_12(14) & NOT mul_temp_12(14) & NOT mul_temp_12(14) & NOT mul_temp_12(14) & NOT mul_temp_12(14) & NOT mul_temp_12(14) & NOT mul_temp_12(14) & NOT mul_temp_12(14) & NOT mul_temp_12(14) & NOT mul_temp_12(14) & NOT mul_temp_12(14) & NOT mul_temp_12(14))), 14), 16);
mul_temp_13 <= data_pipeline(13) * weight(13);
filter_products(13) <= resize(shift_right(mul_temp_13(29 DOWNTO 0) + ( "0" & (mul_temp_13(14) & NOT mul_temp_13(14) & NOT mul_temp_13(14) & NOT mul_temp_13(14) & NOT mul_temp_13(14) & NOT mul_temp_13(14) & NOT mul_temp_13(14) & NOT mul_temp_13(14) & NOT mul_temp_13(14) & NOT mul_temp_13(14) & NOT mul_temp_13(14) & NOT mul_temp_13(14) & NOT mul_temp_13(14) & NOT mul_temp_13(14))), 14), 16);
mul_temp_14 <= data_pipeline(14) * weight(14);
filter_products(14) <= resize(shift_right(mul_temp_14(29 DOWNTO 0) + ( "0" & (mul_temp_14(14) & NOT mul_temp_14(14) & NOT mul_temp_14(14) & NOT mul_temp_14(14) & NOT mul_temp_14(14) & NOT mul_temp_14(14) & NOT mul_temp_14(14) & NOT mul_temp_14(14) & NOT mul_temp_14(14) & NOT mul_temp_14(14) & NOT mul_temp_14(14) & NOT mul_temp_14(14) & NOT mul_temp_14(14) & NOT mul_temp_14(14))), 14), 16);
mul_temp_15 <= data_pipeline(15) * weight(15);
filter_products(15) <= resize(shift_right(mul_temp_15(29 DOWNTO 0) + ( "0" & (mul_temp_15(14) & NOT mul_temp_15(14) & NOT mul_temp_15(14) & NOT mul_temp_15(14) & NOT mul_temp_15(14) & NOT mul_temp_15(14) & NOT mul_temp_15(14) & NOT mul_temp_15(14) & NOT mul_temp_15(14) & NOT mul_temp_15(14) & NOT mul_temp_15(14) & NOT mul_temp_15(14) & NOT mul_temp_15(14) & NOT mul_temp_15(14))), 14), 16);
-- linear sum of filter products
add_cast <= filter_products(0);
add_cast_1 <= filter_products(1);
add_temp <= resize(add_cast, 17) + resize(add_cast_1, 17);
sum_1 <= add_temp(15 DOWNTO 0);
add_cast_2 <= sum_1;
add_cast_3 <= filter_products(2);
add_temp_1 <= resize(add_cast_2, 17) + resize(add_cast_3, 17);
sum_2 <= add_temp_1(15 DOWNTO 0);
add_cast_4 <= sum_2;
add_cast_5 <= filter_products(3);
add_temp_2 <= resize(add_cast_4, 17) + resize(add_cast_5, 17);
sum_3 <= add_temp_2(15 DOWNTO 0);
add_cast_6 <= sum_3;
add_cast_7 <= filter_products(4);
add_temp_3 <= resize(add_cast_6, 17) + resize(add_cast_7, 17);
sum_4 <= add_temp_3(15 DOWNTO 0);
add_cast_8 <= sum_4;
add_cast_9 <= filter_products(5);
add_temp_4 <= resize(add_cast_8, 17) + resize(add_cast_9, 17);
sum_5 <= add_temp_4(15 DOWNTO 0);
add_cast_10 <= sum_5;
add_cast_11 <= filter_products(6);
add_temp_5 <= resize(add_cast_10, 17) + resize(add_cast_11, 17);
sum_6 <= add_temp_5(15 DOWNTO 0);
add_cast_12 <= sum_6;
add_cast_13 <= filter_products(7);
add_temp_6 <= resize(add_cast_12, 17) + resize(add_cast_13, 17);
sum_7 <= add_temp_6(15 DOWNTO 0);
add_cast_14 <= sum_7;
add_cast_15 <= filter_products(8);
add_temp_7 <= resize(add_cast_14, 17) + resize(add_cast_15, 17);
sum_8 <= add_temp_7(15 DOWNTO 0);
add_cast_16 <= sum_8;
add_cast_17 <= filter_products(9);
add_temp_8 <= resize(add_cast_16, 17) + resize(add_cast_17, 17);
sum_9 <= add_temp_8(15 DOWNTO 0);
add_cast_18 <= sum_9;
add_cast_19 <= filter_products(10);
add_temp_9 <= resize(add_cast_18, 17) + resize(add_cast_19, 17);
sum_10 <= add_temp_9(15 DOWNTO 0);
add_cast_20 <= sum_10;
add_cast_21 <= filter_products(11);
add_temp_10 <= resize(add_cast_20, 17) + resize(add_cast_21, 17);
sum_11 <= add_temp_10(15 DOWNTO 0);
add_cast_22 <= sum_11;
add_cast_23 <= filter_products(12);
add_temp_11 <= resize(add_cast_22, 17) + resize(add_cast_23, 17);
sum_12 <= add_temp_11(15 DOWNTO 0);
add_cast_24 <= sum_12;
add_cast_25 <= filter_products(13);
add_temp_12 <= resize(add_cast_24, 17) + resize(add_cast_25, 17);
sum_13 <= add_temp_12(15 DOWNTO 0);
add_cast_26 <= sum_13;
add_cast_27 <= filter_products(14);
add_temp_13 <= resize(add_cast_26, 17) + resize(add_cast_27, 17);
sum_14 <= add_temp_13(15 DOWNTO 0);
add_cast_28 <= sum_14;
add_cast_29 <= filter_products(15);
add_temp_14 <= resize(add_cast_28, 17) + resize(add_cast_29, 17);
filter_sum <= add_temp_14(15 DOWNTO 0);
LMS_Filter_out1 <= filter_sum;
-- * Calculate Filter Error
sub_cast <= d_k_signed;
sub_cast_1 <= filter_sum;
sub_temp <= resize(sub_cast, 17) - resize(sub_cast_1, 17);
LMS_Filter_out2 <= sub_temp(15 DOWNTO 0);
-- ***** LMS Weight Update Function *****
mul_temp_16 <= C_LMS_FILTER_STEP_SIZE * LMS_Filter_out2;
mu_err <= resize(shift_right(mul_temp_16(31) & mul_temp_16(31 DOWNTO 0) + ( "0" & (mul_temp_16(17) & NOT mul_temp_16(17) & NOT mul_temp_16(17) & NOT mul_temp_16(17) & NOT mul_temp_16(17) & NOT mul_temp_16(17) & NOT mul_temp_16(17) & NOT mul_temp_16(17) & NOT mul_temp_16(17) & NOT mul_temp_16(17) & NOT mul_temp_16(17) & NOT mul_temp_16(17) & NOT mul_temp_16(17) & NOT mul_temp_16(17) & NOT mul_temp_16(17) & NOT mul_temp_16(17) & NOT mul_temp_16(17))), 17), 16);
mul_temp_17 <= data_pipeline(0) * mu_err;
mu_err_data_prod(0) <= resize(shift_right(mul_temp_17(29 DOWNTO 0) + ( "0" & (mul_temp_17(14) & NOT mul_temp_17(14) & NOT mul_temp_17(14) & NOT mul_temp_17(14) & NOT mul_temp_17(14) & NOT mul_temp_17(14) & NOT mul_temp_17(14) & NOT mul_temp_17(14) & NOT mul_temp_17(14) & NOT mul_temp_17(14) & NOT mul_temp_17(14) & NOT mul_temp_17(14) & NOT mul_temp_17(14) & NOT mul_temp_17(14))), 14), 16);
mul_temp_18 <= data_pipeline(1) * mu_err;
mu_err_data_prod(1) <= resize(shift_right(mul_temp_18(29 DOWNTO 0) + ( "0" & (mul_temp_18(14) & NOT mul_temp_18(14) & NOT mul_temp_18(14) & NOT mul_temp_18(14) & NOT mul_temp_18(14) & NOT mul_temp_18(14) & NOT mul_temp_18(14) & NOT mul_temp_18(14) & NOT mul_temp_18(14) & NOT mul_temp_18(14) & NOT mul_temp_18(14) & NOT mul_temp_18(14) & NOT mul_temp_18(14) & NOT mul_temp_18(14))), 14), 16);
mul_temp_19 <= data_pipeline(2) * mu_err;
mu_err_data_prod(2) <= resize(shift_right(mul_temp_19(29 DOWNTO 0) + ( "0" & (mul_temp_19(14) & NOT mul_temp_19(14) & NOT mul_temp_19(14) & NOT mul_temp_19(14) & NOT mul_temp_19(14) & NOT mul_temp_19(14) & NOT mul_temp_19(14) & NOT mul_temp_19(14) & NOT mul_temp_19(14) & NOT mul_temp_19(14) & NOT mul_temp_19(14) & NOT mul_temp_19(14) & NOT mul_temp_19(14) & NOT mul_temp_19(14))), 14), 16);
mul_temp_20 <= data_pipeline(3) * mu_err;
mu_err_data_prod(3) <= resize(shift_right(mul_temp_20(29 DOWNTO 0) + ( "0" & (mul_temp_20(14) & NOT mul_temp_20(14) & NOT mul_temp_20(14) & NOT mul_temp_20(14) & NOT mul_temp_20(14) & NOT mul_temp_20(14) & NOT mul_temp_20(14) & NOT mul_temp_20(14) & NOT mul_temp_20(14) & NOT mul_temp_20(14) & NOT mul_temp_20(14) & NOT mul_temp_20(14) & NOT mul_temp_20(14) & NOT mul_temp_20(14))), 14), 16);
mul_temp_21 <= data_pipeline(4) * mu_err;
mu_err_data_prod(4) <= resize(shift_right(mul_temp_21(29 DOWNTO 0) + ( "0" & (mul_temp_21(14) & NOT mul_temp_21(14) & NOT mul_temp_21(14) & NOT mul_temp_21(14) & NOT mul_temp_21(14) & NOT mul_temp_21(14) & NOT mul_temp_21(14) & NOT mul_temp_21(14) & NOT mul_temp_21(14) & NOT mul_temp_21(14) & NOT mul_temp_21(14) & NOT mul_temp_21(14) & NOT mul_temp_21(14) & NOT mul_temp_21(14))), 14), 16);
mul_temp_22 <= data_pipeline(5) * mu_err;
mu_err_data_prod(5) <= resize(shift_right(mul_temp_22(29 DOWNTO 0) + ( "0" & (mul_temp_22(14) & NOT mul_temp_22(14) & NOT mul_temp_22(14) & NOT mul_temp_22(14) & NOT mul_temp_22(14) & NOT mul_temp_22(14) & NOT mul_temp_22(14) & NOT mul_temp_22(14) & NOT mul_temp_22(14) & NOT mul_temp_22(14) & NOT mul_temp_22(14) & NOT mul_temp_22(14) & NOT mul_temp_22(14) & NOT mul_temp_22(14))), 14), 16);
mul_temp_23 <= data_pipeline(6) * mu_err;
mu_err_data_prod(6) <= resize(shift_right(mul_temp_23(29 DOWNTO 0) + ( "0" & (mul_temp_23(14) & NOT mul_temp_23(14) & NOT mul_temp_23(14) & NOT mul_temp_23(14) & NOT mul_temp_23(14) & NOT mul_temp_23(14) & NOT mul_temp_23(14) & NOT mul_temp_23(14) & NOT mul_temp_23(14) & NOT mul_temp_23(14) & NOT mul_temp_23(14) & NOT mul_temp_23(14) & NOT mul_temp_23(14) & NOT mul_temp_23(14))), 14), 16);
mul_temp_24 <= data_pipeline(7) * mu_err;
mu_err_data_prod(7) <= resize(shift_right(mul_temp_24(29 DOWNTO 0) + ( "0" & (mul_temp_24(14) & NOT mul_temp_24(14) & NOT mul_temp_24(14) & NOT mul_temp_24(14) & NOT mul_temp_24(14) & NOT mul_temp_24(14) & NOT mul_temp_24(14) & NOT mul_temp_24(14) & NOT mul_temp_24(14) & NOT mul_temp_24(14) & NOT mul_temp_24(14) & NOT mul_temp_24(14) & NOT mul_temp_24(14) & NOT mul_temp_24(14))), 14), 16);
mul_temp_25 <= data_pipeline(8) * mu_err;
mu_err_data_prod(8) <= resize(shift_right(mul_temp_25(29 DOWNTO 0) + ( "0" & (mul_temp_25(14) & NOT mul_temp_25(14) & NOT mul_temp_25(14) & NOT mul_temp_25(14) & NOT mul_temp_25(14) & NOT mul_temp_25(14) & NOT mul_temp_25(14) & NOT mul_temp_25(14) & NOT mul_temp_25(14) & NOT mul_temp_25(14) & NOT mul_temp_25(14) & NOT mul_temp_25(14) & NOT mul_temp_25(14) & NOT mul_temp_25(14))), 14), 16);
mul_temp_26 <= data_pipeline(9) * mu_err;
mu_err_data_prod(9) <= resize(shift_right(mul_temp_26(29 DOWNTO 0) + ( "0" & (mul_temp_26(14) & NOT mul_temp_26(14) & NOT mul_temp_26(14) & NOT mul_temp_26(14) & NOT mul_temp_26(14) & NOT mul_temp_26(14) & NOT mul_temp_26(14) & NOT mul_temp_26(14) & NOT mul_temp_26(14) & NOT mul_temp_26(14) & NOT mul_temp_26(14) & NOT mul_temp_26(14) & NOT mul_temp_26(14) & NOT mul_temp_26(14))), 14), 16);
mul_temp_27 <= data_pipeline(10) * mu_err;
mu_err_data_prod(10) <= resize(shift_right(mul_temp_27(29 DOWNTO 0) + ( "0" & (mul_temp_27(14) & NOT mul_temp_27(14) & NOT mul_temp_27(14) & NOT mul_temp_27(14) & NOT mul_temp_27(14) & NOT mul_temp_27(14) & NOT mul_temp_27(14) & NOT mul_temp_27(14) & NOT mul_temp_27(14) & NOT mul_temp_27(14) & NOT mul_temp_27(14) & NOT mul_temp_27(14) & NOT mul_temp_27(14) & NOT mul_temp_27(14))), 14), 16);
mul_temp_28 <= data_pipeline(11) * mu_err;
mu_err_data_prod(11) <= resize(shift_right(mul_temp_28(29 DOWNTO 0) + ( "0" & (mul_temp_28(14) & NOT mul_temp_28(14) & NOT mul_temp_28(14) & NOT mul_temp_28(14) & NOT mul_temp_28(14) & NOT mul_temp_28(14) & NOT mul_temp_28(14) & NOT mul_temp_28(14) & NOT mul_temp_28(14) & NOT mul_temp_28(14) & NOT mul_temp_28(14) & NOT mul_temp_28(14) & NOT mul_temp_28(14) & NOT mul_temp_28(14))), 14), 16);
mul_temp_29 <= data_pipeline(12) * mu_err;
mu_err_data_prod(12) <= resize(shift_right(mul_temp_29(29 DOWNTO 0) + ( "0" & (mul_temp_29(14) & NOT mul_temp_29(14) & NOT mul_temp_29(14) & NOT mul_temp_29(14) & NOT mul_temp_29(14) & NOT mul_temp_29(14) & NOT mul_temp_29(14) & NOT mul_temp_29(14) & NOT mul_temp_29(14) & NOT mul_temp_29(14) & NOT mul_temp_29(14) & NOT mul_temp_29(14) & NOT mul_temp_29(14) & NOT mul_temp_29(14))), 14), 16);
mul_temp_30 <= data_pipeline(13) * mu_err;
mu_err_data_prod(13) <= resize(shift_right(mul_temp_30(29 DOWNTO 0) + ( "0" & (mul_temp_30(14) & NOT mul_temp_30(14) & NOT mul_temp_30(14) & NOT mul_temp_30(14) & NOT mul_temp_30(14) & NOT mul_temp_30(14) & NOT mul_temp_30(14) & NOT mul_temp_30(14) & NOT mul_temp_30(14) & NOT mul_temp_30(14) & NOT mul_temp_30(14) & NOT mul_temp_30(14) & NOT mul_temp_30(14) & NOT mul_temp_30(14))), 14), 16);
mul_temp_31 <= data_pipeline(14) * mu_err;
mu_err_data_prod(14) <= resize(shift_right(mul_temp_31(29 DOWNTO 0) + ( "0" & (mul_temp_31(14) & NOT mul_temp_31(14) & NOT mul_temp_31(14) & NOT mul_temp_31(14) & NOT mul_temp_31(14) & NOT mul_temp_31(14) & NOT mul_temp_31(14) & NOT mul_temp_31(14) & NOT mul_temp_31(14) & NOT mul_temp_31(14) & NOT mul_temp_31(14) & NOT mul_temp_31(14) & NOT mul_temp_31(14) & NOT mul_temp_31(14))), 14), 16);
mul_temp_32 <= data_pipeline(15) * mu_err;
mu_err_data_prod(15) <= resize(shift_right(mul_temp_32(29 DOWNTO 0) + ( "0" & (mul_temp_32(14) & NOT mul_temp_32(14) & NOT mul_temp_32(14) & NOT mul_temp_32(14) & NOT mul_temp_32(14) & NOT mul_temp_32(14) & NOT mul_temp_32(14) & NOT mul_temp_32(14) & NOT mul_temp_32(14) & NOT mul_temp_32(14) & NOT mul_temp_32(14) & NOT mul_temp_32(14) & NOT mul_temp_32(14) & NOT mul_temp_32(14))), 14), 16);
-- * LMS_Filter Weight Accumulator
add_cast_30 <= weight(0);
add_cast_31 <= mu_err_data_prod(0);
add_temp_15 <= resize(add_cast_30, 17) + resize(add_cast_31, 17);
weight_adder_output(0) <= add_temp_15(15 DOWNTO 0);
add_cast_32 <= weight(1);
add_cast_33 <= mu_err_data_prod(1);
add_temp_16 <= resize(add_cast_32, 17) + resize(add_cast_33, 17);
weight_adder_output(1) <= add_temp_16(15 DOWNTO 0);
add_cast_34 <= weight(2);
add_cast_35 <= mu_err_data_prod(2);
add_temp_17 <= resize(add_cast_34, 17) + resize(add_cast_35, 17);
weight_adder_output(2) <= add_temp_17(15 DOWNTO 0);
add_cast_36 <= weight(3);
add_cast_37 <= mu_err_data_prod(3);
add_temp_18 <= resize(add_cast_36, 17) + resize(add_cast_37, 17);
weight_adder_output(3) <= add_temp_18(15 DOWNTO 0);
add_cast_38 <= weight(4);
add_cast_39 <= mu_err_data_prod(4);
add_temp_19 <= resize(add_cast_38, 17) + resize(add_cast_39, 17);
weight_adder_output(4) <= add_temp_19(15 DOWNTO 0);
add_cast_40 <= weight(5);
add_cast_41 <= mu_err_data_prod(5);
add_temp_20 <= resize(add_cast_40, 17) + resize(add_cast_41, 17);
weight_adder_output(5) <= add_temp_20(15 DOWNTO 0);
add_cast_42 <= weight(6);
add_cast_43 <= mu_err_data_prod(6);
add_temp_21 <= resize(add_cast_42, 17) + resize(add_cast_43, 17);
weight_adder_output(6) <= add_temp_21(15 DOWNTO 0);
add_cast_44 <= weight(7);
add_cast_45 <= mu_err_data_prod(7);
add_temp_22 <= resize(add_cast_44, 17) + resize(add_cast_45, 17);
weight_adder_output(7) <= add_temp_22(15 DOWNTO 0);
add_cast_46 <= weight(8);
add_cast_47 <= mu_err_data_prod(8);
add_temp_23 <= resize(add_cast_46, 17) + resize(add_cast_47, 17);
weight_adder_output(8) <= add_temp_23(15 DOWNTO 0);
add_cast_48 <= weight(9);
add_cast_49 <= mu_err_data_prod(9);
add_temp_24 <= resize(add_cast_48, 17) + resize(add_cast_49, 17);
weight_adder_output(9) <= add_temp_24(15 DOWNTO 0);
add_cast_50 <= weight(10);
add_cast_51 <= mu_err_data_prod(10);
add_temp_25 <= resize(add_cast_50, 17) + resize(add_cast_51, 17);
weight_adder_output(10) <= add_temp_25(15 DOWNTO 0);
add_cast_52 <= weight(11);
add_cast_53 <= mu_err_data_prod(11);
add_temp_26 <= resize(add_cast_52, 17) + resize(add_cast_53, 17);
weight_adder_output(11) <= add_temp_26(15 DOWNTO 0);
add_cast_54 <= weight(12);
add_cast_55 <= mu_err_data_prod(12);
add_temp_27 <= resize(add_cast_54, 17) + resize(add_cast_55, 17);
weight_adder_output(12) <= add_temp_27(15 DOWNTO 0);
add_cast_56 <= weight(13);
add_cast_57 <= mu_err_data_prod(13);
add_temp_28 <= resize(add_cast_56, 17) + resize(add_cast_57, 17);
weight_adder_output(13) <= add_temp_28(15 DOWNTO 0);
add_cast_58 <= weight(14);
add_cast_59 <= mu_err_data_prod(14);
add_temp_29 <= resize(add_cast_58, 17) + resize(add_cast_59, 17);
weight_adder_output(14) <= add_temp_29(15 DOWNTO 0);
add_cast_60 <= weight(15);
add_cast_61 <= mu_err_data_prod(15);
add_temp_30 <= resize(add_cast_60, 17) + resize(add_cast_61, 17);
weight_adder_output(15) <= add_temp_30(15 DOWNTO 0);
LMS_Filter_acc_temp_process2 : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
weight <= (OTHERS => (OTHERS => '0'));
ELSIF clk'event AND clk = '1' THEN
IF enb = '1' THEN
weight(0 TO 15) <= weight_adder_output(0 TO 15);
END IF;
END IF;
END PROCESS LMS_Filter_acc_temp_process2;
e_k <= std_logic_vector(LMS_Filter_out2);
ce_out <= clk_enable;
END rtl;
|
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2013, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
ROM_form.vhd
Production template for a 1K program for KCPSM6 in a Virtex-6 device using a
RAMB18E1 primitive.
Ken Chapman (Xilinx Ltd)
5th August 2011 - First Release
14th March 2013 - Unused address inputs on BRAMs connected High to reflect
descriptions UG363.
This is a VHDL template file for the KCPSM6 assembler.
This VHDL file is not valid as input directly into a synthesis or a simulation tool.
The assembler will read this template and insert the information required to complete
the definition of program ROM and write it out to a new '.vhd' file that is ready for
synthesis and simulation.
This template can be modified to define alternative memory definitions. However, you are
responsible for ensuring the template is correct as the assembler does not perform any
checking of the VHDL.
The assembler identifies all text enclosed by {} characters, and replaces these
character strings. All templates should include these {} character strings for
the assembler to work correctly.
The next line is used to determine where the template actually starts.
{begin template}
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2013, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
--
-- Production definition of a 1K program for KCPSM6 in a Virtex-6 device using a
-- RAMB18E1 primitive.
--
-- Note: The complete 12-bit address bus is connected to KCPSM6 to facilitate future code
-- expansion with minimum changes being required to the hardware description.
-- Only the lower 10-bits of the address are actually used for the 1K address range
-- 000 to 3FF hex.
--
-- Program defined by '{psmname}.psm'.
--
-- Generated by KCPSM6 Assembler: {timestamp}.
--
-- Assembler used ROM_form template: ROM_form_V6_1K_14March13.vhd
--
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library unisim;
use unisim.vcomponents.all;
--
--
entity {name} is
Port ( address : in std_logic_vector(11 downto 0);
instruction : out std_logic_vector(17 downto 0);
enable : in std_logic;
clk : in std_logic);
end {name};
--
architecture low_level_definition of {name} is
--
signal address_a : std_logic_vector(13 downto 0);
signal data_in_a : std_logic_vector(17 downto 0);
signal data_out_a : std_logic_vector(17 downto 0);
signal address_b : std_logic_vector(13 downto 0);
signal data_in_b : std_logic_vector(17 downto 0);
signal data_out_b : std_logic_vector(17 downto 0);
signal enable_b : std_logic;
signal clk_b : std_logic;
signal we_b : std_logic_vector(3 downto 0);
--
begin
--
address_a <= address(9 downto 0) & "1111";
instruction <= data_out_a(17 downto 0);
data_in_a <= "0000000000000000" & address(11 downto 10);
--
address_b <= "11111111111111";
data_in_b <= data_out_b(17 downto 0);
enable_b <= '0';
we_b <= "0000";
clk_b <= '0';
--
--
--
kcpsm6_rom: RAMB18E1
generic map ( READ_WIDTH_A => 18,
WRITE_WIDTH_A => 18,
DOA_REG => 0,
INIT_A => "000000000000000000",
RSTREG_PRIORITY_A => "REGCE",
SRVAL_A => X"000000000000000000",
WRITE_MODE_A => "WRITE_FIRST",
READ_WIDTH_B => 18,
WRITE_WIDTH_B => 18,
DOB_REG => 0,
INIT_B => X"000000000000000000",
RSTREG_PRIORITY_B => "REGCE",
SRVAL_B => X"000000000000000000",
WRITE_MODE_B => "WRITE_FIRST",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
SIM_DEVICE => "VIRTEX6",
INIT_00 => X"{INIT_00}",
INIT_01 => X"{INIT_01}",
INIT_02 => X"{INIT_02}",
INIT_03 => X"{INIT_03}",
INIT_04 => X"{INIT_04}",
INIT_05 => X"{INIT_05}",
INIT_06 => X"{INIT_06}",
INIT_07 => X"{INIT_07}",
INIT_08 => X"{INIT_08}",
INIT_09 => X"{INIT_09}",
INIT_0A => X"{INIT_0A}",
INIT_0B => X"{INIT_0B}",
INIT_0C => X"{INIT_0C}",
INIT_0D => X"{INIT_0D}",
INIT_0E => X"{INIT_0E}",
INIT_0F => X"{INIT_0F}",
INIT_10 => X"{INIT_10}",
INIT_11 => X"{INIT_11}",
INIT_12 => X"{INIT_12}",
INIT_13 => X"{INIT_13}",
INIT_14 => X"{INIT_14}",
INIT_15 => X"{INIT_15}",
INIT_16 => X"{INIT_16}",
INIT_17 => X"{INIT_17}",
INIT_18 => X"{INIT_18}",
INIT_19 => X"{INIT_19}",
INIT_1A => X"{INIT_1A}",
INIT_1B => X"{INIT_1B}",
INIT_1C => X"{INIT_1C}",
INIT_1D => X"{INIT_1D}",
INIT_1E => X"{INIT_1E}",
INIT_1F => X"{INIT_1F}",
INIT_20 => X"{INIT_20}",
INIT_21 => X"{INIT_21}",
INIT_22 => X"{INIT_22}",
INIT_23 => X"{INIT_23}",
INIT_24 => X"{INIT_24}",
INIT_25 => X"{INIT_25}",
INIT_26 => X"{INIT_26}",
INIT_27 => X"{INIT_27}",
INIT_28 => X"{INIT_28}",
INIT_29 => X"{INIT_29}",
INIT_2A => X"{INIT_2A}",
INIT_2B => X"{INIT_2B}",
INIT_2C => X"{INIT_2C}",
INIT_2D => X"{INIT_2D}",
INIT_2E => X"{INIT_2E}",
INIT_2F => X"{INIT_2F}",
INIT_30 => X"{INIT_30}",
INIT_31 => X"{INIT_31}",
INIT_32 => X"{INIT_32}",
INIT_33 => X"{INIT_33}",
INIT_34 => X"{INIT_34}",
INIT_35 => X"{INIT_35}",
INIT_36 => X"{INIT_36}",
INIT_37 => X"{INIT_37}",
INIT_38 => X"{INIT_38}",
INIT_39 => X"{INIT_39}",
INIT_3A => X"{INIT_3A}",
INIT_3B => X"{INIT_3B}",
INIT_3C => X"{INIT_3C}",
INIT_3D => X"{INIT_3D}",
INIT_3E => X"{INIT_3E}",
INIT_3F => X"{INIT_3F}",
INITP_00 => X"{INITP_00}",
INITP_01 => X"{INITP_01}",
INITP_02 => X"{INITP_02}",
INITP_03 => X"{INITP_03}",
INITP_04 => X"{INITP_04}",
INITP_05 => X"{INITP_05}",
INITP_06 => X"{INITP_06}",
INITP_07 => X"{INITP_07}")
port map( ADDRARDADDR => address_a,
ENARDEN => enable,
CLKARDCLK => clk,
DOADO => data_out_a(15 downto 0),
DOPADOP => data_out_a(17 downto 16),
DIADI => data_in_a(15 downto 0),
DIPADIP => data_in_a(17 downto 16),
WEA => "00",
REGCEAREGCE => '0',
RSTRAMARSTRAM => '0',
RSTREGARSTREG => '0',
ADDRBWRADDR => address_b,
ENBWREN => enable_b,
CLKBWRCLK => clk_b,
DOBDO => data_out_b(15 downto 0),
DOPBDOP => data_out_b(17 downto 16),
DIBDI => data_in_b(15 downto 0),
DIPBDIP => data_in_b(17 downto 16),
WEBWE => we_b,
REGCEB => '0',
RSTRAMB => '0',
RSTREGB => '0');
--
--
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- END OF FILE {name}.vhd
--
------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------
-- Engineer: [email protected]
--
-- Create Date: 22:35:50 01/09/2015
-- Design Name: HDMI block averager
-- Module Name: - Behavioral
-- Project Name: Neppielight
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity averager is
Port (
clk_pixel : IN std_logic;
--
i_red : IN std_logic_vector(7 downto 0);
i_green : IN std_logic_vector(7 downto 0);
i_blue : IN std_logic_vector(7 downto 0);
i_blank : IN std_logic;
i_hsync : IN std_logic;
i_vsync : IN std_logic;
--
framebuffer : OUT std_logic_vector(0 to 25*24-1);
o_red : OUT std_logic_vector(7 downto 0);
o_green : OUT std_logic_vector(7 downto 0);
o_blue : OUT std_logic_vector(7 downto 0);
o_blank : OUT std_logic;
o_hsync : OUT std_logic;
o_vsync : OUT std_logic);
end averager;
architecture Behavioral of averager is
-------------------------
-- Part of the pipeline
-------------------------
signal a_red : std_logic_vector(7 downto 0);
signal a_green : std_logic_vector(7 downto 0);
signal a_blue : std_logic_vector(7 downto 0);
signal a_blank : std_logic;
signal a_hsync : std_logic;
signal a_vsync : std_logic;
-------------------------------
-- Counters for screen position
-------------------------------
signal x : STD_LOGIC_VECTOR (10 downto 0);
signal y : STD_LOGIC_VECTOR (10 downto 0);
constant nblocks : integer := 25;
-- signal pixel : std_logic_vector(23 downto 0) := (others => '0');
type accumulator_type is array (0 to nblocks-1,0 to 3) of std_logic_vector(21 downto 0);
signal accumulator : accumulator_type;
--signal blocknr : integer range 0 to 10;
type blockcoords_type is array (0 to nblocks-1) of integer;
-- Due to the details of the construction, we start in the lower left corner
-- and work our way clockwise.
-- Laterally, we've got more leds than pixels, so we'll have partially verlapping boxes.
constant startx : blockcoords_type := ( 0, 0, 0, 0, 0,0,144,288,432,576,720,864,1008,1152,1152,1152,1152,1152,1152,987,823,658,494,329,164);
constant starty : blockcoords_type := (592,472,356,238,118,0, 0, 0, 0, 0, 0, 0, 0, 0, 118, 238, 356, 472, 592,592,592,592,592,592,592);
type gamma_lut_type is array ( 0 to 255) of std_logic_vector(7 downto 0);
constant gamma_lut : gamma_lut_type := (
X"01", X"01", X"01", X"01", X"01", X"01", X"01", X"01", X"01", X"01", X"01", X"01", X"01", X"01",
X"01", X"01", X"01", X"01", X"01", X"01", X"01", X"01", X"02", X"02", X"02", X"02", X"02", X"02",
X"02", X"02", X"02", X"02", X"02", X"03", X"03", X"03", X"03", X"03", X"03", X"03", X"03", X"04",
X"04", X"04", X"04", X"04", X"05", X"05", X"05", X"05", X"05", X"06", X"06", X"06", X"06", X"06",
X"07", X"07", X"07", X"08", X"08", X"08", X"08", X"09", X"09", X"09", X"0A", X"0A", X"0A", X"0B",
X"0B", X"0B", X"0C", X"0C", X"0D", X"0D", X"0D", X"0E", X"0E", X"0F", X"0F", X"0F", X"10", X"10",
X"11", X"11", X"12", X"12", X"13", X"13", X"14", X"14", X"15", X"15", X"16", X"17", X"17", X"18",
X"18", X"19", X"19", X"1A", X"1B", X"1B", X"1C", X"1D", X"1D", X"1E", X"1F", X"1F", X"20", X"21",
X"21", X"22", X"23", X"24", X"24", X"25", X"26", X"27", X"28", X"28", X"29", X"2A", X"2B", X"2C",
X"2D", X"2D", X"2E", X"2F", X"30", X"31", X"32", X"33", X"34", X"35", X"36", X"37", X"38", X"39",
X"3A", X"3B", X"3C", X"3D", X"3E", X"3F", X"40", X"41", X"42", X"43", X"44", X"46", X"47", X"48",
X"49", X"4A", X"4B", X"4D", X"4E", X"4F", X"50", X"51", X"53", X"54", X"55", X"57", X"58", X"59",
X"5A", X"5C", X"5D", X"5F", X"60", X"61", X"63", X"64", X"66", X"67", X"68", X"6A", X"6B", X"6D",
X"6E", X"70", X"71", X"73", X"74", X"76", X"78", X"79", X"7B", X"7C", X"7E", X"80", X"81", X"83",
X"85", X"86", X"88", X"8A", X"8B", X"8D", X"8F", X"91", X"92", X"94", X"96", X"98", X"9A", X"9B",
X"9D", X"9F", X"A1", X"A3", X"A5", X"A7", X"A9", X"AB", X"AD", X"AF", X"B1", X"B3", X"B5", X"B7",
X"B9", X"BB", X"BD", X"BF", X"C1", X"C3", X"C5", X"C7", X"CA", X"CC", X"CE", X"D0", X"D2", X"D5",
X"D7", X"D9", X"DB", X"DE", X"E0", X"E2", X"E4", X"E7", X"E9", X"EC", X"EE", X"F0", X"F3", X"F5",
X"F8", X"FA", X"FD", X"FF");
begin
process(clk_pixel)
variable blockedge : std_logic := '0';
begin
if rising_edge(clk_pixel) then
for bn in 0 to nblocks-1 loop
if unsigned(x) >= startx(bn) and unsigned(x) < startx(bn)+128 and
unsigned(y) >= starty(bn) and unsigned(y) < starty(bn)+128 then
-- We are a part of block bn. Accumulate the color info.
accumulator(bn,0) <= std_logic_vector(unsigned(accumulator(bn,0)) + unsigned(a_red));
accumulator(bn,1) <= std_logic_vector(unsigned(accumulator(bn,1)) + unsigned(a_green));
accumulator(bn,2) <= std_logic_vector(unsigned(accumulator(bn,2)) + unsigned(a_blue));
end if;
end loop;
-- debug, mark the block corners in red
-- blockedge := '0';
-- for bn in 0 to nblocks-1 loop
-- if (unsigned(x) = startx(bn) or unsigned(x) = startx(bn)+128) and
-- (unsigned(y) = starty(bn) or unsigned(y) = starty(bn)+128) then
-- blockedge := '1';
-- end if;
-- end loop;
--
-- if blockedge = '0' then
o_red <= a_red;
o_green <= a_green;
o_blue <= a_blue;
-- else
-- o_red <= X"FF";
-- o_green <= X"00";
-- o_blue <= X"00";
-- end if;
o_blank <= a_blank;
o_hsync <= a_hsync;
o_vsync <= a_vsync;
a_red <= i_red;
a_green <= i_green;
a_blue <= i_blue;
a_blank <= i_blank;
a_hsync <= i_hsync;
a_vsync <= i_vsync;
-- Working out where we are in the screen..
if i_vsync /= a_vsync then
y <= (others => '0');
if i_vsync = '1' then
for i in 0 to nblocks-1 loop
for c in 0 to 2 loop
framebuffer(c * 8 + i * 24 to i * 24 + c * 8 + 7) <= gamma_lut(to_integer(unsigned(accumulator(i,c)(21 downto 14))));
accumulator(i,c) <= (others => '0');
end loop;
end loop;
end if;
end if;
if i_blank = '0' then
x <= std_logic_vector(unsigned(x) + 1);
end if;
-- Start of the blanking interval?
if a_blank = '0' and i_blank = '1' then
y <= std_logic_vector(unsigned(y) + 1);
x <= (others => '0');
end if;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Engineer: [email protected]
--
-- Create Date: 22:35:50 01/09/2015
-- Design Name: HDMI block averager
-- Module Name: - Behavioral
-- Project Name: Neppielight
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity averager is
Port (
clk_pixel : IN std_logic;
--
i_red : IN std_logic_vector(7 downto 0);
i_green : IN std_logic_vector(7 downto 0);
i_blue : IN std_logic_vector(7 downto 0);
i_blank : IN std_logic;
i_hsync : IN std_logic;
i_vsync : IN std_logic;
--
framebuffer : OUT std_logic_vector(0 to 25*24-1);
o_red : OUT std_logic_vector(7 downto 0);
o_green : OUT std_logic_vector(7 downto 0);
o_blue : OUT std_logic_vector(7 downto 0);
o_blank : OUT std_logic;
o_hsync : OUT std_logic;
o_vsync : OUT std_logic);
end averager;
architecture Behavioral of averager is
-------------------------
-- Part of the pipeline
-------------------------
signal a_red : std_logic_vector(7 downto 0);
signal a_green : std_logic_vector(7 downto 0);
signal a_blue : std_logic_vector(7 downto 0);
signal a_blank : std_logic;
signal a_hsync : std_logic;
signal a_vsync : std_logic;
-------------------------------
-- Counters for screen position
-------------------------------
signal x : STD_LOGIC_VECTOR (10 downto 0);
signal y : STD_LOGIC_VECTOR (10 downto 0);
constant nblocks : integer := 25;
-- signal pixel : std_logic_vector(23 downto 0) := (others => '0');
type accumulator_type is array (0 to nblocks-1,0 to 3) of std_logic_vector(21 downto 0);
signal accumulator : accumulator_type;
--signal blocknr : integer range 0 to 10;
type blockcoords_type is array (0 to nblocks-1) of integer;
-- Due to the details of the construction, we start in the lower left corner
-- and work our way clockwise.
-- Laterally, we've got more leds than pixels, so we'll have partially verlapping boxes.
constant startx : blockcoords_type := ( 0, 0, 0, 0, 0,0,144,288,432,576,720,864,1008,1152,1152,1152,1152,1152,1152,987,823,658,494,329,164);
constant starty : blockcoords_type := (592,472,356,238,118,0, 0, 0, 0, 0, 0, 0, 0, 0, 118, 238, 356, 472, 592,592,592,592,592,592,592);
type gamma_lut_type is array ( 0 to 255) of std_logic_vector(7 downto 0);
constant gamma_lut : gamma_lut_type := (
X"01", X"01", X"01", X"01", X"01", X"01", X"01", X"01", X"01", X"01", X"01", X"01", X"01", X"01",
X"01", X"01", X"01", X"01", X"01", X"01", X"01", X"01", X"02", X"02", X"02", X"02", X"02", X"02",
X"02", X"02", X"02", X"02", X"02", X"03", X"03", X"03", X"03", X"03", X"03", X"03", X"03", X"04",
X"04", X"04", X"04", X"04", X"05", X"05", X"05", X"05", X"05", X"06", X"06", X"06", X"06", X"06",
X"07", X"07", X"07", X"08", X"08", X"08", X"08", X"09", X"09", X"09", X"0A", X"0A", X"0A", X"0B",
X"0B", X"0B", X"0C", X"0C", X"0D", X"0D", X"0D", X"0E", X"0E", X"0F", X"0F", X"0F", X"10", X"10",
X"11", X"11", X"12", X"12", X"13", X"13", X"14", X"14", X"15", X"15", X"16", X"17", X"17", X"18",
X"18", X"19", X"19", X"1A", X"1B", X"1B", X"1C", X"1D", X"1D", X"1E", X"1F", X"1F", X"20", X"21",
X"21", X"22", X"23", X"24", X"24", X"25", X"26", X"27", X"28", X"28", X"29", X"2A", X"2B", X"2C",
X"2D", X"2D", X"2E", X"2F", X"30", X"31", X"32", X"33", X"34", X"35", X"36", X"37", X"38", X"39",
X"3A", X"3B", X"3C", X"3D", X"3E", X"3F", X"40", X"41", X"42", X"43", X"44", X"46", X"47", X"48",
X"49", X"4A", X"4B", X"4D", X"4E", X"4F", X"50", X"51", X"53", X"54", X"55", X"57", X"58", X"59",
X"5A", X"5C", X"5D", X"5F", X"60", X"61", X"63", X"64", X"66", X"67", X"68", X"6A", X"6B", X"6D",
X"6E", X"70", X"71", X"73", X"74", X"76", X"78", X"79", X"7B", X"7C", X"7E", X"80", X"81", X"83",
X"85", X"86", X"88", X"8A", X"8B", X"8D", X"8F", X"91", X"92", X"94", X"96", X"98", X"9A", X"9B",
X"9D", X"9F", X"A1", X"A3", X"A5", X"A7", X"A9", X"AB", X"AD", X"AF", X"B1", X"B3", X"B5", X"B7",
X"B9", X"BB", X"BD", X"BF", X"C1", X"C3", X"C5", X"C7", X"CA", X"CC", X"CE", X"D0", X"D2", X"D5",
X"D7", X"D9", X"DB", X"DE", X"E0", X"E2", X"E4", X"E7", X"E9", X"EC", X"EE", X"F0", X"F3", X"F5",
X"F8", X"FA", X"FD", X"FF");
begin
process(clk_pixel)
variable blockedge : std_logic := '0';
begin
if rising_edge(clk_pixel) then
for bn in 0 to nblocks-1 loop
if unsigned(x) >= startx(bn) and unsigned(x) < startx(bn)+128 and
unsigned(y) >= starty(bn) and unsigned(y) < starty(bn)+128 then
-- We are a part of block bn. Accumulate the color info.
accumulator(bn,0) <= std_logic_vector(unsigned(accumulator(bn,0)) + unsigned(a_red));
accumulator(bn,1) <= std_logic_vector(unsigned(accumulator(bn,1)) + unsigned(a_green));
accumulator(bn,2) <= std_logic_vector(unsigned(accumulator(bn,2)) + unsigned(a_blue));
end if;
end loop;
-- debug, mark the block corners in red
-- blockedge := '0';
-- for bn in 0 to nblocks-1 loop
-- if (unsigned(x) = startx(bn) or unsigned(x) = startx(bn)+128) and
-- (unsigned(y) = starty(bn) or unsigned(y) = starty(bn)+128) then
-- blockedge := '1';
-- end if;
-- end loop;
--
-- if blockedge = '0' then
o_red <= a_red;
o_green <= a_green;
o_blue <= a_blue;
-- else
-- o_red <= X"FF";
-- o_green <= X"00";
-- o_blue <= X"00";
-- end if;
o_blank <= a_blank;
o_hsync <= a_hsync;
o_vsync <= a_vsync;
a_red <= i_red;
a_green <= i_green;
a_blue <= i_blue;
a_blank <= i_blank;
a_hsync <= i_hsync;
a_vsync <= i_vsync;
-- Working out where we are in the screen..
if i_vsync /= a_vsync then
y <= (others => '0');
if i_vsync = '1' then
for i in 0 to nblocks-1 loop
for c in 0 to 2 loop
framebuffer(c * 8 + i * 24 to i * 24 + c * 8 + 7) <= gamma_lut(to_integer(unsigned(accumulator(i,c)(21 downto 14))));
accumulator(i,c) <= (others => '0');
end loop;
end loop;
end if;
end if;
if i_blank = '0' then
x <= std_logic_vector(unsigned(x) + 1);
end if;
-- Start of the blanking interval?
if a_blank = '0' and i_blank = '1' then
y <= std_logic_vector(unsigned(y) + 1);
x <= (others => '0');
end if;
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
-- bfm_system.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bfm_system is
port (
sys_reset : in std_logic;
sys_clk : in std_logic
);
end bfm_system;
architecture STRUCTURE of bfm_system is
component bfm_processor_wrapper is
port (
PLB_CLK : in std_logic;
PLB_RESET : in std_logic;
SYNCH_OUT : out std_logic_vector(0 to 31);
SYNCH_IN : in std_logic_vector(0 to 31);
PLB_MAddrAck : in std_logic;
PLB_MSsize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MBusy : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to 127);
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrBTerm : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_buslock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to 15);
M_msize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_UABus : out std_logic_vector(0 to 31);
M_ABus : out std_logic_vector(0 to 31);
M_wrDBus : out std_logic_vector(0 to 127);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic
);
end component;
component bfm_memory_wrapper is
port (
PLB_CLK : in std_logic;
PLB_RESET : in std_logic;
SYNCH_OUT : out std_logic_vector(0 to 31);
SYNCH_IN : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to 0);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 15);
PLB_msize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_TAttribute : in std_logic_vector(0 to 15);
PLB_lockErr : in std_logic;
PLB_UABus : in std_logic_vector(0 to 31);
PLB_ABus : in std_logic_vector(0 to 31);
PLB_wrDBus : in std_logic_vector(0 to 127);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_rdpendReq : in std_logic;
PLB_wrpendReq : in std_logic;
PLB_rdpendPri : in std_logic_vector(0 to 1);
PLB_wrpendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
Sl_addrAck : out std_logic;
Sl_ssize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 127);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 1);
Sl_MRdErr : out std_logic_vector(0 to 1);
Sl_MWrErr : out std_logic_vector(0 to 1);
Sl_MIRQ : out std_logic_vector(0 to 1)
);
end component;
component bfm_monitor_wrapper is
port (
PLB_CLK : in std_logic;
PLB_RESET : in std_logic;
SYNCH_OUT : out std_logic_vector(0 to 31);
SYNCH_IN : in std_logic_vector(0 to 31);
M_request : in std_logic_vector(0 to 1);
M_priority : in std_logic_vector(0 to 3);
M_buslock : in std_logic_vector(0 to 1);
M_RNW : in std_logic_vector(0 to 1);
M_BE : in std_logic_vector(0 to 31);
M_msize : in std_logic_vector(0 to 3);
M_size : in std_logic_vector(0 to 7);
M_type : in std_logic_vector(0 to 5);
M_TAttribute : in std_logic_vector(0 to 31);
M_lockErr : in std_logic_vector(0 to 1);
M_abort : in std_logic_vector(0 to 1);
M_UABus : in std_logic_vector(0 to 63);
M_ABus : in std_logic_vector(0 to 63);
M_wrDBus : in std_logic_vector(0 to 255);
M_wrBurst : in std_logic_vector(0 to 1);
M_rdBurst : in std_logic_vector(0 to 1);
PLB_MAddrAck : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic_vector(0 to 1);
PLB_MTimeout : in std_logic_vector(0 to 1);
PLB_MBusy : in std_logic_vector(0 to 1);
PLB_MRdErr : in std_logic_vector(0 to 1);
PLB_MWrErr : in std_logic_vector(0 to 1);
PLB_MIRQ : in std_logic_vector(0 to 1);
PLB_MWrDAck : in std_logic_vector(0 to 1);
PLB_MRdDBus : in std_logic_vector(0 to 255);
PLB_MRdWdAddr : in std_logic_vector(0 to 7);
PLB_MRdDAck : in std_logic_vector(0 to 1);
PLB_MRdBTerm : in std_logic_vector(0 to 1);
PLB_MWrBTerm : in std_logic_vector(0 to 1);
PLB_Mssize : in std_logic_vector(0 to 3);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic_vector(0 to 0);
PLB_wrPrim : in std_logic_vector(0 to 0);
PLB_MasterID : in std_logic_vector(0 to 0);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 15);
PLB_msize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_TAttribute : in std_logic_vector(0 to 15);
PLB_lockErr : in std_logic;
PLB_UABus : in std_logic_vector(0 to 31);
PLB_ABus : in std_logic_vector(0 to 31);
PLB_wrDBus : in std_logic_vector(0 to 127);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_rdpendReq : in std_logic;
PLB_wrpendReq : in std_logic;
PLB_rdpendPri : in std_logic_vector(0 to 1);
PLB_wrpendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
Sl_addrAck : in std_logic_vector(0 to 0);
Sl_wait : in std_logic_vector(0 to 0);
Sl_rearbitrate : in std_logic_vector(0 to 0);
Sl_wrDAck : in std_logic_vector(0 to 0);
Sl_wrComp : in std_logic_vector(0 to 0);
Sl_wrBTerm : in std_logic_vector(0 to 0);
Sl_rdDBus : in std_logic_vector(0 to 127);
Sl_rdWdAddr : in std_logic_vector(0 to 3);
Sl_rdDAck : in std_logic_vector(0 to 0);
Sl_rdComp : in std_logic_vector(0 to 0);
Sl_rdBTerm : in std_logic_vector(0 to 0);
Sl_MBusy : in std_logic_vector(0 to 1);
Sl_MRdErr : in std_logic_vector(0 to 1);
Sl_MWrErr : in std_logic_vector(0 to 1);
Sl_MIRQ : in std_logic_vector(0 to 1);
Sl_ssize : in std_logic_vector(0 to 1);
PLB_SaddrAck : in std_logic;
PLB_Swait : in std_logic;
PLB_Srearbitrate : in std_logic;
PLB_SwrDAck : in std_logic;
PLB_SwrComp : in std_logic;
PLB_SwrBTerm : in std_logic;
PLB_SrdDBus : in std_logic_vector(0 to 127);
PLB_SrdWdAddr : in std_logic_vector(0 to 3);
PLB_SrdDAck : in std_logic;
PLB_SrdComp : in std_logic;
PLB_SrdBTerm : in std_logic;
PLB_SMBusy : in std_logic_vector(0 to 1);
PLB_SMRdErr : in std_logic_vector(0 to 1);
PLB_SMWrErr : in std_logic_vector(0 to 1);
PLB_SMIRQ : in std_logic_vector(0 to 1);
PLB_Sssize : in std_logic_vector(0 to 1)
);
end component;
component synch_bus_wrapper is
port (
FROM_SYNCH_OUT : in std_logic_vector(0 to 127);
TO_SYNCH_IN : out std_logic_vector(0 to 31)
);
end component;
component plb_bus_wrapper is
port (
PLB_Clk : in std_logic;
SYS_Rst : in std_logic;
PLB_Rst : out std_logic;
SPLB_Rst : out std_logic_vector(0 to 0);
MPLB_Rst : out std_logic_vector(0 to 1);
PLB_dcrAck : out std_logic;
PLB_dcrDBus : out std_logic_vector(0 to 31);
DCR_ABus : in std_logic_vector(0 to 9);
DCR_DBus : in std_logic_vector(0 to 31);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
M_ABus : in std_logic_vector(0 to 63);
M_UABus : in std_logic_vector(0 to 63);
M_BE : in std_logic_vector(0 to 31);
M_RNW : in std_logic_vector(0 to 1);
M_abort : in std_logic_vector(0 to 1);
M_busLock : in std_logic_vector(0 to 1);
M_TAttribute : in std_logic_vector(0 to 31);
M_lockErr : in std_logic_vector(0 to 1);
M_MSize : in std_logic_vector(0 to 3);
M_priority : in std_logic_vector(0 to 3);
M_rdBurst : in std_logic_vector(0 to 1);
M_request : in std_logic_vector(0 to 1);
M_size : in std_logic_vector(0 to 7);
M_type : in std_logic_vector(0 to 5);
M_wrBurst : in std_logic_vector(0 to 1);
M_wrDBus : in std_logic_vector(0 to 255);
Sl_addrAck : in std_logic_vector(0 to 0);
Sl_MRdErr : in std_logic_vector(0 to 1);
Sl_MWrErr : in std_logic_vector(0 to 1);
Sl_MBusy : in std_logic_vector(0 to 1);
Sl_rdBTerm : in std_logic_vector(0 to 0);
Sl_rdComp : in std_logic_vector(0 to 0);
Sl_rdDAck : in std_logic_vector(0 to 0);
Sl_rdDBus : in std_logic_vector(0 to 127);
Sl_rdWdAddr : in std_logic_vector(0 to 3);
Sl_rearbitrate : in std_logic_vector(0 to 0);
Sl_SSize : in std_logic_vector(0 to 1);
Sl_wait : in std_logic_vector(0 to 0);
Sl_wrBTerm : in std_logic_vector(0 to 0);
Sl_wrComp : in std_logic_vector(0 to 0);
Sl_wrDAck : in std_logic_vector(0 to 0);
Sl_MIRQ : in std_logic_vector(0 to 1);
PLB_MIRQ : out std_logic_vector(0 to 1);
PLB_ABus : out std_logic_vector(0 to 31);
PLB_UABus : out std_logic_vector(0 to 31);
PLB_BE : out std_logic_vector(0 to 15);
PLB_MAddrAck : out std_logic_vector(0 to 1);
PLB_MTimeout : out std_logic_vector(0 to 1);
PLB_MBusy : out std_logic_vector(0 to 1);
PLB_MRdErr : out std_logic_vector(0 to 1);
PLB_MWrErr : out std_logic_vector(0 to 1);
PLB_MRdBTerm : out std_logic_vector(0 to 1);
PLB_MRdDAck : out std_logic_vector(0 to 1);
PLB_MRdDBus : out std_logic_vector(0 to 255);
PLB_MRdWdAddr : out std_logic_vector(0 to 7);
PLB_MRearbitrate : out std_logic_vector(0 to 1);
PLB_MWrBTerm : out std_logic_vector(0 to 1);
PLB_MWrDAck : out std_logic_vector(0 to 1);
PLB_MSSize : out std_logic_vector(0 to 3);
PLB_PAValid : out std_logic;
PLB_RNW : out std_logic;
PLB_SAValid : out std_logic;
PLB_abort : out std_logic;
PLB_busLock : out std_logic;
PLB_TAttribute : out std_logic_vector(0 to 15);
PLB_lockErr : out std_logic;
PLB_masterID : out std_logic_vector(0 to 0);
PLB_MSize : out std_logic_vector(0 to 1);
PLB_rdPendPri : out std_logic_vector(0 to 1);
PLB_wrPendPri : out std_logic_vector(0 to 1);
PLB_rdPendReq : out std_logic;
PLB_wrPendReq : out std_logic;
PLB_rdBurst : out std_logic;
PLB_rdPrim : out std_logic_vector(0 to 0);
PLB_reqPri : out std_logic_vector(0 to 1);
PLB_size : out std_logic_vector(0 to 3);
PLB_type : out std_logic_vector(0 to 2);
PLB_wrBurst : out std_logic;
PLB_wrDBus : out std_logic_vector(0 to 127);
PLB_wrPrim : out std_logic_vector(0 to 0);
PLB_SaddrAck : out std_logic;
PLB_SMRdErr : out std_logic_vector(0 to 1);
PLB_SMWrErr : out std_logic_vector(0 to 1);
PLB_SMBusy : out std_logic_vector(0 to 1);
PLB_SrdBTerm : out std_logic;
PLB_SrdComp : out std_logic;
PLB_SrdDAck : out std_logic;
PLB_SrdDBus : out std_logic_vector(0 to 127);
PLB_SrdWdAddr : out std_logic_vector(0 to 3);
PLB_Srearbitrate : out std_logic;
PLB_Sssize : out std_logic_vector(0 to 1);
PLB_Swait : out std_logic;
PLB_SwrBTerm : out std_logic;
PLB_SwrComp : out std_logic;
PLB_SwrDAck : out std_logic;
PLB2OPB_rearb : in std_logic_vector(0 to 0);
Bus_Error_Det : out std_logic
);
end component;
component my_core_wrapper is
port (
MPLB_Clk : in std_logic;
MPLB_Rst : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to 15);
M_MSize : out std_logic_vector(0 to 1);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_TAttribute : out std_logic_vector(0 to 15);
M_lockErr : out std_logic;
M_abort : out std_logic;
M_UABus : out std_logic_vector(0 to 31);
M_ABus : out std_logic_vector(0 to 31);
M_wrDBus : out std_logic_vector(0 to 127);
M_wrBurst : out std_logic;
M_rdBurst : out std_logic;
PLB_MAddrAck : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
PLB_MRearbitrate : in std_logic;
PLB_MTimeout : in std_logic;
PLB_MBusy : in std_logic;
PLB_MRdErr : in std_logic;
PLB_MWrErr : in std_logic;
PLB_MIRQ : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to 127);
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRdDAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MWrBTerm : in std_logic;
SYNCH_IN : in std_logic_vector(0 to 31);
SYNCH_OUT : out std_logic_vector(0 to 31)
);
end component;
-- Internal signals
signal net_gnd0 : std_logic;
signal net_gnd1 : std_logic_vector(0 to 0);
signal net_gnd2 : std_logic_vector(0 to 1);
signal net_gnd10 : std_logic_vector(0 to 9);
signal net_gnd32 : std_logic_vector(0 to 31);
signal pgassign1 : std_logic_vector(0 to 127);
signal plb_bus_MPLB_Rst : std_logic_vector(0 to 1);
signal plb_bus_M_ABus : std_logic_vector(0 to 63);
signal plb_bus_M_BE : std_logic_vector(0 to 31);
signal plb_bus_M_MSize : std_logic_vector(0 to 3);
signal plb_bus_M_RNW : std_logic_vector(0 to 1);
signal plb_bus_M_TAttribute : std_logic_vector(0 to 31);
signal plb_bus_M_UABus : std_logic_vector(0 to 63);
signal plb_bus_M_abort : std_logic_vector(0 to 1);
signal plb_bus_M_busLock : std_logic_vector(0 to 1);
signal plb_bus_M_lockErr : std_logic_vector(0 to 1);
signal plb_bus_M_priority : std_logic_vector(0 to 3);
signal plb_bus_M_rdBurst : std_logic_vector(0 to 1);
signal plb_bus_M_request : std_logic_vector(0 to 1);
signal plb_bus_M_size : std_logic_vector(0 to 7);
signal plb_bus_M_type : std_logic_vector(0 to 5);
signal plb_bus_M_wrBurst : std_logic_vector(0 to 1);
signal plb_bus_M_wrDBus : std_logic_vector(0 to 255);
signal plb_bus_PLB_ABus : std_logic_vector(0 to 31);
signal plb_bus_PLB_BE : std_logic_vector(0 to 15);
signal plb_bus_PLB_MAddrAck : std_logic_vector(0 to 1);
signal plb_bus_PLB_MBusy : std_logic_vector(0 to 1);
signal plb_bus_PLB_MIRQ : std_logic_vector(0 to 1);
signal plb_bus_PLB_MRdBTerm : std_logic_vector(0 to 1);
signal plb_bus_PLB_MRdDAck : std_logic_vector(0 to 1);
signal plb_bus_PLB_MRdDBus : std_logic_vector(0 to 255);
signal plb_bus_PLB_MRdErr : std_logic_vector(0 to 1);
signal plb_bus_PLB_MRdWdAddr : std_logic_vector(0 to 7);
signal plb_bus_PLB_MRearbitrate : std_logic_vector(0 to 1);
signal plb_bus_PLB_MSSize : std_logic_vector(0 to 3);
signal plb_bus_PLB_MSize : std_logic_vector(0 to 1);
signal plb_bus_PLB_MTimeout : std_logic_vector(0 to 1);
signal plb_bus_PLB_MWrBTerm : std_logic_vector(0 to 1);
signal plb_bus_PLB_MWrDAck : std_logic_vector(0 to 1);
signal plb_bus_PLB_MWrErr : std_logic_vector(0 to 1);
signal plb_bus_PLB_PAValid : std_logic;
signal plb_bus_PLB_RNW : std_logic;
signal plb_bus_PLB_Rst : std_logic;
signal plb_bus_PLB_SAValid : std_logic;
signal plb_bus_PLB_SMBusy : std_logic_vector(0 to 1);
signal plb_bus_PLB_SMRdErr : std_logic_vector(0 to 1);
signal plb_bus_PLB_SMWrErr : std_logic_vector(0 to 1);
signal plb_bus_PLB_SaddrAck : std_logic;
signal plb_bus_PLB_SrdBTerm : std_logic;
signal plb_bus_PLB_SrdComp : std_logic;
signal plb_bus_PLB_SrdDAck : std_logic;
signal plb_bus_PLB_SrdDBus : std_logic_vector(0 to 127);
signal plb_bus_PLB_SrdWdAddr : std_logic_vector(0 to 3);
signal plb_bus_PLB_Srearbitrate : std_logic;
signal plb_bus_PLB_Sssize : std_logic_vector(0 to 1);
signal plb_bus_PLB_Swait : std_logic;
signal plb_bus_PLB_SwrBTerm : std_logic;
signal plb_bus_PLB_SwrComp : std_logic;
signal plb_bus_PLB_SwrDAck : std_logic;
signal plb_bus_PLB_TAttribute : std_logic_vector(0 to 15);
signal plb_bus_PLB_UABus : std_logic_vector(0 to 31);
signal plb_bus_PLB_abort : std_logic;
signal plb_bus_PLB_busLock : std_logic;
signal plb_bus_PLB_lockErr : std_logic;
signal plb_bus_PLB_masterID : std_logic_vector(0 to 0);
signal plb_bus_PLB_rdBurst : std_logic;
signal plb_bus_PLB_rdPrim : std_logic_vector(0 to 0);
signal plb_bus_PLB_rdpendPri : std_logic_vector(0 to 1);
signal plb_bus_PLB_rdpendReq : std_logic;
signal plb_bus_PLB_reqPri : std_logic_vector(0 to 1);
signal plb_bus_PLB_size : std_logic_vector(0 to 3);
signal plb_bus_PLB_type : std_logic_vector(0 to 2);
signal plb_bus_PLB_wrBurst : std_logic;
signal plb_bus_PLB_wrDBus : std_logic_vector(0 to 127);
signal plb_bus_PLB_wrPrim : std_logic_vector(0 to 0);
signal plb_bus_PLB_wrpendPri : std_logic_vector(0 to 1);
signal plb_bus_PLB_wrpendReq : std_logic;
signal plb_bus_Sl_MBusy : std_logic_vector(0 to 1);
signal plb_bus_Sl_MIRQ : std_logic_vector(0 to 1);
signal plb_bus_Sl_MRdErr : std_logic_vector(0 to 1);
signal plb_bus_Sl_MWrErr : std_logic_vector(0 to 1);
signal plb_bus_Sl_SSize : std_logic_vector(0 to 1);
signal plb_bus_Sl_addrAck : std_logic_vector(0 to 0);
signal plb_bus_Sl_rdBTerm : std_logic_vector(0 to 0);
signal plb_bus_Sl_rdComp : std_logic_vector(0 to 0);
signal plb_bus_Sl_rdDAck : std_logic_vector(0 to 0);
signal plb_bus_Sl_rdDBus : std_logic_vector(0 to 127);
signal plb_bus_Sl_rdWdAddr : std_logic_vector(0 to 3);
signal plb_bus_Sl_rearbitrate : std_logic_vector(0 to 0);
signal plb_bus_Sl_wait : std_logic_vector(0 to 0);
signal plb_bus_Sl_wrBTerm : std_logic_vector(0 to 0);
signal plb_bus_Sl_wrComp : std_logic_vector(0 to 0);
signal plb_bus_Sl_wrDAck : std_logic_vector(0 to 0);
signal synch : std_logic_vector(0 to 31);
signal synch0 : std_logic_vector(0 to 31);
signal synch1 : std_logic_vector(0 to 31);
signal synch2 : std_logic_vector(0 to 31);
signal synch3 : std_logic_vector(0 to 31);
begin
-- Internal assignments
pgassign1(0 to 31) <= synch0(0 to 31);
pgassign1(32 to 63) <= synch1(0 to 31);
pgassign1(64 to 95) <= synch2(0 to 31);
pgassign1(96 to 127) <= synch3(0 to 31);
net_gnd0 <= '0';
net_gnd1(0 to 0) <= B"0";
net_gnd10(0 to 9) <= B"0000000000";
net_gnd2(0 to 1) <= B"00";
net_gnd32(0 to 31) <= B"00000000000000000000000000000000";
bfm_processor : bfm_processor_wrapper
port map (
PLB_CLK => sys_clk,
PLB_RESET => plb_bus_PLB_Rst,
SYNCH_OUT => synch0,
SYNCH_IN => synch,
PLB_MAddrAck => plb_bus_PLB_MAddrAck(0),
PLB_MSsize => plb_bus_PLB_MSSize(0 to 1),
PLB_MRearbitrate => plb_bus_PLB_MRearbitrate(0),
PLB_MTimeout => plb_bus_PLB_MTimeout(0),
PLB_MBusy => plb_bus_PLB_MBusy(0),
PLB_MRdErr => plb_bus_PLB_MRdErr(0),
PLB_MWrErr => plb_bus_PLB_MWrErr(0),
PLB_MIRQ => plb_bus_PLB_MIRQ(0),
PLB_MWrDAck => plb_bus_PLB_MWrDAck(0),
PLB_MRdDBus => plb_bus_PLB_MRdDBus(0 to 127),
PLB_MRdWdAddr => plb_bus_PLB_MRdWdAddr(0 to 3),
PLB_MRdDAck => plb_bus_PLB_MRdDAck(0),
PLB_MRdBTerm => plb_bus_PLB_MRdBTerm(0),
PLB_MWrBTerm => plb_bus_PLB_MWrBTerm(0),
M_request => plb_bus_M_request(0),
M_priority => plb_bus_M_priority(0 to 1),
M_buslock => plb_bus_M_busLock(0),
M_RNW => plb_bus_M_RNW(0),
M_BE => plb_bus_M_BE(0 to 15),
M_msize => plb_bus_M_MSize(0 to 1),
M_size => plb_bus_M_size(0 to 3),
M_type => plb_bus_M_type(0 to 2),
M_TAttribute => plb_bus_M_TAttribute(0 to 15),
M_lockErr => plb_bus_M_lockErr(0),
M_abort => plb_bus_M_abort(0),
M_UABus => plb_bus_M_UABus(0 to 31),
M_ABus => plb_bus_M_ABus(0 to 31),
M_wrDBus => plb_bus_M_wrDBus(0 to 127),
M_wrBurst => plb_bus_M_wrBurst(0),
M_rdBurst => plb_bus_M_rdBurst(0)
);
bfm_memory : bfm_memory_wrapper
port map (
PLB_CLK => sys_clk,
PLB_RESET => plb_bus_PLB_Rst,
SYNCH_OUT => synch1,
SYNCH_IN => synch,
PLB_PAValid => plb_bus_PLB_PAValid,
PLB_SAValid => plb_bus_PLB_SAValid,
PLB_rdPrim => plb_bus_PLB_rdPrim(0),
PLB_wrPrim => plb_bus_PLB_wrPrim(0),
PLB_masterID => plb_bus_PLB_masterID(0 to 0),
PLB_abort => plb_bus_PLB_abort,
PLB_busLock => plb_bus_PLB_busLock,
PLB_RNW => plb_bus_PLB_RNW,
PLB_BE => plb_bus_PLB_BE,
PLB_msize => plb_bus_PLB_MSize,
PLB_size => plb_bus_PLB_size,
PLB_type => plb_bus_PLB_type,
PLB_TAttribute => plb_bus_PLB_TAttribute,
PLB_lockErr => plb_bus_PLB_lockErr,
PLB_UABus => plb_bus_PLB_UABus,
PLB_ABus => plb_bus_PLB_ABus,
PLB_wrDBus => plb_bus_PLB_wrDBus,
PLB_wrBurst => plb_bus_PLB_wrBurst,
PLB_rdBurst => plb_bus_PLB_rdBurst,
PLB_rdpendReq => plb_bus_PLB_rdpendReq,
PLB_wrpendReq => plb_bus_PLB_wrpendReq,
PLB_rdpendPri => plb_bus_PLB_rdpendPri,
PLB_wrpendPri => plb_bus_PLB_wrpendPri,
PLB_reqPri => plb_bus_PLB_reqPri,
Sl_addrAck => plb_bus_Sl_addrAck(0),
Sl_ssize => plb_bus_Sl_SSize,
Sl_wait => plb_bus_Sl_wait(0),
Sl_rearbitrate => plb_bus_Sl_rearbitrate(0),
Sl_wrDAck => plb_bus_Sl_wrDAck(0),
Sl_wrComp => plb_bus_Sl_wrComp(0),
Sl_wrBTerm => plb_bus_Sl_wrBTerm(0),
Sl_rdDBus => plb_bus_Sl_rdDBus,
Sl_rdWdAddr => plb_bus_Sl_rdWdAddr,
Sl_rdDAck => plb_bus_Sl_rdDAck(0),
Sl_rdComp => plb_bus_Sl_rdComp(0),
Sl_rdBTerm => plb_bus_Sl_rdBTerm(0),
Sl_MBusy => plb_bus_Sl_MBusy,
Sl_MRdErr => plb_bus_Sl_MRdErr,
Sl_MWrErr => plb_bus_Sl_MWrErr,
Sl_MIRQ => plb_bus_Sl_MIRQ
);
bfm_monitor : bfm_monitor_wrapper
port map (
PLB_CLK => sys_clk,
PLB_RESET => plb_bus_PLB_Rst,
SYNCH_OUT => synch2,
SYNCH_IN => synch,
M_request => plb_bus_M_request,
M_priority => plb_bus_M_priority,
M_buslock => plb_bus_M_busLock,
M_RNW => plb_bus_M_RNW,
M_BE => plb_bus_M_BE,
M_msize => plb_bus_M_MSize,
M_size => plb_bus_M_size,
M_type => plb_bus_M_type,
M_TAttribute => plb_bus_M_TAttribute,
M_lockErr => plb_bus_M_lockErr,
M_abort => plb_bus_M_abort,
M_UABus => plb_bus_M_UABus,
M_ABus => plb_bus_M_ABus,
M_wrDBus => plb_bus_M_wrDBus,
M_wrBurst => plb_bus_M_wrBurst,
M_rdBurst => plb_bus_M_rdBurst,
PLB_MAddrAck => plb_bus_PLB_MAddrAck,
PLB_MRearbitrate => plb_bus_PLB_MRearbitrate,
PLB_MTimeout => plb_bus_PLB_MTimeout,
PLB_MBusy => plb_bus_PLB_MBusy,
PLB_MRdErr => plb_bus_PLB_MRdErr,
PLB_MWrErr => plb_bus_PLB_MWrErr,
PLB_MIRQ => plb_bus_PLB_MIRQ,
PLB_MWrDAck => plb_bus_PLB_MWrDAck,
PLB_MRdDBus => plb_bus_PLB_MRdDBus,
PLB_MRdWdAddr => plb_bus_PLB_MRdWdAddr,
PLB_MRdDAck => plb_bus_PLB_MRdDAck,
PLB_MRdBTerm => plb_bus_PLB_MRdBTerm,
PLB_MWrBTerm => plb_bus_PLB_MWrBTerm,
PLB_Mssize => plb_bus_PLB_MSSize,
PLB_PAValid => plb_bus_PLB_PAValid,
PLB_SAValid => plb_bus_PLB_SAValid,
PLB_rdPrim => plb_bus_PLB_rdPrim(0 to 0),
PLB_wrPrim => plb_bus_PLB_wrPrim(0 to 0),
PLB_MasterID => plb_bus_PLB_masterID(0 to 0),
PLB_abort => plb_bus_PLB_abort,
PLB_busLock => plb_bus_PLB_busLock,
PLB_RNW => plb_bus_PLB_RNW,
PLB_BE => plb_bus_PLB_BE,
PLB_msize => plb_bus_PLB_MSize,
PLB_size => plb_bus_PLB_size,
PLB_type => plb_bus_PLB_type,
PLB_TAttribute => plb_bus_PLB_TAttribute,
PLB_lockErr => plb_bus_PLB_lockErr,
PLB_UABus => plb_bus_PLB_UABus,
PLB_ABus => plb_bus_PLB_ABus,
PLB_wrDBus => plb_bus_PLB_wrDBus,
PLB_wrBurst => plb_bus_PLB_wrBurst,
PLB_rdBurst => plb_bus_PLB_rdBurst,
PLB_rdpendReq => plb_bus_PLB_rdpendReq,
PLB_wrpendReq => plb_bus_PLB_wrpendReq,
PLB_rdpendPri => plb_bus_PLB_rdpendPri,
PLB_wrpendPri => plb_bus_PLB_wrpendPri,
PLB_reqPri => plb_bus_PLB_reqPri,
Sl_addrAck => plb_bus_Sl_addrAck(0 to 0),
Sl_wait => plb_bus_Sl_wait(0 to 0),
Sl_rearbitrate => plb_bus_Sl_rearbitrate(0 to 0),
Sl_wrDAck => plb_bus_Sl_wrDAck(0 to 0),
Sl_wrComp => plb_bus_Sl_wrComp(0 to 0),
Sl_wrBTerm => plb_bus_Sl_wrBTerm(0 to 0),
Sl_rdDBus => plb_bus_Sl_rdDBus,
Sl_rdWdAddr => plb_bus_Sl_rdWdAddr,
Sl_rdDAck => plb_bus_Sl_rdDAck(0 to 0),
Sl_rdComp => plb_bus_Sl_rdComp(0 to 0),
Sl_rdBTerm => plb_bus_Sl_rdBTerm(0 to 0),
Sl_MBusy => plb_bus_Sl_MBusy,
Sl_MRdErr => plb_bus_Sl_MRdErr,
Sl_MWrErr => plb_bus_Sl_MWrErr,
Sl_MIRQ => plb_bus_Sl_MIRQ,
Sl_ssize => plb_bus_Sl_SSize,
PLB_SaddrAck => plb_bus_PLB_SaddrAck,
PLB_Swait => plb_bus_PLB_Swait,
PLB_Srearbitrate => plb_bus_PLB_Srearbitrate,
PLB_SwrDAck => plb_bus_PLB_SwrDAck,
PLB_SwrComp => plb_bus_PLB_SwrComp,
PLB_SwrBTerm => plb_bus_PLB_SwrBTerm,
PLB_SrdDBus => plb_bus_PLB_SrdDBus,
PLB_SrdWdAddr => plb_bus_PLB_SrdWdAddr,
PLB_SrdDAck => plb_bus_PLB_SrdDAck,
PLB_SrdComp => plb_bus_PLB_SrdComp,
PLB_SrdBTerm => plb_bus_PLB_SrdBTerm,
PLB_SMBusy => plb_bus_PLB_SMBusy,
PLB_SMRdErr => plb_bus_PLB_SMRdErr,
PLB_SMWrErr => plb_bus_PLB_SMWrErr,
PLB_SMIRQ => net_gnd2,
PLB_Sssize => plb_bus_PLB_Sssize
);
synch_bus : synch_bus_wrapper
port map (
FROM_SYNCH_OUT => pgassign1,
TO_SYNCH_IN => synch
);
plb_bus : plb_bus_wrapper
port map (
PLB_Clk => sys_clk,
SYS_Rst => sys_reset,
PLB_Rst => plb_bus_PLB_Rst,
SPLB_Rst => open,
MPLB_Rst => plb_bus_MPLB_Rst,
PLB_dcrAck => open,
PLB_dcrDBus => open,
DCR_ABus => net_gnd10,
DCR_DBus => net_gnd32,
DCR_Read => net_gnd0,
DCR_Write => net_gnd0,
M_ABus => plb_bus_M_ABus,
M_UABus => plb_bus_M_UABus,
M_BE => plb_bus_M_BE,
M_RNW => plb_bus_M_RNW,
M_abort => plb_bus_M_abort,
M_busLock => plb_bus_M_busLock,
M_TAttribute => plb_bus_M_TAttribute,
M_lockErr => plb_bus_M_lockErr,
M_MSize => plb_bus_M_MSize,
M_priority => plb_bus_M_priority,
M_rdBurst => plb_bus_M_rdBurst,
M_request => plb_bus_M_request,
M_size => plb_bus_M_size,
M_type => plb_bus_M_type,
M_wrBurst => plb_bus_M_wrBurst,
M_wrDBus => plb_bus_M_wrDBus,
Sl_addrAck => plb_bus_Sl_addrAck(0 to 0),
Sl_MRdErr => plb_bus_Sl_MRdErr,
Sl_MWrErr => plb_bus_Sl_MWrErr,
Sl_MBusy => plb_bus_Sl_MBusy,
Sl_rdBTerm => plb_bus_Sl_rdBTerm(0 to 0),
Sl_rdComp => plb_bus_Sl_rdComp(0 to 0),
Sl_rdDAck => plb_bus_Sl_rdDAck(0 to 0),
Sl_rdDBus => plb_bus_Sl_rdDBus,
Sl_rdWdAddr => plb_bus_Sl_rdWdAddr,
Sl_rearbitrate => plb_bus_Sl_rearbitrate(0 to 0),
Sl_SSize => plb_bus_Sl_SSize,
Sl_wait => plb_bus_Sl_wait(0 to 0),
Sl_wrBTerm => plb_bus_Sl_wrBTerm(0 to 0),
Sl_wrComp => plb_bus_Sl_wrComp(0 to 0),
Sl_wrDAck => plb_bus_Sl_wrDAck(0 to 0),
Sl_MIRQ => plb_bus_Sl_MIRQ,
PLB_MIRQ => plb_bus_PLB_MIRQ,
PLB_ABus => plb_bus_PLB_ABus,
PLB_UABus => plb_bus_PLB_UABus,
PLB_BE => plb_bus_PLB_BE,
PLB_MAddrAck => plb_bus_PLB_MAddrAck,
PLB_MTimeout => plb_bus_PLB_MTimeout,
PLB_MBusy => plb_bus_PLB_MBusy,
PLB_MRdErr => plb_bus_PLB_MRdErr,
PLB_MWrErr => plb_bus_PLB_MWrErr,
PLB_MRdBTerm => plb_bus_PLB_MRdBTerm,
PLB_MRdDAck => plb_bus_PLB_MRdDAck,
PLB_MRdDBus => plb_bus_PLB_MRdDBus,
PLB_MRdWdAddr => plb_bus_PLB_MRdWdAddr,
PLB_MRearbitrate => plb_bus_PLB_MRearbitrate,
PLB_MWrBTerm => plb_bus_PLB_MWrBTerm,
PLB_MWrDAck => plb_bus_PLB_MWrDAck,
PLB_MSSize => plb_bus_PLB_MSSize,
PLB_PAValid => plb_bus_PLB_PAValid,
PLB_RNW => plb_bus_PLB_RNW,
PLB_SAValid => plb_bus_PLB_SAValid,
PLB_abort => plb_bus_PLB_abort,
PLB_busLock => plb_bus_PLB_busLock,
PLB_TAttribute => plb_bus_PLB_TAttribute,
PLB_lockErr => plb_bus_PLB_lockErr,
PLB_masterID => plb_bus_PLB_masterID(0 to 0),
PLB_MSize => plb_bus_PLB_MSize,
PLB_rdPendPri => plb_bus_PLB_rdpendPri,
PLB_wrPendPri => plb_bus_PLB_wrpendPri,
PLB_rdPendReq => plb_bus_PLB_rdpendReq,
PLB_wrPendReq => plb_bus_PLB_wrpendReq,
PLB_rdBurst => plb_bus_PLB_rdBurst,
PLB_rdPrim => plb_bus_PLB_rdPrim(0 to 0),
PLB_reqPri => plb_bus_PLB_reqPri,
PLB_size => plb_bus_PLB_size,
PLB_type => plb_bus_PLB_type,
PLB_wrBurst => plb_bus_PLB_wrBurst,
PLB_wrDBus => plb_bus_PLB_wrDBus,
PLB_wrPrim => plb_bus_PLB_wrPrim(0 to 0),
PLB_SaddrAck => plb_bus_PLB_SaddrAck,
PLB_SMRdErr => plb_bus_PLB_SMRdErr,
PLB_SMWrErr => plb_bus_PLB_SMWrErr,
PLB_SMBusy => plb_bus_PLB_SMBusy,
PLB_SrdBTerm => plb_bus_PLB_SrdBTerm,
PLB_SrdComp => plb_bus_PLB_SrdComp,
PLB_SrdDAck => plb_bus_PLB_SrdDAck,
PLB_SrdDBus => plb_bus_PLB_SrdDBus,
PLB_SrdWdAddr => plb_bus_PLB_SrdWdAddr,
PLB_Srearbitrate => plb_bus_PLB_Srearbitrate,
PLB_Sssize => plb_bus_PLB_Sssize,
PLB_Swait => plb_bus_PLB_Swait,
PLB_SwrBTerm => plb_bus_PLB_SwrBTerm,
PLB_SwrComp => plb_bus_PLB_SwrComp,
PLB_SwrDAck => plb_bus_PLB_SwrDAck,
PLB2OPB_rearb => net_gnd1(0 to 0),
Bus_Error_Det => open
);
my_core : my_core_wrapper
port map (
MPLB_Clk => sys_clk,
MPLB_Rst => plb_bus_MPLB_Rst(1),
M_request => plb_bus_M_request(1),
M_priority => plb_bus_M_priority(2 to 3),
M_busLock => plb_bus_M_busLock(1),
M_RNW => plb_bus_M_RNW(1),
M_BE => plb_bus_M_BE(16 to 31),
M_MSize => plb_bus_M_MSize(2 to 3),
M_size => plb_bus_M_size(4 to 7),
M_type => plb_bus_M_type(3 to 5),
M_TAttribute => plb_bus_M_TAttribute(16 to 31),
M_lockErr => plb_bus_M_lockErr(1),
M_abort => plb_bus_M_abort(1),
M_UABus => plb_bus_M_UABus(32 to 63),
M_ABus => plb_bus_M_ABus(32 to 63),
M_wrDBus => plb_bus_M_wrDBus(128 to 255),
M_wrBurst => plb_bus_M_wrBurst(1),
M_rdBurst => plb_bus_M_rdBurst(1),
PLB_MAddrAck => plb_bus_PLB_MAddrAck(1),
PLB_MSSize => plb_bus_PLB_MSSize(2 to 3),
PLB_MRearbitrate => plb_bus_PLB_MRearbitrate(1),
PLB_MTimeout => plb_bus_PLB_MTimeout(1),
PLB_MBusy => plb_bus_PLB_MBusy(1),
PLB_MRdErr => plb_bus_PLB_MRdErr(1),
PLB_MWrErr => plb_bus_PLB_MWrErr(1),
PLB_MIRQ => plb_bus_PLB_MIRQ(1),
PLB_MRdDBus => plb_bus_PLB_MRdDBus(128 to 255),
PLB_MRdWdAddr => plb_bus_PLB_MRdWdAddr(4 to 7),
PLB_MRdDAck => plb_bus_PLB_MRdDAck(1),
PLB_MRdBTerm => plb_bus_PLB_MRdBTerm(1),
PLB_MWrDAck => plb_bus_PLB_MWrDAck(1),
PLB_MWrBTerm => plb_bus_PLB_MWrBTerm(1),
SYNCH_IN => synch,
SYNCH_OUT => synch3
);
end architecture STRUCTURE;
|
--
-- Environment package for VHDL-2008
--
-- This is also compiled into the NVC library for use with earlier standards
--
package env is
procedure stop(status : integer);
procedure stop;
procedure finish(status : integer);
procedure finish;
function resolution_limit return delay_length;
end package;
package body env is
procedure stop_impl(finish, have_status : boolean; status : integer) is
procedure nvc_env_stop(finish, have_status : boolean; status : integer);
attribute foreign of nvc_env_stop : procedure is "_nvc_env_stop";
begin
nvc_env_stop(finish, have_status, status);
end procedure;
procedure stop(status : integer) is
begin
stop_impl(finish => false, have_status => true, status => status);
end procedure;
procedure stop is
begin
stop_impl(finish => false, have_status => false, status => 0);
end procedure;
procedure finish(status : integer) is
begin
stop_impl(finish => true, have_status => true, status => status);
end procedure;
procedure finish is
begin
stop_impl(finish => true, have_status => false, status => 0);
end procedure;
function resolution_limit return delay_length is
begin
return fs;
end function;
end package body;
|
--
-- Environment package for VHDL-2008
--
-- This is also compiled into the NVC library for use with earlier standards
--
package env is
procedure stop(status : integer);
procedure stop;
procedure finish(status : integer);
procedure finish;
function resolution_limit return delay_length;
end package;
package body env is
procedure stop_impl(finish, have_status : boolean; status : integer) is
procedure nvc_env_stop(finish, have_status : boolean; status : integer);
attribute foreign of nvc_env_stop : procedure is "_nvc_env_stop";
begin
nvc_env_stop(finish, have_status, status);
end procedure;
procedure stop(status : integer) is
begin
stop_impl(finish => false, have_status => true, status => status);
end procedure;
procedure stop is
begin
stop_impl(finish => false, have_status => false, status => 0);
end procedure;
procedure finish(status : integer) is
begin
stop_impl(finish => true, have_status => true, status => status);
end procedure;
procedure finish is
begin
stop_impl(finish => true, have_status => false, status => 0);
end procedure;
function resolution_limit return delay_length is
begin
return fs;
end function;
end package body;
|
--
-- Environment package for VHDL-2008
--
-- This is also compiled into the NVC library for use with earlier standards
--
package env is
procedure stop(status : integer);
procedure stop;
procedure finish(status : integer);
procedure finish;
function resolution_limit return delay_length;
end package;
package body env is
procedure stop_impl(finish, have_status : boolean; status : integer) is
procedure nvc_env_stop(finish, have_status : boolean; status : integer);
attribute foreign of nvc_env_stop : procedure is "_nvc_env_stop";
begin
nvc_env_stop(finish, have_status, status);
end procedure;
procedure stop(status : integer) is
begin
stop_impl(finish => false, have_status => true, status => status);
end procedure;
procedure stop is
begin
stop_impl(finish => false, have_status => false, status => 0);
end procedure;
procedure finish(status : integer) is
begin
stop_impl(finish => true, have_status => true, status => status);
end procedure;
procedure finish is
begin
stop_impl(finish => true, have_status => false, status => 0);
end procedure;
function resolution_limit return delay_length is
begin
return fs;
end function;
end package body;
|
--
-- Environment package for VHDL-2008
--
-- This is also compiled into the NVC library for use with earlier standards
--
package env is
procedure stop(status : integer);
procedure stop;
procedure finish(status : integer);
procedure finish;
function resolution_limit return delay_length;
end package;
package body env is
procedure stop_impl(finish, have_status : boolean; status : integer) is
procedure nvc_env_stop(finish, have_status : boolean; status : integer);
attribute foreign of nvc_env_stop : procedure is "_nvc_env_stop";
begin
nvc_env_stop(finish, have_status, status);
end procedure;
procedure stop(status : integer) is
begin
stop_impl(finish => false, have_status => true, status => status);
end procedure;
procedure stop is
begin
stop_impl(finish => false, have_status => false, status => 0);
end procedure;
procedure finish(status : integer) is
begin
stop_impl(finish => true, have_status => true, status => status);
end procedure;
procedure finish is
begin
stop_impl(finish => true, have_status => false, status => 0);
end procedure;
function resolution_limit return delay_length is
begin
return fs;
end function;
end package body;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Design Name:
-- Module Name: Interrupts - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 1.00 - File Created 14.05.2007
--
-- Revision 1.10 - Msg Tag incremented. 20.07.2007
--
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library work;
use work.abb64Package.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Interrupts is
port (
-- System Interrupt register from Registers module
Sys_IRQ : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Interrupt generator signals
IG_Reset : in std_logic;
IG_Host_Clear : in std_logic;
IG_Latency : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
IG_Num_Assert : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
IG_Num_Deassert : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
IG_Asserting : out std_logic;
-- Interrupt Interface
cfg_interrupt : out std_logic;
cfg_interrupt_rdy : in std_logic;
cfg_interrupt_mmenable : in std_logic_vector(2 downto 0);
cfg_interrupt_msienable : in std_logic;
cfg_interrupt_msixenable : in std_logic;
cfg_interrupt_msixfm : in std_logic;
cfg_interrupt_di : out std_logic_vector(7 downto 0);
cfg_interrupt_do : in std_logic_vector(7 downto 0);
cfg_interrupt_assert : out std_logic;
-- Irpt Channel
Irpt_Req : out std_logic;
Irpt_RE : in std_logic;
Irpt_Qout : out std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
-- Clock and reset
user_clk : in std_logic;
user_reset : in std_logic
);
end Interrupts;
architecture Behavioral of Interrupts is
-- State machine: Interrupt control
type IrptStates is (IntST_RST
, IntST_Idle
, IntST_Asserting
, IntST_Asserted
, IntST_Deasserting
);
signal edge_Intrpt_State : IrptStates;
signal cfg_interrupt_i : std_logic;
signal cfg_interrupt_di_i : std_logic_vector(7 downto 0);
signal cfg_interrupt_assert_i : std_logic;
signal edge_Irpt_Req_i : std_logic;
signal inta_trigger : std_logic;
signal msi_trigger : std_logic;
signal Irpt_RE_i : std_logic;
signal Irpt_Qout_i : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0)
:= (others => '0');
signal Msg_Tag_Lo : std_logic_vector(3 downto 0);
signal Msg_Code : std_logic_vector(7 downto 0);
signal edge_MsgCode_is_ASSERT : std_logic;
signal Interrupts_ORed : std_logic;
signal Interrupts_ORed_r1 : std_logic;
-- Interrupt Generator
signal IG_Trigger_i : std_logic;
-- Interrupt Generator Counter
signal IG_Counter : std_logic_vector(C_CNT_GINT_WIDTH-1 downto 0);
signal IG_Run : std_logic;
-- Interrupt Generator Statistic: Assert number
signal IG_Num_Assert_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Interrupt Generator Statistic: Deassert number
signal IG_Num_Deassert_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Interrupt Generator indicator
signal IG_Asserting_i : std_logic;
begin
-- Interrupt interface
-- cfg_interrupt should be explicitly clarified!
cfg_interrupt_assert <= cfg_interrupt_assert_i;
cfg_interrupt_di <= cfg_interrupt_di_i;
cfg_interrupt_di_i <= (others => '0');
-- Channel mode interface.
Irpt_RE_i <= Irpt_RE;
Irpt_Qout <= Irpt_Qout_i;
-- ---------------------------------------------------
-- emulates a channel buffer output
-- Note: Type not shows in this buffer
--
-- 127 ~ 97 : reserved
-- 96 : reserved
-- 95 : reserved
-- 94 : Valid
-- 93 ~ 35 : reserved
-- 34 ~ 27 : Msg code
-- 26 ~ 19 : Tag
--
-- 18 ~ 17 : Format
-- 16 ~ 14 : TC
-- 13 : TD
-- 12 : EP
-- 11 ~ 10 : Attribute
-- 9 ~ 0 : Length
--
Irpt_Qout_i(C_CHBUF_QVALID_BIT) <= '1';
Irpt_Qout_i(C_CHBUF_TAG_BIT_TOP downto C_CHBUF_TAG_BIT_BOT) <= C_MSG_TAG_HI & Msg_Tag_Lo;
Irpt_Qout_i(C_CHBUF_MSG_CODE_BIT_TOP downto C_CHBUF_MSG_CODE_BIT_BOT) <= Msg_Code;
Irpt_Qout_i(C_CHBUF_FMT_BIT_TOP downto C_CHBUF_FMT_BIT_BOT) <= C_FMT4_NO_DATA;
Irpt_Qout_i(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT) <= C_ALL_ZEROS(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT);
-- ---------------------------------------------------------------
-- All Interrups are OR'ed
--
Syn_Interrupts_ORed :
process (user_clk)
begin
if user_clk'event and user_clk = '1' then
if Sys_IRQ(C_NUM_OF_INTERRUPTS-1 downto 0)
= C_ALL_ZEROS(C_NUM_OF_INTERRUPTS-1 downto 0)
then
Interrupts_ORed <= '0';
else
Interrupts_ORed <= '1';
end if;
Interrupts_ORed_r1 <= Interrupts_ORed;
end if;
end process;
p_irpt_trig:
process (user_clk)
begin
if rising_edge(user_clk) then
inta_trigger <= Interrupts_ORed;
--rising edge, because interrupt handling differs between legacy INTA and MSI
msi_trigger <= Interrupts_ORed and not(Interrupts_ORed_r1);
end if;
end process;
-------------------------------------------
---- Cfg Interface mode
-------------------------------------------
Gen_Cfg_Irpt : if USE_CFG_INTERRUPT generate
cfg_interrupt <= cfg_interrupt_i;
Irpt_Req <= '0'; -- Cfg interface mode, channel disabled.
Msg_Code <= (others => '0');
States_Machine_Irpt :
process (user_clk, user_reset)
begin
if user_reset = '1' then
edge_Intrpt_State <= IntST_RST;
cfg_interrupt_i <= '0';
cfg_interrupt_assert_i <= '0';
elsif user_clk'event and user_clk = '1' then
case edge_Intrpt_State is
when IntST_RST =>
edge_Intrpt_State <= IntST_Idle;
cfg_interrupt_i <= '0';
cfg_interrupt_assert_i <= '0';
when IntST_Idle =>
if (inta_trigger or msi_trigger) = '1' then
edge_Intrpt_State <= IntST_Asserting;
cfg_interrupt_i <= '1';
cfg_interrupt_assert_i <= not(cfg_interrupt_msienable);
else
edge_Intrpt_State <= IntST_Idle;
cfg_interrupt_i <= '0';
cfg_interrupt_assert_i <= '0';
end if;
when IntST_Asserting =>
if cfg_interrupt_rdy = '0' then
edge_Intrpt_State <= IntST_Asserting;
cfg_interrupt_i <= '1';
cfg_interrupt_assert_i <= not(cfg_interrupt_msienable);
else
if cfg_interrupt_msienable = '1' then
edge_Intrpt_State <= IntST_Idle;
else
edge_Intrpt_State <= IntST_Asserted;
end if;
cfg_interrupt_i <= '0';
cfg_interrupt_assert_i <= not(cfg_interrupt_msienable);
end if;
when IntST_Asserted =>
if Interrupts_ORed = '0' then
edge_Intrpt_State <= IntST_Deasserting;
cfg_interrupt_i <= '1';
cfg_interrupt_assert_i <= '0';
else
edge_Intrpt_State <= IntST_Asserted;
cfg_interrupt_i <= '0';
cfg_interrupt_assert_i <= '1';
end if;
when IntST_Deasserting =>
if cfg_interrupt_rdy = '0' then
edge_Intrpt_State <= IntST_Deasserting;
cfg_interrupt_i <= '1';
cfg_interrupt_assert_i <= '0';
else
edge_Intrpt_State <= IntST_Idle;
cfg_interrupt_i <= '0';
cfg_interrupt_assert_i <= '0';
end if;
when others =>
edge_Intrpt_State <= IntST_Idle;
cfg_interrupt_i <= '0';
cfg_interrupt_assert_i <= '0';
end case;
end if;
end process;
end generate;
----------------------------------------------
-- Channel mode
----------------------------------------------
Gen_Chan_MSI : if not USE_CFG_INTERRUPT generate
cfg_interrupt <= '0'; -- Channel mode, cfg interface disabled.
cfg_interrupt_assert_i <= '0';
Irpt_Req <= edge_Irpt_Req_i;
Msg_Code <= C_MSGCODE_INTA when edge_MsgCode_is_ASSERT = '1'
else C_MSGCODE_INTA_N;
-- State Machine for edge interrupts
State_Machine_edge_Irpt :
process (user_clk, user_reset)
begin
if user_reset = '1' then
edge_Intrpt_State <= IntST_RST;
edge_Irpt_Req_i <= '0';
edge_MsgCode_is_ASSERT <= '0';
elsif user_clk'event and user_clk = '1' then
case edge_Intrpt_State is
when IntST_RST =>
edge_Intrpt_State <= IntST_Idle;
edge_Irpt_Req_i <= '0';
edge_MsgCode_is_ASSERT <= '0';
when IntST_Idle =>
if Interrupts_ORed = '1' then
edge_Intrpt_State <= IntST_Asserting;
edge_Irpt_Req_i <= '1';
edge_MsgCode_is_ASSERT <= edge_MsgCode_is_ASSERT; -- '1';
else
edge_Intrpt_State <= IntST_Idle;
edge_Irpt_Req_i <= '0';
edge_MsgCode_is_ASSERT <= edge_MsgCode_is_ASSERT;
end if;
when IntST_Asserting =>
if Irpt_RE_i = '0' then
edge_Intrpt_State <= IntST_Asserting;
edge_Irpt_Req_i <= '1';
edge_MsgCode_is_ASSERT <= edge_MsgCode_is_ASSERT; -- '1';
else
edge_Intrpt_State <= IntST_Asserted;
edge_Irpt_Req_i <= '0';
edge_MsgCode_is_ASSERT <= '1';
end if;
when IntST_Asserted =>
if Interrupts_ORed = '0' then
edge_Intrpt_State <= IntST_Deasserting;
edge_Irpt_Req_i <= '1';
edge_MsgCode_is_ASSERT <= edge_MsgCode_is_ASSERT; -- !!
else
edge_Intrpt_State <= IntST_Asserted;
edge_Irpt_Req_i <= '0';
edge_MsgCode_is_ASSERT <= edge_MsgCode_is_ASSERT; -- '1';
end if;
when IntST_Deasserting =>
if Irpt_RE_i = '0' then
edge_Intrpt_State <= IntST_Deasserting;
edge_Irpt_Req_i <= '1';
edge_MsgCode_is_ASSERT <= edge_MsgCode_is_ASSERT; -- '0';
else
edge_Intrpt_State <= IntST_Idle;
edge_Irpt_Req_i <= '0';
edge_MsgCode_is_ASSERT <= '0';
end if;
when others =>
edge_Intrpt_State <= IntST_Idle;
edge_Irpt_Req_i <= '0';
edge_MsgCode_is_ASSERT <= '0';
end case;
end if;
end process;
-- Tag of Msg TLP increments
Sync_Msg_Tag_Increment :
process (user_clk, user_reset)
begin
if user_reset = '1' then
Msg_Tag_Lo <= (others => '0');
elsif user_clk'event and user_clk = '1' then
if Irpt_RE_i = '1' then
Msg_Tag_Lo <= Msg_Tag_Lo + '1';
else
Msg_Tag_Lo <= Msg_Tag_Lo;
end if;
end if;
end process;
end generate; -- Gen_Chan_MSI: if not USE_CFG_INTERRUPT
--
-------------- Generate Interrupt Generator ------------------
--
Gen_IG : if IMP_INT_GENERATOR generate
IG_Num_Assert <= IG_Num_Assert_i;
IG_Num_Deassert <= IG_Num_Deassert_i;
IG_Asserting <= IG_Asserting_i;
-- -------------------------------------------------------
-- FSM: generating interrupts
FSM_Generate_Interrupts :
process (user_clk, user_reset)
begin
if user_reset = '1' then
IG_Counter <= (others => '0');
elsif user_clk'event and user_clk = '1' then
if IG_Reset = '1' then
IG_Counter <= (others => '0');
elsif IG_Counter /= C_ALL_ZEROS(C_CNT_GINT_WIDTH-1 downto 0) then
IG_Counter <= IG_Counter - '1';
elsif IG_Run = '0' then
IG_Counter <= (others => '0');
else
IG_Counter <= IG_Latency(C_CNT_GINT_WIDTH-1 downto 0);
end if;
end if;
end process;
-- -------------------------------------------------------
-- Issuing: Interrupt trigger
Synch_Interrupt_Trigger :
process (user_clk, user_reset)
begin
if user_reset = '1' then
IG_Trigger_i <= '0';
elsif user_clk'event and user_clk = '1' then
if IG_Reset = '1' then
IG_Trigger_i <= '0';
elsif IG_Counter = CONV_STD_LOGIC_VECTOR(1, C_CNT_GINT_WIDTH) then
IG_Trigger_i <= '1';
else
IG_Trigger_i <= '0';
end if;
end if;
end process;
-- -------------------------------------------------------
-- register: IG_Run
Synch_IG_Run :
process (user_clk, user_reset)
begin
if user_reset = '1' then
IG_Run <= '0';
elsif user_clk'event and user_clk = '1' then
if IG_Reset = '1' then
IG_Run <= '0';
elsif IG_Latency(C_DBUS_WIDTH-1 downto 2) = C_ALL_ZEROS(C_DBUS_WIDTH-1 downto 2) then
IG_Run <= '0';
else
IG_Run <= '1';
end if;
end if;
end process;
-- -----------------------------------------------
-- Synchronous Register: IG_Num_Assert_i
SysReg_IntGen_Number_of_Assert :
process (user_clk, user_reset)
begin
if user_reset = '1' then
IG_Num_Assert_i <= (others => '0');
elsif user_clk'event and user_clk = '1' then
if IG_Reset = '1' then
IG_Num_Assert_i <= (others => '0');
elsif IG_Trigger_i = '1' then
IG_Num_Assert_i <= IG_Num_Assert_i + '1';
else
IG_Num_Assert_i <= IG_Num_Assert_i;
end if;
end if;
end process;
-- -----------------------------------------------
-- Synchronous Register: IG_Num_Deassert_i
SysReg_IntGen_Number_of_Deassert :
process (user_clk, user_reset)
begin
if user_reset = '1' then
IG_Num_Deassert_i <= (others => '0');
elsif user_clk'event and user_clk = '1' then
if IG_Reset = '1' then
IG_Num_Deassert_i <= (others => '0');
elsif IG_Host_Clear = '1' and IG_Asserting_i = '1' then
IG_Num_Deassert_i <= IG_Num_Deassert_i + '1';
else
IG_Num_Deassert_i <= IG_Num_Deassert_i;
end if;
end if;
end process;
-- -----------------------------------------------
-- Synchronous Register: IG_Asserting_i
SysReg_IntGen_IG_Asserting_i :
process (user_clk, user_reset)
begin
if user_reset = '1' then
IG_Asserting_i <= '0';
elsif user_clk'event and user_clk = '1' then
if IG_Reset = '1' then
IG_Asserting_i <= '0';
elsif IG_Asserting_i = '0' and IG_Trigger_i = '1' then
IG_Asserting_i <= '1';
elsif IG_Asserting_i = '0' and IG_Trigger_i = '0' then
IG_Asserting_i <= '0';
elsif IG_Asserting_i = '1' and IG_Host_Clear = '0' then
IG_Asserting_i <= '1';
elsif IG_Asserting_i = '1' and IG_Host_Clear = '1' then
IG_Asserting_i <= '0';
else
IG_Asserting_i <= IG_Asserting_i;
end if;
end if;
end process;
end generate;
--
-------------- No Generation of Interrupt Generator ----------------
--
NotGen_IG : if not IMP_INT_GENERATOR generate
IG_Num_Assert <= (others => '0');
IG_Num_Deassert <= (others => '0');
IG_Asserting <= '0';
end generate;
end Behavioral;
|
LIBRARY Ieee;
USE ieee.std_logic_1164.all;
ENTITY CLGB IS
PORT (
P0, P1, G0, G1, Cin: IN STD_LOGIC;
Cout1, Cout2: OUT STD_LOGIC
);
END CLGB;
ARCHITECTURE strc_CLGB of CLGB is
BEGIN
Cout1 <= G0 OR (P0 AND Cin);
Cout2 <= G1 OR (P1 AND G0) OR (P1 AND P0 AND Cin);
END strc_CLGB; |
LIBRARY Ieee;
USE ieee.std_logic_1164.all;
ENTITY CLGB IS
PORT (
P0, P1, G0, G1, Cin: IN STD_LOGIC;
Cout1, Cout2: OUT STD_LOGIC
);
END CLGB;
ARCHITECTURE strc_CLGB of CLGB is
BEGIN
Cout1 <= G0 OR (P0 AND Cin);
Cout2 <= G1 OR (P1 AND G0) OR (P1 AND P0 AND Cin);
END strc_CLGB; |
LIBRARY Ieee;
USE ieee.std_logic_1164.all;
ENTITY CLGB IS
PORT (
P0, P1, G0, G1, Cin: IN STD_LOGIC;
Cout1, Cout2: OUT STD_LOGIC
);
END CLGB;
ARCHITECTURE strc_CLGB of CLGB is
BEGIN
Cout1 <= G0 OR (P0 AND Cin);
Cout2 <= G1 OR (P1 AND G0) OR (P1 AND P0 AND Cin);
END strc_CLGB; |
LIBRARY Ieee;
USE ieee.std_logic_1164.all;
ENTITY CLGB IS
PORT (
P0, P1, G0, G1, Cin: IN STD_LOGIC;
Cout1, Cout2: OUT STD_LOGIC
);
END CLGB;
ARCHITECTURE strc_CLGB of CLGB is
BEGIN
Cout1 <= G0 OR (P0 AND Cin);
Cout2 <= G1 OR (P1 AND G0) OR (P1 AND P0 AND Cin);
END strc_CLGB; |
LIBRARY Ieee;
USE ieee.std_logic_1164.all;
ENTITY CLGB IS
PORT (
P0, P1, G0, G1, Cin: IN STD_LOGIC;
Cout1, Cout2: OUT STD_LOGIC
);
END CLGB;
ARCHITECTURE strc_CLGB of CLGB is
BEGIN
Cout1 <= G0 OR (P0 AND Cin);
Cout2 <= G1 OR (P1 AND G0) OR (P1 AND P0 AND Cin);
END strc_CLGB; |
-------------------------------------------------------------------------------
-- $Id: opb_v20.vhd,v 1.1.2.1 2009/10/06 21:15:01 gburch Exp $
-------------------------------------------------------------------------------
-- opb_v20.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: opb_v20.vhd
-- Version: v1.10c
-- Description: IBM OPB (On-chip Peripheral Bus) implementation
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- opb_v20.vhd
-- -- opb_arbiter.vhd
--
--VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- BEGIN_CHANGELOG EDK_Gmm_SP2
-- Upgraded the IP with opb_ipif_v3_01_a
-- END_CHANGELOG
-------------------------------------------------------------------------------
-- BEGIN_CHANGELOG EDK_Im_SP1
--
-- Modified the files below for the processes MASTER_LOOP and MASTERLOOP to
-- remove the latch it was creating:
-- 1) priority_register_logic.vhd
-- 2) arbitration_logic.vhd
-- These modules are present in the opb_arbiter_v1_02_e.
--
-- END_CHANGELOG
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- History:
-- BLT 2001-05-23 First Version
-- ^^^^^^
-- First version of OPB Bus.
-- ~~~~~~
-- BLT 2002-01-08 Added WDT Reset
-- BLT 2002-05-02 Added instantiation of opb_arbiter
-- ALS 2003-01-07 Instantiated opb_arbiter_v1_02_d to optimize
-- opb_timeout (registered it)
-- bsbrao 2004-09-27 Upgraded the arbiter IP with opb_ipif_v3_01_a
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library opb_v20_v1_10_d;
use opb_v20_v1_10_d.or_gate;
use opb_v20_v1_10_d.opb_arbiter;
library Unisim;
use Unisim.vcomponents.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_USE_LUT_OR -- Use LUT-based OR instead of MUXCY-based OR
-- C_EXT_RESET_HIGH -- External reset is active high
-- C_BASEADDR -- OPB Arbiter base address
-- C_HIGHADDR -- OPB Arbiter high address
-- C_NUM_MASTERS -- number of OPB masters
-- C_NUM_SLAVES -- number of OPB slaves (external to opb_v20)
-- Do not include the slave interface of the
-- opb_arbiter (if present) in this total.
-- C_OPB_DWIDTH -- width of OPB data bus
-- C_OPB_AWIDTH -- width of OPB address bus
-- C_DYNAM_PRIORITY -- dynamic or fixed priority
-- C_REG_GRANTS -- registered or combinational grant outputs
-- C_PARK -- bus parking
-- C_PROC_INTRFCE -- OPB slave interface
-- C_DEV_BLK_ID -- device block id
-- C_DEV_MIR_ENABLE -- IPIF mirror capability enable
--
-- Definition of Ports:
-- See OPB specification V2.0
--
-- input SYS_Rst -- System reset
-- input Debug_SYS_Rst -- Reset from JTAG UART for reseting from debugger
-- input WDT_Rst -- Reset from Watchdog Timer
-- input OPB_Clk -- OPB Clock
-- output OPB_Rst -- Reset out to OPB bus
--
-- -- Master outputs
-- input M_ABus -- master address
-- input M_BE -- master byte enables
-- input M_beXfer -- master byte enable transfer
-- input M_busLock -- master buslock
-- input M_DBus -- master databus
-- input M_DBusEn -- master databus enable
-- input M_DBusEn32_63 -- master databus enable for data bits 32:63
-- input M_dwXfer -- master double word transfer
-- input M_fwXfer -- master fullword transfer
-- input M_hwXfer -- master halfword transfer
-- input M_request -- master request
-- input M_RNW -- master read/not write
-- input M_select -- master select
-- input M_seqAddr -- master sequential address
-- -- Slave outputs
-- input Sl_beAck -- slave byte enable acknowledge
-- input Sl_DBus -- slave databus
-- input Sl_DBusEn -- slave databus enable
-- input Sl_DBusEn32_63 -- slave databus enable for data bits 32:63
-- input Sl_errAck -- slave error acknowledge
-- input Sl_dwAck -- slave doubleword acknowledge
-- input Sl_fwAck -- slave fullword acknowledge
-- input Sl_hwAck -- slave halfword acknowledge
-- input Sl_retry -- slave retry
-- input Sl_toutSup -- slave timeout suppress
-- input Sl_xferAck -- slave transfer acknowledge
--
-- -- OPB outputs
-- output OPB_MRequest -- OPB request
-- output OPB_ABus -- OPB address
-- output OPB_BE -- OPB byte enables
-- output OPB_beXfer -- OPB byte enable transfer
-- output OPB_beAck -- OPB
-- output OPB_busLock -- OPB buslock
-- output OPB_rdDBus -- OPB read databus
-- output OPB_wrDBus -- OPB write databus
-- output OPB_DBus -- OPB databus
-- output OPB_errAck -- OPB error acknowledge
-- output OPB_dwAck -- OPB doubleword acknowledge
-- output OPB_dwXfer -- OPB doubleword transfer
-- output OPB_fwAck -- OPB fullword acknowledge
-- output OPB_fwXfer -- OPB fullword transfer
-- output OPB_hwAck -- OPB halfword acknowledge
-- output OPB_hwXfer -- OPB halfword transfer
-- output OPB_MGrant -- OPB master grant
-- output OPB_pendReq -- OPB pending request
-- output OPB_retry -- OPB retry
-- output OPB_RNW -- OPB read/not write
-- output OPB_select -- OPB select
-- output OPB_seqAddr -- OPB sequential address
-- output OPB_timeout -- OPB timeout
-- output OPB_toutSup -- OPB timeout suppress
-- output OPB_xferAck -- OPB transfer acknowledge
--
-- OPB V2.0 Specification exceptions:
--
-- 1. DMA_SlnAck and Sln_dmaReq are not used.
-- 2. Mn_UABus and OPB_UABus are not used since the address bus width is
-- a parameter.
-- 3. M_DBusEn, M_DBusEn32_64, Sl_DBusEn, and Sl_DBusEn32_63 have no function
-- since we require all masters and slaves to drive zero if they are
-- inactive. All AND'ing with select, etc., is done in the master or slave
-- so that the AND is not required in the bus implementation.
-- 4. The OPB_DBus has been split into two intermediate buses, OPB_wrDBus and
-- OPB_rdDBus, for more efficient implementation in FPGA. The OPB_DBus is
-- the OR of these two intermediate buses.
-- 5. OPB_xferAck and OPB_retry MUST be asserted within 15 clock cycles
-- cycles (by the rising edge of the 16th clock) and OPB_toutSup must be
-- asserted by the rising edge of the 14th clock so that OPB_timeout
-- can be registered and FPGA timing is improved
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity opb_v20 is
generic (
-- Bus interconnect generics
C_OPB_AWIDTH : integer := 32;
C_OPB_DWIDTH : integer := 32;
C_NUM_MASTERS : integer := 8;
C_NUM_SLAVES : integer := 4;
C_USE_LUT_OR : integer := 0;
C_EXT_RESET_HIGH : integer := 1;
-- Arbiter generics
C_BASEADDR : std_logic_vector := X"10000000";
C_HIGHADDR : std_logic_vector := X"100001FF";
C_DYNAM_PRIORITY : integer := 1;
C_PARK : integer := 1;
C_PROC_INTRFCE : integer := 1;
C_REG_GRANTS : integer := 1;
C_DEV_BLK_ID : integer := 0;
C_DEV_MIR_ENABLE : integer := 0
);
port (
-- Clock and reset
SYS_Rst : in std_logic;
Debug_SYS_Rst : in std_logic;
WDT_Rst : in std_logic;
OPB_Clk : in std_logic;
OPB_Rst : out std_logic;
-- Master outputs
M_ABus : in std_logic_vector(0 to C_OPB_AWIDTH*C_NUM_MASTERS-1)
:= (others => '0');
M_BE : in std_logic_vector(0 to
(C_OPB_DWIDTH+7)/8*C_NUM_MASTERS-1) := (others => '0');
M_beXfer : in std_logic_vector(0 to C_NUM_MASTERS-1)
:= (others => '0');
M_busLock : in std_logic_vector(0 to C_NUM_MASTERS-1)
:= (others => '0');
M_DBus : in std_logic_vector(0 to C_OPB_DWIDTH*C_NUM_MASTERS-1)
:= (others => '0');
M_DBusEn : in std_logic_vector(0 to C_NUM_MASTERS-1)
:= (others => '1');
M_DBusEn32_63 : in std_logic_vector(0 to C_NUM_MASTERS-1)
:= (others => '1');
M_dwXfer : in std_logic_vector(0 to C_NUM_MASTERS-1)
:= (others => '0');
M_fwXfer : in std_logic_vector(0 to C_NUM_MASTERS-1)
:= (others => '0');
M_hwXfer : in std_logic_vector(0 to C_NUM_MASTERS-1)
:= (others => '0');
M_request : in std_logic_vector(0 to C_NUM_MASTERS-1)
:= (others => '0');
M_RNW : in std_logic_vector(0 to C_NUM_MASTERS-1)
:= (others => '0');
M_select : in std_logic_vector(0 to C_NUM_MASTERS-1)
:= (others => '0');
M_seqAddr : in std_logic_vector(0 to C_NUM_MASTERS-1)
:= (others => '0');
-- Slave outputs
Sl_beAck : in std_logic_vector(0 to C_NUM_SLAVES-1)
:= (others => '0');
Sl_DBus : in std_logic_vector(0 to C_OPB_DWIDTH*
C_NUM_SLAVES-1)
:= (others => '0');
Sl_DBusEn : in std_logic_vector(0 to C_NUM_SLAVES-1)
:= (others => '1');
Sl_DBusEn32_63 : in std_logic_vector(0 to C_NUM_SLAVES-1)
:= (others => '1');
Sl_errAck : in std_logic_vector(0 to C_NUM_SLAVES-1)
:= (others => '0');
Sl_dwAck : in std_logic_vector(0 to C_NUM_SLAVES-1)
:= (others => '0');
Sl_fwAck : in std_logic_vector(0 to C_NUM_SLAVES-1)
:= (others => '0');
Sl_hwAck : in std_logic_vector(0 to C_NUM_SLAVES-1)
:= (others => '0');
Sl_retry : in std_logic_vector(0 to C_NUM_SLAVES-1)
:= (others => '0');
Sl_toutSup : in std_logic_vector(0 to C_NUM_SLAVES-1)
:= (others => '0');
Sl_xferAck : in std_logic_vector(0 to C_NUM_SLAVES-1)
:= (others => '0');
-- OPB outputs
OPB_MRequest : out std_logic_vector(0 to C_NUM_MASTERS-1);
OPB_ABus : out std_logic_vector(0 to C_OPB_AWIDTH-1);
OPB_BE : out std_logic_vector(0 to (C_OPB_DWIDTH+7)/8-1);
OPB_beXfer : out std_logic;
OPB_beAck : out std_logic;
OPB_busLock : out std_logic;
OPB_rdDBus : out std_logic_vector(0 to C_OPB_DWIDTH-1); -- extra
OPB_wrDBus : out std_logic_vector(0 to C_OPB_DWIDTH-1); -- extra
OPB_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
OPB_errAck : out std_logic;
OPB_dwAck : out std_logic;
OPB_dwXfer : out std_logic;
OPB_fwAck : out std_logic;
OPB_fwXfer : out std_logic;
OPB_hwAck : out std_logic;
OPB_hwXfer : out std_logic;
OPB_MGrant : out std_logic_vector(0 to C_NUM_MASTERS-1);
OPB_pendReq : out std_logic_vector(0 to C_NUM_MASTERS-1);
OPB_retry : out std_logic;
OPB_RNW : out std_logic;
OPB_select : out std_logic;
OPB_seqAddr : out std_logic;
OPB_timeout : out std_logic;
OPB_toutSup : out std_logic;
OPB_xferAck : out std_logic
);
end entity opb_v20;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of opb_v20 is
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Function declarations
-----------------------------------------------------------------------------
function Integer_to_Boolean (x: integer) return boolean is
begin
if x=0 then return false;
else return true;
end if;
end function Integer_to_Boolean;
-----------------------------------------------------------------------------
-- Constant declarations
-----------------------------------------------------------------------------
constant C_USE_LUT_OR_B : boolean := Integer_to_Boolean(C_USE_LUT_OR);
-----------------------------------------------------------------------------
-- Signal declarations
-----------------------------------------------------------------------------
signal arb_timeout : std_logic := '0';
signal arb_mgrant : std_logic_vector(0 to C_NUM_MASTERS-1);
signal arb_dbus : std_logic_vector(0 to C_OPB_DWIDTH-1);
signal arb_errack : std_logic;
signal arb_retry : std_logic;
signal arb_toutsup : std_logic;
signal arb_xferack : std_logic;
signal opb_DBus_inputs : std_logic_vector(0 to 2*C_OPB_DWIDTH-1);
signal iOPB_wrDBus : std_logic_vector(0 to C_OPB_DWIDTH-1);
signal iOPB_rdDBus : std_logic_vector(0 to C_OPB_DWIDTH-1);
signal iOPB_beXfer : std_logic_vector(0 to 0);
signal iOPB_beAck : std_logic_vector(0 to 0);
signal iOPB_busLock : std_logic_vector(0 to 0);
signal iOPB_errAck : std_logic_vector(0 to 0);
signal iOPB_dwAck : std_logic_vector(0 to 0);
signal iOPB_dwXfer : std_logic_vector(0 to 0);
signal iOPB_fwAck : std_logic_vector(0 to 0);
signal iOPB_fwXfer : std_logic_vector(0 to 0);
signal iOPB_hwAck : std_logic_vector(0 to 0);
signal iOPB_hwXfer : std_logic_vector(0 to 0);
signal iOPB_retry : std_logic_vector(0 to 0);
signal iOPB_RNW : std_logic_vector(0 to 0);
signal iOPB_select : std_logic_vector(0 to 0);
signal iOPB_seqAddr : std_logic_vector(0 to 0);
signal iOPB_toutSup : std_logic_vector(0 to 0);
signal iOPB_xferAck : std_logic_vector(0 to 0);
signal iOPB_Rst : std_logic;
signal iOPB_ABus : std_logic_vector(0 to C_OPB_AWIDTH-1);
signal iOPB_BE : std_logic_vector(0 to C_OPB_DWIDTH/8-1);
signal srl_time_out : std_logic;
signal sys_rst_i : std_logic;
-----------------------------------------------------------------------------
-- Attribute declarations
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin -- architecture imp
--------------------------------------------------------------------------------
-- Power On Reset to OPB
--------------------------------------------------------------------------------
SYS_RST_PROC: process (SYS_Rst,WDT_Rst,Debug_SYS_Rst) is
variable sys_rst_input : std_logic;
begin
if C_EXT_RESET_HIGH = 0 then
sys_rst_input := not SYS_Rst;
else
sys_rst_input := SYS_Rst;
end if;
sys_rst_i <= sys_rst_input or WDT_Rst or Debug_SYS_Rst;
end process SYS_RST_PROC;
POR_SRL_I: SRL16
-- synthesis translate_off
generic map (
INIT => X"FFFF")
-- synthesis translate_on
port map (
D => '0',
CLK => OPB_Clk,
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
Q => srl_time_out);
POR_FF_I: FDS
port map (
Q => iOPB_Rst,
D => srl_time_out,
C => OPB_Clk,
S => sys_rst_i);
OPB_MRequest <= M_request; -- pass the Master request through
OPB_ABus_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_MASTERS,C_OPB_AWIDTH,C_USE_LUT_OR_B)
port map (M_ABus,iOPB_ABus);
OPB_BE_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_MASTERS,(C_OPB_DWIDTH+7)/8,
C_USE_LUT_OR_B)
port map (M_BE,iOPB_BE);
OPB_beXfer_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_MASTERS,1,C_USE_LUT_OR_B)
port map (M_beXfer,iOPB_beXfer);
OPB_busLock_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_MASTERS,1,C_USE_LUT_OR_B)
port map (M_busLock,iOPB_busLock);
-- The following two signals are not part of the V2.0 spec but are
-- intermediate buses that are OR'ed to form OPB_DBus. They can be
-- used in an implementation to optimize the master and slave OR
-- functions by breaking up the OPB_DBus OR gate.
OPB_wrDBus_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_MASTERS,C_OPB_DWIDTH,C_USE_LUT_OR_B)
port map (M_DBus,iOPB_wrDBus);
opb_DBus_inputs <= iOPB_wrDBus & iOPB_rdDBus;
OPB_rdDBus <= iOPB_rdDBus;
OPB_wrDBus <= iOPB_wrDBus;
OPB_DBus_I: entity opb_v20_v1_10_d.or_gate generic map (2,C_OPB_DWIDTH,C_USE_LUT_OR_B)
port map (opb_DBus_inputs,OPB_DBus);
OPB_dwXfer_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_MASTERS,1,C_USE_LUT_OR_B)
port map (M_dwXfer,iOPB_dwXfer);
OPB_fwXfer_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_MASTERS,1,C_USE_LUT_OR_B)
port map (M_fwXfer,iOPB_fwXfer);
OPB_hwXfer_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_MASTERS,1,C_USE_LUT_OR_B)
port map (M_hwXfer,iOPB_hwXfer);
OPB_MGrant <= arb_mgrant;
-- OPB_pendReq is generated by OR'ing all master requests except
-- a master's own request. It indicates to a master that one or
-- more of the other masters attached to the bus is requesting
-- access.
MORE_THAN_ONE_MASTER_GEN: if C_NUM_MASTERS > 1 generate
OPB_pendReq_GEN: for i in 0 to C_NUM_MASTERS-1 generate
signal or_gate_input : std_logic_vector(0 to C_NUM_MASTERS-2);
begin
OR_ALL_BUT_SELF_PROCESS: process (M_request) is
variable k : integer := 0;
begin
for j in 0 to i-1 loop
or_gate_input(j) <= M_request(j);
end loop;
for j in i+1 to C_NUM_MASTERS-1 loop
or_gate_input(j-1) <= M_request(j);
end loop;
end process OR_ALL_BUT_SELF_PROCESS;
OPB_pendReq_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_MASTERS-1,1,C_USE_LUT_OR_B)
port map (or_gate_input,OPB_pendReq(i to i));
end generate OPB_pendReq_GEN;
end generate MORE_THAN_ONE_MASTER_GEN;
ONLY_ONE_MASTER_GEN: if C_NUM_MASTERS = 1 generate
OPB_pendReq(0) <= '0';
end generate ONLY_ONE_MASTER_GEN;
OPB_RNW_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_MASTERS,1,C_USE_LUT_OR_B)
port map (M_RNW,iOPB_RNW);
OPB_select_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_MASTERS,1,C_USE_LUT_OR_B)
port map (M_select,iOPB_select);
OPB_seqAddr_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_MASTERS,1,C_USE_LUT_OR_B)
port map (M_seqAddr,iOPB_seqAddr);
OPB_hwAck_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_SLAVES,1,C_USE_LUT_OR_B)
port map (Sl_hwAck,iOPB_hwAck);
OPB_fwAck_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_SLAVES,1,C_USE_LUT_OR_B)
port map (Sl_fwAck,iOPB_fwAck);
OPB_dwAck_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_SLAVES,1,C_USE_LUT_OR_B)
port map (Sl_dwAck,iOPB_dwAck);
OPB_beAck_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_SLAVES,1,C_USE_LUT_OR_B)
port map (Sl_beAck,iOPB_beAck);
OPB_timeout <= Arb_timeout; -- pass the Timeout through
--------------------------------------------------------------------------------
-- The following signals must be generated conditionally based on the
-- state of C_PROC_INTRFCE
--------------------------------------------------------------------------------
ARBITER_HAS_PROC_INTF: if C_PROC_INTRFCE /= 0 generate
signal sl_plus_arb_dbus : std_logic_vector(0 to ((C_NUM_SLAVES+1)*C_OPB_DWIDTH)-1);
signal sl_plus_arb_errack : std_logic_vector(0 to C_NUM_SLAVES);
signal sl_plus_arb_retry : std_logic_vector(0 to C_NUM_SLAVES);
signal sl_plus_arb_toutsup : std_logic_vector(0 to C_NUM_SLAVES);
signal sl_plus_arb_xferack : std_logic_vector(0 to C_NUM_SLAVES);
begin
sl_plus_arb_dbus <= Sl_DBus & arb_dbus;
sl_plus_arb_errack <= Sl_errAck & arb_errack;
sl_plus_arb_retry <= Sl_retry & arb_retry;
sl_plus_arb_toutsup <= Sl_toutSup & arb_toutsup;
sl_plus_arb_xferack <= Sl_xferAck & arb_xferack;
OPB_toutSup_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_SLAVES+1,1,C_USE_LUT_OR_B)
port map (sl_plus_arb_toutsup,iOPB_toutSup);
OPB_xferAck_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_SLAVES+1,1,C_USE_LUT_OR_B)
port map (sl_plus_arb_xferack,iOPB_xferAck);
OPB_retry_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_SLAVES+1,1,C_USE_LUT_OR_B)
port map (sl_plus_arb_retry,iOPB_retry);
OPB_errAck_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_SLAVES+1,1,C_USE_LUT_OR_B)
port map (sl_plus_arb_errack,iOPB_errAck);
OPB_rdDBus_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_SLAVES+1,C_OPB_DWIDTH,C_USE_LUT_OR_B)
port map (sl_plus_arb_dbus,iOPB_rdDBus);
end generate ARBITER_HAS_PROC_INTF;
ARBITER_HAS_NO_PROC_INTF: if C_PROC_INTRFCE = 0 generate
begin
OPB_toutSup_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_SLAVES,1,C_USE_LUT_OR_B)
port map (Sl_toutSup,iOPB_toutSup);
OPB_xferAck_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_SLAVES,1,C_USE_LUT_OR_B)
port map (Sl_xferAck,iOPB_xferAck);
OPB_retry_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_SLAVES,1,C_USE_LUT_OR_B)
port map (Sl_retry,iOPB_retry);
OPB_errAck_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_SLAVES,1,C_USE_LUT_OR_B)
port map (Sl_errAck,iOPB_errAck);
OPB_rdDBus_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_SLAVES,C_OPB_DWIDTH,C_USE_LUT_OR_B)
port map (Sl_DBus,iOPB_rdDBus);
end generate ARBITER_HAS_NO_PROC_INTF;
OPB_beXfer <= iOPB_beXfer(0);
OPB_beAck <= iOPB_beAck(0);
OPB_busLock <= iOPB_busLock(0);
OPB_errAck <= iOPB_errAck(0);
OPB_dwAck <= iOPB_dwAck(0);
OPB_dwXfer <= iOPB_dwXfer(0);
OPB_fwAck <= iOPB_fwAck(0);
OPB_fwXfer <= iOPB_fwXfer(0);
OPB_hwAck <= iOPB_hwAck(0);
OPB_hwXfer <= iOPB_hwXfer(0);
OPB_retry <= iOPB_retry(0);
OPB_RNW <= iOPB_RNW(0);
OPB_select <= iOPB_select(0);
OPB_seqAddr <= iOPB_seqAddr(0);
OPB_toutSup <= iOPB_toutSup(0);
OPB_xferAck <= iOPB_xferAck(0);
OPB_Rst <= iOPB_Rst;
OPB_ABus <= iOPB_ABus;
OPB_BE <= iOPB_BE;
OPB_ARBITER_I : entity opb_v20_v1_10_d.opb_arbiter
generic map (
C_BASEADDR => C_BASEADDR,
C_HIGHADDR => C_HIGHADDR,
C_NUM_MASTERS => C_NUM_MASTERS,
C_OPB_DWIDTH => C_OPB_DWIDTH,
C_OPB_AWIDTH => C_OPB_AWIDTH,
C_DYNAM_PRIORITY => C_DYNAM_PRIORITY,
C_REG_GRANTS => C_REG_GRANTS,
C_PARK => C_PARK,
C_PROC_INTRFCE => C_PROC_INTRFCE,
C_DEV_BLK_ID => C_DEV_BLK_ID,
C_DEV_MIR_ENABLE => C_DEV_MIR_ENABLE)
port map (
ARB_DBus => arb_dbus,
ARB_ErrAck => arb_errack,
ARB_Retry => arb_retry,
ARB_ToutSup => arb_toutsup,
ARB_XferAck => arb_xferack,
OPB_Clk => OPB_clk,
M_request => M_request,
OPB_Abus => iOPB_ABus,
OPB_BE => iOPB_BE,
OPB_buslock => iOPB_busLock(0),
OPB_Dbus => iOPB_wrDBus,
OPB_MGrant => arb_mgrant,
OPB_retry => iOPB_retry(0),
OPB_RNW => iOPB_rnw(0),
OPB_select => iOPB_select(0),
OPB_seqAddr => iOPB_seqaddr(0),
OPB_timeout => arb_timeout,
OPB_toutSup => iOPB_toutsup(0),
OPB_xferAck => iOPB_xferack(0),
OPB_Rst => iOPB_Rst);
end architecture imp;
|
-------------------------------------------------------------------------------
-- $Id: opb_v20.vhd,v 1.1.2.1 2009/10/06 21:15:01 gburch Exp $
-------------------------------------------------------------------------------
-- opb_v20.vhd - entity/architecture pair
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: opb_v20.vhd
-- Version: v1.10c
-- Description: IBM OPB (On-chip Peripheral Bus) implementation
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- opb_v20.vhd
-- -- opb_arbiter.vhd
--
--VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- BEGIN_CHANGELOG EDK_Gmm_SP2
-- Upgraded the IP with opb_ipif_v3_01_a
-- END_CHANGELOG
-------------------------------------------------------------------------------
-- BEGIN_CHANGELOG EDK_Im_SP1
--
-- Modified the files below for the processes MASTER_LOOP and MASTERLOOP to
-- remove the latch it was creating:
-- 1) priority_register_logic.vhd
-- 2) arbitration_logic.vhd
-- These modules are present in the opb_arbiter_v1_02_e.
--
-- END_CHANGELOG
-------------------------------------------------------------------------------
-- Author: B.L. Tise
-- History:
-- BLT 2001-05-23 First Version
-- ^^^^^^
-- First version of OPB Bus.
-- ~~~~~~
-- BLT 2002-01-08 Added WDT Reset
-- BLT 2002-05-02 Added instantiation of opb_arbiter
-- ALS 2003-01-07 Instantiated opb_arbiter_v1_02_d to optimize
-- opb_timeout (registered it)
-- bsbrao 2004-09-27 Upgraded the arbiter IP with opb_ipif_v3_01_a
--
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library opb_v20_v1_10_d;
use opb_v20_v1_10_d.or_gate;
use opb_v20_v1_10_d.opb_arbiter;
library Unisim;
use Unisim.vcomponents.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_USE_LUT_OR -- Use LUT-based OR instead of MUXCY-based OR
-- C_EXT_RESET_HIGH -- External reset is active high
-- C_BASEADDR -- OPB Arbiter base address
-- C_HIGHADDR -- OPB Arbiter high address
-- C_NUM_MASTERS -- number of OPB masters
-- C_NUM_SLAVES -- number of OPB slaves (external to opb_v20)
-- Do not include the slave interface of the
-- opb_arbiter (if present) in this total.
-- C_OPB_DWIDTH -- width of OPB data bus
-- C_OPB_AWIDTH -- width of OPB address bus
-- C_DYNAM_PRIORITY -- dynamic or fixed priority
-- C_REG_GRANTS -- registered or combinational grant outputs
-- C_PARK -- bus parking
-- C_PROC_INTRFCE -- OPB slave interface
-- C_DEV_BLK_ID -- device block id
-- C_DEV_MIR_ENABLE -- IPIF mirror capability enable
--
-- Definition of Ports:
-- See OPB specification V2.0
--
-- input SYS_Rst -- System reset
-- input Debug_SYS_Rst -- Reset from JTAG UART for reseting from debugger
-- input WDT_Rst -- Reset from Watchdog Timer
-- input OPB_Clk -- OPB Clock
-- output OPB_Rst -- Reset out to OPB bus
--
-- -- Master outputs
-- input M_ABus -- master address
-- input M_BE -- master byte enables
-- input M_beXfer -- master byte enable transfer
-- input M_busLock -- master buslock
-- input M_DBus -- master databus
-- input M_DBusEn -- master databus enable
-- input M_DBusEn32_63 -- master databus enable for data bits 32:63
-- input M_dwXfer -- master double word transfer
-- input M_fwXfer -- master fullword transfer
-- input M_hwXfer -- master halfword transfer
-- input M_request -- master request
-- input M_RNW -- master read/not write
-- input M_select -- master select
-- input M_seqAddr -- master sequential address
-- -- Slave outputs
-- input Sl_beAck -- slave byte enable acknowledge
-- input Sl_DBus -- slave databus
-- input Sl_DBusEn -- slave databus enable
-- input Sl_DBusEn32_63 -- slave databus enable for data bits 32:63
-- input Sl_errAck -- slave error acknowledge
-- input Sl_dwAck -- slave doubleword acknowledge
-- input Sl_fwAck -- slave fullword acknowledge
-- input Sl_hwAck -- slave halfword acknowledge
-- input Sl_retry -- slave retry
-- input Sl_toutSup -- slave timeout suppress
-- input Sl_xferAck -- slave transfer acknowledge
--
-- -- OPB outputs
-- output OPB_MRequest -- OPB request
-- output OPB_ABus -- OPB address
-- output OPB_BE -- OPB byte enables
-- output OPB_beXfer -- OPB byte enable transfer
-- output OPB_beAck -- OPB
-- output OPB_busLock -- OPB buslock
-- output OPB_rdDBus -- OPB read databus
-- output OPB_wrDBus -- OPB write databus
-- output OPB_DBus -- OPB databus
-- output OPB_errAck -- OPB error acknowledge
-- output OPB_dwAck -- OPB doubleword acknowledge
-- output OPB_dwXfer -- OPB doubleword transfer
-- output OPB_fwAck -- OPB fullword acknowledge
-- output OPB_fwXfer -- OPB fullword transfer
-- output OPB_hwAck -- OPB halfword acknowledge
-- output OPB_hwXfer -- OPB halfword transfer
-- output OPB_MGrant -- OPB master grant
-- output OPB_pendReq -- OPB pending request
-- output OPB_retry -- OPB retry
-- output OPB_RNW -- OPB read/not write
-- output OPB_select -- OPB select
-- output OPB_seqAddr -- OPB sequential address
-- output OPB_timeout -- OPB timeout
-- output OPB_toutSup -- OPB timeout suppress
-- output OPB_xferAck -- OPB transfer acknowledge
--
-- OPB V2.0 Specification exceptions:
--
-- 1. DMA_SlnAck and Sln_dmaReq are not used.
-- 2. Mn_UABus and OPB_UABus are not used since the address bus width is
-- a parameter.
-- 3. M_DBusEn, M_DBusEn32_64, Sl_DBusEn, and Sl_DBusEn32_63 have no function
-- since we require all masters and slaves to drive zero if they are
-- inactive. All AND'ing with select, etc., is done in the master or slave
-- so that the AND is not required in the bus implementation.
-- 4. The OPB_DBus has been split into two intermediate buses, OPB_wrDBus and
-- OPB_rdDBus, for more efficient implementation in FPGA. The OPB_DBus is
-- the OR of these two intermediate buses.
-- 5. OPB_xferAck and OPB_retry MUST be asserted within 15 clock cycles
-- cycles (by the rising edge of the 16th clock) and OPB_toutSup must be
-- asserted by the rising edge of the 14th clock so that OPB_timeout
-- can be registered and FPGA timing is improved
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Entity section
-----------------------------------------------------------------------------
entity opb_v20 is
generic (
-- Bus interconnect generics
C_OPB_AWIDTH : integer := 32;
C_OPB_DWIDTH : integer := 32;
C_NUM_MASTERS : integer := 8;
C_NUM_SLAVES : integer := 4;
C_USE_LUT_OR : integer := 0;
C_EXT_RESET_HIGH : integer := 1;
-- Arbiter generics
C_BASEADDR : std_logic_vector := X"10000000";
C_HIGHADDR : std_logic_vector := X"100001FF";
C_DYNAM_PRIORITY : integer := 1;
C_PARK : integer := 1;
C_PROC_INTRFCE : integer := 1;
C_REG_GRANTS : integer := 1;
C_DEV_BLK_ID : integer := 0;
C_DEV_MIR_ENABLE : integer := 0
);
port (
-- Clock and reset
SYS_Rst : in std_logic;
Debug_SYS_Rst : in std_logic;
WDT_Rst : in std_logic;
OPB_Clk : in std_logic;
OPB_Rst : out std_logic;
-- Master outputs
M_ABus : in std_logic_vector(0 to C_OPB_AWIDTH*C_NUM_MASTERS-1)
:= (others => '0');
M_BE : in std_logic_vector(0 to
(C_OPB_DWIDTH+7)/8*C_NUM_MASTERS-1) := (others => '0');
M_beXfer : in std_logic_vector(0 to C_NUM_MASTERS-1)
:= (others => '0');
M_busLock : in std_logic_vector(0 to C_NUM_MASTERS-1)
:= (others => '0');
M_DBus : in std_logic_vector(0 to C_OPB_DWIDTH*C_NUM_MASTERS-1)
:= (others => '0');
M_DBusEn : in std_logic_vector(0 to C_NUM_MASTERS-1)
:= (others => '1');
M_DBusEn32_63 : in std_logic_vector(0 to C_NUM_MASTERS-1)
:= (others => '1');
M_dwXfer : in std_logic_vector(0 to C_NUM_MASTERS-1)
:= (others => '0');
M_fwXfer : in std_logic_vector(0 to C_NUM_MASTERS-1)
:= (others => '0');
M_hwXfer : in std_logic_vector(0 to C_NUM_MASTERS-1)
:= (others => '0');
M_request : in std_logic_vector(0 to C_NUM_MASTERS-1)
:= (others => '0');
M_RNW : in std_logic_vector(0 to C_NUM_MASTERS-1)
:= (others => '0');
M_select : in std_logic_vector(0 to C_NUM_MASTERS-1)
:= (others => '0');
M_seqAddr : in std_logic_vector(0 to C_NUM_MASTERS-1)
:= (others => '0');
-- Slave outputs
Sl_beAck : in std_logic_vector(0 to C_NUM_SLAVES-1)
:= (others => '0');
Sl_DBus : in std_logic_vector(0 to C_OPB_DWIDTH*
C_NUM_SLAVES-1)
:= (others => '0');
Sl_DBusEn : in std_logic_vector(0 to C_NUM_SLAVES-1)
:= (others => '1');
Sl_DBusEn32_63 : in std_logic_vector(0 to C_NUM_SLAVES-1)
:= (others => '1');
Sl_errAck : in std_logic_vector(0 to C_NUM_SLAVES-1)
:= (others => '0');
Sl_dwAck : in std_logic_vector(0 to C_NUM_SLAVES-1)
:= (others => '0');
Sl_fwAck : in std_logic_vector(0 to C_NUM_SLAVES-1)
:= (others => '0');
Sl_hwAck : in std_logic_vector(0 to C_NUM_SLAVES-1)
:= (others => '0');
Sl_retry : in std_logic_vector(0 to C_NUM_SLAVES-1)
:= (others => '0');
Sl_toutSup : in std_logic_vector(0 to C_NUM_SLAVES-1)
:= (others => '0');
Sl_xferAck : in std_logic_vector(0 to C_NUM_SLAVES-1)
:= (others => '0');
-- OPB outputs
OPB_MRequest : out std_logic_vector(0 to C_NUM_MASTERS-1);
OPB_ABus : out std_logic_vector(0 to C_OPB_AWIDTH-1);
OPB_BE : out std_logic_vector(0 to (C_OPB_DWIDTH+7)/8-1);
OPB_beXfer : out std_logic;
OPB_beAck : out std_logic;
OPB_busLock : out std_logic;
OPB_rdDBus : out std_logic_vector(0 to C_OPB_DWIDTH-1); -- extra
OPB_wrDBus : out std_logic_vector(0 to C_OPB_DWIDTH-1); -- extra
OPB_DBus : out std_logic_vector(0 to C_OPB_DWIDTH-1);
OPB_errAck : out std_logic;
OPB_dwAck : out std_logic;
OPB_dwXfer : out std_logic;
OPB_fwAck : out std_logic;
OPB_fwXfer : out std_logic;
OPB_hwAck : out std_logic;
OPB_hwXfer : out std_logic;
OPB_MGrant : out std_logic_vector(0 to C_NUM_MASTERS-1);
OPB_pendReq : out std_logic_vector(0 to C_NUM_MASTERS-1);
OPB_retry : out std_logic;
OPB_RNW : out std_logic;
OPB_select : out std_logic;
OPB_seqAddr : out std_logic;
OPB_timeout : out std_logic;
OPB_toutSup : out std_logic;
OPB_xferAck : out std_logic
);
end entity opb_v20;
-----------------------------------------------------------------------------
-- Architecture section
-----------------------------------------------------------------------------
architecture imp of opb_v20 is
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Function declarations
-----------------------------------------------------------------------------
function Integer_to_Boolean (x: integer) return boolean is
begin
if x=0 then return false;
else return true;
end if;
end function Integer_to_Boolean;
-----------------------------------------------------------------------------
-- Constant declarations
-----------------------------------------------------------------------------
constant C_USE_LUT_OR_B : boolean := Integer_to_Boolean(C_USE_LUT_OR);
-----------------------------------------------------------------------------
-- Signal declarations
-----------------------------------------------------------------------------
signal arb_timeout : std_logic := '0';
signal arb_mgrant : std_logic_vector(0 to C_NUM_MASTERS-1);
signal arb_dbus : std_logic_vector(0 to C_OPB_DWIDTH-1);
signal arb_errack : std_logic;
signal arb_retry : std_logic;
signal arb_toutsup : std_logic;
signal arb_xferack : std_logic;
signal opb_DBus_inputs : std_logic_vector(0 to 2*C_OPB_DWIDTH-1);
signal iOPB_wrDBus : std_logic_vector(0 to C_OPB_DWIDTH-1);
signal iOPB_rdDBus : std_logic_vector(0 to C_OPB_DWIDTH-1);
signal iOPB_beXfer : std_logic_vector(0 to 0);
signal iOPB_beAck : std_logic_vector(0 to 0);
signal iOPB_busLock : std_logic_vector(0 to 0);
signal iOPB_errAck : std_logic_vector(0 to 0);
signal iOPB_dwAck : std_logic_vector(0 to 0);
signal iOPB_dwXfer : std_logic_vector(0 to 0);
signal iOPB_fwAck : std_logic_vector(0 to 0);
signal iOPB_fwXfer : std_logic_vector(0 to 0);
signal iOPB_hwAck : std_logic_vector(0 to 0);
signal iOPB_hwXfer : std_logic_vector(0 to 0);
signal iOPB_retry : std_logic_vector(0 to 0);
signal iOPB_RNW : std_logic_vector(0 to 0);
signal iOPB_select : std_logic_vector(0 to 0);
signal iOPB_seqAddr : std_logic_vector(0 to 0);
signal iOPB_toutSup : std_logic_vector(0 to 0);
signal iOPB_xferAck : std_logic_vector(0 to 0);
signal iOPB_Rst : std_logic;
signal iOPB_ABus : std_logic_vector(0 to C_OPB_AWIDTH-1);
signal iOPB_BE : std_logic_vector(0 to C_OPB_DWIDTH/8-1);
signal srl_time_out : std_logic;
signal sys_rst_i : std_logic;
-----------------------------------------------------------------------------
-- Attribute declarations
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Begin architecture
-----------------------------------------------------------------------------
begin -- architecture imp
--------------------------------------------------------------------------------
-- Power On Reset to OPB
--------------------------------------------------------------------------------
SYS_RST_PROC: process (SYS_Rst,WDT_Rst,Debug_SYS_Rst) is
variable sys_rst_input : std_logic;
begin
if C_EXT_RESET_HIGH = 0 then
sys_rst_input := not SYS_Rst;
else
sys_rst_input := SYS_Rst;
end if;
sys_rst_i <= sys_rst_input or WDT_Rst or Debug_SYS_Rst;
end process SYS_RST_PROC;
POR_SRL_I: SRL16
-- synthesis translate_off
generic map (
INIT => X"FFFF")
-- synthesis translate_on
port map (
D => '0',
CLK => OPB_Clk,
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
Q => srl_time_out);
POR_FF_I: FDS
port map (
Q => iOPB_Rst,
D => srl_time_out,
C => OPB_Clk,
S => sys_rst_i);
OPB_MRequest <= M_request; -- pass the Master request through
OPB_ABus_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_MASTERS,C_OPB_AWIDTH,C_USE_LUT_OR_B)
port map (M_ABus,iOPB_ABus);
OPB_BE_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_MASTERS,(C_OPB_DWIDTH+7)/8,
C_USE_LUT_OR_B)
port map (M_BE,iOPB_BE);
OPB_beXfer_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_MASTERS,1,C_USE_LUT_OR_B)
port map (M_beXfer,iOPB_beXfer);
OPB_busLock_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_MASTERS,1,C_USE_LUT_OR_B)
port map (M_busLock,iOPB_busLock);
-- The following two signals are not part of the V2.0 spec but are
-- intermediate buses that are OR'ed to form OPB_DBus. They can be
-- used in an implementation to optimize the master and slave OR
-- functions by breaking up the OPB_DBus OR gate.
OPB_wrDBus_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_MASTERS,C_OPB_DWIDTH,C_USE_LUT_OR_B)
port map (M_DBus,iOPB_wrDBus);
opb_DBus_inputs <= iOPB_wrDBus & iOPB_rdDBus;
OPB_rdDBus <= iOPB_rdDBus;
OPB_wrDBus <= iOPB_wrDBus;
OPB_DBus_I: entity opb_v20_v1_10_d.or_gate generic map (2,C_OPB_DWIDTH,C_USE_LUT_OR_B)
port map (opb_DBus_inputs,OPB_DBus);
OPB_dwXfer_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_MASTERS,1,C_USE_LUT_OR_B)
port map (M_dwXfer,iOPB_dwXfer);
OPB_fwXfer_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_MASTERS,1,C_USE_LUT_OR_B)
port map (M_fwXfer,iOPB_fwXfer);
OPB_hwXfer_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_MASTERS,1,C_USE_LUT_OR_B)
port map (M_hwXfer,iOPB_hwXfer);
OPB_MGrant <= arb_mgrant;
-- OPB_pendReq is generated by OR'ing all master requests except
-- a master's own request. It indicates to a master that one or
-- more of the other masters attached to the bus is requesting
-- access.
MORE_THAN_ONE_MASTER_GEN: if C_NUM_MASTERS > 1 generate
OPB_pendReq_GEN: for i in 0 to C_NUM_MASTERS-1 generate
signal or_gate_input : std_logic_vector(0 to C_NUM_MASTERS-2);
begin
OR_ALL_BUT_SELF_PROCESS: process (M_request) is
variable k : integer := 0;
begin
for j in 0 to i-1 loop
or_gate_input(j) <= M_request(j);
end loop;
for j in i+1 to C_NUM_MASTERS-1 loop
or_gate_input(j-1) <= M_request(j);
end loop;
end process OR_ALL_BUT_SELF_PROCESS;
OPB_pendReq_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_MASTERS-1,1,C_USE_LUT_OR_B)
port map (or_gate_input,OPB_pendReq(i to i));
end generate OPB_pendReq_GEN;
end generate MORE_THAN_ONE_MASTER_GEN;
ONLY_ONE_MASTER_GEN: if C_NUM_MASTERS = 1 generate
OPB_pendReq(0) <= '0';
end generate ONLY_ONE_MASTER_GEN;
OPB_RNW_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_MASTERS,1,C_USE_LUT_OR_B)
port map (M_RNW,iOPB_RNW);
OPB_select_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_MASTERS,1,C_USE_LUT_OR_B)
port map (M_select,iOPB_select);
OPB_seqAddr_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_MASTERS,1,C_USE_LUT_OR_B)
port map (M_seqAddr,iOPB_seqAddr);
OPB_hwAck_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_SLAVES,1,C_USE_LUT_OR_B)
port map (Sl_hwAck,iOPB_hwAck);
OPB_fwAck_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_SLAVES,1,C_USE_LUT_OR_B)
port map (Sl_fwAck,iOPB_fwAck);
OPB_dwAck_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_SLAVES,1,C_USE_LUT_OR_B)
port map (Sl_dwAck,iOPB_dwAck);
OPB_beAck_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_SLAVES,1,C_USE_LUT_OR_B)
port map (Sl_beAck,iOPB_beAck);
OPB_timeout <= Arb_timeout; -- pass the Timeout through
--------------------------------------------------------------------------------
-- The following signals must be generated conditionally based on the
-- state of C_PROC_INTRFCE
--------------------------------------------------------------------------------
ARBITER_HAS_PROC_INTF: if C_PROC_INTRFCE /= 0 generate
signal sl_plus_arb_dbus : std_logic_vector(0 to ((C_NUM_SLAVES+1)*C_OPB_DWIDTH)-1);
signal sl_plus_arb_errack : std_logic_vector(0 to C_NUM_SLAVES);
signal sl_plus_arb_retry : std_logic_vector(0 to C_NUM_SLAVES);
signal sl_plus_arb_toutsup : std_logic_vector(0 to C_NUM_SLAVES);
signal sl_plus_arb_xferack : std_logic_vector(0 to C_NUM_SLAVES);
begin
sl_plus_arb_dbus <= Sl_DBus & arb_dbus;
sl_plus_arb_errack <= Sl_errAck & arb_errack;
sl_plus_arb_retry <= Sl_retry & arb_retry;
sl_plus_arb_toutsup <= Sl_toutSup & arb_toutsup;
sl_plus_arb_xferack <= Sl_xferAck & arb_xferack;
OPB_toutSup_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_SLAVES+1,1,C_USE_LUT_OR_B)
port map (sl_plus_arb_toutsup,iOPB_toutSup);
OPB_xferAck_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_SLAVES+1,1,C_USE_LUT_OR_B)
port map (sl_plus_arb_xferack,iOPB_xferAck);
OPB_retry_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_SLAVES+1,1,C_USE_LUT_OR_B)
port map (sl_plus_arb_retry,iOPB_retry);
OPB_errAck_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_SLAVES+1,1,C_USE_LUT_OR_B)
port map (sl_plus_arb_errack,iOPB_errAck);
OPB_rdDBus_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_SLAVES+1,C_OPB_DWIDTH,C_USE_LUT_OR_B)
port map (sl_plus_arb_dbus,iOPB_rdDBus);
end generate ARBITER_HAS_PROC_INTF;
ARBITER_HAS_NO_PROC_INTF: if C_PROC_INTRFCE = 0 generate
begin
OPB_toutSup_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_SLAVES,1,C_USE_LUT_OR_B)
port map (Sl_toutSup,iOPB_toutSup);
OPB_xferAck_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_SLAVES,1,C_USE_LUT_OR_B)
port map (Sl_xferAck,iOPB_xferAck);
OPB_retry_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_SLAVES,1,C_USE_LUT_OR_B)
port map (Sl_retry,iOPB_retry);
OPB_errAck_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_SLAVES,1,C_USE_LUT_OR_B)
port map (Sl_errAck,iOPB_errAck);
OPB_rdDBus_I: entity opb_v20_v1_10_d.or_gate generic map (C_NUM_SLAVES,C_OPB_DWIDTH,C_USE_LUT_OR_B)
port map (Sl_DBus,iOPB_rdDBus);
end generate ARBITER_HAS_NO_PROC_INTF;
OPB_beXfer <= iOPB_beXfer(0);
OPB_beAck <= iOPB_beAck(0);
OPB_busLock <= iOPB_busLock(0);
OPB_errAck <= iOPB_errAck(0);
OPB_dwAck <= iOPB_dwAck(0);
OPB_dwXfer <= iOPB_dwXfer(0);
OPB_fwAck <= iOPB_fwAck(0);
OPB_fwXfer <= iOPB_fwXfer(0);
OPB_hwAck <= iOPB_hwAck(0);
OPB_hwXfer <= iOPB_hwXfer(0);
OPB_retry <= iOPB_retry(0);
OPB_RNW <= iOPB_RNW(0);
OPB_select <= iOPB_select(0);
OPB_seqAddr <= iOPB_seqAddr(0);
OPB_toutSup <= iOPB_toutSup(0);
OPB_xferAck <= iOPB_xferAck(0);
OPB_Rst <= iOPB_Rst;
OPB_ABus <= iOPB_ABus;
OPB_BE <= iOPB_BE;
OPB_ARBITER_I : entity opb_v20_v1_10_d.opb_arbiter
generic map (
C_BASEADDR => C_BASEADDR,
C_HIGHADDR => C_HIGHADDR,
C_NUM_MASTERS => C_NUM_MASTERS,
C_OPB_DWIDTH => C_OPB_DWIDTH,
C_OPB_AWIDTH => C_OPB_AWIDTH,
C_DYNAM_PRIORITY => C_DYNAM_PRIORITY,
C_REG_GRANTS => C_REG_GRANTS,
C_PARK => C_PARK,
C_PROC_INTRFCE => C_PROC_INTRFCE,
C_DEV_BLK_ID => C_DEV_BLK_ID,
C_DEV_MIR_ENABLE => C_DEV_MIR_ENABLE)
port map (
ARB_DBus => arb_dbus,
ARB_ErrAck => arb_errack,
ARB_Retry => arb_retry,
ARB_ToutSup => arb_toutsup,
ARB_XferAck => arb_xferack,
OPB_Clk => OPB_clk,
M_request => M_request,
OPB_Abus => iOPB_ABus,
OPB_BE => iOPB_BE,
OPB_buslock => iOPB_busLock(0),
OPB_Dbus => iOPB_wrDBus,
OPB_MGrant => arb_mgrant,
OPB_retry => iOPB_retry(0),
OPB_RNW => iOPB_rnw(0),
OPB_select => iOPB_select(0),
OPB_seqAddr => iOPB_seqaddr(0),
OPB_timeout => arb_timeout,
OPB_toutSup => iOPB_toutsup(0),
OPB_xferAck => iOPB_xferack(0),
OPB_Rst => iOPB_Rst);
end architecture imp;
|
-- Revision history:
-- 10.08.2015 Patrick Appenheimer created
-- 10.08.2015 Carlos Minamisava Faria moore state machine states definition
-- 10.08.2015 Carlos Minamisava Faria & Patrick Appenheimer Instructions added
-- 11.08.2015 Patrick Appenheimer added state_register and state_decode
-- 12.08.2015 Patrick Appenheimer minor changes
-- 14.08.2015 Patrick Appenheimer stall logic changed
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library WORK;
use WORK.all;
entity FSM is
port (
clk : in std_logic;
rst : in std_logic;
instr_in : in std_logic_vector(31 downto 0);
stall : in std_logic;
out_currentstate : out std_logic_vector(4 downto 0);
out_nextstate : out std_logic_vector(4 downto 0);
out_buffer : out std_logic_vector(29 downto 0);
out_busy : out std_logic;
in_go : in std_logic
);
end entity FSM;
architecture behavioral of FSM is
-- State Machine --
constant s0 : std_logic_vector(4 downto 0) := b"00000";
constant s1 : std_logic_vector(4 downto 0) := b"00001";
constant s2 : std_logic_vector(4 downto 0) := b"00010";
constant s3 : std_logic_vector(4 downto 0) := b"00011";
constant s4 : std_logic_vector(4 downto 0) := b"00100";
constant sX : std_logic_vector(4 downto 0) := b"11111";
-- Arithmetic --
constant addiu : std_logic_vector(5 downto 0) := b"0010_01"; -- Type I
-- Data Transfer --
constant lui : std_logic_vector(5 downto 0) := b"0011_11"; -- Type I -Register access
constant lbu : std_logic_vector(5 downto 0) := b"1001_00"; -- Type I -Memory access
constant lw : std_logic_vector(5 downto 0) := b"1000_11"; -- Type I -Memory access
constant sb : std_logic_vector(5 downto 0) := b"101000"; -- Type I -Memory access
constant sw : std_logic_vector(5 downto 0) := b"101011"; -- Type I -Memory access
-- Logical --
constant slti : std_logic_vector(5 downto 0) := b"001010"; -- Type I
constant andi : std_logic_vector(5 downto 0) := b"0011_00"; -- Type I
constant shift : std_logic_vector(5 downto 0) := b"0000_00"; -- Type R -NOP is read as sll $0,$0,0
-- Conditional branch --
constant beqz : std_logic_vector(5 downto 0) := b"000100"; -- Type I
constant bnez : std_logic_vector(5 downto 0) := b"000101"; -- Type I
-- Unconditional jump --
constant j : std_logic_vector(5 downto 0) := b"0000_10"; -- Type J
constant jalx : std_logic_vector(5 downto 0) := b"0011_01"; -- Type J
constant r_type : std_logic_vector(5 downto 0) := b"0000_00"; -- Type R
-- output_buffer is a register with all control outputs of the state machine:
-- output_buffer (29 downto 29): pc_mux : out std_logic;
-- output_buffer (28 downto 27): id_regdest_mux : out std_logic_vector (1 downto 0);
-- output_buffer (26 downto 25): id_regshift_mux : out std_logic_vector (1 downto 0);
-- output_buffer (24 downto 24): id_enable_regs : out std_logic;
-- output_buffer (23 downto 22): exc_mux1 : out std_logic_vector(1 downto 0);
-- output_buffer (21 downto 20): exc_mux2 : out std_logic_vector(1 downto 0);
-- output_buffer (19 downto 14): alu_instruction : out std_logic_vector(5 downto 0);
-- output_buffer (13 downto 13): mem_mux_decision : out std_logic;
-- output_buffer (12 downto 9): rd_mask : out std_logic_vector(3 downto 0);
-- output_buffer (8 downto 5): wr_mask : out std_logic_vector(3 downto 0);
-- output_buffer (4 downto 0): stage_control : out std_logic_vector(4 downto 0);
signal output_buffer : std_logic_vector(29 downto 0);
signal currentstate : std_logic_vector(4 downto 0);
signal nextstate : std_logic_vector(4 downto 0);
begin
state_encode: process(currentstate, stall, in_go)
begin
case currentstate is
when sX =>
if (in_go = '1') then
nextstate <= s0;
else
nextstate <= sX;
end if;
when s0 =>
if (stall = '0') then
nextstate <= s1;
else
nextstate <= s0;
end if;
when s1 =>
if (stall = '0') then
nextstate <= s2;
else
nextstate <= s1;
end if;
when s2 =>
if (stall = '0') then
nextstate <= s3;
else
nextstate <= s2;
end if;
when s3 =>
if (stall = '0') then
nextstate <= sX;
else
nextstate <= s3;
end if;
when s4 =>
if (stall = '0') then
nextstate <= sX;
else
nextstate <= s4;
end if;
when others => nextstate <= sX;
end case;
end process state_encode;
state_register: process(rst, clk)
begin
if (rst = '1') then
currentstate <= sX;
elsif (clk'event and clk = '1') then
currentstate <= nextstate;
end if;
end process state_register;
out_buffer_ctrl: process(clk)
begin
if(clk'event and clk = '0') then
out_buffer <= output_buffer;
end if;
end process;
state_decode: process(currentstate)
begin
out_currentstate <= currentstate;
out_nextstate <= nextstate;
case currentstate is
when sX =>
out_busy <= '0';
when s0 =>
out_busy <= '1';
when s3 =>
out_busy <= '0';
when others =>
-- do something
end case;
end process state_decode;
out_buff_ctr: process(instr_in)
begin
case instr_in (31 downto 26) is
when lui => output_buffer <= b"0_10_01_1_00_01_000100_0_0000_0000_11111";
when addiu => output_buffer <= b"0_10_00_1_10_01_100000_0_0000_0000_11111";
when lbu => output_buffer <= b"0_10_00_1_10_01_100000_1_0001_0000_11111";
when lw => output_buffer <= b"0_10_00_1_10_01_100000_1_1111_0000_11111";
when sb => output_buffer <= b"0_10_00_0_10_01_100000_0_0000_0001_11111";
when sw => output_buffer <= b"0_10_00_0_10_01_100000_0_0000_1111_11111";
when slti => output_buffer <= b"0_10_00_1_10_01_001000_0_0000_0000_11111";
when andi => output_buffer <= b"0_10_01_1_00_01_100100_0_0000_0000_11111";
when shift => output_buffer <= b"0_00_00_1_00_00_001000_0_0000_0000_11111";
when beqz => output_buffer <= b"1_10_00_0_00_00_000001_0_0000_0000_11111";
when bnez => output_buffer <= b"1_10_00_0_00_00_000001_0_0000_0000_11111";
when j => output_buffer <= b"1_10_00_0_00_00_000001_0_0000_0000_11111";
when jalx => output_buffer <= b"1_10_00_0_00_00_000001_0_0000_0000_11111";
--when r_type => output_buffer <= b"0_00_00_1_10_00_000000_0_0000_0000_11111";
when others => output_buffer <= b"0_00_00_0_00_00_000000_0_0000_0000_11111";
end case;
end process;
end architecture behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1851.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01851ent IS
END c07s01b00x00p08n01i01851ent;
ARCHITECTURE c07s01b00x00p08n01i01851arch OF c07s01b00x00p08n01i01851ent IS
BEGIN
TESTING : PROCESS
type byte is range TESTING to 3; -- process label illegal here
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01851 - Process labels are not permitted as primaries in a range expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01851arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1851.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01851ent IS
END c07s01b00x00p08n01i01851ent;
ARCHITECTURE c07s01b00x00p08n01i01851arch OF c07s01b00x00p08n01i01851ent IS
BEGIN
TESTING : PROCESS
type byte is range TESTING to 3; -- process label illegal here
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01851 - Process labels are not permitted as primaries in a range expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01851arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1851.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01851ent IS
END c07s01b00x00p08n01i01851ent;
ARCHITECTURE c07s01b00x00p08n01i01851arch OF c07s01b00x00p08n01i01851ent IS
BEGIN
TESTING : PROCESS
type byte is range TESTING to 3; -- process label illegal here
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01851 - Process labels are not permitted as primaries in a range expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01851arch;
|
The VHDL backend
Written by Magnus Danielson and improved by Thomas Heidel
A few things you have to care about:
1. In order to generate valid component declarations, you
have to add an additional attribute to each pin.
"type=IN" or "type=OUT" or "type=INOUT"
2. The "device" attribute must be unique to a symbol!
The verilog symbols of the same type for example, have all
the same device attribute and will therefore not work.
3. Make sure your component-library picks up the vhdl symbols instead
of the verilog symbols Library paths that show up last are searched
first!
|
The VHDL backend
Written by Magnus Danielson and improved by Thomas Heidel
A few things you have to care about:
1. In order to generate valid component declarations, you
have to add an additional attribute to each pin.
"type=IN" or "type=OUT" or "type=INOUT"
2. The "device" attribute must be unique to a symbol!
The verilog symbols of the same type for example, have all
the same device attribute and will therefore not work.
3. Make sure your component-library picks up the vhdl symbols instead
of the verilog symbols Library paths that show up last are searched
first!
|
The VHDL backend
Written by Magnus Danielson and improved by Thomas Heidel
A few things you have to care about:
1. In order to generate valid component declarations, you
have to add an additional attribute to each pin.
"type=IN" or "type=OUT" or "type=INOUT"
2. The "device" attribute must be unique to a symbol!
The verilog symbols of the same type for example, have all
the same device attribute and will therefore not work.
3. Make sure your component-library picks up the vhdl symbols instead
of the verilog symbols Library paths that show up last are searched
first!
|
The VHDL backend
Written by Magnus Danielson and improved by Thomas Heidel
A few things you have to care about:
1. In order to generate valid component declarations, you
have to add an additional attribute to each pin.
"type=IN" or "type=OUT" or "type=INOUT"
2. The "device" attribute must be unique to a symbol!
The verilog symbols of the same type for example, have all
the same device attribute and will therefore not work.
3. Make sure your component-library picks up the vhdl symbols instead
of the verilog symbols Library paths that show up last are searched
first!
|
The VHDL backend
Written by Magnus Danielson and improved by Thomas Heidel
A few things you have to care about:
1. In order to generate valid component declarations, you
have to add an additional attribute to each pin.
"type=IN" or "type=OUT" or "type=INOUT"
2. The "device" attribute must be unique to a symbol!
The verilog symbols of the same type for example, have all
the same device attribute and will therefore not work.
3. Make sure your component-library picks up the vhdl symbols instead
of the verilog symbols Library paths that show up last are searched
first!
|
The VHDL backend
Written by Magnus Danielson and improved by Thomas Heidel
A few things you have to care about:
1. In order to generate valid component declarations, you
have to add an additional attribute to each pin.
"type=IN" or "type=OUT" or "type=INOUT"
2. The "device" attribute must be unique to a symbol!
The verilog symbols of the same type for example, have all
the same device attribute and will therefore not work.
3. Make sure your component-library picks up the vhdl symbols instead
of the verilog symbols Library paths that show up last are searched
first!
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Demultiplexer_4x1 is
Port ( Selector : in STD_LOGIC_VECTOR(3 downto 0);
input: in STD_LOGIC;
output_A, output_B, output_C, output_D, output_E, output_F, output_G, output_H : out STD_LOGIC;
output_I, output_J, output_K, output_L, output_M, output_N, output_O, output_P : out STD_LOGIC);
end Demultiplexer_4x1;
architecture skeleton of Demultiplexer_4x1 is
begin
with Selector select
output_A <= input when "0000",
'0' when others;
with Selector select
output_B <= input when "0001",
'0' when others;
with Selector select
output_C <= input when "0010",
'0' when others;
with Selector select
output_D <= input when "0011",
'0' when others;
with Selector select
output_E <= input when "0100",
'0' when others;
with Selector select
output_F <= input when "0101",
'0' when others;
with Selector select
output_G <= input when "0110",
'0' when others;
with Selector select
output_H <= input when "0111",
'0' when others;
with Selector select
output_I <= input when "1000",
'0' when others;
with Selector select
output_J <= input when "1001",
'0' when others;
with Selector select
output_K <= input when "1010",
'0' when others;
with Selector select
output_L <= input when "1011",
'0' when others;
with Selector select
output_M <= input when "1100",
'0' when others;
with Selector select
output_N <= input when "1101",
'0' when others;
with Selector select
output_O <= input when "1110",
'0' when others;
with Selector select
output_P <= input when "1111",
'0' when others;
end skeleton; |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ex5_jed is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(1 downto 0)
);
end ex5_jed;
architecture behaviour of ex5_jed is
constant s1: std_logic_vector(3 downto 0) := "0100";
constant s0: std_logic_vector(3 downto 0) := "0101";
constant s7: std_logic_vector(3 downto 0) := "1001";
constant s5: std_logic_vector(3 downto 0) := "1101";
constant s4: std_logic_vector(3 downto 0) := "0001";
constant s2: std_logic_vector(3 downto 0) := "0110";
constant s3: std_logic_vector(3 downto 0) := "1100";
constant s6: std_logic_vector(3 downto 0) := "0111";
constant s8: std_logic_vector(3 downto 0) := "0011";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "--";
case current_state is
when s1 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s7; output <= "00";
elsif std_match(input, "10") then next_state <= s5; output <= "11";
elsif std_match(input, "11") then next_state <= s4; output <= "--";
end if;
when s2 =>
if std_match(input, "00") then next_state <= s1; output <= "--";
elsif std_match(input, "01") then next_state <= s4; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "00";
end if;
when s3 =>
if std_match(input, "00") then next_state <= s3; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "00";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s7; output <= "11";
end if;
when s4 =>
if std_match(input, "00") then next_state <= s5; output <= "00";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s1; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when s5 =>
if std_match(input, "00") then next_state <= s0; output <= "11";
elsif std_match(input, "01") then next_state <= s6; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "11";
elsif std_match(input, "11") then next_state <= s0; output <= "11";
end if;
when s6 =>
if std_match(input, "00") then next_state <= s0; output <= "11";
elsif std_match(input, "01") then next_state <= s5; output <= "--";
elsif std_match(input, "10") then next_state <= s1; output <= "11";
elsif std_match(input, "11") then next_state <= s0; output <= "11";
end if;
when s7 =>
if std_match(input, "00") then next_state <= s6; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "11";
elsif std_match(input, "10") then next_state <= s2; output <= "--";
elsif std_match(input, "11") then next_state <= s8; output <= "--";
end if;
when s8 =>
if std_match(input, "00") then next_state <= s3; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s1; output <= "00";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when others => next_state <= "----"; output <= "--";
end case;
end process;
end behaviour;
|
----------------------------------------------------------------------------
--
-- Atmel AVR ALU Test Entity Declaration
--
-- This is the entity declaration which must be used for building the ALU
-- portion of the AVR design for testing.
--
-- Revision History:
-- 17 Apr 98 Glen George Initial revision.
-- 20 Apr 98 Glen George Fixed minor syntax bugs.
-- 18 Apr 04 Glen George Updated comments and formatting.
-- 21 Jan 06 Glen George Updated comments.
-- 28 Jan 15 Bryan He Added connections to ALU and control block
--
----------------------------------------------------------------------------
--
-- ALU_TEST
--
-- This is the ALU testing interface. It just brings all the important
-- ALU signals out for testing along with the Instruction Register.
--
-- Inputs:
-- IR - Instruction Register (16 bits)
-- OperandA - first operand to ALU (8 bits) - looks like the output
-- of the register array
-- OperandB - second operand to ALU (8 bits) - looks like the output
-- of the register array
-- clock - the system clock
--
-- Outputs:
-- Result - result of the ALU operation selected by the Instruction
-- Register (8 bits)
-- StatReg - Status Register contents (8 bits)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library opcodes;
use opcodes.opcodes.all;
entity ALU_TEST is
port(
IR : in opcode_word; -- Instruction Register
OperandA : in std_logic_vector(7 downto 0); -- first operand
OperandB : in std_logic_vector(7 downto 0); -- second operand
clock : in std_logic; -- system clock
Result : out std_logic_vector(7 downto 0); -- ALU result
StatReg : out std_logic_vector(7 downto 0) -- status register
);
end ALU_TEST;
architecture Structural of ALU_TEST is
-- Communication between Control Unit and ALU
signal ALUBlockSel : std_logic_vector(1 downto 0);
signal ALUBlockInstructionSel : std_logic_vector(3 downto 0);
signal ALUOp2Sel : std_logic;
signal ImmediateOut : std_logic_vector(7 downto 0);
signal ALUStatusMask : std_logic_vector(7 downto 0);
signal ALUStatusBitChangeEn : std_logic;
signal ALUBitClrSet : std_logic;
signal ALUBitTOp : std_logic;
signal RegIn : std_logic_vector(7 downto 0);
-- Unused signals from Control Unit (should go to registers)
signal EnableIn : std_logic;
signal SelIn : std_logic_vector(6 downto 0);
signal SelA : std_logic_vector(6 downto 0);
signal SelB : std_logic_vector(6 downto 0);
begin
-- Connect the ALU to the testing interface (reads input values and gives
-- status and result)
ALU : entity work.ALU
port map (
clock => clock,
ALUBlockSel => ALUBlockSel,
ALUBlockInstructionSel => ALUBlockInstructionSel,
ALUOp2Sel => ALUOp2Sel,
ImmediateOut => ImmediateOut,
ALUStatusMask => ALUStatusMask,
ALUStatusBitChangeEn => ALUStatusBitChangeEn,
ALUBitClrSet => ALUBitClrSet,
ALUBitTOp => ALUBitTOp,
RegAOut => OperandA,
RegBOut => OperandB,
RegIn => Result,
RegStatus => StatReg
);
-- Connect the Control Unit to the testing interface (reads instruction
-- and tells ALU what to do)
ControlUnit : entity work.AVRControl
port map (
clock => clock,
IR => IR,
ProgDB => (others => 'X'),
MemRegAddr => (others => '0'),
ALUStatusMask => ALUStatusMask,
ALUStatusBitChangeEn => ALUStatusBitChangeEn,
ALUBitClrSet => ALUBitClrSet,
ALUBitTOp => ALUBitTOp,
ALUOp2Sel => ALUOp2Sel,
ImmediateOut => ImmediateOut,
ALUBlockSel => ALUBlockSel,
ALUBlockInstructionSel => ALUBlockInstructionSel,
EnableIn => EnableIn,
SelIn => SelIn,
SelA => SelA,
SelB => SelB,
DataIOSel => open,
AddrOffset => open,
SpecAddr => open,
SpecWr => open,
RegDataInSel => open,
MemAddr => open
);
end Structural;
|
-------------------------------------------------------------------------------
-- (c) Copyright 2012 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------------------
-- Filename: axi_traffic_gen_v2_0_7_bmg_wrap.v
-- Version : v1.0
-- Description: BMG Wrapper
-- Verilog-Standard:verilog-2001
-----------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
library lib_bmg_v1_0_2;
use lib_bmg_v1_0_2.all;
entity axi_traffic_gen_v2_0_7_bmg_wrap is
generic
(
-- Device Family
c_family : string := "virtex5";
c_xdevicefamily : string := "virtex5";
-- Finest Resolution Device Family
-- "Virtex2"
-- "Virtex2-Pro"
-- "Virtex4"
-- "Virtex5"
-- "Spartan-3A"
-- "Spartan-3A DSP"
c_elaboration_dir : string := "";
-- Memory Specific Configurations
c_mem_type : integer := 2;
-- This wrapper only supports the True Dual Port RAM
-- 0: Single Port RAM
-- 1: Simple Dual Port RAM
-- 2: True Dual Port RAM
-- 3: Single Port Rom
-- 4: Dual Port RAM
c_algorithm : integer := 1;
-- 0: Selectable Primative
-- 1: Minimum Area
c_prim_type : integer := 1;
-- 0: ( 1-bit wide)
-- 1: ( 2-bit wide)
-- 2: ( 4-bit wide)
-- 3: ( 9-bit wide)
-- 4: (18-bit wide)
-- 5: (36-bit wide)
-- 6: (72-bit wide, single port only)
c_byte_size : integer := 9; -- 8 or 9
-- Simulation Behavior Options
c_sim_collision_check : string := "NONE";
-- "None"
-- "Generate_X"
-- "All"
-- "Warnings_only"
c_common_clk : integer := 1; -- 0, 1
c_disable_warn_bhv_coll : integer := 0; -- 0, 1
c_disable_warn_bhv_range : integer := 0; -- 0, 1
-- Initialization Configuration Options
c_load_init_file : integer := 0;
c_init_file_name : string := "no_coe_file_loaded";
c_use_default_data : integer := 0; -- 0, 1
c_default_data : string := "0"; -- "..."
-- Port A Specific Configurations
c_has_mem_output_regs_a : integer := 0; -- 0, 1
c_has_mux_output_regs_a : integer := 0; -- 0, 1
c_write_width_a : integer := 32; -- 1 to 1152
c_read_width_a : integer := 32; -- 1 to 1152
c_write_depth_a : integer := 64; -- 2 to 9011200
c_read_depth_a : integer := 64; -- 2 to 9011200
c_addra_width : integer := 6; -- 1 to 24
c_write_mode_a : string := "WRITE_FIRST";
-- "Write_First"
-- "Read_first"
-- "No_Change"
c_has_ena : integer := 1; -- 0, 1
c_has_regcea : integer := 0; -- 0, 1
c_has_ssra : integer := 0; -- 0, 1
c_sinita_val : string := "0"; --"..."
c_use_byte_wea : integer := 0; -- 0, 1
c_wea_width : integer := 1; -- 1 to 128
-- Port B Specific Configurations
c_has_mem_output_regs_b : integer := 0; -- 0, 1
c_has_mux_output_regs_b : integer := 0; -- 0, 1
c_write_width_b : integer := 32; -- 1 to 1152
c_read_width_b : integer := 32; -- 1 to 1152
c_write_depth_b : integer := 64; -- 2 to 9011200
c_read_depth_b : integer := 64; -- 2 to 9011200
c_addrb_width : integer := 6; -- 1 to 24
c_write_mode_b : string := "WRITE_FIRST";
-- "Write_First"
-- "Read_first"
-- "No_Change"
c_has_enb : integer := 1; -- 0, 1
c_has_regceb : integer := 0; -- 0, 1
c_has_ssrb : integer := 0; -- 0, 1
c_sinitb_val : string := "0"; -- "..."
c_use_byte_web : integer := 0; -- 0, 1
c_web_width : integer := 1; -- 1 to 128
-- Other Miscellaneous Configurations
c_mux_pipeline_stages : integer := 0; -- 0, 1, 2, 3
-- The number of pipeline stages within the MUX
-- for both Port A and Port B
c_use_ecc : integer := 0;
-- See DS512 for the limited core option selections for ECC support
c_use_ramb16bwer_rst_bhv : integer := 0--; --0, 1
-- c_corename : string := "blk_mem_gen_v2_7"
--Uncommenting the above parameter (C_CORENAME) will cause
--the a failure in NGCBuild!!!
);
port
(
clka : in std_logic;
ssra : in std_logic := '0';
dina : in std_logic_vector(c_write_width_a-1 downto 0) := (OTHERS => '0');
addra : in std_logic_vector(c_addra_width-1 downto 0);
ena : in std_logic := '1';
regcea : in std_logic := '1';
wea : in std_logic_vector(c_wea_width-1 downto 0) := (OTHERS => '0');
douta : out std_logic_vector(c_read_width_a-1 downto 0);
clkb : in std_logic := '0';
ssrb : in std_logic := '0';
dinb : in std_logic_vector(c_write_width_b-1 downto 0) := (OTHERS => '0');
addrb : in std_logic_vector(c_addrb_width-1 downto 0) := (OTHERS => '0');
enb : in std_logic := '1';
regceb : in std_logic := '1';
web : in std_logic_vector(c_web_width-1 downto 0) := (OTHERS => '0');
doutb : out std_logic_vector(c_read_width_b-1 downto 0);
dbiterr : out std_logic;
-- Double bit error that that cannot be auto corrected by ECC
sbiterr : out std_logic
-- Single Bit Error that has been auto corrected on the output bus
);
end entity axi_traffic_gen_v2_0_7_bmg_wrap;
architecture implementation of axi_traffic_gen_v2_0_7_bmg_wrap is
begin
-- component blk_mem_gen_wrapper is
-- generic
-- (
-- c_family : string := "virtex5";
-- c_xdevicefamily : string := "virtex5";
-- c_elaboration_dir : string := "";
-- c_mem_type : integer := 2;
-- c_algorithm : integer := 1;
-- c_prim_type : integer := 1;
-- c_byte_size : integer := 9; -- 8 or 9
-- c_sim_collision_check : string := "NONE";
-- c_common_clk : integer := 1; -- 0, 1
-- c_disable_warn_bhv_coll : integer := 0; -- 0, 1
-- c_disable_warn_bhv_range : integer := 0; -- 0, 1
-- c_load_init_file : integer := 0;
-- c_init_file_name : string := "no_coe_file_loaded";
-- c_use_default_data : integer := 0; -- 0, 1
-- c_default_data : string := "0"; -- "..."
-- c_has_mem_output_regs_a : integer := 0; -- 0, 1
-- c_has_mux_output_regs_a : integer := 0; -- 0, 1
-- c_write_width_a : integer := 32; -- 1 to 1152
-- c_read_width_a : integer := 32; -- 1 to 1152
-- c_write_depth_a : integer := 64; -- 2 to 9011200
-- c_read_depth_a : integer := 64; -- 2 to 9011200
-- c_addra_width : integer := 6; -- 1 to 24
-- c_write_mode_a : string := "WRITE_FIRST";
-- c_has_ena : integer := 1; -- 0, 1
-- c_has_regcea : integer := 0; -- 0, 1
-- c_has_ssra : integer := 0; -- 0, 1
-- c_sinita_val : string := "0"; --"..."
-- c_use_byte_wea : integer := 0; -- 0, 1
-- c_wea_width : integer := 1; -- 1 to 128
-- c_has_mem_output_regs_b : integer := 0; -- 0, 1
-- c_has_mux_output_regs_b : integer := 0; -- 0, 1
-- c_write_width_b : integer := 32; -- 1 to 1152
-- c_read_width_b : integer := 32; -- 1 to 1152
-- c_write_depth_b : integer := 64; -- 2 to 9011200
-- c_read_depth_b : integer := 64; -- 2 to 9011200
-- c_addrb_width : integer := 6; -- 1 to 24
-- c_write_mode_b : string := "WRITE_FIRST";
-- c_has_enb : integer := 1; -- 0, 1
-- c_has_regceb : integer := 0; -- 0, 1
-- c_has_ssrb : integer := 0; -- 0, 1
-- c_sinitb_val : string := "0"; -- "..."
-- c_use_byte_web : integer := 0; -- 0, 1
-- c_web_width : integer := 1; -- 1 to 128
-- c_mux_pipeline_stages : integer := 0; -- 0, 1, 2, 3
-- c_use_ecc : integer := 0;
-- c_use_ramb16bwer_rst_bhv : integer := 0--; --0, 1
-- );
-- port
-- (
-- clka : in std_logic;
-- ssra : in std_logic := '0';
-- dina : in std_logic_vector(c_write_width_a-1 downto 0) := (OTHERS => '0');
-- addra : in std_logic_vector(c_addra_width-1 downto 0);
-- ena : in std_logic := '1';
-- regcea : in std_logic := '1';
-- wea : in std_logic_vector(c_wea_width-1 downto 0) := (OTHERS => '0');
-- douta : out std_logic_vector(c_read_width_a-1 downto 0);
-- clkb : in std_logic := '0';
-- ssrb : in std_logic := '0';
-- dinb : in std_logic_vector(c_write_width_b-1 downto 0) := (OTHERS => '0');
-- addrb : in std_logic_vector(c_addrb_width-1 downto 0) := (OTHERS => '0');
-- enb : in std_logic := '1';
-- regceb : in std_logic := '1';
-- web : in std_logic_vector(c_web_width-1 downto 0) := (OTHERS => '0');
-- doutb : out std_logic_vector(c_read_width_b-1 downto 0);
-- dbiterr : out std_logic;
-- sbiterr : out std_logic
-- );
--end component;
proc_bmg :entity lib_bmg_v1_0_2.blk_mem_gen_wrapper
generic map
(
c_family => c_family ,
c_xdevicefamily => c_xdevicefamily ,
c_elaboration_dir => c_elaboration_dir ,
c_mem_type => c_mem_type ,
c_algorithm => c_algorithm ,
c_prim_type => c_prim_type ,
c_byte_size => c_byte_size ,
c_sim_collision_check => c_sim_collision_check ,
c_common_clk => c_common_clk ,
c_disable_warn_bhv_coll => c_disable_warn_bhv_coll ,
c_disable_warn_bhv_range => c_disable_warn_bhv_range ,
c_load_init_file => c_load_init_file ,
c_init_file_name => c_init_file_name ,
c_use_default_data => c_use_default_data ,
c_default_data => c_default_data ,
c_has_mem_output_regs_a => c_has_mem_output_regs_a ,
c_has_mux_output_regs_a => c_has_mux_output_regs_a ,
c_write_width_a => c_write_width_a ,
c_read_width_a => c_read_width_a ,
c_write_depth_a => c_write_depth_a ,
c_read_depth_a => c_read_depth_a ,
c_addra_width => c_addra_width ,
c_write_mode_a => c_write_mode_a ,
c_has_ena => c_has_ena ,
c_has_regcea => c_has_regcea ,
c_has_ssra => c_has_ssra ,
c_sinita_val => c_sinita_val ,
c_use_byte_wea => c_use_byte_wea ,
c_wea_width => c_wea_width ,
c_has_mem_output_regs_b => c_has_mem_output_regs_b ,
c_has_mux_output_regs_b => c_has_mux_output_regs_b ,
c_write_width_b => c_write_width_b ,
c_read_width_b => c_read_width_b ,
c_write_depth_b => c_write_depth_b ,
c_read_depth_b => c_read_depth_b ,
c_addrb_width => c_addrb_width ,
c_write_mode_b => c_write_mode_b ,
c_has_enb => c_has_enb ,
c_has_regceb => c_has_regceb ,
c_has_ssrb => c_has_ssrb ,
c_sinitb_val => c_sinitb_val ,
c_use_byte_web => c_use_byte_web ,
c_web_width => c_web_width ,
c_mux_pipeline_stages => c_mux_pipeline_stages ,
c_use_ecc => c_use_ecc ,
c_use_ramb16bwer_rst_bhv => c_use_ramb16bwer_rst_bhv
)
port map (
clka => clka ,
ssra => ssra ,
dina => dina ,
addra => addra ,
ena => ena ,
regcea => regcea ,
wea => wea ,
douta => douta ,
clkb => clkb ,
ssrb => ssrb ,
dinb => dinb ,
addrb => addrb ,
enb => enb ,
regceb => regceb ,
web => web ,
doutb => doutb ,
dbiterr => dbiterr ,
sbiterr => sbiterr
);
end implementation;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
Jg7ZSB2xI/J/jQikm8Zlko862zAjpKBGuPSRLj2TaHEWC5rTzr3rFiYHZX6yv0DYk/Y584dxn1Aj
ZJ3fEMF2Eg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
J8XF87MjtG6MD92nYNEuYX3aIPS/zAQYepXrxQuouCoZ7DifIM+PcGRYhyHbT1c+x8wNqIyddvPX
H9E20LneyNoZup9aJc0KklSHkCBi4RFSlJYfEHGi7VuQ4DoNHay9ZZOx7KnkG5nTkuG8dZKhL494
1mvb9OIoIew9S5frQi8=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
FESqZcf5Kd2nw6uez2DBxPYJSBV8lpPPNkL9mii7n9rOA23QnwFT4gzsX2GnAKh0RRoHvqDgwQe2
oriJIgtSnO9GoEYt557lwN4pjAIARzzVKmQozG4a0ZADHcAuh9dE9U2pgm4IYqaA0WHemsJP3RdH
ZWLIA5hjsrEEni35ostJyYxky5xMLNN1/n6HMS0umCbRhs8srgz/a5uvWD7FFpEZ2a0utgDi9MEX
Ot7P9GN3AM5Ug4guXH512IazlVntMqLUCdCGexOO2NqFhGpAvwGxJCtx5XjHjmGW+9m1bqRxt0uC
W0qg1W0dWBjrERQ1cn2SGOV3FZ9QqHCbH1eBSw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
sBWw2a997MC11UDckC6eUhzOMD6OyRi9hIrFSmKM1LtA+EoEe9hBOU+xWnNJxZwh5q/2lTaLVnRD
SOXNd1eh6E6oJtNfyy/eD/u9oSEqrtEAnNkzfHKZvGwMHsKFUk23bSYe/H7pvyiU6gwLB/zQXKRM
aU3uU6qaXWsFaGyQrek=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
I+E3SG6eIVl+eQQNtE5uT75GDZk2w8MwukclTFsLuB0JtjwI9/9l+wqqevSEAZVNako39sma+Yy+
6sWVRLVPo7PjKtoO7mmywH+p7yQSorsf+a3ZiNjDaYRK+f9GNaE4daxPW5KbJ1GJwaVjbrTJXjms
6KviB77YrfOEwKiKJnAPEYDYIIKzPfz0pkPKCCTKaUXpj+fFxyjC7bycPwfKU244d5RTVzX4xHcW
KE2Pbl2/gBhqu0EO5W1xcfaXIFlrwR2GLFrc0Upm7pO12jbH3NSKac9EirjKD5ICy3GjrAPQM9pC
bmcrUujXKJAoYdm46Fb/QQhF+yxNF515651OtA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13008)
`protect data_block
iXdONubG+SYUpFk1+3xjbTmoWUUth5YI3Atb1aEXZ+saXE5+BGO3fPH5sUZBPpBGvC0XNFvrYkWj
mKjKwY2xZcfJ/srndO8S7QOgA1cW3PG5z/BUIxX97bocLtxDa3aP0B0gUaWXB16YHYdYTkHrQeeT
kByzxROgmclqf0h4i+dNw17ZHgg4lSONS85uKTmrmSH+AeVrAMTnAeRVAxyAfN5NPuWFW82kE644
IywqVXyFo+6EjcTaT9MuzpUSuPIiC1uoPJBymXXqJqXLPFIf66+E0NgglyW1yofbtINgNhR1sgx9
DeAt8JD9ezW0dwIbuBVdM7WPULLxlhRiEjVxJrWWqEe7iSi5KOvb5fzvI83hsOJKOziBELmUOamM
/T8ir8zwHa8BgpammyJqhRLzlVnk0jc0ui0l2oBOLEZatZDKIkibZ103V0P30wEv3kgy6CHZSlsx
o+2FQ+rWnn+NLza2SdRplpZXZVeaSlrNxSpEgYaaVJ1hfYU4shpw1gY2+WgUCqWSpnJ07oVnlkGj
XgvkoW7LarBgf5DSufA7OrUOvhEovDc22xsKo/6q9ikE/FrAsfq/b6I1GPuHTq4tNmNgFLJLqW0b
o15QkRHGCFSFVYp01JsJfRhVklzXE3+toKZwdGB3lL7SLiSo1jny3g5F6camzx2bFmrQu5Czeo5C
/YTWlRYi0Y0z4kUwtLuCniSOj5fXjvS+rZqv0fMbSpKDz3yNPptEql6mPHK324bJZULNhyCzaxZu
6mfclZBjFvrJ40zJfG+hWRGPBj7lEQwK9mvMkOaLF3QzB85I/PtNnp79JEkmMsrgHxSoHMgJJoNG
GeQSVZp39h6ji6XfgW1Z402TkKgSqu9DZ/p/XrxV+T9xgzoHNhQQve11khlld5aZoR2Fz0dS6DWY
htxdwg3F3n0HldhSiTENVbQCnSgvpe16MCIUhBeebBdANdreKwenIpNtmV7T3c/f+GPQpaMe0uyD
CAdVU3O6rVoXt3dusGugSMUIauBbyvk9b1/gmJUdGw420PMi+IvocYBxDF0DyTxNo84nnK+qbJ94
1vTQU0XHzhNk+/bfIO9wIOTa/xR7TnIbwelmHQ2DvCac7jth9H9aFIFV77VLdx+lJOWqki9wagmw
xd6Y0RDu6Fnko3AlZAnPA8AV/fBoS/o9Mbb9XenXcb0Gxv3pWX0F5FX3/IYEv+LqJ0x1dnqXRtJd
f3XkTKRhmAv1RHZN4Ijf/26mX+vAAf+WHJboPQj6tVKWcjoiLGqDoK25y5/n695WQznpJm0jhAyt
n3ga+4uHldOnqkP3JRRSm/A4D1m6LtnYsvrEfBKMXTTJyBxZl5SwwWtzjpQQfAmwUjmxt2oRGiwx
WQNGqkz+TTiFQ5ezlAWncaJscI0KVffI14NwBnVogLcYtDZjOXRpYxrr1uPSV4WFyXUYK4w2H515
u1OVDSE7ERA09Y3+88cM1NHWW0nuzw97Ca/B2ksxC+9UGpBq92Z62ZAfYE55Aa4zCYLfmwGVRBoE
feQhSr3J5McYr/O7r8Ns83MgdkOnLTw3Yu6yAGgxoNDOPqr31lpfWEQ6EBJJ8ymfrpl6w2iI0Pou
3Yt8LzN0Xb5Dn9kcNAAqwxEZncjIHsHGjZgKYuGELLEqeJFypgffVVzo69kF06N/3OGu0IsB+NZF
oNQ9CNZnL8ZD6tsKknOLbWTeUN78pkwcJSqYtXBgkyD9UOx8BGFgrNj4k4z+thMS4m1D1R1APj1T
J88qHzUW5a/i6Y/y1jxvgWiDQZCX0O/oRG76lZxPz4TlYHjWusiXb9KDRuPVTj1KXsjEKkQnt27m
ekgt9Y85Eg+SKoLC8QlLzPn+Jcm3krZYv0Wv7jyISxNzhIMEnrX5lGwQHMrLaX5IYgiOb6LFz6IK
ITY2vvm+uKEKRxh+aN9SdKlZF1F3I/lQJIoicGjJsI0/TY/1NH23//QzdaqgGMK9f+g4fHgMnvke
VnsKr37PDikQLBnz8VK4rdoHartXGc4nB9HSQbY05Q0EXZTEG7wXnpOXD9cG0r2pKjjTEwKlW1WK
XwBxuuNvLZY7vEMV7Iv7VPRzudJFyIsVj91zKTZ0kvtHkYK9/Jhpakiy4ooYnNPj/I9D5vYH11kY
K03oqu2tM2sNKJHOzDo12gfCZxIZYp/3Mv7bMTL6UPp1Kc41QS5EkOliFb/hBIpI598iZnnxZiFo
nswi53iePFr4IhvL4XCufFkfN3Kjf1ozXowHvE9PaNfeJyKSK3TclZgUUJB7DxEcXSrXqocyxOmJ
W0rkdt8E4XvSQ9RXnGw08moTmC4Ay/Qm1Hk4VROcz2C5M/BEbD/z3r3rCD6G+I39slabSKb3EPL3
yrBJHvH+XBU/Og2/F6Y4BGtbmBqc+F5Cbezzs97Hchh3W3YUs4BFHq2a++VcEFyHwTHgMli9VaOY
w2XwIS59gPOO1G3+YudsX73xWFwLxSGEqElr5GNcKSybx/KUKP5fuA1KtcxvUurdTXSeBDqf/vsb
KDBcshsTTQzLHqcmaC8u4PSTzQ4l7S73EUXoM9h59/9naeorj1kALVcSetLAa4LyKoKpxpfrlObn
rL7OH4Hnjr6Xt3C5YcPxh2yGykFBndcoUZYxzNUeLBqBjfYju9soiqCkwcqCDBojqq/Z+t605AzQ
PlXjKhmrcz6ds7eYwO1u4KMZFAC4HXvTNL25zDJHkxcTZzcax8gptFOxcmyBZ9nafcZZ/+cu8svY
5OGfVdRDFOlq4Y2nRCAxb5++FTVg0oNkMP67MsAoGCTGfqFHS0mrScicIetb/lC+TbNO+Wx8Nuvo
jOhSu7tAZH4FwoFNudmSrlrGXOVPDeSb95Wvl1EHIVJ/Bt+g8jHN7L3EuP3iYbeXKJNzmhruepU5
/9pGEYnfaVZv1EKuQD0tsS2tShyClZNZ02zxc1YKjbJF/98+1kndtLO0JqmeBEH4rtJUuqe7mh2q
3HpCmfwguA144Kp23ARkOQKAzTh6YE6taVcJGIZlE51FSZyJS2qaXvOUgyHmpQhhl+Qxu5eRp4CR
QgzCw2U8MoWaz4w04G4jBnldDEQkY9jZIq+iS9RwoHGYNmHbhjhRvjxbtqzpMvHb/qKjvHeLin6o
DWEUotoR4Vrbzse2tpKJagIlmH0mstt5BRRPIFMWwHml2VAoln6STdwmzqHItJ6M1wiy2xuBiMOF
jUrBgmufBslF3pAgUBsF9WfKVFnAL01FY8FVdk+WqWK8dUuwLxslJ21FehhfnaDHm/mGR+l/ZIvC
5OmSQaWH27vJT9tlaf+k50s5SF5h9+2C39bKKqW3vSiy3QerLtGmSi6jOHgLfeJPXps+f10PwsjL
fu5qe3IpeezwjDGOXOD8p2CFbqt44kw+23UtDbUfSrJ6wAs7MWNTdUpltMm4hBdW6EEu4Azr8eaE
rOo76O0rP+ct2UXu2buMDccPuOXRwDdptZvw8V6N/qk6ER21uotJk6xKN7fR/Qy19SZYyc35NF92
oMxdadmKfm9fstBbj1aQUG39cPtIBhIIGxUtI112wstvH6fdPb3Gc/7kf2XsGSSawaj3yusoei/d
aYxfLFPeRcORl1oie2nUPwgrzeGcVBicSBcOTGut38nPCyDBKgPPlqUCYDAlWL6e/O/F+eo3HJ8+
Pv8/1ZmfjG24OpCOUChEp76UToTNv66MkIZ7mi/n1fRYk0B/bs7rZytYIgOZEqlLQlqcZ+uKP7pF
gp8kYzRYgBlskLTPWHXesRRfAklL7mcfyrb+kdJwBKowSRhzpbaokwK1C7zDb1obTNbfnr2IZuMC
4Jkve0+vsuZsZDLKWVrVL4gtmEcdpo9dQ9QUnMKbIjmaUtwMQgSCsRzJJwYy9GWDRS4tPB7V/uMd
WkiXyEPITTQxDOQV5famzC1g6uwZeGRNXKKl6Xf3srI8MeJDEr24ifgrZI5RhWlgne7gfOOOHcSb
cfj5uEDoV9nUeqKBPNQCGDJKzKNK3U4UWIUQDwxcby0iUIXu7mcRrPVQ+i8ZSIkNv7uQ63qD8FJ0
0PnuAovE/oecSIx6Us1avEcX7YzKkqjLUWgs2LZOJPMD6dk8MDoMo7ysX5Sl6Tl9JF14RntPqd5i
2mOS72ZPwr9U6SOt4tavm4B/XYOdmY3LdjECmA+G+O9xhvQeiUbpMmCIQGaQ+JLdC43Nu51CMH+m
bsHsVrUO8pxdQqrRm5yGNtBFQJqdg7cWayjf2D658JcIp73SPJd2nsAV1KXVI2I2++AhSCex0spz
H0+4Xjq4I6wcBpiB9ES5IPwBRuCAU+KNF7cxUJfb9AH4MtrABYZp7EUgpGF3kkDgbIMWWy5kI8iQ
gwoif6mSiXdAR43lYDI8ydMmi1P+QqvyE1uwf57rwrXcT9XTolTEyHeathKbcF9H2e/NusWFssxn
ZAsHucSrjOtuhevUZv1j+NFO/tsWJEgQUWwHFUSHl0tSZJr21Jtv04QAXDIe9uKviuEi8M1Zye2q
VIB12DuPRPB5Y5ZTt6VJEynbZczesS1k6ndss5lIqg4YxeC3iPwEQtab/YwbJyKTlDFjJ05Z3I0a
5V+JL20SaQEidsS8+tML5OVYqOF+X5YAnPAd46ujVVHrWIUqpcTvJny9iLXWMp2puwu15oYG/J87
uOBUIg52PONeRo/2ZROHRSCXUnPQQFvIxzzNph+Jqt5ZIXMTZJMFegj5FhwuthtnL7o7o/k8Lyey
YgY+A6AeZeXkPNrO3/jyNDHcx8ngg7j4n4zOIMOsYL1Eq5h2QYgfEDCRImFX+a8vMUUFhFzlUq8Q
+YnZ/g5GghVy02e84jV91RSbdXodjfxIQtHYXE6WajRfQd9Xmc3BRk+8Uk+VlXiEv+gFdtE1jMEl
Y4J6vlUOaVEh0nfexf06/T7jVeseoM1c9nznKqaRyS5cnfLG1Xc/l4idfhct0jnfD4xyo6ztKKc7
ZoWW//Ob3qeNG3mBXNZQUJMmhE2P89DViTozT+GQTzA785Y4apmPojF8ZI66ombhB0Bej2RInX0L
Wdog3njTuUmLQllhN8s0QQIfhHteB+eIH8vSm4vihPzrjwPyRL84uuW5TibDb8uA3j2aXmJ8sARQ
ijh3bM9ltfHOSh+gdfA2CwTtjpCuJPY18zeVTbwrjKjXjO5I50Svt+1f62XsFYJ7w0IzUqVuGGKi
IQIkrQLlKPh5bBbBhVsC9dBjmkkRCGBuawHh0VgUNV1IjwtHW05jlfEyrTJWjUlntujZrtGWGc9z
VRjyV83unGC9AEscKVLm7hTcgw1Uejk7JhTYsWrmnXD/2yniLpA31qEtSZdL4A+bEwKAKbWiQxsG
COwzFFI8dfZ3qGevBY8aA47DZ5uUd0z1t0IeSunBnsNh1mnMj3oOS89PX0dRhciuDE7dbg8+0tBW
9EmHn3PKRmNL1ipXvHIIfYuYc5Od3somla8JnQyl6jBAle2+RUahuA5yMVZLiJ923n8qhGYa7t/S
dKPTiknun9P6w19cPSXpI4v02Mjg5ALkLsMe+4Y4TqElQ07w7hiHGsu7EYCQzpVovud5f/db+g1b
nI9MEUV4/hYX4rVfPm8CDe4KkNvnGMro1E0JXv57X0O0escjc2QvaFP1SNc9KVhyZLJ3lYvDXd3x
YVU8eDke68BRejyCkl7EsUFiyPvyFYF6Vb4XpEWRIiW+qCj2eTK3JY3aS5ubeehk/Df3D3xYofdw
Ps9O02/Xns/UUZj/VWl3GeoM5uK1ckObVDlRwnQlSIa8X6EKAtGbeEyKDtZ/wF9Cd9+6zByRakKG
yAZ0kiS0dH8wvu9JtejXD0Yu3vjX6UgRJprZ9GYUKRN+1KYS/OlJ7wFri824lniD6LCqZb7L0BdN
l4AQ6kM4NrXLDT427YeMNGPoE6FY5QyFuqPLdFUJ1X71o6q6ATkecmV00kaGAk2x2TwwVpfHHpTj
Kab4Xhl93ic752GhbFNJw6BBquu6DFjJEenEJKGIs/Qq5lM1W9MQ+OoHd/On8K+ThjECiWzVBpbX
19ZnKrWbyfTNu+idotUkQRkHnMZfO1oe+p4eeCIPk2f4sRaxVoz4jtahxDdZzrqbgs2lXrQ+h92Z
MJ4JqtyCA2LWlrYOiTgfV6jeJnOT7p8EqA1r5gNMMf73uzJqRhTbLYdhoqY1V9brJqIelEZGwlIV
eObr7vF2SmXqVv+D2+vRjpT9sANMCBFzg5JJXtAYiHbLFJ8WXPAhwsZkuoP/a4pQreq3LHnioRRA
NlirCIpTHWBjIlScqQefBKKuvJKIAZwO+0G5Wa9FG/eQwqM92Ugne64Czm5BwKe1nXlS4MqmO1um
I0b60Gb9nWnTtKFce6YOmmSwUB/FFOT+muekdItDqFC6AtF+AvtUQ+LxE6jEogPrV975od5PONSK
1XCKPqiO75OrG0GvVL4W+lvNsSWCkx5ezq+J+I4ba63UyxL0UJ7ASgXjyUprZVizgkZujeNC59rB
YTyaZRMVtLjriqdEgpHVnA/Mp3OaA/WJJuD4XtLIIkizKKnJpII+saXW9Tzz69ET5zQhZ2lTxjF5
bAPXtnHSYBcyt7s1Junm0aBhPpsstcrQt7A4CDyX1wRNxsrG6K64S70LNtZkzN7p/toH2QOd1Ntn
vk428QrP2w/+RDHCWuPAXKJk1GKTaYFb9o2RlxWMOf782ar2knfS5VHhd59BblwWY0nW2IA61OCo
4OxPCxRPE0HUO5Iq4wg+HMth/Anm8AdPmfHbIYvwHtItB+bqDht1Hr5pQkOydqpCJvnPvYtauzq9
rTq3A3t+nYHY1Q9lwG9WfMcGaK4de8jHn9WrrkEwVnnLj21jZlnV0ZxET7ZlY98c02e1rwVnrWr+
Je5t8HKCBYOR7JCv6DaVwvNIAoqVP51AsGin6sd9h+HhA6aVypIaWjf9tyloV/NzduLhvfjhcV66
WNNxNcgfaDRoCt8Ryd99nsYqwm1v7Tq4EtN0gtX+WoGxn4zzDoF8M3R+yb9b+7YNchfY5n5bXQFn
MCE3vBHAKjWg5uk1qBr75cAu1Qca7g5K92MfGhc+jnnTTux0rvAu8+tJ6X+Edf5DHKiflbQgiG9J
7CTAsB9Q7zkjtJcl7OcPuHTk/3LAHhWdPeIm1LX4NVzF/kt1kI5Vptuu12DpHErhezSs6YWCLAr9
6A5AUIXq46nPZDI79z+GCMgY6Do/KG9RHrttH+qyncHGFhJFIJwAGmHFyM4TXAc56a/ioJI75zBa
csW6uOhgYQo1rVjjGg0JOHgoL2hiSo1cgO8FbaYeABImPoC6h+UmyWIrHPEva8RCDqBIIxYacjF3
Sablky4HqOOqTH3Po3i1W4hePeUWVfmiHqGg+rRQvXt3I5KcOa9BHeP8PLH8WbZnHhybI90AJW4B
ghGrLgpA0BouIjoGXWb28lm9b1cn52FbIvymS/YVDidtBow6phD7ORIC7RN96opz0bgfDpBsFfKk
C1g5JN/wmgOIQ0XanlsorghXFG/y5P9M6hRDR47vsyrhrmea9/a7kEhdCuFyvPL842LMx+nKI3eS
FvJtjqUdksjTtLmVF8b8u6sqwU6UFtHtD9r3ZhLPKmoXtg9KfoRBC245DQs/EvRySHvQuseOcjXx
5RkzTTZ3jjy69kCHaFf8TsIzpmT1k2o6SeItN2z/XLhHF+cOKcMNTrOPKzOndIfCrhVvXL1vUIfY
opdi/RQbj0WYsFBlZxN22CeeLsqS/sFkzosL0tk/QrsDCAW2e5lDVZfaROYbFV2DVaBtCaPsukxr
ii6dJlm6iBgbH592u+f2mI9ze3K3bpsNH3CfLCIYDDI55iw6Qwnxg8cyeNwWyMIdLanykfH7Ju8c
ZcGGHpV0gE7uf5qc3HOBJHrSdvYc359vywTxDuP9P+SJDyx+t60gzygUEutg3fdY29j2wgp2D8A/
gRAG1SnHdPc55yCIzkndYxPE3e9z/tEfzN9bpWTkjECzzAYAeBBClkKk4paB5YWIjvLEVqoh0jfA
ZVK4BErzQihjWblDamZIenulFel5DULaJy+tH7Htt7XS99+kxeShV3OxFaxZmv2wZlozcdBjCWZ+
ibrVwA2Fw4qpfd2/mR9C8rkmZHFEyhlqgOObFsCbVRVhAPifX+s1OAHQnzvqqri2oe0KqyF8nWeY
YkcYb/hkSqPmV/mUoM9CDDcgJQ+MssByY5UZxPuSg35Rlo8SrIeat1xZbZ1y4R/59kJonl4hERMX
KzK/D2HsaS6LuWMCBBAk190mDb1DELlboatAk2U+ynZWeDcMUgeu7V2MDcR+56IG1e6MK9vMw5p5
kyb4IC0NudHIppagDkhVyqyMLYHhl4fbHjw3zJQwP5DmLffEb5u1TgBzbzxhqvOlYpBCjrIXvzo5
JSFcaTA+aXCzM3WWjZeX0dSP3MZV5gcz4e6tELgJxNQhelnifyxFrqU+OJYBo8oJUKU4sCKPafmH
2Dufn9IKryoxUA59p75/NZadSANaqUvLXoqQoRVrbKBRrK9TINJPx//uJsJ6S7btepIbmQmJw7Ui
lEkn2HbtLf7cwgdXyCjgKBL9z+onHs1P8Q78w6U33GSl3kyvbK8KJhTDTcEvB3bHQCd4qeuM4ahE
gk8UNAIAZbbTnza8Y8OhN+gGthKNYe1/+TmfuVD5AB9HbsIB8bazOCqKyifB+eGZVQtn6uB7ShIW
OdpMNUZuhaxwTq469qaRr8EjNS2xE06TFRrauI9CRpMBCBZNSFyTIssidoQWA5JVHGO6eqyXwfgB
vB2BxeV7SQGitHtabgdw08LzDXd6ctJ1tKT2OCht/xesY4Od6hO3ra+xvEGINCjT8XK1s9Q4P4u7
R0GKZ7oa3h3BylbAaJq5fKMjRqLGkXFvjWMTc6rhESpWck6m0TlmfdsXflsCxYWLEibvVDaevwsT
E+uA1UOEjCr+SWq0pClD4fxV1IqCSIwD/hgVnlpu03nhBk9PDfmrDaSeHLKm/uh4y4ogBCKQtQT1
JmW0IgNIaA13zSdQN6wD6dryxMF48Cc/THO3QtA3vl5svNKVWk+mEYu2tNApzArCa+Ifl+x58cC9
9RTOIl2fc9Gy38ArM6S39s+PeEh96xUGVCbAueyKhiO75V2yVROYvgGkC6Qi/KAqaEirBS922Zru
Ye+TY6Q4phjpf/CHGsK0WpRIwokqgkhZ14OC//k+ax0V3DhAJqQ/TcPI2ooG2EpPNdNPYrcXwXRp
9ck4cTWqITnoGg4hzs6/cxrjxIE0OhNYgLKht8zL35OZrJfHJ+KEVNCyOw/JMRpAsB7J4/54DcTW
FsvTSEABYu0I5LqKvs/BLx2tmmXjJqpjTFLA3FqNOPrrfhGkaRxQtAytJKyZibGWAgx1mzNrsrIN
+C2npOErzVY4oGBuXXV9X0qmwkQ/aU7UIyKQa90gmpax3j16L7/R/v9Do0W88WlGrCKZwOiEWfce
kh2fzKBoB+AJHxikJOg6488LLmaxBrPcA4O77GNwoOgWKufHrGUc+MJpYZhzJJ1I4O0l026xoXXo
LfGceXZT/vdoovMcrGf91X099uQQsDy8jqLLziX9f+6qIZUHx47hD4ECXJXV6QyY2lQ4h+gJiOzW
hP1yGVP5PD9jRurrtxcMEuYwQsmIPutHpbt4inFagIVxVX9BbPqyLsiSsfmKkGK5Kui7tWDDHIA0
eBmaW9Xu5hOBy1+qLvCOIPX18643fQWKajUy9kWmB+s9itfVOFuKKshtG/SnRpe5Wetoztp+kuxH
OHaxb4zGcDpebbDjrU55ej4pFpJgg38H7ljkMiGkkLGAn+TwllHeojnqM2mghE1tPG8vjPHD+CMY
uj4exjB1GU1JGByWyms9F0oRdvKliwlIQ05hpPAyMEIoiHHg9hkaOoKrQ+U5vQVga9ofIcH0BZ2L
TEFBqYxtRkqi4yYYMh5zLQ+fJEGSVs0ajiLIwoH1KKmaF1eErvEW86s3d4unJxkpkb2QxBqkebLv
JJIQglskZ6GmqiO9cPpVueo8cyP0ZXXzO1gdxrpLVKx+QPyPIwzRP/x/j6EEgh/rsVZSK81enbkK
HThbYw08GTi/RjVybS7QcsMrMB9FbuzEEAyWs5XH7NlXRTzjwB+huO/s4/BtGuaYwfvD1cXk/UWd
nqYfKzMwtaat+LQjmbPXAHvLdvRbtvSLJLWZSxVURGl8Ez0ZuIyvn35lFNZqh6I1QwAjFQ8WDl7S
9ZuT3xlLkSzxUZOUfC8QdaYV+oklrWZdkKm54M9bfeNQfeRBvylbzdEuIbgkquF02UOH9XJUquuS
Sw0qNuWzAEAK4rLchd4NfuCGNl0J+TSytnoQy/XzF5H8qSc2SQuA18fc0o9Jl0A+dm/ZfdbfMPXU
XLz5bFi3TQ3Jlc25v8IJaoN744m0G+vpEdMPPYrqHz4sXSbIDKbthpOcBfqeTkf+lAq7OG2e0MUm
XWTkWs7LMG8gLWzgi/QEryCMMmbub89tfonU2WLEzS8DyNBeXNj60RV1Xc+d0YWUXJawbOTH9xSD
sg3FK1palRgTIyTAIZm92pZlZPYnu7Roff/MBsVfIbFL+lryo+IP2H6+RyijU7aNlpC5ckqeJTOa
Lah7+s9892HqcXgQ2r3auRNlgI8Sk937dlmT68UjZdWJpi/HLmrCNTVCb+vmctVvQppEusxvG0Jy
kpI1bkdgFQnYIPzTWTODGyjCnghdoRX6ZmfSmculY9PnrF5vJGCSgOpDbZIy++PoYNN/ca9pwb+h
TXSnO9khtCRrt25rryyYrr9M+bUWr6OIr3ud8EaDfMSVCzGdNDBC/iJPfnXYTvdTC7/uWz9v1woz
pGV+m8tzkZjzBHRhDO4CeGWSR3/5H4K+KIHojAT6sCVM1j1wAXZfa0bBXCAiP/TStnZ/UputQgoS
ESPZIVRO4tMkHjNqhPLr0XwO8rmlZK4ejmOWlsYJelRZ5iKeJAKOfD6aTOhrR6Gt1rmz1r5Oe+86
JZqmDk25bLMoZZXMeFrjp81q+KwjxgnVSThF6n87/Z8Br+h7sRZZcjWKBi6UhB7e/XTroPxTNudc
ypLjHedZkWxBnpyAy7HpSv+YmOi7nVDh8opsPlwmMcnyRo87+NKEbI79LVlM/l0iO6Fcfbbm28IL
nQbzcjckRBPNb6ERDo6fOPb+NfdVhDlHNy2QeNc72nI3H+pKanVLjstwurg883OZymM6m9bYDLeX
vsRwJernuWDwDXa7KqyJHa/B/eqqMJR/1CFDdfQzfPr2GRIkx8E23sCVgfEYC8UpQUMMAdpg1nAR
ykbIzOa9QJ9c1RGx/hz0fQuUduOb/a5ltvxQRTySNojTlAdncANN7ewSXNJs2Lpp9S3d4j82cMbt
1o2k9pl3ngSxgOOp0fm1HfKjaX9kRMyDbTq7WsAGxwjV/c9nCtmsWxIVGccFSpaNqMYiusvV/0es
r1/q4Fs46kQDJWoi1uyjoDOxxhok+CLmhPVDTlI0ZZr/Y6cwnMuuhks14z/R/YocI8AkGVW+HH98
VsLZNoQIFlcN/SgbPdnaB0OsGHWOsvLUjeSVTFgi7LhtyP2x4scEDCFLfnlspPF3GjbefjIiNEov
rReMj8XKZIexeb9IQeclWRSwXowB0rP1imG+jlL+D9zOv1O8cOhqhRloK62IBi/Wyv9AkmX7EBeR
Z/8wjNay/o4TW/8RsdNOT+8ok/J9vIn5ggctes7WCP/nFkP2WAM1nABVzqyPW26FTGgOCSJ979Fk
x0toxJdlkxb3v0+7lyz1sDv23dt2MlPHqAws1fLdkuovJoKkZ1dlR2NcYCZZPhXjWgvzzwJHlOsB
8gL1IRBL+zYIREP6X3E1poTEEjOq5+tVhVW+WfQBvn6K6xJfsD64LSuwqrVkS1mkzj1TvHxBgRLh
IitT/JuCh0BbwOpt8MsdRQYSA2wJfEG5LoyQsaPpqn2B+WY+1icpU894ty+gRfAAeoIMfCrYMTC1
QY2UMBEuTUb73zaWP6Q7x62Y1YNaD9XESB/ZqWcKT5vIILi9B7TVW0E85E8Hv31PLvY892k8E4LH
huoZ7k7QPkNFdr0xNSSCxH4kgJAXcKrDZ4VTmOLFbUORZFvFEOI3nIV1LRkpvMdO56DWOh4JH78y
YGL9L9QZzbHeQ6rTMNo9CVCa2A1E4zR1SamoBYYtCyzgYKWSwI14selgW7p7Psh5CPcPlQga6rx7
VW4VzokHR07Iq4NniBqqYUCd+RzWwmALqHgpl2U+DVn+4ESKLisI20E0cY5g/ZVY6kMwIQuqWbA5
m+vnwg6f/GJp9gaLfGgh2zKsfvBeHq0XmFw6IQsZst3amWm49qs4uc0dZmuBZkmKK9aGbDnJolL+
+HL1kGBLZUO0+fJin7bYrRHIFYYoZbVYSzy4yX9TgenFG6zYnHS/l16hWZqqfSRzFjgyVwVKF/9E
MwnqImGOVyQ7J+n7uU+AAdP4VR2x3Il35Dhkh6+alwEtB1s/cSs3aiHQ1RKw82qd7N1hEs9lBkW3
BxeVyN8cfAPsmg5mWb1ljOoSb7iX64/9fwuvq13w+piUMxoRXj4bYRn11EPIg3sNkwKXyMx2KJ/J
kuzsGL9ExkUGmzH1Y9CQj2N4Oyx9zjq71VmAzX00Ej6+bzJ2aklj9tv+DnxVIyeoaGvH+3XvFMRK
X/BWsc7+QJfE3eyG9N+YkeZonu+cU3qYTNL+Bw8yamX5zgP4v0k7wXJvdZzCytHB4yLj/F0rW9jJ
arbRSAbHAjCJ6BD4z4AkWvZiZR4WnQ/KOmkMoQrdHRkVRI1QJSXEc55t5uJKmu/GhhfGWPg85J1e
lJ1J3CCFS6e9fG26WV6mYdIEsdKlIKbQjD14w8Oy3KHVczWo9VvKAH12y+g0tdLD+Ag3uOOls7iv
LQy5AizOtPdU7HV1W4NNyWMET14SXbod/LE65NMlIM6jGc8ER0lIKnUfptsVKDF02RLR1yNhn/d7
fmlnhLCRMM51bqDQvlLiMocGsFJCzKw7HBLsASom6Nd/fgRF8xvbwDH7OUsncfeuJiC7AZDAdViq
rC/oB6QwI8TA6CXGAhiI8N/xzptIZ+klEWze4ENMstSH6LlbbIKf56od4VvTTkX85X/P0xDc3Fub
daDexnB067MRkmm/eupSXI9D3OLHr2rPzD9QvGe9/w9P/iiD5p7V3K5qgVcejFTdeYoPYsNJ5bwK
HoN2SRwb6s9WEHPBNlJi+Rll4Xc4vxclzF0plhYWBZVMtDEyeGRNekfz5VariivlbvA3ZpLA2Yzj
lkjD3EIraEnwqDQqT6bBMTHD5sPvIaRuokoYdEqiaL75ZEY0ZDhy4jKACuS7prqhn60SoXMKW1xe
LsJsUCgdgKkCSe3fSGkAZdo/bK7crQ+mqvsbtjgE4CNOxy2T2ZpSnJBhTcVPvhn8W1GB+EjrHIfa
RS/P+lvWENV1PWi85odvoFPP2VWxqeNQ2lLyii9zzMmYNbMhJjF087p6IDPyNq8HwAMNgs+l6JDC
tbOGYt9kMB+czH7rbWe3xWp1yavknXF41UVkrYMYKse5LVvQtHlZJdg0gtfoaR0vCSP7s/6oeFjP
6BIJ/FSAyeLSP4ObMAo1i2124f97gbP+7pMTNSLNrLv4aZD9XOmwvtdixrMAQRZscsyTgF2h11Ue
Tzih4cjJl4bqW9gJ71sWHEdHYruSGcCbrCe2KbJA+9hTSDsJtfdXAi7m3bjL+OUQ8m8Xf9Cfss3A
NWEuU8lRIeO5VCOdZKgO4R2RB45lJ7NyUL/RafKZozgN/i8t0FX+cklls4L/vu87i8A2NgY/Ok/K
3690T9KSdZxIO6OYv25l8k0HsygockP4QhDUPForiNropyUUsbYER3yeYZUf2TYlpEagET75rRI1
2PBJSao5eRsqhbhT14V8Zv4HYxv9GdxzVHZKF86QtR9bEIsQnxZ0YTsovwVzaRWMTtUTedn5PZ8U
JZbkNq3zJUCq+n+TulivCxdBkTIsorpT7+a/+2M32u3M74kvXOoDi3emCYm9IuOFHwaGQgoMdPmt
lW8iLuKKqy/MccgXLz7JfJnxYz4JwhvY2IpupqxdlsttyuXfqS07tOCP47d4edKCH9D/W49aEMRU
/SgAFUdOIYbREO421ZjOopEfuA0eR5ygDSkQf6dGw03b3TGsVvxwnhKERefF5cUeV+Sxz1KI32WH
kcYc6zgntxT8eRDjhp6d2yWx0v/ysZzNgTgMeB7mbk10kpnB0b7h637z8iX46sfMXq0JFomI76v2
l8I646CEQatWvxmakVWdrcQ/uuVvFvBl0OfhYsbgPw+tuRiGwYgzsFjSw9pMFWJoKbvHZstD+7h4
bWH63Vkm2yzLSoks+9wPdCLqKeSvHGA6C9Q5djsKn2SOlauVuRIQyqOk0YG8tIW0Eic2zMUYCCIt
6lz12rd/usiO10p7wiIvGXidb3NLI+MwWhWAYMCUG+Mgm7APMJbbHOm77fowLz5zV/Rs/6VD4uZV
nvnxRteVagtXXCkiMD5W4InZgvq12Sj8hppvYJ7oott7UM4jff2ziOSUPdiu6nhrLpBhi6dzfLec
ot4eLfgPVkW8+xV2mWAN891ji+mc8QBINhSAPLouZJ8AyAGvO83NB6GnQM56MFpjlaYJS+4TFJ93
NTLyvmPInQyoZOajtGRhGlsgdnvEdXSPAUQ2BZTgameaBRs9LsPEh1Y43+J1uyRI6fXErGCJPg6U
9efqVgRobI3Fhgu1eItNuLOseysDprIlxIz79z8ySo+1XLmsZgKp0QFaX1Fhq0wP4t481WIgy/kj
/Z+FAPOZLJbUG8sEo0Vih91S2sql0GY4yORoVZ5zx3JHiffCeCr1tLhT4sQRlwbzY/y1xSUU/ZDN
XzUoPCRrTHxApvYqOFPT+qFZ+vi/UaAftQNDVQSBzxFA/LxopC5pJEVi2mrYlZ3oueUTx3EHOp82
b2LiDk6UPnxZH0zdPQBtr13TPjTgJfFL+FVLUvzqeOJDwko5RYaLmcGYxeVa2Gzsh3rNW1KMwvfE
c6IVV/+g5jTz/iHKpFcOWclEqqn40rAzHXQ1QNuzXzKAOicqI+KX32Irf2QVTl8178biX3+3kusr
eFOsv6836hr3DjTNf7qAkGrCk8lChd3V9iYcEOQZ7KRDykBXfpGU7Qk+8tzpU+r1cj8AQ4+w0CqA
lDlfONdv6Nk/fq/RAHmVhX0pd9fckbonJAg72zazCvO4Xn3kAZdp+2Nmc5UwjN+U3egb74FuPKGM
NdTRLPvjQwMoP9mg2dNVH5iC0QWcY3Dj2sYCg/ALXxG7HV03UFvKZ/AZKssA47IofJ+Pn2oO0oJ8
w4ylFe98xloVwyv9NESeeVPGuYr+KirBJ1ty3GkCRF2HW8tBsSz60/QeBMe4ifhzlJIMcG8FKV/z
BqXUDYpO/W5hogGEpE6s2Ti3NfXxki+jXlRWo6YVfhKkLHMH7SqCFx+c7XnrYfx9YP/DSwPcT83h
+k7Ciey0cMYNVyFtdbOG1LzIJM+5/rCq6X4w8nlT/2ExfY6kYObFismDI2oTpszqR7NiPCpD45P0
z5qRNXEDcdzbECsgK06+0jf0B4a6V5Yt2YlUklRR0IsD/51ucVvAX+yUG9X3PcyOsm05iBRlIQaY
jvd7EOa/cieRbu5dBACs/2C8EQfbzPznfYNV1mvXkXzSXC9q7KXPzzHOsug0GCgxikCMHeTXHDmX
lL24pW6pViuELSQW14IeZZxhh+28/ciZ8iJukv1vsh40gw0E4hMC/XtFUx2kW+gPrwrsT4brWrW5
imvcjRWjPCOdNe61DT8u+PvRBAdA3kGSjbHEHF/tgOfmW5EFLavF0osXZkwRbVsnEmpR1Si+ISbv
Zozo4j5GHr0uC7CyOrugIVncIAJa3AJY/vX08GlV6CxqJ6j5HbQLEpRF8XR2qKA2xhZwQMo9N0mi
2hKzfoahmkD0OjSTbJxfo7jJuODAYAbfFFb/G+5ieTbpdbqPQG/iDpl4XdBuq+J74suA0IQCxoV6
UNNdNPlwdxC0jxh/0mFkfX4poLdzkjipGkvLLWcoBhAuWUSH6ocifFwdnbwkdljh5BNvq6gHYQmO
K8nfdbpy4Eonr3+G28XxsESbTV9iSSuaWQq1imTZzbO+mqmRzOJ4GPUsgXttlFI1eQiFaKRCJvCF
T5BE5DEyHarpSPLseU4oTx1A7lmQT0WLQ9SCDRfGO19O4zSfERrpSJrO0U/4OA7EUmm47WI7aB6o
yjS4BhSJSyu0YJQKBr5dHOOJ77XAFA9bYOUROkWOtnQJ1bKYoPvTtFXkRKWzb4S8DZWysF/N375s
gsAWoSsWKLzIJ1qSBoo95UJi0moAplGlxIyw3il8rHPqc6GdqMGlTc4ZzhVFiQfep5BR0KN2l25v
L83ot/fSeYjClbRaEiVGD9YcKXTq+PYuAzHNNhv9SywOmGwHsEmMASLCYdb7uuYHqqJkYVpbyirq
YuYyBDQfOni3tDG9iRFiHImfYnygq/VjpSUSBaqH3QxZAnkzHkHf4OJmn+IsR1fqL+KwNu3f0gv0
19OlDizWlWlJ3e6fsHAvY3nPBGtNaXHX7oPtxyn8ifZMWSHnIYD/WyDPBLo82U38Z+rf8q0raLPn
gha0mKz5AGniZcghzxRzl4cs9Qh8BhtD4qPmeWujP8l9/i94T9r57T/xugHTa+xnoD4N/+sJjBB0
C2u1OIZTbKsp1UEsZtfcNrNZQuZKmI7zaSfkL2/Kytds6DAO4Jgxz7uP1AxpcDwOduZrqiCXu/ai
DnVCs6FQkKNo81nmYR5/jkX3Lq/onKY4EZguAqpAGLZnyGCkUIgmu1cAE722m7L1Vn0TZLPPVMCI
N3VmF3BW2mdpG89PK4XoX/dmQIsqQN6h7NF1VNAk8DaDr/AvzmN5xxiH1YXwbd48aP/n9QW3Exxu
ohad+9GfvHaHaNarQw+JdZQOvo/h5Py/O2sZ6ljUQKyyene+AlhFSuy82HHny8mG2Bs6gKBC0Rjh
3hdGnsrdCJOetyIxCfS5W22xEm3c71sw9ayszKSa69E+Fc9PTbyWvGw3ATi0H76drtI90UGZ/lMO
fpI14KeZxrDGAhOu9uGsz17i1mkNPhEZs6ul7EZVvqWOZsMM7kagdHCyeTwye5IMZVnmTq3Q8Xwe
4W9lMEwrY043Ne/PRNKes1kU/+ZIX9DrFtWqirH9dFEeBnuy4072kf6RmVr6SO/bo2HUso3ZQNHp
WnY6TTvUrJnoDK8ryAy8UcyOxHvfab0dN2bSkzyWHJ1xeY+kDyWgoCnNNJzH9t1o4dmN6AhC337g
jVIu8YNIa45p3DwLYeN1Fv+FSzw/hzYpZMcM3URadSuYVQkAKkomh8LZxX0D78pcjJlgndp6hehi
bDjKlV21uTrJiR5N
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
Jg7ZSB2xI/J/jQikm8Zlko862zAjpKBGuPSRLj2TaHEWC5rTzr3rFiYHZX6yv0DYk/Y584dxn1Aj
ZJ3fEMF2Eg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
J8XF87MjtG6MD92nYNEuYX3aIPS/zAQYepXrxQuouCoZ7DifIM+PcGRYhyHbT1c+x8wNqIyddvPX
H9E20LneyNoZup9aJc0KklSHkCBi4RFSlJYfEHGi7VuQ4DoNHay9ZZOx7KnkG5nTkuG8dZKhL494
1mvb9OIoIew9S5frQi8=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
FESqZcf5Kd2nw6uez2DBxPYJSBV8lpPPNkL9mii7n9rOA23QnwFT4gzsX2GnAKh0RRoHvqDgwQe2
oriJIgtSnO9GoEYt557lwN4pjAIARzzVKmQozG4a0ZADHcAuh9dE9U2pgm4IYqaA0WHemsJP3RdH
ZWLIA5hjsrEEni35ostJyYxky5xMLNN1/n6HMS0umCbRhs8srgz/a5uvWD7FFpEZ2a0utgDi9MEX
Ot7P9GN3AM5Ug4guXH512IazlVntMqLUCdCGexOO2NqFhGpAvwGxJCtx5XjHjmGW+9m1bqRxt0uC
W0qg1W0dWBjrERQ1cn2SGOV3FZ9QqHCbH1eBSw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
sBWw2a997MC11UDckC6eUhzOMD6OyRi9hIrFSmKM1LtA+EoEe9hBOU+xWnNJxZwh5q/2lTaLVnRD
SOXNd1eh6E6oJtNfyy/eD/u9oSEqrtEAnNkzfHKZvGwMHsKFUk23bSYe/H7pvyiU6gwLB/zQXKRM
aU3uU6qaXWsFaGyQrek=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
I+E3SG6eIVl+eQQNtE5uT75GDZk2w8MwukclTFsLuB0JtjwI9/9l+wqqevSEAZVNako39sma+Yy+
6sWVRLVPo7PjKtoO7mmywH+p7yQSorsf+a3ZiNjDaYRK+f9GNaE4daxPW5KbJ1GJwaVjbrTJXjms
6KviB77YrfOEwKiKJnAPEYDYIIKzPfz0pkPKCCTKaUXpj+fFxyjC7bycPwfKU244d5RTVzX4xHcW
KE2Pbl2/gBhqu0EO5W1xcfaXIFlrwR2GLFrc0Upm7pO12jbH3NSKac9EirjKD5ICy3GjrAPQM9pC
bmcrUujXKJAoYdm46Fb/QQhF+yxNF515651OtA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13008)
`protect data_block
iXdONubG+SYUpFk1+3xjbTmoWUUth5YI3Atb1aEXZ+saXE5+BGO3fPH5sUZBPpBGvC0XNFvrYkWj
mKjKwY2xZcfJ/srndO8S7QOgA1cW3PG5z/BUIxX97bocLtxDa3aP0B0gUaWXB16YHYdYTkHrQeeT
kByzxROgmclqf0h4i+dNw17ZHgg4lSONS85uKTmrmSH+AeVrAMTnAeRVAxyAfN5NPuWFW82kE644
IywqVXyFo+6EjcTaT9MuzpUSuPIiC1uoPJBymXXqJqXLPFIf66+E0NgglyW1yofbtINgNhR1sgx9
DeAt8JD9ezW0dwIbuBVdM7WPULLxlhRiEjVxJrWWqEe7iSi5KOvb5fzvI83hsOJKOziBELmUOamM
/T8ir8zwHa8BgpammyJqhRLzlVnk0jc0ui0l2oBOLEZatZDKIkibZ103V0P30wEv3kgy6CHZSlsx
o+2FQ+rWnn+NLza2SdRplpZXZVeaSlrNxSpEgYaaVJ1hfYU4shpw1gY2+WgUCqWSpnJ07oVnlkGj
XgvkoW7LarBgf5DSufA7OrUOvhEovDc22xsKo/6q9ikE/FrAsfq/b6I1GPuHTq4tNmNgFLJLqW0b
o15QkRHGCFSFVYp01JsJfRhVklzXE3+toKZwdGB3lL7SLiSo1jny3g5F6camzx2bFmrQu5Czeo5C
/YTWlRYi0Y0z4kUwtLuCniSOj5fXjvS+rZqv0fMbSpKDz3yNPptEql6mPHK324bJZULNhyCzaxZu
6mfclZBjFvrJ40zJfG+hWRGPBj7lEQwK9mvMkOaLF3QzB85I/PtNnp79JEkmMsrgHxSoHMgJJoNG
GeQSVZp39h6ji6XfgW1Z402TkKgSqu9DZ/p/XrxV+T9xgzoHNhQQve11khlld5aZoR2Fz0dS6DWY
htxdwg3F3n0HldhSiTENVbQCnSgvpe16MCIUhBeebBdANdreKwenIpNtmV7T3c/f+GPQpaMe0uyD
CAdVU3O6rVoXt3dusGugSMUIauBbyvk9b1/gmJUdGw420PMi+IvocYBxDF0DyTxNo84nnK+qbJ94
1vTQU0XHzhNk+/bfIO9wIOTa/xR7TnIbwelmHQ2DvCac7jth9H9aFIFV77VLdx+lJOWqki9wagmw
xd6Y0RDu6Fnko3AlZAnPA8AV/fBoS/o9Mbb9XenXcb0Gxv3pWX0F5FX3/IYEv+LqJ0x1dnqXRtJd
f3XkTKRhmAv1RHZN4Ijf/26mX+vAAf+WHJboPQj6tVKWcjoiLGqDoK25y5/n695WQznpJm0jhAyt
n3ga+4uHldOnqkP3JRRSm/A4D1m6LtnYsvrEfBKMXTTJyBxZl5SwwWtzjpQQfAmwUjmxt2oRGiwx
WQNGqkz+TTiFQ5ezlAWncaJscI0KVffI14NwBnVogLcYtDZjOXRpYxrr1uPSV4WFyXUYK4w2H515
u1OVDSE7ERA09Y3+88cM1NHWW0nuzw97Ca/B2ksxC+9UGpBq92Z62ZAfYE55Aa4zCYLfmwGVRBoE
feQhSr3J5McYr/O7r8Ns83MgdkOnLTw3Yu6yAGgxoNDOPqr31lpfWEQ6EBJJ8ymfrpl6w2iI0Pou
3Yt8LzN0Xb5Dn9kcNAAqwxEZncjIHsHGjZgKYuGELLEqeJFypgffVVzo69kF06N/3OGu0IsB+NZF
oNQ9CNZnL8ZD6tsKknOLbWTeUN78pkwcJSqYtXBgkyD9UOx8BGFgrNj4k4z+thMS4m1D1R1APj1T
J88qHzUW5a/i6Y/y1jxvgWiDQZCX0O/oRG76lZxPz4TlYHjWusiXb9KDRuPVTj1KXsjEKkQnt27m
ekgt9Y85Eg+SKoLC8QlLzPn+Jcm3krZYv0Wv7jyISxNzhIMEnrX5lGwQHMrLaX5IYgiOb6LFz6IK
ITY2vvm+uKEKRxh+aN9SdKlZF1F3I/lQJIoicGjJsI0/TY/1NH23//QzdaqgGMK9f+g4fHgMnvke
VnsKr37PDikQLBnz8VK4rdoHartXGc4nB9HSQbY05Q0EXZTEG7wXnpOXD9cG0r2pKjjTEwKlW1WK
XwBxuuNvLZY7vEMV7Iv7VPRzudJFyIsVj91zKTZ0kvtHkYK9/Jhpakiy4ooYnNPj/I9D5vYH11kY
K03oqu2tM2sNKJHOzDo12gfCZxIZYp/3Mv7bMTL6UPp1Kc41QS5EkOliFb/hBIpI598iZnnxZiFo
nswi53iePFr4IhvL4XCufFkfN3Kjf1ozXowHvE9PaNfeJyKSK3TclZgUUJB7DxEcXSrXqocyxOmJ
W0rkdt8E4XvSQ9RXnGw08moTmC4Ay/Qm1Hk4VROcz2C5M/BEbD/z3r3rCD6G+I39slabSKb3EPL3
yrBJHvH+XBU/Og2/F6Y4BGtbmBqc+F5Cbezzs97Hchh3W3YUs4BFHq2a++VcEFyHwTHgMli9VaOY
w2XwIS59gPOO1G3+YudsX73xWFwLxSGEqElr5GNcKSybx/KUKP5fuA1KtcxvUurdTXSeBDqf/vsb
KDBcshsTTQzLHqcmaC8u4PSTzQ4l7S73EUXoM9h59/9naeorj1kALVcSetLAa4LyKoKpxpfrlObn
rL7OH4Hnjr6Xt3C5YcPxh2yGykFBndcoUZYxzNUeLBqBjfYju9soiqCkwcqCDBojqq/Z+t605AzQ
PlXjKhmrcz6ds7eYwO1u4KMZFAC4HXvTNL25zDJHkxcTZzcax8gptFOxcmyBZ9nafcZZ/+cu8svY
5OGfVdRDFOlq4Y2nRCAxb5++FTVg0oNkMP67MsAoGCTGfqFHS0mrScicIetb/lC+TbNO+Wx8Nuvo
jOhSu7tAZH4FwoFNudmSrlrGXOVPDeSb95Wvl1EHIVJ/Bt+g8jHN7L3EuP3iYbeXKJNzmhruepU5
/9pGEYnfaVZv1EKuQD0tsS2tShyClZNZ02zxc1YKjbJF/98+1kndtLO0JqmeBEH4rtJUuqe7mh2q
3HpCmfwguA144Kp23ARkOQKAzTh6YE6taVcJGIZlE51FSZyJS2qaXvOUgyHmpQhhl+Qxu5eRp4CR
QgzCw2U8MoWaz4w04G4jBnldDEQkY9jZIq+iS9RwoHGYNmHbhjhRvjxbtqzpMvHb/qKjvHeLin6o
DWEUotoR4Vrbzse2tpKJagIlmH0mstt5BRRPIFMWwHml2VAoln6STdwmzqHItJ6M1wiy2xuBiMOF
jUrBgmufBslF3pAgUBsF9WfKVFnAL01FY8FVdk+WqWK8dUuwLxslJ21FehhfnaDHm/mGR+l/ZIvC
5OmSQaWH27vJT9tlaf+k50s5SF5h9+2C39bKKqW3vSiy3QerLtGmSi6jOHgLfeJPXps+f10PwsjL
fu5qe3IpeezwjDGOXOD8p2CFbqt44kw+23UtDbUfSrJ6wAs7MWNTdUpltMm4hBdW6EEu4Azr8eaE
rOo76O0rP+ct2UXu2buMDccPuOXRwDdptZvw8V6N/qk6ER21uotJk6xKN7fR/Qy19SZYyc35NF92
oMxdadmKfm9fstBbj1aQUG39cPtIBhIIGxUtI112wstvH6fdPb3Gc/7kf2XsGSSawaj3yusoei/d
aYxfLFPeRcORl1oie2nUPwgrzeGcVBicSBcOTGut38nPCyDBKgPPlqUCYDAlWL6e/O/F+eo3HJ8+
Pv8/1ZmfjG24OpCOUChEp76UToTNv66MkIZ7mi/n1fRYk0B/bs7rZytYIgOZEqlLQlqcZ+uKP7pF
gp8kYzRYgBlskLTPWHXesRRfAklL7mcfyrb+kdJwBKowSRhzpbaokwK1C7zDb1obTNbfnr2IZuMC
4Jkve0+vsuZsZDLKWVrVL4gtmEcdpo9dQ9QUnMKbIjmaUtwMQgSCsRzJJwYy9GWDRS4tPB7V/uMd
WkiXyEPITTQxDOQV5famzC1g6uwZeGRNXKKl6Xf3srI8MeJDEr24ifgrZI5RhWlgne7gfOOOHcSb
cfj5uEDoV9nUeqKBPNQCGDJKzKNK3U4UWIUQDwxcby0iUIXu7mcRrPVQ+i8ZSIkNv7uQ63qD8FJ0
0PnuAovE/oecSIx6Us1avEcX7YzKkqjLUWgs2LZOJPMD6dk8MDoMo7ysX5Sl6Tl9JF14RntPqd5i
2mOS72ZPwr9U6SOt4tavm4B/XYOdmY3LdjECmA+G+O9xhvQeiUbpMmCIQGaQ+JLdC43Nu51CMH+m
bsHsVrUO8pxdQqrRm5yGNtBFQJqdg7cWayjf2D658JcIp73SPJd2nsAV1KXVI2I2++AhSCex0spz
H0+4Xjq4I6wcBpiB9ES5IPwBRuCAU+KNF7cxUJfb9AH4MtrABYZp7EUgpGF3kkDgbIMWWy5kI8iQ
gwoif6mSiXdAR43lYDI8ydMmi1P+QqvyE1uwf57rwrXcT9XTolTEyHeathKbcF9H2e/NusWFssxn
ZAsHucSrjOtuhevUZv1j+NFO/tsWJEgQUWwHFUSHl0tSZJr21Jtv04QAXDIe9uKviuEi8M1Zye2q
VIB12DuPRPB5Y5ZTt6VJEynbZczesS1k6ndss5lIqg4YxeC3iPwEQtab/YwbJyKTlDFjJ05Z3I0a
5V+JL20SaQEidsS8+tML5OVYqOF+X5YAnPAd46ujVVHrWIUqpcTvJny9iLXWMp2puwu15oYG/J87
uOBUIg52PONeRo/2ZROHRSCXUnPQQFvIxzzNph+Jqt5ZIXMTZJMFegj5FhwuthtnL7o7o/k8Lyey
YgY+A6AeZeXkPNrO3/jyNDHcx8ngg7j4n4zOIMOsYL1Eq5h2QYgfEDCRImFX+a8vMUUFhFzlUq8Q
+YnZ/g5GghVy02e84jV91RSbdXodjfxIQtHYXE6WajRfQd9Xmc3BRk+8Uk+VlXiEv+gFdtE1jMEl
Y4J6vlUOaVEh0nfexf06/T7jVeseoM1c9nznKqaRyS5cnfLG1Xc/l4idfhct0jnfD4xyo6ztKKc7
ZoWW//Ob3qeNG3mBXNZQUJMmhE2P89DViTozT+GQTzA785Y4apmPojF8ZI66ombhB0Bej2RInX0L
Wdog3njTuUmLQllhN8s0QQIfhHteB+eIH8vSm4vihPzrjwPyRL84uuW5TibDb8uA3j2aXmJ8sARQ
ijh3bM9ltfHOSh+gdfA2CwTtjpCuJPY18zeVTbwrjKjXjO5I50Svt+1f62XsFYJ7w0IzUqVuGGKi
IQIkrQLlKPh5bBbBhVsC9dBjmkkRCGBuawHh0VgUNV1IjwtHW05jlfEyrTJWjUlntujZrtGWGc9z
VRjyV83unGC9AEscKVLm7hTcgw1Uejk7JhTYsWrmnXD/2yniLpA31qEtSZdL4A+bEwKAKbWiQxsG
COwzFFI8dfZ3qGevBY8aA47DZ5uUd0z1t0IeSunBnsNh1mnMj3oOS89PX0dRhciuDE7dbg8+0tBW
9EmHn3PKRmNL1ipXvHIIfYuYc5Od3somla8JnQyl6jBAle2+RUahuA5yMVZLiJ923n8qhGYa7t/S
dKPTiknun9P6w19cPSXpI4v02Mjg5ALkLsMe+4Y4TqElQ07w7hiHGsu7EYCQzpVovud5f/db+g1b
nI9MEUV4/hYX4rVfPm8CDe4KkNvnGMro1E0JXv57X0O0escjc2QvaFP1SNc9KVhyZLJ3lYvDXd3x
YVU8eDke68BRejyCkl7EsUFiyPvyFYF6Vb4XpEWRIiW+qCj2eTK3JY3aS5ubeehk/Df3D3xYofdw
Ps9O02/Xns/UUZj/VWl3GeoM5uK1ckObVDlRwnQlSIa8X6EKAtGbeEyKDtZ/wF9Cd9+6zByRakKG
yAZ0kiS0dH8wvu9JtejXD0Yu3vjX6UgRJprZ9GYUKRN+1KYS/OlJ7wFri824lniD6LCqZb7L0BdN
l4AQ6kM4NrXLDT427YeMNGPoE6FY5QyFuqPLdFUJ1X71o6q6ATkecmV00kaGAk2x2TwwVpfHHpTj
Kab4Xhl93ic752GhbFNJw6BBquu6DFjJEenEJKGIs/Qq5lM1W9MQ+OoHd/On8K+ThjECiWzVBpbX
19ZnKrWbyfTNu+idotUkQRkHnMZfO1oe+p4eeCIPk2f4sRaxVoz4jtahxDdZzrqbgs2lXrQ+h92Z
MJ4JqtyCA2LWlrYOiTgfV6jeJnOT7p8EqA1r5gNMMf73uzJqRhTbLYdhoqY1V9brJqIelEZGwlIV
eObr7vF2SmXqVv+D2+vRjpT9sANMCBFzg5JJXtAYiHbLFJ8WXPAhwsZkuoP/a4pQreq3LHnioRRA
NlirCIpTHWBjIlScqQefBKKuvJKIAZwO+0G5Wa9FG/eQwqM92Ugne64Czm5BwKe1nXlS4MqmO1um
I0b60Gb9nWnTtKFce6YOmmSwUB/FFOT+muekdItDqFC6AtF+AvtUQ+LxE6jEogPrV975od5PONSK
1XCKPqiO75OrG0GvVL4W+lvNsSWCkx5ezq+J+I4ba63UyxL0UJ7ASgXjyUprZVizgkZujeNC59rB
YTyaZRMVtLjriqdEgpHVnA/Mp3OaA/WJJuD4XtLIIkizKKnJpII+saXW9Tzz69ET5zQhZ2lTxjF5
bAPXtnHSYBcyt7s1Junm0aBhPpsstcrQt7A4CDyX1wRNxsrG6K64S70LNtZkzN7p/toH2QOd1Ntn
vk428QrP2w/+RDHCWuPAXKJk1GKTaYFb9o2RlxWMOf782ar2knfS5VHhd59BblwWY0nW2IA61OCo
4OxPCxRPE0HUO5Iq4wg+HMth/Anm8AdPmfHbIYvwHtItB+bqDht1Hr5pQkOydqpCJvnPvYtauzq9
rTq3A3t+nYHY1Q9lwG9WfMcGaK4de8jHn9WrrkEwVnnLj21jZlnV0ZxET7ZlY98c02e1rwVnrWr+
Je5t8HKCBYOR7JCv6DaVwvNIAoqVP51AsGin6sd9h+HhA6aVypIaWjf9tyloV/NzduLhvfjhcV66
WNNxNcgfaDRoCt8Ryd99nsYqwm1v7Tq4EtN0gtX+WoGxn4zzDoF8M3R+yb9b+7YNchfY5n5bXQFn
MCE3vBHAKjWg5uk1qBr75cAu1Qca7g5K92MfGhc+jnnTTux0rvAu8+tJ6X+Edf5DHKiflbQgiG9J
7CTAsB9Q7zkjtJcl7OcPuHTk/3LAHhWdPeIm1LX4NVzF/kt1kI5Vptuu12DpHErhezSs6YWCLAr9
6A5AUIXq46nPZDI79z+GCMgY6Do/KG9RHrttH+qyncHGFhJFIJwAGmHFyM4TXAc56a/ioJI75zBa
csW6uOhgYQo1rVjjGg0JOHgoL2hiSo1cgO8FbaYeABImPoC6h+UmyWIrHPEva8RCDqBIIxYacjF3
Sablky4HqOOqTH3Po3i1W4hePeUWVfmiHqGg+rRQvXt3I5KcOa9BHeP8PLH8WbZnHhybI90AJW4B
ghGrLgpA0BouIjoGXWb28lm9b1cn52FbIvymS/YVDidtBow6phD7ORIC7RN96opz0bgfDpBsFfKk
C1g5JN/wmgOIQ0XanlsorghXFG/y5P9M6hRDR47vsyrhrmea9/a7kEhdCuFyvPL842LMx+nKI3eS
FvJtjqUdksjTtLmVF8b8u6sqwU6UFtHtD9r3ZhLPKmoXtg9KfoRBC245DQs/EvRySHvQuseOcjXx
5RkzTTZ3jjy69kCHaFf8TsIzpmT1k2o6SeItN2z/XLhHF+cOKcMNTrOPKzOndIfCrhVvXL1vUIfY
opdi/RQbj0WYsFBlZxN22CeeLsqS/sFkzosL0tk/QrsDCAW2e5lDVZfaROYbFV2DVaBtCaPsukxr
ii6dJlm6iBgbH592u+f2mI9ze3K3bpsNH3CfLCIYDDI55iw6Qwnxg8cyeNwWyMIdLanykfH7Ju8c
ZcGGHpV0gE7uf5qc3HOBJHrSdvYc359vywTxDuP9P+SJDyx+t60gzygUEutg3fdY29j2wgp2D8A/
gRAG1SnHdPc55yCIzkndYxPE3e9z/tEfzN9bpWTkjECzzAYAeBBClkKk4paB5YWIjvLEVqoh0jfA
ZVK4BErzQihjWblDamZIenulFel5DULaJy+tH7Htt7XS99+kxeShV3OxFaxZmv2wZlozcdBjCWZ+
ibrVwA2Fw4qpfd2/mR9C8rkmZHFEyhlqgOObFsCbVRVhAPifX+s1OAHQnzvqqri2oe0KqyF8nWeY
YkcYb/hkSqPmV/mUoM9CDDcgJQ+MssByY5UZxPuSg35Rlo8SrIeat1xZbZ1y4R/59kJonl4hERMX
KzK/D2HsaS6LuWMCBBAk190mDb1DELlboatAk2U+ynZWeDcMUgeu7V2MDcR+56IG1e6MK9vMw5p5
kyb4IC0NudHIppagDkhVyqyMLYHhl4fbHjw3zJQwP5DmLffEb5u1TgBzbzxhqvOlYpBCjrIXvzo5
JSFcaTA+aXCzM3WWjZeX0dSP3MZV5gcz4e6tELgJxNQhelnifyxFrqU+OJYBo8oJUKU4sCKPafmH
2Dufn9IKryoxUA59p75/NZadSANaqUvLXoqQoRVrbKBRrK9TINJPx//uJsJ6S7btepIbmQmJw7Ui
lEkn2HbtLf7cwgdXyCjgKBL9z+onHs1P8Q78w6U33GSl3kyvbK8KJhTDTcEvB3bHQCd4qeuM4ahE
gk8UNAIAZbbTnza8Y8OhN+gGthKNYe1/+TmfuVD5AB9HbsIB8bazOCqKyifB+eGZVQtn6uB7ShIW
OdpMNUZuhaxwTq469qaRr8EjNS2xE06TFRrauI9CRpMBCBZNSFyTIssidoQWA5JVHGO6eqyXwfgB
vB2BxeV7SQGitHtabgdw08LzDXd6ctJ1tKT2OCht/xesY4Od6hO3ra+xvEGINCjT8XK1s9Q4P4u7
R0GKZ7oa3h3BylbAaJq5fKMjRqLGkXFvjWMTc6rhESpWck6m0TlmfdsXflsCxYWLEibvVDaevwsT
E+uA1UOEjCr+SWq0pClD4fxV1IqCSIwD/hgVnlpu03nhBk9PDfmrDaSeHLKm/uh4y4ogBCKQtQT1
JmW0IgNIaA13zSdQN6wD6dryxMF48Cc/THO3QtA3vl5svNKVWk+mEYu2tNApzArCa+Ifl+x58cC9
9RTOIl2fc9Gy38ArM6S39s+PeEh96xUGVCbAueyKhiO75V2yVROYvgGkC6Qi/KAqaEirBS922Zru
Ye+TY6Q4phjpf/CHGsK0WpRIwokqgkhZ14OC//k+ax0V3DhAJqQ/TcPI2ooG2EpPNdNPYrcXwXRp
9ck4cTWqITnoGg4hzs6/cxrjxIE0OhNYgLKht8zL35OZrJfHJ+KEVNCyOw/JMRpAsB7J4/54DcTW
FsvTSEABYu0I5LqKvs/BLx2tmmXjJqpjTFLA3FqNOPrrfhGkaRxQtAytJKyZibGWAgx1mzNrsrIN
+C2npOErzVY4oGBuXXV9X0qmwkQ/aU7UIyKQa90gmpax3j16L7/R/v9Do0W88WlGrCKZwOiEWfce
kh2fzKBoB+AJHxikJOg6488LLmaxBrPcA4O77GNwoOgWKufHrGUc+MJpYZhzJJ1I4O0l026xoXXo
LfGceXZT/vdoovMcrGf91X099uQQsDy8jqLLziX9f+6qIZUHx47hD4ECXJXV6QyY2lQ4h+gJiOzW
hP1yGVP5PD9jRurrtxcMEuYwQsmIPutHpbt4inFagIVxVX9BbPqyLsiSsfmKkGK5Kui7tWDDHIA0
eBmaW9Xu5hOBy1+qLvCOIPX18643fQWKajUy9kWmB+s9itfVOFuKKshtG/SnRpe5Wetoztp+kuxH
OHaxb4zGcDpebbDjrU55ej4pFpJgg38H7ljkMiGkkLGAn+TwllHeojnqM2mghE1tPG8vjPHD+CMY
uj4exjB1GU1JGByWyms9F0oRdvKliwlIQ05hpPAyMEIoiHHg9hkaOoKrQ+U5vQVga9ofIcH0BZ2L
TEFBqYxtRkqi4yYYMh5zLQ+fJEGSVs0ajiLIwoH1KKmaF1eErvEW86s3d4unJxkpkb2QxBqkebLv
JJIQglskZ6GmqiO9cPpVueo8cyP0ZXXzO1gdxrpLVKx+QPyPIwzRP/x/j6EEgh/rsVZSK81enbkK
HThbYw08GTi/RjVybS7QcsMrMB9FbuzEEAyWs5XH7NlXRTzjwB+huO/s4/BtGuaYwfvD1cXk/UWd
nqYfKzMwtaat+LQjmbPXAHvLdvRbtvSLJLWZSxVURGl8Ez0ZuIyvn35lFNZqh6I1QwAjFQ8WDl7S
9ZuT3xlLkSzxUZOUfC8QdaYV+oklrWZdkKm54M9bfeNQfeRBvylbzdEuIbgkquF02UOH9XJUquuS
Sw0qNuWzAEAK4rLchd4NfuCGNl0J+TSytnoQy/XzF5H8qSc2SQuA18fc0o9Jl0A+dm/ZfdbfMPXU
XLz5bFi3TQ3Jlc25v8IJaoN744m0G+vpEdMPPYrqHz4sXSbIDKbthpOcBfqeTkf+lAq7OG2e0MUm
XWTkWs7LMG8gLWzgi/QEryCMMmbub89tfonU2WLEzS8DyNBeXNj60RV1Xc+d0YWUXJawbOTH9xSD
sg3FK1palRgTIyTAIZm92pZlZPYnu7Roff/MBsVfIbFL+lryo+IP2H6+RyijU7aNlpC5ckqeJTOa
Lah7+s9892HqcXgQ2r3auRNlgI8Sk937dlmT68UjZdWJpi/HLmrCNTVCb+vmctVvQppEusxvG0Jy
kpI1bkdgFQnYIPzTWTODGyjCnghdoRX6ZmfSmculY9PnrF5vJGCSgOpDbZIy++PoYNN/ca9pwb+h
TXSnO9khtCRrt25rryyYrr9M+bUWr6OIr3ud8EaDfMSVCzGdNDBC/iJPfnXYTvdTC7/uWz9v1woz
pGV+m8tzkZjzBHRhDO4CeGWSR3/5H4K+KIHojAT6sCVM1j1wAXZfa0bBXCAiP/TStnZ/UputQgoS
ESPZIVRO4tMkHjNqhPLr0XwO8rmlZK4ejmOWlsYJelRZ5iKeJAKOfD6aTOhrR6Gt1rmz1r5Oe+86
JZqmDk25bLMoZZXMeFrjp81q+KwjxgnVSThF6n87/Z8Br+h7sRZZcjWKBi6UhB7e/XTroPxTNudc
ypLjHedZkWxBnpyAy7HpSv+YmOi7nVDh8opsPlwmMcnyRo87+NKEbI79LVlM/l0iO6Fcfbbm28IL
nQbzcjckRBPNb6ERDo6fOPb+NfdVhDlHNy2QeNc72nI3H+pKanVLjstwurg883OZymM6m9bYDLeX
vsRwJernuWDwDXa7KqyJHa/B/eqqMJR/1CFDdfQzfPr2GRIkx8E23sCVgfEYC8UpQUMMAdpg1nAR
ykbIzOa9QJ9c1RGx/hz0fQuUduOb/a5ltvxQRTySNojTlAdncANN7ewSXNJs2Lpp9S3d4j82cMbt
1o2k9pl3ngSxgOOp0fm1HfKjaX9kRMyDbTq7WsAGxwjV/c9nCtmsWxIVGccFSpaNqMYiusvV/0es
r1/q4Fs46kQDJWoi1uyjoDOxxhok+CLmhPVDTlI0ZZr/Y6cwnMuuhks14z/R/YocI8AkGVW+HH98
VsLZNoQIFlcN/SgbPdnaB0OsGHWOsvLUjeSVTFgi7LhtyP2x4scEDCFLfnlspPF3GjbefjIiNEov
rReMj8XKZIexeb9IQeclWRSwXowB0rP1imG+jlL+D9zOv1O8cOhqhRloK62IBi/Wyv9AkmX7EBeR
Z/8wjNay/o4TW/8RsdNOT+8ok/J9vIn5ggctes7WCP/nFkP2WAM1nABVzqyPW26FTGgOCSJ979Fk
x0toxJdlkxb3v0+7lyz1sDv23dt2MlPHqAws1fLdkuovJoKkZ1dlR2NcYCZZPhXjWgvzzwJHlOsB
8gL1IRBL+zYIREP6X3E1poTEEjOq5+tVhVW+WfQBvn6K6xJfsD64LSuwqrVkS1mkzj1TvHxBgRLh
IitT/JuCh0BbwOpt8MsdRQYSA2wJfEG5LoyQsaPpqn2B+WY+1icpU894ty+gRfAAeoIMfCrYMTC1
QY2UMBEuTUb73zaWP6Q7x62Y1YNaD9XESB/ZqWcKT5vIILi9B7TVW0E85E8Hv31PLvY892k8E4LH
huoZ7k7QPkNFdr0xNSSCxH4kgJAXcKrDZ4VTmOLFbUORZFvFEOI3nIV1LRkpvMdO56DWOh4JH78y
YGL9L9QZzbHeQ6rTMNo9CVCa2A1E4zR1SamoBYYtCyzgYKWSwI14selgW7p7Psh5CPcPlQga6rx7
VW4VzokHR07Iq4NniBqqYUCd+RzWwmALqHgpl2U+DVn+4ESKLisI20E0cY5g/ZVY6kMwIQuqWbA5
m+vnwg6f/GJp9gaLfGgh2zKsfvBeHq0XmFw6IQsZst3amWm49qs4uc0dZmuBZkmKK9aGbDnJolL+
+HL1kGBLZUO0+fJin7bYrRHIFYYoZbVYSzy4yX9TgenFG6zYnHS/l16hWZqqfSRzFjgyVwVKF/9E
MwnqImGOVyQ7J+n7uU+AAdP4VR2x3Il35Dhkh6+alwEtB1s/cSs3aiHQ1RKw82qd7N1hEs9lBkW3
BxeVyN8cfAPsmg5mWb1ljOoSb7iX64/9fwuvq13w+piUMxoRXj4bYRn11EPIg3sNkwKXyMx2KJ/J
kuzsGL9ExkUGmzH1Y9CQj2N4Oyx9zjq71VmAzX00Ej6+bzJ2aklj9tv+DnxVIyeoaGvH+3XvFMRK
X/BWsc7+QJfE3eyG9N+YkeZonu+cU3qYTNL+Bw8yamX5zgP4v0k7wXJvdZzCytHB4yLj/F0rW9jJ
arbRSAbHAjCJ6BD4z4AkWvZiZR4WnQ/KOmkMoQrdHRkVRI1QJSXEc55t5uJKmu/GhhfGWPg85J1e
lJ1J3CCFS6e9fG26WV6mYdIEsdKlIKbQjD14w8Oy3KHVczWo9VvKAH12y+g0tdLD+Ag3uOOls7iv
LQy5AizOtPdU7HV1W4NNyWMET14SXbod/LE65NMlIM6jGc8ER0lIKnUfptsVKDF02RLR1yNhn/d7
fmlnhLCRMM51bqDQvlLiMocGsFJCzKw7HBLsASom6Nd/fgRF8xvbwDH7OUsncfeuJiC7AZDAdViq
rC/oB6QwI8TA6CXGAhiI8N/xzptIZ+klEWze4ENMstSH6LlbbIKf56od4VvTTkX85X/P0xDc3Fub
daDexnB067MRkmm/eupSXI9D3OLHr2rPzD9QvGe9/w9P/iiD5p7V3K5qgVcejFTdeYoPYsNJ5bwK
HoN2SRwb6s9WEHPBNlJi+Rll4Xc4vxclzF0plhYWBZVMtDEyeGRNekfz5VariivlbvA3ZpLA2Yzj
lkjD3EIraEnwqDQqT6bBMTHD5sPvIaRuokoYdEqiaL75ZEY0ZDhy4jKACuS7prqhn60SoXMKW1xe
LsJsUCgdgKkCSe3fSGkAZdo/bK7crQ+mqvsbtjgE4CNOxy2T2ZpSnJBhTcVPvhn8W1GB+EjrHIfa
RS/P+lvWENV1PWi85odvoFPP2VWxqeNQ2lLyii9zzMmYNbMhJjF087p6IDPyNq8HwAMNgs+l6JDC
tbOGYt9kMB+czH7rbWe3xWp1yavknXF41UVkrYMYKse5LVvQtHlZJdg0gtfoaR0vCSP7s/6oeFjP
6BIJ/FSAyeLSP4ObMAo1i2124f97gbP+7pMTNSLNrLv4aZD9XOmwvtdixrMAQRZscsyTgF2h11Ue
Tzih4cjJl4bqW9gJ71sWHEdHYruSGcCbrCe2KbJA+9hTSDsJtfdXAi7m3bjL+OUQ8m8Xf9Cfss3A
NWEuU8lRIeO5VCOdZKgO4R2RB45lJ7NyUL/RafKZozgN/i8t0FX+cklls4L/vu87i8A2NgY/Ok/K
3690T9KSdZxIO6OYv25l8k0HsygockP4QhDUPForiNropyUUsbYER3yeYZUf2TYlpEagET75rRI1
2PBJSao5eRsqhbhT14V8Zv4HYxv9GdxzVHZKF86QtR9bEIsQnxZ0YTsovwVzaRWMTtUTedn5PZ8U
JZbkNq3zJUCq+n+TulivCxdBkTIsorpT7+a/+2M32u3M74kvXOoDi3emCYm9IuOFHwaGQgoMdPmt
lW8iLuKKqy/MccgXLz7JfJnxYz4JwhvY2IpupqxdlsttyuXfqS07tOCP47d4edKCH9D/W49aEMRU
/SgAFUdOIYbREO421ZjOopEfuA0eR5ygDSkQf6dGw03b3TGsVvxwnhKERefF5cUeV+Sxz1KI32WH
kcYc6zgntxT8eRDjhp6d2yWx0v/ysZzNgTgMeB7mbk10kpnB0b7h637z8iX46sfMXq0JFomI76v2
l8I646CEQatWvxmakVWdrcQ/uuVvFvBl0OfhYsbgPw+tuRiGwYgzsFjSw9pMFWJoKbvHZstD+7h4
bWH63Vkm2yzLSoks+9wPdCLqKeSvHGA6C9Q5djsKn2SOlauVuRIQyqOk0YG8tIW0Eic2zMUYCCIt
6lz12rd/usiO10p7wiIvGXidb3NLI+MwWhWAYMCUG+Mgm7APMJbbHOm77fowLz5zV/Rs/6VD4uZV
nvnxRteVagtXXCkiMD5W4InZgvq12Sj8hppvYJ7oott7UM4jff2ziOSUPdiu6nhrLpBhi6dzfLec
ot4eLfgPVkW8+xV2mWAN891ji+mc8QBINhSAPLouZJ8AyAGvO83NB6GnQM56MFpjlaYJS+4TFJ93
NTLyvmPInQyoZOajtGRhGlsgdnvEdXSPAUQ2BZTgameaBRs9LsPEh1Y43+J1uyRI6fXErGCJPg6U
9efqVgRobI3Fhgu1eItNuLOseysDprIlxIz79z8ySo+1XLmsZgKp0QFaX1Fhq0wP4t481WIgy/kj
/Z+FAPOZLJbUG8sEo0Vih91S2sql0GY4yORoVZ5zx3JHiffCeCr1tLhT4sQRlwbzY/y1xSUU/ZDN
XzUoPCRrTHxApvYqOFPT+qFZ+vi/UaAftQNDVQSBzxFA/LxopC5pJEVi2mrYlZ3oueUTx3EHOp82
b2LiDk6UPnxZH0zdPQBtr13TPjTgJfFL+FVLUvzqeOJDwko5RYaLmcGYxeVa2Gzsh3rNW1KMwvfE
c6IVV/+g5jTz/iHKpFcOWclEqqn40rAzHXQ1QNuzXzKAOicqI+KX32Irf2QVTl8178biX3+3kusr
eFOsv6836hr3DjTNf7qAkGrCk8lChd3V9iYcEOQZ7KRDykBXfpGU7Qk+8tzpU+r1cj8AQ4+w0CqA
lDlfONdv6Nk/fq/RAHmVhX0pd9fckbonJAg72zazCvO4Xn3kAZdp+2Nmc5UwjN+U3egb74FuPKGM
NdTRLPvjQwMoP9mg2dNVH5iC0QWcY3Dj2sYCg/ALXxG7HV03UFvKZ/AZKssA47IofJ+Pn2oO0oJ8
w4ylFe98xloVwyv9NESeeVPGuYr+KirBJ1ty3GkCRF2HW8tBsSz60/QeBMe4ifhzlJIMcG8FKV/z
BqXUDYpO/W5hogGEpE6s2Ti3NfXxki+jXlRWo6YVfhKkLHMH7SqCFx+c7XnrYfx9YP/DSwPcT83h
+k7Ciey0cMYNVyFtdbOG1LzIJM+5/rCq6X4w8nlT/2ExfY6kYObFismDI2oTpszqR7NiPCpD45P0
z5qRNXEDcdzbECsgK06+0jf0B4a6V5Yt2YlUklRR0IsD/51ucVvAX+yUG9X3PcyOsm05iBRlIQaY
jvd7EOa/cieRbu5dBACs/2C8EQfbzPznfYNV1mvXkXzSXC9q7KXPzzHOsug0GCgxikCMHeTXHDmX
lL24pW6pViuELSQW14IeZZxhh+28/ciZ8iJukv1vsh40gw0E4hMC/XtFUx2kW+gPrwrsT4brWrW5
imvcjRWjPCOdNe61DT8u+PvRBAdA3kGSjbHEHF/tgOfmW5EFLavF0osXZkwRbVsnEmpR1Si+ISbv
Zozo4j5GHr0uC7CyOrugIVncIAJa3AJY/vX08GlV6CxqJ6j5HbQLEpRF8XR2qKA2xhZwQMo9N0mi
2hKzfoahmkD0OjSTbJxfo7jJuODAYAbfFFb/G+5ieTbpdbqPQG/iDpl4XdBuq+J74suA0IQCxoV6
UNNdNPlwdxC0jxh/0mFkfX4poLdzkjipGkvLLWcoBhAuWUSH6ocifFwdnbwkdljh5BNvq6gHYQmO
K8nfdbpy4Eonr3+G28XxsESbTV9iSSuaWQq1imTZzbO+mqmRzOJ4GPUsgXttlFI1eQiFaKRCJvCF
T5BE5DEyHarpSPLseU4oTx1A7lmQT0WLQ9SCDRfGO19O4zSfERrpSJrO0U/4OA7EUmm47WI7aB6o
yjS4BhSJSyu0YJQKBr5dHOOJ77XAFA9bYOUROkWOtnQJ1bKYoPvTtFXkRKWzb4S8DZWysF/N375s
gsAWoSsWKLzIJ1qSBoo95UJi0moAplGlxIyw3il8rHPqc6GdqMGlTc4ZzhVFiQfep5BR0KN2l25v
L83ot/fSeYjClbRaEiVGD9YcKXTq+PYuAzHNNhv9SywOmGwHsEmMASLCYdb7uuYHqqJkYVpbyirq
YuYyBDQfOni3tDG9iRFiHImfYnygq/VjpSUSBaqH3QxZAnkzHkHf4OJmn+IsR1fqL+KwNu3f0gv0
19OlDizWlWlJ3e6fsHAvY3nPBGtNaXHX7oPtxyn8ifZMWSHnIYD/WyDPBLo82U38Z+rf8q0raLPn
gha0mKz5AGniZcghzxRzl4cs9Qh8BhtD4qPmeWujP8l9/i94T9r57T/xugHTa+xnoD4N/+sJjBB0
C2u1OIZTbKsp1UEsZtfcNrNZQuZKmI7zaSfkL2/Kytds6DAO4Jgxz7uP1AxpcDwOduZrqiCXu/ai
DnVCs6FQkKNo81nmYR5/jkX3Lq/onKY4EZguAqpAGLZnyGCkUIgmu1cAE722m7L1Vn0TZLPPVMCI
N3VmF3BW2mdpG89PK4XoX/dmQIsqQN6h7NF1VNAk8DaDr/AvzmN5xxiH1YXwbd48aP/n9QW3Exxu
ohad+9GfvHaHaNarQw+JdZQOvo/h5Py/O2sZ6ljUQKyyene+AlhFSuy82HHny8mG2Bs6gKBC0Rjh
3hdGnsrdCJOetyIxCfS5W22xEm3c71sw9ayszKSa69E+Fc9PTbyWvGw3ATi0H76drtI90UGZ/lMO
fpI14KeZxrDGAhOu9uGsz17i1mkNPhEZs6ul7EZVvqWOZsMM7kagdHCyeTwye5IMZVnmTq3Q8Xwe
4W9lMEwrY043Ne/PRNKes1kU/+ZIX9DrFtWqirH9dFEeBnuy4072kf6RmVr6SO/bo2HUso3ZQNHp
WnY6TTvUrJnoDK8ryAy8UcyOxHvfab0dN2bSkzyWHJ1xeY+kDyWgoCnNNJzH9t1o4dmN6AhC337g
jVIu8YNIa45p3DwLYeN1Fv+FSzw/hzYpZMcM3URadSuYVQkAKkomh8LZxX0D78pcjJlgndp6hehi
bDjKlV21uTrJiR5N
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
Jg7ZSB2xI/J/jQikm8Zlko862zAjpKBGuPSRLj2TaHEWC5rTzr3rFiYHZX6yv0DYk/Y584dxn1Aj
ZJ3fEMF2Eg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
J8XF87MjtG6MD92nYNEuYX3aIPS/zAQYepXrxQuouCoZ7DifIM+PcGRYhyHbT1c+x8wNqIyddvPX
H9E20LneyNoZup9aJc0KklSHkCBi4RFSlJYfEHGi7VuQ4DoNHay9ZZOx7KnkG5nTkuG8dZKhL494
1mvb9OIoIew9S5frQi8=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
FESqZcf5Kd2nw6uez2DBxPYJSBV8lpPPNkL9mii7n9rOA23QnwFT4gzsX2GnAKh0RRoHvqDgwQe2
oriJIgtSnO9GoEYt557lwN4pjAIARzzVKmQozG4a0ZADHcAuh9dE9U2pgm4IYqaA0WHemsJP3RdH
ZWLIA5hjsrEEni35ostJyYxky5xMLNN1/n6HMS0umCbRhs8srgz/a5uvWD7FFpEZ2a0utgDi9MEX
Ot7P9GN3AM5Ug4guXH512IazlVntMqLUCdCGexOO2NqFhGpAvwGxJCtx5XjHjmGW+9m1bqRxt0uC
W0qg1W0dWBjrERQ1cn2SGOV3FZ9QqHCbH1eBSw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
sBWw2a997MC11UDckC6eUhzOMD6OyRi9hIrFSmKM1LtA+EoEe9hBOU+xWnNJxZwh5q/2lTaLVnRD
SOXNd1eh6E6oJtNfyy/eD/u9oSEqrtEAnNkzfHKZvGwMHsKFUk23bSYe/H7pvyiU6gwLB/zQXKRM
aU3uU6qaXWsFaGyQrek=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
I+E3SG6eIVl+eQQNtE5uT75GDZk2w8MwukclTFsLuB0JtjwI9/9l+wqqevSEAZVNako39sma+Yy+
6sWVRLVPo7PjKtoO7mmywH+p7yQSorsf+a3ZiNjDaYRK+f9GNaE4daxPW5KbJ1GJwaVjbrTJXjms
6KviB77YrfOEwKiKJnAPEYDYIIKzPfz0pkPKCCTKaUXpj+fFxyjC7bycPwfKU244d5RTVzX4xHcW
KE2Pbl2/gBhqu0EO5W1xcfaXIFlrwR2GLFrc0Upm7pO12jbH3NSKac9EirjKD5ICy3GjrAPQM9pC
bmcrUujXKJAoYdm46Fb/QQhF+yxNF515651OtA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13008)
`protect data_block
iXdONubG+SYUpFk1+3xjbTmoWUUth5YI3Atb1aEXZ+saXE5+BGO3fPH5sUZBPpBGvC0XNFvrYkWj
mKjKwY2xZcfJ/srndO8S7QOgA1cW3PG5z/BUIxX97bocLtxDa3aP0B0gUaWXB16YHYdYTkHrQeeT
kByzxROgmclqf0h4i+dNw17ZHgg4lSONS85uKTmrmSH+AeVrAMTnAeRVAxyAfN5NPuWFW82kE644
IywqVXyFo+6EjcTaT9MuzpUSuPIiC1uoPJBymXXqJqXLPFIf66+E0NgglyW1yofbtINgNhR1sgx9
DeAt8JD9ezW0dwIbuBVdM7WPULLxlhRiEjVxJrWWqEe7iSi5KOvb5fzvI83hsOJKOziBELmUOamM
/T8ir8zwHa8BgpammyJqhRLzlVnk0jc0ui0l2oBOLEZatZDKIkibZ103V0P30wEv3kgy6CHZSlsx
o+2FQ+rWnn+NLza2SdRplpZXZVeaSlrNxSpEgYaaVJ1hfYU4shpw1gY2+WgUCqWSpnJ07oVnlkGj
XgvkoW7LarBgf5DSufA7OrUOvhEovDc22xsKo/6q9ikE/FrAsfq/b6I1GPuHTq4tNmNgFLJLqW0b
o15QkRHGCFSFVYp01JsJfRhVklzXE3+toKZwdGB3lL7SLiSo1jny3g5F6camzx2bFmrQu5Czeo5C
/YTWlRYi0Y0z4kUwtLuCniSOj5fXjvS+rZqv0fMbSpKDz3yNPptEql6mPHK324bJZULNhyCzaxZu
6mfclZBjFvrJ40zJfG+hWRGPBj7lEQwK9mvMkOaLF3QzB85I/PtNnp79JEkmMsrgHxSoHMgJJoNG
GeQSVZp39h6ji6XfgW1Z402TkKgSqu9DZ/p/XrxV+T9xgzoHNhQQve11khlld5aZoR2Fz0dS6DWY
htxdwg3F3n0HldhSiTENVbQCnSgvpe16MCIUhBeebBdANdreKwenIpNtmV7T3c/f+GPQpaMe0uyD
CAdVU3O6rVoXt3dusGugSMUIauBbyvk9b1/gmJUdGw420PMi+IvocYBxDF0DyTxNo84nnK+qbJ94
1vTQU0XHzhNk+/bfIO9wIOTa/xR7TnIbwelmHQ2DvCac7jth9H9aFIFV77VLdx+lJOWqki9wagmw
xd6Y0RDu6Fnko3AlZAnPA8AV/fBoS/o9Mbb9XenXcb0Gxv3pWX0F5FX3/IYEv+LqJ0x1dnqXRtJd
f3XkTKRhmAv1RHZN4Ijf/26mX+vAAf+WHJboPQj6tVKWcjoiLGqDoK25y5/n695WQznpJm0jhAyt
n3ga+4uHldOnqkP3JRRSm/A4D1m6LtnYsvrEfBKMXTTJyBxZl5SwwWtzjpQQfAmwUjmxt2oRGiwx
WQNGqkz+TTiFQ5ezlAWncaJscI0KVffI14NwBnVogLcYtDZjOXRpYxrr1uPSV4WFyXUYK4w2H515
u1OVDSE7ERA09Y3+88cM1NHWW0nuzw97Ca/B2ksxC+9UGpBq92Z62ZAfYE55Aa4zCYLfmwGVRBoE
feQhSr3J5McYr/O7r8Ns83MgdkOnLTw3Yu6yAGgxoNDOPqr31lpfWEQ6EBJJ8ymfrpl6w2iI0Pou
3Yt8LzN0Xb5Dn9kcNAAqwxEZncjIHsHGjZgKYuGELLEqeJFypgffVVzo69kF06N/3OGu0IsB+NZF
oNQ9CNZnL8ZD6tsKknOLbWTeUN78pkwcJSqYtXBgkyD9UOx8BGFgrNj4k4z+thMS4m1D1R1APj1T
J88qHzUW5a/i6Y/y1jxvgWiDQZCX0O/oRG76lZxPz4TlYHjWusiXb9KDRuPVTj1KXsjEKkQnt27m
ekgt9Y85Eg+SKoLC8QlLzPn+Jcm3krZYv0Wv7jyISxNzhIMEnrX5lGwQHMrLaX5IYgiOb6LFz6IK
ITY2vvm+uKEKRxh+aN9SdKlZF1F3I/lQJIoicGjJsI0/TY/1NH23//QzdaqgGMK9f+g4fHgMnvke
VnsKr37PDikQLBnz8VK4rdoHartXGc4nB9HSQbY05Q0EXZTEG7wXnpOXD9cG0r2pKjjTEwKlW1WK
XwBxuuNvLZY7vEMV7Iv7VPRzudJFyIsVj91zKTZ0kvtHkYK9/Jhpakiy4ooYnNPj/I9D5vYH11kY
K03oqu2tM2sNKJHOzDo12gfCZxIZYp/3Mv7bMTL6UPp1Kc41QS5EkOliFb/hBIpI598iZnnxZiFo
nswi53iePFr4IhvL4XCufFkfN3Kjf1ozXowHvE9PaNfeJyKSK3TclZgUUJB7DxEcXSrXqocyxOmJ
W0rkdt8E4XvSQ9RXnGw08moTmC4Ay/Qm1Hk4VROcz2C5M/BEbD/z3r3rCD6G+I39slabSKb3EPL3
yrBJHvH+XBU/Og2/F6Y4BGtbmBqc+F5Cbezzs97Hchh3W3YUs4BFHq2a++VcEFyHwTHgMli9VaOY
w2XwIS59gPOO1G3+YudsX73xWFwLxSGEqElr5GNcKSybx/KUKP5fuA1KtcxvUurdTXSeBDqf/vsb
KDBcshsTTQzLHqcmaC8u4PSTzQ4l7S73EUXoM9h59/9naeorj1kALVcSetLAa4LyKoKpxpfrlObn
rL7OH4Hnjr6Xt3C5YcPxh2yGykFBndcoUZYxzNUeLBqBjfYju9soiqCkwcqCDBojqq/Z+t605AzQ
PlXjKhmrcz6ds7eYwO1u4KMZFAC4HXvTNL25zDJHkxcTZzcax8gptFOxcmyBZ9nafcZZ/+cu8svY
5OGfVdRDFOlq4Y2nRCAxb5++FTVg0oNkMP67MsAoGCTGfqFHS0mrScicIetb/lC+TbNO+Wx8Nuvo
jOhSu7tAZH4FwoFNudmSrlrGXOVPDeSb95Wvl1EHIVJ/Bt+g8jHN7L3EuP3iYbeXKJNzmhruepU5
/9pGEYnfaVZv1EKuQD0tsS2tShyClZNZ02zxc1YKjbJF/98+1kndtLO0JqmeBEH4rtJUuqe7mh2q
3HpCmfwguA144Kp23ARkOQKAzTh6YE6taVcJGIZlE51FSZyJS2qaXvOUgyHmpQhhl+Qxu5eRp4CR
QgzCw2U8MoWaz4w04G4jBnldDEQkY9jZIq+iS9RwoHGYNmHbhjhRvjxbtqzpMvHb/qKjvHeLin6o
DWEUotoR4Vrbzse2tpKJagIlmH0mstt5BRRPIFMWwHml2VAoln6STdwmzqHItJ6M1wiy2xuBiMOF
jUrBgmufBslF3pAgUBsF9WfKVFnAL01FY8FVdk+WqWK8dUuwLxslJ21FehhfnaDHm/mGR+l/ZIvC
5OmSQaWH27vJT9tlaf+k50s5SF5h9+2C39bKKqW3vSiy3QerLtGmSi6jOHgLfeJPXps+f10PwsjL
fu5qe3IpeezwjDGOXOD8p2CFbqt44kw+23UtDbUfSrJ6wAs7MWNTdUpltMm4hBdW6EEu4Azr8eaE
rOo76O0rP+ct2UXu2buMDccPuOXRwDdptZvw8V6N/qk6ER21uotJk6xKN7fR/Qy19SZYyc35NF92
oMxdadmKfm9fstBbj1aQUG39cPtIBhIIGxUtI112wstvH6fdPb3Gc/7kf2XsGSSawaj3yusoei/d
aYxfLFPeRcORl1oie2nUPwgrzeGcVBicSBcOTGut38nPCyDBKgPPlqUCYDAlWL6e/O/F+eo3HJ8+
Pv8/1ZmfjG24OpCOUChEp76UToTNv66MkIZ7mi/n1fRYk0B/bs7rZytYIgOZEqlLQlqcZ+uKP7pF
gp8kYzRYgBlskLTPWHXesRRfAklL7mcfyrb+kdJwBKowSRhzpbaokwK1C7zDb1obTNbfnr2IZuMC
4Jkve0+vsuZsZDLKWVrVL4gtmEcdpo9dQ9QUnMKbIjmaUtwMQgSCsRzJJwYy9GWDRS4tPB7V/uMd
WkiXyEPITTQxDOQV5famzC1g6uwZeGRNXKKl6Xf3srI8MeJDEr24ifgrZI5RhWlgne7gfOOOHcSb
cfj5uEDoV9nUeqKBPNQCGDJKzKNK3U4UWIUQDwxcby0iUIXu7mcRrPVQ+i8ZSIkNv7uQ63qD8FJ0
0PnuAovE/oecSIx6Us1avEcX7YzKkqjLUWgs2LZOJPMD6dk8MDoMo7ysX5Sl6Tl9JF14RntPqd5i
2mOS72ZPwr9U6SOt4tavm4B/XYOdmY3LdjECmA+G+O9xhvQeiUbpMmCIQGaQ+JLdC43Nu51CMH+m
bsHsVrUO8pxdQqrRm5yGNtBFQJqdg7cWayjf2D658JcIp73SPJd2nsAV1KXVI2I2++AhSCex0spz
H0+4Xjq4I6wcBpiB9ES5IPwBRuCAU+KNF7cxUJfb9AH4MtrABYZp7EUgpGF3kkDgbIMWWy5kI8iQ
gwoif6mSiXdAR43lYDI8ydMmi1P+QqvyE1uwf57rwrXcT9XTolTEyHeathKbcF9H2e/NusWFssxn
ZAsHucSrjOtuhevUZv1j+NFO/tsWJEgQUWwHFUSHl0tSZJr21Jtv04QAXDIe9uKviuEi8M1Zye2q
VIB12DuPRPB5Y5ZTt6VJEynbZczesS1k6ndss5lIqg4YxeC3iPwEQtab/YwbJyKTlDFjJ05Z3I0a
5V+JL20SaQEidsS8+tML5OVYqOF+X5YAnPAd46ujVVHrWIUqpcTvJny9iLXWMp2puwu15oYG/J87
uOBUIg52PONeRo/2ZROHRSCXUnPQQFvIxzzNph+Jqt5ZIXMTZJMFegj5FhwuthtnL7o7o/k8Lyey
YgY+A6AeZeXkPNrO3/jyNDHcx8ngg7j4n4zOIMOsYL1Eq5h2QYgfEDCRImFX+a8vMUUFhFzlUq8Q
+YnZ/g5GghVy02e84jV91RSbdXodjfxIQtHYXE6WajRfQd9Xmc3BRk+8Uk+VlXiEv+gFdtE1jMEl
Y4J6vlUOaVEh0nfexf06/T7jVeseoM1c9nznKqaRyS5cnfLG1Xc/l4idfhct0jnfD4xyo6ztKKc7
ZoWW//Ob3qeNG3mBXNZQUJMmhE2P89DViTozT+GQTzA785Y4apmPojF8ZI66ombhB0Bej2RInX0L
Wdog3njTuUmLQllhN8s0QQIfhHteB+eIH8vSm4vihPzrjwPyRL84uuW5TibDb8uA3j2aXmJ8sARQ
ijh3bM9ltfHOSh+gdfA2CwTtjpCuJPY18zeVTbwrjKjXjO5I50Svt+1f62XsFYJ7w0IzUqVuGGKi
IQIkrQLlKPh5bBbBhVsC9dBjmkkRCGBuawHh0VgUNV1IjwtHW05jlfEyrTJWjUlntujZrtGWGc9z
VRjyV83unGC9AEscKVLm7hTcgw1Uejk7JhTYsWrmnXD/2yniLpA31qEtSZdL4A+bEwKAKbWiQxsG
COwzFFI8dfZ3qGevBY8aA47DZ5uUd0z1t0IeSunBnsNh1mnMj3oOS89PX0dRhciuDE7dbg8+0tBW
9EmHn3PKRmNL1ipXvHIIfYuYc5Od3somla8JnQyl6jBAle2+RUahuA5yMVZLiJ923n8qhGYa7t/S
dKPTiknun9P6w19cPSXpI4v02Mjg5ALkLsMe+4Y4TqElQ07w7hiHGsu7EYCQzpVovud5f/db+g1b
nI9MEUV4/hYX4rVfPm8CDe4KkNvnGMro1E0JXv57X0O0escjc2QvaFP1SNc9KVhyZLJ3lYvDXd3x
YVU8eDke68BRejyCkl7EsUFiyPvyFYF6Vb4XpEWRIiW+qCj2eTK3JY3aS5ubeehk/Df3D3xYofdw
Ps9O02/Xns/UUZj/VWl3GeoM5uK1ckObVDlRwnQlSIa8X6EKAtGbeEyKDtZ/wF9Cd9+6zByRakKG
yAZ0kiS0dH8wvu9JtejXD0Yu3vjX6UgRJprZ9GYUKRN+1KYS/OlJ7wFri824lniD6LCqZb7L0BdN
l4AQ6kM4NrXLDT427YeMNGPoE6FY5QyFuqPLdFUJ1X71o6q6ATkecmV00kaGAk2x2TwwVpfHHpTj
Kab4Xhl93ic752GhbFNJw6BBquu6DFjJEenEJKGIs/Qq5lM1W9MQ+OoHd/On8K+ThjECiWzVBpbX
19ZnKrWbyfTNu+idotUkQRkHnMZfO1oe+p4eeCIPk2f4sRaxVoz4jtahxDdZzrqbgs2lXrQ+h92Z
MJ4JqtyCA2LWlrYOiTgfV6jeJnOT7p8EqA1r5gNMMf73uzJqRhTbLYdhoqY1V9brJqIelEZGwlIV
eObr7vF2SmXqVv+D2+vRjpT9sANMCBFzg5JJXtAYiHbLFJ8WXPAhwsZkuoP/a4pQreq3LHnioRRA
NlirCIpTHWBjIlScqQefBKKuvJKIAZwO+0G5Wa9FG/eQwqM92Ugne64Czm5BwKe1nXlS4MqmO1um
I0b60Gb9nWnTtKFce6YOmmSwUB/FFOT+muekdItDqFC6AtF+AvtUQ+LxE6jEogPrV975od5PONSK
1XCKPqiO75OrG0GvVL4W+lvNsSWCkx5ezq+J+I4ba63UyxL0UJ7ASgXjyUprZVizgkZujeNC59rB
YTyaZRMVtLjriqdEgpHVnA/Mp3OaA/WJJuD4XtLIIkizKKnJpII+saXW9Tzz69ET5zQhZ2lTxjF5
bAPXtnHSYBcyt7s1Junm0aBhPpsstcrQt7A4CDyX1wRNxsrG6K64S70LNtZkzN7p/toH2QOd1Ntn
vk428QrP2w/+RDHCWuPAXKJk1GKTaYFb9o2RlxWMOf782ar2knfS5VHhd59BblwWY0nW2IA61OCo
4OxPCxRPE0HUO5Iq4wg+HMth/Anm8AdPmfHbIYvwHtItB+bqDht1Hr5pQkOydqpCJvnPvYtauzq9
rTq3A3t+nYHY1Q9lwG9WfMcGaK4de8jHn9WrrkEwVnnLj21jZlnV0ZxET7ZlY98c02e1rwVnrWr+
Je5t8HKCBYOR7JCv6DaVwvNIAoqVP51AsGin6sd9h+HhA6aVypIaWjf9tyloV/NzduLhvfjhcV66
WNNxNcgfaDRoCt8Ryd99nsYqwm1v7Tq4EtN0gtX+WoGxn4zzDoF8M3R+yb9b+7YNchfY5n5bXQFn
MCE3vBHAKjWg5uk1qBr75cAu1Qca7g5K92MfGhc+jnnTTux0rvAu8+tJ6X+Edf5DHKiflbQgiG9J
7CTAsB9Q7zkjtJcl7OcPuHTk/3LAHhWdPeIm1LX4NVzF/kt1kI5Vptuu12DpHErhezSs6YWCLAr9
6A5AUIXq46nPZDI79z+GCMgY6Do/KG9RHrttH+qyncHGFhJFIJwAGmHFyM4TXAc56a/ioJI75zBa
csW6uOhgYQo1rVjjGg0JOHgoL2hiSo1cgO8FbaYeABImPoC6h+UmyWIrHPEva8RCDqBIIxYacjF3
Sablky4HqOOqTH3Po3i1W4hePeUWVfmiHqGg+rRQvXt3I5KcOa9BHeP8PLH8WbZnHhybI90AJW4B
ghGrLgpA0BouIjoGXWb28lm9b1cn52FbIvymS/YVDidtBow6phD7ORIC7RN96opz0bgfDpBsFfKk
C1g5JN/wmgOIQ0XanlsorghXFG/y5P9M6hRDR47vsyrhrmea9/a7kEhdCuFyvPL842LMx+nKI3eS
FvJtjqUdksjTtLmVF8b8u6sqwU6UFtHtD9r3ZhLPKmoXtg9KfoRBC245DQs/EvRySHvQuseOcjXx
5RkzTTZ3jjy69kCHaFf8TsIzpmT1k2o6SeItN2z/XLhHF+cOKcMNTrOPKzOndIfCrhVvXL1vUIfY
opdi/RQbj0WYsFBlZxN22CeeLsqS/sFkzosL0tk/QrsDCAW2e5lDVZfaROYbFV2DVaBtCaPsukxr
ii6dJlm6iBgbH592u+f2mI9ze3K3bpsNH3CfLCIYDDI55iw6Qwnxg8cyeNwWyMIdLanykfH7Ju8c
ZcGGHpV0gE7uf5qc3HOBJHrSdvYc359vywTxDuP9P+SJDyx+t60gzygUEutg3fdY29j2wgp2D8A/
gRAG1SnHdPc55yCIzkndYxPE3e9z/tEfzN9bpWTkjECzzAYAeBBClkKk4paB5YWIjvLEVqoh0jfA
ZVK4BErzQihjWblDamZIenulFel5DULaJy+tH7Htt7XS99+kxeShV3OxFaxZmv2wZlozcdBjCWZ+
ibrVwA2Fw4qpfd2/mR9C8rkmZHFEyhlqgOObFsCbVRVhAPifX+s1OAHQnzvqqri2oe0KqyF8nWeY
YkcYb/hkSqPmV/mUoM9CDDcgJQ+MssByY5UZxPuSg35Rlo8SrIeat1xZbZ1y4R/59kJonl4hERMX
KzK/D2HsaS6LuWMCBBAk190mDb1DELlboatAk2U+ynZWeDcMUgeu7V2MDcR+56IG1e6MK9vMw5p5
kyb4IC0NudHIppagDkhVyqyMLYHhl4fbHjw3zJQwP5DmLffEb5u1TgBzbzxhqvOlYpBCjrIXvzo5
JSFcaTA+aXCzM3WWjZeX0dSP3MZV5gcz4e6tELgJxNQhelnifyxFrqU+OJYBo8oJUKU4sCKPafmH
2Dufn9IKryoxUA59p75/NZadSANaqUvLXoqQoRVrbKBRrK9TINJPx//uJsJ6S7btepIbmQmJw7Ui
lEkn2HbtLf7cwgdXyCjgKBL9z+onHs1P8Q78w6U33GSl3kyvbK8KJhTDTcEvB3bHQCd4qeuM4ahE
gk8UNAIAZbbTnza8Y8OhN+gGthKNYe1/+TmfuVD5AB9HbsIB8bazOCqKyifB+eGZVQtn6uB7ShIW
OdpMNUZuhaxwTq469qaRr8EjNS2xE06TFRrauI9CRpMBCBZNSFyTIssidoQWA5JVHGO6eqyXwfgB
vB2BxeV7SQGitHtabgdw08LzDXd6ctJ1tKT2OCht/xesY4Od6hO3ra+xvEGINCjT8XK1s9Q4P4u7
R0GKZ7oa3h3BylbAaJq5fKMjRqLGkXFvjWMTc6rhESpWck6m0TlmfdsXflsCxYWLEibvVDaevwsT
E+uA1UOEjCr+SWq0pClD4fxV1IqCSIwD/hgVnlpu03nhBk9PDfmrDaSeHLKm/uh4y4ogBCKQtQT1
JmW0IgNIaA13zSdQN6wD6dryxMF48Cc/THO3QtA3vl5svNKVWk+mEYu2tNApzArCa+Ifl+x58cC9
9RTOIl2fc9Gy38ArM6S39s+PeEh96xUGVCbAueyKhiO75V2yVROYvgGkC6Qi/KAqaEirBS922Zru
Ye+TY6Q4phjpf/CHGsK0WpRIwokqgkhZ14OC//k+ax0V3DhAJqQ/TcPI2ooG2EpPNdNPYrcXwXRp
9ck4cTWqITnoGg4hzs6/cxrjxIE0OhNYgLKht8zL35OZrJfHJ+KEVNCyOw/JMRpAsB7J4/54DcTW
FsvTSEABYu0I5LqKvs/BLx2tmmXjJqpjTFLA3FqNOPrrfhGkaRxQtAytJKyZibGWAgx1mzNrsrIN
+C2npOErzVY4oGBuXXV9X0qmwkQ/aU7UIyKQa90gmpax3j16L7/R/v9Do0W88WlGrCKZwOiEWfce
kh2fzKBoB+AJHxikJOg6488LLmaxBrPcA4O77GNwoOgWKufHrGUc+MJpYZhzJJ1I4O0l026xoXXo
LfGceXZT/vdoovMcrGf91X099uQQsDy8jqLLziX9f+6qIZUHx47hD4ECXJXV6QyY2lQ4h+gJiOzW
hP1yGVP5PD9jRurrtxcMEuYwQsmIPutHpbt4inFagIVxVX9BbPqyLsiSsfmKkGK5Kui7tWDDHIA0
eBmaW9Xu5hOBy1+qLvCOIPX18643fQWKajUy9kWmB+s9itfVOFuKKshtG/SnRpe5Wetoztp+kuxH
OHaxb4zGcDpebbDjrU55ej4pFpJgg38H7ljkMiGkkLGAn+TwllHeojnqM2mghE1tPG8vjPHD+CMY
uj4exjB1GU1JGByWyms9F0oRdvKliwlIQ05hpPAyMEIoiHHg9hkaOoKrQ+U5vQVga9ofIcH0BZ2L
TEFBqYxtRkqi4yYYMh5zLQ+fJEGSVs0ajiLIwoH1KKmaF1eErvEW86s3d4unJxkpkb2QxBqkebLv
JJIQglskZ6GmqiO9cPpVueo8cyP0ZXXzO1gdxrpLVKx+QPyPIwzRP/x/j6EEgh/rsVZSK81enbkK
HThbYw08GTi/RjVybS7QcsMrMB9FbuzEEAyWs5XH7NlXRTzjwB+huO/s4/BtGuaYwfvD1cXk/UWd
nqYfKzMwtaat+LQjmbPXAHvLdvRbtvSLJLWZSxVURGl8Ez0ZuIyvn35lFNZqh6I1QwAjFQ8WDl7S
9ZuT3xlLkSzxUZOUfC8QdaYV+oklrWZdkKm54M9bfeNQfeRBvylbzdEuIbgkquF02UOH9XJUquuS
Sw0qNuWzAEAK4rLchd4NfuCGNl0J+TSytnoQy/XzF5H8qSc2SQuA18fc0o9Jl0A+dm/ZfdbfMPXU
XLz5bFi3TQ3Jlc25v8IJaoN744m0G+vpEdMPPYrqHz4sXSbIDKbthpOcBfqeTkf+lAq7OG2e0MUm
XWTkWs7LMG8gLWzgi/QEryCMMmbub89tfonU2WLEzS8DyNBeXNj60RV1Xc+d0YWUXJawbOTH9xSD
sg3FK1palRgTIyTAIZm92pZlZPYnu7Roff/MBsVfIbFL+lryo+IP2H6+RyijU7aNlpC5ckqeJTOa
Lah7+s9892HqcXgQ2r3auRNlgI8Sk937dlmT68UjZdWJpi/HLmrCNTVCb+vmctVvQppEusxvG0Jy
kpI1bkdgFQnYIPzTWTODGyjCnghdoRX6ZmfSmculY9PnrF5vJGCSgOpDbZIy++PoYNN/ca9pwb+h
TXSnO9khtCRrt25rryyYrr9M+bUWr6OIr3ud8EaDfMSVCzGdNDBC/iJPfnXYTvdTC7/uWz9v1woz
pGV+m8tzkZjzBHRhDO4CeGWSR3/5H4K+KIHojAT6sCVM1j1wAXZfa0bBXCAiP/TStnZ/UputQgoS
ESPZIVRO4tMkHjNqhPLr0XwO8rmlZK4ejmOWlsYJelRZ5iKeJAKOfD6aTOhrR6Gt1rmz1r5Oe+86
JZqmDk25bLMoZZXMeFrjp81q+KwjxgnVSThF6n87/Z8Br+h7sRZZcjWKBi6UhB7e/XTroPxTNudc
ypLjHedZkWxBnpyAy7HpSv+YmOi7nVDh8opsPlwmMcnyRo87+NKEbI79LVlM/l0iO6Fcfbbm28IL
nQbzcjckRBPNb6ERDo6fOPb+NfdVhDlHNy2QeNc72nI3H+pKanVLjstwurg883OZymM6m9bYDLeX
vsRwJernuWDwDXa7KqyJHa/B/eqqMJR/1CFDdfQzfPr2GRIkx8E23sCVgfEYC8UpQUMMAdpg1nAR
ykbIzOa9QJ9c1RGx/hz0fQuUduOb/a5ltvxQRTySNojTlAdncANN7ewSXNJs2Lpp9S3d4j82cMbt
1o2k9pl3ngSxgOOp0fm1HfKjaX9kRMyDbTq7WsAGxwjV/c9nCtmsWxIVGccFSpaNqMYiusvV/0es
r1/q4Fs46kQDJWoi1uyjoDOxxhok+CLmhPVDTlI0ZZr/Y6cwnMuuhks14z/R/YocI8AkGVW+HH98
VsLZNoQIFlcN/SgbPdnaB0OsGHWOsvLUjeSVTFgi7LhtyP2x4scEDCFLfnlspPF3GjbefjIiNEov
rReMj8XKZIexeb9IQeclWRSwXowB0rP1imG+jlL+D9zOv1O8cOhqhRloK62IBi/Wyv9AkmX7EBeR
Z/8wjNay/o4TW/8RsdNOT+8ok/J9vIn5ggctes7WCP/nFkP2WAM1nABVzqyPW26FTGgOCSJ979Fk
x0toxJdlkxb3v0+7lyz1sDv23dt2MlPHqAws1fLdkuovJoKkZ1dlR2NcYCZZPhXjWgvzzwJHlOsB
8gL1IRBL+zYIREP6X3E1poTEEjOq5+tVhVW+WfQBvn6K6xJfsD64LSuwqrVkS1mkzj1TvHxBgRLh
IitT/JuCh0BbwOpt8MsdRQYSA2wJfEG5LoyQsaPpqn2B+WY+1icpU894ty+gRfAAeoIMfCrYMTC1
QY2UMBEuTUb73zaWP6Q7x62Y1YNaD9XESB/ZqWcKT5vIILi9B7TVW0E85E8Hv31PLvY892k8E4LH
huoZ7k7QPkNFdr0xNSSCxH4kgJAXcKrDZ4VTmOLFbUORZFvFEOI3nIV1LRkpvMdO56DWOh4JH78y
YGL9L9QZzbHeQ6rTMNo9CVCa2A1E4zR1SamoBYYtCyzgYKWSwI14selgW7p7Psh5CPcPlQga6rx7
VW4VzokHR07Iq4NniBqqYUCd+RzWwmALqHgpl2U+DVn+4ESKLisI20E0cY5g/ZVY6kMwIQuqWbA5
m+vnwg6f/GJp9gaLfGgh2zKsfvBeHq0XmFw6IQsZst3amWm49qs4uc0dZmuBZkmKK9aGbDnJolL+
+HL1kGBLZUO0+fJin7bYrRHIFYYoZbVYSzy4yX9TgenFG6zYnHS/l16hWZqqfSRzFjgyVwVKF/9E
MwnqImGOVyQ7J+n7uU+AAdP4VR2x3Il35Dhkh6+alwEtB1s/cSs3aiHQ1RKw82qd7N1hEs9lBkW3
BxeVyN8cfAPsmg5mWb1ljOoSb7iX64/9fwuvq13w+piUMxoRXj4bYRn11EPIg3sNkwKXyMx2KJ/J
kuzsGL9ExkUGmzH1Y9CQj2N4Oyx9zjq71VmAzX00Ej6+bzJ2aklj9tv+DnxVIyeoaGvH+3XvFMRK
X/BWsc7+QJfE3eyG9N+YkeZonu+cU3qYTNL+Bw8yamX5zgP4v0k7wXJvdZzCytHB4yLj/F0rW9jJ
arbRSAbHAjCJ6BD4z4AkWvZiZR4WnQ/KOmkMoQrdHRkVRI1QJSXEc55t5uJKmu/GhhfGWPg85J1e
lJ1J3CCFS6e9fG26WV6mYdIEsdKlIKbQjD14w8Oy3KHVczWo9VvKAH12y+g0tdLD+Ag3uOOls7iv
LQy5AizOtPdU7HV1W4NNyWMET14SXbod/LE65NMlIM6jGc8ER0lIKnUfptsVKDF02RLR1yNhn/d7
fmlnhLCRMM51bqDQvlLiMocGsFJCzKw7HBLsASom6Nd/fgRF8xvbwDH7OUsncfeuJiC7AZDAdViq
rC/oB6QwI8TA6CXGAhiI8N/xzptIZ+klEWze4ENMstSH6LlbbIKf56od4VvTTkX85X/P0xDc3Fub
daDexnB067MRkmm/eupSXI9D3OLHr2rPzD9QvGe9/w9P/iiD5p7V3K5qgVcejFTdeYoPYsNJ5bwK
HoN2SRwb6s9WEHPBNlJi+Rll4Xc4vxclzF0plhYWBZVMtDEyeGRNekfz5VariivlbvA3ZpLA2Yzj
lkjD3EIraEnwqDQqT6bBMTHD5sPvIaRuokoYdEqiaL75ZEY0ZDhy4jKACuS7prqhn60SoXMKW1xe
LsJsUCgdgKkCSe3fSGkAZdo/bK7crQ+mqvsbtjgE4CNOxy2T2ZpSnJBhTcVPvhn8W1GB+EjrHIfa
RS/P+lvWENV1PWi85odvoFPP2VWxqeNQ2lLyii9zzMmYNbMhJjF087p6IDPyNq8HwAMNgs+l6JDC
tbOGYt9kMB+czH7rbWe3xWp1yavknXF41UVkrYMYKse5LVvQtHlZJdg0gtfoaR0vCSP7s/6oeFjP
6BIJ/FSAyeLSP4ObMAo1i2124f97gbP+7pMTNSLNrLv4aZD9XOmwvtdixrMAQRZscsyTgF2h11Ue
Tzih4cjJl4bqW9gJ71sWHEdHYruSGcCbrCe2KbJA+9hTSDsJtfdXAi7m3bjL+OUQ8m8Xf9Cfss3A
NWEuU8lRIeO5VCOdZKgO4R2RB45lJ7NyUL/RafKZozgN/i8t0FX+cklls4L/vu87i8A2NgY/Ok/K
3690T9KSdZxIO6OYv25l8k0HsygockP4QhDUPForiNropyUUsbYER3yeYZUf2TYlpEagET75rRI1
2PBJSao5eRsqhbhT14V8Zv4HYxv9GdxzVHZKF86QtR9bEIsQnxZ0YTsovwVzaRWMTtUTedn5PZ8U
JZbkNq3zJUCq+n+TulivCxdBkTIsorpT7+a/+2M32u3M74kvXOoDi3emCYm9IuOFHwaGQgoMdPmt
lW8iLuKKqy/MccgXLz7JfJnxYz4JwhvY2IpupqxdlsttyuXfqS07tOCP47d4edKCH9D/W49aEMRU
/SgAFUdOIYbREO421ZjOopEfuA0eR5ygDSkQf6dGw03b3TGsVvxwnhKERefF5cUeV+Sxz1KI32WH
kcYc6zgntxT8eRDjhp6d2yWx0v/ysZzNgTgMeB7mbk10kpnB0b7h637z8iX46sfMXq0JFomI76v2
l8I646CEQatWvxmakVWdrcQ/uuVvFvBl0OfhYsbgPw+tuRiGwYgzsFjSw9pMFWJoKbvHZstD+7h4
bWH63Vkm2yzLSoks+9wPdCLqKeSvHGA6C9Q5djsKn2SOlauVuRIQyqOk0YG8tIW0Eic2zMUYCCIt
6lz12rd/usiO10p7wiIvGXidb3NLI+MwWhWAYMCUG+Mgm7APMJbbHOm77fowLz5zV/Rs/6VD4uZV
nvnxRteVagtXXCkiMD5W4InZgvq12Sj8hppvYJ7oott7UM4jff2ziOSUPdiu6nhrLpBhi6dzfLec
ot4eLfgPVkW8+xV2mWAN891ji+mc8QBINhSAPLouZJ8AyAGvO83NB6GnQM56MFpjlaYJS+4TFJ93
NTLyvmPInQyoZOajtGRhGlsgdnvEdXSPAUQ2BZTgameaBRs9LsPEh1Y43+J1uyRI6fXErGCJPg6U
9efqVgRobI3Fhgu1eItNuLOseysDprIlxIz79z8ySo+1XLmsZgKp0QFaX1Fhq0wP4t481WIgy/kj
/Z+FAPOZLJbUG8sEo0Vih91S2sql0GY4yORoVZ5zx3JHiffCeCr1tLhT4sQRlwbzY/y1xSUU/ZDN
XzUoPCRrTHxApvYqOFPT+qFZ+vi/UaAftQNDVQSBzxFA/LxopC5pJEVi2mrYlZ3oueUTx3EHOp82
b2LiDk6UPnxZH0zdPQBtr13TPjTgJfFL+FVLUvzqeOJDwko5RYaLmcGYxeVa2Gzsh3rNW1KMwvfE
c6IVV/+g5jTz/iHKpFcOWclEqqn40rAzHXQ1QNuzXzKAOicqI+KX32Irf2QVTl8178biX3+3kusr
eFOsv6836hr3DjTNf7qAkGrCk8lChd3V9iYcEOQZ7KRDykBXfpGU7Qk+8tzpU+r1cj8AQ4+w0CqA
lDlfONdv6Nk/fq/RAHmVhX0pd9fckbonJAg72zazCvO4Xn3kAZdp+2Nmc5UwjN+U3egb74FuPKGM
NdTRLPvjQwMoP9mg2dNVH5iC0QWcY3Dj2sYCg/ALXxG7HV03UFvKZ/AZKssA47IofJ+Pn2oO0oJ8
w4ylFe98xloVwyv9NESeeVPGuYr+KirBJ1ty3GkCRF2HW8tBsSz60/QeBMe4ifhzlJIMcG8FKV/z
BqXUDYpO/W5hogGEpE6s2Ti3NfXxki+jXlRWo6YVfhKkLHMH7SqCFx+c7XnrYfx9YP/DSwPcT83h
+k7Ciey0cMYNVyFtdbOG1LzIJM+5/rCq6X4w8nlT/2ExfY6kYObFismDI2oTpszqR7NiPCpD45P0
z5qRNXEDcdzbECsgK06+0jf0B4a6V5Yt2YlUklRR0IsD/51ucVvAX+yUG9X3PcyOsm05iBRlIQaY
jvd7EOa/cieRbu5dBACs/2C8EQfbzPznfYNV1mvXkXzSXC9q7KXPzzHOsug0GCgxikCMHeTXHDmX
lL24pW6pViuELSQW14IeZZxhh+28/ciZ8iJukv1vsh40gw0E4hMC/XtFUx2kW+gPrwrsT4brWrW5
imvcjRWjPCOdNe61DT8u+PvRBAdA3kGSjbHEHF/tgOfmW5EFLavF0osXZkwRbVsnEmpR1Si+ISbv
Zozo4j5GHr0uC7CyOrugIVncIAJa3AJY/vX08GlV6CxqJ6j5HbQLEpRF8XR2qKA2xhZwQMo9N0mi
2hKzfoahmkD0OjSTbJxfo7jJuODAYAbfFFb/G+5ieTbpdbqPQG/iDpl4XdBuq+J74suA0IQCxoV6
UNNdNPlwdxC0jxh/0mFkfX4poLdzkjipGkvLLWcoBhAuWUSH6ocifFwdnbwkdljh5BNvq6gHYQmO
K8nfdbpy4Eonr3+G28XxsESbTV9iSSuaWQq1imTZzbO+mqmRzOJ4GPUsgXttlFI1eQiFaKRCJvCF
T5BE5DEyHarpSPLseU4oTx1A7lmQT0WLQ9SCDRfGO19O4zSfERrpSJrO0U/4OA7EUmm47WI7aB6o
yjS4BhSJSyu0YJQKBr5dHOOJ77XAFA9bYOUROkWOtnQJ1bKYoPvTtFXkRKWzb4S8DZWysF/N375s
gsAWoSsWKLzIJ1qSBoo95UJi0moAplGlxIyw3il8rHPqc6GdqMGlTc4ZzhVFiQfep5BR0KN2l25v
L83ot/fSeYjClbRaEiVGD9YcKXTq+PYuAzHNNhv9SywOmGwHsEmMASLCYdb7uuYHqqJkYVpbyirq
YuYyBDQfOni3tDG9iRFiHImfYnygq/VjpSUSBaqH3QxZAnkzHkHf4OJmn+IsR1fqL+KwNu3f0gv0
19OlDizWlWlJ3e6fsHAvY3nPBGtNaXHX7oPtxyn8ifZMWSHnIYD/WyDPBLo82U38Z+rf8q0raLPn
gha0mKz5AGniZcghzxRzl4cs9Qh8BhtD4qPmeWujP8l9/i94T9r57T/xugHTa+xnoD4N/+sJjBB0
C2u1OIZTbKsp1UEsZtfcNrNZQuZKmI7zaSfkL2/Kytds6DAO4Jgxz7uP1AxpcDwOduZrqiCXu/ai
DnVCs6FQkKNo81nmYR5/jkX3Lq/onKY4EZguAqpAGLZnyGCkUIgmu1cAE722m7L1Vn0TZLPPVMCI
N3VmF3BW2mdpG89PK4XoX/dmQIsqQN6h7NF1VNAk8DaDr/AvzmN5xxiH1YXwbd48aP/n9QW3Exxu
ohad+9GfvHaHaNarQw+JdZQOvo/h5Py/O2sZ6ljUQKyyene+AlhFSuy82HHny8mG2Bs6gKBC0Rjh
3hdGnsrdCJOetyIxCfS5W22xEm3c71sw9ayszKSa69E+Fc9PTbyWvGw3ATi0H76drtI90UGZ/lMO
fpI14KeZxrDGAhOu9uGsz17i1mkNPhEZs6ul7EZVvqWOZsMM7kagdHCyeTwye5IMZVnmTq3Q8Xwe
4W9lMEwrY043Ne/PRNKes1kU/+ZIX9DrFtWqirH9dFEeBnuy4072kf6RmVr6SO/bo2HUso3ZQNHp
WnY6TTvUrJnoDK8ryAy8UcyOxHvfab0dN2bSkzyWHJ1xeY+kDyWgoCnNNJzH9t1o4dmN6AhC337g
jVIu8YNIa45p3DwLYeN1Fv+FSzw/hzYpZMcM3URadSuYVQkAKkomh8LZxX0D78pcjJlgndp6hehi
bDjKlV21uTrJiR5N
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
Jg7ZSB2xI/J/jQikm8Zlko862zAjpKBGuPSRLj2TaHEWC5rTzr3rFiYHZX6yv0DYk/Y584dxn1Aj
ZJ3fEMF2Eg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
J8XF87MjtG6MD92nYNEuYX3aIPS/zAQYepXrxQuouCoZ7DifIM+PcGRYhyHbT1c+x8wNqIyddvPX
H9E20LneyNoZup9aJc0KklSHkCBi4RFSlJYfEHGi7VuQ4DoNHay9ZZOx7KnkG5nTkuG8dZKhL494
1mvb9OIoIew9S5frQi8=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
FESqZcf5Kd2nw6uez2DBxPYJSBV8lpPPNkL9mii7n9rOA23QnwFT4gzsX2GnAKh0RRoHvqDgwQe2
oriJIgtSnO9GoEYt557lwN4pjAIARzzVKmQozG4a0ZADHcAuh9dE9U2pgm4IYqaA0WHemsJP3RdH
ZWLIA5hjsrEEni35ostJyYxky5xMLNN1/n6HMS0umCbRhs8srgz/a5uvWD7FFpEZ2a0utgDi9MEX
Ot7P9GN3AM5Ug4guXH512IazlVntMqLUCdCGexOO2NqFhGpAvwGxJCtx5XjHjmGW+9m1bqRxt0uC
W0qg1W0dWBjrERQ1cn2SGOV3FZ9QqHCbH1eBSw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
sBWw2a997MC11UDckC6eUhzOMD6OyRi9hIrFSmKM1LtA+EoEe9hBOU+xWnNJxZwh5q/2lTaLVnRD
SOXNd1eh6E6oJtNfyy/eD/u9oSEqrtEAnNkzfHKZvGwMHsKFUk23bSYe/H7pvyiU6gwLB/zQXKRM
aU3uU6qaXWsFaGyQrek=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
I+E3SG6eIVl+eQQNtE5uT75GDZk2w8MwukclTFsLuB0JtjwI9/9l+wqqevSEAZVNako39sma+Yy+
6sWVRLVPo7PjKtoO7mmywH+p7yQSorsf+a3ZiNjDaYRK+f9GNaE4daxPW5KbJ1GJwaVjbrTJXjms
6KviB77YrfOEwKiKJnAPEYDYIIKzPfz0pkPKCCTKaUXpj+fFxyjC7bycPwfKU244d5RTVzX4xHcW
KE2Pbl2/gBhqu0EO5W1xcfaXIFlrwR2GLFrc0Upm7pO12jbH3NSKac9EirjKD5ICy3GjrAPQM9pC
bmcrUujXKJAoYdm46Fb/QQhF+yxNF515651OtA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13008)
`protect data_block
iXdONubG+SYUpFk1+3xjbTmoWUUth5YI3Atb1aEXZ+saXE5+BGO3fPH5sUZBPpBGvC0XNFvrYkWj
mKjKwY2xZcfJ/srndO8S7QOgA1cW3PG5z/BUIxX97bocLtxDa3aP0B0gUaWXB16YHYdYTkHrQeeT
kByzxROgmclqf0h4i+dNw17ZHgg4lSONS85uKTmrmSH+AeVrAMTnAeRVAxyAfN5NPuWFW82kE644
IywqVXyFo+6EjcTaT9MuzpUSuPIiC1uoPJBymXXqJqXLPFIf66+E0NgglyW1yofbtINgNhR1sgx9
DeAt8JD9ezW0dwIbuBVdM7WPULLxlhRiEjVxJrWWqEe7iSi5KOvb5fzvI83hsOJKOziBELmUOamM
/T8ir8zwHa8BgpammyJqhRLzlVnk0jc0ui0l2oBOLEZatZDKIkibZ103V0P30wEv3kgy6CHZSlsx
o+2FQ+rWnn+NLza2SdRplpZXZVeaSlrNxSpEgYaaVJ1hfYU4shpw1gY2+WgUCqWSpnJ07oVnlkGj
XgvkoW7LarBgf5DSufA7OrUOvhEovDc22xsKo/6q9ikE/FrAsfq/b6I1GPuHTq4tNmNgFLJLqW0b
o15QkRHGCFSFVYp01JsJfRhVklzXE3+toKZwdGB3lL7SLiSo1jny3g5F6camzx2bFmrQu5Czeo5C
/YTWlRYi0Y0z4kUwtLuCniSOj5fXjvS+rZqv0fMbSpKDz3yNPptEql6mPHK324bJZULNhyCzaxZu
6mfclZBjFvrJ40zJfG+hWRGPBj7lEQwK9mvMkOaLF3QzB85I/PtNnp79JEkmMsrgHxSoHMgJJoNG
GeQSVZp39h6ji6XfgW1Z402TkKgSqu9DZ/p/XrxV+T9xgzoHNhQQve11khlld5aZoR2Fz0dS6DWY
htxdwg3F3n0HldhSiTENVbQCnSgvpe16MCIUhBeebBdANdreKwenIpNtmV7T3c/f+GPQpaMe0uyD
CAdVU3O6rVoXt3dusGugSMUIauBbyvk9b1/gmJUdGw420PMi+IvocYBxDF0DyTxNo84nnK+qbJ94
1vTQU0XHzhNk+/bfIO9wIOTa/xR7TnIbwelmHQ2DvCac7jth9H9aFIFV77VLdx+lJOWqki9wagmw
xd6Y0RDu6Fnko3AlZAnPA8AV/fBoS/o9Mbb9XenXcb0Gxv3pWX0F5FX3/IYEv+LqJ0x1dnqXRtJd
f3XkTKRhmAv1RHZN4Ijf/26mX+vAAf+WHJboPQj6tVKWcjoiLGqDoK25y5/n695WQznpJm0jhAyt
n3ga+4uHldOnqkP3JRRSm/A4D1m6LtnYsvrEfBKMXTTJyBxZl5SwwWtzjpQQfAmwUjmxt2oRGiwx
WQNGqkz+TTiFQ5ezlAWncaJscI0KVffI14NwBnVogLcYtDZjOXRpYxrr1uPSV4WFyXUYK4w2H515
u1OVDSE7ERA09Y3+88cM1NHWW0nuzw97Ca/B2ksxC+9UGpBq92Z62ZAfYE55Aa4zCYLfmwGVRBoE
feQhSr3J5McYr/O7r8Ns83MgdkOnLTw3Yu6yAGgxoNDOPqr31lpfWEQ6EBJJ8ymfrpl6w2iI0Pou
3Yt8LzN0Xb5Dn9kcNAAqwxEZncjIHsHGjZgKYuGELLEqeJFypgffVVzo69kF06N/3OGu0IsB+NZF
oNQ9CNZnL8ZD6tsKknOLbWTeUN78pkwcJSqYtXBgkyD9UOx8BGFgrNj4k4z+thMS4m1D1R1APj1T
J88qHzUW5a/i6Y/y1jxvgWiDQZCX0O/oRG76lZxPz4TlYHjWusiXb9KDRuPVTj1KXsjEKkQnt27m
ekgt9Y85Eg+SKoLC8QlLzPn+Jcm3krZYv0Wv7jyISxNzhIMEnrX5lGwQHMrLaX5IYgiOb6LFz6IK
ITY2vvm+uKEKRxh+aN9SdKlZF1F3I/lQJIoicGjJsI0/TY/1NH23//QzdaqgGMK9f+g4fHgMnvke
VnsKr37PDikQLBnz8VK4rdoHartXGc4nB9HSQbY05Q0EXZTEG7wXnpOXD9cG0r2pKjjTEwKlW1WK
XwBxuuNvLZY7vEMV7Iv7VPRzudJFyIsVj91zKTZ0kvtHkYK9/Jhpakiy4ooYnNPj/I9D5vYH11kY
K03oqu2tM2sNKJHOzDo12gfCZxIZYp/3Mv7bMTL6UPp1Kc41QS5EkOliFb/hBIpI598iZnnxZiFo
nswi53iePFr4IhvL4XCufFkfN3Kjf1ozXowHvE9PaNfeJyKSK3TclZgUUJB7DxEcXSrXqocyxOmJ
W0rkdt8E4XvSQ9RXnGw08moTmC4Ay/Qm1Hk4VROcz2C5M/BEbD/z3r3rCD6G+I39slabSKb3EPL3
yrBJHvH+XBU/Og2/F6Y4BGtbmBqc+F5Cbezzs97Hchh3W3YUs4BFHq2a++VcEFyHwTHgMli9VaOY
w2XwIS59gPOO1G3+YudsX73xWFwLxSGEqElr5GNcKSybx/KUKP5fuA1KtcxvUurdTXSeBDqf/vsb
KDBcshsTTQzLHqcmaC8u4PSTzQ4l7S73EUXoM9h59/9naeorj1kALVcSetLAa4LyKoKpxpfrlObn
rL7OH4Hnjr6Xt3C5YcPxh2yGykFBndcoUZYxzNUeLBqBjfYju9soiqCkwcqCDBojqq/Z+t605AzQ
PlXjKhmrcz6ds7eYwO1u4KMZFAC4HXvTNL25zDJHkxcTZzcax8gptFOxcmyBZ9nafcZZ/+cu8svY
5OGfVdRDFOlq4Y2nRCAxb5++FTVg0oNkMP67MsAoGCTGfqFHS0mrScicIetb/lC+TbNO+Wx8Nuvo
jOhSu7tAZH4FwoFNudmSrlrGXOVPDeSb95Wvl1EHIVJ/Bt+g8jHN7L3EuP3iYbeXKJNzmhruepU5
/9pGEYnfaVZv1EKuQD0tsS2tShyClZNZ02zxc1YKjbJF/98+1kndtLO0JqmeBEH4rtJUuqe7mh2q
3HpCmfwguA144Kp23ARkOQKAzTh6YE6taVcJGIZlE51FSZyJS2qaXvOUgyHmpQhhl+Qxu5eRp4CR
QgzCw2U8MoWaz4w04G4jBnldDEQkY9jZIq+iS9RwoHGYNmHbhjhRvjxbtqzpMvHb/qKjvHeLin6o
DWEUotoR4Vrbzse2tpKJagIlmH0mstt5BRRPIFMWwHml2VAoln6STdwmzqHItJ6M1wiy2xuBiMOF
jUrBgmufBslF3pAgUBsF9WfKVFnAL01FY8FVdk+WqWK8dUuwLxslJ21FehhfnaDHm/mGR+l/ZIvC
5OmSQaWH27vJT9tlaf+k50s5SF5h9+2C39bKKqW3vSiy3QerLtGmSi6jOHgLfeJPXps+f10PwsjL
fu5qe3IpeezwjDGOXOD8p2CFbqt44kw+23UtDbUfSrJ6wAs7MWNTdUpltMm4hBdW6EEu4Azr8eaE
rOo76O0rP+ct2UXu2buMDccPuOXRwDdptZvw8V6N/qk6ER21uotJk6xKN7fR/Qy19SZYyc35NF92
oMxdadmKfm9fstBbj1aQUG39cPtIBhIIGxUtI112wstvH6fdPb3Gc/7kf2XsGSSawaj3yusoei/d
aYxfLFPeRcORl1oie2nUPwgrzeGcVBicSBcOTGut38nPCyDBKgPPlqUCYDAlWL6e/O/F+eo3HJ8+
Pv8/1ZmfjG24OpCOUChEp76UToTNv66MkIZ7mi/n1fRYk0B/bs7rZytYIgOZEqlLQlqcZ+uKP7pF
gp8kYzRYgBlskLTPWHXesRRfAklL7mcfyrb+kdJwBKowSRhzpbaokwK1C7zDb1obTNbfnr2IZuMC
4Jkve0+vsuZsZDLKWVrVL4gtmEcdpo9dQ9QUnMKbIjmaUtwMQgSCsRzJJwYy9GWDRS4tPB7V/uMd
WkiXyEPITTQxDOQV5famzC1g6uwZeGRNXKKl6Xf3srI8MeJDEr24ifgrZI5RhWlgne7gfOOOHcSb
cfj5uEDoV9nUeqKBPNQCGDJKzKNK3U4UWIUQDwxcby0iUIXu7mcRrPVQ+i8ZSIkNv7uQ63qD8FJ0
0PnuAovE/oecSIx6Us1avEcX7YzKkqjLUWgs2LZOJPMD6dk8MDoMo7ysX5Sl6Tl9JF14RntPqd5i
2mOS72ZPwr9U6SOt4tavm4B/XYOdmY3LdjECmA+G+O9xhvQeiUbpMmCIQGaQ+JLdC43Nu51CMH+m
bsHsVrUO8pxdQqrRm5yGNtBFQJqdg7cWayjf2D658JcIp73SPJd2nsAV1KXVI2I2++AhSCex0spz
H0+4Xjq4I6wcBpiB9ES5IPwBRuCAU+KNF7cxUJfb9AH4MtrABYZp7EUgpGF3kkDgbIMWWy5kI8iQ
gwoif6mSiXdAR43lYDI8ydMmi1P+QqvyE1uwf57rwrXcT9XTolTEyHeathKbcF9H2e/NusWFssxn
ZAsHucSrjOtuhevUZv1j+NFO/tsWJEgQUWwHFUSHl0tSZJr21Jtv04QAXDIe9uKviuEi8M1Zye2q
VIB12DuPRPB5Y5ZTt6VJEynbZczesS1k6ndss5lIqg4YxeC3iPwEQtab/YwbJyKTlDFjJ05Z3I0a
5V+JL20SaQEidsS8+tML5OVYqOF+X5YAnPAd46ujVVHrWIUqpcTvJny9iLXWMp2puwu15oYG/J87
uOBUIg52PONeRo/2ZROHRSCXUnPQQFvIxzzNph+Jqt5ZIXMTZJMFegj5FhwuthtnL7o7o/k8Lyey
YgY+A6AeZeXkPNrO3/jyNDHcx8ngg7j4n4zOIMOsYL1Eq5h2QYgfEDCRImFX+a8vMUUFhFzlUq8Q
+YnZ/g5GghVy02e84jV91RSbdXodjfxIQtHYXE6WajRfQd9Xmc3BRk+8Uk+VlXiEv+gFdtE1jMEl
Y4J6vlUOaVEh0nfexf06/T7jVeseoM1c9nznKqaRyS5cnfLG1Xc/l4idfhct0jnfD4xyo6ztKKc7
ZoWW//Ob3qeNG3mBXNZQUJMmhE2P89DViTozT+GQTzA785Y4apmPojF8ZI66ombhB0Bej2RInX0L
Wdog3njTuUmLQllhN8s0QQIfhHteB+eIH8vSm4vihPzrjwPyRL84uuW5TibDb8uA3j2aXmJ8sARQ
ijh3bM9ltfHOSh+gdfA2CwTtjpCuJPY18zeVTbwrjKjXjO5I50Svt+1f62XsFYJ7w0IzUqVuGGKi
IQIkrQLlKPh5bBbBhVsC9dBjmkkRCGBuawHh0VgUNV1IjwtHW05jlfEyrTJWjUlntujZrtGWGc9z
VRjyV83unGC9AEscKVLm7hTcgw1Uejk7JhTYsWrmnXD/2yniLpA31qEtSZdL4A+bEwKAKbWiQxsG
COwzFFI8dfZ3qGevBY8aA47DZ5uUd0z1t0IeSunBnsNh1mnMj3oOS89PX0dRhciuDE7dbg8+0tBW
9EmHn3PKRmNL1ipXvHIIfYuYc5Od3somla8JnQyl6jBAle2+RUahuA5yMVZLiJ923n8qhGYa7t/S
dKPTiknun9P6w19cPSXpI4v02Mjg5ALkLsMe+4Y4TqElQ07w7hiHGsu7EYCQzpVovud5f/db+g1b
nI9MEUV4/hYX4rVfPm8CDe4KkNvnGMro1E0JXv57X0O0escjc2QvaFP1SNc9KVhyZLJ3lYvDXd3x
YVU8eDke68BRejyCkl7EsUFiyPvyFYF6Vb4XpEWRIiW+qCj2eTK3JY3aS5ubeehk/Df3D3xYofdw
Ps9O02/Xns/UUZj/VWl3GeoM5uK1ckObVDlRwnQlSIa8X6EKAtGbeEyKDtZ/wF9Cd9+6zByRakKG
yAZ0kiS0dH8wvu9JtejXD0Yu3vjX6UgRJprZ9GYUKRN+1KYS/OlJ7wFri824lniD6LCqZb7L0BdN
l4AQ6kM4NrXLDT427YeMNGPoE6FY5QyFuqPLdFUJ1X71o6q6ATkecmV00kaGAk2x2TwwVpfHHpTj
Kab4Xhl93ic752GhbFNJw6BBquu6DFjJEenEJKGIs/Qq5lM1W9MQ+OoHd/On8K+ThjECiWzVBpbX
19ZnKrWbyfTNu+idotUkQRkHnMZfO1oe+p4eeCIPk2f4sRaxVoz4jtahxDdZzrqbgs2lXrQ+h92Z
MJ4JqtyCA2LWlrYOiTgfV6jeJnOT7p8EqA1r5gNMMf73uzJqRhTbLYdhoqY1V9brJqIelEZGwlIV
eObr7vF2SmXqVv+D2+vRjpT9sANMCBFzg5JJXtAYiHbLFJ8WXPAhwsZkuoP/a4pQreq3LHnioRRA
NlirCIpTHWBjIlScqQefBKKuvJKIAZwO+0G5Wa9FG/eQwqM92Ugne64Czm5BwKe1nXlS4MqmO1um
I0b60Gb9nWnTtKFce6YOmmSwUB/FFOT+muekdItDqFC6AtF+AvtUQ+LxE6jEogPrV975od5PONSK
1XCKPqiO75OrG0GvVL4W+lvNsSWCkx5ezq+J+I4ba63UyxL0UJ7ASgXjyUprZVizgkZujeNC59rB
YTyaZRMVtLjriqdEgpHVnA/Mp3OaA/WJJuD4XtLIIkizKKnJpII+saXW9Tzz69ET5zQhZ2lTxjF5
bAPXtnHSYBcyt7s1Junm0aBhPpsstcrQt7A4CDyX1wRNxsrG6K64S70LNtZkzN7p/toH2QOd1Ntn
vk428QrP2w/+RDHCWuPAXKJk1GKTaYFb9o2RlxWMOf782ar2knfS5VHhd59BblwWY0nW2IA61OCo
4OxPCxRPE0HUO5Iq4wg+HMth/Anm8AdPmfHbIYvwHtItB+bqDht1Hr5pQkOydqpCJvnPvYtauzq9
rTq3A3t+nYHY1Q9lwG9WfMcGaK4de8jHn9WrrkEwVnnLj21jZlnV0ZxET7ZlY98c02e1rwVnrWr+
Je5t8HKCBYOR7JCv6DaVwvNIAoqVP51AsGin6sd9h+HhA6aVypIaWjf9tyloV/NzduLhvfjhcV66
WNNxNcgfaDRoCt8Ryd99nsYqwm1v7Tq4EtN0gtX+WoGxn4zzDoF8M3R+yb9b+7YNchfY5n5bXQFn
MCE3vBHAKjWg5uk1qBr75cAu1Qca7g5K92MfGhc+jnnTTux0rvAu8+tJ6X+Edf5DHKiflbQgiG9J
7CTAsB9Q7zkjtJcl7OcPuHTk/3LAHhWdPeIm1LX4NVzF/kt1kI5Vptuu12DpHErhezSs6YWCLAr9
6A5AUIXq46nPZDI79z+GCMgY6Do/KG9RHrttH+qyncHGFhJFIJwAGmHFyM4TXAc56a/ioJI75zBa
csW6uOhgYQo1rVjjGg0JOHgoL2hiSo1cgO8FbaYeABImPoC6h+UmyWIrHPEva8RCDqBIIxYacjF3
Sablky4HqOOqTH3Po3i1W4hePeUWVfmiHqGg+rRQvXt3I5KcOa9BHeP8PLH8WbZnHhybI90AJW4B
ghGrLgpA0BouIjoGXWb28lm9b1cn52FbIvymS/YVDidtBow6phD7ORIC7RN96opz0bgfDpBsFfKk
C1g5JN/wmgOIQ0XanlsorghXFG/y5P9M6hRDR47vsyrhrmea9/a7kEhdCuFyvPL842LMx+nKI3eS
FvJtjqUdksjTtLmVF8b8u6sqwU6UFtHtD9r3ZhLPKmoXtg9KfoRBC245DQs/EvRySHvQuseOcjXx
5RkzTTZ3jjy69kCHaFf8TsIzpmT1k2o6SeItN2z/XLhHF+cOKcMNTrOPKzOndIfCrhVvXL1vUIfY
opdi/RQbj0WYsFBlZxN22CeeLsqS/sFkzosL0tk/QrsDCAW2e5lDVZfaROYbFV2DVaBtCaPsukxr
ii6dJlm6iBgbH592u+f2mI9ze3K3bpsNH3CfLCIYDDI55iw6Qwnxg8cyeNwWyMIdLanykfH7Ju8c
ZcGGHpV0gE7uf5qc3HOBJHrSdvYc359vywTxDuP9P+SJDyx+t60gzygUEutg3fdY29j2wgp2D8A/
gRAG1SnHdPc55yCIzkndYxPE3e9z/tEfzN9bpWTkjECzzAYAeBBClkKk4paB5YWIjvLEVqoh0jfA
ZVK4BErzQihjWblDamZIenulFel5DULaJy+tH7Htt7XS99+kxeShV3OxFaxZmv2wZlozcdBjCWZ+
ibrVwA2Fw4qpfd2/mR9C8rkmZHFEyhlqgOObFsCbVRVhAPifX+s1OAHQnzvqqri2oe0KqyF8nWeY
YkcYb/hkSqPmV/mUoM9CDDcgJQ+MssByY5UZxPuSg35Rlo8SrIeat1xZbZ1y4R/59kJonl4hERMX
KzK/D2HsaS6LuWMCBBAk190mDb1DELlboatAk2U+ynZWeDcMUgeu7V2MDcR+56IG1e6MK9vMw5p5
kyb4IC0NudHIppagDkhVyqyMLYHhl4fbHjw3zJQwP5DmLffEb5u1TgBzbzxhqvOlYpBCjrIXvzo5
JSFcaTA+aXCzM3WWjZeX0dSP3MZV5gcz4e6tELgJxNQhelnifyxFrqU+OJYBo8oJUKU4sCKPafmH
2Dufn9IKryoxUA59p75/NZadSANaqUvLXoqQoRVrbKBRrK9TINJPx//uJsJ6S7btepIbmQmJw7Ui
lEkn2HbtLf7cwgdXyCjgKBL9z+onHs1P8Q78w6U33GSl3kyvbK8KJhTDTcEvB3bHQCd4qeuM4ahE
gk8UNAIAZbbTnza8Y8OhN+gGthKNYe1/+TmfuVD5AB9HbsIB8bazOCqKyifB+eGZVQtn6uB7ShIW
OdpMNUZuhaxwTq469qaRr8EjNS2xE06TFRrauI9CRpMBCBZNSFyTIssidoQWA5JVHGO6eqyXwfgB
vB2BxeV7SQGitHtabgdw08LzDXd6ctJ1tKT2OCht/xesY4Od6hO3ra+xvEGINCjT8XK1s9Q4P4u7
R0GKZ7oa3h3BylbAaJq5fKMjRqLGkXFvjWMTc6rhESpWck6m0TlmfdsXflsCxYWLEibvVDaevwsT
E+uA1UOEjCr+SWq0pClD4fxV1IqCSIwD/hgVnlpu03nhBk9PDfmrDaSeHLKm/uh4y4ogBCKQtQT1
JmW0IgNIaA13zSdQN6wD6dryxMF48Cc/THO3QtA3vl5svNKVWk+mEYu2tNApzArCa+Ifl+x58cC9
9RTOIl2fc9Gy38ArM6S39s+PeEh96xUGVCbAueyKhiO75V2yVROYvgGkC6Qi/KAqaEirBS922Zru
Ye+TY6Q4phjpf/CHGsK0WpRIwokqgkhZ14OC//k+ax0V3DhAJqQ/TcPI2ooG2EpPNdNPYrcXwXRp
9ck4cTWqITnoGg4hzs6/cxrjxIE0OhNYgLKht8zL35OZrJfHJ+KEVNCyOw/JMRpAsB7J4/54DcTW
FsvTSEABYu0I5LqKvs/BLx2tmmXjJqpjTFLA3FqNOPrrfhGkaRxQtAytJKyZibGWAgx1mzNrsrIN
+C2npOErzVY4oGBuXXV9X0qmwkQ/aU7UIyKQa90gmpax3j16L7/R/v9Do0W88WlGrCKZwOiEWfce
kh2fzKBoB+AJHxikJOg6488LLmaxBrPcA4O77GNwoOgWKufHrGUc+MJpYZhzJJ1I4O0l026xoXXo
LfGceXZT/vdoovMcrGf91X099uQQsDy8jqLLziX9f+6qIZUHx47hD4ECXJXV6QyY2lQ4h+gJiOzW
hP1yGVP5PD9jRurrtxcMEuYwQsmIPutHpbt4inFagIVxVX9BbPqyLsiSsfmKkGK5Kui7tWDDHIA0
eBmaW9Xu5hOBy1+qLvCOIPX18643fQWKajUy9kWmB+s9itfVOFuKKshtG/SnRpe5Wetoztp+kuxH
OHaxb4zGcDpebbDjrU55ej4pFpJgg38H7ljkMiGkkLGAn+TwllHeojnqM2mghE1tPG8vjPHD+CMY
uj4exjB1GU1JGByWyms9F0oRdvKliwlIQ05hpPAyMEIoiHHg9hkaOoKrQ+U5vQVga9ofIcH0BZ2L
TEFBqYxtRkqi4yYYMh5zLQ+fJEGSVs0ajiLIwoH1KKmaF1eErvEW86s3d4unJxkpkb2QxBqkebLv
JJIQglskZ6GmqiO9cPpVueo8cyP0ZXXzO1gdxrpLVKx+QPyPIwzRP/x/j6EEgh/rsVZSK81enbkK
HThbYw08GTi/RjVybS7QcsMrMB9FbuzEEAyWs5XH7NlXRTzjwB+huO/s4/BtGuaYwfvD1cXk/UWd
nqYfKzMwtaat+LQjmbPXAHvLdvRbtvSLJLWZSxVURGl8Ez0ZuIyvn35lFNZqh6I1QwAjFQ8WDl7S
9ZuT3xlLkSzxUZOUfC8QdaYV+oklrWZdkKm54M9bfeNQfeRBvylbzdEuIbgkquF02UOH9XJUquuS
Sw0qNuWzAEAK4rLchd4NfuCGNl0J+TSytnoQy/XzF5H8qSc2SQuA18fc0o9Jl0A+dm/ZfdbfMPXU
XLz5bFi3TQ3Jlc25v8IJaoN744m0G+vpEdMPPYrqHz4sXSbIDKbthpOcBfqeTkf+lAq7OG2e0MUm
XWTkWs7LMG8gLWzgi/QEryCMMmbub89tfonU2WLEzS8DyNBeXNj60RV1Xc+d0YWUXJawbOTH9xSD
sg3FK1palRgTIyTAIZm92pZlZPYnu7Roff/MBsVfIbFL+lryo+IP2H6+RyijU7aNlpC5ckqeJTOa
Lah7+s9892HqcXgQ2r3auRNlgI8Sk937dlmT68UjZdWJpi/HLmrCNTVCb+vmctVvQppEusxvG0Jy
kpI1bkdgFQnYIPzTWTODGyjCnghdoRX6ZmfSmculY9PnrF5vJGCSgOpDbZIy++PoYNN/ca9pwb+h
TXSnO9khtCRrt25rryyYrr9M+bUWr6OIr3ud8EaDfMSVCzGdNDBC/iJPfnXYTvdTC7/uWz9v1woz
pGV+m8tzkZjzBHRhDO4CeGWSR3/5H4K+KIHojAT6sCVM1j1wAXZfa0bBXCAiP/TStnZ/UputQgoS
ESPZIVRO4tMkHjNqhPLr0XwO8rmlZK4ejmOWlsYJelRZ5iKeJAKOfD6aTOhrR6Gt1rmz1r5Oe+86
JZqmDk25bLMoZZXMeFrjp81q+KwjxgnVSThF6n87/Z8Br+h7sRZZcjWKBi6UhB7e/XTroPxTNudc
ypLjHedZkWxBnpyAy7HpSv+YmOi7nVDh8opsPlwmMcnyRo87+NKEbI79LVlM/l0iO6Fcfbbm28IL
nQbzcjckRBPNb6ERDo6fOPb+NfdVhDlHNy2QeNc72nI3H+pKanVLjstwurg883OZymM6m9bYDLeX
vsRwJernuWDwDXa7KqyJHa/B/eqqMJR/1CFDdfQzfPr2GRIkx8E23sCVgfEYC8UpQUMMAdpg1nAR
ykbIzOa9QJ9c1RGx/hz0fQuUduOb/a5ltvxQRTySNojTlAdncANN7ewSXNJs2Lpp9S3d4j82cMbt
1o2k9pl3ngSxgOOp0fm1HfKjaX9kRMyDbTq7WsAGxwjV/c9nCtmsWxIVGccFSpaNqMYiusvV/0es
r1/q4Fs46kQDJWoi1uyjoDOxxhok+CLmhPVDTlI0ZZr/Y6cwnMuuhks14z/R/YocI8AkGVW+HH98
VsLZNoQIFlcN/SgbPdnaB0OsGHWOsvLUjeSVTFgi7LhtyP2x4scEDCFLfnlspPF3GjbefjIiNEov
rReMj8XKZIexeb9IQeclWRSwXowB0rP1imG+jlL+D9zOv1O8cOhqhRloK62IBi/Wyv9AkmX7EBeR
Z/8wjNay/o4TW/8RsdNOT+8ok/J9vIn5ggctes7WCP/nFkP2WAM1nABVzqyPW26FTGgOCSJ979Fk
x0toxJdlkxb3v0+7lyz1sDv23dt2MlPHqAws1fLdkuovJoKkZ1dlR2NcYCZZPhXjWgvzzwJHlOsB
8gL1IRBL+zYIREP6X3E1poTEEjOq5+tVhVW+WfQBvn6K6xJfsD64LSuwqrVkS1mkzj1TvHxBgRLh
IitT/JuCh0BbwOpt8MsdRQYSA2wJfEG5LoyQsaPpqn2B+WY+1icpU894ty+gRfAAeoIMfCrYMTC1
QY2UMBEuTUb73zaWP6Q7x62Y1YNaD9XESB/ZqWcKT5vIILi9B7TVW0E85E8Hv31PLvY892k8E4LH
huoZ7k7QPkNFdr0xNSSCxH4kgJAXcKrDZ4VTmOLFbUORZFvFEOI3nIV1LRkpvMdO56DWOh4JH78y
YGL9L9QZzbHeQ6rTMNo9CVCa2A1E4zR1SamoBYYtCyzgYKWSwI14selgW7p7Psh5CPcPlQga6rx7
VW4VzokHR07Iq4NniBqqYUCd+RzWwmALqHgpl2U+DVn+4ESKLisI20E0cY5g/ZVY6kMwIQuqWbA5
m+vnwg6f/GJp9gaLfGgh2zKsfvBeHq0XmFw6IQsZst3amWm49qs4uc0dZmuBZkmKK9aGbDnJolL+
+HL1kGBLZUO0+fJin7bYrRHIFYYoZbVYSzy4yX9TgenFG6zYnHS/l16hWZqqfSRzFjgyVwVKF/9E
MwnqImGOVyQ7J+n7uU+AAdP4VR2x3Il35Dhkh6+alwEtB1s/cSs3aiHQ1RKw82qd7N1hEs9lBkW3
BxeVyN8cfAPsmg5mWb1ljOoSb7iX64/9fwuvq13w+piUMxoRXj4bYRn11EPIg3sNkwKXyMx2KJ/J
kuzsGL9ExkUGmzH1Y9CQj2N4Oyx9zjq71VmAzX00Ej6+bzJ2aklj9tv+DnxVIyeoaGvH+3XvFMRK
X/BWsc7+QJfE3eyG9N+YkeZonu+cU3qYTNL+Bw8yamX5zgP4v0k7wXJvdZzCytHB4yLj/F0rW9jJ
arbRSAbHAjCJ6BD4z4AkWvZiZR4WnQ/KOmkMoQrdHRkVRI1QJSXEc55t5uJKmu/GhhfGWPg85J1e
lJ1J3CCFS6e9fG26WV6mYdIEsdKlIKbQjD14w8Oy3KHVczWo9VvKAH12y+g0tdLD+Ag3uOOls7iv
LQy5AizOtPdU7HV1W4NNyWMET14SXbod/LE65NMlIM6jGc8ER0lIKnUfptsVKDF02RLR1yNhn/d7
fmlnhLCRMM51bqDQvlLiMocGsFJCzKw7HBLsASom6Nd/fgRF8xvbwDH7OUsncfeuJiC7AZDAdViq
rC/oB6QwI8TA6CXGAhiI8N/xzptIZ+klEWze4ENMstSH6LlbbIKf56od4VvTTkX85X/P0xDc3Fub
daDexnB067MRkmm/eupSXI9D3OLHr2rPzD9QvGe9/w9P/iiD5p7V3K5qgVcejFTdeYoPYsNJ5bwK
HoN2SRwb6s9WEHPBNlJi+Rll4Xc4vxclzF0plhYWBZVMtDEyeGRNekfz5VariivlbvA3ZpLA2Yzj
lkjD3EIraEnwqDQqT6bBMTHD5sPvIaRuokoYdEqiaL75ZEY0ZDhy4jKACuS7prqhn60SoXMKW1xe
LsJsUCgdgKkCSe3fSGkAZdo/bK7crQ+mqvsbtjgE4CNOxy2T2ZpSnJBhTcVPvhn8W1GB+EjrHIfa
RS/P+lvWENV1PWi85odvoFPP2VWxqeNQ2lLyii9zzMmYNbMhJjF087p6IDPyNq8HwAMNgs+l6JDC
tbOGYt9kMB+czH7rbWe3xWp1yavknXF41UVkrYMYKse5LVvQtHlZJdg0gtfoaR0vCSP7s/6oeFjP
6BIJ/FSAyeLSP4ObMAo1i2124f97gbP+7pMTNSLNrLv4aZD9XOmwvtdixrMAQRZscsyTgF2h11Ue
Tzih4cjJl4bqW9gJ71sWHEdHYruSGcCbrCe2KbJA+9hTSDsJtfdXAi7m3bjL+OUQ8m8Xf9Cfss3A
NWEuU8lRIeO5VCOdZKgO4R2RB45lJ7NyUL/RafKZozgN/i8t0FX+cklls4L/vu87i8A2NgY/Ok/K
3690T9KSdZxIO6OYv25l8k0HsygockP4QhDUPForiNropyUUsbYER3yeYZUf2TYlpEagET75rRI1
2PBJSao5eRsqhbhT14V8Zv4HYxv9GdxzVHZKF86QtR9bEIsQnxZ0YTsovwVzaRWMTtUTedn5PZ8U
JZbkNq3zJUCq+n+TulivCxdBkTIsorpT7+a/+2M32u3M74kvXOoDi3emCYm9IuOFHwaGQgoMdPmt
lW8iLuKKqy/MccgXLz7JfJnxYz4JwhvY2IpupqxdlsttyuXfqS07tOCP47d4edKCH9D/W49aEMRU
/SgAFUdOIYbREO421ZjOopEfuA0eR5ygDSkQf6dGw03b3TGsVvxwnhKERefF5cUeV+Sxz1KI32WH
kcYc6zgntxT8eRDjhp6d2yWx0v/ysZzNgTgMeB7mbk10kpnB0b7h637z8iX46sfMXq0JFomI76v2
l8I646CEQatWvxmakVWdrcQ/uuVvFvBl0OfhYsbgPw+tuRiGwYgzsFjSw9pMFWJoKbvHZstD+7h4
bWH63Vkm2yzLSoks+9wPdCLqKeSvHGA6C9Q5djsKn2SOlauVuRIQyqOk0YG8tIW0Eic2zMUYCCIt
6lz12rd/usiO10p7wiIvGXidb3NLI+MwWhWAYMCUG+Mgm7APMJbbHOm77fowLz5zV/Rs/6VD4uZV
nvnxRteVagtXXCkiMD5W4InZgvq12Sj8hppvYJ7oott7UM4jff2ziOSUPdiu6nhrLpBhi6dzfLec
ot4eLfgPVkW8+xV2mWAN891ji+mc8QBINhSAPLouZJ8AyAGvO83NB6GnQM56MFpjlaYJS+4TFJ93
NTLyvmPInQyoZOajtGRhGlsgdnvEdXSPAUQ2BZTgameaBRs9LsPEh1Y43+J1uyRI6fXErGCJPg6U
9efqVgRobI3Fhgu1eItNuLOseysDprIlxIz79z8ySo+1XLmsZgKp0QFaX1Fhq0wP4t481WIgy/kj
/Z+FAPOZLJbUG8sEo0Vih91S2sql0GY4yORoVZ5zx3JHiffCeCr1tLhT4sQRlwbzY/y1xSUU/ZDN
XzUoPCRrTHxApvYqOFPT+qFZ+vi/UaAftQNDVQSBzxFA/LxopC5pJEVi2mrYlZ3oueUTx3EHOp82
b2LiDk6UPnxZH0zdPQBtr13TPjTgJfFL+FVLUvzqeOJDwko5RYaLmcGYxeVa2Gzsh3rNW1KMwvfE
c6IVV/+g5jTz/iHKpFcOWclEqqn40rAzHXQ1QNuzXzKAOicqI+KX32Irf2QVTl8178biX3+3kusr
eFOsv6836hr3DjTNf7qAkGrCk8lChd3V9iYcEOQZ7KRDykBXfpGU7Qk+8tzpU+r1cj8AQ4+w0CqA
lDlfONdv6Nk/fq/RAHmVhX0pd9fckbonJAg72zazCvO4Xn3kAZdp+2Nmc5UwjN+U3egb74FuPKGM
NdTRLPvjQwMoP9mg2dNVH5iC0QWcY3Dj2sYCg/ALXxG7HV03UFvKZ/AZKssA47IofJ+Pn2oO0oJ8
w4ylFe98xloVwyv9NESeeVPGuYr+KirBJ1ty3GkCRF2HW8tBsSz60/QeBMe4ifhzlJIMcG8FKV/z
BqXUDYpO/W5hogGEpE6s2Ti3NfXxki+jXlRWo6YVfhKkLHMH7SqCFx+c7XnrYfx9YP/DSwPcT83h
+k7Ciey0cMYNVyFtdbOG1LzIJM+5/rCq6X4w8nlT/2ExfY6kYObFismDI2oTpszqR7NiPCpD45P0
z5qRNXEDcdzbECsgK06+0jf0B4a6V5Yt2YlUklRR0IsD/51ucVvAX+yUG9X3PcyOsm05iBRlIQaY
jvd7EOa/cieRbu5dBACs/2C8EQfbzPznfYNV1mvXkXzSXC9q7KXPzzHOsug0GCgxikCMHeTXHDmX
lL24pW6pViuELSQW14IeZZxhh+28/ciZ8iJukv1vsh40gw0E4hMC/XtFUx2kW+gPrwrsT4brWrW5
imvcjRWjPCOdNe61DT8u+PvRBAdA3kGSjbHEHF/tgOfmW5EFLavF0osXZkwRbVsnEmpR1Si+ISbv
Zozo4j5GHr0uC7CyOrugIVncIAJa3AJY/vX08GlV6CxqJ6j5HbQLEpRF8XR2qKA2xhZwQMo9N0mi
2hKzfoahmkD0OjSTbJxfo7jJuODAYAbfFFb/G+5ieTbpdbqPQG/iDpl4XdBuq+J74suA0IQCxoV6
UNNdNPlwdxC0jxh/0mFkfX4poLdzkjipGkvLLWcoBhAuWUSH6ocifFwdnbwkdljh5BNvq6gHYQmO
K8nfdbpy4Eonr3+G28XxsESbTV9iSSuaWQq1imTZzbO+mqmRzOJ4GPUsgXttlFI1eQiFaKRCJvCF
T5BE5DEyHarpSPLseU4oTx1A7lmQT0WLQ9SCDRfGO19O4zSfERrpSJrO0U/4OA7EUmm47WI7aB6o
yjS4BhSJSyu0YJQKBr5dHOOJ77XAFA9bYOUROkWOtnQJ1bKYoPvTtFXkRKWzb4S8DZWysF/N375s
gsAWoSsWKLzIJ1qSBoo95UJi0moAplGlxIyw3il8rHPqc6GdqMGlTc4ZzhVFiQfep5BR0KN2l25v
L83ot/fSeYjClbRaEiVGD9YcKXTq+PYuAzHNNhv9SywOmGwHsEmMASLCYdb7uuYHqqJkYVpbyirq
YuYyBDQfOni3tDG9iRFiHImfYnygq/VjpSUSBaqH3QxZAnkzHkHf4OJmn+IsR1fqL+KwNu3f0gv0
19OlDizWlWlJ3e6fsHAvY3nPBGtNaXHX7oPtxyn8ifZMWSHnIYD/WyDPBLo82U38Z+rf8q0raLPn
gha0mKz5AGniZcghzxRzl4cs9Qh8BhtD4qPmeWujP8l9/i94T9r57T/xugHTa+xnoD4N/+sJjBB0
C2u1OIZTbKsp1UEsZtfcNrNZQuZKmI7zaSfkL2/Kytds6DAO4Jgxz7uP1AxpcDwOduZrqiCXu/ai
DnVCs6FQkKNo81nmYR5/jkX3Lq/onKY4EZguAqpAGLZnyGCkUIgmu1cAE722m7L1Vn0TZLPPVMCI
N3VmF3BW2mdpG89PK4XoX/dmQIsqQN6h7NF1VNAk8DaDr/AvzmN5xxiH1YXwbd48aP/n9QW3Exxu
ohad+9GfvHaHaNarQw+JdZQOvo/h5Py/O2sZ6ljUQKyyene+AlhFSuy82HHny8mG2Bs6gKBC0Rjh
3hdGnsrdCJOetyIxCfS5W22xEm3c71sw9ayszKSa69E+Fc9PTbyWvGw3ATi0H76drtI90UGZ/lMO
fpI14KeZxrDGAhOu9uGsz17i1mkNPhEZs6ul7EZVvqWOZsMM7kagdHCyeTwye5IMZVnmTq3Q8Xwe
4W9lMEwrY043Ne/PRNKes1kU/+ZIX9DrFtWqirH9dFEeBnuy4072kf6RmVr6SO/bo2HUso3ZQNHp
WnY6TTvUrJnoDK8ryAy8UcyOxHvfab0dN2bSkzyWHJ1xeY+kDyWgoCnNNJzH9t1o4dmN6AhC337g
jVIu8YNIa45p3DwLYeN1Fv+FSzw/hzYpZMcM3URadSuYVQkAKkomh8LZxX0D78pcjJlgndp6hehi
bDjKlV21uTrJiR5N
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
Jg7ZSB2xI/J/jQikm8Zlko862zAjpKBGuPSRLj2TaHEWC5rTzr3rFiYHZX6yv0DYk/Y584dxn1Aj
ZJ3fEMF2Eg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
J8XF87MjtG6MD92nYNEuYX3aIPS/zAQYepXrxQuouCoZ7DifIM+PcGRYhyHbT1c+x8wNqIyddvPX
H9E20LneyNoZup9aJc0KklSHkCBi4RFSlJYfEHGi7VuQ4DoNHay9ZZOx7KnkG5nTkuG8dZKhL494
1mvb9OIoIew9S5frQi8=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
FESqZcf5Kd2nw6uez2DBxPYJSBV8lpPPNkL9mii7n9rOA23QnwFT4gzsX2GnAKh0RRoHvqDgwQe2
oriJIgtSnO9GoEYt557lwN4pjAIARzzVKmQozG4a0ZADHcAuh9dE9U2pgm4IYqaA0WHemsJP3RdH
ZWLIA5hjsrEEni35ostJyYxky5xMLNN1/n6HMS0umCbRhs8srgz/a5uvWD7FFpEZ2a0utgDi9MEX
Ot7P9GN3AM5Ug4guXH512IazlVntMqLUCdCGexOO2NqFhGpAvwGxJCtx5XjHjmGW+9m1bqRxt0uC
W0qg1W0dWBjrERQ1cn2SGOV3FZ9QqHCbH1eBSw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
sBWw2a997MC11UDckC6eUhzOMD6OyRi9hIrFSmKM1LtA+EoEe9hBOU+xWnNJxZwh5q/2lTaLVnRD
SOXNd1eh6E6oJtNfyy/eD/u9oSEqrtEAnNkzfHKZvGwMHsKFUk23bSYe/H7pvyiU6gwLB/zQXKRM
aU3uU6qaXWsFaGyQrek=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
I+E3SG6eIVl+eQQNtE5uT75GDZk2w8MwukclTFsLuB0JtjwI9/9l+wqqevSEAZVNako39sma+Yy+
6sWVRLVPo7PjKtoO7mmywH+p7yQSorsf+a3ZiNjDaYRK+f9GNaE4daxPW5KbJ1GJwaVjbrTJXjms
6KviB77YrfOEwKiKJnAPEYDYIIKzPfz0pkPKCCTKaUXpj+fFxyjC7bycPwfKU244d5RTVzX4xHcW
KE2Pbl2/gBhqu0EO5W1xcfaXIFlrwR2GLFrc0Upm7pO12jbH3NSKac9EirjKD5ICy3GjrAPQM9pC
bmcrUujXKJAoYdm46Fb/QQhF+yxNF515651OtA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13008)
`protect data_block
iXdONubG+SYUpFk1+3xjbTmoWUUth5YI3Atb1aEXZ+saXE5+BGO3fPH5sUZBPpBGvC0XNFvrYkWj
mKjKwY2xZcfJ/srndO8S7QOgA1cW3PG5z/BUIxX97bocLtxDa3aP0B0gUaWXB16YHYdYTkHrQeeT
kByzxROgmclqf0h4i+dNw17ZHgg4lSONS85uKTmrmSH+AeVrAMTnAeRVAxyAfN5NPuWFW82kE644
IywqVXyFo+6EjcTaT9MuzpUSuPIiC1uoPJBymXXqJqXLPFIf66+E0NgglyW1yofbtINgNhR1sgx9
DeAt8JD9ezW0dwIbuBVdM7WPULLxlhRiEjVxJrWWqEe7iSi5KOvb5fzvI83hsOJKOziBELmUOamM
/T8ir8zwHa8BgpammyJqhRLzlVnk0jc0ui0l2oBOLEZatZDKIkibZ103V0P30wEv3kgy6CHZSlsx
o+2FQ+rWnn+NLza2SdRplpZXZVeaSlrNxSpEgYaaVJ1hfYU4shpw1gY2+WgUCqWSpnJ07oVnlkGj
XgvkoW7LarBgf5DSufA7OrUOvhEovDc22xsKo/6q9ikE/FrAsfq/b6I1GPuHTq4tNmNgFLJLqW0b
o15QkRHGCFSFVYp01JsJfRhVklzXE3+toKZwdGB3lL7SLiSo1jny3g5F6camzx2bFmrQu5Czeo5C
/YTWlRYi0Y0z4kUwtLuCniSOj5fXjvS+rZqv0fMbSpKDz3yNPptEql6mPHK324bJZULNhyCzaxZu
6mfclZBjFvrJ40zJfG+hWRGPBj7lEQwK9mvMkOaLF3QzB85I/PtNnp79JEkmMsrgHxSoHMgJJoNG
GeQSVZp39h6ji6XfgW1Z402TkKgSqu9DZ/p/XrxV+T9xgzoHNhQQve11khlld5aZoR2Fz0dS6DWY
htxdwg3F3n0HldhSiTENVbQCnSgvpe16MCIUhBeebBdANdreKwenIpNtmV7T3c/f+GPQpaMe0uyD
CAdVU3O6rVoXt3dusGugSMUIauBbyvk9b1/gmJUdGw420PMi+IvocYBxDF0DyTxNo84nnK+qbJ94
1vTQU0XHzhNk+/bfIO9wIOTa/xR7TnIbwelmHQ2DvCac7jth9H9aFIFV77VLdx+lJOWqki9wagmw
xd6Y0RDu6Fnko3AlZAnPA8AV/fBoS/o9Mbb9XenXcb0Gxv3pWX0F5FX3/IYEv+LqJ0x1dnqXRtJd
f3XkTKRhmAv1RHZN4Ijf/26mX+vAAf+WHJboPQj6tVKWcjoiLGqDoK25y5/n695WQznpJm0jhAyt
n3ga+4uHldOnqkP3JRRSm/A4D1m6LtnYsvrEfBKMXTTJyBxZl5SwwWtzjpQQfAmwUjmxt2oRGiwx
WQNGqkz+TTiFQ5ezlAWncaJscI0KVffI14NwBnVogLcYtDZjOXRpYxrr1uPSV4WFyXUYK4w2H515
u1OVDSE7ERA09Y3+88cM1NHWW0nuzw97Ca/B2ksxC+9UGpBq92Z62ZAfYE55Aa4zCYLfmwGVRBoE
feQhSr3J5McYr/O7r8Ns83MgdkOnLTw3Yu6yAGgxoNDOPqr31lpfWEQ6EBJJ8ymfrpl6w2iI0Pou
3Yt8LzN0Xb5Dn9kcNAAqwxEZncjIHsHGjZgKYuGELLEqeJFypgffVVzo69kF06N/3OGu0IsB+NZF
oNQ9CNZnL8ZD6tsKknOLbWTeUN78pkwcJSqYtXBgkyD9UOx8BGFgrNj4k4z+thMS4m1D1R1APj1T
J88qHzUW5a/i6Y/y1jxvgWiDQZCX0O/oRG76lZxPz4TlYHjWusiXb9KDRuPVTj1KXsjEKkQnt27m
ekgt9Y85Eg+SKoLC8QlLzPn+Jcm3krZYv0Wv7jyISxNzhIMEnrX5lGwQHMrLaX5IYgiOb6LFz6IK
ITY2vvm+uKEKRxh+aN9SdKlZF1F3I/lQJIoicGjJsI0/TY/1NH23//QzdaqgGMK9f+g4fHgMnvke
VnsKr37PDikQLBnz8VK4rdoHartXGc4nB9HSQbY05Q0EXZTEG7wXnpOXD9cG0r2pKjjTEwKlW1WK
XwBxuuNvLZY7vEMV7Iv7VPRzudJFyIsVj91zKTZ0kvtHkYK9/Jhpakiy4ooYnNPj/I9D5vYH11kY
K03oqu2tM2sNKJHOzDo12gfCZxIZYp/3Mv7bMTL6UPp1Kc41QS5EkOliFb/hBIpI598iZnnxZiFo
nswi53iePFr4IhvL4XCufFkfN3Kjf1ozXowHvE9PaNfeJyKSK3TclZgUUJB7DxEcXSrXqocyxOmJ
W0rkdt8E4XvSQ9RXnGw08moTmC4Ay/Qm1Hk4VROcz2C5M/BEbD/z3r3rCD6G+I39slabSKb3EPL3
yrBJHvH+XBU/Og2/F6Y4BGtbmBqc+F5Cbezzs97Hchh3W3YUs4BFHq2a++VcEFyHwTHgMli9VaOY
w2XwIS59gPOO1G3+YudsX73xWFwLxSGEqElr5GNcKSybx/KUKP5fuA1KtcxvUurdTXSeBDqf/vsb
KDBcshsTTQzLHqcmaC8u4PSTzQ4l7S73EUXoM9h59/9naeorj1kALVcSetLAa4LyKoKpxpfrlObn
rL7OH4Hnjr6Xt3C5YcPxh2yGykFBndcoUZYxzNUeLBqBjfYju9soiqCkwcqCDBojqq/Z+t605AzQ
PlXjKhmrcz6ds7eYwO1u4KMZFAC4HXvTNL25zDJHkxcTZzcax8gptFOxcmyBZ9nafcZZ/+cu8svY
5OGfVdRDFOlq4Y2nRCAxb5++FTVg0oNkMP67MsAoGCTGfqFHS0mrScicIetb/lC+TbNO+Wx8Nuvo
jOhSu7tAZH4FwoFNudmSrlrGXOVPDeSb95Wvl1EHIVJ/Bt+g8jHN7L3EuP3iYbeXKJNzmhruepU5
/9pGEYnfaVZv1EKuQD0tsS2tShyClZNZ02zxc1YKjbJF/98+1kndtLO0JqmeBEH4rtJUuqe7mh2q
3HpCmfwguA144Kp23ARkOQKAzTh6YE6taVcJGIZlE51FSZyJS2qaXvOUgyHmpQhhl+Qxu5eRp4CR
QgzCw2U8MoWaz4w04G4jBnldDEQkY9jZIq+iS9RwoHGYNmHbhjhRvjxbtqzpMvHb/qKjvHeLin6o
DWEUotoR4Vrbzse2tpKJagIlmH0mstt5BRRPIFMWwHml2VAoln6STdwmzqHItJ6M1wiy2xuBiMOF
jUrBgmufBslF3pAgUBsF9WfKVFnAL01FY8FVdk+WqWK8dUuwLxslJ21FehhfnaDHm/mGR+l/ZIvC
5OmSQaWH27vJT9tlaf+k50s5SF5h9+2C39bKKqW3vSiy3QerLtGmSi6jOHgLfeJPXps+f10PwsjL
fu5qe3IpeezwjDGOXOD8p2CFbqt44kw+23UtDbUfSrJ6wAs7MWNTdUpltMm4hBdW6EEu4Azr8eaE
rOo76O0rP+ct2UXu2buMDccPuOXRwDdptZvw8V6N/qk6ER21uotJk6xKN7fR/Qy19SZYyc35NF92
oMxdadmKfm9fstBbj1aQUG39cPtIBhIIGxUtI112wstvH6fdPb3Gc/7kf2XsGSSawaj3yusoei/d
aYxfLFPeRcORl1oie2nUPwgrzeGcVBicSBcOTGut38nPCyDBKgPPlqUCYDAlWL6e/O/F+eo3HJ8+
Pv8/1ZmfjG24OpCOUChEp76UToTNv66MkIZ7mi/n1fRYk0B/bs7rZytYIgOZEqlLQlqcZ+uKP7pF
gp8kYzRYgBlskLTPWHXesRRfAklL7mcfyrb+kdJwBKowSRhzpbaokwK1C7zDb1obTNbfnr2IZuMC
4Jkve0+vsuZsZDLKWVrVL4gtmEcdpo9dQ9QUnMKbIjmaUtwMQgSCsRzJJwYy9GWDRS4tPB7V/uMd
WkiXyEPITTQxDOQV5famzC1g6uwZeGRNXKKl6Xf3srI8MeJDEr24ifgrZI5RhWlgne7gfOOOHcSb
cfj5uEDoV9nUeqKBPNQCGDJKzKNK3U4UWIUQDwxcby0iUIXu7mcRrPVQ+i8ZSIkNv7uQ63qD8FJ0
0PnuAovE/oecSIx6Us1avEcX7YzKkqjLUWgs2LZOJPMD6dk8MDoMo7ysX5Sl6Tl9JF14RntPqd5i
2mOS72ZPwr9U6SOt4tavm4B/XYOdmY3LdjECmA+G+O9xhvQeiUbpMmCIQGaQ+JLdC43Nu51CMH+m
bsHsVrUO8pxdQqrRm5yGNtBFQJqdg7cWayjf2D658JcIp73SPJd2nsAV1KXVI2I2++AhSCex0spz
H0+4Xjq4I6wcBpiB9ES5IPwBRuCAU+KNF7cxUJfb9AH4MtrABYZp7EUgpGF3kkDgbIMWWy5kI8iQ
gwoif6mSiXdAR43lYDI8ydMmi1P+QqvyE1uwf57rwrXcT9XTolTEyHeathKbcF9H2e/NusWFssxn
ZAsHucSrjOtuhevUZv1j+NFO/tsWJEgQUWwHFUSHl0tSZJr21Jtv04QAXDIe9uKviuEi8M1Zye2q
VIB12DuPRPB5Y5ZTt6VJEynbZczesS1k6ndss5lIqg4YxeC3iPwEQtab/YwbJyKTlDFjJ05Z3I0a
5V+JL20SaQEidsS8+tML5OVYqOF+X5YAnPAd46ujVVHrWIUqpcTvJny9iLXWMp2puwu15oYG/J87
uOBUIg52PONeRo/2ZROHRSCXUnPQQFvIxzzNph+Jqt5ZIXMTZJMFegj5FhwuthtnL7o7o/k8Lyey
YgY+A6AeZeXkPNrO3/jyNDHcx8ngg7j4n4zOIMOsYL1Eq5h2QYgfEDCRImFX+a8vMUUFhFzlUq8Q
+YnZ/g5GghVy02e84jV91RSbdXodjfxIQtHYXE6WajRfQd9Xmc3BRk+8Uk+VlXiEv+gFdtE1jMEl
Y4J6vlUOaVEh0nfexf06/T7jVeseoM1c9nznKqaRyS5cnfLG1Xc/l4idfhct0jnfD4xyo6ztKKc7
ZoWW//Ob3qeNG3mBXNZQUJMmhE2P89DViTozT+GQTzA785Y4apmPojF8ZI66ombhB0Bej2RInX0L
Wdog3njTuUmLQllhN8s0QQIfhHteB+eIH8vSm4vihPzrjwPyRL84uuW5TibDb8uA3j2aXmJ8sARQ
ijh3bM9ltfHOSh+gdfA2CwTtjpCuJPY18zeVTbwrjKjXjO5I50Svt+1f62XsFYJ7w0IzUqVuGGKi
IQIkrQLlKPh5bBbBhVsC9dBjmkkRCGBuawHh0VgUNV1IjwtHW05jlfEyrTJWjUlntujZrtGWGc9z
VRjyV83unGC9AEscKVLm7hTcgw1Uejk7JhTYsWrmnXD/2yniLpA31qEtSZdL4A+bEwKAKbWiQxsG
COwzFFI8dfZ3qGevBY8aA47DZ5uUd0z1t0IeSunBnsNh1mnMj3oOS89PX0dRhciuDE7dbg8+0tBW
9EmHn3PKRmNL1ipXvHIIfYuYc5Od3somla8JnQyl6jBAle2+RUahuA5yMVZLiJ923n8qhGYa7t/S
dKPTiknun9P6w19cPSXpI4v02Mjg5ALkLsMe+4Y4TqElQ07w7hiHGsu7EYCQzpVovud5f/db+g1b
nI9MEUV4/hYX4rVfPm8CDe4KkNvnGMro1E0JXv57X0O0escjc2QvaFP1SNc9KVhyZLJ3lYvDXd3x
YVU8eDke68BRejyCkl7EsUFiyPvyFYF6Vb4XpEWRIiW+qCj2eTK3JY3aS5ubeehk/Df3D3xYofdw
Ps9O02/Xns/UUZj/VWl3GeoM5uK1ckObVDlRwnQlSIa8X6EKAtGbeEyKDtZ/wF9Cd9+6zByRakKG
yAZ0kiS0dH8wvu9JtejXD0Yu3vjX6UgRJprZ9GYUKRN+1KYS/OlJ7wFri824lniD6LCqZb7L0BdN
l4AQ6kM4NrXLDT427YeMNGPoE6FY5QyFuqPLdFUJ1X71o6q6ATkecmV00kaGAk2x2TwwVpfHHpTj
Kab4Xhl93ic752GhbFNJw6BBquu6DFjJEenEJKGIs/Qq5lM1W9MQ+OoHd/On8K+ThjECiWzVBpbX
19ZnKrWbyfTNu+idotUkQRkHnMZfO1oe+p4eeCIPk2f4sRaxVoz4jtahxDdZzrqbgs2lXrQ+h92Z
MJ4JqtyCA2LWlrYOiTgfV6jeJnOT7p8EqA1r5gNMMf73uzJqRhTbLYdhoqY1V9brJqIelEZGwlIV
eObr7vF2SmXqVv+D2+vRjpT9sANMCBFzg5JJXtAYiHbLFJ8WXPAhwsZkuoP/a4pQreq3LHnioRRA
NlirCIpTHWBjIlScqQefBKKuvJKIAZwO+0G5Wa9FG/eQwqM92Ugne64Czm5BwKe1nXlS4MqmO1um
I0b60Gb9nWnTtKFce6YOmmSwUB/FFOT+muekdItDqFC6AtF+AvtUQ+LxE6jEogPrV975od5PONSK
1XCKPqiO75OrG0GvVL4W+lvNsSWCkx5ezq+J+I4ba63UyxL0UJ7ASgXjyUprZVizgkZujeNC59rB
YTyaZRMVtLjriqdEgpHVnA/Mp3OaA/WJJuD4XtLIIkizKKnJpII+saXW9Tzz69ET5zQhZ2lTxjF5
bAPXtnHSYBcyt7s1Junm0aBhPpsstcrQt7A4CDyX1wRNxsrG6K64S70LNtZkzN7p/toH2QOd1Ntn
vk428QrP2w/+RDHCWuPAXKJk1GKTaYFb9o2RlxWMOf782ar2knfS5VHhd59BblwWY0nW2IA61OCo
4OxPCxRPE0HUO5Iq4wg+HMth/Anm8AdPmfHbIYvwHtItB+bqDht1Hr5pQkOydqpCJvnPvYtauzq9
rTq3A3t+nYHY1Q9lwG9WfMcGaK4de8jHn9WrrkEwVnnLj21jZlnV0ZxET7ZlY98c02e1rwVnrWr+
Je5t8HKCBYOR7JCv6DaVwvNIAoqVP51AsGin6sd9h+HhA6aVypIaWjf9tyloV/NzduLhvfjhcV66
WNNxNcgfaDRoCt8Ryd99nsYqwm1v7Tq4EtN0gtX+WoGxn4zzDoF8M3R+yb9b+7YNchfY5n5bXQFn
MCE3vBHAKjWg5uk1qBr75cAu1Qca7g5K92MfGhc+jnnTTux0rvAu8+tJ6X+Edf5DHKiflbQgiG9J
7CTAsB9Q7zkjtJcl7OcPuHTk/3LAHhWdPeIm1LX4NVzF/kt1kI5Vptuu12DpHErhezSs6YWCLAr9
6A5AUIXq46nPZDI79z+GCMgY6Do/KG9RHrttH+qyncHGFhJFIJwAGmHFyM4TXAc56a/ioJI75zBa
csW6uOhgYQo1rVjjGg0JOHgoL2hiSo1cgO8FbaYeABImPoC6h+UmyWIrHPEva8RCDqBIIxYacjF3
Sablky4HqOOqTH3Po3i1W4hePeUWVfmiHqGg+rRQvXt3I5KcOa9BHeP8PLH8WbZnHhybI90AJW4B
ghGrLgpA0BouIjoGXWb28lm9b1cn52FbIvymS/YVDidtBow6phD7ORIC7RN96opz0bgfDpBsFfKk
C1g5JN/wmgOIQ0XanlsorghXFG/y5P9M6hRDR47vsyrhrmea9/a7kEhdCuFyvPL842LMx+nKI3eS
FvJtjqUdksjTtLmVF8b8u6sqwU6UFtHtD9r3ZhLPKmoXtg9KfoRBC245DQs/EvRySHvQuseOcjXx
5RkzTTZ3jjy69kCHaFf8TsIzpmT1k2o6SeItN2z/XLhHF+cOKcMNTrOPKzOndIfCrhVvXL1vUIfY
opdi/RQbj0WYsFBlZxN22CeeLsqS/sFkzosL0tk/QrsDCAW2e5lDVZfaROYbFV2DVaBtCaPsukxr
ii6dJlm6iBgbH592u+f2mI9ze3K3bpsNH3CfLCIYDDI55iw6Qwnxg8cyeNwWyMIdLanykfH7Ju8c
ZcGGHpV0gE7uf5qc3HOBJHrSdvYc359vywTxDuP9P+SJDyx+t60gzygUEutg3fdY29j2wgp2D8A/
gRAG1SnHdPc55yCIzkndYxPE3e9z/tEfzN9bpWTkjECzzAYAeBBClkKk4paB5YWIjvLEVqoh0jfA
ZVK4BErzQihjWblDamZIenulFel5DULaJy+tH7Htt7XS99+kxeShV3OxFaxZmv2wZlozcdBjCWZ+
ibrVwA2Fw4qpfd2/mR9C8rkmZHFEyhlqgOObFsCbVRVhAPifX+s1OAHQnzvqqri2oe0KqyF8nWeY
YkcYb/hkSqPmV/mUoM9CDDcgJQ+MssByY5UZxPuSg35Rlo8SrIeat1xZbZ1y4R/59kJonl4hERMX
KzK/D2HsaS6LuWMCBBAk190mDb1DELlboatAk2U+ynZWeDcMUgeu7V2MDcR+56IG1e6MK9vMw5p5
kyb4IC0NudHIppagDkhVyqyMLYHhl4fbHjw3zJQwP5DmLffEb5u1TgBzbzxhqvOlYpBCjrIXvzo5
JSFcaTA+aXCzM3WWjZeX0dSP3MZV5gcz4e6tELgJxNQhelnifyxFrqU+OJYBo8oJUKU4sCKPafmH
2Dufn9IKryoxUA59p75/NZadSANaqUvLXoqQoRVrbKBRrK9TINJPx//uJsJ6S7btepIbmQmJw7Ui
lEkn2HbtLf7cwgdXyCjgKBL9z+onHs1P8Q78w6U33GSl3kyvbK8KJhTDTcEvB3bHQCd4qeuM4ahE
gk8UNAIAZbbTnza8Y8OhN+gGthKNYe1/+TmfuVD5AB9HbsIB8bazOCqKyifB+eGZVQtn6uB7ShIW
OdpMNUZuhaxwTq469qaRr8EjNS2xE06TFRrauI9CRpMBCBZNSFyTIssidoQWA5JVHGO6eqyXwfgB
vB2BxeV7SQGitHtabgdw08LzDXd6ctJ1tKT2OCht/xesY4Od6hO3ra+xvEGINCjT8XK1s9Q4P4u7
R0GKZ7oa3h3BylbAaJq5fKMjRqLGkXFvjWMTc6rhESpWck6m0TlmfdsXflsCxYWLEibvVDaevwsT
E+uA1UOEjCr+SWq0pClD4fxV1IqCSIwD/hgVnlpu03nhBk9PDfmrDaSeHLKm/uh4y4ogBCKQtQT1
JmW0IgNIaA13zSdQN6wD6dryxMF48Cc/THO3QtA3vl5svNKVWk+mEYu2tNApzArCa+Ifl+x58cC9
9RTOIl2fc9Gy38ArM6S39s+PeEh96xUGVCbAueyKhiO75V2yVROYvgGkC6Qi/KAqaEirBS922Zru
Ye+TY6Q4phjpf/CHGsK0WpRIwokqgkhZ14OC//k+ax0V3DhAJqQ/TcPI2ooG2EpPNdNPYrcXwXRp
9ck4cTWqITnoGg4hzs6/cxrjxIE0OhNYgLKht8zL35OZrJfHJ+KEVNCyOw/JMRpAsB7J4/54DcTW
FsvTSEABYu0I5LqKvs/BLx2tmmXjJqpjTFLA3FqNOPrrfhGkaRxQtAytJKyZibGWAgx1mzNrsrIN
+C2npOErzVY4oGBuXXV9X0qmwkQ/aU7UIyKQa90gmpax3j16L7/R/v9Do0W88WlGrCKZwOiEWfce
kh2fzKBoB+AJHxikJOg6488LLmaxBrPcA4O77GNwoOgWKufHrGUc+MJpYZhzJJ1I4O0l026xoXXo
LfGceXZT/vdoovMcrGf91X099uQQsDy8jqLLziX9f+6qIZUHx47hD4ECXJXV6QyY2lQ4h+gJiOzW
hP1yGVP5PD9jRurrtxcMEuYwQsmIPutHpbt4inFagIVxVX9BbPqyLsiSsfmKkGK5Kui7tWDDHIA0
eBmaW9Xu5hOBy1+qLvCOIPX18643fQWKajUy9kWmB+s9itfVOFuKKshtG/SnRpe5Wetoztp+kuxH
OHaxb4zGcDpebbDjrU55ej4pFpJgg38H7ljkMiGkkLGAn+TwllHeojnqM2mghE1tPG8vjPHD+CMY
uj4exjB1GU1JGByWyms9F0oRdvKliwlIQ05hpPAyMEIoiHHg9hkaOoKrQ+U5vQVga9ofIcH0BZ2L
TEFBqYxtRkqi4yYYMh5zLQ+fJEGSVs0ajiLIwoH1KKmaF1eErvEW86s3d4unJxkpkb2QxBqkebLv
JJIQglskZ6GmqiO9cPpVueo8cyP0ZXXzO1gdxrpLVKx+QPyPIwzRP/x/j6EEgh/rsVZSK81enbkK
HThbYw08GTi/RjVybS7QcsMrMB9FbuzEEAyWs5XH7NlXRTzjwB+huO/s4/BtGuaYwfvD1cXk/UWd
nqYfKzMwtaat+LQjmbPXAHvLdvRbtvSLJLWZSxVURGl8Ez0ZuIyvn35lFNZqh6I1QwAjFQ8WDl7S
9ZuT3xlLkSzxUZOUfC8QdaYV+oklrWZdkKm54M9bfeNQfeRBvylbzdEuIbgkquF02UOH9XJUquuS
Sw0qNuWzAEAK4rLchd4NfuCGNl0J+TSytnoQy/XzF5H8qSc2SQuA18fc0o9Jl0A+dm/ZfdbfMPXU
XLz5bFi3TQ3Jlc25v8IJaoN744m0G+vpEdMPPYrqHz4sXSbIDKbthpOcBfqeTkf+lAq7OG2e0MUm
XWTkWs7LMG8gLWzgi/QEryCMMmbub89tfonU2WLEzS8DyNBeXNj60RV1Xc+d0YWUXJawbOTH9xSD
sg3FK1palRgTIyTAIZm92pZlZPYnu7Roff/MBsVfIbFL+lryo+IP2H6+RyijU7aNlpC5ckqeJTOa
Lah7+s9892HqcXgQ2r3auRNlgI8Sk937dlmT68UjZdWJpi/HLmrCNTVCb+vmctVvQppEusxvG0Jy
kpI1bkdgFQnYIPzTWTODGyjCnghdoRX6ZmfSmculY9PnrF5vJGCSgOpDbZIy++PoYNN/ca9pwb+h
TXSnO9khtCRrt25rryyYrr9M+bUWr6OIr3ud8EaDfMSVCzGdNDBC/iJPfnXYTvdTC7/uWz9v1woz
pGV+m8tzkZjzBHRhDO4CeGWSR3/5H4K+KIHojAT6sCVM1j1wAXZfa0bBXCAiP/TStnZ/UputQgoS
ESPZIVRO4tMkHjNqhPLr0XwO8rmlZK4ejmOWlsYJelRZ5iKeJAKOfD6aTOhrR6Gt1rmz1r5Oe+86
JZqmDk25bLMoZZXMeFrjp81q+KwjxgnVSThF6n87/Z8Br+h7sRZZcjWKBi6UhB7e/XTroPxTNudc
ypLjHedZkWxBnpyAy7HpSv+YmOi7nVDh8opsPlwmMcnyRo87+NKEbI79LVlM/l0iO6Fcfbbm28IL
nQbzcjckRBPNb6ERDo6fOPb+NfdVhDlHNy2QeNc72nI3H+pKanVLjstwurg883OZymM6m9bYDLeX
vsRwJernuWDwDXa7KqyJHa/B/eqqMJR/1CFDdfQzfPr2GRIkx8E23sCVgfEYC8UpQUMMAdpg1nAR
ykbIzOa9QJ9c1RGx/hz0fQuUduOb/a5ltvxQRTySNojTlAdncANN7ewSXNJs2Lpp9S3d4j82cMbt
1o2k9pl3ngSxgOOp0fm1HfKjaX9kRMyDbTq7WsAGxwjV/c9nCtmsWxIVGccFSpaNqMYiusvV/0es
r1/q4Fs46kQDJWoi1uyjoDOxxhok+CLmhPVDTlI0ZZr/Y6cwnMuuhks14z/R/YocI8AkGVW+HH98
VsLZNoQIFlcN/SgbPdnaB0OsGHWOsvLUjeSVTFgi7LhtyP2x4scEDCFLfnlspPF3GjbefjIiNEov
rReMj8XKZIexeb9IQeclWRSwXowB0rP1imG+jlL+D9zOv1O8cOhqhRloK62IBi/Wyv9AkmX7EBeR
Z/8wjNay/o4TW/8RsdNOT+8ok/J9vIn5ggctes7WCP/nFkP2WAM1nABVzqyPW26FTGgOCSJ979Fk
x0toxJdlkxb3v0+7lyz1sDv23dt2MlPHqAws1fLdkuovJoKkZ1dlR2NcYCZZPhXjWgvzzwJHlOsB
8gL1IRBL+zYIREP6X3E1poTEEjOq5+tVhVW+WfQBvn6K6xJfsD64LSuwqrVkS1mkzj1TvHxBgRLh
IitT/JuCh0BbwOpt8MsdRQYSA2wJfEG5LoyQsaPpqn2B+WY+1icpU894ty+gRfAAeoIMfCrYMTC1
QY2UMBEuTUb73zaWP6Q7x62Y1YNaD9XESB/ZqWcKT5vIILi9B7TVW0E85E8Hv31PLvY892k8E4LH
huoZ7k7QPkNFdr0xNSSCxH4kgJAXcKrDZ4VTmOLFbUORZFvFEOI3nIV1LRkpvMdO56DWOh4JH78y
YGL9L9QZzbHeQ6rTMNo9CVCa2A1E4zR1SamoBYYtCyzgYKWSwI14selgW7p7Psh5CPcPlQga6rx7
VW4VzokHR07Iq4NniBqqYUCd+RzWwmALqHgpl2U+DVn+4ESKLisI20E0cY5g/ZVY6kMwIQuqWbA5
m+vnwg6f/GJp9gaLfGgh2zKsfvBeHq0XmFw6IQsZst3amWm49qs4uc0dZmuBZkmKK9aGbDnJolL+
+HL1kGBLZUO0+fJin7bYrRHIFYYoZbVYSzy4yX9TgenFG6zYnHS/l16hWZqqfSRzFjgyVwVKF/9E
MwnqImGOVyQ7J+n7uU+AAdP4VR2x3Il35Dhkh6+alwEtB1s/cSs3aiHQ1RKw82qd7N1hEs9lBkW3
BxeVyN8cfAPsmg5mWb1ljOoSb7iX64/9fwuvq13w+piUMxoRXj4bYRn11EPIg3sNkwKXyMx2KJ/J
kuzsGL9ExkUGmzH1Y9CQj2N4Oyx9zjq71VmAzX00Ej6+bzJ2aklj9tv+DnxVIyeoaGvH+3XvFMRK
X/BWsc7+QJfE3eyG9N+YkeZonu+cU3qYTNL+Bw8yamX5zgP4v0k7wXJvdZzCytHB4yLj/F0rW9jJ
arbRSAbHAjCJ6BD4z4AkWvZiZR4WnQ/KOmkMoQrdHRkVRI1QJSXEc55t5uJKmu/GhhfGWPg85J1e
lJ1J3CCFS6e9fG26WV6mYdIEsdKlIKbQjD14w8Oy3KHVczWo9VvKAH12y+g0tdLD+Ag3uOOls7iv
LQy5AizOtPdU7HV1W4NNyWMET14SXbod/LE65NMlIM6jGc8ER0lIKnUfptsVKDF02RLR1yNhn/d7
fmlnhLCRMM51bqDQvlLiMocGsFJCzKw7HBLsASom6Nd/fgRF8xvbwDH7OUsncfeuJiC7AZDAdViq
rC/oB6QwI8TA6CXGAhiI8N/xzptIZ+klEWze4ENMstSH6LlbbIKf56od4VvTTkX85X/P0xDc3Fub
daDexnB067MRkmm/eupSXI9D3OLHr2rPzD9QvGe9/w9P/iiD5p7V3K5qgVcejFTdeYoPYsNJ5bwK
HoN2SRwb6s9WEHPBNlJi+Rll4Xc4vxclzF0plhYWBZVMtDEyeGRNekfz5VariivlbvA3ZpLA2Yzj
lkjD3EIraEnwqDQqT6bBMTHD5sPvIaRuokoYdEqiaL75ZEY0ZDhy4jKACuS7prqhn60SoXMKW1xe
LsJsUCgdgKkCSe3fSGkAZdo/bK7crQ+mqvsbtjgE4CNOxy2T2ZpSnJBhTcVPvhn8W1GB+EjrHIfa
RS/P+lvWENV1PWi85odvoFPP2VWxqeNQ2lLyii9zzMmYNbMhJjF087p6IDPyNq8HwAMNgs+l6JDC
tbOGYt9kMB+czH7rbWe3xWp1yavknXF41UVkrYMYKse5LVvQtHlZJdg0gtfoaR0vCSP7s/6oeFjP
6BIJ/FSAyeLSP4ObMAo1i2124f97gbP+7pMTNSLNrLv4aZD9XOmwvtdixrMAQRZscsyTgF2h11Ue
Tzih4cjJl4bqW9gJ71sWHEdHYruSGcCbrCe2KbJA+9hTSDsJtfdXAi7m3bjL+OUQ8m8Xf9Cfss3A
NWEuU8lRIeO5VCOdZKgO4R2RB45lJ7NyUL/RafKZozgN/i8t0FX+cklls4L/vu87i8A2NgY/Ok/K
3690T9KSdZxIO6OYv25l8k0HsygockP4QhDUPForiNropyUUsbYER3yeYZUf2TYlpEagET75rRI1
2PBJSao5eRsqhbhT14V8Zv4HYxv9GdxzVHZKF86QtR9bEIsQnxZ0YTsovwVzaRWMTtUTedn5PZ8U
JZbkNq3zJUCq+n+TulivCxdBkTIsorpT7+a/+2M32u3M74kvXOoDi3emCYm9IuOFHwaGQgoMdPmt
lW8iLuKKqy/MccgXLz7JfJnxYz4JwhvY2IpupqxdlsttyuXfqS07tOCP47d4edKCH9D/W49aEMRU
/SgAFUdOIYbREO421ZjOopEfuA0eR5ygDSkQf6dGw03b3TGsVvxwnhKERefF5cUeV+Sxz1KI32WH
kcYc6zgntxT8eRDjhp6d2yWx0v/ysZzNgTgMeB7mbk10kpnB0b7h637z8iX46sfMXq0JFomI76v2
l8I646CEQatWvxmakVWdrcQ/uuVvFvBl0OfhYsbgPw+tuRiGwYgzsFjSw9pMFWJoKbvHZstD+7h4
bWH63Vkm2yzLSoks+9wPdCLqKeSvHGA6C9Q5djsKn2SOlauVuRIQyqOk0YG8tIW0Eic2zMUYCCIt
6lz12rd/usiO10p7wiIvGXidb3NLI+MwWhWAYMCUG+Mgm7APMJbbHOm77fowLz5zV/Rs/6VD4uZV
nvnxRteVagtXXCkiMD5W4InZgvq12Sj8hppvYJ7oott7UM4jff2ziOSUPdiu6nhrLpBhi6dzfLec
ot4eLfgPVkW8+xV2mWAN891ji+mc8QBINhSAPLouZJ8AyAGvO83NB6GnQM56MFpjlaYJS+4TFJ93
NTLyvmPInQyoZOajtGRhGlsgdnvEdXSPAUQ2BZTgameaBRs9LsPEh1Y43+J1uyRI6fXErGCJPg6U
9efqVgRobI3Fhgu1eItNuLOseysDprIlxIz79z8ySo+1XLmsZgKp0QFaX1Fhq0wP4t481WIgy/kj
/Z+FAPOZLJbUG8sEo0Vih91S2sql0GY4yORoVZ5zx3JHiffCeCr1tLhT4sQRlwbzY/y1xSUU/ZDN
XzUoPCRrTHxApvYqOFPT+qFZ+vi/UaAftQNDVQSBzxFA/LxopC5pJEVi2mrYlZ3oueUTx3EHOp82
b2LiDk6UPnxZH0zdPQBtr13TPjTgJfFL+FVLUvzqeOJDwko5RYaLmcGYxeVa2Gzsh3rNW1KMwvfE
c6IVV/+g5jTz/iHKpFcOWclEqqn40rAzHXQ1QNuzXzKAOicqI+KX32Irf2QVTl8178biX3+3kusr
eFOsv6836hr3DjTNf7qAkGrCk8lChd3V9iYcEOQZ7KRDykBXfpGU7Qk+8tzpU+r1cj8AQ4+w0CqA
lDlfONdv6Nk/fq/RAHmVhX0pd9fckbonJAg72zazCvO4Xn3kAZdp+2Nmc5UwjN+U3egb74FuPKGM
NdTRLPvjQwMoP9mg2dNVH5iC0QWcY3Dj2sYCg/ALXxG7HV03UFvKZ/AZKssA47IofJ+Pn2oO0oJ8
w4ylFe98xloVwyv9NESeeVPGuYr+KirBJ1ty3GkCRF2HW8tBsSz60/QeBMe4ifhzlJIMcG8FKV/z
BqXUDYpO/W5hogGEpE6s2Ti3NfXxki+jXlRWo6YVfhKkLHMH7SqCFx+c7XnrYfx9YP/DSwPcT83h
+k7Ciey0cMYNVyFtdbOG1LzIJM+5/rCq6X4w8nlT/2ExfY6kYObFismDI2oTpszqR7NiPCpD45P0
z5qRNXEDcdzbECsgK06+0jf0B4a6V5Yt2YlUklRR0IsD/51ucVvAX+yUG9X3PcyOsm05iBRlIQaY
jvd7EOa/cieRbu5dBACs/2C8EQfbzPznfYNV1mvXkXzSXC9q7KXPzzHOsug0GCgxikCMHeTXHDmX
lL24pW6pViuELSQW14IeZZxhh+28/ciZ8iJukv1vsh40gw0E4hMC/XtFUx2kW+gPrwrsT4brWrW5
imvcjRWjPCOdNe61DT8u+PvRBAdA3kGSjbHEHF/tgOfmW5EFLavF0osXZkwRbVsnEmpR1Si+ISbv
Zozo4j5GHr0uC7CyOrugIVncIAJa3AJY/vX08GlV6CxqJ6j5HbQLEpRF8XR2qKA2xhZwQMo9N0mi
2hKzfoahmkD0OjSTbJxfo7jJuODAYAbfFFb/G+5ieTbpdbqPQG/iDpl4XdBuq+J74suA0IQCxoV6
UNNdNPlwdxC0jxh/0mFkfX4poLdzkjipGkvLLWcoBhAuWUSH6ocifFwdnbwkdljh5BNvq6gHYQmO
K8nfdbpy4Eonr3+G28XxsESbTV9iSSuaWQq1imTZzbO+mqmRzOJ4GPUsgXttlFI1eQiFaKRCJvCF
T5BE5DEyHarpSPLseU4oTx1A7lmQT0WLQ9SCDRfGO19O4zSfERrpSJrO0U/4OA7EUmm47WI7aB6o
yjS4BhSJSyu0YJQKBr5dHOOJ77XAFA9bYOUROkWOtnQJ1bKYoPvTtFXkRKWzb4S8DZWysF/N375s
gsAWoSsWKLzIJ1qSBoo95UJi0moAplGlxIyw3il8rHPqc6GdqMGlTc4ZzhVFiQfep5BR0KN2l25v
L83ot/fSeYjClbRaEiVGD9YcKXTq+PYuAzHNNhv9SywOmGwHsEmMASLCYdb7uuYHqqJkYVpbyirq
YuYyBDQfOni3tDG9iRFiHImfYnygq/VjpSUSBaqH3QxZAnkzHkHf4OJmn+IsR1fqL+KwNu3f0gv0
19OlDizWlWlJ3e6fsHAvY3nPBGtNaXHX7oPtxyn8ifZMWSHnIYD/WyDPBLo82U38Z+rf8q0raLPn
gha0mKz5AGniZcghzxRzl4cs9Qh8BhtD4qPmeWujP8l9/i94T9r57T/xugHTa+xnoD4N/+sJjBB0
C2u1OIZTbKsp1UEsZtfcNrNZQuZKmI7zaSfkL2/Kytds6DAO4Jgxz7uP1AxpcDwOduZrqiCXu/ai
DnVCs6FQkKNo81nmYR5/jkX3Lq/onKY4EZguAqpAGLZnyGCkUIgmu1cAE722m7L1Vn0TZLPPVMCI
N3VmF3BW2mdpG89PK4XoX/dmQIsqQN6h7NF1VNAk8DaDr/AvzmN5xxiH1YXwbd48aP/n9QW3Exxu
ohad+9GfvHaHaNarQw+JdZQOvo/h5Py/O2sZ6ljUQKyyene+AlhFSuy82HHny8mG2Bs6gKBC0Rjh
3hdGnsrdCJOetyIxCfS5W22xEm3c71sw9ayszKSa69E+Fc9PTbyWvGw3ATi0H76drtI90UGZ/lMO
fpI14KeZxrDGAhOu9uGsz17i1mkNPhEZs6ul7EZVvqWOZsMM7kagdHCyeTwye5IMZVnmTq3Q8Xwe
4W9lMEwrY043Ne/PRNKes1kU/+ZIX9DrFtWqirH9dFEeBnuy4072kf6RmVr6SO/bo2HUso3ZQNHp
WnY6TTvUrJnoDK8ryAy8UcyOxHvfab0dN2bSkzyWHJ1xeY+kDyWgoCnNNJzH9t1o4dmN6AhC337g
jVIu8YNIa45p3DwLYeN1Fv+FSzw/hzYpZMcM3URadSuYVQkAKkomh8LZxX0D78pcjJlgndp6hehi
bDjKlV21uTrJiR5N
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
Jg7ZSB2xI/J/jQikm8Zlko862zAjpKBGuPSRLj2TaHEWC5rTzr3rFiYHZX6yv0DYk/Y584dxn1Aj
ZJ3fEMF2Eg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
J8XF87MjtG6MD92nYNEuYX3aIPS/zAQYepXrxQuouCoZ7DifIM+PcGRYhyHbT1c+x8wNqIyddvPX
H9E20LneyNoZup9aJc0KklSHkCBi4RFSlJYfEHGi7VuQ4DoNHay9ZZOx7KnkG5nTkuG8dZKhL494
1mvb9OIoIew9S5frQi8=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
FESqZcf5Kd2nw6uez2DBxPYJSBV8lpPPNkL9mii7n9rOA23QnwFT4gzsX2GnAKh0RRoHvqDgwQe2
oriJIgtSnO9GoEYt557lwN4pjAIARzzVKmQozG4a0ZADHcAuh9dE9U2pgm4IYqaA0WHemsJP3RdH
ZWLIA5hjsrEEni35ostJyYxky5xMLNN1/n6HMS0umCbRhs8srgz/a5uvWD7FFpEZ2a0utgDi9MEX
Ot7P9GN3AM5Ug4guXH512IazlVntMqLUCdCGexOO2NqFhGpAvwGxJCtx5XjHjmGW+9m1bqRxt0uC
W0qg1W0dWBjrERQ1cn2SGOV3FZ9QqHCbH1eBSw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
sBWw2a997MC11UDckC6eUhzOMD6OyRi9hIrFSmKM1LtA+EoEe9hBOU+xWnNJxZwh5q/2lTaLVnRD
SOXNd1eh6E6oJtNfyy/eD/u9oSEqrtEAnNkzfHKZvGwMHsKFUk23bSYe/H7pvyiU6gwLB/zQXKRM
aU3uU6qaXWsFaGyQrek=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
I+E3SG6eIVl+eQQNtE5uT75GDZk2w8MwukclTFsLuB0JtjwI9/9l+wqqevSEAZVNako39sma+Yy+
6sWVRLVPo7PjKtoO7mmywH+p7yQSorsf+a3ZiNjDaYRK+f9GNaE4daxPW5KbJ1GJwaVjbrTJXjms
6KviB77YrfOEwKiKJnAPEYDYIIKzPfz0pkPKCCTKaUXpj+fFxyjC7bycPwfKU244d5RTVzX4xHcW
KE2Pbl2/gBhqu0EO5W1xcfaXIFlrwR2GLFrc0Upm7pO12jbH3NSKac9EirjKD5ICy3GjrAPQM9pC
bmcrUujXKJAoYdm46Fb/QQhF+yxNF515651OtA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13008)
`protect data_block
iXdONubG+SYUpFk1+3xjbTmoWUUth5YI3Atb1aEXZ+saXE5+BGO3fPH5sUZBPpBGvC0XNFvrYkWj
mKjKwY2xZcfJ/srndO8S7QOgA1cW3PG5z/BUIxX97bocLtxDa3aP0B0gUaWXB16YHYdYTkHrQeeT
kByzxROgmclqf0h4i+dNw17ZHgg4lSONS85uKTmrmSH+AeVrAMTnAeRVAxyAfN5NPuWFW82kE644
IywqVXyFo+6EjcTaT9MuzpUSuPIiC1uoPJBymXXqJqXLPFIf66+E0NgglyW1yofbtINgNhR1sgx9
DeAt8JD9ezW0dwIbuBVdM7WPULLxlhRiEjVxJrWWqEe7iSi5KOvb5fzvI83hsOJKOziBELmUOamM
/T8ir8zwHa8BgpammyJqhRLzlVnk0jc0ui0l2oBOLEZatZDKIkibZ103V0P30wEv3kgy6CHZSlsx
o+2FQ+rWnn+NLza2SdRplpZXZVeaSlrNxSpEgYaaVJ1hfYU4shpw1gY2+WgUCqWSpnJ07oVnlkGj
XgvkoW7LarBgf5DSufA7OrUOvhEovDc22xsKo/6q9ikE/FrAsfq/b6I1GPuHTq4tNmNgFLJLqW0b
o15QkRHGCFSFVYp01JsJfRhVklzXE3+toKZwdGB3lL7SLiSo1jny3g5F6camzx2bFmrQu5Czeo5C
/YTWlRYi0Y0z4kUwtLuCniSOj5fXjvS+rZqv0fMbSpKDz3yNPptEql6mPHK324bJZULNhyCzaxZu
6mfclZBjFvrJ40zJfG+hWRGPBj7lEQwK9mvMkOaLF3QzB85I/PtNnp79JEkmMsrgHxSoHMgJJoNG
GeQSVZp39h6ji6XfgW1Z402TkKgSqu9DZ/p/XrxV+T9xgzoHNhQQve11khlld5aZoR2Fz0dS6DWY
htxdwg3F3n0HldhSiTENVbQCnSgvpe16MCIUhBeebBdANdreKwenIpNtmV7T3c/f+GPQpaMe0uyD
CAdVU3O6rVoXt3dusGugSMUIauBbyvk9b1/gmJUdGw420PMi+IvocYBxDF0DyTxNo84nnK+qbJ94
1vTQU0XHzhNk+/bfIO9wIOTa/xR7TnIbwelmHQ2DvCac7jth9H9aFIFV77VLdx+lJOWqki9wagmw
xd6Y0RDu6Fnko3AlZAnPA8AV/fBoS/o9Mbb9XenXcb0Gxv3pWX0F5FX3/IYEv+LqJ0x1dnqXRtJd
f3XkTKRhmAv1RHZN4Ijf/26mX+vAAf+WHJboPQj6tVKWcjoiLGqDoK25y5/n695WQznpJm0jhAyt
n3ga+4uHldOnqkP3JRRSm/A4D1m6LtnYsvrEfBKMXTTJyBxZl5SwwWtzjpQQfAmwUjmxt2oRGiwx
WQNGqkz+TTiFQ5ezlAWncaJscI0KVffI14NwBnVogLcYtDZjOXRpYxrr1uPSV4WFyXUYK4w2H515
u1OVDSE7ERA09Y3+88cM1NHWW0nuzw97Ca/B2ksxC+9UGpBq92Z62ZAfYE55Aa4zCYLfmwGVRBoE
feQhSr3J5McYr/O7r8Ns83MgdkOnLTw3Yu6yAGgxoNDOPqr31lpfWEQ6EBJJ8ymfrpl6w2iI0Pou
3Yt8LzN0Xb5Dn9kcNAAqwxEZncjIHsHGjZgKYuGELLEqeJFypgffVVzo69kF06N/3OGu0IsB+NZF
oNQ9CNZnL8ZD6tsKknOLbWTeUN78pkwcJSqYtXBgkyD9UOx8BGFgrNj4k4z+thMS4m1D1R1APj1T
J88qHzUW5a/i6Y/y1jxvgWiDQZCX0O/oRG76lZxPz4TlYHjWusiXb9KDRuPVTj1KXsjEKkQnt27m
ekgt9Y85Eg+SKoLC8QlLzPn+Jcm3krZYv0Wv7jyISxNzhIMEnrX5lGwQHMrLaX5IYgiOb6LFz6IK
ITY2vvm+uKEKRxh+aN9SdKlZF1F3I/lQJIoicGjJsI0/TY/1NH23//QzdaqgGMK9f+g4fHgMnvke
VnsKr37PDikQLBnz8VK4rdoHartXGc4nB9HSQbY05Q0EXZTEG7wXnpOXD9cG0r2pKjjTEwKlW1WK
XwBxuuNvLZY7vEMV7Iv7VPRzudJFyIsVj91zKTZ0kvtHkYK9/Jhpakiy4ooYnNPj/I9D5vYH11kY
K03oqu2tM2sNKJHOzDo12gfCZxIZYp/3Mv7bMTL6UPp1Kc41QS5EkOliFb/hBIpI598iZnnxZiFo
nswi53iePFr4IhvL4XCufFkfN3Kjf1ozXowHvE9PaNfeJyKSK3TclZgUUJB7DxEcXSrXqocyxOmJ
W0rkdt8E4XvSQ9RXnGw08moTmC4Ay/Qm1Hk4VROcz2C5M/BEbD/z3r3rCD6G+I39slabSKb3EPL3
yrBJHvH+XBU/Og2/F6Y4BGtbmBqc+F5Cbezzs97Hchh3W3YUs4BFHq2a++VcEFyHwTHgMli9VaOY
w2XwIS59gPOO1G3+YudsX73xWFwLxSGEqElr5GNcKSybx/KUKP5fuA1KtcxvUurdTXSeBDqf/vsb
KDBcshsTTQzLHqcmaC8u4PSTzQ4l7S73EUXoM9h59/9naeorj1kALVcSetLAa4LyKoKpxpfrlObn
rL7OH4Hnjr6Xt3C5YcPxh2yGykFBndcoUZYxzNUeLBqBjfYju9soiqCkwcqCDBojqq/Z+t605AzQ
PlXjKhmrcz6ds7eYwO1u4KMZFAC4HXvTNL25zDJHkxcTZzcax8gptFOxcmyBZ9nafcZZ/+cu8svY
5OGfVdRDFOlq4Y2nRCAxb5++FTVg0oNkMP67MsAoGCTGfqFHS0mrScicIetb/lC+TbNO+Wx8Nuvo
jOhSu7tAZH4FwoFNudmSrlrGXOVPDeSb95Wvl1EHIVJ/Bt+g8jHN7L3EuP3iYbeXKJNzmhruepU5
/9pGEYnfaVZv1EKuQD0tsS2tShyClZNZ02zxc1YKjbJF/98+1kndtLO0JqmeBEH4rtJUuqe7mh2q
3HpCmfwguA144Kp23ARkOQKAzTh6YE6taVcJGIZlE51FSZyJS2qaXvOUgyHmpQhhl+Qxu5eRp4CR
QgzCw2U8MoWaz4w04G4jBnldDEQkY9jZIq+iS9RwoHGYNmHbhjhRvjxbtqzpMvHb/qKjvHeLin6o
DWEUotoR4Vrbzse2tpKJagIlmH0mstt5BRRPIFMWwHml2VAoln6STdwmzqHItJ6M1wiy2xuBiMOF
jUrBgmufBslF3pAgUBsF9WfKVFnAL01FY8FVdk+WqWK8dUuwLxslJ21FehhfnaDHm/mGR+l/ZIvC
5OmSQaWH27vJT9tlaf+k50s5SF5h9+2C39bKKqW3vSiy3QerLtGmSi6jOHgLfeJPXps+f10PwsjL
fu5qe3IpeezwjDGOXOD8p2CFbqt44kw+23UtDbUfSrJ6wAs7MWNTdUpltMm4hBdW6EEu4Azr8eaE
rOo76O0rP+ct2UXu2buMDccPuOXRwDdptZvw8V6N/qk6ER21uotJk6xKN7fR/Qy19SZYyc35NF92
oMxdadmKfm9fstBbj1aQUG39cPtIBhIIGxUtI112wstvH6fdPb3Gc/7kf2XsGSSawaj3yusoei/d
aYxfLFPeRcORl1oie2nUPwgrzeGcVBicSBcOTGut38nPCyDBKgPPlqUCYDAlWL6e/O/F+eo3HJ8+
Pv8/1ZmfjG24OpCOUChEp76UToTNv66MkIZ7mi/n1fRYk0B/bs7rZytYIgOZEqlLQlqcZ+uKP7pF
gp8kYzRYgBlskLTPWHXesRRfAklL7mcfyrb+kdJwBKowSRhzpbaokwK1C7zDb1obTNbfnr2IZuMC
4Jkve0+vsuZsZDLKWVrVL4gtmEcdpo9dQ9QUnMKbIjmaUtwMQgSCsRzJJwYy9GWDRS4tPB7V/uMd
WkiXyEPITTQxDOQV5famzC1g6uwZeGRNXKKl6Xf3srI8MeJDEr24ifgrZI5RhWlgne7gfOOOHcSb
cfj5uEDoV9nUeqKBPNQCGDJKzKNK3U4UWIUQDwxcby0iUIXu7mcRrPVQ+i8ZSIkNv7uQ63qD8FJ0
0PnuAovE/oecSIx6Us1avEcX7YzKkqjLUWgs2LZOJPMD6dk8MDoMo7ysX5Sl6Tl9JF14RntPqd5i
2mOS72ZPwr9U6SOt4tavm4B/XYOdmY3LdjECmA+G+O9xhvQeiUbpMmCIQGaQ+JLdC43Nu51CMH+m
bsHsVrUO8pxdQqrRm5yGNtBFQJqdg7cWayjf2D658JcIp73SPJd2nsAV1KXVI2I2++AhSCex0spz
H0+4Xjq4I6wcBpiB9ES5IPwBRuCAU+KNF7cxUJfb9AH4MtrABYZp7EUgpGF3kkDgbIMWWy5kI8iQ
gwoif6mSiXdAR43lYDI8ydMmi1P+QqvyE1uwf57rwrXcT9XTolTEyHeathKbcF9H2e/NusWFssxn
ZAsHucSrjOtuhevUZv1j+NFO/tsWJEgQUWwHFUSHl0tSZJr21Jtv04QAXDIe9uKviuEi8M1Zye2q
VIB12DuPRPB5Y5ZTt6VJEynbZczesS1k6ndss5lIqg4YxeC3iPwEQtab/YwbJyKTlDFjJ05Z3I0a
5V+JL20SaQEidsS8+tML5OVYqOF+X5YAnPAd46ujVVHrWIUqpcTvJny9iLXWMp2puwu15oYG/J87
uOBUIg52PONeRo/2ZROHRSCXUnPQQFvIxzzNph+Jqt5ZIXMTZJMFegj5FhwuthtnL7o7o/k8Lyey
YgY+A6AeZeXkPNrO3/jyNDHcx8ngg7j4n4zOIMOsYL1Eq5h2QYgfEDCRImFX+a8vMUUFhFzlUq8Q
+YnZ/g5GghVy02e84jV91RSbdXodjfxIQtHYXE6WajRfQd9Xmc3BRk+8Uk+VlXiEv+gFdtE1jMEl
Y4J6vlUOaVEh0nfexf06/T7jVeseoM1c9nznKqaRyS5cnfLG1Xc/l4idfhct0jnfD4xyo6ztKKc7
ZoWW//Ob3qeNG3mBXNZQUJMmhE2P89DViTozT+GQTzA785Y4apmPojF8ZI66ombhB0Bej2RInX0L
Wdog3njTuUmLQllhN8s0QQIfhHteB+eIH8vSm4vihPzrjwPyRL84uuW5TibDb8uA3j2aXmJ8sARQ
ijh3bM9ltfHOSh+gdfA2CwTtjpCuJPY18zeVTbwrjKjXjO5I50Svt+1f62XsFYJ7w0IzUqVuGGKi
IQIkrQLlKPh5bBbBhVsC9dBjmkkRCGBuawHh0VgUNV1IjwtHW05jlfEyrTJWjUlntujZrtGWGc9z
VRjyV83unGC9AEscKVLm7hTcgw1Uejk7JhTYsWrmnXD/2yniLpA31qEtSZdL4A+bEwKAKbWiQxsG
COwzFFI8dfZ3qGevBY8aA47DZ5uUd0z1t0IeSunBnsNh1mnMj3oOS89PX0dRhciuDE7dbg8+0tBW
9EmHn3PKRmNL1ipXvHIIfYuYc5Od3somla8JnQyl6jBAle2+RUahuA5yMVZLiJ923n8qhGYa7t/S
dKPTiknun9P6w19cPSXpI4v02Mjg5ALkLsMe+4Y4TqElQ07w7hiHGsu7EYCQzpVovud5f/db+g1b
nI9MEUV4/hYX4rVfPm8CDe4KkNvnGMro1E0JXv57X0O0escjc2QvaFP1SNc9KVhyZLJ3lYvDXd3x
YVU8eDke68BRejyCkl7EsUFiyPvyFYF6Vb4XpEWRIiW+qCj2eTK3JY3aS5ubeehk/Df3D3xYofdw
Ps9O02/Xns/UUZj/VWl3GeoM5uK1ckObVDlRwnQlSIa8X6EKAtGbeEyKDtZ/wF9Cd9+6zByRakKG
yAZ0kiS0dH8wvu9JtejXD0Yu3vjX6UgRJprZ9GYUKRN+1KYS/OlJ7wFri824lniD6LCqZb7L0BdN
l4AQ6kM4NrXLDT427YeMNGPoE6FY5QyFuqPLdFUJ1X71o6q6ATkecmV00kaGAk2x2TwwVpfHHpTj
Kab4Xhl93ic752GhbFNJw6BBquu6DFjJEenEJKGIs/Qq5lM1W9MQ+OoHd/On8K+ThjECiWzVBpbX
19ZnKrWbyfTNu+idotUkQRkHnMZfO1oe+p4eeCIPk2f4sRaxVoz4jtahxDdZzrqbgs2lXrQ+h92Z
MJ4JqtyCA2LWlrYOiTgfV6jeJnOT7p8EqA1r5gNMMf73uzJqRhTbLYdhoqY1V9brJqIelEZGwlIV
eObr7vF2SmXqVv+D2+vRjpT9sANMCBFzg5JJXtAYiHbLFJ8WXPAhwsZkuoP/a4pQreq3LHnioRRA
NlirCIpTHWBjIlScqQefBKKuvJKIAZwO+0G5Wa9FG/eQwqM92Ugne64Czm5BwKe1nXlS4MqmO1um
I0b60Gb9nWnTtKFce6YOmmSwUB/FFOT+muekdItDqFC6AtF+AvtUQ+LxE6jEogPrV975od5PONSK
1XCKPqiO75OrG0GvVL4W+lvNsSWCkx5ezq+J+I4ba63UyxL0UJ7ASgXjyUprZVizgkZujeNC59rB
YTyaZRMVtLjriqdEgpHVnA/Mp3OaA/WJJuD4XtLIIkizKKnJpII+saXW9Tzz69ET5zQhZ2lTxjF5
bAPXtnHSYBcyt7s1Junm0aBhPpsstcrQt7A4CDyX1wRNxsrG6K64S70LNtZkzN7p/toH2QOd1Ntn
vk428QrP2w/+RDHCWuPAXKJk1GKTaYFb9o2RlxWMOf782ar2knfS5VHhd59BblwWY0nW2IA61OCo
4OxPCxRPE0HUO5Iq4wg+HMth/Anm8AdPmfHbIYvwHtItB+bqDht1Hr5pQkOydqpCJvnPvYtauzq9
rTq3A3t+nYHY1Q9lwG9WfMcGaK4de8jHn9WrrkEwVnnLj21jZlnV0ZxET7ZlY98c02e1rwVnrWr+
Je5t8HKCBYOR7JCv6DaVwvNIAoqVP51AsGin6sd9h+HhA6aVypIaWjf9tyloV/NzduLhvfjhcV66
WNNxNcgfaDRoCt8Ryd99nsYqwm1v7Tq4EtN0gtX+WoGxn4zzDoF8M3R+yb9b+7YNchfY5n5bXQFn
MCE3vBHAKjWg5uk1qBr75cAu1Qca7g5K92MfGhc+jnnTTux0rvAu8+tJ6X+Edf5DHKiflbQgiG9J
7CTAsB9Q7zkjtJcl7OcPuHTk/3LAHhWdPeIm1LX4NVzF/kt1kI5Vptuu12DpHErhezSs6YWCLAr9
6A5AUIXq46nPZDI79z+GCMgY6Do/KG9RHrttH+qyncHGFhJFIJwAGmHFyM4TXAc56a/ioJI75zBa
csW6uOhgYQo1rVjjGg0JOHgoL2hiSo1cgO8FbaYeABImPoC6h+UmyWIrHPEva8RCDqBIIxYacjF3
Sablky4HqOOqTH3Po3i1W4hePeUWVfmiHqGg+rRQvXt3I5KcOa9BHeP8PLH8WbZnHhybI90AJW4B
ghGrLgpA0BouIjoGXWb28lm9b1cn52FbIvymS/YVDidtBow6phD7ORIC7RN96opz0bgfDpBsFfKk
C1g5JN/wmgOIQ0XanlsorghXFG/y5P9M6hRDR47vsyrhrmea9/a7kEhdCuFyvPL842LMx+nKI3eS
FvJtjqUdksjTtLmVF8b8u6sqwU6UFtHtD9r3ZhLPKmoXtg9KfoRBC245DQs/EvRySHvQuseOcjXx
5RkzTTZ3jjy69kCHaFf8TsIzpmT1k2o6SeItN2z/XLhHF+cOKcMNTrOPKzOndIfCrhVvXL1vUIfY
opdi/RQbj0WYsFBlZxN22CeeLsqS/sFkzosL0tk/QrsDCAW2e5lDVZfaROYbFV2DVaBtCaPsukxr
ii6dJlm6iBgbH592u+f2mI9ze3K3bpsNH3CfLCIYDDI55iw6Qwnxg8cyeNwWyMIdLanykfH7Ju8c
ZcGGHpV0gE7uf5qc3HOBJHrSdvYc359vywTxDuP9P+SJDyx+t60gzygUEutg3fdY29j2wgp2D8A/
gRAG1SnHdPc55yCIzkndYxPE3e9z/tEfzN9bpWTkjECzzAYAeBBClkKk4paB5YWIjvLEVqoh0jfA
ZVK4BErzQihjWblDamZIenulFel5DULaJy+tH7Htt7XS99+kxeShV3OxFaxZmv2wZlozcdBjCWZ+
ibrVwA2Fw4qpfd2/mR9C8rkmZHFEyhlqgOObFsCbVRVhAPifX+s1OAHQnzvqqri2oe0KqyF8nWeY
YkcYb/hkSqPmV/mUoM9CDDcgJQ+MssByY5UZxPuSg35Rlo8SrIeat1xZbZ1y4R/59kJonl4hERMX
KzK/D2HsaS6LuWMCBBAk190mDb1DELlboatAk2U+ynZWeDcMUgeu7V2MDcR+56IG1e6MK9vMw5p5
kyb4IC0NudHIppagDkhVyqyMLYHhl4fbHjw3zJQwP5DmLffEb5u1TgBzbzxhqvOlYpBCjrIXvzo5
JSFcaTA+aXCzM3WWjZeX0dSP3MZV5gcz4e6tELgJxNQhelnifyxFrqU+OJYBo8oJUKU4sCKPafmH
2Dufn9IKryoxUA59p75/NZadSANaqUvLXoqQoRVrbKBRrK9TINJPx//uJsJ6S7btepIbmQmJw7Ui
lEkn2HbtLf7cwgdXyCjgKBL9z+onHs1P8Q78w6U33GSl3kyvbK8KJhTDTcEvB3bHQCd4qeuM4ahE
gk8UNAIAZbbTnza8Y8OhN+gGthKNYe1/+TmfuVD5AB9HbsIB8bazOCqKyifB+eGZVQtn6uB7ShIW
OdpMNUZuhaxwTq469qaRr8EjNS2xE06TFRrauI9CRpMBCBZNSFyTIssidoQWA5JVHGO6eqyXwfgB
vB2BxeV7SQGitHtabgdw08LzDXd6ctJ1tKT2OCht/xesY4Od6hO3ra+xvEGINCjT8XK1s9Q4P4u7
R0GKZ7oa3h3BylbAaJq5fKMjRqLGkXFvjWMTc6rhESpWck6m0TlmfdsXflsCxYWLEibvVDaevwsT
E+uA1UOEjCr+SWq0pClD4fxV1IqCSIwD/hgVnlpu03nhBk9PDfmrDaSeHLKm/uh4y4ogBCKQtQT1
JmW0IgNIaA13zSdQN6wD6dryxMF48Cc/THO3QtA3vl5svNKVWk+mEYu2tNApzArCa+Ifl+x58cC9
9RTOIl2fc9Gy38ArM6S39s+PeEh96xUGVCbAueyKhiO75V2yVROYvgGkC6Qi/KAqaEirBS922Zru
Ye+TY6Q4phjpf/CHGsK0WpRIwokqgkhZ14OC//k+ax0V3DhAJqQ/TcPI2ooG2EpPNdNPYrcXwXRp
9ck4cTWqITnoGg4hzs6/cxrjxIE0OhNYgLKht8zL35OZrJfHJ+KEVNCyOw/JMRpAsB7J4/54DcTW
FsvTSEABYu0I5LqKvs/BLx2tmmXjJqpjTFLA3FqNOPrrfhGkaRxQtAytJKyZibGWAgx1mzNrsrIN
+C2npOErzVY4oGBuXXV9X0qmwkQ/aU7UIyKQa90gmpax3j16L7/R/v9Do0W88WlGrCKZwOiEWfce
kh2fzKBoB+AJHxikJOg6488LLmaxBrPcA4O77GNwoOgWKufHrGUc+MJpYZhzJJ1I4O0l026xoXXo
LfGceXZT/vdoovMcrGf91X099uQQsDy8jqLLziX9f+6qIZUHx47hD4ECXJXV6QyY2lQ4h+gJiOzW
hP1yGVP5PD9jRurrtxcMEuYwQsmIPutHpbt4inFagIVxVX9BbPqyLsiSsfmKkGK5Kui7tWDDHIA0
eBmaW9Xu5hOBy1+qLvCOIPX18643fQWKajUy9kWmB+s9itfVOFuKKshtG/SnRpe5Wetoztp+kuxH
OHaxb4zGcDpebbDjrU55ej4pFpJgg38H7ljkMiGkkLGAn+TwllHeojnqM2mghE1tPG8vjPHD+CMY
uj4exjB1GU1JGByWyms9F0oRdvKliwlIQ05hpPAyMEIoiHHg9hkaOoKrQ+U5vQVga9ofIcH0BZ2L
TEFBqYxtRkqi4yYYMh5zLQ+fJEGSVs0ajiLIwoH1KKmaF1eErvEW86s3d4unJxkpkb2QxBqkebLv
JJIQglskZ6GmqiO9cPpVueo8cyP0ZXXzO1gdxrpLVKx+QPyPIwzRP/x/j6EEgh/rsVZSK81enbkK
HThbYw08GTi/RjVybS7QcsMrMB9FbuzEEAyWs5XH7NlXRTzjwB+huO/s4/BtGuaYwfvD1cXk/UWd
nqYfKzMwtaat+LQjmbPXAHvLdvRbtvSLJLWZSxVURGl8Ez0ZuIyvn35lFNZqh6I1QwAjFQ8WDl7S
9ZuT3xlLkSzxUZOUfC8QdaYV+oklrWZdkKm54M9bfeNQfeRBvylbzdEuIbgkquF02UOH9XJUquuS
Sw0qNuWzAEAK4rLchd4NfuCGNl0J+TSytnoQy/XzF5H8qSc2SQuA18fc0o9Jl0A+dm/ZfdbfMPXU
XLz5bFi3TQ3Jlc25v8IJaoN744m0G+vpEdMPPYrqHz4sXSbIDKbthpOcBfqeTkf+lAq7OG2e0MUm
XWTkWs7LMG8gLWzgi/QEryCMMmbub89tfonU2WLEzS8DyNBeXNj60RV1Xc+d0YWUXJawbOTH9xSD
sg3FK1palRgTIyTAIZm92pZlZPYnu7Roff/MBsVfIbFL+lryo+IP2H6+RyijU7aNlpC5ckqeJTOa
Lah7+s9892HqcXgQ2r3auRNlgI8Sk937dlmT68UjZdWJpi/HLmrCNTVCb+vmctVvQppEusxvG0Jy
kpI1bkdgFQnYIPzTWTODGyjCnghdoRX6ZmfSmculY9PnrF5vJGCSgOpDbZIy++PoYNN/ca9pwb+h
TXSnO9khtCRrt25rryyYrr9M+bUWr6OIr3ud8EaDfMSVCzGdNDBC/iJPfnXYTvdTC7/uWz9v1woz
pGV+m8tzkZjzBHRhDO4CeGWSR3/5H4K+KIHojAT6sCVM1j1wAXZfa0bBXCAiP/TStnZ/UputQgoS
ESPZIVRO4tMkHjNqhPLr0XwO8rmlZK4ejmOWlsYJelRZ5iKeJAKOfD6aTOhrR6Gt1rmz1r5Oe+86
JZqmDk25bLMoZZXMeFrjp81q+KwjxgnVSThF6n87/Z8Br+h7sRZZcjWKBi6UhB7e/XTroPxTNudc
ypLjHedZkWxBnpyAy7HpSv+YmOi7nVDh8opsPlwmMcnyRo87+NKEbI79LVlM/l0iO6Fcfbbm28IL
nQbzcjckRBPNb6ERDo6fOPb+NfdVhDlHNy2QeNc72nI3H+pKanVLjstwurg883OZymM6m9bYDLeX
vsRwJernuWDwDXa7KqyJHa/B/eqqMJR/1CFDdfQzfPr2GRIkx8E23sCVgfEYC8UpQUMMAdpg1nAR
ykbIzOa9QJ9c1RGx/hz0fQuUduOb/a5ltvxQRTySNojTlAdncANN7ewSXNJs2Lpp9S3d4j82cMbt
1o2k9pl3ngSxgOOp0fm1HfKjaX9kRMyDbTq7WsAGxwjV/c9nCtmsWxIVGccFSpaNqMYiusvV/0es
r1/q4Fs46kQDJWoi1uyjoDOxxhok+CLmhPVDTlI0ZZr/Y6cwnMuuhks14z/R/YocI8AkGVW+HH98
VsLZNoQIFlcN/SgbPdnaB0OsGHWOsvLUjeSVTFgi7LhtyP2x4scEDCFLfnlspPF3GjbefjIiNEov
rReMj8XKZIexeb9IQeclWRSwXowB0rP1imG+jlL+D9zOv1O8cOhqhRloK62IBi/Wyv9AkmX7EBeR
Z/8wjNay/o4TW/8RsdNOT+8ok/J9vIn5ggctes7WCP/nFkP2WAM1nABVzqyPW26FTGgOCSJ979Fk
x0toxJdlkxb3v0+7lyz1sDv23dt2MlPHqAws1fLdkuovJoKkZ1dlR2NcYCZZPhXjWgvzzwJHlOsB
8gL1IRBL+zYIREP6X3E1poTEEjOq5+tVhVW+WfQBvn6K6xJfsD64LSuwqrVkS1mkzj1TvHxBgRLh
IitT/JuCh0BbwOpt8MsdRQYSA2wJfEG5LoyQsaPpqn2B+WY+1icpU894ty+gRfAAeoIMfCrYMTC1
QY2UMBEuTUb73zaWP6Q7x62Y1YNaD9XESB/ZqWcKT5vIILi9B7TVW0E85E8Hv31PLvY892k8E4LH
huoZ7k7QPkNFdr0xNSSCxH4kgJAXcKrDZ4VTmOLFbUORZFvFEOI3nIV1LRkpvMdO56DWOh4JH78y
YGL9L9QZzbHeQ6rTMNo9CVCa2A1E4zR1SamoBYYtCyzgYKWSwI14selgW7p7Psh5CPcPlQga6rx7
VW4VzokHR07Iq4NniBqqYUCd+RzWwmALqHgpl2U+DVn+4ESKLisI20E0cY5g/ZVY6kMwIQuqWbA5
m+vnwg6f/GJp9gaLfGgh2zKsfvBeHq0XmFw6IQsZst3amWm49qs4uc0dZmuBZkmKK9aGbDnJolL+
+HL1kGBLZUO0+fJin7bYrRHIFYYoZbVYSzy4yX9TgenFG6zYnHS/l16hWZqqfSRzFjgyVwVKF/9E
MwnqImGOVyQ7J+n7uU+AAdP4VR2x3Il35Dhkh6+alwEtB1s/cSs3aiHQ1RKw82qd7N1hEs9lBkW3
BxeVyN8cfAPsmg5mWb1ljOoSb7iX64/9fwuvq13w+piUMxoRXj4bYRn11EPIg3sNkwKXyMx2KJ/J
kuzsGL9ExkUGmzH1Y9CQj2N4Oyx9zjq71VmAzX00Ej6+bzJ2aklj9tv+DnxVIyeoaGvH+3XvFMRK
X/BWsc7+QJfE3eyG9N+YkeZonu+cU3qYTNL+Bw8yamX5zgP4v0k7wXJvdZzCytHB4yLj/F0rW9jJ
arbRSAbHAjCJ6BD4z4AkWvZiZR4WnQ/KOmkMoQrdHRkVRI1QJSXEc55t5uJKmu/GhhfGWPg85J1e
lJ1J3CCFS6e9fG26WV6mYdIEsdKlIKbQjD14w8Oy3KHVczWo9VvKAH12y+g0tdLD+Ag3uOOls7iv
LQy5AizOtPdU7HV1W4NNyWMET14SXbod/LE65NMlIM6jGc8ER0lIKnUfptsVKDF02RLR1yNhn/d7
fmlnhLCRMM51bqDQvlLiMocGsFJCzKw7HBLsASom6Nd/fgRF8xvbwDH7OUsncfeuJiC7AZDAdViq
rC/oB6QwI8TA6CXGAhiI8N/xzptIZ+klEWze4ENMstSH6LlbbIKf56od4VvTTkX85X/P0xDc3Fub
daDexnB067MRkmm/eupSXI9D3OLHr2rPzD9QvGe9/w9P/iiD5p7V3K5qgVcejFTdeYoPYsNJ5bwK
HoN2SRwb6s9WEHPBNlJi+Rll4Xc4vxclzF0plhYWBZVMtDEyeGRNekfz5VariivlbvA3ZpLA2Yzj
lkjD3EIraEnwqDQqT6bBMTHD5sPvIaRuokoYdEqiaL75ZEY0ZDhy4jKACuS7prqhn60SoXMKW1xe
LsJsUCgdgKkCSe3fSGkAZdo/bK7crQ+mqvsbtjgE4CNOxy2T2ZpSnJBhTcVPvhn8W1GB+EjrHIfa
RS/P+lvWENV1PWi85odvoFPP2VWxqeNQ2lLyii9zzMmYNbMhJjF087p6IDPyNq8HwAMNgs+l6JDC
tbOGYt9kMB+czH7rbWe3xWp1yavknXF41UVkrYMYKse5LVvQtHlZJdg0gtfoaR0vCSP7s/6oeFjP
6BIJ/FSAyeLSP4ObMAo1i2124f97gbP+7pMTNSLNrLv4aZD9XOmwvtdixrMAQRZscsyTgF2h11Ue
Tzih4cjJl4bqW9gJ71sWHEdHYruSGcCbrCe2KbJA+9hTSDsJtfdXAi7m3bjL+OUQ8m8Xf9Cfss3A
NWEuU8lRIeO5VCOdZKgO4R2RB45lJ7NyUL/RafKZozgN/i8t0FX+cklls4L/vu87i8A2NgY/Ok/K
3690T9KSdZxIO6OYv25l8k0HsygockP4QhDUPForiNropyUUsbYER3yeYZUf2TYlpEagET75rRI1
2PBJSao5eRsqhbhT14V8Zv4HYxv9GdxzVHZKF86QtR9bEIsQnxZ0YTsovwVzaRWMTtUTedn5PZ8U
JZbkNq3zJUCq+n+TulivCxdBkTIsorpT7+a/+2M32u3M74kvXOoDi3emCYm9IuOFHwaGQgoMdPmt
lW8iLuKKqy/MccgXLz7JfJnxYz4JwhvY2IpupqxdlsttyuXfqS07tOCP47d4edKCH9D/W49aEMRU
/SgAFUdOIYbREO421ZjOopEfuA0eR5ygDSkQf6dGw03b3TGsVvxwnhKERefF5cUeV+Sxz1KI32WH
kcYc6zgntxT8eRDjhp6d2yWx0v/ysZzNgTgMeB7mbk10kpnB0b7h637z8iX46sfMXq0JFomI76v2
l8I646CEQatWvxmakVWdrcQ/uuVvFvBl0OfhYsbgPw+tuRiGwYgzsFjSw9pMFWJoKbvHZstD+7h4
bWH63Vkm2yzLSoks+9wPdCLqKeSvHGA6C9Q5djsKn2SOlauVuRIQyqOk0YG8tIW0Eic2zMUYCCIt
6lz12rd/usiO10p7wiIvGXidb3NLI+MwWhWAYMCUG+Mgm7APMJbbHOm77fowLz5zV/Rs/6VD4uZV
nvnxRteVagtXXCkiMD5W4InZgvq12Sj8hppvYJ7oott7UM4jff2ziOSUPdiu6nhrLpBhi6dzfLec
ot4eLfgPVkW8+xV2mWAN891ji+mc8QBINhSAPLouZJ8AyAGvO83NB6GnQM56MFpjlaYJS+4TFJ93
NTLyvmPInQyoZOajtGRhGlsgdnvEdXSPAUQ2BZTgameaBRs9LsPEh1Y43+J1uyRI6fXErGCJPg6U
9efqVgRobI3Fhgu1eItNuLOseysDprIlxIz79z8ySo+1XLmsZgKp0QFaX1Fhq0wP4t481WIgy/kj
/Z+FAPOZLJbUG8sEo0Vih91S2sql0GY4yORoVZ5zx3JHiffCeCr1tLhT4sQRlwbzY/y1xSUU/ZDN
XzUoPCRrTHxApvYqOFPT+qFZ+vi/UaAftQNDVQSBzxFA/LxopC5pJEVi2mrYlZ3oueUTx3EHOp82
b2LiDk6UPnxZH0zdPQBtr13TPjTgJfFL+FVLUvzqeOJDwko5RYaLmcGYxeVa2Gzsh3rNW1KMwvfE
c6IVV/+g5jTz/iHKpFcOWclEqqn40rAzHXQ1QNuzXzKAOicqI+KX32Irf2QVTl8178biX3+3kusr
eFOsv6836hr3DjTNf7qAkGrCk8lChd3V9iYcEOQZ7KRDykBXfpGU7Qk+8tzpU+r1cj8AQ4+w0CqA
lDlfONdv6Nk/fq/RAHmVhX0pd9fckbonJAg72zazCvO4Xn3kAZdp+2Nmc5UwjN+U3egb74FuPKGM
NdTRLPvjQwMoP9mg2dNVH5iC0QWcY3Dj2sYCg/ALXxG7HV03UFvKZ/AZKssA47IofJ+Pn2oO0oJ8
w4ylFe98xloVwyv9NESeeVPGuYr+KirBJ1ty3GkCRF2HW8tBsSz60/QeBMe4ifhzlJIMcG8FKV/z
BqXUDYpO/W5hogGEpE6s2Ti3NfXxki+jXlRWo6YVfhKkLHMH7SqCFx+c7XnrYfx9YP/DSwPcT83h
+k7Ciey0cMYNVyFtdbOG1LzIJM+5/rCq6X4w8nlT/2ExfY6kYObFismDI2oTpszqR7NiPCpD45P0
z5qRNXEDcdzbECsgK06+0jf0B4a6V5Yt2YlUklRR0IsD/51ucVvAX+yUG9X3PcyOsm05iBRlIQaY
jvd7EOa/cieRbu5dBACs/2C8EQfbzPznfYNV1mvXkXzSXC9q7KXPzzHOsug0GCgxikCMHeTXHDmX
lL24pW6pViuELSQW14IeZZxhh+28/ciZ8iJukv1vsh40gw0E4hMC/XtFUx2kW+gPrwrsT4brWrW5
imvcjRWjPCOdNe61DT8u+PvRBAdA3kGSjbHEHF/tgOfmW5EFLavF0osXZkwRbVsnEmpR1Si+ISbv
Zozo4j5GHr0uC7CyOrugIVncIAJa3AJY/vX08GlV6CxqJ6j5HbQLEpRF8XR2qKA2xhZwQMo9N0mi
2hKzfoahmkD0OjSTbJxfo7jJuODAYAbfFFb/G+5ieTbpdbqPQG/iDpl4XdBuq+J74suA0IQCxoV6
UNNdNPlwdxC0jxh/0mFkfX4poLdzkjipGkvLLWcoBhAuWUSH6ocifFwdnbwkdljh5BNvq6gHYQmO
K8nfdbpy4Eonr3+G28XxsESbTV9iSSuaWQq1imTZzbO+mqmRzOJ4GPUsgXttlFI1eQiFaKRCJvCF
T5BE5DEyHarpSPLseU4oTx1A7lmQT0WLQ9SCDRfGO19O4zSfERrpSJrO0U/4OA7EUmm47WI7aB6o
yjS4BhSJSyu0YJQKBr5dHOOJ77XAFA9bYOUROkWOtnQJ1bKYoPvTtFXkRKWzb4S8DZWysF/N375s
gsAWoSsWKLzIJ1qSBoo95UJi0moAplGlxIyw3il8rHPqc6GdqMGlTc4ZzhVFiQfep5BR0KN2l25v
L83ot/fSeYjClbRaEiVGD9YcKXTq+PYuAzHNNhv9SywOmGwHsEmMASLCYdb7uuYHqqJkYVpbyirq
YuYyBDQfOni3tDG9iRFiHImfYnygq/VjpSUSBaqH3QxZAnkzHkHf4OJmn+IsR1fqL+KwNu3f0gv0
19OlDizWlWlJ3e6fsHAvY3nPBGtNaXHX7oPtxyn8ifZMWSHnIYD/WyDPBLo82U38Z+rf8q0raLPn
gha0mKz5AGniZcghzxRzl4cs9Qh8BhtD4qPmeWujP8l9/i94T9r57T/xugHTa+xnoD4N/+sJjBB0
C2u1OIZTbKsp1UEsZtfcNrNZQuZKmI7zaSfkL2/Kytds6DAO4Jgxz7uP1AxpcDwOduZrqiCXu/ai
DnVCs6FQkKNo81nmYR5/jkX3Lq/onKY4EZguAqpAGLZnyGCkUIgmu1cAE722m7L1Vn0TZLPPVMCI
N3VmF3BW2mdpG89PK4XoX/dmQIsqQN6h7NF1VNAk8DaDr/AvzmN5xxiH1YXwbd48aP/n9QW3Exxu
ohad+9GfvHaHaNarQw+JdZQOvo/h5Py/O2sZ6ljUQKyyene+AlhFSuy82HHny8mG2Bs6gKBC0Rjh
3hdGnsrdCJOetyIxCfS5W22xEm3c71sw9ayszKSa69E+Fc9PTbyWvGw3ATi0H76drtI90UGZ/lMO
fpI14KeZxrDGAhOu9uGsz17i1mkNPhEZs6ul7EZVvqWOZsMM7kagdHCyeTwye5IMZVnmTq3Q8Xwe
4W9lMEwrY043Ne/PRNKes1kU/+ZIX9DrFtWqirH9dFEeBnuy4072kf6RmVr6SO/bo2HUso3ZQNHp
WnY6TTvUrJnoDK8ryAy8UcyOxHvfab0dN2bSkzyWHJ1xeY+kDyWgoCnNNJzH9t1o4dmN6AhC337g
jVIu8YNIa45p3DwLYeN1Fv+FSzw/hzYpZMcM3URadSuYVQkAKkomh8LZxX0D78pcjJlgndp6hehi
bDjKlV21uTrJiR5N
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
Jg7ZSB2xI/J/jQikm8Zlko862zAjpKBGuPSRLj2TaHEWC5rTzr3rFiYHZX6yv0DYk/Y584dxn1Aj
ZJ3fEMF2Eg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
J8XF87MjtG6MD92nYNEuYX3aIPS/zAQYepXrxQuouCoZ7DifIM+PcGRYhyHbT1c+x8wNqIyddvPX
H9E20LneyNoZup9aJc0KklSHkCBi4RFSlJYfEHGi7VuQ4DoNHay9ZZOx7KnkG5nTkuG8dZKhL494
1mvb9OIoIew9S5frQi8=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
FESqZcf5Kd2nw6uez2DBxPYJSBV8lpPPNkL9mii7n9rOA23QnwFT4gzsX2GnAKh0RRoHvqDgwQe2
oriJIgtSnO9GoEYt557lwN4pjAIARzzVKmQozG4a0ZADHcAuh9dE9U2pgm4IYqaA0WHemsJP3RdH
ZWLIA5hjsrEEni35ostJyYxky5xMLNN1/n6HMS0umCbRhs8srgz/a5uvWD7FFpEZ2a0utgDi9MEX
Ot7P9GN3AM5Ug4guXH512IazlVntMqLUCdCGexOO2NqFhGpAvwGxJCtx5XjHjmGW+9m1bqRxt0uC
W0qg1W0dWBjrERQ1cn2SGOV3FZ9QqHCbH1eBSw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
sBWw2a997MC11UDckC6eUhzOMD6OyRi9hIrFSmKM1LtA+EoEe9hBOU+xWnNJxZwh5q/2lTaLVnRD
SOXNd1eh6E6oJtNfyy/eD/u9oSEqrtEAnNkzfHKZvGwMHsKFUk23bSYe/H7pvyiU6gwLB/zQXKRM
aU3uU6qaXWsFaGyQrek=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
I+E3SG6eIVl+eQQNtE5uT75GDZk2w8MwukclTFsLuB0JtjwI9/9l+wqqevSEAZVNako39sma+Yy+
6sWVRLVPo7PjKtoO7mmywH+p7yQSorsf+a3ZiNjDaYRK+f9GNaE4daxPW5KbJ1GJwaVjbrTJXjms
6KviB77YrfOEwKiKJnAPEYDYIIKzPfz0pkPKCCTKaUXpj+fFxyjC7bycPwfKU244d5RTVzX4xHcW
KE2Pbl2/gBhqu0EO5W1xcfaXIFlrwR2GLFrc0Upm7pO12jbH3NSKac9EirjKD5ICy3GjrAPQM9pC
bmcrUujXKJAoYdm46Fb/QQhF+yxNF515651OtA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13008)
`protect data_block
iXdONubG+SYUpFk1+3xjbTmoWUUth5YI3Atb1aEXZ+saXE5+BGO3fPH5sUZBPpBGvC0XNFvrYkWj
mKjKwY2xZcfJ/srndO8S7QOgA1cW3PG5z/BUIxX97bocLtxDa3aP0B0gUaWXB16YHYdYTkHrQeeT
kByzxROgmclqf0h4i+dNw17ZHgg4lSONS85uKTmrmSH+AeVrAMTnAeRVAxyAfN5NPuWFW82kE644
IywqVXyFo+6EjcTaT9MuzpUSuPIiC1uoPJBymXXqJqXLPFIf66+E0NgglyW1yofbtINgNhR1sgx9
DeAt8JD9ezW0dwIbuBVdM7WPULLxlhRiEjVxJrWWqEe7iSi5KOvb5fzvI83hsOJKOziBELmUOamM
/T8ir8zwHa8BgpammyJqhRLzlVnk0jc0ui0l2oBOLEZatZDKIkibZ103V0P30wEv3kgy6CHZSlsx
o+2FQ+rWnn+NLza2SdRplpZXZVeaSlrNxSpEgYaaVJ1hfYU4shpw1gY2+WgUCqWSpnJ07oVnlkGj
XgvkoW7LarBgf5DSufA7OrUOvhEovDc22xsKo/6q9ikE/FrAsfq/b6I1GPuHTq4tNmNgFLJLqW0b
o15QkRHGCFSFVYp01JsJfRhVklzXE3+toKZwdGB3lL7SLiSo1jny3g5F6camzx2bFmrQu5Czeo5C
/YTWlRYi0Y0z4kUwtLuCniSOj5fXjvS+rZqv0fMbSpKDz3yNPptEql6mPHK324bJZULNhyCzaxZu
6mfclZBjFvrJ40zJfG+hWRGPBj7lEQwK9mvMkOaLF3QzB85I/PtNnp79JEkmMsrgHxSoHMgJJoNG
GeQSVZp39h6ji6XfgW1Z402TkKgSqu9DZ/p/XrxV+T9xgzoHNhQQve11khlld5aZoR2Fz0dS6DWY
htxdwg3F3n0HldhSiTENVbQCnSgvpe16MCIUhBeebBdANdreKwenIpNtmV7T3c/f+GPQpaMe0uyD
CAdVU3O6rVoXt3dusGugSMUIauBbyvk9b1/gmJUdGw420PMi+IvocYBxDF0DyTxNo84nnK+qbJ94
1vTQU0XHzhNk+/bfIO9wIOTa/xR7TnIbwelmHQ2DvCac7jth9H9aFIFV77VLdx+lJOWqki9wagmw
xd6Y0RDu6Fnko3AlZAnPA8AV/fBoS/o9Mbb9XenXcb0Gxv3pWX0F5FX3/IYEv+LqJ0x1dnqXRtJd
f3XkTKRhmAv1RHZN4Ijf/26mX+vAAf+WHJboPQj6tVKWcjoiLGqDoK25y5/n695WQznpJm0jhAyt
n3ga+4uHldOnqkP3JRRSm/A4D1m6LtnYsvrEfBKMXTTJyBxZl5SwwWtzjpQQfAmwUjmxt2oRGiwx
WQNGqkz+TTiFQ5ezlAWncaJscI0KVffI14NwBnVogLcYtDZjOXRpYxrr1uPSV4WFyXUYK4w2H515
u1OVDSE7ERA09Y3+88cM1NHWW0nuzw97Ca/B2ksxC+9UGpBq92Z62ZAfYE55Aa4zCYLfmwGVRBoE
feQhSr3J5McYr/O7r8Ns83MgdkOnLTw3Yu6yAGgxoNDOPqr31lpfWEQ6EBJJ8ymfrpl6w2iI0Pou
3Yt8LzN0Xb5Dn9kcNAAqwxEZncjIHsHGjZgKYuGELLEqeJFypgffVVzo69kF06N/3OGu0IsB+NZF
oNQ9CNZnL8ZD6tsKknOLbWTeUN78pkwcJSqYtXBgkyD9UOx8BGFgrNj4k4z+thMS4m1D1R1APj1T
J88qHzUW5a/i6Y/y1jxvgWiDQZCX0O/oRG76lZxPz4TlYHjWusiXb9KDRuPVTj1KXsjEKkQnt27m
ekgt9Y85Eg+SKoLC8QlLzPn+Jcm3krZYv0Wv7jyISxNzhIMEnrX5lGwQHMrLaX5IYgiOb6LFz6IK
ITY2vvm+uKEKRxh+aN9SdKlZF1F3I/lQJIoicGjJsI0/TY/1NH23//QzdaqgGMK9f+g4fHgMnvke
VnsKr37PDikQLBnz8VK4rdoHartXGc4nB9HSQbY05Q0EXZTEG7wXnpOXD9cG0r2pKjjTEwKlW1WK
XwBxuuNvLZY7vEMV7Iv7VPRzudJFyIsVj91zKTZ0kvtHkYK9/Jhpakiy4ooYnNPj/I9D5vYH11kY
K03oqu2tM2sNKJHOzDo12gfCZxIZYp/3Mv7bMTL6UPp1Kc41QS5EkOliFb/hBIpI598iZnnxZiFo
nswi53iePFr4IhvL4XCufFkfN3Kjf1ozXowHvE9PaNfeJyKSK3TclZgUUJB7DxEcXSrXqocyxOmJ
W0rkdt8E4XvSQ9RXnGw08moTmC4Ay/Qm1Hk4VROcz2C5M/BEbD/z3r3rCD6G+I39slabSKb3EPL3
yrBJHvH+XBU/Og2/F6Y4BGtbmBqc+F5Cbezzs97Hchh3W3YUs4BFHq2a++VcEFyHwTHgMli9VaOY
w2XwIS59gPOO1G3+YudsX73xWFwLxSGEqElr5GNcKSybx/KUKP5fuA1KtcxvUurdTXSeBDqf/vsb
KDBcshsTTQzLHqcmaC8u4PSTzQ4l7S73EUXoM9h59/9naeorj1kALVcSetLAa4LyKoKpxpfrlObn
rL7OH4Hnjr6Xt3C5YcPxh2yGykFBndcoUZYxzNUeLBqBjfYju9soiqCkwcqCDBojqq/Z+t605AzQ
PlXjKhmrcz6ds7eYwO1u4KMZFAC4HXvTNL25zDJHkxcTZzcax8gptFOxcmyBZ9nafcZZ/+cu8svY
5OGfVdRDFOlq4Y2nRCAxb5++FTVg0oNkMP67MsAoGCTGfqFHS0mrScicIetb/lC+TbNO+Wx8Nuvo
jOhSu7tAZH4FwoFNudmSrlrGXOVPDeSb95Wvl1EHIVJ/Bt+g8jHN7L3EuP3iYbeXKJNzmhruepU5
/9pGEYnfaVZv1EKuQD0tsS2tShyClZNZ02zxc1YKjbJF/98+1kndtLO0JqmeBEH4rtJUuqe7mh2q
3HpCmfwguA144Kp23ARkOQKAzTh6YE6taVcJGIZlE51FSZyJS2qaXvOUgyHmpQhhl+Qxu5eRp4CR
QgzCw2U8MoWaz4w04G4jBnldDEQkY9jZIq+iS9RwoHGYNmHbhjhRvjxbtqzpMvHb/qKjvHeLin6o
DWEUotoR4Vrbzse2tpKJagIlmH0mstt5BRRPIFMWwHml2VAoln6STdwmzqHItJ6M1wiy2xuBiMOF
jUrBgmufBslF3pAgUBsF9WfKVFnAL01FY8FVdk+WqWK8dUuwLxslJ21FehhfnaDHm/mGR+l/ZIvC
5OmSQaWH27vJT9tlaf+k50s5SF5h9+2C39bKKqW3vSiy3QerLtGmSi6jOHgLfeJPXps+f10PwsjL
fu5qe3IpeezwjDGOXOD8p2CFbqt44kw+23UtDbUfSrJ6wAs7MWNTdUpltMm4hBdW6EEu4Azr8eaE
rOo76O0rP+ct2UXu2buMDccPuOXRwDdptZvw8V6N/qk6ER21uotJk6xKN7fR/Qy19SZYyc35NF92
oMxdadmKfm9fstBbj1aQUG39cPtIBhIIGxUtI112wstvH6fdPb3Gc/7kf2XsGSSawaj3yusoei/d
aYxfLFPeRcORl1oie2nUPwgrzeGcVBicSBcOTGut38nPCyDBKgPPlqUCYDAlWL6e/O/F+eo3HJ8+
Pv8/1ZmfjG24OpCOUChEp76UToTNv66MkIZ7mi/n1fRYk0B/bs7rZytYIgOZEqlLQlqcZ+uKP7pF
gp8kYzRYgBlskLTPWHXesRRfAklL7mcfyrb+kdJwBKowSRhzpbaokwK1C7zDb1obTNbfnr2IZuMC
4Jkve0+vsuZsZDLKWVrVL4gtmEcdpo9dQ9QUnMKbIjmaUtwMQgSCsRzJJwYy9GWDRS4tPB7V/uMd
WkiXyEPITTQxDOQV5famzC1g6uwZeGRNXKKl6Xf3srI8MeJDEr24ifgrZI5RhWlgne7gfOOOHcSb
cfj5uEDoV9nUeqKBPNQCGDJKzKNK3U4UWIUQDwxcby0iUIXu7mcRrPVQ+i8ZSIkNv7uQ63qD8FJ0
0PnuAovE/oecSIx6Us1avEcX7YzKkqjLUWgs2LZOJPMD6dk8MDoMo7ysX5Sl6Tl9JF14RntPqd5i
2mOS72ZPwr9U6SOt4tavm4B/XYOdmY3LdjECmA+G+O9xhvQeiUbpMmCIQGaQ+JLdC43Nu51CMH+m
bsHsVrUO8pxdQqrRm5yGNtBFQJqdg7cWayjf2D658JcIp73SPJd2nsAV1KXVI2I2++AhSCex0spz
H0+4Xjq4I6wcBpiB9ES5IPwBRuCAU+KNF7cxUJfb9AH4MtrABYZp7EUgpGF3kkDgbIMWWy5kI8iQ
gwoif6mSiXdAR43lYDI8ydMmi1P+QqvyE1uwf57rwrXcT9XTolTEyHeathKbcF9H2e/NusWFssxn
ZAsHucSrjOtuhevUZv1j+NFO/tsWJEgQUWwHFUSHl0tSZJr21Jtv04QAXDIe9uKviuEi8M1Zye2q
VIB12DuPRPB5Y5ZTt6VJEynbZczesS1k6ndss5lIqg4YxeC3iPwEQtab/YwbJyKTlDFjJ05Z3I0a
5V+JL20SaQEidsS8+tML5OVYqOF+X5YAnPAd46ujVVHrWIUqpcTvJny9iLXWMp2puwu15oYG/J87
uOBUIg52PONeRo/2ZROHRSCXUnPQQFvIxzzNph+Jqt5ZIXMTZJMFegj5FhwuthtnL7o7o/k8Lyey
YgY+A6AeZeXkPNrO3/jyNDHcx8ngg7j4n4zOIMOsYL1Eq5h2QYgfEDCRImFX+a8vMUUFhFzlUq8Q
+YnZ/g5GghVy02e84jV91RSbdXodjfxIQtHYXE6WajRfQd9Xmc3BRk+8Uk+VlXiEv+gFdtE1jMEl
Y4J6vlUOaVEh0nfexf06/T7jVeseoM1c9nznKqaRyS5cnfLG1Xc/l4idfhct0jnfD4xyo6ztKKc7
ZoWW//Ob3qeNG3mBXNZQUJMmhE2P89DViTozT+GQTzA785Y4apmPojF8ZI66ombhB0Bej2RInX0L
Wdog3njTuUmLQllhN8s0QQIfhHteB+eIH8vSm4vihPzrjwPyRL84uuW5TibDb8uA3j2aXmJ8sARQ
ijh3bM9ltfHOSh+gdfA2CwTtjpCuJPY18zeVTbwrjKjXjO5I50Svt+1f62XsFYJ7w0IzUqVuGGKi
IQIkrQLlKPh5bBbBhVsC9dBjmkkRCGBuawHh0VgUNV1IjwtHW05jlfEyrTJWjUlntujZrtGWGc9z
VRjyV83unGC9AEscKVLm7hTcgw1Uejk7JhTYsWrmnXD/2yniLpA31qEtSZdL4A+bEwKAKbWiQxsG
COwzFFI8dfZ3qGevBY8aA47DZ5uUd0z1t0IeSunBnsNh1mnMj3oOS89PX0dRhciuDE7dbg8+0tBW
9EmHn3PKRmNL1ipXvHIIfYuYc5Od3somla8JnQyl6jBAle2+RUahuA5yMVZLiJ923n8qhGYa7t/S
dKPTiknun9P6w19cPSXpI4v02Mjg5ALkLsMe+4Y4TqElQ07w7hiHGsu7EYCQzpVovud5f/db+g1b
nI9MEUV4/hYX4rVfPm8CDe4KkNvnGMro1E0JXv57X0O0escjc2QvaFP1SNc9KVhyZLJ3lYvDXd3x
YVU8eDke68BRejyCkl7EsUFiyPvyFYF6Vb4XpEWRIiW+qCj2eTK3JY3aS5ubeehk/Df3D3xYofdw
Ps9O02/Xns/UUZj/VWl3GeoM5uK1ckObVDlRwnQlSIa8X6EKAtGbeEyKDtZ/wF9Cd9+6zByRakKG
yAZ0kiS0dH8wvu9JtejXD0Yu3vjX6UgRJprZ9GYUKRN+1KYS/OlJ7wFri824lniD6LCqZb7L0BdN
l4AQ6kM4NrXLDT427YeMNGPoE6FY5QyFuqPLdFUJ1X71o6q6ATkecmV00kaGAk2x2TwwVpfHHpTj
Kab4Xhl93ic752GhbFNJw6BBquu6DFjJEenEJKGIs/Qq5lM1W9MQ+OoHd/On8K+ThjECiWzVBpbX
19ZnKrWbyfTNu+idotUkQRkHnMZfO1oe+p4eeCIPk2f4sRaxVoz4jtahxDdZzrqbgs2lXrQ+h92Z
MJ4JqtyCA2LWlrYOiTgfV6jeJnOT7p8EqA1r5gNMMf73uzJqRhTbLYdhoqY1V9brJqIelEZGwlIV
eObr7vF2SmXqVv+D2+vRjpT9sANMCBFzg5JJXtAYiHbLFJ8WXPAhwsZkuoP/a4pQreq3LHnioRRA
NlirCIpTHWBjIlScqQefBKKuvJKIAZwO+0G5Wa9FG/eQwqM92Ugne64Czm5BwKe1nXlS4MqmO1um
I0b60Gb9nWnTtKFce6YOmmSwUB/FFOT+muekdItDqFC6AtF+AvtUQ+LxE6jEogPrV975od5PONSK
1XCKPqiO75OrG0GvVL4W+lvNsSWCkx5ezq+J+I4ba63UyxL0UJ7ASgXjyUprZVizgkZujeNC59rB
YTyaZRMVtLjriqdEgpHVnA/Mp3OaA/WJJuD4XtLIIkizKKnJpII+saXW9Tzz69ET5zQhZ2lTxjF5
bAPXtnHSYBcyt7s1Junm0aBhPpsstcrQt7A4CDyX1wRNxsrG6K64S70LNtZkzN7p/toH2QOd1Ntn
vk428QrP2w/+RDHCWuPAXKJk1GKTaYFb9o2RlxWMOf782ar2knfS5VHhd59BblwWY0nW2IA61OCo
4OxPCxRPE0HUO5Iq4wg+HMth/Anm8AdPmfHbIYvwHtItB+bqDht1Hr5pQkOydqpCJvnPvYtauzq9
rTq3A3t+nYHY1Q9lwG9WfMcGaK4de8jHn9WrrkEwVnnLj21jZlnV0ZxET7ZlY98c02e1rwVnrWr+
Je5t8HKCBYOR7JCv6DaVwvNIAoqVP51AsGin6sd9h+HhA6aVypIaWjf9tyloV/NzduLhvfjhcV66
WNNxNcgfaDRoCt8Ryd99nsYqwm1v7Tq4EtN0gtX+WoGxn4zzDoF8M3R+yb9b+7YNchfY5n5bXQFn
MCE3vBHAKjWg5uk1qBr75cAu1Qca7g5K92MfGhc+jnnTTux0rvAu8+tJ6X+Edf5DHKiflbQgiG9J
7CTAsB9Q7zkjtJcl7OcPuHTk/3LAHhWdPeIm1LX4NVzF/kt1kI5Vptuu12DpHErhezSs6YWCLAr9
6A5AUIXq46nPZDI79z+GCMgY6Do/KG9RHrttH+qyncHGFhJFIJwAGmHFyM4TXAc56a/ioJI75zBa
csW6uOhgYQo1rVjjGg0JOHgoL2hiSo1cgO8FbaYeABImPoC6h+UmyWIrHPEva8RCDqBIIxYacjF3
Sablky4HqOOqTH3Po3i1W4hePeUWVfmiHqGg+rRQvXt3I5KcOa9BHeP8PLH8WbZnHhybI90AJW4B
ghGrLgpA0BouIjoGXWb28lm9b1cn52FbIvymS/YVDidtBow6phD7ORIC7RN96opz0bgfDpBsFfKk
C1g5JN/wmgOIQ0XanlsorghXFG/y5P9M6hRDR47vsyrhrmea9/a7kEhdCuFyvPL842LMx+nKI3eS
FvJtjqUdksjTtLmVF8b8u6sqwU6UFtHtD9r3ZhLPKmoXtg9KfoRBC245DQs/EvRySHvQuseOcjXx
5RkzTTZ3jjy69kCHaFf8TsIzpmT1k2o6SeItN2z/XLhHF+cOKcMNTrOPKzOndIfCrhVvXL1vUIfY
opdi/RQbj0WYsFBlZxN22CeeLsqS/sFkzosL0tk/QrsDCAW2e5lDVZfaROYbFV2DVaBtCaPsukxr
ii6dJlm6iBgbH592u+f2mI9ze3K3bpsNH3CfLCIYDDI55iw6Qwnxg8cyeNwWyMIdLanykfH7Ju8c
ZcGGHpV0gE7uf5qc3HOBJHrSdvYc359vywTxDuP9P+SJDyx+t60gzygUEutg3fdY29j2wgp2D8A/
gRAG1SnHdPc55yCIzkndYxPE3e9z/tEfzN9bpWTkjECzzAYAeBBClkKk4paB5YWIjvLEVqoh0jfA
ZVK4BErzQihjWblDamZIenulFel5DULaJy+tH7Htt7XS99+kxeShV3OxFaxZmv2wZlozcdBjCWZ+
ibrVwA2Fw4qpfd2/mR9C8rkmZHFEyhlqgOObFsCbVRVhAPifX+s1OAHQnzvqqri2oe0KqyF8nWeY
YkcYb/hkSqPmV/mUoM9CDDcgJQ+MssByY5UZxPuSg35Rlo8SrIeat1xZbZ1y4R/59kJonl4hERMX
KzK/D2HsaS6LuWMCBBAk190mDb1DELlboatAk2U+ynZWeDcMUgeu7V2MDcR+56IG1e6MK9vMw5p5
kyb4IC0NudHIppagDkhVyqyMLYHhl4fbHjw3zJQwP5DmLffEb5u1TgBzbzxhqvOlYpBCjrIXvzo5
JSFcaTA+aXCzM3WWjZeX0dSP3MZV5gcz4e6tELgJxNQhelnifyxFrqU+OJYBo8oJUKU4sCKPafmH
2Dufn9IKryoxUA59p75/NZadSANaqUvLXoqQoRVrbKBRrK9TINJPx//uJsJ6S7btepIbmQmJw7Ui
lEkn2HbtLf7cwgdXyCjgKBL9z+onHs1P8Q78w6U33GSl3kyvbK8KJhTDTcEvB3bHQCd4qeuM4ahE
gk8UNAIAZbbTnza8Y8OhN+gGthKNYe1/+TmfuVD5AB9HbsIB8bazOCqKyifB+eGZVQtn6uB7ShIW
OdpMNUZuhaxwTq469qaRr8EjNS2xE06TFRrauI9CRpMBCBZNSFyTIssidoQWA5JVHGO6eqyXwfgB
vB2BxeV7SQGitHtabgdw08LzDXd6ctJ1tKT2OCht/xesY4Od6hO3ra+xvEGINCjT8XK1s9Q4P4u7
R0GKZ7oa3h3BylbAaJq5fKMjRqLGkXFvjWMTc6rhESpWck6m0TlmfdsXflsCxYWLEibvVDaevwsT
E+uA1UOEjCr+SWq0pClD4fxV1IqCSIwD/hgVnlpu03nhBk9PDfmrDaSeHLKm/uh4y4ogBCKQtQT1
JmW0IgNIaA13zSdQN6wD6dryxMF48Cc/THO3QtA3vl5svNKVWk+mEYu2tNApzArCa+Ifl+x58cC9
9RTOIl2fc9Gy38ArM6S39s+PeEh96xUGVCbAueyKhiO75V2yVROYvgGkC6Qi/KAqaEirBS922Zru
Ye+TY6Q4phjpf/CHGsK0WpRIwokqgkhZ14OC//k+ax0V3DhAJqQ/TcPI2ooG2EpPNdNPYrcXwXRp
9ck4cTWqITnoGg4hzs6/cxrjxIE0OhNYgLKht8zL35OZrJfHJ+KEVNCyOw/JMRpAsB7J4/54DcTW
FsvTSEABYu0I5LqKvs/BLx2tmmXjJqpjTFLA3FqNOPrrfhGkaRxQtAytJKyZibGWAgx1mzNrsrIN
+C2npOErzVY4oGBuXXV9X0qmwkQ/aU7UIyKQa90gmpax3j16L7/R/v9Do0W88WlGrCKZwOiEWfce
kh2fzKBoB+AJHxikJOg6488LLmaxBrPcA4O77GNwoOgWKufHrGUc+MJpYZhzJJ1I4O0l026xoXXo
LfGceXZT/vdoovMcrGf91X099uQQsDy8jqLLziX9f+6qIZUHx47hD4ECXJXV6QyY2lQ4h+gJiOzW
hP1yGVP5PD9jRurrtxcMEuYwQsmIPutHpbt4inFagIVxVX9BbPqyLsiSsfmKkGK5Kui7tWDDHIA0
eBmaW9Xu5hOBy1+qLvCOIPX18643fQWKajUy9kWmB+s9itfVOFuKKshtG/SnRpe5Wetoztp+kuxH
OHaxb4zGcDpebbDjrU55ej4pFpJgg38H7ljkMiGkkLGAn+TwllHeojnqM2mghE1tPG8vjPHD+CMY
uj4exjB1GU1JGByWyms9F0oRdvKliwlIQ05hpPAyMEIoiHHg9hkaOoKrQ+U5vQVga9ofIcH0BZ2L
TEFBqYxtRkqi4yYYMh5zLQ+fJEGSVs0ajiLIwoH1KKmaF1eErvEW86s3d4unJxkpkb2QxBqkebLv
JJIQglskZ6GmqiO9cPpVueo8cyP0ZXXzO1gdxrpLVKx+QPyPIwzRP/x/j6EEgh/rsVZSK81enbkK
HThbYw08GTi/RjVybS7QcsMrMB9FbuzEEAyWs5XH7NlXRTzjwB+huO/s4/BtGuaYwfvD1cXk/UWd
nqYfKzMwtaat+LQjmbPXAHvLdvRbtvSLJLWZSxVURGl8Ez0ZuIyvn35lFNZqh6I1QwAjFQ8WDl7S
9ZuT3xlLkSzxUZOUfC8QdaYV+oklrWZdkKm54M9bfeNQfeRBvylbzdEuIbgkquF02UOH9XJUquuS
Sw0qNuWzAEAK4rLchd4NfuCGNl0J+TSytnoQy/XzF5H8qSc2SQuA18fc0o9Jl0A+dm/ZfdbfMPXU
XLz5bFi3TQ3Jlc25v8IJaoN744m0G+vpEdMPPYrqHz4sXSbIDKbthpOcBfqeTkf+lAq7OG2e0MUm
XWTkWs7LMG8gLWzgi/QEryCMMmbub89tfonU2WLEzS8DyNBeXNj60RV1Xc+d0YWUXJawbOTH9xSD
sg3FK1palRgTIyTAIZm92pZlZPYnu7Roff/MBsVfIbFL+lryo+IP2H6+RyijU7aNlpC5ckqeJTOa
Lah7+s9892HqcXgQ2r3auRNlgI8Sk937dlmT68UjZdWJpi/HLmrCNTVCb+vmctVvQppEusxvG0Jy
kpI1bkdgFQnYIPzTWTODGyjCnghdoRX6ZmfSmculY9PnrF5vJGCSgOpDbZIy++PoYNN/ca9pwb+h
TXSnO9khtCRrt25rryyYrr9M+bUWr6OIr3ud8EaDfMSVCzGdNDBC/iJPfnXYTvdTC7/uWz9v1woz
pGV+m8tzkZjzBHRhDO4CeGWSR3/5H4K+KIHojAT6sCVM1j1wAXZfa0bBXCAiP/TStnZ/UputQgoS
ESPZIVRO4tMkHjNqhPLr0XwO8rmlZK4ejmOWlsYJelRZ5iKeJAKOfD6aTOhrR6Gt1rmz1r5Oe+86
JZqmDk25bLMoZZXMeFrjp81q+KwjxgnVSThF6n87/Z8Br+h7sRZZcjWKBi6UhB7e/XTroPxTNudc
ypLjHedZkWxBnpyAy7HpSv+YmOi7nVDh8opsPlwmMcnyRo87+NKEbI79LVlM/l0iO6Fcfbbm28IL
nQbzcjckRBPNb6ERDo6fOPb+NfdVhDlHNy2QeNc72nI3H+pKanVLjstwurg883OZymM6m9bYDLeX
vsRwJernuWDwDXa7KqyJHa/B/eqqMJR/1CFDdfQzfPr2GRIkx8E23sCVgfEYC8UpQUMMAdpg1nAR
ykbIzOa9QJ9c1RGx/hz0fQuUduOb/a5ltvxQRTySNojTlAdncANN7ewSXNJs2Lpp9S3d4j82cMbt
1o2k9pl3ngSxgOOp0fm1HfKjaX9kRMyDbTq7WsAGxwjV/c9nCtmsWxIVGccFSpaNqMYiusvV/0es
r1/q4Fs46kQDJWoi1uyjoDOxxhok+CLmhPVDTlI0ZZr/Y6cwnMuuhks14z/R/YocI8AkGVW+HH98
VsLZNoQIFlcN/SgbPdnaB0OsGHWOsvLUjeSVTFgi7LhtyP2x4scEDCFLfnlspPF3GjbefjIiNEov
rReMj8XKZIexeb9IQeclWRSwXowB0rP1imG+jlL+D9zOv1O8cOhqhRloK62IBi/Wyv9AkmX7EBeR
Z/8wjNay/o4TW/8RsdNOT+8ok/J9vIn5ggctes7WCP/nFkP2WAM1nABVzqyPW26FTGgOCSJ979Fk
x0toxJdlkxb3v0+7lyz1sDv23dt2MlPHqAws1fLdkuovJoKkZ1dlR2NcYCZZPhXjWgvzzwJHlOsB
8gL1IRBL+zYIREP6X3E1poTEEjOq5+tVhVW+WfQBvn6K6xJfsD64LSuwqrVkS1mkzj1TvHxBgRLh
IitT/JuCh0BbwOpt8MsdRQYSA2wJfEG5LoyQsaPpqn2B+WY+1icpU894ty+gRfAAeoIMfCrYMTC1
QY2UMBEuTUb73zaWP6Q7x62Y1YNaD9XESB/ZqWcKT5vIILi9B7TVW0E85E8Hv31PLvY892k8E4LH
huoZ7k7QPkNFdr0xNSSCxH4kgJAXcKrDZ4VTmOLFbUORZFvFEOI3nIV1LRkpvMdO56DWOh4JH78y
YGL9L9QZzbHeQ6rTMNo9CVCa2A1E4zR1SamoBYYtCyzgYKWSwI14selgW7p7Psh5CPcPlQga6rx7
VW4VzokHR07Iq4NniBqqYUCd+RzWwmALqHgpl2U+DVn+4ESKLisI20E0cY5g/ZVY6kMwIQuqWbA5
m+vnwg6f/GJp9gaLfGgh2zKsfvBeHq0XmFw6IQsZst3amWm49qs4uc0dZmuBZkmKK9aGbDnJolL+
+HL1kGBLZUO0+fJin7bYrRHIFYYoZbVYSzy4yX9TgenFG6zYnHS/l16hWZqqfSRzFjgyVwVKF/9E
MwnqImGOVyQ7J+n7uU+AAdP4VR2x3Il35Dhkh6+alwEtB1s/cSs3aiHQ1RKw82qd7N1hEs9lBkW3
BxeVyN8cfAPsmg5mWb1ljOoSb7iX64/9fwuvq13w+piUMxoRXj4bYRn11EPIg3sNkwKXyMx2KJ/J
kuzsGL9ExkUGmzH1Y9CQj2N4Oyx9zjq71VmAzX00Ej6+bzJ2aklj9tv+DnxVIyeoaGvH+3XvFMRK
X/BWsc7+QJfE3eyG9N+YkeZonu+cU3qYTNL+Bw8yamX5zgP4v0k7wXJvdZzCytHB4yLj/F0rW9jJ
arbRSAbHAjCJ6BD4z4AkWvZiZR4WnQ/KOmkMoQrdHRkVRI1QJSXEc55t5uJKmu/GhhfGWPg85J1e
lJ1J3CCFS6e9fG26WV6mYdIEsdKlIKbQjD14w8Oy3KHVczWo9VvKAH12y+g0tdLD+Ag3uOOls7iv
LQy5AizOtPdU7HV1W4NNyWMET14SXbod/LE65NMlIM6jGc8ER0lIKnUfptsVKDF02RLR1yNhn/d7
fmlnhLCRMM51bqDQvlLiMocGsFJCzKw7HBLsASom6Nd/fgRF8xvbwDH7OUsncfeuJiC7AZDAdViq
rC/oB6QwI8TA6CXGAhiI8N/xzptIZ+klEWze4ENMstSH6LlbbIKf56od4VvTTkX85X/P0xDc3Fub
daDexnB067MRkmm/eupSXI9D3OLHr2rPzD9QvGe9/w9P/iiD5p7V3K5qgVcejFTdeYoPYsNJ5bwK
HoN2SRwb6s9WEHPBNlJi+Rll4Xc4vxclzF0plhYWBZVMtDEyeGRNekfz5VariivlbvA3ZpLA2Yzj
lkjD3EIraEnwqDQqT6bBMTHD5sPvIaRuokoYdEqiaL75ZEY0ZDhy4jKACuS7prqhn60SoXMKW1xe
LsJsUCgdgKkCSe3fSGkAZdo/bK7crQ+mqvsbtjgE4CNOxy2T2ZpSnJBhTcVPvhn8W1GB+EjrHIfa
RS/P+lvWENV1PWi85odvoFPP2VWxqeNQ2lLyii9zzMmYNbMhJjF087p6IDPyNq8HwAMNgs+l6JDC
tbOGYt9kMB+czH7rbWe3xWp1yavknXF41UVkrYMYKse5LVvQtHlZJdg0gtfoaR0vCSP7s/6oeFjP
6BIJ/FSAyeLSP4ObMAo1i2124f97gbP+7pMTNSLNrLv4aZD9XOmwvtdixrMAQRZscsyTgF2h11Ue
Tzih4cjJl4bqW9gJ71sWHEdHYruSGcCbrCe2KbJA+9hTSDsJtfdXAi7m3bjL+OUQ8m8Xf9Cfss3A
NWEuU8lRIeO5VCOdZKgO4R2RB45lJ7NyUL/RafKZozgN/i8t0FX+cklls4L/vu87i8A2NgY/Ok/K
3690T9KSdZxIO6OYv25l8k0HsygockP4QhDUPForiNropyUUsbYER3yeYZUf2TYlpEagET75rRI1
2PBJSao5eRsqhbhT14V8Zv4HYxv9GdxzVHZKF86QtR9bEIsQnxZ0YTsovwVzaRWMTtUTedn5PZ8U
JZbkNq3zJUCq+n+TulivCxdBkTIsorpT7+a/+2M32u3M74kvXOoDi3emCYm9IuOFHwaGQgoMdPmt
lW8iLuKKqy/MccgXLz7JfJnxYz4JwhvY2IpupqxdlsttyuXfqS07tOCP47d4edKCH9D/W49aEMRU
/SgAFUdOIYbREO421ZjOopEfuA0eR5ygDSkQf6dGw03b3TGsVvxwnhKERefF5cUeV+Sxz1KI32WH
kcYc6zgntxT8eRDjhp6d2yWx0v/ysZzNgTgMeB7mbk10kpnB0b7h637z8iX46sfMXq0JFomI76v2
l8I646CEQatWvxmakVWdrcQ/uuVvFvBl0OfhYsbgPw+tuRiGwYgzsFjSw9pMFWJoKbvHZstD+7h4
bWH63Vkm2yzLSoks+9wPdCLqKeSvHGA6C9Q5djsKn2SOlauVuRIQyqOk0YG8tIW0Eic2zMUYCCIt
6lz12rd/usiO10p7wiIvGXidb3NLI+MwWhWAYMCUG+Mgm7APMJbbHOm77fowLz5zV/Rs/6VD4uZV
nvnxRteVagtXXCkiMD5W4InZgvq12Sj8hppvYJ7oott7UM4jff2ziOSUPdiu6nhrLpBhi6dzfLec
ot4eLfgPVkW8+xV2mWAN891ji+mc8QBINhSAPLouZJ8AyAGvO83NB6GnQM56MFpjlaYJS+4TFJ93
NTLyvmPInQyoZOajtGRhGlsgdnvEdXSPAUQ2BZTgameaBRs9LsPEh1Y43+J1uyRI6fXErGCJPg6U
9efqVgRobI3Fhgu1eItNuLOseysDprIlxIz79z8ySo+1XLmsZgKp0QFaX1Fhq0wP4t481WIgy/kj
/Z+FAPOZLJbUG8sEo0Vih91S2sql0GY4yORoVZ5zx3JHiffCeCr1tLhT4sQRlwbzY/y1xSUU/ZDN
XzUoPCRrTHxApvYqOFPT+qFZ+vi/UaAftQNDVQSBzxFA/LxopC5pJEVi2mrYlZ3oueUTx3EHOp82
b2LiDk6UPnxZH0zdPQBtr13TPjTgJfFL+FVLUvzqeOJDwko5RYaLmcGYxeVa2Gzsh3rNW1KMwvfE
c6IVV/+g5jTz/iHKpFcOWclEqqn40rAzHXQ1QNuzXzKAOicqI+KX32Irf2QVTl8178biX3+3kusr
eFOsv6836hr3DjTNf7qAkGrCk8lChd3V9iYcEOQZ7KRDykBXfpGU7Qk+8tzpU+r1cj8AQ4+w0CqA
lDlfONdv6Nk/fq/RAHmVhX0pd9fckbonJAg72zazCvO4Xn3kAZdp+2Nmc5UwjN+U3egb74FuPKGM
NdTRLPvjQwMoP9mg2dNVH5iC0QWcY3Dj2sYCg/ALXxG7HV03UFvKZ/AZKssA47IofJ+Pn2oO0oJ8
w4ylFe98xloVwyv9NESeeVPGuYr+KirBJ1ty3GkCRF2HW8tBsSz60/QeBMe4ifhzlJIMcG8FKV/z
BqXUDYpO/W5hogGEpE6s2Ti3NfXxki+jXlRWo6YVfhKkLHMH7SqCFx+c7XnrYfx9YP/DSwPcT83h
+k7Ciey0cMYNVyFtdbOG1LzIJM+5/rCq6X4w8nlT/2ExfY6kYObFismDI2oTpszqR7NiPCpD45P0
z5qRNXEDcdzbECsgK06+0jf0B4a6V5Yt2YlUklRR0IsD/51ucVvAX+yUG9X3PcyOsm05iBRlIQaY
jvd7EOa/cieRbu5dBACs/2C8EQfbzPznfYNV1mvXkXzSXC9q7KXPzzHOsug0GCgxikCMHeTXHDmX
lL24pW6pViuELSQW14IeZZxhh+28/ciZ8iJukv1vsh40gw0E4hMC/XtFUx2kW+gPrwrsT4brWrW5
imvcjRWjPCOdNe61DT8u+PvRBAdA3kGSjbHEHF/tgOfmW5EFLavF0osXZkwRbVsnEmpR1Si+ISbv
Zozo4j5GHr0uC7CyOrugIVncIAJa3AJY/vX08GlV6CxqJ6j5HbQLEpRF8XR2qKA2xhZwQMo9N0mi
2hKzfoahmkD0OjSTbJxfo7jJuODAYAbfFFb/G+5ieTbpdbqPQG/iDpl4XdBuq+J74suA0IQCxoV6
UNNdNPlwdxC0jxh/0mFkfX4poLdzkjipGkvLLWcoBhAuWUSH6ocifFwdnbwkdljh5BNvq6gHYQmO
K8nfdbpy4Eonr3+G28XxsESbTV9iSSuaWQq1imTZzbO+mqmRzOJ4GPUsgXttlFI1eQiFaKRCJvCF
T5BE5DEyHarpSPLseU4oTx1A7lmQT0WLQ9SCDRfGO19O4zSfERrpSJrO0U/4OA7EUmm47WI7aB6o
yjS4BhSJSyu0YJQKBr5dHOOJ77XAFA9bYOUROkWOtnQJ1bKYoPvTtFXkRKWzb4S8DZWysF/N375s
gsAWoSsWKLzIJ1qSBoo95UJi0moAplGlxIyw3il8rHPqc6GdqMGlTc4ZzhVFiQfep5BR0KN2l25v
L83ot/fSeYjClbRaEiVGD9YcKXTq+PYuAzHNNhv9SywOmGwHsEmMASLCYdb7uuYHqqJkYVpbyirq
YuYyBDQfOni3tDG9iRFiHImfYnygq/VjpSUSBaqH3QxZAnkzHkHf4OJmn+IsR1fqL+KwNu3f0gv0
19OlDizWlWlJ3e6fsHAvY3nPBGtNaXHX7oPtxyn8ifZMWSHnIYD/WyDPBLo82U38Z+rf8q0raLPn
gha0mKz5AGniZcghzxRzl4cs9Qh8BhtD4qPmeWujP8l9/i94T9r57T/xugHTa+xnoD4N/+sJjBB0
C2u1OIZTbKsp1UEsZtfcNrNZQuZKmI7zaSfkL2/Kytds6DAO4Jgxz7uP1AxpcDwOduZrqiCXu/ai
DnVCs6FQkKNo81nmYR5/jkX3Lq/onKY4EZguAqpAGLZnyGCkUIgmu1cAE722m7L1Vn0TZLPPVMCI
N3VmF3BW2mdpG89PK4XoX/dmQIsqQN6h7NF1VNAk8DaDr/AvzmN5xxiH1YXwbd48aP/n9QW3Exxu
ohad+9GfvHaHaNarQw+JdZQOvo/h5Py/O2sZ6ljUQKyyene+AlhFSuy82HHny8mG2Bs6gKBC0Rjh
3hdGnsrdCJOetyIxCfS5W22xEm3c71sw9ayszKSa69E+Fc9PTbyWvGw3ATi0H76drtI90UGZ/lMO
fpI14KeZxrDGAhOu9uGsz17i1mkNPhEZs6ul7EZVvqWOZsMM7kagdHCyeTwye5IMZVnmTq3Q8Xwe
4W9lMEwrY043Ne/PRNKes1kU/+ZIX9DrFtWqirH9dFEeBnuy4072kf6RmVr6SO/bo2HUso3ZQNHp
WnY6TTvUrJnoDK8ryAy8UcyOxHvfab0dN2bSkzyWHJ1xeY+kDyWgoCnNNJzH9t1o4dmN6AhC337g
jVIu8YNIa45p3DwLYeN1Fv+FSzw/hzYpZMcM3URadSuYVQkAKkomh8LZxX0D78pcjJlgndp6hehi
bDjKlV21uTrJiR5N
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
Jg7ZSB2xI/J/jQikm8Zlko862zAjpKBGuPSRLj2TaHEWC5rTzr3rFiYHZX6yv0DYk/Y584dxn1Aj
ZJ3fEMF2Eg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
J8XF87MjtG6MD92nYNEuYX3aIPS/zAQYepXrxQuouCoZ7DifIM+PcGRYhyHbT1c+x8wNqIyddvPX
H9E20LneyNoZup9aJc0KklSHkCBi4RFSlJYfEHGi7VuQ4DoNHay9ZZOx7KnkG5nTkuG8dZKhL494
1mvb9OIoIew9S5frQi8=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
FESqZcf5Kd2nw6uez2DBxPYJSBV8lpPPNkL9mii7n9rOA23QnwFT4gzsX2GnAKh0RRoHvqDgwQe2
oriJIgtSnO9GoEYt557lwN4pjAIARzzVKmQozG4a0ZADHcAuh9dE9U2pgm4IYqaA0WHemsJP3RdH
ZWLIA5hjsrEEni35ostJyYxky5xMLNN1/n6HMS0umCbRhs8srgz/a5uvWD7FFpEZ2a0utgDi9MEX
Ot7P9GN3AM5Ug4guXH512IazlVntMqLUCdCGexOO2NqFhGpAvwGxJCtx5XjHjmGW+9m1bqRxt0uC
W0qg1W0dWBjrERQ1cn2SGOV3FZ9QqHCbH1eBSw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
sBWw2a997MC11UDckC6eUhzOMD6OyRi9hIrFSmKM1LtA+EoEe9hBOU+xWnNJxZwh5q/2lTaLVnRD
SOXNd1eh6E6oJtNfyy/eD/u9oSEqrtEAnNkzfHKZvGwMHsKFUk23bSYe/H7pvyiU6gwLB/zQXKRM
aU3uU6qaXWsFaGyQrek=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
I+E3SG6eIVl+eQQNtE5uT75GDZk2w8MwukclTFsLuB0JtjwI9/9l+wqqevSEAZVNako39sma+Yy+
6sWVRLVPo7PjKtoO7mmywH+p7yQSorsf+a3ZiNjDaYRK+f9GNaE4daxPW5KbJ1GJwaVjbrTJXjms
6KviB77YrfOEwKiKJnAPEYDYIIKzPfz0pkPKCCTKaUXpj+fFxyjC7bycPwfKU244d5RTVzX4xHcW
KE2Pbl2/gBhqu0EO5W1xcfaXIFlrwR2GLFrc0Upm7pO12jbH3NSKac9EirjKD5ICy3GjrAPQM9pC
bmcrUujXKJAoYdm46Fb/QQhF+yxNF515651OtA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13008)
`protect data_block
iXdONubG+SYUpFk1+3xjbTmoWUUth5YI3Atb1aEXZ+saXE5+BGO3fPH5sUZBPpBGvC0XNFvrYkWj
mKjKwY2xZcfJ/srndO8S7QOgA1cW3PG5z/BUIxX97bocLtxDa3aP0B0gUaWXB16YHYdYTkHrQeeT
kByzxROgmclqf0h4i+dNw17ZHgg4lSONS85uKTmrmSH+AeVrAMTnAeRVAxyAfN5NPuWFW82kE644
IywqVXyFo+6EjcTaT9MuzpUSuPIiC1uoPJBymXXqJqXLPFIf66+E0NgglyW1yofbtINgNhR1sgx9
DeAt8JD9ezW0dwIbuBVdM7WPULLxlhRiEjVxJrWWqEe7iSi5KOvb5fzvI83hsOJKOziBELmUOamM
/T8ir8zwHa8BgpammyJqhRLzlVnk0jc0ui0l2oBOLEZatZDKIkibZ103V0P30wEv3kgy6CHZSlsx
o+2FQ+rWnn+NLza2SdRplpZXZVeaSlrNxSpEgYaaVJ1hfYU4shpw1gY2+WgUCqWSpnJ07oVnlkGj
XgvkoW7LarBgf5DSufA7OrUOvhEovDc22xsKo/6q9ikE/FrAsfq/b6I1GPuHTq4tNmNgFLJLqW0b
o15QkRHGCFSFVYp01JsJfRhVklzXE3+toKZwdGB3lL7SLiSo1jny3g5F6camzx2bFmrQu5Czeo5C
/YTWlRYi0Y0z4kUwtLuCniSOj5fXjvS+rZqv0fMbSpKDz3yNPptEql6mPHK324bJZULNhyCzaxZu
6mfclZBjFvrJ40zJfG+hWRGPBj7lEQwK9mvMkOaLF3QzB85I/PtNnp79JEkmMsrgHxSoHMgJJoNG
GeQSVZp39h6ji6XfgW1Z402TkKgSqu9DZ/p/XrxV+T9xgzoHNhQQve11khlld5aZoR2Fz0dS6DWY
htxdwg3F3n0HldhSiTENVbQCnSgvpe16MCIUhBeebBdANdreKwenIpNtmV7T3c/f+GPQpaMe0uyD
CAdVU3O6rVoXt3dusGugSMUIauBbyvk9b1/gmJUdGw420PMi+IvocYBxDF0DyTxNo84nnK+qbJ94
1vTQU0XHzhNk+/bfIO9wIOTa/xR7TnIbwelmHQ2DvCac7jth9H9aFIFV77VLdx+lJOWqki9wagmw
xd6Y0RDu6Fnko3AlZAnPA8AV/fBoS/o9Mbb9XenXcb0Gxv3pWX0F5FX3/IYEv+LqJ0x1dnqXRtJd
f3XkTKRhmAv1RHZN4Ijf/26mX+vAAf+WHJboPQj6tVKWcjoiLGqDoK25y5/n695WQznpJm0jhAyt
n3ga+4uHldOnqkP3JRRSm/A4D1m6LtnYsvrEfBKMXTTJyBxZl5SwwWtzjpQQfAmwUjmxt2oRGiwx
WQNGqkz+TTiFQ5ezlAWncaJscI0KVffI14NwBnVogLcYtDZjOXRpYxrr1uPSV4WFyXUYK4w2H515
u1OVDSE7ERA09Y3+88cM1NHWW0nuzw97Ca/B2ksxC+9UGpBq92Z62ZAfYE55Aa4zCYLfmwGVRBoE
feQhSr3J5McYr/O7r8Ns83MgdkOnLTw3Yu6yAGgxoNDOPqr31lpfWEQ6EBJJ8ymfrpl6w2iI0Pou
3Yt8LzN0Xb5Dn9kcNAAqwxEZncjIHsHGjZgKYuGELLEqeJFypgffVVzo69kF06N/3OGu0IsB+NZF
oNQ9CNZnL8ZD6tsKknOLbWTeUN78pkwcJSqYtXBgkyD9UOx8BGFgrNj4k4z+thMS4m1D1R1APj1T
J88qHzUW5a/i6Y/y1jxvgWiDQZCX0O/oRG76lZxPz4TlYHjWusiXb9KDRuPVTj1KXsjEKkQnt27m
ekgt9Y85Eg+SKoLC8QlLzPn+Jcm3krZYv0Wv7jyISxNzhIMEnrX5lGwQHMrLaX5IYgiOb6LFz6IK
ITY2vvm+uKEKRxh+aN9SdKlZF1F3I/lQJIoicGjJsI0/TY/1NH23//QzdaqgGMK9f+g4fHgMnvke
VnsKr37PDikQLBnz8VK4rdoHartXGc4nB9HSQbY05Q0EXZTEG7wXnpOXD9cG0r2pKjjTEwKlW1WK
XwBxuuNvLZY7vEMV7Iv7VPRzudJFyIsVj91zKTZ0kvtHkYK9/Jhpakiy4ooYnNPj/I9D5vYH11kY
K03oqu2tM2sNKJHOzDo12gfCZxIZYp/3Mv7bMTL6UPp1Kc41QS5EkOliFb/hBIpI598iZnnxZiFo
nswi53iePFr4IhvL4XCufFkfN3Kjf1ozXowHvE9PaNfeJyKSK3TclZgUUJB7DxEcXSrXqocyxOmJ
W0rkdt8E4XvSQ9RXnGw08moTmC4Ay/Qm1Hk4VROcz2C5M/BEbD/z3r3rCD6G+I39slabSKb3EPL3
yrBJHvH+XBU/Og2/F6Y4BGtbmBqc+F5Cbezzs97Hchh3W3YUs4BFHq2a++VcEFyHwTHgMli9VaOY
w2XwIS59gPOO1G3+YudsX73xWFwLxSGEqElr5GNcKSybx/KUKP5fuA1KtcxvUurdTXSeBDqf/vsb
KDBcshsTTQzLHqcmaC8u4PSTzQ4l7S73EUXoM9h59/9naeorj1kALVcSetLAa4LyKoKpxpfrlObn
rL7OH4Hnjr6Xt3C5YcPxh2yGykFBndcoUZYxzNUeLBqBjfYju9soiqCkwcqCDBojqq/Z+t605AzQ
PlXjKhmrcz6ds7eYwO1u4KMZFAC4HXvTNL25zDJHkxcTZzcax8gptFOxcmyBZ9nafcZZ/+cu8svY
5OGfVdRDFOlq4Y2nRCAxb5++FTVg0oNkMP67MsAoGCTGfqFHS0mrScicIetb/lC+TbNO+Wx8Nuvo
jOhSu7tAZH4FwoFNudmSrlrGXOVPDeSb95Wvl1EHIVJ/Bt+g8jHN7L3EuP3iYbeXKJNzmhruepU5
/9pGEYnfaVZv1EKuQD0tsS2tShyClZNZ02zxc1YKjbJF/98+1kndtLO0JqmeBEH4rtJUuqe7mh2q
3HpCmfwguA144Kp23ARkOQKAzTh6YE6taVcJGIZlE51FSZyJS2qaXvOUgyHmpQhhl+Qxu5eRp4CR
QgzCw2U8MoWaz4w04G4jBnldDEQkY9jZIq+iS9RwoHGYNmHbhjhRvjxbtqzpMvHb/qKjvHeLin6o
DWEUotoR4Vrbzse2tpKJagIlmH0mstt5BRRPIFMWwHml2VAoln6STdwmzqHItJ6M1wiy2xuBiMOF
jUrBgmufBslF3pAgUBsF9WfKVFnAL01FY8FVdk+WqWK8dUuwLxslJ21FehhfnaDHm/mGR+l/ZIvC
5OmSQaWH27vJT9tlaf+k50s5SF5h9+2C39bKKqW3vSiy3QerLtGmSi6jOHgLfeJPXps+f10PwsjL
fu5qe3IpeezwjDGOXOD8p2CFbqt44kw+23UtDbUfSrJ6wAs7MWNTdUpltMm4hBdW6EEu4Azr8eaE
rOo76O0rP+ct2UXu2buMDccPuOXRwDdptZvw8V6N/qk6ER21uotJk6xKN7fR/Qy19SZYyc35NF92
oMxdadmKfm9fstBbj1aQUG39cPtIBhIIGxUtI112wstvH6fdPb3Gc/7kf2XsGSSawaj3yusoei/d
aYxfLFPeRcORl1oie2nUPwgrzeGcVBicSBcOTGut38nPCyDBKgPPlqUCYDAlWL6e/O/F+eo3HJ8+
Pv8/1ZmfjG24OpCOUChEp76UToTNv66MkIZ7mi/n1fRYk0B/bs7rZytYIgOZEqlLQlqcZ+uKP7pF
gp8kYzRYgBlskLTPWHXesRRfAklL7mcfyrb+kdJwBKowSRhzpbaokwK1C7zDb1obTNbfnr2IZuMC
4Jkve0+vsuZsZDLKWVrVL4gtmEcdpo9dQ9QUnMKbIjmaUtwMQgSCsRzJJwYy9GWDRS4tPB7V/uMd
WkiXyEPITTQxDOQV5famzC1g6uwZeGRNXKKl6Xf3srI8MeJDEr24ifgrZI5RhWlgne7gfOOOHcSb
cfj5uEDoV9nUeqKBPNQCGDJKzKNK3U4UWIUQDwxcby0iUIXu7mcRrPVQ+i8ZSIkNv7uQ63qD8FJ0
0PnuAovE/oecSIx6Us1avEcX7YzKkqjLUWgs2LZOJPMD6dk8MDoMo7ysX5Sl6Tl9JF14RntPqd5i
2mOS72ZPwr9U6SOt4tavm4B/XYOdmY3LdjECmA+G+O9xhvQeiUbpMmCIQGaQ+JLdC43Nu51CMH+m
bsHsVrUO8pxdQqrRm5yGNtBFQJqdg7cWayjf2D658JcIp73SPJd2nsAV1KXVI2I2++AhSCex0spz
H0+4Xjq4I6wcBpiB9ES5IPwBRuCAU+KNF7cxUJfb9AH4MtrABYZp7EUgpGF3kkDgbIMWWy5kI8iQ
gwoif6mSiXdAR43lYDI8ydMmi1P+QqvyE1uwf57rwrXcT9XTolTEyHeathKbcF9H2e/NusWFssxn
ZAsHucSrjOtuhevUZv1j+NFO/tsWJEgQUWwHFUSHl0tSZJr21Jtv04QAXDIe9uKviuEi8M1Zye2q
VIB12DuPRPB5Y5ZTt6VJEynbZczesS1k6ndss5lIqg4YxeC3iPwEQtab/YwbJyKTlDFjJ05Z3I0a
5V+JL20SaQEidsS8+tML5OVYqOF+X5YAnPAd46ujVVHrWIUqpcTvJny9iLXWMp2puwu15oYG/J87
uOBUIg52PONeRo/2ZROHRSCXUnPQQFvIxzzNph+Jqt5ZIXMTZJMFegj5FhwuthtnL7o7o/k8Lyey
YgY+A6AeZeXkPNrO3/jyNDHcx8ngg7j4n4zOIMOsYL1Eq5h2QYgfEDCRImFX+a8vMUUFhFzlUq8Q
+YnZ/g5GghVy02e84jV91RSbdXodjfxIQtHYXE6WajRfQd9Xmc3BRk+8Uk+VlXiEv+gFdtE1jMEl
Y4J6vlUOaVEh0nfexf06/T7jVeseoM1c9nznKqaRyS5cnfLG1Xc/l4idfhct0jnfD4xyo6ztKKc7
ZoWW//Ob3qeNG3mBXNZQUJMmhE2P89DViTozT+GQTzA785Y4apmPojF8ZI66ombhB0Bej2RInX0L
Wdog3njTuUmLQllhN8s0QQIfhHteB+eIH8vSm4vihPzrjwPyRL84uuW5TibDb8uA3j2aXmJ8sARQ
ijh3bM9ltfHOSh+gdfA2CwTtjpCuJPY18zeVTbwrjKjXjO5I50Svt+1f62XsFYJ7w0IzUqVuGGKi
IQIkrQLlKPh5bBbBhVsC9dBjmkkRCGBuawHh0VgUNV1IjwtHW05jlfEyrTJWjUlntujZrtGWGc9z
VRjyV83unGC9AEscKVLm7hTcgw1Uejk7JhTYsWrmnXD/2yniLpA31qEtSZdL4A+bEwKAKbWiQxsG
COwzFFI8dfZ3qGevBY8aA47DZ5uUd0z1t0IeSunBnsNh1mnMj3oOS89PX0dRhciuDE7dbg8+0tBW
9EmHn3PKRmNL1ipXvHIIfYuYc5Od3somla8JnQyl6jBAle2+RUahuA5yMVZLiJ923n8qhGYa7t/S
dKPTiknun9P6w19cPSXpI4v02Mjg5ALkLsMe+4Y4TqElQ07w7hiHGsu7EYCQzpVovud5f/db+g1b
nI9MEUV4/hYX4rVfPm8CDe4KkNvnGMro1E0JXv57X0O0escjc2QvaFP1SNc9KVhyZLJ3lYvDXd3x
YVU8eDke68BRejyCkl7EsUFiyPvyFYF6Vb4XpEWRIiW+qCj2eTK3JY3aS5ubeehk/Df3D3xYofdw
Ps9O02/Xns/UUZj/VWl3GeoM5uK1ckObVDlRwnQlSIa8X6EKAtGbeEyKDtZ/wF9Cd9+6zByRakKG
yAZ0kiS0dH8wvu9JtejXD0Yu3vjX6UgRJprZ9GYUKRN+1KYS/OlJ7wFri824lniD6LCqZb7L0BdN
l4AQ6kM4NrXLDT427YeMNGPoE6FY5QyFuqPLdFUJ1X71o6q6ATkecmV00kaGAk2x2TwwVpfHHpTj
Kab4Xhl93ic752GhbFNJw6BBquu6DFjJEenEJKGIs/Qq5lM1W9MQ+OoHd/On8K+ThjECiWzVBpbX
19ZnKrWbyfTNu+idotUkQRkHnMZfO1oe+p4eeCIPk2f4sRaxVoz4jtahxDdZzrqbgs2lXrQ+h92Z
MJ4JqtyCA2LWlrYOiTgfV6jeJnOT7p8EqA1r5gNMMf73uzJqRhTbLYdhoqY1V9brJqIelEZGwlIV
eObr7vF2SmXqVv+D2+vRjpT9sANMCBFzg5JJXtAYiHbLFJ8WXPAhwsZkuoP/a4pQreq3LHnioRRA
NlirCIpTHWBjIlScqQefBKKuvJKIAZwO+0G5Wa9FG/eQwqM92Ugne64Czm5BwKe1nXlS4MqmO1um
I0b60Gb9nWnTtKFce6YOmmSwUB/FFOT+muekdItDqFC6AtF+AvtUQ+LxE6jEogPrV975od5PONSK
1XCKPqiO75OrG0GvVL4W+lvNsSWCkx5ezq+J+I4ba63UyxL0UJ7ASgXjyUprZVizgkZujeNC59rB
YTyaZRMVtLjriqdEgpHVnA/Mp3OaA/WJJuD4XtLIIkizKKnJpII+saXW9Tzz69ET5zQhZ2lTxjF5
bAPXtnHSYBcyt7s1Junm0aBhPpsstcrQt7A4CDyX1wRNxsrG6K64S70LNtZkzN7p/toH2QOd1Ntn
vk428QrP2w/+RDHCWuPAXKJk1GKTaYFb9o2RlxWMOf782ar2knfS5VHhd59BblwWY0nW2IA61OCo
4OxPCxRPE0HUO5Iq4wg+HMth/Anm8AdPmfHbIYvwHtItB+bqDht1Hr5pQkOydqpCJvnPvYtauzq9
rTq3A3t+nYHY1Q9lwG9WfMcGaK4de8jHn9WrrkEwVnnLj21jZlnV0ZxET7ZlY98c02e1rwVnrWr+
Je5t8HKCBYOR7JCv6DaVwvNIAoqVP51AsGin6sd9h+HhA6aVypIaWjf9tyloV/NzduLhvfjhcV66
WNNxNcgfaDRoCt8Ryd99nsYqwm1v7Tq4EtN0gtX+WoGxn4zzDoF8M3R+yb9b+7YNchfY5n5bXQFn
MCE3vBHAKjWg5uk1qBr75cAu1Qca7g5K92MfGhc+jnnTTux0rvAu8+tJ6X+Edf5DHKiflbQgiG9J
7CTAsB9Q7zkjtJcl7OcPuHTk/3LAHhWdPeIm1LX4NVzF/kt1kI5Vptuu12DpHErhezSs6YWCLAr9
6A5AUIXq46nPZDI79z+GCMgY6Do/KG9RHrttH+qyncHGFhJFIJwAGmHFyM4TXAc56a/ioJI75zBa
csW6uOhgYQo1rVjjGg0JOHgoL2hiSo1cgO8FbaYeABImPoC6h+UmyWIrHPEva8RCDqBIIxYacjF3
Sablky4HqOOqTH3Po3i1W4hePeUWVfmiHqGg+rRQvXt3I5KcOa9BHeP8PLH8WbZnHhybI90AJW4B
ghGrLgpA0BouIjoGXWb28lm9b1cn52FbIvymS/YVDidtBow6phD7ORIC7RN96opz0bgfDpBsFfKk
C1g5JN/wmgOIQ0XanlsorghXFG/y5P9M6hRDR47vsyrhrmea9/a7kEhdCuFyvPL842LMx+nKI3eS
FvJtjqUdksjTtLmVF8b8u6sqwU6UFtHtD9r3ZhLPKmoXtg9KfoRBC245DQs/EvRySHvQuseOcjXx
5RkzTTZ3jjy69kCHaFf8TsIzpmT1k2o6SeItN2z/XLhHF+cOKcMNTrOPKzOndIfCrhVvXL1vUIfY
opdi/RQbj0WYsFBlZxN22CeeLsqS/sFkzosL0tk/QrsDCAW2e5lDVZfaROYbFV2DVaBtCaPsukxr
ii6dJlm6iBgbH592u+f2mI9ze3K3bpsNH3CfLCIYDDI55iw6Qwnxg8cyeNwWyMIdLanykfH7Ju8c
ZcGGHpV0gE7uf5qc3HOBJHrSdvYc359vywTxDuP9P+SJDyx+t60gzygUEutg3fdY29j2wgp2D8A/
gRAG1SnHdPc55yCIzkndYxPE3e9z/tEfzN9bpWTkjECzzAYAeBBClkKk4paB5YWIjvLEVqoh0jfA
ZVK4BErzQihjWblDamZIenulFel5DULaJy+tH7Htt7XS99+kxeShV3OxFaxZmv2wZlozcdBjCWZ+
ibrVwA2Fw4qpfd2/mR9C8rkmZHFEyhlqgOObFsCbVRVhAPifX+s1OAHQnzvqqri2oe0KqyF8nWeY
YkcYb/hkSqPmV/mUoM9CDDcgJQ+MssByY5UZxPuSg35Rlo8SrIeat1xZbZ1y4R/59kJonl4hERMX
KzK/D2HsaS6LuWMCBBAk190mDb1DELlboatAk2U+ynZWeDcMUgeu7V2MDcR+56IG1e6MK9vMw5p5
kyb4IC0NudHIppagDkhVyqyMLYHhl4fbHjw3zJQwP5DmLffEb5u1TgBzbzxhqvOlYpBCjrIXvzo5
JSFcaTA+aXCzM3WWjZeX0dSP3MZV5gcz4e6tELgJxNQhelnifyxFrqU+OJYBo8oJUKU4sCKPafmH
2Dufn9IKryoxUA59p75/NZadSANaqUvLXoqQoRVrbKBRrK9TINJPx//uJsJ6S7btepIbmQmJw7Ui
lEkn2HbtLf7cwgdXyCjgKBL9z+onHs1P8Q78w6U33GSl3kyvbK8KJhTDTcEvB3bHQCd4qeuM4ahE
gk8UNAIAZbbTnza8Y8OhN+gGthKNYe1/+TmfuVD5AB9HbsIB8bazOCqKyifB+eGZVQtn6uB7ShIW
OdpMNUZuhaxwTq469qaRr8EjNS2xE06TFRrauI9CRpMBCBZNSFyTIssidoQWA5JVHGO6eqyXwfgB
vB2BxeV7SQGitHtabgdw08LzDXd6ctJ1tKT2OCht/xesY4Od6hO3ra+xvEGINCjT8XK1s9Q4P4u7
R0GKZ7oa3h3BylbAaJq5fKMjRqLGkXFvjWMTc6rhESpWck6m0TlmfdsXflsCxYWLEibvVDaevwsT
E+uA1UOEjCr+SWq0pClD4fxV1IqCSIwD/hgVnlpu03nhBk9PDfmrDaSeHLKm/uh4y4ogBCKQtQT1
JmW0IgNIaA13zSdQN6wD6dryxMF48Cc/THO3QtA3vl5svNKVWk+mEYu2tNApzArCa+Ifl+x58cC9
9RTOIl2fc9Gy38ArM6S39s+PeEh96xUGVCbAueyKhiO75V2yVROYvgGkC6Qi/KAqaEirBS922Zru
Ye+TY6Q4phjpf/CHGsK0WpRIwokqgkhZ14OC//k+ax0V3DhAJqQ/TcPI2ooG2EpPNdNPYrcXwXRp
9ck4cTWqITnoGg4hzs6/cxrjxIE0OhNYgLKht8zL35OZrJfHJ+KEVNCyOw/JMRpAsB7J4/54DcTW
FsvTSEABYu0I5LqKvs/BLx2tmmXjJqpjTFLA3FqNOPrrfhGkaRxQtAytJKyZibGWAgx1mzNrsrIN
+C2npOErzVY4oGBuXXV9X0qmwkQ/aU7UIyKQa90gmpax3j16L7/R/v9Do0W88WlGrCKZwOiEWfce
kh2fzKBoB+AJHxikJOg6488LLmaxBrPcA4O77GNwoOgWKufHrGUc+MJpYZhzJJ1I4O0l026xoXXo
LfGceXZT/vdoovMcrGf91X099uQQsDy8jqLLziX9f+6qIZUHx47hD4ECXJXV6QyY2lQ4h+gJiOzW
hP1yGVP5PD9jRurrtxcMEuYwQsmIPutHpbt4inFagIVxVX9BbPqyLsiSsfmKkGK5Kui7tWDDHIA0
eBmaW9Xu5hOBy1+qLvCOIPX18643fQWKajUy9kWmB+s9itfVOFuKKshtG/SnRpe5Wetoztp+kuxH
OHaxb4zGcDpebbDjrU55ej4pFpJgg38H7ljkMiGkkLGAn+TwllHeojnqM2mghE1tPG8vjPHD+CMY
uj4exjB1GU1JGByWyms9F0oRdvKliwlIQ05hpPAyMEIoiHHg9hkaOoKrQ+U5vQVga9ofIcH0BZ2L
TEFBqYxtRkqi4yYYMh5zLQ+fJEGSVs0ajiLIwoH1KKmaF1eErvEW86s3d4unJxkpkb2QxBqkebLv
JJIQglskZ6GmqiO9cPpVueo8cyP0ZXXzO1gdxrpLVKx+QPyPIwzRP/x/j6EEgh/rsVZSK81enbkK
HThbYw08GTi/RjVybS7QcsMrMB9FbuzEEAyWs5XH7NlXRTzjwB+huO/s4/BtGuaYwfvD1cXk/UWd
nqYfKzMwtaat+LQjmbPXAHvLdvRbtvSLJLWZSxVURGl8Ez0ZuIyvn35lFNZqh6I1QwAjFQ8WDl7S
9ZuT3xlLkSzxUZOUfC8QdaYV+oklrWZdkKm54M9bfeNQfeRBvylbzdEuIbgkquF02UOH9XJUquuS
Sw0qNuWzAEAK4rLchd4NfuCGNl0J+TSytnoQy/XzF5H8qSc2SQuA18fc0o9Jl0A+dm/ZfdbfMPXU
XLz5bFi3TQ3Jlc25v8IJaoN744m0G+vpEdMPPYrqHz4sXSbIDKbthpOcBfqeTkf+lAq7OG2e0MUm
XWTkWs7LMG8gLWzgi/QEryCMMmbub89tfonU2WLEzS8DyNBeXNj60RV1Xc+d0YWUXJawbOTH9xSD
sg3FK1palRgTIyTAIZm92pZlZPYnu7Roff/MBsVfIbFL+lryo+IP2H6+RyijU7aNlpC5ckqeJTOa
Lah7+s9892HqcXgQ2r3auRNlgI8Sk937dlmT68UjZdWJpi/HLmrCNTVCb+vmctVvQppEusxvG0Jy
kpI1bkdgFQnYIPzTWTODGyjCnghdoRX6ZmfSmculY9PnrF5vJGCSgOpDbZIy++PoYNN/ca9pwb+h
TXSnO9khtCRrt25rryyYrr9M+bUWr6OIr3ud8EaDfMSVCzGdNDBC/iJPfnXYTvdTC7/uWz9v1woz
pGV+m8tzkZjzBHRhDO4CeGWSR3/5H4K+KIHojAT6sCVM1j1wAXZfa0bBXCAiP/TStnZ/UputQgoS
ESPZIVRO4tMkHjNqhPLr0XwO8rmlZK4ejmOWlsYJelRZ5iKeJAKOfD6aTOhrR6Gt1rmz1r5Oe+86
JZqmDk25bLMoZZXMeFrjp81q+KwjxgnVSThF6n87/Z8Br+h7sRZZcjWKBi6UhB7e/XTroPxTNudc
ypLjHedZkWxBnpyAy7HpSv+YmOi7nVDh8opsPlwmMcnyRo87+NKEbI79LVlM/l0iO6Fcfbbm28IL
nQbzcjckRBPNb6ERDo6fOPb+NfdVhDlHNy2QeNc72nI3H+pKanVLjstwurg883OZymM6m9bYDLeX
vsRwJernuWDwDXa7KqyJHa/B/eqqMJR/1CFDdfQzfPr2GRIkx8E23sCVgfEYC8UpQUMMAdpg1nAR
ykbIzOa9QJ9c1RGx/hz0fQuUduOb/a5ltvxQRTySNojTlAdncANN7ewSXNJs2Lpp9S3d4j82cMbt
1o2k9pl3ngSxgOOp0fm1HfKjaX9kRMyDbTq7WsAGxwjV/c9nCtmsWxIVGccFSpaNqMYiusvV/0es
r1/q4Fs46kQDJWoi1uyjoDOxxhok+CLmhPVDTlI0ZZr/Y6cwnMuuhks14z/R/YocI8AkGVW+HH98
VsLZNoQIFlcN/SgbPdnaB0OsGHWOsvLUjeSVTFgi7LhtyP2x4scEDCFLfnlspPF3GjbefjIiNEov
rReMj8XKZIexeb9IQeclWRSwXowB0rP1imG+jlL+D9zOv1O8cOhqhRloK62IBi/Wyv9AkmX7EBeR
Z/8wjNay/o4TW/8RsdNOT+8ok/J9vIn5ggctes7WCP/nFkP2WAM1nABVzqyPW26FTGgOCSJ979Fk
x0toxJdlkxb3v0+7lyz1sDv23dt2MlPHqAws1fLdkuovJoKkZ1dlR2NcYCZZPhXjWgvzzwJHlOsB
8gL1IRBL+zYIREP6X3E1poTEEjOq5+tVhVW+WfQBvn6K6xJfsD64LSuwqrVkS1mkzj1TvHxBgRLh
IitT/JuCh0BbwOpt8MsdRQYSA2wJfEG5LoyQsaPpqn2B+WY+1icpU894ty+gRfAAeoIMfCrYMTC1
QY2UMBEuTUb73zaWP6Q7x62Y1YNaD9XESB/ZqWcKT5vIILi9B7TVW0E85E8Hv31PLvY892k8E4LH
huoZ7k7QPkNFdr0xNSSCxH4kgJAXcKrDZ4VTmOLFbUORZFvFEOI3nIV1LRkpvMdO56DWOh4JH78y
YGL9L9QZzbHeQ6rTMNo9CVCa2A1E4zR1SamoBYYtCyzgYKWSwI14selgW7p7Psh5CPcPlQga6rx7
VW4VzokHR07Iq4NniBqqYUCd+RzWwmALqHgpl2U+DVn+4ESKLisI20E0cY5g/ZVY6kMwIQuqWbA5
m+vnwg6f/GJp9gaLfGgh2zKsfvBeHq0XmFw6IQsZst3amWm49qs4uc0dZmuBZkmKK9aGbDnJolL+
+HL1kGBLZUO0+fJin7bYrRHIFYYoZbVYSzy4yX9TgenFG6zYnHS/l16hWZqqfSRzFjgyVwVKF/9E
MwnqImGOVyQ7J+n7uU+AAdP4VR2x3Il35Dhkh6+alwEtB1s/cSs3aiHQ1RKw82qd7N1hEs9lBkW3
BxeVyN8cfAPsmg5mWb1ljOoSb7iX64/9fwuvq13w+piUMxoRXj4bYRn11EPIg3sNkwKXyMx2KJ/J
kuzsGL9ExkUGmzH1Y9CQj2N4Oyx9zjq71VmAzX00Ej6+bzJ2aklj9tv+DnxVIyeoaGvH+3XvFMRK
X/BWsc7+QJfE3eyG9N+YkeZonu+cU3qYTNL+Bw8yamX5zgP4v0k7wXJvdZzCytHB4yLj/F0rW9jJ
arbRSAbHAjCJ6BD4z4AkWvZiZR4WnQ/KOmkMoQrdHRkVRI1QJSXEc55t5uJKmu/GhhfGWPg85J1e
lJ1J3CCFS6e9fG26WV6mYdIEsdKlIKbQjD14w8Oy3KHVczWo9VvKAH12y+g0tdLD+Ag3uOOls7iv
LQy5AizOtPdU7HV1W4NNyWMET14SXbod/LE65NMlIM6jGc8ER0lIKnUfptsVKDF02RLR1yNhn/d7
fmlnhLCRMM51bqDQvlLiMocGsFJCzKw7HBLsASom6Nd/fgRF8xvbwDH7OUsncfeuJiC7AZDAdViq
rC/oB6QwI8TA6CXGAhiI8N/xzptIZ+klEWze4ENMstSH6LlbbIKf56od4VvTTkX85X/P0xDc3Fub
daDexnB067MRkmm/eupSXI9D3OLHr2rPzD9QvGe9/w9P/iiD5p7V3K5qgVcejFTdeYoPYsNJ5bwK
HoN2SRwb6s9WEHPBNlJi+Rll4Xc4vxclzF0plhYWBZVMtDEyeGRNekfz5VariivlbvA3ZpLA2Yzj
lkjD3EIraEnwqDQqT6bBMTHD5sPvIaRuokoYdEqiaL75ZEY0ZDhy4jKACuS7prqhn60SoXMKW1xe
LsJsUCgdgKkCSe3fSGkAZdo/bK7crQ+mqvsbtjgE4CNOxy2T2ZpSnJBhTcVPvhn8W1GB+EjrHIfa
RS/P+lvWENV1PWi85odvoFPP2VWxqeNQ2lLyii9zzMmYNbMhJjF087p6IDPyNq8HwAMNgs+l6JDC
tbOGYt9kMB+czH7rbWe3xWp1yavknXF41UVkrYMYKse5LVvQtHlZJdg0gtfoaR0vCSP7s/6oeFjP
6BIJ/FSAyeLSP4ObMAo1i2124f97gbP+7pMTNSLNrLv4aZD9XOmwvtdixrMAQRZscsyTgF2h11Ue
Tzih4cjJl4bqW9gJ71sWHEdHYruSGcCbrCe2KbJA+9hTSDsJtfdXAi7m3bjL+OUQ8m8Xf9Cfss3A
NWEuU8lRIeO5VCOdZKgO4R2RB45lJ7NyUL/RafKZozgN/i8t0FX+cklls4L/vu87i8A2NgY/Ok/K
3690T9KSdZxIO6OYv25l8k0HsygockP4QhDUPForiNropyUUsbYER3yeYZUf2TYlpEagET75rRI1
2PBJSao5eRsqhbhT14V8Zv4HYxv9GdxzVHZKF86QtR9bEIsQnxZ0YTsovwVzaRWMTtUTedn5PZ8U
JZbkNq3zJUCq+n+TulivCxdBkTIsorpT7+a/+2M32u3M74kvXOoDi3emCYm9IuOFHwaGQgoMdPmt
lW8iLuKKqy/MccgXLz7JfJnxYz4JwhvY2IpupqxdlsttyuXfqS07tOCP47d4edKCH9D/W49aEMRU
/SgAFUdOIYbREO421ZjOopEfuA0eR5ygDSkQf6dGw03b3TGsVvxwnhKERefF5cUeV+Sxz1KI32WH
kcYc6zgntxT8eRDjhp6d2yWx0v/ysZzNgTgMeB7mbk10kpnB0b7h637z8iX46sfMXq0JFomI76v2
l8I646CEQatWvxmakVWdrcQ/uuVvFvBl0OfhYsbgPw+tuRiGwYgzsFjSw9pMFWJoKbvHZstD+7h4
bWH63Vkm2yzLSoks+9wPdCLqKeSvHGA6C9Q5djsKn2SOlauVuRIQyqOk0YG8tIW0Eic2zMUYCCIt
6lz12rd/usiO10p7wiIvGXidb3NLI+MwWhWAYMCUG+Mgm7APMJbbHOm77fowLz5zV/Rs/6VD4uZV
nvnxRteVagtXXCkiMD5W4InZgvq12Sj8hppvYJ7oott7UM4jff2ziOSUPdiu6nhrLpBhi6dzfLec
ot4eLfgPVkW8+xV2mWAN891ji+mc8QBINhSAPLouZJ8AyAGvO83NB6GnQM56MFpjlaYJS+4TFJ93
NTLyvmPInQyoZOajtGRhGlsgdnvEdXSPAUQ2BZTgameaBRs9LsPEh1Y43+J1uyRI6fXErGCJPg6U
9efqVgRobI3Fhgu1eItNuLOseysDprIlxIz79z8ySo+1XLmsZgKp0QFaX1Fhq0wP4t481WIgy/kj
/Z+FAPOZLJbUG8sEo0Vih91S2sql0GY4yORoVZ5zx3JHiffCeCr1tLhT4sQRlwbzY/y1xSUU/ZDN
XzUoPCRrTHxApvYqOFPT+qFZ+vi/UaAftQNDVQSBzxFA/LxopC5pJEVi2mrYlZ3oueUTx3EHOp82
b2LiDk6UPnxZH0zdPQBtr13TPjTgJfFL+FVLUvzqeOJDwko5RYaLmcGYxeVa2Gzsh3rNW1KMwvfE
c6IVV/+g5jTz/iHKpFcOWclEqqn40rAzHXQ1QNuzXzKAOicqI+KX32Irf2QVTl8178biX3+3kusr
eFOsv6836hr3DjTNf7qAkGrCk8lChd3V9iYcEOQZ7KRDykBXfpGU7Qk+8tzpU+r1cj8AQ4+w0CqA
lDlfONdv6Nk/fq/RAHmVhX0pd9fckbonJAg72zazCvO4Xn3kAZdp+2Nmc5UwjN+U3egb74FuPKGM
NdTRLPvjQwMoP9mg2dNVH5iC0QWcY3Dj2sYCg/ALXxG7HV03UFvKZ/AZKssA47IofJ+Pn2oO0oJ8
w4ylFe98xloVwyv9NESeeVPGuYr+KirBJ1ty3GkCRF2HW8tBsSz60/QeBMe4ifhzlJIMcG8FKV/z
BqXUDYpO/W5hogGEpE6s2Ti3NfXxki+jXlRWo6YVfhKkLHMH7SqCFx+c7XnrYfx9YP/DSwPcT83h
+k7Ciey0cMYNVyFtdbOG1LzIJM+5/rCq6X4w8nlT/2ExfY6kYObFismDI2oTpszqR7NiPCpD45P0
z5qRNXEDcdzbECsgK06+0jf0B4a6V5Yt2YlUklRR0IsD/51ucVvAX+yUG9X3PcyOsm05iBRlIQaY
jvd7EOa/cieRbu5dBACs/2C8EQfbzPznfYNV1mvXkXzSXC9q7KXPzzHOsug0GCgxikCMHeTXHDmX
lL24pW6pViuELSQW14IeZZxhh+28/ciZ8iJukv1vsh40gw0E4hMC/XtFUx2kW+gPrwrsT4brWrW5
imvcjRWjPCOdNe61DT8u+PvRBAdA3kGSjbHEHF/tgOfmW5EFLavF0osXZkwRbVsnEmpR1Si+ISbv
Zozo4j5GHr0uC7CyOrugIVncIAJa3AJY/vX08GlV6CxqJ6j5HbQLEpRF8XR2qKA2xhZwQMo9N0mi
2hKzfoahmkD0OjSTbJxfo7jJuODAYAbfFFb/G+5ieTbpdbqPQG/iDpl4XdBuq+J74suA0IQCxoV6
UNNdNPlwdxC0jxh/0mFkfX4poLdzkjipGkvLLWcoBhAuWUSH6ocifFwdnbwkdljh5BNvq6gHYQmO
K8nfdbpy4Eonr3+G28XxsESbTV9iSSuaWQq1imTZzbO+mqmRzOJ4GPUsgXttlFI1eQiFaKRCJvCF
T5BE5DEyHarpSPLseU4oTx1A7lmQT0WLQ9SCDRfGO19O4zSfERrpSJrO0U/4OA7EUmm47WI7aB6o
yjS4BhSJSyu0YJQKBr5dHOOJ77XAFA9bYOUROkWOtnQJ1bKYoPvTtFXkRKWzb4S8DZWysF/N375s
gsAWoSsWKLzIJ1qSBoo95UJi0moAplGlxIyw3il8rHPqc6GdqMGlTc4ZzhVFiQfep5BR0KN2l25v
L83ot/fSeYjClbRaEiVGD9YcKXTq+PYuAzHNNhv9SywOmGwHsEmMASLCYdb7uuYHqqJkYVpbyirq
YuYyBDQfOni3tDG9iRFiHImfYnygq/VjpSUSBaqH3QxZAnkzHkHf4OJmn+IsR1fqL+KwNu3f0gv0
19OlDizWlWlJ3e6fsHAvY3nPBGtNaXHX7oPtxyn8ifZMWSHnIYD/WyDPBLo82U38Z+rf8q0raLPn
gha0mKz5AGniZcghzxRzl4cs9Qh8BhtD4qPmeWujP8l9/i94T9r57T/xugHTa+xnoD4N/+sJjBB0
C2u1OIZTbKsp1UEsZtfcNrNZQuZKmI7zaSfkL2/Kytds6DAO4Jgxz7uP1AxpcDwOduZrqiCXu/ai
DnVCs6FQkKNo81nmYR5/jkX3Lq/onKY4EZguAqpAGLZnyGCkUIgmu1cAE722m7L1Vn0TZLPPVMCI
N3VmF3BW2mdpG89PK4XoX/dmQIsqQN6h7NF1VNAk8DaDr/AvzmN5xxiH1YXwbd48aP/n9QW3Exxu
ohad+9GfvHaHaNarQw+JdZQOvo/h5Py/O2sZ6ljUQKyyene+AlhFSuy82HHny8mG2Bs6gKBC0Rjh
3hdGnsrdCJOetyIxCfS5W22xEm3c71sw9ayszKSa69E+Fc9PTbyWvGw3ATi0H76drtI90UGZ/lMO
fpI14KeZxrDGAhOu9uGsz17i1mkNPhEZs6ul7EZVvqWOZsMM7kagdHCyeTwye5IMZVnmTq3Q8Xwe
4W9lMEwrY043Ne/PRNKes1kU/+ZIX9DrFtWqirH9dFEeBnuy4072kf6RmVr6SO/bo2HUso3ZQNHp
WnY6TTvUrJnoDK8ryAy8UcyOxHvfab0dN2bSkzyWHJ1xeY+kDyWgoCnNNJzH9t1o4dmN6AhC337g
jVIu8YNIa45p3DwLYeN1Fv+FSzw/hzYpZMcM3URadSuYVQkAKkomh8LZxX0D78pcjJlgndp6hehi
bDjKlV21uTrJiR5N
`protect end_protected
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.all;
use work.procedures.all;
entity mp_indirect_fetch is
port(
rst : in std_logic;
clk : in std_logic;
cmd_in : in t_vliw;
arg_in : in t_data_array(5 downto 0);
mem_addra: out std_logic_vector(9 downto 0);
mem_ena : out std_logic;
mem_doa : in t_data;
mem_addrb: out std_logic_vector(9 downto 0);
mem_enb : out std_logic;
mem_dob : in t_data;
arg_out : out t_data_array(5 downto 0);
val_out : out t_data_array(5 downto 0);
cmd_out : out t_vliw
);
end mp_indirect_fetch;
architecture Structural of mp_indirect_fetch is
type fetch_type is (idle, fetcha, fetchb, fetchc, store_arg);
signal fetch_state : fetch_type;
signal fetch_state_1 : fetch_type;
signal cmd : t_vliw;
signal val : t_data_array(5 downto 0);
signal arg : t_data_array(5 downto 0);
signal arg_r : t_data_array(5 downto 0);
signal addr : t_data_array(1 downto 0);
signal to_fetch : std_logic_vector(1 downto 0);
signal to_fetch_1 : std_logic_vector(1 downto 0);
signal memchunk : t_2array(1 downto 0);
begin
arg_mux: for i in 5 downto 0 generate
arg(i) <= index2val(arg_in, cmd_in.arg_assign(i));
end generate arg_mux;
state: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
fetch_state <= idle;
fetch_state_1 <= idle;
cmd <= empty_vliw;
to_fetch <= (others => '0');
else
case fetch_state is
when idle =>
cmd <= cmd_in;
arg_r <= arg;
arg_out <= arg_in;
addr <= arg(1 downto 0);
memchunk <= cmd_in.mem_memchunk(1 downto 0);
if cmd_in.mem_fetch(0) = '0' then
fetch_state <= idle;
else
fetch_state <= fetcha;
to_fetch <= cmd_in.mem_fetch(1 downto 0);
end if;
when fetcha =>
addr <= arg_r(3 downto 2);
memchunk <= cmd.mem_memchunk(3 downto 2);
if cmd.mem_fetch(2) = '0' then
to_fetch <= (others => '0');
fetch_state <= store_arg;
else
to_fetch <= cmd.mem_fetch(3 downto 2);
fetch_state <= fetchb;
end if;
when fetchb =>
addr <= arg_r(5 downto 4);
memchunk <= cmd.mem_memchunk(5 downto 4);
if cmd.mem_fetch(4) = '0' then
to_fetch <= (others => '0');
fetch_state <= store_arg;
else
to_fetch <= cmd.mem_fetch(5 downto 4);
fetch_state <= fetchc;
end if;
when fetchc =>
fetch_state <= store_arg;
to_fetch <= (others => '0');
when store_arg =>
fetch_state <= idle;
end case;
fetch_state_1 <= fetch_state;
to_fetch_1 <= to_fetch;
end if;
end if;
end process state;
store: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
val <= (others => (others => '0'));
else
if fetch_state = idle then
for i in 0 to 5 loop
if cmd_in.arg_val(i) = '1' then
val(i) <= arg(i);
end if;
end loop;
elsif fetch_state_1 = fetcha then
if to_fetch_1(0) = '1' then
val(0) <= mem_doa;
end if;
if to_fetch_1(1) = '1' then
val(1) <= mem_dob;
end if;
elsif fetch_state_1 = fetchb then
if to_fetch_1(0) = '1' then
val(2) <= mem_doa;
end if;
if to_fetch_1(1) = '1' then
val(3) <= mem_dob;
end if;
elsif fetch_state_1 = fetchc then
if to_fetch_1(0) = '1' then
val(4) <= mem_doa;
end if;
if to_fetch_1(1) = '1' then
val(5) <= mem_dob;
end if;
end if;
end if;
end if;
end process store;
mem_ena <= to_fetch(0);
mem_enb <= to_fetch(1);
mem_addra(9 downto 8) <= memchunk(0);
mem_addra(7 downto 0) <= addr(0);
mem_addrb(9 downto 8) <= memchunk(1);
mem_addrb(7 downto 0) <= addr(1);
cmd_out <= cmd when fetch_state = idle else
empty_vliw;
val_out <= val;
end Structural;
|
library IEEE, LFSR;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
--------------------------------------------------------------------------------
entity pulse_counter is
generic (
G_counter_width : natural := 17;
G_period : natural := 10000
);
port(
CLK : in std_logic;
RESET : in std_logic;
PULSE : out std_logic
);
end pulse_counter;
--------------------------------------------------------------------------------
architecture rtl of pulse_counter is
subtype T_COUNTER is unsigned(G_counter_width-1 downto 0);
constant C_ZERO : T_COUNTER := (others => '0');
signal COUNTER : T_COUNTER;
begin
PULSE <= '1' when COUNTER = C_ZERO else '0';
counter_proc: process (CLK) is
begin
if rising_edge(CLK) then
if RESET = '1' then
COUNTER <= C_ZERO;
else
if to_integer(COUNTER) = G_period-1 then
COUNTER <= C_ZERO;
else
COUNTER <= COUNTER + 1;
end if;
end if;
end if;
end process counter_proc;
end rtl; |
----------------------------------------------------------------------------------
-- Company: Traducciones Magno
-- Engineer: Magno
--
-- Create Date: 18.03.2018 20:49:09
-- Design Name:
-- Module Name: FIFO_Input - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity FIFO_B2B is
Generic( FIFO_DEPTH : integer := 32;
PROG_FULL_TH : integer := 16);
Port( clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din_tready : OUT STD_LOGIC;
din_tvalid : IN STD_LOGIC;
din_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dout_tready : IN STD_LOGIC;
dout_tvalid : OUT STD_LOGIC;
dout_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
prog_full : OUT STD_LOGIC );
end FIFO_B2B;
architecture Behavioral of FIFO_B2B is
type FIFO_Array_t is array(FIFO_DEPTH-1 downto 0) of STD_LOGIC_VECTOR(7 downto 0);
signal FIFO_Array : FIFO_Array_t := (others => (others => '0'));
signal wr_ptr : integer range 0 to FIFO_DEPTH-1 := 0;
signal rd_ptr : integer range 0 to FIFO_DEPTH-1 := 0;
signal data_cnt : integer range 0 to FIFO_DEPTH := 0;
signal din_tready_i : STD_LOGIC := '0';
signal dout_tvalid_i : STD_LOGIC := '0';
begin
Process( clk )
Begin
if rising_edge( clk ) then
if( srst = '1' ) then
FIFO_Array <= (others => (others => '0'));
wr_ptr <= 0;
rd_ptr <= 0;
data_cnt <= 0;
else
-- write command
if( din_tready_i = '1' AND din_tvalid = '1' ) then
-- write data to array
FIFO_Array(wr_ptr) <= din_tdata;
-- check write pointer limits
if( wr_ptr = (FIFO_DEPTH-1) ) then
wr_ptr <= 0;
else
wr_ptr <= wr_ptr + 1;
end if;
end if;
-- read command
if( dout_tready = '1' AND dout_tvalid_i = '1' ) then
-- check read pointer limits
if( rd_ptr = (FIFO_DEPTH-1) ) then
rd_ptr <= 0;
else
rd_ptr <= rd_ptr + 1;
end if;
end if;
-- occupancy control
-- write only
if((din_tready_i = '1' AND din_tvalid = '1') AND
(dout_tready = '0' OR dout_tvalid_i = '0')) then
data_cnt <= data_cnt + 1;
-- read only
elsif((din_tready_i = '0' OR din_tvalid = '0') AND
(dout_tready = '1' AND dout_tvalid_i = '1')) then
data_cnt <= data_cnt - 1;
end if;
end if;
end if;
End Process;
-- first word fall-through
dout_tdata <= FIFO_Array(rd_ptr);
dout_tvalid_i <= '0' when (data_cnt = 0 OR srst = '1') else '1';
dout_tvalid <= dout_tvalid_i;
-- flow control signals
empty <= '1' when data_cnt = 0 else '0';
full <= NOT din_tready_i;
prog_full <= '1' when (data_cnt >= PROG_FULL_TH OR srst = '1') else '0';
din_tready_i <= '0' when (data_cnt > (FIFO_DEPTH-1) OR srst = '1') else '1';
din_tready <= din_tready_i;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company: Traducciones Magno
-- Engineer: Magno
--
-- Create Date: 18.03.2018 20:49:09
-- Design Name:
-- Module Name: FIFO_Input - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity FIFO_B2B is
Generic( FIFO_DEPTH : integer := 32;
PROG_FULL_TH : integer := 16);
Port( clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din_tready : OUT STD_LOGIC;
din_tvalid : IN STD_LOGIC;
din_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dout_tready : IN STD_LOGIC;
dout_tvalid : OUT STD_LOGIC;
dout_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
prog_full : OUT STD_LOGIC );
end FIFO_B2B;
architecture Behavioral of FIFO_B2B is
type FIFO_Array_t is array(FIFO_DEPTH-1 downto 0) of STD_LOGIC_VECTOR(7 downto 0);
signal FIFO_Array : FIFO_Array_t := (others => (others => '0'));
signal wr_ptr : integer range 0 to FIFO_DEPTH-1 := 0;
signal rd_ptr : integer range 0 to FIFO_DEPTH-1 := 0;
signal data_cnt : integer range 0 to FIFO_DEPTH := 0;
signal din_tready_i : STD_LOGIC := '0';
signal dout_tvalid_i : STD_LOGIC := '0';
begin
Process( clk )
Begin
if rising_edge( clk ) then
if( srst = '1' ) then
FIFO_Array <= (others => (others => '0'));
wr_ptr <= 0;
rd_ptr <= 0;
data_cnt <= 0;
else
-- write command
if( din_tready_i = '1' AND din_tvalid = '1' ) then
-- write data to array
FIFO_Array(wr_ptr) <= din_tdata;
-- check write pointer limits
if( wr_ptr = (FIFO_DEPTH-1) ) then
wr_ptr <= 0;
else
wr_ptr <= wr_ptr + 1;
end if;
end if;
-- read command
if( dout_tready = '1' AND dout_tvalid_i = '1' ) then
-- check read pointer limits
if( rd_ptr = (FIFO_DEPTH-1) ) then
rd_ptr <= 0;
else
rd_ptr <= rd_ptr + 1;
end if;
end if;
-- occupancy control
-- write only
if((din_tready_i = '1' AND din_tvalid = '1') AND
(dout_tready = '0' OR dout_tvalid_i = '0')) then
data_cnt <= data_cnt + 1;
-- read only
elsif((din_tready_i = '0' OR din_tvalid = '0') AND
(dout_tready = '1' AND dout_tvalid_i = '1')) then
data_cnt <= data_cnt - 1;
end if;
end if;
end if;
End Process;
-- first word fall-through
dout_tdata <= FIFO_Array(rd_ptr);
dout_tvalid_i <= '0' when (data_cnt = 0 OR srst = '1') else '1';
dout_tvalid <= dout_tvalid_i;
-- flow control signals
empty <= '1' when data_cnt = 0 else '0';
full <= NOT din_tready_i;
prog_full <= '1' when (data_cnt >= PROG_FULL_TH OR srst = '1') else '0';
din_tready_i <= '0' when (data_cnt > (FIFO_DEPTH-1) OR srst = '1') else '1';
din_tready <= din_tready_i;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity output_split5 is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(2 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
ra0_addr : in std_logic_vector(2 downto 0);
wa0_en : in std_logic;
clk : in std_logic
);
end output_split5;
architecture augh of output_split5 is
-- Embedded RAM
type ram_type is array (0 to 7) of std_logic_vector(7 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity output_split5 is
port (
wa0_data : in std_logic_vector(7 downto 0);
wa0_addr : in std_logic_vector(2 downto 0);
ra0_data : out std_logic_vector(7 downto 0);
ra0_addr : in std_logic_vector(2 downto 0);
wa0_en : in std_logic;
clk : in std_logic
);
end output_split5;
architecture augh of output_split5 is
-- Embedded RAM
type ram_type is array (0 to 7) of std_logic_vector(7 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) );
end architecture;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all;
library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
entity tb_a2d_d2a is
end tb_a2d_d2a;
architecture TB_a2d_d2a of tb_a2d_d2a is
-- Component declarations
-- Signal declarations
terminal ana_out : electrical;
terminal analog_in : electrical;
signal clock : std_ulogic;
signal start : std_ulogic;
signal eoc : std_ulogic;
signal eoc_logic: std_logic;
signal oe : std_logic;
signal data_bus : std_ulogic_vector(0 to 9);
signal latch : std_ulogic;
signal latch_logic : std_logic;
signal nn_eoc : std_logic;
signal or_out : std_logic;
signal n_eoc : std_logic;
begin
-- Signal assignments
eoc_logic <= To_X01Z(eoc); -- convert std_ulogic to std_logic
latch <= To_X01(latch_logic); -- convert std_logic to std_ulogic
-- Component instances
ad1 : entity work.a2d_nbit(sar)
port map(
dout => data_bus,
ain => analog_in,
clk => clock,
start => start,
eoc => eoc
);
v1 : entity work.v_sine(ideal)
generic map(
freq => 2.5,
amplitude => 2.5,
offset => 2.5,
phase => 0.0
)
port map(
pos => analog_in,
neg => ELECTRICAL_REF
);
inv1 : entity work.inverter(ideal)
generic map(
delay => 2us
)
port map(
input => or_out,
output => oe
);
inv2 : entity work.inverter(ideal)
generic map(
delay => 2us
)
port map(
input => n_eoc,
output => nn_eoc
);
or1 : entity work.or2(ideal)
port map(
in1 => n_eoc,
in2 => nn_eoc,
output => or_out
);
inv3 : entity work.inverter(ideal)
generic map(
delay => 0us
)
port map(
input => eoc_logic,
output => n_eoc
);
U2 : entity work.buff(ideal)
generic map(
delay => 250ns
)
port map(
input => oe,
output => latch_logic
);
da1 : entity work.dac_10_bit(behavioral)
port map(
bus_in => data_bus,
analog_out => ana_out,
clk => latch
);
-- clock
P_clock :
process
begin
clock <= '1';
wait for 50.0 us;
clock <= '0';
wait for 50.0 us;
end process P_clock;
-- start
P_start :
process
begin
start <= '0';
wait for 2.0 ms;
start <= '1';
wait for 0.2 ms;
start <= '0';
wait for 2.0 ms;
end process P_start;
end TB_a2d_d2a;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all;
library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
entity tb_a2d_d2a is
end tb_a2d_d2a;
architecture TB_a2d_d2a of tb_a2d_d2a is
-- Component declarations
-- Signal declarations
terminal ana_out : electrical;
terminal analog_in : electrical;
signal clock : std_ulogic;
signal start : std_ulogic;
signal eoc : std_ulogic;
signal eoc_logic: std_logic;
signal oe : std_logic;
signal data_bus : std_ulogic_vector(0 to 9);
signal latch : std_ulogic;
signal latch_logic : std_logic;
signal nn_eoc : std_logic;
signal or_out : std_logic;
signal n_eoc : std_logic;
begin
-- Signal assignments
eoc_logic <= To_X01Z(eoc); -- convert std_ulogic to std_logic
latch <= To_X01(latch_logic); -- convert std_logic to std_ulogic
-- Component instances
ad1 : entity work.a2d_nbit(sar)
port map(
dout => data_bus,
ain => analog_in,
clk => clock,
start => start,
eoc => eoc
);
v1 : entity work.v_sine(ideal)
generic map(
freq => 2.5,
amplitude => 2.5,
offset => 2.5,
phase => 0.0
)
port map(
pos => analog_in,
neg => ELECTRICAL_REF
);
inv1 : entity work.inverter(ideal)
generic map(
delay => 2us
)
port map(
input => or_out,
output => oe
);
inv2 : entity work.inverter(ideal)
generic map(
delay => 2us
)
port map(
input => n_eoc,
output => nn_eoc
);
or1 : entity work.or2(ideal)
port map(
in1 => n_eoc,
in2 => nn_eoc,
output => or_out
);
inv3 : entity work.inverter(ideal)
generic map(
delay => 0us
)
port map(
input => eoc_logic,
output => n_eoc
);
U2 : entity work.buff(ideal)
generic map(
delay => 250ns
)
port map(
input => oe,
output => latch_logic
);
da1 : entity work.dac_10_bit(behavioral)
port map(
bus_in => data_bus,
analog_out => ana_out,
clk => latch
);
-- clock
P_clock :
process
begin
clock <= '1';
wait for 50.0 us;
clock <= '0';
wait for 50.0 us;
end process P_clock;
-- start
P_start :
process
begin
start <= '0';
wait for 2.0 ms;
start <= '1';
wait for 0.2 ms;
start <= '0';
wait for 2.0 ms;
end process P_start;
end TB_a2d_d2a;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all;
library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
entity tb_a2d_d2a is
end tb_a2d_d2a;
architecture TB_a2d_d2a of tb_a2d_d2a is
-- Component declarations
-- Signal declarations
terminal ana_out : electrical;
terminal analog_in : electrical;
signal clock : std_ulogic;
signal start : std_ulogic;
signal eoc : std_ulogic;
signal eoc_logic: std_logic;
signal oe : std_logic;
signal data_bus : std_ulogic_vector(0 to 9);
signal latch : std_ulogic;
signal latch_logic : std_logic;
signal nn_eoc : std_logic;
signal or_out : std_logic;
signal n_eoc : std_logic;
begin
-- Signal assignments
eoc_logic <= To_X01Z(eoc); -- convert std_ulogic to std_logic
latch <= To_X01(latch_logic); -- convert std_logic to std_ulogic
-- Component instances
ad1 : entity work.a2d_nbit(sar)
port map(
dout => data_bus,
ain => analog_in,
clk => clock,
start => start,
eoc => eoc
);
v1 : entity work.v_sine(ideal)
generic map(
freq => 2.5,
amplitude => 2.5,
offset => 2.5,
phase => 0.0
)
port map(
pos => analog_in,
neg => ELECTRICAL_REF
);
inv1 : entity work.inverter(ideal)
generic map(
delay => 2us
)
port map(
input => or_out,
output => oe
);
inv2 : entity work.inverter(ideal)
generic map(
delay => 2us
)
port map(
input => n_eoc,
output => nn_eoc
);
or1 : entity work.or2(ideal)
port map(
in1 => n_eoc,
in2 => nn_eoc,
output => or_out
);
inv3 : entity work.inverter(ideal)
generic map(
delay => 0us
)
port map(
input => eoc_logic,
output => n_eoc
);
U2 : entity work.buff(ideal)
generic map(
delay => 250ns
)
port map(
input => oe,
output => latch_logic
);
da1 : entity work.dac_10_bit(behavioral)
port map(
bus_in => data_bus,
analog_out => ana_out,
clk => latch
);
-- clock
P_clock :
process
begin
clock <= '1';
wait for 50.0 us;
clock <= '0';
wait for 50.0 us;
end process P_clock;
-- start
P_start :
process
begin
start <= '0';
wait for 2.0 ms;
start <= '1';
wait for 0.2 ms;
start <= '0';
wait for 2.0 ms;
end process P_start;
end TB_a2d_d2a;
|
----------------------------------------------------------------------------------
-- flags.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Flags register.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity flags is
port(
data : in std_logic_vector(10 downto 0);
clock : in std_logic;
write : in std_logic;
demux : out std_logic;
filter : out std_logic;
external : out std_logic;
inverted : out std_logic;
disabledGroups : out std_logic_vector (3 downto 0);
rle : out std_logic;
test_mode : out std_logic;
data_size : out std_logic_vector (1 downto 0);
num_scheme : out std_logic
);
end flags;
architecture behavioral of flags is
signal ds : std_logic_vector (1 downto 0);
begin
-- write flags
process (clock)
begin
if rising_edge(clock) then
if write = '1' then
demux <= data(0);
filter <= data(1);
external <= data(6);
inverted <= data(7);
disabledGroups <= data(5 downto 2);
rle <= data(8);
num_scheme <= data(9);
test_mode <= data(10);
data_size <= ds;
end if;
end if;
end process;
ds <=
"01" when data(5 downto 2) = "1110" else
"01" when data(5 downto 2) = "1101" else
"01" when data(5 downto 2) = "1011" else
"01" when data(5 downto 2) = "0111" else
"10" when data(5 downto 2) = "1100" else
"10" when data(5 downto 2) = "1010" else
"10" when data(5 downto 2) = "0110" else
"10" when data(5 downto 2) = "1001" else
"10" when data(5 downto 2) = "0101" else
"10" when data(5 downto 2) = "0011" else
"00";
end behavioral;
|
----------------------------------------------------------------------------------
-- flags.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Flags register.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity flags is
port(
data : in std_logic_vector(10 downto 0);
clock : in std_logic;
write : in std_logic;
demux : out std_logic;
filter : out std_logic;
external : out std_logic;
inverted : out std_logic;
disabledGroups : out std_logic_vector (3 downto 0);
rle : out std_logic;
test_mode : out std_logic;
data_size : out std_logic_vector (1 downto 0);
num_scheme : out std_logic
);
end flags;
architecture behavioral of flags is
signal ds : std_logic_vector (1 downto 0);
begin
-- write flags
process (clock)
begin
if rising_edge(clock) then
if write = '1' then
demux <= data(0);
filter <= data(1);
external <= data(6);
inverted <= data(7);
disabledGroups <= data(5 downto 2);
rle <= data(8);
num_scheme <= data(9);
test_mode <= data(10);
data_size <= ds;
end if;
end if;
end process;
ds <=
"01" when data(5 downto 2) = "1110" else
"01" when data(5 downto 2) = "1101" else
"01" when data(5 downto 2) = "1011" else
"01" when data(5 downto 2) = "0111" else
"10" when data(5 downto 2) = "1100" else
"10" when data(5 downto 2) = "1010" else
"10" when data(5 downto 2) = "0110" else
"10" when data(5 downto 2) = "1001" else
"10" when data(5 downto 2) = "0101" else
"10" when data(5 downto 2) = "0011" else
"00";
end behavioral;
|
----------------------------------------------------------------------------------
-- flags.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Flags register.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity flags is
port(
data : in std_logic_vector(10 downto 0);
clock : in std_logic;
write : in std_logic;
demux : out std_logic;
filter : out std_logic;
external : out std_logic;
inverted : out std_logic;
disabledGroups : out std_logic_vector (3 downto 0);
rle : out std_logic;
test_mode : out std_logic;
data_size : out std_logic_vector (1 downto 0);
num_scheme : out std_logic
);
end flags;
architecture behavioral of flags is
signal ds : std_logic_vector (1 downto 0);
begin
-- write flags
process (clock)
begin
if rising_edge(clock) then
if write = '1' then
demux <= data(0);
filter <= data(1);
external <= data(6);
inverted <= data(7);
disabledGroups <= data(5 downto 2);
rle <= data(8);
num_scheme <= data(9);
test_mode <= data(10);
data_size <= ds;
end if;
end if;
end process;
ds <=
"01" when data(5 downto 2) = "1110" else
"01" when data(5 downto 2) = "1101" else
"01" when data(5 downto 2) = "1011" else
"01" when data(5 downto 2) = "0111" else
"10" when data(5 downto 2) = "1100" else
"10" when data(5 downto 2) = "1010" else
"10" when data(5 downto 2) = "0110" else
"10" when data(5 downto 2) = "1001" else
"10" when data(5 downto 2) = "0101" else
"10" when data(5 downto 2) = "0011" else
"00";
end behavioral;
|
----------------------------------------------------------------------------------
-- flags.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Flags register.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity flags is
port(
data : in std_logic_vector(10 downto 0);
clock : in std_logic;
write : in std_logic;
demux : out std_logic;
filter : out std_logic;
external : out std_logic;
inverted : out std_logic;
disabledGroups : out std_logic_vector (3 downto 0);
rle : out std_logic;
test_mode : out std_logic;
data_size : out std_logic_vector (1 downto 0);
num_scheme : out std_logic
);
end flags;
architecture behavioral of flags is
signal ds : std_logic_vector (1 downto 0);
begin
-- write flags
process (clock)
begin
if rising_edge(clock) then
if write = '1' then
demux <= data(0);
filter <= data(1);
external <= data(6);
inverted <= data(7);
disabledGroups <= data(5 downto 2);
rle <= data(8);
num_scheme <= data(9);
test_mode <= data(10);
data_size <= ds;
end if;
end if;
end process;
ds <=
"01" when data(5 downto 2) = "1110" else
"01" when data(5 downto 2) = "1101" else
"01" when data(5 downto 2) = "1011" else
"01" when data(5 downto 2) = "0111" else
"10" when data(5 downto 2) = "1100" else
"10" when data(5 downto 2) = "1010" else
"10" when data(5 downto 2) = "0110" else
"10" when data(5 downto 2) = "1001" else
"10" when data(5 downto 2) = "0101" else
"10" when data(5 downto 2) = "0011" else
"00";
end behavioral;
|
----------------------------------------------------------------------------------
-- flags.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Flags register.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity flags is
port(
data : in std_logic_vector(10 downto 0);
clock : in std_logic;
write : in std_logic;
demux : out std_logic;
filter : out std_logic;
external : out std_logic;
inverted : out std_logic;
disabledGroups : out std_logic_vector (3 downto 0);
rle : out std_logic;
test_mode : out std_logic;
data_size : out std_logic_vector (1 downto 0);
num_scheme : out std_logic
);
end flags;
architecture behavioral of flags is
signal ds : std_logic_vector (1 downto 0);
begin
-- write flags
process (clock)
begin
if rising_edge(clock) then
if write = '1' then
demux <= data(0);
filter <= data(1);
external <= data(6);
inverted <= data(7);
disabledGroups <= data(5 downto 2);
rle <= data(8);
num_scheme <= data(9);
test_mode <= data(10);
data_size <= ds;
end if;
end if;
end process;
ds <=
"01" when data(5 downto 2) = "1110" else
"01" when data(5 downto 2) = "1101" else
"01" when data(5 downto 2) = "1011" else
"01" when data(5 downto 2) = "0111" else
"10" when data(5 downto 2) = "1100" else
"10" when data(5 downto 2) = "1010" else
"10" when data(5 downto 2) = "0110" else
"10" when data(5 downto 2) = "1001" else
"10" when data(5 downto 2) = "0101" else
"10" when data(5 downto 2) = "0011" else
"00";
end behavioral;
|
----------------------------------------------------------------------------------
-- flags.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Flags register.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity flags is
port(
data : in std_logic_vector(10 downto 0);
clock : in std_logic;
write : in std_logic;
demux : out std_logic;
filter : out std_logic;
external : out std_logic;
inverted : out std_logic;
disabledGroups : out std_logic_vector (3 downto 0);
rle : out std_logic;
test_mode : out std_logic;
data_size : out std_logic_vector (1 downto 0);
num_scheme : out std_logic
);
end flags;
architecture behavioral of flags is
signal ds : std_logic_vector (1 downto 0);
begin
-- write flags
process (clock)
begin
if rising_edge(clock) then
if write = '1' then
demux <= data(0);
filter <= data(1);
external <= data(6);
inverted <= data(7);
disabledGroups <= data(5 downto 2);
rle <= data(8);
num_scheme <= data(9);
test_mode <= data(10);
data_size <= ds;
end if;
end if;
end process;
ds <=
"01" when data(5 downto 2) = "1110" else
"01" when data(5 downto 2) = "1101" else
"01" when data(5 downto 2) = "1011" else
"01" when data(5 downto 2) = "0111" else
"10" when data(5 downto 2) = "1100" else
"10" when data(5 downto 2) = "1010" else
"10" when data(5 downto 2) = "0110" else
"10" when data(5 downto 2) = "1001" else
"10" when data(5 downto 2) = "0101" else
"10" when data(5 downto 2) = "0011" else
"00";
end behavioral;
|
----------------------------------------------------------------------------------
-- flags.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Flags register.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity flags is
port(
data : in std_logic_vector(10 downto 0);
clock : in std_logic;
write : in std_logic;
demux : out std_logic;
filter : out std_logic;
external : out std_logic;
inverted : out std_logic;
disabledGroups : out std_logic_vector (3 downto 0);
rle : out std_logic;
test_mode : out std_logic;
data_size : out std_logic_vector (1 downto 0);
num_scheme : out std_logic
);
end flags;
architecture behavioral of flags is
signal ds : std_logic_vector (1 downto 0);
begin
-- write flags
process (clock)
begin
if rising_edge(clock) then
if write = '1' then
demux <= data(0);
filter <= data(1);
external <= data(6);
inverted <= data(7);
disabledGroups <= data(5 downto 2);
rle <= data(8);
num_scheme <= data(9);
test_mode <= data(10);
data_size <= ds;
end if;
end if;
end process;
ds <=
"01" when data(5 downto 2) = "1110" else
"01" when data(5 downto 2) = "1101" else
"01" when data(5 downto 2) = "1011" else
"01" when data(5 downto 2) = "0111" else
"10" when data(5 downto 2) = "1100" else
"10" when data(5 downto 2) = "1010" else
"10" when data(5 downto 2) = "0110" else
"10" when data(5 downto 2) = "1001" else
"10" when data(5 downto 2) = "0101" else
"10" when data(5 downto 2) = "0011" else
"00";
end behavioral;
|
----------------------------------------------------------------------------------
-- flags.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Flags register.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity flags is
port(
data : in std_logic_vector(10 downto 0);
clock : in std_logic;
write : in std_logic;
demux : out std_logic;
filter : out std_logic;
external : out std_logic;
inverted : out std_logic;
disabledGroups : out std_logic_vector (3 downto 0);
rle : out std_logic;
test_mode : out std_logic;
data_size : out std_logic_vector (1 downto 0);
num_scheme : out std_logic
);
end flags;
architecture behavioral of flags is
signal ds : std_logic_vector (1 downto 0);
begin
-- write flags
process (clock)
begin
if rising_edge(clock) then
if write = '1' then
demux <= data(0);
filter <= data(1);
external <= data(6);
inverted <= data(7);
disabledGroups <= data(5 downto 2);
rle <= data(8);
num_scheme <= data(9);
test_mode <= data(10);
data_size <= ds;
end if;
end if;
end process;
ds <=
"01" when data(5 downto 2) = "1110" else
"01" when data(5 downto 2) = "1101" else
"01" when data(5 downto 2) = "1011" else
"01" when data(5 downto 2) = "0111" else
"10" when data(5 downto 2) = "1100" else
"10" when data(5 downto 2) = "1010" else
"10" when data(5 downto 2) = "0110" else
"10" when data(5 downto 2) = "1001" else
"10" when data(5 downto 2) = "0101" else
"10" when data(5 downto 2) = "0011" else
"00";
end behavioral;
|
----------------------------------------------------------------------------------
-- flags.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Flags register.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity flags is
port(
data : in std_logic_vector(10 downto 0);
clock : in std_logic;
write : in std_logic;
demux : out std_logic;
filter : out std_logic;
external : out std_logic;
inverted : out std_logic;
disabledGroups : out std_logic_vector (3 downto 0);
rle : out std_logic;
test_mode : out std_logic;
data_size : out std_logic_vector (1 downto 0);
num_scheme : out std_logic
);
end flags;
architecture behavioral of flags is
signal ds : std_logic_vector (1 downto 0);
begin
-- write flags
process (clock)
begin
if rising_edge(clock) then
if write = '1' then
demux <= data(0);
filter <= data(1);
external <= data(6);
inverted <= data(7);
disabledGroups <= data(5 downto 2);
rle <= data(8);
num_scheme <= data(9);
test_mode <= data(10);
data_size <= ds;
end if;
end if;
end process;
ds <=
"01" when data(5 downto 2) = "1110" else
"01" when data(5 downto 2) = "1101" else
"01" when data(5 downto 2) = "1011" else
"01" when data(5 downto 2) = "0111" else
"10" when data(5 downto 2) = "1100" else
"10" when data(5 downto 2) = "1010" else
"10" when data(5 downto 2) = "0110" else
"10" when data(5 downto 2) = "1001" else
"10" when data(5 downto 2) = "0101" else
"10" when data(5 downto 2) = "0011" else
"00";
end behavioral;
|
----------------------------------------------------------------------------------
-- flags.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Flags register.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity flags is
port(
data : in std_logic_vector(10 downto 0);
clock : in std_logic;
write : in std_logic;
demux : out std_logic;
filter : out std_logic;
external : out std_logic;
inverted : out std_logic;
disabledGroups : out std_logic_vector (3 downto 0);
rle : out std_logic;
test_mode : out std_logic;
data_size : out std_logic_vector (1 downto 0);
num_scheme : out std_logic
);
end flags;
architecture behavioral of flags is
signal ds : std_logic_vector (1 downto 0);
begin
-- write flags
process (clock)
begin
if rising_edge(clock) then
if write = '1' then
demux <= data(0);
filter <= data(1);
external <= data(6);
inverted <= data(7);
disabledGroups <= data(5 downto 2);
rle <= data(8);
num_scheme <= data(9);
test_mode <= data(10);
data_size <= ds;
end if;
end if;
end process;
ds <=
"01" when data(5 downto 2) = "1110" else
"01" when data(5 downto 2) = "1101" else
"01" when data(5 downto 2) = "1011" else
"01" when data(5 downto 2) = "0111" else
"10" when data(5 downto 2) = "1100" else
"10" when data(5 downto 2) = "1010" else
"10" when data(5 downto 2) = "0110" else
"10" when data(5 downto 2) = "1001" else
"10" when data(5 downto 2) = "0101" else
"10" when data(5 downto 2) = "0011" else
"00";
end behavioral;
|
----------------------------------------------------------------------------------
-- flags.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Flags register.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity flags is
port(
data : in std_logic_vector(10 downto 0);
clock : in std_logic;
write : in std_logic;
demux : out std_logic;
filter : out std_logic;
external : out std_logic;
inverted : out std_logic;
disabledGroups : out std_logic_vector (3 downto 0);
rle : out std_logic;
test_mode : out std_logic;
data_size : out std_logic_vector (1 downto 0);
num_scheme : out std_logic
);
end flags;
architecture behavioral of flags is
signal ds : std_logic_vector (1 downto 0);
begin
-- write flags
process (clock)
begin
if rising_edge(clock) then
if write = '1' then
demux <= data(0);
filter <= data(1);
external <= data(6);
inverted <= data(7);
disabledGroups <= data(5 downto 2);
rle <= data(8);
num_scheme <= data(9);
test_mode <= data(10);
data_size <= ds;
end if;
end if;
end process;
ds <=
"01" when data(5 downto 2) = "1110" else
"01" when data(5 downto 2) = "1101" else
"01" when data(5 downto 2) = "1011" else
"01" when data(5 downto 2) = "0111" else
"10" when data(5 downto 2) = "1100" else
"10" when data(5 downto 2) = "1010" else
"10" when data(5 downto 2) = "0110" else
"10" when data(5 downto 2) = "1001" else
"10" when data(5 downto 2) = "0101" else
"10" when data(5 downto 2) = "0011" else
"00";
end behavioral;
|
----------------------------------------------------------------------------------
-- flags.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Flags register.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity flags is
port(
data : in std_logic_vector(10 downto 0);
clock : in std_logic;
write : in std_logic;
demux : out std_logic;
filter : out std_logic;
external : out std_logic;
inverted : out std_logic;
disabledGroups : out std_logic_vector (3 downto 0);
rle : out std_logic;
test_mode : out std_logic;
data_size : out std_logic_vector (1 downto 0);
num_scheme : out std_logic
);
end flags;
architecture behavioral of flags is
signal ds : std_logic_vector (1 downto 0);
begin
-- write flags
process (clock)
begin
if rising_edge(clock) then
if write = '1' then
demux <= data(0);
filter <= data(1);
external <= data(6);
inverted <= data(7);
disabledGroups <= data(5 downto 2);
rle <= data(8);
num_scheme <= data(9);
test_mode <= data(10);
data_size <= ds;
end if;
end if;
end process;
ds <=
"01" when data(5 downto 2) = "1110" else
"01" when data(5 downto 2) = "1101" else
"01" when data(5 downto 2) = "1011" else
"01" when data(5 downto 2) = "0111" else
"10" when data(5 downto 2) = "1100" else
"10" when data(5 downto 2) = "1010" else
"10" when data(5 downto 2) = "0110" else
"10" when data(5 downto 2) = "1001" else
"10" when data(5 downto 2) = "0101" else
"10" when data(5 downto 2) = "0011" else
"00";
end behavioral;
|
----------------------------------------------------------------------------------
-- flags.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Flags register.
--
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity flags is
port(
data : in std_logic_vector(10 downto 0);
clock : in std_logic;
write : in std_logic;
demux : out std_logic;
filter : out std_logic;
external : out std_logic;
inverted : out std_logic;
disabledGroups : out std_logic_vector (3 downto 0);
rle : out std_logic;
test_mode : out std_logic;
data_size : out std_logic_vector (1 downto 0);
num_scheme : out std_logic
);
end flags;
architecture behavioral of flags is
signal ds : std_logic_vector (1 downto 0);
begin
-- write flags
process (clock)
begin
if rising_edge(clock) then
if write = '1' then
demux <= data(0);
filter <= data(1);
external <= data(6);
inverted <= data(7);
disabledGroups <= data(5 downto 2);
rle <= data(8);
num_scheme <= data(9);
test_mode <= data(10);
data_size <= ds;
end if;
end if;
end process;
ds <=
"01" when data(5 downto 2) = "1110" else
"01" when data(5 downto 2) = "1101" else
"01" when data(5 downto 2) = "1011" else
"01" when data(5 downto 2) = "0111" else
"10" when data(5 downto 2) = "1100" else
"10" when data(5 downto 2) = "1010" else
"10" when data(5 downto 2) = "0110" else
"10" when data(5 downto 2) = "1001" else
"10" when data(5 downto 2) = "0101" else
"10" when data(5 downto 2) = "0011" else
"00";
end behavioral;
|
-- This is a wrapper made for calling Pixel_On_Text.vhd form verilog
-- Since I'm not familiar with mapping string and structure(point_2d) bewteen verilog and vhdl, this is a simple walkaround.
-- By using Pixel_On_Text2.vhd, this file may not be necessary anymore.
-- However, sometimes it's a bit more convenient to group all you text in one place.
-- I also include some sample code for acheiving dynamic text(a simple way).
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
-- note this line.The package is compiled to this directory by default.
-- so don't forget to include this directory.
library work;
-- this line also is must.This includes the particular package into your program.
use work.commonPak.all;
entity wrapper is
Port (
clk: in std_logic;
xCoord: in std_logic_vector(11 downto 0);
yCoord: in std_logic_vector(11 downto 0);
pixOn: out std_logic
);
end wrapper;
architecture Behavioral of wrapper is
signal h : integer := to_integer(signed(xCoord));
signal v : integer := to_integer(signed(yCoord));
-- results
signal d1 : std_logic := '0';
signal d2 : std_logic := '0';
signal d3 : std_logic := '0';
begin
textElement1: entity work.Pixel_On_Text
generic map (
textLength => 38
)
port map(
clk => clk,
displayText => "Pixel_On_Text -- test 1!@#$ at (50,50)",
position => (50, 50),
horzCoord => h,
vertCoord => v,
pixel => d1
);
textElement2: entity work.Pixel_On_Text
generic map (
textLength => 39
)
port map(
clk => clk,
displayText => "Pixel_On_Text -- test 2%^&* at (500,50)",
position => (500, 50),
horzCoord => h,
vertCoord => v,
pixel => d2
);
textElement3: entity work.Pixel_On_Text
generic map (
textLength => 41
)
port map(
clk => clk,
displayText => "Pixel_On_Text -- test 3()_+-= at (50,130)",
position => (50, 130),
horzCoord => h,
vertCoord => v,
pixel => d3
);
-- -- This is a simply way for a dynamic text. Of course, I know you probably have a better solution :)
-- -- With a new input "timeDiv", we can switch on different string
-- with timeDiv select
-- timeDivDigitNum <= "Time/Div: 0.8 sec/div " when 0,
-- "Time/Div: 0.2 sec/div " when 1,
-- "Time/Div: 0.1 sec/div " when 2,
-- "Time/Div: 100 ms/div " when 3,
-- "Time/Div: 50 ms/div " when 4,
-- "Time/Div: 10 ms/div " when 5,
-- "Time/Div: 1 ms/div " when 6,
-- "Time/Div: 0.1ms/div " when 7,
-- "Time/Div: unknown " when OTHERS;
-- textDrawElement4: entity work.Pixel_On_Text
-- generic map (
-- textLength => 23
-- )
-- port map(
-- clk => clk,
-- reset => reset,
-- textPassage => timeDivDigitNum ,--& integer'image(timeDiv),
-- position => (70, 90),
-- hCount => h,
-- vCount => v,
-- drawElement => d4
-- );
pixelInTextGroup: process(clk)
begin
if rising_edge(clk) then
-- the pixel is on when one of the text matched
pixOn <= d1 or d2 or d3;
end if;
end process;
end Behavioral;
|
--*****************************************************************************
--*************************** VHDL Source Code ******************************
--*****************************************************************************
-- vim: set ts=2 sw=2 tw=78 et :
--
-- DESIGNER NAME: Ryan Tucker <[email protected]>
--
-- LAB NAME: Lab 7: Game System
--
-- FILE NAME: codebreaker_top.vhd
--
-------------------------------------------------------------------------------
-- Description:
-- This module is the top level module for the CodeBreaker game system
--
--*****************************************************************************
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library work;
-------------------------------------------------------------------------------
-- Port Declarations --
-------------------------------------------------------------------------------
entity codebreaker_top is
port (
-- Inputs
CLOCK_50 : in std_logic;
KEY : in std_logic_vector (3 downto 0);
-- Outputs
LEDG : out std_logic_vector(7 downto 0);
LEDR : out std_logic_vector(17 downto 0);
HEX7 : out std_logic_vector(6 downto 0);
HEX6 : out std_logic_vector(6 downto 0);
HEX5 : out std_logic_vector(6 downto 0);
HEX4 : out std_logic_vector(6 downto 0);
HEX3 : out std_logic_vector(6 downto 0);
HEX2 : out std_logic_vector(6 downto 0);
HEX1 : out std_logic_vector(6 downto 0);
HEX0 : out std_logic_vector(6 downto 0)
);
end codebreaker_top;
architecture structure of codebreaker_top is
component nios_system
port (
clk_clk : in std_logic;
reset_reset_n : in std_logic;
pio_keys_export : in std_logic_vector(1 downto 0);
--
led_toggle_pulse_export : out std_logic;
pio_countdown_export : out std_logic_vector(7 downto 0);
pio_leds_export : out std_logic_vector(1 downto 0)
);
end component nios_system;
signal led_toggle_pulse : std_logic;
signal led_gate : std_logic := '0';
signal leds : std_logic_vector(1 downto 0);
signal countdown : std_logic_vector(7 downto 0);
begin
NiosII : nios_system
port map(
clk_clk => clock_50,
reset_reset_n => key(0),
pio_keys_export => key(2 downto 1),
--
led_toggle_pulse_export => led_toggle_pulse,
pio_countdown_export => countdown,
pio_leds_export => leds
);
-- process: led_gate_p
-- updates the LED toggle gate signal on led toggle timers
led_gate_p : process (clock_50, key(0)) is
begin
if (key(0) = '0') then
led_gate <= '0';
elsif (rising_edge(clock_50)) then
if (led_toggle_pulse = '1') then
led_gate <= not led_gate;
end if;
end if;
end process led_gate_p;
-- combinational logic for controlling the LEDs
ledr <= (others => '1') when (leds(0) = '1' and led_gate = '1') -- LOSER
else (others => '0');
ledg <= (others => '1') when (leds(1) = '1' and led_gate = '1') -- WINNER
else (others => '0');
-- force unused 7-seg displays off
hex7 <= (others => '1');
hex6 <= (others => '1');
hex5 <= (others => '1');
hex4 <= (others => '1');
hex3 <= (others => '1');
hex2 <= (others => '1');
ssd_tens: entity work.seven_segment port map (
digit => "0" & countdown(6 downto 4),
enable => countdown(7),
bank => '0',
sevenseg => hex1
);
ssd_ones: entity work.seven_segment port map (
digit => countdown(3 downto 0),
enable => countdown(7),
bank => '0',
sevenseg => hex0
);
end structure;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: apbctrl
-- File: apbctrl.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AMBA AHB/APB bridge with plug&play support
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config_types.all;
use grlib.config.all;
use grlib.amba.all;
use grlib.stdlib.all;
entity apbctrl is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
nslaves : integer range 1 to NAPBSLV := NAPBSLV;
debug : integer range 0 to 2 := 2;
icheck : integer range 0 to 1 := 1;
enbusmon : integer range 0 to 1 := 0;
asserterr : integer range 0 to 1 := 0;
assertwarn : integer range 0 to 1 := 0;
pslvdisable : integer := 0;
mcheck : integer range 0 to 1 := 1;
ccheck : integer range 0 to 1 := 1
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbi : in ahb_slv_in_type;
ahbo : out ahb_slv_out_type;
apbi : out apb_slv_in_type;
apbo : in apb_slv_out_vector
);
end;
architecture struct of apbctrl is
signal lahbi : ahb_slv_in_vector_type(0 to 0);
signal lahbo : ahb_slv_out_vector_type(0 to 0);
signal lapbi : apb_slv_in_vector;
signal lwp : std_logic_vector(0 to 0);
signal lwpv : std_logic_vector(256-1 downto 0);
begin
lahbi(0) <= ahbi;
ahbo <= lahbo(0);
apbi <= lapbi(0);
lwp(0) <= '0';
lwpv <= (others => '0');
apbx : apbctrlx
generic map(
hindex0 => hindex,
haddr0 => haddr,
hmask0 => hmask,
hindex1 => 0,
haddr1 => 0,
hmask1 => 0,
nslaves => nslaves,
nports => 1,
wprot => 0,
debug => debug,
icheck => icheck,
enbusmon => enbusmon,
asserterr => asserterr,
assertwarn => assertwarn,
pslvdisable => pslvdisable,
mcheck => mcheck,
ccheck => ccheck)
port map(
rst => rst,
clk => clk,
ahbi => lahbi,
ahbo => lahbo,
apbi => lapbi,
apbo => apbo,
wp => lwp,
wpv => lwpv);
end;
|
--------------------------------------------------------------------------------
-- Title : VHDL Support Level Module
-- File : tri_mode_ethernet_mac_0_support.vhd
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: This module holds the support level for the Tri-Mode
-- Ethernet MAC IP. It contains potentially shareable FPGA
-- resources such as clocking, reset and IDELAYCTRL logic.
-- This can be used as-is in a single core design, or adapted
-- for use with multi-core implementations.
--------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
--------------------------------------------------------------------------------
-- The entity declaration for the block support level
--------------------------------------------------------------------------------
entity tri_mode_ethernet_mac_0_support is
port(
gtx_clk : in std_logic;
-- asynchronous reset
glbl_rstn : in std_logic;
rx_axi_rstn : in std_logic;
tx_axi_rstn : in std_logic;
-- Receiver Interface
----------------------------
rx_statistics_vector : out std_logic_vector(27 downto 0);
rx_statistics_valid : out std_logic;
rx_mac_aclk : out std_logic;
rx_reset : out std_logic;
rx_axis_mac_tdata : out std_logic_vector(7 downto 0);
rx_axis_mac_tvalid : out std_logic;
rx_axis_mac_tlast : out std_logic;
rx_axis_mac_tuser : out std_logic;
-- Transmitter Interface
-------------------------------
tx_ifg_delay : in std_logic_vector(7 downto 0);
tx_statistics_vector : out std_logic_vector(31 downto 0);
tx_statistics_valid : out std_logic;
tx_mac_aclk : out std_logic;
tx_reset : out std_logic;
tx_axis_mac_tdata : in std_logic_vector(7 downto 0);
tx_axis_mac_tvalid : in std_logic;
tx_axis_mac_tlast : in std_logic;
tx_axis_mac_tuser : in std_logic_vector(0 downto 0);
tx_axis_mac_tready : out std_logic;
-- MAC Control Interface
------------------------
pause_req : in std_logic;
pause_val : in std_logic_vector(15 downto 0);
speedis100 : out std_logic;
speedis10100 : out std_logic;
-- GMII Interface
-----------------
gmii_txd : out std_logic_vector(7 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_rxd : in std_logic_vector(7 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
-- MDIO Interface
-----------------
mdio : inout std_logic;
mdc : out std_logic;
-- AXI-Lite Interface
-----------------
s_axi_aclk : in std_logic;
s_axi_resetn : in std_logic;
s_axi_awaddr : in std_logic_vector(11 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(31 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(11 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
mac_irq : out std_logic
);
end tri_mode_ethernet_mac_0_support;
architecture wrapper of tri_mode_ethernet_mac_0_support is
------------------------------------------------------------------------------
-- Component declaration for the TEMAC core
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0
port(
gtx_clk : in std_logic;
-- asynchronous reset
glbl_rstn : in std_logic;
rx_axi_rstn : in std_logic;
tx_axi_rstn : in std_logic;
-- Receiver Interface
----------------------------
rx_statistics_vector : out std_logic_vector(27 downto 0);
rx_statistics_valid : out std_logic;
rx_mac_aclk : out std_logic;
rx_reset : out std_logic;
rx_axis_mac_tdata : out std_logic_vector(7 downto 0);
rx_axis_mac_tvalid : out std_logic;
rx_axis_mac_tlast : out std_logic;
rx_axis_mac_tuser : out std_logic;
-- Transmitter Interface
-------------------------------
tx_ifg_delay : in std_logic_vector(7 downto 0);
tx_statistics_vector : out std_logic_vector(31 downto 0);
tx_statistics_valid : out std_logic;
tx_mac_aclk : out std_logic;
tx_reset : out std_logic;
tx_axis_mac_tdata : in std_logic_vector(7 downto 0);
tx_axis_mac_tvalid : in std_logic;
tx_axis_mac_tlast : in std_logic;
tx_axis_mac_tuser : in std_logic_vector(0 downto 0);
tx_axis_mac_tready : out std_logic;
-- MAC Control Interface
------------------------
pause_req : in std_logic;
pause_val : in std_logic_vector(15 downto 0);
speedis100 : out std_logic;
speedis10100 : out std_logic;
-- GMII Interface
-----------------
gmii_txd : out std_logic_vector(7 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_rxd : in std_logic_vector(7 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
-- MDIO Interface
-----------------
mdio : inout std_logic;
mdc : out std_logic;
-- AXI-Lite Interface
-----------------
s_axi_aclk : in std_logic;
s_axi_resetn : in std_logic;
s_axi_awaddr : in std_logic_vector(11 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(31 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(11 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
mac_irq : out std_logic
);
end component;
begin
-----------------------------------------------------------------------------
-- Instantiate the TEMAC core
-----------------------------------------------------------------------------
tri_mode_ethernet_mac_i : tri_mode_ethernet_mac_0
port map (
gtx_clk => gtx_clk,
-- asynchronous reset
glbl_rstn => glbl_rstn,
rx_axi_rstn => rx_axi_rstn,
tx_axi_rstn => tx_axi_rstn,
-- Receiver Interface
----------------------------
rx_statistics_vector => rx_statistics_vector,
rx_statistics_valid => rx_statistics_valid,
rx_mac_aclk => rx_mac_aclk,
rx_reset => rx_reset,
rx_axis_mac_tdata => rx_axis_mac_tdata,
rx_axis_mac_tvalid => rx_axis_mac_tvalid,
rx_axis_mac_tlast => rx_axis_mac_tlast,
rx_axis_mac_tuser => rx_axis_mac_tuser,
-- Transmitter Interface
-------------------------------
tx_ifg_delay => tx_ifg_delay,
tx_statistics_vector => tx_statistics_vector,
tx_statistics_valid => tx_statistics_valid,
tx_mac_aclk => tx_mac_aclk,
tx_reset => tx_reset,
tx_axis_mac_tdata => tx_axis_mac_tdata,
tx_axis_mac_tvalid => tx_axis_mac_tvalid,
tx_axis_mac_tlast => tx_axis_mac_tlast,
tx_axis_mac_tuser => tx_axis_mac_tuser,
tx_axis_mac_tready => tx_axis_mac_tready,
-- MAC Control Interface
------------------------
pause_req => pause_req,
pause_val => pause_val,
speedis100 => speedis100,
speedis10100 => speedis10100,
-- GMII Interface
-----------------
gmii_txd => gmii_txd,
gmii_tx_en => gmii_tx_en,
gmii_tx_er => gmii_tx_er,
gmii_rxd => gmii_rxd,
gmii_rx_dv => gmii_rx_dv,
gmii_rx_er => gmii_rx_er,
-- MDIO Interface
-----------------
mdio => mdio,
mdc => mdc,
-- AXI-Lite Interface
-----------------
s_axi_aclk => s_axi_aclk,
s_axi_resetn => s_axi_resetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
mac_irq => mac_irq
);
end wrapper;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1797.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p02n01i01797ent IS
END c07s01b00x00p02n01i01797ent;
ARCHITECTURE c07s01b00x00p02n01i01797arch OF c07s01b00x00p02n01i01797ent IS
-- architecture declaration section
BEGIN
-- architecture statement part
TESTING: PROCESS
BEGIN
-- testcase code
Assert FALSE
Report "***PASSED TEST: c07s01b00x00p02n01i01797"
Severity NOTE;
-- testcase code
Assert FALSE
Report "***FAILED TEST: c07s01b00x00p02n01i01797"
Severity ERROR;
wait; -- forever
END PROCESS TESTING;
END c07s01b00x00p02n01i01797arch;
-- CONFIGURATION c07s01b00x00p02n01i01797cfg OF c07s01b00x00p02n01i01797ent IS
-- FOR c07s01b00x00p02n01i01797arch
-- END FOR;
-- END c07s01b00x00p02n01i01797cfg;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1797.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p02n01i01797ent IS
END c07s01b00x00p02n01i01797ent;
ARCHITECTURE c07s01b00x00p02n01i01797arch OF c07s01b00x00p02n01i01797ent IS
-- architecture declaration section
BEGIN
-- architecture statement part
TESTING: PROCESS
BEGIN
-- testcase code
Assert FALSE
Report "***PASSED TEST: c07s01b00x00p02n01i01797"
Severity NOTE;
-- testcase code
Assert FALSE
Report "***FAILED TEST: c07s01b00x00p02n01i01797"
Severity ERROR;
wait; -- forever
END PROCESS TESTING;
END c07s01b00x00p02n01i01797arch;
-- CONFIGURATION c07s01b00x00p02n01i01797cfg OF c07s01b00x00p02n01i01797ent IS
-- FOR c07s01b00x00p02n01i01797arch
-- END FOR;
-- END c07s01b00x00p02n01i01797cfg;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1797.vhd,v 1.2 2001-10-26 16:30:12 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p02n01i01797ent IS
END c07s01b00x00p02n01i01797ent;
ARCHITECTURE c07s01b00x00p02n01i01797arch OF c07s01b00x00p02n01i01797ent IS
-- architecture declaration section
BEGIN
-- architecture statement part
TESTING: PROCESS
BEGIN
-- testcase code
Assert FALSE
Report "***PASSED TEST: c07s01b00x00p02n01i01797"
Severity NOTE;
-- testcase code
Assert FALSE
Report "***FAILED TEST: c07s01b00x00p02n01i01797"
Severity ERROR;
wait; -- forever
END PROCESS TESTING;
END c07s01b00x00p02n01i01797arch;
-- CONFIGURATION c07s01b00x00p02n01i01797cfg OF c07s01b00x00p02n01i01797ent IS
-- FOR c07s01b00x00p02n01i01797arch
-- END FOR;
-- END c07s01b00x00p02n01i01797cfg;
|
Subsets and Splits
No saved queries yet
Save your SQL queries to embed, download, and access them later. Queries will appear here once saved.