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-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2947.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s02b00x00p08n02i02947ent IS
END c02s02b00x00p08n02i02947ent;
ARCHITECTURE c02s02b00x00p08n02i02947arch OF c02s02b00x00p08n02i02947ent IS
procedure proc1 (A:bit; B: out boolean) is
begin
if A = '1' then
B := TRUE;
else
B := FALSE;
end if;
-- Failure_here : label must be the same as subprogram identifier
end proc;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s02b00x00p08n02i02947 - Designator at the end of subprogram body is not the same as the designator of the subprogram."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s02b00x00p08n02i02947arch;
|
--
-- File Name: NameStorePkg.vhd
-- Design Unit Name: NameStorePkg
-- Revision: STANDARD VERSION
--
-- Maintainer: Jim Lewis email: [email protected]
-- Contributor(s):
-- Jim Lewis SynthWorks
--
--
-- Package Defines
-- Data structure for name.
--
-- Developed for:
-- SynthWorks Design Inc.
-- VHDL Training Classes
-- 11898 SW 128th Ave. Tigard, Or 97223
-- http://www.SynthWorks.com
--
-- Revision History:
-- Date Version Description
-- 02/2022 2022.02 Updated NewID for Updated NewID and Find with ParentID and Search.
-- Supports searching in CoveragePkg, ScoreboardGenericPkg, and MemoryPkg.
-- 06/2021 2021.06 Initial revision. Derrived from NamePkg.vhd
--
--
-- This file is part of OSVVM.
--
-- Copyright (c) 2021-2022 by SynthWorks Design Inc.
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- https://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
use std.textio.all ;
use work.ResolutionPkg.all ;
use work.AlertLogPkg.all ;
package NameStorePkg is
type NameIDType is record
ID : integer_max ;
end record NameIDType ;
alias NameStoreIDType is NameIDType ;
type NameIDArrayType is array (integer range <>) of NameIDType ;
type NameSearchType is (PRIVATE, NAME, NAME_AND_PARENT, NAME_AND_PARENT_ELSE_PRIVATE) ;
constant ID_NOT_FOUND : NameIDType := (ID => -1) ;
------------------------------------------------------------
impure function NewID (
iName : String ;
ParentID : AlertLogIdType := ALERTLOG_BASE_ID ;
Search : NameSearchType := NAME
) return NameIDType ;
------------------------------------------------------------
procedure Set (
ID : NameIDType ;
iName : String ;
ParentID : AlertLogIdType := ALERTLOG_BASE_ID ;
Search : NameSearchType := NAME
) ;
impure function Get (ID : NameIDType ; DefaultName : string := "") return string ;
------------------------------------------------------------
impure function Find (
iName : String ;
ParentID : AlertLogIdType := ALERTLOG_BASE_ID ;
Search : NameSearchType := NAME
) return NameIDType ;
impure function GetOpt (ID : NameIDType) return string ;
impure function IsSet (ID : NameIDType) return boolean ;
procedure Clear (ID : NameIDType) ; -- clear name
procedure Deallocate(ID : NameIDType) ; -- effectively alias to clear name
------------------------------------------------------------
-- Helper function for NewID in data structures
function ResolveSearch (
UniqueParent : boolean ;
Search : NameSearchType
) return NameSearchType ;
type NameStorePType is protected
------------------------------------------------------------
impure function NewID (
iName : String ;
ParentID : AlertLogIdType := ALERTLOG_BASE_ID ;
Search : NameSearchType := NAME
) return integer ;
------------------------------------------------------------
procedure Set (
ID : integer ;
iName : String ;
ParentID : AlertLogIdType := ALERTLOG_BASE_ID ;
Search : NameSearchType := NAME
) ;
impure function Get (ID : integer ; DefaultName : string := "") return string ;
------------------------------------------------------------
impure function Find (
iName : String ;
ParentID : AlertLogIdType := ALERTLOG_BASE_ID ;
Search : NameSearchType := NAME
) return integer ;
impure function GetOpt (ID : integer) return string ;
impure function IsSet (ID : integer) return boolean ;
procedure Clear (ID : integer) ; -- clear name
procedure Deallocate(ID : integer) ; -- effectively alias to clear name
end protected NameStorePType ;
end package NameStorePkg ;
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
--- ///////////////////////////////////////////////////////////////////////////
package body NameStorePkg is
type NameStorePType is protected body
type NameItemRecType is record
Name : Line ;
ParentID : AlertLogIDType ;
Search : NameSearchType ;
end record NameItemRecType ;
type NameArrayType is array (integer range <>) of NameItemRecType ;
type NameArrayPtrType is access NameArrayType ;
-- type LineArrayType is array (integer range <>) of Line ;
-- type LineArrayPtrType is access LineArrayType ;
-- variable NameArrayPtr : LineArrayPtrType ;
variable NameArrayPtr : NameArrayPtrType ;
variable NumItems : integer := 0 ;
-- constant MIN_NUM_ITEMS : integer := 4 ; -- Temporarily small for testing
constant MIN_NUM_ITEMS : integer := 32 ; -- Min amount to resize array
------------------------------------------------------------
-- Package Local
function NormalizeArraySize( NewNumItems, MinNumItems : integer ) return integer is
------------------------------------------------------------
variable NormNumItems : integer ;
variable ModNumItems : integer ;
begin
NormNumItems := NewNumItems ;
ModNumItems := NewNumItems mod MinNumItems ;
if ModNumItems > 0 then
NormNumItems := NormNumItems + (MinNumItems - ModNumItems) ;
end if ;
return NormNumItems ;
end function NormalizeArraySize ;
------------------------------------------------------------
-- Package Local
procedure GrowNumberItems (
------------------------------------------------------------
variable ItemArrayPtr : InOut NameArrayPtrType ;
variable NumItems : InOut integer ;
constant GrowAmount : in integer ;
-- constant NewNumItems : in integer ;
-- constant CurNumItems : in integer ;
constant MinNumItems : in integer
) is
variable oldItemArrayPtr : NameArrayPtrType ;
constant NewNumItems : integer := NumItems + GrowAmount ;
constant NewSize : integer := NormalizeArraySize(NewNumItems, MinNumItems) ;
begin
if ItemArrayPtr = NULL then
ItemArrayPtr := new NameArrayType(1 to NewSize) ;
elsif NewNumItems > ItemArrayPtr'length then
oldItemArrayPtr := ItemArrayPtr ;
ItemArrayPtr := new NameArrayType(1 to NewSize) ;
ItemArrayPtr(1 to NumItems) := oldItemArrayPtr(1 to NumItems) ;
deallocate(oldItemArrayPtr) ;
end if ;
NumItems := NewNumItems ;
end procedure GrowNumberItems ;
------------------------------------------------------------
impure function NewID (
------------------------------------------------------------
iName : String ;
ParentID : AlertLogIdType := ALERTLOG_BASE_ID ;
Search : NameSearchType := NAME
) return integer is
begin
GrowNumberItems(NameArrayPtr, NumItems, 1, MIN_NUM_ITEMS) ;
Set(NumItems, iName, ParentID, Search) ;
return NumItems ;
end function NewID ;
------------------------------------------------------------
procedure Set (
------------------------------------------------------------
ID : integer ;
iName : String ;
ParentID : AlertLogIdType := ALERTLOG_BASE_ID ;
Search : NameSearchType := NAME
) is
begin
deallocate(NameArrayPtr(ID).Name) ;
NameArrayPtr(ID).Name := new string'(iName) ;
NameArrayPtr(ID).Search := Search ;
NameArrayPtr(ID).ParentID := ParentID ;
end procedure Set ;
------------------------------------------------------------
impure function Get (ID : integer ; DefaultName : string := "") return string is
------------------------------------------------------------
begin
if NameArrayPtr(ID).Name = NULL then
return DefaultName ;
else
return NameArrayPtr(ID).Name.all ;
end if ;
end function Get ;
------------------------------------------------------------
-- Local
impure function FindName (iName : String) return integer is
------------------------------------------------------------
begin
for ID in 1 to NumItems loop
-- skip if private
next when NameArrayPtr(ID).Search = PRIVATE ;
-- find Name
if iName = NameArrayPtr(ID).Name.all then
return ID ;
end if ;
end loop ;
return ID_NOT_FOUND.ID ;
end function FindName ;
------------------------------------------------------------
-- Local
impure function FindNameAndParent (iName : String; ParentID : AlertLogIdType) return integer is
------------------------------------------------------------
begin
for ID in 1 to NumItems loop
-- skip if private
next when NameArrayPtr(ID).Search = PRIVATE ;
-- find Name and Parent
if iName = NameArrayPtr(ID).Name.all and (ParentID = NameArrayPtr(ID).ParentID or NameArrayPtr(ID).Search = NAME) then
return ID ;
end if ;
end loop ;
return ID_NOT_FOUND.ID ;
end function FindNameAndParent ;
------------------------------------------------------------
impure function Find (
------------------------------------------------------------
iName : String ;
ParentID : AlertLogIdType := ALERTLOG_BASE_ID ;
Search : NameSearchType := NAME
) return integer is
begin
case Search is
when PRIVATE => return ID_NOT_FOUND.ID ;
when NAME => return FindName(iName) ;
when others => return FindNameAndParent(iName, ParentID) ;
end case ;
end function Find ;
------------------------------------------------------------
impure function GetOpt (ID : integer) return string is
------------------------------------------------------------
begin
if NameArrayPtr(ID).Name = NULL then
return NUL & "" ;
else
return NameArrayPtr(ID).Name.all ;
end if ;
end function GetOpt ;
------------------------------------------------------------
impure function IsSet (ID : integer) return boolean is
------------------------------------------------------------
begin
return NameArrayPtr(ID).Name /= NULL ;
end function IsSet ;
------------------------------------------------------------
procedure Clear (ID : integer) is
------------------------------------------------------------
begin
deallocate(NameArrayPtr(ID).Name) ;
end procedure Clear ;
------------------------------------------------------------
procedure Deallocate(ID : integer) is
------------------------------------------------------------
begin
Clear(ID) ;
end procedure Deallocate ;
end protected body NameStorePType ;
-- /////////////////////////////////////////
-- /////////////////////////////////////////
-- Singleton Data Structure
-- /////////////////////////////////////////
-- /////////////////////////////////////////
shared variable NameStore : NameStorePType ;
------------------------------------------------------------
impure function NewID (
------------------------------------------------------------
iName : String ;
ParentID : AlertLogIdType := ALERTLOG_BASE_ID ;
Search : NameSearchType := NAME
) return NameIDType is
variable Result : NameIDType ;
begin
Result.ID := NameStore.NewID(iName) ;
return Result ;
end function NewID ;
------------------------------------------------------------
procedure Set (
------------------------------------------------------------
ID : NameIDType ;
iName : String ;
ParentID : AlertLogIdType := ALERTLOG_BASE_ID ;
Search : NameSearchType := NAME
) is
begin
NameStore.set(ID.ID, iName) ;
end procedure Set ;
------------------------------------------------------------
impure function Get (ID : NameIDType ; DefaultName : string := "") return string is
------------------------------------------------------------
begin
return NameStore.Get(ID.ID, DefaultName) ;
end function Get ;
------------------------------------------------------------
impure function Find (
------------------------------------------------------------
iName : String ;
ParentID : AlertLogIdType := ALERTLOG_BASE_ID ;
Search : NameSearchType := NAME
) return NameIDType is
begin
return NameIDType'(ID => NameStore.Find(iName)) ;
end function Find ;
------------------------------------------------------------
impure function GetOpt (ID : NameIDType) return string is
------------------------------------------------------------
begin
return NameStore.Get(ID.ID) ;
end function GetOpt ;
------------------------------------------------------------
impure function IsSet (ID : NameIDType) return boolean is
------------------------------------------------------------
begin
return NameStore.IsSet(ID.ID) ;
end function IsSet ;
------------------------------------------------------------
procedure Clear (ID : NameIDType) is
------------------------------------------------------------
begin
NameStore.Clear(ID.ID) ;
end procedure Clear ;
------------------------------------------------------------
procedure Deallocate(ID : NameIDType) is
------------------------------------------------------------
begin
NameStore.Clear(ID.ID) ;
end procedure Deallocate ;
------------------------------------------------------------
-- Helper function for NewID in data structures
function ResolveSearch (
------------------------------------------------------------
UniqueParent : boolean ;
Search : NameSearchType
) return NameSearchType is
variable result : NameSearchType ;
begin
if search = NAME_AND_PARENT_ELSE_PRIVATE then
result := NAME_AND_PARENT when UniqueParent else PRIVATE ;
else
result := Search ;
end if ;
return result ;
end function ResolveSearch ;
end package body NameStorePkg ; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.fastfilter_types.all;
entity fastfilterElement is
generic(
KERNEL_SIZE : integer;
PIXEL_SIZE : integer
);
port(
clk : in std_logic;
reset_n : in std_logic;
enable : in std_logic;
in_data : in pixel_array (0 to KERNEL_SIZE * KERNEL_SIZE - 1);
in_dv : in std_logic;
in_fv : in std_logic;
in_kernel : in pixel_array (0 to KERNEL_SIZE * KERNEL_SIZE - 1);
in_norm : in std_logic_vector(PIXEL_SIZE-1 downto 0);
out_data : out std_logic_vector(PIXEL_SIZE-1 downto 0);
out_dv : out std_logic;
out_fv : out std_logic
);
end fastfilterElement;
architecture bhv of fastfilterElement is
-- Signals
type pixel_array_s1 is array (0 to KERNEL_SIZE * KERNEL_SIZE - 1) of signed (PIXEL_SIZE downto 0);
signal px : pixel_array_s1 ;
signal kernel_s : pixel_array_s1 ;
signal res : signed (PIXEL_SIZE downto 0);
signal all_valid : std_logic;
signal tmp0 : signed(pixel_size downto 0);
signal tmp1 : signed(pixel_size downto 0);
signal tmp2 : signed(pixel_size downto 0);
signal tmp3 : signed(pixel_size downto 0);
signal tmp4 : signed(pixel_size downto 0);
signal tmp5 : signed(pixel_size downto 0);
signal tmp6 : signed(pixel_size downto 0);
signal tmp7 : signed(pixel_size downto 0);
signal tmp8 : signed(pixel_size downto 0);
signal tmp9 : signed(pixel_size downto 0);
signal tmp10 : signed(pixel_size downto 0);
signal tmp11 : signed(pixel_size downto 0);
signal tmp12 : signed(pixel_size downto 0);
signal px1 : signed(pixel_size downto 0);
signal px2 : signed(pixel_size downto 0);
signal px3 : signed(pixel_size downto 0);
begin
-- All valid : Logic and
all_valid <= in_dv and in_fv and enable;
UNSIGNED_CAST : for i in 0 to ( KERNEL_SIZE * KERNEL_SIZE - 1 ) generate
px(i) <= signed('0' & in_data(i));
end generate;
process(clk)
begin
if (all_valid='1') then
tmp0 <= px(0);
tmp1 <= px(1);
tmp2 <= px(2);
tmp3 <= px(3);
tmp4 <= px(4);
tmp5 <= px(5);
tmp6 <= px(6);
tmp7 <= px(7);
tmp8 <= px(8);
tmp9 <= px(9);
tmp10 <= px(10);
tmp11 <= px(11);
tmp12 <= px(12);
px1 <= px(13);
px2 <= px(18);
px3 <= px(17);
if ( (tmp12(0) = '1')
and (tmp0(0) = '0')
and (tmp1(0) = '0')
and (tmp2(0) = '0')
and (tmp3(0) = '0')
and (tmp4(0) = '0')
and (tmp5(0) = '0')
and (tmp6(0) = '0')
and (tmp7(0) = '0')
and (tmp8(0) = '0')
and (tmp9(0) = '0')
and (tmp10(0) = '0')
and (tmp11(0) = '0')) then
if ( px1(0) = '1' and px2(0) = '0' and px3(0) = '0' and px1 < tmp11 ) then
res <= (others => '1');
elsif ( px1(0) = '0' and px2(0) = '1' and px3(0) = '0' and px2 < tmp11 ) then
res <= (others => '1');
elsif ( px1(0) = '0' and px2(0) = '0' and px3(0) = '1' and px3 < tmp11 ) then
res <= (others => '1');
elsif ( px1(0) = '1' and px2(0) = '1' and px3(0) = '0' and px1 < tmp11 and px2 < tmp11) then
res <= (others => '1');
elsif ( px1(0) = '1' and px2(0) = '0' and px3(0) = '1' and px1 < tmp11 and px3 < tmp11 ) then
res <= (others => '1');
elsif ( px1(0) = '0' and px2(0) = '1' and px3(0) = '1' and px2 < tmp11 and px3 < tmp11 ) then
res <= (others => '1');
elsif ( px1(0) = '1' and px2(0) = '1' and px3(0) = '0' and px1 < tmp11 and px2 < tmp11 ) then
res <= (others => '1');
elsif ( px1(0) = '1' and px2(0) = '1' and px3(0) = '1' and px1 < tmp11 and px3 < tmp11 and px2 < tmp11) then
res <= (others => '1');
elsif ( px1(0) = '0' and px2(0) = '0' and px3(0) = '0' ) then
res <= (others => '1');
end if;
else
res <= px(11);
end if;
end if;
out_data <= std_logic_vector (res(PIXEL_SIZE-1 downto 0));
end process;
out_fv <= in_fv;
out_dv <= in_dv;
end bhv;
|
--------------------------------------------------------------------------------
-- (c) Copyright 1995 - 2010 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectual property --
-- laws. --
-- --
-- DISCLAIMER --
-- This disclaimer is not a license and does not grant any --
-- rights to the materials distributed herewith. Except as --
-- otherwise provided in a valid license issued to you by --
-- Xilinx, and to the maximum extent permitted by applicable --
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --
-- (2) Xilinx shall not be liable (whether in contract or tort, --
-- including negligence, or under any other theory of --
-- liability) for any loss or damage of any kind or nature --
-- related to, arising under or in connection with these --
-- materials, including for any direct, or any indirect, --
-- special, incidental, or consequential loss or damage --
-- (including loss of data, profits, goodwill, or any type of --
-- loss or damage suffered as a result of any action brought --
-- by a third party) even if such damage or loss was --
-- reasonably foreseeable or Xilinx had been advised of the --
-- possibility of the same. --
-- --
-- CRITICAL APPLICATIONS --
-- Xilinx products are not designed or intended to be fail- --
-- safe, or for use in any application requiring fail-safe --
-- performance, such as life-support or safety devices or --
-- systems, Class III medical devices, nuclear facilities, --
-- applications related to the deployment of airbags, or any --
-- other applications that could lead to death, personal --
-- injury, or severe property or environmental damage --
-- (individually and collectively, "Critical --
-- Applications"). Customer assumes the sole risk and --
-- liability of any use of Xilinx products in Critical --
-- Applications, subject only to applicable laws and --
-- regulations governing limitations on product liability. --
-- --
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --
-- PART OF THIS FILE AT ALL TIMES. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file shift_ram.vhd when simulating
-- the core, shift_ram. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY shift_ram IS
port (
d: in std_logic_vector(26 downto 0);
clk: in std_logic;
ce: in std_logic;
q: out std_logic_vector(26 downto 0));
END shift_ram;
ARCHITECTURE shift_ram_a OF shift_ram IS
-- synthesis translate_off
component wrapped_shift_ram
port (
d: in std_logic_vector(26 downto 0);
clk: in std_logic;
ce: in std_logic;
q: out std_logic_vector(26 downto 0));
end component;
-- Configuration specification
for all : wrapped_shift_ram use entity XilinxCoreLib.c_shift_ram_v11_0(behavioral)
generic map(
c_parser_type => 0,
c_read_mif => 0,
c_has_a => 0,
c_sync_priority => 1,
c_opt_goal => 0,
c_has_sclr => 0,
c_width => 27,
c_verbosity => 0,
c_ainit_val => "000000000000000000000000000",
c_has_ce => 1,
c_sync_enable => 0,
c_depth => 797,
c_sinit_val => "000000000000000000000000000",
c_has_sset => 0,
c_has_sinit => 0,
c_mem_init_file => "no_coe_file_loaded",
c_shift_type => 0,
c_default_data => "000000000000000000000000000",
c_reg_last_bit => 1,
c_xdevicefamily => "virtex5",
c_addr_width => 4);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_shift_ram
port map (
d => d,
clk => clk,
ce => ce,
q => q);
-- synthesis translate_on
END shift_ram_a;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Brett Bourgeois
--
-- Create Date: 11:49:41 04/24/2015
-- Design Name:
-- Module Name: decode_dp - Structural
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE work.UMDRISC_pkg.ALL;
use work.all;
entity decode is
port (
--Input
clk: in std_logic;
rst: in std_logic;
--
ADRS_A: in std_logic_vector (3 downto 0);
ADRS_B: in std_logic_vector (3 downto 0);
imm: in std_logic_vector (3 downto 0);
instruction: in std_logic_vector (15 downto 0);
--Control Signals
imm_mux_sel: in std_logic;
--Output
--==
imm_out : out std_logic
--==
);
end decode;
architecture Structural of decode is
signal imm_mux_out: std_logic_vector(7 downto 0) := (others => '0');
begin
--MUX2to1
MUX2to1: entity work.MUX2to1
generic map( vectorSize => adrs_width)
port map(
SEL => imm_mux_sel,
IN_1 => ADRS_B,
IN_2 => imm,
OUTPUT => imm_mux_out
);
--Register Bank
-- regBank: entity work.regbank
-- port map(
-- );
--registers to hold data
end Structural;
architecture behavioral of decode is
begin
end behavioral;
|
-- NEED RESULT: ARCH00179.P1: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00179.P2: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00179.P3: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00179.P4: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00179.P5: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00179.P6: Multi inertial transactions occurred on signal asg with slice name prefixed by a selected name on LHS passed
-- NEED RESULT: ARCH00179: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS passed
-- NEED RESULT: ARCH00179: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS passed
-- NEED RESULT: ARCH00179: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS passed
-- NEED RESULT: ARCH00179: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS passed
-- NEED RESULT: ARCH00179: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS passed
-- NEED RESULT: ARCH00179: One inertial transaction occurred on signal asg with slice name prefixed by an selected name on LHS passed
-- NEED RESULT: P6: Inertial transactions entirely completed failed
-- NEED RESULT: P5: Inertial transactions entirely completed failed
-- NEED RESULT: P4: Inertial transactions entirely completed failed
-- NEED RESULT: P3: Inertial transactions entirely completed failed
-- NEED RESULT: P2: Inertial transactions entirely completed failed
-- NEED RESULT: P1: Inertial transactions entirely completed failed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00179
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (1)
-- 8.3 (2)
-- 8.3 (4)
-- 8.3 (5)
-- 8.3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- PKG00179
-- PKG00179/BODY
-- E00000(ARCH00179)
-- ENT00179_Test_Bench(ARCH00179_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
package PKG00179 is
type r_st_arr1_vector is record
f1 : integer ;
f2 : st_arr1_vector ;
end record ;
function c_r_st_arr1_vector_1 return r_st_arr1_vector ;
-- (c_integer_1, c_st_arr1_vector_1) ;
function c_r_st_arr1_vector_2 return r_st_arr1_vector ;
-- (c_integer_2, c_st_arr1_vector_2) ;
--
type r_st_arr2_vector is record
f1 : integer ;
f2 : st_arr2_vector ;
end record ;
function c_r_st_arr2_vector_1 return r_st_arr2_vector ;
-- (c_integer_1, c_st_arr2_vector_1) ;
function c_r_st_arr2_vector_2 return r_st_arr2_vector ;
-- (c_integer_2, c_st_arr2_vector_2) ;
--
type r_st_arr3_vector is record
f1 : integer ;
f2 : st_arr3_vector ;
end record ;
function c_r_st_arr3_vector_1 return r_st_arr3_vector ;
-- (c_integer_1, c_st_arr3_vector_1) ;
function c_r_st_arr3_vector_2 return r_st_arr3_vector ;
-- (c_integer_2, c_st_arr3_vector_2) ;
--
type r_st_rec1_vector is record
f1 : integer ;
f2 : st_rec1_vector ;
end record ;
function c_r_st_rec1_vector_1 return r_st_rec1_vector ;
-- (c_integer_1, c_st_rec1_vector_1) ;
function c_r_st_rec1_vector_2 return r_st_rec1_vector ;
-- (c_integer_2, c_st_rec1_vector_2) ;
--
type r_st_rec2_vector is record
f1 : integer ;
f2 : st_rec2_vector ;
end record ;
function c_r_st_rec2_vector_1 return r_st_rec2_vector ;
-- (c_integer_1, c_st_rec2_vector_1) ;
function c_r_st_rec2_vector_2 return r_st_rec2_vector ;
-- (c_integer_2, c_st_rec2_vector_2) ;
--
type r_st_rec3_vector is record
f1 : integer ;
f2 : st_rec3_vector ;
end record ;
function c_r_st_rec3_vector_1 return r_st_rec3_vector ;
-- (c_integer_1, c_st_rec3_vector_1) ;
function c_r_st_rec3_vector_2 return r_st_rec3_vector ;
-- (c_integer_2, c_st_rec3_vector_2) ;
--
--
end PKG00179 ;
--
package body PKG00179 is
function c_r_st_arr1_vector_1 return r_st_arr1_vector
is begin
return (c_integer_1, c_st_arr1_vector_1) ;
end c_r_st_arr1_vector_1 ;
--
function c_r_st_arr1_vector_2 return r_st_arr1_vector
is begin
return (c_integer_2, c_st_arr1_vector_2) ;
end c_r_st_arr1_vector_2 ;
--
--
function c_r_st_arr2_vector_1 return r_st_arr2_vector
is begin
return (c_integer_1, c_st_arr2_vector_1) ;
end c_r_st_arr2_vector_1 ;
--
function c_r_st_arr2_vector_2 return r_st_arr2_vector
is begin
return (c_integer_2, c_st_arr2_vector_2) ;
end c_r_st_arr2_vector_2 ;
--
--
function c_r_st_arr3_vector_1 return r_st_arr3_vector
is begin
return (c_integer_1, c_st_arr3_vector_1) ;
end c_r_st_arr3_vector_1 ;
--
function c_r_st_arr3_vector_2 return r_st_arr3_vector
is begin
return (c_integer_2, c_st_arr3_vector_2) ;
end c_r_st_arr3_vector_2 ;
--
--
function c_r_st_rec1_vector_1 return r_st_rec1_vector
is begin
return (c_integer_1, c_st_rec1_vector_1) ;
end c_r_st_rec1_vector_1 ;
--
function c_r_st_rec1_vector_2 return r_st_rec1_vector
is begin
return (c_integer_2, c_st_rec1_vector_2) ;
end c_r_st_rec1_vector_2 ;
--
--
function c_r_st_rec2_vector_1 return r_st_rec2_vector
is begin
return (c_integer_1, c_st_rec2_vector_1) ;
end c_r_st_rec2_vector_1 ;
--
function c_r_st_rec2_vector_2 return r_st_rec2_vector
is begin
return (c_integer_2, c_st_rec2_vector_2) ;
end c_r_st_rec2_vector_2 ;
--
--
function c_r_st_rec3_vector_1 return r_st_rec3_vector
is begin
return (c_integer_1, c_st_rec3_vector_1) ;
end c_r_st_rec3_vector_1 ;
--
function c_r_st_rec3_vector_2 return r_st_rec3_vector
is begin
return (c_integer_2, c_st_rec3_vector_2) ;
end c_r_st_rec3_vector_2 ;
--
--
--
end PKG00179 ;
--
use WORK.STANDARD_TYPES.all ;
use WORK.PKG00179.all ;
architecture ARCH00179 of E00000 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_r_st_arr1_vector : chk_sig_type := -1 ;
signal chk_r_st_arr2_vector : chk_sig_type := -1 ;
signal chk_r_st_arr3_vector : chk_sig_type := -1 ;
signal chk_r_st_rec1_vector : chk_sig_type := -1 ;
signal chk_r_st_rec2_vector : chk_sig_type := -1 ;
signal chk_r_st_rec3_vector : chk_sig_type := -1 ;
--
signal s_r_st_arr1_vector : r_st_arr1_vector
:= c_r_st_arr1_vector_1 ;
signal s_r_st_arr2_vector : r_st_arr2_vector
:= c_r_st_arr2_vector_1 ;
signal s_r_st_arr3_vector : r_st_arr3_vector
:= c_r_st_arr3_vector_1 ;
signal s_r_st_rec1_vector : r_st_rec1_vector
:= c_r_st_rec1_vector_1 ;
signal s_r_st_rec2_vector : r_st_rec2_vector
:= c_r_st_rec2_vector_1 ;
signal s_r_st_rec3_vector : r_st_rec3_vector
:= c_r_st_rec3_vector_1 ;
--
begin
P1 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr1_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00179.P1" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr1_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr1_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00179" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00179" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr1_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr1_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00179" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_arr1_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00179" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00179" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_arr1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_r_st_arr1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_r_st_arr1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions entirely completed",
chk_r_st_arr1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
P2 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr2_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00179.P2" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr2_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr2_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00179" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00179" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr2_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr2_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00179" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_arr2_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00179" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00179" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_arr2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_r_st_arr2_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P2 ;
--
PGEN_CHKP_2 :
process ( chk_r_st_arr2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions entirely completed",
chk_r_st_arr2_vector = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
P3 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr3_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00179.P3" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr3_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr3_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00179" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00179" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr3_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_arr3_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00179" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_arr3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_arr3_vector.f2 (lowb+1 to highb-1) =
c_r_st_arr3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00179" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00179" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_arr3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_r_st_arr3_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P3 ;
--
PGEN_CHKP_3 :
process ( chk_r_st_arr3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions entirely completed",
chk_r_st_arr3_vector = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
P4 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec1_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00179.P4" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec1_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec1_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00179" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00179" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec1_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec1_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00179" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec1_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_rec1_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec1_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00179" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00179" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_r_st_rec1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P4 ;
--
PGEN_CHKP_4 :
process ( chk_r_st_rec1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Inertial transactions entirely completed",
chk_r_st_rec1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
--
P5 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec2_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00179.P5" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec2_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec2_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00179" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00179" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec2_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec2_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00179" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec2_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_rec2_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec2_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00179" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00179" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_r_st_rec2_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P5 ;
--
PGEN_CHKP_5 :
process ( chk_r_st_rec2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Inertial transactions entirely completed",
chk_r_st_rec2_vector = 8 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
--
P6 :
process
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
begin
case counter is
when 0
=> s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec3_vector_2.f2
(lowb+1 to highb-1) after 10 ns,
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00179.P6" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name prefixed by a selected name on LHS",
correct ) ;
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec3_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec3_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 5 ns ;
--
when 4
=> correct :=
correct and
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00179" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <= transport
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 100 ns ;
--
when 5
=> correct :=
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00179" ,
"Old transactions were removed on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec3_vector_2.f2
(lowb+1 to highb-1) after 10 ns ,
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 20 ns ,
c_r_st_rec3_vector_2.f2
(lowb+1 to highb-1) after 30 ns ,
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 6
=> correct :=
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_2.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00179" ,
"One inertial transaction occurred on signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
-- Last transaction above is marked
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) <=
c_r_st_rec3_vector_1.f2
(lowb+1 to highb-1) after 40 ns ;
--
when 7
=> correct :=
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_r_st_rec3_vector.f2 (lowb+1 to highb-1) =
c_r_st_rec3_vector_1.f2 (lowb+1 to highb-1) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00179" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00179" ,
"Inertial semantics check on a signal " &
"asg with slice name prefixed by an selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_r_st_rec3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
wait until (not s_r_st_rec3_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P6 ;
--
PGEN_CHKP_6 :
process ( chk_r_st_rec3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Inertial transactions entirely completed",
chk_r_st_rec3_vector = 8 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
--
--
end ARCH00179 ;
--
entity ENT00179_Test_Bench is
end ENT00179_Test_Bench ;
--
architecture ARCH00179_Test_Bench of ENT00179_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00179 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00179_Test_Bench ;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity cnt02 is
port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
low : out std_logic
);
end cnt02;
architecture behav of cnt02 is
signal counter : integer range 0 to 63;
begin
process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
counter <= 63;
else
counter <= counter - 1;
end if;
end if;
end process;
low <= '1' when counter < 60 else '0';
end behav;
|
-----------------------------------------------------------------------------------------
-- --
-- This file is part of the CAPH Compiler distribution --
-- http://caph.univ-bpclermont.fr --
-- --
-- Jocelyn SEROT --
-- [email protected] --
-- --
-- Copyright 2011-2015 Jocelyn SEROT. All rights reserved. --
-- This file is distributed under the terms of the GNU Library General Public License --
-- with the special exception on linking described in file ../LICENSE. --
-- --
-----------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package core is
function cond(e1: boolean; e2: signed; e3: signed) return signed;
function cond(e1: boolean; e2: unsigned; e3: unsigned) return unsigned;
function cond(e1: boolean; e2: std_logic_vector; e3: std_logic_vector) return std_logic_vector;
function eq(e1: signed; e2: signed) return unsigned;
function eq(e1: unsigned; e2: unsigned) return unsigned;
function mul(e1: signed; e2: signed) return signed;
function mul(e1: unsigned; e2: unsigned) return unsigned;
function to_std_logic_vector(e: unsigned; s: natural) return std_logic_vector;
function to_std_logic_vector(e: signed; s: natural) return std_logic_vector;
function to_std_logic_vector(e: boolean; s: natural) return std_logic_vector;
function from_std_logic_vector(e: std_logic_vector; s: natural) return unsigned;
function from_std_logic_vector(e: std_logic_vector; s: natural) return signed;
function from_std_logic_vector(e: std_logic_vector; s: natural) return boolean;
function from_std_logic_vector(e: std_logic_vector; s: natural) return std_logic_vector;
function to_bool(e: unsigned) return boolean;
function to_bool(e: signed) return boolean;
function to_bool(e: std_logic_vector) return boolean;
function conv_unsigned(e: unsigned; s: natural) return unsigned;
function conv_unsigned(e: signed; s: natural) return unsigned;
function conv_unsigned(e: boolean; s: natural) return unsigned;
function conv_unsigned(e: integer; s: natural) return unsigned;
function conv_signed(e: signed; s: natural) return signed;
function conv_signed(e: unsigned; s: natural) return signed;
function conv_signed(e: boolean; s: natural) return signed;
function conv_signed(e: integer; s: natural) return signed;
function to_integer(e: integer) return integer;
function to_string(v : std_logic_vector) return string; -- for debug only
procedure dump_slv(name: string; v: std_logic_vector); -- for debug only
component stream_in is
generic ( filename: string := "input.bin"; size: integer := 10; period: integer := 2; blanking: boolean := false );
port ( full : in std_logic;
dout : out std_logic_vector(size-1 downto 0);
wr : out std_logic; -- write (push) signal, active 1 on clk^
clk : in std_logic;
rst : in std_logic
);
end component;
component stream_out is
generic ( filename: string := "vhdl_result.dat"; size: integer := 10);
port ( empty : in std_logic;
din : in std_logic_vector(size-1 downto 0);
rd : out std_logic; -- read (pop) signal
clk : in std_logic;
rst : in std_logic
);
end component;
component port_in is
generic ( filename: string := ""; size: integer := 10; ival: bit_vector);
port ( full : in std_logic;
dout : out std_logic_vector(size-1 downto 0);
wr : out std_logic; -- write (push) signal, active 1 on clk^
clk : in std_logic;
rst : in std_logic
);
end component;
component port_out is
generic ( filename: string := "result.bin"; size: integer := 10 );
port ( empty : in std_logic;
din : in std_logic_vector(size-1 downto 0);
rd : out std_logic; -- read (pop) signal, active 1 on clk^
clk : in std_logic;
rst : in std_logic
);
end component;
--~
--~ component split2 is
--~ generic ( size: integer := 10);
--~ port (
--~ d_f: out std_logic;
--~ d : in std_logic_vector (size-1 downto 0);
--~ d_wr : in std_logic;
--~ d1_f : in std_logic;
--~ d1 : out std_logic_vector(size-1 downto 0);
--~ d1_wr : out std_logic;
--~ d2_f : in std_logic;
--~ d2 : out std_logic_vector(size-1 downto 0);
--~ d2_wr : out std_logic
--~ );
--~ end component;
--~
--~ component split3 is
--~ generic ( size: integer := 10);
--~ port (
--~ d_f: out std_logic;
--~ d : in std_logic_vector (size-1 downto 0);
--~ d_wr : in std_logic;
--~ d1_f : in std_logic;
--~ d1 : out std_logic_vector(size-1 downto 0);
--~ d1_wr : out std_logic;
--~ d2_f : in std_logic;
--~ d2 : out std_logic_vector(size-1 downto 0);
--~ d2_wr : out std_logic;
--~ d3_f : in std_logic;
--~ d3 : out std_logic_vector(size-1 downto 0);
--~ d3_wr : out std_logic
--~ );
--~ end component;
--~
--~ component split4 is
--~ generic ( size: integer := 10);
--~ port (
--~ d_f: out std_logic;
--~ d : in std_logic_vector (size-1 downto 0);
--~ d_wr : in std_logic;
--~ d1_f : in std_logic;
--~ d1 : out std_logic_vector(size-1 downto 0);
--~ d1_wr : out std_logic;
--~ d2_f : in std_logic;
--~ d2 : out std_logic_vector(size-1 downto 0);
--~ d2_wr : out std_logic;
--~ d3_f : in std_logic;
--~ d3 : out std_logic_vector(size-1 downto 0);
--~ d3_wr : out std_logic;
--~ d4_f : in std_logic;
--~ d4 : out std_logic_vector(size-1 downto 0);
--~ d4_wr : out std_logic
--~ );
--~ end component;
--~
--~ component split5 is
--~ generic ( size: integer := 10);
--~ port (
--~ d_f: out std_logic;
--~ d : in std_logic_vector (size-1 downto 0);
--~ d_wr : in std_logic;
--~ d1_f : in std_logic;
--~ d1 : out std_logic_vector(size-1 downto 0);
--~ d1_wr : out std_logic;
--~ d2_f : in std_logic;
--~ d2 : out std_logic_vector(size-1 downto 0);
--~ d2_wr : out std_logic;
--~ d3_f : in std_logic;
--~ d3 : out std_logic_vector(size-1 downto 0);
--~ d3_wr : out std_logic;
--~ d4_f : in std_logic;
--~ d4 : out std_logic_vector(size-1 downto 0);
--~ d4_wr : out std_logic;
--~ d5_f : in std_logic;
--~ d5 : out std_logic_vector(size-1 downto 0);
--~ d5_wr : out std_logic
--~ );
--~ end component;
--~
--~ component split6 is
--~ generic ( size: integer := 10);
--~ port (
--~ d_f: out std_logic;
--~ d : in std_logic_vector (size-1 downto 0);
--~ d_wr : in std_logic;
--~ d1_f : in std_logic;
--~ d1 : out std_logic_vector(size-1 downto 0);
--~ d1_wr : out std_logic;
--~ d2_f : in std_logic;
--~ d2 : out std_logic_vector(size-1 downto 0);
--~ d2_wr : out std_logic;
--~ d3_f : in std_logic;
--~ d3 : out std_logic_vector(size-1 downto 0);
--~ d3_wr : out std_logic;
--~ d4_f : in std_logic;
--~ d4 : out std_logic_vector(size-1 downto 0);
--~ d4_wr : out std_logic;
--~ d5_f : in std_logic;
--~ d5 : out std_logic_vector(size-1 downto 0);
--~ d5_wr : out std_logic;
--~ d6_f : in std_logic;
--~ d6 : out std_logic_vector(size-1 downto 0);
--~ d6_wr : out std_logic
--~ );
--~ end component;
--component decoder is
-- generic ( size: integer := 8 )
-- port (
-- sel: in integer;
-- outp: std_logic_vector ( size-1 downto 0)
-- );
--end component;
end core;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- use STD.textio.all; -- FOR DEBUG ONLY
package body core is
function cond(e1: boolean; e2: signed; e3: signed) return signed is
begin
if e1 then return e2; else return e3; end if;
end;
function cond(e1: boolean; e2: unsigned; e3: unsigned) return unsigned is
begin
if e1 then return e2; else return e3; end if;
end;
function cond(e1: boolean; e2: std_logic_vector; e3: std_logic_vector) return std_logic_vector is
begin
if e1 then return e2; else return e3; end if;
end;
function eq(e1: signed; e2: signed) return unsigned is
begin
if ( e1 = e2 ) then
return "1";
else
return "0";
end if;
end;
function eq(e1: unsigned; e2: unsigned) return unsigned is
begin
if ( e1 = e2 ) then
return "1";
else
return "0";
end if;
end;
function maximum(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function mul (e1: signed; e2: signed) return signed is
constant length: INTEGER := maximum(e1'length, e2'length);
begin
return resize(e1*e2, length);
end;
function mul (e1: unsigned; e2: unsigned) return unsigned is
constant length: INTEGER := maximum(e1'length, e2'length);
begin
return resize(e1*e2, length);
end;
function to_std_logic_vector(e: unsigned; s:natural) return std_logic_vector is
begin
return STD_LOGIC_VECTOR(resize(e,s));
end;
function to_std_logic_vector(e: signed; s:natural) return std_logic_vector is
begin
return STD_LOGIC_VECTOR(resize(e,s));
end;
function to_std_logic_vector(e: boolean; s:natural) return std_logic_vector is
begin
if e then
return STD_LOGIC_VECTOR(TO_UNSIGNED(0,s-1)) & "1";
else
return STD_LOGIC_VECTOR(TO_UNSIGNED(0,s-1)) & "0";
end if;
end;
function from_std_logic_vector(e: std_logic_vector; s:natural) return unsigned is
begin
-- return UNSIGNED(e(s-1 downto 0));
-- return UNSIGNED(e(e'high downto e'high-s+1));
return UNSIGNED(e(s-1 downto 0)); -- Changed in v2.6.2: in variants, fields are RIGHT justified
end;
function from_std_logic_vector(e: std_logic_vector; s:natural) return signed is
begin
-- return SIGNED(e(s-1 downto 0));
-- return SIGNED(e(e'high downto e'high-s+1));
return SIGNED(e(s-1 downto 0)); -- Changed in v2.6.2: in variants, fields are RIGHT justified
end;
function from_std_logic_vector(e: std_logic_vector; s:natural) return boolean is
begin
-- if e(e'high downto e'high) = "1" then
if e(0 downto 0) = "1" then -- Changed in v2.6.2: in variants, fields are RIGHT justified
return true;
else
return false;
end if;
end;
function from_std_logic_vector(e: std_logic_vector; s:natural) return std_logic_vector is
begin
return (e(s-1 downto 0)); -- Changed in v2.6.2: in variants, fields are RIGHT justified
-- return e(e'high downto e'high-s+1);
end;
function to_bool(e: unsigned) return boolean is
begin
if e = (e'range=>'0') then return false; else return true; end if;
end;
function to_bool(e: signed) return boolean is
begin
if e = (e'range=>'0') then return false; else return true; end if;
end;
function to_bool(e: std_logic_vector) return boolean is
begin
if e = (e'range=>'0') then return false; else return true; end if;
end;
function conv_unsigned(e: unsigned; s: natural) return unsigned is
begin
return resize(e, s);
end;
function conv_unsigned(e: signed; s: natural) return unsigned is
begin
return resize(unsigned(e), s);
end;
function conv_unsigned(e: boolean; s: natural) return unsigned is
begin
if ( e ) then return to_unsigned(1,s); else return to_unsigned(0,s); end if;
end;
function conv_unsigned(e: integer; s: natural) return unsigned is
begin
return to_unsigned(e,s);
end;
function conv_signed(e: signed; s: natural) return signed is
begin
return resize(e, s);
end;
function conv_signed(e: unsigned; s: natural) return signed is
begin
return resize(signed('0' & e), s);
end;
function conv_signed(e: boolean; s: natural) return signed is
begin
if ( e ) then return to_signed(1,s); else return to_signed(0,s); end if;
end;
function conv_signed(e: integer; s: natural) return signed is
begin
return to_signed(e,s);
end;
function to_integer(e: integer) return integer is
begin
return e;
end;
-- Debug aux fns
function to_string(v : std_logic_vector) return string is
variable s : string(1 to v'length) := (others => 'x');
variable c : string(1 to 3);
variable j : integer := 1;
begin
for i in v'high downto v'low loop
c := std_logic'image(v(i));
s(j to j) := c(2 to 2); -- c is a 3 character string (with quotes) !
j := j+1;
end loop;
return s;
end to_string;
procedure dump_slv(name: string; v: std_logic_vector) is
begin
report name & "[" & integer'image(v'high) & ":" & integer'image(v'low) & "]=" & to_string(v);
end;
end package body core;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2272.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p14n01i02272ent IS
END c07s02b06x00p14n01i02272ent;
ARCHITECTURE c07s02b06x00p14n01i02272arch OF c07s02b06x00p14n01i02272ent IS
signal SS : TIME;
BEGIN
TESTING: PROCESS
variable A : TIME := 3 * 11 ns;
variable R : REAL := 7.9999;
variable S : INTEGER := 1;
BEGIN
SS <= R * ( S * A ); -- context 4
wait for 10 ns;
assert NOT((-0.01 ns < (SS - 3*11*7.9999 ns)) and ((SS - 3*11*7.9999 ns) < 0.01 ns))
report "***PASSED TEST: c07s02b06x00p14n01i02272"
severity NOTE;
assert ((-0.01 ns < (SS - 3*11*7.9999 ns)) and ((SS - 3*11*7.9999 ns) < 0.01 ns))
report "***FAILED TEST: c07s02b06x00p14n01i02272 - The left operand of the multiplication operation can be an integer type and the right operand of physical type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p14n01i02272arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2272.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p14n01i02272ent IS
END c07s02b06x00p14n01i02272ent;
ARCHITECTURE c07s02b06x00p14n01i02272arch OF c07s02b06x00p14n01i02272ent IS
signal SS : TIME;
BEGIN
TESTING: PROCESS
variable A : TIME := 3 * 11 ns;
variable R : REAL := 7.9999;
variable S : INTEGER := 1;
BEGIN
SS <= R * ( S * A ); -- context 4
wait for 10 ns;
assert NOT((-0.01 ns < (SS - 3*11*7.9999 ns)) and ((SS - 3*11*7.9999 ns) < 0.01 ns))
report "***PASSED TEST: c07s02b06x00p14n01i02272"
severity NOTE;
assert ((-0.01 ns < (SS - 3*11*7.9999 ns)) and ((SS - 3*11*7.9999 ns) < 0.01 ns))
report "***FAILED TEST: c07s02b06x00p14n01i02272 - The left operand of the multiplication operation can be an integer type and the right operand of physical type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p14n01i02272arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2272.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p14n01i02272ent IS
END c07s02b06x00p14n01i02272ent;
ARCHITECTURE c07s02b06x00p14n01i02272arch OF c07s02b06x00p14n01i02272ent IS
signal SS : TIME;
BEGIN
TESTING: PROCESS
variable A : TIME := 3 * 11 ns;
variable R : REAL := 7.9999;
variable S : INTEGER := 1;
BEGIN
SS <= R * ( S * A ); -- context 4
wait for 10 ns;
assert NOT((-0.01 ns < (SS - 3*11*7.9999 ns)) and ((SS - 3*11*7.9999 ns) < 0.01 ns))
report "***PASSED TEST: c07s02b06x00p14n01i02272"
severity NOTE;
assert ((-0.01 ns < (SS - 3*11*7.9999 ns)) and ((SS - 3*11*7.9999 ns) < 0.01 ns))
report "***FAILED TEST: c07s02b06x00p14n01i02272 - The left operand of the multiplication operation can be an integer type and the right operand of physical type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p14n01i02272arch;
|
library ieee;
use ieee.std_logic_1164.all;
entity heartbeat is
port ( clk: out std_logic);
end heartbeat;
architecture behaviour of heartbeat
is
constant clk_period : time := 10 ns;
begin
-- Clock process definition
clk_process: process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
end behaviour;
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 19:49:29 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_rst_ps7_0_100M_0_stub.vhdl
-- Design : ip_design_rst_ps7_0_100M_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "slowest_sync_clk,ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "proc_sys_reset,Vivado 2017.3";
begin
end;
|
entity foo is end;
architecture bar of foo is
constant xA : std.standard.INTEGER;
constant xB : INTEGER := -128;
constant xC : INTEGER := 127;
constant yA : std.standard.NATURAL;
constant yB : NATURAL := 0;
constant yC : NATURAL := 127;
constant zA : std.standard.POSITIVE;
constant zB : POSITIVE := 1;
constant zC : POSITIVE := 127;
constant uA : std.standard.INTEGER_VECTOR;
constant uB : INTEGER_VECTOR(0 to 1) := (-42, 42);
begin end;
|
component ghrd_10as066n2_pb_lwh2f is
generic (
DATA_WIDTH : integer := 32;
SYMBOL_WIDTH : integer := 8;
HDL_ADDR_WIDTH : integer := 10;
BURSTCOUNT_WIDTH : integer := 1;
PIPELINE_COMMAND : integer := 1;
PIPELINE_RESPONSE : integer := 1
);
port (
clk : in std_logic := 'X'; -- clk
m0_waitrequest : in std_logic := 'X'; -- waitrequest
m0_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others => 'X'); -- readdata
m0_readdatavalid : in std_logic := 'X'; -- readdatavalid
m0_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0); -- burstcount
m0_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0); -- writedata
m0_address : out std_logic_vector(HDL_ADDR_WIDTH-1 downto 0); -- address
m0_write : out std_logic; -- write
m0_read : out std_logic; -- read
m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable
m0_debugaccess : out std_logic; -- debugaccess
reset : in std_logic := 'X'; -- reset
s0_waitrequest : out std_logic; -- waitrequest
s0_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0); -- readdata
s0_readdatavalid : out std_logic; -- readdatavalid
s0_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0) := (others => 'X'); -- burstcount
s0_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others => 'X'); -- writedata
s0_address : in std_logic_vector(HDL_ADDR_WIDTH-1 downto 0) := (others => 'X'); -- address
s0_write : in std_logic := 'X'; -- write
s0_read : in std_logic := 'X'; -- read
s0_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
s0_debugaccess : in std_logic := 'X' -- debugaccess
);
end component ghrd_10as066n2_pb_lwh2f;
u0 : component ghrd_10as066n2_pb_lwh2f
generic map (
DATA_WIDTH => INTEGER_VALUE_FOR_DATA_WIDTH,
SYMBOL_WIDTH => INTEGER_VALUE_FOR_SYMBOL_WIDTH,
HDL_ADDR_WIDTH => INTEGER_VALUE_FOR_HDL_ADDR_WIDTH,
BURSTCOUNT_WIDTH => INTEGER_VALUE_FOR_BURSTCOUNT_WIDTH,
PIPELINE_COMMAND => INTEGER_VALUE_FOR_PIPELINE_COMMAND,
PIPELINE_RESPONSE => INTEGER_VALUE_FOR_PIPELINE_RESPONSE
)
port map (
clk => CONNECTED_TO_clk, -- clk.clk
m0_waitrequest => CONNECTED_TO_m0_waitrequest, -- m0.waitrequest
m0_readdata => CONNECTED_TO_m0_readdata, -- .readdata
m0_readdatavalid => CONNECTED_TO_m0_readdatavalid, -- .readdatavalid
m0_burstcount => CONNECTED_TO_m0_burstcount, -- .burstcount
m0_writedata => CONNECTED_TO_m0_writedata, -- .writedata
m0_address => CONNECTED_TO_m0_address, -- .address
m0_write => CONNECTED_TO_m0_write, -- .write
m0_read => CONNECTED_TO_m0_read, -- .read
m0_byteenable => CONNECTED_TO_m0_byteenable, -- .byteenable
m0_debugaccess => CONNECTED_TO_m0_debugaccess, -- .debugaccess
reset => CONNECTED_TO_reset, -- reset.reset
s0_waitrequest => CONNECTED_TO_s0_waitrequest, -- s0.waitrequest
s0_readdata => CONNECTED_TO_s0_readdata, -- .readdata
s0_readdatavalid => CONNECTED_TO_s0_readdatavalid, -- .readdatavalid
s0_burstcount => CONNECTED_TO_s0_burstcount, -- .burstcount
s0_writedata => CONNECTED_TO_s0_writedata, -- .writedata
s0_address => CONNECTED_TO_s0_address, -- .address
s0_write => CONNECTED_TO_s0_write, -- .write
s0_read => CONNECTED_TO_s0_read, -- .read
s0_byteenable => CONNECTED_TO_s0_byteenable, -- .byteenable
s0_debugaccess => CONNECTED_TO_s0_debugaccess -- .debugaccess
);
|
--!
--! Copyright 2019 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all; -- or_reduce()
library commonlib;
use commonlib.types_common.all;
--! RIVER CPU specific library.
library riverlib;
--! RIVER CPU configuration constants.
use riverlib.river_cfg.all;
entity MemAccess is generic (
async_reset : boolean
);
port (
i_clk : in std_logic;
i_nrst : in std_logic;
i_e_valid : in std_logic; -- Execution stage outputs are valid
i_e_pc : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0); -- Execution stage instruction pointer
i_e_instr : in std_logic_vector(31 downto 0); -- Execution stage instruction value
i_e_flushd : in std_logic;
o_flushd : out std_logic;
i_memop_waddr : in std_logic_vector(5 downto 0); -- Register address to be written (0=no writing)
i_memop_wtag : in std_logic_vector(3 downto 0);
i_memop_wdata : in std_logic_vector(RISCV_ARCH-1 downto 0); -- Register value to be written
i_memop_sign_ext : in std_logic; -- Load data with sign extending (if less than 8 Bytes)
i_memop_load : in std_logic; -- Load data from memory and write to i_res_addr
i_memop_store : in std_logic; -- Store i_res_data value into memory
i_memop_size : in std_logic_vector(1 downto 0); -- Encoded memory transaction size in bytes: 0=1B; 1=2B; 2=4B; 3=8B
i_memop_addr : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0); -- Memory access address
o_memop_ready : out std_logic; -- Ready to accept memop request
o_wb_wena : out std_logic; -- Write enable signal
o_wb_waddr : out std_logic_vector(5 downto 0); -- Output register address (0 = x0 = no write)
o_wb_wdata : out std_logic_vector(RISCV_ARCH-1 downto 0); -- Register value
o_wb_wtag : out std_logic_vector(3 downto 0);
i_wb_ready : in std_logic;
-- Memory interface:
i_mem_req_ready : in std_logic;
o_mem_valid : out std_logic; -- Memory request is valid
o_mem_write : out std_logic; -- Memory write request
o_mem_addr : out std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0); -- Data path requested address
o_mem_wdata : out std_logic_vector(63 downto 0); -- Data path requested data (write transaction)
o_mem_wstrb : out std_logic_vector(7 downto 0); -- 8-bytes aligned strobs
i_mem_data_valid : in std_logic; -- Data path memory response is valid
i_mem_data_addr : in std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0); -- Data path memory response address
i_mem_data : in std_logic_vector(63 downto 0); -- Data path memory response value
o_mem_resp_ready : out std_logic
);
end;
architecture arch_MemAccess of MemAccess is
constant State_Idle : std_logic_vector(1 downto 0) := "00";
constant State_WaitReqAccept : std_logic_vector(1 downto 0) := "01";
constant State_WaitResponse : std_logic_vector(1 downto 0) := "10";
constant State_Hold : std_logic_vector(1 downto 0) := "11";
constant zero64 : std_logic_vector(63 downto 0) := (others => '0');
type RegistersType is record
state : std_logic_vector(1 downto 0);
memop_w : std_logic;
memop_addr : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
memop_wdata : std_logic_vector(63 downto 0);
memop_wstrb : std_logic_vector(7 downto 0);
memop_sign_ext : std_logic;
memop_size : std_logic_vector(1 downto 0);
memop_res_pc : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
memop_res_instr : std_logic_vector(31 downto 0);
memop_res_addr : std_logic_vector(5 downto 0);
memop_res_data : std_logic_vector(RISCV_ARCH-1 downto 0);
memop_res_wena : std_logic;
memop_wtag : std_logic_vector(3 downto 0);
hold_rdata : std_logic_vector(RISCV_ARCH-1 downto 0);
end record;
constant R_RESET : RegistersType := (
State_Idle, -- state
'0', (others => '0'), -- memop_w, memop_addr
(others => '0'), (others => '0'), -- memop_wdata, memop_wstrb
'0', (others => '0'), -- memop_sign_ext, memop_size
(others => '0'), (others => '0'), -- memop_res_pc, memop_res_instr
(others => '0'), -- memop_res_addr
(others => '0'), '0', -- memop_res_data, memop_res_wena
(others => '0'), -- memop_wtag
(others => '0') -- hold_rdata
);
signal r, rin : RegistersType;
-- TODO: move into separate module
-- queue signals before move into separate module
constant QUEUE_WIDTH : integer := 1 -- i_e_flushd
+ 4 -- wtag
+ 64 -- wdata width
+ 8 -- wdata btyes
+ RISCV_ARCH
+ 6
+ 32
+ CFG_CPU_ADDR_BITS
+ 2
+ 1
+ 1
+ CFG_CPU_ADDR_BITS
;
signal queue_we : std_logic;
signal queue_re : std_logic;
signal queue_data_i : std_logic_vector(QUEUE_WIDTH-1 downto 0);
signal queue_data_o : std_logic_vector(QUEUE_WIDTH-1 downto 0);
signal queue_nempty : std_logic;
signal queue_full : std_logic;
begin
queue0 : Queue generic map (
async_reset => async_reset,
szbits => 2,
dbits => QUEUE_WIDTH
) port map (
i_clk => i_clk,
i_nrst => i_nrst,
i_re => queue_re,
i_we => queue_we,
i_wdata => queue_data_i,
o_rdata => queue_data_o,
o_full => queue_full,
o_nempty => queue_nempty
);
comb : process(i_nrst, i_e_valid, i_e_pc, i_e_instr, i_memop_waddr, i_memop_wtag, i_memop_wdata,
i_memop_sign_ext, i_memop_load, i_memop_store, i_memop_size, i_memop_addr,
i_wb_ready, i_mem_data_addr, i_mem_req_ready, i_mem_data_valid,
i_mem_data_addr, i_mem_data, i_e_flushd,
queue_data_o, queue_nempty, queue_full, r)
variable v : RegistersType;
variable vb_memop_wdata : std_logic_vector(63 downto 0);
variable vb_memop_wstrb : std_logic_vector(7 downto 0);
variable v_mem_valid : std_logic;
variable v_mem_write : std_logic;
variable v_mem_sign_ext : std_logic;
variable vb_mem_sz : std_logic_vector(1 downto 0);
variable vb_mem_addr : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
variable vb_mem_rdata : std_logic_vector(63 downto 0);
variable v_queue_re : std_logic;
variable v_flushd : std_logic;
variable vb_mem_wtag : std_logic_vector(3 downto 0);
variable vb_mem_wdata : std_logic_vector(63 downto 0);
variable vb_mem_wstrb : std_logic_vector(7 downto 0);
variable vb_mem_resp_shifted : std_logic_vector(63 downto 0);
variable vb_mem_data_unsigned : std_logic_vector(63 downto 0);
variable vb_mem_data_signed : std_logic_vector(63 downto 0);
variable vb_res_data : std_logic_vector(RISCV_ARCH-1 downto 0);
variable vb_res_addr : std_logic_vector(5 downto 0);
variable vb_e_pc : std_logic_vector(CFG_CPU_ADDR_BITS-1 downto 0);
variable vb_e_instr : std_logic_vector(31 downto 0);
variable v_memop_ready : std_logic;
variable v_o_wena : std_logic;
variable vb_o_waddr : std_logic_vector(5 downto 0);
variable vb_o_wdata : std_logic_vector(RISCV_ARCH-1 downto 0);
variable vb_o_wtag : std_logic_vector(3 downto 0);
begin
v := r;
v_mem_valid := '0';
v_queue_re := '0';
vb_mem_resp_shifted := (others => '0');
vb_mem_data_unsigned := (others => '0');
vb_mem_data_signed := (others => '0');
vb_memop_wdata := (others => '0');
vb_memop_wstrb := (others => '0');
v_o_wena := '0';
vb_o_waddr := (others => '0');
vb_o_wdata := (others => '0');
vb_o_wtag := (others => '0');
case i_memop_size is
when "00" =>
vb_memop_wdata := i_memop_wdata(7 downto 0) & i_memop_wdata(7 downto 0)
& i_memop_wdata(7 downto 0) & i_memop_wdata(7 downto 0)
& i_memop_wdata(7 downto 0) & i_memop_wdata(7 downto 0)
& i_memop_wdata(7 downto 0) & i_memop_wdata(7 downto 0);
if i_memop_addr(2 downto 0) = "000" then
vb_memop_wstrb := X"01";
elsif i_memop_addr(2 downto 0) = "001" then
vb_memop_wstrb := X"02";
elsif i_memop_addr(2 downto 0) = "010" then
vb_memop_wstrb := X"04";
elsif i_memop_addr(2 downto 0) = "011" then
vb_memop_wstrb := X"08";
elsif i_memop_addr(2 downto 0) = "100" then
vb_memop_wstrb := X"10";
elsif i_memop_addr(2 downto 0) = "101" then
vb_memop_wstrb := X"20";
elsif i_memop_addr(2 downto 0) = "110" then
vb_memop_wstrb := X"40";
elsif i_memop_addr(2 downto 0) = "111" then
vb_memop_wstrb := X"80";
end if;
when "01" =>
vb_memop_wdata := i_memop_wdata(15 downto 0) & i_memop_wdata(15 downto 0)
& i_memop_wdata(15 downto 0) & i_memop_wdata(15 downto 0);
if i_memop_addr(2 downto 1) = "00" then
vb_memop_wstrb := X"03";
elsif i_memop_addr(2 downto 1) = "01" then
vb_memop_wstrb := X"0C";
elsif i_memop_addr(2 downto 1) = "10" then
vb_memop_wstrb := X"30";
else
vb_memop_wstrb := X"C0";
end if;
when "10" =>
vb_memop_wdata := i_memop_wdata(31 downto 0) & i_memop_wdata(31 downto 0);
if i_memop_addr(2) = '1' then
vb_memop_wstrb := X"F0";
else
vb_memop_wstrb := X"0F";
end if;
when "11" =>
vb_memop_wdata := i_memop_wdata;
vb_memop_wstrb := X"FF";
when others =>
end case;
-- Form Queue inputs:
queue_data_i <= i_e_flushd & i_memop_wtag & vb_memop_wdata & vb_memop_wstrb &
i_memop_wdata & i_memop_waddr & i_e_instr & i_e_pc &
i_memop_size & i_memop_sign_ext & i_memop_store &
i_memop_addr;
queue_we <= i_e_valid and (i_memop_load or i_memop_store or i_e_flushd);
-- Split Queue outputs:
v_flushd := queue_data_o(2*CFG_CPU_ADDR_BITS+RISCV_ARCH+8+64+46);
vb_mem_wtag := queue_data_o(2*CFG_CPU_ADDR_BITS+RISCV_ARCH+8+64+45 downto
2*CFG_CPU_ADDR_BITS+RISCV_ARCH+8+64+42);
vb_mem_wdata := queue_data_o(2*CFG_CPU_ADDR_BITS+RISCV_ARCH+8+64+42-1 downto
2*CFG_CPU_ADDR_BITS+RISCV_ARCH+8+42);
vb_mem_wstrb := queue_data_o(2*CFG_CPU_ADDR_BITS+RISCV_ARCH+8+42-1 downto
2*CFG_CPU_ADDR_BITS+RISCV_ARCH+42);
vb_res_data := queue_data_o(2*CFG_CPU_ADDR_BITS+RISCV_ARCH+42-1 downto
2*CFG_CPU_ADDR_BITS+42);
vb_res_addr := queue_data_o(2*CFG_CPU_ADDR_BITS+42-1 downto
2*CFG_CPU_ADDR_BITS+36);
vb_e_instr := queue_data_o(2*CFG_CPU_ADDR_BITS+36-1 downto
2*CFG_CPU_ADDR_BITS+4);
vb_e_pc := queue_data_o(2*CFG_CPU_ADDR_BITS+4-1 downto CFG_CPU_ADDR_BITS+4);
vb_mem_sz := queue_data_o(CFG_CPU_ADDR_BITS+3 downto CFG_CPU_ADDR_BITS+2);
v_mem_sign_ext := queue_data_o(CFG_CPU_ADDR_BITS+1);
v_mem_write := queue_data_o(CFG_CPU_ADDR_BITS);
vb_mem_addr := queue_data_o(CFG_CPU_ADDR_BITS-1 downto 0);
case r.memop_addr(2 downto 0) is
when "001" => vb_mem_resp_shifted := zero64(7 downto 0) & i_mem_data(63 downto 8);
when "010" => vb_mem_resp_shifted := zero64(15 downto 0) & i_mem_data(63 downto 16);
when "011" => vb_mem_resp_shifted := zero64(23 downto 0) & i_mem_data(63 downto 24);
when "100" => vb_mem_resp_shifted := zero64(31 downto 0) & i_mem_data(63 downto 32);
when "101" => vb_mem_resp_shifted := zero64(39 downto 0) & i_mem_data(63 downto 40);
when "110" => vb_mem_resp_shifted := zero64(47 downto 0) & i_mem_data(63 downto 48);
when "111" => vb_mem_resp_shifted := zero64(55 downto 0) & i_mem_data(63 downto 56);
when others => vb_mem_resp_shifted := i_mem_data;
end case;
case r.memop_size is
when MEMOP_1B =>
vb_mem_data_unsigned(7 downto 0) := vb_mem_resp_shifted(7 downto 0);
vb_mem_data_signed(7 downto 0) := vb_mem_resp_shifted(7 downto 0);
vb_mem_data_signed(63 downto 8) := (others => vb_mem_resp_shifted(7));
when MEMOP_2B =>
vb_mem_data_unsigned(15 downto 0) := vb_mem_resp_shifted(15 downto 0);
vb_mem_data_signed(15 downto 0) := vb_mem_resp_shifted(15 downto 0);
vb_mem_data_signed(63 downto 16) := (others => vb_mem_resp_shifted(15));
when MEMOP_4B =>
vb_mem_data_unsigned(31 downto 0) := vb_mem_resp_shifted(31 downto 0);
vb_mem_data_signed(31 downto 0) := vb_mem_resp_shifted(31 downto 0);
vb_mem_data_signed(63 downto 32) := (others => vb_mem_resp_shifted(31));
when others =>
vb_mem_data_unsigned := vb_mem_resp_shifted;
vb_mem_data_signed := vb_mem_resp_shifted;
end case;
if r.memop_w = '0' then
if r.memop_sign_ext = '1' then
vb_mem_rdata := vb_mem_data_signed;
else
vb_mem_rdata := vb_mem_data_unsigned;
end if;
else
vb_mem_rdata := r.memop_res_data;
end if;
case r.state is
when State_Idle =>
v_queue_re := '1';
if queue_nempty = '1' then
v_mem_valid := not v_flushd;
v.memop_res_pc := vb_e_pc;
v.memop_res_instr := vb_e_instr;
v.memop_res_addr := vb_res_addr;
v.memop_res_data := vb_res_data;
v.memop_res_wena := or_reduce(vb_res_addr);
v.memop_addr := vb_mem_addr;
v.memop_wdata := vb_mem_wdata;
v.memop_wtag := vb_mem_wtag;
v.memop_wstrb := vb_mem_wstrb;
v.memop_w := v_mem_write;
v.memop_sign_ext := v_mem_sign_ext;
v.memop_size := vb_mem_sz;
if v_flushd = '1' then
-- do nothing
elsif i_mem_req_ready = '1' then
v.state := State_WaitResponse;
else
v.state := State_WaitReqAccept;
end if;
end if;
when State_WaitReqAccept =>
v_mem_valid := '1';
v_mem_write := r.memop_w;
vb_mem_sz := r.memop_size;
vb_mem_addr := r.memop_addr;
vb_mem_wdata := r.memop_wdata;
vb_mem_wstrb := r.memop_wstrb;
vb_res_data := r.memop_res_data;
if i_mem_req_ready = '1' then
v.state := State_WaitResponse;
end if;
when State_WaitResponse =>
if i_mem_data_valid = '0' then
-- Do nothing
else
v_o_wena := r.memop_res_wena;
vb_o_waddr := r.memop_res_addr;
vb_o_wdata := vb_mem_rdata;
vb_o_wtag := r.memop_wtag;
v_queue_re := '1';
if r.memop_res_wena = '1' and i_wb_ready = '0' then
-- Inject only one clock hold-on and wait a couple of clocks
v_queue_re := '0';
v.state := State_Hold;
v.hold_rdata := vb_mem_rdata;
elsif queue_nempty = '1' then
v_mem_valid := not v_flushd;
v.memop_res_pc := vb_e_pc;
v.memop_res_instr := vb_e_instr;
v.memop_res_addr := vb_res_addr;
v.memop_res_data := vb_res_data;
v.memop_res_wena := or_reduce(vb_res_addr);
v.memop_addr := vb_mem_addr;
v.memop_wdata := vb_mem_wdata;
v.memop_wtag := vb_mem_wtag;
v.memop_wstrb := vb_mem_wstrb;
v.memop_w := v_mem_write;
v.memop_sign_ext := v_mem_sign_ext;
v.memop_size := vb_mem_sz;
if v_flushd = '1' then
v.state := State_Idle;
elsif i_mem_req_ready = '1' then
v.state := State_WaitResponse;
else
v.state := State_WaitReqAccept;
end if;
else
v.state := State_Idle;
end if;
end if;
when State_Hold =>
v_o_wena := r.memop_res_wena;
vb_o_waddr := r.memop_res_addr;
vb_o_wdata := r.hold_rdata;
vb_o_wtag := r.memop_wtag;
if i_wb_ready = '1' then
v_queue_re := '1';
if queue_nempty = '1' then
v_mem_valid := not v_flushd;
v.memop_res_pc := vb_e_pc;
v.memop_res_instr := vb_e_instr;
v.memop_res_addr := vb_res_addr;
v.memop_res_data := vb_res_data;
v.memop_res_wena := or_reduce(vb_res_addr);
v.memop_addr := vb_mem_addr;
v.memop_wdata := vb_mem_wdata;
v.memop_wtag := vb_mem_wtag;
v.memop_wstrb := vb_mem_wstrb;
v.memop_w := v_mem_write;
v.memop_sign_ext := v_mem_sign_ext;
v.memop_size := vb_mem_sz;
if v_flushd = '1' then
v.state := State_Idle;
elsif i_mem_req_ready = '1' then
v.state := State_WaitResponse;
else
v.state := State_WaitReqAccept;
end if;
else
v.state := State_Idle;
end if;
end if;
when others =>
end case;
v_memop_ready := '1';
if queue_full = '1' then
v_memop_ready := '0';
end if;
if not async_reset and i_nrst = '0' then
v := R_RESET;
end if;
queue_re <= v_queue_re;
o_flushd <= queue_nempty and v_flushd and v_queue_re;
o_mem_resp_ready <= '1';
o_mem_valid <= v_mem_valid;
o_mem_write <= v_mem_write;
o_mem_addr <= vb_mem_addr(CFG_CPU_ADDR_BITS-1 downto 3) & "000";
o_mem_wdata <= vb_mem_wdata;
o_mem_wstrb <= vb_mem_wstrb;
o_memop_ready <= v_memop_ready;
o_wb_wena <= v_o_wena;
o_wb_waddr <= vb_o_waddr;
o_wb_wdata <= vb_o_wdata;
o_wb_wtag <= vb_o_wtag;
rin <= v;
end process;
-- registers:
regs : process(i_clk, i_nrst)
begin
if async_reset and i_nrst = '0' then
r <= R_RESET;
elsif rising_edge(i_clk) then
r <= rin;
end if;
end process;
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3102.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s01b00x00p11n01i03102ent IS
ATTRIBUTE attr1 : INTEGER;
END c05s01b00x00p11n01i03102ent;
ARCHITECTURE c05s01b00x00p11n01i03102arch OF c05s01b00x00p11n01i03102ent IS
SIGNAL s1,s2,s3 : BIT;
SIGNAL s4,s5 : INTEGER;
SIGNAL s6,s7 : STRING(1 TO 3);
CONSTANT c1,c2,c3 : BIT := '0';
CONSTANT c4,c5 : INTEGER := 1;
CONSTANT c6,c7 : STRING(1 TO 3) := "ABC";
ATTRIBUTE attr1 OF ALL : SIGNAL IS 20;
ATTRIBUTE attr1 OF ALL : CONSTANT IS 101;
BEGIN
TESTING: PROCESS
BEGIN
ASSERT s1'attr1 = 20 REPORT "Bad value for s1'attr1" SEVERITY FAILURE;
ASSERT s2'attr1 = 20 REPORT "Bad value for s2'attr1" SEVERITY FAILURE;
ASSERT s3'attr1 = 20 REPORT "Bad value for s3'attr1" SEVERITY FAILURE;
ASSERT s4'attr1 = 20 REPORT "Bad value for s4'attr1" SEVERITY FAILURE;
ASSERT s5'attr1 = 20 REPORT "Bad value for s5'attr1" SEVERITY FAILURE;
ASSERT s6'attr1 = 20 REPORT "Bad value for s6'attr1" SEVERITY FAILURE;
ASSERT s7'attr1 = 20 REPORT "Bad value for s7'attr1" SEVERITY FAILURE;
ASSERT c1'attr1 = 101 REPORT "Bad value for c1'attr1" SEVERITY FAILURE;
ASSERT c2'attr1 = 101 REPORT "Bad value for c2'attr1" SEVERITY FAILURE;
ASSERT c3'attr1 = 101 REPORT "Bad value for c3'attr1" SEVERITY FAILURE;
ASSERT c4'attr1 = 101 REPORT "Bad value for c4'attr1" SEVERITY FAILURE;
ASSERT c5'attr1 = 101 REPORT "Bad value for c5'attr1" SEVERITY FAILURE;
ASSERT c6'attr1 = 101 REPORT "Bad value for c6'attr1" SEVERITY FAILURE;
ASSERT c7'attr1 = 101 REPORT "Bad value for c7'attr1" SEVERITY FAILURE;
assert NOT( s1'attr1 = 20 and
s2'attr1 = 20 and
s3'attr1 = 20 and
s4'attr1 = 20 and
s5'attr1 = 20 and
s6'attr1 = 20 and
s7'attr1 = 20 and
c1'attr1 = 101 and
c2'attr1 = 101 and
c3'attr1 = 101 and
c4'attr1 = 101 and
c5'attr1 = 101 and
c6'attr1 = 101 and
c7'attr1 = 101 )
report "***PASSED TEST: c05s01b00x00p11n01i03102"
severity NOTE;
assert ( s1'attr1 = 20 and
s2'attr1 = 20 and
s3'attr1 = 20 and
s4'attr1 = 20 and
s5'attr1 = 20 and
s6'attr1 = 20 and
s7'attr1 = 20 and
c1'attr1 = 101 and
c2'attr1 = 101 and
c3'attr1 = 101 and
c4'attr1 = 101 and
c5'attr1 = 101 and
c6'attr1 = 101 and
c7'attr1 = 101 )
report "***FAILED TEST: c05s01b00x00p11n01i03102 - Reserved work all as attribute specification test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s01b00x00p11n01i03102arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3102.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s01b00x00p11n01i03102ent IS
ATTRIBUTE attr1 : INTEGER;
END c05s01b00x00p11n01i03102ent;
ARCHITECTURE c05s01b00x00p11n01i03102arch OF c05s01b00x00p11n01i03102ent IS
SIGNAL s1,s2,s3 : BIT;
SIGNAL s4,s5 : INTEGER;
SIGNAL s6,s7 : STRING(1 TO 3);
CONSTANT c1,c2,c3 : BIT := '0';
CONSTANT c4,c5 : INTEGER := 1;
CONSTANT c6,c7 : STRING(1 TO 3) := "ABC";
ATTRIBUTE attr1 OF ALL : SIGNAL IS 20;
ATTRIBUTE attr1 OF ALL : CONSTANT IS 101;
BEGIN
TESTING: PROCESS
BEGIN
ASSERT s1'attr1 = 20 REPORT "Bad value for s1'attr1" SEVERITY FAILURE;
ASSERT s2'attr1 = 20 REPORT "Bad value for s2'attr1" SEVERITY FAILURE;
ASSERT s3'attr1 = 20 REPORT "Bad value for s3'attr1" SEVERITY FAILURE;
ASSERT s4'attr1 = 20 REPORT "Bad value for s4'attr1" SEVERITY FAILURE;
ASSERT s5'attr1 = 20 REPORT "Bad value for s5'attr1" SEVERITY FAILURE;
ASSERT s6'attr1 = 20 REPORT "Bad value for s6'attr1" SEVERITY FAILURE;
ASSERT s7'attr1 = 20 REPORT "Bad value for s7'attr1" SEVERITY FAILURE;
ASSERT c1'attr1 = 101 REPORT "Bad value for c1'attr1" SEVERITY FAILURE;
ASSERT c2'attr1 = 101 REPORT "Bad value for c2'attr1" SEVERITY FAILURE;
ASSERT c3'attr1 = 101 REPORT "Bad value for c3'attr1" SEVERITY FAILURE;
ASSERT c4'attr1 = 101 REPORT "Bad value for c4'attr1" SEVERITY FAILURE;
ASSERT c5'attr1 = 101 REPORT "Bad value for c5'attr1" SEVERITY FAILURE;
ASSERT c6'attr1 = 101 REPORT "Bad value for c6'attr1" SEVERITY FAILURE;
ASSERT c7'attr1 = 101 REPORT "Bad value for c7'attr1" SEVERITY FAILURE;
assert NOT( s1'attr1 = 20 and
s2'attr1 = 20 and
s3'attr1 = 20 and
s4'attr1 = 20 and
s5'attr1 = 20 and
s6'attr1 = 20 and
s7'attr1 = 20 and
c1'attr1 = 101 and
c2'attr1 = 101 and
c3'attr1 = 101 and
c4'attr1 = 101 and
c5'attr1 = 101 and
c6'attr1 = 101 and
c7'attr1 = 101 )
report "***PASSED TEST: c05s01b00x00p11n01i03102"
severity NOTE;
assert ( s1'attr1 = 20 and
s2'attr1 = 20 and
s3'attr1 = 20 and
s4'attr1 = 20 and
s5'attr1 = 20 and
s6'attr1 = 20 and
s7'attr1 = 20 and
c1'attr1 = 101 and
c2'attr1 = 101 and
c3'attr1 = 101 and
c4'attr1 = 101 and
c5'attr1 = 101 and
c6'attr1 = 101 and
c7'attr1 = 101 )
report "***FAILED TEST: c05s01b00x00p11n01i03102 - Reserved work all as attribute specification test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s01b00x00p11n01i03102arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3102.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s01b00x00p11n01i03102ent IS
ATTRIBUTE attr1 : INTEGER;
END c05s01b00x00p11n01i03102ent;
ARCHITECTURE c05s01b00x00p11n01i03102arch OF c05s01b00x00p11n01i03102ent IS
SIGNAL s1,s2,s3 : BIT;
SIGNAL s4,s5 : INTEGER;
SIGNAL s6,s7 : STRING(1 TO 3);
CONSTANT c1,c2,c3 : BIT := '0';
CONSTANT c4,c5 : INTEGER := 1;
CONSTANT c6,c7 : STRING(1 TO 3) := "ABC";
ATTRIBUTE attr1 OF ALL : SIGNAL IS 20;
ATTRIBUTE attr1 OF ALL : CONSTANT IS 101;
BEGIN
TESTING: PROCESS
BEGIN
ASSERT s1'attr1 = 20 REPORT "Bad value for s1'attr1" SEVERITY FAILURE;
ASSERT s2'attr1 = 20 REPORT "Bad value for s2'attr1" SEVERITY FAILURE;
ASSERT s3'attr1 = 20 REPORT "Bad value for s3'attr1" SEVERITY FAILURE;
ASSERT s4'attr1 = 20 REPORT "Bad value for s4'attr1" SEVERITY FAILURE;
ASSERT s5'attr1 = 20 REPORT "Bad value for s5'attr1" SEVERITY FAILURE;
ASSERT s6'attr1 = 20 REPORT "Bad value for s6'attr1" SEVERITY FAILURE;
ASSERT s7'attr1 = 20 REPORT "Bad value for s7'attr1" SEVERITY FAILURE;
ASSERT c1'attr1 = 101 REPORT "Bad value for c1'attr1" SEVERITY FAILURE;
ASSERT c2'attr1 = 101 REPORT "Bad value for c2'attr1" SEVERITY FAILURE;
ASSERT c3'attr1 = 101 REPORT "Bad value for c3'attr1" SEVERITY FAILURE;
ASSERT c4'attr1 = 101 REPORT "Bad value for c4'attr1" SEVERITY FAILURE;
ASSERT c5'attr1 = 101 REPORT "Bad value for c5'attr1" SEVERITY FAILURE;
ASSERT c6'attr1 = 101 REPORT "Bad value for c6'attr1" SEVERITY FAILURE;
ASSERT c7'attr1 = 101 REPORT "Bad value for c7'attr1" SEVERITY FAILURE;
assert NOT( s1'attr1 = 20 and
s2'attr1 = 20 and
s3'attr1 = 20 and
s4'attr1 = 20 and
s5'attr1 = 20 and
s6'attr1 = 20 and
s7'attr1 = 20 and
c1'attr1 = 101 and
c2'attr1 = 101 and
c3'attr1 = 101 and
c4'attr1 = 101 and
c5'attr1 = 101 and
c6'attr1 = 101 and
c7'attr1 = 101 )
report "***PASSED TEST: c05s01b00x00p11n01i03102"
severity NOTE;
assert ( s1'attr1 = 20 and
s2'attr1 = 20 and
s3'attr1 = 20 and
s4'attr1 = 20 and
s5'attr1 = 20 and
s6'attr1 = 20 and
s7'attr1 = 20 and
c1'attr1 = 101 and
c2'attr1 = 101 and
c3'attr1 = 101 and
c4'attr1 = 101 and
c5'attr1 = 101 and
c6'attr1 = 101 and
c7'attr1 = 101 )
report "***FAILED TEST: c05s01b00x00p11n01i03102 - Reserved work all as attribute specification test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s01b00x00p11n01i03102arch;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: spi2ahb_apb
-- File: spi2ahb_apb.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- Contact: [email protected]
-- Description: Simple SPI slave providing a bridge to AMBA AHB
-- This entity provides an APB interface for setting defining the
-- AHB address window that can be accessed from SPI.
-- See spi2ahbx.vhd and GRIP for documentation
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.spi.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.conv_std_logic;
use grlib.stdlib.conv_std_logic_vector;
entity spi2ahb_apb is
generic (
-- AHB Configuration
hindex : integer := 0;
--
ahbaddrh : integer := 0;
ahbaddrl : integer := 0;
ahbmaskh : integer := 0;
ahbmaskl : integer := 0;
resen : integer := 0;
-- APB configuration
pindex : integer := 0; -- slave bus index
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
--
oepol : integer range 0 to 1 := 0;
--
filter : integer range 2 to 512 := 2;
--
cpol : integer range 0 to 1 := 0;
cpha : integer range 0 to 1 := 0
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
--
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
-- SPI signals
spii : in spi_in_type;
spio : out spi_out_type
);
end entity spi2ahb_apb;
architecture rtl of spi2ahb_apb is
-- Register offsets
constant CTRL_OFF : std_logic_vector(4 downto 2) := "000";
constant STS_OFF : std_logic_vector(4 downto 2) := "001";
constant ADDR_OFF : std_logic_vector(4 downto 2) := "010";
constant MASK_OFF : std_logic_vector(4 downto 2) := "011";
-- AMBA PnP
constant PCONFIG : apb_config_type := (
0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_SPI2AHB, 0, 0, 0),
1 => apb_iobar(paddr, pmask));
type apb_reg_type is record
spi2ahbi : spi2ahb_in_type;
irq : std_ulogic;
irqen : std_ulogic;
prot : std_ulogic;
protx : std_ulogic;
wr : std_ulogic;
dma : std_ulogic;
dmax : std_ulogic;
end record;
signal r, rin : apb_reg_type;
signal spi2ahbo : spi2ahb_out_type;
begin
bridge : spi2ahbx
generic map (hindex => hindex, oepol => oepol, filter => filter,
cpol => cpol, cpha => cpha)
port map (rstn => rstn, clk => clk, ahbi => ahbi, ahbo => ahbo,
spii => spii, spio => spio, spi2ahbi => r.spi2ahbi,
spi2ahbo => spi2ahbo);
comb: process (r, rstn, apbi, spi2ahbo)
variable v : apb_reg_type;
variable apbaddr : std_logic_vector(4 downto 2);
variable apbout : std_logic_vector(31 downto 0);
variable irqout : std_logic_vector(NAHBIRQ-1 downto 0);
begin
v := r; apbaddr := apbi.paddr(apbaddr'range); apbout := (others => '0');
v.irq := '0'; irqout := (others => '0'); irqout(pirq) := r.irq;
v.protx := spi2ahbo.prot; v.dmax := spi2ahbo.dma;
---------------------------------------------------------------------------
-- APB register interface
---------------------------------------------------------------------------
-- read registers
if (apbi.psel(pindex) and apbi.penable) = '1' then
case apbaddr is
when CTRL_OFF => apbout(1 downto 0) := r.irqen & r.spi2ahbi.en;
when STS_OFF => apbout(2 downto 0) := r.prot & r.wr & r.dma;
when ADDR_OFF => apbout := r.spi2ahbi.haddr;
when MASK_OFF => apbout := r.spi2ahbi.hmask;
when others => null;
end case;
end if;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbaddr is
when CTRL_OFF => v.irqen := apbi.pwdata(1); v.spi2ahbi.en := apbi.pwdata(0);
when STS_OFF => v.dma := r.dma and not apbi.pwdata(0);
v.prot := r.prot and not apbi.pwdata(2);
when ADDR_OFF => v.spi2ahbi.haddr := apbi.pwdata;
when MASK_OFF => v.spi2ahbi.hmask := apbi.pwdata;
when others => null;
end case;
end if;
-- interrupt and status register handling
if ((spi2ahbo.dma and not r.dmax) or
(spi2ahbo.prot and not r.protx)) = '1' then
v.dma := '1'; v.prot := r.prot or spi2ahbo.prot; v.wr := spi2ahbo.wr;
if (r.irqen and not r.dma) = '1' then v.irq := '1'; end if;
end if;
---------------------------------------------------------------------------
-- reset
---------------------------------------------------------------------------
if rstn = '0' then
v.spi2ahbi.en := conv_std_logic(resen = 1);
v.spi2ahbi.haddr := conv_std_logic_vector(ahbaddrh, 16) &
conv_std_logic_vector(ahbaddrl, 16);
v.spi2ahbi.hmask := conv_std_logic_vector(ahbmaskh, 16) &
conv_std_logic_vector(ahbmaskl, 16);
v.irqen := '0'; v.prot := '0'; v.wr := '0'; v.dma := '0';
end if;
---------------------------------------------------------------------------
-- signal assignments
---------------------------------------------------------------------------
-- update registers
rin <= v;
-- update outputs
apbo.prdata <= apbout;
apbo.pirq <= irqout;
apbo.pconfig <= PCONFIG;
apbo.pindex <= pindex;
end process comb;
reg: process(clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process reg;
-- Boot message provided in spi2ahbx...
end architecture rtl;
|
entity tb_vector8_test1 is
end tb_vector8_test1;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_vector8_test1 is
signal r : std_logic;
begin
dut: entity work.vector8_test1
port map (r);
process
begin
wait for 1 ns;
assert r = '1' severity failure;
wait;
end process;
end behav;
|
--------------------------------------------------------------------------------
--Copyright (c) 2014, Benjamin Bässler <[email protected]>
--All rights reserved.
--
--Redistribution and use in source and binary forms, with or without
--modification, are permitted provided that the following conditions are met:
--
--* Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
--
--* Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
--
--THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
--IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
--FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
--DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
--SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
--CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
--OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
--OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
--! @file labeling_box.vhd
--! @brief Connected Component Labeling two pass and computation of bound boxes
--! @author Benjamin Bässler
--! @email [email protected]
--! @date 2013-06-04
--------------------------------------------------------------------------------
--! Use standard library
library ieee;
--! Use numeric std
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
use work.types.all;
use work.utils.all;
--! The two pass algorithem implemented in labeling.vhd
--! will be run and the output of labels used to compute
--! the bound boxes with the boundbox.vhd.
--! The boundbox has a internal heap to store boundboxes
--! if the memory is to small the the error signal will
--! rise and the output of the boxes is incompleat
entity labeling_box is
generic(
--! Max image width
G_MAX_IMG_WIDTH : NATURAL := C_MAX_IMAGE_WIDTH;
--! Max image height
G_MAX_IMG_HEIGHT : NATURAL := C_MAX_IMAGE_HEIGHT
);
port(
--! Clock input
clk_in : in STD_LOGIC;
--! Reset input
rst_in : in STD_LOGIC;
--! Output if the labeling stalls
stall_out : out STD_LOGIC;
--! Input to stall the output of the labeling
stall_in : in STD_LOGIC;
--! input data are valid
data_valid_in : in STD_LOGIC;
--! Pixel input 0 => background, 1=> foreground
px_in : in STD_LOGIC;
--! width of the image at the input
img_width_in : in STD_LOGIC_VECTOR(log2_ceil(G_MAX_IMG_WIDTH) downto 0);
--! height of the image
img_height_in : in STD_LOGIC_VECTOR(log2_ceil(G_MAX_IMG_HEIGHT) downto 0);
--! High if the boundbox output valid
box_valid_out : out STD_LOGIC;
--! output of bound box upper x
box_start_x_out : out STD_LOGIC_VECTOR(log2_ceil(G_MAX_IMG_WIDTH) - 1 downto 0);
--! output of bound box upper y
box_start_y_out : out STD_LOGIC_VECTOR(log2_ceil(G_MAX_IMG_HEIGHT) - 1 downto 0);
--! output of bound box lower x
box_end_x_out : out STD_LOGIC_VECTOR(log2_ceil(G_MAX_IMG_WIDTH) - 1 downto 0);
--! output of bound box lower y
box_end_y_out : out STD_LOGIC_VECTOR(log2_ceil(G_MAX_IMG_HEIGHT) - 1 downto 0);
--! high if all boxes are computed
box_done_out : out STD_LOGIC;
--! High if the output of at least one box is wrong
error_out : out STD_LOGIC_VECTOR(C_ERR_REF_SIZE - 1 downto 0)
);
end entity labeling_box;
--! @brief arc description
--! @details more detailed description
architecture labeling_box_arc of labeling_box is
--! State machine
type T_STATE is (LABELING, BOXES);
signal state : T_STATE;
signal stall_lbl_s : STD_LOGIC;
signal valid_lbl_out_s : STD_LOGIC;
signal last_lbl_s : STD_LOGIC;
signal label_s : STD_LOGIC_VECTOR(T_LABEL'RANGE);
signal box_rst_s : STD_LOGIC;
signal box_done_s : STD_LOGIC;
signal lbl_err_s : STD_LOGIC;
signal last_box_noti_s : STD_LOGIC := '1';
signal box_out_s : T_BOX;
begin
box_start_x_out <= STD_LOGIC_VECTOR(box_out_s(T_X_START));
box_start_y_out <= STD_LOGIC_VECTOR(box_out_s(T_Y_START));
box_end_x_out <= STD_LOGIC_VECTOR(box_out_s(T_X_END));
box_end_y_out <= STD_LOGIC_VECTOR(box_out_s(T_Y_END));
error_out(0) <= lbl_err_s;
p_pipe_state : process(clk_in) is
begin
if rising_edge(clk_in) then
if rst_in = '1' then
state <= LABELING;
box_rst_s <= '1';
box_done_out <= '0';
else
box_done_out <= '0';
box_rst_s <= '0';
case state is
when LABELING =>
if last_lbl_s = '1' then
state <= BOXES;
end if;
when BOXES =>
if box_done_s = '1' then
state <= LABELING;
box_done_out <= '1';
box_rst_s <= '1';
end if;
end case;
end if; -- rst
end if; --clk
end process p_pipe_state;
my_labeling : entity work.labeling PORT MAP(
clk_in => clk_in,
rst_in => rst_in,
stall_out => stall_lbl_s,
stall_in => stall_in,
px_in => px_in,
img_width_in => img_width_in,
img_height_in => img_height_in,
data_valid_out => valid_lbl_out_s,
data_valid_in => data_valid_in,
last_lbl_out => last_lbl_s,
label_out => label_s,
error_out => lbl_err_s
);
boundbox : entity work.boundbox PORT MAP(
clk_in => clk_in,
rst_in => box_rst_s,
stall_in => stall_in,
lbl_valid_in => valid_lbl_out_s,
label_in => UNSIGNED(label_s),
box_valid_out => box_valid_out,
box_out => box_out_s,
box_done_out => box_done_s,
error_out => open,
img_width_in => UNSIGNED(img_width_in),
img_height_in => UNSIGNED(img_height_in)
);
end labeling_box_arc;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.slot_bus_pkg.all;
entity slot_slave is
port (
clock : in std_logic;
reset : in std_logic;
-- Cartridge pins
RSTn : in std_logic;
IO1n : in std_logic;
IO2n : in std_logic;
ROMLn : in std_logic;
ROMHn : in std_logic;
BA : in std_logic;
GAMEn : in std_logic;
EXROMn : in std_logic;
RWn : in std_logic;
ADDRESS : in std_logic_vector(15 downto 0);
DATA_in : in std_logic_vector(7 downto 0);
DATA_out : out std_logic_vector(7 downto 0) := (others => '0');
DATA_tri : out std_logic;
-- interface with memory controller
mem_req : out std_logic; -- our memory request to serve slot
mem_size : out unsigned(1 downto 0);
mem_rwn : out std_logic;
mem_rack : in std_logic;
mem_dack : in std_logic;
mem_count : in unsigned(1 downto 0);
mem_rdata : in std_logic_vector(7 downto 0);
mem_wdata : out std_logic_vector(7 downto 0);
-- mem_addr comes from cartridge logic
reset_out : out std_logic;
-- timing inputs
phi2_tick : in std_logic;
do_sample_addr : in std_logic;
do_probe_end : in std_logic;
do_sample_io : in std_logic;
do_io_event : in std_logic;
-- interface with freezer (cartridge) logic
allow_serve : in std_logic := '0'; -- from timing unit (modified version of serve_enable)
serve_rom : in std_logic := '0'; -- ROML or ROMH
serve_io1 : in std_logic := '0'; -- IO1n
serve_io2 : in std_logic := '0'; -- IO2n
allow_write : in std_logic := '0';
kernal_enable : in std_logic := '0';
kernal_probe : out std_logic := '0';
kernal_area : out std_logic := '0';
force_ultimax : out std_logic := '0';
do_reg_output : in std_logic := '0';
epyx_timeout : out std_logic; -- '0' => epyx is on, '1' epyx is off
cpu_write : out std_logic; -- for freezer
slot_req : out t_slot_req;
slot_resp : in t_slot_resp;
-- interface with hardware
BUFFER_ENn : out std_logic );
end slot_slave;
architecture gideon of slot_slave is
signal address_c : std_logic_vector(15 downto 0) := (others => '0');
signal data_c : std_logic_vector(7 downto 0) := X"FF";
signal io1n_c : std_logic := '1';
signal io2n_c : std_logic := '1';
signal rwn_c : std_logic := '1';
signal romhn_c : std_logic := '1';
signal romln_c : std_logic := '1';
signal ba_c : std_logic := '0';
signal dav : std_logic := '0';
signal addr_is_io : boolean;
signal addr_is_kernal : std_logic;
signal mem_req_ff : std_logic;
signal mem_size_i : unsigned(1 downto 0);
signal servicable : std_logic;
signal io_out : boolean := false;
signal io_read_cond : std_logic;
signal io_write_cond: std_logic;
signal late_write_cond : std_logic;
signal ultimax : std_logic;
signal ultimax_d : std_logic := '0';
signal ultimax_d2 : std_logic := '0';
signal last_rwn : std_logic;
signal mem_wdata_i : std_logic_vector(7 downto 0);
signal kernal_probe_i : std_logic;
signal kernal_area_i : std_logic;
signal mem_data_0 : std_logic_vector(7 downto 0) := X"00";
signal mem_data_1 : std_logic_vector(7 downto 0) := X"00";
signal data_mux : std_logic;
attribute register_duplication : string;
attribute register_duplication of rwn_c : signal is "no";
attribute register_duplication of io1n_c : signal is "no";
attribute register_duplication of io2n_c : signal is "no";
attribute register_duplication of romln_c : signal is "no";
attribute register_duplication of romhn_c : signal is "no";
attribute register_duplication of reset_out : signal is "no";
type t_state is (idle, mem_access, wait_end, reg_out);
attribute iob : string;
attribute iob of data_c : signal is "true";
signal state : t_state;
-- attribute fsm_encoding : string;
-- attribute fsm_encoding of state : signal is "sequential";
signal epyx_timer : unsigned(6 downto 0) := (others => '0');
signal epyx_reset : std_logic := '0';
begin
slot_req.io_write <= do_io_event and io_write_cond;
slot_req.io_read <= do_io_event and io_read_cond;
slot_req.late_write <= do_io_event and late_write_cond;
slot_req.io_read_early <= '1' when (addr_is_io and rwn_c='1' and do_sample_addr='1') else '0';
process(clock)
begin
if rising_edge(clock) then
-- synchronization
if mem_req_ff='0' then -- don't change while an access is taking place
rwn_c <= RWn;
address_c <= ADDRESS;
end if;
reset_out <= reset or not RSTn;
ba_c <= BA;
io1n_c <= IO1n;
io2n_c <= IO2n;
romln_c <= ROMLn;
romhn_c <= ROMHn;
data_c <= DATA_in;
ultimax <= not GAMEn and EXROMn;
ultimax_d <= ultimax;
ultimax_d2 <= ultimax_d;
if epyx_reset='1' then
epyx_timer <= (others => '1');
epyx_timeout <= '0';
elsif phi2_tick='1' then
if epyx_timer = "0000000" then
epyx_timeout <= '1';
else
epyx_timer <= epyx_timer - 1;
end if;
end if;
slot_req.bus_write <= '0';
if do_sample_io='1' then
cpu_write <= not RWn;
slot_req.bus_write <= not RWn;
slot_req.io_address <= unsigned(address_c);
mem_wdata_i <= data_c;
late_write_cond <= not rwn_c;
io_write_cond <= not rwn_c and (not io2n_c or not io1n_c);
io_read_cond <= rwn_c and (not io2n_c or not io1n_c);
epyx_reset <= not io2n_c or not io1n_c or not romln_c or not RSTn;
end if;
if do_probe_end='1' then
data_mux <= kernal_probe_i and not romhn_c;
force_ultimax <= kernal_probe_i;
kernal_probe_i <= '0';
elsif do_io_event='1' then
force_ultimax <= '0';
end if;
case state is
when idle =>
mem_size_i <= "00";
if do_sample_addr='1' then
-- register output
if slot_resp.reg_output='1' and addr_is_io and rwn_c='1' then -- read register
mem_data_0 <= slot_resp.data;
io_out <= true;
dav <= '1';
state <= reg_out;
elsif allow_serve='1' and servicable='1' and rwn_c='1' then
io_out <= false;
-- memory read
if kernal_enable='1' and ultimax='0' and addr_is_kernal='1' and ba_c='1' then
kernal_probe_i <= '1';
kernal_area_i <= '1';
mem_size_i <= "01";
end if;
if addr_is_io then
if ba_c='1' then -- only serve IO when BA='1' (Fix for Ethernet)
mem_req_ff <= '1';
state <= mem_access;
end if;
if address_c(8)='0' and serve_io1='1' then
io_out <= (rwn_c='1');
elsif address_c(8)='1' and serve_io2='1' then
io_out <= (rwn_c='1');
end if;
else -- non-IO, always serve
mem_req_ff <= '1';
state <= mem_access;
end if;
end if;
elsif do_sample_io='1' and rwn_c='0' then
if allow_write='1' then
-- memory write
if address_c(14)='1' then -- IO range
if io2n_c='0' or io1n_c='0' then
mem_req_ff <= '1';
state <= mem_access;
end if;
else
mem_req_ff <= '1';
state <= mem_access;
end if;
elsif kernal_enable='1' and addr_is_kernal='1' then
-- do mirror to kernal write address
mem_req_ff <= '1';
state <= mem_access;
kernal_area_i <= '1';
end if;
end if;
when mem_access =>
if mem_rack='1' then
mem_req_ff <= '0'; -- clear request
if rwn_c='0' then -- if write, we're done.
kernal_area_i <= '0';
state <= idle;
else -- if read, then we need to wait for the data
state <= wait_end;
end if;
end if;
-- this will never happen, because we have latency from RAM.
-- if mem_dack='1' then -- in case the data comes immediately
-- DATA_out <= mem_rdata;
-- dav <= '1';
-- end if;
when wait_end =>
if mem_dack='1' then -- the data is available, put it on the bus!
if mem_count="00" then
mem_data_0 <= mem_rdata;
else
mem_data_1 <= mem_rdata;
end if;
dav <= '1';
end if;
if phi2_tick='1' or do_io_event='1' then -- around the clock edges
kernal_area_i <= '0';
state <= idle;
io_out <= false;
dav <= '0';
end if;
when reg_out =>
mem_data_0 <= slot_resp.data;
if phi2_tick='1' or do_io_event='1' then -- around the clock edges
state <= idle;
io_out <= false;
dav <= '0';
end if;
when others =>
null;
end case;
if (kernal_area_i='1') then
DATA_tri <= not romhn_c and ultimax_d2 and rwn_c;
elsif (io_out and (io1n_c='0' or io2n_c='0')) or
((romln_c='0' or romhn_c='0') and (rwn_c='1')) then
DATA_tri <= mem_dack or dav;
else
DATA_tri <= '0';
end if;
if reset='1' then
data_mux <= '0';
last_rwn <= '1';
dav <= '0';
state <= idle;
mem_req_ff <= '0';
mem_size_i <= "00";
io_out <= false;
io_read_cond <= '0';
io_write_cond <= '0';
late_write_cond <= '0';
slot_req.io_address <= (others => '0');
cpu_write <= '0';
epyx_reset <= '1';
kernal_probe_i <= '0';
kernal_area_i <= '0';
force_ultimax <= '0';
end if;
end if;
end process;
-- combinatoric
addr_is_io <= (address_c(15 downto 9)="1101111"); -- DE/DF
addr_is_kernal <= '1' when (address_c(15 downto 13)="111") else '0';
process(rwn_c, address_c, addr_is_io, romln_c, romhn_c, serve_rom, serve_io1, serve_io2, ultimax, kernal_enable, ba_c)
begin
servicable <= '0';
if rwn_c='1' then
if addr_is_io and (serve_io1='1' or serve_io2='1') then
servicable <= '1';
end if;
-- if (romln_c='0' or romhn_c='0') and (serve_rom='1') then -- our decode is faster!
if address_c(15 downto 14)="10" and (serve_rom='1') then -- 8000-BFFF
servicable <= '1';
end if;
if address_c(15 downto 13)="111" and (serve_rom='1') and (ultimax='1') then
servicable <= '1';
end if;
if address_c(15 downto 13)="111" and (kernal_enable='1') and (ba_c='1') then
servicable <= '1';
end if;
end if;
end process;
mem_req <= mem_req_ff;
mem_rwn <= rwn_c;
mem_wdata <= mem_wdata_i;
mem_size <= mem_size_i;
BUFFER_ENn <= '0';
DATA_out <= mem_data_0 when data_mux='0' else mem_data_1;
slot_req.data <= mem_wdata_i;
slot_req.bus_address <= unsigned(address_c(15 downto 0));
kernal_probe <= kernal_probe_i;
kernal_area <= kernal_area_i;
end gideon;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.slot_bus_pkg.all;
entity slot_slave is
port (
clock : in std_logic;
reset : in std_logic;
-- Cartridge pins
RSTn : in std_logic;
IO1n : in std_logic;
IO2n : in std_logic;
ROMLn : in std_logic;
ROMHn : in std_logic;
BA : in std_logic;
GAMEn : in std_logic;
EXROMn : in std_logic;
RWn : in std_logic;
ADDRESS : in std_logic_vector(15 downto 0);
DATA_in : in std_logic_vector(7 downto 0);
DATA_out : out std_logic_vector(7 downto 0) := (others => '0');
DATA_tri : out std_logic;
-- interface with memory controller
mem_req : out std_logic; -- our memory request to serve slot
mem_size : out unsigned(1 downto 0);
mem_rwn : out std_logic;
mem_rack : in std_logic;
mem_dack : in std_logic;
mem_count : in unsigned(1 downto 0);
mem_rdata : in std_logic_vector(7 downto 0);
mem_wdata : out std_logic_vector(7 downto 0);
-- mem_addr comes from cartridge logic
reset_out : out std_logic;
-- timing inputs
phi2_tick : in std_logic;
do_sample_addr : in std_logic;
do_probe_end : in std_logic;
do_sample_io : in std_logic;
do_io_event : in std_logic;
-- interface with freezer (cartridge) logic
allow_serve : in std_logic := '0'; -- from timing unit (modified version of serve_enable)
serve_rom : in std_logic := '0'; -- ROML or ROMH
serve_io1 : in std_logic := '0'; -- IO1n
serve_io2 : in std_logic := '0'; -- IO2n
allow_write : in std_logic := '0';
kernal_enable : in std_logic := '0';
kernal_probe : out std_logic := '0';
kernal_area : out std_logic := '0';
force_ultimax : out std_logic := '0';
do_reg_output : in std_logic := '0';
epyx_timeout : out std_logic; -- '0' => epyx is on, '1' epyx is off
cpu_write : out std_logic; -- for freezer
slot_req : out t_slot_req;
slot_resp : in t_slot_resp;
-- interface with hardware
BUFFER_ENn : out std_logic );
end slot_slave;
architecture gideon of slot_slave is
signal address_c : std_logic_vector(15 downto 0) := (others => '0');
signal data_c : std_logic_vector(7 downto 0) := X"FF";
signal io1n_c : std_logic := '1';
signal io2n_c : std_logic := '1';
signal rwn_c : std_logic := '1';
signal romhn_c : std_logic := '1';
signal romln_c : std_logic := '1';
signal ba_c : std_logic := '0';
signal dav : std_logic := '0';
signal addr_is_io : boolean;
signal addr_is_kernal : std_logic;
signal mem_req_ff : std_logic;
signal mem_size_i : unsigned(1 downto 0);
signal servicable : std_logic;
signal io_out : boolean := false;
signal io_read_cond : std_logic;
signal io_write_cond: std_logic;
signal late_write_cond : std_logic;
signal ultimax : std_logic;
signal ultimax_d : std_logic := '0';
signal ultimax_d2 : std_logic := '0';
signal last_rwn : std_logic;
signal mem_wdata_i : std_logic_vector(7 downto 0);
signal kernal_probe_i : std_logic;
signal kernal_area_i : std_logic;
signal mem_data_0 : std_logic_vector(7 downto 0) := X"00";
signal mem_data_1 : std_logic_vector(7 downto 0) := X"00";
signal data_mux : std_logic;
attribute register_duplication : string;
attribute register_duplication of rwn_c : signal is "no";
attribute register_duplication of io1n_c : signal is "no";
attribute register_duplication of io2n_c : signal is "no";
attribute register_duplication of romln_c : signal is "no";
attribute register_duplication of romhn_c : signal is "no";
attribute register_duplication of reset_out : signal is "no";
type t_state is (idle, mem_access, wait_end, reg_out);
attribute iob : string;
attribute iob of data_c : signal is "true";
signal state : t_state;
-- attribute fsm_encoding : string;
-- attribute fsm_encoding of state : signal is "sequential";
signal epyx_timer : unsigned(6 downto 0) := (others => '0');
signal epyx_reset : std_logic := '0';
begin
slot_req.io_write <= do_io_event and io_write_cond;
slot_req.io_read <= do_io_event and io_read_cond;
slot_req.late_write <= do_io_event and late_write_cond;
slot_req.io_read_early <= '1' when (addr_is_io and rwn_c='1' and do_sample_addr='1') else '0';
process(clock)
begin
if rising_edge(clock) then
-- synchronization
if mem_req_ff='0' then -- don't change while an access is taking place
rwn_c <= RWn;
address_c <= ADDRESS;
end if;
reset_out <= reset or not RSTn;
ba_c <= BA;
io1n_c <= IO1n;
io2n_c <= IO2n;
romln_c <= ROMLn;
romhn_c <= ROMHn;
data_c <= DATA_in;
ultimax <= not GAMEn and EXROMn;
ultimax_d <= ultimax;
ultimax_d2 <= ultimax_d;
if epyx_reset='1' then
epyx_timer <= (others => '1');
epyx_timeout <= '0';
elsif phi2_tick='1' then
if epyx_timer = "0000000" then
epyx_timeout <= '1';
else
epyx_timer <= epyx_timer - 1;
end if;
end if;
slot_req.bus_write <= '0';
if do_sample_io='1' then
cpu_write <= not RWn;
slot_req.bus_write <= not RWn;
slot_req.io_address <= unsigned(address_c);
mem_wdata_i <= data_c;
late_write_cond <= not rwn_c;
io_write_cond <= not rwn_c and (not io2n_c or not io1n_c);
io_read_cond <= rwn_c and (not io2n_c or not io1n_c);
epyx_reset <= not io2n_c or not io1n_c or not romln_c or not RSTn;
end if;
if do_probe_end='1' then
data_mux <= kernal_probe_i and not romhn_c;
force_ultimax <= kernal_probe_i;
kernal_probe_i <= '0';
elsif do_io_event='1' then
force_ultimax <= '0';
end if;
case state is
when idle =>
mem_size_i <= "00";
if do_sample_addr='1' then
-- register output
if slot_resp.reg_output='1' and addr_is_io and rwn_c='1' then -- read register
mem_data_0 <= slot_resp.data;
io_out <= true;
dav <= '1';
state <= reg_out;
elsif allow_serve='1' and servicable='1' and rwn_c='1' then
io_out <= false;
-- memory read
if kernal_enable='1' and ultimax='0' and addr_is_kernal='1' and ba_c='1' then
kernal_probe_i <= '1';
kernal_area_i <= '1';
mem_size_i <= "01";
end if;
if addr_is_io then
if ba_c='1' then -- only serve IO when BA='1' (Fix for Ethernet)
mem_req_ff <= '1';
state <= mem_access;
end if;
if address_c(8)='0' and serve_io1='1' then
io_out <= (rwn_c='1');
elsif address_c(8)='1' and serve_io2='1' then
io_out <= (rwn_c='1');
end if;
else -- non-IO, always serve
mem_req_ff <= '1';
state <= mem_access;
end if;
end if;
elsif do_sample_io='1' and rwn_c='0' then
if allow_write='1' then
-- memory write
if address_c(14)='1' then -- IO range
if io2n_c='0' or io1n_c='0' then
mem_req_ff <= '1';
state <= mem_access;
end if;
else
mem_req_ff <= '1';
state <= mem_access;
end if;
elsif kernal_enable='1' and addr_is_kernal='1' then
-- do mirror to kernal write address
mem_req_ff <= '1';
state <= mem_access;
kernal_area_i <= '1';
end if;
end if;
when mem_access =>
if mem_rack='1' then
mem_req_ff <= '0'; -- clear request
if rwn_c='0' then -- if write, we're done.
kernal_area_i <= '0';
state <= idle;
else -- if read, then we need to wait for the data
state <= wait_end;
end if;
end if;
-- this will never happen, because we have latency from RAM.
-- if mem_dack='1' then -- in case the data comes immediately
-- DATA_out <= mem_rdata;
-- dav <= '1';
-- end if;
when wait_end =>
if mem_dack='1' then -- the data is available, put it on the bus!
if mem_count="00" then
mem_data_0 <= mem_rdata;
else
mem_data_1 <= mem_rdata;
end if;
dav <= '1';
end if;
if phi2_tick='1' or do_io_event='1' then -- around the clock edges
kernal_area_i <= '0';
state <= idle;
io_out <= false;
dav <= '0';
end if;
when reg_out =>
mem_data_0 <= slot_resp.data;
if phi2_tick='1' or do_io_event='1' then -- around the clock edges
state <= idle;
io_out <= false;
dav <= '0';
end if;
when others =>
null;
end case;
if (kernal_area_i='1') then
DATA_tri <= not romhn_c and ultimax_d2 and rwn_c;
elsif (io_out and (io1n_c='0' or io2n_c='0')) or
((romln_c='0' or romhn_c='0') and (rwn_c='1')) then
DATA_tri <= mem_dack or dav;
else
DATA_tri <= '0';
end if;
if reset='1' then
data_mux <= '0';
last_rwn <= '1';
dav <= '0';
state <= idle;
mem_req_ff <= '0';
mem_size_i <= "00";
io_out <= false;
io_read_cond <= '0';
io_write_cond <= '0';
late_write_cond <= '0';
slot_req.io_address <= (others => '0');
cpu_write <= '0';
epyx_reset <= '1';
kernal_probe_i <= '0';
kernal_area_i <= '0';
force_ultimax <= '0';
end if;
end if;
end process;
-- combinatoric
addr_is_io <= (address_c(15 downto 9)="1101111"); -- DE/DF
addr_is_kernal <= '1' when (address_c(15 downto 13)="111") else '0';
process(rwn_c, address_c, addr_is_io, romln_c, romhn_c, serve_rom, serve_io1, serve_io2, ultimax, kernal_enable, ba_c)
begin
servicable <= '0';
if rwn_c='1' then
if addr_is_io and (serve_io1='1' or serve_io2='1') then
servicable <= '1';
end if;
-- if (romln_c='0' or romhn_c='0') and (serve_rom='1') then -- our decode is faster!
if address_c(15 downto 14)="10" and (serve_rom='1') then -- 8000-BFFF
servicable <= '1';
end if;
if address_c(15 downto 13)="111" and (serve_rom='1') and (ultimax='1') then
servicable <= '1';
end if;
if address_c(15 downto 13)="111" and (kernal_enable='1') and (ba_c='1') then
servicable <= '1';
end if;
end if;
end process;
mem_req <= mem_req_ff;
mem_rwn <= rwn_c;
mem_wdata <= mem_wdata_i;
mem_size <= mem_size_i;
BUFFER_ENn <= '0';
DATA_out <= mem_data_0 when data_mux='0' else mem_data_1;
slot_req.data <= mem_wdata_i;
slot_req.bus_address <= unsigned(address_c(15 downto 0));
kernal_probe <= kernal_probe_i;
kernal_area <= kernal_area_i;
end gideon;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.slot_bus_pkg.all;
entity slot_slave is
port (
clock : in std_logic;
reset : in std_logic;
-- Cartridge pins
RSTn : in std_logic;
IO1n : in std_logic;
IO2n : in std_logic;
ROMLn : in std_logic;
ROMHn : in std_logic;
BA : in std_logic;
GAMEn : in std_logic;
EXROMn : in std_logic;
RWn : in std_logic;
ADDRESS : in std_logic_vector(15 downto 0);
DATA_in : in std_logic_vector(7 downto 0);
DATA_out : out std_logic_vector(7 downto 0) := (others => '0');
DATA_tri : out std_logic;
-- interface with memory controller
mem_req : out std_logic; -- our memory request to serve slot
mem_size : out unsigned(1 downto 0);
mem_rwn : out std_logic;
mem_rack : in std_logic;
mem_dack : in std_logic;
mem_count : in unsigned(1 downto 0);
mem_rdata : in std_logic_vector(7 downto 0);
mem_wdata : out std_logic_vector(7 downto 0);
-- mem_addr comes from cartridge logic
reset_out : out std_logic;
-- timing inputs
phi2_tick : in std_logic;
do_sample_addr : in std_logic;
do_probe_end : in std_logic;
do_sample_io : in std_logic;
do_io_event : in std_logic;
-- interface with freezer (cartridge) logic
allow_serve : in std_logic := '0'; -- from timing unit (modified version of serve_enable)
serve_rom : in std_logic := '0'; -- ROML or ROMH
serve_io1 : in std_logic := '0'; -- IO1n
serve_io2 : in std_logic := '0'; -- IO2n
allow_write : in std_logic := '0';
kernal_enable : in std_logic := '0';
kernal_probe : out std_logic := '0';
kernal_area : out std_logic := '0';
force_ultimax : out std_logic := '0';
do_reg_output : in std_logic := '0';
epyx_timeout : out std_logic; -- '0' => epyx is on, '1' epyx is off
cpu_write : out std_logic; -- for freezer
slot_req : out t_slot_req;
slot_resp : in t_slot_resp;
-- interface with hardware
BUFFER_ENn : out std_logic );
end slot_slave;
architecture gideon of slot_slave is
signal address_c : std_logic_vector(15 downto 0) := (others => '0');
signal data_c : std_logic_vector(7 downto 0) := X"FF";
signal io1n_c : std_logic := '1';
signal io2n_c : std_logic := '1';
signal rwn_c : std_logic := '1';
signal romhn_c : std_logic := '1';
signal romln_c : std_logic := '1';
signal ba_c : std_logic := '0';
signal dav : std_logic := '0';
signal addr_is_io : boolean;
signal addr_is_kernal : std_logic;
signal mem_req_ff : std_logic;
signal mem_size_i : unsigned(1 downto 0);
signal servicable : std_logic;
signal io_out : boolean := false;
signal io_read_cond : std_logic;
signal io_write_cond: std_logic;
signal late_write_cond : std_logic;
signal ultimax : std_logic;
signal ultimax_d : std_logic := '0';
signal ultimax_d2 : std_logic := '0';
signal last_rwn : std_logic;
signal mem_wdata_i : std_logic_vector(7 downto 0);
signal kernal_probe_i : std_logic;
signal kernal_area_i : std_logic;
signal mem_data_0 : std_logic_vector(7 downto 0) := X"00";
signal mem_data_1 : std_logic_vector(7 downto 0) := X"00";
signal data_mux : std_logic;
attribute register_duplication : string;
attribute register_duplication of rwn_c : signal is "no";
attribute register_duplication of io1n_c : signal is "no";
attribute register_duplication of io2n_c : signal is "no";
attribute register_duplication of romln_c : signal is "no";
attribute register_duplication of romhn_c : signal is "no";
attribute register_duplication of reset_out : signal is "no";
type t_state is (idle, mem_access, wait_end, reg_out);
attribute iob : string;
attribute iob of data_c : signal is "true";
signal state : t_state;
-- attribute fsm_encoding : string;
-- attribute fsm_encoding of state : signal is "sequential";
signal epyx_timer : unsigned(6 downto 0) := (others => '0');
signal epyx_reset : std_logic := '0';
begin
slot_req.io_write <= do_io_event and io_write_cond;
slot_req.io_read <= do_io_event and io_read_cond;
slot_req.late_write <= do_io_event and late_write_cond;
slot_req.io_read_early <= '1' when (addr_is_io and rwn_c='1' and do_sample_addr='1') else '0';
process(clock)
begin
if rising_edge(clock) then
-- synchronization
if mem_req_ff='0' then -- don't change while an access is taking place
rwn_c <= RWn;
address_c <= ADDRESS;
end if;
reset_out <= reset or not RSTn;
ba_c <= BA;
io1n_c <= IO1n;
io2n_c <= IO2n;
romln_c <= ROMLn;
romhn_c <= ROMHn;
data_c <= DATA_in;
ultimax <= not GAMEn and EXROMn;
ultimax_d <= ultimax;
ultimax_d2 <= ultimax_d;
if epyx_reset='1' then
epyx_timer <= (others => '1');
epyx_timeout <= '0';
elsif phi2_tick='1' then
if epyx_timer = "0000000" then
epyx_timeout <= '1';
else
epyx_timer <= epyx_timer - 1;
end if;
end if;
slot_req.bus_write <= '0';
if do_sample_io='1' then
cpu_write <= not RWn;
slot_req.bus_write <= not RWn;
slot_req.io_address <= unsigned(address_c);
mem_wdata_i <= data_c;
late_write_cond <= not rwn_c;
io_write_cond <= not rwn_c and (not io2n_c or not io1n_c);
io_read_cond <= rwn_c and (not io2n_c or not io1n_c);
epyx_reset <= not io2n_c or not io1n_c or not romln_c or not RSTn;
end if;
if do_probe_end='1' then
data_mux <= kernal_probe_i and not romhn_c;
force_ultimax <= kernal_probe_i;
kernal_probe_i <= '0';
elsif do_io_event='1' then
force_ultimax <= '0';
end if;
case state is
when idle =>
mem_size_i <= "00";
if do_sample_addr='1' then
-- register output
if slot_resp.reg_output='1' and addr_is_io and rwn_c='1' then -- read register
mem_data_0 <= slot_resp.data;
io_out <= true;
dav <= '1';
state <= reg_out;
elsif allow_serve='1' and servicable='1' and rwn_c='1' then
io_out <= false;
-- memory read
if kernal_enable='1' and ultimax='0' and addr_is_kernal='1' and ba_c='1' then
kernal_probe_i <= '1';
kernal_area_i <= '1';
mem_size_i <= "01";
end if;
if addr_is_io then
if ba_c='1' then -- only serve IO when BA='1' (Fix for Ethernet)
mem_req_ff <= '1';
state <= mem_access;
end if;
if address_c(8)='0' and serve_io1='1' then
io_out <= (rwn_c='1');
elsif address_c(8)='1' and serve_io2='1' then
io_out <= (rwn_c='1');
end if;
else -- non-IO, always serve
mem_req_ff <= '1';
state <= mem_access;
end if;
end if;
elsif do_sample_io='1' and rwn_c='0' then
if allow_write='1' then
-- memory write
if address_c(14)='1' then -- IO range
if io2n_c='0' or io1n_c='0' then
mem_req_ff <= '1';
state <= mem_access;
end if;
else
mem_req_ff <= '1';
state <= mem_access;
end if;
elsif kernal_enable='1' and addr_is_kernal='1' then
-- do mirror to kernal write address
mem_req_ff <= '1';
state <= mem_access;
kernal_area_i <= '1';
end if;
end if;
when mem_access =>
if mem_rack='1' then
mem_req_ff <= '0'; -- clear request
if rwn_c='0' then -- if write, we're done.
kernal_area_i <= '0';
state <= idle;
else -- if read, then we need to wait for the data
state <= wait_end;
end if;
end if;
-- this will never happen, because we have latency from RAM.
-- if mem_dack='1' then -- in case the data comes immediately
-- DATA_out <= mem_rdata;
-- dav <= '1';
-- end if;
when wait_end =>
if mem_dack='1' then -- the data is available, put it on the bus!
if mem_count="00" then
mem_data_0 <= mem_rdata;
else
mem_data_1 <= mem_rdata;
end if;
dav <= '1';
end if;
if phi2_tick='1' or do_io_event='1' then -- around the clock edges
kernal_area_i <= '0';
state <= idle;
io_out <= false;
dav <= '0';
end if;
when reg_out =>
mem_data_0 <= slot_resp.data;
if phi2_tick='1' or do_io_event='1' then -- around the clock edges
state <= idle;
io_out <= false;
dav <= '0';
end if;
when others =>
null;
end case;
if (kernal_area_i='1') then
DATA_tri <= not romhn_c and ultimax_d2 and rwn_c;
elsif (io_out and (io1n_c='0' or io2n_c='0')) or
((romln_c='0' or romhn_c='0') and (rwn_c='1')) then
DATA_tri <= mem_dack or dav;
else
DATA_tri <= '0';
end if;
if reset='1' then
data_mux <= '0';
last_rwn <= '1';
dav <= '0';
state <= idle;
mem_req_ff <= '0';
mem_size_i <= "00";
io_out <= false;
io_read_cond <= '0';
io_write_cond <= '0';
late_write_cond <= '0';
slot_req.io_address <= (others => '0');
cpu_write <= '0';
epyx_reset <= '1';
kernal_probe_i <= '0';
kernal_area_i <= '0';
force_ultimax <= '0';
end if;
end if;
end process;
-- combinatoric
addr_is_io <= (address_c(15 downto 9)="1101111"); -- DE/DF
addr_is_kernal <= '1' when (address_c(15 downto 13)="111") else '0';
process(rwn_c, address_c, addr_is_io, romln_c, romhn_c, serve_rom, serve_io1, serve_io2, ultimax, kernal_enable, ba_c)
begin
servicable <= '0';
if rwn_c='1' then
if addr_is_io and (serve_io1='1' or serve_io2='1') then
servicable <= '1';
end if;
-- if (romln_c='0' or romhn_c='0') and (serve_rom='1') then -- our decode is faster!
if address_c(15 downto 14)="10" and (serve_rom='1') then -- 8000-BFFF
servicable <= '1';
end if;
if address_c(15 downto 13)="111" and (serve_rom='1') and (ultimax='1') then
servicable <= '1';
end if;
if address_c(15 downto 13)="111" and (kernal_enable='1') and (ba_c='1') then
servicable <= '1';
end if;
end if;
end process;
mem_req <= mem_req_ff;
mem_rwn <= rwn_c;
mem_wdata <= mem_wdata_i;
mem_size <= mem_size_i;
BUFFER_ENn <= '0';
DATA_out <= mem_data_0 when data_mux='0' else mem_data_1;
slot_req.data <= mem_wdata_i;
slot_req.bus_address <= unsigned(address_c(15 downto 0));
kernal_probe <= kernal_probe_i;
kernal_area <= kernal_area_i;
end gideon;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.slot_bus_pkg.all;
entity slot_slave is
port (
clock : in std_logic;
reset : in std_logic;
-- Cartridge pins
RSTn : in std_logic;
IO1n : in std_logic;
IO2n : in std_logic;
ROMLn : in std_logic;
ROMHn : in std_logic;
BA : in std_logic;
GAMEn : in std_logic;
EXROMn : in std_logic;
RWn : in std_logic;
ADDRESS : in std_logic_vector(15 downto 0);
DATA_in : in std_logic_vector(7 downto 0);
DATA_out : out std_logic_vector(7 downto 0) := (others => '0');
DATA_tri : out std_logic;
-- interface with memory controller
mem_req : out std_logic; -- our memory request to serve slot
mem_size : out unsigned(1 downto 0);
mem_rwn : out std_logic;
mem_rack : in std_logic;
mem_dack : in std_logic;
mem_count : in unsigned(1 downto 0);
mem_rdata : in std_logic_vector(7 downto 0);
mem_wdata : out std_logic_vector(7 downto 0);
-- mem_addr comes from cartridge logic
reset_out : out std_logic;
-- timing inputs
phi2_tick : in std_logic;
do_sample_addr : in std_logic;
do_probe_end : in std_logic;
do_sample_io : in std_logic;
do_io_event : in std_logic;
-- interface with freezer (cartridge) logic
allow_serve : in std_logic := '0'; -- from timing unit (modified version of serve_enable)
serve_rom : in std_logic := '0'; -- ROML or ROMH
serve_io1 : in std_logic := '0'; -- IO1n
serve_io2 : in std_logic := '0'; -- IO2n
allow_write : in std_logic := '0';
kernal_enable : in std_logic := '0';
kernal_probe : out std_logic := '0';
kernal_area : out std_logic := '0';
force_ultimax : out std_logic := '0';
do_reg_output : in std_logic := '0';
epyx_timeout : out std_logic; -- '0' => epyx is on, '1' epyx is off
cpu_write : out std_logic; -- for freezer
slot_req : out t_slot_req;
slot_resp : in t_slot_resp;
-- interface with hardware
BUFFER_ENn : out std_logic );
end slot_slave;
architecture gideon of slot_slave is
signal address_c : std_logic_vector(15 downto 0) := (others => '0');
signal data_c : std_logic_vector(7 downto 0) := X"FF";
signal io1n_c : std_logic := '1';
signal io2n_c : std_logic := '1';
signal rwn_c : std_logic := '1';
signal romhn_c : std_logic := '1';
signal romln_c : std_logic := '1';
signal ba_c : std_logic := '0';
signal dav : std_logic := '0';
signal addr_is_io : boolean;
signal addr_is_kernal : std_logic;
signal mem_req_ff : std_logic;
signal mem_size_i : unsigned(1 downto 0);
signal servicable : std_logic;
signal io_out : boolean := false;
signal io_read_cond : std_logic;
signal io_write_cond: std_logic;
signal late_write_cond : std_logic;
signal ultimax : std_logic;
signal ultimax_d : std_logic := '0';
signal ultimax_d2 : std_logic := '0';
signal last_rwn : std_logic;
signal mem_wdata_i : std_logic_vector(7 downto 0);
signal kernal_probe_i : std_logic;
signal kernal_area_i : std_logic;
signal mem_data_0 : std_logic_vector(7 downto 0) := X"00";
signal mem_data_1 : std_logic_vector(7 downto 0) := X"00";
signal data_mux : std_logic;
attribute register_duplication : string;
attribute register_duplication of rwn_c : signal is "no";
attribute register_duplication of io1n_c : signal is "no";
attribute register_duplication of io2n_c : signal is "no";
attribute register_duplication of romln_c : signal is "no";
attribute register_duplication of romhn_c : signal is "no";
attribute register_duplication of reset_out : signal is "no";
type t_state is (idle, mem_access, wait_end, reg_out);
attribute iob : string;
attribute iob of data_c : signal is "true";
signal state : t_state;
-- attribute fsm_encoding : string;
-- attribute fsm_encoding of state : signal is "sequential";
signal epyx_timer : unsigned(6 downto 0) := (others => '0');
signal epyx_reset : std_logic := '0';
begin
slot_req.io_write <= do_io_event and io_write_cond;
slot_req.io_read <= do_io_event and io_read_cond;
slot_req.late_write <= do_io_event and late_write_cond;
slot_req.io_read_early <= '1' when (addr_is_io and rwn_c='1' and do_sample_addr='1') else '0';
process(clock)
begin
if rising_edge(clock) then
-- synchronization
if mem_req_ff='0' then -- don't change while an access is taking place
rwn_c <= RWn;
address_c <= ADDRESS;
end if;
reset_out <= reset or not RSTn;
ba_c <= BA;
io1n_c <= IO1n;
io2n_c <= IO2n;
romln_c <= ROMLn;
romhn_c <= ROMHn;
data_c <= DATA_in;
ultimax <= not GAMEn and EXROMn;
ultimax_d <= ultimax;
ultimax_d2 <= ultimax_d;
if epyx_reset='1' then
epyx_timer <= (others => '1');
epyx_timeout <= '0';
elsif phi2_tick='1' then
if epyx_timer = "0000000" then
epyx_timeout <= '1';
else
epyx_timer <= epyx_timer - 1;
end if;
end if;
slot_req.bus_write <= '0';
if do_sample_io='1' then
cpu_write <= not RWn;
slot_req.bus_write <= not RWn;
slot_req.io_address <= unsigned(address_c);
mem_wdata_i <= data_c;
late_write_cond <= not rwn_c;
io_write_cond <= not rwn_c and (not io2n_c or not io1n_c);
io_read_cond <= rwn_c and (not io2n_c or not io1n_c);
epyx_reset <= not io2n_c or not io1n_c or not romln_c or not RSTn;
end if;
if do_probe_end='1' then
data_mux <= kernal_probe_i and not romhn_c;
force_ultimax <= kernal_probe_i;
kernal_probe_i <= '0';
elsif do_io_event='1' then
force_ultimax <= '0';
end if;
case state is
when idle =>
mem_size_i <= "00";
if do_sample_addr='1' then
-- register output
if slot_resp.reg_output='1' and addr_is_io and rwn_c='1' then -- read register
mem_data_0 <= slot_resp.data;
io_out <= true;
dav <= '1';
state <= reg_out;
elsif allow_serve='1' and servicable='1' and rwn_c='1' then
io_out <= false;
-- memory read
if kernal_enable='1' and ultimax='0' and addr_is_kernal='1' and ba_c='1' then
kernal_probe_i <= '1';
kernal_area_i <= '1';
mem_size_i <= "01";
end if;
if addr_is_io then
if ba_c='1' then -- only serve IO when BA='1' (Fix for Ethernet)
mem_req_ff <= '1';
state <= mem_access;
end if;
if address_c(8)='0' and serve_io1='1' then
io_out <= (rwn_c='1');
elsif address_c(8)='1' and serve_io2='1' then
io_out <= (rwn_c='1');
end if;
else -- non-IO, always serve
mem_req_ff <= '1';
state <= mem_access;
end if;
end if;
elsif do_sample_io='1' and rwn_c='0' then
if allow_write='1' then
-- memory write
if address_c(14)='1' then -- IO range
if io2n_c='0' or io1n_c='0' then
mem_req_ff <= '1';
state <= mem_access;
end if;
else
mem_req_ff <= '1';
state <= mem_access;
end if;
elsif kernal_enable='1' and addr_is_kernal='1' then
-- do mirror to kernal write address
mem_req_ff <= '1';
state <= mem_access;
kernal_area_i <= '1';
end if;
end if;
when mem_access =>
if mem_rack='1' then
mem_req_ff <= '0'; -- clear request
if rwn_c='0' then -- if write, we're done.
kernal_area_i <= '0';
state <= idle;
else -- if read, then we need to wait for the data
state <= wait_end;
end if;
end if;
-- this will never happen, because we have latency from RAM.
-- if mem_dack='1' then -- in case the data comes immediately
-- DATA_out <= mem_rdata;
-- dav <= '1';
-- end if;
when wait_end =>
if mem_dack='1' then -- the data is available, put it on the bus!
if mem_count="00" then
mem_data_0 <= mem_rdata;
else
mem_data_1 <= mem_rdata;
end if;
dav <= '1';
end if;
if phi2_tick='1' or do_io_event='1' then -- around the clock edges
kernal_area_i <= '0';
state <= idle;
io_out <= false;
dav <= '0';
end if;
when reg_out =>
mem_data_0 <= slot_resp.data;
if phi2_tick='1' or do_io_event='1' then -- around the clock edges
state <= idle;
io_out <= false;
dav <= '0';
end if;
when others =>
null;
end case;
if (kernal_area_i='1') then
DATA_tri <= not romhn_c and ultimax_d2 and rwn_c;
elsif (io_out and (io1n_c='0' or io2n_c='0')) or
((romln_c='0' or romhn_c='0') and (rwn_c='1')) then
DATA_tri <= mem_dack or dav;
else
DATA_tri <= '0';
end if;
if reset='1' then
data_mux <= '0';
last_rwn <= '1';
dav <= '0';
state <= idle;
mem_req_ff <= '0';
mem_size_i <= "00";
io_out <= false;
io_read_cond <= '0';
io_write_cond <= '0';
late_write_cond <= '0';
slot_req.io_address <= (others => '0');
cpu_write <= '0';
epyx_reset <= '1';
kernal_probe_i <= '0';
kernal_area_i <= '0';
force_ultimax <= '0';
end if;
end if;
end process;
-- combinatoric
addr_is_io <= (address_c(15 downto 9)="1101111"); -- DE/DF
addr_is_kernal <= '1' when (address_c(15 downto 13)="111") else '0';
process(rwn_c, address_c, addr_is_io, romln_c, romhn_c, serve_rom, serve_io1, serve_io2, ultimax, kernal_enable, ba_c)
begin
servicable <= '0';
if rwn_c='1' then
if addr_is_io and (serve_io1='1' or serve_io2='1') then
servicable <= '1';
end if;
-- if (romln_c='0' or romhn_c='0') and (serve_rom='1') then -- our decode is faster!
if address_c(15 downto 14)="10" and (serve_rom='1') then -- 8000-BFFF
servicable <= '1';
end if;
if address_c(15 downto 13)="111" and (serve_rom='1') and (ultimax='1') then
servicable <= '1';
end if;
if address_c(15 downto 13)="111" and (kernal_enable='1') and (ba_c='1') then
servicable <= '1';
end if;
end if;
end process;
mem_req <= mem_req_ff;
mem_rwn <= rwn_c;
mem_wdata <= mem_wdata_i;
mem_size <= mem_size_i;
BUFFER_ENn <= '0';
DATA_out <= mem_data_0 when data_mux='0' else mem_data_1;
slot_req.data <= mem_wdata_i;
slot_req.bus_address <= unsigned(address_c(15 downto 0));
kernal_probe <= kernal_probe_i;
kernal_area <= kernal_area_i;
end gideon;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc44.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x01p02n01i00044ent IS
END c04s03b01x01p02n01i00044ent;
ARCHITECTURE c04s03b01x01p02n01i00044arch OF c04s03b01x01p02n01i00044ent IS
constant c: integer (2+3); -- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s03b01x01p02n01i00044 - Syntactic error in constant declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b01x01p02n01i00044arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc44.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x01p02n01i00044ent IS
END c04s03b01x01p02n01i00044ent;
ARCHITECTURE c04s03b01x01p02n01i00044arch OF c04s03b01x01p02n01i00044ent IS
constant c: integer (2+3); -- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s03b01x01p02n01i00044 - Syntactic error in constant declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b01x01p02n01i00044arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc44.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x01p02n01i00044ent IS
END c04s03b01x01p02n01i00044ent;
ARCHITECTURE c04s03b01x01p02n01i00044arch OF c04s03b01x01p02n01i00044ent IS
constant c: integer (2+3); -- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s03b01x01p02n01i00044 - Syntactic error in constant declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b01x01p02n01i00044arch;
|
--ÀûÓÃbufferʵÏֵķÖƵÆ÷£¬´úÂëÁ¿ÉÙÓÚÓÃCNT10¸ÄÔì
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY FrequencyDivider is
PORT(
data: in std_logic_vector(15 downto 0);--16λԤÖÃÊý£¬load·Ç¸ßµçƽÖÃÊý
en,clk:in std_logic;--ʹÄÜ£¬Ê±ÖÓ
q: buffer std_logic_vector(15 downto 0);--16λ¼ÆÊý
cout:buffer std_logic--Òç³ö룬¸ßµçƽÒç³ö£¬ÓÃbuffer±£´æ״̬ȡ·´£¬ÇáÒ×ʵÏÖ·ÖƵ
);
END FrequencyDivider;
architecture behavior OF FrequencyDivider IS
BEGIN
process(clk,en,cout) begin
if(rising_edge(clk)) then --ʱÖÓÉÏÉýÑØʱ¿ªÊ¼¹¤×÷
if(en='1')then --Enable£¬¿ª¹Ø
if(q=data-1)then --qΪdata£¬Òç³öʵÏÖ·ÖƵ£¬ÒòΪ´Ó0¿ªÊ¼¼ÓËùÒÔÒª¼õ1
q<="0000000000000000";
if(cout='1') then
cout<='0';
else
cout<='1';
end if;
else
q<=q+1;
end if;
else
q<=q;
end if;
end if;
end process;
END behavior;
--ÁÖ²Ó±ó
--https://github.com/lincanbin
--20150504 |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1506.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s08b00x00p14n04i01506ent IS
END c08s08b00x00p14n04i01506ent;
ARCHITECTURE c08s08b00x00p14n04i01506arch OF c08s08b00x00p14n04i01506ent IS
BEGIN
TESTING: PROCESS
type day is (sun,mon,tue,wed,thu,fri,sat);
type rec_type is
record
element : day;
end record;
variable s_day ; day;
BEGIN
case s_day is
when sun => NULL;
when mon => NULL;
when elements => NULL;
when others => NULL;
end case;
assert FALSE
report "***FAILED TEST: c08s08b00x00p14n04i01506 - A simple name is not allowed as an alternative in a CASE statement"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s08b00x00p14n04i01506arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1506.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s08b00x00p14n04i01506ent IS
END c08s08b00x00p14n04i01506ent;
ARCHITECTURE c08s08b00x00p14n04i01506arch OF c08s08b00x00p14n04i01506ent IS
BEGIN
TESTING: PROCESS
type day is (sun,mon,tue,wed,thu,fri,sat);
type rec_type is
record
element : day;
end record;
variable s_day ; day;
BEGIN
case s_day is
when sun => NULL;
when mon => NULL;
when elements => NULL;
when others => NULL;
end case;
assert FALSE
report "***FAILED TEST: c08s08b00x00p14n04i01506 - A simple name is not allowed as an alternative in a CASE statement"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s08b00x00p14n04i01506arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1506.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s08b00x00p14n04i01506ent IS
END c08s08b00x00p14n04i01506ent;
ARCHITECTURE c08s08b00x00p14n04i01506arch OF c08s08b00x00p14n04i01506ent IS
BEGIN
TESTING: PROCESS
type day is (sun,mon,tue,wed,thu,fri,sat);
type rec_type is
record
element : day;
end record;
variable s_day ; day;
BEGIN
case s_day is
when sun => NULL;
when mon => NULL;
when elements => NULL;
when others => NULL;
end case;
assert FALSE
report "***FAILED TEST: c08s08b00x00p14n04i01506 - A simple name is not allowed as an alternative in a CASE statement"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s08b00x00p14n04i01506arch;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_a_e
--
-- Generated
-- by: wig
-- on: Sat Mar 3 17:08:41 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -nodelta ../case.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_a_e-rtl-a_1.vhd,v 1.1 2007/03/05 08:58:59 wig Exp $
-- $Date: 2007/03/05 08:58:59 $
-- $Log: inst_a_e-rtl-a_1.vhd,v $
-- Revision 1.1 2007/03/05 08:58:59 wig
-- Upgraded testcases
-- case/force still not fully operational (internal names keep case).
--
-- Revision 1.1 2007/03/03 17:24:06 wig
-- Updated testcase for case matches. Added filename serialization.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.101 2007/03/01 16:28:38 wig Exp
--
-- Generator: mix_0.pl Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_a_e
--
architecture rtl of inst_a_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component inst_aa_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_aa_e
case_aa_p : out _E_CONNTYPE
-- End of Generated Port for Entity inst_aa_e
);
end component;
-- ---------
component inst_ab_e
-- No Generated Generics
port (
-- Generated Port for Entity inst_ab_e
case_ab_p : in _E_CONNTYPE
-- End of Generated Port for Entity inst_ab_e
);
end component;
-- ---------
component inst_ac_e
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
--
-- Generated Signal List
--
signal Case : ;
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_aa
inst_aa: inst_aa_e
port map (
case_aa_p => Case
);
-- End of Generated Instance Port Map for inst_aa
-- Generated Instance Port Map for inst_ab
inst_ab: inst_ab_e
port map (
case_ab_p => Case
);
-- End of Generated Instance Port Map for inst_ab
-- Generated Instance Port Map for inst_ac
inst_ac: inst_ac_e
;
-- End of Generated Instance Port Map for inst_ac
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
--------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 08-02-2016
-- Module Name: fulladdr.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity fulladdr is
port(a, b : in std_logic_vector(3 downto 0);
c_in : in std_logic;
c_out : out std_logic;
sum : out std_logic_vector(3 downto 0));
end entity fulladdr;
architecture rtl of fulladdr is
signal im : std_logic_vector(4 downto 0);
begin
im <= ('0'&a) + ('0'&b) + c_in;
sum <= im(3 downto 0);
c_out <= im(4);
end architecture rtl;
|
--------------------------------------------------------------------------------
-- Author: Parham Alvani ([email protected])
--
-- Create Date: 08-02-2016
-- Module Name: fulladdr.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity fulladdr is
port(a, b : in std_logic_vector(3 downto 0);
c_in : in std_logic;
c_out : out std_logic;
sum : out std_logic_vector(3 downto 0));
end entity fulladdr;
architecture rtl of fulladdr is
signal im : std_logic_vector(4 downto 0);
begin
im <= ('0'&a) + ('0'&b) + c_in;
sum <= im(3 downto 0);
c_out <= im(4);
end architecture rtl;
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "goertzel_pipeline"
-------------------------------------------------------------------------------
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.signalprocessing_pkg.all;
-------------------------------------------------------------------------------
entity goertzel_pipeline_tb is
end entity goertzel_pipeline_tb;
-------------------------------------------------------------------------------
architecture tb of goertzel_pipeline_tb is
-- component generics
constant Q : natural := 13;
-- component ports
signal coef_p : goertzel_coef_type := (others => '0');
signal input_p : goertzel_input_type := (others => '0');
signal delay_p : goertzel_result_type := (others => (others => '0'));
signal result_p : goertzel_result_type := (others => (others => '0'));
-- clock
signal clk : std_logic := '1';
begin -- architecture tb
-- component instantiation
DUT : entity work.goertzel_pipeline
generic map (
Q => Q)
port map (
coef_p => coef_p,
input_p => input_p,
delay_p => delay_p,
result_p => result_p,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
-- waveform generation
WaveGen_Proc : process
begin
wait until clk = '0';
wait until clk = '0';
-- resize is not exactly what's intende because it takes care of the sign
-- bit (MSB) when truncating. But for simple test purposes this does not
-- matter as the actual data is unimportant.
coef_p <= resize(x"323fe", coef_p'length);
delay_p <= resize(x"1ffff", 18) & resize(x"14238", 18);
input_p <= resize(x"193af", input_p'length);
end process WaveGen_Proc;
end architecture tb;
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "goertzel_pipeline"
-------------------------------------------------------------------------------
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2012
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.signalprocessing_pkg.all;
-------------------------------------------------------------------------------
entity goertzel_pipeline_tb is
end entity goertzel_pipeline_tb;
-------------------------------------------------------------------------------
architecture tb of goertzel_pipeline_tb is
-- component generics
constant Q : natural := 13;
-- component ports
signal coef_p : goertzel_coef_type := (others => '0');
signal input_p : goertzel_input_type := (others => '0');
signal delay_p : goertzel_result_type := (others => (others => '0'));
signal result_p : goertzel_result_type := (others => (others => '0'));
-- clock
signal clk : std_logic := '1';
begin -- architecture tb
-- component instantiation
DUT : entity work.goertzel_pipeline
generic map (
Q => Q)
port map (
coef_p => coef_p,
input_p => input_p,
delay_p => delay_p,
result_p => result_p,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
-- waveform generation
WaveGen_Proc : process
begin
wait until clk = '0';
wait until clk = '0';
-- resize is not exactly what's intende because it takes care of the sign
-- bit (MSB) when truncating. But for simple test purposes this does not
-- matter as the actual data is unimportant.
coef_p <= resize(x"323fe", coef_p'length);
delay_p <= resize(x"1ffff", 18) & resize(x"14238", 18);
input_p <= resize(x"193af", input_p'length);
end process WaveGen_Proc;
end architecture tb;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: ALU_Toplevel
-- Project Name: ALU
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: ALU top level
---------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.all;
entity ALU is
Port ( CLK : in STD_LOGIC;
RA : in STD_LOGIC_VECTOR (7 downto 0);
RB : in STD_LOGIC_VECTOR (7 downto 0);
OPCODE : in STD_LOGIC_VECTOR (3 downto 0);
CCR : out STD_LOGIC_VECTOR (3 downto 0);
ALU_OUT : out STD_LOGIC_VECTOR (7 downto 0);
LDST_OUT : out STD_LOGIC_VECTOR (7 downto 0));
end ALU;
architecture Structural of ALU is
signal arith : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal logic : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal shift : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal memory : STD_LOGIC_VECTOR (7 downto 0) := (OTHERS => '0');
signal ccr_arith : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
signal ccr_logic : STD_LOGIC_VECTOR (3 downto 0) := (OTHERS => '0');
begin
LDST_OUT <= memory;
Arith_Unit: entity work.Arith_Unit
port map( A => RA,
B => RB,
OP => OPCODE(2 downto 0),
CCR => ccr_arith,
RESULT => arith);
Logic_Unit: entity work.Logic_Unit
port map( A => RA,
B => RB,
OP => OPCODE(2 downto 0),
CCR => ccr_logic,
RESULT => logic);
shift_unit: entity work.alu_shift_unit
port map( A => RA,
COUNT => RB(2 downto 0),
OP => opcode(3),
RESULT => shift);
Load_Store_Unit: entity work.Load_Store_Unit
port map( CLK => CLK,
A => RA,
IMMED => RB,
OP => opcode,
RESULT => memory);
ALU_Mux: entity work.ALU_Mux
port map( OP => opcode,
ARITH => arith,
LOGIC => logic,
SHIFT => shift,
MEMORY => memory,
CCR_ARITH => ccr_arith,
CCR_LOGIC => ccr_logic,
ALU_OUT => ALU_OUT,
CCR_OUT => CCR);
end Structural;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := spartan3;
constant CFG_MEMTECH : integer := spartan3;
constant CFG_PADTECH : integer := spartan3;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := spartan3;
constant CFG_CLKMUL : integer := (8);
constant CFG_CLKDIV : integer := (25);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 4;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 2;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 2;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 4 + 64*0;
constant CFG_ATBSZ : integer := 4;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 1;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#001234#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDR2SP : integer := 1;
constant CFG_DDR2SP_INIT : integer := 1;
constant CFG_DDR2SP_FREQ : integer := (125);
constant CFG_DDR2SP_TRFC : integer := (130);
constant CFG_DDR2SP_DATAWIDTH : integer := (32);
constant CFG_DDR2SP_FTEN : integer := 0;
constant CFG_DDR2SP_FTWIDTH : integer := 0;
constant CFG_DDR2SP_COL : integer := (10);
constant CFG_DDR2SP_SIZE : integer := (128);
constant CFG_DDR2SP_DELAY0 : integer := (0);
constant CFG_DDR2SP_DELAY1 : integer := (0);
constant CFG_DDR2SP_DELAY2 : integer := (0);
constant CFG_DDR2SP_DELAY3 : integer := (0);
constant CFG_DDR2SP_DELAY4 : integer := (0);
constant CFG_DDR2SP_DELAY5 : integer := (0);
constant CFG_DDR2SP_DELAY6 : integer := (0);
constant CFG_DDR2SP_DELAY7 : integer := (0);
constant CFG_DDR2SP_NOSYNC : integer := 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 16;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- SVGA controller
constant CFG_SVGA_ENABLE : integer := 0;
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 0;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#0#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 0;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := 1;
constant CFG_SPIMCTRL_ASCALER : integer := 1;
constant CFG_SPIMCTRL_PWRUPCNT : integer := 0;
constant CFG_SPIMCTRL_OFFSET : integer := 16#0#;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 0;
constant CFG_SPICTRL_NUM : integer := 1;
constant CFG_SPICTRL_SLVS : integer := 1;
constant CFG_SPICTRL_FIFO : integer := 1;
constant CFG_SPICTRL_SLVREG : integer := 0;
constant CFG_SPICTRL_ODMODE : integer := 0;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 0;
constant CFG_SPICTRL_MAXWLEN : integer := 0;
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
-------------------------------------------------------------------------------
--
-- T8x48 ROM
-- Wrapper for ROM model from the LPM library.
--
-- $Id: t48_rom-lpm-a.vhd,v 1.1 2006-06-21 00:58:27 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
architecture lpm of t48_rom is
component lpm_rom
generic (
LPM_WIDTH : positive;
LPM_TYPE : string := "LPM_ROM";
LPM_WIDTHAD : positive;
LPM_NUMWORDS : natural := 0;
LPM_FILE : string;
LPM_ADDRESS_CONTROL : string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_HINT : string := "UNUSED"
);
port (
address : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
inclock : in std_logic;
outclock : in std_logic;
memenab : in std_logic;
q : out std_logic_vector(LPM_WIDTH-1 downto 0)
);
end component;
signal vdd_s : std_logic;
begin
vdd_s <= '1';
rom_b : lpm_rom
generic map (
LPM_WIDTH => 8,
LPM_TYPE => "LPM_ROM",
LPM_WIDTHAD => 10,
LPM_NUMWORDS => 2 ** 10,
LPM_FILE => "rom_t48.hex",
LPM_ADDRESS_CONTROL => "REGISTERED",
LPM_OUTDATA => "UNREGISTERED",
LPM_HINT => "UNUSED"
)
port map (
address => rom_addr_i,
inclock => clk_i,
outclock => clk_i,
memenab => vdd_s,
q => rom_data_o
);
end lpm;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-------------------------------------------------------------------------------
|
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.CONV_STD_LOGIC_VECTOR;
use work.PhoenixPackage.all;
use IEEE.std_logic_textio.all;
use STD.textio.all;
use IEEE.std_logic_unsigned.all;
entity topNoC is
end;
architecture topNoC of topNoC is
signal clock : regNrot:=(others=>'0');
signal reset : std_logic;
signal clock_rx: regNrot:=(others=>'0');
signal rx, credit_o: regNrot;
signal clock_tx, tx, credit_i, testLink_i, testLink_o: regNrot;
signal data_in, data_out : arrayNrot_regflit;
signal currentTime: std_logic_vector(4*TAM_FLIT-1 downto 0) := (others=>'0');
begin
reset <= '1', '0' after 10 ns;
clock <= not clock after 10 ns;
clock_rx <= not clock_rx after 10 ns;
--credit_i <= (others=>'1');
credit_i <= tx;
testLink_i <= (others=>'0');
NOC: Entity work.NOC
port map(
clock => clock,
reset => reset,
clock_rxLocal => clock_rx,
rxLocal => rx,
data_inLocal_flit => data_in,
credit_oLocal => credit_o,
clock_txLocal => clock_tx,
txLocal => tx,
data_outLocal_flit => data_out,
credit_iLocal => credit_i
);
-- 0: destino do pacote
-- 1: tamanho do pacote
-- 2: nodo origem
-- 3 a 6: timestamp do nodo de origem
-- 7 a 8: numero de sequencia do pacote
-- 9 a 12: timestamp de entrada na rede
-- 13+: payload
process (reset, clock(0))
begin
if (reset = '1') then
currentTime <= (others=>'0');
elsif (rising_edge(clock(0))) then
currentTime <= currentTime + 1;
end if;
end process;
InputModules: for i in 0 to (NROT-1) generate
IM : Entity work.inputModule
generic map(address => NUMBER_TO_ADDRESS(i))
port map(
done => rx(i),
data => data_in(i),
enable => credit_o(i),
currentTime => currentTime
);
end generate InputModules;
OutputModules: for i in 0 to (NROT-1) generate
OM : Entity work.outputModule
generic map(address => NUMBER_TO_ADDRESS(i))
port map(
clock => clock(i),
tx => tx(i),
data => data_out(i),
currentTime => currentTime
);
end generate OutputModules;
end topNoC;
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <[email protected]>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.types_pkg.all;
use work.string_methods_pkg.all;
use work.adaptations_pkg.all;
use work.license_pkg.all;
use work.alert_hierarchy_pkg.all;
use work.protected_types_pkg.all;
use std.env.all;
package methods_pkg is
-- Shared variables
shared variable shared_initialised_util : boolean := false;
shared variable shared_msg_id_panel : t_msg_id_panel := C_MSG_ID_PANEL_DEFAULT;
shared variable shared_log_file_name_is_set : boolean := false;
shared variable shared_alert_file_name_is_set : boolean := false;
shared variable shared_warned_time_stamp_trunc : boolean := false;
shared variable shared_alert_attention : t_alert_attention:= C_DEFAULT_ALERT_ATTENTION;
shared variable shared_stop_limit : t_alert_counters := C_DEFAULT_STOP_LIMIT;
shared variable shared_log_hdr_for_waveview : string(1 to C_LOG_HDR_FOR_WAVEVIEW_WIDTH);
shared variable shared_current_log_hdr : t_current_log_hdr;
shared variable shared_seed1 : positive;
shared variable shared_seed2 : positive;
shared variable shared_flag_array : t_sync_flag_record_array := (others => C_SYNC_FLAG_DEFAULT);
shared variable protected_semaphore : t_protected_semaphore;
shared variable protected_broadcast_semaphore : t_protected_semaphore;
shared variable protected_response_semaphore : t_protected_semaphore;
shared variable shared_uvvm_status : t_uvvm_status;
signal global_trigger : std_logic := 'L';
signal global_barrier : std_logic := 'X';
-- -- ============================================================================
-- -- Initialisation and license
-- -- ============================================================================
-- procedure initialise_util(
-- constant dummy : in t_void
-- );
--
-- ============================================================================
-- File handling (that needs to use other utility methods)
-- ============================================================================
procedure check_file_open_status(
constant status : in file_open_status;
constant file_name : in string
);
procedure set_alert_file_name(
constant file_name : string := C_ALERT_FILE_NAME
);
-- msg_id is unused. This is a deprecated overload
procedure set_alert_file_name(
constant file_name : string := C_ALERT_FILE_NAME;
constant msg_id : t_msg_id
);
procedure set_log_file_name(
constant file_name : string := C_LOG_FILE_NAME
);
-- msg_id is unused. This is a deprecated overload
procedure set_log_file_name(
constant file_name : string := C_LOG_FILE_NAME;
constant msg_id : t_msg_id
);
-- ============================================================================
-- Log-related
-- ============================================================================
procedure log(
msg_id : t_msg_id;
msg : string;
scope : string := C_TB_SCOPE_DEFAULT;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
log_destination : t_log_destination := shared_default_log_destination;
log_file_name : string := C_LOG_FILE_NAME;
open_mode : file_open_kind := append_mode
);
procedure log_text_block(
msg_id : t_msg_id;
variable text_block : inout line;
formatting : t_log_format; -- FORMATTED or UNFORMATTED
msg_header : string := "";
scope : string := C_TB_SCOPE_DEFAULT;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
log_if_block_empty : t_log_if_block_empty := WRITE_HDR_IF_BLOCK_EMPTY;
log_destination : t_log_destination := shared_default_log_destination;
log_file_name : string := C_LOG_FILE_NAME;
open_mode : file_open_kind := append_mode
);
procedure write_to_file (
file_name : string;
open_mode : file_open_kind;
variable my_line : inout line
);
-- Enable and Disable do not have a Scope parameter as they are only allowed from main test sequencer
procedure enable_log_msg(
constant msg_id : t_msg_id;
variable msg_id_panel : inout t_msg_id_panel;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT;
constant quietness : t_quietness := NON_QUIET
);
procedure enable_log_msg(
msg_id : t_msg_id;
msg : string;
quietness : t_quietness := NON_QUIET
) ;
procedure enable_log_msg(
msg_id : t_msg_id;
quietness : t_quietness := NON_QUIET
) ;
procedure disable_log_msg(
constant msg_id : t_msg_id;
variable msg_id_panel : inout t_msg_id_panel;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT;
constant quietness : t_quietness := NON_QUIET
);
procedure disable_log_msg(
msg_id : t_msg_id;
msg : string;
quietness : t_quietness := NON_QUIET
);
procedure disable_log_msg(
msg_id : t_msg_id;
quietness : t_quietness := NON_QUIET
);
impure function is_log_msg_enabled(
msg_id : t_msg_id;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) return boolean;
procedure set_log_destination(
constant log_destination : t_log_destination;
constant quietness : t_quietness := NON_QUIET
);
-- ============================================================================
-- Alert-related
-- ============================================================================
procedure alert(
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
-- Dedicated alert-procedures all alert levels (less verbose - as 2 rather than 3 parameters...)
procedure note(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure tb_note(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure warning(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure tb_warning(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure manual_check(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure error(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure tb_error(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure failure(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure tb_failure(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure increment_expected_alerts(
constant alert_level : t_alert_level;
constant number : natural := 1;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure report_alert_counters(
constant order : in t_order
);
procedure report_alert_counters(
constant dummy : in t_void
);
procedure report_global_ctrl(
constant dummy : in t_void
);
procedure report_msg_id_panel(
constant dummy : in t_void
);
procedure set_alert_attention(
alert_level : t_alert_level;
attention : t_attention;
msg : string := ""
);
impure function get_alert_attention(
alert_level : t_alert_level
) return t_attention;
procedure set_alert_stop_limit(
alert_level : t_alert_level;
value : natural
);
impure function get_alert_stop_limit(
alert_level : t_alert_level
) return natural;
impure function get_alert_counter(
alert_level: t_alert_level;
attention : t_attention := REGARD
) return natural;
procedure increment_alert_counter(
alert_level: t_alert_level;
attention : t_attention := REGARD; -- regard, expect, ignore
number : natural := 1
);
-- ============================================================================
-- Deprecate message
-- ============================================================================
procedure deprecate(
caller_name : string;
constant msg : string := ""
);
-- ============================================================================
-- Non time consuming checks
-- ============================================================================
-- Matching if same width or only zeros in "extended width"
function matching_widths(
value1: std_logic_vector;
value2: std_logic_vector
) return boolean;
function matching_widths(
value1: unsigned;
value2: unsigned
) return boolean;
function matching_widths(
value1: signed;
value2: signed
) return boolean;
-- function version of check_value (with return value)
impure function check_value(
constant value : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean ;
impure function check_value(
constant value : boolean;
constant exp : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean ;
impure function check_value(
constant value : std_logic;
constant exp : std_logic;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean ;
impure function check_value(
constant value : std_logic;
constant exp : std_logic;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean ;
impure function check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
) return boolean ;
impure function check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
) return boolean ;
impure function check_value(
constant value : unsigned;
constant exp : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "unsigned"
) return boolean ;
impure function check_value(
constant value : signed;
constant exp : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "signed"
) return boolean ;
impure function check_value(
constant value : integer;
constant exp : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean ;
impure function check_value(
constant value : real;
constant exp : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean ;
impure function check_value(
constant value : time;
constant exp : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean ;
impure function check_value(
constant value : string;
constant exp : string;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean ;
-- procedure version of check_value (no return value)
procedure check_value(
constant value : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : boolean;
constant exp : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
);
procedure check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
);
procedure check_value(
constant value : unsigned;
constant exp : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "unsigned"
);
procedure check_value(
constant value : signed;
constant exp : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "signed"
);
procedure check_value(
constant value : std_logic;
constant exp : std_logic;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : std_logic;
constant exp : std_logic;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : integer;
constant exp : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : real;
constant exp : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : time;
constant exp : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
procedure check_value(
constant value : string;
constant exp : string;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
);
-- Check_value_in_range
impure function check_value_in_range (
constant value : integer;
constant min_value : integer;
constant max_value : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()";
constant value_type : string := "integer"
) return boolean;
impure function check_value_in_range (
constant value : unsigned;
constant min_value : unsigned;
constant max_value : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()";
constant value_type : string := "unsigned"
) return boolean;
impure function check_value_in_range (
constant value : signed;
constant min_value : signed;
constant max_value : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()";
constant value_type : string := "signed"
) return boolean;
impure function check_value_in_range (
constant value : time;
constant min_value : time;
constant max_value : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) return boolean;
impure function check_value_in_range (
constant value : real;
constant min_value : real;
constant max_value : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) return boolean;
-- Procedure overloads for check_value_in_range
procedure check_value_in_range (
constant value : integer;
constant min_value : integer;
constant max_value : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
);
procedure check_value_in_range (
constant value : unsigned;
constant min_value : unsigned;
constant max_value : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
);
procedure check_value_in_range (
constant value : signed;
constant min_value : signed;
constant max_value : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
);
procedure check_value_in_range (
constant value : time;
constant min_value : time;
constant max_value : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
);
procedure check_value_in_range (
constant value : real;
constant min_value : real;
constant max_value : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
);
-- Check_stable
procedure check_stable(
signal target : boolean;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "boolean"
);
procedure check_stable(
signal target : std_logic_vector;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "slv"
);
procedure check_stable(
signal target : unsigned;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "unsigned"
);
procedure check_stable(
signal target : signed;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "signed"
);
procedure check_stable(
signal target : std_logic;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "std_logic"
);
procedure check_stable(
signal target : integer;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "integer"
);
procedure check_stable(
signal target : real;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "real"
);
impure function random (
constant length : integer
) return std_logic_vector;
impure function random (
constant VOID : t_void
) return std_logic;
impure function random (
constant min_value : integer;
constant max_value : integer
) return integer;
impure function random (
constant min_value : real;
constant max_value : real
) return real;
impure function random (
constant min_value : time;
constant max_value : time
) return time;
procedure random (
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout std_logic_vector
);
procedure random (
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout std_logic
);
procedure random (
constant min_value : integer;
constant max_value : integer;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout integer
);
procedure random (
constant min_value : real;
constant max_value : real;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout real
);
procedure random (
constant min_value : time;
constant max_value : time;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout time
);
procedure randomize (
constant seed1 : positive;
constant seed2 : positive;
constant msg : string := "randomizing seeds";
constant scope : string := C_TB_SCOPE_DEFAULT
);
procedure randomise (
constant seed1 : positive;
constant seed2 : positive;
constant msg : string := "randomising seeds";
constant scope : string := C_TB_SCOPE_DEFAULT
);
-- Warning! This function should NOT be used outside the UVVM library.
-- Function is only included to support internal functionality.
-- The function can be removed without notification.
function matching_values(
value1: std_logic_vector;
value2: std_logic_vector
) return boolean;
-- ============================================================================
-- Time consuming checks
-- ============================================================================
procedure await_change(
signal target : boolean;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "boolean"
);
procedure await_change(
signal target : std_logic;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "std_logic"
);
procedure await_change(
signal target : std_logic_vector;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "slv"
);
procedure await_change(
signal target : unsigned;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "unsigned"
);
procedure await_change(
signal target : signed;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "signed"
);
procedure await_change(
signal target : integer;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "integer"
);
procedure await_change(
signal target : real;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "real"
);
procedure await_value (
signal target : boolean;
constant exp : boolean;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : std_logic;
constant exp : std_logic;
constant match_strictness : t_match_strictness;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : std_logic;
constant exp : std_logic;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : std_logic_vector;
constant exp : std_logic_vector;
constant match_strictness : t_match_strictness;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : std_logic_vector;
constant exp : std_logic_vector;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : unsigned;
constant exp : unsigned;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : signed;
constant exp : signed;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : integer;
constant exp : integer;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_value (
signal target : real;
constant exp : real;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : boolean;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : std_logic;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : std_logic_vector;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : unsigned;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : signed;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : integer;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure await_stable (
signal target : real;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_value : std_logic;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_value : std_logic;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_value : std_logic;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout boolean;
constant pulse_value : boolean;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout boolean;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout boolean;
constant pulse_value : boolean;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout boolean;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout boolean;
constant pulse_value : boolean;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout boolean;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_value : std_logic_vector;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_value : std_logic_vector;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_value : std_logic_vector;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure gen_pulse(
signal target : inout std_logic_vector;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
);
procedure clock_generator(
signal clock_signal : inout std_logic;
constant clock_period : in time;
constant clock_high_percentage : in natural range 1 to 99 := 50
);
-- Overloaded version with duty cycle in time
procedure clock_generator(
signal clock_signal : inout std_logic;
constant clock_period : in time;
constant clock_high_time : in time
);
-- Overloaded version with clock count
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_count : inout natural;
constant clock_period : in time;
constant clock_high_percentage : in natural range 1 to 99 := 50
);
-- Overloaded version with clock count and duty cycle in time
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_count : inout natural;
constant clock_period : in time;
constant clock_high_time : in time
);
-- Overloaded version with clock enable and clock name
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
constant clock_period : in time;
constant clock_name : in string;
constant clock_high_percentage : in natural range 1 to 99 := 50
);
-- Overloaded version with clock enable, clock name
-- and duty cycle in time.
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
constant clock_period : in time;
constant clock_name : in string;
constant clock_high_time : in time
);
-- Overloaded version with clock enable, clock name
-- and clock count
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
signal clock_count : out natural;
constant clock_period : in time;
constant clock_name : in string;
constant clock_high_percentage : in natural range 1 to 99 := 50
);
-- Overloaded version with clock enable, clock name,
-- clock count and duty cycle in time.
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
signal clock_count : out natural;
constant clock_period : in time;
constant clock_name : in string;
constant clock_high_time : in time
);
procedure deallocate_line_if_exists(
variable line_to_be_deallocated : inout line
);
-- ============================================================================
-- Synchronisation methods
-- ============================================================================
-- method to block a global flag with the name flag_name
procedure block_flag(
constant flag_name : in string;
constant msg : in string
);
-- method to unblock a global flag with the name flag_name
procedure unblock_flag(
constant flag_name : in string;
constant msg : in string;
signal trigger : inout std_logic
);
-- method to wait for the global flag with the name flag_name
procedure await_unblock_flag(
constant flag_name : in string;
constant timeout : in time;
constant msg : in string;
constant flag_returning : in t_flag_returning := KEEP_UNBLOCKED;
constant timeout_severity : in t_alert_level := ERROR
);
procedure await_barrier(
signal barrier_signal : inout std_logic;
constant timeout : in time;
constant msg : in string;
constant timeout_severity : in t_alert_level := ERROR
);
-------------------------------------------
-- await_semaphore_in_delta_cycles
-------------------------------------------
-- tries to lock the semaphore for C_NUM_SEMAPHORE_LOCK_TRIES in adaptations_pkg
procedure await_semaphore_in_delta_cycles(
variable semaphore : inout t_protected_semaphore
);
-------------------------------------------
-- release_semaphore
-------------------------------------------
-- releases the semaphore
procedure release_semaphore(
variable semaphore : inout t_protected_semaphore
);
end package methods_pkg;
--=================================================================================================
--=================================================================================================
--=================================================================================================
package body methods_pkg is
constant C_BURIED_SCOPE : string := "(Util buried)";
-- The following constants are not used. Report statements in the given functions allow elaboration time messages
constant C_BITVIS_LICENSE_INITIALISED : boolean := show_license(VOID);
constant C_BITVIS_LIBRARY_INFO_SHOWN : boolean := show_uvvm_utility_library_info(VOID);
constant C_BITVIS_LIBRARY_RELEASE_INFO_SHOWN : boolean := show_uvvm_utility_library_release_info(VOID);
-- ============================================================================
-- Initialisation and license
-- ============================================================================
-- -- Executed a single time ONLY
-- procedure pot_show_license(
-- constant dummy : in t_void
-- ) is
-- begin
-- if not shared_license_shown then
-- show_license(v_trial_license);
-- shared_license_shown := true;
-- end if;
-- end;
-- -- Executed a single time ONLY
-- procedure initialise_util(
-- constant dummy : in t_void
-- ) is
-- begin
-- set_log_file_name(C_LOG_FILE_NAME);
-- set_alert_file_name(C_ALERT_FILE_NAME);
-- shared_license_shown.set(1);
-- shared_initialised_util.set(true);
-- end;
procedure pot_initialise_util(
constant dummy : in t_void
) is
variable v_minimum_log_line_width : natural := 0;
begin
if not shared_initialised_util then
shared_initialised_util := true;
if not shared_log_file_name_is_set then
set_log_file_name(C_LOG_FILE_NAME);
end if;
if not shared_alert_file_name_is_set then
set_alert_file_name(C_ALERT_FILE_NAME);
end if;
if C_ENABLE_HIERARCHICAL_ALERTS then
initialize_hierarchy;
end if;
-- Check that all log widths are valid
v_minimum_log_line_width := v_minimum_log_line_width + C_LOG_PREFIX_WIDTH + C_LOG_TIME_WIDTH + 5; -- Add 5 for spaces
if not (C_SHOW_LOG_ID or C_SHOW_LOG_SCOPE) then
v_minimum_log_line_width := v_minimum_log_line_width + 10; -- Minimum length in order to wrap lines properly
else
if C_SHOW_LOG_ID then
v_minimum_log_line_width := v_minimum_log_line_width + C_LOG_MSG_ID_WIDTH;
end if;
if C_SHOW_LOG_SCOPE then
v_minimum_log_line_width := v_minimum_log_line_width + C_LOG_SCOPE_WIDTH;
end if;
end if;
bitvis_assert(C_LOG_LINE_WIDTH >= v_minimum_log_line_width, failure, "C_LOG_LINE_WIDTH is too low. Needs to higher than " & to_string(v_minimum_log_line_width) & ". ", C_SCOPE);
--show_license(VOID);
-- if C_SHOW_uvvm_utilITY_LIBRARY_INFO then
-- show_uvvm_utility_library_info(VOID);
-- end if;
-- if C_SHOW_uvvm_utilITY_LIBRARY_RELEASE_INFO then
-- show_uvvm_utility_library_release_info(VOID);
-- end if;
end if;
end;
procedure deallocate_line_if_exists(
variable line_to_be_deallocated : inout line
) is
begin
if line_to_be_deallocated /= NULL then
deallocate(line_to_be_deallocated);
end if;
end procedure deallocate_line_if_exists;
-- ============================================================================
-- File handling (that needs to use other utility methods)
-- ============================================================================
procedure check_file_open_status(
constant status : in file_open_status;
constant file_name : in string
) is
begin
case status is
when open_ok =>
null; --**** logmsg (if log is open for write)
when status_error =>
alert(tb_warning, "File: " & file_name & " is already open", "SCOPE_TBD");
when name_error =>
alert(tb_error, "Cannot create file: " & file_name, "SCOPE TBD");
when mode_error =>
alert(tb_error, "File: " & file_name & " exists, but cannot be opened in write mode", "SCOPE TBD");
end case;
end;
procedure set_alert_file_name(
constant file_name : string := C_ALERT_FILE_NAME
) is
variable v_file_open_status: file_open_status;
begin
if C_WARNING_ON_LOG_ALERT_FILE_RUNTIME_RENAME and shared_alert_file_name_is_set then
warning("alert file name already set. Setting new alert file " & file_name);
end if;
shared_alert_file_name_is_set := true;
file_close(ALERT_FILE);
file_open(v_file_open_status, ALERT_FILE, file_name, write_mode);
check_file_open_status(v_file_open_status, file_name);
if now > 0 ns then -- Do not show note if set at the very start.
-- NOTE: We should usually use log() instead of report. However,
-- in this case, there is an issue with log() initialising
-- the log file and therefore blocking subsequent set_log_file_name().
report "alert file name set: " & file_name;
end if;
end;
procedure set_alert_file_name(
constant file_name : string := C_ALERT_FILE_NAME;
constant msg_id : t_msg_id
) is
variable v_file_open_status: file_open_status;
begin
deprecate(get_procedure_name_from_instance_name(file_name'instance_name), "msg_id parameter is no longer in use. Please call this procedure without the msg_id parameter.");
set_alert_file_name(file_name);
end;
procedure set_log_file_name(
constant file_name : string := C_LOG_FILE_NAME
) is
variable v_file_open_status: file_open_status;
begin
if C_WARNING_ON_LOG_ALERT_FILE_RUNTIME_RENAME and shared_log_file_name_is_set then
warning("log file name already set. Setting new log file " & file_name);
end if;
shared_log_file_name_is_set := true;
file_close(LOG_FILE);
file_open(v_file_open_status, LOG_FILE, file_name, write_mode);
check_file_open_status(v_file_open_status, file_name);
if now > 0 ns then -- Do not show note if set at the very start.
-- NOTE: We should usually use log() instead of report. However,
-- in this case, there is an issue with log() initialising
-- the alert file and therefore blocking subsequent set_alert_file_name().
report "log file name set: " & file_name;
end if;
end;
procedure set_log_file_name(
constant file_name : string := C_LOG_FILE_NAME;
constant msg_id : t_msg_id
) is
begin
-- msg_id is no longer in use. However, can not call deprecate() since Util may not
-- have opened a log file yet. Attempting to call deprecate() when there is no open
-- log file will cause a fatal error. Leaving this alone with no message.
set_log_file_name(file_name);
end;
-- ============================================================================
-- Log-related
-- ============================================================================
impure function align_log_time(
value : time
) return string is
variable v_line : line;
variable v_value_width : natural;
variable v_result : string(1 to 50); -- sufficient for any relevant time value
variable v_result_width : natural;
variable v_delimeter_pos : natural;
variable v_time_number_width : natural;
variable v_time_width : natural;
variable v_num_initial_blanks : integer;
variable v_found_decimal_point : boolean;
begin
-- 1. Store normal write (to string) and note width
write(v_line, value, LEFT, 0, C_LOG_TIME_BASE); -- required as width is unknown
v_value_width := v_line'length;
v_result(1 to v_value_width) := v_line.all;
deallocate(v_line);
-- 2. Search for decimal point or space between number and unit
v_found_decimal_point := true; -- default
v_delimeter_pos := pos_of_leftmost('.', v_result(1 to v_value_width), 0);
if v_delimeter_pos = 0 then -- No decimal point found
v_found_decimal_point := false;
v_delimeter_pos := pos_of_leftmost(' ', v_result(1 to v_value_width), 0);
end if;
-- Potentially alert if time stamp is truncated.
if C_LOG_TIME_TRUNC_WARNING then
if not shared_warned_time_stamp_trunc then
if (C_LOG_TIME_DECIMALS < (v_value_width - 3 - v_delimeter_pos)) THEN
alert(TB_WARNING, "Time stamp has been truncated to " & to_string(C_LOG_TIME_DECIMALS) &
" decimal(s) in the next log message - settable in adaptations_pkg." &
" (Actual time stamp has more decimals than displayed) " &
"\nThis alert is shown once only.",
C_BURIED_SCOPE);
shared_warned_time_stamp_trunc := true;
end if;
end if;
end if;
-- 3. Derive Time number (integer or real)
if C_LOG_TIME_DECIMALS = 0 then
v_time_number_width := v_delimeter_pos - 1;
-- v_result as is
else -- i.e. a decimal value is required
if v_found_decimal_point then
v_result(v_value_width - 2 to v_result'right) := (others => '0'); -- Zero extend
else -- Shift right after integer part and add point
v_result(v_delimeter_pos + 1 to v_result'right) := v_result(v_delimeter_pos to v_result'right - 1);
v_result(v_delimeter_pos) := '.';
v_result(v_value_width - 1 to v_result'right) := (others => '0'); -- Zero extend
end if;
v_time_number_width := v_delimeter_pos + C_LOG_TIME_DECIMALS;
end if;
-- 4. Add time unit for full time specification
v_time_width := v_time_number_width + 3;
if C_LOG_TIME_BASE = ns then
v_result(v_time_number_width + 1 to v_time_width) := " ns";
else
v_result(v_time_number_width + 1 to v_time_width) := " ps";
end if;
-- 5. Prefix
v_num_initial_blanks := maximum(0, (C_LOG_TIME_WIDTH - v_time_width));
if v_num_initial_blanks > 0 then
v_result(v_num_initial_blanks + 1 to v_result'right) := v_result(1 to v_result'right - v_num_initial_blanks);
v_result(1 to v_num_initial_blanks) := fill_string(' ', v_num_initial_blanks);
v_result_width := C_LOG_TIME_WIDTH;
else
-- v_result as is
v_result_width := v_time_width;
end if;
return v_result(1 to v_result_width);
end function align_log_time;
-- Writes Line to a file without modifying the contents of the line
-- Not yet available in VHDL
procedure tee (
file file_handle : text;
variable my_line : inout line
) is
variable v_line : line;
begin
write (v_line, my_line.all);
writeline(file_handle, v_line);
end procedure tee;
-- Open, append/write to and close file. Also deallocates contents of the line
procedure write_to_file (
file_name : string;
open_mode : file_open_kind;
variable my_line : inout line
) is
file v_specified_file_pointer : text;
begin
file_open(v_specified_file_pointer, file_name, open_mode);
writeline(v_specified_file_pointer, my_line);
file_close(v_specified_file_pointer);
end procedure write_to_file;
procedure log(
msg_id : t_msg_id;
msg : string;
scope : string := C_TB_SCOPE_DEFAULT;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel; -- compatible with old code
log_destination : t_log_destination := shared_default_log_destination;
log_file_name : string := C_LOG_FILE_NAME;
open_mode : file_open_kind := append_mode
) is
variable v_msg : line;
variable v_msg_indent : line;
variable v_msg_indent_width : natural;
variable v_info : line;
variable v_info_final : line;
variable v_log_msg_id : string(1 to C_LOG_MSG_ID_WIDTH);
variable v_log_scope : string(1 to C_LOG_SCOPE_WIDTH);
variable v_log_pre_msg_width : natural;
begin
-- Check if message ID is enabled
if (msg_id_panel(msg_id) = ENABLED) then
pot_initialise_util(VOID); -- Only executed the first time called
-- Prepare strings for msg_id and scope
v_log_msg_id := to_upper(justify(to_string(msg_id), LEFT, C_LOG_MSG_ID_WIDTH, KEEP_LEADING_SPACE, ALLOW_TRUNCATE));
if (scope = "") then
v_log_scope := justify("(non scoped)", LEFT, C_LOG_SCOPE_WIDTH, KEEP_LEADING_SPACE, ALLOW_TRUNCATE);
else
v_log_scope := justify(to_string(scope), LEFT, C_LOG_SCOPE_WIDTH, KEEP_LEADING_SPACE, ALLOW_TRUNCATE);
end if;
-- Handle actual log info line
-- First write all fields preceeding the actual message - in order to measure their width
-- (Prefix is taken care of later)
write(v_info,
return_string_if_true(v_log_msg_id, C_SHOW_LOG_ID) & -- Optional
" " & align_log_time(now) & " " &
return_string_if_true(v_log_scope, C_SHOW_LOG_SCOPE) & " "); -- Optional
v_log_pre_msg_width := v_info'length; -- Width of string preceeding the actual message
-- Handle \r as potential initial open line
if msg'length > 1 then
if C_USE_BACKSLASH_R_AS_LF and (msg(1 to 2) = "\r") then
write(v_info_final, LF); -- Start transcript with an empty line
write(v_msg, remove_initial_chars(msg, 2));
else
write(v_msg, msg);
end if;
end if;
-- Handle dedicated ID indentation.
write(v_msg_indent, to_string(C_MSG_ID_INDENT(msg_id)));
v_msg_indent_width := v_msg_indent'length;
write(v_info, v_msg_indent.all);
deallocate_line_if_exists(v_msg_indent);
-- Then add the message it self (after replacing \n with LF
if msg'length > 1 then
write(v_info, to_string(replace_backslash_n_with_lf(v_msg.all)));
end if;
deallocate_line_if_exists(v_msg);
if not C_SINGLE_LINE_LOG then
-- Modify and align info-string if additional lines are required (after wrapping lines)
wrap_lines(v_info, 1, v_log_pre_msg_width + v_msg_indent_width + 1, C_LOG_LINE_WIDTH-C_LOG_PREFIX_WIDTH);
else
-- Remove line feed character if
-- single line log/alert enabled
replace(v_info, LF, ' ');
end if;
-- Handle potential log header by including info-lines inside the log header format and update of waveview header.
if (msg_id = ID_LOG_HDR) then
write(v_info_final, LF & LF);
-- also update the Log header string
shared_current_log_hdr.normal := justify(msg, LEFT, C_LOG_HDR_FOR_WAVEVIEW_WIDTH, KEEP_LEADING_SPACE, ALLOW_TRUNCATE);
shared_log_hdr_for_waveview := justify(msg, LEFT, C_LOG_HDR_FOR_WAVEVIEW_WIDTH, KEEP_LEADING_SPACE, ALLOW_TRUNCATE);
elsif (msg_id = ID_LOG_HDR_LARGE) then
write(v_info_final, LF & LF);
shared_current_log_hdr.large := justify(msg, LEFT, C_LOG_HDR_FOR_WAVEVIEW_WIDTH, KEEP_LEADING_SPACE, ALLOW_TRUNCATE);
write(v_info_final, fill_string('=', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)) & LF);
elsif (msg_id = ID_LOG_HDR_XL) then
write(v_info_final, LF & LF);
shared_current_log_hdr.xl := justify(msg, LEFT, C_LOG_HDR_FOR_WAVEVIEW_WIDTH, KEEP_LEADING_SPACE, ALLOW_TRUNCATE);
write(v_info_final, LF & fill_string('#', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH))& LF & LF);
end if;
write(v_info_final, v_info.all); -- include actual info
deallocate_line_if_exists(v_info);
-- Handle rest of potential log header
if (msg_id = ID_LOG_HDR) then
write(v_info_final, LF & fill_string('-', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)));
elsif (msg_id = ID_LOG_HDR_LARGE) then
write(v_info_final, LF & fill_string('=', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)));
elsif (msg_id = ID_LOG_HDR_XL) then
write(v_info_final, LF & LF & fill_string('#', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)) & LF & LF);
end if;
-- Add prefix to all lines
prefix_lines(v_info_final);
-- Write the info string to the target file
if log_file_name = "" and (log_destination = LOG_ONLY or log_destination = CONSOLE_AND_LOG) then
-- Output file specified, but file name was invalid.
alert(TB_ERROR, "log called with log_destination " & to_upper(to_string(log_destination)) & ", but log file name was empty.");
else
case log_destination is
when CONSOLE_AND_LOG =>
tee(OUTPUT, v_info_final); -- write to transcript, while keeping the line contents
-- write to file
if log_file_name = C_LOG_FILE_NAME then
-- If the log file is the default file, it is not necessary to open and close it again
writeline(LOG_FILE, v_info_final);
else
-- If the log file is a custom file name, the file will have to be opened.
write_to_file(log_file_name, open_mode, v_info_final);
end if;
when CONSOLE_ONLY =>
writeline(OUTPUT, v_info_final); -- Write to console and deallocate line
when LOG_ONLY =>
if log_file_name = C_LOG_FILE_NAME then
-- If the log file is the default file, it is not necessary to open and close it again
writeline(LOG_FILE, v_info_final);
else
-- If the log file is a custom file name, the file will have to be opened.
write_to_file(log_file_name, open_mode, v_info_final);
end if;
end case;
end if;
end if;
end;
-- Logging for multi line text. Also deallocates the text_block, for consistency.
procedure log_text_block(
msg_id : t_msg_id;
variable text_block : inout line;
formatting : t_log_format; -- FORMATTED or UNFORMATTED
msg_header : string := "";
scope : string := C_TB_SCOPE_DEFAULT;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
log_if_block_empty : t_log_if_block_empty := WRITE_HDR_IF_BLOCK_EMPTY;
log_destination : t_log_destination := shared_default_log_destination;
log_file_name : string := C_LOG_FILE_NAME;
open_mode : file_open_kind := append_mode
) is
variable v_text_block_empty_note : string(1 to 26) := "Note: Text block was empty";
variable v_header_line : line;
variable v_log_body : line;
variable v_text_block_is_empty : boolean;
begin
if ((log_file_name = "") and ((log_destination = CONSOLE_AND_LOG) or (log_destination = LOG_ONLY))) then
alert(TB_ERROR, "log_text_block called with log_destination " & to_upper(to_string(log_destination)) & ", but log file name was empty.");
-- Check if message ID is enabled
elsif (msg_id_panel(msg_id) = ENABLED) then
pot_initialise_util(VOID); -- Only executed the first time called
v_text_block_is_empty := (text_block = NULL);
if(formatting = UNFORMATTED) then
if(not v_text_block_is_empty) then
-- Write the info string to the target file without any header, footer or indentation
case log_destination is
when CONSOLE_AND_LOG =>
tee(OUTPUT, text_block); -- Write to console, but keep text_block
-- Write to log and deallocate text_block. Open specified file if not open.
if log_file_name = C_LOG_FILE_NAME then
writeline(LOG_FILE, text_block);
else
write_to_file(log_file_name, open_mode, text_block);
end if;
when CONSOLE_ONLY =>
writeline(OUTPUT, text_block); -- Write to console and deallocate text_block
when LOG_ONLY =>
-- Write to log and deallocate text_block. Open specified file if not open.
if log_file_name = C_LOG_FILE_NAME then
writeline(LOG_FILE, text_block);
else
write_to_file(log_file_name, open_mode, text_block);
end if;
end case;
end if;
elsif not (v_text_block_is_empty and (log_if_block_empty = SKIP_LOG_IF_BLOCK_EMPTY)) then
-- Add and print header
write(v_header_line, LF & LF & fill_string('*', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)));
prefix_lines(v_header_line);
-- Add header underline, body and footer
write(v_log_body, fill_string('-', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)) & LF);
if v_text_block_is_empty then
if log_if_block_empty = NOTIFY_IF_BLOCK_EMPTY then
write(v_log_body, v_text_block_empty_note); -- Notify that the text block was empty
end if;
else
write(v_log_body, text_block.all); -- include input text
end if;
write(v_log_body, LF & fill_string('*', (C_LOG_LINE_WIDTH - C_LOG_PREFIX_WIDTH)) & LF);
prefix_lines(v_log_body);
case log_destination is
when CONSOLE_AND_LOG =>
-- Write header to console
tee(OUTPUT, v_header_line);
-- Write header to file, and open/close if not default log file
if log_file_name = C_LOG_FILE_NAME then
writeline(LOG_FILE, v_header_line);
else
write_to_file(log_file_name, open_mode, v_header_line);
end if;
-- Write header message to specified destination
log(msg_id, msg_header, scope, msg_id_panel, CONSOLE_AND_LOG, log_file_name, append_mode);
-- Write log body to console
tee(OUTPUT, v_log_body);
-- Write log body to specified file
if log_file_name = C_LOG_FILE_NAME then
writeline(LOG_FILE, v_log_body);
else
write_to_file(log_file_name, append_mode, v_log_body);
end if;
when CONSOLE_ONLY =>
-- Write to console and deallocate all lines
writeline(OUTPUT, v_header_line);
log(msg_id, msg_header, scope, msg_id_panel, CONSOLE_ONLY);
writeline(OUTPUT, v_log_body);
when LOG_ONLY =>
-- Write to log and deallocate text_block. Open specified file if not open.
if log_file_name = C_LOG_FILE_NAME then
writeline(LOG_FILE, v_header_line);
log(msg_id, msg_header, scope, msg_id_panel, LOG_ONLY);
writeline(LOG_FILE, v_log_body);
else
write_to_file(log_file_name, open_mode, v_header_line);
log(msg_id, msg_header, scope, msg_id_panel, LOG_ONLY, log_file_name, append_mode);
write_to_file(log_file_name, append_mode, v_log_body);
end if;
end case;
-- Deallocate text block to give writeline()-like behaviour
-- for formatted output
deallocate(text_block);
end if;
end if;
end;
procedure enable_log_msg(
constant msg_id : t_msg_id;
variable msg_id_panel : inout t_msg_id_panel;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT;
constant quietness : t_quietness := NON_QUIET
) is
begin
case msg_id is
when ID_NEVER =>
null; -- Shall not be possible to enable
tb_warning("enable_log_msg() ignored for " & to_upper(to_string(msg_id)) & " (not allowed). " & add_msg_delimiter(msg), scope);
when ALL_MESSAGES =>
for i in t_msg_id'left to t_msg_id'right loop
msg_id_panel(i) := ENABLED;
end loop;
msg_id_panel(ID_NEVER) := DISABLED;
msg_id_panel(ID_BITVIS_DEBUG) := DISABLED;
if quietness = NON_QUIET then
log(ID_LOG_MSG_CTRL, "enable_log_msg(" & to_upper(to_string(msg_id)) & "). " & add_msg_delimiter(msg), scope);
end if;
when others =>
msg_id_panel(msg_id) := ENABLED;
if quietness = NON_QUIET then
log(ID_LOG_MSG_CTRL, "enable_log_msg(" & to_upper(to_string(msg_id)) & "). " & add_msg_delimiter(msg), scope);
end if;
end case;
end;
procedure enable_log_msg(
msg_id : t_msg_id;
msg : string;
quietness : t_quietness := NON_QUIET
) is
begin
enable_log_msg(msg_id, shared_msg_id_panel, msg, C_TB_SCOPE_DEFAULT, quietness);
end;
procedure enable_log_msg(
msg_id : t_msg_id;
quietness : t_quietness := NON_QUIET
) is
begin
enable_log_msg(msg_id, shared_msg_id_panel, "", C_TB_SCOPE_DEFAULT, quietness);
end;
procedure disable_log_msg(
constant msg_id : t_msg_id;
variable msg_id_panel : inout t_msg_id_panel;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT;
constant quietness : t_quietness := NON_QUIET
) is
begin
case msg_id is
when ALL_MESSAGES =>
if quietness = NON_QUIET then
log(ID_LOG_MSG_CTRL, "disable_log_msg(" & to_upper(to_string(msg_id)) & "). " & add_msg_delimiter(msg), scope);
end if;
for i in t_msg_id'left to t_msg_id'right loop
msg_id_panel(i) := DISABLED;
end loop;
when others =>
msg_id_panel(msg_id) := DISABLED;
if quietness = NON_QUIET then
log(ID_LOG_MSG_CTRL, "disable_log_msg(" & to_upper(to_string(msg_id)) & "). " & add_msg_delimiter(msg), scope);
end if;
end case;
end;
procedure disable_log_msg(
msg_id : t_msg_id;
msg : string;
quietness : t_quietness := NON_QUIET
) is
begin
disable_log_msg(msg_id, shared_msg_id_panel, msg, C_TB_SCOPE_DEFAULT, quietness);
end;
procedure disable_log_msg(
msg_id : t_msg_id;
quietness : t_quietness := NON_QUIET
) is
begin
disable_log_msg(msg_id, shared_msg_id_panel, "", C_TB_SCOPE_DEFAULT, quietness);
end;
impure function is_log_msg_enabled(
msg_id : t_msg_id;
msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) return boolean is
begin
if msg_id_panel(msg_id) = ENABLED then
return true;
else
return false;
end if;
end;
procedure set_log_destination(
constant log_destination : t_log_destination;
constant quietness : t_quietness := NON_QUIET
) is
begin
if quietness = NON_QUIET then
log(ID_LOG_MSG_CTRL, "Changing log destination to " & to_string(log_destination) & ". Was " & to_string(shared_default_log_destination) & ". ", C_TB_SCOPE_DEFAULT);
end if;
shared_default_log_destination := log_destination;
end;
-- ============================================================================
-- Alert-related
-- ============================================================================
-- Shared variable for all the alert counters for different attention
shared variable protected_alert_attention_counters : t_protected_alert_attention_counters;
procedure alert(
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
variable v_msg : line; -- msg after pot. replacement of \n
variable v_info : line;
constant C_ATTENTION : t_attention := get_alert_attention(alert_level);
begin
if alert_level /= NO_ALERT then
pot_initialise_util(VOID); -- Only executed the first time called
if C_ENABLE_HIERARCHICAL_ALERTS then
-- Call the hierarchical alert function
hierarchical_alert(alert_level, to_string(msg), to_string(scope), C_ATTENTION);
else
-- Perform the non-hierarchical alert function
write(v_msg, replace_backslash_n_with_lf(to_string(msg)));
-- 1. Increase relevant alert counter. Exit if ignore is set for this alert type.
if get_alert_attention(alert_level) = IGNORE then
-- protected_alert_counters.increment(alert_level, IGNORE);
increment_alert_counter(alert_level, IGNORE);
else
--protected_alert_counters.increment(alert_level, REGARD);
increment_alert_counter(alert_level, REGARD);
-- 2. Write first part of alert message
-- Serious alerts need more attention - thus more space and lines
if (alert_level > MANUAL_CHECK) then
write(v_info, LF & fill_string('=', C_LOG_INFO_WIDTH));
end if;
write(v_info, LF & "*** ");
-- 3. Remove line feed character (LF)
-- if single line alert enabled.
if not C_SINGLE_LINE_ALERT then
write(v_info, to_upper(to_string(alert_level)) & " #" & to_string(get_alert_counter(alert_level)) & " ***" & LF &
justify( to_string(now, C_LOG_TIME_BASE), RIGHT, C_LOG_TIME_WIDTH) & " " & to_string(scope) & LF &
wrap_lines(v_msg.all, C_LOG_TIME_WIDTH + 4, C_LOG_TIME_WIDTH + 4, C_LOG_INFO_WIDTH));
else
replace(v_msg, LF, ' ');
write(v_info, to_upper(to_string(alert_level)) & " #" & to_string(get_alert_counter(alert_level)) & " ***" &
justify( to_string(now, C_LOG_TIME_BASE), RIGHT, C_LOG_TIME_WIDTH) & " " & to_string(scope) &
" " & v_msg.all);
end if;
deallocate_line_if_exists(v_msg);
-- 4. Write stop message if stop-limit is reached for number of this alert
if (get_alert_stop_limit(alert_level) /= 0) and
(get_alert_counter(alert_level) >= get_alert_stop_limit(alert_level)) then
write(v_info, LF & LF & "Simulator has been paused as requested after " &
to_string(get_alert_counter(alert_level)) & " " &
to_upper(to_string(alert_level)) & LF);
if (alert_level = MANUAL_CHECK) then
write(v_info, "Carry out above check." & LF &
"Then continue simulation from within simulator." & LF);
else
write(v_info, string'("*** To find the root cause of this alert, " &
"step out the HDL calling stack in your simulator. ***" & LF &
"*** For example, step out until you reach the call from the test sequencer. ***"));
end if;
end if;
-- 5. Write last part of alert message
if (alert_level > MANUAL_CHECK) then
write(v_info, LF & fill_string('=', C_LOG_INFO_WIDTH) & LF & LF);
else
write(v_info, LF);
end if;
prefix_lines(v_info);
tee(OUTPUT, v_info);
tee(ALERT_FILE, v_info);
writeline(LOG_FILE, v_info);
-- 6. Stop simulation if stop-limit is reached for number of this alert
if (get_alert_stop_limit(alert_level) /= 0) then
if (get_alert_counter(alert_level) >= get_alert_stop_limit(alert_level)) then
assert false
report "This single Failure line has been provoked to stop the simulation. See alert-message above"
severity failure;
end if;
end if;
end if;
end if;
end if;
end;
-- Dedicated alert-procedures all alert levels (less verbose - as 2 rather than 3 parameters...)
procedure note(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(note, msg, scope);
end;
procedure tb_note(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(tb_note, msg, scope);
end;
procedure warning(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(warning, msg, scope);
end;
procedure tb_warning(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(tb_warning, msg, scope);
end;
procedure manual_check(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(manual_check, msg, scope);
end;
procedure error(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(error, msg, scope);
end;
procedure tb_error(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(tb_error, msg, scope);
end;
procedure failure(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(failure, msg, scope);
end;
procedure tb_failure(
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
alert(tb_failure, msg, scope);
end;
procedure increment_expected_alerts(
constant alert_level : t_alert_level;
constant number : natural := 1;
constant msg : string := "";
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
if alert_level = NO_ALERT then
alert(TB_WARNING, "increment_expected_alerts not allowed for alert_level NO_ALERT. " & add_msg_delimiter(msg), scope);
else
if not C_ENABLE_HIERARCHICAL_ALERTS then
increment_alert_counter(alert_level, EXPECT, number);
log(ID_UTIL_SETUP, "incremented expected " & to_upper(to_string(alert_level)) & "s by " & to_string(number) & ". " & add_msg_delimiter(msg), scope);
else
increment_expected_alerts(C_BASE_HIERARCHY_LEVEL, alert_level, number);
end if;
end if;
end;
-- Arguments:
-- - order = FINAL : print out Simulation Success/Fail
procedure report_alert_counters(
constant order : in t_order
) is
begin
pot_initialise_util(VOID); -- Only executed the first time called
if not C_ENABLE_HIERARCHICAL_ALERTS then
protected_alert_attention_counters.to_string(order);
else
print_hierarchical_log(order);
end if;
end;
-- This version (with the t_void argument) is kept for backwards compatibility
procedure report_alert_counters(
constant dummy : in t_void
) is
begin
report_alert_counters(FINAL); -- Default when calling this old method is order=FINAL
end;
procedure report_global_ctrl(
constant dummy : in t_void
) is
constant prefix : string := C_LOG_PREFIX & " ";
variable v_line : line;
begin
pot_initialise_util(VOID); -- Only executed the first time called
write(v_line,
LF &
fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
"*** REPORT OF GLOBAL CTRL ***" & LF &
fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
" IGNORE STOP_LIMIT " & LF);
for i in NOTE to t_alert_level'right loop
write(v_line, " " & to_upper(to_string(i, 13, LEFT)) & ": "); -- Severity
write(v_line, to_string(get_alert_attention(i), 7, RIGHT) & " "); -- column 1
write(v_line, to_string(integer'(get_alert_stop_limit(i)), 6, RIGHT, KEEP_LEADING_SPACE) & " " & LF); -- column 2
end loop;
write(v_line, fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF);
wrap_lines(v_line, 1, 1, C_LOG_LINE_WIDTH-prefix'length);
prefix_lines(v_line, prefix);
-- Write the info string to the target file
tee(OUTPUT, v_line);
writeline(LOG_FILE, v_line);
end;
procedure report_msg_id_panel(
constant dummy : in t_void
) is
constant prefix : string := C_LOG_PREFIX & " ";
variable v_line : line;
begin
pot_initialise_util(VOID); -- Only executed the first time called
write(v_line,
LF &
fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
"*** REPORT OF MSG ID PANEL ***" & LF &
fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF &
" " & justify("ID", LEFT, C_LOG_MSG_ID_WIDTH) & " Status" & LF &
" " & fill_string('-', C_LOG_MSG_ID_WIDTH) & " ------" & LF);
for i in t_msg_id'left to t_msg_id'right loop
if ((i /= ALL_MESSAGES) and ((i /= NO_ID) and (i /= ID_NEVER))) then -- report all but ID_NEVER, NO_ID and ALL_MESSAGES
write(v_line, " " & to_upper(to_string(i, C_LOG_MSG_ID_WIDTH+5, LEFT)) & ": "); -- MSG_ID
write(v_line,to_upper(to_string(shared_msg_id_panel(i))) & " " & LF); -- Enabled/disabled
end if;
end loop;
write(v_line, fill_string('-', (C_LOG_LINE_WIDTH - prefix'length)) & LF);
wrap_lines(v_line, 1, 1, C_LOG_LINE_WIDTH-prefix'length);
prefix_lines(v_line, prefix);
-- Write the info string to the target file
tee(OUTPUT, v_line);
writeline(LOG_FILE, v_line);
end;
procedure set_alert_attention(
alert_level : t_alert_level;
attention : t_attention;
msg : string := ""
) is
begin
if alert_level = NO_ALERT then
tb_warning("set_alert_attention not allowed for alert_level NO_ALERT (always IGNORE).");
else
check_value(attention = IGNORE or attention = REGARD, TB_WARNING,
"set_alert_attention only supported for IGNORE and REGARD", C_BURIED_SCOPE, ID_NEVER);
shared_alert_attention(alert_level) := attention;
log(ID_ALERT_CTRL, "set_alert_attention(" & to_upper(to_string(alert_level)) & ", " & to_string(attention) & "). " & add_msg_delimiter(msg));
end if;
end;
impure function get_alert_attention(
alert_level : t_alert_level
) return t_attention is
begin
if alert_level = NO_ALERT then
return IGNORE;
else
return shared_alert_attention(alert_level);
end if;
end;
procedure set_alert_stop_limit(
alert_level : t_alert_level;
value : natural
) is
begin
if alert_level = NO_ALERT then
tb_warning("set_alert_stop_limit not allowed for alert_level NO_ALERT (stop limit always 0).");
else
if not C_ENABLE_HIERARCHICAL_ALERTS then
shared_stop_limit(alert_level) := value;
-- Evaluate new stop limit in case it is less than or equal to the current alert counter for this alert level
-- If that is the case, a new alert with the same alert level shall be triggered.
if (get_alert_stop_limit(alert_level) /= 0) and
(get_alert_counter(alert_level) >= get_alert_stop_limit(alert_level)) then
alert(alert_level, "Alert stop limit for " & to_upper(to_string(alert_level)) & " set to " & to_string(value) &
", which is lower than the current " & to_upper(to_string(alert_level)) & " count (" & to_string(get_alert_counter(alert_level)) & ").");
end if;
else
-- If hierarchical alerts enabled, update top level
-- alert stop limit.
set_hierarchical_alert_top_level_stop_limit(alert_level, value);
end if;
end if;
end;
impure function get_alert_stop_limit(
alert_level : t_alert_level
) return natural is
begin
if alert_level = NO_ALERT then
return 0;
else
if not C_ENABLE_HIERARCHICAL_ALERTS then
return shared_stop_limit(alert_level);
else
return get_hierarchical_alert_top_level_stop_limit(alert_level);
end if;
end if;
end;
impure function get_alert_counter(
alert_level: t_alert_level;
attention : t_attention := REGARD
) return natural is
begin
return protected_alert_attention_counters.get(alert_level, attention);
end;
procedure increment_alert_counter(
alert_level : t_alert_level;
attention : t_attention := REGARD; -- regard, expect, ignore
number : natural := 1
) is
type alert_array is array (1 to 6) of t_alert_level;
constant alert_check_array : alert_array := (WARNING, TB_WARNING, ERROR, TB_ERROR, FAILURE, TB_FAILURE);
alias warning_and_worse is shared_uvvm_status.no_unexpected_simulation_warnings_or_worse;
alias error_and_worse is shared_uvvm_status.no_unexpected_simulation_errors_or_worse;
begin
protected_alert_attention_counters.increment(alert_level, attention, number);
-- Update simulation status
if (attention = REGARD) or (attention = EXPECT) then
if (alert_level /= NO_ALERT) and (alert_level /= NOTE) and (alert_level /= TB_NOTE) and (alert_level /= MANUAL_CHECK) then
warning_and_worse := 1; -- default
error_and_worse := 1; -- default
-- Compare expected and current allerts
for i in 1 to alert_check_array'high loop
if (get_alert_counter(alert_check_array(i), REGARD) > get_alert_counter(alert_check_array(i), EXPECT)) then
-- warning and worse
warning_and_worse := 0;
-- error and worse
if not(alert_check_array(i) = WARNING) and not(alert_check_array(i) = TB_WARNING) then
error_and_worse := 0;
end if;
end if;
end loop;
end if;
end if;
end;
-- ============================================================================
-- Deprecation message
-- ============================================================================
procedure deprecate(
caller_name : string;
constant msg : string := ""
) is
variable v_found : boolean;
begin
v_found := false;
if C_DEPRECATE_SETTING /= NO_DEPRECATE then -- only perform if deprecation enabled
l_find_caller_name_in_list:
for i in deprecated_subprogram_list'range loop
if deprecated_subprogram_list(i) = justify(caller_name, RIGHT, 100) then
v_found := true;
exit l_find_caller_name_in_list;
end if;
end loop;
if v_found then
-- Has already been printed.
if C_DEPRECATE_SETTING = ALWAYS_DEPRECATE then
log(ID_UTIL_SETUP, "Sub-program " & caller_name & " is outdated and has been replaced by another sub-program." & LF & msg);
else -- C_DEPRECATE_SETTING = DEPRECATE_ONCE
null;
end if;
else
-- Has not been printed yet.
l_insert_caller_name_in_first_available:
for i in deprecated_subprogram_list'range loop
if deprecated_subprogram_list(i) = justify("", RIGHT, 100) then
deprecated_subprogram_list(i) := justify(caller_name, RIGHT, 100);
exit l_insert_caller_name_in_first_available;
end if;
end loop;
log(ID_UTIL_SETUP, "Sub-program " & caller_name & " is outdated and has been replaced by another sub-program." & LF & msg);
end if;
end if;
end;
-- ============================================================================
-- Non time consuming checks
-- ============================================================================
-- NOTE: Index in range N downto 0, with -1 meaning not found
function idx_leftmost_p1_in_p2(
target : std_logic;
vector : std_logic_vector
) return integer is
alias a_vector : std_logic_vector(vector'length - 1 downto 0) is vector;
constant result_if_not_found : integer := -1; -- To indicate not found
begin
bitvis_assert(vector'length > 0, ERROR, "idx_leftmost_p1_in_p2()", "String input is empty");
for i in a_vector'left downto a_vector'right loop
if (a_vector(i) = target) then
return i;
end if;
end loop;
return result_if_not_found;
end;
-- Matching if same width or only zeros in "extended width"
function matching_widths(
value1: std_logic_vector;
value2: std_logic_vector
) return boolean is
-- Normalize vectors to (N downto 0)
alias a_value1: std_logic_vector(value1'length - 1 downto 0) is value1;
alias a_value2: std_logic_vector(value2'length - 1 downto 0) is value2;
begin
if (a_value1'left >= maximum( idx_leftmost_p1_in_p2('1', a_value2), 0)) and
(a_value2'left >= maximum( idx_leftmost_p1_in_p2('1', a_value1), 0)) then
return true;
else
return false;
end if;
end;
function matching_widths(
value1: unsigned;
value2: unsigned
) return boolean is
begin
return matching_widths(std_logic_vector(value1), std_logic_vector(value2));
end;
function matching_widths(
value1: signed;
value2: signed
) return boolean is
begin
return matching_widths(std_logic_vector(value1), std_logic_vector(value2));
end;
-- Compare values, but ignore any leading zero's at higher indexes than v_min_length-1.
function matching_values(
value1: std_logic_vector;
value2: std_logic_vector
) return boolean is
-- Normalize vectors to (N downto 0)
alias a_value1 : std_logic_vector(value1'length - 1 downto 0) is value1;
alias a_value2 : std_logic_vector(value2'length - 1 downto 0) is value2;
variable v_min_length : natural := minimum(a_value1'length, a_value2'length);
variable v_match : boolean := true; -- as default prior to checking
begin
if matching_widths(a_value1, a_value2) then
if not std_match( a_value1(v_min_length-1 downto 0), a_value2(v_min_length-1 downto 0) ) then
v_match := false;
end if;
else
v_match := false;
end if;
return v_match;
end;
function matching_values(
value1: unsigned;
value2: unsigned
) return boolean is
begin
return matching_values(std_logic_vector(value1),std_logic_vector(value2));
end;
function matching_values(
value1: signed;
value2: signed
) return boolean is
begin
return matching_values(std_logic_vector(value1),std_logic_vector(value2));
end;
-- Function check_value,
-- returning 'true' if OK
impure function check_value(
constant value : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
begin
if value then
log(msg_id, caller_name & " => OK, for boolean true. " & add_msg_delimiter(msg), scope, msg_id_panel);
else
alert(alert_level, caller_name & " => Failed. Boolean was false. " & add_msg_delimiter(msg), scope);
end if;
return value;
end;
impure function check_value(
constant value : boolean;
constant exp : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
constant v_value_str : string := to_string(value);
constant v_exp_str : string := to_string(exp);
begin
if value = exp then
log(msg_id, caller_name & " => OK, for boolean " & v_value_str & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. Boolean was " & v_value_str & ". Expected " & v_exp_str & ". " & LF & msg, scope);
return false;
end if;
end;
impure function check_value(
constant value : std_logic;
constant exp : std_logic;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
constant value_type : string := "std_logic";
constant v_value_str : string := to_string(value);
constant v_exp_str : string := to_string(exp);
begin
if std_match(value, exp) then
if value = exp then
log(msg_id, caller_name & " => OK, for " & value_type & " '" & v_value_str & "'. " & add_msg_delimiter(msg), scope, msg_id_panel);
else
if match_strictness = MATCH_STD then
log(msg_id, caller_name & " => OK, for " & value_type & " '" & v_value_str & "' (exp: '" & v_exp_str & "'). " & add_msg_delimiter(msg), scope, msg_id_panel);
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was '" & v_value_str & "'. Expected '" & v_exp_str & "'" & LF & msg, scope);
return false;
end if;
end if;
return true;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was '" & v_value_str & "'. Expected '" & v_exp_str & "'" & LF & msg, scope);
return false;
end if;
end;
impure function check_value(
constant value : std_logic;
constant exp : std_logic;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
constant value_type : string := "std_logic";
constant v_value_str : string := to_string(value);
constant v_exp_str : string := to_string(exp);
begin
return check_value(value, exp, MATCH_STD, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
impure function check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
) return boolean is
-- Normalise vectors to (N downto 0)
alias a_value : std_logic_vector(value'length - 1 downto 0) is value;
alias a_exp : std_logic_vector(exp'length - 1 downto 0) is exp;
constant v_value_str : string := to_string(a_value, radix, format,INCL_RADIX);
constant v_exp_str : string := to_string(a_exp, radix, format,INCL_RADIX);
variable v_check_ok : boolean := true; -- as default prior to checking
begin
-- AS_IS format has been deprecated and will be removed in the near future
if format = AS_IS then
deprecate(get_procedure_name_from_instance_name(value'instance_name), "format 'AS_IS' has been deprecated. Use KEEP_LEADING_0.");
end if;
v_check_ok := matching_values(a_value, a_exp);
if v_check_ok then
if v_value_str = v_exp_str then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & "'. " & add_msg_delimiter(msg), scope, msg_id_panel);
else
-- H,L or - is present in v_exp_str
if match_strictness = MATCH_STD then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & "' (exp: " & v_exp_str & "'). " & add_msg_delimiter(msg),
scope, msg_id_panel);
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & "'. Expected " & v_exp_str & "'" & LF & msg, scope);
end if;
end if;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & "'. Expected " & v_exp_str & "'" & LF & msg, scope);
end if;
return v_check_ok;
end;
impure function check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
) return boolean is
-- Normalise vectors to (N downto 0)
alias a_value : std_logic_vector(value'length - 1 downto 0) is value;
alias a_exp : std_logic_vector(exp'length - 1 downto 0) is exp;
constant v_value_str : string := to_string(a_value, radix, format);
constant v_exp_str : string := to_string(a_exp, radix, format);
variable v_check_ok : boolean := true; -- as default prior to checking
begin
return check_value(value, exp, MATCH_STD, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
impure function check_value(
constant value : unsigned;
constant exp : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "unsigned"
) return boolean is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(std_logic_vector(value), std_logic_vector(exp), alert_level, msg, scope,
radix, format, msg_id, msg_id_panel, caller_name, value_type);
return v_check_ok;
end;
impure function check_value(
constant value : signed;
constant exp : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "signed"
) return boolean is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(std_logic_vector(value), std_logic_vector(exp), alert_level, msg, scope,
radix, format, msg_id, msg_id_panel, caller_name, value_type);
return v_check_ok;
end;
impure function check_value(
constant value : integer;
constant exp : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
constant value_type : string := "int";
constant v_value_str : string := to_string(value);
constant v_exp_str : string := to_string(exp);
begin
if value = exp then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected " & v_exp_str & LF & msg, scope);
return false;
end if;
end;
impure function check_value(
constant value : real;
constant exp : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
constant value_type : string := "real";
constant v_value_str : string := to_string(value);
constant v_exp_str : string := to_string(exp);
begin
if value = exp then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected " & v_exp_str & LF & msg, scope);
return false;
end if;
end;
impure function check_value(
constant value : time;
constant exp : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
constant value_type : string := "time";
constant v_value_str : string := to_string(value);
constant v_exp_str : string := to_string(exp);
begin
if value = exp then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected " & v_exp_str & LF & msg, scope);
return false;
end if;
end;
impure function check_value(
constant value : string;
constant exp : string;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) return boolean is
constant value_type : string := "string";
begin
if value = exp then
log(msg_id, caller_name & " => OK, for " & value_type & " '" & value & "'. " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was '" & value & "'. Expected '" & exp & "'" & LF & msg, scope);
return false;
end if;
end;
----------------------------------------------------------------------
-- Overloads for check_value functions,
-- to allow for no return value
----------------------------------------------------------------------
procedure check_value(
constant value : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : boolean;
constant exp : boolean;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : std_logic;
constant exp : std_logic;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, match_strictness, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : std_logic;
constant exp : std_logic;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, MATCH_STD, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant match_strictness : t_match_strictness;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, match_strictness, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_value(
constant value : std_logic_vector;
constant exp : std_logic_vector;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "slv"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_value(
constant value : unsigned;
constant exp : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "unsigned"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_value(
constant value : signed;
constant exp : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()";
constant value_type : string := "signed"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, radix, format, msg_id, msg_id_panel, caller_name, value_type);
end;
procedure check_value(
constant value : integer;
constant exp : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : real;
constant exp : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : time;
constant exp : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value(
constant value : string;
constant exp : string;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value(value, exp, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
------------------------------------------------------------------------
-- check_value_in_range
------------------------------------------------------------------------
impure function check_value_in_range (
constant value : integer;
constant min_value : integer;
constant max_value : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()";
constant value_type : string := "integer"
) return boolean is
constant v_value_str : string := to_string(value);
constant v_min_value_str : string := to_string(min_value);
constant v_max_value_str : string := to_string(max_value);
variable v_check_ok : boolean;
begin
-- Sanity check
check_value(max_value >= min_value, TB_ERROR, scope,
" => min_value (" & v_min_value_str & ") must be less than max_value("& v_max_value_str & ")" & LF & msg, ID_NEVER, msg_id_panel, caller_name);
if (value >= min_value and value <= max_value) then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected between " & v_min_value_str & " and " & v_max_value_str & LF & msg, scope);
return false;
end if;
end;
impure function check_value_in_range (
constant value : unsigned;
constant min_value : unsigned;
constant max_value : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()";
constant value_type : string := "unsigned"
) return boolean is
constant v_value_str : string := to_string(value);
constant v_min_value_str : string := to_string(min_value);
constant v_max_value_str : string := to_string(max_value);
begin
-- Sanity check
check_value(max_value >= min_value, TB_ERROR, scope,
" => min_value (" & v_min_value_str & ") must be less than max_value("& v_max_value_str & ")" & LF & msg, ID_NEVER, msg_id_panel, caller_name);
if (value >= min_value and value <= max_value) then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected between " & v_min_value_str & " and " & v_max_value_str & LF & msg, scope);
return false;
end if;
end;
impure function check_value_in_range (
constant value : signed;
constant min_value : signed;
constant max_value : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()";
constant value_type : string := "signed"
) return boolean is
constant v_value_str : string := to_string(value);
constant v_min_value_str : string := to_string(min_value);
constant v_max_value_str : string := to_string(max_value);
begin
-- Sanity check
check_value(max_value >= min_value, TB_ERROR, scope,
" => min_value (" & v_min_value_str & ") must be less than max_value("& v_max_value_str & ")" & LF & msg, ID_NEVER, msg_id_panel, caller_name);
if (value >= min_value and value <= max_value) then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected between " & v_min_value_str & " and " & v_max_value_str & LF & msg, scope);
return false;
end if;
end;
impure function check_value_in_range (
constant value : time;
constant min_value : time;
constant max_value : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) return boolean is
constant value_type : string := "time";
constant v_value_str : string := to_string(value);
constant v_min_value_str : string := to_string(min_value);
constant v_max_value_str : string := to_string(max_value);
variable v_check_ok : boolean;
begin
-- Sanity check
check_value(max_value >= min_value, TB_ERROR, scope,
" => min_value (" & v_min_value_str & ") must be less than max_value("& v_max_value_str & ")" & LF & msg, ID_NEVER, msg_id_panel, caller_name);
if (value >= min_value and value <= max_value) then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected between " & v_min_value_str & " and " & v_max_value_str & LF & msg, scope);
return false;
end if;
end;
impure function check_value_in_range (
constant value : real;
constant min_value : real;
constant max_value : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) return boolean is
constant value_type : string := "real";
constant v_value_str : string := to_string(value);
constant v_min_value_str : string := to_string(min_value);
constant v_max_value_str : string := to_string(max_value);
variable v_check_ok : boolean;
begin
-- Sanity check
check_value(max_value >= min_value, TB_ERROR,
" => min_value (" & v_min_value_str & ") must be less than max_value("& v_max_value_str & ")" & LF & msg, scope,
ID_NEVER, msg_id_panel, caller_name);
if (value >= min_value and value <= max_value) then
log(msg_id, caller_name & " => OK, for " & value_type & " " & v_value_str & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
return true;
else
alert(alert_level, caller_name & " => Failed. " & value_type & " Was " & v_value_str & ". Expected between " & v_min_value_str & " and " & v_max_value_str & LF & msg, scope);
return false;
end if;
end;
--------------------------------------------------------------------------------
-- check_value_in_range procedures :
-- Call the corresponding function and discard the return value
--------------------------------------------------------------------------------
procedure check_value_in_range (
constant value : integer;
constant min_value : integer;
constant max_value : integer;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value_in_range (
constant value : unsigned;
constant min_value : unsigned;
constant max_value : unsigned;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value_in_range (
constant value : signed;
constant min_value : signed;
constant max_value : signed;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value_in_range (
constant value : time;
constant min_value : time;
constant max_value : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
procedure check_value_in_range (
constant value : real;
constant min_value : real;
constant max_value : real;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_value_in_range()"
) is
variable v_check_ok : boolean;
begin
v_check_ok := check_value_in_range(value, min_value, max_value, alert_level, msg, scope, msg_id, msg_id_panel, caller_name);
end;
--------------------------------------------------------------------------------
-- check_stable
--------------------------------------------------------------------------------
procedure check_stable(
signal target : boolean;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "boolean"
) is
constant value_string : string := to_string(target);
constant last_value_string : string := to_string(target'last_value);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
if (last_change >= stable_req) then
log(msg_id, caller_name & " => OK. Stable at " & value_string & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
alert(alert_level, caller_name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
procedure check_stable(
signal target : std_logic_vector;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "slv"
) is
constant value_string : string := 'x' & to_string(target, HEX);
constant last_value_string : string := 'x' & to_string(target'last_value, HEX);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
if (last_change >= stable_req) then
log(msg_id, caller_name & " => OK. Stable at " & value_string & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
alert(alert_level, caller_name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
procedure check_stable(
signal target : unsigned;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "unsigned"
) is
constant value_string : string := 'x' & to_string(target, HEX);
constant last_value_string : string := 'x' & to_string(target'last_value, HEX);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
if (last_change >= stable_req) then
log(msg_id, caller_name & " => OK. Stable at " & value_string & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
alert(alert_level, caller_name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
procedure check_stable(
signal target : signed;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "signed"
) is
constant value_string : string := 'x' & to_string(target, HEX);
constant last_value_string : string := 'x' & to_string(target'last_value, HEX);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
if (last_change >= stable_req) then
log(msg_id, caller_name & " => OK. Stable at " & value_string & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
alert(alert_level, caller_name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
procedure check_stable(
signal target : std_logic;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "std_logic"
) is
constant value_string : string := to_string(target);
constant last_value_string : string := to_string(target'last_value);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
if (last_change >= stable_req) then
log(msg_id, caller_name & " => OK. Stable at " & value_string & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
alert(alert_level, caller_name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
procedure check_stable(
signal target : integer;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "integer"
) is
constant value_string : string := to_string(target);
constant last_value_string : string := to_string(target'last_value);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
if (last_change >= stable_req) then
log(msg_id, caller_name & " => OK." & value_string & " stable at " & value_string & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
alert(alert_level, caller_name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
procedure check_stable(
signal target : real;
constant stable_req : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "check_stable()";
constant value_type : string := "real"
) is
constant value_string : string := to_string(target);
constant last_value_string : string := to_string(target'last_value);
constant last_change : time := target'last_event;
constant last_change_string : string := to_string(last_change, ns);
begin
if (last_change >= stable_req) then
log(msg_id, caller_name & " => OK." & value_string & " stable at " & value_string & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
alert(alert_level, caller_name & " => Failed. Switched from " & last_value_string & " to " &
value_string & " " & last_change_string & " ago. Expected stable for " & to_string(stable_req) & LF & msg, scope);
end if;
end;
-- check_time_window is used to check if a given condition occurred between
-- min_time and max_time
-- Usage: wait for requested condition until max_time is reached, then call check_time_window().
-- The input 'success' is needed to distinguish between the following cases:
-- - the signal reached success condition at max_time,
-- - max_time was reached with no success condition
procedure check_time_window(
constant success : boolean; -- F.ex target'event, or target=exp
constant elapsed_time : time;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant name : string;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
-- Sanity check
check_value(max_time >= min_time, TB_ERROR, name & " => min_time must be less than max_time." & LF & msg, scope, ID_NEVER, msg_id_panel, name);
if elapsed_time < min_time then
alert(alert_level, name & " => Failed. Condition occurred too early, after " &
to_string(elapsed_time, C_LOG_TIME_BASE) & ". " & add_msg_delimiter(msg), scope);
elsif success then
log(msg_id, name & " => OK. Condition occurred after " &
to_string(elapsed_time, C_LOG_TIME_BASE) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else -- max_time reached with no success
alert(alert_level, name & " => Failed. Timed out after " &
to_string(max_time, C_LOG_TIME_BASE) & ". " & add_msg_delimiter(msg), scope);
end if;
end;
----------------------------------------------------------------------------
-- Random functions
----------------------------------------------------------------------------
-- Return a random std_logic_vector, using overload for the integer version of random()
impure function random (
constant length : integer
) return std_logic_vector is
variable random_vec : std_logic_vector(length-1 downto 0);
begin
-- Iterate through each bit and randomly set to 0 or 1
for i in 0 to length-1 loop
random_vec(i downto i) := std_logic_vector(to_unsigned(random(0,1), 1));
end loop;
return random_vec;
end;
-- Return a random std_logic, using overload for the SLV version of random()
impure function random (
constant VOID : t_void
) return std_logic is
variable v_random_bit : std_logic_vector(0 downto 0);
begin
-- randomly set bit to 0 or 1
v_random_bit := random(1);
return v_random_bit(0);
end;
-- Return a random integer between min_value and max_value
-- Use global seeds
impure function random (
constant min_value : integer;
constant max_value : integer
) return integer is
variable v_rand_scaled : integer;
variable v_seed1 : positive := shared_seed1;
variable v_seed2 : positive := shared_seed2;
begin
random(min_value, max_value, v_seed1, v_seed2, v_rand_scaled);
-- Write back seeds
shared_seed1 := v_seed1;
shared_seed2 := v_seed2;
return v_rand_scaled;
end;
-- Return a random real between min_value and max_value
-- Use global seeds
impure function random (
constant min_value : real;
constant max_value : real
) return real is
variable v_rand_scaled : real;
variable v_seed1 : positive := shared_seed1;
variable v_seed2 : positive := shared_seed2;
begin
random(min_value, max_value, v_seed1, v_seed2, v_rand_scaled);
-- Write back seeds
shared_seed1 := v_seed1;
shared_seed2 := v_seed2;
return v_rand_scaled;
end;
-- Return a random time between min time and max time, using overload for the integer version of random()
impure function random (
constant min_value : time;
constant max_value : time
) return time is
begin
return random(min_value/1 ns, max_value/1 ns) * 1 ns;
end;
--
-- Procedure versions of random(), where seeds can be specified
--
-- Set target to a random SLV, using overload for the integer version of random().
procedure random (
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout std_logic_vector
) is
variable v_length : integer := v_target'length;
begin
-- Iterate through each bit and randomly set to 0 or 1
for i in 0 to v_length-1 loop
v_target(i downto i) := std_logic_vector(to_unsigned(random(0,1),1));
end loop;
end;
-- Set target to a random SL, using overload for the integer version of random().
procedure random (
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout std_logic
) is
variable v_random_slv : std_logic_vector(0 downto 0);
begin
v_random_slv := std_logic_vector(to_unsigned(random(0,1),1));
v_target := v_random_slv(0);
end;
-- Set target to a random integer between min_value and max_value
procedure random (
constant min_value : integer;
constant max_value : integer;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout integer
) is
variable v_rand : real;
begin
-- Random real-number value in range 0 to 1.0
uniform(v_seed1, v_seed2, v_rand);
-- Scale to a random integer between min_value and max_value
v_target := min_value + integer(trunc(v_rand*real(1+max_value-min_value)));
end;
-- Set target to a random integer between min_value and max_value
procedure random (
constant min_value : real;
constant max_value : real;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout real
) is
variable v_rand : real;
begin
-- Random real-number value in range 0 to 1.0
uniform(v_seed1, v_seed2, v_rand);
-- Scale to a random integer between min_value and max_value
v_target := min_value + v_rand*(max_value-min_value);
end;
-- Set target to a random integer between min_value and max_value
procedure random (
constant min_value : time;
constant max_value : time;
variable v_seed1 : inout positive;
variable v_seed2 : inout positive;
variable v_target : inout time
) is
variable v_rand : real;
variable v_rand_int : integer;
begin
-- Random real-number value in range 0 to 1.0
uniform(v_seed1, v_seed2, v_rand);
-- Scale to a random integer between min_value and max_value
v_rand_int := min_value/1 ns + integer(trunc(v_rand*real(1 + max_value/1 ns - min_value / 1 ns)));
v_target := v_rand_int * 1 ns;
end;
-- Set global seeds
procedure randomize (
constant seed1 : positive;
constant seed2 : positive;
constant msg : string := "randomizing seeds";
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
log(ID_UTIL_SETUP, "Setting global seeds to " & to_string(seed1) & ", " & to_string(seed2), scope);
shared_seed1 := seed1;
shared_seed2 := seed2;
end;
-- Set global seeds
procedure randomise (
constant seed1 : positive;
constant seed2 : positive;
constant msg : string := "randomising seeds";
constant scope : string := C_TB_SCOPE_DEFAULT
) is
begin
deprecate(get_procedure_name_from_instance_name(seed1'instance_name), "Use randomize().");
log(ID_UTIL_SETUP, "Setting global seeds to " & to_string(seed1) & ", " & to_string(seed2), scope);
shared_seed1 := seed1;
shared_seed2 := seed2;
end;
-- ============================================================================
-- Time consuming checks
-- ============================================================================
--------------------------------------------------------------------------------
-- await_change
-- A signal change is required, but may happen already after 1 delta if min_time = 0 ns
--------------------------------------------------------------------------------
procedure await_change(
signal target : boolean;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "boolean"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " &
to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_change(
signal target : std_logic;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "std_logic"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " &
to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_change(
signal target : std_logic_vector;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "slv"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " &
to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_change(
signal target : unsigned;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "unsigned"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " &
to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
-- Note that overloading by casting target to slv without creating a new signal doesn't work
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_change(
signal target : signed;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "signed"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " &
to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_change(
signal target : integer;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "integer"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_change(
signal target : real;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel: t_msg_id_panel := shared_msg_id_panel;
constant value_type : string := "real"
) is
constant name : string := "await_change(" & value_type & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
constant start_time : time := now;
begin
wait on target for max_time;
check_time_window(target'event, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
--------------------------------------------------------------------------------
-- await_value
--------------------------------------------------------------------------------
-- Potential improvements
-- - Adding an option that the signal must last for more than one delta cycle
-- or a specified time
-- - Adding an "AS_IS" option that does not allow the signal to change to other values
-- before it changes to the expected value
--
-- The input signal is allowed to change to other values before ending up on the expected value,
-- as long as it changes to the expected value within the time window (min_time to max_time).
-- Wait for target = expected or timeout after max_time.
-- Then check if (and when) the value changed to the expected
procedure await_value (
signal target : boolean;
constant exp : boolean;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "boolean";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
if (target /= exp) then
wait until (target = exp) for max_time;
end if;
check_time_window((target = exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_value (
signal target : std_logic;
constant exp : std_logic;
constant match_strictness : t_match_strictness;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "std_logic";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
variable success : boolean := false;
begin
success := false;
if match_strictness = MATCH_EXACT then
if (target /= exp) then
wait until (target = exp) for max_time;
end if;
if (target = exp) then
success := true;
end if;
else
if ((exp = '1' or exp = 'H') and (target /= '1') and (target /= 'H')) then
wait until (target = '1' or target = 'H') for max_time;
elsif ((exp = '0' or exp = 'L') and (target /= '0') and (target /= 'L')) then
wait until (target = '0' or target = 'L') for max_time;
end if;
if ((exp = '1' or exp = 'H') and (target = '1' or target = 'H')) then
success := true;
elsif ((exp = '0' or exp = 'L') and (target = '0' or target = 'L')) then
success := true;
end if;
end if;
check_time_window(success, now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_value (
signal target : std_logic;
constant exp : std_logic;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "std_logic";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
await_value(target, exp, MATCH_EXACT, min_time, max_time, alert_level, msg, scope, msg_id, msg_id_panel);
end;
procedure await_value (
signal target : std_logic_vector;
constant exp : std_logic_vector;
constant match_strictness : t_match_strictness;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "slv";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp, radix, format, INCL_RADIX);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
-- AS_IS format has been deprecated and will be removed in the near future
if format = AS_IS then
deprecate(get_procedure_name_from_instance_name(target'instance_name), "format 'AS_IS' has been deprecated. Use KEEP_LEADING_0.");
end if;
if matching_widths(target, exp) then
if match_strictness = MATCH_STD then
if not matching_values(target, exp) then
wait until matching_values(target, exp) for max_time;
end if;
check_time_window(matching_values(target, exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
else
if (target /= exp) then
wait until (target = exp) for max_time;
end if;
check_time_window((target = exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end if;
else
alert(alert_level, name & " => Failed. Widths did not match. " & add_msg_delimiter(msg), scope);
end if;
end;
procedure await_value (
signal target : std_logic_vector;
constant exp : std_logic_vector;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "slv";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp, radix, format, INCL_RADIX);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
await_value(target, exp, MATCH_STD, min_time, max_time, alert_level, msg, scope, radix, format, msg_id, msg_id_panel);
end;
procedure await_value (
signal target : unsigned;
constant exp : unsigned;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "unsigned";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp, radix, format, INCL_RADIX);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
-- AS_IS format has been deprecated and will be removed in the near future
if format = AS_IS then
deprecate(get_procedure_name_from_instance_name(target'instance_name), "format 'AS_IS' has been deprecated. Use KEEP_LEADING_0.");
end if;
if matching_widths(target, exp) then
if not matching_values(target, exp) then
wait until matching_values(target, exp) for max_time;
end if;
check_time_window(matching_values(target, exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
else
alert(alert_level, name & " => Failed. Widths did not match. " & add_msg_delimiter(msg), scope);
end if;
end;
procedure await_value (
signal target : signed;
constant exp : signed;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant radix : t_radix := HEX_BIN_IF_INVALID;
constant format : t_format_zeros := SKIP_LEADING_0;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "signed";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp, radix, format, INCL_RADIX);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
-- AS_IS format has been deprecated and will be removed in the near future
if format = AS_IS then
deprecate(get_procedure_name_from_instance_name(target'instance_name), "format 'AS_IS' has been deprecated. Use KEEP_LEADING_0.");
end if;
if matching_widths(target, exp) then
if not matching_values(target, exp) then
wait until matching_values(target, exp) for max_time;
end if;
check_time_window(matching_values(target, exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
else
alert(alert_level, name & " => Failed. Widths did not match. " & add_msg_delimiter(msg), scope);
end if;
end;
procedure await_value (
signal target : integer;
constant exp : integer;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "integer";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
if (target /= exp) then
wait until (target = exp) for max_time;
end if;
check_time_window((target = exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
procedure await_value (
signal target : real;
constant exp : real;
constant min_time : time;
constant max_time : time;
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "real";
constant start_time : time := now;
constant v_exp_str : string := to_string(exp);
constant name : string := "await_value(" & value_type & " " & v_exp_str & ", " &
to_string(min_time, ns) & ", " & to_string(max_time, ns) & ")";
begin
if (target /= exp) then
wait until (target = exp) for max_time;
end if;
check_time_window((target = exp), now-start_time, min_time, max_time, alert_level, name, msg, scope, msg_id, msg_id_panel);
end;
-- Helper procedure:
-- Convert time from 'FROM_LAST_EVENT' to 'FROM_NOW'
procedure await_stable_calc_time (
constant target_last_event : time;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
variable stable_req_from_now : inout time; -- Calculated stable requirement from now
variable timeout_from_await_stable_entry : inout time; -- Calculated timeout from procedure entry
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "await_stable_calc_time()";
variable stable_req_met : inout boolean -- When true, the stable requirement is satisfied
) is
begin
stable_req_met := false;
-- Convert stable_req so that it points to "time_from_now"
if stable_req_from = FROM_NOW then
stable_req_from_now := stable_req;
elsif stable_req_from = FROM_LAST_EVENT then
-- Signal has already been stable for target'last_event,
-- so we can subtract this in the FROM_NOW version.
stable_req_from_now := stable_req - target_last_event;
else
alert(tb_error, caller_name & " => Unknown stable_req_from. " & add_msg_delimiter(msg), scope);
end if;
-- Convert timeout so that it points to "time_from_now"
if timeout_from = FROM_NOW then
timeout_from_await_stable_entry := timeout;
elsif timeout_from = FROM_LAST_EVENT then
timeout_from_await_stable_entry := timeout - target_last_event;
else
alert(tb_error, caller_name & " => Unknown timeout_from. " & add_msg_delimiter(msg), scope);
end if;
-- Check if requirement is already OK
if (stable_req_from_now <= 0 ns) then
log(msg_id, caller_name & " => OK. Condition occurred immediately. " & add_msg_delimiter(msg), scope, msg_id_panel);
stable_req_met := true;
end if;
-- Check if it is impossible to achieve stable_req before timeout
if (stable_req_from_now > timeout_from_await_stable_entry) then
alert(alert_level, caller_name & " => Failed immediately: Stable for stable_req = " & to_string(stable_req_from_now, ns) &
" is not possible before timeout = " & to_string(timeout_from_await_stable_entry, ns) &
". " & add_msg_delimiter(msg), scope);
stable_req_met := true;
end if;
end;
-- Helper procedure:
procedure await_stable_checks (
constant start_time : time; -- Time at await_stable() procedure entry
constant stable_req : time; -- Minimum stable requirement
variable stable_req_from_now : inout time; -- Minimum stable requirement from now
variable timeout_from_await_stable_entry : inout time; -- Timeout value converted to FROM_NOW
constant time_since_last_event : time; -- Time since previous event
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel;
constant caller_name : string := "await_stable_checks()";
variable stable_req_met : inout boolean -- When true, the stable requirement is satisfied
) is
variable v_time_left : time; -- Remaining time until timeout
variable v_elapsed_time : time := 0 ns; -- Time since procedure entry
begin
stable_req_met := false;
v_elapsed_time := now - start_time;
v_time_left := timeout_from_await_stable_entry - v_elapsed_time;
-- Check if target has been stable for stable_req
if (time_since_last_event >= stable_req_from_now) then
log(msg_id, caller_name & " => OK. Condition occurred after " &
to_string(v_elapsed_time, C_LOG_TIME_BASE) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
stable_req_met := true;
end if;
--
-- Prepare for the next iteration in the loop in await_stable() procedure:
--
if not stable_req_met then
-- Now that an event has occurred, the stable requirement is stable_req from now (regardless of stable_req_from)
stable_req_from_now := stable_req;
-- Check if it is impossible to achieve stable_req before timeout
if (stable_req_from_now > v_time_left) then
alert(alert_level, caller_name & " => Failed. After " & to_string(v_elapsed_time, C_LOG_TIME_BASE) &
", stable for stable_req = " & to_string(stable_req_from_now, ns) &
" is not possible before timeout = " & to_string(timeout_from_await_stable_entry, ns) &
"(time since last event = " & to_string(time_since_last_event, ns) &
". " & add_msg_delimiter(msg), scope);
stable_req_met := true;
end if;
end if;
end;
-- Wait until the target signal has been stable for at least 'stable_req'
-- Report an error if this does not occurr within the time specified by 'timeout'.
-- Note : 'Stable' refers to that the signal has not had an event (i.e. not changed value).
-- Description of arguments:
-- stable_req_from = FROM_NOW : Target must be stable 'stable_req' from now
-- stable_req_from = FROM_LAST_EVENT : Target must be stable 'stable_req' from the last event of target.
-- timeout_from = FROM_NOW : The timeout argument is given in time from now
-- timeout_from = FROM_LAST_EVENT : The timeout argument is given in time the last event of target.
procedure await_stable (
signal target : boolean;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "boolean";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occurr
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
-- Note that the waiting for target'event can't be called from overloaded procedures where 'target' is a different type.
-- Instead, the common code is put in helper procedures
procedure await_stable (
signal target : std_logic;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "std_logic";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occurr
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
procedure await_stable (
signal target : std_logic_vector;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "std_logic_vector";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occurr
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
procedure await_stable (
signal target : unsigned;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "unsigned";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occurr
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
procedure await_stable (
signal target : signed;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "signed";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occurr
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
procedure await_stable (
signal target : integer;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "integer";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occur
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
procedure await_stable (
signal target : real;
constant stable_req : time; -- Minimum stable requirement
constant stable_req_from : t_from_point_in_time; -- Which point in time stable_req starts
constant timeout : time; -- Timeout if stable_req not achieved
constant timeout_from : t_from_point_in_time; -- Which point in time the timeout starts
constant alert_level : t_alert_level;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_POS_ACK;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant value_type : string := "real";
constant start_time : time := now;
constant name : string := "await_stable(" & value_type & ", " & to_string(stable_req, ns) &
", " & to_string(timeout, ns) & ")";
variable v_stable_req_from_now : time; -- Stable_req relative to now.
variable v_timeout_from_proc_entry : time; -- Timeout relative to time of procedure entry
variable v_stable_req_met : boolean := false; -- When true, the procedure is done and has logged a conclusion.
begin
-- Use a helper procedure to simplify overloading
await_stable_calc_time(
target_last_event => target'last_event,
stable_req => stable_req,
stable_req_from => stable_req_from,
timeout => timeout,
timeout_from => timeout_from,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
-- Start waiting for target'event or stable_req time, unless :
-- - stable_req already achieved, or
-- - it is already too late to be stable for stable_req before timeout will occur
while not v_stable_req_met loop
wait until target'event for v_stable_req_from_now;
-- Use a helper procedure to simplify overloading
await_stable_checks (
start_time => start_time,
stable_req => stable_req,
stable_req_from_now => v_stable_req_from_now,
timeout_from_await_stable_entry => v_timeout_from_proc_entry,
time_since_last_event => target'last_event,
alert_level => alert_level,
msg => msg,
scope => scope,
msg_id => msg_id,
msg_id_panel => msg_id_panel,
caller_name => name,
stable_req_met => v_stable_req_met);
end loop;
end;
-----------------------------------------------------------------------------------
-- gen_pulse(sl)
-- Generate a pulse on a std_logic for a certain amount of time
--
-- If blocking_mode = BLOCKING : Procedure waits until the pulse is done before returning to the caller.
-- If blocking_mode = NON_BLOCKING : Procedure starts the pulse, schedules the end of the pulse, then returns to the caller immediately.
--
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_value : std_logic;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant init_value : std_logic := target;
begin
log(msg_id, "Pulse to " & to_string(pulse_value) &
" for " & to_string(pulse_duration) & ". " & add_msg_delimiter(msg), scope);
check_value(target /= pulse_value, TB_ERROR, "gen_pulse: target was already " & to_string(pulse_value) & ". " & add_msg_delimiter(msg), scope, ID_NEVER);
target <= pulse_value; -- Start pulse
if (blocking_mode = BLOCKING) then
wait for pulse_duration;
target <= init_value;
else
target <= transport init_value after pulse_duration;
end if;
end;
-- Overload to allow excluding the pulse_value argument:
-- Make pulse_value = '1' by default
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
gen_pulse(target, '1', pulse_duration, blocking_mode, msg, scope, msg_id, msg_id_panel); -- Blocking mode by default
end;
-- Overload to allow excluding the blocking_mode and pulse_value arguments:
-- Make blocking_mode = BLOCKING and pulse_value = '1' by default
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
gen_pulse(target, '1', pulse_duration, BLOCKING, msg, scope, msg_id, msg_id_panel); -- Blocking mode by default
end;
-- Overload to allow excluding the blocking_mode argument:
-- Make blocking_mode = BLOCKING by default
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_value : std_logic;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
gen_pulse(target, pulse_value, pulse_duration, BLOCKING, msg, scope, msg_id, msg_id_panel); -- Blocking mode by default
end;
-- gen_pulse(sl)
-- Generate a pulse on a std_logic for a certain number of clock cycles
procedure gen_pulse(
signal target : inout std_logic;
constant pulse_value : std_logic;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant init_value : std_logic := target;
begin
log(msg_id, "Pulse to " & to_string(pulse_value) &
" for " & to_string(num_periods) & " clk cycles. " & add_msg_delimiter(msg), scope);
if (num_periods > 0) then
wait until falling_edge(clock_signal);
check_value(target /= pulse_value, TB_ERROR, "gen_pulse: target was already " & to_string(pulse_value) & ". " & add_msg_delimiter(msg), scope, ID_NEVER);
target <= pulse_value;
for i in 1 to num_periods loop
wait until falling_edge(clock_signal);
end loop;
else -- Pulse for one delta cycle only
check_value(target /= pulse_value, TB_ERROR, "gen_pulse: target was already " & to_string(pulse_value) & ". " & add_msg_delimiter(msg), scope, ID_NEVER);
target <= pulse_value;
wait for 0 ns;
end if;
target <= init_value;
end;
-- Overload to allow excluding the pulse_value argument:
-- Make pulse_value = '1' by default
procedure gen_pulse(
signal target : inout std_logic;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
gen_pulse(target, '1', clock_signal, num_periods, msg, scope, msg_id, msg_id_panel); -- pulse_value = '1' by default
end;
procedure gen_pulse(
signal target : inout boolean;
constant pulse_value : boolean;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant init_value : boolean := target;
begin
log(msg_id, "Pulse to " & to_string(pulse_value) &
" for " & to_string(pulse_duration) & ". " & add_msg_delimiter(msg), scope);
check_value(target /= pulse_value, TB_ERROR, "gen_pulse: target was already " & to_string(pulse_value) & ". " & add_msg_delimiter(msg), scope, ID_NEVER);
target <= pulse_value; -- Start pulse
if (blocking_mode = BLOCKING) then
wait for pulse_duration;
target <= init_value;
else
target <= transport init_value after pulse_duration;
end if;
end;
-- Overload to allow excluding the pulse_value argument:
-- Make pulse_value = true by default
procedure gen_pulse(
signal target : inout boolean;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
gen_pulse(target, true, pulse_duration, blocking_mode, msg, scope, msg_id, msg_id_panel); -- Blocking mode by default
end;
-- Overload to allow excluding the blocking_mode and pulse_value arguments:
-- Make blocking_mode = BLOCKING and pulse_value = true by default
procedure gen_pulse(
signal target : inout boolean;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
gen_pulse(target, true, pulse_duration, BLOCKING, msg, scope, msg_id, msg_id_panel); -- Blocking mode by default
end;
-- Overload to allow excluding the blocking_mode argument:
-- Make blocking_mode = BLOCKING by default
procedure gen_pulse(
signal target : inout boolean;
constant pulse_value : boolean;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
gen_pulse(target, pulse_value, pulse_duration, BLOCKING, msg, scope, msg_id, msg_id_panel); -- Blocking mode by default
end;
-- Generate a pulse on a boolean for a certain number of clock cycles
procedure gen_pulse(
signal target : inout boolean;
constant pulse_value : boolean;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant init_value : boolean := target;
begin
log(msg_id, "Pulse to " & to_string(pulse_value) &
" for " & to_string(num_periods) & " clk cycles. " & add_msg_delimiter(msg), scope);
if (num_periods > 0) then
wait until falling_edge(clock_signal);
check_value(target /= pulse_value, TB_ERROR, "gen_pulse: target was already " & to_string(pulse_value) & ". " & add_msg_delimiter(msg), scope, ID_NEVER);
target <= pulse_value;
for i in 1 to num_periods loop
wait until falling_edge(clock_signal);
end loop;
else -- Pulse for one delta cycle only
check_value(target /= pulse_value, TB_ERROR, "gen_pulse: target was already " & to_string(pulse_value) & ". " & add_msg_delimiter(msg), scope, ID_NEVER);
target <= pulse_value;
wait for 0 ns;
end if;
target <= init_value;
end;
-- Overload to allow excluding the pulse_value argument:
-- Make pulse_value = true by default
procedure gen_pulse(
signal target : inout boolean;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
gen_pulse(target, true, clock_signal, num_periods, msg, scope, msg_id, msg_id_panel); -- pulse_value = '1' by default
end;
-- gen_pulse(slv)
-- Generate a pulse on a std_logic_vector for a certain amount of time
--
-- If blocking_mode = BLOCKING : Procedure waits until the pulse is done before returning to the caller.
-- If blocking_mode = NON_BLOCKING : Procedure starts the pulse, schedules the end of the pulse, then returns to the caller immediately.
--
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_value : std_logic_vector;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant init_value : std_logic_vector(target'range) := target;
variable v_target : std_logic_vector(target'length-1 downto 0) := target;
variable v_pulse : std_logic_vector(pulse_value'length-1 downto 0) := pulse_value;
begin
log(msg_id, "Pulse to " & to_string(pulse_value, HEX, AS_IS, INCL_RADIX) &
" for " & to_string(pulse_duration) & ". " & add_msg_delimiter(msg), scope);
check_value(target /= pulse_value, TB_ERROR, "gen_pulse: target was already " & to_string(pulse_value) & ". " & add_msg_delimiter(msg), scope, ID_NEVER);
for i in 0 to (v_target'length-1) loop
if pulse_value(i) /= '-' then
v_target(i) := v_pulse(i); -- Generate pulse
end if;
end loop;
target <= v_target;
if (blocking_mode = BLOCKING) then
wait for pulse_duration;
target <= init_value;
else
target <= transport init_value after pulse_duration;
end if;
end;
-- Overload to allow excluding the pulse_value argument:
-- Make pulse_value = (others => '1') by default
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_duration : time;
constant blocking_mode : t_blocking_mode;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant pulse_value : std_logic_vector(target'range) := (others => '1');
begin
gen_pulse(target, pulse_value, pulse_duration, blocking_mode, msg, scope, msg_id, msg_id_panel); -- Blocking mode by default
end;
-- Overload to allow excluding the blocking_mode and pulse_value arguments:
-- Make blocking_mode = BLOCKING and pulse_value = (others => '1') by default
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant pulse_value : std_logic_vector(target'range) := (others => '1');
begin
gen_pulse(target, pulse_value, pulse_duration, BLOCKING, msg, scope, msg_id, msg_id_panel); -- Blocking mode by default
end;
-- Overload to allow excluding the blocking_mode argument:
-- Make blocking_mode = BLOCKING by default
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_value : std_logic_vector;
constant pulse_duration : time;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
begin
gen_pulse(target, pulse_value, pulse_duration, BLOCKING, msg, scope, msg_id, msg_id_panel); -- Blocking mode by default
end;
-- gen_pulse(slv)
-- Generate a pulse on a std_logic_vector for a certain number of clock cycles
procedure gen_pulse(
signal target : inout std_logic_vector;
constant pulse_value : std_logic_vector;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant init_value : std_logic_vector(target'range) := target;
constant v_pulse : std_logic_vector(pulse_value'length-1 downto 0) := pulse_value;
variable v_target : std_logic_vector(target'length-1 downto 0) := target;
begin
log(msg_id, "Pulse to " & to_string(pulse_value, HEX, AS_IS, INCL_RADIX) &
" for " & to_string(num_periods) & " clk cycles. " & add_msg_delimiter(msg), scope);
check_value(target /= pulse_value, TB_ERROR, "gen_pulse: target was already " & to_string(pulse_value) & ". " & add_msg_delimiter(msg), scope, ID_NEVER);
if (num_periods > 0) then
wait until falling_edge(clock_signal);
for i in 0 to (v_target'length-1) loop
if v_pulse(i) /= '-' then
v_target(i) := v_pulse(i); -- Generate pulse
end if;
end loop;
target <= v_target;
for i in 1 to num_periods loop
wait until falling_edge(clock_signal);
end loop;
else -- Pulse for one delta cycle only
for i in 0 to (v_target'length-1) loop
if v_pulse(i) /= '-' then
v_target(i) := v_pulse(i); -- Generate pulse
end if;
end loop;
target <= v_target;
wait for 0 ns;
end if;
target <= init_value;
end;
-- Overload to allow excluding the pulse_value argument:
-- Make pulse_value = (others => '1') by default
procedure gen_pulse(
signal target : inout std_logic_vector;
signal clock_signal : std_logic;
constant num_periods : natural;
constant msg : string;
constant scope : string := C_TB_SCOPE_DEFAULT;
constant msg_id : t_msg_id := ID_GEN_PULSE;
constant msg_id_panel : t_msg_id_panel := shared_msg_id_panel
) is
constant pulse_value : std_logic_vector(target'range) := (others => '1');
begin
gen_pulse(target, pulse_value, clock_signal, num_periods, msg, scope, msg_id, msg_id_panel); -- pulse_value = (others => '1') by default
end;
--------------------------------------------
-- Clock generators :
-- Include this as a concurrent procedure from your test bench.
-- ( Including this procedure call as a concurrent statement directly in your architecture
-- is in fact identical to a process, where the procedure parameters is the sensitivity list )
-- Set duty cycle by setting clock_high_percentage from 1 to 99. Beware of rounding errors.
--------------------------------------------
procedure clock_generator(
signal clock_signal : inout std_logic;
constant clock_period : in time;
constant clock_high_percentage : in natural range 1 to 99 := 50
) is
-- Making sure any rounding error after calculating period/2 is not accumulated.
constant C_FIRST_HALF_CLK_PERIOD : time := clock_period * clock_high_percentage/100;
begin
loop
clock_signal <= '1';
wait for C_FIRST_HALF_CLK_PERIOD;
clock_signal <= '0';
wait for (clock_period - C_FIRST_HALF_CLK_PERIOD);
end loop;
end;
--------------------------------------------
-- Clock generator overload:
-- Include this as a concurrent procedure from your test bench.
-- ( Including this procedure call as a concurrent statement directly in your architecture
-- is in fact identical to a process, where the procedure parameters is the sensitivity list )
-- Set duty cycle by setting clock_high_time.
--------------------------------------------
procedure clock_generator(
signal clock_signal : inout std_logic;
constant clock_period : in time;
constant clock_high_time : in time
) is
begin
check_value(clock_high_time < clock_period, TB_ERROR, "clock_generator: parameter clock_high_time must be lower than parameter clock_period!", C_TB_SCOPE_DEFAULT, ID_NEVER);
loop
clock_signal <= '1';
wait for clock_high_time;
clock_signal <= '0';
wait for (clock_period - clock_high_time);
end loop;
end;
--------------------------------------------
-- Clock generator overload:
-- - Count variable (clock_count) is added as an output. Wraps when reaching max value of
-- natural type.
-- - Set duty cycle by setting clock_high_percentage from 1 to 99. Beware of rounding errors.
--------------------------------------------
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_count : inout natural;
constant clock_period : in time;
constant clock_high_percentage : in natural range 1 to 99 := 50
) is
-- Making sure any rounding error after calculating period/2 is not accumulated.
constant C_FIRST_HALF_CLK_PERIOD : time := clock_period * clock_high_percentage/100;
begin
clock_count <= 0;
loop
clock_signal <= '0'; -- Should start on 0
wait for C_FIRST_HALF_CLK_PERIOD;
-- Update clock_count when clock_signal is set to '1'
if clock_count < natural'right then
clock_count <= clock_count + 1;
else -- Wrap when reached max value of natural
clock_count <= 0;
end if;
clock_signal <= '1';
wait for (clock_period - C_FIRST_HALF_CLK_PERIOD);
end loop;
end;
--------------------------------------------
-- Clock generator overload:
-- - Counter clock_count is given as an output. Wraps when reaching max value of
-- natural type.
-- - Set duty cycle by setting clock_high_time.
--------------------------------------------
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_count : inout natural;
constant clock_period : in time;
constant clock_high_time : in time
) is
begin
clock_count <= 0;
check_value(clock_high_time < clock_period, TB_ERROR, "clock_generator: parameter clock_high_time must be lower than parameter clock_period!", C_TB_SCOPE_DEFAULT, ID_NEVER);
loop
clock_signal <= '0';
wait for clock_high_time;
if clock_count < natural'right then
clock_count <= clock_count + 1;
else -- Wrap when reached max value of natural
clock_count <= 0;
end if;
clock_signal <= '1';
wait for (clock_period - clock_high_time);
end loop;
end;
--------------------------------------------
-- Clock generator overload:
-- - Enable signal (clock_ena) is added as a parameter
-- - The clock goes to '1' immediately when the clock is enabled (clock_ena = true)
-- - Log when the clock_ena changes. clock_name is used in the log message.
-- - Set duty cycle by setting clock_high_percentage from 1 to 99. Beware of rounding errors.
--------------------------------------------
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
constant clock_period : in time;
constant clock_name : in string;
constant clock_high_percentage : in natural range 1 to 99 := 50
) is
-- Making sure any rounding error after calculating period/2 is not accumulated.
constant C_FIRST_HALF_CLK_PERIOD : time := clock_period * clock_high_percentage/100;
begin
loop
if not clock_ena then
if now /= 0 ps then
log(ID_CLOCK_GEN, "Stopping clock " & clock_name);
end if;
clock_signal <= '0';
wait until clock_ena;
log(ID_CLOCK_GEN, "Starting clock " & clock_name);
end if;
clock_signal <= '1';
wait for C_FIRST_HALF_CLK_PERIOD;
clock_signal <= '0';
wait for (clock_period - C_FIRST_HALF_CLK_PERIOD);
end loop;
end;
--------------------------------------------
-- Clock generator overload:
-- - Enable signal (clock_ena) is added as a parameter
-- - The clock goes to '1' immediately when the clock is enabled (clock_ena = true)
-- - Log when the clock_ena changes. clock_name is used in the log message.
-- inferred to be low time.
-- - Set duty cycle by setting clock_high_time.
--------------------------------------------
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
constant clock_period : in time;
constant clock_name : in string;
constant clock_high_time : in time
) is
begin
check_value(clock_high_time < clock_period, TB_ERROR, "clock_generator: parameter clock_high_time must be lower than parameter clock_period!", C_TB_SCOPE_DEFAULT, ID_NEVER);
loop
if not clock_ena then
if now /= 0 ps then
log(ID_CLOCK_GEN, "Stopping clock " & clock_name);
end if;
clock_signal <= '0';
wait until clock_ena;
log(ID_CLOCK_GEN, "Starting clock " & clock_name);
end if;
clock_signal <= '1';
wait for clock_high_time;
clock_signal <= '0';
wait for (clock_period - clock_high_time);
end loop;
end;
--------------------------------------------
-- Clock generator overload:
-- - Enable signal (clock_ena) is added as a parameter
-- - The clock goes to '1' immediately when the clock is enabled (clock_ena = true)
-- - Log when the clock_ena changes. clock_name is used in the log message.
-- - Count variable (clock_count) is added as an output. Wraps when reaching max value of
-- natural type.
-- - Set duty cycle by setting clock_high_percentage from 1 to 99. Beware of rounding errors.
--------------------------------------------
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
signal clock_count : out natural;
constant clock_period : in time;
constant clock_name : in string;
constant clock_high_percentage : in natural range 1 to 99 := 50
) is
-- Making sure any rounding error after calculating period/2 is not accumulated.
constant C_FIRST_HALF_CLK_PERIOD : time := clock_period * clock_high_percentage/100;
variable v_clock_count : natural := 0;
begin
clock_count <= v_clock_count;
loop
if not clock_ena then
if now /= 0 ps then
log(ID_CLOCK_GEN, "Stopping clock " & clock_name);
end if;
clock_signal <= '0';
wait until clock_ena;
log(ID_CLOCK_GEN, "Starting clock " & clock_name);
end if;
clock_signal <= '1';
wait for C_FIRST_HALF_CLK_PERIOD;
clock_signal <= '0';
wait for (clock_period - C_FIRST_HALF_CLK_PERIOD);
if v_clock_count < natural'right then
v_clock_count := v_clock_count + 1;
else -- Wrap when reached max value of natural
v_clock_count := 0;
end if;
clock_count <= v_clock_count;
end loop;
end;
--------------------------------------------
-- Clock generator overload:
-- - Enable signal (clock_ena) is added as a parameter
-- - The clock goes to '1' immediately when the clock is enabled (clock_ena = true)
-- - Log when the clock_ena changes. clock_name is used in the log message.
-- inferred to be low time.
-- - Count variable (clock_count) is added as an output. Wraps when reaching max value of
-- natural type.
-- - Set duty cycle by setting clock_high_time.
--------------------------------------------
procedure clock_generator(
signal clock_signal : inout std_logic;
signal clock_ena : in boolean;
signal clock_count : out natural;
constant clock_period : in time;
constant clock_name : in string;
constant clock_high_time : in time
) is
variable v_clock_count : natural := 0;
begin
clock_count <= v_clock_count;
check_value(clock_high_time < clock_period, TB_ERROR, "clock_generator: parameter clock_high_time must be lower than parameter clock_period!", C_TB_SCOPE_DEFAULT, ID_NEVER);
loop
if not clock_ena then
if now /= 0 ps then
log(ID_CLOCK_GEN, "Stopping clock " & clock_name);
end if;
clock_signal <= '0';
wait until clock_ena;
log(ID_CLOCK_GEN, "Starting clock " & clock_name);
end if;
clock_signal <= '1';
wait for clock_high_time;
clock_signal <= '0';
wait for (clock_period - clock_high_time);
if v_clock_count < natural'right then
v_clock_count := v_clock_count + 1;
else -- Wrap when reached max value of natural
v_clock_count := 0;
end if;
clock_count <= v_clock_count;
end loop;
end;
-- ============================================================================
-- Synchronisation methods
-- ============================================================================
procedure block_flag(
constant flag_name : in string;
constant msg : in string
) is
begin
-- Block the flag if it was used before
for i in shared_flag_array'range loop
if shared_flag_array(i).flag_name(flag_name'range) = flag_name or shared_flag_array(i).flag_name = (shared_flag_array(i).flag_name'range => ' ') then
shared_flag_array(i).flag_name(flag_name'range) := flag_name;
shared_flag_array(i).is_active := true;
exit;
end if;
end loop;
log(ID_BLOCKING, "Blocking " & flag_name & ". " & add_msg_delimiter(msg), C_SCOPE);
end procedure;
procedure unblock_flag(
constant flag_name : in string;
constant msg : in string;
signal trigger : inout std_logic
) is
variable found : boolean := false;
begin
-- check if the flag has already been added. If not add it.
for i in shared_flag_array'range loop
if shared_flag_array(i).flag_name(flag_name'range) = flag_name or shared_flag_array(i).flag_name = (shared_flag_array(i).flag_name'range => ' ') then
shared_flag_array(i).flag_name(flag_name'range) := flag_name;
shared_flag_array(i).is_active := false;
found := true;
log(ID_BLOCKING, "Unblocking " & flag_name & ". " & add_msg_delimiter(msg), C_SCOPE);
gen_pulse(trigger, 0 ns, "pulsing global_trigger. " & add_msg_delimiter(msg), C_TB_SCOPE_DEFAULT, ID_NEVER);
exit;
end if;
end loop;
if found = false then
log(ID_BLOCKING, "The flag " & flag_name & " was not found and the maximum of flags were used. Configure in adaptations_pkg. " & add_msg_delimiter(msg), C_SCOPE);
end if;
end procedure;
procedure await_unblock_flag(
constant flag_name : in string;
constant timeout : in time;
constant msg : in string;
constant flag_returning : in t_flag_returning := KEEP_UNBLOCKED;
constant timeout_severity : in t_alert_level := ERROR
) is
variable v_flag_is_active : boolean := true;
constant start_time : time := now;
begin
-- check if flag was not unblocked before
for i in shared_flag_array'range loop
-- check if the flag was already in the global_flag array. If it was not -> add it to the first free space
if shared_flag_array(i).flag_name(flag_name'range) = flag_name or shared_flag_array(i).flag_name = (shared_flag_array(i).flag_name'range => ' ') then
shared_flag_array(i).flag_name(flag_name'range) := flag_name;
v_flag_is_active := shared_flag_array(i).is_active;
if v_flag_is_active = false then
log(ID_BLOCKING, flag_name & " was not blocked. " & add_msg_delimiter(msg), C_SCOPE);
if flag_returning = RETURN_TO_BLOCK then
-- wait for all sequencer that are waiting for that flag before reseting it
wait for 0 ns;
shared_flag_array(i).is_active := true;
end if;
end if;
exit;
end if;
end loop;
if v_flag_is_active = true then
-- log before while loop. Otherwise the message will be printed everytime the global_trigger was triggered.
log(ID_BLOCKING, "Waiting for " & flag_name & " to be unblocked. " & add_msg_delimiter(msg), C_SCOPE);
end if;
while v_flag_is_active = true loop
if timeout /= 0 ns then
wait until rising_edge(global_trigger) for ((start_time + timeout) - now);
check_value(global_trigger = '1', timeout_severity, flag_name & " timed out" & add_msg_delimiter(msg), C_SCOPE, ID_NEVER);
if global_trigger /= '1' then
exit;
end if;
else
wait until rising_edge(global_trigger);
end if;
for i in shared_flag_array'range loop
if shared_flag_array(i).flag_name(flag_name'range) = flag_name then
v_flag_is_active := shared_flag_array(i).is_active;
if v_flag_is_active = false then
log(ID_BLOCKING, flag_name & " was unblocked. " & add_msg_delimiter(msg), C_SCOPE);
if flag_returning = RETURN_TO_BLOCK then
-- wait for all sequencer that are waiting for that flag before reseting it
wait for 0 ns;
shared_flag_array(i).is_active := true;
end if;
end if;
end if;
end loop;
end loop;
end procedure;
procedure await_barrier(
signal barrier_signal : inout std_logic;
constant timeout : in time;
constant msg : in string;
constant timeout_severity : in t_alert_level := ERROR
)is
begin
-- set barrier signal to 0
barrier_signal <= '0';
log(ID_BLOCKING, "Waiting for barrier. " & add_msg_delimiter(msg), C_SCOPE);
-- wait until all sequencer using that barrier_signal wait for it
if timeout = 0 ns then
wait until barrier_signal = '0';
else
wait until barrier_signal = '0' for timeout;
end if;
if barrier_signal /= '0' then
-- timeout
alert(timeout_severity, "Timeout while waiting for barrier signal. " & add_msg_delimiter(msg), C_SCOPE);
else
log(ID_BLOCKING, "Barrier received. " & add_msg_delimiter(msg), C_SCOPE);
end if;
barrier_signal <= '1';
end procedure;
procedure await_semaphore_in_delta_cycles(
variable semaphore : inout t_protected_semaphore
) is
variable v_cnt_lock_tries : natural := 0;
begin
while semaphore.get_semaphore = false and v_cnt_lock_tries < C_NUM_SEMAPHORE_LOCK_TRIES loop
wait for 0 ns;
v_cnt_lock_tries := v_cnt_lock_tries + 1;
end loop;
if v_cnt_lock_tries = C_NUM_SEMAPHORE_LOCK_TRIES then
tb_error("Failed to acquire semaphore when sending command to VVC", C_SCOPE);
end if;
end procedure;
procedure release_semaphore(
variable semaphore : inout t_protected_semaphore
) is
begin
semaphore.release_semaphore;
end procedure;
end package body methods_pkg;
|
entity vhpi3 is
end entity;
architecture test of vhpi3 is
type weight is range -100 to 4000
units
g;
kg = 1000 g;
end units;
signal x : weight := 2 g;
begin
end architecture;
|
entity vhpi3 is
end entity;
architecture test of vhpi3 is
type weight is range -100 to 4000
units
g;
kg = 1000 g;
end units;
signal x : weight := 2 g;
begin
end architecture;
|
entity vhpi3 is
end entity;
architecture test of vhpi3 is
type weight is range -100 to 4000
units
g;
kg = 1000 g;
end units;
signal x : weight := 2 g;
begin
end architecture;
|
------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 8; -- rom data width (8/32)
romdepth : integer := 23; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 20; -- ram address depth
srambanks : integer := 1 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
component leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
-- Clock and reset
diff_clkin_top_125_p: in std_ulogic;
diff_clkin_bot_125_p: in std_ulogic;
clkin_50_fpga_right: in std_ulogic;
clkin_50_fpga_top: in std_ulogic;
clkout_sma: out std_ulogic;
cpu_resetn: in std_ulogic;
-- DDR3
ddr3_ck_p: out std_ulogic;
ddr3_ck_n: out std_ulogic;
ddr3_cke: out std_ulogic;
ddr3_rstn: out std_ulogic;
ddr3_csn: out std_ulogic;
ddr3_rasn: out std_ulogic;
ddr3_casn: out std_ulogic;
ddr3_wen: out std_ulogic;
ddr3_ba: out std_logic_vector(2 downto 0);
ddr3_a : out std_logic_vector(13 downto 0);
ddr3_dqs_p: inout std_logic_vector(3 downto 0);
ddr3_dqs_n: inout std_logic_vector(3 downto 0);
ddr3_dq: inout std_logic_vector(31 downto 0);
ddr3_dm: out std_logic_vector(3 downto 0);
ddr3_odt: out std_ulogic;
ddr3_oct_rzq: in std_ulogic;
-- LPDDR2
lpddr2_ck_p: out std_ulogic;
lpddr2_ck_n: out std_ulogic;
lpddr2_cke: out std_ulogic;
lpddr2_a: out std_logic_vector(9 downto 0);
lpddr2_dqs_p: inout std_logic_vector(1 downto 0);
lpddr2_dqs_n: inout std_logic_vector(1 downto 0);
lpddr2_dq: inout std_logic_vector(15 downto 0);
lpddr2_dm: out std_logic_vector(1 downto 0);
lpddr2_csn: out std_ulogic;
lpddr2_oct_rzq: in std_ulogic;
-- Flash and SSRAM interface
fm_a: out std_logic_vector(26 downto 1);
fm_d: in std_logic_vector(15 downto 0);
flash_clk: out std_ulogic;
flash_resetn: out std_ulogic;
flash_cen: out std_ulogic;
flash_advn: out std_ulogic;
flash_wen: out std_ulogic;
flash_oen: out std_ulogic;
flash_rdybsyn: in std_ulogic;
ssram_clk: out std_ulogic;
ssram_oen: out std_ulogic;
sram_cen: out std_ulogic;
ssram_bwen: out std_ulogic;
ssram_bwan: out std_ulogic;
ssram_bwbn: out std_ulogic;
ssram_adscn: out std_ulogic;
ssram_adspn: out std_ulogic;
ssram_zzn: out std_ulogic; -- Name incorrect, this is active high
ssram_advn: out std_ulogic;
-- EEPROM
eeprom_scl : out std_ulogic;
eeprom_sda : inout std_ulogic;
-- UART
uart_rxd : in std_ulogic;
uart_rts : in std_ulogic; -- Note CTS and RTS mixed up on PCB
uart_txd : out std_ulogic;
uart_cts : out std_ulogic;
-- USB UART Interface
usb_uart_rstn : in std_ulogic; -- inout
usb_uart_ri : in std_ulogic;
usb_uart_dcd : in std_ulogic;
usb_uart_dtr : out std_ulogic;
usb_uart_dsr : in std_ulogic;
usb_uart_txd : out std_ulogic;
usb_uart_rxd : in std_ulogic;
usb_uart_rts : in std_ulogic;
usb_uart_cts : out std_ulogic;
usb_uart_gpio2 : in std_ulogic;
usb_uart_suspend : in std_ulogic;
usb_uart_suspendn : in std_ulogic;
-- Ethernet port A
eneta_rx_clk: in std_ulogic;
eneta_tx_clk: in std_ulogic;
eneta_intn: in std_ulogic;
eneta_resetn: out std_ulogic;
eneta_mdio: inout std_ulogic;
eneta_mdc: out std_ulogic;
eneta_rx_er: in std_ulogic;
eneta_tx_er: out std_ulogic;
eneta_rx_col: in std_ulogic;
eneta_rx_crs: in std_ulogic;
eneta_tx_d: out std_logic_vector(3 downto 0);
eneta_rx_d: in std_logic_vector(3 downto 0);
eneta_gtx_clk: out std_ulogic;
eneta_tx_en: out std_ulogic;
eneta_rx_dv: in std_ulogic;
-- Ethernet port B
enetb_rx_clk: in std_ulogic;
enetb_tx_clk: in std_ulogic;
enetb_intn: in std_ulogic;
enetb_resetn: out std_ulogic;
enetb_mdio: inout std_ulogic;
enetb_mdc: out std_ulogic;
enetb_rx_er: in std_ulogic;
enetb_tx_er: out std_ulogic;
enetb_rx_col: in std_ulogic;
enetb_rx_crs: in std_ulogic;
enetb_tx_d: out std_logic_vector(3 downto 0);
enetb_rx_d: in std_logic_vector(3 downto 0);
enetb_gtx_clk: out std_ulogic;
enetb_tx_en: out std_ulogic;
enetb_rx_dv: in std_ulogic;
-- LEDs, switches, GPIO
user_led : out std_logic_vector(3 downto 0);
user_dipsw : in std_logic_vector(3 downto 0);
dip_3p3V : in std_ulogic;
user_pb : in std_logic_vector(3 downto 0);
overtemp_fpga : out std_ulogic;
header_p : in std_logic_vector(5 downto 0); -- inout
header_n : in std_logic_vector(5 downto 0); -- inout
header_d : in std_logic_vector(7 downto 0); -- inout
-- LCD
lcd_data : in std_logic_vector(7 downto 0); -- inout
lcd_wen : out std_ulogic;
lcd_csn : out std_ulogic;
lcd_d_cn : out std_ulogic;
-- HIGH-SPEED-MEZZANINE-CARD Interface
-- hsmc_clk_in0: in std_ulogic;
-- hsmc_clk_out0: out std_ulogic;
-- hsmc_clk_in_p: in std_logic_vector(2 downto 1);
-- hsmc_clk_out_p: out std_logic_vector(2 downto 1);
-- hsmc_d: in std_logic_vector(3 downto 0); -- inout
-- hsmc_tx_d_p: out std_logic_vector(16 downto 0);
-- hsmc_rx_d_p: in std_logic_vector(16 downto 0);
-- hsmc_rx_led: out std_ulogic;
-- hsmc_tx_led: out std_ulogic;
-- hsmc_scl: out std_ulogic;
-- hsmc_sda: in std_ulogic; -- inout
-- hsmc_prsntn: in std_ulogic;
-- MAX V CPLD interface
max5_csn: out std_ulogic;
max5_wen: out std_ulogic;
max5_oen: out std_ulogic;
max5_ben: out std_logic_vector(3 downto 0);
max5_clk: out std_ulogic;
-- USB Blaster II
usb_clk : in std_ulogic;
usb_data : in std_logic_vector(7 downto 0); -- inout
usb_addr : in std_logic_vector(1 downto 0); -- inout
usb_scl : in std_ulogic; -- inout
usb_sda : in std_ulogic; -- inout
usb_resetn : in std_ulogic;
usb_oen : in std_ulogic;
usb_rdn : in std_ulogic;
usb_wrn : in std_ulogic;
usb_full : out std_ulogic;
usb_empty : out std_ulogic;
fx2_resetn : in std_ulogic
);
end component;
signal clk125, clk50, clkout: std_ulogic := '0';
signal rst: std_ulogic;
signal user_led: std_logic_vector(3 downto 0);
signal address : std_logic_vector(26 downto 1);
signal data : std_logic_vector(15 downto 0);
signal ramsn : std_ulogic;
signal ramoen : std_ulogic;
signal rwen : std_ulogic;
signal mben : std_logic_vector(3 downto 0);
--signal rwenx : std_logic_vector(3 downto 0);
signal romsn : std_logic;
signal iosn : std_ulogic;
signal oen : std_ulogic;
--signal read : std_ulogic;
signal writen : std_ulogic;
signal brdyn : std_ulogic;
signal bexcn : std_ulogic;
signal wdog : std_ulogic;
signal dsuen, dsutx, dsurx, dsubren, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal error : std_logic;
signal gpio : std_logic_vector(7 downto 0);
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal plllock : std_ulogic;
signal txd1, rxd1 : std_ulogic;
--signal txd2, rxd2 : std_ulogic;
constant lresp : boolean := false;
signal eneta_rx_clk, eneta_tx_clk, enetb_rx_clk, enetb_tx_clk: std_ulogic;
signal eneta_intn, eneta_resetn, enetb_intn, enetb_resetn: std_ulogic;
signal eneta_mdio, enetb_mdio: std_logic;
signal eneta_mdc, enetb_mdc: std_ulogic;
signal eneta_rx_er, eneta_rx_col, eneta_rx_crs, eneta_rx_dv: std_ulogic;
signal enetb_rx_er, enetb_rx_col, enetb_rx_crs, enetb_rx_dv: std_ulogic;
signal eneta_rx_d, enetb_rx_d: std_logic_vector(7 downto 0);
signal eneta_tx_d, enetb_tx_d: std_logic_vector(7 downto 0);
signal eneta_tx_en, eneta_tx_er, enetb_tx_en, enetb_tx_er: std_ulogic;
signal lpddr2_ck, lpddr2_ck_n, lpddr2_cke, lpddr2_cs_n: std_ulogic;
signal lpddr2_ca: std_logic_vector(9 downto 0);
signal lpddr2_dm, lpddr2_dqs, lpddr2_dqs_n: std_logic_vector(3 downto 0);
signal lpddr2_dq: std_logic_vector(31 downto 0);
begin
-- clock and reset
clk125 <= not clk125 after 4 ns;
clk50 <= not clk50 after 10 ns;
rst <= dsurst;
dsubren <= '1'; rxd1 <= '1';
d3 : leon3mp
generic map ( fabtech, memtech, padtech, disas, dbguart, pclow )
port map (
-- Clock and reset
diff_clkin_top_125_p => clk125,
diff_clkin_bot_125_p => clk125,
clkin_50_fpga_right => clk50,
clkin_50_fpga_top => clk50,
clkout_sma => clkout,
cpu_resetn => rst,
-- DDR3
ddr3_ck_p => open,
ddr3_ck_n => open,
ddr3_cke => open,
ddr3_rstn => open,
ddr3_csn => open,
ddr3_rasn => open,
ddr3_casn => open,
ddr3_wen => open,
ddr3_ba => open,
ddr3_a => open,
ddr3_dqs_p => open,
ddr3_dqs_n => open,
ddr3_dq => open,
ddr3_dm => open,
ddr3_odt => open,
ddr3_oct_rzq => '0',
-- LPDDR2
lpddr2_ck_p => lpddr2_ck,
lpddr2_ck_n => lpddr2_ck_n,
lpddr2_cke => lpddr2_cke,
lpddr2_a => lpddr2_ca,
lpddr2_dqs_p => lpddr2_dqs(1 downto 0),
lpddr2_dqs_n => lpddr2_dqs_n(1 downto 0),
lpddr2_dq => lpddr2_dq(15 downto 0),
lpddr2_dm => lpddr2_dm(1 downto 0),
lpddr2_csn => lpddr2_cs_n,
lpddr2_oct_rzq => '0',
-- Flash and SSRAM interface
fm_a => address(26 downto 1),
fm_d => data,
flash_clk => open,
flash_resetn => open,
flash_cen => romsn,
flash_advn => open,
flash_wen => rwen,
flash_oen => oen,
flash_rdybsyn => '1',
ssram_clk => open,
ssram_oen => open,
sram_cen => open,
ssram_bwen => open,
ssram_bwan => open,
ssram_bwbn => open,
ssram_adscn => open,
ssram_adspn => open,
ssram_zzn => open,
ssram_advn => open,
-- EEPROM
eeprom_scl => open,
eeprom_sda => open,
-- UART
uart_rxd => rxd1,
uart_rts => '1',
uart_txd => txd1,
uart_cts => open,
-- USB UART Interface
usb_uart_rstn => '1',
usb_uart_ri => '0',
usb_uart_dcd => '1',
usb_uart_dtr => open,
usb_uart_dsr => '1',
usb_uart_txd => open,
usb_uart_rxd => '1',
usb_uart_rts => '1',
usb_uart_cts => open,
usb_uart_gpio2 => '0',
usb_uart_suspend => '0',
usb_uart_suspendn => '1',
-- Ethernet port A
eneta_rx_clk => eneta_rx_clk,
eneta_tx_clk => eneta_tx_clk,
eneta_intn => eneta_intn,
eneta_resetn => eneta_resetn,
eneta_mdio => eneta_mdio,
eneta_mdc => eneta_mdc,
eneta_rx_er => eneta_rx_er,
eneta_tx_er => eneta_tx_er,
eneta_rx_col => eneta_rx_col,
eneta_rx_crs => eneta_rx_crs,
eneta_tx_d => eneta_tx_d(3 downto 0),
eneta_rx_d => eneta_rx_d(3 downto 0),
eneta_gtx_clk => open,
eneta_tx_en => eneta_tx_en,
eneta_rx_dv => eneta_rx_dv,
-- Ethernet port B
enetb_rx_clk => enetb_rx_clk,
enetb_tx_clk => enetb_tx_clk,
enetb_intn => enetb_intn,
enetb_resetn => enetb_resetn,
enetb_mdio => enetb_mdio,
enetb_mdc => enetb_mdc,
enetb_rx_er => enetb_rx_er,
enetb_tx_er => enetb_tx_er,
enetb_rx_col => enetb_rx_col,
enetb_rx_crs => enetb_rx_crs,
enetb_tx_d => enetb_tx_d(3 downto 0),
enetb_rx_d => enetb_rx_d(3 downto 0),
enetb_gtx_clk => open,
enetb_tx_en => enetb_tx_en,
enetb_rx_dv => enetb_rx_dv,
-- LEDs, switches, GPIO
user_led => user_led,
user_dipsw => "1111",
dip_3p3V => '0',
user_pb => "0000",
overtemp_fpga => open,
header_p => "000000",
header_n => "000000",
header_d => "00000000",
-- LCD
lcd_data => "00000000",
lcd_wen => open,
lcd_csn => open,
lcd_d_cn => open,
-- HIGH-SPEED-MEZZANINE-CARD Interface
-- hsmc_clk_in0 => '0',
-- hsmc_clk_out0 => open,
-- hsmc_clk_in_p => "00",
-- hsmc_clk_out_p => open,
-- hsmc_d => "0000",
-- hsmc_tx_d_p => open,
-- hsmc_rx_d_p => (others => '0'),
-- hsmc_rx_led => open,
-- hsmc_tx_led => open,
-- hsmc_scl => open,
-- hsmc_sda => '0',
-- hsmc_prsntn => '0',
-- MAX V CPLD interface
max5_csn => open,
max5_wen => open,
max5_oen => open,
max5_ben => open,
max5_clk => open,
-- USB Blaster II
usb_clk => '0',
usb_data => (others => '0'),
usb_addr => "00",
usb_scl => '0',
usb_sda => '0',
usb_resetn => '0',
usb_oen => '0',
usb_rdn => '0',
usb_wrn => '0',
usb_full => open,
usb_empty => open,
fx2_resetn => '1'
);
-- 16 bit prom
prom0 : sram16 generic map (index => 4, abits => romdepth, fname => promfile)
port map (address(romdepth downto 1), data,
romsn, romsn, romsn, rwen, oen);
-- ROMSN is pulled down by the MAX V system controller after FPGA programming
-- completed (bug?)
romsn <= 'L';
data <= buskeep(data), (others => 'H') after 250 ns;
error <= user_led(3);
eneta_mdio <= 'H';
enetb_mdio <= 'H';
eneta_tx_d(7 downto 4) <= "0000";
enetb_tx_d(7 downto 4) <= "0000";
p1: phy
generic map(base1000_t_fd => 0, base1000_t_hd => 0, address => 0)
port map(rst, eneta_mdio, eneta_tx_clk, eneta_rx_clk, eneta_rx_d, eneta_rx_dv,
eneta_rx_er, eneta_rx_col, eneta_rx_crs, eneta_tx_d, eneta_tx_en, eneta_tx_er, eneta_mdc,
'0');
p2: phy
generic map(base1000_t_fd => 0, base1000_t_hd => 0, address => 1)
port map(rst, enetb_mdio, enetb_tx_clk, enetb_rx_clk, enetb_rx_d, enetb_rx_dv,
enetb_rx_er, enetb_rx_col, enetb_rx_crs, enetb_tx_d, enetb_tx_en, enetb_tx_er, enetb_mdc,
'0');
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
test0 : grtestmod generic map (width => 16)
port map ( rst, clk50, error, address(21 downto 2), data,
iosn, oen, writen, brdyn);
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 03:23:34 03/25/2015
-- Design Name:
-- Module Name: RISC_MACHINE - Structural
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity RISC_MACHINE is
Port( CLK : IN STD_LOGIC;
PC_RESET: IN STD_LOGIC;
RISC_INST_ENB : IN STD_LOGIC;
CCR_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
DATA_OUT: OUT STD_LOGIC_VECTOR (15 downto 0)
);
end RISC_MACHINE;
architecture Structural of RISC_MACHINE is
signal instruction_in, FETCH_out, fpu_out, OP1_out, OP2_out, s_Bank_Data, s_OPA_REG_A, EX_Forward_out: STD_LOGIC_VECTOR(15 downto 0);
signal pc : STD_LOGIC_VECTOR (9 downto 0);
signal DEC_immediate : STD_LOGIC_VECTOR (7 downto 0);
signal write_address, OPA_OPCODE, DEC_opcode, DEC_reg_a, s_Dec_REG_A,s_DEC_OPCODE_OUT : STD_LOGIC_VECTOR(3 downto 0);
signal OP1_SEL, OP2_SEL : STD_LOGIC_VECTOR (1 downto 0);
signal bank_RW, WB_MEM_WE, WB_MUX_SEL : STD_LOGIC;
begin
U1: entity work.FETCH
Port Map ( CLK => CLK,
DATAIN => instruction_in,
INST_ENB => RISC_INST_ENB,
INST_OUT => FETCH_out,
PC_OUT => pc,
WE => '0'
);
U2: entity work.decode
Port Map ( CLK => CLK,
INST_IN => FETCH_out,
OPCODE => DEC_opcode,
REG_A => DEC_reg_a,
IMMEDIATE => DEC_immediate
);
U3: entity work.op_access
Port Map ( CLK => CLK,
OPCODE_IN => DEC_opcode,
REG_A => DEC_reg_a,
IMMEDIATE => DEC_immediate,
W_ADDR => Write_Address,
OP1_MUX_SEL => OP1_SEL,
OP2_MUX_SEL => OP2_SEL,
BANK_R_W => bank_RW,
BANK_ENB => '1',
BANK_DATA => s_Bank_Data,
DEC_REG_ADDR => s_Dec_REG_A,
OPCODE_OUT => OPA_OPCODE,
EX_FWD_IN => EX_Forward_out,
EX_FWD_ADDR => s_Dec_REG_A,
WB_FWD_IN => s_Bank_Data,
WB_FWD_ADDR => Write_Address,
OP1_OUT => OP1_out,
OP2_OUT => OP2_out
);
U4: entity work.execute
Port Map ( CLK => CLK,
OPCODE => OPA_OPCODE,
OP1 => OP1_out,
OP2 => OP2_out,
Dec_Reg_A_IN => s_Dec_REG_A,
OPA_REG_A => s_OPA_REG_A,
Dec_Reg_A_OUT => Write_Address,
DEC_OPCODE_OUT=> s_DEC_OPCODE_OUT,
EX_FWD_OUT => EX_Forward_out,
FPU_OUT => fpu_out,
CCR => CCR_OUT
);
U5: entity work.write_back
Port Map ( CLK => CLK,
DATA_WE => WB_MEM_WE,
FPU_IN => fpu_out,
REG_A => s_OPA_REG_A,
D_OUT_SEL => WB_MUX_SEL,
WB_OUT => s_Bank_Data
);
Cntrl_unit: entity work.control_unit
Port Map( CLK => CLK,
OPA_OPCODE => DEC_opcode,
OP1_MUX_SEL => OP1_SEL,
OP2_MUX_SEL => OP2_SEL,
REG_BANK_WE => bank_RW,
DATA_MEM_WE => WB_MEM_WE,
WB_OPCODE => s_DEC_OPCODE_OUT,
OPA_D_OUT_SEL => WB_MUX_SEL
);
end Structural;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3114.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s02b00x00p07n01i03114ent_a IS
generic ( g1 : boolean );
port ( p1 : in Bit;
p2 : out Bit );
END c05s02b00x00p07n01i03114ent_a;
ARCHITECTURE c05s02b00x00p07n01i03114arch_a OF c05s02b00x00p07n01i03114ent_a IS
BEGIN
p2 <= p1 after 10 ns;
END c05s02b00x00p07n01i03114arch_a;
configuration c05s02b00x00p07n01i03114cfg_a of c05s02b00x00p07n01i03114ent_a is
for c05s02b00x00p07n01i03114arch_a
end for;
end c05s02b00x00p07n01i03114cfg_a;
ENTITY c05s02b00x00p07n01i03114ent IS
END c05s02b00x00p07n01i03114ent;
ARCHITECTURE c05s02b00x00p07n01i03114arch OF c05s02b00x00p07n01i03114ent IS
component virtual
generic ( g1 : boolean );
port ( p1 : in Bit;
p2 : out Bit );
end component;
for u1 : virtual use entity work.c05s02b00x00p07n01i03114ent_a(c05s02b00x00p07n01i03114arch_a);
for others : virtual use entity work.c05s02b00x00p07n01i03114ent_a(c05s02b00x00p07n01i03114arch_a);
signal s1,s2,s3,s4 : Bit;
BEGIN
u1 : virtual
generic map ( true )
port map (s1, s2);
u2 : virtual
generic map ( true )
port map (s2, s3);
u3 : virtual
generic map ( true )
port map (s3, s4);
TESTING: PROCESS
BEGIN
wait for 30 ns;
assert NOT( s2 = s1 and
s3 = s2 and
s4 = s3 )
report "***PASSED TEST: c05s02b00x00p07n01i03114"
severity NOTE;
assert ( s2 = s1 and
s3 = s2 and
s4 = s3 )
report "***FAILED TEST: c05s02b00x00p07n01i03114 - The use of the others clause did not properly configure an instance which has not been previously configured in a configuration specification in an architecture declarative region."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s02b00x00p07n01i03114arch;
configuration c05s02b00x00p07n01i03114cfg of c05s02b00x00p07n01i03114ent is
for c05s02b00x00p07n01i03114arch
end for;
end c05s02b00x00p07n01i03114cfg;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3114.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s02b00x00p07n01i03114ent_a IS
generic ( g1 : boolean );
port ( p1 : in Bit;
p2 : out Bit );
END c05s02b00x00p07n01i03114ent_a;
ARCHITECTURE c05s02b00x00p07n01i03114arch_a OF c05s02b00x00p07n01i03114ent_a IS
BEGIN
p2 <= p1 after 10 ns;
END c05s02b00x00p07n01i03114arch_a;
configuration c05s02b00x00p07n01i03114cfg_a of c05s02b00x00p07n01i03114ent_a is
for c05s02b00x00p07n01i03114arch_a
end for;
end c05s02b00x00p07n01i03114cfg_a;
ENTITY c05s02b00x00p07n01i03114ent IS
END c05s02b00x00p07n01i03114ent;
ARCHITECTURE c05s02b00x00p07n01i03114arch OF c05s02b00x00p07n01i03114ent IS
component virtual
generic ( g1 : boolean );
port ( p1 : in Bit;
p2 : out Bit );
end component;
for u1 : virtual use entity work.c05s02b00x00p07n01i03114ent_a(c05s02b00x00p07n01i03114arch_a);
for others : virtual use entity work.c05s02b00x00p07n01i03114ent_a(c05s02b00x00p07n01i03114arch_a);
signal s1,s2,s3,s4 : Bit;
BEGIN
u1 : virtual
generic map ( true )
port map (s1, s2);
u2 : virtual
generic map ( true )
port map (s2, s3);
u3 : virtual
generic map ( true )
port map (s3, s4);
TESTING: PROCESS
BEGIN
wait for 30 ns;
assert NOT( s2 = s1 and
s3 = s2 and
s4 = s3 )
report "***PASSED TEST: c05s02b00x00p07n01i03114"
severity NOTE;
assert ( s2 = s1 and
s3 = s2 and
s4 = s3 )
report "***FAILED TEST: c05s02b00x00p07n01i03114 - The use of the others clause did not properly configure an instance which has not been previously configured in a configuration specification in an architecture declarative region."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s02b00x00p07n01i03114arch;
configuration c05s02b00x00p07n01i03114cfg of c05s02b00x00p07n01i03114ent is
for c05s02b00x00p07n01i03114arch
end for;
end c05s02b00x00p07n01i03114cfg;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3114.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c05s02b00x00p07n01i03114ent_a IS
generic ( g1 : boolean );
port ( p1 : in Bit;
p2 : out Bit );
END c05s02b00x00p07n01i03114ent_a;
ARCHITECTURE c05s02b00x00p07n01i03114arch_a OF c05s02b00x00p07n01i03114ent_a IS
BEGIN
p2 <= p1 after 10 ns;
END c05s02b00x00p07n01i03114arch_a;
configuration c05s02b00x00p07n01i03114cfg_a of c05s02b00x00p07n01i03114ent_a is
for c05s02b00x00p07n01i03114arch_a
end for;
end c05s02b00x00p07n01i03114cfg_a;
ENTITY c05s02b00x00p07n01i03114ent IS
END c05s02b00x00p07n01i03114ent;
ARCHITECTURE c05s02b00x00p07n01i03114arch OF c05s02b00x00p07n01i03114ent IS
component virtual
generic ( g1 : boolean );
port ( p1 : in Bit;
p2 : out Bit );
end component;
for u1 : virtual use entity work.c05s02b00x00p07n01i03114ent_a(c05s02b00x00p07n01i03114arch_a);
for others : virtual use entity work.c05s02b00x00p07n01i03114ent_a(c05s02b00x00p07n01i03114arch_a);
signal s1,s2,s3,s4 : Bit;
BEGIN
u1 : virtual
generic map ( true )
port map (s1, s2);
u2 : virtual
generic map ( true )
port map (s2, s3);
u3 : virtual
generic map ( true )
port map (s3, s4);
TESTING: PROCESS
BEGIN
wait for 30 ns;
assert NOT( s2 = s1 and
s3 = s2 and
s4 = s3 )
report "***PASSED TEST: c05s02b00x00p07n01i03114"
severity NOTE;
assert ( s2 = s1 and
s3 = s2 and
s4 = s3 )
report "***FAILED TEST: c05s02b00x00p07n01i03114 - The use of the others clause did not properly configure an instance which has not been previously configured in a configuration specification in an architecture declarative region."
severity ERROR;
wait;
END PROCESS TESTING;
END c05s02b00x00p07n01i03114arch;
configuration c05s02b00x00p07n01i03114cfg of c05s02b00x00p07n01i03114ent is
for c05s02b00x00p07n01i03114arch
end for;
end c05s02b00x00p07n01i03114cfg;
|
-- NEED RESULT: ARCH00366.P1: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00366.P2: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00366.P3: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00366: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00366: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00366: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00366: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00366: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00366: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: P3: Transport transactions completed entirely passed
-- NEED RESULT: P2: Transport transactions completed entirely passed
-- NEED RESULT: P1: Transport transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00366
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (2)
-- 9.5.1 (1)
-- 9.5.1 (2)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00366(ARCH00366)
-- ENT00366_Test_Bench(ARCH00366_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00366 is
port (
s_st_rec1_vector : inout st_rec1_vector
; s_st_rec2_vector : inout st_rec2_vector
; s_st_rec3_vector : inout st_rec3_vector
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec1_vector : chk_sig_type := -1 ;
signal chk_st_rec2_vector : chk_sig_type := -1 ;
signal chk_st_rec3_vector : chk_sig_type := -1 ;
--
end ENT00366 ;
--
--
architecture ARCH00366 of ENT00366 is
subtype chk_time_type is Time ;
signal s_st_rec1_vector_savt : chk_time_type := 0 ns ;
signal s_st_rec2_vector_savt : chk_time_type := 0 ns ;
signal s_st_rec3_vector_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_rec1_vector_cnt : chk_cnt_type := 0 ;
signal s_st_rec2_vector_cnt : chk_cnt_type := 0 ;
signal s_st_rec3_vector_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 3 ;
signal st_rec1_vector_select : select_type := 1 ;
signal st_rec2_vector_select : select_type := 1 ;
signal st_rec3_vector_select : select_type := 1 ;
--
begin
CHG1 :
process ( s_st_rec1_vector )
variable correct : boolean ;
begin
case s_st_rec1_vector_cnt is
when 0
=> null ;
-- s_st_rec1_vector(lowb).f2 <= transport
-- c_st_rec1_vector_2(lowb).f2 after 10 ns,
-- c_st_rec1_vector_1(lowb).f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_2(lowb).f2 and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_1(lowb).f2 and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00366.P1" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec1_vector_select <= transport 2 ;
-- s_st_rec1_vector(lowb).f2 <= transport
-- c_st_rec1_vector_2(lowb).f2 after 10 ns ,
-- c_st_rec1_vector_1(lowb).f2 after 20 ns ,
-- c_st_rec1_vector_2(lowb).f2 after 30 ns ,
-- c_st_rec1_vector_1(lowb).f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_2(lowb).f2 and
(s_st_rec1_vector_savt + 10 ns) = Std.Standard.Now ;
st_rec1_vector_select <= transport 3 ;
-- s_st_rec1_vector(lowb).f2 <= transport
-- c_st_rec1_vector_1(lowb).f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_1(lowb).f2 and
(s_st_rec1_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00366" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00366" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00366" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_rec1_vector_savt <= transport Std.Standard.Now ;
chk_st_rec1_vector <= transport s_st_rec1_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec1_vector_cnt <= transport s_st_rec1_vector_cnt + 1 ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_st_rec1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions completed entirely",
chk_st_rec1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
s_st_rec1_vector(lowb).f2 <= transport
c_st_rec1_vector_2(lowb).f2 after 10 ns,
c_st_rec1_vector_1(lowb).f2 after 20 ns
when st_rec1_vector_select = 1 else
--
c_st_rec1_vector_2(lowb).f2 after 10 ns ,
c_st_rec1_vector_1(lowb).f2 after 20 ns ,
c_st_rec1_vector_2(lowb).f2 after 30 ns ,
c_st_rec1_vector_1(lowb).f2 after 40 ns
when st_rec1_vector_select = 2 else
--
c_st_rec1_vector_1(lowb).f2 after 5 ns ;
--
CHG2 :
process ( s_st_rec2_vector )
variable correct : boolean ;
begin
case s_st_rec2_vector_cnt is
when 0
=> null ;
-- s_st_rec2_vector(lowb).f2 <= transport
-- c_st_rec2_vector_2(lowb).f2 after 10 ns,
-- c_st_rec2_vector_1(lowb).f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_2(lowb).f2 and
(s_st_rec2_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_1(lowb).f2 and
(s_st_rec2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00366.P2" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec2_vector_select <= transport 2 ;
-- s_st_rec2_vector(lowb).f2 <= transport
-- c_st_rec2_vector_2(lowb).f2 after 10 ns ,
-- c_st_rec2_vector_1(lowb).f2 after 20 ns ,
-- c_st_rec2_vector_2(lowb).f2 after 30 ns ,
-- c_st_rec2_vector_1(lowb).f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_2(lowb).f2 and
(s_st_rec2_vector_savt + 10 ns) = Std.Standard.Now ;
st_rec2_vector_select <= transport 3 ;
-- s_st_rec2_vector(lowb).f2 <= transport
-- c_st_rec2_vector_1(lowb).f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_1(lowb).f2 and
(s_st_rec2_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00366" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00366" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00366" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_rec2_vector_savt <= transport Std.Standard.Now ;
chk_st_rec2_vector <= transport s_st_rec2_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec2_vector_cnt <= transport s_st_rec2_vector_cnt + 1 ;
--
end process CHG2 ;
--
PGEN_CHKP_2 :
process ( chk_st_rec2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions completed entirely",
chk_st_rec2_vector = 4 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
s_st_rec2_vector(lowb).f2 <= transport
c_st_rec2_vector_2(lowb).f2 after 10 ns,
c_st_rec2_vector_1(lowb).f2 after 20 ns
when st_rec2_vector_select = 1 else
--
c_st_rec2_vector_2(lowb).f2 after 10 ns ,
c_st_rec2_vector_1(lowb).f2 after 20 ns ,
c_st_rec2_vector_2(lowb).f2 after 30 ns ,
c_st_rec2_vector_1(lowb).f2 after 40 ns
when st_rec2_vector_select = 2 else
--
c_st_rec2_vector_1(lowb).f2 after 5 ns ;
--
CHG3 :
process ( s_st_rec3_vector )
variable correct : boolean ;
begin
case s_st_rec3_vector_cnt is
when 0
=> null ;
-- s_st_rec3_vector(highb).f3 <= transport
-- c_st_rec3_vector_2(highb).f3 after 10 ns,
-- c_st_rec3_vector_1(highb).f3 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3_vector(highb).f3 =
c_st_rec3_vector_2(highb).f3 and
(s_st_rec3_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3_vector(highb).f3 =
c_st_rec3_vector_1(highb).f3 and
(s_st_rec3_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00366.P3" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec3_vector_select <= transport 2 ;
-- s_st_rec3_vector(highb).f3 <= transport
-- c_st_rec3_vector_2(highb).f3 after 10 ns ,
-- c_st_rec3_vector_1(highb).f3 after 20 ns ,
-- c_st_rec3_vector_2(highb).f3 after 30 ns ,
-- c_st_rec3_vector_1(highb).f3 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3_vector(highb).f3 =
c_st_rec3_vector_2(highb).f3 and
(s_st_rec3_vector_savt + 10 ns) = Std.Standard.Now ;
st_rec3_vector_select <= transport 3 ;
-- s_st_rec3_vector(highb).f3 <= transport
-- c_st_rec3_vector_1(highb).f3 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3_vector(highb).f3 =
c_st_rec3_vector_1(highb).f3 and
(s_st_rec3_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00366" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00366" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00366" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_rec3_vector_savt <= transport Std.Standard.Now ;
chk_st_rec3_vector <= transport s_st_rec3_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec3_vector_cnt <= transport s_st_rec3_vector_cnt + 1 ;
--
end process CHG3 ;
--
PGEN_CHKP_3 :
process ( chk_st_rec3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Transport transactions completed entirely",
chk_st_rec3_vector = 4 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
s_st_rec3_vector(highb).f3 <= transport
c_st_rec3_vector_2(highb).f3 after 10 ns,
c_st_rec3_vector_1(highb).f3 after 20 ns
when st_rec3_vector_select = 1 else
--
c_st_rec3_vector_2(highb).f3 after 10 ns ,
c_st_rec3_vector_1(highb).f3 after 20 ns ,
c_st_rec3_vector_2(highb).f3 after 30 ns ,
c_st_rec3_vector_1(highb).f3 after 40 ns
when st_rec3_vector_select = 2 else
--
c_st_rec3_vector_1(highb).f3 after 5 ns ;
--
end ARCH00366 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00366_Test_Bench is
signal s_st_rec1_vector : st_rec1_vector
:= c_st_rec1_vector_1 ;
signal s_st_rec2_vector : st_rec2_vector
:= c_st_rec2_vector_1 ;
signal s_st_rec3_vector : st_rec3_vector
:= c_st_rec3_vector_1 ;
--
end ENT00366_Test_Bench ;
--
--
architecture ARCH00366_Test_Bench of ENT00366_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_rec1_vector : inout st_rec1_vector
; s_st_rec2_vector : inout st_rec2_vector
; s_st_rec3_vector : inout st_rec3_vector
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00366 ( ARCH00366 ) ;
begin
CIS1 : UUT
port map (
s_st_rec1_vector
, s_st_rec2_vector
, s_st_rec3_vector
)
;
end block L1 ;
end ARCH00366_Test_Bench ;
|
--------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2015
-- Entity: usb_cmd_pkg
-- Date:2015-01-18
-- Author: Gideon
-- Description: This package defines the commands that can be sent to the
-- sequencer.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.usb_pkg.all;
package usb_cmd_pkg is
-- Protocol Event
type t_usb_command is ( setup, out_data, in_request, ping );
type t_usb_result is ( res_data, res_ack, res_nak, res_nyet, res_stall, res_error );
type t_usb_cmd_req is record
request : std_logic;
-- command and modifiers (4 bits?)
command : t_usb_command;
do_split : std_logic;
do_data : std_logic;
-- data buffer controls (14 bits)
buffer_index : unsigned(1 downto 0);
data_length : unsigned(9 downto 0);
togglebit : std_logic;
no_data : std_logic;
-- USB addressing (11 bits)
device_addr : unsigned(6 downto 0);
endp_addr : unsigned(3 downto 0);
-- USB addressing (15 bits)
split_hub_addr : unsigned(6 downto 0);
split_port_addr : unsigned(3 downto 0); -- hubs with more than 16 ports are not supported
split_sc : std_logic; -- 0=start 1=complete
split_sp : std_logic; -- 0=full, 1=low
split_et : std_logic_vector(1 downto 0); -- 00=control, 01=iso, 10=bulk, 11=interrupt
end record;
type t_usb_cmd_resp is record
done : std_logic;
result : t_usb_result;
-- data descriptor
data_length : unsigned(9 downto 0);
togglebit : std_logic;
no_data : std_logic;
end record;
-- type t_usb_result_encoded is array (t_usb_result range<>) of std_logic_vector(2 downto 0);
-- constant c_usb_result_encoded : t_usb_result_encoded := (
-- res_data => "001",
-- res_ack => "010",
-- res_nak => "011",
-- res_nyet => "100",
-- res_error => "111" );
type t_usb_command_array is array(natural range <>) of t_usb_command;
constant c_usb_commands_decoded : t_usb_command_array(0 to 3) := ( setup, out_data, in_request, ping );
constant c_usb_cmd_init : t_usb_cmd_req := (
request => '0',
command => setup,
do_split => '0',
do_data => '0',
buffer_index => "00",
data_length => "0000000000",
togglebit => '0',
no_data => '1',
device_addr => "0000000",
endp_addr => X"0",
split_hub_addr => "0000000",
split_port_addr => X"0",
split_sc => '0',
split_sp => '0',
split_et => "00" );
function encode_result (pid : std_logic_vector(3 downto 0)) return t_usb_result;
end package;
package body usb_cmd_pkg is
function encode_result (pid : std_logic_vector(3 downto 0)) return t_usb_result is
variable res : t_usb_result;
begin
case pid is
when c_pid_ack => res := res_ack;
when c_pid_nak => res := res_nak;
when c_pid_nyet => res := res_nyet;
when c_pid_stall => res := res_stall;
when others => res := res_error;
end case;
return res;
end function;
end package body;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: debug
-- File: debug.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: Various debug utilities
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
package debug is
component grtestmod
generic (
halt : integer := 0;
width : integer := 32);
port (
resetn : in std_ulogic;
clk : in std_ulogic;
errorn : in std_ulogic;
address : in std_logic_vector(21 downto 2);
data : inout std_logic_vector(width-1 downto 0);
iosn : in std_ulogic;
oen : in std_ulogic;
writen : in std_ulogic;
brdyn : out std_ulogic;
bexcn : out std_ulogic;
state : out std_logic_vector(1 downto 0);
testdev : out std_logic_vector(19 downto 0);
subtest : out std_logic_vector(7 downto 0)
);
end component;
end;
|
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- avalon64_to_avalon8_0.vhd
-- This file was auto-generated as part of a generation operation.
-- If you edit it your changes will probably be lost.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity avalon64_to_avalon8_0 is
port (
address : in std_logic_vector(14 downto 0) := (others => '0'); -- avalon_slave_0.address
byteenable : in std_logic_vector(7 downto 0) := (others => '0'); -- .byteenable
writedata : in std_logic_vector(63 downto 0) := (others => '0'); -- .writedata
write : in std_logic := '0'; -- .write
readdata : out std_logic_vector(63 downto 0); -- .readdata
read : in std_logic := '0'; -- .read
waitrequest : out std_logic; -- .waitrequest
clk : in std_logic := '0'; -- clock.clk
rst : in std_logic := '0'; -- reset_sink.reset
out_address : out std_logic_vector(17 downto 0); -- conduit_end.export
out_writedata : out std_logic_vector(7 downto 0); -- .export
out_write : out std_logic; -- .export
out_readdata : in std_logic_vector(7 downto 0) := (others => '0'); -- .export
out_read : out std_logic; -- .export
out_waitrequest : in std_logic := '0' -- .export
);
end entity avalon64_to_avalon8_0;
architecture rtl of avalon64_to_avalon8_0 is
component avalon64_to_avalon8 is
generic (
OUT_ADDR_WIDTH : integer := 15
);
port (
address : in std_logic_vector(14 downto 0) := (others => 'X'); -- address
byteenable : in std_logic_vector(7 downto 0) := (others => 'X'); -- byteenable
writedata : in std_logic_vector(63 downto 0) := (others => 'X'); -- writedata
write : in std_logic := 'X'; -- write
readdata : out std_logic_vector(63 downto 0); -- readdata
read : in std_logic := 'X'; -- read
waitrequest : out std_logic; -- waitrequest
clk : in std_logic := 'X'; -- clk
rst : in std_logic := 'X'; -- reset
out_address : out std_logic_vector(17 downto 0); -- export
out_writedata : out std_logic_vector(7 downto 0); -- export
out_write : out std_logic; -- export
out_readdata : in std_logic_vector(7 downto 0) := (others => 'X'); -- export
out_read : out std_logic; -- export
out_waitrequest : in std_logic := 'X' -- export
);
end component avalon64_to_avalon8;
begin
avalon64_to_avalon8_0 : component avalon64_to_avalon8
generic map (
OUT_ADDR_WIDTH => 18
)
port map (
address => address, -- avalon_slave_0.address
byteenable => byteenable, -- .byteenable
writedata => writedata, -- .writedata
write => write, -- .write
readdata => readdata, -- .readdata
read => read, -- .read
waitrequest => waitrequest, -- .waitrequest
clk => clk, -- clock.clk
rst => rst, -- reset_sink.reset
out_address => out_address, -- conduit_end.export
out_writedata => out_writedata, -- .export
out_write => out_write, -- .export
out_readdata => out_readdata, -- .export
out_read => out_read, -- .export
out_waitrequest => out_waitrequest -- .export
);
end architecture rtl; -- of avalon64_to_avalon8_0
|
-- =================================================================================
-- // Name: Bryan Mason, James Batcheler, & Brad McMahon
-- // File: seg7dec
-- // Date: 12/9/2004
-- // Description: Display Component
-- // Class: CSE 378
-- =================================================================================
library IEEE;
use IEEE.std_logic_1164.all;
entity seg7dec is
port (
q : in STD_LOGIC_VECTOR(3 downto 0);
AtoG : out STD_LOGIC_VECTOR(6 downto 0));
end seg7dec;
architecture seg7dec_arch of seg7dec is
begin
process(q)
begin
case q is
when "0000" => AtoG <= "0000001";
when "0001" => AtoG <= "1001111";
when "0010" => AtoG <= "0010010";
when "0011" => AtoG <= "0000110";
when "0100" => AtoG <= "1001100";
when "0101" => AtoG <= "0100100";
when "0110" => AtoG <= "0100000";
when "0111" => AtoG <= "0001101";
when "1000" => AtoG <= "0000000";
when "1001" => AtoG <= "0000100";
when "1010" => AtoG <= "0001000";
when "1011" => AtoG <= "1100000";
when "1100" => AtoG <= "0110001";
when "1101" => AtoG <= "1000010";
when "1110" => AtoG <= "0110000";
when others => AtoG <= "0111000";
end case;
end process;
end seg7dec_arch;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:03:30 03/24/2014
-- Design Name:
-- Module Name: nmea_frame_extractor - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library work ;
use work.logi_utils_pack.all ;
entity nmea_frame_extractor is
generic(nmea_header : string := "$GPRMC");
port(
clk, reset : in std_logic ;
nmea_byte_in : in std_logic_vector(7 downto 0);
new_byte_in : in std_logic ;
nmea_byte_out : out std_logic_vector(7 downto 0);
new_byte_out : out std_logic;
frame_size : out std_logic_vector(7 downto 0);
end_of_frame : out std_logic;
frame_error : out std_logic
);
end nmea_frame_extractor;
architecture Behavioral of nmea_frame_extractor is
type parser_state is (CHECK_HEADER, RECEIVE_INFO, END_OF_DATA);
function headerEqVec(header : string; comp : slv8_array) return boolean is
variable eq : boolean := true ;
variable nmea_char : std_logic_vector(7 downto 0) ;
begin
for i in 0 to ((header'length)-1) loop
nmea_char := (std_logic_vector(to_unsigned( character'pos(header(i+1)), 8))) ;
eq := eq and (nmea_char = comp(i));
end loop ;
return eq ;
end headerEqVec ;
function validField(current : std_logic_vector; fields : slv8_array) return boolean is
variable eq : boolean := false ;
begin
for i in 0 to ((fields'length)-1) loop
eq := eq or (current = fields(i));
end loop ;
return eq ;
end validField ;
signal cur_state, next_state : parser_state ;
signal shift_reg : slv8_array(0 to nmea_header'length-1) ;
signal char_counter : std_logic_vector(7 downto 0) ;
signal compute_checksum : std_logic_vector(7 downto 0) ;
signal en_checksum, reset_checksum, checksum_good : std_logic ;
signal frame_checksum, frame_checksum_high, frame_checksum_low : std_logic_vector(7 downto 0) ;
begin
process(clk, reset)
begin
if reset = '1' then
shift_reg <= (others => (others => '0'));
elsif clk'event and clk = '1' then
if new_byte_in = '1' then
shift_reg(0 to 4) <= shift_reg(1 to 5) ;
shift_reg(5) <= nmea_byte_in ;
end if ;
end if ;
end process ;
process(clk, reset)
begin
if reset = '1' then
cur_state <= CHECK_HEADER;
elsif clk'event and clk = '1' then
cur_state <= next_state ;
end if ;
end process ;
process(cur_state, shift_reg)
begin
next_state <= cur_state;
case cur_state is
when CHECK_HEADER =>
if headerEqVec(nmea_header, shift_reg) then
next_state <= RECEIVE_INFO ;
end if ;
when RECEIVE_INFO =>
if checksum_good = '1' then -- buffer contains '*'
next_state <= END_OF_DATA ;
elsif shift_reg(0) = X"0D" or shift_reg(0) = X"0A" then -- buffer contains '\n' or '\t'
next_state <= CHECK_HEADER ;
end if ;
when END_OF_DATA =>
next_state <= CHECK_HEADER ;
when others =>
next_state <= CHECK_HEADER ;
end case ;
end process ;
process(clk, reset)
begin
if reset = '1'then
char_counter <= X"01" ;
elsif clk'event and clk = '1' then
if shift_reg(0) = X"24" then -- char is '$'
char_counter <= X"01";
elsif cur_state=RECEIVE_INFO and new_byte_in = '1' then -- counting char in frame
char_counter <= char_counter + 1 ;
end if ;
end if ;
end process ;
-- checksum handling ...
process(clk, reset)
begin
if reset = '1'then
compute_checksum <= X"00" ;
en_checksum <= '0' ;
elsif clk'event and clk = '1' then
-- $ is not in checksum
if new_byte_in = '1' and shift_reg(5) = X"24" then
compute_checksum <= X"00";
elsif en_checksum = '1' and new_byte_in = '1' and shift_reg(5) /= X"2A" then
compute_checksum <= compute_checksum xor shift_reg(5);
end if ;
if shift_reg(5) = X"24" then -- $ enables the checksum computation
en_checksum <= '1' ;
elsif shift_reg(5) = X"2A" then -- char is '*', end of
en_checksum <= '0' ;
end if ;
end if ;
end process ;
frame_checksum_high <= (shift_reg(1) - X"30") when shift_reg(1) < X"3A" else
(shift_reg(1) - X"37") ;
frame_checksum_low <= (shift_reg(2) - X"30") when shift_reg(2) < X"3A" else
(shift_reg(2) - X"37") ;
frame_checksum <= frame_checksum_high(3 downto 0) & frame_checksum_low(3 downto 0) ;
reset_checksum <= '1' when nmea_byte_in = X"24" else
'0' ;
checksum_good <= '1' when frame_checksum = compute_checksum and shift_reg(0) = X"2A" else
'0' ;
frame_error <= '1' when cur_state = RECEIVE_INFO and (shift_reg(0) = X"0D" or shift_reg(0) = X"0A") else
'0' ;
frame_size <= char_counter ;
end_of_frame <= '1' when cur_state = END_OF_DATA else
'0' ;
nmea_byte_out <= shift_reg(0) ;
new_byte_out <= new_byte_in when cur_state = RECEIVE_INFO else
'0' ;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:03:30 03/24/2014
-- Design Name:
-- Module Name: nmea_frame_extractor - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library work ;
use work.logi_utils_pack.all ;
entity nmea_frame_extractor is
generic(nmea_header : string := "$GPRMC");
port(
clk, reset : in std_logic ;
nmea_byte_in : in std_logic_vector(7 downto 0);
new_byte_in : in std_logic ;
nmea_byte_out : out std_logic_vector(7 downto 0);
new_byte_out : out std_logic;
frame_size : out std_logic_vector(7 downto 0);
end_of_frame : out std_logic;
frame_error : out std_logic
);
end nmea_frame_extractor;
architecture Behavioral of nmea_frame_extractor is
type parser_state is (CHECK_HEADER, RECEIVE_INFO, END_OF_DATA);
function headerEqVec(header : string; comp : slv8_array) return boolean is
variable eq : boolean := true ;
variable nmea_char : std_logic_vector(7 downto 0) ;
begin
for i in 0 to ((header'length)-1) loop
nmea_char := (std_logic_vector(to_unsigned( character'pos(header(i+1)), 8))) ;
eq := eq and (nmea_char = comp(i));
end loop ;
return eq ;
end headerEqVec ;
function validField(current : std_logic_vector; fields : slv8_array) return boolean is
variable eq : boolean := false ;
begin
for i in 0 to ((fields'length)-1) loop
eq := eq or (current = fields(i));
end loop ;
return eq ;
end validField ;
signal cur_state, next_state : parser_state ;
signal shift_reg : slv8_array(0 to nmea_header'length-1) ;
signal char_counter : std_logic_vector(7 downto 0) ;
signal compute_checksum : std_logic_vector(7 downto 0) ;
signal en_checksum, reset_checksum, checksum_good : std_logic ;
signal frame_checksum, frame_checksum_high, frame_checksum_low : std_logic_vector(7 downto 0) ;
begin
process(clk, reset)
begin
if reset = '1' then
shift_reg <= (others => (others => '0'));
elsif clk'event and clk = '1' then
if new_byte_in = '1' then
shift_reg(0 to 4) <= shift_reg(1 to 5) ;
shift_reg(5) <= nmea_byte_in ;
end if ;
end if ;
end process ;
process(clk, reset)
begin
if reset = '1' then
cur_state <= CHECK_HEADER;
elsif clk'event and clk = '1' then
cur_state <= next_state ;
end if ;
end process ;
process(cur_state, shift_reg)
begin
next_state <= cur_state;
case cur_state is
when CHECK_HEADER =>
if headerEqVec(nmea_header, shift_reg) then
next_state <= RECEIVE_INFO ;
end if ;
when RECEIVE_INFO =>
if checksum_good = '1' then -- buffer contains '*'
next_state <= END_OF_DATA ;
elsif shift_reg(0) = X"0D" or shift_reg(0) = X"0A" then -- buffer contains '\n' or '\t'
next_state <= CHECK_HEADER ;
end if ;
when END_OF_DATA =>
next_state <= CHECK_HEADER ;
when others =>
next_state <= CHECK_HEADER ;
end case ;
end process ;
process(clk, reset)
begin
if reset = '1'then
char_counter <= X"01" ;
elsif clk'event and clk = '1' then
if shift_reg(0) = X"24" then -- char is '$'
char_counter <= X"01";
elsif cur_state=RECEIVE_INFO and new_byte_in = '1' then -- counting char in frame
char_counter <= char_counter + 1 ;
end if ;
end if ;
end process ;
-- checksum handling ...
process(clk, reset)
begin
if reset = '1'then
compute_checksum <= X"00" ;
en_checksum <= '0' ;
elsif clk'event and clk = '1' then
-- $ is not in checksum
if new_byte_in = '1' and shift_reg(5) = X"24" then
compute_checksum <= X"00";
elsif en_checksum = '1' and new_byte_in = '1' and shift_reg(5) /= X"2A" then
compute_checksum <= compute_checksum xor shift_reg(5);
end if ;
if shift_reg(5) = X"24" then -- $ enables the checksum computation
en_checksum <= '1' ;
elsif shift_reg(5) = X"2A" then -- char is '*', end of
en_checksum <= '0' ;
end if ;
end if ;
end process ;
frame_checksum_high <= (shift_reg(1) - X"30") when shift_reg(1) < X"3A" else
(shift_reg(1) - X"37") ;
frame_checksum_low <= (shift_reg(2) - X"30") when shift_reg(2) < X"3A" else
(shift_reg(2) - X"37") ;
frame_checksum <= frame_checksum_high(3 downto 0) & frame_checksum_low(3 downto 0) ;
reset_checksum <= '1' when nmea_byte_in = X"24" else
'0' ;
checksum_good <= '1' when frame_checksum = compute_checksum and shift_reg(0) = X"2A" else
'0' ;
frame_error <= '1' when cur_state = RECEIVE_INFO and (shift_reg(0) = X"0D" or shift_reg(0) = X"0A") else
'0' ;
frame_size <= char_counter ;
end_of_frame <= '1' when cur_state = END_OF_DATA else
'0' ;
nmea_byte_out <= shift_reg(0) ;
new_byte_out <= new_byte_in when cur_state = RECEIVE_INFO else
'0' ;
end Behavioral;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: k7_bram4096x64_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY k7_bram4096x64_tb IS
END ENTITY;
ARCHITECTURE k7_bram4096x64_tb_ARCH OF k7_bram4096x64_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL CLKB : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
CLKB_GEN: PROCESS BEGIN
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY NOTE;
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "TEST PASS"
SEVERITY NOTE;
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
k7_bram4096x64_synth_inst:ENTITY work.k7_bram4096x64_synth
PORT MAP(
CLK_IN => CLK,
CLKB_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
------------------------------------------------------------------------------
-- Company: Red Diamond
-- Engineer: Alexander Geissler
--
-- Create Date: 23:40:00 11/27/2016
-- Design Name: i2s_pkg.vhd
-- Project Name: red-diamond
-- Target Device: EP4CE22C8N
-- Tool Versions: 16.0
-- Description: This I2S package contains a
--
-- Dependencies:
--
-- Revision:
-- Revision 0.1 - File created
-- Revision 0.2 - Added sinus lookup table creation
------------------------------------------------------------------------------
library ieee;
use ieee.math_real.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
package i2s_pkg is
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
constant c_addr : integer := 12;
type t_i2s_in is record
l_channel : std_logic_vector(23 downto 0);
r_channel : std_logic_vector(23 downto 0);
end record;
type t_i2s_out is record
wclk : std_ulogic;
bclk : std_ulogic;
sdata : std_logic;
end record;
type mem_array is array(0 to (2**c_addr)-1) of std_logic_vector(23 downto 0);
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
function cos_lut
return mem_array;
-------------------------------------------------------------------------------
-- Components
-------------------------------------------------------------------------------
component i2s_tx
port (
reset_n : in std_logic;
mclk : in std_logic;
--
i2s_in : in t_i2s_in;
i2s_out : out t_i2s_out
);
end component;
end i2s_pkg;
package body i2s_pkg is
function cos_lut
return mem_array is
constant N : integer := 2**c_addr;
constant N1 : real := real(N);
variable w, k1 : real;
variable memx : mem_array;
begin
for k in 0 to N-1 loop
k1 := (real(k)+0.5)/N1;
w := cos(math_pi_over_2 * k1); -- first quadrant of cosine wave
memx(k) := std_logic_vector(conv_signed(integer(round(8388608.0*w)),24));
end loop;
return memx;
end function cos_lut;
end;
|
library ieee;
use ieee.std_logic_1164.all;
entity dff05 is
port (q : out std_logic_vector(7 downto 0);
d : std_logic_vector(7 downto 0);
clk : std_logic);
end dff05;
architecture behav of dff05 is
begin
process (clk) is
begin
if rising_edge (clk) then
if d (7) = '1' then
q (0) <= d (0);
else
q (2) <= d (2);
end if;
end if;
end process;
end behav;
|
architecture RTL of FIFO is
begin
process is
begin
end process;
process (a) is
begin
end process;
-- Violations below
process is
begin
end process;
process (a)is
begin
end process;
process (a) is
begin
end process;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_563 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_563;
architecture augh of sub_563 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_563 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end sub_563;
architecture augh of sub_563 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '0' - CI
-- If CI is not present, the operation is '0' - '0'
carry_inA <= '0' & in_a & '0';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) - unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
|
-------------------------------------------------------------------------------
--! @file toplevel.vhd
--
--! @brief Toplevel of Nios CN FPGA directIO part
--
--! @details This is the toplevel of the Nios CN FPGA directIO design for the
--! INK DE2-115 Evaluation Board.
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2013
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library libcommon;
use libcommon.global.all;
entity toplevel is
port (
-- 50 MHZ CLK IN
EXT_CLK : in std_logic;
-- PHY Interfaces
PHY_GXCLK : out std_logic_vector(1 downto 0);
PHY_RXCLK : in std_logic_vector(1 downto 0);
PHY_RXER : in std_logic_vector(1 downto 0);
PHY_RXDV : in std_logic_vector(1 downto 0);
PHY_RXD : in std_logic_vector(7 downto 0);
PHY_TXCLK : in std_logic_vector(1 downto 0);
PHY_TXER : out std_logic_vector(1 downto 0);
PHY_TXEN : out std_logic_vector(1 downto 0);
PHY_TXD : out std_logic_vector(7 downto 0);
PHY_MDIO : inout std_logic_vector(1 downto 0);
PHY_MDC : out std_logic_vector(1 downto 0);
PHY_RESET_n : out std_logic_vector(1 downto 0);
-- EPCS
EPCS_DCLK : out std_logic;
EPCS_SCE : out std_logic;
EPCS_SDO : out std_logic;
EPCS_DATA0 : in std_logic;
-- 2 MB SRAM
SRAM_CE_n : out std_logic;
SRAM_OE_n : out std_logic;
SRAM_WE_n : out std_logic;
SRAM_ADDR : out std_logic_vector(20 downto 1);
SRAM_BE_n : out std_logic_vector(1 downto 0);
SRAM_DQ : inout std_logic_vector(15 downto 0);
-- NODE_SWITCH
NODE_SWITCH : in std_logic_vector(7 downto 0);
-- KEY
KEY : in std_logic_vector(3 downto 0);
-- LED
LEDG : out std_logic_vector(7 downto 0);
LEDR : out std_logic_vector(15 downto 0);
-- HEX LED
HEX0 : out std_logic_vector(6 downto 0);
HEX1 : out std_logic_vector(6 downto 0);
HEX2 : out std_logic_vector(6 downto 0);
HEX3 : out std_logic_vector(6 downto 0);
HEX4 : out std_logic_vector(6 downto 0);
HEX5 : out std_logic_vector(6 downto 0);
HEX6 : out std_logic_vector(6 downto 0);
HEX7 : out std_logic_vector(6 downto 0);
-- BENCHMARK_OUT
BENCHMARK : out std_logic_vector(7 downto 0);
-- LCD
LCD_ON : out std_logic;
LCD_BLON : out std_logic;
LCD_DQ : inout std_logic_vector(7 downto 0);
LCD_E : out std_logic;
LCD_RS : out std_logic;
LCD_RW : out std_logic
);
end toplevel;
architecture rtl of toplevel is
component cnSingleGpio is
port (
clk25_clk : in std_logic := 'X';
clk50_clk : in std_logic := 'X';
reset_reset_n : in std_logic := 'X';
clk100_clk : in std_logic := 'X';
-- SRAM
tri_state_0_tcm_address_out : out std_logic_vector(20 downto 0);
tri_state_0_tcm_byteenable_n_out : out std_logic_vector(1 downto 0);
tri_state_0_tcm_read_n_out : out std_logic;
tri_state_0_tcm_write_n_out : out std_logic;
tri_state_0_tcm_data_out : inout std_logic_vector(15 downto 0) := (others => 'X');
tri_state_0_tcm_chipselect_n_out : out std_logic;
-- OPENMAC
openmac_0_mii_txEnable : out std_logic_vector(1 downto 0);
openmac_0_mii_txData : out std_logic_vector(7 downto 0);
openmac_0_mii_txClk : in std_logic_vector(1 downto 0) := (others => 'X');
openmac_0_mii_rxError : in std_logic_vector(1 downto 0) := (others => 'X');
openmac_0_mii_rxDataValid : in std_logic_vector(1 downto 0) := (others => 'X');
openmac_0_mii_rxData : in std_logic_vector(7 downto 0) := (others => 'X');
openmac_0_mii_rxClk : in std_logic_vector(1 downto 0) := (others => 'X');
openmac_0_smi_nPhyRst : out std_logic_vector(1 downto 0);
openmac_0_smi_clk : out std_logic_vector(1 downto 0);
openmac_0_smi_dio : inout std_logic_vector(1 downto 0) := (others => 'X');
-- BENCHMARK
pcp_0_benchmark_pio_export : out std_logic_vector(7 downto 0);
-- EPCS
epcs_flash_dclk : out std_logic;
epcs_flash_sce : out std_logic;
epcs_flash_sdo : out std_logic;
epcs_flash_data0 : in std_logic := 'X';
-- LCD
lcd_data : inout std_logic_vector(7 downto 0) := (others => 'X');
lcd_E : out std_logic;
lcd_RS : out std_logic;
lcd_RW : out std_logic;
-- NODE SWITCH
node_switch_pio_export : in std_logic_vector(7 downto 0) := (others => 'X');
-- STATUS ERROR LED
status_led_pio_export : out std_logic_vector(1 downto 0);
-- HEX
hex_pio_export : out std_logic_vector(31 downto 0);
-- LEDR
ledr_pio_export : out std_logic_vector(15 downto 0);
-- KEY
key_pio_export : in std_logic_vector(3 downto 0) := (others => 'X')
);
end component cnSingleGpio;
-- PLL component
component pll
port (
inclk0 : in std_logic;
c0 : out std_logic;
c1 : out std_logic;
c2 : out std_logic;
c3 : out std_logic;
locked : out std_logic
);
end component;
signal clk25 : std_logic;
signal clk50 : std_logic;
signal clk100 : std_logic;
signal pllLocked : std_logic;
signal sramAddr : std_logic_vector(SRAM_ADDR'high downto 0);
signal plk_status_error : std_logic_vector(1 downto 0);
type tSevenSegArray is array (natural range <>) of std_logic_vector(6 downto 0);
constant cNumberOfHex : natural := 8;
signal hex : std_logic_vector(cNumberOfHex*4-1 downto 0);
signal sevenSegArray : tSevenSegArray(cNumberOfHex-1 downto 0);
begin
SRAM_ADDR <= sramAddr(SRAM_ADDR'range);
PHY_GXCLK <= (others => '0');
PHY_TXER <= (others => '0');
LCD_ON <= '1';
LCD_BLON <= '1';
LEDG <= "000000" & plk_status_error;
inst : component cnSingleGpio
port map (
clk25_clk => clk25,
clk50_clk => clk50,
clk100_clk => clk100,
reset_reset_n => pllLocked,
openmac_0_mii_txEnable => PHY_TXEN,
openmac_0_mii_txData => PHY_TXD,
openmac_0_mii_txClk => PHY_TXCLK,
openmac_0_mii_rxError => PHY_RXER,
openmac_0_mii_rxDataValid => PHY_RXDV,
openmac_0_mii_rxData => PHY_RXD,
openmac_0_mii_rxClk => PHY_RXCLK,
openmac_0_smi_nPhyRst => PHY_RESET_n,
openmac_0_smi_clk => PHY_MDC,
openmac_0_smi_dio => PHY_MDIO,
tri_state_0_tcm_address_out => sramAddr,
tri_state_0_tcm_read_n_out => SRAM_OE_n,
tri_state_0_tcm_byteenable_n_out => SRAM_BE_n,
tri_state_0_tcm_write_n_out => SRAM_WE_n,
tri_state_0_tcm_data_out => SRAM_DQ,
tri_state_0_tcm_chipselect_n_out => SRAM_CE_n,
pcp_0_benchmark_pio_export => BENCHMARK,
epcs_flash_dclk => EPCS_DCLK,
epcs_flash_sce => EPCS_SCE,
epcs_flash_sdo => EPCS_SDO,
epcs_flash_data0 => EPCS_DATA0,
node_switch_pio_export => NODE_SWITCH,
status_led_pio_export => plk_status_error,
lcd_data => LCD_DQ,
lcd_E => LCD_E,
lcd_RS => LCD_RS,
lcd_RW => LCD_RW,
hex_pio_export => hex,
ledr_pio_export => LEDR,
key_pio_export => KEY
);
-- Pll Instance
pllInst : pll
port map (
inclk0 => EXT_CLK,
c0 => clk50,
c1 => clk100,
c2 => clk25,
c3 => open,
locked => pllLocked
);
-- bcd to 7 segment
genBcdTo7Seg : for i in cNumberOfHex-1 downto 0 generate
signal tmpHex : std_logic_vector(3 downto 0);
signal tmpSev : std_logic_vector(6 downto 0);
begin
tmpHex <= hex((i+1)*4-1 downto i*4);
sevenSegArray(i) <= tmpSev;
bcdTo7Seg0 : entity libcommon.bcd2led
port map (
iBcdVal => tmpHex,
oLed => open,
onLed => tmpSev
);
end generate genBcdTo7Seg;
-- assign outports to array
HEX0 <= sevenSegArray(0);
HEX1 <= sevenSegArray(1);
HEX2 <= sevenSegArray(2);
HEX3 <= sevenSegArray(3);
HEX4 <= sevenSegArray(4);
HEX5 <= sevenSegArray(5);
HEX6 <= sevenSegArray(6);
HEX7 <= sevenSegArray(7);
end rtl;
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/ifft_16_bit/RADIX22FFT_SDNF1_1_block.vhd
-- Created: 2017-03-28 01:00:37
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF1_1_block
-- Source Path: ifft_16_bit/IFFT HDL Optimized/RADIX22FFT_SDNF1_1
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY RADIX22FFT_SDNF1_1_block IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
twdlXdin_2_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_2_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_10_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_10_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_3_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_3_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_4_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_4_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_3_vld : OUT std_logic
);
END RADIX22FFT_SDNF1_1_block;
ARCHITECTURE rtl OF RADIX22FFT_SDNF1_1_block IS
-- Signals
SIGNAL twdlXdin_2_re_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL twdlXdin_2_im_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL twdlXdin_10_re_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL twdlXdin_10_im_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 : std_logic;
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next : std_logic;
SIGNAL dout_3_re_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_3_im_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_4_re_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_4_im_tmp : signed(16 DOWNTO 0); -- sfix17
BEGIN
twdlXdin_2_re_signed <= signed(twdlXdin_2_re);
twdlXdin_2_im_signed <= signed(twdlXdin_2_im);
twdlXdin_10_re_signed <= signed(twdlXdin_10_re);
twdlXdin_10_im_signed <= signed(twdlXdin_10_im);
-- Radix22ButterflyG1_NF
Radix22ButterflyG1_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG1_NF_btf1_im_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG1_NF_btf2_re_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG1_NF_btf2_im_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= Radix22ButterflyG1_NF_btf1_re_reg_next;
Radix22ButterflyG1_NF_btf1_im_reg <= Radix22ButterflyG1_NF_btf1_im_reg_next;
Radix22ButterflyG1_NF_btf2_re_reg <= Radix22ButterflyG1_NF_btf2_re_reg_next;
Radix22ButterflyG1_NF_btf2_im_reg <= Radix22ButterflyG1_NF_btf2_im_reg_next;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG1_NF_process;
Radix22ButterflyG1_NF_output : PROCESS (Radix22ButterflyG1_NF_btf1_re_reg, Radix22ButterflyG1_NF_btf1_im_reg,
Radix22ButterflyG1_NF_btf2_re_reg, Radix22ButterflyG1_NF_btf2_im_reg,
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1, twdlXdin_2_re_signed,
twdlXdin_2_im_signed, twdlXdin_10_re_signed, twdlXdin_10_im_signed,
twdlXdin_1_vld)
VARIABLE sra_temp : signed(17 DOWNTO 0);
VARIABLE sra_temp_0 : signed(17 DOWNTO 0);
VARIABLE sra_temp_1 : signed(17 DOWNTO 0);
VARIABLE sra_temp_2 : signed(17 DOWNTO 0);
BEGIN
Radix22ButterflyG1_NF_btf1_re_reg_next <= Radix22ButterflyG1_NF_btf1_re_reg;
Radix22ButterflyG1_NF_btf1_im_reg_next <= Radix22ButterflyG1_NF_btf1_im_reg;
Radix22ButterflyG1_NF_btf2_re_reg_next <= Radix22ButterflyG1_NF_btf2_re_reg;
Radix22ButterflyG1_NF_btf2_im_reg_next <= Radix22ButterflyG1_NF_btf2_im_reg;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next <= twdlXdin_1_vld;
IF twdlXdin_1_vld = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg_next <= resize(twdlXdin_2_re_signed, 18) + resize(twdlXdin_10_re_signed, 18);
Radix22ButterflyG1_NF_btf2_re_reg_next <= resize(twdlXdin_2_re_signed, 18) - resize(twdlXdin_10_re_signed, 18);
Radix22ButterflyG1_NF_btf1_im_reg_next <= resize(twdlXdin_2_im_signed, 18) + resize(twdlXdin_10_im_signed, 18);
Radix22ButterflyG1_NF_btf2_im_reg_next <= resize(twdlXdin_2_im_signed, 18) - resize(twdlXdin_10_im_signed, 18);
END IF;
sra_temp := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf1_re_reg, 1);
dout_3_re_tmp <= sra_temp(16 DOWNTO 0);
sra_temp_0 := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf1_im_reg, 1);
dout_3_im_tmp <= sra_temp_0(16 DOWNTO 0);
sra_temp_1 := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf2_re_reg, 1);
dout_4_re_tmp <= sra_temp_1(16 DOWNTO 0);
sra_temp_2 := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf2_im_reg, 1);
dout_4_im_tmp <= sra_temp_2(16 DOWNTO 0);
dout_3_vld <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1;
END PROCESS Radix22ButterflyG1_NF_output;
dout_3_re <= std_logic_vector(dout_3_re_tmp);
dout_3_im <= std_logic_vector(dout_3_im_tmp);
dout_4_re <= std_logic_vector(dout_4_re_tmp);
dout_4_im <= std_logic_vector(dout_4_im_tmp);
END rtl;
|
--======================================================================
-- timer.vhd :: A simple 16-bit Timer
--
-- (c) Scott L. Baker, Sierra Circuit Design
--======================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity TIMER is
port(
CS : in std_logic; -- chip select
WE : in std_logic; -- write enable
WR_DATA : in std_logic_vector(15 downto 0); -- write data
RD_DATA : out std_logic_vector(15 downto 0); -- read data
IRQ : out std_logic; -- Timer Interrupt
SEL_IC : in std_logic; -- select initial count
RESET : in std_logic; -- system reset
FCLK : in std_logic -- fast clock
);
end entity TIMER;
architecture BEHAVIORAL of TIMER is
--=================================================================
-- Signal definitions
--=================================================================
-- Registers
signal IC_REG : std_logic_vector(15 downto 0); -- initial count
-- Counters
signal PRE : std_logic_vector(14 downto 0); -- prescaler
signal CTR : std_logic_vector(15 downto 0); -- timer count
-- Counter Control
signal PEN : std_logic; -- Prescaler count enable
signal CEN : std_logic; -- Timer count enable
signal DBG : std_logic; -- Debug mode (no prescaler)
signal TRQ : std_logic; -- Timer interrupt
signal LOAD : std_logic; -- load counter
-- Terminal Counts
signal TC : std_logic; -- Timer terminal count
-- Terminal Count Constant
constant PRE_TC : std_logic_vector(14 downto 0) := "100101011100000";
constant DBG_TC : std_logic_vector(14 downto 0) := "000010101010101";
begin
--=============================================
-- Register Writes
--=============================================
REGISTER_WRITES:
process (FCLK)
begin
if (FCLK = '0' and FCLK'event) then
LOAD <= '0';
if (CS = '1' and WE = '1') then
if (SEL_IC = '1') then
IC_REG <= WR_DATA;
LOAD <= '1';
else
TRQ <= '0';
DBG <= WR_DATA(1);
CEN <= WR_DATA(0);
end if;
end if;
-- set timer interrupt
if (TC = '1') then
TRQ <= '1';
end if;
if (RESET = '1') then
TRQ <= '0';
DBG <= '0';
CEN <= '0';
IC_REG <= (others => '0');
end if;
end if;
end process;
IRQ <= TRQ;
RD_DATA <= "000000000000000" & TRQ;
--==================================================
-- Prescaler (divide by 16000)
--==================================================
PRESCALER:
process (FCLK)
begin
if (FCLK = '0' and FCLK'event) then
PEN <= '0';
-- If the counter is enabled then count
if (CEN = '1') then
-- linear-feedback counter
PRE(0) <= PRE(14) xnor PRE(0);
PRE(14 downto 1) <= PRE(13 downto 0);
-- use PRE_TC terminal count for 1-msec
-- use DBG_TC terminal count for debug
if (((DBG = '0') and (PRE = PRE_TC)) or
((DBG = '1') and (PRE = DBG_TC))) then
PRE <= (others => '0');
PEN <= '1';
end if;
end if;
-- reset state
if (RESET = '1') then
PRE <= (others => '0');
PEN <= '0';
end if;
end if;
end process;
--==================================================
-- Timer
--==================================================
TIMER_COUNTER:
process (FCLK)
begin
if (FCLK = '0' and FCLK'event) then
TC <= '0';
-- count at each prescaler terminal count
if (PEN = '1') then
CTR <= CTR - 1;
end if;
-- terminal count
if ((PEN = '1') and (CTR = "0000000000000001")) then
TC <= '1';
-- Reload the counter when the
-- terminal count is reached
CTR <= IC_REG;
end if;
-- load the counter on uP write
if (LOAD = '1') then
CTR <= IC_REG;
end if;
-- reset state
if (RESET = '1') then
CTR <= (others => '1');
TC <= '0';
end if;
end if;
end process;
end architecture BEHAVIORAL;
|
--======================================================================
-- timer.vhd :: A simple 16-bit Timer
--
-- (c) Scott L. Baker, Sierra Circuit Design
--======================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity TIMER is
port(
CS : in std_logic; -- chip select
WE : in std_logic; -- write enable
WR_DATA : in std_logic_vector(15 downto 0); -- write data
RD_DATA : out std_logic_vector(15 downto 0); -- read data
IRQ : out std_logic; -- Timer Interrupt
SEL_IC : in std_logic; -- select initial count
RESET : in std_logic; -- system reset
FCLK : in std_logic -- fast clock
);
end entity TIMER;
architecture BEHAVIORAL of TIMER is
--=================================================================
-- Signal definitions
--=================================================================
-- Registers
signal IC_REG : std_logic_vector(15 downto 0); -- initial count
-- Counters
signal PRE : std_logic_vector(14 downto 0); -- prescaler
signal CTR : std_logic_vector(15 downto 0); -- timer count
-- Counter Control
signal PEN : std_logic; -- Prescaler count enable
signal CEN : std_logic; -- Timer count enable
signal DBG : std_logic; -- Debug mode (no prescaler)
signal TRQ : std_logic; -- Timer interrupt
signal LOAD : std_logic; -- load counter
-- Terminal Counts
signal TC : std_logic; -- Timer terminal count
-- Terminal Count Constant
constant PRE_TC : std_logic_vector(14 downto 0) := "100101011100000";
constant DBG_TC : std_logic_vector(14 downto 0) := "000010101010101";
begin
--=============================================
-- Register Writes
--=============================================
REGISTER_WRITES:
process (FCLK)
begin
if (FCLK = '0' and FCLK'event) then
LOAD <= '0';
if (CS = '1' and WE = '1') then
if (SEL_IC = '1') then
IC_REG <= WR_DATA;
LOAD <= '1';
else
TRQ <= '0';
DBG <= WR_DATA(1);
CEN <= WR_DATA(0);
end if;
end if;
-- set timer interrupt
if (TC = '1') then
TRQ <= '1';
end if;
if (RESET = '1') then
TRQ <= '0';
DBG <= '0';
CEN <= '0';
IC_REG <= (others => '0');
end if;
end if;
end process;
IRQ <= TRQ;
RD_DATA <= "000000000000000" & TRQ;
--==================================================
-- Prescaler (divide by 16000)
--==================================================
PRESCALER:
process (FCLK)
begin
if (FCLK = '0' and FCLK'event) then
PEN <= '0';
-- If the counter is enabled then count
if (CEN = '1') then
-- linear-feedback counter
PRE(0) <= PRE(14) xnor PRE(0);
PRE(14 downto 1) <= PRE(13 downto 0);
-- use PRE_TC terminal count for 1-msec
-- use DBG_TC terminal count for debug
if (((DBG = '0') and (PRE = PRE_TC)) or
((DBG = '1') and (PRE = DBG_TC))) then
PRE <= (others => '0');
PEN <= '1';
end if;
end if;
-- reset state
if (RESET = '1') then
PRE <= (others => '0');
PEN <= '0';
end if;
end if;
end process;
--==================================================
-- Timer
--==================================================
TIMER_COUNTER:
process (FCLK)
begin
if (FCLK = '0' and FCLK'event) then
TC <= '0';
-- count at each prescaler terminal count
if (PEN = '1') then
CTR <= CTR - 1;
end if;
-- terminal count
if ((PEN = '1') and (CTR = "0000000000000001")) then
TC <= '1';
-- Reload the counter when the
-- terminal count is reached
CTR <= IC_REG;
end if;
-- load the counter on uP write
if (LOAD = '1') then
CTR <= IC_REG;
end if;
-- reset state
if (RESET = '1') then
CTR <= (others => '1');
TC <= '0';
end if;
end if;
end process;
end architecture BEHAVIORAL;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_a_e
--
-- Generated
-- by: wig
-- on: Mon Mar 5 13:21:41 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl -variant Calculate -nodelta ../../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_a_e-rtl-conf-c.vhd,v 1.1 2007/03/05 13:22:44 wig Exp $
-- $Date: 2007/03/05 13:22:44 $
-- $Log: inst_a_e-rtl-conf-c.vhd,v $
-- Revision 1.1 2007/03/05 13:22:44 wig
-- Added testcase for selection of macros with ::variant switch
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.104 2007/03/03 17:24:06 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_a_e_rtl_conf / inst_a_e
--
configuration inst_a_e_rtl_conf of inst_a_e is
for rtl
-- Generated Configuration
for inst_1 : inst_1_e
use configuration work.inst_1_e_rtl_conf;
end for;
for inst_10 : inst_10_e
use configuration work.inst_10_e_rtl_conf;
end for;
for inst_2 : inst_2_e
use configuration work.inst_2_e_rtl_conf;
end for;
for inst_6 : inst_6_e
use configuration work.inst_6_e_rtl_conf;
end for;
for inst_7 : inst_7_e
use configuration work.inst_7_e_rtl_conf;
end for;
for inst_8 : inst_8_e
use configuration work.inst_8_e_rtl_conf;
end for;
for inst_9 : inst_9_e
use configuration work.inst_9_e_rtl_conf;
end for;
end for;
end inst_a_e_rtl_conf;
--
-- End of Generated Configuration inst_a_e_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2322.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p01n01i02322ent IS
END c07s02b07x00p01n01i02322ent;
ARCHITECTURE c07s02b07x00p01n01i02322arch OF c07s02b07x00p01n01i02322ent IS
BEGIN
TESTING: PROCESS
type WORD is array(0 to 31) of BIT;
type WORDPTR is access WORD;
variable WORDPTRV : WORDPTR;
BEGIN
WORDPTRV := ABS WORDPTRV;
assert FALSE
report "***FAILED TEST: c07s02b07x00p01n01i02322 - Unary operator abs is predefined for any numeric type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p01n01i02322arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2322.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p01n01i02322ent IS
END c07s02b07x00p01n01i02322ent;
ARCHITECTURE c07s02b07x00p01n01i02322arch OF c07s02b07x00p01n01i02322ent IS
BEGIN
TESTING: PROCESS
type WORD is array(0 to 31) of BIT;
type WORDPTR is access WORD;
variable WORDPTRV : WORDPTR;
BEGIN
WORDPTRV := ABS WORDPTRV;
assert FALSE
report "***FAILED TEST: c07s02b07x00p01n01i02322 - Unary operator abs is predefined for any numeric type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p01n01i02322arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2322.vhd,v 1.2 2001-10-26 16:30:17 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p01n01i02322ent IS
END c07s02b07x00p01n01i02322ent;
ARCHITECTURE c07s02b07x00p01n01i02322arch OF c07s02b07x00p01n01i02322ent IS
BEGIN
TESTING: PROCESS
type WORD is array(0 to 31) of BIT;
type WORDPTR is access WORD;
variable WORDPTRV : WORDPTR;
BEGIN
WORDPTRV := ABS WORDPTRV;
assert FALSE
report "***FAILED TEST: c07s02b07x00p01n01i02322 - Unary operator abs is predefined for any numeric type only."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p01n01i02322arch;
|
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY EmptyUnitWithSpi IS
PORT(
spi_clk : IN STD_LOGIC;
spi_cs : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
spi_miso : OUT STD_LOGIC;
spi_mosi : IN STD_LOGIC
);
END ENTITY;
ARCHITECTURE rtl OF EmptyUnitWithSpi IS
BEGIN
spi_miso <= 'X';
END ARCHITECTURE;
|
-- $Id: fifo_2c_dram2.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Module Name: fifo_2c_dram2 - syn
-- Description: FIFO, two clock domain, distributed RAM based, with
-- enable/busy/valid/hold interface.
--
-- Dependencies: ram_1swar_1ar_gen
-- genlib/gray_cnt_n
-- genlib/gray2bin_gen
--
-- Test bench: tb/tb_fifo_2c_dram
-- Target Devices: generic
-- Tool versions: viv 2015.4-2018.3; ghdl 0.33-0.35 !! NOT FOR ISE !!
-- Note: for usage with ISE use fifo_2c_dram
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-03-24 751 1.0 Initial version (derived from fifo_2c_dram, is
-- exactly same logic, re-written to allow proper
-- usage of vivado constraints)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.genlib.all;
use work.memlib.all;
entity fifo_2c_dram2 is -- fifo, 2 clock, dram based (v2)
generic (
AWIDTH : positive := 5; -- address width (sets size)
DWIDTH : positive := 16); -- data width
port (
CLKW : in slbit; -- clock (write side)
CLKR : in slbit; -- clock (read side)
RESETW : in slbit; -- W|reset from write side
RESETR : in slbit; -- R|reset from read side
DI : in slv(DWIDTH-1 downto 0); -- W|input data
ENA : in slbit; -- W|write enable
BUSY : out slbit; -- W|write port hold
DO : out slv(DWIDTH-1 downto 0); -- R|output data
VAL : out slbit; -- R|read valid
HOLD : in slbit; -- R|read hold
SIZEW : out slv(AWIDTH-1 downto 0); -- W|number slots to write
SIZER : out slv(AWIDTH-1 downto 0) -- R|number slots to read
);
end fifo_2c_dram2;
architecture syn of fifo_2c_dram2 is
subtype a_range is integer range AWIDTH-1 downto 0; -- addr value regs
signal RW_RADDR_S0 : slv(a_range) := (others=>'0'); -- read addr: CLKR->CLKW
signal RW_RADDR_S1 : slv(a_range) := (others=>'0'); -- read addr: CLKW->CLKW
signal RW_SIZEW : slv(a_range) := (others=>'0'); -- slots to write
signal RW_BUSY : slbit := '0'; -- busy flag
signal RW_RSTW : slbit := '0'; -- resetw active
signal RW_RSTW_E_S0 : slbit := '0'; -- rstw-echo: CLKR->CLKW
signal RW_RSTW_E_S1 : slbit := '0'; -- rstw-echo: CLKW->CLKW
signal RW_RSTR_S0 : slbit := '0'; -- resetr: CLKR->CLKW
signal RW_RSTR_S1 : slbit := '0'; -- resetr: CLKW->CLKW
signal NW_SIZEW : slv(a_range) := (others=>'0'); -- slots to write
signal NW_BUSY : slbit := '0'; -- busy flag
signal NW_RSTW : slbit := '0'; -- resetw active
signal RR_WADDR_S0 : slv(a_range) := (others=>'0'); -- write addr: CLKW->CLKR
signal RR_WADDR_S1 : slv(a_range) := (others=>'0'); -- write addr: CLKR->CLKR
signal RR_SIZER : slv(a_range) := (others=>'0'); -- slots to read
signal RR_VAL: slbit := '0'; -- valid flag
signal RR_RSTR : slbit := '0'; -- resetr active
signal RR_RSTR_E_S0 : slbit := '0'; -- rstr-echo: CLKW->CLKR
signal RR_RSTR_E_S1 : slbit := '0'; -- rstr-echo: CLKR->CLKR
signal RR_RSTW_S0 : slbit := '0'; -- resetw: CLKW->CLKR
signal RR_RSTW_S1 : slbit := '0'; -- resetw: CLKR->CLKR
signal NR_SIZER : slv(a_range) := (others=>'0'); -- slots to read
signal NR_VAL: slbit := '0'; -- valid flag
signal NR_RSTR : slbit := '0'; -- resetr active
signal WADDR : slv(AWIDTH-1 downto 0) := (others=>'0');
signal RADDR : slv(AWIDTH-1 downto 0) := (others=>'0');
signal WADDR_BIN_W : slv(AWIDTH-1 downto 0) := (others=>'0');
signal RADDR_BIN_R : slv(AWIDTH-1 downto 0) := (others=>'0');
signal WADDR_BIN_R : slv(AWIDTH-1 downto 0) := (others=>'0');
signal RADDR_BIN_W : slv(AWIDTH-1 downto 0) := (others=>'0');
signal GCW_RST : slbit := '0';
signal GCW_CE : slbit := '0';
signal GCR_RST : slbit := '0';
signal GCR_CE : slbit := '0';
attribute ASYNC_REG: string;
attribute ASYNC_REG of RW_RADDR_S0 : signal is "true";
attribute ASYNC_REG of RW_RADDR_S1 : signal is "true";
attribute ASYNC_REG of RW_RSTW_E_S0 : signal is "true";
attribute ASYNC_REG of RW_RSTW_E_S1 : signal is "true";
attribute ASYNC_REG of RW_RSTR_S0 : signal is "true";
attribute ASYNC_REG of RW_RSTR_S1 : signal is "true";
attribute ASYNC_REG of RR_WADDR_S0 : signal is "true";
attribute ASYNC_REG of RR_WADDR_S1 : signal is "true";
attribute ASYNC_REG of RR_RSTR_E_S0 : signal is "true";
attribute ASYNC_REG of RR_RSTR_E_S1 : signal is "true";
attribute ASYNC_REG of RR_RSTW_S0 : signal is "true";
attribute ASYNC_REG of RR_RSTW_S1 : signal is "true";
begin
RAM : ram_1swar_1ar_gen -- dual ported memory
generic map (
AWIDTH => AWIDTH,
DWIDTH => DWIDTH)
port map (
CLK => CLKW,
WE => GCW_CE,
ADDRA => WADDR,
ADDRB => RADDR,
DI => DI,
DOA => open,
DOB => DO
);
GCW : gray_cnt_gen -- gray counter for write address
generic map (
DWIDTH => AWIDTH)
port map (
CLK => CLKW,
RESET => GCW_RST,
CE => GCW_CE,
DATA => WADDR
);
GCR : gray_cnt_gen -- gray counter for read address
generic map (
DWIDTH => AWIDTH)
port map (
CLK => CLKR,
RESET => GCR_RST,
CE => GCR_CE,
DATA => RADDR
);
G2B_WW : gray2bin_gen -- gray->bin for waddr on write side
generic map (DWIDTH => AWIDTH)
port map (DI => WADDR, DO => WADDR_BIN_W);
G2B_WR : gray2bin_gen -- gray->bin for waddr on read side
generic map (DWIDTH => AWIDTH)
port map (DI => RR_WADDR_S1, DO => WADDR_BIN_R);
G2B_RR : gray2bin_gen -- gray->bin for raddr on read side
generic map (DWIDTH => AWIDTH)
port map (DI => RADDR, DO => RADDR_BIN_R);
G2B_RW : gray2bin_gen -- gray->bin for raddr on write side
generic map (DWIDTH => AWIDTH)
port map (DI => RW_RADDR_S1, DO => RADDR_BIN_W);
--
-- write side --------------------------------------------------------------
--
proc_regw: process (CLKW)
begin
if rising_edge(CLKW) then
RW_RADDR_S0 <= RADDR; -- sync 0: CLKR->CLKW
RW_RADDR_S1 <= RW_RADDR_S0; -- sync 1: CLKW
RW_SIZEW <= NW_SIZEW;
RW_BUSY <= NW_BUSY;
RW_RSTW <= NW_RSTW;
RW_RSTW_E_S0 <= RR_RSTW_S1; -- sync 0: CLKR->CLKW
RW_RSTW_E_S1 <= RW_RSTW_E_S0; -- sync 1: CLKW
RW_RSTR_S0 <= RR_RSTR; -- sync 0: CLKR->CLKW
RW_RSTR_S1 <= RW_RSTR_S0; -- sync 1: CLKW
end if;
end process proc_regw;
proc_nextw: process (RW_BUSY, RW_SIZEW, RW_RSTW, RW_RSTW_E_S1, RW_RSTR_S1,
ENA, RESETW, RADDR_BIN_W, WADDR_BIN_W)
variable ibusy : slbit := '0';
variable irstw : slbit := '0';
variable igcw_ce : slbit := '0';
variable igcw_rst : slbit := '0';
variable isizew : slv(a_range) := (others=>'0');
begin
isizew := slv(unsigned(RADDR_BIN_W) + unsigned(not WADDR_BIN_W));
ibusy := '0';
igcw_ce := '0';
igcw_rst := '0';
if unsigned(isizew) = 0 then -- if no free slots
ibusy := '1'; -- next cycle busy=1
end if;
if ENA='1' and RW_BUSY='0' then -- if ena=1 and this cycle busy=0
igcw_ce := '1'; -- write this value
if unsigned(isizew) = 1 then -- if this last free slot
ibusy := '1'; -- next cycle busy=1
end if;
end if;
irstw := RW_RSTW;
if RESETW = '1' then -- reset(write side) request
irstw := '1'; -- set RSTW flag
elsif RW_RSTW_E_S1 = '1' then -- request gone and return seen
irstw := '0'; -- clear RSTW flag
end if;
if RW_RSTW='1' and RW_RSTW_E_S1='1' then -- RSTW seen on write and read side
igcw_rst := '1'; -- clear write address counter
end if;
if RW_RSTR_S1 = '1' then -- RSTR active
igcw_rst := '1'; -- clear write address counter
end if;
if RESETW='1' or RW_RSTW='1' or RW_RSTW_E_S1='1' or RW_RSTR_S1='1'
then -- RESETW or RESETR active
ibusy := '1'; -- signal write side busy
isizew := (others=>'1');
end if;
NW_BUSY <= ibusy;
NW_RSTW <= irstw;
NW_SIZEW <= isizew;
GCW_CE <= igcw_ce;
GCW_RST <= igcw_rst;
BUSY <= RW_BUSY;
SIZEW <= RW_SIZEW;
end process proc_nextw;
--
-- read side ---------------------------------------------------------------
--
proc_regr: process (CLKR)
begin
if rising_edge(CLKR) then
RR_WADDR_S0 <= WADDR; -- sync 0: CLKW->CLKR
RR_WADDR_S1 <= RR_WADDR_S0; -- sync 1: CLKW
RR_SIZER <= NR_SIZER;
RR_VAL <= NR_VAL;
RR_RSTR <= NR_RSTR;
RR_RSTR_E_S0 <= RW_RSTR_S1; -- sync 0: CLKW->CLKR
RR_RSTR_E_S1 <= RR_RSTR_E_S0; -- sync 1: CLKW
RR_RSTW_S0 <= RW_RSTW; -- sync 0: CLKW->CLKR
RR_RSTW_S1 <= RR_RSTW_S0; -- sync 1: CLKW
end if;
end process proc_regr;
proc_nextr: process (RR_VAL, RR_SIZER, RR_RSTR, RR_RSTR_E_S1, RR_RSTW_S1,
HOLD, RESETR, RADDR_BIN_R, WADDR_BIN_R)
variable ival : slbit := '0';
variable irstr : slbit := '0';
variable igcr_ce : slbit := '0';
variable igcr_rst : slbit := '0';
variable isizer : slv(a_range) := (others=>'0');
begin
isizer := slv(unsigned(WADDR_BIN_R) - unsigned(RADDR_BIN_R));
ival := '1';
igcr_ce := '0';
igcr_rst := '0';
if unsigned(isizer) = 0 then -- if nothing to read
ival := '0'; -- next cycle val=0
end if;
if RR_VAL='1' and HOLD='0' then -- this cycle val=1 and no hold
igcr_ce := '1'; -- retire this value
if unsigned(isizer) = 1 then -- if this is last one
ival := '0'; -- next cycle val=0
end if;
end if;
irstr := RR_RSTR;
if RESETR = '1' then -- reset(read side) request
irstr := '1'; -- set RSTR flag
elsif RR_RSTR_E_S1 = '1' then -- request gone and return seen
irstr := '0'; -- clear RSTR flag
end if;
if RR_RSTR='1' and RR_RSTR_E_S1='1' then -- RSTR seen on read and write side
igcr_rst := '1'; -- clear read address counter
end if;
if RR_RSTW_S1 = '1' then -- RSTW active
igcr_rst := '1'; -- clear read address counter
end if;
if RESETR='1' or RR_RSTR='1' or RR_RSTR_E_S1='1' or RR_RSTW_S1='1'
then -- RESETR or RESETW active
ival := '0'; -- signal read side empty
isizer := (others=>'0');
end if;
NR_VAL <= ival;
NR_RSTR <= irstr;
NR_SIZER <= isizer;
GCR_CE <= igcr_ce;
GCR_RST <= igcr_rst;
VAL <= RR_VAL;
SIZER <= RR_SIZER;
end process proc_nextr;
end syn;
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 19:49:29 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode funcsim
-- /home/mark/Documents/Repos/FPGA_Sandbox/RecComp/Lab3/adventures_with_ip/adventures_with_ip.srcs/sources_1/bd/ip_design/ip/ip_design_axi_gpio_0_0/ip_design_axi_gpio_0_0_sim_netlist.vhdl
-- Design : ip_design_axi_gpio_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ip_design_axi_gpio_0_0_address_decoder is
port (
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
\Not_Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC;
\Not_Dual.gpio_OE_reg[0]\ : out STD_LOGIC;
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30]\ : out STD_LOGIC;
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg[31]\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
Q : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
rst_reg : in STD_LOGIC;
bus2ip_rnw_i_reg : in STD_LOGIC;
\bus2ip_addr_i_reg[8]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
ip2bus_rdack_i_D1 : in STD_LOGIC;
is_read : in STD_LOGIC;
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
ip2bus_wrack_i_D1 : in STD_LOGIC;
is_write_reg : in STD_LOGIC;
gpio_xferAck_Reg : in STD_LOGIC;
GPIO_xferAck_i : in STD_LOGIC;
reg2 : in STD_LOGIC_VECTOR ( 1 downto 0 );
reg1 : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ip_design_axi_gpio_0_0_address_decoder : entity is "address_decoder";
end ip_design_axi_gpio_0_0_address_decoder;
architecture STRUCTURE of ip_design_axi_gpio_0_0_address_decoder is
signal Bus_RNW_reg : STD_LOGIC;
signal Bus_RNW_reg_i_1_n_0 : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\ : STD_LOGIC;
signal \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\ : STD_LOGIC;
signal \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\ : STD_LOGIC;
signal \^mem_decode_gen[0].cs_out_i_reg[0]_0\ : STD_LOGIC;
signal ce_expnd_i_0 : STD_LOGIC;
signal ce_expnd_i_1 : STD_LOGIC;
signal ce_expnd_i_2 : STD_LOGIC;
signal ce_expnd_i_3 : STD_LOGIC;
signal cs_ce_clr : STD_LOGIC;
signal \ip2bus_data_i_D1[30]_i_2_n_0\ : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[2].ce_out_i[2]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1[31]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1[31]_i_3\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \ip2bus_data_i_D1[0]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \ip2bus_data_i_D1[30]_i_2\ : label is "soft_lutpair0";
begin
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ <= \^mem_decode_gen[0].cs_out_i_reg[0]_0\;
s_axi_arready <= \^s_axi_arready\;
s_axi_wready <= \^s_axi_wready\;
Bus_RNW_reg_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => Q,
I2 => Bus_RNW_reg,
O => Bus_RNW_reg_i_1_n_0
);
Bus_RNW_reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Bus_RNW_reg_i_1_n_0,
Q => Bus_RNW_reg,
R => '0'
);
\GEN_BKEND_CE_REGISTERS[0].ce_out_i[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(0),
I1 => \bus2ip_addr_i_reg[8]\(1),
O => ce_expnd_i_3
);
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_3,
Q => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(0),
I1 => \bus2ip_addr_i_reg[8]\(1),
O => ce_expnd_i_2
);
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_2,
Q => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[2].ce_out_i[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(0),
O => ce_expnd_i_1
);
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_1,
Q => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
R => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"EF"
)
port map (
I0 => \^s_axi_wready\,
I1 => \^s_axi_arready\,
I2 => s_axi_aresetn,
O => cs_ce_clr
);
\GEN_BKEND_CE_REGISTERS[3].ce_out_i[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \bus2ip_addr_i_reg[8]\(1),
I1 => \bus2ip_addr_i_reg[8]\(0),
O => ce_expnd_i_0
);
\GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => Q,
D => ce_expnd_i_0,
Q => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
R => cs_ce_clr
);
\MEM_DECODE_GEN[0].cs_out_i[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000E0"
)
port map (
I0 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I1 => Q,
I2 => s_axi_aresetn,
I3 => \^s_axi_arready\,
I4 => \^s_axi_wready\,
O => \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\
);
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\,
Q => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
R => '0'
);
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFF7"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => gpio_xferAck_Reg,
I3 => GPIO_xferAck_i,
O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30]\
);
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1[31]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I1 => \bus2ip_addr_i_reg[8]\(2),
O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg[31]\
);
\Not_Dual.gpio_Data_Out[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAABAA"
)
port map (
I0 => rst_reg,
I1 => bus2ip_rnw_i_reg,
I2 => \bus2ip_addr_i_reg[8]\(0),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => \bus2ip_addr_i_reg[8]\(2),
I5 => \bus2ip_addr_i_reg[8]\(1),
O => \Not_Dual.gpio_Data_Out_reg[0]\
);
\Not_Dual.gpio_OE[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAABAAAAA"
)
port map (
I0 => rst_reg,
I1 => bus2ip_rnw_i_reg,
I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I3 => \bus2ip_addr_i_reg[8]\(2),
I4 => \bus2ip_addr_i_reg[8]\(0),
I5 => \bus2ip_addr_i_reg[8]\(1),
O => \Not_Dual.gpio_OE_reg[0]\
);
\ip2bus_data_i_D1[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00000400"
)
port map (
I0 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
I1 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
I3 => Bus_RNW_reg,
I4 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
O => D(2)
);
\ip2bus_data_i_D1[30]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000F0AC000000000"
)
port map (
I0 => reg2(1),
I1 => reg1(1),
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
I3 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
I4 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
I5 => \ip2bus_data_i_D1[30]_i_2_n_0\,
O => D(1)
);
\ip2bus_data_i_D1[30]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => Bus_RNW_reg,
I1 => \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg\,
O => \ip2bus_data_i_D1[30]_i_2_n_0\
);
\ip2bus_data_i_D1[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000F0AC000000000"
)
port map (
I0 => reg2(0),
I1 => reg1(0),
I2 => \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg\,
I3 => \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg\,
I4 => \GEN_BKEND_CE_REGISTERS[3].ce_out_i_reg\,
I5 => \ip2bus_data_i_D1[30]_i_2_n_0\,
O => D(0)
);
s_axi_arready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAEAAAA"
)
port map (
I0 => ip2bus_rdack_i_D1,
I1 => is_read,
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(2),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(1),
I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3),
I5 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0),
O => \^s_axi_arready\
);
s_axi_wready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAEAAAA"
)
port map (
I0 => ip2bus_wrack_i_D1,
I1 => is_write_reg,
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(2),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(1),
I4 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3),
I5 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(0),
O => \^s_axi_wready\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ip_design_axi_gpio_0_0_cdc_sync is
port (
scndry_vect_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
gpio_io_i : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ip_design_axi_gpio_0_0_cdc_sync : entity is "cdc_sync";
end ip_design_axi_gpio_0_0_cdc_sync;
architecture STRUCTURE of ip_design_axi_gpio_0_0_cdc_sync is
signal s_level_out_bus_d1_cdc_to_0 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_1 : STD_LOGIC;
signal s_level_out_bus_d2_0 : STD_LOGIC;
signal s_level_out_bus_d2_1 : STD_LOGIC;
signal s_level_out_bus_d3_0 : STD_LOGIC;
signal s_level_out_bus_d3_1 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
begin
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_0,
Q => s_level_out_bus_d2_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_1,
Q => s_level_out_bus_d2_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_0,
Q => s_level_out_bus_d3_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_1,
Q => s_level_out_bus_d3_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_0,
Q => scndry_vect_out(0),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_1,
Q => scndry_vect_out(1),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(0),
Q => s_level_out_bus_d1_cdc_to_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(1),
Q => s_level_out_bus_d1_cdc_to_1,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ip_design_axi_gpio_0_0_GPIO_Core is
port (
reg1 : out STD_LOGIC_VECTOR ( 1 downto 0 );
GPIO_xferAck_i : out STD_LOGIC;
gpio_xferAck_Reg : out STD_LOGIC;
reg2 : out STD_LOGIC_VECTOR ( 1 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gpio_io_t[0]\ : out STD_LOGIC;
\gpio_io_t[1]\ : out STD_LOGIC;
ip2bus_rdack_i : out STD_LOGIC;
ip2bus_wrack_i_D1_reg : out STD_LOGIC;
bus2ip_rnw_i_reg : in STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
bus2ip_reset : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\ : in STD_LOGIC;
bus2ip_rnw : in STD_LOGIC;
bus2ip_cs : in STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 3 downto 0 );
rst_reg : in STD_LOGIC;
rst_reg_0 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ip_design_axi_gpio_0_0_GPIO_Core : entity is "GPIO_Core";
end ip_design_axi_gpio_0_0_GPIO_Core;
architecture STRUCTURE of ip_design_axi_gpio_0_0_GPIO_Core is
signal \^gpio_xferack_i\ : STD_LOGIC;
signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1[30]_i_1_n_0\ : STD_LOGIC;
signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2[30]_i_1_n_0\ : STD_LOGIC;
signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1[31]_i_2_n_0\ : STD_LOGIC;
signal \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2[31]_i_1_n_0\ : STD_LOGIC;
signal \Not_Dual.gpio_Data_Out[0]_i_1_n_0\ : STD_LOGIC;
signal \Not_Dual.gpio_Data_Out[1]_i_1_n_0\ : STD_LOGIC;
signal \Not_Dual.gpio_OE[0]_i_1_n_0\ : STD_LOGIC;
signal \Not_Dual.gpio_OE[1]_i_1_n_0\ : STD_LOGIC;
signal gpio_Data_In : STD_LOGIC_VECTOR ( 0 to 1 );
signal gpio_io_i_d2 : STD_LOGIC_VECTOR ( 0 to 1 );
signal \^gpio_io_o\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^gpio_io_t[0]\ : STD_LOGIC;
signal \^gpio_io_t[1]\ : STD_LOGIC;
signal \^gpio_xferack_reg\ : STD_LOGIC;
signal iGPIO_xferAck : STD_LOGIC;
signal \^reg2\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of iGPIO_xferAck_i_1 : label is "soft_lutpair8";
attribute SOFT_HLUTNM of ip2bus_rdack_i_D1_i_1 : label is "soft_lutpair8";
begin
GPIO_xferAck_i <= \^gpio_xferack_i\;
gpio_io_o(1 downto 0) <= \^gpio_io_o\(1 downto 0);
\gpio_io_t[0]\ <= \^gpio_io_t[0]\;
\gpio_io_t[1]\ <= \^gpio_io_t[1]\;
gpio_xferAck_Reg <= \^gpio_xferack_reg\;
reg2(1 downto 0) <= \^reg2\(1 downto 0);
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1[30]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"2C2E22222C222222"
)
port map (
I0 => \^gpio_io_o\(1),
I1 => \^gpio_io_t[1]\,
I2 => Q(1),
I3 => Q(0),
I4 => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\,
I5 => gpio_Data_In(0),
O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1[30]_i_1_n_0\
);
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1[30]_i_1_n_0\,
Q => reg1(1),
R => bus2ip_rnw_i_reg
);
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2[30]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"2C2E22222C222222"
)
port map (
I0 => \^reg2\(1),
I1 => \^gpio_io_t[1]\,
I2 => Q(1),
I3 => Q(0),
I4 => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\,
I5 => gpio_Data_In(0),
O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2[30]_i_1_n_0\
);
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg2[30]_i_1_n_0\,
Q => \^reg2\(1),
R => bus2ip_rnw_i_reg
);
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"2C2E22222C222222"
)
port map (
I0 => \^gpio_io_o\(0),
I1 => \^gpio_io_t[0]\,
I2 => Q(1),
I3 => Q(0),
I4 => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\,
I5 => gpio_Data_In(1),
O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1[31]_i_2_n_0\
);
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg1[31]_i_2_n_0\,
Q => reg1(0),
R => bus2ip_rnw_i_reg
);
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"2C2E22222C222222"
)
port map (
I0 => \^reg2\(0),
I1 => \^gpio_io_t[0]\,
I2 => Q(1),
I3 => Q(0),
I4 => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\,
I5 => gpio_Data_In(1),
O => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2[31]_i_1_n_0\
);
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2[31]_i_1_n_0\,
Q => \^reg2\(0),
R => bus2ip_rnw_i_reg
);
\Not_Dual.INPUT_DOUBLE_REGS3\: entity work.ip_design_axi_gpio_0_0_cdc_sync
port map (
gpio_io_i(1 downto 0) => gpio_io_i(1 downto 0),
s_axi_aclk => s_axi_aclk,
scndry_vect_out(1) => gpio_io_i_d2(0),
scndry_vect_out(0) => gpio_io_i_d2(1)
);
\Not_Dual.gpio_Data_In_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(0),
Q => gpio_Data_In(0),
R => '0'
);
\Not_Dual.gpio_Data_In_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(1),
Q => gpio_Data_In(1),
R => '0'
);
\Not_Dual.gpio_Data_Out[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FB08FFFFFB080000"
)
port map (
I0 => s_axi_wdata(1),
I1 => bus2ip_cs,
I2 => Q(1),
I3 => s_axi_wdata(3),
I4 => rst_reg,
I5 => \^gpio_io_o\(1),
O => \Not_Dual.gpio_Data_Out[0]_i_1_n_0\
);
\Not_Dual.gpio_Data_Out[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FB08FFFFFB080000"
)
port map (
I0 => s_axi_wdata(0),
I1 => bus2ip_cs,
I2 => Q(1),
I3 => s_axi_wdata(2),
I4 => rst_reg,
I5 => \^gpio_io_o\(0),
O => \Not_Dual.gpio_Data_Out[1]_i_1_n_0\
);
\Not_Dual.gpio_Data_Out_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_Data_Out[0]_i_1_n_0\,
Q => \^gpio_io_o\(1),
R => bus2ip_reset
);
\Not_Dual.gpio_Data_Out_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_Data_Out[1]_i_1_n_0\,
Q => \^gpio_io_o\(0),
R => bus2ip_reset
);
\Not_Dual.gpio_OE[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FB08FFFFFB080000"
)
port map (
I0 => s_axi_wdata(1),
I1 => bus2ip_cs,
I2 => Q(1),
I3 => s_axi_wdata(3),
I4 => rst_reg_0,
I5 => \^gpio_io_t[1]\,
O => \Not_Dual.gpio_OE[0]_i_1_n_0\
);
\Not_Dual.gpio_OE[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FB08FFFFFB080000"
)
port map (
I0 => s_axi_wdata(0),
I1 => bus2ip_cs,
I2 => Q(1),
I3 => s_axi_wdata(2),
I4 => rst_reg_0,
I5 => \^gpio_io_t[0]\,
O => \Not_Dual.gpio_OE[1]_i_1_n_0\
);
\Not_Dual.gpio_OE_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE[0]_i_1_n_0\,
Q => \^gpio_io_t[1]\,
S => bus2ip_reset
);
\Not_Dual.gpio_OE_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \Not_Dual.gpio_OE[1]_i_1_n_0\,
Q => \^gpio_io_t[0]\,
S => bus2ip_reset
);
gpio_xferAck_Reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_xferack_i\,
Q => \^gpio_xferack_reg\,
R => bus2ip_reset
);
iGPIO_xferAck_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => bus2ip_cs,
I1 => \^gpio_xferack_reg\,
I2 => \^gpio_xferack_i\,
O => iGPIO_xferAck
);
iGPIO_xferAck_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => iGPIO_xferAck,
Q => \^gpio_xferack_i\,
R => bus2ip_reset
);
ip2bus_rdack_i_D1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^gpio_xferack_i\,
I1 => bus2ip_rnw,
O => ip2bus_rdack_i
);
ip2bus_wrack_i_D1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^gpio_xferack_i\,
I1 => bus2ip_rnw,
O => ip2bus_wrack_i_D1_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ip_design_axi_gpio_0_0_slave_attachment is
port (
SR : out STD_LOGIC;
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30]\ : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\ : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
\Not_Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
\Not_Dual.gpio_OE_reg[0]\ : out STD_LOGIC;
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30]_0\ : out STD_LOGIC;
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg[31]\ : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 2 downto 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
gpio_xferAck_Reg : in STD_LOGIC;
GPIO_xferAck_i : in STD_LOGIC;
\ip2bus_data_i_D1_reg[0]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
reg2 : in STD_LOGIC_VECTOR ( 1 downto 0 );
reg1 : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ip_design_axi_gpio_0_0_slave_attachment : entity is "slave_attachment";
end ip_design_axi_gpio_0_0_slave_attachment;
architecture STRUCTURE of ip_design_axi_gpio_0_0_slave_attachment is
signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^not_dual.allout0_nd.read_reg_gen[0].reg1_reg[30]\ : STD_LOGIC;
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^sr\ : STD_LOGIC;
signal bus2ip_addr : STD_LOGIC_VECTOR ( 0 to 0 );
signal \bus2ip_addr_i[2]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[3]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[8]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[8]_i_2_n_0\ : STD_LOGIC;
signal clear : STD_LOGIC;
signal is_read : STD_LOGIC;
signal is_read_i_1_n_0 : STD_LOGIC;
signal is_write : STD_LOGIC;
signal is_write_i_1_n_0 : STD_LOGIC;
signal is_write_reg_n_0 : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 1 downto 0 );
signal plusOp : STD_LOGIC_VECTOR ( 3 downto 0 );
signal rst_i_1_n_0 : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal s_axi_bvalid_i_i_1_n_0 : STD_LOGIC;
signal \^s_axi_rdata\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \s_axi_rdata_i[0]_i_1_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[1]_i_1_n_0\ : STD_LOGIC;
signal \s_axi_rdata_i[31]_i_1_n_0\ : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal s_axi_rvalid_i_i_1_n_0 : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal start2 : STD_LOGIC;
signal start2_i_1_n_0 : STD_LOGIC;
signal state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \state1__2\ : STD_LOGIC;
signal \state[1]_i_3_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \bus2ip_addr_i[3]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \bus2ip_addr_i[8]_i_2\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of start2_i_1 : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \state[1]_i_3\ : label is "soft_lutpair4";
begin
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30]\ <= \^not_dual.allout0_nd.read_reg_gen[0].reg1_reg[30]\;
Q(1 downto 0) <= \^q\(1 downto 0);
SR <= \^sr\;
s_axi_arready <= \^s_axi_arready\;
s_axi_bvalid <= \^s_axi_bvalid\;
s_axi_rdata(2 downto 0) <= \^s_axi_rdata\(2 downto 0);
s_axi_rvalid <= \^s_axi_rvalid\;
s_axi_wready <= \^s_axi_wready\;
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
O => plusOp(0)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
O => plusOp(1)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
O => plusOp(2)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => state(0),
I1 => state(1),
O => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
O => plusOp(3)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(0),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(1),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(2),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(3),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
R => clear
);
I_DECODER: entity work.ip_design_axi_gpio_0_0_address_decoder
port map (
D(2 downto 0) => D(2 downto 0),
GPIO_xferAck_i => GPIO_xferAck_i,
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\(3 downto 0) => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3 downto 0),
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\,
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30]\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30]_0\,
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg[31]\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg[31]\,
\Not_Dual.gpio_Data_Out_reg[0]\ => \Not_Dual.gpio_Data_Out_reg[0]\,
\Not_Dual.gpio_OE_reg[0]\ => \Not_Dual.gpio_OE_reg[0]\,
Q => start2,
\bus2ip_addr_i_reg[8]\(2) => bus2ip_addr(0),
\bus2ip_addr_i_reg[8]\(1 downto 0) => \^q\(1 downto 0),
bus2ip_rnw_i_reg => \^not_dual.allout0_nd.read_reg_gen[0].reg1_reg[30]\,
gpio_xferAck_Reg => gpio_xferAck_Reg,
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
is_read => is_read,
is_write_reg => is_write_reg_n_0,
reg1(1 downto 0) => reg1(1 downto 0),
reg2(1 downto 0) => reg2(1 downto 0),
rst_reg => \^sr\,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => \^s_axi_arready\,
s_axi_wready => \^s_axi_wready\
);
\bus2ip_addr_i[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => s_axi_araddr(0),
I1 => s_axi_awaddr(0),
I2 => s_axi_arvalid,
O => \bus2ip_addr_i[2]_i_1_n_0\
);
\bus2ip_addr_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => s_axi_araddr(1),
I1 => s_axi_awaddr(1),
I2 => s_axi_arvalid,
O => \bus2ip_addr_i[3]_i_1_n_0\
);
\bus2ip_addr_i[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000000EA"
)
port map (
I0 => s_axi_arvalid,
I1 => s_axi_awvalid,
I2 => s_axi_wvalid,
I3 => state(1),
I4 => state(0),
O => \bus2ip_addr_i[8]_i_1_n_0\
);
\bus2ip_addr_i[8]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"AC"
)
port map (
I0 => s_axi_araddr(2),
I1 => s_axi_awaddr(2),
I2 => s_axi_arvalid,
O => \bus2ip_addr_i[8]_i_2_n_0\
);
\bus2ip_addr_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[2]_i_1_n_0\,
Q => \^q\(0),
R => \^sr\
);
\bus2ip_addr_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[3]_i_1_n_0\,
Q => \^q\(1),
R => \^sr\
);
\bus2ip_addr_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => \bus2ip_addr_i[8]_i_2_n_0\,
Q => bus2ip_addr(0),
R => \^sr\
);
bus2ip_rnw_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => \bus2ip_addr_i[8]_i_1_n_0\,
D => s_axi_arvalid,
Q => \^not_dual.allout0_nd.read_reg_gen[0].reg1_reg[30]\,
R => \^sr\
);
is_read_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"3FFA000A"
)
port map (
I0 => s_axi_arvalid,
I1 => \state1__2\,
I2 => state(0),
I3 => state(1),
I4 => is_read,
O => is_read_i_1_n_0
);
is_read_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_read_i_1_n_0,
Q => is_read,
R => \^sr\
);
is_write_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0040FFFF00400000"
)
port map (
I0 => s_axi_arvalid,
I1 => s_axi_awvalid,
I2 => s_axi_wvalid,
I3 => state(1),
I4 => is_write,
I5 => is_write_reg_n_0,
O => is_write_i_1_n_0
);
is_write_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"F88800000000FFFF"
)
port map (
I0 => \^s_axi_rvalid\,
I1 => s_axi_rready,
I2 => \^s_axi_bvalid\,
I3 => s_axi_bready,
I4 => state(0),
I5 => state(1),
O => is_write
);
is_write_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_write_i_1_n_0,
Q => is_write_reg_n_0,
R => \^sr\
);
rst_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => rst_i_1_n_0
);
rst_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => rst_i_1_n_0,
Q => \^sr\,
R => '0'
);
s_axi_bvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_wready\,
I1 => state(1),
I2 => state(0),
I3 => s_axi_bready,
I4 => \^s_axi_bvalid\,
O => s_axi_bvalid_i_i_1_n_0
);
s_axi_bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_bvalid_i_i_1_n_0,
Q => \^s_axi_bvalid\,
R => \^sr\
);
\s_axi_rdata_i[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => \ip2bus_data_i_D1_reg[0]\(0),
I1 => state(0),
I2 => state(1),
I3 => \^s_axi_rdata\(0),
O => \s_axi_rdata_i[0]_i_1_n_0\
);
\s_axi_rdata_i[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => \ip2bus_data_i_D1_reg[0]\(1),
I1 => state(0),
I2 => state(1),
I3 => \^s_axi_rdata\(1),
O => \s_axi_rdata_i[1]_i_1_n_0\
);
\s_axi_rdata_i[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => \ip2bus_data_i_D1_reg[0]\(2),
I1 => state(0),
I2 => state(1),
I3 => \^s_axi_rdata\(2),
O => \s_axi_rdata_i[31]_i_1_n_0\
);
\s_axi_rdata_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \s_axi_rdata_i[0]_i_1_n_0\,
Q => \^s_axi_rdata\(0),
R => \^sr\
);
\s_axi_rdata_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \s_axi_rdata_i[1]_i_1_n_0\,
Q => \^s_axi_rdata\(1),
R => \^sr\
);
\s_axi_rdata_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => \s_axi_rdata_i[31]_i_1_n_0\,
Q => \^s_axi_rdata\(2),
R => \^sr\
);
s_axi_rvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_arready\,
I1 => state(0),
I2 => state(1),
I3 => s_axi_rready,
I4 => \^s_axi_rvalid\,
O => s_axi_rvalid_i_i_1_n_0
);
s_axi_rvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_rvalid_i_i_1_n_0,
Q => \^s_axi_rvalid\,
R => \^sr\
);
start2_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000000F8"
)
port map (
I0 => s_axi_awvalid,
I1 => s_axi_wvalid,
I2 => s_axi_arvalid,
I3 => state(1),
I4 => state(0),
O => start2_i_1_n_0
);
start2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => start2_i_1_n_0,
Q => start2,
R => \^sr\
);
\state[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"77FC44FC"
)
port map (
I0 => \state1__2\,
I1 => state(0),
I2 => s_axi_arvalid,
I3 => state(1),
I4 => \^s_axi_wready\,
O => p_0_out(0)
);
\state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"5FFC50FC"
)
port map (
I0 => \state1__2\,
I1 => \state[1]_i_3_n_0\,
I2 => state(1),
I3 => state(0),
I4 => \^s_axi_arready\,
O => p_0_out(1)
);
\state[1]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => \state1__2\
);
\state[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => s_axi_wvalid,
I1 => s_axi_awvalid,
I2 => s_axi_arvalid,
O => \state[1]_i_3_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_out(0),
Q => state(0),
R => \^sr\
);
\state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_0_out(1),
Q => state(1),
R => \^sr\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ip_design_axi_gpio_0_0_axi_lite_ipif is
port (
bus2ip_reset : out STD_LOGIC;
bus2ip_rnw : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
bus2ip_cs : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
\Not_Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
\Not_Dual.gpio_OE_reg[0]\ : out STD_LOGIC;
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30]\ : out STD_LOGIC;
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg[31]\ : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 2 downto 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
gpio_xferAck_Reg : in STD_LOGIC;
GPIO_xferAck_i : in STD_LOGIC;
\ip2bus_data_i_D1_reg[0]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
reg2 : in STD_LOGIC_VECTOR ( 1 downto 0 );
reg1 : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ip_design_axi_gpio_0_0_axi_lite_ipif : entity is "axi_lite_ipif";
end ip_design_axi_gpio_0_0_axi_lite_ipif;
architecture STRUCTURE of ip_design_axi_gpio_0_0_axi_lite_ipif is
begin
I_SLAVE_ATTACHMENT: entity work.ip_design_axi_gpio_0_0_slave_attachment
port map (
D(2 downto 0) => D(2 downto 0),
GPIO_xferAck_i => GPIO_xferAck_i,
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\ => bus2ip_cs,
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30]\ => bus2ip_rnw,
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30]_0\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30]\,
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg[31]\ => \Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg[31]\,
\Not_Dual.gpio_Data_Out_reg[0]\ => \Not_Dual.gpio_Data_Out_reg[0]\,
\Not_Dual.gpio_OE_reg[0]\ => \Not_Dual.gpio_OE_reg[0]\,
Q(1 downto 0) => Q(1 downto 0),
SR => bus2ip_reset,
gpio_xferAck_Reg => gpio_xferAck_Reg,
\ip2bus_data_i_D1_reg[0]\(2 downto 0) => \ip2bus_data_i_D1_reg[0]\(2 downto 0),
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
reg1(1 downto 0) => reg1(1 downto 0),
reg2(1 downto 0) => reg2(1 downto 0),
s_axi_aclk => s_axi_aclk,
s_axi_araddr(2 downto 0) => s_axi_araddr(2 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(2 downto 0) => s_axi_awaddr(2 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(2 downto 0) => s_axi_rdata(2 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ip_design_axi_gpio_0_0_axi_gpio is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 1 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 1 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 1 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
gpio2_io_o : out STD_LOGIC_VECTOR ( 31 downto 0 );
gpio2_io_t : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute C_ALL_INPUTS : integer;
attribute C_ALL_INPUTS of ip_design_axi_gpio_0_0_axi_gpio : entity is 0;
attribute C_ALL_INPUTS_2 : integer;
attribute C_ALL_INPUTS_2 of ip_design_axi_gpio_0_0_axi_gpio : entity is 0;
attribute C_ALL_OUTPUTS : integer;
attribute C_ALL_OUTPUTS of ip_design_axi_gpio_0_0_axi_gpio : entity is 0;
attribute C_ALL_OUTPUTS_2 : integer;
attribute C_ALL_OUTPUTS_2 of ip_design_axi_gpio_0_0_axi_gpio : entity is 0;
attribute C_DOUT_DEFAULT : integer;
attribute C_DOUT_DEFAULT of ip_design_axi_gpio_0_0_axi_gpio : entity is 0;
attribute C_DOUT_DEFAULT_2 : integer;
attribute C_DOUT_DEFAULT_2 of ip_design_axi_gpio_0_0_axi_gpio : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of ip_design_axi_gpio_0_0_axi_gpio : entity is "zynq";
attribute C_GPIO2_WIDTH : integer;
attribute C_GPIO2_WIDTH of ip_design_axi_gpio_0_0_axi_gpio : entity is 32;
attribute C_GPIO_WIDTH : integer;
attribute C_GPIO_WIDTH of ip_design_axi_gpio_0_0_axi_gpio : entity is 2;
attribute C_INTERRUPT_PRESENT : integer;
attribute C_INTERRUPT_PRESENT of ip_design_axi_gpio_0_0_axi_gpio : entity is 0;
attribute C_IS_DUAL : integer;
attribute C_IS_DUAL of ip_design_axi_gpio_0_0_axi_gpio : entity is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of ip_design_axi_gpio_0_0_axi_gpio : entity is 9;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of ip_design_axi_gpio_0_0_axi_gpio : entity is 32;
attribute C_TRI_DEFAULT : integer;
attribute C_TRI_DEFAULT of ip_design_axi_gpio_0_0_axi_gpio : entity is -1;
attribute C_TRI_DEFAULT_2 : integer;
attribute C_TRI_DEFAULT_2 of ip_design_axi_gpio_0_0_axi_gpio : entity is -1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of ip_design_axi_gpio_0_0_axi_gpio : entity is "axi_gpio";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of ip_design_axi_gpio_0_0_axi_gpio : entity is "yes";
attribute ip_group : string;
attribute ip_group of ip_design_axi_gpio_0_0_axi_gpio : entity is "LOGICORE";
end ip_design_axi_gpio_0_0_axi_gpio;
architecture STRUCTURE of ip_design_axi_gpio_0_0_axi_gpio is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_10 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_11 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_12 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_7 : STD_LOGIC;
signal GPIO_xferAck_i : STD_LOGIC;
signal bus2ip_addr : STD_LOGIC_VECTOR ( 5 to 6 );
signal bus2ip_cs : STD_LOGIC;
signal bus2ip_reset : STD_LOGIC;
signal bus2ip_rnw : STD_LOGIC;
signal gpio_core_1_n_11 : STD_LOGIC;
signal gpio_xferAck_Reg : STD_LOGIC;
signal ip2bus_data : STD_LOGIC_VECTOR ( 0 to 31 );
signal ip2bus_data_i_D1 : STD_LOGIC_VECTOR ( 0 to 31 );
signal ip2bus_rdack_i : STD_LOGIC;
signal ip2bus_rdack_i_D1 : STD_LOGIC;
signal ip2bus_wrack_i_D1 : STD_LOGIC;
signal reg1 : STD_LOGIC_VECTOR ( 30 to 31 );
signal reg2 : STD_LOGIC_VECTOR ( 30 to 31 );
signal \^s_axi_rdata\ : STD_LOGIC_VECTOR ( 30 downto 0 );
signal \^s_axi_wready\ : STD_LOGIC;
attribute sigis : string;
attribute sigis of ip2intc_irpt : signal is "INTR_LEVEL_HIGH";
attribute max_fanout : string;
attribute max_fanout of s_axi_aclk : signal is "10000";
attribute sigis of s_axi_aclk : signal is "Clk";
attribute max_fanout of s_axi_aresetn : signal is "10000";
attribute sigis of s_axi_aresetn : signal is "Rst";
begin
gpio2_io_o(31) <= \<const0>\;
gpio2_io_o(30) <= \<const0>\;
gpio2_io_o(29) <= \<const0>\;
gpio2_io_o(28) <= \<const0>\;
gpio2_io_o(27) <= \<const0>\;
gpio2_io_o(26) <= \<const0>\;
gpio2_io_o(25) <= \<const0>\;
gpio2_io_o(24) <= \<const0>\;
gpio2_io_o(23) <= \<const0>\;
gpio2_io_o(22) <= \<const0>\;
gpio2_io_o(21) <= \<const0>\;
gpio2_io_o(20) <= \<const0>\;
gpio2_io_o(19) <= \<const0>\;
gpio2_io_o(18) <= \<const0>\;
gpio2_io_o(17) <= \<const0>\;
gpio2_io_o(16) <= \<const0>\;
gpio2_io_o(15) <= \<const0>\;
gpio2_io_o(14) <= \<const0>\;
gpio2_io_o(13) <= \<const0>\;
gpio2_io_o(12) <= \<const0>\;
gpio2_io_o(11) <= \<const0>\;
gpio2_io_o(10) <= \<const0>\;
gpio2_io_o(9) <= \<const0>\;
gpio2_io_o(8) <= \<const0>\;
gpio2_io_o(7) <= \<const0>\;
gpio2_io_o(6) <= \<const0>\;
gpio2_io_o(5) <= \<const0>\;
gpio2_io_o(4) <= \<const0>\;
gpio2_io_o(3) <= \<const0>\;
gpio2_io_o(2) <= \<const0>\;
gpio2_io_o(1) <= \<const0>\;
gpio2_io_o(0) <= \<const0>\;
gpio2_io_t(31) <= \<const1>\;
gpio2_io_t(30) <= \<const1>\;
gpio2_io_t(29) <= \<const1>\;
gpio2_io_t(28) <= \<const1>\;
gpio2_io_t(27) <= \<const1>\;
gpio2_io_t(26) <= \<const1>\;
gpio2_io_t(25) <= \<const1>\;
gpio2_io_t(24) <= \<const1>\;
gpio2_io_t(23) <= \<const1>\;
gpio2_io_t(22) <= \<const1>\;
gpio2_io_t(21) <= \<const1>\;
gpio2_io_t(20) <= \<const1>\;
gpio2_io_t(19) <= \<const1>\;
gpio2_io_t(18) <= \<const1>\;
gpio2_io_t(17) <= \<const1>\;
gpio2_io_t(16) <= \<const1>\;
gpio2_io_t(15) <= \<const1>\;
gpio2_io_t(14) <= \<const1>\;
gpio2_io_t(13) <= \<const1>\;
gpio2_io_t(12) <= \<const1>\;
gpio2_io_t(11) <= \<const1>\;
gpio2_io_t(10) <= \<const1>\;
gpio2_io_t(9) <= \<const1>\;
gpio2_io_t(8) <= \<const1>\;
gpio2_io_t(7) <= \<const1>\;
gpio2_io_t(6) <= \<const1>\;
gpio2_io_t(5) <= \<const1>\;
gpio2_io_t(4) <= \<const1>\;
gpio2_io_t(3) <= \<const1>\;
gpio2_io_t(2) <= \<const1>\;
gpio2_io_t(1) <= \<const1>\;
gpio2_io_t(0) <= \<const1>\;
ip2intc_irpt <= \<const0>\;
s_axi_awready <= \^s_axi_wready\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_rdata(31) <= \^s_axi_rdata\(30);
s_axi_rdata(30) <= \^s_axi_rdata\(30);
s_axi_rdata(29) <= \^s_axi_rdata\(30);
s_axi_rdata(28) <= \^s_axi_rdata\(30);
s_axi_rdata(27) <= \^s_axi_rdata\(30);
s_axi_rdata(26) <= \^s_axi_rdata\(30);
s_axi_rdata(25) <= \^s_axi_rdata\(30);
s_axi_rdata(24) <= \^s_axi_rdata\(30);
s_axi_rdata(23) <= \^s_axi_rdata\(30);
s_axi_rdata(22) <= \^s_axi_rdata\(30);
s_axi_rdata(21) <= \^s_axi_rdata\(30);
s_axi_rdata(20) <= \^s_axi_rdata\(30);
s_axi_rdata(19) <= \^s_axi_rdata\(30);
s_axi_rdata(18) <= \^s_axi_rdata\(30);
s_axi_rdata(17) <= \^s_axi_rdata\(30);
s_axi_rdata(16) <= \^s_axi_rdata\(30);
s_axi_rdata(15) <= \^s_axi_rdata\(30);
s_axi_rdata(14) <= \^s_axi_rdata\(30);
s_axi_rdata(13) <= \^s_axi_rdata\(30);
s_axi_rdata(12) <= \^s_axi_rdata\(30);
s_axi_rdata(11) <= \^s_axi_rdata\(30);
s_axi_rdata(10) <= \^s_axi_rdata\(30);
s_axi_rdata(9) <= \^s_axi_rdata\(30);
s_axi_rdata(8) <= \^s_axi_rdata\(30);
s_axi_rdata(7) <= \^s_axi_rdata\(30);
s_axi_rdata(6) <= \^s_axi_rdata\(30);
s_axi_rdata(5) <= \^s_axi_rdata\(30);
s_axi_rdata(4) <= \^s_axi_rdata\(30);
s_axi_rdata(3) <= \^s_axi_rdata\(30);
s_axi_rdata(2) <= \^s_axi_rdata\(30);
s_axi_rdata(1 downto 0) <= \^s_axi_rdata\(1 downto 0);
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_wready <= \^s_axi_wready\;
AXI_LITE_IPIF_I: entity work.ip_design_axi_gpio_0_0_axi_lite_ipif
port map (
D(2) => ip2bus_data(0),
D(1) => ip2bus_data(30),
D(0) => ip2bus_data(31),
GPIO_xferAck_i => GPIO_xferAck_i,
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[0].reg1_reg[30]\ => AXI_LITE_IPIF_I_n_11,
\Not_Dual.ALLOUT0_ND.READ_REG_GEN[1].reg2_reg[31]\ => AXI_LITE_IPIF_I_n_12,
\Not_Dual.gpio_Data_Out_reg[0]\ => AXI_LITE_IPIF_I_n_7,
\Not_Dual.gpio_OE_reg[0]\ => AXI_LITE_IPIF_I_n_10,
Q(1) => bus2ip_addr(5),
Q(0) => bus2ip_addr(6),
bus2ip_cs => bus2ip_cs,
bus2ip_reset => bus2ip_reset,
bus2ip_rnw => bus2ip_rnw,
gpio_xferAck_Reg => gpio_xferAck_Reg,
\ip2bus_data_i_D1_reg[0]\(2) => ip2bus_data_i_D1(0),
\ip2bus_data_i_D1_reg[0]\(1) => ip2bus_data_i_D1(30),
\ip2bus_data_i_D1_reg[0]\(0) => ip2bus_data_i_D1(31),
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
reg1(1) => reg1(30),
reg1(0) => reg1(31),
reg2(1) => reg2(30),
reg2(0) => reg2(31),
s_axi_aclk => s_axi_aclk,
s_axi_araddr(2) => s_axi_araddr(8),
s_axi_araddr(1 downto 0) => s_axi_araddr(3 downto 2),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(2) => s_axi_awaddr(8),
s_axi_awaddr(1 downto 0) => s_axi_awaddr(3 downto 2),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(2) => \^s_axi_rdata\(30),
s_axi_rdata(1 downto 0) => \^s_axi_rdata\(1 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wready => \^s_axi_wready\,
s_axi_wvalid => s_axi_wvalid
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
gpio_core_1: entity work.ip_design_axi_gpio_0_0_GPIO_Core
port map (
GPIO_xferAck_i => GPIO_xferAck_i,
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\ => AXI_LITE_IPIF_I_n_12,
Q(1) => bus2ip_addr(5),
Q(0) => bus2ip_addr(6),
bus2ip_cs => bus2ip_cs,
bus2ip_reset => bus2ip_reset,
bus2ip_rnw => bus2ip_rnw,
bus2ip_rnw_i_reg => AXI_LITE_IPIF_I_n_11,
gpio_io_i(1 downto 0) => gpio_io_i(1 downto 0),
gpio_io_o(1 downto 0) => gpio_io_o(1 downto 0),
\gpio_io_t[0]\ => gpio_io_t(0),
\gpio_io_t[1]\ => gpio_io_t(1),
gpio_xferAck_Reg => gpio_xferAck_Reg,
ip2bus_rdack_i => ip2bus_rdack_i,
ip2bus_wrack_i_D1_reg => gpio_core_1_n_11,
reg1(1) => reg1(30),
reg1(0) => reg1(31),
reg2(1) => reg2(30),
reg2(0) => reg2(31),
rst_reg => AXI_LITE_IPIF_I_n_7,
rst_reg_0 => AXI_LITE_IPIF_I_n_10,
s_axi_aclk => s_axi_aclk,
s_axi_wdata(3 downto 2) => s_axi_wdata(31 downto 30),
s_axi_wdata(1 downto 0) => s_axi_wdata(1 downto 0)
);
\ip2bus_data_i_D1_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(0),
Q => ip2bus_data_i_D1(0),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(30),
Q => ip2bus_data_i_D1(30),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_data(31),
Q => ip2bus_data_i_D1(31),
R => bus2ip_reset
);
ip2bus_rdack_i_D1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_rdack_i,
Q => ip2bus_rdack_i_D1,
R => bus2ip_reset
);
ip2bus_wrack_i_D1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_core_1_n_11,
Q => ip2bus_wrack_i_D1,
R => bus2ip_reset
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ip_design_axi_gpio_0_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 1 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 1 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of ip_design_axi_gpio_0_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of ip_design_axi_gpio_0_0 : entity is "ip_design_axi_gpio_0_0,axi_gpio,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of ip_design_axi_gpio_0_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of ip_design_axi_gpio_0_0 : entity is "axi_gpio,Vivado 2017.3";
end ip_design_axi_gpio_0_0;
architecture STRUCTURE of ip_design_axi_gpio_0_0 is
signal NLW_U0_ip2intc_irpt_UNCONNECTED : STD_LOGIC;
signal NLW_U0_gpio2_io_o_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_gpio2_io_t_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
attribute C_ALL_INPUTS : integer;
attribute C_ALL_INPUTS of U0 : label is 0;
attribute C_ALL_INPUTS_2 : integer;
attribute C_ALL_INPUTS_2 of U0 : label is 0;
attribute C_ALL_OUTPUTS : integer;
attribute C_ALL_OUTPUTS of U0 : label is 0;
attribute C_ALL_OUTPUTS_2 : integer;
attribute C_ALL_OUTPUTS_2 of U0 : label is 0;
attribute C_DOUT_DEFAULT : integer;
attribute C_DOUT_DEFAULT of U0 : label is 0;
attribute C_DOUT_DEFAULT_2 : integer;
attribute C_DOUT_DEFAULT_2 of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_GPIO2_WIDTH : integer;
attribute C_GPIO2_WIDTH of U0 : label is 32;
attribute C_GPIO_WIDTH : integer;
attribute C_GPIO_WIDTH of U0 : label is 2;
attribute C_INTERRUPT_PRESENT : integer;
attribute C_INTERRUPT_PRESENT of U0 : label is 0;
attribute C_IS_DUAL : integer;
attribute C_IS_DUAL of U0 : label is 0;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of U0 : label is 9;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
attribute C_TRI_DEFAULT : integer;
attribute C_TRI_DEFAULT of U0 : label is -1;
attribute C_TRI_DEFAULT_2 : integer;
attribute C_TRI_DEFAULT_2 of U0 : label is -1;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
attribute ip_group : string;
attribute ip_group of U0 : label is "LOGICORE";
attribute x_interface_info : string;
attribute x_interface_info of s_axi_aclk : signal is "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
attribute x_interface_parameter : string;
attribute x_interface_parameter of s_axi_aclk : signal is "XIL_INTERFACENAME S_AXI_ACLK, ASSOCIATED_BUSIF S_AXI, ASSOCIATED_RESET s_axi_aresetn, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0";
attribute x_interface_info of s_axi_aresetn : signal is "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
attribute x_interface_parameter of s_axi_aresetn : signal is "XIL_INTERFACENAME S_AXI_ARESETN, POLARITY ACTIVE_LOW";
attribute x_interface_info of s_axi_arready : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
attribute x_interface_info of s_axi_arvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
attribute x_interface_info of s_axi_awready : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
attribute x_interface_info of s_axi_awvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
attribute x_interface_info of s_axi_bready : signal is "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
attribute x_interface_info of s_axi_bvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
attribute x_interface_info of s_axi_rready : signal is "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
attribute x_interface_info of s_axi_rvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
attribute x_interface_info of s_axi_wready : signal is "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
attribute x_interface_info of s_axi_wvalid : signal is "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
attribute x_interface_info of gpio_io_i : signal is "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
attribute x_interface_parameter of gpio_io_i : signal is "XIL_INTERFACENAME GPIO, BOARD.ASSOCIATED_PARAM GPIO_BOARD_INTERFACE";
attribute x_interface_info of gpio_io_o : signal is "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
attribute x_interface_info of gpio_io_t : signal is "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
attribute x_interface_info of s_axi_araddr : signal is "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
attribute x_interface_info of s_axi_awaddr : signal is "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
attribute x_interface_parameter of s_axi_awaddr : signal is "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 9, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 0, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0";
attribute x_interface_info of s_axi_bresp : signal is "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
attribute x_interface_info of s_axi_rdata : signal is "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
attribute x_interface_info of s_axi_rresp : signal is "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
attribute x_interface_info of s_axi_wdata : signal is "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
attribute x_interface_info of s_axi_wstrb : signal is "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
begin
U0: entity work.ip_design_axi_gpio_0_0_axi_gpio
port map (
gpio2_io_i(31 downto 0) => B"00000000000000000000000000000000",
gpio2_io_o(31 downto 0) => NLW_U0_gpio2_io_o_UNCONNECTED(31 downto 0),
gpio2_io_t(31 downto 0) => NLW_U0_gpio2_io_t_UNCONNECTED(31 downto 0),
gpio_io_i(1 downto 0) => gpio_io_i(1 downto 0),
gpio_io_o(1 downto 0) => gpio_io_o(1 downto 0),
gpio_io_t(1 downto 0) => gpio_io_t(1 downto 0),
ip2intc_irpt => NLW_U0_ip2intc_irpt_UNCONNECTED,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(8 downto 0) => s_axi_araddr(8 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(8 downto 0) => s_axi_awaddr(8 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY thermometersLogicTB IS
END thermometersLogicTB;
ARCHITECTURE behavior OF thermometersLogicTB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT thermometersLogic
PORT(
rsTxBusy : IN std_logic;
rst : IN std_logic;
clk50Mhz : IN std_logic;
clk3kHz : IN std_logic;
rsDataOut : OUT std_logic_vector(7 downto 0);
rsTxStart : OUT std_logic
);
END COMPONENT;
--Inputs
signal rsTxBusy : std_logic := '0';
signal rst : std_logic := '0';
signal clk50Mhz : std_logic := '0';
signal clk3kHz : std_logic := '0';
--Outputs
signal rsDataOut : std_logic_vector(7 downto 0);
signal rsTxStart : std_logic;
-- Clock period definitions
constant clk50Mhz_period : time := 20 ns;
constant clk3kHz_period : time := 327680 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: thermometersLogic PORT MAP (
rsTxBusy => rsTxBusy,
rst => rst,
clk50Mhz => clk50Mhz,
clk3kHz => clk3kHz,
rsDataOut => rsDataOut,
rsTxStart => rsTxStart
);
-- Clock process definitions
clk50Mhz_process :process
begin
clk50Mhz <= '0';
wait for clk50Mhz_period/2;
clk50Mhz <= '1';
wait for clk50Mhz_period/2;
end process;
clk3kHz_process :process
begin
clk3kHz <= '0';
wait for clk3kHz_period/2;
clk3kHz <= '1';
wait for clk3kHz_period/2;
end process;
rs232Proc: process(rsTxStart)
begin
if rsTxStart'event and rsTxStart = '1' then
rsTxBusy <= '1' after 20 ns, '0' after 78125 ns;
end if;
end process;
-- Stimulus process
stim_proc: process
begin
rst <= '1';
wait for 5 ns;
rst <= '0';
wait;
end process;
END;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_ec_e
--
-- Generated
-- by: wig
-- on: Mon Oct 10 12:25:03 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../bitsplice.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ec_e-e.vhd,v 1.3 2005/11/30 14:20:41 wig Exp $
-- $Date: 2005/11/30 14:20:41 $
-- $Log: inst_ec_e-e.vhd,v $
-- Revision 1.3 2005/11/30 14:20:41 wig
-- Updated testcase references
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.59 2005/10/06 11:21:44 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.37 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_ec_e
--
entity inst_ec_e is
-- Generics:
-- No Generated Generics for Entity inst_ec_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_ec_e
p_mix_c_addr_12_0_gi : in std_ulogic_vector(12 downto 0);
p_mix_c_bus_in_31_0_gi : in std_ulogic_vector(31 downto 0);
p_mix_v_select_2_2_gi : in std_ulogic;
p_mix_v_select_5_5_gi : in std_ulogic
-- End of Generated Port for Entity inst_ec_e
);
end inst_ec_e;
--
-- End of Generated Entity inst_ec_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
library verilog;
use verilog.vl_types.all;
entity datapath_vlg_vec_tst is
end datapath_vlg_vec_tst;
|
---------------------------------------------------------------------------------
--Generator------------------------------------------------------------
--By Kyle Williams, 04/07/2011--------------------------------------------------
--PROJECT DESCRIPTION------------------------------------------------------------
--1--Input Serial data stream----------------------------------------------------
----------------Define Libraries to be used--------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
-----------------ENTITY FOR GENERATOR------------------------------------------
ENTITY generator IS
Generic(N : Integer := 8);
PORT(
clock, reset, load: OUT std_logic;
D : OUT std_logic_vector(n-1 downto 0);
vec : OUT std_logic_vector(N-1 downto 0);
sin : OUT STD_Logic
);
END generator;
-----------------BEHAVIOR OF GENERATOR-----------------------------------------
ARCHITECTURE behavior OF generator IS
-------------------VARIABLE DECLARATION----------------------------------------
signal S_clock: std_logic := '0';
signal S_D: std_logic_vector(n-1 downto 0) := (others =>'0');
signal S_reset: std_logic := '0';
signal S_load: std_logic :='0';
signal tap: std_logic;
signal ssr: std_logic_vector(n-1 downto 0);
-------------------PROCEDUREE------------------------------
BEGIN
S_clock <= not S_clock after 5 ns;
S_D <= "10101011" after 250 ns;
S_reset <= '1' after 10 ns;
-- process
-- begin
-- S_load <= '1';
-- wait for 10 ns;
-- S_load <= '0';
-- wait for 10 ns;
-- end process;
clock <= S_clock;
reset <= S_reset;
load <= S_load;
D <= S_D;
Process(S_Clock,S_Reset,S_Load)
Begin
If(S_reset='0') then
SSR <= (others => '0');
elsif rising_edge(S_Clock) Then
IF S_Load = '1' AND (SSR="00000000" OR SSR="11111111") Then
SSR <= S_D;
ELSE
SSR<= SSR(6 downTo 0)&tap;
END If;
End If;
tap<=SSR(1) XOR SSR(2) XOR SSR(3) XOR SSR(7);
sin<= SSR(7);
vec<= SSR;
End Process;
END behavior;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1900.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01900ent_a IS
generic ( constant bus_width : natural);
port ( signal in_bus : in integer;
signal out_bus : out integer);
END c07s01b00x00p08n01i01900ent_a;
ARCHITECTURE c07s01b00x00p08n01i01900arch_a OF c07s01b00x00p08n01i01900ent_a IS
BEGIN
assert true;
END c07s01b00x00p08n01i01900arch_a;
ENTITY c07s01b00x00p08n01i01900ent IS
END c07s01b00x00p08n01i01900ent;
ARCHITECTURE c07s01b00x00p08n01i01900arch OF c07s01b00x00p08n01i01900ent IS
constant bus_width : natural:= 8;
signal s_int : integer;
signal ibus, obus, obus2 : integer;
component test
generic ( constant bus_width : natural := 5 );
port ( signal in_bus : in integer;
signal out_bus : out integer );
end component;
BEGIN
b: block ( s_int = 0 )
for c2 : test use entity work.ch0701_p00801_91_ent_a(c07s01b00x00p08n01i01900arch_a);
begin
p: process ( s_int )
begin
l: for i in 0 to 7 loop
assert false
report "process labels accepted as primary in a component instantiation generic map expression."
severity note ;
exit l;
end loop l;
end process p;
c2 : test generic map (p) -- process label illegal here
port map (ibus, obus2);
end block b;
TESTING : PROCESS
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01900 - Process labels are not permitted as primaries in a component instantiation generic map expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01900arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1900.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01900ent_a IS
generic ( constant bus_width : natural);
port ( signal in_bus : in integer;
signal out_bus : out integer);
END c07s01b00x00p08n01i01900ent_a;
ARCHITECTURE c07s01b00x00p08n01i01900arch_a OF c07s01b00x00p08n01i01900ent_a IS
BEGIN
assert true;
END c07s01b00x00p08n01i01900arch_a;
ENTITY c07s01b00x00p08n01i01900ent IS
END c07s01b00x00p08n01i01900ent;
ARCHITECTURE c07s01b00x00p08n01i01900arch OF c07s01b00x00p08n01i01900ent IS
constant bus_width : natural:= 8;
signal s_int : integer;
signal ibus, obus, obus2 : integer;
component test
generic ( constant bus_width : natural := 5 );
port ( signal in_bus : in integer;
signal out_bus : out integer );
end component;
BEGIN
b: block ( s_int = 0 )
for c2 : test use entity work.ch0701_p00801_91_ent_a(c07s01b00x00p08n01i01900arch_a);
begin
p: process ( s_int )
begin
l: for i in 0 to 7 loop
assert false
report "process labels accepted as primary in a component instantiation generic map expression."
severity note ;
exit l;
end loop l;
end process p;
c2 : test generic map (p) -- process label illegal here
port map (ibus, obus2);
end block b;
TESTING : PROCESS
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01900 - Process labels are not permitted as primaries in a component instantiation generic map expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01900arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1900.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01900ent_a IS
generic ( constant bus_width : natural);
port ( signal in_bus : in integer;
signal out_bus : out integer);
END c07s01b00x00p08n01i01900ent_a;
ARCHITECTURE c07s01b00x00p08n01i01900arch_a OF c07s01b00x00p08n01i01900ent_a IS
BEGIN
assert true;
END c07s01b00x00p08n01i01900arch_a;
ENTITY c07s01b00x00p08n01i01900ent IS
END c07s01b00x00p08n01i01900ent;
ARCHITECTURE c07s01b00x00p08n01i01900arch OF c07s01b00x00p08n01i01900ent IS
constant bus_width : natural:= 8;
signal s_int : integer;
signal ibus, obus, obus2 : integer;
component test
generic ( constant bus_width : natural := 5 );
port ( signal in_bus : in integer;
signal out_bus : out integer );
end component;
BEGIN
b: block ( s_int = 0 )
for c2 : test use entity work.ch0701_p00801_91_ent_a(c07s01b00x00p08n01i01900arch_a);
begin
p: process ( s_int )
begin
l: for i in 0 to 7 loop
assert false
report "process labels accepted as primary in a component instantiation generic map expression."
severity note ;
exit l;
end loop l;
end process p;
c2 : test generic map (p) -- process label illegal here
port map (ibus, obus2);
end block b;
TESTING : PROCESS
BEGIN
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01900 - Process labels are not permitted as primaries in a component instantiation generic map expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01900arch;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
------------------------------------------------------------
-- This file is automatically generated!
-- Here are the parameters:
-- network size x:2
-- network size y:2
------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.TB_Package.all;
USE ieee.numeric_std.ALL;
use IEEE.math_real."ceil";
use IEEE.math_real."log2";
entity tb_network_2x2 is
end tb_network_2x2;
architecture behavior of tb_network_2x2 is
-- Declaring network component
component network_2x2 is
generic (DATA_WIDTH: integer := 32; DATA_WIDTH_LV : integer:=11);
port (reset: in std_logic;
clk: in std_logic;
--------------
RX_L_0: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_0, valid_out_L_0: out std_logic;
credit_in_L_0, valid_in_L_0: in std_logic;
TX_L_0: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_1: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_1, valid_out_L_1: out std_logic;
credit_in_L_1, valid_in_L_1: in std_logic;
TX_L_1: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_2: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_2, valid_out_L_2: out std_logic;
credit_in_L_2, valid_in_L_2: in std_logic;
TX_L_2: out std_logic_vector (DATA_WIDTH-1 downto 0);
--------------
RX_L_3: in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_out_L_3, valid_out_L_3: out std_logic;
credit_in_L_3, valid_in_L_3: in std_logic;
TX_L_3: out std_logic_vector (DATA_WIDTH_LV-1 downto 0);
--------------
credit_in_LV_0: in std_logic;
valid_out_LV_0 : out std_logic;
TX_LV_0: out std_logic_vector (DATA_WIDTH_LV-1 downto 0);
--------------
credit_in_LV_1: in std_logic;
valid_out_LV_1 : out std_logic;
TX_LV_1: out std_logic_vector (DATA_WIDTH_LV-1 downto 0);
--------------
credit_in_LV_2: in std_logic;
valid_out_LV_2 : out std_logic;
TX_LV_2: out std_logic_vector (DATA_WIDTH_LV-1 downto 0);
--------------
credit_in_LV_3: in std_logic;
valid_out_LV_3 : out std_logic;
TX_LV_3: out std_logic_vector (DATA_WIDTH_LV-1 downto 0)
);
end component;
-- generating bulk signals...
signal RX_L_0, TX_L_0: std_logic_vector (31 downto 0);
signal credit_counter_out_0: std_logic_vector (1 downto 0);
signal credit_out_L_0, credit_in_L_0, valid_in_L_0, valid_out_L_0: std_logic;
signal RX_L_1, TX_L_1: std_logic_vector (31 downto 0);
signal credit_counter_out_1: std_logic_vector (1 downto 0);
signal credit_out_L_1, credit_in_L_1, valid_in_L_1, valid_out_L_1: std_logic;
signal RX_L_2, TX_L_2: std_logic_vector (31 downto 0);
signal credit_counter_out_2: std_logic_vector (1 downto 0);
signal credit_out_L_2, credit_in_L_2, valid_in_L_2, valid_out_L_2: std_logic;
signal RX_L_3, TX_L_3: std_logic_vector (31 downto 0);
signal credit_counter_out_3: std_logic_vector (1 downto 0);
signal credit_out_L_3, credit_in_L_3, valid_in_L_3, valid_out_L_3: std_logic;
signal credit_in_LV_0, credit_in_LV_1, credit_in_LV_2, credit_in_LV_3: std_logic;
signal valid_out_LV_0, valid_out_LV_1, valid_out_LV_2, valid_out_LV_3: std_logic;
signal TX_LV_0, TX_LV_1, TX_LV_2, TX_LV_3: std_logic_vector (10 downto 0);
--------------
constant clk_period : time := 1 ns;
signal reset,clk: std_logic :='0';
begin
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
reset <= '1' after 1 ns;
-- instantiating the network
NoC: network_2x2 generic map (DATA_WIDTH => 32, DATA_WIDTH_LV => 11)
PORT MAP (reset, clk,
RX_L_0, credit_out_L_0, valid_out_L_0, credit_in_L_0, valid_in_L_0, TX_L_0,
RX_L_1, credit_out_L_1, valid_out_L_1, credit_in_L_1, valid_in_L_1, TX_L_1,
RX_L_2, credit_out_L_2, valid_out_L_2, credit_in_L_2, valid_in_L_2, TX_L_2,
RX_L_3, credit_out_L_3, valid_out_L_3, credit_in_L_3, valid_in_L_3, TX_L_3,
credit_in_LV_0, valid_out_LV_0, TX_LV_0,
--------------
credit_in_LV_1,valid_out_LV_1,TX_LV_1,
--------------
credit_in_LV_2, valid_out_LV_2, TX_LV_2,
--------------
credit_in_LV_3,valid_out_LV_3,TX_LV_3);
-- connecting the packet generators
credit_counter_control(clk, credit_out_L_0, valid_in_L_0, credit_counter_out_0);
gen_random_packet(100, 0, 3, 8, 8, 10000 ns, clk, credit_counter_out_0, valid_in_L_0, RX_L_0);
credit_counter_control(clk, credit_out_L_1, valid_in_L_1, credit_counter_out_1);
gen_random_packet(100, 1, 38, 8, 8, 10000 ns, clk, credit_counter_out_1, valid_in_L_1, RX_L_1);
credit_counter_control(clk, credit_out_L_2, valid_in_L_2, credit_counter_out_2);
gen_random_packet(100, 2, 18, 8, 8, 10000 ns, clk, credit_counter_out_2, valid_in_L_2, RX_L_2);
credit_counter_control(clk, credit_out_L_3, valid_in_L_3, credit_counter_out_3);
gen_random_packet(100, 3, 21, 8, 8, 10000 ns, clk, credit_counter_out_3, valid_in_L_3, RX_L_3);
-- connecting the packet receivers
get_packet(32, 5, 0, clk, credit_in_L_0, valid_out_L_0, TX_L_0);
get_packet(32, 5, 1, clk, credit_in_L_1, valid_out_L_1, TX_L_1);
get_packet(32, 5, 2, clk, credit_in_L_2, valid_out_L_2, TX_L_2);
get_packet(32, 5, 3, clk, credit_in_L_3, valid_out_L_3, TX_L_3);
credit_in_LV_0 <= '1';
credit_in_LV_1 <= '1';
credit_in_LV_2 <= '1';
credit_in_LV_3 <= '1';
end;
|
----------------------------------------------------------------------
-- brdRstClk (for some Fusion (Embeded/Start/SCS) Dev Kit )
----------------------------------------------------------------------
-- (c) 2016 by Anton Mause
--
-- Board dependend reset and clock manipulation file.
-- Adjust i_clk from some known clock, so o_clk has BRD_OSC_CLK_MHZ.
-- See "brdConst_pkg.vhd" for specific BRD_OSC_CLK_MHZ values.
-- Sync up o_rst_n to fit to rising edge of o_clk.
--
----------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library fusion;
use fusion.all;
----------------------------------------------------------------------
entity brdRstClk is
port ( i_rst_n, i_clk : in std_logic;
o_rst_n, o_clk : out std_logic );
end brdRstClk;
----------------------------------------------------------------------
architecture rtl of brdRstClk is
signal s_tgl, s_dly_n, s_rst_n : std_logic;
begin
s_rst_n <= i_rst_n;
process(i_clk, s_rst_n)
begin
if s_rst_n = '0' then
s_dly_n <= '0';
s_tgl <= '0';
o_rst_n <= '0';
elsif (i_clk'event and i_clk = '1') then
s_dly_n <= '1';
s_tgl <= not s_tgl;
o_rst_n <= s_dly_n;
end if;
end process;
-- edit BRD_OSC_CLK_MHZ in brdConst_pkg too
o_clk <= i_clk; -- direct
--o_clk <= s_tgl; -- divided
end rtl;
----------------------------------------------------------------------
|
architecture ARCH of ENTITY1 is
begin
U_INST1 : INST1
generic map (
-- Keep Comment
G_GEN_1 => 3,-- Comment
-- Keep Comment
G_GEN_2 => 4, -- Comment
-- Keep Comment
G_GEN_3 => 5-- Comment
-- Keep Comment
)
port map (
-- Keep Comment
PORT_1 => w_port_1, -- Comment
-- Keep Comment
PORT_2 => w_port_2, -- Comment
-- Keep Comment
PORT_3 => w_port_3--Comment
-- Keep Comment
);
end architecture ARCH;
|
-----------------------------------------------------------------------
-- MULTIPLICAÇÃO POR SOMAS SUCESSIVAS
--
-- Mcando, Mcador - Multiplicando e Multiplicador, de N bits
-- start, endop - Início e fim de operação de multiplicação
-- produto - Resultado, com 2N bits
-----------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_unsigned.all;
entity multiplica is
generic(N: integer := 32);
port( Mcando: in std_logic_vector((N-1) downto 0);
Mcador: in std_logic_vector((N-1) downto 0);
clock,start: in std_logic;
endop: out std_logic;
produto: out std_logic_vector(2*N-1 downto 0));
end;
architecture multiplica of multiplica is
type State_type is (inicializa, desloca, calc, termina, fim);
signal EA: State_type;
signal regP : std_logic_vector( N*2 downto 0);
signal regB : std_logic_vector( N downto 0);
signal cont: integer;
begin
--
-- registradores regP, regB, produto, endop e contador de execução
--
process(start, clock)
begin
if start='1'then
regP( N*2 downto N) <= (others=>'0');
regP( N-1 downto 0) <= Mcador;
regB <= '0' & Mcando;
cont <= 1;
endop <= '0';
elsif clock'event and clock='1' then
if EA=calc and regP(0)='1' then
regP(N*2 downto N) <= regP(N*2 downto N) + regB;
elsif EA=desloca then
regP <= '0' & regP(N*2 downto 1);
cont <= cont + 1;
elsif EA=termina then
produto <= regP( N*2-1 downto 0);
endop <= '1';
elsif EA=fim then
endop <= '0';
end if;
end if;
end process;
-- maquina de estados para controlar a multiplicação
process (start, clock)
begin
if start='1'then
EA <= inicializa;
elsif clock'event and clock='1' then
case EA is
when inicializa => EA <= calc;
when calc => EA <= desloca;
when desloca => if cont=N then
EA <= termina;
else
EA <= calc;
end if;
when termina => EA <= fim; -- só serve para gerar o pulso em endop
when fim => EA <= fim;
end case;
end if;
end process;
end multiplica;
-----------------------------------------------------------------------
-- DIVISÃO
-----------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_unsigned.all;
entity divide is
generic(N: integer := 16);
port( divisor: in std_logic_vector( (N-1) downto 0);
dividendo: in std_logic_vector( (N-1) downto 0);
clock,start : in std_logic;
endop : out std_logic;
quociente : out std_logic_vector( N-1 downto 0);
resto : out std_logic_vector( N-1 downto 0));
end;
architecture divide of divide is
type State_type is (inicializa, desloca, calc, termina, fim);
signal EA: State_type;
signal regP : std_logic_vector( N*2 downto 0);
signal regB : std_logic_vector( N downto 0);
signal diferenca : std_logic_vector( N downto 0);
signal cont: integer;
begin
diferenca <= regP( N*2 downto N) - regB( N downto 0);
process(start, clock)
begin
if start='1'then
regP(N*2 downto N) <= (others=>'0');
regP(N-1 downto 0) <= dividendo;
regB <= '0' & divisor;
cont <= 1;
endop <= '0';
elsif clock'event and clock='1' then
if EA=desloca then
regP <= regP( N*2-1 downto 0) & regP(N*2);
elsif EA=calc then
if diferenca(N)='1' then
regP(0)<='0';
else
regP(0)<='1';
regP(N*2 downto N) <= diferenca;
end if;
cont <= cont + 1;
elsif EA=termina then
resto <= regP( N*2-1 downto N);
quociente <= regP( N-1 downto 0);
endop <= '1';
elsif EA=fim then
endop <= '0';
end if;
end if;
end process;
-- maquina de estados para controlar a DIVISAO
process (start, clock)
begin
if start='1'then
EA <= inicializa;
elsif clock'event and clock='1' then
case EA is
when inicializa => EA <= desloca;
when desloca => EA <= calc;
when calc => if cont=N then
EA <= termina;
else
EA <= desloca;
end if;
when termina => EA <= fim; -- só serve para gerar o pulso em endop
when fim => EA <= fim;
end case;
end if;
end process;
end divide;
|
-----------------------------------------------------------------------
-- MULTIPLICAÇÃO POR SOMAS SUCESSIVAS
--
-- Mcando, Mcador - Multiplicando e Multiplicador, de N bits
-- start, endop - Início e fim de operação de multiplicação
-- produto - Resultado, com 2N bits
-----------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_unsigned.all;
entity multiplica is
generic(N: integer := 32);
port( Mcando: in std_logic_vector((N-1) downto 0);
Mcador: in std_logic_vector((N-1) downto 0);
clock,start: in std_logic;
endop: out std_logic;
produto: out std_logic_vector(2*N-1 downto 0));
end;
architecture multiplica of multiplica is
type State_type is (inicializa, desloca, calc, termina, fim);
signal EA: State_type;
signal regP : std_logic_vector( N*2 downto 0);
signal regB : std_logic_vector( N downto 0);
signal cont: integer;
begin
--
-- registradores regP, regB, produto, endop e contador de execução
--
process(start, clock)
begin
if start='1'then
regP( N*2 downto N) <= (others=>'0');
regP( N-1 downto 0) <= Mcador;
regB <= '0' & Mcando;
cont <= 1;
endop <= '0';
elsif clock'event and clock='1' then
if EA=calc and regP(0)='1' then
regP(N*2 downto N) <= regP(N*2 downto N) + regB;
elsif EA=desloca then
regP <= '0' & regP(N*2 downto 1);
cont <= cont + 1;
elsif EA=termina then
produto <= regP( N*2-1 downto 0);
endop <= '1';
elsif EA=fim then
endop <= '0';
end if;
end if;
end process;
-- maquina de estados para controlar a multiplicação
process (start, clock)
begin
if start='1'then
EA <= inicializa;
elsif clock'event and clock='1' then
case EA is
when inicializa => EA <= calc;
when calc => EA <= desloca;
when desloca => if cont=N then
EA <= termina;
else
EA <= calc;
end if;
when termina => EA <= fim; -- só serve para gerar o pulso em endop
when fim => EA <= fim;
end case;
end if;
end process;
end multiplica;
-----------------------------------------------------------------------
-- DIVISÃO
-----------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_unsigned.all;
entity divide is
generic(N: integer := 16);
port( divisor: in std_logic_vector( (N-1) downto 0);
dividendo: in std_logic_vector( (N-1) downto 0);
clock,start : in std_logic;
endop : out std_logic;
quociente : out std_logic_vector( N-1 downto 0);
resto : out std_logic_vector( N-1 downto 0));
end;
architecture divide of divide is
type State_type is (inicializa, desloca, calc, termina, fim);
signal EA: State_type;
signal regP : std_logic_vector( N*2 downto 0);
signal regB : std_logic_vector( N downto 0);
signal diferenca : std_logic_vector( N downto 0);
signal cont: integer;
begin
diferenca <= regP( N*2 downto N) - regB( N downto 0);
process(start, clock)
begin
if start='1'then
regP(N*2 downto N) <= (others=>'0');
regP(N-1 downto 0) <= dividendo;
regB <= '0' & divisor;
cont <= 1;
endop <= '0';
elsif clock'event and clock='1' then
if EA=desloca then
regP <= regP( N*2-1 downto 0) & regP(N*2);
elsif EA=calc then
if diferenca(N)='1' then
regP(0)<='0';
else
regP(0)<='1';
regP(N*2 downto N) <= diferenca;
end if;
cont <= cont + 1;
elsif EA=termina then
resto <= regP( N*2-1 downto N);
quociente <= regP( N-1 downto 0);
endop <= '1';
elsif EA=fim then
endop <= '0';
end if;
end if;
end process;
-- maquina de estados para controlar a DIVISAO
process (start, clock)
begin
if start='1'then
EA <= inicializa;
elsif clock'event and clock='1' then
case EA is
when inicializa => EA <= desloca;
when desloca => EA <= calc;
when calc => if cont=N then
EA <= termina;
else
EA <= desloca;
end if;
when termina => EA <= fim; -- só serve para gerar o pulso em endop
when fim => EA <= fim;
end case;
end if;
end process;
end divide;
|
entity step2_eval is
end entity step2_eval;
library STD;
use STD.textio.all;
library WORK;
use WORK.pkg_readline.all;
use WORK.types.all;
use WORK.printer.all;
use WORK.reader.all;
architecture test of step2_eval is
procedure mal_READ(str: in string; ast: out mal_val_ptr; err: out mal_val_ptr) is
begin
read_str(str, ast, err);
end procedure mal_READ;
-- Forward declaration
procedure EVAL(ast: inout mal_val_ptr; env: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr);
procedure eval_native_func(func_sym: inout mal_val_ptr; args: inout mal_val_ptr; result: out mal_val_ptr) is
variable num_result: integer;
variable a: mal_seq_ptr;
begin
a := args.seq_val;
if func_sym.string_val.all = "+" then
new_number(a(0).number_val + a(1).number_val, result);
elsif func_sym.string_val.all = "-" then
new_number(a(0).number_val - a(1).number_val, result);
elsif func_sym.string_val.all = "*" then
new_number(a(0).number_val * a(1).number_val, result);
elsif func_sym.string_val.all = "/" then
new_number(a(0).number_val / a(1).number_val, result);
else
result := null;
end if;
end procedure eval_native_func;
procedure eval_ast_seq(ast_seq: inout mal_seq_ptr; env: inout mal_val_ptr; result: inout mal_seq_ptr; err: out mal_val_ptr) is
variable eval_err: mal_val_ptr;
begin
result := new mal_seq(0 to ast_seq'length - 1);
for i in result'range loop
EVAL(ast_seq(i), env, result(i), eval_err);
if eval_err /= null then
err := eval_err;
return;
end if;
end loop;
end procedure eval_ast_seq;
procedure eval_ast(ast: inout mal_val_ptr; env: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable key, val, eval_err: mal_val_ptr;
variable new_seq: mal_seq_ptr;
variable i: integer;
begin
case ast.val_type is
when mal_symbol =>
new_string(ast.string_val, key);
hashmap_get(env, key, val);
if val = null then
new_string("'" & ast.string_val.all & "' not found", err);
return;
end if;
result := val;
return;
when mal_list | mal_vector | mal_hashmap =>
eval_ast_seq(ast.seq_val, env, new_seq, eval_err);
if eval_err /= null then
err := eval_err;
return;
end if;
new_seq_obj(ast.val_type, new_seq, result);
return;
when others =>
result := ast;
return;
end case;
end procedure eval_ast;
procedure EVAL(ast: inout mal_val_ptr; env: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable a, call_args, sub_err: mal_val_ptr;
begin
if ast.val_type /= mal_list then
eval_ast(ast, env, result, err);
return;
end if;
if ast.seq_val'length = 0 then
result := ast;
return;
end if;
eval_ast(ast, env, a, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
seq_drop_prefix(a, 1, call_args);
eval_native_func(a.seq_val(0), call_args, result);
end procedure EVAL;
procedure mal_PRINT(exp: inout mal_val_ptr; result: out line) is
begin
pr_str(exp, true, result);
end procedure mal_PRINT;
procedure REP(str: in string; env: inout mal_val_ptr; result: out line; err: out mal_val_ptr) is
variable ast, eval_res, read_err, eval_err: mal_val_ptr;
begin
mal_READ(str, ast, read_err);
if read_err /= null then
err := read_err;
result := null;
return;
end if;
if ast = null then
result := null;
return;
end if;
EVAL(ast, env, eval_res, eval_err);
if eval_err /= null then
err := eval_err;
result := null;
return;
end if;
mal_PRINT(eval_res, result);
end procedure REP;
procedure repl is
variable is_eof: boolean;
variable input_line, result: line;
variable repl_seq: mal_seq_ptr;
variable repl_env, err: mal_val_ptr;
begin
repl_seq := new mal_seq(0 to 7);
new_string("+", repl_seq(0));
new_nativefn("+", repl_seq(1));
new_string("-", repl_seq(2));
new_nativefn("-", repl_seq(3));
new_string("*", repl_seq(4));
new_nativefn("*", repl_seq(5));
new_string("/", repl_seq(6));
new_nativefn("/", repl_seq(7));
new_seq_obj(mal_hashmap, repl_seq, repl_env);
loop
mal_readline("user> ", is_eof, input_line);
exit when is_eof;
next when input_line'length = 0;
REP(input_line.all, repl_env, result, err);
if err /= null then
pr_str(err, false, result);
result := new string'("Error: " & result.all);
end if;
if result /= null then
mal_printline(result.all);
end if;
deallocate(result);
deallocate(err);
end loop;
mal_printline("");
end procedure repl;
begin
repl;
end architecture test;
|
entity step2_eval is
end entity step2_eval;
library STD;
use STD.textio.all;
library WORK;
use WORK.pkg_readline.all;
use WORK.types.all;
use WORK.printer.all;
use WORK.reader.all;
architecture test of step2_eval is
procedure mal_READ(str: in string; ast: out mal_val_ptr; err: out mal_val_ptr) is
begin
read_str(str, ast, err);
end procedure mal_READ;
-- Forward declaration
procedure EVAL(ast: inout mal_val_ptr; env: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr);
procedure eval_native_func(func_sym: inout mal_val_ptr; args: inout mal_val_ptr; result: out mal_val_ptr) is
variable num_result: integer;
variable a: mal_seq_ptr;
begin
a := args.seq_val;
if func_sym.string_val.all = "+" then
new_number(a(0).number_val + a(1).number_val, result);
elsif func_sym.string_val.all = "-" then
new_number(a(0).number_val - a(1).number_val, result);
elsif func_sym.string_val.all = "*" then
new_number(a(0).number_val * a(1).number_val, result);
elsif func_sym.string_val.all = "/" then
new_number(a(0).number_val / a(1).number_val, result);
else
result := null;
end if;
end procedure eval_native_func;
procedure eval_ast_seq(ast_seq: inout mal_seq_ptr; env: inout mal_val_ptr; result: inout mal_seq_ptr; err: out mal_val_ptr) is
variable eval_err: mal_val_ptr;
begin
result := new mal_seq(0 to ast_seq'length - 1);
for i in result'range loop
EVAL(ast_seq(i), env, result(i), eval_err);
if eval_err /= null then
err := eval_err;
return;
end if;
end loop;
end procedure eval_ast_seq;
procedure eval_ast(ast: inout mal_val_ptr; env: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable key, val, eval_err: mal_val_ptr;
variable new_seq: mal_seq_ptr;
variable i: integer;
begin
case ast.val_type is
when mal_symbol =>
new_string(ast.string_val, key);
hashmap_get(env, key, val);
if val = null then
new_string("'" & ast.string_val.all & "' not found", err);
return;
end if;
result := val;
return;
when mal_list | mal_vector | mal_hashmap =>
eval_ast_seq(ast.seq_val, env, new_seq, eval_err);
if eval_err /= null then
err := eval_err;
return;
end if;
new_seq_obj(ast.val_type, new_seq, result);
return;
when others =>
result := ast;
return;
end case;
end procedure eval_ast;
procedure EVAL(ast: inout mal_val_ptr; env: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable a, call_args, sub_err: mal_val_ptr;
begin
if ast.val_type /= mal_list then
eval_ast(ast, env, result, err);
return;
end if;
if ast.seq_val'length = 0 then
result := ast;
return;
end if;
eval_ast(ast, env, a, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
seq_drop_prefix(a, 1, call_args);
eval_native_func(a.seq_val(0), call_args, result);
end procedure EVAL;
procedure mal_PRINT(exp: inout mal_val_ptr; result: out line) is
begin
pr_str(exp, true, result);
end procedure mal_PRINT;
procedure REP(str: in string; env: inout mal_val_ptr; result: out line; err: out mal_val_ptr) is
variable ast, eval_res, read_err, eval_err: mal_val_ptr;
begin
mal_READ(str, ast, read_err);
if read_err /= null then
err := read_err;
result := null;
return;
end if;
if ast = null then
result := null;
return;
end if;
EVAL(ast, env, eval_res, eval_err);
if eval_err /= null then
err := eval_err;
result := null;
return;
end if;
mal_PRINT(eval_res, result);
end procedure REP;
procedure repl is
variable is_eof: boolean;
variable input_line, result: line;
variable repl_seq: mal_seq_ptr;
variable repl_env, err: mal_val_ptr;
begin
repl_seq := new mal_seq(0 to 7);
new_string("+", repl_seq(0));
new_nativefn("+", repl_seq(1));
new_string("-", repl_seq(2));
new_nativefn("-", repl_seq(3));
new_string("*", repl_seq(4));
new_nativefn("*", repl_seq(5));
new_string("/", repl_seq(6));
new_nativefn("/", repl_seq(7));
new_seq_obj(mal_hashmap, repl_seq, repl_env);
loop
mal_readline("user> ", is_eof, input_line);
exit when is_eof;
next when input_line'length = 0;
REP(input_line.all, repl_env, result, err);
if err /= null then
pr_str(err, false, result);
result := new string'("Error: " & result.all);
end if;
if result /= null then
mal_printline(result.all);
end if;
deallocate(result);
deallocate(err);
end loop;
mal_printline("");
end procedure repl;
begin
repl;
end architecture test;
|
entity step2_eval is
end entity step2_eval;
library STD;
use STD.textio.all;
library WORK;
use WORK.pkg_readline.all;
use WORK.types.all;
use WORK.printer.all;
use WORK.reader.all;
architecture test of step2_eval is
procedure mal_READ(str: in string; ast: out mal_val_ptr; err: out mal_val_ptr) is
begin
read_str(str, ast, err);
end procedure mal_READ;
-- Forward declaration
procedure EVAL(ast: inout mal_val_ptr; env: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr);
procedure eval_native_func(func_sym: inout mal_val_ptr; args: inout mal_val_ptr; result: out mal_val_ptr) is
variable num_result: integer;
variable a: mal_seq_ptr;
begin
a := args.seq_val;
if func_sym.string_val.all = "+" then
new_number(a(0).number_val + a(1).number_val, result);
elsif func_sym.string_val.all = "-" then
new_number(a(0).number_val - a(1).number_val, result);
elsif func_sym.string_val.all = "*" then
new_number(a(0).number_val * a(1).number_val, result);
elsif func_sym.string_val.all = "/" then
new_number(a(0).number_val / a(1).number_val, result);
else
result := null;
end if;
end procedure eval_native_func;
procedure eval_ast_seq(ast_seq: inout mal_seq_ptr; env: inout mal_val_ptr; result: inout mal_seq_ptr; err: out mal_val_ptr) is
variable eval_err: mal_val_ptr;
begin
result := new mal_seq(0 to ast_seq'length - 1);
for i in result'range loop
EVAL(ast_seq(i), env, result(i), eval_err);
if eval_err /= null then
err := eval_err;
return;
end if;
end loop;
end procedure eval_ast_seq;
procedure eval_ast(ast: inout mal_val_ptr; env: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable key, val, eval_err: mal_val_ptr;
variable new_seq: mal_seq_ptr;
variable i: integer;
begin
case ast.val_type is
when mal_symbol =>
new_string(ast.string_val, key);
hashmap_get(env, key, val);
if val = null then
new_string("'" & ast.string_val.all & "' not found", err);
return;
end if;
result := val;
return;
when mal_list | mal_vector | mal_hashmap =>
eval_ast_seq(ast.seq_val, env, new_seq, eval_err);
if eval_err /= null then
err := eval_err;
return;
end if;
new_seq_obj(ast.val_type, new_seq, result);
return;
when others =>
result := ast;
return;
end case;
end procedure eval_ast;
procedure EVAL(ast: inout mal_val_ptr; env: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable a, call_args, sub_err: mal_val_ptr;
begin
if ast.val_type /= mal_list then
eval_ast(ast, env, result, err);
return;
end if;
if ast.seq_val'length = 0 then
result := ast;
return;
end if;
eval_ast(ast, env, a, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
seq_drop_prefix(a, 1, call_args);
eval_native_func(a.seq_val(0), call_args, result);
end procedure EVAL;
procedure mal_PRINT(exp: inout mal_val_ptr; result: out line) is
begin
pr_str(exp, true, result);
end procedure mal_PRINT;
procedure REP(str: in string; env: inout mal_val_ptr; result: out line; err: out mal_val_ptr) is
variable ast, eval_res, read_err, eval_err: mal_val_ptr;
begin
mal_READ(str, ast, read_err);
if read_err /= null then
err := read_err;
result := null;
return;
end if;
if ast = null then
result := null;
return;
end if;
EVAL(ast, env, eval_res, eval_err);
if eval_err /= null then
err := eval_err;
result := null;
return;
end if;
mal_PRINT(eval_res, result);
end procedure REP;
procedure repl is
variable is_eof: boolean;
variable input_line, result: line;
variable repl_seq: mal_seq_ptr;
variable repl_env, err: mal_val_ptr;
begin
repl_seq := new mal_seq(0 to 7);
new_string("+", repl_seq(0));
new_nativefn("+", repl_seq(1));
new_string("-", repl_seq(2));
new_nativefn("-", repl_seq(3));
new_string("*", repl_seq(4));
new_nativefn("*", repl_seq(5));
new_string("/", repl_seq(6));
new_nativefn("/", repl_seq(7));
new_seq_obj(mal_hashmap, repl_seq, repl_env);
loop
mal_readline("user> ", is_eof, input_line);
exit when is_eof;
next when input_line'length = 0;
REP(input_line.all, repl_env, result, err);
if err /= null then
pr_str(err, false, result);
result := new string'("Error: " & result.all);
end if;
if result /= null then
mal_printline(result.all);
end if;
deallocate(result);
deallocate(err);
end loop;
mal_printline("");
end procedure repl;
begin
repl;
end architecture test;
|
entity step2_eval is
end entity step2_eval;
library STD;
use STD.textio.all;
library WORK;
use WORK.pkg_readline.all;
use WORK.types.all;
use WORK.printer.all;
use WORK.reader.all;
architecture test of step2_eval is
procedure mal_READ(str: in string; ast: out mal_val_ptr; err: out mal_val_ptr) is
begin
read_str(str, ast, err);
end procedure mal_READ;
-- Forward declaration
procedure EVAL(ast: inout mal_val_ptr; env: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr);
procedure eval_native_func(func_sym: inout mal_val_ptr; args: inout mal_val_ptr; result: out mal_val_ptr) is
variable num_result: integer;
variable a: mal_seq_ptr;
begin
a := args.seq_val;
if func_sym.string_val.all = "+" then
new_number(a(0).number_val + a(1).number_val, result);
elsif func_sym.string_val.all = "-" then
new_number(a(0).number_val - a(1).number_val, result);
elsif func_sym.string_val.all = "*" then
new_number(a(0).number_val * a(1).number_val, result);
elsif func_sym.string_val.all = "/" then
new_number(a(0).number_val / a(1).number_val, result);
else
result := null;
end if;
end procedure eval_native_func;
procedure eval_ast_seq(ast_seq: inout mal_seq_ptr; env: inout mal_val_ptr; result: inout mal_seq_ptr; err: out mal_val_ptr) is
variable eval_err: mal_val_ptr;
begin
result := new mal_seq(0 to ast_seq'length - 1);
for i in result'range loop
EVAL(ast_seq(i), env, result(i), eval_err);
if eval_err /= null then
err := eval_err;
return;
end if;
end loop;
end procedure eval_ast_seq;
procedure eval_ast(ast: inout mal_val_ptr; env: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable key, val, eval_err: mal_val_ptr;
variable new_seq: mal_seq_ptr;
variable i: integer;
begin
case ast.val_type is
when mal_symbol =>
new_string(ast.string_val, key);
hashmap_get(env, key, val);
if val = null then
new_string("'" & ast.string_val.all & "' not found", err);
return;
end if;
result := val;
return;
when mal_list | mal_vector | mal_hashmap =>
eval_ast_seq(ast.seq_val, env, new_seq, eval_err);
if eval_err /= null then
err := eval_err;
return;
end if;
new_seq_obj(ast.val_type, new_seq, result);
return;
when others =>
result := ast;
return;
end case;
end procedure eval_ast;
procedure EVAL(ast: inout mal_val_ptr; env: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable a, call_args, sub_err: mal_val_ptr;
begin
if ast.val_type /= mal_list then
eval_ast(ast, env, result, err);
return;
end if;
if ast.seq_val'length = 0 then
result := ast;
return;
end if;
eval_ast(ast, env, a, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
seq_drop_prefix(a, 1, call_args);
eval_native_func(a.seq_val(0), call_args, result);
end procedure EVAL;
procedure mal_PRINT(exp: inout mal_val_ptr; result: out line) is
begin
pr_str(exp, true, result);
end procedure mal_PRINT;
procedure REP(str: in string; env: inout mal_val_ptr; result: out line; err: out mal_val_ptr) is
variable ast, eval_res, read_err, eval_err: mal_val_ptr;
begin
mal_READ(str, ast, read_err);
if read_err /= null then
err := read_err;
result := null;
return;
end if;
if ast = null then
result := null;
return;
end if;
EVAL(ast, env, eval_res, eval_err);
if eval_err /= null then
err := eval_err;
result := null;
return;
end if;
mal_PRINT(eval_res, result);
end procedure REP;
procedure repl is
variable is_eof: boolean;
variable input_line, result: line;
variable repl_seq: mal_seq_ptr;
variable repl_env, err: mal_val_ptr;
begin
repl_seq := new mal_seq(0 to 7);
new_string("+", repl_seq(0));
new_nativefn("+", repl_seq(1));
new_string("-", repl_seq(2));
new_nativefn("-", repl_seq(3));
new_string("*", repl_seq(4));
new_nativefn("*", repl_seq(5));
new_string("/", repl_seq(6));
new_nativefn("/", repl_seq(7));
new_seq_obj(mal_hashmap, repl_seq, repl_env);
loop
mal_readline("user> ", is_eof, input_line);
exit when is_eof;
next when input_line'length = 0;
REP(input_line.all, repl_env, result, err);
if err /= null then
pr_str(err, false, result);
result := new string'("Error: " & result.all);
end if;
if result /= null then
mal_printline(result.all);
end if;
deallocate(result);
deallocate(err);
end loop;
mal_printline("");
end procedure repl;
begin
repl;
end architecture test;
|
entity step2_eval is
end entity step2_eval;
library STD;
use STD.textio.all;
library WORK;
use WORK.pkg_readline.all;
use WORK.types.all;
use WORK.printer.all;
use WORK.reader.all;
architecture test of step2_eval is
procedure mal_READ(str: in string; ast: out mal_val_ptr; err: out mal_val_ptr) is
begin
read_str(str, ast, err);
end procedure mal_READ;
-- Forward declaration
procedure EVAL(ast: inout mal_val_ptr; env: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr);
procedure eval_native_func(func_sym: inout mal_val_ptr; args: inout mal_val_ptr; result: out mal_val_ptr) is
variable num_result: integer;
variable a: mal_seq_ptr;
begin
a := args.seq_val;
if func_sym.string_val.all = "+" then
new_number(a(0).number_val + a(1).number_val, result);
elsif func_sym.string_val.all = "-" then
new_number(a(0).number_val - a(1).number_val, result);
elsif func_sym.string_val.all = "*" then
new_number(a(0).number_val * a(1).number_val, result);
elsif func_sym.string_val.all = "/" then
new_number(a(0).number_val / a(1).number_val, result);
else
result := null;
end if;
end procedure eval_native_func;
procedure eval_ast_seq(ast_seq: inout mal_seq_ptr; env: inout mal_val_ptr; result: inout mal_seq_ptr; err: out mal_val_ptr) is
variable eval_err: mal_val_ptr;
begin
result := new mal_seq(0 to ast_seq'length - 1);
for i in result'range loop
EVAL(ast_seq(i), env, result(i), eval_err);
if eval_err /= null then
err := eval_err;
return;
end if;
end loop;
end procedure eval_ast_seq;
procedure eval_ast(ast: inout mal_val_ptr; env: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable key, val, eval_err: mal_val_ptr;
variable new_seq: mal_seq_ptr;
variable i: integer;
begin
case ast.val_type is
when mal_symbol =>
new_string(ast.string_val, key);
hashmap_get(env, key, val);
if val = null then
new_string("'" & ast.string_val.all & "' not found", err);
return;
end if;
result := val;
return;
when mal_list | mal_vector | mal_hashmap =>
eval_ast_seq(ast.seq_val, env, new_seq, eval_err);
if eval_err /= null then
err := eval_err;
return;
end if;
new_seq_obj(ast.val_type, new_seq, result);
return;
when others =>
result := ast;
return;
end case;
end procedure eval_ast;
procedure EVAL(ast: inout mal_val_ptr; env: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable a, call_args, sub_err: mal_val_ptr;
begin
if ast.val_type /= mal_list then
eval_ast(ast, env, result, err);
return;
end if;
if ast.seq_val'length = 0 then
result := ast;
return;
end if;
eval_ast(ast, env, a, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
seq_drop_prefix(a, 1, call_args);
eval_native_func(a.seq_val(0), call_args, result);
end procedure EVAL;
procedure mal_PRINT(exp: inout mal_val_ptr; result: out line) is
begin
pr_str(exp, true, result);
end procedure mal_PRINT;
procedure REP(str: in string; env: inout mal_val_ptr; result: out line; err: out mal_val_ptr) is
variable ast, eval_res, read_err, eval_err: mal_val_ptr;
begin
mal_READ(str, ast, read_err);
if read_err /= null then
err := read_err;
result := null;
return;
end if;
if ast = null then
result := null;
return;
end if;
EVAL(ast, env, eval_res, eval_err);
if eval_err /= null then
err := eval_err;
result := null;
return;
end if;
mal_PRINT(eval_res, result);
end procedure REP;
procedure repl is
variable is_eof: boolean;
variable input_line, result: line;
variable repl_seq: mal_seq_ptr;
variable repl_env, err: mal_val_ptr;
begin
repl_seq := new mal_seq(0 to 7);
new_string("+", repl_seq(0));
new_nativefn("+", repl_seq(1));
new_string("-", repl_seq(2));
new_nativefn("-", repl_seq(3));
new_string("*", repl_seq(4));
new_nativefn("*", repl_seq(5));
new_string("/", repl_seq(6));
new_nativefn("/", repl_seq(7));
new_seq_obj(mal_hashmap, repl_seq, repl_env);
loop
mal_readline("user> ", is_eof, input_line);
exit when is_eof;
next when input_line'length = 0;
REP(input_line.all, repl_env, result, err);
if err /= null then
pr_str(err, false, result);
result := new string'("Error: " & result.all);
end if;
if result /= null then
mal_printline(result.all);
end if;
deallocate(result);
deallocate(err);
end loop;
mal_printline("");
end procedure repl;
begin
repl;
end architecture test;
|
entity step2_eval is
end entity step2_eval;
library STD;
use STD.textio.all;
library WORK;
use WORK.pkg_readline.all;
use WORK.types.all;
use WORK.printer.all;
use WORK.reader.all;
architecture test of step2_eval is
procedure mal_READ(str: in string; ast: out mal_val_ptr; err: out mal_val_ptr) is
begin
read_str(str, ast, err);
end procedure mal_READ;
-- Forward declaration
procedure EVAL(ast: inout mal_val_ptr; env: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr);
procedure eval_native_func(func_sym: inout mal_val_ptr; args: inout mal_val_ptr; result: out mal_val_ptr) is
variable num_result: integer;
variable a: mal_seq_ptr;
begin
a := args.seq_val;
if func_sym.string_val.all = "+" then
new_number(a(0).number_val + a(1).number_val, result);
elsif func_sym.string_val.all = "-" then
new_number(a(0).number_val - a(1).number_val, result);
elsif func_sym.string_val.all = "*" then
new_number(a(0).number_val * a(1).number_val, result);
elsif func_sym.string_val.all = "/" then
new_number(a(0).number_val / a(1).number_val, result);
else
result := null;
end if;
end procedure eval_native_func;
procedure eval_ast_seq(ast_seq: inout mal_seq_ptr; env: inout mal_val_ptr; result: inout mal_seq_ptr; err: out mal_val_ptr) is
variable eval_err: mal_val_ptr;
begin
result := new mal_seq(0 to ast_seq'length - 1);
for i in result'range loop
EVAL(ast_seq(i), env, result(i), eval_err);
if eval_err /= null then
err := eval_err;
return;
end if;
end loop;
end procedure eval_ast_seq;
procedure eval_ast(ast: inout mal_val_ptr; env: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable key, val, eval_err: mal_val_ptr;
variable new_seq: mal_seq_ptr;
variable i: integer;
begin
case ast.val_type is
when mal_symbol =>
new_string(ast.string_val, key);
hashmap_get(env, key, val);
if val = null then
new_string("'" & ast.string_val.all & "' not found", err);
return;
end if;
result := val;
return;
when mal_list | mal_vector | mal_hashmap =>
eval_ast_seq(ast.seq_val, env, new_seq, eval_err);
if eval_err /= null then
err := eval_err;
return;
end if;
new_seq_obj(ast.val_type, new_seq, result);
return;
when others =>
result := ast;
return;
end case;
end procedure eval_ast;
procedure EVAL(ast: inout mal_val_ptr; env: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable a, call_args, sub_err: mal_val_ptr;
begin
if ast.val_type /= mal_list then
eval_ast(ast, env, result, err);
return;
end if;
if ast.seq_val'length = 0 then
result := ast;
return;
end if;
eval_ast(ast, env, a, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
seq_drop_prefix(a, 1, call_args);
eval_native_func(a.seq_val(0), call_args, result);
end procedure EVAL;
procedure mal_PRINT(exp: inout mal_val_ptr; result: out line) is
begin
pr_str(exp, true, result);
end procedure mal_PRINT;
procedure REP(str: in string; env: inout mal_val_ptr; result: out line; err: out mal_val_ptr) is
variable ast, eval_res, read_err, eval_err: mal_val_ptr;
begin
mal_READ(str, ast, read_err);
if read_err /= null then
err := read_err;
result := null;
return;
end if;
if ast = null then
result := null;
return;
end if;
EVAL(ast, env, eval_res, eval_err);
if eval_err /= null then
err := eval_err;
result := null;
return;
end if;
mal_PRINT(eval_res, result);
end procedure REP;
procedure repl is
variable is_eof: boolean;
variable input_line, result: line;
variable repl_seq: mal_seq_ptr;
variable repl_env, err: mal_val_ptr;
begin
repl_seq := new mal_seq(0 to 7);
new_string("+", repl_seq(0));
new_nativefn("+", repl_seq(1));
new_string("-", repl_seq(2));
new_nativefn("-", repl_seq(3));
new_string("*", repl_seq(4));
new_nativefn("*", repl_seq(5));
new_string("/", repl_seq(6));
new_nativefn("/", repl_seq(7));
new_seq_obj(mal_hashmap, repl_seq, repl_env);
loop
mal_readline("user> ", is_eof, input_line);
exit when is_eof;
next when input_line'length = 0;
REP(input_line.all, repl_env, result, err);
if err /= null then
pr_str(err, false, result);
result := new string'("Error: " & result.all);
end if;
if result /= null then
mal_printline(result.all);
end if;
deallocate(result);
deallocate(err);
end loop;
mal_printline("");
end procedure repl;
begin
repl;
end architecture test;
|
entity step2_eval is
end entity step2_eval;
library STD;
use STD.textio.all;
library WORK;
use WORK.pkg_readline.all;
use WORK.types.all;
use WORK.printer.all;
use WORK.reader.all;
architecture test of step2_eval is
procedure mal_READ(str: in string; ast: out mal_val_ptr; err: out mal_val_ptr) is
begin
read_str(str, ast, err);
end procedure mal_READ;
-- Forward declaration
procedure EVAL(ast: inout mal_val_ptr; env: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr);
procedure eval_native_func(func_sym: inout mal_val_ptr; args: inout mal_val_ptr; result: out mal_val_ptr) is
variable num_result: integer;
variable a: mal_seq_ptr;
begin
a := args.seq_val;
if func_sym.string_val.all = "+" then
new_number(a(0).number_val + a(1).number_val, result);
elsif func_sym.string_val.all = "-" then
new_number(a(0).number_val - a(1).number_val, result);
elsif func_sym.string_val.all = "*" then
new_number(a(0).number_val * a(1).number_val, result);
elsif func_sym.string_val.all = "/" then
new_number(a(0).number_val / a(1).number_val, result);
else
result := null;
end if;
end procedure eval_native_func;
procedure eval_ast_seq(ast_seq: inout mal_seq_ptr; env: inout mal_val_ptr; result: inout mal_seq_ptr; err: out mal_val_ptr) is
variable eval_err: mal_val_ptr;
begin
result := new mal_seq(0 to ast_seq'length - 1);
for i in result'range loop
EVAL(ast_seq(i), env, result(i), eval_err);
if eval_err /= null then
err := eval_err;
return;
end if;
end loop;
end procedure eval_ast_seq;
procedure eval_ast(ast: inout mal_val_ptr; env: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable key, val, eval_err: mal_val_ptr;
variable new_seq: mal_seq_ptr;
variable i: integer;
begin
case ast.val_type is
when mal_symbol =>
new_string(ast.string_val, key);
hashmap_get(env, key, val);
if val = null then
new_string("'" & ast.string_val.all & "' not found", err);
return;
end if;
result := val;
return;
when mal_list | mal_vector | mal_hashmap =>
eval_ast_seq(ast.seq_val, env, new_seq, eval_err);
if eval_err /= null then
err := eval_err;
return;
end if;
new_seq_obj(ast.val_type, new_seq, result);
return;
when others =>
result := ast;
return;
end case;
end procedure eval_ast;
procedure EVAL(ast: inout mal_val_ptr; env: inout mal_val_ptr; result: out mal_val_ptr; err: out mal_val_ptr) is
variable a, call_args, sub_err: mal_val_ptr;
begin
if ast.val_type /= mal_list then
eval_ast(ast, env, result, err);
return;
end if;
if ast.seq_val'length = 0 then
result := ast;
return;
end if;
eval_ast(ast, env, a, sub_err);
if sub_err /= null then
err := sub_err;
return;
end if;
seq_drop_prefix(a, 1, call_args);
eval_native_func(a.seq_val(0), call_args, result);
end procedure EVAL;
procedure mal_PRINT(exp: inout mal_val_ptr; result: out line) is
begin
pr_str(exp, true, result);
end procedure mal_PRINT;
procedure REP(str: in string; env: inout mal_val_ptr; result: out line; err: out mal_val_ptr) is
variable ast, eval_res, read_err, eval_err: mal_val_ptr;
begin
mal_READ(str, ast, read_err);
if read_err /= null then
err := read_err;
result := null;
return;
end if;
if ast = null then
result := null;
return;
end if;
EVAL(ast, env, eval_res, eval_err);
if eval_err /= null then
err := eval_err;
result := null;
return;
end if;
mal_PRINT(eval_res, result);
end procedure REP;
procedure repl is
variable is_eof: boolean;
variable input_line, result: line;
variable repl_seq: mal_seq_ptr;
variable repl_env, err: mal_val_ptr;
begin
repl_seq := new mal_seq(0 to 7);
new_string("+", repl_seq(0));
new_nativefn("+", repl_seq(1));
new_string("-", repl_seq(2));
new_nativefn("-", repl_seq(3));
new_string("*", repl_seq(4));
new_nativefn("*", repl_seq(5));
new_string("/", repl_seq(6));
new_nativefn("/", repl_seq(7));
new_seq_obj(mal_hashmap, repl_seq, repl_env);
loop
mal_readline("user> ", is_eof, input_line);
exit when is_eof;
next when input_line'length = 0;
REP(input_line.all, repl_env, result, err);
if err /= null then
pr_str(err, false, result);
result := new string'("Error: " & result.all);
end if;
if result /= null then
mal_printline(result.all);
end if;
deallocate(result);
deallocate(err);
end loop;
mal_printline("");
end procedure repl;
begin
repl;
end architecture test;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Fri Oct 27 14:51:03 2017
-- Host : Juice-Laptop running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/RATCPU/Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_Counter10bit_0_0/RAT_Counter10bit_0_0_stub.vhdl
-- Design : RAT_Counter10bit_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity RAT_Counter10bit_0_0 is
Port (
Din : in STD_LOGIC_VECTOR ( 0 to 9 );
LOAD : in STD_LOGIC;
INC : in STD_LOGIC;
RESET : in STD_LOGIC;
CLK : in STD_LOGIC;
COUNT : out STD_LOGIC_VECTOR ( 0 to 9 )
);
end RAT_Counter10bit_0_0;
architecture stub of RAT_Counter10bit_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "Din[0:9],LOAD,INC,RESET,CLK,COUNT[0:9]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "Counter10bit,Vivado 2016.4";
begin
end;
|
--This is an autogenerated file
--Do not modify it by hand
--Generated at 2017-12-08T14:22:41+13:00
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.enforcement_types_PaceEnforcer.all;
entity PaceEnforcer_enforcer_AEI is
port
(
clk : in std_logic;
reset : in std_logic;
t : in unsigned(63 downto 0); --current time in nanoseconds
e : out std_logic; --if enforcement occured
--the input signals
AEI_time : unsigned(63 downto 0) := to_unsigned( 900000000, 64);
--the IN enforce signals (from PLANT to CONTROLLER), and changed by EditI rules
q_ptc : in PaceEnforcer_types_plant_to_controller_enforced_signals;
q_ptc_prime : out PaceEnforcer_types_plant_to_controller_enforced_signals;
--the OUT enforce signals (from CONTROLLER to PLANT), and changed by EditO rules
q_ctp : in PaceEnforcer_types_controller_to_plant_enforced_signals;
q_ctp_prime : out PaceEnforcer_types_controller_to_plant_enforced_signals
);
end entity;
architecture behaviour of PaceEnforcer_enforcer_AEI is
signal trigger_tAEI : std_logic := '0';
signal trigger_tAEI_time : unsigned(63 downto 0) := (others => '0');
begin
--trigger process
process(reset, clk, q, t)
variable q_enf: enforced_signals_PaceEnforcer;
begin
if(rising_edge(clk)) then
--default values
q_enf := q;
e <= '0';
--policies begin
if((trigger_tAEI = '1') and not(((q_enf.AS or q_enf.AP) = '1')) and (t > (AEI_time + trigger_tAEI_time)) ) then
e <= '1';
--recover
q_enf.AP := '1';
end if;
--Triggers begin (triggers are after policies because a policy might edit a value that a trigger depends on)
if(trigger_tAEI = '0' and (((q_enf.VS or q_enf.VP) = '1'))) then
trigger_tAEI <= '1';
trigger_tAEI_time <= t;
end if;
if(trigger_tAEI = '1' and (((q_enf.AS or q_enf.AP) = '1'))) then
trigger_tAEI <= '0';
end if;
q_prime <= q_enf;
end if;
end process;
end architecture;
|
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`protect begin_protected
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`protect end_protected
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "uart_tx"
-------------------------------------------------------------------------------
-- Author : Fabian Greif
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.uart_pkg.all;
-------------------------------------------------------------------------------
entity uart_tx_tb is
end entity uart_tx_tb;
-------------------------------------------------------------------------------
architecture behavourial of uart_tx_tb is
-- component ports
signal txd : std_logic;
signal busy : std_logic;
signal data : std_logic_vector(7 downto 0) := (others => '0');
signal empty : std_logic := '1';
signal re : std_logic;
signal clk_tx_en : std_logic := '0';
signal clk : std_logic := '0';
begin
-- component instantiation
dut : entity work.uart_tx
port map (
txd_p => txd,
busy_p => busy,
data_p => data,
empty_p => empty,
re_p => re,
clk_tx_en => clk_tx_en,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
-- Generate a bit clock
bitclock : process
begin
wait until rising_edge(clk);
clk_tx_en <= '1';
wait until rising_edge(clk);
clk_tx_en <= '0';
wait for 40 ns;
end process bitclock;
-- waveform generation
waveform : process
begin
wait until rising_edge(clk);
empty <= '0';
data <= "00000000"; -- partiy = 1
wait until falling_edge(re);
data <= "11001010"; -- partiy = 1
wait until falling_edge(re);
data <= "00001011"; -- partiy = 0
wait until falling_edge(re);
empty <= '1';
wait for 2 us;
empty <= '0';
data <= "11100101"; -- partiy = 0
wait until falling_edge(re);
data <= "11100100"; -- partiy = 1
wait until falling_edge(re);
empty <= '1';
wait;
end process waveform;
end architecture behavourial;
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "uart_tx"
-------------------------------------------------------------------------------
-- Author : Fabian Greif
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.uart_pkg.all;
-------------------------------------------------------------------------------
entity uart_tx_tb is
end entity uart_tx_tb;
-------------------------------------------------------------------------------
architecture behavourial of uart_tx_tb is
-- component ports
signal txd : std_logic;
signal busy : std_logic;
signal data : std_logic_vector(7 downto 0) := (others => '0');
signal empty : std_logic := '1';
signal re : std_logic;
signal clk_tx_en : std_logic := '0';
signal clk : std_logic := '0';
begin
-- component instantiation
dut : entity work.uart_tx
port map (
txd_p => txd,
busy_p => busy,
data_p => data,
empty_p => empty,
re_p => re,
clk_tx_en => clk_tx_en,
clk => clk);
-- clock generation
clk <= not clk after 10 ns;
-- Generate a bit clock
bitclock : process
begin
wait until rising_edge(clk);
clk_tx_en <= '1';
wait until rising_edge(clk);
clk_tx_en <= '0';
wait for 40 ns;
end process bitclock;
-- waveform generation
waveform : process
begin
wait until rising_edge(clk);
empty <= '0';
data <= "00000000"; -- partiy = 1
wait until falling_edge(re);
data <= "11001010"; -- partiy = 1
wait until falling_edge(re);
data <= "00001011"; -- partiy = 0
wait until falling_edge(re);
empty <= '1';
wait for 2 us;
empty <= '0';
data <= "11100101"; -- partiy = 0
wait until falling_edge(re);
data <= "11100100"; -- partiy = 1
wait until falling_edge(re);
empty <= '1';
wait;
end process waveform;
end architecture behavourial;
|
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