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-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1174.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s06b00x00p06n01i01174ent IS
END c06s06b00x00p06n01i01174ent;
ARCHITECTURE c06s06b00x00p06n01i01174arch OF c06s06b00x00p06n01i01174ent IS
signal POS : Integer;
attribute PIO : positive;
attribute PIO of POS : signal is 10; -- No_failure_here
BEGIN
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT(POS'PIO = 10)
report "***PASSED TEST: c06s06b00x00p06n01i01174"
severity NOTE;
assert (POS'PIO = 10)
report "***FAILED TEST: c06s06b00x00p06n01i01174 - If the attribute designator does not denote a predefined attribute, the static expression in the attribute name must not be present."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s06b00x00p06n01i01174arch;
|
--
-- An array of 2048 bytes that works as a framebuffer for the vgaDriverBuffer
-- module. Holds the RGB pixel data for each location.
--
-- Original author: unknown
--
-- Peter Heatwole, Aaron Barton
-- CPE233, Winter 2012, CalPoly
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ram2k_8 is
port(clk: in STD_LOGIC;
we: in STD_LOGIC;
ra, wa: in STD_LOGIC_VECTOR(10 downto 0);
wd: in STD_LOGIC_VECTOR(7 downto 0);
rd: out STD_LOGIC_VECTOR(7 downto 0);
pixelVal: out STD_LOGIC_VECTOR(7 downto 0)
);
end ram2k_8;
architecture Behavioral of ram2k_8 is
type ramtype is array (2047 downto 0) of STD_LOGIC_VECTOR(7 downto 0);
signal mem: ramtype := (OTHERS => "11100000");
begin
-- three-ported register file
-- read two ports combinationally
-- write third port on rising edge of clock
process(clk) begin
if (clk'event and clk = '1') then
if we = '1' then mem(CONV_INTEGER(wa)) <= wd;
end if;
end if;
end process;
rd <= mem(CONV_INTEGER(ra));
pixelVal <= mem(CONV_INTEGER(wa));
end Behavioral;
|
architecture RTL of FIFO is
signal s_sig1 : std_logic;
signal s_sig2 : std_logic;
-- Violations below
signal sig1 : std_logic;
signal sig2 : std_logic;
begin
end architecture RTL;
|
/***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented in
/ Vivado by Xilinx
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/ This is a testbench generated for the adder module.
/
**************************************************************************************************/
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
library work;
use work.common_data_types_pkg.all;
use work.common_pkg.all;
use work.fixed_generic_pkg.all;
use work.adder_pkg.all;
use work.tb_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity adder_tb is
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture adder_tb1 of adder_tb is
/* constants */
/**************************************************************************************************/
constant UNSIGNED_2COMP_opt : boolean_tb := (true, false); --default
constant DATA_IMM_AFTER_START_opt : boolean_tb := (false, true); --default
constant SPEED_opt : T_speed_tb := (t_medium, true); --exception: value not set
constant MAX_POSSIBLE_BIT_opt : integer_exc_tb := (2, false); --exception: value not set
constant TRUNCATE_TO_BIT_opt : integer_exc_tb := (-2, false); --exception: value not set
constant S : positive := 2; --compulsory
constant used_UNSIGNED_2COMP_opt : boolean := value_used(UNSIGNED_2COMP_opt, false);
constant used_DATA_IMM_AFTER_START_opt : boolean := value_used(DATA_IMM_AFTER_START_opt, false);
constant used_SPEED_opt : T_speed := value_used(SPEED_opt);
constant used_MAX_POSSIBLE_BIT_opt : integer_exc := value_used(MAX_POSSIBLE_BIT_opt);
constant used_TRUNCATE_TO_BIT_opt : integer_exc := value_used(TRUNCATE_TO_BIT_opt);
/* signals */
/**************************************************************************************************/
constant P : positive := 4;
constant NORMALIZED_HIGH : integer := 1;
constant NORMALIZED_LOW : integer := 0;
constant IN_HIGH : natural := NORMALIZED_HIGH+SULV_NEW_ZERO;
constant IN_LOW : natural := NORMALIZED_LOW+SULV_NEW_ZERO;
constant OUT_HIGH : natural := SULV_NEW_ZERO+adder_OH(used_MAX_POSSIBLE_BIT_opt,
S,
P,
NORMALIZED_HIGH);
constant OUT_LOW : natural := SULV_NEW_ZERO+adder_OL(used_TRUNCATE_TO_BIT_opt,
NORMALIZED_LOW);
--IN--
signal input : sulv_v(1 to P)(IN_HIGH downto IN_LOW);
signal clk : std_ulogic := '1';
signal start : std_ulogic;
signal valid_input : std_ulogic;
--OUT--
signal output : std_ulogic_vector(OUT_HIGH downto OUT_LOW);
signal valid_output : std_ulogic;
----------------------------------------------------------------------------------------------------
signal aux_counter1 : unsigned(0 to 29) := to_unsigned(1, 30);
signal aux_counter2 : unsigned(0 to 29) := to_unsigned(2, 30);
/*================================================================================================*/
/*================================================================================================*/
begin
msg_debug("adder_tb_IN_HIGH: " & image(IN_HIGH));
msg_debug("adder_tb_IN_LOW: " & image(IN_LOW));
msg_debug("adder_tb_OUT_HIGH: " & image(OUT_HIGH));
msg_debug("adder_tb_OUT_LOW: " & image(OUT_LOW));
adder1:
entity work.adder
generic map(
UNSIGNED_2COMP_opt => used_UNSIGNED_2COMP_opt,
DATA_IMM_AFTER_START_opt => used_DATA_IMM_AFTER_START_opt,
SPEED_opt => used_SPEED_opt,
MAX_POSSIBLE_BIT_opt => used_MAX_POSSIBLE_BIT_opt,
TRUNCATE_TO_BIT_opt => used_TRUNCATE_TO_BIT_opt,
S => S
)
port map(
input => input,
clk => clk,
start => start,
valid_input => valid_input,
output => output,
valid_output => valid_output
);
--pragma translate off
process (clk)
begin
if rising_edge(clk) then
aux_counter1 <= aux_counter1 + to_unsigned(1, 30);
aux_counter2 <= aux_counter2 + to_unsigned(1, 30);
end if;
end process;
process (clk)
begin
clk <= not clk after 2 ps;
end process;
--generates pseudorandom values for the input
process (clk)
variable real_number : real;
variable seed1 : positive := to_integer(aux_counter1);
variable seed2 : positive := to_integer(aux_counter2);
begin
if rising_edge (clk) then
for i in 1 to P loop
uniform(seed1, seed2, real_number);
input(i) <= to_sulv(to_ufixed(real_number, -1, -1 -IN_HIGH + IN_LOW));
end loop;
end if;
end process;
--pragma translate on
end architecture; |
--!
--! @file: exercise9_3.vhd
--! @brief: function integer to slv
--! @author: Antonio Gutierrez
--! @date: 2013-11-27
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
--------------------------------------
entity entityname is
--generic declarations
port (
in: in std_logic;
out: out std_logic);
function integer_to_slv(s : integer) return std_logic_vector is
variable ss: integer := s;
variable result: std_logic_vector(s'length-1 downto 0);
begin
for1: for i in result'reverse_range loop
result(i) := ss mod 2;
ss := ss / 2;
end loop for1;
return result;
end function integer_to_slv;
end entity entityname;
--------------------------------------
architecture circuit of entityname is
--signals and declarations
begin
--architecture_statements_part
end architecture circuit;
--------------------------------------
|
library ieee ;
use ieee.std_logic_1164.all ;
use std.textio.all ;
entity cond_assign_proc is
end entity cond_assign_proc;
architecture doit of cond_assign_proc is
signal Clk : std_logic := '0' ;
signal Y : std_logic ;
begin
Clk <= not Clk after 10 ns ;
process (all)
begin
Y <= '1' when Clk = '1' else '0' ;
end process ;
process
begin
wait for 500 ns ;
std.env.stop ;
end process ;
end architecture doit ;
|
-- i2c_slave.vhd
--
-- Created on: 08 Jun 2017
-- Author: Fabian Meyer
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity i2c_slave is
generic(RSTDEF: std_logic := '0';
ADDRDEF: std_logic_vector(6 downto 0) := "0100000");
port(rst: in std_logic; -- reset, RSTDEF active
clk: in std_logic; -- clock, rising edge
tx_data: in std_logic_vector(7 downto 0); -- tx, data to send
tx_sent: out std_logic; -- tx was sent, high active
rx_data: out std_logic_vector(7 downto 0); -- rx, data received
rx_recv: out std_logic; -- rx received, high active
busy: out std_logic; -- busy, high active
sda: inout std_logic; -- serial data of I2C
scl: inout std_logic); -- serial clock of I2C
end entity;
architecture behavioral of i2c_slave is
component delay
generic(RSTDEF: std_logic := '0';
DELAYLEN: natural := 8);
port(rst: in std_logic; -- reset, RSTDEF active
clk: in std_logic; -- clock, rising edge
din: in std_logic; -- data in
dout: out std_logic); -- data out
end component;
-- states for FSM
type TState is (SIDLE, SADDR, SSEND_ACK1, SSEND_ACK2, SRECV_ACK, SREAD, SWRITE);
signal state: TState := SIDLE;
-- constant to define cycles per time unit
constant CLKPERMS: natural := 24000;
-- counter for measuring time to timeout after 1ms
constant TIMEOUTLEN: natural := 15;
signal cnt_timeout: unsigned(TIMEOUTLEN-1 downto 0) := (others => '0');
-- data vector for handling traffic internally
constant DATALEN: natural := 8;
signal data: std_logic_vector(DATALEN-1 downto 0) := (others => '0');
-- determines if master reqested read (high) or write (low)
signal rwbit: std_logic := '0';
-- sda signal delayed by 1us
signal sda_del: std_logic := '0';
-- i2c vectors to store previous and current signal
signal scl_vec: std_logic_vector(1 downto 0) := (others => '0');
signal sda_vec: std_logic_vector(1 downto 0) := (others => '0');
-- counter to count bits received / sent
signal cnt_bit: unsigned(2 downto 0) := (others => '0');
begin
-- always let master handle scl
scl <= 'Z';
-- lsb is current scl
scl_vec(0) <= scl;
-- lsb is delayed sda
sda_vec(0) <= sda_del;
-- always busy if not in idle mode
busy <= '0' when state = SIDLE else '1';
-- delay sda signal by 24 cylces (= 1us)
delay1: delay
generic map(RSTDEF => RSTDEF,
DELAYLEN => 24)
port map(rst => rst,
clk => clk,
din => sda,
dout => sda_del);
process(clk, rst)
begin
if rst = RSTDEF then
tx_sent <= '0';
rx_data <= (others => '0');
rx_recv <= '0';
sda <= 'Z';
state <= SIDLE;
cnt_timeout <= (others => '0');
data <= (others => '0');
rwbit <= '0';
scl_vec(1) <= '0';
sda_vec(1) <= '0';
cnt_bit <= (others => '0');
elsif rising_edge(clk) then
-- keep track of previous sda and scl (msb)
sda_vec(1) <= sda_vec(0);
scl_vec(1) <= scl_vec(0);
-- leave sent and recv signals high only one cylce
tx_sent <= '0';
rx_recv <= '0';
-- check for timeout
cnt_timeout <= cnt_timeout + 1;
if scl_vec = "01" then
-- reset timeout on rising scl
cnt_timeout <= (others => '0');
elsif to_integer(cnt_timeout) = CLKPERMS then
-- timeout is reached go into idle state
cnt_timeout <= (others => '0');
state <= SIDLE;
sda <= 'Z';
end if;
-- compute state machine for i2c slave
case state is
when SIDLE =>
-- do nothing
when SADDR =>
if scl_vec = "01" then
-- set data bit depending on cnt_bit
data(7-to_integer(cnt_bit)) <= sda_vec(0);
cnt_bit <= cnt_bit + 1;
-- if cnt_bit is full then we have just received last bit
if cnt_bit = "111" then
rwbit <= sda_vec(0);
if data(DATALEN-1 downto 1) = ADDRDEF then
-- address matches ours, acknowledge
state <= SSEND_ACK1;
else
-- address doesn't match ours, ignore
state <= SIDLE;
end if;
end if;
end if;
when SSEND_ACK1 =>
if scl_vec = "10" then
state <= SSEND_ACK2;
sda <= '0';
end if;
when SSEND_ACK2 =>
if scl_vec = "10" then
-- check if master requested read or write
if rwbit = '1' then
-- master wants to read
-- write first bit on bus
sda <= tx_data(7);
data <= tx_data;
-- start from one because we already wrote first bit
cnt_bit <= "001";
state <= SREAD;
else
-- master wants to write
-- release sda
sda <= 'Z';
cnt_bit <= (others => '0');
state <= SWRITE;
end if;
end if;
when SRECV_ACK =>
if scl_vec = "01" then
if sda_vec(0) /= '0' then
-- received nack: master will send stop cond, but we
-- can simply jump right to idle state
state <= SIDLE;
end if;
elsif scl_vec = "10" then
-- continue read
sda <= tx_data(7); -- write first bit on bus
data <= tx_data;
-- start from 1 because we alreay transmit first bit
cnt_bit <= "001";
state <= SREAD;
end if;
when SREAD =>
if scl_vec = "10" then
sda <= data(7-to_integer(cnt_bit));
cnt_bit <= cnt_bit + 1;
-- if cnt_bit overflowed we finished transmitting last bit
-- note: data is not allowed to contain any 1, only Z or 0
if cnt_bit = "000" then
-- release sda, because we need to listen for ack
-- from master
sda <= 'Z';
state <= SRECV_ACK;
-- notify that we have sent the byte
tx_sent <= '1';
end if;
end if;
when SWRITE =>
if scl_vec = "01" then
data(7-to_integer(cnt_bit)) <= sda_vec(0);
cnt_bit <= cnt_bit + 1;
-- if cnt_bit is full we have just revceived the last bit
if cnt_bit = "111" then
state <= SSEND_ACK1;
-- apply received byte to out port
rx_data <= data(DATALEN-1 downto 1) & sda_vec(0);
-- notify that we have received a new byte
rx_recv <= '1';
end if;
end if;
end case;
-- check for stop / start condition
if scl_vec = "11" and sda_vec = "01" then
-- i2c stop condition
state <= SIDLE;
sda <= 'Z';
elsif scl_vec = "11" and sda_vec = "10" then
-- i2c start condition / repeated start condition
state <= SADDR;
cnt_bit <= (others => '0');
end if;
end if;
end process;
end architecture;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
h2WWSrz+D0TWLPOzP7lOTCZDI/eqUIFnHrDzDQ9v+JR608NI69bpXqoV63l0SVjAuzmbclp7XJBs
ysWydDuWxA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
R869UJMYRO8mVLLNHGSzwGZDZ9qgRHUifful5lYkU1DWVD+AqZ+c2nQgt8NRrBHW9vApUzyq6bXw
8xEjzZBjVl/1uCB2FVTI+VzLDfg0omMmTaDQ05r4QRdwAuVyWz7h5qxKKrrlra0NUBKbbdUg3Ocj
BxU5IPAtaFgIm5dNSRI=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
gBsF+qw2d8x/ccbw2S3MiPmTal2ZtaOYaOwfh7xyo/wWmIHTdVMt+DcqXnwX+tgr/pmEJ66z2mFF
XjRqmRiXJGY3uEOrsF+ziw5Axczu8CBTne+JIIwvxDXzg48XEmU62CVY5sJCwzcSgB6q87k0+rY9
5jb3T3/imgA9kdtRjOI0HhFahNwH/FrgREwigRoChGJlAHUTaNdqIsfvKzKYuE2IzQQdemTirshC
Qf3IazP/ZXEGfCsCo3f39RFDvg0cX1/IOC2xIHvaWPmRvCoK3sAEHc24v7YDdpJpQPEVaW2Lx2PO
mAppT+eYpciY7zd9xnZk7gx856oKg0750LM4xQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
XIrODxiST7VMQRIE1s0vS9fYU3kHdTTPkI5KinLmaC+RZtKbtN/+X6QJsk+DWKFyprRZT1SffHCn
RsqFGUalBiZYEI1SFR/AedXEnT72I0+SsW+BpbA+Zsh77yE0mXZmlIXkj2GTAYf9ktImDkDrvIs4
RlFsG0H+sHxf0jopuDQ=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Kz86WAqS4KgiRahR7qZvs66gcWZfEtOyy6TUVz9LJGmATBQ6vebHZqpbxxobuKlU833xcYR6vyWf
fzSL/ef7LHlP+AOBGvZbiG/EA7Zsn5AVx9dz/l61cqp05v5jrs4rchlZXJckcMP4Yo0PjAcIIwRM
/rNFTABQ/U3LccqE8OV3+WyoT4nmGOm1+1KfKjiAcGoz8yqBPBjG6KfSOh5WOtX3l20nx10lkCnG
yx1IbFE8E899bTQ2DCjHQH4+WUemhZGLIH6BKvRF475e9jiHNXOuckc6B/bbrbsIPvrufGU7ZpY7
FCYjihIaE27Ik8VkNmXEXP00X/GjWwWA8XZ4Tg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7696)
`protect data_block
2D99qemIBj+gqo+uOTOFwm17OEq3H5EcRmGUcRQk+5BWmTL2MwgsMvASZ313Tj0FVh6X3rlZZGRf
DwF2OIh7qhGPd7rcpbyZKO5MJW+monGRtd/DRU/bTeZnlB2zIPdgL8gbviR9LSpGVXUtQalPUegP
5oRQqee3vgMVnc5ChaySFvsbwy12x6CcZ5dSPnXzK3PTD3GIj8umRa7I+U5Mw4NHEKzLTBjTT341
uxaIJjwIvel41/2t9tRjlNxhfmsKX6Qrfm6t7byqimeTAEUOJSZdyx9Or2kvBY9MSD7NSES9Iwcu
zlGxj3lX1BKav9jn2Xu8Y4Abz+vyq6i76KoQjGP4NUk5J7I025R6N4FOJLaZ0qMPRV3J4NgpL/MV
4C60RDVlQ39r0AugQKesg/JVI33hRrQMww29T2Sw7EXJlP4QLcz8l5Kz9F4pVdB3+FJDOvN6rpdE
rz3EhCPq0I3A4XGslR05JtofweVk5cEo4n00TGvlJwSl5EmfT17gaBDCB37q6/6Ns9iyYyAaspEH
StN117sT+9QoZetB2uHHc9BeU8zEK6J8lNtF9aRO89oQSdoSRr/htfJUWLUFwv/d6Fdt5hdta5Uv
jmY+I3z8yY14DbMdmNxWKGrJfspcbhVCSkRTpcEu1upyev4nGy/KgmjyFItZnnldoAmHWxjfYQw3
Tf4KcJz4/m1sNQ8bBaFVkEuIA1IBry0Y6MzrfuWpROFtbaLPXeRJdYMcMqhg72GRXalFXh4vFFcX
wFybV0lxRf7XjGuaF4MPCf95PEJwdwE7SCOKFot3MS8rkZ1r2w/ZhehlU8AnA95You1INuWGMcZn
5866fvZnN61RCjt4eV9EC+jDpZCAva1EIqvyiyfMXqXJ7D7qBI7TDbwTd74mB9F9a1Mo53oNmYMG
vq4n+YgZT+Xw2aQasHJzFNT0aMJ98p29RW8MjVlnQUe4p86a9Pmk3oTgIdulobekf+n46vKqY7/S
HmaTGzlJp1OPMrBQ6kESr90/vjJZQ/vqxBfEM2sV2OwWkFGjhwOku+H+J1QjRB7Ah7uMr0FmHmll
SGSNBDzwmSiL5Q/ETQmwXxEvKMpm7oCMOo6cAUDtHCZrVlGrGiKFT2lCbTGGLdEptQo0JMQU6eMd
BC5lvpxZIBo1tmXenRWFEMgOGJKz0zT+gtrRYOYYTwuhy8kllVBtKYNW5nmHzt3aqc5uMtlMlXeq
1gkTn0+GPXlZBLUhOSPWW5iebbkGfvzaajMGKFEWCUnVScXYzCaKjVFXpnJyQTcgouwxs+4wpLWB
Kexxd1Ml51D6bE1rQn3Cx/BkJTqv+O78G+44+dOGPBFPgfPbolHEzE7CdseSuEOs/Ndmnp4pWTCG
EhX/rVauRzzr7ip0YGyXEAnmsWYyIzD4vtXRjVUkT9pUp3+U8oGXpAkLeV4uCt74XpuFbAWm6McI
+YxLeKlZ2Fg9qN4VrAoet1Dcpx0kndsd7D7OgFKEBAipXcGtT0PdjVF5V9PKyEjkoEBCKampQ9v3
Lg6iFtXGaYuNIxtbPQMs9IeMeT23PkBxGPLVbNxNTDmjTbcrEPCtbo2mL0U6iSzpiPW2g2/g40vG
bIb1YrPKHmXzithrC6dw2DqUwDzbbycQ8TmS/j6ur4Po1NnOkXfG8zz8XIyO3vmwjU6UfzSb1yCo
S9J6/MSpNfFBc0QOCWMyylTzLcOXBo3smgrXYbMGRNT0jrB+aCE0ViXQz/xFOanL8mP4dWAjSYuI
IYWkOM/4vpp4ebF9dse0dkIVAByDG/kUAWz2by4crPCZClO30DknR0VTWOsgQkH8pWR1muNY9vnk
LxXw2vvepbQpSmilKJDDJhYq8N8391YdfYiI94n1fgxFRXqcuVnekOQMdlG2hE55B/1AUD26ZRZI
jfLNm3tdR2Ko2zsGeZbv/833VWiniaIz97gxHdniJEIAr2+BNpEXPsGnQO75B4a31xmhZnCNSP5b
HA8ge0Z3ruVmVFpwdgKyhAp3n9XWpWWBs+UAsDNGjN7rM7XBZKkeeFTyzPYy19482u+v1DNiMabB
7fVPPLPoZp5yzax5dr3AKVuM1SjFHmG1XzQipuklaB1BbiY5X3zwN4MOYP2BYOXEAihVEYvdZjSg
4gWgFk4GxG7szP1ciymzN35thZAB8vn7dL7l1TES4fP4PG0FKTTmGrGFZHaDZHLTvg1QafhHrd3j
ETZ/XxUSMj3lBQRK17bCvkqcz+5hi8WmtwW1gGi031PVYO7qCL9ms9WJvIULaDzxc2hjQgm+2DnX
5QwpyjgrKyqFC3k0RwSFBYJnVPBqeFdnXni8uMhhb9o+tWUEnIm+QRBd3Sv1Fmv2qsAvgWjOCBGe
ZCBNDUzf8LEuvvc6Wqh0ZY/+ZXnz3HYniD3W6C8aIWSP36pp6zCKqIWruV//V/sUd7EZHnvcq88F
dZmnhsRaNyMFDgRgA1CvVeOH2d6o36fdmytFK3llnPusDNUZRGjgQmH67Fz2e3FDvzSom79Qw4Kr
Akq+tjFNLjFqFKIA5vvSZPq5fr5GffSJYIMctcfwpv5oJ3hDSN7U5lFvT9vtBrPScVp1B++Gy2AV
RdiqXN/EcrFyS1O+qw8yQdcG2mUeZz2UUSirFfzZRfJ99FnH4t32uw7upesXDCj0fyWCsADPC8FE
/u1NNhcexzPSekN2OrBmOwdNNnh2zw921zLAvLelMtJ2HvaDmrTJKgaWU2BnNjbsUqVZldgl4LDu
aB1ROAWEmLlLqk5RurJp8vE1r6M73SXHOERZnrbQD+ZYFhUNpL0bkCZNA3KegK8H848hYynlH/Cs
e3cXyxo4V9+kON3RiPz/ZjaV6NYo13Z/fgDsektSSFam7S84R/s6RXnjE6i7matMYvNEAN7XLW7h
CX6aSsaMucOn8m/cI108FUGDmFrPfqvu5NDYWHdEN454bfIGGi2lNILdYOM3Dn4FO3PRpkYpcA1n
0yRwirD7yVMRxCjzsxsmKP3+NnJnzGFS+LOnfZdC22R0FImZWKW8APdS6hYi3EuxKnwgzXy6MwGr
btnzyOQ3ur/vQCroVD7HL/H8qQx7h2m6ajyV6OU0w2rky5hqFam0MiU2/GCAm1n8gG2iI9AW1CGS
Zdjq7DPudsGc96gEXcyf4YaLbh+zCzG6dhl78AedeLxFDkNqlzmLRhfPt4/LzXVPfgizV9fiE7UG
mXRmPGp1AHCaY6MLNB/kXWwKMxXr9U+qMounlUTyd67cAnS090NPxeWnZZn+hZJxx8WD8mSU3FNH
EMRUruPxg/h988TtBRlLCqmj/90KH4i4tcfD5JgkvzWdrzJFHCFx3gFb7RXtLEZJXZxTkJAoAAEP
GNKyvMGkr+rgChpf0fBlKcedf9rb0Fn2bppakcAJYFtXDuWQbbuFuIzpctbnCG5nknE28Xb3rdZl
VYAjx8Gc6+icbL5aK22y1OsKBQof69vbyXrbv7MA0xmw/5GdL2PxSY8WqKXHue9jrVVxm+xVtF3v
II5eG27MjO7d6vG27Djs8k2CnTY4EU9flxnFn/mP14rHSArvkPZ7X/ul9vv3q/7BGROGOpc0S6rW
8yKz4yYTCMsDMADG+E5h048ix+fsfrfWNKgQvSxgnUyfZXobbwRH+yIPBX2Sgwg4g1R6WIXDQai3
47YPVqdsBMZ94bA6bK6ReoD2bNOz9ajLX7z7E/EVDxs55Wx/KzHjciVGrKYFUYDnq9R6QB29MJ6V
8M846yiEtedTSfqXZteZl0XVhMfPys3DfbCM2Tu4gzlNlqRBLGUabJsAPLx1r4FYCbznYhunacMF
YDWsyAFMKgnMSGTS2S+ekUleXW4uMsDXRnH7BC/Y3Fmi2jCSd4DAOQtahwchcBTxJwbuWRVSlVnX
uV9ZK4SOqNXbgRYmeyUuld6sxdU7sqBdI2HtEHKgiUFc7f7VMVbZijsLPEwGGWRb8dgn+dKcPAqE
UegAmHu/Wdq/sdw8PxWQooyYD3yy97eA4QtcbCAiccIXqTUlbYcGrNLke8tDEEXPP5yhnTx++1gK
C3rOzVg/pzr5lZe03CdXT4GmL7Mlp/jjf3K6lhb3NwD7HgGOOBRJBrHNZlGcByfB39pihWN7ZQjF
EQh+I0+u4nnPozCxVHNhfE1wel+O6G47pMLJ7+oTcjU5GDxYvWLp9Ql5sfnrsVFbxxQfSOybRfhW
NSgn6TXgCzIb4RnB5TyXM+29YKh3fb60j6VQkfBuQ1aZrBXfSoSSc5lERndAo7AvbX3Cszd3wP9M
lX2VEcFEQAWHaj8o/3DomMkOx5qSNXSbVn6xWZqeUFWFMOVIh/DNYD4QvPUqicUxM8fHnof7f83y
6VfCwmd848vr9kbX2BqhOxDagD7VxlwaB96Z8dS8ayQdIvNtZhm6Lkd7C3BYCu7sG49lvubtPOou
HWdYhdw7l743ppki6YpNaV/ttTLx2dwkgnolHYipH+tozyfZhK8Tog6J3qka0/M6huMkSPqGHN9F
tZpgrYTbYTpwlKpZEbfkrMwiFdMq02tHo/1/PdVVlpM0FF+Jd42r9UCfo3KLY4YRRhUSherYTUL8
G7Bak8xT61t0a8u2m5vypRZoxEQkqMXhUM+ecJ6MZPVBQnKEBm5YJhH7nw5gbKtqt/1ZN/IT3m/a
dGeUm4e4KuYVg5INsNGJEPruqSkEGpjsJJPjiyGokdiTAh0VTLsAJRE6FjRwYrrp9J6oXycNbhp4
3CLc0+CA9fkErkmSQw/esEgl4iXUYLG2iPFot6rUW0IznRjy2elDHgEJAIKui6CepEbZrzOQp0W+
FNciC9Uz+6HXAXvmg0gVH9IBFFfRz9cyIxpk8rjiQuj2xxyRYtfFUroDeuZhiBOjklonIgO33Hfa
uIb+uYX8cSgVq/Mal13fNMJQV2DfIGgdeYUZRmzzrPYtG+RiPYVgTL1bDf9wSXm6aYIO0Lxrw8IW
Kncimzk5OfctVXz4OtynLfmDeU41yP36fFshJhyh8iNxrPcVYLiZ2wBiZ06rL29iThb8Sapuno3d
VBxR6ndLnqI7KVzeo9M7+u/asFdeXiz2FRnkU8105bF9VFPQCxV11PlVv/vr/emMoRFLbUOBKH3s
pIJvK5AVI7r8Gfscm+onTz9YGgzRZPCeKVg6Gb3Obsk1K++Hikqj0IWoyPVxDY3CenIRlwag/GNQ
oQEyb+IaTzfsHC/uBGuSWgd6JOBI4xHZJ2cLfFowvqy65FQ8B4ju5ZTM7tkZYROB8DZSwyyvYUG6
uHHZh/uIMBTrLUhOCx8CfqQ+g8Fo6j8M1+/1OynJnmG7FDSxjqtwCgQamShIxJV6tAAOcu4NRJGk
3SZWLJXWO82ySYkrYRBth6CNPYmyOFw97PuLPzJhtvJUWjD3dQR1KGSlYONNpDHn4McYyclSPGQ2
IM29+XcKXJFnutZQ7qLlngiqA6jVDACwyvihICc4o6f4YNTD5ktGB7iorcZ/IJtKb7C7HKsH4kVI
0N0rzRrWCa60CQcNNMN1rS/8Qansqgh04HGN0pEfE+kTdGBOhv4R/mR880PyPEVK5h+dGrQQZNV6
YkZyI4lqqksSzNSZBCmdYf1Z1giinFV+S5+uXqDhd2l9uYUxBPbXuipUtK7LJytu5L2xlhM0UfSW
0mQWOv34WSQRGKV+r9XDUGuEtATY5YOZIea63yZ6UyqAFxDEIvdVBQs1gzczlTbhtMNFI6kSQ4ZL
GlwyiC9o+BEiqeDFWo0ozww5KNEg4sYxZi3+i28Kkp36V/GMWKDogcLTXdk9qr3Vj/mcCIcAAaYf
MwIsUU6XiBUGYx0fqZecaJqYfR+dtgfjSDVDETpmPMYVNNxpcWmi1zZKTX4lCZOXLQ/wci5OE5HQ
3psl6wMQar5x0d002ooMTa8MCMNADENUW955tpZp6jtzsxWYvzcAq3a5F1iWnBArjytYZdxK8Wyu
1yJXJeUxB3FOgozTKuD1gfSNU34sGyyZKL1i09R4yDjI8tC36yWJnTKG9TjzwqSGIoJQFefarPjA
dJtVTjsyDnZXaaR/Quyu3AUHX4rRmt7jLYOrm7dusI5dO6VBFzMGHyEH6lZRnKlaeXv16bynajfp
XES/LcEhOiL33thKKmvTx5FIiD61kkaq+xYc7gAgE8bAjVzJ8LmG/uCxXzv2pFfcNsU9bwJoNerS
pnj3DMt/X1dNfdSz0LWfSYIIj9nlNjTtPbPAEpD9tZ+bRbg6x80X5d+PdC4eW1R+4GE1UYMEJOmV
+Kig3fPclWFEbd9LsYVFtLKATVcmoeQUVpzOYtPU6YGK7nQ41gTvnwbHyw7OB2lTaGadZ7UYZS6n
wbi8XXsjJuMuFE7SVQmzXY102+RudV03kROrY3fMwevJbADKYOKdJBGSo/RLlUvXXGVYF+dTkepi
ukp4xkx0yq4nii0AkSGZ3kWejvY9L+Ir9pUdLJ09zOy4K3y6j/v9GjMSFgxRQnFyOcO2vLPgWnoI
TX3Qe5FtENTpGAdPlfy7mLksGEL53+xSLUXU8VxnLL3+oF0zYGI5wQzITxM1x+EZmgfpuAayXym4
EwI01hY4kHOMQSG4eyQv6THVOV2jCPACW7OQitilOBX67OUh2frcYs7w9FBuL9z/TKDVlgIpESk3
NxREQh4SfXzGQA/gqObg93s1fpgQV6Si7XDPXmqZeCGg8H+FjSCyZ3aOIauX+YLTT3nONyHRX90e
V6pT7P418bXf+6uB6Tja9xWuXBkKgW4aM0dhNRMGIqemuGgmQN2qbplS0DSMc87zDloEW41W6vo/
FPRdH7ylTZnPUNRb19HrF93ASDwZ3JR/huKKkBrc49Zw/PfWqcSg7WL5Byvu3uyywjf0210ct2Gd
DCHiQM5LOS6epe5ATOpXyuHu+VhWXxudbokiVIU4XEIZlqk2Icy1vQLmF144H3E+QuphJbKaDJhk
39aNz+eMmeSJNiVW90hexzVyVi04AUYU/rx4aI8IqwAqNWXjekgPpByg71+1uXS1lASUV/BMEJNn
BRaKMEybCpseiC7Iz9kFEDWqQeDSDdfzl6CcNlD1Z98HT9gPogFVz4TXT+1UY/znc6F+K/KXovzY
d4dW4xkUxE4fxN8Fyf0IRO6kFfSUwjWO/NOaHJpsL/y5BtioRgK3SiJ7Z9W7nHQQnB55SdeOutyS
kp6c7CifHKDuY8n7wa49LZYVhFSuAOVVEkH803NgazbXQibQ5pix3EOOHOd+2GyRIutmEQSkdOAc
bdpoUBDPEcG7nO3rWpaEWy+OLPcmpljVDAsKbQ9JJmToLV7+3isEMpSDeME0pNxhIQj2o8WtsECh
35z2/gaPypensjGikajBrdC9kadXaihdmgAzTgvTCnrA8M+0LoI356acTR4+uX15ucN/3qZ+9zu+
6+exrFyTxhfitELDtkEMSSXUg8SeimXbNYK4tXtleiknLmxXjlzKD8GJ8TKrVQLNlfgjWkcEzH+y
Z0PSHS+hl1WJlexVigmu8KDhbur2NkTQN/YUfiVPfvnFSef1LvTAiuqCDyMTF9SHs+/bQvDr83YP
IDAZFAOtD+fi8bFEfOyjehMEJbBszXrSwhcgy8Xx6e01I67NzViMis65T1DAfKxZUxkKSGaA4TfA
F7PmyoX59vjRv6bRlqVKdNKeEttm7b6Y1J/jRQwbSZNquN0JZ49TCYd9XzqHvhjJ+V/Mt5EQmwbX
nbGjfq4qvgtw6HYPEZq7mzsmpXXaeD5n2hgvV/xmXMVUswbWdhJIajbI8qBNbuJq0m21OcsjEnTx
5TwVOzIbEk/NymaatCzPjcXOYwGZyR3q2b0u6qmTrRrXBxg9nQ4zh+ZtEUesuwU6ujWytRgGYVDN
Ba9d1MSft73+b69l9bIRy8jjaU/4O86fR6UdZ5kkikfaV/jGkxU5LUuupracMTHYQOmEddeVrGhd
BbFEJz2BMp8MRlFrUEQGtON428urL497A2CnvKSZ1TqO21DyCk4GTqKoeLr37zz04fXJoDuNqU5T
8ahslid0WXUbc3tEcpFoyn0ta18kYyEsDZJJtEwuW6+P8aMP4Vka/X14+BOaln0rASZuSTGgt4Dm
LvPR6ZL5EeCDYy/JSSsIOB6fk4VFLhRoTeKmJE1Lek7iTUCXM5AzYO4nlOQmQsonIDsDdvctBAql
J6fCBSc1xKxHuz+xhAhF54WUYbCxh2BPY2YVEyyWAFzQWq3IeoaPu/q3Cowp8Jygd3PgIPQq61dg
lNv87j7jOd5wGjr/rSmI4xMNXRSG/I7VuLxdyOpHZVOtGXVF4VlAoFchOce9HxWp7BC619vKVwOI
2jkwsO2RZ6JVE2vDEHMLVLRZyeLWh775bA+km+sDhjZJauAWagRFXo2tJTSfsDUAk2bDk79yhKlC
UIH6ax7PhO1AMszlxOy0BDgywOVjTJZt2DvtTeHjXnO0aBgYz7ihPA+PoYWFQl9ZW+AArsu6m1EA
2cTp6ZIXHJYhRhqH2zF57O3DFjlnAQ5DWuVh4j0A2tD/kMXWnecVoyeltE3RxkyPRbU4tnyTsCGD
Qmrj/85JGpRnjXsMsIe/wpgjZzPWW3Jxvvr9As9IOvgOTB975JOoMHgltlzKkfI07WlHGeju0PLk
AVT1lWGqZSNmgmCuTIFnrdopPuWviuFDzApHE82gIEQ1Nw3b/6Tl9aDvibC3RVjwKgq6iv4O1/Hd
EQ0071CPPzID15M14ULT+PqHmZr3rBFIZnIqKaorHhvXWjMmxgTJHRQ90D4cqSsP02zhfJPJ4veR
QczEeY61RBK320puudhxeJmB7d8OvSgtsJsxQXiH/yyH03C5SWd/RhXyy9TjenzvTyp4Hti1XvXZ
brvea1X7wH0Q3uDXTM1cFT1EpuTxsUv1fscyQwFWRHhbQZv/VMwf5RE7UNja95LmChWd/d8XTlpA
3yUwR+fesAsVRiFkH0h68sjn/qqnP/DWF+qGtcA67+fvg87/raR2gDdIs0qCk5h8HNAlsc3bD/Nj
Tg+JRmqSk7grAlgaQI7mTujaaU9711Jii3LC7EaZmfTsSaG310RWtFkBlSsX6llftWJwwLzB1s+a
d/ykfQbERYp6cFCajlM41tEqJtV22XDpLwtr1I5CMYsh/f/tQVsYzTOi7Hye092v7DVBGbxUROYr
jx3vks3y1CpTy2d7EfGF71s/4re/FsOGK7hCMUdUfWuLAIGp3LlsD+Paw4hYj+baeTmSrQaSe8zF
6RDxQ9f262IpJKYQxm8JZD2dkrBW/WqtERSh5uUjXmK44JMEPbmZpL2L9fNN1CLUJPf+ktFw/Ou0
uddOCNuMuSupg6f1ivFJuOY8e58Z3ACLpQ+ilgDYpXB2+ZORVu4rIdqUb6A4s76HYXfMhqnh0uji
GUrCjQ5HzhWCxj5iyfKWjqCNZTNKZANIa9KAbMzGiB/OFZIDEjOtcxJXwNVfBSffWN8O/qs7gfwS
gREauqgmhj4KubhZz+/jsEgSQU39A3dnSm7dj9v2+DeThQBLb8glSLMSyZ2+p7t4TtTAXxKmV2VK
rAVuSjrcccVeLyXPRsTAvz37BokuXnFzQEp6+s44wHQTjg4vb8jUkeuXPfpeLw8MovAQbcsKjIDl
I8A+2XSyyR7IPf5YjQQQV5gylQjEPHDZWDh/tNBtoLMIWJu9puyJNpE/NlWck3Ut6Xriv8NJGlDe
aRFEHF+Ccu0ImwpVlWGuZvoSHOVxfj3s3D5GGEJdCSwnBu8kBJThtsPl5iSDX7ktRAw5JxmP7dYk
yYc2fZAFt3l7Hhflw6zcko51T64FJSOIWrDpOmT2t23LH4aG9/hlpznA0TjOKdnrLmXsaGETk8jG
2I2I0XBcS8xnbv7nFo0ZK6XZhs0OdCGLycTMJMoBtDddIAiAC2GRWuWwweyluZd4nh0gZYVS8/3H
WQEWVS7dGL3RLcFUOtPl+5zUI/S5KgoRXcU0o69OngxlYLE+4mq1m7MWDb95iIH/vCw1Y6xBs1TW
Pyc/587tngNSkmnRgA2/xMSCFbxQOxUCZM95PWjhSXJZHVFmQLWxO5RMSaZUeWEQyaR/MVDTjYfE
LZ3jBiKzAL92xZ93yA339O2bXutQ6RT4PRky6DeDpJY3hObvWcmJSNcDsNdqpdZyzscFGmaB/7tq
+TsEMdE9i8djkS0529E1eLA6tBJHGbMQskdbV+Tx6SP/7cgTte54DLz8P0DU00PU2wq/mc2D3gFT
bYhnNbYPHlBabum5rFFqwNcv1UJN0NhL5QeeNcWY4CPa+XzSyd7G0OHYDu3YzP2mNGKey9XV56gJ
xQ==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
h2WWSrz+D0TWLPOzP7lOTCZDI/eqUIFnHrDzDQ9v+JR608NI69bpXqoV63l0SVjAuzmbclp7XJBs
ysWydDuWxA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
R869UJMYRO8mVLLNHGSzwGZDZ9qgRHUifful5lYkU1DWVD+AqZ+c2nQgt8NRrBHW9vApUzyq6bXw
8xEjzZBjVl/1uCB2FVTI+VzLDfg0omMmTaDQ05r4QRdwAuVyWz7h5qxKKrrlra0NUBKbbdUg3Ocj
BxU5IPAtaFgIm5dNSRI=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
gBsF+qw2d8x/ccbw2S3MiPmTal2ZtaOYaOwfh7xyo/wWmIHTdVMt+DcqXnwX+tgr/pmEJ66z2mFF
XjRqmRiXJGY3uEOrsF+ziw5Axczu8CBTne+JIIwvxDXzg48XEmU62CVY5sJCwzcSgB6q87k0+rY9
5jb3T3/imgA9kdtRjOI0HhFahNwH/FrgREwigRoChGJlAHUTaNdqIsfvKzKYuE2IzQQdemTirshC
Qf3IazP/ZXEGfCsCo3f39RFDvg0cX1/IOC2xIHvaWPmRvCoK3sAEHc24v7YDdpJpQPEVaW2Lx2PO
mAppT+eYpciY7zd9xnZk7gx856oKg0750LM4xQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
XIrODxiST7VMQRIE1s0vS9fYU3kHdTTPkI5KinLmaC+RZtKbtN/+X6QJsk+DWKFyprRZT1SffHCn
RsqFGUalBiZYEI1SFR/AedXEnT72I0+SsW+BpbA+Zsh77yE0mXZmlIXkj2GTAYf9ktImDkDrvIs4
RlFsG0H+sHxf0jopuDQ=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Kz86WAqS4KgiRahR7qZvs66gcWZfEtOyy6TUVz9LJGmATBQ6vebHZqpbxxobuKlU833xcYR6vyWf
fzSL/ef7LHlP+AOBGvZbiG/EA7Zsn5AVx9dz/l61cqp05v5jrs4rchlZXJckcMP4Yo0PjAcIIwRM
/rNFTABQ/U3LccqE8OV3+WyoT4nmGOm1+1KfKjiAcGoz8yqBPBjG6KfSOh5WOtX3l20nx10lkCnG
yx1IbFE8E899bTQ2DCjHQH4+WUemhZGLIH6BKvRF475e9jiHNXOuckc6B/bbrbsIPvrufGU7ZpY7
FCYjihIaE27Ik8VkNmXEXP00X/GjWwWA8XZ4Tg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7696)
`protect data_block
2D99qemIBj+gqo+uOTOFwm17OEq3H5EcRmGUcRQk+5BWmTL2MwgsMvASZ313Tj0FVh6X3rlZZGRf
DwF2OIh7qhGPd7rcpbyZKO5MJW+monGRtd/DRU/bTeZnlB2zIPdgL8gbviR9LSpGVXUtQalPUegP
5oRQqee3vgMVnc5ChaySFvsbwy12x6CcZ5dSPnXzK3PTD3GIj8umRa7I+U5Mw4NHEKzLTBjTT341
uxaIJjwIvel41/2t9tRjlNxhfmsKX6Qrfm6t7byqimeTAEUOJSZdyx9Or2kvBY9MSD7NSES9Iwcu
zlGxj3lX1BKav9jn2Xu8Y4Abz+vyq6i76KoQjGP4NUk5J7I025R6N4FOJLaZ0qMPRV3J4NgpL/MV
4C60RDVlQ39r0AugQKesg/JVI33hRrQMww29T2Sw7EXJlP4QLcz8l5Kz9F4pVdB3+FJDOvN6rpdE
rz3EhCPq0I3A4XGslR05JtofweVk5cEo4n00TGvlJwSl5EmfT17gaBDCB37q6/6Ns9iyYyAaspEH
StN117sT+9QoZetB2uHHc9BeU8zEK6J8lNtF9aRO89oQSdoSRr/htfJUWLUFwv/d6Fdt5hdta5Uv
jmY+I3z8yY14DbMdmNxWKGrJfspcbhVCSkRTpcEu1upyev4nGy/KgmjyFItZnnldoAmHWxjfYQw3
Tf4KcJz4/m1sNQ8bBaFVkEuIA1IBry0Y6MzrfuWpROFtbaLPXeRJdYMcMqhg72GRXalFXh4vFFcX
wFybV0lxRf7XjGuaF4MPCf95PEJwdwE7SCOKFot3MS8rkZ1r2w/ZhehlU8AnA95You1INuWGMcZn
5866fvZnN61RCjt4eV9EC+jDpZCAva1EIqvyiyfMXqXJ7D7qBI7TDbwTd74mB9F9a1Mo53oNmYMG
vq4n+YgZT+Xw2aQasHJzFNT0aMJ98p29RW8MjVlnQUe4p86a9Pmk3oTgIdulobekf+n46vKqY7/S
HmaTGzlJp1OPMrBQ6kESr90/vjJZQ/vqxBfEM2sV2OwWkFGjhwOku+H+J1QjRB7Ah7uMr0FmHmll
SGSNBDzwmSiL5Q/ETQmwXxEvKMpm7oCMOo6cAUDtHCZrVlGrGiKFT2lCbTGGLdEptQo0JMQU6eMd
BC5lvpxZIBo1tmXenRWFEMgOGJKz0zT+gtrRYOYYTwuhy8kllVBtKYNW5nmHzt3aqc5uMtlMlXeq
1gkTn0+GPXlZBLUhOSPWW5iebbkGfvzaajMGKFEWCUnVScXYzCaKjVFXpnJyQTcgouwxs+4wpLWB
Kexxd1Ml51D6bE1rQn3Cx/BkJTqv+O78G+44+dOGPBFPgfPbolHEzE7CdseSuEOs/Ndmnp4pWTCG
EhX/rVauRzzr7ip0YGyXEAnmsWYyIzD4vtXRjVUkT9pUp3+U8oGXpAkLeV4uCt74XpuFbAWm6McI
+YxLeKlZ2Fg9qN4VrAoet1Dcpx0kndsd7D7OgFKEBAipXcGtT0PdjVF5V9PKyEjkoEBCKampQ9v3
Lg6iFtXGaYuNIxtbPQMs9IeMeT23PkBxGPLVbNxNTDmjTbcrEPCtbo2mL0U6iSzpiPW2g2/g40vG
bIb1YrPKHmXzithrC6dw2DqUwDzbbycQ8TmS/j6ur4Po1NnOkXfG8zz8XIyO3vmwjU6UfzSb1yCo
S9J6/MSpNfFBc0QOCWMyylTzLcOXBo3smgrXYbMGRNT0jrB+aCE0ViXQz/xFOanL8mP4dWAjSYuI
IYWkOM/4vpp4ebF9dse0dkIVAByDG/kUAWz2by4crPCZClO30DknR0VTWOsgQkH8pWR1muNY9vnk
LxXw2vvepbQpSmilKJDDJhYq8N8391YdfYiI94n1fgxFRXqcuVnekOQMdlG2hE55B/1AUD26ZRZI
jfLNm3tdR2Ko2zsGeZbv/833VWiniaIz97gxHdniJEIAr2+BNpEXPsGnQO75B4a31xmhZnCNSP5b
HA8ge0Z3ruVmVFpwdgKyhAp3n9XWpWWBs+UAsDNGjN7rM7XBZKkeeFTyzPYy19482u+v1DNiMabB
7fVPPLPoZp5yzax5dr3AKVuM1SjFHmG1XzQipuklaB1BbiY5X3zwN4MOYP2BYOXEAihVEYvdZjSg
4gWgFk4GxG7szP1ciymzN35thZAB8vn7dL7l1TES4fP4PG0FKTTmGrGFZHaDZHLTvg1QafhHrd3j
ETZ/XxUSMj3lBQRK17bCvkqcz+5hi8WmtwW1gGi031PVYO7qCL9ms9WJvIULaDzxc2hjQgm+2DnX
5QwpyjgrKyqFC3k0RwSFBYJnVPBqeFdnXni8uMhhb9o+tWUEnIm+QRBd3Sv1Fmv2qsAvgWjOCBGe
ZCBNDUzf8LEuvvc6Wqh0ZY/+ZXnz3HYniD3W6C8aIWSP36pp6zCKqIWruV//V/sUd7EZHnvcq88F
dZmnhsRaNyMFDgRgA1CvVeOH2d6o36fdmytFK3llnPusDNUZRGjgQmH67Fz2e3FDvzSom79Qw4Kr
Akq+tjFNLjFqFKIA5vvSZPq5fr5GffSJYIMctcfwpv5oJ3hDSN7U5lFvT9vtBrPScVp1B++Gy2AV
RdiqXN/EcrFyS1O+qw8yQdcG2mUeZz2UUSirFfzZRfJ99FnH4t32uw7upesXDCj0fyWCsADPC8FE
/u1NNhcexzPSekN2OrBmOwdNNnh2zw921zLAvLelMtJ2HvaDmrTJKgaWU2BnNjbsUqVZldgl4LDu
aB1ROAWEmLlLqk5RurJp8vE1r6M73SXHOERZnrbQD+ZYFhUNpL0bkCZNA3KegK8H848hYynlH/Cs
e3cXyxo4V9+kON3RiPz/ZjaV6NYo13Z/fgDsektSSFam7S84R/s6RXnjE6i7matMYvNEAN7XLW7h
CX6aSsaMucOn8m/cI108FUGDmFrPfqvu5NDYWHdEN454bfIGGi2lNILdYOM3Dn4FO3PRpkYpcA1n
0yRwirD7yVMRxCjzsxsmKP3+NnJnzGFS+LOnfZdC22R0FImZWKW8APdS6hYi3EuxKnwgzXy6MwGr
btnzyOQ3ur/vQCroVD7HL/H8qQx7h2m6ajyV6OU0w2rky5hqFam0MiU2/GCAm1n8gG2iI9AW1CGS
Zdjq7DPudsGc96gEXcyf4YaLbh+zCzG6dhl78AedeLxFDkNqlzmLRhfPt4/LzXVPfgizV9fiE7UG
mXRmPGp1AHCaY6MLNB/kXWwKMxXr9U+qMounlUTyd67cAnS090NPxeWnZZn+hZJxx8WD8mSU3FNH
EMRUruPxg/h988TtBRlLCqmj/90KH4i4tcfD5JgkvzWdrzJFHCFx3gFb7RXtLEZJXZxTkJAoAAEP
GNKyvMGkr+rgChpf0fBlKcedf9rb0Fn2bppakcAJYFtXDuWQbbuFuIzpctbnCG5nknE28Xb3rdZl
VYAjx8Gc6+icbL5aK22y1OsKBQof69vbyXrbv7MA0xmw/5GdL2PxSY8WqKXHue9jrVVxm+xVtF3v
II5eG27MjO7d6vG27Djs8k2CnTY4EU9flxnFn/mP14rHSArvkPZ7X/ul9vv3q/7BGROGOpc0S6rW
8yKz4yYTCMsDMADG+E5h048ix+fsfrfWNKgQvSxgnUyfZXobbwRH+yIPBX2Sgwg4g1R6WIXDQai3
47YPVqdsBMZ94bA6bK6ReoD2bNOz9ajLX7z7E/EVDxs55Wx/KzHjciVGrKYFUYDnq9R6QB29MJ6V
8M846yiEtedTSfqXZteZl0XVhMfPys3DfbCM2Tu4gzlNlqRBLGUabJsAPLx1r4FYCbznYhunacMF
YDWsyAFMKgnMSGTS2S+ekUleXW4uMsDXRnH7BC/Y3Fmi2jCSd4DAOQtahwchcBTxJwbuWRVSlVnX
uV9ZK4SOqNXbgRYmeyUuld6sxdU7sqBdI2HtEHKgiUFc7f7VMVbZijsLPEwGGWRb8dgn+dKcPAqE
UegAmHu/Wdq/sdw8PxWQooyYD3yy97eA4QtcbCAiccIXqTUlbYcGrNLke8tDEEXPP5yhnTx++1gK
C3rOzVg/pzr5lZe03CdXT4GmL7Mlp/jjf3K6lhb3NwD7HgGOOBRJBrHNZlGcByfB39pihWN7ZQjF
EQh+I0+u4nnPozCxVHNhfE1wel+O6G47pMLJ7+oTcjU5GDxYvWLp9Ql5sfnrsVFbxxQfSOybRfhW
NSgn6TXgCzIb4RnB5TyXM+29YKh3fb60j6VQkfBuQ1aZrBXfSoSSc5lERndAo7AvbX3Cszd3wP9M
lX2VEcFEQAWHaj8o/3DomMkOx5qSNXSbVn6xWZqeUFWFMOVIh/DNYD4QvPUqicUxM8fHnof7f83y
6VfCwmd848vr9kbX2BqhOxDagD7VxlwaB96Z8dS8ayQdIvNtZhm6Lkd7C3BYCu7sG49lvubtPOou
HWdYhdw7l743ppki6YpNaV/ttTLx2dwkgnolHYipH+tozyfZhK8Tog6J3qka0/M6huMkSPqGHN9F
tZpgrYTbYTpwlKpZEbfkrMwiFdMq02tHo/1/PdVVlpM0FF+Jd42r9UCfo3KLY4YRRhUSherYTUL8
G7Bak8xT61t0a8u2m5vypRZoxEQkqMXhUM+ecJ6MZPVBQnKEBm5YJhH7nw5gbKtqt/1ZN/IT3m/a
dGeUm4e4KuYVg5INsNGJEPruqSkEGpjsJJPjiyGokdiTAh0VTLsAJRE6FjRwYrrp9J6oXycNbhp4
3CLc0+CA9fkErkmSQw/esEgl4iXUYLG2iPFot6rUW0IznRjy2elDHgEJAIKui6CepEbZrzOQp0W+
FNciC9Uz+6HXAXvmg0gVH9IBFFfRz9cyIxpk8rjiQuj2xxyRYtfFUroDeuZhiBOjklonIgO33Hfa
uIb+uYX8cSgVq/Mal13fNMJQV2DfIGgdeYUZRmzzrPYtG+RiPYVgTL1bDf9wSXm6aYIO0Lxrw8IW
Kncimzk5OfctVXz4OtynLfmDeU41yP36fFshJhyh8iNxrPcVYLiZ2wBiZ06rL29iThb8Sapuno3d
VBxR6ndLnqI7KVzeo9M7+u/asFdeXiz2FRnkU8105bF9VFPQCxV11PlVv/vr/emMoRFLbUOBKH3s
pIJvK5AVI7r8Gfscm+onTz9YGgzRZPCeKVg6Gb3Obsk1K++Hikqj0IWoyPVxDY3CenIRlwag/GNQ
oQEyb+IaTzfsHC/uBGuSWgd6JOBI4xHZJ2cLfFowvqy65FQ8B4ju5ZTM7tkZYROB8DZSwyyvYUG6
uHHZh/uIMBTrLUhOCx8CfqQ+g8Fo6j8M1+/1OynJnmG7FDSxjqtwCgQamShIxJV6tAAOcu4NRJGk
3SZWLJXWO82ySYkrYRBth6CNPYmyOFw97PuLPzJhtvJUWjD3dQR1KGSlYONNpDHn4McYyclSPGQ2
IM29+XcKXJFnutZQ7qLlngiqA6jVDACwyvihICc4o6f4YNTD5ktGB7iorcZ/IJtKb7C7HKsH4kVI
0N0rzRrWCa60CQcNNMN1rS/8Qansqgh04HGN0pEfE+kTdGBOhv4R/mR880PyPEVK5h+dGrQQZNV6
YkZyI4lqqksSzNSZBCmdYf1Z1giinFV+S5+uXqDhd2l9uYUxBPbXuipUtK7LJytu5L2xlhM0UfSW
0mQWOv34WSQRGKV+r9XDUGuEtATY5YOZIea63yZ6UyqAFxDEIvdVBQs1gzczlTbhtMNFI6kSQ4ZL
GlwyiC9o+BEiqeDFWo0ozww5KNEg4sYxZi3+i28Kkp36V/GMWKDogcLTXdk9qr3Vj/mcCIcAAaYf
MwIsUU6XiBUGYx0fqZecaJqYfR+dtgfjSDVDETpmPMYVNNxpcWmi1zZKTX4lCZOXLQ/wci5OE5HQ
3psl6wMQar5x0d002ooMTa8MCMNADENUW955tpZp6jtzsxWYvzcAq3a5F1iWnBArjytYZdxK8Wyu
1yJXJeUxB3FOgozTKuD1gfSNU34sGyyZKL1i09R4yDjI8tC36yWJnTKG9TjzwqSGIoJQFefarPjA
dJtVTjsyDnZXaaR/Quyu3AUHX4rRmt7jLYOrm7dusI5dO6VBFzMGHyEH6lZRnKlaeXv16bynajfp
XES/LcEhOiL33thKKmvTx5FIiD61kkaq+xYc7gAgE8bAjVzJ8LmG/uCxXzv2pFfcNsU9bwJoNerS
pnj3DMt/X1dNfdSz0LWfSYIIj9nlNjTtPbPAEpD9tZ+bRbg6x80X5d+PdC4eW1R+4GE1UYMEJOmV
+Kig3fPclWFEbd9LsYVFtLKATVcmoeQUVpzOYtPU6YGK7nQ41gTvnwbHyw7OB2lTaGadZ7UYZS6n
wbi8XXsjJuMuFE7SVQmzXY102+RudV03kROrY3fMwevJbADKYOKdJBGSo/RLlUvXXGVYF+dTkepi
ukp4xkx0yq4nii0AkSGZ3kWejvY9L+Ir9pUdLJ09zOy4K3y6j/v9GjMSFgxRQnFyOcO2vLPgWnoI
TX3Qe5FtENTpGAdPlfy7mLksGEL53+xSLUXU8VxnLL3+oF0zYGI5wQzITxM1x+EZmgfpuAayXym4
EwI01hY4kHOMQSG4eyQv6THVOV2jCPACW7OQitilOBX67OUh2frcYs7w9FBuL9z/TKDVlgIpESk3
NxREQh4SfXzGQA/gqObg93s1fpgQV6Si7XDPXmqZeCGg8H+FjSCyZ3aOIauX+YLTT3nONyHRX90e
V6pT7P418bXf+6uB6Tja9xWuXBkKgW4aM0dhNRMGIqemuGgmQN2qbplS0DSMc87zDloEW41W6vo/
FPRdH7ylTZnPUNRb19HrF93ASDwZ3JR/huKKkBrc49Zw/PfWqcSg7WL5Byvu3uyywjf0210ct2Gd
DCHiQM5LOS6epe5ATOpXyuHu+VhWXxudbokiVIU4XEIZlqk2Icy1vQLmF144H3E+QuphJbKaDJhk
39aNz+eMmeSJNiVW90hexzVyVi04AUYU/rx4aI8IqwAqNWXjekgPpByg71+1uXS1lASUV/BMEJNn
BRaKMEybCpseiC7Iz9kFEDWqQeDSDdfzl6CcNlD1Z98HT9gPogFVz4TXT+1UY/znc6F+K/KXovzY
d4dW4xkUxE4fxN8Fyf0IRO6kFfSUwjWO/NOaHJpsL/y5BtioRgK3SiJ7Z9W7nHQQnB55SdeOutyS
kp6c7CifHKDuY8n7wa49LZYVhFSuAOVVEkH803NgazbXQibQ5pix3EOOHOd+2GyRIutmEQSkdOAc
bdpoUBDPEcG7nO3rWpaEWy+OLPcmpljVDAsKbQ9JJmToLV7+3isEMpSDeME0pNxhIQj2o8WtsECh
35z2/gaPypensjGikajBrdC9kadXaihdmgAzTgvTCnrA8M+0LoI356acTR4+uX15ucN/3qZ+9zu+
6+exrFyTxhfitELDtkEMSSXUg8SeimXbNYK4tXtleiknLmxXjlzKD8GJ8TKrVQLNlfgjWkcEzH+y
Z0PSHS+hl1WJlexVigmu8KDhbur2NkTQN/YUfiVPfvnFSef1LvTAiuqCDyMTF9SHs+/bQvDr83YP
IDAZFAOtD+fi8bFEfOyjehMEJbBszXrSwhcgy8Xx6e01I67NzViMis65T1DAfKxZUxkKSGaA4TfA
F7PmyoX59vjRv6bRlqVKdNKeEttm7b6Y1J/jRQwbSZNquN0JZ49TCYd9XzqHvhjJ+V/Mt5EQmwbX
nbGjfq4qvgtw6HYPEZq7mzsmpXXaeD5n2hgvV/xmXMVUswbWdhJIajbI8qBNbuJq0m21OcsjEnTx
5TwVOzIbEk/NymaatCzPjcXOYwGZyR3q2b0u6qmTrRrXBxg9nQ4zh+ZtEUesuwU6ujWytRgGYVDN
Ba9d1MSft73+b69l9bIRy8jjaU/4O86fR6UdZ5kkikfaV/jGkxU5LUuupracMTHYQOmEddeVrGhd
BbFEJz2BMp8MRlFrUEQGtON428urL497A2CnvKSZ1TqO21DyCk4GTqKoeLr37zz04fXJoDuNqU5T
8ahslid0WXUbc3tEcpFoyn0ta18kYyEsDZJJtEwuW6+P8aMP4Vka/X14+BOaln0rASZuSTGgt4Dm
LvPR6ZL5EeCDYy/JSSsIOB6fk4VFLhRoTeKmJE1Lek7iTUCXM5AzYO4nlOQmQsonIDsDdvctBAql
J6fCBSc1xKxHuz+xhAhF54WUYbCxh2BPY2YVEyyWAFzQWq3IeoaPu/q3Cowp8Jygd3PgIPQq61dg
lNv87j7jOd5wGjr/rSmI4xMNXRSG/I7VuLxdyOpHZVOtGXVF4VlAoFchOce9HxWp7BC619vKVwOI
2jkwsO2RZ6JVE2vDEHMLVLRZyeLWh775bA+km+sDhjZJauAWagRFXo2tJTSfsDUAk2bDk79yhKlC
UIH6ax7PhO1AMszlxOy0BDgywOVjTJZt2DvtTeHjXnO0aBgYz7ihPA+PoYWFQl9ZW+AArsu6m1EA
2cTp6ZIXHJYhRhqH2zF57O3DFjlnAQ5DWuVh4j0A2tD/kMXWnecVoyeltE3RxkyPRbU4tnyTsCGD
Qmrj/85JGpRnjXsMsIe/wpgjZzPWW3Jxvvr9As9IOvgOTB975JOoMHgltlzKkfI07WlHGeju0PLk
AVT1lWGqZSNmgmCuTIFnrdopPuWviuFDzApHE82gIEQ1Nw3b/6Tl9aDvibC3RVjwKgq6iv4O1/Hd
EQ0071CPPzID15M14ULT+PqHmZr3rBFIZnIqKaorHhvXWjMmxgTJHRQ90D4cqSsP02zhfJPJ4veR
QczEeY61RBK320puudhxeJmB7d8OvSgtsJsxQXiH/yyH03C5SWd/RhXyy9TjenzvTyp4Hti1XvXZ
brvea1X7wH0Q3uDXTM1cFT1EpuTxsUv1fscyQwFWRHhbQZv/VMwf5RE7UNja95LmChWd/d8XTlpA
3yUwR+fesAsVRiFkH0h68sjn/qqnP/DWF+qGtcA67+fvg87/raR2gDdIs0qCk5h8HNAlsc3bD/Nj
Tg+JRmqSk7grAlgaQI7mTujaaU9711Jii3LC7EaZmfTsSaG310RWtFkBlSsX6llftWJwwLzB1s+a
d/ykfQbERYp6cFCajlM41tEqJtV22XDpLwtr1I5CMYsh/f/tQVsYzTOi7Hye092v7DVBGbxUROYr
jx3vks3y1CpTy2d7EfGF71s/4re/FsOGK7hCMUdUfWuLAIGp3LlsD+Paw4hYj+baeTmSrQaSe8zF
6RDxQ9f262IpJKYQxm8JZD2dkrBW/WqtERSh5uUjXmK44JMEPbmZpL2L9fNN1CLUJPf+ktFw/Ou0
uddOCNuMuSupg6f1ivFJuOY8e58Z3ACLpQ+ilgDYpXB2+ZORVu4rIdqUb6A4s76HYXfMhqnh0uji
GUrCjQ5HzhWCxj5iyfKWjqCNZTNKZANIa9KAbMzGiB/OFZIDEjOtcxJXwNVfBSffWN8O/qs7gfwS
gREauqgmhj4KubhZz+/jsEgSQU39A3dnSm7dj9v2+DeThQBLb8glSLMSyZ2+p7t4TtTAXxKmV2VK
rAVuSjrcccVeLyXPRsTAvz37BokuXnFzQEp6+s44wHQTjg4vb8jUkeuXPfpeLw8MovAQbcsKjIDl
I8A+2XSyyR7IPf5YjQQQV5gylQjEPHDZWDh/tNBtoLMIWJu9puyJNpE/NlWck3Ut6Xriv8NJGlDe
aRFEHF+Ccu0ImwpVlWGuZvoSHOVxfj3s3D5GGEJdCSwnBu8kBJThtsPl5iSDX7ktRAw5JxmP7dYk
yYc2fZAFt3l7Hhflw6zcko51T64FJSOIWrDpOmT2t23LH4aG9/hlpznA0TjOKdnrLmXsaGETk8jG
2I2I0XBcS8xnbv7nFo0ZK6XZhs0OdCGLycTMJMoBtDddIAiAC2GRWuWwweyluZd4nh0gZYVS8/3H
WQEWVS7dGL3RLcFUOtPl+5zUI/S5KgoRXcU0o69OngxlYLE+4mq1m7MWDb95iIH/vCw1Y6xBs1TW
Pyc/587tngNSkmnRgA2/xMSCFbxQOxUCZM95PWjhSXJZHVFmQLWxO5RMSaZUeWEQyaR/MVDTjYfE
LZ3jBiKzAL92xZ93yA339O2bXutQ6RT4PRky6DeDpJY3hObvWcmJSNcDsNdqpdZyzscFGmaB/7tq
+TsEMdE9i8djkS0529E1eLA6tBJHGbMQskdbV+Tx6SP/7cgTte54DLz8P0DU00PU2wq/mc2D3gFT
bYhnNbYPHlBabum5rFFqwNcv1UJN0NhL5QeeNcWY4CPa+XzSyd7G0OHYDu3YzP2mNGKey9XV56gJ
xQ==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
h2WWSrz+D0TWLPOzP7lOTCZDI/eqUIFnHrDzDQ9v+JR608NI69bpXqoV63l0SVjAuzmbclp7XJBs
ysWydDuWxA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
R869UJMYRO8mVLLNHGSzwGZDZ9qgRHUifful5lYkU1DWVD+AqZ+c2nQgt8NRrBHW9vApUzyq6bXw
8xEjzZBjVl/1uCB2FVTI+VzLDfg0omMmTaDQ05r4QRdwAuVyWz7h5qxKKrrlra0NUBKbbdUg3Ocj
BxU5IPAtaFgIm5dNSRI=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
gBsF+qw2d8x/ccbw2S3MiPmTal2ZtaOYaOwfh7xyo/wWmIHTdVMt+DcqXnwX+tgr/pmEJ66z2mFF
XjRqmRiXJGY3uEOrsF+ziw5Axczu8CBTne+JIIwvxDXzg48XEmU62CVY5sJCwzcSgB6q87k0+rY9
5jb3T3/imgA9kdtRjOI0HhFahNwH/FrgREwigRoChGJlAHUTaNdqIsfvKzKYuE2IzQQdemTirshC
Qf3IazP/ZXEGfCsCo3f39RFDvg0cX1/IOC2xIHvaWPmRvCoK3sAEHc24v7YDdpJpQPEVaW2Lx2PO
mAppT+eYpciY7zd9xnZk7gx856oKg0750LM4xQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
XIrODxiST7VMQRIE1s0vS9fYU3kHdTTPkI5KinLmaC+RZtKbtN/+X6QJsk+DWKFyprRZT1SffHCn
RsqFGUalBiZYEI1SFR/AedXEnT72I0+SsW+BpbA+Zsh77yE0mXZmlIXkj2GTAYf9ktImDkDrvIs4
RlFsG0H+sHxf0jopuDQ=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Kz86WAqS4KgiRahR7qZvs66gcWZfEtOyy6TUVz9LJGmATBQ6vebHZqpbxxobuKlU833xcYR6vyWf
fzSL/ef7LHlP+AOBGvZbiG/EA7Zsn5AVx9dz/l61cqp05v5jrs4rchlZXJckcMP4Yo0PjAcIIwRM
/rNFTABQ/U3LccqE8OV3+WyoT4nmGOm1+1KfKjiAcGoz8yqBPBjG6KfSOh5WOtX3l20nx10lkCnG
yx1IbFE8E899bTQ2DCjHQH4+WUemhZGLIH6BKvRF475e9jiHNXOuckc6B/bbrbsIPvrufGU7ZpY7
FCYjihIaE27Ik8VkNmXEXP00X/GjWwWA8XZ4Tg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7696)
`protect data_block
2D99qemIBj+gqo+uOTOFwm17OEq3H5EcRmGUcRQk+5BWmTL2MwgsMvASZ313Tj0FVh6X3rlZZGRf
DwF2OIh7qhGPd7rcpbyZKO5MJW+monGRtd/DRU/bTeZnlB2zIPdgL8gbviR9LSpGVXUtQalPUegP
5oRQqee3vgMVnc5ChaySFvsbwy12x6CcZ5dSPnXzK3PTD3GIj8umRa7I+U5Mw4NHEKzLTBjTT341
uxaIJjwIvel41/2t9tRjlNxhfmsKX6Qrfm6t7byqimeTAEUOJSZdyx9Or2kvBY9MSD7NSES9Iwcu
zlGxj3lX1BKav9jn2Xu8Y4Abz+vyq6i76KoQjGP4NUk5J7I025R6N4FOJLaZ0qMPRV3J4NgpL/MV
4C60RDVlQ39r0AugQKesg/JVI33hRrQMww29T2Sw7EXJlP4QLcz8l5Kz9F4pVdB3+FJDOvN6rpdE
rz3EhCPq0I3A4XGslR05JtofweVk5cEo4n00TGvlJwSl5EmfT17gaBDCB37q6/6Ns9iyYyAaspEH
StN117sT+9QoZetB2uHHc9BeU8zEK6J8lNtF9aRO89oQSdoSRr/htfJUWLUFwv/d6Fdt5hdta5Uv
jmY+I3z8yY14DbMdmNxWKGrJfspcbhVCSkRTpcEu1upyev4nGy/KgmjyFItZnnldoAmHWxjfYQw3
Tf4KcJz4/m1sNQ8bBaFVkEuIA1IBry0Y6MzrfuWpROFtbaLPXeRJdYMcMqhg72GRXalFXh4vFFcX
wFybV0lxRf7XjGuaF4MPCf95PEJwdwE7SCOKFot3MS8rkZ1r2w/ZhehlU8AnA95You1INuWGMcZn
5866fvZnN61RCjt4eV9EC+jDpZCAva1EIqvyiyfMXqXJ7D7qBI7TDbwTd74mB9F9a1Mo53oNmYMG
vq4n+YgZT+Xw2aQasHJzFNT0aMJ98p29RW8MjVlnQUe4p86a9Pmk3oTgIdulobekf+n46vKqY7/S
HmaTGzlJp1OPMrBQ6kESr90/vjJZQ/vqxBfEM2sV2OwWkFGjhwOku+H+J1QjRB7Ah7uMr0FmHmll
SGSNBDzwmSiL5Q/ETQmwXxEvKMpm7oCMOo6cAUDtHCZrVlGrGiKFT2lCbTGGLdEptQo0JMQU6eMd
BC5lvpxZIBo1tmXenRWFEMgOGJKz0zT+gtrRYOYYTwuhy8kllVBtKYNW5nmHzt3aqc5uMtlMlXeq
1gkTn0+GPXlZBLUhOSPWW5iebbkGfvzaajMGKFEWCUnVScXYzCaKjVFXpnJyQTcgouwxs+4wpLWB
Kexxd1Ml51D6bE1rQn3Cx/BkJTqv+O78G+44+dOGPBFPgfPbolHEzE7CdseSuEOs/Ndmnp4pWTCG
EhX/rVauRzzr7ip0YGyXEAnmsWYyIzD4vtXRjVUkT9pUp3+U8oGXpAkLeV4uCt74XpuFbAWm6McI
+YxLeKlZ2Fg9qN4VrAoet1Dcpx0kndsd7D7OgFKEBAipXcGtT0PdjVF5V9PKyEjkoEBCKampQ9v3
Lg6iFtXGaYuNIxtbPQMs9IeMeT23PkBxGPLVbNxNTDmjTbcrEPCtbo2mL0U6iSzpiPW2g2/g40vG
bIb1YrPKHmXzithrC6dw2DqUwDzbbycQ8TmS/j6ur4Po1NnOkXfG8zz8XIyO3vmwjU6UfzSb1yCo
S9J6/MSpNfFBc0QOCWMyylTzLcOXBo3smgrXYbMGRNT0jrB+aCE0ViXQz/xFOanL8mP4dWAjSYuI
IYWkOM/4vpp4ebF9dse0dkIVAByDG/kUAWz2by4crPCZClO30DknR0VTWOsgQkH8pWR1muNY9vnk
LxXw2vvepbQpSmilKJDDJhYq8N8391YdfYiI94n1fgxFRXqcuVnekOQMdlG2hE55B/1AUD26ZRZI
jfLNm3tdR2Ko2zsGeZbv/833VWiniaIz97gxHdniJEIAr2+BNpEXPsGnQO75B4a31xmhZnCNSP5b
HA8ge0Z3ruVmVFpwdgKyhAp3n9XWpWWBs+UAsDNGjN7rM7XBZKkeeFTyzPYy19482u+v1DNiMabB
7fVPPLPoZp5yzax5dr3AKVuM1SjFHmG1XzQipuklaB1BbiY5X3zwN4MOYP2BYOXEAihVEYvdZjSg
4gWgFk4GxG7szP1ciymzN35thZAB8vn7dL7l1TES4fP4PG0FKTTmGrGFZHaDZHLTvg1QafhHrd3j
ETZ/XxUSMj3lBQRK17bCvkqcz+5hi8WmtwW1gGi031PVYO7qCL9ms9WJvIULaDzxc2hjQgm+2DnX
5QwpyjgrKyqFC3k0RwSFBYJnVPBqeFdnXni8uMhhb9o+tWUEnIm+QRBd3Sv1Fmv2qsAvgWjOCBGe
ZCBNDUzf8LEuvvc6Wqh0ZY/+ZXnz3HYniD3W6C8aIWSP36pp6zCKqIWruV//V/sUd7EZHnvcq88F
dZmnhsRaNyMFDgRgA1CvVeOH2d6o36fdmytFK3llnPusDNUZRGjgQmH67Fz2e3FDvzSom79Qw4Kr
Akq+tjFNLjFqFKIA5vvSZPq5fr5GffSJYIMctcfwpv5oJ3hDSN7U5lFvT9vtBrPScVp1B++Gy2AV
RdiqXN/EcrFyS1O+qw8yQdcG2mUeZz2UUSirFfzZRfJ99FnH4t32uw7upesXDCj0fyWCsADPC8FE
/u1NNhcexzPSekN2OrBmOwdNNnh2zw921zLAvLelMtJ2HvaDmrTJKgaWU2BnNjbsUqVZldgl4LDu
aB1ROAWEmLlLqk5RurJp8vE1r6M73SXHOERZnrbQD+ZYFhUNpL0bkCZNA3KegK8H848hYynlH/Cs
e3cXyxo4V9+kON3RiPz/ZjaV6NYo13Z/fgDsektSSFam7S84R/s6RXnjE6i7matMYvNEAN7XLW7h
CX6aSsaMucOn8m/cI108FUGDmFrPfqvu5NDYWHdEN454bfIGGi2lNILdYOM3Dn4FO3PRpkYpcA1n
0yRwirD7yVMRxCjzsxsmKP3+NnJnzGFS+LOnfZdC22R0FImZWKW8APdS6hYi3EuxKnwgzXy6MwGr
btnzyOQ3ur/vQCroVD7HL/H8qQx7h2m6ajyV6OU0w2rky5hqFam0MiU2/GCAm1n8gG2iI9AW1CGS
Zdjq7DPudsGc96gEXcyf4YaLbh+zCzG6dhl78AedeLxFDkNqlzmLRhfPt4/LzXVPfgizV9fiE7UG
mXRmPGp1AHCaY6MLNB/kXWwKMxXr9U+qMounlUTyd67cAnS090NPxeWnZZn+hZJxx8WD8mSU3FNH
EMRUruPxg/h988TtBRlLCqmj/90KH4i4tcfD5JgkvzWdrzJFHCFx3gFb7RXtLEZJXZxTkJAoAAEP
GNKyvMGkr+rgChpf0fBlKcedf9rb0Fn2bppakcAJYFtXDuWQbbuFuIzpctbnCG5nknE28Xb3rdZl
VYAjx8Gc6+icbL5aK22y1OsKBQof69vbyXrbv7MA0xmw/5GdL2PxSY8WqKXHue9jrVVxm+xVtF3v
II5eG27MjO7d6vG27Djs8k2CnTY4EU9flxnFn/mP14rHSArvkPZ7X/ul9vv3q/7BGROGOpc0S6rW
8yKz4yYTCMsDMADG+E5h048ix+fsfrfWNKgQvSxgnUyfZXobbwRH+yIPBX2Sgwg4g1R6WIXDQai3
47YPVqdsBMZ94bA6bK6ReoD2bNOz9ajLX7z7E/EVDxs55Wx/KzHjciVGrKYFUYDnq9R6QB29MJ6V
8M846yiEtedTSfqXZteZl0XVhMfPys3DfbCM2Tu4gzlNlqRBLGUabJsAPLx1r4FYCbznYhunacMF
YDWsyAFMKgnMSGTS2S+ekUleXW4uMsDXRnH7BC/Y3Fmi2jCSd4DAOQtahwchcBTxJwbuWRVSlVnX
uV9ZK4SOqNXbgRYmeyUuld6sxdU7sqBdI2HtEHKgiUFc7f7VMVbZijsLPEwGGWRb8dgn+dKcPAqE
UegAmHu/Wdq/sdw8PxWQooyYD3yy97eA4QtcbCAiccIXqTUlbYcGrNLke8tDEEXPP5yhnTx++1gK
C3rOzVg/pzr5lZe03CdXT4GmL7Mlp/jjf3K6lhb3NwD7HgGOOBRJBrHNZlGcByfB39pihWN7ZQjF
EQh+I0+u4nnPozCxVHNhfE1wel+O6G47pMLJ7+oTcjU5GDxYvWLp9Ql5sfnrsVFbxxQfSOybRfhW
NSgn6TXgCzIb4RnB5TyXM+29YKh3fb60j6VQkfBuQ1aZrBXfSoSSc5lERndAo7AvbX3Cszd3wP9M
lX2VEcFEQAWHaj8o/3DomMkOx5qSNXSbVn6xWZqeUFWFMOVIh/DNYD4QvPUqicUxM8fHnof7f83y
6VfCwmd848vr9kbX2BqhOxDagD7VxlwaB96Z8dS8ayQdIvNtZhm6Lkd7C3BYCu7sG49lvubtPOou
HWdYhdw7l743ppki6YpNaV/ttTLx2dwkgnolHYipH+tozyfZhK8Tog6J3qka0/M6huMkSPqGHN9F
tZpgrYTbYTpwlKpZEbfkrMwiFdMq02tHo/1/PdVVlpM0FF+Jd42r9UCfo3KLY4YRRhUSherYTUL8
G7Bak8xT61t0a8u2m5vypRZoxEQkqMXhUM+ecJ6MZPVBQnKEBm5YJhH7nw5gbKtqt/1ZN/IT3m/a
dGeUm4e4KuYVg5INsNGJEPruqSkEGpjsJJPjiyGokdiTAh0VTLsAJRE6FjRwYrrp9J6oXycNbhp4
3CLc0+CA9fkErkmSQw/esEgl4iXUYLG2iPFot6rUW0IznRjy2elDHgEJAIKui6CepEbZrzOQp0W+
FNciC9Uz+6HXAXvmg0gVH9IBFFfRz9cyIxpk8rjiQuj2xxyRYtfFUroDeuZhiBOjklonIgO33Hfa
uIb+uYX8cSgVq/Mal13fNMJQV2DfIGgdeYUZRmzzrPYtG+RiPYVgTL1bDf9wSXm6aYIO0Lxrw8IW
Kncimzk5OfctVXz4OtynLfmDeU41yP36fFshJhyh8iNxrPcVYLiZ2wBiZ06rL29iThb8Sapuno3d
VBxR6ndLnqI7KVzeo9M7+u/asFdeXiz2FRnkU8105bF9VFPQCxV11PlVv/vr/emMoRFLbUOBKH3s
pIJvK5AVI7r8Gfscm+onTz9YGgzRZPCeKVg6Gb3Obsk1K++Hikqj0IWoyPVxDY3CenIRlwag/GNQ
oQEyb+IaTzfsHC/uBGuSWgd6JOBI4xHZJ2cLfFowvqy65FQ8B4ju5ZTM7tkZYROB8DZSwyyvYUG6
uHHZh/uIMBTrLUhOCx8CfqQ+g8Fo6j8M1+/1OynJnmG7FDSxjqtwCgQamShIxJV6tAAOcu4NRJGk
3SZWLJXWO82ySYkrYRBth6CNPYmyOFw97PuLPzJhtvJUWjD3dQR1KGSlYONNpDHn4McYyclSPGQ2
IM29+XcKXJFnutZQ7qLlngiqA6jVDACwyvihICc4o6f4YNTD5ktGB7iorcZ/IJtKb7C7HKsH4kVI
0N0rzRrWCa60CQcNNMN1rS/8Qansqgh04HGN0pEfE+kTdGBOhv4R/mR880PyPEVK5h+dGrQQZNV6
YkZyI4lqqksSzNSZBCmdYf1Z1giinFV+S5+uXqDhd2l9uYUxBPbXuipUtK7LJytu5L2xlhM0UfSW
0mQWOv34WSQRGKV+r9XDUGuEtATY5YOZIea63yZ6UyqAFxDEIvdVBQs1gzczlTbhtMNFI6kSQ4ZL
GlwyiC9o+BEiqeDFWo0ozww5KNEg4sYxZi3+i28Kkp36V/GMWKDogcLTXdk9qr3Vj/mcCIcAAaYf
MwIsUU6XiBUGYx0fqZecaJqYfR+dtgfjSDVDETpmPMYVNNxpcWmi1zZKTX4lCZOXLQ/wci5OE5HQ
3psl6wMQar5x0d002ooMTa8MCMNADENUW955tpZp6jtzsxWYvzcAq3a5F1iWnBArjytYZdxK8Wyu
1yJXJeUxB3FOgozTKuD1gfSNU34sGyyZKL1i09R4yDjI8tC36yWJnTKG9TjzwqSGIoJQFefarPjA
dJtVTjsyDnZXaaR/Quyu3AUHX4rRmt7jLYOrm7dusI5dO6VBFzMGHyEH6lZRnKlaeXv16bynajfp
XES/LcEhOiL33thKKmvTx5FIiD61kkaq+xYc7gAgE8bAjVzJ8LmG/uCxXzv2pFfcNsU9bwJoNerS
pnj3DMt/X1dNfdSz0LWfSYIIj9nlNjTtPbPAEpD9tZ+bRbg6x80X5d+PdC4eW1R+4GE1UYMEJOmV
+Kig3fPclWFEbd9LsYVFtLKATVcmoeQUVpzOYtPU6YGK7nQ41gTvnwbHyw7OB2lTaGadZ7UYZS6n
wbi8XXsjJuMuFE7SVQmzXY102+RudV03kROrY3fMwevJbADKYOKdJBGSo/RLlUvXXGVYF+dTkepi
ukp4xkx0yq4nii0AkSGZ3kWejvY9L+Ir9pUdLJ09zOy4K3y6j/v9GjMSFgxRQnFyOcO2vLPgWnoI
TX3Qe5FtENTpGAdPlfy7mLksGEL53+xSLUXU8VxnLL3+oF0zYGI5wQzITxM1x+EZmgfpuAayXym4
EwI01hY4kHOMQSG4eyQv6THVOV2jCPACW7OQitilOBX67OUh2frcYs7w9FBuL9z/TKDVlgIpESk3
NxREQh4SfXzGQA/gqObg93s1fpgQV6Si7XDPXmqZeCGg8H+FjSCyZ3aOIauX+YLTT3nONyHRX90e
V6pT7P418bXf+6uB6Tja9xWuXBkKgW4aM0dhNRMGIqemuGgmQN2qbplS0DSMc87zDloEW41W6vo/
FPRdH7ylTZnPUNRb19HrF93ASDwZ3JR/huKKkBrc49Zw/PfWqcSg7WL5Byvu3uyywjf0210ct2Gd
DCHiQM5LOS6epe5ATOpXyuHu+VhWXxudbokiVIU4XEIZlqk2Icy1vQLmF144H3E+QuphJbKaDJhk
39aNz+eMmeSJNiVW90hexzVyVi04AUYU/rx4aI8IqwAqNWXjekgPpByg71+1uXS1lASUV/BMEJNn
BRaKMEybCpseiC7Iz9kFEDWqQeDSDdfzl6CcNlD1Z98HT9gPogFVz4TXT+1UY/znc6F+K/KXovzY
d4dW4xkUxE4fxN8Fyf0IRO6kFfSUwjWO/NOaHJpsL/y5BtioRgK3SiJ7Z9W7nHQQnB55SdeOutyS
kp6c7CifHKDuY8n7wa49LZYVhFSuAOVVEkH803NgazbXQibQ5pix3EOOHOd+2GyRIutmEQSkdOAc
bdpoUBDPEcG7nO3rWpaEWy+OLPcmpljVDAsKbQ9JJmToLV7+3isEMpSDeME0pNxhIQj2o8WtsECh
35z2/gaPypensjGikajBrdC9kadXaihdmgAzTgvTCnrA8M+0LoI356acTR4+uX15ucN/3qZ+9zu+
6+exrFyTxhfitELDtkEMSSXUg8SeimXbNYK4tXtleiknLmxXjlzKD8GJ8TKrVQLNlfgjWkcEzH+y
Z0PSHS+hl1WJlexVigmu8KDhbur2NkTQN/YUfiVPfvnFSef1LvTAiuqCDyMTF9SHs+/bQvDr83YP
IDAZFAOtD+fi8bFEfOyjehMEJbBszXrSwhcgy8Xx6e01I67NzViMis65T1DAfKxZUxkKSGaA4TfA
F7PmyoX59vjRv6bRlqVKdNKeEttm7b6Y1J/jRQwbSZNquN0JZ49TCYd9XzqHvhjJ+V/Mt5EQmwbX
nbGjfq4qvgtw6HYPEZq7mzsmpXXaeD5n2hgvV/xmXMVUswbWdhJIajbI8qBNbuJq0m21OcsjEnTx
5TwVOzIbEk/NymaatCzPjcXOYwGZyR3q2b0u6qmTrRrXBxg9nQ4zh+ZtEUesuwU6ujWytRgGYVDN
Ba9d1MSft73+b69l9bIRy8jjaU/4O86fR6UdZ5kkikfaV/jGkxU5LUuupracMTHYQOmEddeVrGhd
BbFEJz2BMp8MRlFrUEQGtON428urL497A2CnvKSZ1TqO21DyCk4GTqKoeLr37zz04fXJoDuNqU5T
8ahslid0WXUbc3tEcpFoyn0ta18kYyEsDZJJtEwuW6+P8aMP4Vka/X14+BOaln0rASZuSTGgt4Dm
LvPR6ZL5EeCDYy/JSSsIOB6fk4VFLhRoTeKmJE1Lek7iTUCXM5AzYO4nlOQmQsonIDsDdvctBAql
J6fCBSc1xKxHuz+xhAhF54WUYbCxh2BPY2YVEyyWAFzQWq3IeoaPu/q3Cowp8Jygd3PgIPQq61dg
lNv87j7jOd5wGjr/rSmI4xMNXRSG/I7VuLxdyOpHZVOtGXVF4VlAoFchOce9HxWp7BC619vKVwOI
2jkwsO2RZ6JVE2vDEHMLVLRZyeLWh775bA+km+sDhjZJauAWagRFXo2tJTSfsDUAk2bDk79yhKlC
UIH6ax7PhO1AMszlxOy0BDgywOVjTJZt2DvtTeHjXnO0aBgYz7ihPA+PoYWFQl9ZW+AArsu6m1EA
2cTp6ZIXHJYhRhqH2zF57O3DFjlnAQ5DWuVh4j0A2tD/kMXWnecVoyeltE3RxkyPRbU4tnyTsCGD
Qmrj/85JGpRnjXsMsIe/wpgjZzPWW3Jxvvr9As9IOvgOTB975JOoMHgltlzKkfI07WlHGeju0PLk
AVT1lWGqZSNmgmCuTIFnrdopPuWviuFDzApHE82gIEQ1Nw3b/6Tl9aDvibC3RVjwKgq6iv4O1/Hd
EQ0071CPPzID15M14ULT+PqHmZr3rBFIZnIqKaorHhvXWjMmxgTJHRQ90D4cqSsP02zhfJPJ4veR
QczEeY61RBK320puudhxeJmB7d8OvSgtsJsxQXiH/yyH03C5SWd/RhXyy9TjenzvTyp4Hti1XvXZ
brvea1X7wH0Q3uDXTM1cFT1EpuTxsUv1fscyQwFWRHhbQZv/VMwf5RE7UNja95LmChWd/d8XTlpA
3yUwR+fesAsVRiFkH0h68sjn/qqnP/DWF+qGtcA67+fvg87/raR2gDdIs0qCk5h8HNAlsc3bD/Nj
Tg+JRmqSk7grAlgaQI7mTujaaU9711Jii3LC7EaZmfTsSaG310RWtFkBlSsX6llftWJwwLzB1s+a
d/ykfQbERYp6cFCajlM41tEqJtV22XDpLwtr1I5CMYsh/f/tQVsYzTOi7Hye092v7DVBGbxUROYr
jx3vks3y1CpTy2d7EfGF71s/4re/FsOGK7hCMUdUfWuLAIGp3LlsD+Paw4hYj+baeTmSrQaSe8zF
6RDxQ9f262IpJKYQxm8JZD2dkrBW/WqtERSh5uUjXmK44JMEPbmZpL2L9fNN1CLUJPf+ktFw/Ou0
uddOCNuMuSupg6f1ivFJuOY8e58Z3ACLpQ+ilgDYpXB2+ZORVu4rIdqUb6A4s76HYXfMhqnh0uji
GUrCjQ5HzhWCxj5iyfKWjqCNZTNKZANIa9KAbMzGiB/OFZIDEjOtcxJXwNVfBSffWN8O/qs7gfwS
gREauqgmhj4KubhZz+/jsEgSQU39A3dnSm7dj9v2+DeThQBLb8glSLMSyZ2+p7t4TtTAXxKmV2VK
rAVuSjrcccVeLyXPRsTAvz37BokuXnFzQEp6+s44wHQTjg4vb8jUkeuXPfpeLw8MovAQbcsKjIDl
I8A+2XSyyR7IPf5YjQQQV5gylQjEPHDZWDh/tNBtoLMIWJu9puyJNpE/NlWck3Ut6Xriv8NJGlDe
aRFEHF+Ccu0ImwpVlWGuZvoSHOVxfj3s3D5GGEJdCSwnBu8kBJThtsPl5iSDX7ktRAw5JxmP7dYk
yYc2fZAFt3l7Hhflw6zcko51T64FJSOIWrDpOmT2t23LH4aG9/hlpznA0TjOKdnrLmXsaGETk8jG
2I2I0XBcS8xnbv7nFo0ZK6XZhs0OdCGLycTMJMoBtDddIAiAC2GRWuWwweyluZd4nh0gZYVS8/3H
WQEWVS7dGL3RLcFUOtPl+5zUI/S5KgoRXcU0o69OngxlYLE+4mq1m7MWDb95iIH/vCw1Y6xBs1TW
Pyc/587tngNSkmnRgA2/xMSCFbxQOxUCZM95PWjhSXJZHVFmQLWxO5RMSaZUeWEQyaR/MVDTjYfE
LZ3jBiKzAL92xZ93yA339O2bXutQ6RT4PRky6DeDpJY3hObvWcmJSNcDsNdqpdZyzscFGmaB/7tq
+TsEMdE9i8djkS0529E1eLA6tBJHGbMQskdbV+Tx6SP/7cgTte54DLz8P0DU00PU2wq/mc2D3gFT
bYhnNbYPHlBabum5rFFqwNcv1UJN0NhL5QeeNcWY4CPa+XzSyd7G0OHYDu3YzP2mNGKey9XV56gJ
xQ==
`protect end_protected
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_19_source-b.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library math;
architecture behavior of source is
begin
token_generator : process is
variable source_name : string(1 to name_max_length) := (others => ' ');
variable source_name_length : natural;
variable next_token_id : token_id_type := 0;
variable next_arrival_time : time;
variable number_of_tokens_generated : natural := 0;
variable inter_arrival_time : natural; -- in time_unit
variable sum_of_inter_arrival_times : real := 0.0; -- in time_unit
variable sum_of_squares_of_inter_arrival_times : real := 0.0; --in time_unit**2
variable random_info : random_info_record;
variable random_number : real;
use std.textio.all;
file info_file : text;
variable L : line;
use math.math_real.sqrt;
procedure write_summary is
variable measured_mean_inter_arrival_time : real
:= sum_of_inter_arrival_times / real(number_of_tokens_generated);
variable measured_std_dev_of_inter_arrival_times : real
:= sqrt ( ( sum_of_squares_of_inter_arrival_times
- sum_of_inter_arrival_times**2 / real(number_of_tokens_generated) )
/ real( number_of_tokens_generated - 1 ) );
begin
write(L, string'("Summary information for source "));
write(L, name);
write(L, string'(" up to time "));
write(L, now, unit => time_unit);
writeline(info_file, L);
write(L, string'(" Inter arrival distribution: "));
write(L, distribution_type'image(distribution));
write(L, string'(" with mean inter arrival time of "));
write(L, mean_inter_arrival_time, unit => time_unit);
writeline(info_file, L);
write(L, string'(" Number of tokens generated = "));
write(L, natural(next_token_id));
writeline(info_file, L);
write(L, string'(" Mean inter arrival time = "));
write(L, measured_mean_inter_arrival_time * time_unit, unit => time_unit);
writeline(info_file, L);
write(L, string'(" Standard deviation of inter arrival times = "));
write(L, measured_std_dev_of_inter_arrival_times * time_unit, unit => time_unit);
writeline(info_file, L);
writeline(info_file, L);
end procedure write_summary;
procedure write_trace is
begin
write(L, string'("Source "));
write(L, name);
write(L, string'(": at "));
write(L, now, unit => time_unit);
write(L, string'(" generated token "));
write(L, natural(next_token_id));
writeline(info_file, L);
end procedure write_trace;
begin
if name'length > name_max_length then
source_name := name(1 to name_max_length);
source_name_length := name_max_length;
else
source_name(1 to name'length) := name;
source_name_length := name'length;
end if;
file_open(info_file, info_file_name, write_mode);
case distribution is
when fixed =>
init_fixed(random_info, real(mean_inter_arrival_time / time_unit));
when uniform =>
init_uniform( random_info,
lower_bound => 0.0,
upper_bound => 2.0 * real(mean_inter_arrival_time / time_unit),
seed => seed );
when exponential =>
init_exponential( random_info,
mean => real(mean_inter_arrival_time / time_unit),
seed => seed );
end case;
loop
generate_random(random_info, random_number);
inter_arrival_time := natural(random_number);
next_arrival_time := inter_arrival_time * time_unit + now;
loop
wait on info_detail'transaction for next_arrival_time - now;
if info_detail'active and info_detail = summary then
write_summary;
end if;
exit when next_arrival_time = now;
end loop;
out_arc <= arc_type'( transaction => not out_arc.transaction'driving_value,
token => token_type'( source_name => source_name,
source_name_length => source_name_length,
id => next_token_id,
creation_time => now ) );
number_of_tokens_generated := number_of_tokens_generated + 1;
sum_of_inter_arrival_times := sum_of_inter_arrival_times
+ real(inter_arrival_time);
sum_of_squares_of_inter_arrival_times := sum_of_squares_of_inter_arrival_times
+ real(inter_arrival_time) ** 2;
if info_detail = trace then
write_trace;
end if;
next_token_id := next_token_id + 1;
end loop;
end process token_generator;
end architecture behavior;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_19_source-b.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library math;
architecture behavior of source is
begin
token_generator : process is
variable source_name : string(1 to name_max_length) := (others => ' ');
variable source_name_length : natural;
variable next_token_id : token_id_type := 0;
variable next_arrival_time : time;
variable number_of_tokens_generated : natural := 0;
variable inter_arrival_time : natural; -- in time_unit
variable sum_of_inter_arrival_times : real := 0.0; -- in time_unit
variable sum_of_squares_of_inter_arrival_times : real := 0.0; --in time_unit**2
variable random_info : random_info_record;
variable random_number : real;
use std.textio.all;
file info_file : text;
variable L : line;
use math.math_real.sqrt;
procedure write_summary is
variable measured_mean_inter_arrival_time : real
:= sum_of_inter_arrival_times / real(number_of_tokens_generated);
variable measured_std_dev_of_inter_arrival_times : real
:= sqrt ( ( sum_of_squares_of_inter_arrival_times
- sum_of_inter_arrival_times**2 / real(number_of_tokens_generated) )
/ real( number_of_tokens_generated - 1 ) );
begin
write(L, string'("Summary information for source "));
write(L, name);
write(L, string'(" up to time "));
write(L, now, unit => time_unit);
writeline(info_file, L);
write(L, string'(" Inter arrival distribution: "));
write(L, distribution_type'image(distribution));
write(L, string'(" with mean inter arrival time of "));
write(L, mean_inter_arrival_time, unit => time_unit);
writeline(info_file, L);
write(L, string'(" Number of tokens generated = "));
write(L, natural(next_token_id));
writeline(info_file, L);
write(L, string'(" Mean inter arrival time = "));
write(L, measured_mean_inter_arrival_time * time_unit, unit => time_unit);
writeline(info_file, L);
write(L, string'(" Standard deviation of inter arrival times = "));
write(L, measured_std_dev_of_inter_arrival_times * time_unit, unit => time_unit);
writeline(info_file, L);
writeline(info_file, L);
end procedure write_summary;
procedure write_trace is
begin
write(L, string'("Source "));
write(L, name);
write(L, string'(": at "));
write(L, now, unit => time_unit);
write(L, string'(" generated token "));
write(L, natural(next_token_id));
writeline(info_file, L);
end procedure write_trace;
begin
if name'length > name_max_length then
source_name := name(1 to name_max_length);
source_name_length := name_max_length;
else
source_name(1 to name'length) := name;
source_name_length := name'length;
end if;
file_open(info_file, info_file_name, write_mode);
case distribution is
when fixed =>
init_fixed(random_info, real(mean_inter_arrival_time / time_unit));
when uniform =>
init_uniform( random_info,
lower_bound => 0.0,
upper_bound => 2.0 * real(mean_inter_arrival_time / time_unit),
seed => seed );
when exponential =>
init_exponential( random_info,
mean => real(mean_inter_arrival_time / time_unit),
seed => seed );
end case;
loop
generate_random(random_info, random_number);
inter_arrival_time := natural(random_number);
next_arrival_time := inter_arrival_time * time_unit + now;
loop
wait on info_detail'transaction for next_arrival_time - now;
if info_detail'active and info_detail = summary then
write_summary;
end if;
exit when next_arrival_time = now;
end loop;
out_arc <= arc_type'( transaction => not out_arc.transaction'driving_value,
token => token_type'( source_name => source_name,
source_name_length => source_name_length,
id => next_token_id,
creation_time => now ) );
number_of_tokens_generated := number_of_tokens_generated + 1;
sum_of_inter_arrival_times := sum_of_inter_arrival_times
+ real(inter_arrival_time);
sum_of_squares_of_inter_arrival_times := sum_of_squares_of_inter_arrival_times
+ real(inter_arrival_time) ** 2;
if info_detail = trace then
write_trace;
end if;
next_token_id := next_token_id + 1;
end loop;
end process token_generator;
end architecture behavior;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_19_source-b.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library math;
architecture behavior of source is
begin
token_generator : process is
variable source_name : string(1 to name_max_length) := (others => ' ');
variable source_name_length : natural;
variable next_token_id : token_id_type := 0;
variable next_arrival_time : time;
variable number_of_tokens_generated : natural := 0;
variable inter_arrival_time : natural; -- in time_unit
variable sum_of_inter_arrival_times : real := 0.0; -- in time_unit
variable sum_of_squares_of_inter_arrival_times : real := 0.0; --in time_unit**2
variable random_info : random_info_record;
variable random_number : real;
use std.textio.all;
file info_file : text;
variable L : line;
use math.math_real.sqrt;
procedure write_summary is
variable measured_mean_inter_arrival_time : real
:= sum_of_inter_arrival_times / real(number_of_tokens_generated);
variable measured_std_dev_of_inter_arrival_times : real
:= sqrt ( ( sum_of_squares_of_inter_arrival_times
- sum_of_inter_arrival_times**2 / real(number_of_tokens_generated) )
/ real( number_of_tokens_generated - 1 ) );
begin
write(L, string'("Summary information for source "));
write(L, name);
write(L, string'(" up to time "));
write(L, now, unit => time_unit);
writeline(info_file, L);
write(L, string'(" Inter arrival distribution: "));
write(L, distribution_type'image(distribution));
write(L, string'(" with mean inter arrival time of "));
write(L, mean_inter_arrival_time, unit => time_unit);
writeline(info_file, L);
write(L, string'(" Number of tokens generated = "));
write(L, natural(next_token_id));
writeline(info_file, L);
write(L, string'(" Mean inter arrival time = "));
write(L, measured_mean_inter_arrival_time * time_unit, unit => time_unit);
writeline(info_file, L);
write(L, string'(" Standard deviation of inter arrival times = "));
write(L, measured_std_dev_of_inter_arrival_times * time_unit, unit => time_unit);
writeline(info_file, L);
writeline(info_file, L);
end procedure write_summary;
procedure write_trace is
begin
write(L, string'("Source "));
write(L, name);
write(L, string'(": at "));
write(L, now, unit => time_unit);
write(L, string'(" generated token "));
write(L, natural(next_token_id));
writeline(info_file, L);
end procedure write_trace;
begin
if name'length > name_max_length then
source_name := name(1 to name_max_length);
source_name_length := name_max_length;
else
source_name(1 to name'length) := name;
source_name_length := name'length;
end if;
file_open(info_file, info_file_name, write_mode);
case distribution is
when fixed =>
init_fixed(random_info, real(mean_inter_arrival_time / time_unit));
when uniform =>
init_uniform( random_info,
lower_bound => 0.0,
upper_bound => 2.0 * real(mean_inter_arrival_time / time_unit),
seed => seed );
when exponential =>
init_exponential( random_info,
mean => real(mean_inter_arrival_time / time_unit),
seed => seed );
end case;
loop
generate_random(random_info, random_number);
inter_arrival_time := natural(random_number);
next_arrival_time := inter_arrival_time * time_unit + now;
loop
wait on info_detail'transaction for next_arrival_time - now;
if info_detail'active and info_detail = summary then
write_summary;
end if;
exit when next_arrival_time = now;
end loop;
out_arc <= arc_type'( transaction => not out_arc.transaction'driving_value,
token => token_type'( source_name => source_name,
source_name_length => source_name_length,
id => next_token_id,
creation_time => now ) );
number_of_tokens_generated := number_of_tokens_generated + 1;
sum_of_inter_arrival_times := sum_of_inter_arrival_times
+ real(inter_arrival_time);
sum_of_squares_of_inter_arrival_times := sum_of_squares_of_inter_arrival_times
+ real(inter_arrival_time) ** 2;
if info_detail = trace then
write_trace;
end if;
next_token_id := next_token_id + 1;
end loop;
end process token_generator;
end architecture behavior;
|
entity ENTITY1 is
generic (
wait_generic : std_logic := '0'
);
port (
wait_port : std_logic := '1'
);
end entity ENTITY1;
architecture ARCH of ENTITY1 is
signal wait_for_something : std_logic;
component ENTITY2 is
generic (
wait_generic : std_logic := '0'
);
port (
wait_port : std_logic := '1'
);
end component ENTITY2;
begin
PROC1 : process (wait_for_something) is
-- wait <-- this should not be classified as a wait
variable wait_for_other_thing : std_logic;
begin
wait for 10ns;
wait on a,b;
wait until a = '0';
end process PROC1;
U_ENTITY2 : ENTITY2
generic map (
wait_generic => '0'
)
port map (
wait_port => '1'
);
end architecture ARCH;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc298.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b03x01p01n03i00298ent IS
END c03s01b03x01p01n03i00298ent;
ARCHITECTURE c03s01b03x01p01n03i00298arch OF c03s01b03x01p01n03i00298ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( (us = 1000 ns) and
(ms = 1000 us) and
(sec = 1000 ms) )
report "***PASSED TEST: c03s01b03x01p01n03i00298"
severity NOTE;
assert ( (us = 1000 ns) and
(ms = 1000 us) and
(sec = 1000 ms) )
report "***FAILED TEST: c03s01b03x01p01n03i00298 - Type TIME is defined with an ascending ragne."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b03x01p01n03i00298arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc298.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b03x01p01n03i00298ent IS
END c03s01b03x01p01n03i00298ent;
ARCHITECTURE c03s01b03x01p01n03i00298arch OF c03s01b03x01p01n03i00298ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( (us = 1000 ns) and
(ms = 1000 us) and
(sec = 1000 ms) )
report "***PASSED TEST: c03s01b03x01p01n03i00298"
severity NOTE;
assert ( (us = 1000 ns) and
(ms = 1000 us) and
(sec = 1000 ms) )
report "***FAILED TEST: c03s01b03x01p01n03i00298 - Type TIME is defined with an ascending ragne."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b03x01p01n03i00298arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc298.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b03x01p01n03i00298ent IS
END c03s01b03x01p01n03i00298ent;
ARCHITECTURE c03s01b03x01p01n03i00298arch OF c03s01b03x01p01n03i00298ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( (us = 1000 ns) and
(ms = 1000 us) and
(sec = 1000 ms) )
report "***PASSED TEST: c03s01b03x01p01n03i00298"
severity NOTE;
assert ( (us = 1000 ns) and
(ms = 1000 us) and
(sec = 1000 ms) )
report "***FAILED TEST: c03s01b03x01p01n03i00298 - Type TIME is defined with an ascending ragne."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b03x01p01n03i00298arch;
|
configuration conf of ent is
use work.foo;
attribute x of y : signal is 5;
for arch
for all : comp
use entity work.foo(x);
end for;
for blah : moo use configuration work.blafsfd; end for;
end for;
end configuration;
|
entity ENT00001_Test_Bench is
end entity ENT00001_Test_Bench;
architecture arch of ENT00001_Test_Bench is
signal clk : integer := 0;
constant CYCLES : integer := 10000;
-- {{{
signal a0001 : integer;
signal a0002 : integer;
signal a0003 : integer;
signal a0004 : integer;
signal a0005 : integer;
signal a0006 : integer;
signal a0007 : integer;
signal a0008 : integer;
signal a0009 : integer;
signal a0010 : integer;
signal a0011 : integer;
signal a0012 : integer;
signal a0013 : integer;
signal a0014 : integer;
signal a0015 : integer;
signal a0016 : integer;
signal a0017 : integer;
signal a0018 : integer;
signal a0019 : integer;
signal a0020 : integer;
signal a0021 : integer;
signal a0022 : integer;
signal a0023 : integer;
signal a0024 : integer;
signal a0025 : integer;
signal a0026 : integer;
signal a0027 : integer;
signal a0028 : integer;
signal a0029 : integer;
signal a0030 : integer;
signal a0031 : integer;
signal a0032 : integer;
signal a0033 : integer;
signal a0034 : integer;
signal a0035 : integer;
signal a0036 : integer;
signal a0037 : integer;
signal a0038 : integer;
signal a0039 : integer;
signal a0040 : integer;
signal a0041 : integer;
signal a0042 : integer;
signal a0043 : integer;
signal a0044 : integer;
signal a0045 : integer;
signal a0046 : integer;
signal a0047 : integer;
signal a0048 : integer;
signal a0049 : integer;
signal a0050 : integer;
signal a0051 : integer;
signal a0052 : integer;
signal a0053 : integer;
signal a0054 : integer;
signal a0055 : integer;
signal a0056 : integer;
signal a0057 : integer;
signal a0058 : integer;
signal a0059 : integer;
signal a0060 : integer;
signal a0061 : integer;
signal a0062 : integer;
signal a0063 : integer;
signal a0064 : integer;
signal a0065 : integer;
signal a0066 : integer;
signal a0067 : integer;
signal a0068 : integer;
signal a0069 : integer;
signal a0070 : integer;
signal a0071 : integer;
signal a0072 : integer;
signal a0073 : integer;
signal a0074 : integer;
signal a0075 : integer;
signal a0076 : integer;
signal a0077 : integer;
signal a0078 : integer;
signal a0079 : integer;
signal a0080 : integer;
signal a0081 : integer;
signal a0082 : integer;
signal a0083 : integer;
signal a0084 : integer;
signal a0085 : integer;
signal a0086 : integer;
signal a0087 : integer;
signal a0088 : integer;
signal a0089 : integer;
signal a0090 : integer;
signal a0091 : integer;
signal a0092 : integer;
signal a0093 : integer;
signal a0094 : integer;
signal a0095 : integer;
signal a0096 : integer;
signal a0097 : integer;
signal a0098 : integer;
signal a0099 : integer;
signal a0100 : integer;
signal a0101 : integer;
signal a0102 : integer;
signal a0103 : integer;
signal a0104 : integer;
signal a0105 : integer;
signal a0106 : integer;
signal a0107 : integer;
signal a0108 : integer;
signal a0109 : integer;
signal a0110 : integer;
signal a0111 : integer;
signal a0112 : integer;
signal a0113 : integer;
signal a0114 : integer;
signal a0115 : integer;
signal a0116 : integer;
signal a0117 : integer;
signal a0118 : integer;
signal a0119 : integer;
signal a0120 : integer;
signal a0121 : integer;
signal a0122 : integer;
signal a0123 : integer;
signal a0124 : integer;
signal a0125 : integer;
signal a0126 : integer;
signal a0127 : integer;
signal a0128 : integer;
signal a0129 : integer;
signal a0130 : integer;
signal a0131 : integer;
signal a0132 : integer;
signal a0133 : integer;
signal a0134 : integer;
signal a0135 : integer;
signal a0136 : integer;
signal a0137 : integer;
signal a0138 : integer;
signal a0139 : integer;
signal a0140 : integer;
signal a0141 : integer;
signal a0142 : integer;
signal a0143 : integer;
signal a0144 : integer;
signal a0145 : integer;
signal a0146 : integer;
signal a0147 : integer;
signal a0148 : integer;
signal a0149 : integer;
signal a0150 : integer;
signal a0151 : integer;
signal a0152 : integer;
signal a0153 : integer;
signal a0154 : integer;
signal a0155 : integer;
signal a0156 : integer;
signal a0157 : integer;
signal a0158 : integer;
signal a0159 : integer;
signal a0160 : integer;
signal a0161 : integer;
signal a0162 : integer;
signal a0163 : integer;
signal a0164 : integer;
signal a0165 : integer;
signal a0166 : integer;
signal a0167 : integer;
signal a0168 : integer;
signal a0169 : integer;
signal a0170 : integer;
signal a0171 : integer;
signal a0172 : integer;
signal a0173 : integer;
signal a0174 : integer;
signal a0175 : integer;
signal a0176 : integer;
signal a0177 : integer;
signal a0178 : integer;
signal a0179 : integer;
signal a0180 : integer;
signal a0181 : integer;
signal a0182 : integer;
signal a0183 : integer;
signal a0184 : integer;
signal a0185 : integer;
signal a0186 : integer;
signal a0187 : integer;
signal a0188 : integer;
signal a0189 : integer;
signal a0190 : integer;
signal a0191 : integer;
signal a0192 : integer;
signal a0193 : integer;
signal a0194 : integer;
signal a0195 : integer;
signal a0196 : integer;
signal a0197 : integer;
signal a0198 : integer;
signal a0199 : integer;
signal a0200 : integer;
signal a0201 : integer;
signal a0202 : integer;
signal a0203 : integer;
signal a0204 : integer;
signal a0205 : integer;
signal a0206 : integer;
signal a0207 : integer;
signal a0208 : integer;
signal a0209 : integer;
signal a0210 : integer;
signal a0211 : integer;
signal a0212 : integer;
signal a0213 : integer;
signal a0214 : integer;
signal a0215 : integer;
signal a0216 : integer;
signal a0217 : integer;
signal a0218 : integer;
signal a0219 : integer;
signal a0220 : integer;
signal a0221 : integer;
signal a0222 : integer;
signal a0223 : integer;
signal a0224 : integer;
signal a0225 : integer;
signal a0226 : integer;
signal a0227 : integer;
signal a0228 : integer;
signal a0229 : integer;
signal a0230 : integer;
signal a0231 : integer;
signal a0232 : integer;
signal a0233 : integer;
signal a0234 : integer;
signal a0235 : integer;
signal a0236 : integer;
signal a0237 : integer;
signal a0238 : integer;
signal a0239 : integer;
signal a0240 : integer;
signal a0241 : integer;
signal a0242 : integer;
signal a0243 : integer;
signal a0244 : integer;
signal a0245 : integer;
signal a0246 : integer;
signal a0247 : integer;
signal a0248 : integer;
signal a0249 : integer;
signal a0250 : integer;
signal a0251 : integer;
signal a0252 : integer;
signal a0253 : integer;
signal a0254 : integer;
signal a0255 : integer;
signal a0256 : integer;
signal a0257 : integer;
signal a0258 : integer;
signal a0259 : integer;
signal a0260 : integer;
signal a0261 : integer;
signal a0262 : integer;
signal a0263 : integer;
signal a0264 : integer;
signal a0265 : integer;
signal a0266 : integer;
signal a0267 : integer;
signal a0268 : integer;
signal a0269 : integer;
signal a0270 : integer;
signal a0271 : integer;
signal a0272 : integer;
signal a0273 : integer;
signal a0274 : integer;
signal a0275 : integer;
signal a0276 : integer;
signal a0277 : integer;
signal a0278 : integer;
signal a0279 : integer;
signal a0280 : integer;
signal a0281 : integer;
signal a0282 : integer;
signal a0283 : integer;
signal a0284 : integer;
signal a0285 : integer;
signal a0286 : integer;
signal a0287 : integer;
signal a0288 : integer;
signal a0289 : integer;
signal a0290 : integer;
signal a0291 : integer;
signal a0292 : integer;
signal a0293 : integer;
signal a0294 : integer;
signal a0295 : integer;
signal a0296 : integer;
signal a0297 : integer;
signal a0298 : integer;
signal a0299 : integer;
signal a0300 : integer;
signal a0301 : integer;
signal a0302 : integer;
signal a0303 : integer;
signal a0304 : integer;
signal a0305 : integer;
signal a0306 : integer;
signal a0307 : integer;
signal a0308 : integer;
signal a0309 : integer;
signal a0310 : integer;
signal a0311 : integer;
signal a0312 : integer;
signal a0313 : integer;
signal a0314 : integer;
signal a0315 : integer;
signal a0316 : integer;
signal a0317 : integer;
signal a0318 : integer;
signal a0319 : integer;
signal a0320 : integer;
signal a0321 : integer;
signal a0322 : integer;
signal a0323 : integer;
signal a0324 : integer;
signal a0325 : integer;
signal a0326 : integer;
signal a0327 : integer;
signal a0328 : integer;
signal a0329 : integer;
signal a0330 : integer;
signal a0331 : integer;
signal a0332 : integer;
signal a0333 : integer;
signal a0334 : integer;
signal a0335 : integer;
signal a0336 : integer;
signal a0337 : integer;
signal a0338 : integer;
signal a0339 : integer;
signal a0340 : integer;
signal a0341 : integer;
signal a0342 : integer;
signal a0343 : integer;
signal a0344 : integer;
signal a0345 : integer;
signal a0346 : integer;
signal a0347 : integer;
signal a0348 : integer;
signal a0349 : integer;
signal a0350 : integer;
signal a0351 : integer;
signal a0352 : integer;
signal a0353 : integer;
signal a0354 : integer;
signal a0355 : integer;
signal a0356 : integer;
signal a0357 : integer;
signal a0358 : integer;
signal a0359 : integer;
signal a0360 : integer;
signal a0361 : integer;
signal a0362 : integer;
signal a0363 : integer;
signal a0364 : integer;
signal a0365 : integer;
signal a0366 : integer;
signal a0367 : integer;
signal a0368 : integer;
signal a0369 : integer;
signal a0370 : integer;
signal a0371 : integer;
signal a0372 : integer;
signal a0373 : integer;
signal a0374 : integer;
signal a0375 : integer;
signal a0376 : integer;
signal a0377 : integer;
signal a0378 : integer;
signal a0379 : integer;
signal a0380 : integer;
signal a0381 : integer;
signal a0382 : integer;
signal a0383 : integer;
signal a0384 : integer;
signal a0385 : integer;
signal a0386 : integer;
signal a0387 : integer;
signal a0388 : integer;
signal a0389 : integer;
signal a0390 : integer;
signal a0391 : integer;
signal a0392 : integer;
signal a0393 : integer;
signal a0394 : integer;
signal a0395 : integer;
signal a0396 : integer;
signal a0397 : integer;
signal a0398 : integer;
signal a0399 : integer;
signal a0400 : integer;
signal a0401 : integer;
signal a0402 : integer;
signal a0403 : integer;
signal a0404 : integer;
signal a0405 : integer;
signal a0406 : integer;
signal a0407 : integer;
signal a0408 : integer;
signal a0409 : integer;
signal a0410 : integer;
signal a0411 : integer;
signal a0412 : integer;
signal a0413 : integer;
signal a0414 : integer;
signal a0415 : integer;
signal a0416 : integer;
signal a0417 : integer;
signal a0418 : integer;
signal a0419 : integer;
signal a0420 : integer;
signal a0421 : integer;
signal a0422 : integer;
signal a0423 : integer;
signal a0424 : integer;
signal a0425 : integer;
signal a0426 : integer;
signal a0427 : integer;
signal a0428 : integer;
signal a0429 : integer;
signal a0430 : integer;
signal a0431 : integer;
signal a0432 : integer;
signal a0433 : integer;
signal a0434 : integer;
signal a0435 : integer;
signal a0436 : integer;
signal a0437 : integer;
signal a0438 : integer;
signal a0439 : integer;
signal a0440 : integer;
signal a0441 : integer;
signal a0442 : integer;
signal a0443 : integer;
signal a0444 : integer;
signal a0445 : integer;
signal a0446 : integer;
signal a0447 : integer;
signal a0448 : integer;
signal a0449 : integer;
signal a0450 : integer;
signal a0451 : integer;
signal a0452 : integer;
signal a0453 : integer;
signal a0454 : integer;
signal a0455 : integer;
signal a0456 : integer;
signal a0457 : integer;
signal a0458 : integer;
signal a0459 : integer;
signal a0460 : integer;
signal a0461 : integer;
signal a0462 : integer;
signal a0463 : integer;
signal a0464 : integer;
signal a0465 : integer;
signal a0466 : integer;
signal a0467 : integer;
signal a0468 : integer;
signal a0469 : integer;
signal a0470 : integer;
signal a0471 : integer;
signal a0472 : integer;
signal a0473 : integer;
signal a0474 : integer;
signal a0475 : integer;
signal a0476 : integer;
signal a0477 : integer;
signal a0478 : integer;
signal a0479 : integer;
signal a0480 : integer;
signal a0481 : integer;
signal a0482 : integer;
signal a0483 : integer;
signal a0484 : integer;
signal a0485 : integer;
signal a0486 : integer;
signal a0487 : integer;
signal a0488 : integer;
signal a0489 : integer;
signal a0490 : integer;
signal a0491 : integer;
signal a0492 : integer;
signal a0493 : integer;
signal a0494 : integer;
signal a0495 : integer;
signal a0496 : integer;
signal a0497 : integer;
signal a0498 : integer;
signal a0499 : integer;
signal a0500 : integer;
signal a0501 : integer;
signal a0502 : integer;
signal a0503 : integer;
signal a0504 : integer;
signal a0505 : integer;
signal a0506 : integer;
signal a0507 : integer;
signal a0508 : integer;
signal a0509 : integer;
signal a0510 : integer;
signal a0511 : integer;
signal a0512 : integer;
signal a0513 : integer;
signal a0514 : integer;
signal a0515 : integer;
signal a0516 : integer;
signal a0517 : integer;
signal a0518 : integer;
signal a0519 : integer;
signal a0520 : integer;
signal a0521 : integer;
signal a0522 : integer;
signal a0523 : integer;
signal a0524 : integer;
signal a0525 : integer;
signal a0526 : integer;
signal a0527 : integer;
signal a0528 : integer;
signal a0529 : integer;
signal a0530 : integer;
signal a0531 : integer;
signal a0532 : integer;
signal a0533 : integer;
signal a0534 : integer;
signal a0535 : integer;
signal a0536 : integer;
signal a0537 : integer;
signal a0538 : integer;
signal a0539 : integer;
signal a0540 : integer;
signal a0541 : integer;
signal a0542 : integer;
signal a0543 : integer;
signal a0544 : integer;
signal a0545 : integer;
signal a0546 : integer;
signal a0547 : integer;
signal a0548 : integer;
signal a0549 : integer;
signal a0550 : integer;
signal a0551 : integer;
signal a0552 : integer;
signal a0553 : integer;
signal a0554 : integer;
signal a0555 : integer;
signal a0556 : integer;
signal a0557 : integer;
signal a0558 : integer;
signal a0559 : integer;
signal a0560 : integer;
signal a0561 : integer;
signal a0562 : integer;
signal a0563 : integer;
signal a0564 : integer;
signal a0565 : integer;
signal a0566 : integer;
signal a0567 : integer;
signal a0568 : integer;
signal a0569 : integer;
signal a0570 : integer;
signal a0571 : integer;
signal a0572 : integer;
signal a0573 : integer;
signal a0574 : integer;
signal a0575 : integer;
signal a0576 : integer;
signal a0577 : integer;
signal a0578 : integer;
signal a0579 : integer;
signal a0580 : integer;
signal a0581 : integer;
signal a0582 : integer;
signal a0583 : integer;
signal a0584 : integer;
signal a0585 : integer;
signal a0586 : integer;
signal a0587 : integer;
signal a0588 : integer;
signal a0589 : integer;
signal a0590 : integer;
signal a0591 : integer;
signal a0592 : integer;
signal a0593 : integer;
signal a0594 : integer;
signal a0595 : integer;
signal a0596 : integer;
signal a0597 : integer;
signal a0598 : integer;
signal a0599 : integer;
signal a0600 : integer;
signal a0601 : integer;
signal a0602 : integer;
signal a0603 : integer;
signal a0604 : integer;
signal a0605 : integer;
signal a0606 : integer;
signal a0607 : integer;
signal a0608 : integer;
signal a0609 : integer;
signal a0610 : integer;
signal a0611 : integer;
signal a0612 : integer;
signal a0613 : integer;
signal a0614 : integer;
signal a0615 : integer;
signal a0616 : integer;
signal a0617 : integer;
signal a0618 : integer;
signal a0619 : integer;
signal a0620 : integer;
signal a0621 : integer;
signal a0622 : integer;
signal a0623 : integer;
signal a0624 : integer;
signal a0625 : integer;
signal a0626 : integer;
signal a0627 : integer;
signal a0628 : integer;
signal a0629 : integer;
signal a0630 : integer;
signal a0631 : integer;
signal a0632 : integer;
signal a0633 : integer;
signal a0634 : integer;
signal a0635 : integer;
signal a0636 : integer;
signal a0637 : integer;
signal a0638 : integer;
signal a0639 : integer;
signal a0640 : integer;
signal a0641 : integer;
signal a0642 : integer;
signal a0643 : integer;
signal a0644 : integer;
signal a0645 : integer;
signal a0646 : integer;
signal a0647 : integer;
signal a0648 : integer;
signal a0649 : integer;
signal a0650 : integer;
signal a0651 : integer;
signal a0652 : integer;
signal a0653 : integer;
signal a0654 : integer;
signal a0655 : integer;
signal a0656 : integer;
signal a0657 : integer;
signal a0658 : integer;
signal a0659 : integer;
signal a0660 : integer;
signal a0661 : integer;
signal a0662 : integer;
signal a0663 : integer;
signal a0664 : integer;
signal a0665 : integer;
signal a0666 : integer;
signal a0667 : integer;
signal a0668 : integer;
signal a0669 : integer;
signal a0670 : integer;
signal a0671 : integer;
signal a0672 : integer;
signal a0673 : integer;
signal a0674 : integer;
signal a0675 : integer;
signal a0676 : integer;
signal a0677 : integer;
signal a0678 : integer;
signal a0679 : integer;
signal a0680 : integer;
signal a0681 : integer;
signal a0682 : integer;
signal a0683 : integer;
signal a0684 : integer;
signal a0685 : integer;
signal a0686 : integer;
signal a0687 : integer;
signal a0688 : integer;
signal a0689 : integer;
signal a0690 : integer;
signal a0691 : integer;
signal a0692 : integer;
signal a0693 : integer;
signal a0694 : integer;
signal a0695 : integer;
signal a0696 : integer;
signal a0697 : integer;
signal a0698 : integer;
signal a0699 : integer;
signal a0700 : integer;
signal a0701 : integer;
signal a0702 : integer;
signal a0703 : integer;
signal a0704 : integer;
signal a0705 : integer;
signal a0706 : integer;
signal a0707 : integer;
signal a0708 : integer;
signal a0709 : integer;
signal a0710 : integer;
signal a0711 : integer;
signal a0712 : integer;
signal a0713 : integer;
signal a0714 : integer;
signal a0715 : integer;
signal a0716 : integer;
signal a0717 : integer;
signal a0718 : integer;
signal a0719 : integer;
signal a0720 : integer;
signal a0721 : integer;
signal a0722 : integer;
signal a0723 : integer;
signal a0724 : integer;
signal a0725 : integer;
signal a0726 : integer;
signal a0727 : integer;
signal a0728 : integer;
signal a0729 : integer;
signal a0730 : integer;
signal a0731 : integer;
signal a0732 : integer;
signal a0733 : integer;
signal a0734 : integer;
signal a0735 : integer;
signal a0736 : integer;
signal a0737 : integer;
signal a0738 : integer;
signal a0739 : integer;
signal a0740 : integer;
signal a0741 : integer;
signal a0742 : integer;
signal a0743 : integer;
signal a0744 : integer;
signal a0745 : integer;
signal a0746 : integer;
signal a0747 : integer;
signal a0748 : integer;
signal a0749 : integer;
signal a0750 : integer;
signal a0751 : integer;
signal a0752 : integer;
signal a0753 : integer;
signal a0754 : integer;
signal a0755 : integer;
signal a0756 : integer;
signal a0757 : integer;
signal a0758 : integer;
signal a0759 : integer;
signal a0760 : integer;
signal a0761 : integer;
signal a0762 : integer;
signal a0763 : integer;
signal a0764 : integer;
signal a0765 : integer;
signal a0766 : integer;
signal a0767 : integer;
signal a0768 : integer;
signal a0769 : integer;
signal a0770 : integer;
signal a0771 : integer;
signal a0772 : integer;
signal a0773 : integer;
signal a0774 : integer;
signal a0775 : integer;
signal a0776 : integer;
signal a0777 : integer;
signal a0778 : integer;
signal a0779 : integer;
signal a0780 : integer;
signal a0781 : integer;
signal a0782 : integer;
signal a0783 : integer;
signal a0784 : integer;
signal a0785 : integer;
signal a0786 : integer;
signal a0787 : integer;
signal a0788 : integer;
signal a0789 : integer;
signal a0790 : integer;
signal a0791 : integer;
signal a0792 : integer;
signal a0793 : integer;
signal a0794 : integer;
signal a0795 : integer;
signal a0796 : integer;
signal a0797 : integer;
signal a0798 : integer;
signal a0799 : integer;
signal a0800 : integer;
signal a0801 : integer;
signal a0802 : integer;
signal a0803 : integer;
signal a0804 : integer;
signal a0805 : integer;
signal a0806 : integer;
signal a0807 : integer;
signal a0808 : integer;
signal a0809 : integer;
signal a0810 : integer;
signal a0811 : integer;
signal a0812 : integer;
signal a0813 : integer;
signal a0814 : integer;
signal a0815 : integer;
signal a0816 : integer;
signal a0817 : integer;
signal a0818 : integer;
signal a0819 : integer;
signal a0820 : integer;
signal a0821 : integer;
signal a0822 : integer;
signal a0823 : integer;
signal a0824 : integer;
signal a0825 : integer;
signal a0826 : integer;
signal a0827 : integer;
signal a0828 : integer;
signal a0829 : integer;
signal a0830 : integer;
signal a0831 : integer;
signal a0832 : integer;
signal a0833 : integer;
signal a0834 : integer;
signal a0835 : integer;
signal a0836 : integer;
signal a0837 : integer;
signal a0838 : integer;
signal a0839 : integer;
signal a0840 : integer;
signal a0841 : integer;
signal a0842 : integer;
signal a0843 : integer;
signal a0844 : integer;
signal a0845 : integer;
signal a0846 : integer;
signal a0847 : integer;
signal a0848 : integer;
signal a0849 : integer;
signal a0850 : integer;
signal a0851 : integer;
signal a0852 : integer;
signal a0853 : integer;
signal a0854 : integer;
signal a0855 : integer;
signal a0856 : integer;
signal a0857 : integer;
signal a0858 : integer;
signal a0859 : integer;
signal a0860 : integer;
signal a0861 : integer;
signal a0862 : integer;
signal a0863 : integer;
signal a0864 : integer;
signal a0865 : integer;
signal a0866 : integer;
signal a0867 : integer;
signal a0868 : integer;
signal a0869 : integer;
signal a0870 : integer;
signal a0871 : integer;
signal a0872 : integer;
signal a0873 : integer;
signal a0874 : integer;
signal a0875 : integer;
signal a0876 : integer;
signal a0877 : integer;
signal a0878 : integer;
signal a0879 : integer;
signal a0880 : integer;
signal a0881 : integer;
signal a0882 : integer;
signal a0883 : integer;
signal a0884 : integer;
signal a0885 : integer;
signal a0886 : integer;
signal a0887 : integer;
signal a0888 : integer;
signal a0889 : integer;
signal a0890 : integer;
signal a0891 : integer;
signal a0892 : integer;
signal a0893 : integer;
signal a0894 : integer;
signal a0895 : integer;
signal a0896 : integer;
signal a0897 : integer;
signal a0898 : integer;
signal a0899 : integer;
signal a0900 : integer;
signal a0901 : integer;
signal a0902 : integer;
signal a0903 : integer;
signal a0904 : integer;
signal a0905 : integer;
signal a0906 : integer;
signal a0907 : integer;
signal a0908 : integer;
signal a0909 : integer;
signal a0910 : integer;
signal a0911 : integer;
signal a0912 : integer;
signal a0913 : integer;
signal a0914 : integer;
signal a0915 : integer;
signal a0916 : integer;
signal a0917 : integer;
signal a0918 : integer;
signal a0919 : integer;
signal a0920 : integer;
signal a0921 : integer;
signal a0922 : integer;
signal a0923 : integer;
signal a0924 : integer;
signal a0925 : integer;
signal a0926 : integer;
signal a0927 : integer;
signal a0928 : integer;
signal a0929 : integer;
signal a0930 : integer;
signal a0931 : integer;
signal a0932 : integer;
signal a0933 : integer;
signal a0934 : integer;
signal a0935 : integer;
signal a0936 : integer;
signal a0937 : integer;
signal a0938 : integer;
signal a0939 : integer;
signal a0940 : integer;
signal a0941 : integer;
signal a0942 : integer;
signal a0943 : integer;
signal a0944 : integer;
signal a0945 : integer;
signal a0946 : integer;
signal a0947 : integer;
signal a0948 : integer;
signal a0949 : integer;
signal a0950 : integer;
signal a0951 : integer;
signal a0952 : integer;
signal a0953 : integer;
signal a0954 : integer;
signal a0955 : integer;
signal a0956 : integer;
signal a0957 : integer;
signal a0958 : integer;
signal a0959 : integer;
signal a0960 : integer;
signal a0961 : integer;
signal a0962 : integer;
signal a0963 : integer;
signal a0964 : integer;
signal a0965 : integer;
signal a0966 : integer;
signal a0967 : integer;
signal a0968 : integer;
signal a0969 : integer;
signal a0970 : integer;
signal a0971 : integer;
signal a0972 : integer;
signal a0973 : integer;
signal a0974 : integer;
signal a0975 : integer;
signal a0976 : integer;
signal a0977 : integer;
signal a0978 : integer;
signal a0979 : integer;
signal a0980 : integer;
signal a0981 : integer;
signal a0982 : integer;
signal a0983 : integer;
signal a0984 : integer;
signal a0985 : integer;
signal a0986 : integer;
signal a0987 : integer;
signal a0988 : integer;
signal a0989 : integer;
signal a0990 : integer;
signal a0991 : integer;
signal a0992 : integer;
signal a0993 : integer;
signal a0994 : integer;
signal a0995 : integer;
signal a0996 : integer;
signal a0997 : integer;
signal a0998 : integer;
signal a0999 : integer;
signal a1000 : integer;
-- }}}
begin
main: process(clk)
--{{{
begin
a0001 <= clk;
a0002 <= clk;
a0003 <= clk;
a0004 <= clk;
a0005 <= clk;
a0006 <= clk;
a0007 <= clk;
a0008 <= clk;
a0009 <= clk;
a0010 <= clk;
a0011 <= clk;
a0012 <= clk;
a0013 <= clk;
a0014 <= clk;
a0015 <= clk;
a0016 <= clk;
a0017 <= clk;
a0018 <= clk;
a0019 <= clk;
a0020 <= clk;
a0021 <= clk;
a0022 <= clk;
a0023 <= clk;
a0024 <= clk;
a0025 <= clk;
a0026 <= clk;
a0027 <= clk;
a0028 <= clk;
a0029 <= clk;
a0030 <= clk;
a0031 <= clk;
a0032 <= clk;
a0033 <= clk;
a0034 <= clk;
a0035 <= clk;
a0036 <= clk;
a0037 <= clk;
a0038 <= clk;
a0039 <= clk;
a0040 <= clk;
a0041 <= clk;
a0042 <= clk;
a0043 <= clk;
a0044 <= clk;
a0045 <= clk;
a0046 <= clk;
a0047 <= clk;
a0048 <= clk;
a0049 <= clk;
a0050 <= clk;
a0051 <= clk;
a0052 <= clk;
a0053 <= clk;
a0054 <= clk;
a0055 <= clk;
a0056 <= clk;
a0057 <= clk;
a0058 <= clk;
a0059 <= clk;
a0060 <= clk;
a0061 <= clk;
a0062 <= clk;
a0063 <= clk;
a0064 <= clk;
a0065 <= clk;
a0066 <= clk;
a0067 <= clk;
a0068 <= clk;
a0069 <= clk;
a0070 <= clk;
a0071 <= clk;
a0072 <= clk;
a0073 <= clk;
a0074 <= clk;
a0075 <= clk;
a0076 <= clk;
a0077 <= clk;
a0078 <= clk;
a0079 <= clk;
a0080 <= clk;
a0081 <= clk;
a0082 <= clk;
a0083 <= clk;
a0084 <= clk;
a0085 <= clk;
a0086 <= clk;
a0087 <= clk;
a0088 <= clk;
a0089 <= clk;
a0090 <= clk;
a0091 <= clk;
a0092 <= clk;
a0093 <= clk;
a0094 <= clk;
a0095 <= clk;
a0096 <= clk;
a0097 <= clk;
a0098 <= clk;
a0099 <= clk;
a0100 <= clk;
a0101 <= clk;
a0102 <= clk;
a0103 <= clk;
a0104 <= clk;
a0105 <= clk;
a0106 <= clk;
a0107 <= clk;
a0108 <= clk;
a0109 <= clk;
a0110 <= clk;
a0111 <= clk;
a0112 <= clk;
a0113 <= clk;
a0114 <= clk;
a0115 <= clk;
a0116 <= clk;
a0117 <= clk;
a0118 <= clk;
a0119 <= clk;
a0120 <= clk;
a0121 <= clk;
a0122 <= clk;
a0123 <= clk;
a0124 <= clk;
a0125 <= clk;
a0126 <= clk;
a0127 <= clk;
a0128 <= clk;
a0129 <= clk;
a0130 <= clk;
a0131 <= clk;
a0132 <= clk;
a0133 <= clk;
a0134 <= clk;
a0135 <= clk;
a0136 <= clk;
a0137 <= clk;
a0138 <= clk;
a0139 <= clk;
a0140 <= clk;
a0141 <= clk;
a0142 <= clk;
a0143 <= clk;
a0144 <= clk;
a0145 <= clk;
a0146 <= clk;
a0147 <= clk;
a0148 <= clk;
a0149 <= clk;
a0150 <= clk;
a0151 <= clk;
a0152 <= clk;
a0153 <= clk;
a0154 <= clk;
a0155 <= clk;
a0156 <= clk;
a0157 <= clk;
a0158 <= clk;
a0159 <= clk;
a0160 <= clk;
a0161 <= clk;
a0162 <= clk;
a0163 <= clk;
a0164 <= clk;
a0165 <= clk;
a0166 <= clk;
a0167 <= clk;
a0168 <= clk;
a0169 <= clk;
a0170 <= clk;
a0171 <= clk;
a0172 <= clk;
a0173 <= clk;
a0174 <= clk;
a0175 <= clk;
a0176 <= clk;
a0177 <= clk;
a0178 <= clk;
a0179 <= clk;
a0180 <= clk;
a0181 <= clk;
a0182 <= clk;
a0183 <= clk;
a0184 <= clk;
a0185 <= clk;
a0186 <= clk;
a0187 <= clk;
a0188 <= clk;
a0189 <= clk;
a0190 <= clk;
a0191 <= clk;
a0192 <= clk;
a0193 <= clk;
a0194 <= clk;
a0195 <= clk;
a0196 <= clk;
a0197 <= clk;
a0198 <= clk;
a0199 <= clk;
a0200 <= clk;
a0201 <= clk;
a0202 <= clk;
a0203 <= clk;
a0204 <= clk;
a0205 <= clk;
a0206 <= clk;
a0207 <= clk;
a0208 <= clk;
a0209 <= clk;
a0210 <= clk;
a0211 <= clk;
a0212 <= clk;
a0213 <= clk;
a0214 <= clk;
a0215 <= clk;
a0216 <= clk;
a0217 <= clk;
a0218 <= clk;
a0219 <= clk;
a0220 <= clk;
a0221 <= clk;
a0222 <= clk;
a0223 <= clk;
a0224 <= clk;
a0225 <= clk;
a0226 <= clk;
a0227 <= clk;
a0228 <= clk;
a0229 <= clk;
a0230 <= clk;
a0231 <= clk;
a0232 <= clk;
a0233 <= clk;
a0234 <= clk;
a0235 <= clk;
a0236 <= clk;
a0237 <= clk;
a0238 <= clk;
a0239 <= clk;
a0240 <= clk;
a0241 <= clk;
a0242 <= clk;
a0243 <= clk;
a0244 <= clk;
a0245 <= clk;
a0246 <= clk;
a0247 <= clk;
a0248 <= clk;
a0249 <= clk;
a0250 <= clk;
a0251 <= clk;
a0252 <= clk;
a0253 <= clk;
a0254 <= clk;
a0255 <= clk;
a0256 <= clk;
a0257 <= clk;
a0258 <= clk;
a0259 <= clk;
a0260 <= clk;
a0261 <= clk;
a0262 <= clk;
a0263 <= clk;
a0264 <= clk;
a0265 <= clk;
a0266 <= clk;
a0267 <= clk;
a0268 <= clk;
a0269 <= clk;
a0270 <= clk;
a0271 <= clk;
a0272 <= clk;
a0273 <= clk;
a0274 <= clk;
a0275 <= clk;
a0276 <= clk;
a0277 <= clk;
a0278 <= clk;
a0279 <= clk;
a0280 <= clk;
a0281 <= clk;
a0282 <= clk;
a0283 <= clk;
a0284 <= clk;
a0285 <= clk;
a0286 <= clk;
a0287 <= clk;
a0288 <= clk;
a0289 <= clk;
a0290 <= clk;
a0291 <= clk;
a0292 <= clk;
a0293 <= clk;
a0294 <= clk;
a0295 <= clk;
a0296 <= clk;
a0297 <= clk;
a0298 <= clk;
a0299 <= clk;
a0300 <= clk;
a0301 <= clk;
a0302 <= clk;
a0303 <= clk;
a0304 <= clk;
a0305 <= clk;
a0306 <= clk;
a0307 <= clk;
a0308 <= clk;
a0309 <= clk;
a0310 <= clk;
a0311 <= clk;
a0312 <= clk;
a0313 <= clk;
a0314 <= clk;
a0315 <= clk;
a0316 <= clk;
a0317 <= clk;
a0318 <= clk;
a0319 <= clk;
a0320 <= clk;
a0321 <= clk;
a0322 <= clk;
a0323 <= clk;
a0324 <= clk;
a0325 <= clk;
a0326 <= clk;
a0327 <= clk;
a0328 <= clk;
a0329 <= clk;
a0330 <= clk;
a0331 <= clk;
a0332 <= clk;
a0333 <= clk;
a0334 <= clk;
a0335 <= clk;
a0336 <= clk;
a0337 <= clk;
a0338 <= clk;
a0339 <= clk;
a0340 <= clk;
a0341 <= clk;
a0342 <= clk;
a0343 <= clk;
a0344 <= clk;
a0345 <= clk;
a0346 <= clk;
a0347 <= clk;
a0348 <= clk;
a0349 <= clk;
a0350 <= clk;
a0351 <= clk;
a0352 <= clk;
a0353 <= clk;
a0354 <= clk;
a0355 <= clk;
a0356 <= clk;
a0357 <= clk;
a0358 <= clk;
a0359 <= clk;
a0360 <= clk;
a0361 <= clk;
a0362 <= clk;
a0363 <= clk;
a0364 <= clk;
a0365 <= clk;
a0366 <= clk;
a0367 <= clk;
a0368 <= clk;
a0369 <= clk;
a0370 <= clk;
a0371 <= clk;
a0372 <= clk;
a0373 <= clk;
a0374 <= clk;
a0375 <= clk;
a0376 <= clk;
a0377 <= clk;
a0378 <= clk;
a0379 <= clk;
a0380 <= clk;
a0381 <= clk;
a0382 <= clk;
a0383 <= clk;
a0384 <= clk;
a0385 <= clk;
a0386 <= clk;
a0387 <= clk;
a0388 <= clk;
a0389 <= clk;
a0390 <= clk;
a0391 <= clk;
a0392 <= clk;
a0393 <= clk;
a0394 <= clk;
a0395 <= clk;
a0396 <= clk;
a0397 <= clk;
a0398 <= clk;
a0399 <= clk;
a0400 <= clk;
a0401 <= clk;
a0402 <= clk;
a0403 <= clk;
a0404 <= clk;
a0405 <= clk;
a0406 <= clk;
a0407 <= clk;
a0408 <= clk;
a0409 <= clk;
a0410 <= clk;
a0411 <= clk;
a0412 <= clk;
a0413 <= clk;
a0414 <= clk;
a0415 <= clk;
a0416 <= clk;
a0417 <= clk;
a0418 <= clk;
a0419 <= clk;
a0420 <= clk;
a0421 <= clk;
a0422 <= clk;
a0423 <= clk;
a0424 <= clk;
a0425 <= clk;
a0426 <= clk;
a0427 <= clk;
a0428 <= clk;
a0429 <= clk;
a0430 <= clk;
a0431 <= clk;
a0432 <= clk;
a0433 <= clk;
a0434 <= clk;
a0435 <= clk;
a0436 <= clk;
a0437 <= clk;
a0438 <= clk;
a0439 <= clk;
a0440 <= clk;
a0441 <= clk;
a0442 <= clk;
a0443 <= clk;
a0444 <= clk;
a0445 <= clk;
a0446 <= clk;
a0447 <= clk;
a0448 <= clk;
a0449 <= clk;
a0450 <= clk;
a0451 <= clk;
a0452 <= clk;
a0453 <= clk;
a0454 <= clk;
a0455 <= clk;
a0456 <= clk;
a0457 <= clk;
a0458 <= clk;
a0459 <= clk;
a0460 <= clk;
a0461 <= clk;
a0462 <= clk;
a0463 <= clk;
a0464 <= clk;
a0465 <= clk;
a0466 <= clk;
a0467 <= clk;
a0468 <= clk;
a0469 <= clk;
a0470 <= clk;
a0471 <= clk;
a0472 <= clk;
a0473 <= clk;
a0474 <= clk;
a0475 <= clk;
a0476 <= clk;
a0477 <= clk;
a0478 <= clk;
a0479 <= clk;
a0480 <= clk;
a0481 <= clk;
a0482 <= clk;
a0483 <= clk;
a0484 <= clk;
a0485 <= clk;
a0486 <= clk;
a0487 <= clk;
a0488 <= clk;
a0489 <= clk;
a0490 <= clk;
a0491 <= clk;
a0492 <= clk;
a0493 <= clk;
a0494 <= clk;
a0495 <= clk;
a0496 <= clk;
a0497 <= clk;
a0498 <= clk;
a0499 <= clk;
a0500 <= clk;
a0501 <= clk;
a0502 <= clk;
a0503 <= clk;
a0504 <= clk;
a0505 <= clk;
a0506 <= clk;
a0507 <= clk;
a0508 <= clk;
a0509 <= clk;
a0510 <= clk;
a0511 <= clk;
a0512 <= clk;
a0513 <= clk;
a0514 <= clk;
a0515 <= clk;
a0516 <= clk;
a0517 <= clk;
a0518 <= clk;
a0519 <= clk;
a0520 <= clk;
a0521 <= clk;
a0522 <= clk;
a0523 <= clk;
a0524 <= clk;
a0525 <= clk;
a0526 <= clk;
a0527 <= clk;
a0528 <= clk;
a0529 <= clk;
a0530 <= clk;
a0531 <= clk;
a0532 <= clk;
a0533 <= clk;
a0534 <= clk;
a0535 <= clk;
a0536 <= clk;
a0537 <= clk;
a0538 <= clk;
a0539 <= clk;
a0540 <= clk;
a0541 <= clk;
a0542 <= clk;
a0543 <= clk;
a0544 <= clk;
a0545 <= clk;
a0546 <= clk;
a0547 <= clk;
a0548 <= clk;
a0549 <= clk;
a0550 <= clk;
a0551 <= clk;
a0552 <= clk;
a0553 <= clk;
a0554 <= clk;
a0555 <= clk;
a0556 <= clk;
a0557 <= clk;
a0558 <= clk;
a0559 <= clk;
a0560 <= clk;
a0561 <= clk;
a0562 <= clk;
a0563 <= clk;
a0564 <= clk;
a0565 <= clk;
a0566 <= clk;
a0567 <= clk;
a0568 <= clk;
a0569 <= clk;
a0570 <= clk;
a0571 <= clk;
a0572 <= clk;
a0573 <= clk;
a0574 <= clk;
a0575 <= clk;
a0576 <= clk;
a0577 <= clk;
a0578 <= clk;
a0579 <= clk;
a0580 <= clk;
a0581 <= clk;
a0582 <= clk;
a0583 <= clk;
a0584 <= clk;
a0585 <= clk;
a0586 <= clk;
a0587 <= clk;
a0588 <= clk;
a0589 <= clk;
a0590 <= clk;
a0591 <= clk;
a0592 <= clk;
a0593 <= clk;
a0594 <= clk;
a0595 <= clk;
a0596 <= clk;
a0597 <= clk;
a0598 <= clk;
a0599 <= clk;
a0600 <= clk;
a0601 <= clk;
a0602 <= clk;
a0603 <= clk;
a0604 <= clk;
a0605 <= clk;
a0606 <= clk;
a0607 <= clk;
a0608 <= clk;
a0609 <= clk;
a0610 <= clk;
a0611 <= clk;
a0612 <= clk;
a0613 <= clk;
a0614 <= clk;
a0615 <= clk;
a0616 <= clk;
a0617 <= clk;
a0618 <= clk;
a0619 <= clk;
a0620 <= clk;
a0621 <= clk;
a0622 <= clk;
a0623 <= clk;
a0624 <= clk;
a0625 <= clk;
a0626 <= clk;
a0627 <= clk;
a0628 <= clk;
a0629 <= clk;
a0630 <= clk;
a0631 <= clk;
a0632 <= clk;
a0633 <= clk;
a0634 <= clk;
a0635 <= clk;
a0636 <= clk;
a0637 <= clk;
a0638 <= clk;
a0639 <= clk;
a0640 <= clk;
a0641 <= clk;
a0642 <= clk;
a0643 <= clk;
a0644 <= clk;
a0645 <= clk;
a0646 <= clk;
a0647 <= clk;
a0648 <= clk;
a0649 <= clk;
a0650 <= clk;
a0651 <= clk;
a0652 <= clk;
a0653 <= clk;
a0654 <= clk;
a0655 <= clk;
a0656 <= clk;
a0657 <= clk;
a0658 <= clk;
a0659 <= clk;
a0660 <= clk;
a0661 <= clk;
a0662 <= clk;
a0663 <= clk;
a0664 <= clk;
a0665 <= clk;
a0666 <= clk;
a0667 <= clk;
a0668 <= clk;
a0669 <= clk;
a0670 <= clk;
a0671 <= clk;
a0672 <= clk;
a0673 <= clk;
a0674 <= clk;
a0675 <= clk;
a0676 <= clk;
a0677 <= clk;
a0678 <= clk;
a0679 <= clk;
a0680 <= clk;
a0681 <= clk;
a0682 <= clk;
a0683 <= clk;
a0684 <= clk;
a0685 <= clk;
a0686 <= clk;
a0687 <= clk;
a0688 <= clk;
a0689 <= clk;
a0690 <= clk;
a0691 <= clk;
a0692 <= clk;
a0693 <= clk;
a0694 <= clk;
a0695 <= clk;
a0696 <= clk;
a0697 <= clk;
a0698 <= clk;
a0699 <= clk;
a0700 <= clk;
a0701 <= clk;
a0702 <= clk;
a0703 <= clk;
a0704 <= clk;
a0705 <= clk;
a0706 <= clk;
a0707 <= clk;
a0708 <= clk;
a0709 <= clk;
a0710 <= clk;
a0711 <= clk;
a0712 <= clk;
a0713 <= clk;
a0714 <= clk;
a0715 <= clk;
a0716 <= clk;
a0717 <= clk;
a0718 <= clk;
a0719 <= clk;
a0720 <= clk;
a0721 <= clk;
a0722 <= clk;
a0723 <= clk;
a0724 <= clk;
a0725 <= clk;
a0726 <= clk;
a0727 <= clk;
a0728 <= clk;
a0729 <= clk;
a0730 <= clk;
a0731 <= clk;
a0732 <= clk;
a0733 <= clk;
a0734 <= clk;
a0735 <= clk;
a0736 <= clk;
a0737 <= clk;
a0738 <= clk;
a0739 <= clk;
a0740 <= clk;
a0741 <= clk;
a0742 <= clk;
a0743 <= clk;
a0744 <= clk;
a0745 <= clk;
a0746 <= clk;
a0747 <= clk;
a0748 <= clk;
a0749 <= clk;
a0750 <= clk;
a0751 <= clk;
a0752 <= clk;
a0753 <= clk;
a0754 <= clk;
a0755 <= clk;
a0756 <= clk;
a0757 <= clk;
a0758 <= clk;
a0759 <= clk;
a0760 <= clk;
a0761 <= clk;
a0762 <= clk;
a0763 <= clk;
a0764 <= clk;
a0765 <= clk;
a0766 <= clk;
a0767 <= clk;
a0768 <= clk;
a0769 <= clk;
a0770 <= clk;
a0771 <= clk;
a0772 <= clk;
a0773 <= clk;
a0774 <= clk;
a0775 <= clk;
a0776 <= clk;
a0777 <= clk;
a0778 <= clk;
a0779 <= clk;
a0780 <= clk;
a0781 <= clk;
a0782 <= clk;
a0783 <= clk;
a0784 <= clk;
a0785 <= clk;
a0786 <= clk;
a0787 <= clk;
a0788 <= clk;
a0789 <= clk;
a0790 <= clk;
a0791 <= clk;
a0792 <= clk;
a0793 <= clk;
a0794 <= clk;
a0795 <= clk;
a0796 <= clk;
a0797 <= clk;
a0798 <= clk;
a0799 <= clk;
a0800 <= clk;
a0801 <= clk;
a0802 <= clk;
a0803 <= clk;
a0804 <= clk;
a0805 <= clk;
a0806 <= clk;
a0807 <= clk;
a0808 <= clk;
a0809 <= clk;
a0810 <= clk;
a0811 <= clk;
a0812 <= clk;
a0813 <= clk;
a0814 <= clk;
a0815 <= clk;
a0816 <= clk;
a0817 <= clk;
a0818 <= clk;
a0819 <= clk;
a0820 <= clk;
a0821 <= clk;
a0822 <= clk;
a0823 <= clk;
a0824 <= clk;
a0825 <= clk;
a0826 <= clk;
a0827 <= clk;
a0828 <= clk;
a0829 <= clk;
a0830 <= clk;
a0831 <= clk;
a0832 <= clk;
a0833 <= clk;
a0834 <= clk;
a0835 <= clk;
a0836 <= clk;
a0837 <= clk;
a0838 <= clk;
a0839 <= clk;
a0840 <= clk;
a0841 <= clk;
a0842 <= clk;
a0843 <= clk;
a0844 <= clk;
a0845 <= clk;
a0846 <= clk;
a0847 <= clk;
a0848 <= clk;
a0849 <= clk;
a0850 <= clk;
a0851 <= clk;
a0852 <= clk;
a0853 <= clk;
a0854 <= clk;
a0855 <= clk;
a0856 <= clk;
a0857 <= clk;
a0858 <= clk;
a0859 <= clk;
a0860 <= clk;
a0861 <= clk;
a0862 <= clk;
a0863 <= clk;
a0864 <= clk;
a0865 <= clk;
a0866 <= clk;
a0867 <= clk;
a0868 <= clk;
a0869 <= clk;
a0870 <= clk;
a0871 <= clk;
a0872 <= clk;
a0873 <= clk;
a0874 <= clk;
a0875 <= clk;
a0876 <= clk;
a0877 <= clk;
a0878 <= clk;
a0879 <= clk;
a0880 <= clk;
a0881 <= clk;
a0882 <= clk;
a0883 <= clk;
a0884 <= clk;
a0885 <= clk;
a0886 <= clk;
a0887 <= clk;
a0888 <= clk;
a0889 <= clk;
a0890 <= clk;
a0891 <= clk;
a0892 <= clk;
a0893 <= clk;
a0894 <= clk;
a0895 <= clk;
a0896 <= clk;
a0897 <= clk;
a0898 <= clk;
a0899 <= clk;
a0900 <= clk;
a0901 <= clk;
a0902 <= clk;
a0903 <= clk;
a0904 <= clk;
a0905 <= clk;
a0906 <= clk;
a0907 <= clk;
a0908 <= clk;
a0909 <= clk;
a0910 <= clk;
a0911 <= clk;
a0912 <= clk;
a0913 <= clk;
a0914 <= clk;
a0915 <= clk;
a0916 <= clk;
a0917 <= clk;
a0918 <= clk;
a0919 <= clk;
a0920 <= clk;
a0921 <= clk;
a0922 <= clk;
a0923 <= clk;
a0924 <= clk;
a0925 <= clk;
a0926 <= clk;
a0927 <= clk;
a0928 <= clk;
a0929 <= clk;
a0930 <= clk;
a0931 <= clk;
a0932 <= clk;
a0933 <= clk;
a0934 <= clk;
a0935 <= clk;
a0936 <= clk;
a0937 <= clk;
a0938 <= clk;
a0939 <= clk;
a0940 <= clk;
a0941 <= clk;
a0942 <= clk;
a0943 <= clk;
a0944 <= clk;
a0945 <= clk;
a0946 <= clk;
a0947 <= clk;
a0948 <= clk;
a0949 <= clk;
a0950 <= clk;
a0951 <= clk;
a0952 <= clk;
a0953 <= clk;
a0954 <= clk;
a0955 <= clk;
a0956 <= clk;
a0957 <= clk;
a0958 <= clk;
a0959 <= clk;
a0960 <= clk;
a0961 <= clk;
a0962 <= clk;
a0963 <= clk;
a0964 <= clk;
a0965 <= clk;
a0966 <= clk;
a0967 <= clk;
a0968 <= clk;
a0969 <= clk;
a0970 <= clk;
a0971 <= clk;
a0972 <= clk;
a0973 <= clk;
a0974 <= clk;
a0975 <= clk;
a0976 <= clk;
a0977 <= clk;
a0978 <= clk;
a0979 <= clk;
a0980 <= clk;
a0981 <= clk;
a0982 <= clk;
a0983 <= clk;
a0984 <= clk;
a0985 <= clk;
a0986 <= clk;
a0987 <= clk;
a0988 <= clk;
a0989 <= clk;
a0990 <= clk;
a0991 <= clk;
a0992 <= clk;
a0993 <= clk;
a0994 <= clk;
a0995 <= clk;
a0996 <= clk;
a0997 <= clk;
a0998 <= clk;
a0999 <= clk;
a1000 <= clk;
report "tick";
--}}}
end process;
terminator : process(clk)
begin
if clk >= CYCLES then
assert false report "end of simulation" severity failure;
-- else
-- report "tick";
end if;
end process;
clk <= (clk+1) after 1 us;
end;
|
entity args is
end entity;
architecture a of args is
function func(x, y : in integer) return integer is
begin
return x + y;
end function;
procedure proc(x, y : in integer) is
begin
end procedure;
begin
process is
variable a, b, c : integer;
begin
c := func(x => a, y => b);
c := func(a, y => b);
c := func(y => b, x => a);
proc(y => b, x => a);
end process;
end architecture;
|
entity args is
end entity;
architecture a of args is
function func(x, y : in integer) return integer is
begin
return x + y;
end function;
procedure proc(x, y : in integer) is
begin
end procedure;
begin
process is
variable a, b, c : integer;
begin
c := func(x => a, y => b);
c := func(a, y => b);
c := func(y => b, x => a);
proc(y => b, x => a);
end process;
end architecture;
|
entity args is
end entity;
architecture a of args is
function func(x, y : in integer) return integer is
begin
return x + y;
end function;
procedure proc(x, y : in integer) is
begin
end procedure;
begin
process is
variable a, b, c : integer;
begin
c := func(x => a, y => b);
c := func(a, y => b);
c := func(y => b, x => a);
proc(y => b, x => a);
end process;
end architecture;
|
entity args is
end entity;
architecture a of args is
function func(x, y : in integer) return integer is
begin
return x + y;
end function;
procedure proc(x, y : in integer) is
begin
end procedure;
begin
process is
variable a, b, c : integer;
begin
c := func(x => a, y => b);
c := func(a, y => b);
c := func(y => b, x => a);
proc(y => b, x => a);
end process;
end architecture;
|
entity args is
end entity;
architecture a of args is
function func(x, y : in integer) return integer is
begin
return x + y;
end function;
procedure proc(x, y : in integer) is
begin
end procedure;
begin
process is
variable a, b, c : integer;
begin
c := func(x => a, y => b);
c := func(a, y => b);
c := func(y => b, x => a);
proc(y => b, x => a);
end process;
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3064.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s03b02x02p05n01i03064ent IS
port(con : in BIT := '1'; clk : out BIT);
END c12s03b02x02p05n01i03064ent;
ARCHITECTURE c12s03b02x02p05n01i03064arch OF c12s03b02x02p05n01i03064ent IS
BEGIN
TESTING: PROCESS
begin
clk <= con;
wait;
END PROCESS TESTING;
END c12s03b02x02p05n01i03064arch_a;
ENTITY c12s03b02x02p05n01i03064ent IS
port (C : out bit);
END c12s03b02x02p05n01i03064ent;
ARCHITECTURE c12s03b02x02p05n01i03064arch OF c12s03b02x02p05n01i03064ent IS
component c12s03b02x02p05n01i03064ent_aa
port(con : in bit:='1'; clk : out bit);
end component;
for all: c12s03b02x02p05n01i03064ent_aa use entity work.fail(c12s03b02x02p05n01i03064arch_a); -- Failure_here
BEGIN
T1: test port map(open,C);
TESTING: PROCESS
BEGIN
assert FAILED
report "***FAILED TEST: c12s03b02x02p05n01i03064 - Entity declaration and the corresponding body implied by the binding indication do not exist within the specified library."
severity ERROR;
wait;
END PROCESS TESTING;
END c12s03b02x02p05n01i03064arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3064.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s03b02x02p05n01i03064ent IS
port(con : in BIT := '1'; clk : out BIT);
END c12s03b02x02p05n01i03064ent;
ARCHITECTURE c12s03b02x02p05n01i03064arch OF c12s03b02x02p05n01i03064ent IS
BEGIN
TESTING: PROCESS
begin
clk <= con;
wait;
END PROCESS TESTING;
END c12s03b02x02p05n01i03064arch_a;
ENTITY c12s03b02x02p05n01i03064ent IS
port (C : out bit);
END c12s03b02x02p05n01i03064ent;
ARCHITECTURE c12s03b02x02p05n01i03064arch OF c12s03b02x02p05n01i03064ent IS
component c12s03b02x02p05n01i03064ent_aa
port(con : in bit:='1'; clk : out bit);
end component;
for all: c12s03b02x02p05n01i03064ent_aa use entity work.fail(c12s03b02x02p05n01i03064arch_a); -- Failure_here
BEGIN
T1: test port map(open,C);
TESTING: PROCESS
BEGIN
assert FAILED
report "***FAILED TEST: c12s03b02x02p05n01i03064 - Entity declaration and the corresponding body implied by the binding indication do not exist within the specified library."
severity ERROR;
wait;
END PROCESS TESTING;
END c12s03b02x02p05n01i03064arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3064.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s03b02x02p05n01i03064ent IS
port(con : in BIT := '1'; clk : out BIT);
END c12s03b02x02p05n01i03064ent;
ARCHITECTURE c12s03b02x02p05n01i03064arch OF c12s03b02x02p05n01i03064ent IS
BEGIN
TESTING: PROCESS
begin
clk <= con;
wait;
END PROCESS TESTING;
END c12s03b02x02p05n01i03064arch_a;
ENTITY c12s03b02x02p05n01i03064ent IS
port (C : out bit);
END c12s03b02x02p05n01i03064ent;
ARCHITECTURE c12s03b02x02p05n01i03064arch OF c12s03b02x02p05n01i03064ent IS
component c12s03b02x02p05n01i03064ent_aa
port(con : in bit:='1'; clk : out bit);
end component;
for all: c12s03b02x02p05n01i03064ent_aa use entity work.fail(c12s03b02x02p05n01i03064arch_a); -- Failure_here
BEGIN
T1: test port map(open,C);
TESTING: PROCESS
BEGIN
assert FAILED
report "***FAILED TEST: c12s03b02x02p05n01i03064 - Entity declaration and the corresponding body implied by the binding indication do not exist within the specified library."
severity ERROR;
wait;
END PROCESS TESTING;
END c12s03b02x02p05n01i03064arch;
|
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.ALL;
entity cpu_writeback is
port (regwrite : in std_logic;
memtoreg : in std_logic;
aluout : in std_logic_vector(31 downto 0);
readdata : in std_logic_vector(31 downto 0);
writereg : in std_logic_vector(4 downto 0);
writereg_n : out std_logic_vector(4 downto 0);
result_n : out std_logic_vector(31 downto 0);
regwrite_n : out std_logic);
end entity cpu_writeback;
architecture rtl of cpu_writeback is
signal result : std_logic_vector(31 downto 0);
begin
result <= readdata when memtoreg = '1' else
aluout;
writereg_n <= writereg;
result_n <= result;
regwrite_n <= regwrite;
end architecture rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1054.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p03n02i01054ent IS
END c06s04b00x00p03n02i01054ent;
ARCHITECTURE c06s04b00x00p03n02i01054arch OF c06s04b00x00p03n02i01054ent IS
BEGIN
TESTING: PROCESS
type ENUM1 is (EN1, EN2, EN3);
type A12 is array (ENUM1) of BOOLEAN;
variable V1: BOOLEAN;
variable V12: A12 ;
BEGIN
V1 := V12(EN3, EN2); -- ONE MORE
-- SEMANTIC ERROR: ACTUAL INDEX POSITIONS DO NOT CORRESPOND TO
-- INDEX POSITIONS IN TYPE DECLARATION
assert FALSE
report "***FAILED TEST: c06s04b00x00p03n02i01054 - The expresion should be the same type as the corresponding index."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p03n02i01054arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1054.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p03n02i01054ent IS
END c06s04b00x00p03n02i01054ent;
ARCHITECTURE c06s04b00x00p03n02i01054arch OF c06s04b00x00p03n02i01054ent IS
BEGIN
TESTING: PROCESS
type ENUM1 is (EN1, EN2, EN3);
type A12 is array (ENUM1) of BOOLEAN;
variable V1: BOOLEAN;
variable V12: A12 ;
BEGIN
V1 := V12(EN3, EN2); -- ONE MORE
-- SEMANTIC ERROR: ACTUAL INDEX POSITIONS DO NOT CORRESPOND TO
-- INDEX POSITIONS IN TYPE DECLARATION
assert FALSE
report "***FAILED TEST: c06s04b00x00p03n02i01054 - The expresion should be the same type as the corresponding index."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p03n02i01054arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1054.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p03n02i01054ent IS
END c06s04b00x00p03n02i01054ent;
ARCHITECTURE c06s04b00x00p03n02i01054arch OF c06s04b00x00p03n02i01054ent IS
BEGIN
TESTING: PROCESS
type ENUM1 is (EN1, EN2, EN3);
type A12 is array (ENUM1) of BOOLEAN;
variable V1: BOOLEAN;
variable V12: A12 ;
BEGIN
V1 := V12(EN3, EN2); -- ONE MORE
-- SEMANTIC ERROR: ACTUAL INDEX POSITIONS DO NOT CORRESPOND TO
-- INDEX POSITIONS IN TYPE DECLARATION
assert FALSE
report "***FAILED TEST: c06s04b00x00p03n02i01054 - The expresion should be the same type as the corresponding index."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p03n02i01054arch;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
GAL5gnoL9tLJJ5c5WUbEnhNujFGP9EnwUoi9xzXE4eQkda34c4j5WIeurwKyTvM7ybU0+qT8H8DU
FIjDzcA6DA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
midpBXE0gV0pe7sIfwspmkvl1TD6JyTcOY1yll0eecWih4T3asW0A+XVSj5+YMRsoQsZDLxYxpye
LNocIstDJV4qB3k+TWc6+PwsntpGGfcJW8RlahJ84f8fsxAmRgp9/kY/cEfcmmv6Z953/pNXfsX+
kt56LMI2YZcGH4CxQ1M=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
4yj13ITOC3rvDq6jtshCphcxjgw+EEMjN86pFFoZ6GMHo7G4NSCdCcnPRRNhsA6Cdn0ujnbAX3c8
OFc74UqbUfr/2MA1qAaJnDXVisFJ0CR8S0Z9j2zxErQHjGz8m0ZEQffZu/sm2tW/k6C56OOLnuML
ydq37WFOgofmRilegCLbqTTBToxsyzlcyclw3jvrgSWJUhpsExnXwYugBFmqWXurC60dPbD6vbWA
HGTT8bdxsOAl7ggcN1+05cztDrg+OvDrsmOiRwZ4Z0TFgviEA8dX7YS0NpOOZc0evlnGylQGWEAe
/AcXwq1iVekpsg9j8czWl0fN5m7mfz7d7HCWgg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
0HyUH0TBlQh+LR8PeM0fIthJEJTjUgha+nm7wT0JC9DEDlWC+JA7MKDlLtg3Oqoi6vk6nd/Kl2+8
8ED4YJ1OeeJWGmdAiHVTCJI/wD3YTc+3kw8HwE2smdZbk6Eng79NCcH9cDiZZ9HvRysk7Y0vaeHi
BZGjZtm/noDbWLC/leo=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
bQcWkfP1h2AlfHRzlDmxyWNV97ypx3EejiEE2MYqemHZQTneSJaDrX7npaBDAou/28JnnBWS2WFz
QAoXwKzwtI7lfEXBx7xca7otLn3U9Q4Qms4+3FH6eYt7BqbWfFMgy+X259pdCo6xkGITUuak4wH0
mvlM+XNGxxrNvvnQ2n5rMx+2mO/ugY2i7yy+5R/WNNt0ByKO1SZbHpGd6m3lEceZDdhPXHmNgkSO
xWimnrPBTsAmLGCCcgJZcghJoZRWXZ5joZR6txubXuzc75nBmORg7GZEDnr0hs3tnXCP5mKRFaDl
6csuEPTt/tfd7k+j8mlRMvYXOSjg7uJzwF7Vdg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7088)
`protect data_block
GB7U3A/4HMoOlE0vj4GL2VWSUbCW8a1uUc8FVEtkSVPnIHDkYLq52z0qPrn8acur6OC9/0D+p1ZC
FKYGzbBYDJ/vd1IFmKBHiu9Q8boZpFF8Qp3rmJ5a+MlUJjl/h74rAXBfvMKq+EHO8f/WJR2rceoR
fp7bNpVoL8l9gaWx5L6LUMouezKL3kWYkfwE0j0hyK4lrXsTUafFo87z+aCqk9D7LFFk5hVX5U9z
fbcBA2RLFaBYsz2zbDdcbFhlF4KFfldcK3hxCYWsrpARMdX2tNkqkTfS7HOFGAKmk4GMmg+xyNdw
T5ZlGBkFMUxQQKfjrg0x2GXaUzj+OdTBdpxcpbSqfxsz4N6rb85y8esIz30YUu7+/R6of+qe2c6M
22iVinhWqTQ7eeuuAgjru9gT9+4E5WhvoFL8PpXBftaT9zQdpXr6RSSRXA5/0RXUtHKprmBgH+5f
9h0AH/NnjDPFg8O+U9h5V5UOLPkNSiAyF8PXtt9rGY5oFqWzpHVz9fBso7le7+ZUssVEXDLcBx6M
lqW2DNFzjVljRKcHED3jKpcHNBhFiS7/nW4WKN1QufjfBB+66AMY4HP1qrHmRDpu0VdVSTF4gN9a
03ehRctV6EwSjOXU1AbjaowqZ3zKIPtY8HB64in8JVeLeLB42R1q1SvRZLIf0zjMDsOWirb3ustV
JK24+WxeL2SCwI7BjWil6piUXC8sD1CvKvhGJhwzNwm8UWKnWXJ17p7+DP1G8MkDtPb1xpQxnFxT
SUuF+FzG3cBTw0RWh6upwjrNXJxfWufUxbWtEcMlFP4kyEtbtFBvSZ9JuicipBojjlDlkZJYsHD8
bZ/zdZA0L4nh098esxEJ+V4PQJKE0UKY0sOPwBI/XG6XykVg5mnS+WG5D/bSpgiUlhufHFBAkn4S
Law/1A+stnzvmkqkjA7ap6htZB0z5mBBAfUq6lI0CWUVgMuIH+oFOb1r99a95HW75j2AP9YTLiNU
ueBuyvtjMmJwlyEC5deSrMnKvf4TCUAUChGH/P96NO6n+7LrCz3Tg+hz2Gy9GRxLAzTpKbzKOUt+
FJwgM7B9rS/ALAHa+U0RM2TWireuVte2rG7FUdHbISyXogNMfnidATG/Aq2C41TcugDQNlPdK1PH
H+3+Za8JX2IjcyFBpEqOWRV21LgtPreKmZas3D6D9UoNyITuPSCP8hkhoUeyU48hYHBG1kcS6XPg
jSdHZbuZXj53B6M1Lbm8axGRg7ke19pP2qQkR3sQfDRp2S04R4VTdFLWREFlHm3efr7cET9PpsUK
OqqbeEKU9ODfpUgu8VJnPUHD3WecbS0wZ3MEf44N4DzibTrKi2sN4EeND0WQkagpOEB92ktB4f84
yhd5NAPz8Hp9WmvGhuOwX1exLZfC1r5m14wyO4bZDGSgi+3o/feOsNBmQ153T7vnzaHYKiUjrrIP
VBax9YHSPofOxxEGMa2lujMU1VF7bDJrvRfxxqqXdbJ2EYt8VgCmXq/XwpErrkAN3tuTyFfEZOHd
7Rc0+9M0d187+/GtK7/tVep1QHqzGRn6r4XayZ+AZKTJCiTFZEalqTzlRYdgbH4JoCtCCZSVzyFJ
BqpSZfp5/fR43jVPSnrH+91EywV1UtDIGqtyxAbg2nXYIM0Kwh58kfGZtO9Ustv1qatzGl7sP6eG
i59TRSdUL/CbIZjXgx8FJIltJEV+NzEsasFayuzL+RZz8Gba2Ot+sHJrrZH5Er60uiaGl8OWVjcs
DoESi/QFAQoq02bVpOw95hZ60Nod5KWEcI7vgzGWqLRNudNjB/H4e880jeUJOx9dLVfryTkNkXLm
sGs9Kmi/oIBBAVB8HK+d+6creFrCmc6Dm45y9T7dbY+p+JGemhsXNRaMRZlBvCoBnAs0bBGri8U1
CklfWypyDvgSAUwc5HUAau4VjtFHZEc8oGsPYuKFjY9A5cLyoRjmWHoajE9fd1KAkXEURVSXnPEg
wBta0QcRwZnZ8zjtiLiXIRFgAdIRZLY/A5nka0YcHLp7HUVIqgHwQTxWbstCrLIJoDbMGaBkwsne
ziSfGOz7RfCUGeC8SWLw0Dc58hwUm4WojskjWe1C2UnT0kRerHMGrGitKGRk5x4V/Q9svudja27K
5+RVFjP36uKUVv0XcdboVq5ob83hOvs7Llal4yhh33dPIL6GiuZqOM6c7Qw1L1Sa+UnFP71lBWKf
A9KGTiEX9strGzjPXoJIWOmwRi9WF9AZ6xM74Qrir5nAQp84stVjnnFFlr6wD5S7Qp2rcWCDKHtJ
p9Ss2jwO+mY2GWlgqQisFms8H9zvmnULeZygFeb8ONaXgutoCOra1HqWLDLLymGYa7bx+4qIVoD8
aXNgvsJG3hARodNlzyGZ3vVaxY6nTjKDB2ddPrOcSDeT85UAhvuhmWZ4Gxb7PwRHOvs+iTycUsYt
OyL/wXo8umxiUEhUo1FRn6R4MUbOE58Ear6H3XOsB6FRVJs6oHxOEuXydQWDt1hAiveZvXRNUGon
jcaIzqAt0Zgj/6U5b5Vx9NaRtLqx5zV+7rMfL2Lj1AX7ysjUfLK4G8vGVMNFXhuX8on2UP0UJRtO
Cqa/0JndYvw+NjUuCyuepq8QjFP+jruss2KgzEJlAZxr5ANPVv5GD4Dhngw0tQeHzeOXDU2Qf25+
g3tq1HOOX4GpJ+Ep0dcfeMksD0t4anEVvi53p6QtYhPduJO8qCIbycEzSMPkwIXUMTVFKeRI2pd5
v8haTSDQYbilpce2yyQD6aXxlR/KbXlXPgy+37cyRWfwNTGcoG8UEZtsWNJFl/6u7zA/ZbYVEMpN
ZxvcjTnimtWqIgEeLnjZuDdIV3ozvusjSCBOvuw/4bciNA+Eyb0ah/Fo93sVZMtI82th0flpdz0/
InCSbP9ZGpy5sqHHNEdrxVDsCnQn4qnTZEIS93kNmuJzg2hJ5y4A6PqNgOxHEW1b39NKaGruz42L
TOpWNqB4du7E4onb0CDI8Z2POfiIq8C/rGAVMMpZcpEUiWb+Hl+7X4DLkdV8ZKeS6VE4lc51SSMD
Si1DwNAGuaVuvIZ7f4N68A9TQ1805iQQ7XwuG9kywRXxzBQNz4wRQasjBvqX0BBF02gnScxFSO2+
UMWEccyp7qJjISt5D9EClI+1tDV3nX0SJWa6rAp3kLjmse+lgjk6ZnVy3zgGMAeRoU+QQGkwZder
wNRP3HS6t/14HVcq1VJOjT+beTF203ZoqaIhD7NnRfiJjJ3y1NgHkmYMcaX60YWX0RjlofrNvSmy
j3LdqzelYQuLqlqyoZ5ECVgTXmSeZERruH9lyKMXk72uiRcH1grYHF0MXO+hfTqSnO9WyFKGDn0a
YZuPm61Y8yj3H0eA+UfzhBo+zU7kw0zLgDOTg5imWv7/fFOjjcm3vbc/FiGxvP0Aku/zvBeCfCYr
OtLZpNXP/IqNACmdYKyVy+O8HW1hDZmbI9p0Fgdxn2ZP5BkPQGsJEPW/yb2vdAFZ8unjPHtvom3+
JURZYBU9yW/R7yPsuei2Lw2UxnZkydM2zSwmNvpgoiw/fpfUpBUHIGVR+6eICtB44bQQirkWwm1p
a718cIcK7B3NjcMvrN+2sf4ZG9mo2ctOdAGh6n2cV9weL5I0/phZhxcpOgfYfyrQBKtd+5tK/R8L
icg718TTLu0aXbyVE9NNtS1FPG9E5+9gh6qV3g0q5TtCcbiOCDB4WbAcL7m3K34mj4aW10g3uLjE
H2wtYicivPPgwp3Kr8volRTP8yvH5kSmgFVkZi2DlqQyIg6w9ESvXP8MBXlC8/nq1GbHb9HU2xOV
9jVApmmedAHKKno3AMtu/ZsOEOeTbNJr0MgE4+kt7t2gnnk9EJ06doYqMT6qXdzPVX2lZEOCF7ab
tJPG4tPhmG6ko6bul4fTwcNjxdPLalK0tJWjQ1JKwxOhQTrYdGIc0Sp3uUskAl/sVo/rLx0P1lwO
EGEeKhkZy6M/gACBvFpAIpHK2QZoGy+er49IECmhnzdKbQs/z5FFGNboIdVaexe3PyaCu4qihJql
IigFwY4Tr1FeTin3g9hwwyJosA5Hfp7LViOxWkzu91kU0Wm9oivqwdwTm+/dSJjqv3xIJ6hbJsLE
SS1Knf9gaPTmMoJAVA+1tk0mY1B7UNTLGcP/KiunjUmn6Sf0wBDdx0LQJYOkTjd7RAMByLdvrH/I
bWMXQu0KVf2BUFJhRrdT1c5Z8gNWb6HGCcioRYa/irgtZoYPX3auYWOR2DCDMhMxZcGCCVYdwQq0
lrJc6YYURWoYWsTcEuM7QRs8cwCpvx/Q3wCzvDP0GgLwi4WVGcaHanHsi5YjgSaxdNNxrpOl3ymj
CJqV01ilWAwf3KWnEepvS09U9Wjb7tNVG4Qp/xXPkXZEox8O2kWvkYbSoMfCpF0fw0CVLpNa9SnM
J8Tzq9AHNW7GdAzSuY90kByrvFRkslqbSujOLSX2xahRosCIJv/godNuEtpMtMObkLKNE69uukS/
KmMpYmRVfT2cCbZCozxp7L0owaYKVUctyn0NjN3Bmh8e+7rg3/6Jj0CphpMaRy7m1rByLb3C3KEl
0XPCb+CIPHa3x9mNX6NWlBzEHpHE5yv1trzmwBg8xhJJ//da0aysN+bEyEAW66snPkDl3ZAf6imB
/TCl7Aeg1tl+KMzOsltV/BYlJq3zSbIU/dUfA9vIj/ofSmbJKwEuUYuTpFuWDc898wARqv4yzUCA
H0qZYh3CdXsnhwB+1RuTlWB9F97jm7s9A9bFWk6wMfDH1OHLz35x722RMMmPtNNAQIbf2BPKzUUg
p2TciZHa9HShNCtX7o+Lztf8bpQy4NkD/vqFXBbLa/FLw3ltR6SYra6NRjWkYKV6/KB/uumRiAR1
wGIaEfBx/ygxnXH6d7NPNN89Z5p8oRZ712yaxXlULYPctg6GKxNKsfgJ3RGSSRsBJsDfoYN3afFs
KhU/epm/TS4GM9KgIOMaRyzuWuhY/QxiwLZwqaQWQxZKl7ZaxIB01nr9PVTLbiw6ORUip/BR2wgz
EFLS7r3IhY9F7sJNlrLJG4vlhyu+45K9NiboRzMAtHPQAZ1Z2rtPfhwgfHfWw0s+mFyJt0FWRLLi
mNfLN1esrtXJZ0jTWzV1yO8Sse5D5FMJTLF2yBy/Z/Cgk9Jd66VyY4lMmYy3RXAhvO0cSrg6p06y
5hXwwEto35u2JlbzUKz76p1yeYa/l5ySzjW+yj/i8Rl/uN3fUVYF028BDv708v8HxQG6VsbG52I+
AMIHnLr8bWaffyl5IrfPLFiikjHKu2fANO6xPRqZZzLdzX7UzBNJ01lSSb1caxfTLFI92dp0u8XQ
AkOzyvcT86I6hinY7Y+6apZ38rOY5VADqDcJVb8QRjl7uYzkLFoTJWKFgnLlMptKBPEKi20A+aNC
3VN1Iu/Jun+jLGKYetnnmeoZyzf/Q12AtNJvbsyqiOcWbmoT4nK6NeIfIu5o/oy9WVgz4djBru2q
6bU6JpoArpgUsgsk9so5PuN7ZnZ7Z3oaRiIKHfPIdSV1k6ImVrPQqIMPIPHEBzComHXd9SwAIXIM
tD//+YTPsMGV4fiJKSpyN9i1+msyYgV6MDUMfnGeKD5jzXyZXQvr7ohzTzuMBlYW9es3SploDT8Z
BFJIsEFJcItV5BUpbRFXT6Ldaro1ArRr8Mn/yCq1HhDWY8lt5ygMahg2FKjLoDUmGKA40kAB89ur
U2H6uNnMK6Yz9rqRi2eOD4r9oqRUClg7P8ohNVyyNKSYVrEYGURyjHGTMwPEoSqNXaT2Pe1/dGnI
Pm2Tf4mJxiVKt8LHfpo/HWJkwF5Q6rOipbM58AkCHMNn5JaHMhjjolSwjLpDrHji0VFrWXGvI6vY
DRtvyTPA4aZWGO1TsEx/S2g+U73MmYTc/VnPgHmWpPmtEOOpYIY4AyswlmqURdoggn8sbKvmz+Pr
SRqOMGVtKFXPyylLp4WXOe4nmKaazZcuWDC18aaarUXr2KnyCl5yg4PCnOmcMbFxG8IbY6I05SdD
+q7mx+6Bb0JvKR0t9vKj+ATcABZL2Kr8vySB1MctLLQb68zjW7jso/Pw04hUClj8pSmfz35bLut/
xj7gtf+yK1m3hzGA1noJl4ogEoYqgTBVAMZCEMHKr7BQ+uqY3+bM8D1k9QFu/w4AqAqIjY7HEQVz
T7n0gFdfTAu+USFQMiVKaspYVTxA4rA/tTOf2pUrBO+lzlH3GInASzgmYJhtzeIgb8FutzczIBC4
0YX7t7ty1Ehul39MZG7xUriUTiRLBaMFDXUIpz8DiTjhWc/U54/Lf7U13n72z1MK1wkG6TNNOBiR
Fs6QH6sRISL6pLhj/sKPY3EGjLkyiIpN3yvVyZxDNKw/8NI52tBkxtCaWQV7X/ojv/TLYPmzTstJ
e0GC9OtO11VDxrqNWgvGlKNkPL8ABFDmS8lat5EnXBvGyvLDnZQVSVR0/Ml8CS+kxyOOnDM1q4vl
mJEN7xfC3nNALnQLxbwk7vEEEs7nW3hfROmATcfkvxkziuyCyorJ0Q6lpiaoNbE3H9XkTszYrIQk
bTUf/+6X1wIf+VSa25/2CoxCvx/u0VhUniB35XOXUBt5Q0YS6HcoRy6TOVY5eSl85mJIAUX0Vx0I
pzUyuAFCbHhNHtmuSUi3veJhjI3QjExeWrBo5HTylcfzEtPTpgDjegF7akjyln500gLiULc56/4k
W1Y/y5M2E3drMJGKNthnv4ajw9amfTu5BQFVCEG5BXq5pDqmTbcV5U9lP4+ctYmKCt91zlPzADdd
6ufMaLEtUXsHurV7pNqdrtUUaYXPHcMz10SP7qn19NSqhDiOJHSRGmlXyhHIVEKK+Fzcw7DlSmGt
HQoVM58sTFlKiMyrOYxeFJZRB/AummwKoTsJt+tVMlwjQ/k2dbxR/alSktSTFqdWTEw2cvKo63Sw
c7gJzGQqKehtWzgXDbuClFnAPxkmHLwsOhzYIKKr2bV3FuaONmjLvrjyf/MwCj9FbFArEvSzdG+H
hvrdI/U0JM3Bh5158VEp6UuvrCRBMo9Yo+8RWcH17RO8eEF7JYECUJ49YoJDd4UJLLvFGvWZ0m9T
o+lsm6Qkx3rVoW8cGYXgKK3SbEeKlBXkez282YNAqf9aRaYk5T+9jWopw0Mf+Kw2RWjsB5R2bbOT
p7MNoNcYGyHarMq9F5Git1d7ilNVIA5plSIMaLWj2C3BQyYjmd66jk1yJ/asASPP78zlOZKTZ8Hz
EG7oZamdtaV8BI4McNP3M9UKwxN2cvDr0frBU2prG9mnwCoTMKco68ItXoXS7U1AU3wyZEDAOxan
0FVAUdGISm1h/kt7nlGsWq3NDlkaU/9OAHmKOUXa4RyAAICfkVuwFjs6ktlKy5ZeEp46jRAD3R/e
xlcO+q0stOTndjQ+51zF0gqvcWJgKuXYbEACP93LOmW7C5VX+7oKUpxsKxe3HOcBCfKLDuiRO7Uf
2bbHxNmLh3zeadGqVlplWWwpKQziZHL/FMV4AFKwPuk7B9ASkJFknvgGKoMS20G+iIUSBo63wwFM
M/yOlzx9FfKgxH6e6CJvxFz0FBSg/Xn8zt0B7lzEe2H4pQRGLIlQLonRp0c0OJLs7uB0RT6IhXmc
hHqhUmqRWr7w164saj2U9VLD2hDc37thtDyaqdaJAXHVZl5DkX59QA3QUxgQgxIYNpOLQAc6vzUB
5lFzEs1xseM/drxP8/Ymqqfd7yKioBjvEy+aLM6eQTqQ6GGtHGubwxBox/EPa0DofYiS98B5zy7H
Q+FESO6JofnavVsgtcLtkyh/nCY8GB0Xf0UFuSm0s+1zTI4NQuJfYo0qkIqWUbqsk12C0wQukEjR
zNjAETNvGBm1Lg6oSVly0Jg6cc4OnznSV1Fn0VhD9riecyaBXju9PZyiBbNicRP8o3/5LVBu/tRE
DERbGrOg0rdTOPn9y9qysvT/lnYyNRtDby33W3yMNLy/JsVDURtnGNnoaqoYTIkbZicCgrGEtei/
YkCzv4/HofRxULQfrtn375XTqFtqKq9FxYuXhpWzG6MZL/UXFwFh7gL9fvcj+ya6JpLk2oeZlIYq
cLJw9YLu4XcQJoJLt9oQtk5abEjEiFE5nRZh2/S76cJCo0uPJpEB2rdAKFYHuTdyX1svQi4j0gxw
HFWnrTjPXu7Ed0xFsecyDDyCi5IcSk+2z6f4NfTiV0qA1lqwEiTF77W8hlQRzk+cVMb0+EZ/oIam
bNTX8XJPQW9Dxj1zH7tO/I7KLbg+XgTsgsvwCpB9g2AX0mxNc+Vh7UgX3Sc6y2un6u/y4rah4QCt
O+BZZ+MN9SkkMH3wkvJ/2G2bTJCMGHB9EIO5FZF6+7SytMIugH0wwBetTSwOJG7F0N7FAKBtvcY4
hxPtMdkj6b3qE7eGI50s+wf7eldJGrj2P6bD5z2tAaZUCMzNxRL54Zv7c4jpgoU2uZCLsMPoqqlY
fDeVCZgx0QBG0B7eUhHPEFGZ5uu9oXSNbv8UssUsthjQLTI29+EA1kNEEYbgjKmtFJ+/BxgK0AAj
IwVrsU/3OdpEf/P7Cm1WmMqu40EPkzqYhDNCYLlwL5BWGMpK1KaCdbHcNqyhZZ2MOeMQkxxy3TuY
q6neJHrHeGX2nvTOdA6PjakDgQkws+M3/EePV0zVBt+PzwMN4x+0FnnVILFBW0TjjFHnsMgO8WYI
DowovFHGvuQgD2u8jp80UH4R039lfqMGJMdNGeZ1d0vqCCi8LvQ3h9lLi2txzQGXoPRyxu3dK877
y1O0c7jwYW365CS+BMu1u7RTt1CqjKQStja9jV75pHpN0SaRrsDFCTJQyU3ryaKexS4xwrsgWeny
LiPiK2ZpiZWuRWPXJsl3lFBMkJB1k7VAj4iaHqiwGeb5dwQbhDy8IBiIB/et9QDzzy0JWaDdBiAg
bAIgIxorRJRUIW9qvsHsbTlumXUK9fdpeXNttF+bLKLk1QzQM2WZWbb8IZ4+wA4EFJ5ZdJo+BWZ9
L2D70r4C6z/c52Go/oijPXtU1/yNLaYSyq/V5/+aIiXd54CaSXPvcBxODKTlnlpolvYeI0ABu7Wy
2405hh1JCDAJf9y68OPVaWKkI6sCQaiLdrdVMCYgstcq2lbtynffxhQJgTRdZJjaps4HqyWbn3Db
rdzTibw0J8zJi/vStHM2bqDQSwG/A2N2U1cBwIHXHZhSP4cVZdO77/LD8/3g7EetOobq/2HL/dRb
pv4kbE4qTGn/3rVVrXibuuGlrlMZ/F67FbmeTZ5KNSUTH8ryL+Dsi/gTi7z/T4tAkVSXTLeDdWnO
aafdDx0ZHwBeunNddw5QUPyCbZCY8K1NJX+VCb+zMkqyRqoHEzYI0hLY/0vZLB1decgS1OFbnXj5
SvfxAou6Cmwnb4LnrnaNLlfT3OQzQftmr3M5AgK5sJ7I/uJz2rvqkBTtQIbV/3jB2PtsQTwtLDN7
hTI0vbw2UHYX8S4MSsROFd1z/Gs=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
GAL5gnoL9tLJJ5c5WUbEnhNujFGP9EnwUoi9xzXE4eQkda34c4j5WIeurwKyTvM7ybU0+qT8H8DU
FIjDzcA6DA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
midpBXE0gV0pe7sIfwspmkvl1TD6JyTcOY1yll0eecWih4T3asW0A+XVSj5+YMRsoQsZDLxYxpye
LNocIstDJV4qB3k+TWc6+PwsntpGGfcJW8RlahJ84f8fsxAmRgp9/kY/cEfcmmv6Z953/pNXfsX+
kt56LMI2YZcGH4CxQ1M=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
4yj13ITOC3rvDq6jtshCphcxjgw+EEMjN86pFFoZ6GMHo7G4NSCdCcnPRRNhsA6Cdn0ujnbAX3c8
OFc74UqbUfr/2MA1qAaJnDXVisFJ0CR8S0Z9j2zxErQHjGz8m0ZEQffZu/sm2tW/k6C56OOLnuML
ydq37WFOgofmRilegCLbqTTBToxsyzlcyclw3jvrgSWJUhpsExnXwYugBFmqWXurC60dPbD6vbWA
HGTT8bdxsOAl7ggcN1+05cztDrg+OvDrsmOiRwZ4Z0TFgviEA8dX7YS0NpOOZc0evlnGylQGWEAe
/AcXwq1iVekpsg9j8czWl0fN5m7mfz7d7HCWgg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
0HyUH0TBlQh+LR8PeM0fIthJEJTjUgha+nm7wT0JC9DEDlWC+JA7MKDlLtg3Oqoi6vk6nd/Kl2+8
8ED4YJ1OeeJWGmdAiHVTCJI/wD3YTc+3kw8HwE2smdZbk6Eng79NCcH9cDiZZ9HvRysk7Y0vaeHi
BZGjZtm/noDbWLC/leo=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
bQcWkfP1h2AlfHRzlDmxyWNV97ypx3EejiEE2MYqemHZQTneSJaDrX7npaBDAou/28JnnBWS2WFz
QAoXwKzwtI7lfEXBx7xca7otLn3U9Q4Qms4+3FH6eYt7BqbWfFMgy+X259pdCo6xkGITUuak4wH0
mvlM+XNGxxrNvvnQ2n5rMx+2mO/ugY2i7yy+5R/WNNt0ByKO1SZbHpGd6m3lEceZDdhPXHmNgkSO
xWimnrPBTsAmLGCCcgJZcghJoZRWXZ5joZR6txubXuzc75nBmORg7GZEDnr0hs3tnXCP5mKRFaDl
6csuEPTt/tfd7k+j8mlRMvYXOSjg7uJzwF7Vdg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7088)
`protect data_block
GB7U3A/4HMoOlE0vj4GL2VWSUbCW8a1uUc8FVEtkSVPnIHDkYLq52z0qPrn8acur6OC9/0D+p1ZC
FKYGzbBYDJ/vd1IFmKBHiu9Q8boZpFF8Qp3rmJ5a+MlUJjl/h74rAXBfvMKq+EHO8f/WJR2rceoR
fp7bNpVoL8l9gaWx5L6LUMouezKL3kWYkfwE0j0hyK4lrXsTUafFo87z+aCqk9D7LFFk5hVX5U9z
fbcBA2RLFaBYsz2zbDdcbFhlF4KFfldcK3hxCYWsrpARMdX2tNkqkTfS7HOFGAKmk4GMmg+xyNdw
T5ZlGBkFMUxQQKfjrg0x2GXaUzj+OdTBdpxcpbSqfxsz4N6rb85y8esIz30YUu7+/R6of+qe2c6M
22iVinhWqTQ7eeuuAgjru9gT9+4E5WhvoFL8PpXBftaT9zQdpXr6RSSRXA5/0RXUtHKprmBgH+5f
9h0AH/NnjDPFg8O+U9h5V5UOLPkNSiAyF8PXtt9rGY5oFqWzpHVz9fBso7le7+ZUssVEXDLcBx6M
lqW2DNFzjVljRKcHED3jKpcHNBhFiS7/nW4WKN1QufjfBB+66AMY4HP1qrHmRDpu0VdVSTF4gN9a
03ehRctV6EwSjOXU1AbjaowqZ3zKIPtY8HB64in8JVeLeLB42R1q1SvRZLIf0zjMDsOWirb3ustV
JK24+WxeL2SCwI7BjWil6piUXC8sD1CvKvhGJhwzNwm8UWKnWXJ17p7+DP1G8MkDtPb1xpQxnFxT
SUuF+FzG3cBTw0RWh6upwjrNXJxfWufUxbWtEcMlFP4kyEtbtFBvSZ9JuicipBojjlDlkZJYsHD8
bZ/zdZA0L4nh098esxEJ+V4PQJKE0UKY0sOPwBI/XG6XykVg5mnS+WG5D/bSpgiUlhufHFBAkn4S
Law/1A+stnzvmkqkjA7ap6htZB0z5mBBAfUq6lI0CWUVgMuIH+oFOb1r99a95HW75j2AP9YTLiNU
ueBuyvtjMmJwlyEC5deSrMnKvf4TCUAUChGH/P96NO6n+7LrCz3Tg+hz2Gy9GRxLAzTpKbzKOUt+
FJwgM7B9rS/ALAHa+U0RM2TWireuVte2rG7FUdHbISyXogNMfnidATG/Aq2C41TcugDQNlPdK1PH
H+3+Za8JX2IjcyFBpEqOWRV21LgtPreKmZas3D6D9UoNyITuPSCP8hkhoUeyU48hYHBG1kcS6XPg
jSdHZbuZXj53B6M1Lbm8axGRg7ke19pP2qQkR3sQfDRp2S04R4VTdFLWREFlHm3efr7cET9PpsUK
OqqbeEKU9ODfpUgu8VJnPUHD3WecbS0wZ3MEf44N4DzibTrKi2sN4EeND0WQkagpOEB92ktB4f84
yhd5NAPz8Hp9WmvGhuOwX1exLZfC1r5m14wyO4bZDGSgi+3o/feOsNBmQ153T7vnzaHYKiUjrrIP
VBax9YHSPofOxxEGMa2lujMU1VF7bDJrvRfxxqqXdbJ2EYt8VgCmXq/XwpErrkAN3tuTyFfEZOHd
7Rc0+9M0d187+/GtK7/tVep1QHqzGRn6r4XayZ+AZKTJCiTFZEalqTzlRYdgbH4JoCtCCZSVzyFJ
BqpSZfp5/fR43jVPSnrH+91EywV1UtDIGqtyxAbg2nXYIM0Kwh58kfGZtO9Ustv1qatzGl7sP6eG
i59TRSdUL/CbIZjXgx8FJIltJEV+NzEsasFayuzL+RZz8Gba2Ot+sHJrrZH5Er60uiaGl8OWVjcs
DoESi/QFAQoq02bVpOw95hZ60Nod5KWEcI7vgzGWqLRNudNjB/H4e880jeUJOx9dLVfryTkNkXLm
sGs9Kmi/oIBBAVB8HK+d+6creFrCmc6Dm45y9T7dbY+p+JGemhsXNRaMRZlBvCoBnAs0bBGri8U1
CklfWypyDvgSAUwc5HUAau4VjtFHZEc8oGsPYuKFjY9A5cLyoRjmWHoajE9fd1KAkXEURVSXnPEg
wBta0QcRwZnZ8zjtiLiXIRFgAdIRZLY/A5nka0YcHLp7HUVIqgHwQTxWbstCrLIJoDbMGaBkwsne
ziSfGOz7RfCUGeC8SWLw0Dc58hwUm4WojskjWe1C2UnT0kRerHMGrGitKGRk5x4V/Q9svudja27K
5+RVFjP36uKUVv0XcdboVq5ob83hOvs7Llal4yhh33dPIL6GiuZqOM6c7Qw1L1Sa+UnFP71lBWKf
A9KGTiEX9strGzjPXoJIWOmwRi9WF9AZ6xM74Qrir5nAQp84stVjnnFFlr6wD5S7Qp2rcWCDKHtJ
p9Ss2jwO+mY2GWlgqQisFms8H9zvmnULeZygFeb8ONaXgutoCOra1HqWLDLLymGYa7bx+4qIVoD8
aXNgvsJG3hARodNlzyGZ3vVaxY6nTjKDB2ddPrOcSDeT85UAhvuhmWZ4Gxb7PwRHOvs+iTycUsYt
OyL/wXo8umxiUEhUo1FRn6R4MUbOE58Ear6H3XOsB6FRVJs6oHxOEuXydQWDt1hAiveZvXRNUGon
jcaIzqAt0Zgj/6U5b5Vx9NaRtLqx5zV+7rMfL2Lj1AX7ysjUfLK4G8vGVMNFXhuX8on2UP0UJRtO
Cqa/0JndYvw+NjUuCyuepq8QjFP+jruss2KgzEJlAZxr5ANPVv5GD4Dhngw0tQeHzeOXDU2Qf25+
g3tq1HOOX4GpJ+Ep0dcfeMksD0t4anEVvi53p6QtYhPduJO8qCIbycEzSMPkwIXUMTVFKeRI2pd5
v8haTSDQYbilpce2yyQD6aXxlR/KbXlXPgy+37cyRWfwNTGcoG8UEZtsWNJFl/6u7zA/ZbYVEMpN
ZxvcjTnimtWqIgEeLnjZuDdIV3ozvusjSCBOvuw/4bciNA+Eyb0ah/Fo93sVZMtI82th0flpdz0/
InCSbP9ZGpy5sqHHNEdrxVDsCnQn4qnTZEIS93kNmuJzg2hJ5y4A6PqNgOxHEW1b39NKaGruz42L
TOpWNqB4du7E4onb0CDI8Z2POfiIq8C/rGAVMMpZcpEUiWb+Hl+7X4DLkdV8ZKeS6VE4lc51SSMD
Si1DwNAGuaVuvIZ7f4N68A9TQ1805iQQ7XwuG9kywRXxzBQNz4wRQasjBvqX0BBF02gnScxFSO2+
UMWEccyp7qJjISt5D9EClI+1tDV3nX0SJWa6rAp3kLjmse+lgjk6ZnVy3zgGMAeRoU+QQGkwZder
wNRP3HS6t/14HVcq1VJOjT+beTF203ZoqaIhD7NnRfiJjJ3y1NgHkmYMcaX60YWX0RjlofrNvSmy
j3LdqzelYQuLqlqyoZ5ECVgTXmSeZERruH9lyKMXk72uiRcH1grYHF0MXO+hfTqSnO9WyFKGDn0a
YZuPm61Y8yj3H0eA+UfzhBo+zU7kw0zLgDOTg5imWv7/fFOjjcm3vbc/FiGxvP0Aku/zvBeCfCYr
OtLZpNXP/IqNACmdYKyVy+O8HW1hDZmbI9p0Fgdxn2ZP5BkPQGsJEPW/yb2vdAFZ8unjPHtvom3+
JURZYBU9yW/R7yPsuei2Lw2UxnZkydM2zSwmNvpgoiw/fpfUpBUHIGVR+6eICtB44bQQirkWwm1p
a718cIcK7B3NjcMvrN+2sf4ZG9mo2ctOdAGh6n2cV9weL5I0/phZhxcpOgfYfyrQBKtd+5tK/R8L
icg718TTLu0aXbyVE9NNtS1FPG9E5+9gh6qV3g0q5TtCcbiOCDB4WbAcL7m3K34mj4aW10g3uLjE
H2wtYicivPPgwp3Kr8volRTP8yvH5kSmgFVkZi2DlqQyIg6w9ESvXP8MBXlC8/nq1GbHb9HU2xOV
9jVApmmedAHKKno3AMtu/ZsOEOeTbNJr0MgE4+kt7t2gnnk9EJ06doYqMT6qXdzPVX2lZEOCF7ab
tJPG4tPhmG6ko6bul4fTwcNjxdPLalK0tJWjQ1JKwxOhQTrYdGIc0Sp3uUskAl/sVo/rLx0P1lwO
EGEeKhkZy6M/gACBvFpAIpHK2QZoGy+er49IECmhnzdKbQs/z5FFGNboIdVaexe3PyaCu4qihJql
IigFwY4Tr1FeTin3g9hwwyJosA5Hfp7LViOxWkzu91kU0Wm9oivqwdwTm+/dSJjqv3xIJ6hbJsLE
SS1Knf9gaPTmMoJAVA+1tk0mY1B7UNTLGcP/KiunjUmn6Sf0wBDdx0LQJYOkTjd7RAMByLdvrH/I
bWMXQu0KVf2BUFJhRrdT1c5Z8gNWb6HGCcioRYa/irgtZoYPX3auYWOR2DCDMhMxZcGCCVYdwQq0
lrJc6YYURWoYWsTcEuM7QRs8cwCpvx/Q3wCzvDP0GgLwi4WVGcaHanHsi5YjgSaxdNNxrpOl3ymj
CJqV01ilWAwf3KWnEepvS09U9Wjb7tNVG4Qp/xXPkXZEox8O2kWvkYbSoMfCpF0fw0CVLpNa9SnM
J8Tzq9AHNW7GdAzSuY90kByrvFRkslqbSujOLSX2xahRosCIJv/godNuEtpMtMObkLKNE69uukS/
KmMpYmRVfT2cCbZCozxp7L0owaYKVUctyn0NjN3Bmh8e+7rg3/6Jj0CphpMaRy7m1rByLb3C3KEl
0XPCb+CIPHa3x9mNX6NWlBzEHpHE5yv1trzmwBg8xhJJ//da0aysN+bEyEAW66snPkDl3ZAf6imB
/TCl7Aeg1tl+KMzOsltV/BYlJq3zSbIU/dUfA9vIj/ofSmbJKwEuUYuTpFuWDc898wARqv4yzUCA
H0qZYh3CdXsnhwB+1RuTlWB9F97jm7s9A9bFWk6wMfDH1OHLz35x722RMMmPtNNAQIbf2BPKzUUg
p2TciZHa9HShNCtX7o+Lztf8bpQy4NkD/vqFXBbLa/FLw3ltR6SYra6NRjWkYKV6/KB/uumRiAR1
wGIaEfBx/ygxnXH6d7NPNN89Z5p8oRZ712yaxXlULYPctg6GKxNKsfgJ3RGSSRsBJsDfoYN3afFs
KhU/epm/TS4GM9KgIOMaRyzuWuhY/QxiwLZwqaQWQxZKl7ZaxIB01nr9PVTLbiw6ORUip/BR2wgz
EFLS7r3IhY9F7sJNlrLJG4vlhyu+45K9NiboRzMAtHPQAZ1Z2rtPfhwgfHfWw0s+mFyJt0FWRLLi
mNfLN1esrtXJZ0jTWzV1yO8Sse5D5FMJTLF2yBy/Z/Cgk9Jd66VyY4lMmYy3RXAhvO0cSrg6p06y
5hXwwEto35u2JlbzUKz76p1yeYa/l5ySzjW+yj/i8Rl/uN3fUVYF028BDv708v8HxQG6VsbG52I+
AMIHnLr8bWaffyl5IrfPLFiikjHKu2fANO6xPRqZZzLdzX7UzBNJ01lSSb1caxfTLFI92dp0u8XQ
AkOzyvcT86I6hinY7Y+6apZ38rOY5VADqDcJVb8QRjl7uYzkLFoTJWKFgnLlMptKBPEKi20A+aNC
3VN1Iu/Jun+jLGKYetnnmeoZyzf/Q12AtNJvbsyqiOcWbmoT4nK6NeIfIu5o/oy9WVgz4djBru2q
6bU6JpoArpgUsgsk9so5PuN7ZnZ7Z3oaRiIKHfPIdSV1k6ImVrPQqIMPIPHEBzComHXd9SwAIXIM
tD//+YTPsMGV4fiJKSpyN9i1+msyYgV6MDUMfnGeKD5jzXyZXQvr7ohzTzuMBlYW9es3SploDT8Z
BFJIsEFJcItV5BUpbRFXT6Ldaro1ArRr8Mn/yCq1HhDWY8lt5ygMahg2FKjLoDUmGKA40kAB89ur
U2H6uNnMK6Yz9rqRi2eOD4r9oqRUClg7P8ohNVyyNKSYVrEYGURyjHGTMwPEoSqNXaT2Pe1/dGnI
Pm2Tf4mJxiVKt8LHfpo/HWJkwF5Q6rOipbM58AkCHMNn5JaHMhjjolSwjLpDrHji0VFrWXGvI6vY
DRtvyTPA4aZWGO1TsEx/S2g+U73MmYTc/VnPgHmWpPmtEOOpYIY4AyswlmqURdoggn8sbKvmz+Pr
SRqOMGVtKFXPyylLp4WXOe4nmKaazZcuWDC18aaarUXr2KnyCl5yg4PCnOmcMbFxG8IbY6I05SdD
+q7mx+6Bb0JvKR0t9vKj+ATcABZL2Kr8vySB1MctLLQb68zjW7jso/Pw04hUClj8pSmfz35bLut/
xj7gtf+yK1m3hzGA1noJl4ogEoYqgTBVAMZCEMHKr7BQ+uqY3+bM8D1k9QFu/w4AqAqIjY7HEQVz
T7n0gFdfTAu+USFQMiVKaspYVTxA4rA/tTOf2pUrBO+lzlH3GInASzgmYJhtzeIgb8FutzczIBC4
0YX7t7ty1Ehul39MZG7xUriUTiRLBaMFDXUIpz8DiTjhWc/U54/Lf7U13n72z1MK1wkG6TNNOBiR
Fs6QH6sRISL6pLhj/sKPY3EGjLkyiIpN3yvVyZxDNKw/8NI52tBkxtCaWQV7X/ojv/TLYPmzTstJ
e0GC9OtO11VDxrqNWgvGlKNkPL8ABFDmS8lat5EnXBvGyvLDnZQVSVR0/Ml8CS+kxyOOnDM1q4vl
mJEN7xfC3nNALnQLxbwk7vEEEs7nW3hfROmATcfkvxkziuyCyorJ0Q6lpiaoNbE3H9XkTszYrIQk
bTUf/+6X1wIf+VSa25/2CoxCvx/u0VhUniB35XOXUBt5Q0YS6HcoRy6TOVY5eSl85mJIAUX0Vx0I
pzUyuAFCbHhNHtmuSUi3veJhjI3QjExeWrBo5HTylcfzEtPTpgDjegF7akjyln500gLiULc56/4k
W1Y/y5M2E3drMJGKNthnv4ajw9amfTu5BQFVCEG5BXq5pDqmTbcV5U9lP4+ctYmKCt91zlPzADdd
6ufMaLEtUXsHurV7pNqdrtUUaYXPHcMz10SP7qn19NSqhDiOJHSRGmlXyhHIVEKK+Fzcw7DlSmGt
HQoVM58sTFlKiMyrOYxeFJZRB/AummwKoTsJt+tVMlwjQ/k2dbxR/alSktSTFqdWTEw2cvKo63Sw
c7gJzGQqKehtWzgXDbuClFnAPxkmHLwsOhzYIKKr2bV3FuaONmjLvrjyf/MwCj9FbFArEvSzdG+H
hvrdI/U0JM3Bh5158VEp6UuvrCRBMo9Yo+8RWcH17RO8eEF7JYECUJ49YoJDd4UJLLvFGvWZ0m9T
o+lsm6Qkx3rVoW8cGYXgKK3SbEeKlBXkez282YNAqf9aRaYk5T+9jWopw0Mf+Kw2RWjsB5R2bbOT
p7MNoNcYGyHarMq9F5Git1d7ilNVIA5plSIMaLWj2C3BQyYjmd66jk1yJ/asASPP78zlOZKTZ8Hz
EG7oZamdtaV8BI4McNP3M9UKwxN2cvDr0frBU2prG9mnwCoTMKco68ItXoXS7U1AU3wyZEDAOxan
0FVAUdGISm1h/kt7nlGsWq3NDlkaU/9OAHmKOUXa4RyAAICfkVuwFjs6ktlKy5ZeEp46jRAD3R/e
xlcO+q0stOTndjQ+51zF0gqvcWJgKuXYbEACP93LOmW7C5VX+7oKUpxsKxe3HOcBCfKLDuiRO7Uf
2bbHxNmLh3zeadGqVlplWWwpKQziZHL/FMV4AFKwPuk7B9ASkJFknvgGKoMS20G+iIUSBo63wwFM
M/yOlzx9FfKgxH6e6CJvxFz0FBSg/Xn8zt0B7lzEe2H4pQRGLIlQLonRp0c0OJLs7uB0RT6IhXmc
hHqhUmqRWr7w164saj2U9VLD2hDc37thtDyaqdaJAXHVZl5DkX59QA3QUxgQgxIYNpOLQAc6vzUB
5lFzEs1xseM/drxP8/Ymqqfd7yKioBjvEy+aLM6eQTqQ6GGtHGubwxBox/EPa0DofYiS98B5zy7H
Q+FESO6JofnavVsgtcLtkyh/nCY8GB0Xf0UFuSm0s+1zTI4NQuJfYo0qkIqWUbqsk12C0wQukEjR
zNjAETNvGBm1Lg6oSVly0Jg6cc4OnznSV1Fn0VhD9riecyaBXju9PZyiBbNicRP8o3/5LVBu/tRE
DERbGrOg0rdTOPn9y9qysvT/lnYyNRtDby33W3yMNLy/JsVDURtnGNnoaqoYTIkbZicCgrGEtei/
YkCzv4/HofRxULQfrtn375XTqFtqKq9FxYuXhpWzG6MZL/UXFwFh7gL9fvcj+ya6JpLk2oeZlIYq
cLJw9YLu4XcQJoJLt9oQtk5abEjEiFE5nRZh2/S76cJCo0uPJpEB2rdAKFYHuTdyX1svQi4j0gxw
HFWnrTjPXu7Ed0xFsecyDDyCi5IcSk+2z6f4NfTiV0qA1lqwEiTF77W8hlQRzk+cVMb0+EZ/oIam
bNTX8XJPQW9Dxj1zH7tO/I7KLbg+XgTsgsvwCpB9g2AX0mxNc+Vh7UgX3Sc6y2un6u/y4rah4QCt
O+BZZ+MN9SkkMH3wkvJ/2G2bTJCMGHB9EIO5FZF6+7SytMIugH0wwBetTSwOJG7F0N7FAKBtvcY4
hxPtMdkj6b3qE7eGI50s+wf7eldJGrj2P6bD5z2tAaZUCMzNxRL54Zv7c4jpgoU2uZCLsMPoqqlY
fDeVCZgx0QBG0B7eUhHPEFGZ5uu9oXSNbv8UssUsthjQLTI29+EA1kNEEYbgjKmtFJ+/BxgK0AAj
IwVrsU/3OdpEf/P7Cm1WmMqu40EPkzqYhDNCYLlwL5BWGMpK1KaCdbHcNqyhZZ2MOeMQkxxy3TuY
q6neJHrHeGX2nvTOdA6PjakDgQkws+M3/EePV0zVBt+PzwMN4x+0FnnVILFBW0TjjFHnsMgO8WYI
DowovFHGvuQgD2u8jp80UH4R039lfqMGJMdNGeZ1d0vqCCi8LvQ3h9lLi2txzQGXoPRyxu3dK877
y1O0c7jwYW365CS+BMu1u7RTt1CqjKQStja9jV75pHpN0SaRrsDFCTJQyU3ryaKexS4xwrsgWeny
LiPiK2ZpiZWuRWPXJsl3lFBMkJB1k7VAj4iaHqiwGeb5dwQbhDy8IBiIB/et9QDzzy0JWaDdBiAg
bAIgIxorRJRUIW9qvsHsbTlumXUK9fdpeXNttF+bLKLk1QzQM2WZWbb8IZ4+wA4EFJ5ZdJo+BWZ9
L2D70r4C6z/c52Go/oijPXtU1/yNLaYSyq/V5/+aIiXd54CaSXPvcBxODKTlnlpolvYeI0ABu7Wy
2405hh1JCDAJf9y68OPVaWKkI6sCQaiLdrdVMCYgstcq2lbtynffxhQJgTRdZJjaps4HqyWbn3Db
rdzTibw0J8zJi/vStHM2bqDQSwG/A2N2U1cBwIHXHZhSP4cVZdO77/LD8/3g7EetOobq/2HL/dRb
pv4kbE4qTGn/3rVVrXibuuGlrlMZ/F67FbmeTZ5KNSUTH8ryL+Dsi/gTi7z/T4tAkVSXTLeDdWnO
aafdDx0ZHwBeunNddw5QUPyCbZCY8K1NJX+VCb+zMkqyRqoHEzYI0hLY/0vZLB1decgS1OFbnXj5
SvfxAou6Cmwnb4LnrnaNLlfT3OQzQftmr3M5AgK5sJ7I/uJz2rvqkBTtQIbV/3jB2PtsQTwtLDN7
hTI0vbw2UHYX8S4MSsROFd1z/Gs=
`protect end_protected
|
--Latest version of all project files available at http://opencores.org/project,wrimm
--See License.txt for license details
--See WrimmManual.pdf for the Wishbone Datasheet and implementation details.
--See wrimm subversion project for version history
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.WrimmPackage.all;
entity Wrimm_Top is
port (
WishboneClock : in std_logic;
WishboneReset : out std_logic;
MasterPStrobe : in std_logic;
MasterPWrEn : in std_logic;
MasterPCyc : in std_logic;
MasterPAddr : in WbAddrType;
MasterPDataToSlave : in WbDataType;
MasterPAck : out std_logic;
MasterPErr : out std_logic;
MasterPRty : out std_logic;
MasterPDataFrSlave : out WbDataType;
MasterQStrobe : in std_logic;
MasterQWrEn : in std_logic;
MasterQCyc : in std_logic;
MasterQAddr : in WbAddrType;
MasterQDataToSlave : in WbDataType;
MasterQAck : out std_logic;
MasterQErr : out std_logic;
MasterQRty : out std_logic;
MasterQDataFrSlave : out WbDataType;
StatusRegA : in std_logic_vector(0 to 7);
StatusRegB : in std_logic_vector(0 to 7);
StatusRegC : in std_logic_vector(0 to 7);
SettingRegX : out std_logic_vector(0 to 7);
SettingRstX : in std_logic;
SettingRegY : out std_logic_vector(0 to 7);
SettingRstY : in std_logic;
SettingRegZ : out std_logic_vector(0 to 7);
SettingRstZ : in std_logic;
TriggerRegR : out std_logic;
TriggerClrR : in std_logic;
TriggerRegS : out std_logic;
TriggerClrS : in std_logic;
TriggerRegT : out std_logic;
TriggerClrT : in std_logic;
rstZ : in std_logic); --Global asyncronous reset for initialization
end entity Wrimm_Top;
architecture structure of Wrimm_Top is
component Wrimm is
--generic (
-- MasterParams : WbMasterDefType;
-- SlaveParams : WbSlaveDefType;
-- StatusParams : StatusFieldDefType;
-- SettingParams : SettingFieldDefType;
-- TriggerParams : TriggerFieldDefType);
port (
WbClk : in std_logic;
WbRst : out std_logic;
WbMasterIn : in WbMasterOutArray; --Signals from Masters
WbMasterOut : out WbSlaveOutArray; --Signals to Masters
-- WbSlaveIn : out WbMasterOutArray;
-- WbSlaveOut : in WbSlaveOutArray;
StatusRegs : in StatusArrayType;
SettingRegs : out SettingArrayType;
SettingRsts : in SettingArrayBitType;
Triggers : out TriggerArrayType;
TriggerClr : in TriggerArrayType;
rstZ : in std_logic); --Asynchronous reset
end component Wrimm;
signal masterQOut : WbSlaveOutType;
signal masterQIn : WbMasterOutType;
begin
MasterQAck <= masterQOut.ack;
MasterQErr <= masterQOut.err;
MasterQRty <= masterQOut.rty;
MasterQDataFrSlave <= masterQOut.data;
masterQIn.strobe <= MasterQStrobe;
masterQIn.wren <= MasterQWrEn;
masterQIn.cyc <= MasterQCyc;
masterQIn.addr <= MasterQAddr;
masterQIn.data <= MasterQDataToSlave;
instWrimm: Wrimm
--generic map(
-- MasterParams => ,
-- SlaveParams => ,
-- StatusParams => StatusParams,
-- SettingParams => SettingParams,
-- TriggerParams => TriggerParams)
port map(
WbClk => WishboneClock,
WbRst => WishboneReset,
WbMasterIn(P).strobe => MasterPStrobe,
WbMasterIn(P).wren => MasterPWrEn,
WbMasterIn(P).cyc => MasterPCyc,
WbMasterIn(P).addr => MasterPAddr,
WbMasterIn(P).data => MasterPDataToSlave,
WbMasterIn(Q) => masterQIn,
WbMasterOut(P).ack => MasterPAck,
WbMasterOut(P).err => MasterPErr,
WbMasterOut(P).rty => MasterPRty,
WbMasterOut(P).data => MasterPDataFrSlave,
WbMasterOut(Q) => masterQOut,
--WbSlaveIn => ,
--WbSlaveOut => ,
StatusRegs(StatusA) => StatusRegA,
StatusRegs(StatusB) => StatusRegB,
StatusRegs(StatusC) => StatusRegC,
SettingRegs(SettingX) => SettingRegX,
SettingRegs(SettingY) => SettingRegY,
SettingRegs(SettingZ) => SettingRegZ,
SettingRsts(SettingX) => SettingRstX,
SettingRsts(SettingY) => SettingRstY,
SettingRsts(SettingZ) => SettingRstZ,
Triggers(TriggerR) => TriggerRegR,
Triggers(TriggerS) => TriggerRegS,
Triggers(TriggerT) => TriggerRegT,
TriggerClr(TriggerR) => TriggerClrR,
TriggerClr(TriggerS) => TriggerClrS,
TriggerClr(TriggerT) => TriggerClrT,
rstZ => rstZ); --Asynchronous reset
end architecture structure; |
------------------------------------------------------------------------------------------------------------------------
-- Parallel port (8/16bit) for PDI
--
-- Copyright (C) 2010 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2010-08-31 V0.01 zelenkaj First version
-- 2010-10-18 V0.02 zelenkaj added selection Big/Little Endian
-- use bidirectional data bus
-- 2010-11-15 V0.03 zelenkaj bug fix for 16bit parallel interface
-- 2010-11-23 V0.04 zelenkaj added 2 GPIO pins driving "00"
-- 2010-11-29 V0.05 zelenkaj full endianness consideration
-- 2011-03-21 V0.06 zelenkaj clean up
-- 2011-04-04 V0.10 zelenkaj change of concept
-- 2011-12-02 V0.11 zelenkaj Added I, O and T instead of IO ports
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity pdi_par is
generic (
papDataWidth_g : integer := 8;
papBigEnd_g : boolean := false; --deprecated
papGenIoBuf_g : boolean := true
);
port (
-- 8/16bit parallel
pap_cs : in std_logic;
pap_rd : in std_logic;
pap_wr : in std_logic;
pap_be : in std_logic_vector(papDataWidth_g/8-1 downto 0);
pap_addr : in std_logic_vector(15 downto 0);
pap_data : inout std_logic_vector(papDataWidth_g-1 downto 0);
pap_data_I : in std_logic_vector(papDataWidth_g-1 downto 0) := (others => '0');
pap_data_O : out std_logic_vector(papDataWidth_g-1 downto 0);
pap_data_T : out std_logic;
pap_ack : out std_logic;
-- clock for AP side
ap_reset : in std_logic;
ap_clk : in std_logic;
-- Avalon Slave Interface for AP
ap_chipselect : out std_logic;
ap_read : out std_logic;
ap_write : out std_logic;
ap_byteenable : out std_logic_vector(3 DOWNTO 0);
ap_address : out std_logic_vector(12 DOWNTO 0);
ap_writedata : out std_logic_vector(31 DOWNTO 0);
ap_readdata : in std_logic_vector(31 DOWNTO 0);
-- GPIO
pap_gpio : inout std_logic_vector(1 downto 0);
pap_gpio_I : in std_logic_vector(1 downto 0) := (others => '0');
pap_gpio_O : out std_logic_vector(1 downto 0);
pap_gpio_T : out std_logic_vector(1 downto 0)
);
end entity pdi_par;
architecture rtl of pdi_par is
signal ap_byteenable_s : std_logic_vector(ap_byteenable'range);
signal ap_write_s : std_logic;
signal pap_gpiooe_s : std_logic_vector(pap_gpio'range);
--signals being sync'd to ap_clk
signal pap_wrdata_s : std_logic_vector(pap_data'range);
signal pap_wrdata_ss : std_logic_vector(pap_data'range);
signal pap_rddata_s : std_logic_vector(pap_data'range);
signal pap_rddata_ss : std_logic_vector(pap_data'range);
signal pap_addr_s : std_logic_vector(pap_addr'range);
signal pap_cs_s : std_logic;
signal pap_rd_s : std_logic; --and with cs
signal pap_wr_s : std_logic; --and with cs
signal pap_be_s : std_logic_vector(pap_be'range);
--write register
signal writeRegister : std_logic_vector(pap_data'range);
--data tri state buffer
signal pap_doe_s : std_logic;
signal tsb_cnt, tsb_cnt_next : std_logic_vector(1 downto 0);
signal ap_address_write, ap_address_write_l : std_logic_vector(ap_address'range);
signal ap_byteenable_write, ap_byteenable_write_l : std_logic_vector(ap_byteenable'range);
signal ap_address_read : std_logic_vector(ap_address'range);
signal ap_byteenable_read : std_logic_vector(ap_byteenable'range);
begin
--reserved for further features not yet defined
genIoGpBuf : if papGenIoBuf_g generate
begin
pap_gpio <= "00" when pap_gpiooe_s = "11" else (others => 'Z');
end generate;
pap_gpiooe_s <= (others => '1');
pap_gpio_O <= "00";
pap_gpio_T <= not pap_gpiooe_s; --'1' = In, '0' = Out
-------------------------------------------------------------------------------------
-- tri-state buffer
genIoDatBuf : if papGenIoBuf_g generate
begin
pap_data <= pap_rddata_s when pap_doe_s = '1' else (others => 'Z');
end generate;
pap_data_O <= pap_rddata_s;
pap_data_T <= not pap_doe_s; --'1' = In, '0' = Out
-- write data register
-- latches data at falling edge of pap_wr
theWrDataReg : process(pap_wr, ap_reset)
begin
if ap_reset = '1' then
writeRegister <= (others => '0');
elsif pap_wr = '0' and pap_wr'event then
if papGenIoBuf_g then
writeRegister <= pap_data;
else
writeRegister <= pap_data_I;
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- store addr and be for write access
-- note: this reduces the address hold time to zero
--
addrStore : process(ap_clk, ap_reset)
begin
if ap_reset = '1' then
ap_address_write_l <= (others => '0');
ap_byteenable_write_l <= (others => '0');
ap_address_write <= (others => '0');
ap_byteenable_write <= (others => '0');
elsif ap_clk = '1' and ap_clk'event then
if pap_cs_s = '1' then
ap_address_write_l <= pap_addr_s(ap_address'left+2 downto 2);
ap_byteenable_write_l <= ap_byteenable_s;
end if;
ap_address_write <= ap_address_write_l;
ap_byteenable_write <= ap_byteenable_write_l;
end if;
end process;
ap_address_read <= pap_addr_s(ap_address'left+2 downto 2);
ap_byteenable_read <= ap_byteenable_s;
ap_address <= ap_address_write when ap_write_s = '1' else
ap_address_read;
ap_byteenable <= ap_byteenable_write when ap_write_s = '1' else
ap_byteenable_read;
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- generate write and read strobes and chipselect
-- note: pap_cs_s is already and'd with pap_rd_s and pap_wr_s
--falling edge latches write data, sync'd write strobe falls too
wrEdgeDet : entity work.edgeDet
port map (
din => pap_wr_s,
rising => open,
falling => ap_write_s,
any => open,
clk => ap_clk,
rst => ap_reset
);
ap_write <= ap_write_s;
--use the timeout counter highest bit
ap_read <= pap_rd_s and not ap_write_s;
ap_chipselect <= (pap_cs_s and pap_rd_s) or ap_write_s;
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- generate ack signal
pap_ack <= pap_doe_s or ap_write_s;
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- generate output enable signal for tri state buffer (with timeout)
pap_doe_s <= tsb_cnt(tsb_cnt'left) and pap_rd_s;
triStatBufCnt : process(ap_clk, ap_reset)
begin
if ap_reset = '1' then
tsb_cnt <= (others => '0');
elsif ap_clk = '1' and ap_clk'event then
tsb_cnt <= tsb_cnt_next;
end if;
end process;
tsb_cnt_next <= tsb_cnt when pap_doe_s = '1' else
tsb_cnt + 1 when pap_rd_s = '1' else
(others => '0');
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- generate 8 or 16 bit signals
gen8bitSigs : if papDataWidth_g = 8 generate
ap_byteenable_s <= "0001" when pap_addr_s(1 downto 0) = "00" else
"0010" when pap_addr_s(1 downto 0) = "01" else
"0100" when pap_addr_s(1 downto 0) = "10" else
"1000" when pap_addr_s(1 downto 0) = "11" else
(others => '0');
ap_writedata <= pap_wrdata_s & pap_wrdata_s & pap_wrdata_s & pap_wrdata_s;
pap_rddata_s <= ap_readdata( 7 downto 0) when ap_byteenable_s = "0001" else
ap_readdata(15 downto 8) when ap_byteenable_s = "0010" else
ap_readdata(23 downto 16) when ap_byteenable_s = "0100" else
ap_readdata(31 downto 24) when ap_byteenable_s = "1000" else
(others => '0');
end generate gen8bitSigs;
genBeSigs16bit : if papDataWidth_g = 16 generate
ap_byteenable_s <= "0001" when pap_addr_s(1 downto 1) = "0" and pap_be_s = "01" else
"0010" when pap_addr_s(1 downto 1) = "0" and pap_be_s = "10" else
"0011" when pap_addr_s(1 downto 1) = "0" and pap_be_s = "11" else
"0100" when pap_addr_s(1 downto 1) = "1" and pap_be_s = "01" else
"1000" when pap_addr_s(1 downto 1) = "1" and pap_be_s = "10" else
"1100" when pap_addr_s(1 downto 1) = "1" and pap_be_s = "11" else
(others => '0');
-- ap_byteenable <= ap_byteenable_s;
pap_wrdata_ss <= pap_wrdata_s;
ap_writedata <= pap_wrdata_ss & pap_wrdata_ss;
pap_rddata_ss <= ap_readdata( 7 downto 0) & ap_readdata( 7 downto 0) when ap_byteenable_s = "0001" else
ap_readdata(15 downto 8) & ap_readdata(15 downto 8) when ap_byteenable_s = "0010" else
ap_readdata(15 downto 0) when ap_byteenable_s = "0011" else
ap_readdata(23 downto 16) & ap_readdata(23 downto 16) when ap_byteenable_s = "0100" else
ap_readdata(31 downto 24) & ap_readdata(31 downto 24) when ap_byteenable_s = "1000" else
ap_readdata(31 downto 16) when ap_byteenable_s = "1100" else
(others => '0');
pap_rddata_s <= pap_rddata_ss;
end generate genBeSigs16bit;
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
--sync those signals
syncAddrGen : for i in pap_addr'range generate
syncAddr : entity work.sync
port map (
din => pap_addr(i),
dout => pap_addr_s(i),
clk => ap_clk,
rst => ap_reset
);
end generate;
syncBeGen : for i in pap_be'range generate
syncBe : entity work.sync
port map (
din => pap_be(i),
dout => pap_be_s(i),
clk => ap_clk,
rst => ap_reset
);
end generate;
syncWrRegGen : for i in writeRegister'range generate
syncWrReg : entity work.sync
port map (
din => writeRegister(i),
dout => pap_wrdata_s(i),
clk => ap_clk,
rst => ap_reset
);
end generate;
theMagicBlock : block
signal pap_rd_tmp, pap_wr_tmp, pap_cs_tmp : std_logic;
begin
syncCs : entity work.sync
port map (
din => pap_cs,
dout => pap_cs_tmp,
clk => ap_clk,
rst => ap_reset
);
pap_cs_s <= pap_cs_tmp;
syncRd : entity work.sync
port map (
din => pap_rd,
dout => pap_rd_tmp,
clk => ap_clk,
rst => ap_reset
);
pap_rd_s <= pap_rd_tmp and pap_cs_tmp;
syncWr : entity work.sync
port map (
din => pap_wr,
dout => pap_wr_tmp,
clk => ap_clk,
rst => ap_reset
);
pap_wr_s <= pap_wr_tmp;
end block;
--
-------------------------------------------------------------------------------------
end architecture rtl;
|
------------------------------------------------------------------------------------------------------------------------
-- Parallel port (8/16bit) for PDI
--
-- Copyright (C) 2010 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2010-08-31 V0.01 zelenkaj First version
-- 2010-10-18 V0.02 zelenkaj added selection Big/Little Endian
-- use bidirectional data bus
-- 2010-11-15 V0.03 zelenkaj bug fix for 16bit parallel interface
-- 2010-11-23 V0.04 zelenkaj added 2 GPIO pins driving "00"
-- 2010-11-29 V0.05 zelenkaj full endianness consideration
-- 2011-03-21 V0.06 zelenkaj clean up
-- 2011-04-04 V0.10 zelenkaj change of concept
-- 2011-12-02 V0.11 zelenkaj Added I, O and T instead of IO ports
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity pdi_par is
generic (
papDataWidth_g : integer := 8;
papBigEnd_g : boolean := false; --deprecated
papGenIoBuf_g : boolean := true
);
port (
-- 8/16bit parallel
pap_cs : in std_logic;
pap_rd : in std_logic;
pap_wr : in std_logic;
pap_be : in std_logic_vector(papDataWidth_g/8-1 downto 0);
pap_addr : in std_logic_vector(15 downto 0);
pap_data : inout std_logic_vector(papDataWidth_g-1 downto 0);
pap_data_I : in std_logic_vector(papDataWidth_g-1 downto 0) := (others => '0');
pap_data_O : out std_logic_vector(papDataWidth_g-1 downto 0);
pap_data_T : out std_logic;
pap_ack : out std_logic;
-- clock for AP side
ap_reset : in std_logic;
ap_clk : in std_logic;
-- Avalon Slave Interface for AP
ap_chipselect : out std_logic;
ap_read : out std_logic;
ap_write : out std_logic;
ap_byteenable : out std_logic_vector(3 DOWNTO 0);
ap_address : out std_logic_vector(12 DOWNTO 0);
ap_writedata : out std_logic_vector(31 DOWNTO 0);
ap_readdata : in std_logic_vector(31 DOWNTO 0);
-- GPIO
pap_gpio : inout std_logic_vector(1 downto 0);
pap_gpio_I : in std_logic_vector(1 downto 0) := (others => '0');
pap_gpio_O : out std_logic_vector(1 downto 0);
pap_gpio_T : out std_logic_vector(1 downto 0)
);
end entity pdi_par;
architecture rtl of pdi_par is
signal ap_byteenable_s : std_logic_vector(ap_byteenable'range);
signal ap_write_s : std_logic;
signal pap_gpiooe_s : std_logic_vector(pap_gpio'range);
--signals being sync'd to ap_clk
signal pap_wrdata_s : std_logic_vector(pap_data'range);
signal pap_wrdata_ss : std_logic_vector(pap_data'range);
signal pap_rddata_s : std_logic_vector(pap_data'range);
signal pap_rddata_ss : std_logic_vector(pap_data'range);
signal pap_addr_s : std_logic_vector(pap_addr'range);
signal pap_cs_s : std_logic;
signal pap_rd_s : std_logic; --and with cs
signal pap_wr_s : std_logic; --and with cs
signal pap_be_s : std_logic_vector(pap_be'range);
--write register
signal writeRegister : std_logic_vector(pap_data'range);
--data tri state buffer
signal pap_doe_s : std_logic;
signal tsb_cnt, tsb_cnt_next : std_logic_vector(1 downto 0);
signal ap_address_write, ap_address_write_l : std_logic_vector(ap_address'range);
signal ap_byteenable_write, ap_byteenable_write_l : std_logic_vector(ap_byteenable'range);
signal ap_address_read : std_logic_vector(ap_address'range);
signal ap_byteenable_read : std_logic_vector(ap_byteenable'range);
begin
--reserved for further features not yet defined
genIoGpBuf : if papGenIoBuf_g generate
begin
pap_gpio <= "00" when pap_gpiooe_s = "11" else (others => 'Z');
end generate;
pap_gpiooe_s <= (others => '1');
pap_gpio_O <= "00";
pap_gpio_T <= not pap_gpiooe_s; --'1' = In, '0' = Out
-------------------------------------------------------------------------------------
-- tri-state buffer
genIoDatBuf : if papGenIoBuf_g generate
begin
pap_data <= pap_rddata_s when pap_doe_s = '1' else (others => 'Z');
end generate;
pap_data_O <= pap_rddata_s;
pap_data_T <= not pap_doe_s; --'1' = In, '0' = Out
-- write data register
-- latches data at falling edge of pap_wr
theWrDataReg : process(pap_wr, ap_reset)
begin
if ap_reset = '1' then
writeRegister <= (others => '0');
elsif pap_wr = '0' and pap_wr'event then
if papGenIoBuf_g then
writeRegister <= pap_data;
else
writeRegister <= pap_data_I;
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- store addr and be for write access
-- note: this reduces the address hold time to zero
--
addrStore : process(ap_clk, ap_reset)
begin
if ap_reset = '1' then
ap_address_write_l <= (others => '0');
ap_byteenable_write_l <= (others => '0');
ap_address_write <= (others => '0');
ap_byteenable_write <= (others => '0');
elsif ap_clk = '1' and ap_clk'event then
if pap_cs_s = '1' then
ap_address_write_l <= pap_addr_s(ap_address'left+2 downto 2);
ap_byteenable_write_l <= ap_byteenable_s;
end if;
ap_address_write <= ap_address_write_l;
ap_byteenable_write <= ap_byteenable_write_l;
end if;
end process;
ap_address_read <= pap_addr_s(ap_address'left+2 downto 2);
ap_byteenable_read <= ap_byteenable_s;
ap_address <= ap_address_write when ap_write_s = '1' else
ap_address_read;
ap_byteenable <= ap_byteenable_write when ap_write_s = '1' else
ap_byteenable_read;
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- generate write and read strobes and chipselect
-- note: pap_cs_s is already and'd with pap_rd_s and pap_wr_s
--falling edge latches write data, sync'd write strobe falls too
wrEdgeDet : entity work.edgeDet
port map (
din => pap_wr_s,
rising => open,
falling => ap_write_s,
any => open,
clk => ap_clk,
rst => ap_reset
);
ap_write <= ap_write_s;
--use the timeout counter highest bit
ap_read <= pap_rd_s and not ap_write_s;
ap_chipselect <= (pap_cs_s and pap_rd_s) or ap_write_s;
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- generate ack signal
pap_ack <= pap_doe_s or ap_write_s;
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- generate output enable signal for tri state buffer (with timeout)
pap_doe_s <= tsb_cnt(tsb_cnt'left) and pap_rd_s;
triStatBufCnt : process(ap_clk, ap_reset)
begin
if ap_reset = '1' then
tsb_cnt <= (others => '0');
elsif ap_clk = '1' and ap_clk'event then
tsb_cnt <= tsb_cnt_next;
end if;
end process;
tsb_cnt_next <= tsb_cnt when pap_doe_s = '1' else
tsb_cnt + 1 when pap_rd_s = '1' else
(others => '0');
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- generate 8 or 16 bit signals
gen8bitSigs : if papDataWidth_g = 8 generate
ap_byteenable_s <= "0001" when pap_addr_s(1 downto 0) = "00" else
"0010" when pap_addr_s(1 downto 0) = "01" else
"0100" when pap_addr_s(1 downto 0) = "10" else
"1000" when pap_addr_s(1 downto 0) = "11" else
(others => '0');
ap_writedata <= pap_wrdata_s & pap_wrdata_s & pap_wrdata_s & pap_wrdata_s;
pap_rddata_s <= ap_readdata( 7 downto 0) when ap_byteenable_s = "0001" else
ap_readdata(15 downto 8) when ap_byteenable_s = "0010" else
ap_readdata(23 downto 16) when ap_byteenable_s = "0100" else
ap_readdata(31 downto 24) when ap_byteenable_s = "1000" else
(others => '0');
end generate gen8bitSigs;
genBeSigs16bit : if papDataWidth_g = 16 generate
ap_byteenable_s <= "0001" when pap_addr_s(1 downto 1) = "0" and pap_be_s = "01" else
"0010" when pap_addr_s(1 downto 1) = "0" and pap_be_s = "10" else
"0011" when pap_addr_s(1 downto 1) = "0" and pap_be_s = "11" else
"0100" when pap_addr_s(1 downto 1) = "1" and pap_be_s = "01" else
"1000" when pap_addr_s(1 downto 1) = "1" and pap_be_s = "10" else
"1100" when pap_addr_s(1 downto 1) = "1" and pap_be_s = "11" else
(others => '0');
-- ap_byteenable <= ap_byteenable_s;
pap_wrdata_ss <= pap_wrdata_s;
ap_writedata <= pap_wrdata_ss & pap_wrdata_ss;
pap_rddata_ss <= ap_readdata( 7 downto 0) & ap_readdata( 7 downto 0) when ap_byteenable_s = "0001" else
ap_readdata(15 downto 8) & ap_readdata(15 downto 8) when ap_byteenable_s = "0010" else
ap_readdata(15 downto 0) when ap_byteenable_s = "0011" else
ap_readdata(23 downto 16) & ap_readdata(23 downto 16) when ap_byteenable_s = "0100" else
ap_readdata(31 downto 24) & ap_readdata(31 downto 24) when ap_byteenable_s = "1000" else
ap_readdata(31 downto 16) when ap_byteenable_s = "1100" else
(others => '0');
pap_rddata_s <= pap_rddata_ss;
end generate genBeSigs16bit;
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
--sync those signals
syncAddrGen : for i in pap_addr'range generate
syncAddr : entity work.sync
port map (
din => pap_addr(i),
dout => pap_addr_s(i),
clk => ap_clk,
rst => ap_reset
);
end generate;
syncBeGen : for i in pap_be'range generate
syncBe : entity work.sync
port map (
din => pap_be(i),
dout => pap_be_s(i),
clk => ap_clk,
rst => ap_reset
);
end generate;
syncWrRegGen : for i in writeRegister'range generate
syncWrReg : entity work.sync
port map (
din => writeRegister(i),
dout => pap_wrdata_s(i),
clk => ap_clk,
rst => ap_reset
);
end generate;
theMagicBlock : block
signal pap_rd_tmp, pap_wr_tmp, pap_cs_tmp : std_logic;
begin
syncCs : entity work.sync
port map (
din => pap_cs,
dout => pap_cs_tmp,
clk => ap_clk,
rst => ap_reset
);
pap_cs_s <= pap_cs_tmp;
syncRd : entity work.sync
port map (
din => pap_rd,
dout => pap_rd_tmp,
clk => ap_clk,
rst => ap_reset
);
pap_rd_s <= pap_rd_tmp and pap_cs_tmp;
syncWr : entity work.sync
port map (
din => pap_wr,
dout => pap_wr_tmp,
clk => ap_clk,
rst => ap_reset
);
pap_wr_s <= pap_wr_tmp;
end block;
--
-------------------------------------------------------------------------------------
end architecture rtl;
|
------------------------------------------------------------------------------------------------------------------------
-- Parallel port (8/16bit) for PDI
--
-- Copyright (C) 2010 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2010-08-31 V0.01 zelenkaj First version
-- 2010-10-18 V0.02 zelenkaj added selection Big/Little Endian
-- use bidirectional data bus
-- 2010-11-15 V0.03 zelenkaj bug fix for 16bit parallel interface
-- 2010-11-23 V0.04 zelenkaj added 2 GPIO pins driving "00"
-- 2010-11-29 V0.05 zelenkaj full endianness consideration
-- 2011-03-21 V0.06 zelenkaj clean up
-- 2011-04-04 V0.10 zelenkaj change of concept
-- 2011-12-02 V0.11 zelenkaj Added I, O and T instead of IO ports
------------------------------------------------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity pdi_par is
generic (
papDataWidth_g : integer := 8;
papBigEnd_g : boolean := false; --deprecated
papGenIoBuf_g : boolean := true
);
port (
-- 8/16bit parallel
pap_cs : in std_logic;
pap_rd : in std_logic;
pap_wr : in std_logic;
pap_be : in std_logic_vector(papDataWidth_g/8-1 downto 0);
pap_addr : in std_logic_vector(15 downto 0);
pap_data : inout std_logic_vector(papDataWidth_g-1 downto 0);
pap_data_I : in std_logic_vector(papDataWidth_g-1 downto 0) := (others => '0');
pap_data_O : out std_logic_vector(papDataWidth_g-1 downto 0);
pap_data_T : out std_logic;
pap_ack : out std_logic;
-- clock for AP side
ap_reset : in std_logic;
ap_clk : in std_logic;
-- Avalon Slave Interface for AP
ap_chipselect : out std_logic;
ap_read : out std_logic;
ap_write : out std_logic;
ap_byteenable : out std_logic_vector(3 DOWNTO 0);
ap_address : out std_logic_vector(12 DOWNTO 0);
ap_writedata : out std_logic_vector(31 DOWNTO 0);
ap_readdata : in std_logic_vector(31 DOWNTO 0);
-- GPIO
pap_gpio : inout std_logic_vector(1 downto 0);
pap_gpio_I : in std_logic_vector(1 downto 0) := (others => '0');
pap_gpio_O : out std_logic_vector(1 downto 0);
pap_gpio_T : out std_logic_vector(1 downto 0)
);
end entity pdi_par;
architecture rtl of pdi_par is
signal ap_byteenable_s : std_logic_vector(ap_byteenable'range);
signal ap_write_s : std_logic;
signal pap_gpiooe_s : std_logic_vector(pap_gpio'range);
--signals being sync'd to ap_clk
signal pap_wrdata_s : std_logic_vector(pap_data'range);
signal pap_wrdata_ss : std_logic_vector(pap_data'range);
signal pap_rddata_s : std_logic_vector(pap_data'range);
signal pap_rddata_ss : std_logic_vector(pap_data'range);
signal pap_addr_s : std_logic_vector(pap_addr'range);
signal pap_cs_s : std_logic;
signal pap_rd_s : std_logic; --and with cs
signal pap_wr_s : std_logic; --and with cs
signal pap_be_s : std_logic_vector(pap_be'range);
--write register
signal writeRegister : std_logic_vector(pap_data'range);
--data tri state buffer
signal pap_doe_s : std_logic;
signal tsb_cnt, tsb_cnt_next : std_logic_vector(1 downto 0);
signal ap_address_write, ap_address_write_l : std_logic_vector(ap_address'range);
signal ap_byteenable_write, ap_byteenable_write_l : std_logic_vector(ap_byteenable'range);
signal ap_address_read : std_logic_vector(ap_address'range);
signal ap_byteenable_read : std_logic_vector(ap_byteenable'range);
begin
--reserved for further features not yet defined
genIoGpBuf : if papGenIoBuf_g generate
begin
pap_gpio <= "00" when pap_gpiooe_s = "11" else (others => 'Z');
end generate;
pap_gpiooe_s <= (others => '1');
pap_gpio_O <= "00";
pap_gpio_T <= not pap_gpiooe_s; --'1' = In, '0' = Out
-------------------------------------------------------------------------------------
-- tri-state buffer
genIoDatBuf : if papGenIoBuf_g generate
begin
pap_data <= pap_rddata_s when pap_doe_s = '1' else (others => 'Z');
end generate;
pap_data_O <= pap_rddata_s;
pap_data_T <= not pap_doe_s; --'1' = In, '0' = Out
-- write data register
-- latches data at falling edge of pap_wr
theWrDataReg : process(pap_wr, ap_reset)
begin
if ap_reset = '1' then
writeRegister <= (others => '0');
elsif pap_wr = '0' and pap_wr'event then
if papGenIoBuf_g then
writeRegister <= pap_data;
else
writeRegister <= pap_data_I;
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- store addr and be for write access
-- note: this reduces the address hold time to zero
--
addrStore : process(ap_clk, ap_reset)
begin
if ap_reset = '1' then
ap_address_write_l <= (others => '0');
ap_byteenable_write_l <= (others => '0');
ap_address_write <= (others => '0');
ap_byteenable_write <= (others => '0');
elsif ap_clk = '1' and ap_clk'event then
if pap_cs_s = '1' then
ap_address_write_l <= pap_addr_s(ap_address'left+2 downto 2);
ap_byteenable_write_l <= ap_byteenable_s;
end if;
ap_address_write <= ap_address_write_l;
ap_byteenable_write <= ap_byteenable_write_l;
end if;
end process;
ap_address_read <= pap_addr_s(ap_address'left+2 downto 2);
ap_byteenable_read <= ap_byteenable_s;
ap_address <= ap_address_write when ap_write_s = '1' else
ap_address_read;
ap_byteenable <= ap_byteenable_write when ap_write_s = '1' else
ap_byteenable_read;
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- generate write and read strobes and chipselect
-- note: pap_cs_s is already and'd with pap_rd_s and pap_wr_s
--falling edge latches write data, sync'd write strobe falls too
wrEdgeDet : entity work.edgeDet
port map (
din => pap_wr_s,
rising => open,
falling => ap_write_s,
any => open,
clk => ap_clk,
rst => ap_reset
);
ap_write <= ap_write_s;
--use the timeout counter highest bit
ap_read <= pap_rd_s and not ap_write_s;
ap_chipselect <= (pap_cs_s and pap_rd_s) or ap_write_s;
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- generate ack signal
pap_ack <= pap_doe_s or ap_write_s;
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- generate output enable signal for tri state buffer (with timeout)
pap_doe_s <= tsb_cnt(tsb_cnt'left) and pap_rd_s;
triStatBufCnt : process(ap_clk, ap_reset)
begin
if ap_reset = '1' then
tsb_cnt <= (others => '0');
elsif ap_clk = '1' and ap_clk'event then
tsb_cnt <= tsb_cnt_next;
end if;
end process;
tsb_cnt_next <= tsb_cnt when pap_doe_s = '1' else
tsb_cnt + 1 when pap_rd_s = '1' else
(others => '0');
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
-- generate 8 or 16 bit signals
gen8bitSigs : if papDataWidth_g = 8 generate
ap_byteenable_s <= "0001" when pap_addr_s(1 downto 0) = "00" else
"0010" when pap_addr_s(1 downto 0) = "01" else
"0100" when pap_addr_s(1 downto 0) = "10" else
"1000" when pap_addr_s(1 downto 0) = "11" else
(others => '0');
ap_writedata <= pap_wrdata_s & pap_wrdata_s & pap_wrdata_s & pap_wrdata_s;
pap_rddata_s <= ap_readdata( 7 downto 0) when ap_byteenable_s = "0001" else
ap_readdata(15 downto 8) when ap_byteenable_s = "0010" else
ap_readdata(23 downto 16) when ap_byteenable_s = "0100" else
ap_readdata(31 downto 24) when ap_byteenable_s = "1000" else
(others => '0');
end generate gen8bitSigs;
genBeSigs16bit : if papDataWidth_g = 16 generate
ap_byteenable_s <= "0001" when pap_addr_s(1 downto 1) = "0" and pap_be_s = "01" else
"0010" when pap_addr_s(1 downto 1) = "0" and pap_be_s = "10" else
"0011" when pap_addr_s(1 downto 1) = "0" and pap_be_s = "11" else
"0100" when pap_addr_s(1 downto 1) = "1" and pap_be_s = "01" else
"1000" when pap_addr_s(1 downto 1) = "1" and pap_be_s = "10" else
"1100" when pap_addr_s(1 downto 1) = "1" and pap_be_s = "11" else
(others => '0');
-- ap_byteenable <= ap_byteenable_s;
pap_wrdata_ss <= pap_wrdata_s;
ap_writedata <= pap_wrdata_ss & pap_wrdata_ss;
pap_rddata_ss <= ap_readdata( 7 downto 0) & ap_readdata( 7 downto 0) when ap_byteenable_s = "0001" else
ap_readdata(15 downto 8) & ap_readdata(15 downto 8) when ap_byteenable_s = "0010" else
ap_readdata(15 downto 0) when ap_byteenable_s = "0011" else
ap_readdata(23 downto 16) & ap_readdata(23 downto 16) when ap_byteenable_s = "0100" else
ap_readdata(31 downto 24) & ap_readdata(31 downto 24) when ap_byteenable_s = "1000" else
ap_readdata(31 downto 16) when ap_byteenable_s = "1100" else
(others => '0');
pap_rddata_s <= pap_rddata_ss;
end generate genBeSigs16bit;
--
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
--sync those signals
syncAddrGen : for i in pap_addr'range generate
syncAddr : entity work.sync
port map (
din => pap_addr(i),
dout => pap_addr_s(i),
clk => ap_clk,
rst => ap_reset
);
end generate;
syncBeGen : for i in pap_be'range generate
syncBe : entity work.sync
port map (
din => pap_be(i),
dout => pap_be_s(i),
clk => ap_clk,
rst => ap_reset
);
end generate;
syncWrRegGen : for i in writeRegister'range generate
syncWrReg : entity work.sync
port map (
din => writeRegister(i),
dout => pap_wrdata_s(i),
clk => ap_clk,
rst => ap_reset
);
end generate;
theMagicBlock : block
signal pap_rd_tmp, pap_wr_tmp, pap_cs_tmp : std_logic;
begin
syncCs : entity work.sync
port map (
din => pap_cs,
dout => pap_cs_tmp,
clk => ap_clk,
rst => ap_reset
);
pap_cs_s <= pap_cs_tmp;
syncRd : entity work.sync
port map (
din => pap_rd,
dout => pap_rd_tmp,
clk => ap_clk,
rst => ap_reset
);
pap_rd_s <= pap_rd_tmp and pap_cs_tmp;
syncWr : entity work.sync
port map (
din => pap_wr,
dout => pap_wr_tmp,
clk => ap_clk,
rst => ap_reset
);
pap_wr_s <= pap_wr_tmp;
end block;
--
-------------------------------------------------------------------------------------
end architecture rtl;
|
-- CPU controller.
-- Main controller code of the CPU - fetching, decoding and
-- executing instructions.
--
-- Luz micro-controller implementation
-- Eli Bendersky (C) 2008-2010
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.cpu_defs.all;
use work.utils_pak.all;
-- The main CPU controller module.
--
entity controller is
port
(
clk: in std_logic;
reset_n: in std_logic;
-- memory interface
--
mem_read: out std_logic;
mem_write: out std_logic;
mem_bytesel: out std_logic_vector(3 downto 0);
mem_addr: out word;
mem_data_out: out word;
mem_ack: in std_logic;
mem_data_in: in word;
-- interface to the register file
--
reg_sel_a: out std_logic_vector(4 downto 0);
reg_a_out: in word;
reg_sel_b: out std_logic_vector(4 downto 0);
reg_b_out: in word;
reg_sel_c: out std_logic_vector(4 downto 0);
reg_c_out: in word;
reg_sel_y: out std_logic_vector(4 downto 0);
reg_write_y: out std_logic;
reg_y_in: out word;
reg_sel_z: out std_logic_vector(4 downto 0);
reg_write_z: out std_logic;
reg_z_in: out word;
-- interface to the ALU
--
alu_op: out cpu_opcode;
alu_rs_in: out word;
alu_rt_in: out word;
alu_rd_in: out word;
alu_imm_in: out word;
alu_output_a: in word;
alu_output_b: in word;
-- interface to the program counter
--
pc_in: out word;
pc_write: out std_logic;
pc_out: in word;
dummy: out std_logic
);
end controller;
architecture controller_arc of controller is
signal PC_ff, NPC_ff: word;
signal IR_ff: word;
signal Rs_ff, Rt_ff, Rd_ff: word;
signal Imm_unsigned_ff: word;
signal Imm_signed_ff: word;
signal ALU_out_a_ff: word;
signal ALU_out_b_ff: word;
signal LMD_ff: word;
signal OP_ff: cpu_opcode;
signal load_addr_ff: word;
signal store_addr_ff: word;
signal branch_addr_ff: word;
signal reg_rs_sel: std_logic_vector(4 downto 0);
signal reg_rt_sel: std_logic_vector(4 downto 0);
signal reg_rd_sel: std_logic_vector(4 downto 0);
-- CPU execution cycles:
--
-- out_of_reset:
--
type cycle_type is
(
halted,
out_of_reset,
fetch,
decode,
execution,
memory_access,
write_back
);
signal cycle: cycle_type;
signal instr_fetch: boolean;
signal instr_is_load: boolean;
signal instr_is_store: boolean;
signal instr_is_branch: boolean;
signal instr_writes_back: boolean;
signal instr_result_dword: boolean;
signal branch_is_taken: boolean;
begin
-- The main state machine process
--
proc_cycle: process(clk, reset_n)
begin
if (reset_n = '0') then
cycle <= out_of_reset;
elsif (rising_edge(clk)) then
case (cycle) is
when out_of_reset =>
cycle <= fetch;
-- When data is ready in mem_data_in, move to
-- the decoding cycle.
--
when fetch =>
if mem_ack = '1' then
cycle <= decode;
end if;
-- During the decoding cycle the instruction is
-- taken from IR and is decoded into its
-- constituents.
--
when decode =>
cycle <= execution;
-- During the execution cycle, the ALU does its
-- work on the arguments taken from registers.
--
when execution =>
cycle <= memory_access;
-- The memory access is for memory loads/stores.
--
when memory_access =>
if ( not (instr_is_store or instr_is_load) or
mem_ack = '1') then
cycle <= write_back;
end if;
when write_back =>
cycle <= fetch;
when halted =>
cycle <= halted;
when others =>
end case;
end if;
end process;
-- Updating the value of the program counter when in memory
-- access cycle. The value is either changed to a branch
-- address for branch instructions, or just advanced by 4 for
-- other instructions. ZZZ: what about JR?!
--
pc_write <= '1' when cycle = memory_access else '0';
pc_in <= branch_addr_ff when instr_is_branch and branch_is_taken else
std_logic_vector(unsigned(PC_ff) + 4);
-- Next PC
--
NPC_ff <= pc_out;
-- Stores the program counter for later usage
--
proc_PC_ff: process(clk, reset_n)
begin
if (reset_n = '0') then
PC_ff <= NPC_ff;
elsif (rising_edge(clk)) then
if cycle = fetch then
PC_ff <= NPC_ff;
end if;
end if;
end process;
-- Instruction fetch
--
instr_fetch <= cycle = fetch;
-- Helper signals for identifying instruction types
--
with OP_ff select
instr_is_load <= true when OP_LB | OP_LBU | OP_LH | OP_LHU | OP_LW,
false when others;
with OP_ff select
instr_is_store <= true when OP_SB | OP_SH | OP_SW,
false when others;
with OP_ff select
instr_is_branch <= true when OP_BEQ | OP_BNE | OP_BGE |
OP_BGT | OP_BLE | OP_BLT |
OP_BGEU | OP_BGTU |
OP_BLEU | OP_BLTU,
false when others;
-- instr_writes_back: an instruction that stores a result in
-- a register
--
with OP_ff select
instr_writes_back <= true when OP_ADD | OP_ADDI | OP_SUB |
OP_SUBI | OP_MULU | OP_MUL |
OP_DIVU | OP_DIV | OP_LUI |
OP_SLL | OP_SLLI | OP_SRL |
OP_SRLI | OP_AND | OP_ANDI |
OP_OR | OP_ORI | OP_NOR |
OP_XOR | OP_LB | OP_LBU |
OP_LH | OP_LHU | OP_LW |
OP_CALL,
false when others;
-- instr_result_dword: an instruction that produces a 64-bit
-- result
--
with OP_ff select
instr_result_dword <= true when OP_MUL | OP_MULU |
OP_DIV | OP_DIVU,
false when others;
branch_is_taken <= instr_is_branch and ALU_out_a_ff(0) = '1';
-- Read from memory when:
-- * fetching an instruction
-- * executing a load instruction
--
mem_read <= '1' when instr_fetch or
(cycle = memory_access and instr_is_load)
else '0';
-- Write to memory when executing a store instruction
--
mem_write <= '1' when cycle = memory_access and instr_is_store else '0';
-- Byte select lines depend on the width of the load/store
-- access. For instructions, words are fetched.
--
mem_bytesel <= "1111" when instr_fetch else
"0001" when OP_ff = OP_SB or OP_ff = OP_LB or OP_ff = OP_LBU else
"0011" when OP_ff = OP_SH or OP_ff = OP_LH or OP_ff = OP_LHU else
"1111" when OP_ff = OP_LW or OP_ff = OP_SW else
"0000";
-- Memory address
--
mem_addr <= NPC_ff when instr_fetch else
load_addr_ff when cycle = memory_access and instr_is_load else
store_addr_ff when cycle = memory_access and instr_is_store
else (others => '0');
-- Memory data in is taken from Rs in store instructions
--
mem_data_out <= Rs_ff;
-- The instruction register holds the current instruction
-- read from the memory.
-- Since the memory outputs are synchronous, IR_ff is just an
-- alias. It will be read only on rising_edge(clk), so it
-- really represents a register.
--
IR_ff <= mem_data_in;
-- The opcode
--
proc_OP_ff: process(clk, reset_n)
begin
if (reset_n = '0') then
OP_ff <= (others => '0');
elsif (rising_edge(clk)) then
OP_ff <= IR_ff(31 downto 26);
end if;
end process;
reg_rd_sel <= IR_ff(25 downto 21);
reg_rs_sel <= IR_ff(20 downto 16);
reg_rt_sel <= IR_ff(15 downto 11);
reg_sel_a <= reg_rd_sel;
reg_sel_b <= reg_rs_sel;
reg_sel_c <= reg_rt_sel;
-- The unsigned (zero-extended) and signed (sign-extended)
-- interpretations of the immediate value.
-- Both are delayed by a clock cycle to be ready in the same
-- cycle with the values of registers.
--
proc_Imm_ff: process(clk, reset_n)
begin
if (reset_n = '0') then
Imm_unsigned_ff <= (others => '0');
Imm_signed_ff <= (others => '0');
elsif (rising_edge(clk)) then
Imm_unsigned_ff <= std_logic_vector(resize(unsigned(IR_ff(15 downto 0)), 32));
Imm_signed_ff <= std_logic_vector(resize(signed(IR_ff(15 downto 0)), 32));
end if;
end process;
-- Contents of registers.
--
Rd_ff <= reg_a_out;
Rs_ff <= reg_b_out;
Rt_ff <= reg_c_out;
-- ALU arguments and outputs
--
alu_op <= OP_ff;
alu_rs_in <= Rs_ff;
alu_rt_in <= Rt_ff;
alu_rd_in <= Rd_ff;
alu_imm_in <= Imm_unsigned_ff;
ALU_out_a_ff <= alu_output_a;
ALU_out_b_ff <= alu_output_b;
-- load and store addresses, computed during the execution
-- cycle.
--
proc_load_addr_ff: process(clk, reset_n)
begin
if (reset_n = '0') then
load_addr_ff <= (others => '0');
elsif (rising_edge(clk)) then
load_addr_ff <= std_logic_vector(signed(Rs_ff) + signed(Imm_signed_ff));
end if;
end process;
proc_store_addr_ff: process(clk, reset_n)
begin
if (reset_n = '0') then
store_addr_ff <= (others => '0');
elsif (rising_edge(clk)) then
store_addr_ff <= std_logic_vector(signed(Rd_ff) + signed(Imm_signed_ff));
end if;
end process;
-- Loaded memory data
--
LMD_ff <= mem_data_in;
-- branch address, computed during the execution cycle.
--
proc_branch_addr_ff: process(clk, reset_n)
begin
if (reset_n = '0') then
branch_addr_ff <= (others => '0');
elsif (rising_edge(clk)) then
if cycle = execution then
branch_addr_ff <= std_logic_vector(signed(PC_ff) + shift_left(signed(Imm_signed_ff), 2));
end if;
end if;
end process;
-- writing to registers
--
reg_y_in <= ALU_out_a_ff;
reg_z_in <= ALU_out_b_ff;
-- Port y is Rd
-- Port z is R(d+1) unless d is 31
--
reg_sel_y <= reg_rd_sel;
reg_sel_z <= (others => '0') when unsigned(reg_rd_sel) = 31 else
std_logic_vector(unsigned(reg_rd_sel) + 1);
reg_write_y <= '1' when (cycle = write_back and
instr_writes_back and
unsigned(reg_rd_sel) /= 0)
else '0';
reg_write_z <= '1' when (cycle = write_back and
instr_result_dword and
unsigned(reg_rd_sel) /= 31)
else '0';
end;
|
-- CPU controller.
-- Main controller code of the CPU - fetching, decoding and
-- executing instructions.
--
-- Luz micro-controller implementation
-- Eli Bendersky (C) 2008-2010
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.cpu_defs.all;
use work.utils_pak.all;
-- The main CPU controller module.
--
entity controller is
port
(
clk: in std_logic;
reset_n: in std_logic;
-- memory interface
--
mem_read: out std_logic;
mem_write: out std_logic;
mem_bytesel: out std_logic_vector(3 downto 0);
mem_addr: out word;
mem_data_out: out word;
mem_ack: in std_logic;
mem_data_in: in word;
-- interface to the register file
--
reg_sel_a: out std_logic_vector(4 downto 0);
reg_a_out: in word;
reg_sel_b: out std_logic_vector(4 downto 0);
reg_b_out: in word;
reg_sel_c: out std_logic_vector(4 downto 0);
reg_c_out: in word;
reg_sel_y: out std_logic_vector(4 downto 0);
reg_write_y: out std_logic;
reg_y_in: out word;
reg_sel_z: out std_logic_vector(4 downto 0);
reg_write_z: out std_logic;
reg_z_in: out word;
-- interface to the ALU
--
alu_op: out cpu_opcode;
alu_rs_in: out word;
alu_rt_in: out word;
alu_rd_in: out word;
alu_imm_in: out word;
alu_output_a: in word;
alu_output_b: in word;
-- interface to the program counter
--
pc_in: out word;
pc_write: out std_logic;
pc_out: in word;
dummy: out std_logic
);
end controller;
architecture controller_arc of controller is
signal PC_ff, NPC_ff: word;
signal IR_ff: word;
signal Rs_ff, Rt_ff, Rd_ff: word;
signal Imm_unsigned_ff: word;
signal Imm_signed_ff: word;
signal ALU_out_a_ff: word;
signal ALU_out_b_ff: word;
signal LMD_ff: word;
signal OP_ff: cpu_opcode;
signal load_addr_ff: word;
signal store_addr_ff: word;
signal branch_addr_ff: word;
signal reg_rs_sel: std_logic_vector(4 downto 0);
signal reg_rt_sel: std_logic_vector(4 downto 0);
signal reg_rd_sel: std_logic_vector(4 downto 0);
-- CPU execution cycles:
--
-- out_of_reset:
--
type cycle_type is
(
halted,
out_of_reset,
fetch,
decode,
execution,
memory_access,
write_back
);
signal cycle: cycle_type;
signal instr_fetch: boolean;
signal instr_is_load: boolean;
signal instr_is_store: boolean;
signal instr_is_branch: boolean;
signal instr_writes_back: boolean;
signal instr_result_dword: boolean;
signal branch_is_taken: boolean;
begin
-- The main state machine process
--
proc_cycle: process(clk, reset_n)
begin
if (reset_n = '0') then
cycle <= out_of_reset;
elsif (rising_edge(clk)) then
case (cycle) is
when out_of_reset =>
cycle <= fetch;
-- When data is ready in mem_data_in, move to
-- the decoding cycle.
--
when fetch =>
if mem_ack = '1' then
cycle <= decode;
end if;
-- During the decoding cycle the instruction is
-- taken from IR and is decoded into its
-- constituents.
--
when decode =>
cycle <= execution;
-- During the execution cycle, the ALU does its
-- work on the arguments taken from registers.
--
when execution =>
cycle <= memory_access;
-- The memory access is for memory loads/stores.
--
when memory_access =>
if ( not (instr_is_store or instr_is_load) or
mem_ack = '1') then
cycle <= write_back;
end if;
when write_back =>
cycle <= fetch;
when halted =>
cycle <= halted;
when others =>
end case;
end if;
end process;
-- Updating the value of the program counter when in memory
-- access cycle. The value is either changed to a branch
-- address for branch instructions, or just advanced by 4 for
-- other instructions. ZZZ: what about JR?!
--
pc_write <= '1' when cycle = memory_access else '0';
pc_in <= branch_addr_ff when instr_is_branch and branch_is_taken else
std_logic_vector(unsigned(PC_ff) + 4);
-- Next PC
--
NPC_ff <= pc_out;
-- Stores the program counter for later usage
--
proc_PC_ff: process(clk, reset_n)
begin
if (reset_n = '0') then
PC_ff <= NPC_ff;
elsif (rising_edge(clk)) then
if cycle = fetch then
PC_ff <= NPC_ff;
end if;
end if;
end process;
-- Instruction fetch
--
instr_fetch <= cycle = fetch;
-- Helper signals for identifying instruction types
--
with OP_ff select
instr_is_load <= true when OP_LB | OP_LBU | OP_LH | OP_LHU | OP_LW,
false when others;
with OP_ff select
instr_is_store <= true when OP_SB | OP_SH | OP_SW,
false when others;
with OP_ff select
instr_is_branch <= true when OP_BEQ | OP_BNE | OP_BGE |
OP_BGT | OP_BLE | OP_BLT |
OP_BGEU | OP_BGTU |
OP_BLEU | OP_BLTU,
false when others;
-- instr_writes_back: an instruction that stores a result in
-- a register
--
with OP_ff select
instr_writes_back <= true when OP_ADD | OP_ADDI | OP_SUB |
OP_SUBI | OP_MULU | OP_MUL |
OP_DIVU | OP_DIV | OP_LUI |
OP_SLL | OP_SLLI | OP_SRL |
OP_SRLI | OP_AND | OP_ANDI |
OP_OR | OP_ORI | OP_NOR |
OP_XOR | OP_LB | OP_LBU |
OP_LH | OP_LHU | OP_LW |
OP_CALL,
false when others;
-- instr_result_dword: an instruction that produces a 64-bit
-- result
--
with OP_ff select
instr_result_dword <= true when OP_MUL | OP_MULU |
OP_DIV | OP_DIVU,
false when others;
branch_is_taken <= instr_is_branch and ALU_out_a_ff(0) = '1';
-- Read from memory when:
-- * fetching an instruction
-- * executing a load instruction
--
mem_read <= '1' when instr_fetch or
(cycle = memory_access and instr_is_load)
else '0';
-- Write to memory when executing a store instruction
--
mem_write <= '1' when cycle = memory_access and instr_is_store else '0';
-- Byte select lines depend on the width of the load/store
-- access. For instructions, words are fetched.
--
mem_bytesel <= "1111" when instr_fetch else
"0001" when OP_ff = OP_SB or OP_ff = OP_LB or OP_ff = OP_LBU else
"0011" when OP_ff = OP_SH or OP_ff = OP_LH or OP_ff = OP_LHU else
"1111" when OP_ff = OP_LW or OP_ff = OP_SW else
"0000";
-- Memory address
--
mem_addr <= NPC_ff when instr_fetch else
load_addr_ff when cycle = memory_access and instr_is_load else
store_addr_ff when cycle = memory_access and instr_is_store
else (others => '0');
-- Memory data in is taken from Rs in store instructions
--
mem_data_out <= Rs_ff;
-- The instruction register holds the current instruction
-- read from the memory.
-- Since the memory outputs are synchronous, IR_ff is just an
-- alias. It will be read only on rising_edge(clk), so it
-- really represents a register.
--
IR_ff <= mem_data_in;
-- The opcode
--
proc_OP_ff: process(clk, reset_n)
begin
if (reset_n = '0') then
OP_ff <= (others => '0');
elsif (rising_edge(clk)) then
OP_ff <= IR_ff(31 downto 26);
end if;
end process;
reg_rd_sel <= IR_ff(25 downto 21);
reg_rs_sel <= IR_ff(20 downto 16);
reg_rt_sel <= IR_ff(15 downto 11);
reg_sel_a <= reg_rd_sel;
reg_sel_b <= reg_rs_sel;
reg_sel_c <= reg_rt_sel;
-- The unsigned (zero-extended) and signed (sign-extended)
-- interpretations of the immediate value.
-- Both are delayed by a clock cycle to be ready in the same
-- cycle with the values of registers.
--
proc_Imm_ff: process(clk, reset_n)
begin
if (reset_n = '0') then
Imm_unsigned_ff <= (others => '0');
Imm_signed_ff <= (others => '0');
elsif (rising_edge(clk)) then
Imm_unsigned_ff <= std_logic_vector(resize(unsigned(IR_ff(15 downto 0)), 32));
Imm_signed_ff <= std_logic_vector(resize(signed(IR_ff(15 downto 0)), 32));
end if;
end process;
-- Contents of registers.
--
Rd_ff <= reg_a_out;
Rs_ff <= reg_b_out;
Rt_ff <= reg_c_out;
-- ALU arguments and outputs
--
alu_op <= OP_ff;
alu_rs_in <= Rs_ff;
alu_rt_in <= Rt_ff;
alu_rd_in <= Rd_ff;
alu_imm_in <= Imm_unsigned_ff;
ALU_out_a_ff <= alu_output_a;
ALU_out_b_ff <= alu_output_b;
-- load and store addresses, computed during the execution
-- cycle.
--
proc_load_addr_ff: process(clk, reset_n)
begin
if (reset_n = '0') then
load_addr_ff <= (others => '0');
elsif (rising_edge(clk)) then
load_addr_ff <= std_logic_vector(signed(Rs_ff) + signed(Imm_signed_ff));
end if;
end process;
proc_store_addr_ff: process(clk, reset_n)
begin
if (reset_n = '0') then
store_addr_ff <= (others => '0');
elsif (rising_edge(clk)) then
store_addr_ff <= std_logic_vector(signed(Rd_ff) + signed(Imm_signed_ff));
end if;
end process;
-- Loaded memory data
--
LMD_ff <= mem_data_in;
-- branch address, computed during the execution cycle.
--
proc_branch_addr_ff: process(clk, reset_n)
begin
if (reset_n = '0') then
branch_addr_ff <= (others => '0');
elsif (rising_edge(clk)) then
if cycle = execution then
branch_addr_ff <= std_logic_vector(signed(PC_ff) + shift_left(signed(Imm_signed_ff), 2));
end if;
end if;
end process;
-- writing to registers
--
reg_y_in <= ALU_out_a_ff;
reg_z_in <= ALU_out_b_ff;
-- Port y is Rd
-- Port z is R(d+1) unless d is 31
--
reg_sel_y <= reg_rd_sel;
reg_sel_z <= (others => '0') when unsigned(reg_rd_sel) = 31 else
std_logic_vector(unsigned(reg_rd_sel) + 1);
reg_write_y <= '1' when (cycle = write_back and
instr_writes_back and
unsigned(reg_rd_sel) /= 0)
else '0';
reg_write_z <= '1' when (cycle = write_back and
instr_result_dword and
unsigned(reg_rd_sel) /= 31)
else '0';
end;
|
entity sub is
port (
x : in integer;
y : out boolean );
end entity;
architecture test of sub is
begin
y <= x'delayed(5 ns) > x;
end architecture;
-------------------------------------------------------------------------------
entity implicit3 is
end entity;
architecture test of implicit3 is
signal x : integer := 0;
signal y : boolean;
begin
sub_i: entity work.sub
port map (x, y);
process is
begin
x <= 1;
wait for 1 ns;
assert not y;
wait for 5 ns;
assert not y;
x <= -1;
wait for 5 ns;
assert y;
wait;
end process;
end architecture;
|
entity sub is
port (
x : in integer;
y : out boolean );
end entity;
architecture test of sub is
begin
y <= x'delayed(5 ns) > x;
end architecture;
-------------------------------------------------------------------------------
entity implicit3 is
end entity;
architecture test of implicit3 is
signal x : integer := 0;
signal y : boolean;
begin
sub_i: entity work.sub
port map (x, y);
process is
begin
x <= 1;
wait for 1 ns;
assert not y;
wait for 5 ns;
assert not y;
x <= -1;
wait for 5 ns;
assert y;
wait;
end process;
end architecture;
|
entity sub is
port (
x : in integer;
y : out boolean );
end entity;
architecture test of sub is
begin
y <= x'delayed(5 ns) > x;
end architecture;
-------------------------------------------------------------------------------
entity implicit3 is
end entity;
architecture test of implicit3 is
signal x : integer := 0;
signal y : boolean;
begin
sub_i: entity work.sub
port map (x, y);
process is
begin
x <= 1;
wait for 1 ns;
assert not y;
wait for 5 ns;
assert not y;
x <= -1;
wait for 5 ns;
assert y;
wait;
end process;
end architecture;
|
entity sub is
port (
x : in integer;
y : out boolean );
end entity;
architecture test of sub is
begin
y <= x'delayed(5 ns) > x;
end architecture;
-------------------------------------------------------------------------------
entity implicit3 is
end entity;
architecture test of implicit3 is
signal x : integer := 0;
signal y : boolean;
begin
sub_i: entity work.sub
port map (x, y);
process is
begin
x <= 1;
wait for 1 ns;
assert not y;
wait for 5 ns;
assert not y;
x <= -1;
wait for 5 ns;
assert y;
wait;
end process;
end architecture;
|
entity sub is
port (
x : in integer;
y : out boolean );
end entity;
architecture test of sub is
begin
y <= x'delayed(5 ns) > x;
end architecture;
-------------------------------------------------------------------------------
entity implicit3 is
end entity;
architecture test of implicit3 is
signal x : integer := 0;
signal y : boolean;
begin
sub_i: entity work.sub
port map (x, y);
process is
begin
x <= 1;
wait for 1 ns;
assert not y;
wait for 5 ns;
assert not y;
x <= -1;
wait for 5 ns;
assert y;
wait;
end process;
end architecture;
|
-- (c) Copyright 1995-2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:dds_compiler:6.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY dds_compiler_v6_0;
USE dds_compiler_v6_0.dds_compiler_v6_0;
ENTITY dds IS
PORT (
aclk : IN STD_LOGIC;
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END dds;
ARCHITECTURE dds_arch OF dds IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF dds_arch: ARCHITECTURE IS "yes";
COMPONENT dds_compiler_v6_0 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_MODE_OF_OPERATION : INTEGER;
C_MODULUS : INTEGER;
C_ACCUMULATOR_WIDTH : INTEGER;
C_CHANNELS : INTEGER;
C_HAS_PHASE_OUT : INTEGER;
C_HAS_PHASEGEN : INTEGER;
C_HAS_SINCOS : INTEGER;
C_LATENCY : INTEGER;
C_MEM_TYPE : INTEGER;
C_NEGATIVE_COSINE : INTEGER;
C_NEGATIVE_SINE : INTEGER;
C_NOISE_SHAPING : INTEGER;
C_OUTPUTS_REQUIRED : INTEGER;
C_OUTPUT_FORM : INTEGER;
C_OUTPUT_WIDTH : INTEGER;
C_PHASE_ANGLE_WIDTH : INTEGER;
C_PHASE_INCREMENT : INTEGER;
C_PHASE_INCREMENT_VALUE : STRING;
C_RESYNC : INTEGER;
C_PHASE_OFFSET : INTEGER;
C_PHASE_OFFSET_VALUE : STRING;
C_OPTIMISE_GOAL : INTEGER;
C_USE_DSP48 : INTEGER;
C_POR_MODE : INTEGER;
C_AMPLITUDE : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_HAS_TLAST : INTEGER;
C_HAS_TREADY : INTEGER;
C_HAS_S_PHASE : INTEGER;
C_S_PHASE_TDATA_WIDTH : INTEGER;
C_S_PHASE_HAS_TUSER : INTEGER;
C_S_PHASE_TUSER_WIDTH : INTEGER;
C_HAS_S_CONFIG : INTEGER;
C_S_CONFIG_SYNC_MODE : INTEGER;
C_S_CONFIG_TDATA_WIDTH : INTEGER;
C_HAS_M_DATA : INTEGER;
C_M_DATA_TDATA_WIDTH : INTEGER;
C_M_DATA_HAS_TUSER : INTEGER;
C_M_DATA_TUSER_WIDTH : INTEGER;
C_HAS_M_PHASE : INTEGER;
C_M_PHASE_TDATA_WIDTH : INTEGER;
C_M_PHASE_HAS_TUSER : INTEGER;
C_M_PHASE_TUSER_WIDTH : INTEGER;
C_DEBUG_INTERFACE : INTEGER;
C_CHAN_WIDTH : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_phase_tvalid : IN STD_LOGIC;
s_axis_phase_tready : OUT STD_LOGIC;
s_axis_phase_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_phase_tlast : IN STD_LOGIC;
s_axis_phase_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_config_tlast : IN STD_LOGIC;
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tready : IN STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
m_axis_data_tlast : OUT STD_LOGIC;
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_phase_tvalid : OUT STD_LOGIC;
m_axis_phase_tready : IN STD_LOGIC;
m_axis_phase_tdata : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_phase_tlast : OUT STD_LOGIC;
m_axis_phase_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
event_pinc_invalid : OUT STD_LOGIC;
event_poff_invalid : OUT STD_LOGIC;
event_phase_in_invalid : OUT STD_LOGIC;
event_s_phase_tlast_missing : OUT STD_LOGIC;
event_s_phase_tlast_unexpected : OUT STD_LOGIC;
event_s_phase_chanid_incorrect : OUT STD_LOGIC;
event_s_config_tlast_missing : OUT STD_LOGIC;
event_s_config_tlast_unexpected : OUT STD_LOGIC
);
END COMPONENT dds_compiler_v6_0;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
BEGIN
U0 : dds_compiler_v6_0
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_MODE_OF_OPERATION => 0,
C_MODULUS => 9,
C_ACCUMULATOR_WIDTH => 45,
C_CHANNELS => 5,
C_HAS_PHASE_OUT => 0,
C_HAS_PHASEGEN => 1,
C_HAS_SINCOS => 1,
C_LATENCY => 3,
C_MEM_TYPE => 1,
C_NEGATIVE_COSINE => 0,
C_NEGATIVE_SINE => 0,
C_NOISE_SHAPING => 0,
C_OUTPUTS_REQUIRED => 2,
C_OUTPUT_FORM => 0,
C_OUTPUT_WIDTH => 8,
C_PHASE_ANGLE_WIDTH => 8,
C_PHASE_INCREMENT => 2,
C_PHASE_INCREMENT_VALUE => "100000000000000000000000000000000000,1000000000000000000000000000000000000,10000000000000000000000000000000000000,100000000000000000000000000000000000000,1000000000000000000000000000000000000000,0,0,0,0,0,0,0,0,0,0,0",
C_RESYNC => 0,
C_PHASE_OFFSET => 0,
C_PHASE_OFFSET_VALUE => "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0",
C_OPTIMISE_GOAL => 0,
C_USE_DSP48 => 0,
C_POR_MODE => 0,
C_AMPLITUDE => 0,
C_HAS_ACLKEN => 0,
C_HAS_ARESETN => 0,
C_HAS_TLAST => 0,
C_HAS_TREADY => 0,
C_HAS_S_PHASE => 0,
C_S_PHASE_TDATA_WIDTH => 1,
C_S_PHASE_HAS_TUSER => 0,
C_S_PHASE_TUSER_WIDTH => 1,
C_HAS_S_CONFIG => 0,
C_S_CONFIG_SYNC_MODE => 0,
C_S_CONFIG_TDATA_WIDTH => 1,
C_HAS_M_DATA => 1,
C_M_DATA_TDATA_WIDTH => 16,
C_M_DATA_HAS_TUSER => 0,
C_M_DATA_TUSER_WIDTH => 1,
C_HAS_M_PHASE => 0,
C_M_PHASE_TDATA_WIDTH => 1,
C_M_PHASE_HAS_TUSER => 0,
C_M_PHASE_TUSER_WIDTH => 1,
C_DEBUG_INTERFACE => 0,
C_CHAN_WIDTH => 3
)
PORT MAP (
aclk => aclk,
aclken => '1',
aresetn => '1',
s_axis_phase_tvalid => '0',
s_axis_phase_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_phase_tlast => '0',
s_axis_phase_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_config_tvalid => '0',
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_config_tlast => '0',
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tready => '0',
m_axis_data_tdata => m_axis_data_tdata,
m_axis_phase_tready => '0'
);
END dds_arch;
|
-------------------------------------------------------------------------------
-- axi_sg_ftch_mngr
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_mngr.vhd
-- Description: This entity manages fetching of descriptors.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 7/20/10 v1_00_a
-- ^^^^^^
-- CR568950
-- Qualified reseting of sg_idle from axi_sg_ftch_pntr with associated channel's
-- flush control.
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Rolled axi_sg library version to version v2_00_a
-- ~~~~~~
-- GAB 10/21/10 v4_03
-- ^^^^^^
-- Rolled version to v4_03
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2;
use axi_vdma_v6_2.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_ftch_mngr is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_SG_CH1_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch for channel 1
C_SG_CH2_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch for channel 1
C_SG_FTCH_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_CH1_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_SG_CH2_ENBL_STALE_ERROR : integer range 0 to 1 := 1
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Channel 1 Control and Status --
ch1_run_stop : in std_logic ; --
ch1_desc_flush : in std_logic ; --
ch1_updt_done : in std_logic ; --
ch1_ftch_idle : out std_logic ; --
ch1_ftch_active : out std_logic ; --
ch1_ftch_interr_set : out std_logic ; --
ch1_ftch_slverr_set : out std_logic ; --
ch1_ftch_decerr_set : out std_logic ; --
ch1_ftch_err_early : out std_logic ; --
ch1_ftch_stale_desc : out std_logic ; --
ch1_tailpntr_enabled : in std_logic ; --
ch1_taildesc_wren : in std_logic ; --
ch1_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_nxtdesc_wren : in std_logic ; --
ch1_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_ftch_queue_empty : in std_logic ; --
ch1_ftch_queue_full : in std_logic ; --
ch1_ftch_pause : in std_logic ; --
--
-- Channel 2 Control and Status --
ch2_run_stop : in std_logic ; --
ch2_updt_done : in std_logic ; --
ch2_desc_flush : in std_logic ; --
ch2_ftch_idle : out std_logic ; --
ch2_ftch_active : out std_logic ; --
ch2_ftch_interr_set : out std_logic ; --
ch2_ftch_slverr_set : out std_logic ; --
ch2_ftch_decerr_set : out std_logic ; --
ch2_ftch_err_early : out std_logic ; --
ch2_ftch_stale_desc : out std_logic ; --
ch2_tailpntr_enabled : in std_logic ; --
ch2_taildesc_wren : in std_logic ; --
ch2_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_nxtdesc_wren : in std_logic ; --
ch2_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_ftch_queue_empty : in std_logic ; --
ch2_ftch_queue_full : in std_logic ; --
ch2_ftch_pause : in std_logic ; --
--
nxtdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- Read response for detecting slverr, decerr early --
m_axi_sg_rresp : in std_logic_vector(1 downto 0) ; --
m_axi_sg_rvalid : in std_logic ; --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_ftch_cmd_tvalid : out std_logic ; --
s_axis_ftch_cmd_tready : in std_logic ; --
s_axis_ftch_cmd_tdata : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_ftch_sts_tvalid : in std_logic ; --
m_axis_ftch_sts_tready : out std_logic ; --
m_axis_ftch_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_ftch_sts_tkeep : in std_logic_vector(0 downto 0) ; --
mm2s_err : in std_logic ; --
--
--
ftch_cmnd_wr : out std_logic ; --
ftch_cmnd_data : out std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
ftch_stale_desc : in std_logic ; --
updt_error : in std_logic ; --
ftch_error : out std_logic ; --
ftch_error_addr : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) --
);
end axi_sg_ftch_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ftch_cmnd_wr_i : std_logic := '0';
signal ftch_cmnd_data_i : std_logic_vector
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0)
:= (others => '0');
signal ch1_sg_idle : std_logic := '0';
signal ch1_fetch_address : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0)
:= (others => '0');
signal ch2_sg_idle : std_logic := '0';
signal ch2_fetch_address : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0)
:= (others => '0');
signal ftch_done : std_logic := '0';
signal ftch_error_i : std_logic := '0';
signal ftch_interr : std_logic := '0';
signal ftch_slverr : std_logic := '0';
signal ftch_decerr : std_logic := '0';
signal ftch_error_early : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
ftch_cmnd_wr <= ftch_cmnd_wr_i;
ftch_cmnd_data <= ftch_cmnd_data_i;
ftch_error <= ftch_error_i;
-------------------------------------------------------------------------------
-- Scatter Gather Fetch State Machine
-------------------------------------------------------------------------------
I_FTCH_SG : entity axi_vdma_v6_2.axi_sg_ftch_sm
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2 ,
C_SG_CH1_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH ,
C_SG_CH2_WORDS_TO_FETCH => C_SG_CH2_WORDS_TO_FETCH ,
C_SG_FTCH_DESC2QUEUE => C_SG_FTCH_DESC2QUEUE ,
C_SG_CH1_ENBL_STALE_ERROR => C_SG_CH1_ENBL_STALE_ERROR ,
C_SG_CH2_ENBL_STALE_ERROR => C_SG_CH2_ENBL_STALE_ERROR
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
updt_error => updt_error ,
-- Channel 1 Control and Status
ch1_run_stop => ch1_run_stop ,
ch1_updt_done => ch1_updt_done ,
ch1_desc_flush => ch1_desc_flush ,
ch1_sg_idle => ch1_sg_idle ,
ch1_tailpntr_enabled => ch1_tailpntr_enabled ,
ch1_ftch_queue_empty => ch1_ftch_queue_empty ,
ch1_ftch_queue_full => ch1_ftch_queue_full ,
ch1_fetch_address => ch1_fetch_address ,
ch1_ftch_active => ch1_ftch_active ,
ch1_ftch_idle => ch1_ftch_idle ,
ch1_ftch_interr_set => ch1_ftch_interr_set ,
ch1_ftch_slverr_set => ch1_ftch_slverr_set ,
ch1_ftch_decerr_set => ch1_ftch_decerr_set ,
ch1_ftch_err_early => ch1_ftch_err_early ,
ch1_ftch_stale_desc => ch1_ftch_stale_desc ,
ch1_ftch_pause => ch1_ftch_pause ,
-- Channel 2 Control and Status
ch2_run_stop => ch2_run_stop ,
ch2_updt_done => ch2_updt_done ,
ch2_desc_flush => ch2_desc_flush ,
ch2_sg_idle => ch2_sg_idle ,
ch2_tailpntr_enabled => ch2_tailpntr_enabled ,
ch2_ftch_queue_empty => ch2_ftch_queue_empty ,
ch2_ftch_queue_full => ch2_ftch_queue_full ,
ch2_fetch_address => ch2_fetch_address ,
ch2_ftch_active => ch2_ftch_active ,
ch2_ftch_idle => ch2_ftch_idle ,
ch2_ftch_interr_set => ch2_ftch_interr_set ,
ch2_ftch_slverr_set => ch2_ftch_slverr_set ,
ch2_ftch_decerr_set => ch2_ftch_decerr_set ,
ch2_ftch_err_early => ch2_ftch_err_early ,
ch2_ftch_stale_desc => ch2_ftch_stale_desc ,
ch2_ftch_pause => ch2_ftch_pause ,
-- Transfer Request
ftch_cmnd_wr => ftch_cmnd_wr_i ,
ftch_cmnd_data => ftch_cmnd_data_i ,
-- Transfer Status
ftch_done => ftch_done ,
ftch_error => ftch_error_i ,
ftch_interr => ftch_interr ,
ftch_slverr => ftch_slverr ,
ftch_decerr => ftch_decerr ,
ftch_stale_desc => ftch_stale_desc ,
ftch_error_addr => ftch_error_addr ,
ftch_error_early => ftch_error_early
);
-------------------------------------------------------------------------------
-- Scatter Gather Fetch Pointer Manager
-------------------------------------------------------------------------------
I_FTCH_PNTR_MNGR : entity axi_vdma_v6_2.axi_sg_ftch_pntr
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_INCLUDE_CH1 => C_INCLUDE_CH1 ,
C_INCLUDE_CH2 => C_INCLUDE_CH2
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
nxtdesc => nxtdesc ,
-------------------------------
-- CHANNEL 1
-------------------------------
ch1_run_stop => ch1_run_stop ,
ch1_desc_flush => ch1_desc_flush ,--CR568950
-- CURDESC update on run/stop assertion (from ftch_sm)
ch1_curdesc => ch1_curdesc ,
-- TAILDESC update on CPU write (from axi_dma_reg_module)
ch1_tailpntr_enabled => ch1_tailpntr_enabled ,
ch1_taildesc_wren => ch1_taildesc_wren ,
ch1_taildesc => ch1_taildesc ,
-- NXTDESC update on descriptor fetch (from axi_sg_ftchq_if)
ch1_nxtdesc_wren => ch1_nxtdesc_wren ,
-- Current address of descriptor to fetch
ch1_fetch_address => ch1_fetch_address ,
ch1_sg_idle => ch1_sg_idle ,
-------------------------------
-- CHANNEL 2
-------------------------------
ch2_run_stop => ch2_run_stop ,
ch2_desc_flush => ch2_desc_flush ,--CR568950
-- CURDESC update on run/stop assertion (from ftch_sm)
ch2_curdesc => ch2_curdesc ,
-- TAILDESC update on CPU write (from axi_dma_reg_module)
ch2_tailpntr_enabled => ch2_tailpntr_enabled ,
ch2_taildesc_wren => ch2_taildesc_wren ,
ch2_taildesc => ch2_taildesc ,
-- NXTDESC update on descriptor fetch (from axi_sg_ftchq_if)
ch2_nxtdesc_wren => ch2_nxtdesc_wren ,
-- Current address of descriptor to fetch
ch2_fetch_address => ch2_fetch_address ,
ch2_sg_idle => ch2_sg_idle
);
-------------------------------------------------------------------------------
-- Scatter Gather Fetch Command / Status Interface
-------------------------------------------------------------------------------
I_FTCH_CMDSTS_IF : entity axi_vdma_v6_2.axi_sg_ftch_cmdsts_if
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Fetch command write interface from fetch sm
ftch_cmnd_wr => ftch_cmnd_wr_i ,
ftch_cmnd_data => ftch_cmnd_data_i ,
-- Read response for detecting slverr, decerr early
m_axi_sg_rresp => m_axi_sg_rresp ,
m_axi_sg_rvalid => m_axi_sg_rvalid ,
-- User Command Interface Ports (AXI Stream)
s_axis_ftch_cmd_tvalid => s_axis_ftch_cmd_tvalid ,
s_axis_ftch_cmd_tready => s_axis_ftch_cmd_tready ,
s_axis_ftch_cmd_tdata => s_axis_ftch_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_ftch_sts_tvalid => m_axis_ftch_sts_tvalid ,
m_axis_ftch_sts_tready => m_axis_ftch_sts_tready ,
m_axis_ftch_sts_tdata => m_axis_ftch_sts_tdata ,
m_axis_ftch_sts_tkeep => m_axis_ftch_sts_tkeep ,
-- Scatter Gather Fetch Status
mm2s_err => mm2s_err ,
ftch_done => ftch_done ,
ftch_error => ftch_error_i ,
ftch_interr => ftch_interr ,
ftch_slverr => ftch_slverr ,
ftch_decerr => ftch_decerr ,
ftch_error_early => ftch_error_early
);
end implementation;
|
-----------------------------------------------------------------------------------------------------------
--
-- INTEGER OPERAND SQUARE ROOT EXTRACTION
--
-- Created by Claudio Brunelli, 2003
--
-----------------------------------------------------------------------------------------------------------
--Copyright (c) 2004, Tampere University of Technology.
--All rights reserved.
--Redistribution and use in source and binary forms, with or without modification,
--are permitted provided that the following conditions are met:
--* Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--* Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
--* Neither the name of Tampere University of Technology nor the names of its
-- contributors may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--THIS HARDWARE DESCRIPTION OR SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
--CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
--LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND NONINFRINGEMENT AND
--FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
--OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
--EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
--PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
--BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--ARISING IN ANY WAY OUT OF THE USE OF THIS HARDWARE DESCRIPTION OR SOFTWARE, EVEN
--IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.cop_definitions.all;
use work.cop_components.all;
entity integer_sqrt is
port( clk : in std_logic;
reset : in std_logic;
input : in std_logic_vector(radicand_width-1 downto 0);
output : out std_logic_vector(sqrt_width-1 downto 0);
remainder : out std_logic_vector(rem_width-1 downto 0) );
end integer_sqrt ;
-------------------------------------------------------------------------------
architecture rtl of integer_sqrt is
type int_bus is array (k_max downto 0) of integer;
type vector_bus is array (k_max-1 downto 0) of std_logic_vector(rem_width+1 downto 0);
type unsigned_bus is array (k_max-1 downto 0) of unsigned(sqrt_width+1 downto 0);
signal q, r : int_bus;
signal vector_r : vector_bus;
signal unsigned_q : unsigned_bus;
signal q01 : integer;
signal vector_q0 : std_logic_vector(sqrt_width-1 downto 0);
signal converted_q22,
converted_q17,
converted_q12,
converted_q7,
converted_q2 : std_logic_vector(sqrt_width+2 downto 0);
signal converted_r22,
converted_r17,
converted_r12,
converted_r7,
converted_r2 : std_logic_vector(rem_width+2 downto 0);
signal pipelined_q22,
pipelined_q17,
pipelined_q12,
pipelined_q7,
pipelined_q2 : std_logic_vector(sqrt_width+2 downto 0);
signal pipelined_r22,
pipelined_r17,
pipelined_r12,
pipelined_r7,
pipelined_r2 : std_logic_vector(rem_width+2 downto 0);
signal integer_q22,
integer_q17,
integer_q12,
integer_q7,
integer_q2 : integer;
signal integer_r22,
integer_r17,
integer_r12,
integer_r7,
integer_r2 : integer;
signal input43_34,
input33_24,
input23_14,
input13_4 : std_logic_vector(9 downto 0);
signal input3_0 : std_logic_vector(3 downto 0);
signal delayed_input43_34,
delayed_input33_24,
delayed_input23_14,
delayed_input13_4 : std_logic_vector(9 downto 0);
signal delayed_input3_0 : std_logic_vector(3 downto 0);
signal fixed_enable : std_logic;
begin
-----------------------------------------------------------------------------------------------------------------
fixed_enable <= '1';
q(k_max) <= 0; -- q(26) value
r(k_max) <= 0; -- r(26) value
input43_34 <= input(43 downto 34);
input33_24 <= input(33 downto 24);
input23_14 <= input(23 downto 14);
input13_4 <= input(13 downto 4);
input3_0 <= input(3 downto 0);
INPUT43_34_PIPELINE: simple_register_chain
generic map (length => 1, width => 10)
port map ( clk => clk, reset => reset, enable => fixed_enable, reg_chain_in => input43_34 , reg_chain_out => delayed_input43_34);
INPUT33_24_PIPELINE: simple_register_chain
generic map (length => 2, width => 10)
port map ( clk => clk, reset => reset, enable => fixed_enable, reg_chain_in => input33_24 , reg_chain_out => delayed_input33_24);
INPUT23_14_PIPELINE: simple_register_chain
generic map (length => 3, width => 10)
port map ( clk => clk, reset => reset, enable => fixed_enable, reg_chain_in => input23_14 , reg_chain_out => delayed_input23_14);
INPUT13_4_PIPELINE: simple_register_chain
generic map (length => 4, width => 10)
port map ( clk => clk, reset => reset, enable => fixed_enable, reg_chain_in => input13_4 , reg_chain_out => delayed_input13_4);
INPUT3_0_PIPELINE: simple_register_chain
generic map (length => 5, width => 4)
port map ( clk => clk, reset => reset, enable => fixed_enable, reg_chain_in => input3_0 , reg_chain_out => delayed_input3_0);
-- k = k_max-1 = 25
process(r, input, vector_r, q)
begin
vector_r(25) <= ( (conv_std_logic_vector(r(26), rem_width)) & input(51) & input(50) ); -- va da 3 a 1
unsigned_q(25) <= ( conv_unsigned( q(26), sqrt_width) & "01" ); -- vale 1 !!!
r(25) <= ( conv_integer(signed(vector_r(25))) - 1 ); -- sicuramente > o = a 0 ( va da 2 a 0)
q(25) <= 1;
end process;
-------------------------------------------------------
-- k = k_max-1 = 24
process(r, input, q, vector_r, unsigned_q)
begin
vector_r(24) <= ( (conv_std_logic_vector(r(25), rem_width)) & input(49) & input(48) );
if ( r(25) >= 0 ) then
unsigned_q(24) <= ( conv_unsigned(q(25), sqrt_width) & "01" );
r(24) <= ( conv_integer(signed(vector_r(24))) - conv_integer(unsigned_q(24)) );
else
unsigned_q(24) <= ( conv_unsigned(q(25), sqrt_width) & "11" );
r(24) <= ( conv_integer(signed(vector_r(24))) + conv_integer(unsigned_q(24)) );
end if;
if ( r(24) >= 0 ) then
q(24) <= conv_integer( unsigned(unsigned_q(24)(k_max downto 2) & '1') );
else
q(24) <= conv_integer( unsigned(unsigned_q(24)(k_max downto 2) & '0') );
end if;
end process;
-------------------------------------------------------
-- k = k_max-1 = 23
process(r, input, q, vector_r, unsigned_q)
begin
vector_r(23) <= ( (conv_std_logic_vector(r(24), rem_width)) & input(47) & input(46) );
if ( r(24) >= 0 ) then
unsigned_q(23) <= ( conv_unsigned(q(24), sqrt_width) & "01" );
r(23) <= ( conv_integer(signed(vector_r(23))) - conv_integer(unsigned_q(23)) );
else
unsigned_q(23) <= ( conv_unsigned(q(24), sqrt_width) & "11" );
r(23) <= ( conv_integer(signed(vector_r(23))) + conv_integer(unsigned_q(23)) );
end if;
if ( r(23) >= 0 ) then
q(23) <= conv_integer( unsigned(unsigned_q(23)(k_max downto 2) & '1') );
else
q(23) <= conv_integer( unsigned(unsigned_q(23)(k_max downto 2) & '0') );
end if;
end process;
-------------------------------------------------------
-- k = k_max-1 = 22
process(r, input, q, vector_r, unsigned_q)
begin
vector_r(22) <= ( (conv_std_logic_vector(r(23), rem_width)) & input(45) & input(44) ); -- 30 bit
if ( r(23) >= 0 ) then
unsigned_q(22) <= ( conv_unsigned(q(23), sqrt_width) & "01" ); -- 28 bit
r(22) <= ( conv_integer(signed(vector_r(22))) - conv_integer(unsigned_q(22)) );
else
unsigned_q(22) <= ( conv_unsigned(q(23), sqrt_width) & "11" );
r(22) <= ( conv_integer(signed(vector_r(22))) + conv_integer(unsigned_q(22)) );
end if;
if ( r(22) >= 0 ) then
q(22) <= conv_integer( unsigned(unsigned_q(22)(k_max downto 2) & '1') );
else
q(22) <= conv_integer( unsigned(unsigned_q(22)(k_max downto 2) & '0') );
end if;
end process;
converted_q22 <= conv_std_logic_vector(q(22), sqrt_width+3);
converted_r22 <= conv_std_logic_vector(r(22), rem_width+3);
Q22_PIPELINE_REG: data_register generic map (reg_width => sqrt_width+3)
port map (clk => clk, reset => reset, data_in => converted_q22, data_out => pipelined_q22);
R22_PIPELINE_REG: data_register generic map (reg_width => rem_width+3)
port map (clk => clk, reset => reset, data_in => converted_r22, data_out => pipelined_r22);
integer_q22 <= conv_integer( signed(pipelined_q22) );
integer_r22 <= conv_integer( signed(pipelined_r22) );
-------------------------------------------------------
-- k = k_max-1 = 21
process(r, integer_r22, delayed_input43_34, integer_q22, vector_r, unsigned_q)
begin
vector_r(21) <= ( (conv_std_logic_vector(integer_r22, rem_width)) & delayed_input43_34(9) & delayed_input43_34(8) );
if ( integer_r22 >= 0 ) then
unsigned_q(21) <= ( conv_unsigned(integer_q22, sqrt_width) & "01" );
r(21) <= ( conv_integer(signed(vector_r(21))) - conv_integer(unsigned_q(21)) );
else
unsigned_q(21) <= ( conv_unsigned(integer_q22, sqrt_width) & "11" );
r(21) <= ( conv_integer(signed(vector_r(21))) + conv_integer(unsigned_q(21)) );
end if;
if ( r(21) >= 0 ) then
q(21) <= conv_integer( unsigned(unsigned_q(21)(k_max downto 2) & '1') );
else
q(21) <= conv_integer( unsigned(unsigned_q(21)(k_max downto 2) & '0') );
end if;
end process;
-------------------------------------------------------
-- k = k_max-1 = 20
process(r, delayed_input43_34, q, vector_r, unsigned_q)
begin
vector_r(20) <= ( (conv_std_logic_vector(r(21), rem_width)) & delayed_input43_34(7) & delayed_input43_34(6) );
if ( r(21) >= 0 ) then
unsigned_q(20) <= ( conv_unsigned(q(21), sqrt_width) & "01" );
r(20) <= ( conv_integer(signed(vector_r(20))) - conv_integer(unsigned_q(20)) );
else
unsigned_q(20) <= ( conv_unsigned(q(21), sqrt_width) & "11" );
r(20) <= ( conv_integer(signed(vector_r(20))) + conv_integer(unsigned_q(20)) );
end if;
if ( r(20) >= 0 ) then
q(20) <= conv_integer( unsigned(unsigned_q(20)(k_max downto 2) & '1') );
else
q(20) <= conv_integer( unsigned(unsigned_q(20)(k_max downto 2) & '0') );
end if;
end process;
-------------------------------------------------------
-- k = k_max-1 = 19
process(r, delayed_input43_34, q, vector_r, unsigned_q)
begin
vector_r(19) <= ( (conv_std_logic_vector(r(20), rem_width)) & delayed_input43_34(5) & delayed_input43_34(4) );
if ( r(20) >= 0 ) then
unsigned_q(19) <= ( conv_unsigned(q(20), sqrt_width) & "01" );
r(19) <= ( conv_integer(signed(vector_r(19))) - conv_integer(unsigned_q(19)) );
else
unsigned_q(19) <= ( conv_unsigned(q(20), sqrt_width) & "11" );
r(19) <= ( conv_integer(signed(vector_r(19))) + conv_integer(unsigned_q(19)) );
end if;
if ( r(19) >= 0 ) then
q(19) <= conv_integer( unsigned(unsigned_q(19)(k_max downto 2) & '1') );
else
q(19) <= conv_integer( unsigned(unsigned_q(19)(k_max downto 2) & '0') );
end if;
end process;
-------------------------------------------------------
-- k = k_max-1 = 18
process(r, delayed_input43_34, q, vector_r, unsigned_q)
begin
vector_r(18) <= ( (conv_std_logic_vector(r(19), rem_width)) & delayed_input43_34(3) & delayed_input43_34(2) );
if ( r(19) >= 0 ) then
unsigned_q(18) <= ( conv_unsigned(q(19), sqrt_width) & "01" );
r(18) <= ( conv_integer(signed(vector_r(18))) - conv_integer(unsigned_q(18)) );
else
unsigned_q(18) <= ( conv_unsigned(q(19), sqrt_width) & "11" );
r(18) <= ( conv_integer(signed(vector_r(18))) + conv_integer(unsigned_q(18)) );
end if;
if ( r(18) >= 0 ) then
q(18) <= conv_integer( unsigned(unsigned_q(18)(k_max downto 2) & '1') );
else
q(18) <= conv_integer( unsigned(unsigned_q(18)(k_max downto 2) & '0') );
end if;
end process;
-------------------------------------------------------
-- k = k_max-1 = 17
process(r, delayed_input43_34, q, vector_r, unsigned_q)
begin
vector_r(17) <= ( (conv_std_logic_vector(r(18), rem_width)) & delayed_input43_34(1) & delayed_input43_34(0) );
if ( r(18) >= 0 ) then
unsigned_q(17) <= ( conv_unsigned(q(18), sqrt_width) & "01" );
r(17) <= ( conv_integer(signed(vector_r(17))) - conv_integer(unsigned_q(17)) );
else
unsigned_q(17) <= ( conv_unsigned(q(18), sqrt_width) & "11" );
r(17) <= ( conv_integer(signed(vector_r(17))) + conv_integer(unsigned_q(17)) );
end if;
if ( r(17) >= 0 ) then
q(17) <= conv_integer( unsigned(unsigned_q(17)(k_max downto 2) & '1') );
else
q(17) <= conv_integer( unsigned(unsigned_q(17)(k_max downto 2) & '0') );
end if;
end process;
converted_q17 <= conv_std_logic_vector(q(17), sqrt_width+3);
converted_r17 <= conv_std_logic_vector(r(17), rem_width+3);
Q17_PIPELINE_REG: data_register generic map (reg_width => sqrt_width+3)
port map (clk => clk, reset => reset, data_in => converted_q17, data_out => pipelined_q17);
R17_PIPELINE_REG: data_register generic map (reg_width => rem_width+3)
port map (clk => clk, reset => reset, data_in => converted_r17, data_out => pipelined_r17);
integer_q17 <= conv_integer( signed(pipelined_q17) );
integer_r17 <= conv_integer( signed(pipelined_r17) );
-------------------------------------------------------
-- k = k_max-1 = 16
process(r, integer_r17, delayed_input33_24, integer_q17, vector_r, unsigned_q)
begin
vector_r(16) <= ( (conv_std_logic_vector(integer_r17, rem_width)) & delayed_input33_24(9) & delayed_input33_24(8) );
if ( integer_r17 >= 0 ) then
unsigned_q(16) <= ( conv_unsigned(integer_q17, sqrt_width) & "01" );
r(16) <= ( conv_integer(signed(vector_r(16))) - conv_integer(unsigned_q(16)) );
else
unsigned_q(16) <= ( conv_unsigned(integer_q17, sqrt_width) & "11" );
r(16) <= ( conv_integer(signed(vector_r(16))) + conv_integer(unsigned_q(16)) );
end if;
if ( r(16) >= 0 ) then
q(16) <= conv_integer( unsigned(unsigned_q(16)(k_max downto 2) & '1') );
else
q(16) <= conv_integer( unsigned(unsigned_q(16)(k_max downto 2) & '0') );
end if;
end process;
-------------------------------------------------------
-- k = k_max-1 = 15
process(r, delayed_input33_24, q, vector_r, unsigned_q)
begin
vector_r(15) <= ( (conv_std_logic_vector(r(16), rem_width)) & delayed_input33_24(7) & delayed_input33_24(6) );
if ( r(16) >= 0 ) then
unsigned_q(15) <= ( conv_unsigned(q(16), sqrt_width) & "01" );
r(15) <= ( conv_integer(signed(vector_r(15))) - conv_integer(unsigned_q(15)) );
else
unsigned_q(15) <= ( conv_unsigned(q(16), sqrt_width) & "11" );
r(15) <= ( conv_integer(signed(vector_r(15))) + conv_integer(unsigned_q(15)) );
end if;
if ( r(15) >= 0 ) then
q(15) <= conv_integer( unsigned(unsigned_q(15)(k_max downto 2) & '1') );
else
q(15) <= conv_integer( unsigned(unsigned_q(15)(k_max downto 2) & '0') );
end if;
end process;
-------------------------------------------------------
-- k = k_max-1 = 14
process(r, delayed_input33_24, q, vector_r, unsigned_q)
begin
vector_r(14) <= ( (conv_std_logic_vector(r(15), rem_width)) & delayed_input33_24(5) & delayed_input33_24(4) );
if ( r(15) >= 0 ) then
unsigned_q(14) <= ( conv_unsigned(q(15), sqrt_width) & "01" );
r(14) <= ( conv_integer(signed(vector_r(14))) - conv_integer(unsigned_q(14)) );
else
unsigned_q(14) <= ( conv_unsigned(q(15), sqrt_width) & "11" );
r(14) <= ( conv_integer(signed(vector_r(14))) + conv_integer(unsigned_q(14)) );
end if;
if ( r(14) >= 0 ) then
q(14) <= conv_integer( unsigned(unsigned_q(14)(k_max downto 2) & '1') );
else
q(14) <= conv_integer( unsigned(unsigned_q(14)(k_max downto 2) & '0') );
end if;
end process;
-------------------------------------------------------
-- k = k_max-1 = 13
process(r, delayed_input33_24, q, vector_r, unsigned_q)
begin
vector_r(13) <= ( (conv_std_logic_vector(r(14), rem_width)) & delayed_input33_24(3) & delayed_input33_24(2) );
if ( r(14) >= 0 ) then
unsigned_q(13) <= ( conv_unsigned(q(14), sqrt_width) & "01" );
r(13) <= ( conv_integer(signed(vector_r(13))) - conv_integer(unsigned_q(13)) );
else
unsigned_q(13) <= ( conv_unsigned(q(14), sqrt_width) & "11" );
r(13) <= ( conv_integer(signed(vector_r(13))) + conv_integer(unsigned_q(13)) );
end if;
if ( r(13) >= 0 ) then
q(13) <= conv_integer( unsigned(unsigned_q(13)(k_max downto 2) & '1') );
else
q(13) <= conv_integer( unsigned(unsigned_q(13)(k_max downto 2) & '0') );
end if;
end process;
-------------------------------------------------------
-- k = k_max-1 = 12
process(r, delayed_input33_24, q, vector_r, unsigned_q)
begin
vector_r(12) <= ( (conv_std_logic_vector(r(13), rem_width)) & delayed_input33_24(1) & delayed_input33_24(0) );
if ( r(13) >= 0 ) then
unsigned_q(12) <= ( conv_unsigned(q(13), sqrt_width) & "01" );
r(12) <= ( conv_integer(signed(vector_r(12))) - conv_integer(unsigned_q(12)) );
else
unsigned_q(12) <= ( conv_unsigned(q(13), sqrt_width) & "11" );
r(12) <= ( conv_integer(signed(vector_r(12))) + conv_integer(unsigned_q(12)) );
end if;
if ( r(12) >= 0 ) then
q(12) <= conv_integer( unsigned(unsigned_q(12)(k_max downto 2) & '1') );
else
q(12) <= conv_integer( unsigned(unsigned_q(12)(k_max downto 2) & '0') );
end if;
end process;
converted_q12 <= conv_std_logic_vector(q(12), sqrt_width+3);
converted_r12 <= conv_std_logic_vector(r(12), rem_width+3);
Q12_PIPELINE_REG: data_register generic map (reg_width => sqrt_width+3)
port map (clk => clk, reset => reset, data_in => converted_q12, data_out => pipelined_q12);
R12_PIPELINE_REG: data_register generic map (reg_width => rem_width+3)
port map (clk => clk, reset => reset, data_in => converted_r12, data_out => pipelined_r12);
integer_q12 <= conv_integer( signed(pipelined_q12) );
integer_r12 <= conv_integer( signed(pipelined_r12) );
-------------------------------------------------------
-- k = k_max-1 = 11
process(r, integer_r12, delayed_input23_14, integer_q12, vector_r, unsigned_q)
begin
vector_r(11) <= ( (conv_std_logic_vector(integer_r12, rem_width)) & delayed_input23_14(9) & delayed_input23_14(8) );
if ( integer_r12 >= 0 ) then
unsigned_q(11) <= ( conv_unsigned(integer_q12, sqrt_width) & "01" );
r(11) <= ( conv_integer(signed(vector_r(11))) - conv_integer(unsigned_q(11)) );
else
unsigned_q(11) <= ( conv_unsigned(integer_q12, sqrt_width) & "11" );
r(11) <= ( conv_integer(signed(vector_r(11))) + conv_integer(unsigned_q(11)) );
end if;
if ( r(11) >= 0 ) then
q(11) <= conv_integer( unsigned(unsigned_q(11)(k_max downto 2) & '1') );
else
q(11) <= conv_integer( unsigned(unsigned_q(11)(k_max downto 2) & '0') );
end if;
end process;
-------------------------------------------------------
-- k = k_max-1 = 10
process(r, delayed_input23_14, q, vector_r, unsigned_q)
begin
vector_r(10) <= ( (conv_std_logic_vector(r(11), rem_width)) & delayed_input23_14(7) & delayed_input23_14(6) );
if ( r(11) >= 0 ) then
unsigned_q(10) <= ( conv_unsigned(q(11), sqrt_width) & "01" );
r(10) <= ( conv_integer(signed(vector_r(10))) - conv_integer(unsigned_q(10)) );
else
unsigned_q(10) <= ( conv_unsigned(q(11), sqrt_width) & "11" );
r(10) <= ( conv_integer(signed(vector_r(10))) + conv_integer(unsigned_q(10)) );
end if;
if ( r(10) >= 0 ) then
q(10) <= conv_integer( unsigned(unsigned_q(10)(k_max downto 2) & '1') );
else
q(10) <= conv_integer( unsigned(unsigned_q(10)(k_max downto 2) & '0') );
end if;
end process;
-------------------------------------------------------
-- k = k_max-1 = 9
process(r, delayed_input23_14, q, vector_r, unsigned_q)
begin
vector_r(9) <= ( (conv_std_logic_vector(r(10), rem_width)) & delayed_input23_14(5) & delayed_input23_14(4) );
if ( r(10) >= 0 ) then
unsigned_q(9) <= ( conv_unsigned(q(10), sqrt_width) & "01" );
r(9) <= ( conv_integer(signed(vector_r(9))) - conv_integer(unsigned_q(9)) );
else
unsigned_q(9) <= ( conv_unsigned(q(10), sqrt_width) & "11" );
r(9) <= ( conv_integer(signed(vector_r(9))) + conv_integer(unsigned_q(9)) );
end if;
if ( r(9) >= 0 ) then
q(9) <= conv_integer( unsigned(unsigned_q(9)(k_max downto 2) & '1') );
else
q(9) <= conv_integer( unsigned(unsigned_q(9)(k_max downto 2) & '0') );
end if;
end process;
-------------------------------------------------------
-- k = k_max-1 = 8
process(r, delayed_input23_14, q, vector_r, unsigned_q)
begin
vector_r(8) <= ( (conv_std_logic_vector(r(9), rem_width)) & delayed_input23_14(3) & delayed_input23_14(2) );
if ( r(9) >= 0 ) then
unsigned_q(8) <= ( conv_unsigned(q(9), sqrt_width) & "01" );
r(8) <= ( conv_integer(signed(vector_r(8))) - conv_integer(unsigned_q(8)) );
else
unsigned_q(8) <= ( conv_unsigned(q(9), sqrt_width) & "11" );
r(8) <= ( conv_integer(signed(vector_r(8))) + conv_integer(unsigned_q(8)) );
end if;
if ( r(8) >= 0 ) then
q(8) <= conv_integer( unsigned(unsigned_q(8)(k_max downto 2) & '1') );
else
q(8) <= conv_integer( unsigned(unsigned_q(8)(k_max downto 2) & '0') );
end if;
end process;
-------------------------------------------------------
-- k = k_max-1 = 7
process(r, delayed_input23_14, q, vector_r, unsigned_q)
begin
vector_r(7) <= ( (conv_std_logic_vector(r(8), rem_width)) & delayed_input23_14(1) & delayed_input23_14(0) );
if ( r(8) >= 0 ) then
unsigned_q(7) <= ( conv_unsigned(q(8), sqrt_width) & "01" );
r(7) <= ( conv_integer(signed(vector_r(7))) - conv_integer(unsigned_q(7)) );
else
unsigned_q(7) <= ( conv_unsigned(q(8), sqrt_width) & "11" );
r(7) <= ( conv_integer(signed(vector_r(7))) + conv_integer(unsigned_q(7)) );
end if;
if ( r(7) >= 0 ) then
q(7) <= conv_integer( unsigned(unsigned_q(7)(k_max downto 2) & '1') );
else
q(7) <= conv_integer( unsigned(unsigned_q(7)(k_max downto 2) & '0') );
end if;
end process;
converted_q7 <= conv_std_logic_vector(q(7), sqrt_width+3);
converted_r7 <= conv_std_logic_vector(r(7), rem_width+3);
Q7_PIPELINE_REG: data_register generic map (reg_width => sqrt_width+3)
port map (clk => clk, reset => reset, data_in => converted_q7, data_out => pipelined_q7);
R7_PIPELINE_REG: data_register generic map (reg_width => rem_width+3)
port map (clk => clk, reset => reset, data_in => converted_r7, data_out => pipelined_r7);
integer_q7 <= conv_integer( signed(pipelined_q7) );
integer_r7 <= conv_integer( signed(pipelined_r7) );
-------------------------------------------------------
-- k = k_max-1 = 6
process(r, integer_r7, delayed_input13_4, integer_q7, vector_r, unsigned_q)
begin
vector_r(6) <= ( (conv_std_logic_vector(integer_r7, rem_width)) & delayed_input13_4(9) & delayed_input13_4(8) );
if ( integer_r7 >= 0 ) then
unsigned_q(6) <= ( conv_unsigned(integer_q7, sqrt_width) & "01" );
r(6) <= ( conv_integer(signed(vector_r(6))) - conv_integer(unsigned_q(6)) );
else
unsigned_q(6) <= ( conv_unsigned(integer_q7, sqrt_width) & "11" );
r(6) <= ( conv_integer(signed(vector_r(6))) + conv_integer(unsigned_q(6)) );
end if;
if ( r(6) >= 0 ) then
q(6) <= conv_integer( unsigned(unsigned_q(6)(k_max downto 2) & '1') );
else
q(6) <= conv_integer( unsigned(unsigned_q(6)(k_max downto 2) & '0') );
end if;
end process;
-------------------------------------------------------
-- k = k_max-1 = 5
process(r, delayed_input13_4, q, vector_r, unsigned_q)
begin
vector_r(5) <= ( (conv_std_logic_vector(r(6), rem_width)) & delayed_input13_4(7) & delayed_input13_4(6) );
if ( r(6) >= 0 ) then
unsigned_q(5) <= ( conv_unsigned(q(6), sqrt_width) & "01" );
r(5) <= ( conv_integer(signed(vector_r(5))) - conv_integer(unsigned_q(5)) );
else
unsigned_q(5) <= ( conv_unsigned(q(6), sqrt_width) & "11" );
r(5) <= ( conv_integer(signed(vector_r(5))) + conv_integer(unsigned_q(5)) );
end if;
if ( r(5) >= 0 ) then
q(5) <= conv_integer( unsigned(unsigned_q(5)(k_max downto 2) & '1') );
else
q(5) <= conv_integer( unsigned(unsigned_q(5)(k_max downto 2) & '0') );
end if;
end process;
-------------------------------------------------------
-- k = k_max-1 = 4
process(r, delayed_input13_4, q, vector_r, unsigned_q)
begin
vector_r(4) <= ( (conv_std_logic_vector(r(5), rem_width)) & delayed_input13_4(5) & delayed_input13_4(4) );
if ( r(5) >= 0 ) then
unsigned_q(4) <= ( conv_unsigned(q(5), sqrt_width) & "01" );
r(4) <= ( conv_integer(signed(vector_r(4))) - conv_integer(unsigned_q(4)) );
else
unsigned_q(4) <= ( conv_unsigned(q(5), sqrt_width) & "11" );
r(4) <= ( conv_integer(signed(vector_r(4))) + conv_integer(unsigned_q(4)) );
end if;
if ( r(4) >= 0 ) then
q(4) <= conv_integer( unsigned(unsigned_q(4)(k_max downto 2) & '1') );
else
q(4) <= conv_integer( unsigned(unsigned_q(4)(k_max downto 2) & '0') );
end if;
end process;
-------------------------------------------------------
-- k = k_max-1 = 3
process(r, delayed_input13_4, q, vector_r, unsigned_q)
begin
vector_r(3) <= ( (conv_std_logic_vector(r(4), rem_width)) & delayed_input13_4(3) & delayed_input13_4(2) );
if ( r(4) >= 0 ) then
unsigned_q(3) <= ( conv_unsigned(q(4), sqrt_width) & "01" );
r(3) <= ( conv_integer(signed(vector_r(3))) - conv_integer(unsigned_q(3)) );
else
unsigned_q(3) <= ( conv_unsigned(q(4), sqrt_width) & "11" );
r(3) <= ( conv_integer(signed(vector_r(3))) + conv_integer(unsigned_q(3)) );
end if;
if ( r(3) >= 0 ) then
q(3) <= conv_integer( unsigned(unsigned_q(3)(k_max downto 2) & '1') );
else
q(3) <= conv_integer( unsigned(unsigned_q(3)(k_max downto 2) & '0') );
end if;
end process;
-------------------------------------------------------
-- k = k_max-1 = 2
process(r, delayed_input13_4, q, vector_r, unsigned_q)
begin
vector_r(2) <= ( (conv_std_logic_vector(r(3), rem_width)) & delayed_input13_4(1) & delayed_input13_4(0) );
if ( r(3) >= 0 ) then
unsigned_q(2) <= ( conv_unsigned(q(3), sqrt_width) & "01" );
r(2) <= ( conv_integer(signed(vector_r(2))) - conv_integer(unsigned_q(2)) );
else
unsigned_q(2) <= ( conv_unsigned(q(3), sqrt_width) & "11" );
r(2) <= ( conv_integer(signed(vector_r(2))) + conv_integer(unsigned_q(2)) );
end if;
if ( r(2) >= 0 ) then
q(2) <= conv_integer( unsigned(unsigned_q(2)(k_max downto 2) & '1') );
else
q(2) <= conv_integer( unsigned(unsigned_q(2)(k_max downto 2) & '0') );
end if;
end process;
converted_q2 <= conv_std_logic_vector(q(2), sqrt_width+3);
converted_r2 <= conv_std_logic_vector(r(2), rem_width+3);
Q2_PIPELINE_REG: data_register generic map (reg_width => sqrt_width+3)
port map (clk => clk, reset => reset, data_in => converted_q2, data_out => pipelined_q2);
R2_PIPELINE_REG: data_register generic map (reg_width => rem_width+3)
port map (clk => clk, reset => reset, data_in => converted_r2, data_out => pipelined_r2);
integer_q2 <= conv_integer( signed(pipelined_q2) );
integer_r2 <= conv_integer( signed(pipelined_r2) );
-------------------------------------------------------
-- k = k_max-1 = 1
process(r, integer_r2, delayed_input3_0, integer_q2, vector_r, unsigned_q)
begin
vector_r(1) <= ( (conv_std_logic_vector(integer_r2, rem_width)) & delayed_input3_0(3) & delayed_input3_0(2) );
if ( integer_r2 >= 0 ) then
unsigned_q(1) <= ( conv_unsigned(integer_q2, sqrt_width) & "01" );
r(1) <= ( conv_integer(signed(vector_r(1))) - conv_integer(unsigned_q(1)) );
else
unsigned_q(1) <= ( conv_unsigned(integer_q2, sqrt_width) & "11" );
r(1) <= ( conv_integer(signed(vector_r(1))) + conv_integer(unsigned_q(1)) );
end if;
if ( r(1) >= 0 ) then
q(1) <= conv_integer( unsigned(unsigned_q(1)(k_max downto 2) & '1') );
else
q(1) <= conv_integer( unsigned(unsigned_q(1)(k_max downto 2) & '0') );
end if;
end process;
-------------------------------------------------------
-- k = k_max-1 = 0
process(r, delayed_input3_0, q, vector_r, unsigned_q)
begin
vector_r(0) <= ( (conv_std_logic_vector(r(1), rem_width)) & delayed_input3_0(1) & delayed_input3_0(0) );
if ( r(1) >= 0 ) then
unsigned_q(0) <= ( conv_unsigned(q(1), sqrt_width) & "01" );
r(0) <= ( conv_integer(signed(vector_r(0))) - conv_integer(unsigned_q(0)) );
else
unsigned_q(0) <= ( conv_unsigned(q(1), sqrt_width) & "11" );
r(0) <= ( conv_integer(signed(vector_r(0))) + conv_integer(unsigned_q(0)) );
end if;
if ( r(0) >= 0 ) then
q(0) <= conv_integer( unsigned(unsigned_q(0)(k_max downto 2) & '1') );
else
q(0) <= conv_integer( unsigned(unsigned_q(0)(k_max downto 2) & '0') );
end if;
end process;
-------------------------------------------------------
process(q, vector_q0, r, q01)
begin
vector_q0 <= conv_std_logic_vector(q(0), sqrt_width);
q01 <= conv_integer( unsigned(vector_q0 & '1') );
if (r(0) < 0) then
remainder <= conv_std_logic_vector(r(0) + q01, sqrt_width+2);
else
remainder <= conv_std_logic_vector(r(0), sqrt_width+2);
end if;
end process;
------------------------------------------------------------------------
output <= conv_std_logic_vector(q(0), sqrt_width);
-----------------------------------------------------------------------------------------------------------------
end rtl;
|
--
-- threadA.vhd
-- measurement thread
--
-- Author: Enno Luebbers <[email protected]>
-- Date: 18.02.2008
--
-- This file is part of the ReconOS project <http://www.reconos.de>.
-- University of Paderborn, Computer Engineering Group.
--
-- (C) Copyright University of Paderborn 2008.
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
library reconos_v2_00_a;
use reconos_v2_00_a.reconos_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity hwt_data is
generic (
C_BURST_AWIDTH : integer := 11;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic;
-- external timebase
i_timeBase : in std_logic_vector(0 to C_OSIF_DATA_WIDTH-1)
);
end hwt_data;
architecture Behavioral of hwt_data is
-- timer address (FIXME: hardcoded!)
constant TIMER_ADDR : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := X"50004000";
-- ReconOS resources used by this thread
constant C_MB_TRANSFER : std_logic_vector(0 to 31) := X"00000000";
constant C_MB_RESULT : std_logic_vector(0 to 31) := X"00000001";
-- OS synchronization state machine states
type t_state is (
STATE_INIT, -- load configuration address
STATE_READ_SRC, -- load source address
STATE_READ_DST, -- load destination address
STATE_READ_BLKSIZE, -- load transfer size
STATE_WAIT, -- wait (not used)
STATE_READTIME_START, -- measure start time
STATE_READ_MBOX, -- read data from mbox
STATE_INC_ADDR,
STATE_READ_MEM_SINGLE, -- read data from memory (single word)
STATE_READ_MEM_BURST, -- read data from memory (burst)
STATE_READTIME_STOP,
STATE_WRITE_MBOX, -- write data to mbox
STATE_WRITE_MEM_SINGLE, -- write data to memory (single word)
STATE_WRITE_MEM_BURST, -- write data to memory (burst)
STATE_WRITETIME_STOP, -- measure stop time
STATE_POST_READTIME_1, -- post times
STATE_POST_READTIME_2,
STATE_POST_WRITETIME_1,
STATE_POST_WRITETIME_2,
STATE_EXIT
);
signal state : t_state := STATE_INIT;
-- address of data in main memory
-- RAM address
signal RAMAddr : std_logic_vector(0 to C_BURST_AWIDTH-1);
begin
-- hook up RAM signals
o_RAMClk <= clk;
o_RAMAddr <= RAMAddr(0 to C_BURST_AWIDTH-2) & not RAMAddr(C_BURST_AWIDTH-1); -- invert LSB of address to get the word ordering right
-- o_RAMWE <= '0';
-- o_RAMData <= (others => '0');
-- OS synchronization state machine
state_proc : process(clk, reset)
variable done : boolean;
variable success : boolean;
variable burst_counter : natural range 0 to 8192/128 - 1; -- transfer 128 bytes at once
variable trans_counter : natural range 0 to 8192/4 - 1; -- transfer 4 bytes at once
-- addresses
variable conf_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable src_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable dst_address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
variable block_size : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- timing values
variable readtime_1 : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := X"AFFE0001";
variable readtime_2 : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := X"AFFE0001";
variable writetime_1 : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := X"AFFE0002";
variable writetime_2 : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := X"AFFE0002";
variable burstlen_bytes : natural range 1 to 128;
variable burstlen_cycles : natural range 1 to 16;
variable bursts : natural range 0 to 8192/128 - 1;
begin
if reset = '1' then
reconos_reset(o_osif, i_osif);
src_address := (others => '0');
dst_address := (others => '0');
state <= STATE_INIT;
o_RAMWE <= '0';
o_RAMData <= (others => '0');
burst_counter := 0;
trans_counter := 0;
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case state is
-- read init data (address of configuration struct)
when STATE_INIT =>
reconos_get_init_data(done, o_osif, i_osif, conf_address);
if done then
state <= STATE_READ_SRC;
end if;
-- read source address (0 means mbox)
when STATE_READ_SRC =>
reconos_read(done, o_osif, i_osif, conf_address, src_address);
if done then
state <= STATE_READ_DST;
end if;
-- read destination address (0 means mbox)
when STATE_READ_DST =>
reconos_read(done, o_osif, i_osif, conf_address, dst_address);
if done then
state <= STATE_READ_BLKSIZE;
end if;
-- read block size (in bytes)
when STATE_READ_BLKSIZE =>
reconos_read(done, o_osif, i_osif, conf_address, block_size);
if done then
state <= STATE_WAIT;
end if;
-- wait
when STATE_WAIT =>
burst_counter := 0;
state <= STATE_READTIME_START;
-- get start time of burst transfer, decide on mechanism (single, mbox, burst)
when STATE_READTIME_START =>
readtime_1 := i_timeBase;
if src_address = X"0000_0000" then
-- read from mailbox
state <= STATE_READ_MBOX;
else
if block_size = 4 then
RAMAddr <= (others => '0');
state <= STATE_READ_MEM_SINGLE;
else
if block_size < 128 then
burstlen_bytes := conv_integer(block_size);
bursts <= 1;
else
burstlen_bytes := 128;
bursts := conv_integer(block_size)/8;
end if;
burstlen_cycles := burstlen_bytes/8;
state <= STATE_READ_MEM_BURST;
end if;
end if;
-- read single word into burst ram
when STATE_READ_MEM_SINGLE =>
reconos_thread_exit(o_osif, i_osif, X"0000_0001");
-- reconos_read_s(done, o_osif, i_osif, src_address, o_RAMData);
-- if done then
-- o_RAMWE <= '1';
-- state <= STATE_READTIME_STOP;
-- end if;
-- read data from main memory into local burst RAM.
when STATE_READ_MEM_BURST =>
reconos_thread_exit(o_osif, i_osif, X"0000_0002");
-- reconos_read_burst_l (done,
-- o_osif,
-- i_osif,
-- std_logic_vector(TO_UNSIGNED(burst_counter*burstlen_bytes, C_OSIF_DATA_WIDTH)),
-- src_address+(burst_counter*burstlen_bytes),
-- burstlen_cycles
-- );
-- if done then
-- if burst_counter = bursts - 1 then
-- trans_counter := 0;
-- RAMAddr <= (others => '0');
-- state <= STATE_READTIME_STOP;
-- else
-- burst_counter := burst_counter + 1;
-- end if;
-- end if;
-- read data from mbox into local burst RAM
when STATE_READ_MBOX =>
reconos_thread_exit(o_osif, i_osif, X"0000_0003");
-- o_RAMWE <= '0';
-- reconos_mbox_get_s(done, success, o_osif, i_osif, C_MB_TRANSFER, o_RAMData);
-- if done and success then
-- o_RAMWE <= '1';
-- if trans_counter = conv_integer(block_size)/4 - 1 then
-- burst_counter := 0;
-- state <= STATE_READTIME_STOP;
-- else
-- state <= STATE_INC_ADDR;
-- trans_counter := trans_counter + 1;
-- end if;
-- end if;
-- increment RAM address for writing to BRAM
when STATE_INC_ADDR =>
o_RAMWE <= '0';
RAMAddr <= RAMAddr + 1; -- note that this is delayed by one clock cycle
state <= STATE_READ_MBOX;
-- get stop time of burst transfer
when STATE_READTIME_STOP =>
o_RAMWE <= '0';
RAMAddr <= (others => '0');
readtime_2 := i_timeBase;
writetime_1 := readtime_2; -- nach der Messung ist vor der Messung :)
if dst_address = X"0000_0000" then
-- write from mailbox
state <= STATE_WRITE_MBOX;
else
if block_size = 4 then
RAMAddr <= (others => '0');
state <= STATE_WRITE_MEM_SINGLE;
else
if block_size < 128 then
burstlen_bytes := conv_integer(block_size);
bursts := 1;
else
burstlen_bytes := 128;
bursts := conv_integer(block_size)/8;
end if;
burstlen_cycles := burstlen_bytes/8;
state <= STATE_WRITE_MEM_BURST;
end if;
end if;
-- transfer data across mailbox
-- this state also hides the RAM access timing, since this is a multi-cycle
-- command, and the "data" parameter is only transferred in the second cycle.
when STATE_WRITE_MBOX =>
reconos_mbox_put(done, success, o_osif, i_osif, C_MB_TRANSFER, i_RAMData);
if done and success then
if trans_counter = conv_integer(block_size)/4 - 1 then
state <= STATE_WRITETIME_STOP;
else
RAMAddr <= RAMAddr + 1;
trans_counter := trans_counter + 1;
end if;
end if;
-- write single word from burst ram to memory
when STATE_WRITE_MEM_SINGLE =>
reconos_write(done, o_osif, i_osif, dst_address, i_RAMData);
if done then
o_RAMWE <= '1';
state <= STATE_WRITETIME_STOP;
end if;
-- write data from burst RAM into main memory
when STATE_WRITE_MEM_BURST =>
reconos_write_burst_l (done,
o_osif,
i_osif,
std_logic_vector(TO_UNSIGNED(burst_counter*burstlen_bytes, C_OSIF_DATA_WIDTH)),
dst_address+(burst_counter*burstlen_bytes),
burstlen_cycles
);
if done then
if burst_counter = bursts - 1 then
trans_counter := 0;
RAMAddr <= (others => '0');
state <= STATE_READTIME_STOP;
else
burst_counter := burst_counter + 1;
end if;
end if;
-- get stop time of FIFO transfer
when STATE_WRITETIME_STOP =>
writetime_2 := i_timeBase;
state <= STATE_POST_READTIME_1;
-- write read time to mailbox
when STATE_POST_READTIME_1 =>
reconos_mbox_put(done, success, o_osif, i_osif, C_MB_RESULT, readtime_1);
if done and success then
state <= STATE_POST_READTIME_2;
end if;
when STATE_POST_READTIME_2 =>
reconos_mbox_put(done, success, o_osif, i_osif, C_MB_RESULT, readtime_2);
if done and success then
state <= STATE_POST_WRITETIME_1;
end if;
-- write transfer time to mailbox
when STATE_POST_WRITETIME_1 =>
reconos_mbox_put(done, success, o_osif, i_osif, C_MB_RESULT, writetime_1);
if done and success then
state <= STATE_POST_WRITETIME_2;
end if;
when STATE_POST_WRITETIME_2 =>
reconos_mbox_put(done, success, o_osif, i_osif, C_MB_RESULT, writetime_2);
if done and success then
state <= STATE_EXIT;
end if;
when STATE_EXIT =>
reconos_thread_exit( o_osif, i_osif, X"0000_1111" );
when others =>
state <= STATE_INIT;
end case;
end if;
end if;
end process;
end Behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1504.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s08b00x00p14n03i01504ent IS
END c08s08b00x00p14n03i01504ent;
ARCHITECTURE c08s08b00x00p14n03i01504arch OF c08s08b00x00p14n03i01504ent IS
BEGIN
TESTING: PROCESS
variable x : integer;
BEGIN
case x is
when 1 to 19 => NULL;
when others | 32 => NULL;
end case;
assert FALSE
report "***FAILED TEST: c08s08b00x00p14n03i01504 - OTHERS choice is allowed as the last choice and it must be the only choice"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s08b00x00p14n03i01504arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1504.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s08b00x00p14n03i01504ent IS
END c08s08b00x00p14n03i01504ent;
ARCHITECTURE c08s08b00x00p14n03i01504arch OF c08s08b00x00p14n03i01504ent IS
BEGIN
TESTING: PROCESS
variable x : integer;
BEGIN
case x is
when 1 to 19 => NULL;
when others | 32 => NULL;
end case;
assert FALSE
report "***FAILED TEST: c08s08b00x00p14n03i01504 - OTHERS choice is allowed as the last choice and it must be the only choice"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s08b00x00p14n03i01504arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1504.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s08b00x00p14n03i01504ent IS
END c08s08b00x00p14n03i01504ent;
ARCHITECTURE c08s08b00x00p14n03i01504arch OF c08s08b00x00p14n03i01504ent IS
BEGIN
TESTING: PROCESS
variable x : integer;
BEGIN
case x is
when 1 to 19 => NULL;
when others | 32 => NULL;
end case;
assert FALSE
report "***FAILED TEST: c08s08b00x00p14n03i01504 - OTHERS choice is allowed as the last choice and it must be the only choice"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s08b00x00p14n03i01504arch;
|
--------------------------------------------------------------------------------
-- Title : Error Module
-- Project : 16z091-01
--------------------------------------------------------------------------------
-- File : error.vhd
-- Author : Susanne Reinfelder
-- Email : [email protected]
-- Organization: MEN Mikro Elektronik Nuremberg GmbH
-- Created : 03.12.2010
--------------------------------------------------------------------------------
-- Simulator : ModelSim PE 6.6a / ModelSim AE 6.5e sp1
-- Synthesis :
--------------------------------------------------------------------------------
-- Description :
-- errors on RxModule, TxModule or hard IP core are collected here and passed
-- to Wishbone modules through a FIFO
--------------------------------------------------------------------------------
-- Hierarchy :
-- ip_16z091_01
-- rx_module
-- rx_ctrl
-- rx_get_data
-- rx_fifo
-- rx_len_cntr
-- wb_master
-- wb_slave
-- tx_module
-- tx_ctrl
-- tx_put_data
-- tx_compl_timeout
-- tx_fifo_data
-- tx_fifo_header
-- * error
-- err_fifo
-- init
-- interrupt_core
-- interrupt_wb
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
entity error is
port(
clk : in std_logic;
rst : in std_logic;
wb_clk : in std_logic;
wb_rst : in std_logic;
-- Rx Module
rx_tag_id : in std_logic_vector(7 downto 0);
rx_ecrc_err : in std_logic;
rx_type_fmt_err : in std_logic_vector(1 downto 0);
-- Tx Module
tx_compl_abort : in std_logic;
tx_timeout : in std_logic;
-- Interrupt
wb_num_err : in std_logic;
-- Wishbone
error_ecrc_err : out std_logic;
error_timeout : out std_logic;
error_tag_id : out std_logic_vector(7 downto 0);
error_cor_ext_rcv : out std_logic_vector(1 downto 0);
error_cor_ext_rpl : out std_logic;
error_rpl : out std_logic;
error_r2c0 : out std_logic;
error_msi_num : out std_logic;
-- IP Core
derr_cor_ext_rcv : in std_logic_vector(1 downto 0);
derr_cor_ext_rpl : in std_logic;
derr_rpl : in std_logic;
r2c_err0 : in std_logic;
cpl_err : out std_logic_vector(6 downto 0);
cpl_pending : out std_logic
);
end entity error;
-- ****************************************************************************
architecture error_arch of error is
-- internal signals -----------------------------------------------------------
signal err_fifo_clr : std_logic;
signal err_fifo_wr_enable : std_logic;
signal err_fifo_in : std_logic_vector(15 downto 0);
-- uncomment next line when increasing FIFO depth
-- signal err_fifo_full : std_logic;
signal err_fifo_rd_enable : std_logic;
signal err_fifo_out : std_logic_vector(15 downto 0);
signal err_fifo_empty : std_logic;
signal get_value : std_logic;
signal wb_num_err_q : std_logic;
signal wb_num_err_qq : std_logic;
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
signal ip_error_in : std_logic_vector(14 downto 0);
signal ip_error_last : std_logic_vector(14 downto 0) := (others => '0');
-------------------------------------------------------------------------------
begin
-- instanciate components -----------------------------------------------------
err_fifo_comp : dcfifo
generic map (
intended_device_family => "Cyclone IV GX",
lpm_numwords => 4,
lpm_showahead => "OFF",
lpm_type => "dcfifo",
lpm_width => 16,
lpm_widthu => 2,
overflow_checking => "ON",
rdsync_delaypipe => 4,
underflow_checking => "ON",
use_eab => "ON",
write_aclr_synch => "OFF",
wrsync_delaypipe => 4)
port map (
aclr => err_fifo_clr,
wrclk => clk,
wrreq => err_fifo_wr_enable,
data => err_fifo_in,
wrempty => open,
wrfull => open,
rdclk => wb_clk,
rdreq => err_fifo_rd_enable,
q => err_fifo_out,
rdempty => err_fifo_empty,
rdfull => open);
-------------------------------------------------------------------------------
fifo_wr : process(clk, rst)
begin
if(rst = '1') then
err_fifo_wr_enable <= '0';
err_fifo_in <= (others => '0');
err_fifo_clr <= '1';
ip_error_last <= (others => '0');
elsif(clk'event and clk = '1') then
err_fifo_clr <= '0';
-- store errors if new error occred
if(ip_error_last /= ip_error_in) then
err_fifo_wr_enable <= '1';
err_fifo_in <= '0' & ip_error_in;
ip_error_last <= ip_error_in;
end if;
-- reset signals
if(err_fifo_wr_enable = '1') then
err_fifo_wr_enable <= '0';
err_fifo_in <= (others => '0');
end if;
end if;
end process fifo_wr;
-------------------------------------------------------------------------------
fifo_rd : process(wb_clk, wb_rst)
begin
if(wb_rst = '1') then
error_timeout <= '0';
error_r2c0 <= '0';
error_rpl <= '0';
error_cor_ext_rpl <= '0';
error_cor_ext_rcv <= (others => '0');
error_ecrc_err <= '0';
error_tag_id <= (others => '0');
error_msi_num <= '0';
err_fifo_rd_enable <= '0';
get_value <= '0';
wb_num_err_q <= '0';
wb_num_err_qq <= '0';
elsif(wb_clk'event and wb_clk = '1') then
-- sample wb_num_err because this is synchronous to clk
wb_num_err_q <= wb_num_err;
wb_num_err_qq <= wb_num_err_q;
-- read values as soon as they appear
if(err_fifo_empty = '0') then
err_fifo_rd_enable <= '1';
end if;
-- reset enable an start analysis of value read from FIFO
if(err_fifo_rd_enable = '1') then
err_fifo_rd_enable <= '0';
get_value <= '1';
end if;
-- propagate error signals to outer environment
if(get_value = '1') then
get_value <= '0';
error_timeout <= err_fifo_out(14);
error_r2c0 <= err_fifo_out(13);
error_rpl <= err_fifo_out(12);
error_cor_ext_rpl <= err_fifo_out(11);
error_cor_ext_rcv <= err_fifo_out(10 downto 9);
error_ecrc_err <= err_fifo_out(8);
error_tag_id <= err_fifo_out(7 downto 0);
else
error_timeout <= '0';
error_r2c0 <= '0';
error_rpl <= '0';
error_cor_ext_rpl <= '0';
error_cor_ext_rcv <= (others => '0');
error_ecrc_err <= '0';
error_tag_id <= (others => '0');
end if;
-- propagate error signals to outer environment
error_msi_num <= wb_num_err_qq;
end if;
end process fifo_rd;
-------------------------------------------------------------------------------
-- capture occuring errors
ip_error_in(14) <= '1' when tx_timeout = '1' else '0';
ip_error_in(13) <= '1' when r2c_err0 = '1' else '0';
ip_error_in(12) <= '1' when derr_rpl = '1' else '0';
ip_error_in(11) <= '1' when derr_cor_ext_rpl = '1' else '0';
ip_error_in(10 downto 9) <= derr_cor_ext_rcv when derr_cor_ext_rcv /= "00" else "00";
ip_error_in(8) <= '1' when rx_ecrc_err = '1' else '0';
ip_error_in(7 downto 0) <= rx_tag_id when rx_ecrc_err = '1' else (others => '0');
cpl_err(6) <= '0';
cpl_err(5) <= '0' when rst = '1' else
'1' when rx_type_fmt_err = "01" else
'0';
cpl_err(4) <= '0' when rst = '1' else
'1' when rx_type_fmt_err = "10" else
'0';
cpl_err(3) <= '0';
cpl_err(2) <= '0' when rst = '1' else
'1' when tx_compl_abort = '1' else
'0';
cpl_err(1 downto 0) <= (others => '0');
cpl_pending <= '0';
-------------------------------------------------------------------------------
end architecture error_arch;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
YRC/Ga8ExLo0jQ10bS6whk8Z5meT5KspFZ0T0eyXvGZk+I9FgDoEWejdq647+YmMBK6O65b6Kwo5
yZCcnAjt7g==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Kvsn1bIfzmtzfHxzHMsfdZaiDP7zPEt1AFS8BGj+N8/dopIpvzktqw+Zu2cHMt6TtPn+MTMZvaZN
pOWkBgN0KEAEbgSXBN+uliEYgSceTulS22EKY57bZDvXz9VlnF7VKgSpSBI/fL22b7UWiKas3TwR
a7km49m011xwpo4OL+Y=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
mD5f136cC/LpJdX+bTZN6WcxYO/SDKtntruYkiw2yX1zJCL1EfsprVOjozXek0U4gGh/LFFVQbrD
X9WBZRrm7HX3w5uMSIIyekYiFcqQuITeLyn35xrOhb2febDpSuxuoKBOHtkmyACywzyxzZrmagou
jsXcZUvnv6tsEbuPrrsc9djo9UXa4ga8WMKKCyJR8a7Dnop7W8hyXAPf73yJYsBIhc8lL8rxOOAL
wJnsW2VMXmE7251zOZ7J1Zo9I3+vtjXj6ARRr9CcOSt61PUji+u7Wjw7h0Cn8g7ovkyiWX1C0fM+
yXHYSiUAet53UB1GzGQxOO9gb/D3UMpdN9prlQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
xLYbsQDNP2R7D91aJrtT24ZHLSTAus76qbR8zaLcRuGZyPW5n20bJ/Lrcd4pRj0x66+pU6r02ZTh
Wy4wJvP9ytjjPXq+1p925czdzjRoh5RVFHp+GvMR7fKgP39xsj2w+/HFKA+ZCc/rO5Bk94qM9Jaq
Pji7y2MjWO6y3sTKttc=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
D1YeX2ofy6beslx2y48GtchFyGbmVToaYSamzAM9dHVDdGhwvh3Sfmfmh/29mrBrptu7iGxyZxra
E6ctLvA1W72K3A/z90QulzPyrxiufWHra466HZfvRpi0dxebM09wct7vxaWaz/vYdsUUdEBBsS3W
6Z0urojJq0XrmZA0uzgtBWF+Ploo6NzioNymE3lbS3UyKmW1Dqms6hAP7/uwQDMOxYB8hfk3TQZy
GFUDmcM76QhX+I9ermK8LBixGFKaa5SfZeon+noy9EQsOigUPhjdWLvLyMteyyyGWACDwNbM8YtK
23Uv+po76UL9+skFwYf18f298GR99w4FfIgQCg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4448)
`protect data_block
aJ7gySCTyie2eYKkPpOPdPZFCxgBtymXYe5AMAgdXP3ZiysEBZ9eO7RGC4Z8YzUIpb4DAYt4W+hd
rRcLEu+c9etm3hKyfd4T9A3AIV1Cx8TWTTE9qcJ5j+yLWky27XT0y097vEMvcCY+h7D7jts5Xh+I
X5AUXEZ16b0bEsq7dhtckWLpLFYR8+AolnP1/4+ziSI6ZzwXvXVTDGKCBplez3DuSiXe9RKfS3It
Jpuot+aXYix51aPeB11GyEWTImdv7t3XDg9SSKtJZ8Gt4kU+x0LwWdl7z38XePUC/3B4uBk3+JP4
7SvdJdMbiCO4wsHsxkDRQE1WXFTQxiy5yamNkrm1RPImjQKFLjBfg2R4muacj70Gv4RQxwm5FYv2
fIciYYJJ5iix/WDnZ7E0O6IjEompGUYWJmuokc77x4TcShn6URq9aOqgl4E30NyMZWw12PzNA7Sn
ZaEU9S+NaEv1gw3cQnF5fJb9pWKT0CF1Isk3ZS3WMaWpohuVrpUaGJ/b9JNWj46sJqX6DikCEzkF
YjythkL7eecd2jXAwnHESa09S5cf83qE61szWBjetNliNpqPNdH6q1u04rNzEcPvZqm5EjPsD2fe
a73H08Vhr6bSnZMC+Cbce3LoMC2IUHDSXCZm/wMdV3nwH/vM8b5VBjZcs3kIPfyUb1BXrEXIV8pS
2V+EOICG3joYEuZ9p5v4M7hlgWtyfgbD9RolWRFsmgh6QCFRtYO+h1pcoDEk0QLGSO0qodAi32SS
pp7Wfz/zkpS0RUrRgfP8iL2iz6vR4XDUxM8ETz68UC9jmySQ5FH5C4GHvy2NHx12axER3bVPk0qX
vr+Ah6htG9sjcy4JsmqqNXNQISSF0oPyp5byHsD5Nch8Co/Ytcx90OFS9KdSUpB+or3veLU8duy5
X/+RCFt8EBpHqqBnolqkJpzizfabHI4mfVsG7VlMR07um8BxrCEJJ7hUd6haIBkS+yJiO69LTHLc
n50k4Mm2/mYCMpJFNQAStKismJeqfIcwY5wsU25mXGfBEIdyf9qs2QLxAXCxL9z7NUPDrg+2atc2
QaqRxtf+0XBbRMfc//uOAKsgdWGx66+qDZUREj8yCvDXEF262Lldo7SCz02AJR+g90ZhY8mQaS11
WmuXf4i10fHsNiLODl7gipAPtrhvQtvuTaN+MGzzpRqCVXYac9g5vZSqgxuM5hBN1vJknoeXWE92
mBnpeeu6O/U3QYEnxH1Py1t8hyyCGDC08Kl9ILLGSM/kv3qLXfyHaGvXSefDR30E/FoePl8CFXrD
Bfi0Y8UdKh26qQmEnz3PDVvcTNtq7ym9YC/qgcdi5x1C63+0lGaLJFZTEM39lYrrbh2RieAo5VoD
BgTPUWHhV1DNvhFeNduScnrOp4BW81JoRIis3Yq6Rl0efb+TwZNBP/oJ8kim0QqM7rJPv/PNJ9Zb
3vPnjNHlgtQWSdgSenX2JaJ6QJTWfAjksBi92YLYIV5aFrHxMW1H7B9kbwFJIQBMYz61pb7GSvbB
ReUGJ4QkbEOVarQ1k0N+BgzFx6bbFYwAvJh/NXU4Ji47RRWetbi2Db8CPXQX+bQKsHUjCCPcMVu4
Ju6+dlUfslJcdk1LcK9ByzOGzlThfCYA71G9yx7Frjfp8oiWsAV9tSYDPLZvznDVi8TIqGTy5Ko1
gI50YgvBn8wqlARndT6DdE/PRWoalU7huXy2COmOZxRVPXqCfPeMPj3d2SjxAJyo5xFVm9D+rht6
Yexx10sMxSyHdlz71+/cxx/uG0BYrGSokLz3LL5cotBR80d3J4LTLCQpnpgxPHrsb/RK6qFf/erG
KUTsb4WP6q7aRMVYJbBM9Nn04mJXJ9JyyU3OOjcHLeuQ7QJdmBXISJBGHHyEVggJuM+UqyfbvIZb
rsl64+rfLZAZH8oL/3JaeqLAfOGRF44lVAb373lrS4XwyR5/X7i92/KyM3OlTNxot4RtWf2gy2gq
QUphblB1FrvHLmQvKcUGVMoywpcEvtaSF4F6N3vOb3RfmPBZnoQoRRZO60avrL1W+kc5wD5gJfNl
UJGuBfCiLKxzSnFnL9sQzmnYHHyhMUtuqDwba2tnlWS0xmDLRrlUzUjsuSeSpjlBU8xQFz+3NwDl
zqAk/4aTNLRmC1chVm+ff6BFymdWrtbY6qMrAp6nGbPbgw8iPHwWV76nNucgflEPe/F+L7iUYlNx
m24z31Aa4OF8h/iberskD/2xBaKBfzhQQGu+ZJ/w8lEjpbKIu+ChrLAWfGvoECm0YRa+LBlbG7Uq
xavHMAndkRvF/cV/tAC6thz56qjK/OqmUEIvcIYMWceSNOtiryVXVjis9/UdnSsF25akc5s9c+A7
5q1iE11joKh1y1jxGWZEkgMzDgPcMXG0hdCfsySD333WTkquyKUkXyErT0v+or+wiFYXx89+RXU/
5G9sle7NkB3LRqm0Umk/rcgH57cpkOEcOWfyJYA6WL/gFGuvO8AiTZAygFAGYBP6MSDf/MIe6Js2
A66OSENOx8vCG8or9PPe1EzZH2WoaZXaLSOW/9nwvovDpCn6oa7DJ+h0HmsKy59lruGg9RmFNvDK
CFZSVO+WAbPNMujr6VGN1YYlpXb32aM2DbwuEt02lD30d74jBAWhW1B1qdy/e6kmhWZ7fA3g31Ct
X4KdiBjNmdX8fn9RtHW2p0ydyCOY9BLxu5CGq55TWHzHHMPlGZtc03JFOxid08MLuR6y2UD2cdHk
9HRJCtlYJg5DE0prce0IyEXwrtah3L+d5koG5JS9OBbblnTF5fppT18WKMRofi7fhc+P3UpEggs6
hnu5n9LPS4OfIOMzE7MFmO249EQy9mcrKU1Aizaqjh5LEank8Eobx7K4LhV/XngcJi252rpNd/IX
MFdv1cAvwKc/qy9LGemT0TzTX6l/B5mtNgXwh3FuHwDe7L0z/EZWCjtbeKXUm8JOlXp+b4cuEb+n
g1d2O7TLqt3fZLV2FOIxcLbGrUvTKvFLzwXoN3mEL6G4e+Nrq5BepH1AnvRqaxxtMhK/XrM/Yxwj
5PGyQtBBfnEDLsr9qVvUs47nWnByTpPZbK7wB6JL9uTvl1ftACqQMmC39Ra/L05zbeeyumwfXBYj
hJB/TCz87MBCO7Bk04ef+IrZAjkNK5pU/BsXh4VyFReaRC3U6m8FX3DSmXcXT/ZYpbn0/3OlQPDl
wnJmXktdKh1DMBkFOdWKVYD6yNpNXQrtBfphFry/7OEAvzD21+Dmpz4b42QxgMZWigREruFNhUWv
EMK/i8xncsKo8yNskvWCcN3NvTTvCOZachxw85d4g7fcz9Y249YkOulga1Hq3LKbNCAoCXfimRrT
af4/Ly9MX6LQIdnS+YAezYh0dphSwTYqMRlmuLhAFvVmwE36qI4m1EQgE09YCqbNeq1QvRteRYyd
22acYdN11j8K9/JEoPZ7cFWLLLZlla+cgUUR69yNiSC5EWN9yCfQlrAvowzIfapXO/H8a1gukzYu
x3kvQ0kL09BxjES+pjtxTvf+WUpmP4Ty5vjqX2nNZ5sBcS8+02ihAr7LI4iuvnaJRyIFqZc3dn9+
UUS6Gq5T3MnjC4xTf+HTzGu62SD1FaH9orz34O9Jd3TFeWj4IJNS0jufjlFqkXu9GYx1AH7Hc57r
h8l+Xz0ND+xFu7+oJMR+wtzB253Ato9EEiFpOgaJSsy73PeKK+H+KbZvC/EtmUz+LLg9hwxuLdhi
MysxBlOFCBlJn4n6bLJlnNEHFjURriwSRjjLvAP5uwxCv8qhIZcVGfGzTiW2R4qyJ5Yktso6jH8q
uBjtKk04fcPTt9TOB4N66b3PzMRs9t/SzHv3Y/9c51UgU0suSSzMOCV/tJMOrE/AQg3Ts52KNARn
HW7SEwq7pfeNSafmBhlhFzyGs/1eBv3GIjYNCno8pGx5XMFdFLo1Cz5IbV9E5KRdwkB8eopdS2sd
bif0st+q3gnNP+rtXW9+TTUtMpbYW0GKizBk6PuXVkH2Z69C56k+orwdZ8M+mA9KiPtp6PFU+0yr
PaRhaFWBREESBbodgGrNX9lhqBilRuevU48E1EaNgSTRlYp8FbtEHwl7RHfmRSwVHVoU50viLwZB
IOiboPDZqwcJEfxiS46yCACC8xtmFLGwjPQlYKef2aVlmcv3EpzEf8SaCWhSqx2cQmbg1Jd0k71D
y6Jk10VU5bv1xzvp5glhFEU/wyrUIojKLTbBIo+Ug+D4ESDseL2mSCMOEZwD4u4cWWtE2rHTmNR9
8bLd0RDa6fR2cgRZnn4p/pnx7/0n6oW3DjL67pVLIqBB8Dy9k0t8UyC1ju5Ijz4jZ3EI+fQDYCUL
hk9cRFYIGzRTnj2u7no57/UTMewB+p4y7UajUV2JE10Ryjx8w6u+26RmoEoh7JCnrkEn3jQ5K+y3
4DOBDSYQtAIQ8/i8+yjFfk7w5ZNBtEtyVkQ3LjQHUpQ5GcSRiT01Mhjgr+aQ1hDVs6AXuEX6bNCB
x+aiisneNqjmg7EYOrQI1k25Ou5UXRN7Y5a7IGB4tV0HlAfP7ffz0jjb3++poUHGxG5LmU9Tx1Sc
GtPTV/wIsi/Ylt+WmyxFnQyxE2U6e7/UD/CuMl+d8LdSGbQF18hPr+noQYMUGHcvF2jSpJFVTLbT
OfKtt/NfsLtSxQh3araJq2sujX7Po716MUhkXAJz3Sn4wUrWSmDQRnwEBq66/YWn6mbkLLlqnuE5
r8//+dFqcPCYMX/4SUV1RZXCjYnyBAQtRkPXrbjT1asEli64ky4kxXrVs159RMshzXRiR8c+o1AX
/C/fo/ddXs2BR7TMRKUPiXDYNlyHtr6NEM0ZhQlPGtUQ+M/qUi9Cbfro3A3CmwnMqcNFb4bclLsW
d5MVVH/bVuO4USp7tIIQwD4utHGJchpOR9MZjNAI6FCDfyRIAcBAEfCARwRQxzx4el1Xwsa4gPIY
T8PSjXsuZRJbitK2CuaxdyPaLJamlsbL/WB0s2MyibbcLcnPOjSOanoLV9zmWkLGuqOvhwR1WYxS
lAvtNXVFpcVNYKDGu61WCph92xbbqKymzbIFm+pzLWYT0lrp3b5KYVdFN8UJ3EuF5lc9JDa3QN/Z
9Ksco1gDTdIq+YwTyOOzF5G4ej/iW+fPrH8rRoeknCkik95ZuZOwbObikt+WnDNATNucdOMCZwWt
ilFetMxrqLcOfgFN/nT3BmEV5ZHTPBsO4Fs6x4kNoU/ANo+y6uqNtNnVS77zeRZR3FlTlY5L2MSP
1cp+KsDH7i9KcZPt1XfyWfVcHpyulwC77nFah5XkPS/mIMz9sNbpqSaHxME/RxXFwLF/RaQVTh3T
Pru3ZrMjB9WBfmG6rrj6OTMTDo8c8Fq/uB8rJBV7V3u5EQokp0SM6b56H/aYnoeiYgIkcP79SGO4
huAJV2BljWC/jeIzpYVB1xa91sO39LXI7x9ShwkahkG2KhSh97e2uMft9ZrXg3ecK3eUdQr2D2v1
tgSMDvdyvEzq+/QBvgKzYmtO3dLamcnPaeIulqPzUnBpDlrBja7tnqUojIgOZSWygZixrM6lbE8t
vOo44pDNDZcCvSly/FxhScquWTqACYCx675IQ6sQrjHkzHNLI9aeLoVp1U6qxx/P3mz4k4PKe8+X
hd9xflQJdfrz2EbdwpYL/PM973op/6QllJJ41zM6EyqJM4bfEcwdevVlKgzyPTM4UfDmNWFUgVh4
lkcbxK8zD+Yr++arFTk6mQ4Z1gYTiRwH+fjP5P1ypBEWKeXSypdQv7iPqmb1bJiA1gvnMy2jjiUU
j3QSST+7xcAvxMdfNNMmJv9gDAGC7nOT4+D5Q6Ws4b+iuWAcNHQK/ljiNsR6jG9oR9VHePif5HmP
u+mYJBPmtaj/C/PT20DESgizqSS8T+JwoS9CumG/VCp1whNHKJ8tTDUiqOktEbsjKij9hnp5APRF
vQ8=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
YRC/Ga8ExLo0jQ10bS6whk8Z5meT5KspFZ0T0eyXvGZk+I9FgDoEWejdq647+YmMBK6O65b6Kwo5
yZCcnAjt7g==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Kvsn1bIfzmtzfHxzHMsfdZaiDP7zPEt1AFS8BGj+N8/dopIpvzktqw+Zu2cHMt6TtPn+MTMZvaZN
pOWkBgN0KEAEbgSXBN+uliEYgSceTulS22EKY57bZDvXz9VlnF7VKgSpSBI/fL22b7UWiKas3TwR
a7km49m011xwpo4OL+Y=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
mD5f136cC/LpJdX+bTZN6WcxYO/SDKtntruYkiw2yX1zJCL1EfsprVOjozXek0U4gGh/LFFVQbrD
X9WBZRrm7HX3w5uMSIIyekYiFcqQuITeLyn35xrOhb2febDpSuxuoKBOHtkmyACywzyxzZrmagou
jsXcZUvnv6tsEbuPrrsc9djo9UXa4ga8WMKKCyJR8a7Dnop7W8hyXAPf73yJYsBIhc8lL8rxOOAL
wJnsW2VMXmE7251zOZ7J1Zo9I3+vtjXj6ARRr9CcOSt61PUji+u7Wjw7h0Cn8g7ovkyiWX1C0fM+
yXHYSiUAet53UB1GzGQxOO9gb/D3UMpdN9prlQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
xLYbsQDNP2R7D91aJrtT24ZHLSTAus76qbR8zaLcRuGZyPW5n20bJ/Lrcd4pRj0x66+pU6r02ZTh
Wy4wJvP9ytjjPXq+1p925czdzjRoh5RVFHp+GvMR7fKgP39xsj2w+/HFKA+ZCc/rO5Bk94qM9Jaq
Pji7y2MjWO6y3sTKttc=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
D1YeX2ofy6beslx2y48GtchFyGbmVToaYSamzAM9dHVDdGhwvh3Sfmfmh/29mrBrptu7iGxyZxra
E6ctLvA1W72K3A/z90QulzPyrxiufWHra466HZfvRpi0dxebM09wct7vxaWaz/vYdsUUdEBBsS3W
6Z0urojJq0XrmZA0uzgtBWF+Ploo6NzioNymE3lbS3UyKmW1Dqms6hAP7/uwQDMOxYB8hfk3TQZy
GFUDmcM76QhX+I9ermK8LBixGFKaa5SfZeon+noy9EQsOigUPhjdWLvLyMteyyyGWACDwNbM8YtK
23Uv+po76UL9+skFwYf18f298GR99w4FfIgQCg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4448)
`protect data_block
aJ7gySCTyie2eYKkPpOPdPZFCxgBtymXYe5AMAgdXP3ZiysEBZ9eO7RGC4Z8YzUIpb4DAYt4W+hd
rRcLEu+c9etm3hKyfd4T9A3AIV1Cx8TWTTE9qcJ5j+yLWky27XT0y097vEMvcCY+h7D7jts5Xh+I
X5AUXEZ16b0bEsq7dhtckWLpLFYR8+AolnP1/4+ziSI6ZzwXvXVTDGKCBplez3DuSiXe9RKfS3It
Jpuot+aXYix51aPeB11GyEWTImdv7t3XDg9SSKtJZ8Gt4kU+x0LwWdl7z38XePUC/3B4uBk3+JP4
7SvdJdMbiCO4wsHsxkDRQE1WXFTQxiy5yamNkrm1RPImjQKFLjBfg2R4muacj70Gv4RQxwm5FYv2
fIciYYJJ5iix/WDnZ7E0O6IjEompGUYWJmuokc77x4TcShn6URq9aOqgl4E30NyMZWw12PzNA7Sn
ZaEU9S+NaEv1gw3cQnF5fJb9pWKT0CF1Isk3ZS3WMaWpohuVrpUaGJ/b9JNWj46sJqX6DikCEzkF
YjythkL7eecd2jXAwnHESa09S5cf83qE61szWBjetNliNpqPNdH6q1u04rNzEcPvZqm5EjPsD2fe
a73H08Vhr6bSnZMC+Cbce3LoMC2IUHDSXCZm/wMdV3nwH/vM8b5VBjZcs3kIPfyUb1BXrEXIV8pS
2V+EOICG3joYEuZ9p5v4M7hlgWtyfgbD9RolWRFsmgh6QCFRtYO+h1pcoDEk0QLGSO0qodAi32SS
pp7Wfz/zkpS0RUrRgfP8iL2iz6vR4XDUxM8ETz68UC9jmySQ5FH5C4GHvy2NHx12axER3bVPk0qX
vr+Ah6htG9sjcy4JsmqqNXNQISSF0oPyp5byHsD5Nch8Co/Ytcx90OFS9KdSUpB+or3veLU8duy5
X/+RCFt8EBpHqqBnolqkJpzizfabHI4mfVsG7VlMR07um8BxrCEJJ7hUd6haIBkS+yJiO69LTHLc
n50k4Mm2/mYCMpJFNQAStKismJeqfIcwY5wsU25mXGfBEIdyf9qs2QLxAXCxL9z7NUPDrg+2atc2
QaqRxtf+0XBbRMfc//uOAKsgdWGx66+qDZUREj8yCvDXEF262Lldo7SCz02AJR+g90ZhY8mQaS11
WmuXf4i10fHsNiLODl7gipAPtrhvQtvuTaN+MGzzpRqCVXYac9g5vZSqgxuM5hBN1vJknoeXWE92
mBnpeeu6O/U3QYEnxH1Py1t8hyyCGDC08Kl9ILLGSM/kv3qLXfyHaGvXSefDR30E/FoePl8CFXrD
Bfi0Y8UdKh26qQmEnz3PDVvcTNtq7ym9YC/qgcdi5x1C63+0lGaLJFZTEM39lYrrbh2RieAo5VoD
BgTPUWHhV1DNvhFeNduScnrOp4BW81JoRIis3Yq6Rl0efb+TwZNBP/oJ8kim0QqM7rJPv/PNJ9Zb
3vPnjNHlgtQWSdgSenX2JaJ6QJTWfAjksBi92YLYIV5aFrHxMW1H7B9kbwFJIQBMYz61pb7GSvbB
ReUGJ4QkbEOVarQ1k0N+BgzFx6bbFYwAvJh/NXU4Ji47RRWetbi2Db8CPXQX+bQKsHUjCCPcMVu4
Ju6+dlUfslJcdk1LcK9ByzOGzlThfCYA71G9yx7Frjfp8oiWsAV9tSYDPLZvznDVi8TIqGTy5Ko1
gI50YgvBn8wqlARndT6DdE/PRWoalU7huXy2COmOZxRVPXqCfPeMPj3d2SjxAJyo5xFVm9D+rht6
Yexx10sMxSyHdlz71+/cxx/uG0BYrGSokLz3LL5cotBR80d3J4LTLCQpnpgxPHrsb/RK6qFf/erG
KUTsb4WP6q7aRMVYJbBM9Nn04mJXJ9JyyU3OOjcHLeuQ7QJdmBXISJBGHHyEVggJuM+UqyfbvIZb
rsl64+rfLZAZH8oL/3JaeqLAfOGRF44lVAb373lrS4XwyR5/X7i92/KyM3OlTNxot4RtWf2gy2gq
QUphblB1FrvHLmQvKcUGVMoywpcEvtaSF4F6N3vOb3RfmPBZnoQoRRZO60avrL1W+kc5wD5gJfNl
UJGuBfCiLKxzSnFnL9sQzmnYHHyhMUtuqDwba2tnlWS0xmDLRrlUzUjsuSeSpjlBU8xQFz+3NwDl
zqAk/4aTNLRmC1chVm+ff6BFymdWrtbY6qMrAp6nGbPbgw8iPHwWV76nNucgflEPe/F+L7iUYlNx
m24z31Aa4OF8h/iberskD/2xBaKBfzhQQGu+ZJ/w8lEjpbKIu+ChrLAWfGvoECm0YRa+LBlbG7Uq
xavHMAndkRvF/cV/tAC6thz56qjK/OqmUEIvcIYMWceSNOtiryVXVjis9/UdnSsF25akc5s9c+A7
5q1iE11joKh1y1jxGWZEkgMzDgPcMXG0hdCfsySD333WTkquyKUkXyErT0v+or+wiFYXx89+RXU/
5G9sle7NkB3LRqm0Umk/rcgH57cpkOEcOWfyJYA6WL/gFGuvO8AiTZAygFAGYBP6MSDf/MIe6Js2
A66OSENOx8vCG8or9PPe1EzZH2WoaZXaLSOW/9nwvovDpCn6oa7DJ+h0HmsKy59lruGg9RmFNvDK
CFZSVO+WAbPNMujr6VGN1YYlpXb32aM2DbwuEt02lD30d74jBAWhW1B1qdy/e6kmhWZ7fA3g31Ct
X4KdiBjNmdX8fn9RtHW2p0ydyCOY9BLxu5CGq55TWHzHHMPlGZtc03JFOxid08MLuR6y2UD2cdHk
9HRJCtlYJg5DE0prce0IyEXwrtah3L+d5koG5JS9OBbblnTF5fppT18WKMRofi7fhc+P3UpEggs6
hnu5n9LPS4OfIOMzE7MFmO249EQy9mcrKU1Aizaqjh5LEank8Eobx7K4LhV/XngcJi252rpNd/IX
MFdv1cAvwKc/qy9LGemT0TzTX6l/B5mtNgXwh3FuHwDe7L0z/EZWCjtbeKXUm8JOlXp+b4cuEb+n
g1d2O7TLqt3fZLV2FOIxcLbGrUvTKvFLzwXoN3mEL6G4e+Nrq5BepH1AnvRqaxxtMhK/XrM/Yxwj
5PGyQtBBfnEDLsr9qVvUs47nWnByTpPZbK7wB6JL9uTvl1ftACqQMmC39Ra/L05zbeeyumwfXBYj
hJB/TCz87MBCO7Bk04ef+IrZAjkNK5pU/BsXh4VyFReaRC3U6m8FX3DSmXcXT/ZYpbn0/3OlQPDl
wnJmXktdKh1DMBkFOdWKVYD6yNpNXQrtBfphFry/7OEAvzD21+Dmpz4b42QxgMZWigREruFNhUWv
EMK/i8xncsKo8yNskvWCcN3NvTTvCOZachxw85d4g7fcz9Y249YkOulga1Hq3LKbNCAoCXfimRrT
af4/Ly9MX6LQIdnS+YAezYh0dphSwTYqMRlmuLhAFvVmwE36qI4m1EQgE09YCqbNeq1QvRteRYyd
22acYdN11j8K9/JEoPZ7cFWLLLZlla+cgUUR69yNiSC5EWN9yCfQlrAvowzIfapXO/H8a1gukzYu
x3kvQ0kL09BxjES+pjtxTvf+WUpmP4Ty5vjqX2nNZ5sBcS8+02ihAr7LI4iuvnaJRyIFqZc3dn9+
UUS6Gq5T3MnjC4xTf+HTzGu62SD1FaH9orz34O9Jd3TFeWj4IJNS0jufjlFqkXu9GYx1AH7Hc57r
h8l+Xz0ND+xFu7+oJMR+wtzB253Ato9EEiFpOgaJSsy73PeKK+H+KbZvC/EtmUz+LLg9hwxuLdhi
MysxBlOFCBlJn4n6bLJlnNEHFjURriwSRjjLvAP5uwxCv8qhIZcVGfGzTiW2R4qyJ5Yktso6jH8q
uBjtKk04fcPTt9TOB4N66b3PzMRs9t/SzHv3Y/9c51UgU0suSSzMOCV/tJMOrE/AQg3Ts52KNARn
HW7SEwq7pfeNSafmBhlhFzyGs/1eBv3GIjYNCno8pGx5XMFdFLo1Cz5IbV9E5KRdwkB8eopdS2sd
bif0st+q3gnNP+rtXW9+TTUtMpbYW0GKizBk6PuXVkH2Z69C56k+orwdZ8M+mA9KiPtp6PFU+0yr
PaRhaFWBREESBbodgGrNX9lhqBilRuevU48E1EaNgSTRlYp8FbtEHwl7RHfmRSwVHVoU50viLwZB
IOiboPDZqwcJEfxiS46yCACC8xtmFLGwjPQlYKef2aVlmcv3EpzEf8SaCWhSqx2cQmbg1Jd0k71D
y6Jk10VU5bv1xzvp5glhFEU/wyrUIojKLTbBIo+Ug+D4ESDseL2mSCMOEZwD4u4cWWtE2rHTmNR9
8bLd0RDa6fR2cgRZnn4p/pnx7/0n6oW3DjL67pVLIqBB8Dy9k0t8UyC1ju5Ijz4jZ3EI+fQDYCUL
hk9cRFYIGzRTnj2u7no57/UTMewB+p4y7UajUV2JE10Ryjx8w6u+26RmoEoh7JCnrkEn3jQ5K+y3
4DOBDSYQtAIQ8/i8+yjFfk7w5ZNBtEtyVkQ3LjQHUpQ5GcSRiT01Mhjgr+aQ1hDVs6AXuEX6bNCB
x+aiisneNqjmg7EYOrQI1k25Ou5UXRN7Y5a7IGB4tV0HlAfP7ffz0jjb3++poUHGxG5LmU9Tx1Sc
GtPTV/wIsi/Ylt+WmyxFnQyxE2U6e7/UD/CuMl+d8LdSGbQF18hPr+noQYMUGHcvF2jSpJFVTLbT
OfKtt/NfsLtSxQh3araJq2sujX7Po716MUhkXAJz3Sn4wUrWSmDQRnwEBq66/YWn6mbkLLlqnuE5
r8//+dFqcPCYMX/4SUV1RZXCjYnyBAQtRkPXrbjT1asEli64ky4kxXrVs159RMshzXRiR8c+o1AX
/C/fo/ddXs2BR7TMRKUPiXDYNlyHtr6NEM0ZhQlPGtUQ+M/qUi9Cbfro3A3CmwnMqcNFb4bclLsW
d5MVVH/bVuO4USp7tIIQwD4utHGJchpOR9MZjNAI6FCDfyRIAcBAEfCARwRQxzx4el1Xwsa4gPIY
T8PSjXsuZRJbitK2CuaxdyPaLJamlsbL/WB0s2MyibbcLcnPOjSOanoLV9zmWkLGuqOvhwR1WYxS
lAvtNXVFpcVNYKDGu61WCph92xbbqKymzbIFm+pzLWYT0lrp3b5KYVdFN8UJ3EuF5lc9JDa3QN/Z
9Ksco1gDTdIq+YwTyOOzF5G4ej/iW+fPrH8rRoeknCkik95ZuZOwbObikt+WnDNATNucdOMCZwWt
ilFetMxrqLcOfgFN/nT3BmEV5ZHTPBsO4Fs6x4kNoU/ANo+y6uqNtNnVS77zeRZR3FlTlY5L2MSP
1cp+KsDH7i9KcZPt1XfyWfVcHpyulwC77nFah5XkPS/mIMz9sNbpqSaHxME/RxXFwLF/RaQVTh3T
Pru3ZrMjB9WBfmG6rrj6OTMTDo8c8Fq/uB8rJBV7V3u5EQokp0SM6b56H/aYnoeiYgIkcP79SGO4
huAJV2BljWC/jeIzpYVB1xa91sO39LXI7x9ShwkahkG2KhSh97e2uMft9ZrXg3ecK3eUdQr2D2v1
tgSMDvdyvEzq+/QBvgKzYmtO3dLamcnPaeIulqPzUnBpDlrBja7tnqUojIgOZSWygZixrM6lbE8t
vOo44pDNDZcCvSly/FxhScquWTqACYCx675IQ6sQrjHkzHNLI9aeLoVp1U6qxx/P3mz4k4PKe8+X
hd9xflQJdfrz2EbdwpYL/PM973op/6QllJJ41zM6EyqJM4bfEcwdevVlKgzyPTM4UfDmNWFUgVh4
lkcbxK8zD+Yr++arFTk6mQ4Z1gYTiRwH+fjP5P1ypBEWKeXSypdQv7iPqmb1bJiA1gvnMy2jjiUU
j3QSST+7xcAvxMdfNNMmJv9gDAGC7nOT4+D5Q6Ws4b+iuWAcNHQK/ljiNsR6jG9oR9VHePif5HmP
u+mYJBPmtaj/C/PT20DESgizqSS8T+JwoS9CumG/VCp1whNHKJ8tTDUiqOktEbsjKij9hnp5APRF
vQ8=
`protect end_protected
|
library verilog;
use verilog.vl_types.all;
entity cw3_vlg_sample_tst is
port(
BT1 : in vl_logic;
BT3 : in vl_logic;
SW0 : in vl_logic;
sampler_tx : out vl_logic
);
end cw3_vlg_sample_tst;
|
-------------------------------------------------------------------------------
-- $Id: inferred_lut4.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- inferred_lut4.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2001-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: inferred_lut4.vhd
--
-- Description: This module is used to infer a LUT4 instantiation in
-- structural VHDL. It is compatable with Synplicity and xst
-- synthesis tools.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- inferred_lut4.vhd
--
-------------------------------------------------------------------------------
-- Author: D.Thorpe
--
-- History:
-- DET 2001-10-11 LUT4 implementation to work around xst lut4 problem with
-- INIT generic. Adapted from XST France work-around
-- solution sent to Bert Tise.
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "Bus_clk", "Bus_clk_div#", "Bus_clk_#x"
-- Bus_rst signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.std_logic_arith.all;
library ieee;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------
entity inferred_lut4 is
generic (INIT : bit_vector(15 downto 0));
port (
O : out std_logic;
I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic
);
end entity inferred_lut4;
-------------------------------------------------------------------------------
architecture implementation of inferred_lut4 is
signal b : std_logic_vector(3 downto 0);
signal tmp : integer range 0 to 15;
begin
b <= (I3, I2, I1, I0);
tmp <= conv_integer(b);
O <= To_StdUlogic(INIT(tmp));
end architecture implementation;
|
package p is
generic(
function generic_f(b:bit) return boolean;
function generic_f(b:boolean) return bit
);
function f(b:bit ) return boolean;
function f(b:boolean) return bit ;
end package;
package body p is
function f(b:bit ) return boolean is begin return generic_f(b); end function;
function f(b:boolean) return bit is begin return generic_f(b); end function;
end package body;
entity e is end entity;
architecture a of e is
function f(b:bit ) return boolean is begin return false; end function;
function f(b:boolean) return bit is begin return '0' ; end function;
package q is new work.p generic map(f,f);
begin
assert q.f('0') report "msg2" severity note;
end architecture;
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/hdl_ofdm_tx/hdl_ofdm_tx.vhd
-- Created: 2018-02-27 13:25:18
--
-- Generated by MATLAB 9.3 and HDL Coder 3.11
--
--
-- -------------------------------------------------------------
-- Rate and Clocking Details
-- -------------------------------------------------------------
-- Model base rate: 0.0001
-- Target subsystem base rate: 0.0001
--
--
-- Clock Enable Sample Time
-- -------------------------------------------------------------
-- ce_out 0.0001
-- -------------------------------------------------------------
--
--
-- Output Signal Clock Enable Sample Time
-- -------------------------------------------------------------
-- tx_signal ce_out 0.0001
-- -------------------------------------------------------------
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: hdl_ofdm_tx
-- Source Path: hdl_ofdm_tx
-- Hierarchy Level: 0
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
LIBRARY work_hdl_modulator;
USE work.hdl_ofdm_tx_pkg.ALL;
ENTITY hdl_ofdm_tx IS
PORT( clk : IN std_logic;
reset : IN std_logic;
clk_enable : IN std_logic;
In1 : IN std_logic_vector(7 DOWNTO 0); -- uint8
ce_out : OUT std_logic;
tx_signal : OUT std_logic_vector(36 DOWNTO 0) -- sfix37_En27
);
END hdl_ofdm_tx;
ARCHITECTURE rtl OF hdl_ofdm_tx IS
-- Component Declarations
COMPONENT hdl_ofdm_tx_tc
PORT( clk : IN std_logic;
reset : IN std_logic;
clk_enable : IN std_logic;
enb : OUT std_logic;
enb_1_1_1 : OUT std_logic;
enb_1_16_0 : OUT std_logic
);
END COMPONENT;
COMPONENT bit_reversal
PORT( u_re : IN vector_of_std_logic_vector16(0 TO 15); -- sfix16_En13 [16]
u_im : IN vector_of_std_logic_vector16(0 TO 15); -- sfix16_En13 [16]
y_re : OUT vector_of_std_logic_vector16(0 TO 15); -- sfix16_En13 [16]
y_im : OUT vector_of_std_logic_vector16(0 TO 15) -- sfix16_En13 [16]
);
END COMPONENT;
COMPONENT ifft
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
dataIn_re : IN vector_of_std_logic_vector16(0 TO 15); -- sfix16_En13 [16]
dataIn_im : IN vector_of_std_logic_vector16(0 TO 15); -- sfix16_En13 [16]
validIn : IN std_logic;
dataOut_re : OUT vector_of_std_logic_vector20(0 TO 15); -- sfix20_En13 [16]
dataOut_im : OUT vector_of_std_logic_vector20(0 TO 15); -- sfix20_En13 [16]
validOut : OUT std_logic
);
END COMPONENT;
COMPONENT hdl_modulator
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
real_signal : IN std_logic_vector(19 DOWNTO 0); -- sfix20_En13
imag_signal : IN std_logic_vector(19 DOWNTO 0); -- sfix20_En13
baseband_mixed_signal : OUT std_logic_vector(36 DOWNTO 0) -- sfix37_En27
);
END COMPONENT;
-- Component Configuration Statements
FOR ALL : hdl_ofdm_tx_tc
USE ENTITY work.hdl_ofdm_tx_tc(rtl);
FOR ALL : bit_reversal
USE ENTITY work.bit_reversal(rtl);
FOR ALL : ifft
USE ENTITY work.ifft(rtl);
FOR ALL : hdl_modulator
USE ENTITY work_hdl_modulator.hdl_modulator_hdl_modulator(rtl);
-- Constants
CONSTANT alpha_table_data_re : vector_of_signed16(0 TO 15) :=
(to_signed(-16#6000#, 16), to_signed(-16#6000#, 16), to_signed(-16#6000#, 16), to_signed(-16#6000#, 16),
to_signed(-16#2000#, 16), to_signed(-16#2000#, 16), to_signed(-16#2000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#6000#, 16), to_signed(16#6000#, 16), to_signed(16#6000#, 16),
to_signed(16#2000#, 16), to_signed(16#2000#, 16), to_signed(16#2000#, 16), to_signed(16#2000#, 16)); -- sfix16 [16]
CONSTANT alpha_table_data_im : vector_of_signed16(0 TO 15) :=
(to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16)); -- sfix16 [16]
CONSTANT alpha_table_data_re_2 : vector_of_signed16(0 TO 15) :=
(to_signed(-16#6000#, 16), to_signed(-16#6000#, 16), to_signed(-16#6000#, 16), to_signed(-16#6000#, 16),
to_signed(-16#2000#, 16), to_signed(-16#2000#, 16), to_signed(-16#2000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#6000#, 16), to_signed(16#6000#, 16), to_signed(16#6000#, 16),
to_signed(16#2000#, 16), to_signed(16#2000#, 16), to_signed(16#2000#, 16), to_signed(16#2000#, 16)); -- sfix16 [16]
CONSTANT alpha_table_data_im_2 : vector_of_signed16(0 TO 15) :=
(to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16)); -- sfix16 [16]
CONSTANT alpha_table_data_re_4 : vector_of_signed16(0 TO 15) :=
(to_signed(-16#6000#, 16), to_signed(-16#6000#, 16), to_signed(-16#6000#, 16), to_signed(-16#6000#, 16),
to_signed(-16#2000#, 16), to_signed(-16#2000#, 16), to_signed(-16#2000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#6000#, 16), to_signed(16#6000#, 16), to_signed(16#6000#, 16),
to_signed(16#2000#, 16), to_signed(16#2000#, 16), to_signed(16#2000#, 16), to_signed(16#2000#, 16)); -- sfix16 [16]
CONSTANT alpha_table_data_im_4 : vector_of_signed16(0 TO 15) :=
(to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16)); -- sfix16 [16]
CONSTANT alpha_table_data_re_6 : vector_of_signed16(0 TO 15) :=
(to_signed(-16#6000#, 16), to_signed(-16#6000#, 16), to_signed(-16#6000#, 16), to_signed(-16#6000#, 16),
to_signed(-16#2000#, 16), to_signed(-16#2000#, 16), to_signed(-16#2000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#6000#, 16), to_signed(16#6000#, 16), to_signed(16#6000#, 16),
to_signed(16#2000#, 16), to_signed(16#2000#, 16), to_signed(16#2000#, 16), to_signed(16#2000#, 16)); -- sfix16 [16]
CONSTANT alpha_table_data_im_6 : vector_of_signed16(0 TO 15) :=
(to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16)); -- sfix16 [16]
CONSTANT alpha_table_data_re_8 : vector_of_signed16(0 TO 15) :=
(to_signed(-16#6000#, 16), to_signed(-16#6000#, 16), to_signed(-16#6000#, 16), to_signed(-16#6000#, 16),
to_signed(-16#2000#, 16), to_signed(-16#2000#, 16), to_signed(-16#2000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#6000#, 16), to_signed(16#6000#, 16), to_signed(16#6000#, 16),
to_signed(16#2000#, 16), to_signed(16#2000#, 16), to_signed(16#2000#, 16), to_signed(16#2000#, 16)); -- sfix16 [16]
CONSTANT alpha_table_data_im_8 : vector_of_signed16(0 TO 15) :=
(to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16)); -- sfix16 [16]
CONSTANT alpha_table_data_re_10 : vector_of_signed16(0 TO 15) :=
(to_signed(-16#6000#, 16), to_signed(-16#6000#, 16), to_signed(-16#6000#, 16), to_signed(-16#6000#, 16),
to_signed(-16#2000#, 16), to_signed(-16#2000#, 16), to_signed(-16#2000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#6000#, 16), to_signed(16#6000#, 16), to_signed(16#6000#, 16),
to_signed(16#2000#, 16), to_signed(16#2000#, 16), to_signed(16#2000#, 16), to_signed(16#2000#, 16)); -- sfix16 [16]
CONSTANT alpha_table_data_im_10 : vector_of_signed16(0 TO 15) :=
(to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16)); -- sfix16 [16]
CONSTANT alpha_table_data_re_12 : vector_of_signed16(0 TO 15) :=
(to_signed(-16#6000#, 16), to_signed(-16#6000#, 16), to_signed(-16#6000#, 16), to_signed(-16#6000#, 16),
to_signed(-16#2000#, 16), to_signed(-16#2000#, 16), to_signed(-16#2000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#6000#, 16), to_signed(16#6000#, 16), to_signed(16#6000#, 16),
to_signed(16#2000#, 16), to_signed(16#2000#, 16), to_signed(16#2000#, 16), to_signed(16#2000#, 16)); -- sfix16 [16]
CONSTANT alpha_table_data_im_12 : vector_of_signed16(0 TO 15) :=
(to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16)); -- sfix16 [16]
CONSTANT alpha_table_data_re_14 : vector_of_signed16(0 TO 15) :=
(to_signed(-16#6000#, 16), to_signed(-16#6000#, 16), to_signed(-16#6000#, 16), to_signed(-16#6000#, 16),
to_signed(-16#2000#, 16), to_signed(-16#2000#, 16), to_signed(-16#2000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#6000#, 16), to_signed(16#6000#, 16), to_signed(16#6000#, 16),
to_signed(16#2000#, 16), to_signed(16#2000#, 16), to_signed(16#2000#, 16), to_signed(16#2000#, 16)); -- sfix16 [16]
CONSTANT alpha_table_data_im_14 : vector_of_signed16(0 TO 15) :=
(to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16)); -- sfix16 [16]
CONSTANT alpha_table_data_re_16 : vector_of_signed16(0 TO 15) :=
(to_signed(-16#6000#, 16), to_signed(-16#6000#, 16), to_signed(-16#6000#, 16), to_signed(-16#6000#, 16),
to_signed(-16#2000#, 16), to_signed(-16#2000#, 16), to_signed(-16#2000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#6000#, 16), to_signed(16#6000#, 16), to_signed(16#6000#, 16),
to_signed(16#2000#, 16), to_signed(16#2000#, 16), to_signed(16#2000#, 16), to_signed(16#2000#, 16)); -- sfix16 [16]
CONSTANT alpha_table_data_im_16 : vector_of_signed16(0 TO 15) :=
(to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16)); -- sfix16 [16]
CONSTANT alpha_table_data_re_18 : vector_of_signed16(0 TO 15) :=
(to_signed(-16#6000#, 16), to_signed(-16#6000#, 16), to_signed(-16#6000#, 16), to_signed(-16#6000#, 16),
to_signed(-16#2000#, 16), to_signed(-16#2000#, 16), to_signed(-16#2000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#6000#, 16), to_signed(16#6000#, 16), to_signed(16#6000#, 16),
to_signed(16#2000#, 16), to_signed(16#2000#, 16), to_signed(16#2000#, 16), to_signed(16#2000#, 16)); -- sfix16 [16]
CONSTANT alpha_table_data_im_18 : vector_of_signed16(0 TO 15) :=
(to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16)); -- sfix16 [16]
CONSTANT alpha_table_data_re_20 : vector_of_signed16(0 TO 15) :=
(to_signed(-16#6000#, 16), to_signed(-16#6000#, 16), to_signed(-16#6000#, 16), to_signed(-16#6000#, 16),
to_signed(-16#2000#, 16), to_signed(-16#2000#, 16), to_signed(-16#2000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#6000#, 16), to_signed(16#6000#, 16), to_signed(16#6000#, 16),
to_signed(16#2000#, 16), to_signed(16#2000#, 16), to_signed(16#2000#, 16), to_signed(16#2000#, 16)); -- sfix16 [16]
CONSTANT alpha_table_data_im_20 : vector_of_signed16(0 TO 15) :=
(to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16)); -- sfix16 [16]
CONSTANT alpha_table_data_re_22 : vector_of_signed16(0 TO 15) :=
(to_signed(-16#6000#, 16), to_signed(-16#6000#, 16), to_signed(-16#6000#, 16), to_signed(-16#6000#, 16),
to_signed(-16#2000#, 16), to_signed(-16#2000#, 16), to_signed(-16#2000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#6000#, 16), to_signed(16#6000#, 16), to_signed(16#6000#, 16),
to_signed(16#2000#, 16), to_signed(16#2000#, 16), to_signed(16#2000#, 16), to_signed(16#2000#, 16)); -- sfix16 [16]
CONSTANT alpha_table_data_im_22 : vector_of_signed16(0 TO 15) :=
(to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16)); -- sfix16 [16]
CONSTANT alpha_table_data_re_24 : vector_of_signed16(0 TO 15) :=
(to_signed(-16#6000#, 16), to_signed(-16#6000#, 16), to_signed(-16#6000#, 16), to_signed(-16#6000#, 16),
to_signed(-16#2000#, 16), to_signed(-16#2000#, 16), to_signed(-16#2000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#6000#, 16), to_signed(16#6000#, 16), to_signed(16#6000#, 16),
to_signed(16#2000#, 16), to_signed(16#2000#, 16), to_signed(16#2000#, 16), to_signed(16#2000#, 16)); -- sfix16 [16]
CONSTANT alpha_table_data_im_24 : vector_of_signed16(0 TO 15) :=
(to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16)); -- sfix16 [16]
CONSTANT alpha_table_data_re_26 : vector_of_signed16(0 TO 15) :=
(to_signed(-16#6000#, 16), to_signed(-16#6000#, 16), to_signed(-16#6000#, 16), to_signed(-16#6000#, 16),
to_signed(-16#2000#, 16), to_signed(-16#2000#, 16), to_signed(-16#2000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#6000#, 16), to_signed(16#6000#, 16), to_signed(16#6000#, 16),
to_signed(16#2000#, 16), to_signed(16#2000#, 16), to_signed(16#2000#, 16), to_signed(16#2000#, 16)); -- sfix16 [16]
CONSTANT alpha_table_data_im_26 : vector_of_signed16(0 TO 15) :=
(to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16)); -- sfix16 [16]
CONSTANT alpha_table_data_re_28 : vector_of_signed16(0 TO 15) :=
(to_signed(-16#6000#, 16), to_signed(-16#6000#, 16), to_signed(-16#6000#, 16), to_signed(-16#6000#, 16),
to_signed(-16#2000#, 16), to_signed(-16#2000#, 16), to_signed(-16#2000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#6000#, 16), to_signed(16#6000#, 16), to_signed(16#6000#, 16),
to_signed(16#2000#, 16), to_signed(16#2000#, 16), to_signed(16#2000#, 16), to_signed(16#2000#, 16)); -- sfix16 [16]
CONSTANT alpha_table_data_im_28 : vector_of_signed16(0 TO 15) :=
(to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16)); -- sfix16 [16]
CONSTANT alpha_table_data_re_30 : vector_of_signed16(0 TO 15) :=
(to_signed(-16#6000#, 16), to_signed(-16#6000#, 16), to_signed(-16#6000#, 16), to_signed(-16#6000#, 16),
to_signed(-16#2000#, 16), to_signed(-16#2000#, 16), to_signed(-16#2000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#6000#, 16), to_signed(16#6000#, 16), to_signed(16#6000#, 16),
to_signed(16#2000#, 16), to_signed(16#2000#, 16), to_signed(16#2000#, 16), to_signed(16#2000#, 16)); -- sfix16 [16]
CONSTANT alpha_table_data_im_30 : vector_of_signed16(0 TO 15) :=
(to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16),
to_signed(16#6000#, 16), to_signed(16#2000#, 16), to_signed(-16#6000#, 16), to_signed(-16#2000#, 16)); -- sfix16 [16]
-- Functions
-- HDLCODER_TO_STDLOGIC
FUNCTION hdlcoder_to_stdlogic(arg: boolean) RETURN std_logic IS
BEGIN
IF arg THEN
RETURN '1';
ELSE
RETURN '0';
END IF;
END FUNCTION;
-- Signals
SIGNAL enb : std_logic;
SIGNAL enb_1_16_0 : std_logic;
SIGNAL enb_1_1_1 : std_logic;
SIGNAL Model_out1 : std_logic_vector(36 DOWNTO 0); -- ufix37
SIGNAL deserializer_contl_cnt : unsigned(4 DOWNTO 0); -- ufix5
SIGNAL deserializer_contl_validOutput : std_logic;
SIGNAL deserializer_innerRegEn : std_logic;
SIGNAL deserializer_innerRegCtrolEn : std_logic;
SIGNAL deserializer_outBypassEn : std_logic;
SIGNAL deserializer_tapDelayEn : std_logic;
SIGNAL deserializer_hOutSignalsContl : std_logic;
SIGNAL deserializer_tapDelayEn_1 : std_logic;
SIGNAL In1_unsigned : unsigned(7 DOWNTO 0); -- uint8
SIGNAL deserializer_tapout : vector_of_unsigned8(0 TO 14); -- uint8 [15]
SIGNAL deserializer_muxOut : vector_of_unsigned8(0 TO 15); -- uint8 [16]
SIGNAL deserializer_out1 : vector_of_unsigned8(0 TO 15); -- uint8 [16]
SIGNAL deserializer_out1_0 : unsigned(7 DOWNTO 0); -- uint8
SIGNAL constellationLUTaddress : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL qam_mod_0_out1_re : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL qam_mod_0_out1_im : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL deserializer_out1_1 : unsigned(7 DOWNTO 0); -- uint8
SIGNAL constellationLUTaddress_1 : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL qam_mod_1_out1_re : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL qam_mod_1_out1_im : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL deserializer_out1_2 : unsigned(7 DOWNTO 0); -- uint8
SIGNAL constellationLUTaddress_2 : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL qam_mod_2_out1_re : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL qam_mod_2_out1_im : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL deserializer_out1_3 : unsigned(7 DOWNTO 0); -- uint8
SIGNAL constellationLUTaddress_3 : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL qam_mod_3_out1_re : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL qam_mod_3_out1_im : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL deserializer_out1_4 : unsigned(7 DOWNTO 0); -- uint8
SIGNAL constellationLUTaddress_4 : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL qam_mod_4_out1_re : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL qam_mod_4_out1_im : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL deserializer_out1_5 : unsigned(7 DOWNTO 0); -- uint8
SIGNAL constellationLUTaddress_5 : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL qam_mod_5_out1_re : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL qam_mod_5_out1_im : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL deserializer_out1_6 : unsigned(7 DOWNTO 0); -- uint8
SIGNAL constellationLUTaddress_6 : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL qam_mod_6_out1_re : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL qam_mod_6_out1_im : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL deserializer_out1_7 : unsigned(7 DOWNTO 0); -- uint8
SIGNAL constellationLUTaddress_7 : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL qam_mod_7_out1_re : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL qam_mod_7_out1_im : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL deserializer_out1_8 : unsigned(7 DOWNTO 0); -- uint8
SIGNAL constellationLUTaddress_8 : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL qam_mod_8_out1_re : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL qam_mod_8_out1_im : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL deserializer_out1_9 : unsigned(7 DOWNTO 0); -- uint8
SIGNAL constellationLUTaddress_9 : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL qam_mod_9_out1_re : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL qam_mod_9_out1_im : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL deserializer_out1_10 : unsigned(7 DOWNTO 0); -- uint8
SIGNAL constellationLUTaddress_10 : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL qam_mod_10_out1_re : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL qam_mod_10_out1_im : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL deserializer_out1_11 : unsigned(7 DOWNTO 0); -- uint8
SIGNAL constellationLUTaddress_11 : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL qam_mod_11_out1_re : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL qam_mod_11_out1_im : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL deserializer_out1_12 : unsigned(7 DOWNTO 0); -- uint8
SIGNAL constellationLUTaddress_12 : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL qam_mod_12_out1_re : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL qam_mod_12_out1_im : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL deserializer_out1_13 : unsigned(7 DOWNTO 0); -- uint8
SIGNAL constellationLUTaddress_13 : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL qam_mod_13_out1_re : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL qam_mod_13_out1_im : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL deserializer_out1_14 : unsigned(7 DOWNTO 0); -- uint8
SIGNAL constellationLUTaddress_14 : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL qam_mod_14_out1_re : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL qam_mod_14_out1_im : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL deserializer_out1_15 : unsigned(7 DOWNTO 0); -- uint8
SIGNAL constellationLUTaddress_15 : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL qam_mod_15_out1_re : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL qam_mod_15_out1_im : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL Mux_out1_re : vector_of_signed16(0 TO 15); -- sfix16_En13 [16]
SIGNAL Mux_out1_im : vector_of_signed16(0 TO 15); -- sfix16_En13 [16]
SIGNAL Mux_out1_re_1 : vector_of_std_logic_vector16(0 TO 15); -- ufix16 [16]
SIGNAL Mux_out1_im_1 : vector_of_std_logic_vector16(0 TO 15); -- ufix16 [16]
SIGNAL y_re : vector_of_std_logic_vector16(0 TO 15); -- ufix16 [16]
SIGNAL y_im : vector_of_std_logic_vector16(0 TO 15); -- ufix16 [16]
SIGNAL deserializer_out2 : std_logic;
SIGNAL ifft_out1_re : vector_of_std_logic_vector20(0 TO 15); -- ufix20 [16]
SIGNAL ifft_out1_im : vector_of_std_logic_vector20(0 TO 15); -- ufix20 [16]
SIGNAL ifft_out2 : std_logic;
SIGNAL real_serializer_contl_cnt : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL real_serializer_invldSignal : std_logic;
SIGNAL ifft_out1_re_signed : vector_of_signed20(0 TO 15); -- sfix20_En13 [16]
SIGNAL ifft_out1_im_signed : vector_of_signed20(0 TO 15); -- sfix20_En13 [16]
SIGNAL serial_in_1 : vector_of_signed20(0 TO 15); -- sfix20_En13 [16]
SIGNAL imag_serializer_contl_cnt : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL imag_serializer_invldSignal : std_logic;
SIGNAL serial_in_1_1 : vector_of_signed20(0 TO 15); -- sfix20_En13 [16]
SIGNAL real_serializer_data : vector_of_signed20(0 TO 14); -- sfix20 [15]
SIGNAL real_serializer_data_next : vector_of_signed20(0 TO 14); -- sfix20_En13 [15]
SIGNAL serializer_PostProcessed_2 : signed(19 DOWNTO 0); -- sfix20_En13
SIGNAL imag_serializer_data : vector_of_signed20(0 TO 14); -- sfix20 [15]
SIGNAL imag_serializer_data_next : vector_of_signed20(0 TO 14); -- sfix20_En13 [15]
SIGNAL serializer_PostProcessed_3 : signed(19 DOWNTO 0); -- sfix20_En13
BEGIN
u_hdl_ofdm_tx_tc : hdl_ofdm_tx_tc
PORT MAP( clk => clk,
reset => reset,
clk_enable => clk_enable,
enb => enb,
enb_1_1_1 => enb_1_1_1,
enb_1_16_0 => enb_1_16_0
);
u_bit_reversal : bit_reversal
PORT MAP( u_re => Mux_out1_re_1, -- sfix16_En13 [16]
u_im => Mux_out1_im_1, -- sfix16_En13 [16]
y_re => y_re, -- sfix16_En13 [16]
y_im => y_im -- sfix16_En13 [16]
);
u_ifft : ifft
PORT MAP( clk => clk,
reset => reset,
enb_1_16_0 => enb_1_16_0,
dataIn_re => y_re, -- sfix16_En13 [16]
dataIn_im => y_im, -- sfix16_En13 [16]
validIn => deserializer_out2,
dataOut_re => ifft_out1_re, -- sfix20_En13 [16]
dataOut_im => ifft_out1_im, -- sfix20_En13 [16]
validOut => ifft_out2
);
u_Model : hdl_modulator
PORT MAP( clk => clk,
reset => reset,
enb => enb,
real_signal => std_logic_vector(serializer_PostProcessed_2), -- sfix20_En13
imag_signal => std_logic_vector(serializer_PostProcessed_3), -- sfix20_En13
baseband_mixed_signal => Model_out1 -- sfix37_En27
);
deserializer_contl_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
deserializer_contl_cnt <= to_unsigned(16#00#, 5);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
IF deserializer_contl_cnt = to_unsigned(16#0F#, 5) THEN
deserializer_contl_cnt <= to_unsigned(16#00#, 5);
ELSE
deserializer_contl_cnt <= deserializer_contl_cnt + to_unsigned(16#01#, 5);
END IF;
END IF;
END IF;
END PROCESS deserializer_contl_process;
deserializer_tapDelayEn <= hdlcoder_to_stdlogic(deserializer_contl_cnt < to_unsigned(16#0F#, 5));
deserializer_contl_validOutput <= '1' WHEN deserializer_contl_cnt = to_unsigned(16#0F#, 5) ELSE
'0';
deserializer_hOutSignalsContl <= '1' WHEN deserializer_contl_validOutput = '1' ELSE
'0';
deserializer_innerRegEn <= '1' WHEN deserializer_contl_validOutput = '1' ELSE
'0';
deserializer_innerRegCtrolEn <= '1' WHEN deserializer_contl_validOutput = '1' ELSE
'0';
deserializer_outBypassEn <= '1';
deserializer_tapDelayEn_1 <= enb AND deserializer_tapDelayEn;
In1_unsigned <= unsigned(In1);
deserializer_tapDelayComp_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
deserializer_tapout <= (OTHERS => to_unsigned(16#00#, 8));
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' AND deserializer_tapDelayEn_1 = '1' THEN
deserializer_tapout(14) <= In1_unsigned;
deserializer_tapout(0 TO 13) <= deserializer_tapout(1 TO 14);
END IF;
END IF;
END PROCESS deserializer_tapDelayComp_process;
deserializer_muxOut(0) <= deserializer_tapout(0);
deserializer_muxOut(1) <= deserializer_tapout(1);
deserializer_muxOut(2) <= deserializer_tapout(2);
deserializer_muxOut(3) <= deserializer_tapout(3);
deserializer_muxOut(4) <= deserializer_tapout(4);
deserializer_muxOut(5) <= deserializer_tapout(5);
deserializer_muxOut(6) <= deserializer_tapout(6);
deserializer_muxOut(7) <= deserializer_tapout(7);
deserializer_muxOut(8) <= deserializer_tapout(8);
deserializer_muxOut(9) <= deserializer_tapout(9);
deserializer_muxOut(10) <= deserializer_tapout(10);
deserializer_muxOut(11) <= deserializer_tapout(11);
deserializer_muxOut(12) <= deserializer_tapout(12);
deserializer_muxOut(13) <= deserializer_tapout(13);
deserializer_muxOut(14) <= deserializer_tapout(14);
deserializer_muxOut(15) <= unsigned(In1);
deserializer_regComp_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
deserializer_out1 <= (OTHERS => to_unsigned(16#00#, 8));
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' AND deserializer_innerRegEn = '1' THEN
deserializer_out1 <= deserializer_muxOut;
END IF;
END IF;
END PROCESS deserializer_regComp_process;
deserializer_out1_0 <= deserializer_out1(0);
constellationLUTaddress <= deserializer_out1_0(3 DOWNTO 0);
qam_mod_0_out1_re <= alpha_table_data_re(to_integer(constellationLUTaddress));
qam_mod_0_out1_im <= alpha_table_data_im(to_integer(constellationLUTaddress));
deserializer_out1_1 <= deserializer_out1(1);
constellationLUTaddress_1 <= deserializer_out1_1(3 DOWNTO 0);
qam_mod_1_out1_re <= alpha_table_data_re_2(to_integer(constellationLUTaddress_1));
qam_mod_1_out1_im <= alpha_table_data_im_2(to_integer(constellationLUTaddress_1));
deserializer_out1_2 <= deserializer_out1(2);
constellationLUTaddress_2 <= deserializer_out1_2(3 DOWNTO 0);
qam_mod_2_out1_re <= alpha_table_data_re_4(to_integer(constellationLUTaddress_2));
qam_mod_2_out1_im <= alpha_table_data_im_4(to_integer(constellationLUTaddress_2));
deserializer_out1_3 <= deserializer_out1(3);
constellationLUTaddress_3 <= deserializer_out1_3(3 DOWNTO 0);
qam_mod_3_out1_re <= alpha_table_data_re_6(to_integer(constellationLUTaddress_3));
qam_mod_3_out1_im <= alpha_table_data_im_6(to_integer(constellationLUTaddress_3));
deserializer_out1_4 <= deserializer_out1(4);
constellationLUTaddress_4 <= deserializer_out1_4(3 DOWNTO 0);
qam_mod_4_out1_re <= alpha_table_data_re_8(to_integer(constellationLUTaddress_4));
qam_mod_4_out1_im <= alpha_table_data_im_8(to_integer(constellationLUTaddress_4));
deserializer_out1_5 <= deserializer_out1(5);
constellationLUTaddress_5 <= deserializer_out1_5(3 DOWNTO 0);
qam_mod_5_out1_re <= alpha_table_data_re_10(to_integer(constellationLUTaddress_5));
qam_mod_5_out1_im <= alpha_table_data_im_10(to_integer(constellationLUTaddress_5));
deserializer_out1_6 <= deserializer_out1(6);
constellationLUTaddress_6 <= deserializer_out1_6(3 DOWNTO 0);
qam_mod_6_out1_re <= alpha_table_data_re_12(to_integer(constellationLUTaddress_6));
qam_mod_6_out1_im <= alpha_table_data_im_12(to_integer(constellationLUTaddress_6));
deserializer_out1_7 <= deserializer_out1(7);
constellationLUTaddress_7 <= deserializer_out1_7(3 DOWNTO 0);
qam_mod_7_out1_re <= alpha_table_data_re_14(to_integer(constellationLUTaddress_7));
qam_mod_7_out1_im <= alpha_table_data_im_14(to_integer(constellationLUTaddress_7));
deserializer_out1_8 <= deserializer_out1(8);
constellationLUTaddress_8 <= deserializer_out1_8(3 DOWNTO 0);
qam_mod_8_out1_re <= alpha_table_data_re_16(to_integer(constellationLUTaddress_8));
qam_mod_8_out1_im <= alpha_table_data_im_16(to_integer(constellationLUTaddress_8));
deserializer_out1_9 <= deserializer_out1(9);
constellationLUTaddress_9 <= deserializer_out1_9(3 DOWNTO 0);
qam_mod_9_out1_re <= alpha_table_data_re_18(to_integer(constellationLUTaddress_9));
qam_mod_9_out1_im <= alpha_table_data_im_18(to_integer(constellationLUTaddress_9));
deserializer_out1_10 <= deserializer_out1(10);
constellationLUTaddress_10 <= deserializer_out1_10(3 DOWNTO 0);
qam_mod_10_out1_re <= alpha_table_data_re_20(to_integer(constellationLUTaddress_10));
qam_mod_10_out1_im <= alpha_table_data_im_20(to_integer(constellationLUTaddress_10));
deserializer_out1_11 <= deserializer_out1(11);
constellationLUTaddress_11 <= deserializer_out1_11(3 DOWNTO 0);
qam_mod_11_out1_re <= alpha_table_data_re_22(to_integer(constellationLUTaddress_11));
qam_mod_11_out1_im <= alpha_table_data_im_22(to_integer(constellationLUTaddress_11));
deserializer_out1_12 <= deserializer_out1(12);
constellationLUTaddress_12 <= deserializer_out1_12(3 DOWNTO 0);
qam_mod_12_out1_re <= alpha_table_data_re_24(to_integer(constellationLUTaddress_12));
qam_mod_12_out1_im <= alpha_table_data_im_24(to_integer(constellationLUTaddress_12));
deserializer_out1_13 <= deserializer_out1(13);
constellationLUTaddress_13 <= deserializer_out1_13(3 DOWNTO 0);
qam_mod_13_out1_re <= alpha_table_data_re_26(to_integer(constellationLUTaddress_13));
qam_mod_13_out1_im <= alpha_table_data_im_26(to_integer(constellationLUTaddress_13));
deserializer_out1_14 <= deserializer_out1(14);
constellationLUTaddress_14 <= deserializer_out1_14(3 DOWNTO 0);
qam_mod_14_out1_re <= alpha_table_data_re_28(to_integer(constellationLUTaddress_14));
qam_mod_14_out1_im <= alpha_table_data_im_28(to_integer(constellationLUTaddress_14));
deserializer_out1_15 <= deserializer_out1(15);
constellationLUTaddress_15 <= deserializer_out1_15(3 DOWNTO 0);
qam_mod_15_out1_re <= alpha_table_data_re_30(to_integer(constellationLUTaddress_15));
qam_mod_15_out1_im <= alpha_table_data_im_30(to_integer(constellationLUTaddress_15));
Mux_out1_re(0) <= qam_mod_0_out1_re;
Mux_out1_re(1) <= qam_mod_1_out1_re;
Mux_out1_re(2) <= qam_mod_2_out1_re;
Mux_out1_re(3) <= qam_mod_3_out1_re;
Mux_out1_re(4) <= qam_mod_4_out1_re;
Mux_out1_re(5) <= qam_mod_5_out1_re;
Mux_out1_re(6) <= qam_mod_6_out1_re;
Mux_out1_re(7) <= qam_mod_7_out1_re;
Mux_out1_re(8) <= qam_mod_8_out1_re;
Mux_out1_re(9) <= qam_mod_9_out1_re;
Mux_out1_re(10) <= qam_mod_10_out1_re;
Mux_out1_re(11) <= qam_mod_11_out1_re;
Mux_out1_re(12) <= qam_mod_12_out1_re;
Mux_out1_re(13) <= qam_mod_13_out1_re;
Mux_out1_re(14) <= qam_mod_14_out1_re;
Mux_out1_re(15) <= qam_mod_15_out1_re;
outputgen3: FOR k IN 0 TO 15 GENERATE
Mux_out1_re_1(k) <= std_logic_vector(Mux_out1_re(k));
END GENERATE;
Mux_out1_im(0) <= qam_mod_0_out1_im;
Mux_out1_im(1) <= qam_mod_1_out1_im;
Mux_out1_im(2) <= qam_mod_2_out1_im;
Mux_out1_im(3) <= qam_mod_3_out1_im;
Mux_out1_im(4) <= qam_mod_4_out1_im;
Mux_out1_im(5) <= qam_mod_5_out1_im;
Mux_out1_im(6) <= qam_mod_6_out1_im;
Mux_out1_im(7) <= qam_mod_7_out1_im;
Mux_out1_im(8) <= qam_mod_8_out1_im;
Mux_out1_im(9) <= qam_mod_9_out1_im;
Mux_out1_im(10) <= qam_mod_10_out1_im;
Mux_out1_im(11) <= qam_mod_11_out1_im;
Mux_out1_im(12) <= qam_mod_12_out1_im;
Mux_out1_im(13) <= qam_mod_13_out1_im;
Mux_out1_im(14) <= qam_mod_14_out1_im;
Mux_out1_im(15) <= qam_mod_15_out1_im;
outputgen2: FOR k IN 0 TO 15 GENERATE
Mux_out1_im_1(k) <= std_logic_vector(Mux_out1_im(k));
END GENERATE;
deserializer_regComp_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
deserializer_out2 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' AND deserializer_innerRegCtrolEn = '1' THEN
deserializer_out2 <= deserializer_hOutSignalsContl;
END IF;
END IF;
END PROCESS deserializer_regComp_1_process;
real_serializer_contl_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
real_serializer_contl_cnt <= to_unsigned(16#0#, 4);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
IF real_serializer_contl_cnt = to_unsigned(16#F#, 4) THEN
real_serializer_contl_cnt <= to_unsigned(16#0#, 4);
ELSE
real_serializer_contl_cnt <= real_serializer_contl_cnt + to_unsigned(16#1#, 4);
END IF;
END IF;
END IF;
END PROCESS real_serializer_contl_process;
real_serializer_invldSignal <= '1' WHEN real_serializer_contl_cnt = to_unsigned(16#0#, 4) ELSE
'0';
outputgen1: FOR k IN 0 TO 15 GENERATE
ifft_out1_re_signed(k) <= signed(ifft_out1_re(k));
END GENERATE;
serial_in_1 <= ifft_out1_re_signed;
imag_serializer_contl_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
imag_serializer_contl_cnt <= to_unsigned(16#0#, 4);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
IF imag_serializer_contl_cnt = to_unsigned(16#F#, 4) THEN
imag_serializer_contl_cnt <= to_unsigned(16#0#, 4);
ELSE
imag_serializer_contl_cnt <= imag_serializer_contl_cnt + to_unsigned(16#1#, 4);
END IF;
END IF;
END IF;
END PROCESS imag_serializer_contl_process;
imag_serializer_invldSignal <= '1' WHEN imag_serializer_contl_cnt = to_unsigned(16#0#, 4) ELSE
'0';
outputgen: FOR k IN 0 TO 15 GENERATE
ifft_out1_im_signed(k) <= signed(ifft_out1_im(k));
END GENERATE;
serial_in_1_1 <= ifft_out1_im_signed;
real_serializer_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
real_serializer_data <= (OTHERS => to_signed(16#00000#, 20));
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
real_serializer_data <= real_serializer_data_next;
END IF;
END IF;
END PROCESS real_serializer_process;
real_serializer_output : PROCESS (real_serializer_data, real_serializer_invldSignal, serial_in_1)
BEGIN
real_serializer_data_next <= real_serializer_data;
IF real_serializer_invldSignal /= '0' THEN
serializer_PostProcessed_2 <= serial_in_1(0);
ELSE
serializer_PostProcessed_2 <= real_serializer_data(0);
END IF;
IF real_serializer_invldSignal /= '0' THEN
real_serializer_data_next(0 TO 14) <= serial_in_1(1 TO 15);
ELSE
real_serializer_data_next(0 TO 13) <= real_serializer_data(1 TO 14);
real_serializer_data_next(14) <= serial_in_1(15);
END IF;
END PROCESS real_serializer_output;
imag_serializer_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
imag_serializer_data <= (OTHERS => to_signed(16#00000#, 20));
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
imag_serializer_data <= imag_serializer_data_next;
END IF;
END IF;
END PROCESS imag_serializer_process;
imag_serializer_output : PROCESS (imag_serializer_data, imag_serializer_invldSignal, serial_in_1_1)
BEGIN
imag_serializer_data_next <= imag_serializer_data;
IF imag_serializer_invldSignal /= '0' THEN
serializer_PostProcessed_3 <= serial_in_1_1(0);
ELSE
serializer_PostProcessed_3 <= imag_serializer_data(0);
END IF;
IF imag_serializer_invldSignal /= '0' THEN
imag_serializer_data_next(0 TO 14) <= serial_in_1_1(1 TO 15);
ELSE
imag_serializer_data_next(0 TO 13) <= imag_serializer_data(1 TO 14);
imag_serializer_data_next(14) <= serial_in_1_1(15);
END IF;
END PROCESS imag_serializer_output;
ce_out <= enb_1_1_1;
tx_signal <= Model_out1;
END rtl;
|
-------------------------------------------------------------------------------
--
-- (c) B&R, 2011
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity sync is
generic(
doSync_g : boolean := true
);
port(
clk : in std_logic;
rst : in std_logic;
din : in std_logic;
dout : out std_logic
);
end sync;
architecture rtl of sync is
signal s0, s1 : std_logic := '0';
begin
genSync : if doSync_g = true generate
process(clk)--, rst)
begin
if clk = '1' and clk'event then
s0 <= din; --reg0
s1 <= s0; --reg1
end if;
end process;
end generate;
dout <= s1 when doSync_g = true else din; --reg1 output
end rtl;
|
-------------------------------------------------------------------------------
--
-- (c) B&R, 2011
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
entity sync is
generic(
doSync_g : boolean := true
);
port(
clk : in std_logic;
rst : in std_logic;
din : in std_logic;
dout : out std_logic
);
end sync;
architecture rtl of sync is
signal s0, s1 : std_logic := '0';
begin
genSync : if doSync_g = true generate
process(clk)--, rst)
begin
if clk = '1' and clk'event then
s0 <= din; --reg0
s1 <= s0; --reg1
end if;
end process;
end generate;
dout <= s1 when doSync_g = true else din; --reg1 output
end rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2206.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02206ent IS
END c07s02b06x00p01n01i02206ent;
ARCHITECTURE c07s02b06x00p01n01i02206arch OF c07s02b06x00p01n01i02206ent IS
BEGIN
TESTING: PROCESS
constant a : real := 10.0 / 2.0;
BEGIN
assert NOT(a = 5.0)
report "***PASSED TEST: c07s02b06x00p01n01i02206"
severity NOTE;
assert (a = 5.0)
report "***FAILED TEST: c07s02b06x00p01n01i02206 - Multiplying operators are predefined only for integer and floating point types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02206arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2206.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02206ent IS
END c07s02b06x00p01n01i02206ent;
ARCHITECTURE c07s02b06x00p01n01i02206arch OF c07s02b06x00p01n01i02206ent IS
BEGIN
TESTING: PROCESS
constant a : real := 10.0 / 2.0;
BEGIN
assert NOT(a = 5.0)
report "***PASSED TEST: c07s02b06x00p01n01i02206"
severity NOTE;
assert (a = 5.0)
report "***FAILED TEST: c07s02b06x00p01n01i02206 - Multiplying operators are predefined only for integer and floating point types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02206arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2206.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p01n01i02206ent IS
END c07s02b06x00p01n01i02206ent;
ARCHITECTURE c07s02b06x00p01n01i02206arch OF c07s02b06x00p01n01i02206ent IS
BEGIN
TESTING: PROCESS
constant a : real := 10.0 / 2.0;
BEGIN
assert NOT(a = 5.0)
report "***PASSED TEST: c07s02b06x00p01n01i02206"
severity NOTE;
assert (a = 5.0)
report "***FAILED TEST: c07s02b06x00p01n01i02206 - Multiplying operators are predefined only for integer and floating point types."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p01n01i02206arch;
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
--
-- Title : DCT
-- Design : MDCT Core
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : ROMO.VHD
-- Created : Sat Mar 5 7:37 2006
-- Modified : Dez. 30 2008 - Andreas Bergmann
-- Libs and Typeconversion fixed due Xilinx Synthesis errors
--
--------------------------------------------------------------------------------
--
-- Description : ROM for DCT matrix constant cosine coefficients (odd part)
--
--------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-- 5:0
-- 5:4 = select matrix row (1 out of 4)
-- 3:0 = select precomputed MAC ( 1 out of 16)
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
use WORK.MDCT_PKG.all;
entity ROMO is
port(
addr : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
clk : in STD_LOGIC;
datao : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0)
);
end ROMO;
architecture RTL of ROMO is
type ROM_TYPE is array (0 to 2**ROMADDR_W-1)
of STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
constant rom : ROM_TYPE :=
(
(others => '0'),
std_logic_vector( to_signed(GP, ROMDATA_W) ),
std_logic_vector( to_signed(FP, ROMDATA_W) ),
std_logic_vector( to_signed(FP+GP, ROMDATA_W) ),
std_logic_vector( to_signed(EP, ROMDATA_W) ),
std_logic_vector( to_signed(EP+GP, ROMDATA_W) ),
std_logic_vector( to_signed(EP+FP, ROMDATA_W) ),
std_logic_vector( to_signed(EP+FP+GP, ROMDATA_W) ),
std_logic_vector( to_signed(DP, ROMDATA_W) ),
std_logic_vector( to_signed(DP+GP, ROMDATA_W) ),
std_logic_vector( to_signed(DP+FP, ROMDATA_W) ),
std_logic_vector( to_signed(DP+FP+GP, ROMDATA_W) ),
std_logic_vector( to_signed(DP+EP, ROMDATA_W) ),
std_logic_vector( to_signed(DP+EP+GP, ROMDATA_W) ),
std_logic_vector( to_signed(DP+EP+FP, ROMDATA_W) ),
std_logic_vector( to_signed(DP+EP+FP+GP,ROMDATA_W) ),
(others => '0'),
std_logic_vector( to_signed(FM, ROMDATA_W) ),
std_logic_vector( to_signed(DM, ROMDATA_W) ),
std_logic_vector( to_signed(DM+FM, ROMDATA_W) ),
std_logic_vector( to_signed(GM, ROMDATA_W) ),
std_logic_vector( to_signed(GM+FM, ROMDATA_W) ),
std_logic_vector( to_signed(GM+DM, ROMDATA_W) ),
std_logic_vector( to_signed(GM+DM+FM, ROMDATA_W) ),
std_logic_vector( to_signed(EP, ROMDATA_W) ),
std_logic_vector( to_signed(EP+FM, ROMDATA_W) ),
std_logic_vector( to_signed(EP+DM, ROMDATA_W) ),
std_logic_vector( to_signed(EP+DM+FM, ROMDATA_W) ),
std_logic_vector( to_signed(EP+GM, ROMDATA_W) ),
std_logic_vector( to_signed(EP+GM+FM, ROMDATA_W) ),
std_logic_vector( to_signed(EP+GM+DM, ROMDATA_W) ),
std_logic_vector( to_signed(EP+GM+DM+FM, ROMDATA_W) ),
(others => '0'),
std_logic_vector( to_signed(EP, ROMDATA_W) ),
std_logic_vector( to_signed(GP, ROMDATA_W) ),
std_logic_vector( to_signed(EP+GP, ROMDATA_W) ),
std_logic_vector( to_signed(DM, ROMDATA_W) ),
std_logic_vector( to_signed(DM+EP, ROMDATA_W) ),
std_logic_vector( to_signed(DM+GP, ROMDATA_W) ),
std_logic_vector( to_signed(DM+GP+EP, ROMDATA_W) ),
std_logic_vector( to_signed(FP, ROMDATA_W) ),
std_logic_vector( to_signed(FP+EP, ROMDATA_W) ),
std_logic_vector( to_signed(FP+GP, ROMDATA_W) ),
std_logic_vector( to_signed(FP+GP+EP, ROMDATA_W) ),
std_logic_vector( to_signed(FP+DM, ROMDATA_W) ),
std_logic_vector( to_signed(FP+DM+EP, ROMDATA_W) ),
std_logic_vector( to_signed(FP+DM+GP, ROMDATA_W) ),
std_logic_vector( to_signed(FP+DM+GP+EP, ROMDATA_W) ),
(others => '0'),
std_logic_vector( to_signed(DM, ROMDATA_W) ),
std_logic_vector( to_signed(EP, ROMDATA_W) ),
std_logic_vector( to_signed(EP+DM, ROMDATA_W) ),
std_logic_vector( to_signed(FM, ROMDATA_W) ),
std_logic_vector( to_signed(FM+DM, ROMDATA_W) ),
std_logic_vector( to_signed(FM+EP, ROMDATA_W) ),
std_logic_vector( to_signed(FM+EP+DM, ROMDATA_W) ),
std_logic_vector( to_signed(GP, ROMDATA_W) ),
std_logic_vector( to_signed(GP+DM, ROMDATA_W) ),
std_logic_vector( to_signed(GP+EP, ROMDATA_W) ),
std_logic_vector( to_signed(GP+EP+DM, ROMDATA_W) ),
std_logic_vector( to_signed(GP+FM, ROMDATA_W) ),
std_logic_vector( to_signed(GP+FM+DM, ROMDATA_W) ),
std_logic_vector( to_signed(GP+FM+EP, ROMDATA_W) ),
std_logic_vector( to_signed(GP+FM+EP+DM, ROMDATA_W) )
);
begin
process(clk)
begin
if clk = '1' and clk'event then
datao <= rom( to_integer(unsigned(addr)) );
end if;
end process;
end RTL;
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
--
-- Title : DCT
-- Design : MDCT Core
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : ROMO.VHD
-- Created : Sat Mar 5 7:37 2006
-- Modified : Dez. 30 2008 - Andreas Bergmann
-- Libs and Typeconversion fixed due Xilinx Synthesis errors
--
--------------------------------------------------------------------------------
--
-- Description : ROM for DCT matrix constant cosine coefficients (odd part)
--
--------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-- 5:0
-- 5:4 = select matrix row (1 out of 4)
-- 3:0 = select precomputed MAC ( 1 out of 16)
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
use WORK.MDCT_PKG.all;
entity ROMO is
port(
addr : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
clk : in STD_LOGIC;
datao : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0)
);
end ROMO;
architecture RTL of ROMO is
type ROM_TYPE is array (0 to 2**ROMADDR_W-1)
of STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
constant rom : ROM_TYPE :=
(
(others => '0'),
std_logic_vector( to_signed(GP, ROMDATA_W) ),
std_logic_vector( to_signed(FP, ROMDATA_W) ),
std_logic_vector( to_signed(FP+GP, ROMDATA_W) ),
std_logic_vector( to_signed(EP, ROMDATA_W) ),
std_logic_vector( to_signed(EP+GP, ROMDATA_W) ),
std_logic_vector( to_signed(EP+FP, ROMDATA_W) ),
std_logic_vector( to_signed(EP+FP+GP, ROMDATA_W) ),
std_logic_vector( to_signed(DP, ROMDATA_W) ),
std_logic_vector( to_signed(DP+GP, ROMDATA_W) ),
std_logic_vector( to_signed(DP+FP, ROMDATA_W) ),
std_logic_vector( to_signed(DP+FP+GP, ROMDATA_W) ),
std_logic_vector( to_signed(DP+EP, ROMDATA_W) ),
std_logic_vector( to_signed(DP+EP+GP, ROMDATA_W) ),
std_logic_vector( to_signed(DP+EP+FP, ROMDATA_W) ),
std_logic_vector( to_signed(DP+EP+FP+GP,ROMDATA_W) ),
(others => '0'),
std_logic_vector( to_signed(FM, ROMDATA_W) ),
std_logic_vector( to_signed(DM, ROMDATA_W) ),
std_logic_vector( to_signed(DM+FM, ROMDATA_W) ),
std_logic_vector( to_signed(GM, ROMDATA_W) ),
std_logic_vector( to_signed(GM+FM, ROMDATA_W) ),
std_logic_vector( to_signed(GM+DM, ROMDATA_W) ),
std_logic_vector( to_signed(GM+DM+FM, ROMDATA_W) ),
std_logic_vector( to_signed(EP, ROMDATA_W) ),
std_logic_vector( to_signed(EP+FM, ROMDATA_W) ),
std_logic_vector( to_signed(EP+DM, ROMDATA_W) ),
std_logic_vector( to_signed(EP+DM+FM, ROMDATA_W) ),
std_logic_vector( to_signed(EP+GM, ROMDATA_W) ),
std_logic_vector( to_signed(EP+GM+FM, ROMDATA_W) ),
std_logic_vector( to_signed(EP+GM+DM, ROMDATA_W) ),
std_logic_vector( to_signed(EP+GM+DM+FM, ROMDATA_W) ),
(others => '0'),
std_logic_vector( to_signed(EP, ROMDATA_W) ),
std_logic_vector( to_signed(GP, ROMDATA_W) ),
std_logic_vector( to_signed(EP+GP, ROMDATA_W) ),
std_logic_vector( to_signed(DM, ROMDATA_W) ),
std_logic_vector( to_signed(DM+EP, ROMDATA_W) ),
std_logic_vector( to_signed(DM+GP, ROMDATA_W) ),
std_logic_vector( to_signed(DM+GP+EP, ROMDATA_W) ),
std_logic_vector( to_signed(FP, ROMDATA_W) ),
std_logic_vector( to_signed(FP+EP, ROMDATA_W) ),
std_logic_vector( to_signed(FP+GP, ROMDATA_W) ),
std_logic_vector( to_signed(FP+GP+EP, ROMDATA_W) ),
std_logic_vector( to_signed(FP+DM, ROMDATA_W) ),
std_logic_vector( to_signed(FP+DM+EP, ROMDATA_W) ),
std_logic_vector( to_signed(FP+DM+GP, ROMDATA_W) ),
std_logic_vector( to_signed(FP+DM+GP+EP, ROMDATA_W) ),
(others => '0'),
std_logic_vector( to_signed(DM, ROMDATA_W) ),
std_logic_vector( to_signed(EP, ROMDATA_W) ),
std_logic_vector( to_signed(EP+DM, ROMDATA_W) ),
std_logic_vector( to_signed(FM, ROMDATA_W) ),
std_logic_vector( to_signed(FM+DM, ROMDATA_W) ),
std_logic_vector( to_signed(FM+EP, ROMDATA_W) ),
std_logic_vector( to_signed(FM+EP+DM, ROMDATA_W) ),
std_logic_vector( to_signed(GP, ROMDATA_W) ),
std_logic_vector( to_signed(GP+DM, ROMDATA_W) ),
std_logic_vector( to_signed(GP+EP, ROMDATA_W) ),
std_logic_vector( to_signed(GP+EP+DM, ROMDATA_W) ),
std_logic_vector( to_signed(GP+FM, ROMDATA_W) ),
std_logic_vector( to_signed(GP+FM+DM, ROMDATA_W) ),
std_logic_vector( to_signed(GP+FM+EP, ROMDATA_W) ),
std_logic_vector( to_signed(GP+FM+EP+DM, ROMDATA_W) )
);
begin
process(clk)
begin
if clk = '1' and clk'event then
datao <= rom( to_integer(unsigned(addr)) );
end if;
end process;
end RTL;
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
--
-- Title : DCT
-- Design : MDCT Core
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : ROMO.VHD
-- Created : Sat Mar 5 7:37 2006
-- Modified : Dez. 30 2008 - Andreas Bergmann
-- Libs and Typeconversion fixed due Xilinx Synthesis errors
--
--------------------------------------------------------------------------------
--
-- Description : ROM for DCT matrix constant cosine coefficients (odd part)
--
--------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-- 5:0
-- 5:4 = select matrix row (1 out of 4)
-- 3:0 = select precomputed MAC ( 1 out of 16)
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
use WORK.MDCT_PKG.all;
entity ROMO is
port(
addr : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
clk : in STD_LOGIC;
datao : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0)
);
end ROMO;
architecture RTL of ROMO is
type ROM_TYPE is array (0 to 2**ROMADDR_W-1)
of STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
constant rom : ROM_TYPE :=
(
(others => '0'),
std_logic_vector( to_signed(GP, ROMDATA_W) ),
std_logic_vector( to_signed(FP, ROMDATA_W) ),
std_logic_vector( to_signed(FP+GP, ROMDATA_W) ),
std_logic_vector( to_signed(EP, ROMDATA_W) ),
std_logic_vector( to_signed(EP+GP, ROMDATA_W) ),
std_logic_vector( to_signed(EP+FP, ROMDATA_W) ),
std_logic_vector( to_signed(EP+FP+GP, ROMDATA_W) ),
std_logic_vector( to_signed(DP, ROMDATA_W) ),
std_logic_vector( to_signed(DP+GP, ROMDATA_W) ),
std_logic_vector( to_signed(DP+FP, ROMDATA_W) ),
std_logic_vector( to_signed(DP+FP+GP, ROMDATA_W) ),
std_logic_vector( to_signed(DP+EP, ROMDATA_W) ),
std_logic_vector( to_signed(DP+EP+GP, ROMDATA_W) ),
std_logic_vector( to_signed(DP+EP+FP, ROMDATA_W) ),
std_logic_vector( to_signed(DP+EP+FP+GP,ROMDATA_W) ),
(others => '0'),
std_logic_vector( to_signed(FM, ROMDATA_W) ),
std_logic_vector( to_signed(DM, ROMDATA_W) ),
std_logic_vector( to_signed(DM+FM, ROMDATA_W) ),
std_logic_vector( to_signed(GM, ROMDATA_W) ),
std_logic_vector( to_signed(GM+FM, ROMDATA_W) ),
std_logic_vector( to_signed(GM+DM, ROMDATA_W) ),
std_logic_vector( to_signed(GM+DM+FM, ROMDATA_W) ),
std_logic_vector( to_signed(EP, ROMDATA_W) ),
std_logic_vector( to_signed(EP+FM, ROMDATA_W) ),
std_logic_vector( to_signed(EP+DM, ROMDATA_W) ),
std_logic_vector( to_signed(EP+DM+FM, ROMDATA_W) ),
std_logic_vector( to_signed(EP+GM, ROMDATA_W) ),
std_logic_vector( to_signed(EP+GM+FM, ROMDATA_W) ),
std_logic_vector( to_signed(EP+GM+DM, ROMDATA_W) ),
std_logic_vector( to_signed(EP+GM+DM+FM, ROMDATA_W) ),
(others => '0'),
std_logic_vector( to_signed(EP, ROMDATA_W) ),
std_logic_vector( to_signed(GP, ROMDATA_W) ),
std_logic_vector( to_signed(EP+GP, ROMDATA_W) ),
std_logic_vector( to_signed(DM, ROMDATA_W) ),
std_logic_vector( to_signed(DM+EP, ROMDATA_W) ),
std_logic_vector( to_signed(DM+GP, ROMDATA_W) ),
std_logic_vector( to_signed(DM+GP+EP, ROMDATA_W) ),
std_logic_vector( to_signed(FP, ROMDATA_W) ),
std_logic_vector( to_signed(FP+EP, ROMDATA_W) ),
std_logic_vector( to_signed(FP+GP, ROMDATA_W) ),
std_logic_vector( to_signed(FP+GP+EP, ROMDATA_W) ),
std_logic_vector( to_signed(FP+DM, ROMDATA_W) ),
std_logic_vector( to_signed(FP+DM+EP, ROMDATA_W) ),
std_logic_vector( to_signed(FP+DM+GP, ROMDATA_W) ),
std_logic_vector( to_signed(FP+DM+GP+EP, ROMDATA_W) ),
(others => '0'),
std_logic_vector( to_signed(DM, ROMDATA_W) ),
std_logic_vector( to_signed(EP, ROMDATA_W) ),
std_logic_vector( to_signed(EP+DM, ROMDATA_W) ),
std_logic_vector( to_signed(FM, ROMDATA_W) ),
std_logic_vector( to_signed(FM+DM, ROMDATA_W) ),
std_logic_vector( to_signed(FM+EP, ROMDATA_W) ),
std_logic_vector( to_signed(FM+EP+DM, ROMDATA_W) ),
std_logic_vector( to_signed(GP, ROMDATA_W) ),
std_logic_vector( to_signed(GP+DM, ROMDATA_W) ),
std_logic_vector( to_signed(GP+EP, ROMDATA_W) ),
std_logic_vector( to_signed(GP+EP+DM, ROMDATA_W) ),
std_logic_vector( to_signed(GP+FM, ROMDATA_W) ),
std_logic_vector( to_signed(GP+FM+DM, ROMDATA_W) ),
std_logic_vector( to_signed(GP+FM+EP, ROMDATA_W) ),
std_logic_vector( to_signed(GP+FM+EP+DM, ROMDATA_W) )
);
begin
process(clk)
begin
if clk = '1' and clk'event then
datao <= rom( to_integer(unsigned(addr)) );
end if;
end process;
end RTL;
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
--
-- Title : DCT
-- Design : MDCT Core
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : ROMO.VHD
-- Created : Sat Mar 5 7:37 2006
-- Modified : Dez. 30 2008 - Andreas Bergmann
-- Libs and Typeconversion fixed due Xilinx Synthesis errors
--
--------------------------------------------------------------------------------
--
-- Description : ROM for DCT matrix constant cosine coefficients (odd part)
--
--------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-- 5:0
-- 5:4 = select matrix row (1 out of 4)
-- 3:0 = select precomputed MAC ( 1 out of 16)
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
use WORK.MDCT_PKG.all;
entity ROMO is
port(
addr : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
clk : in STD_LOGIC;
datao : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0)
);
end ROMO;
architecture RTL of ROMO is
type ROM_TYPE is array (0 to 2**ROMADDR_W-1)
of STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
constant rom : ROM_TYPE :=
(
(others => '0'),
std_logic_vector( to_signed(GP, ROMDATA_W) ),
std_logic_vector( to_signed(FP, ROMDATA_W) ),
std_logic_vector( to_signed(FP+GP, ROMDATA_W) ),
std_logic_vector( to_signed(EP, ROMDATA_W) ),
std_logic_vector( to_signed(EP+GP, ROMDATA_W) ),
std_logic_vector( to_signed(EP+FP, ROMDATA_W) ),
std_logic_vector( to_signed(EP+FP+GP, ROMDATA_W) ),
std_logic_vector( to_signed(DP, ROMDATA_W) ),
std_logic_vector( to_signed(DP+GP, ROMDATA_W) ),
std_logic_vector( to_signed(DP+FP, ROMDATA_W) ),
std_logic_vector( to_signed(DP+FP+GP, ROMDATA_W) ),
std_logic_vector( to_signed(DP+EP, ROMDATA_W) ),
std_logic_vector( to_signed(DP+EP+GP, ROMDATA_W) ),
std_logic_vector( to_signed(DP+EP+FP, ROMDATA_W) ),
std_logic_vector( to_signed(DP+EP+FP+GP,ROMDATA_W) ),
(others => '0'),
std_logic_vector( to_signed(FM, ROMDATA_W) ),
std_logic_vector( to_signed(DM, ROMDATA_W) ),
std_logic_vector( to_signed(DM+FM, ROMDATA_W) ),
std_logic_vector( to_signed(GM, ROMDATA_W) ),
std_logic_vector( to_signed(GM+FM, ROMDATA_W) ),
std_logic_vector( to_signed(GM+DM, ROMDATA_W) ),
std_logic_vector( to_signed(GM+DM+FM, ROMDATA_W) ),
std_logic_vector( to_signed(EP, ROMDATA_W) ),
std_logic_vector( to_signed(EP+FM, ROMDATA_W) ),
std_logic_vector( to_signed(EP+DM, ROMDATA_W) ),
std_logic_vector( to_signed(EP+DM+FM, ROMDATA_W) ),
std_logic_vector( to_signed(EP+GM, ROMDATA_W) ),
std_logic_vector( to_signed(EP+GM+FM, ROMDATA_W) ),
std_logic_vector( to_signed(EP+GM+DM, ROMDATA_W) ),
std_logic_vector( to_signed(EP+GM+DM+FM, ROMDATA_W) ),
(others => '0'),
std_logic_vector( to_signed(EP, ROMDATA_W) ),
std_logic_vector( to_signed(GP, ROMDATA_W) ),
std_logic_vector( to_signed(EP+GP, ROMDATA_W) ),
std_logic_vector( to_signed(DM, ROMDATA_W) ),
std_logic_vector( to_signed(DM+EP, ROMDATA_W) ),
std_logic_vector( to_signed(DM+GP, ROMDATA_W) ),
std_logic_vector( to_signed(DM+GP+EP, ROMDATA_W) ),
std_logic_vector( to_signed(FP, ROMDATA_W) ),
std_logic_vector( to_signed(FP+EP, ROMDATA_W) ),
std_logic_vector( to_signed(FP+GP, ROMDATA_W) ),
std_logic_vector( to_signed(FP+GP+EP, ROMDATA_W) ),
std_logic_vector( to_signed(FP+DM, ROMDATA_W) ),
std_logic_vector( to_signed(FP+DM+EP, ROMDATA_W) ),
std_logic_vector( to_signed(FP+DM+GP, ROMDATA_W) ),
std_logic_vector( to_signed(FP+DM+GP+EP, ROMDATA_W) ),
(others => '0'),
std_logic_vector( to_signed(DM, ROMDATA_W) ),
std_logic_vector( to_signed(EP, ROMDATA_W) ),
std_logic_vector( to_signed(EP+DM, ROMDATA_W) ),
std_logic_vector( to_signed(FM, ROMDATA_W) ),
std_logic_vector( to_signed(FM+DM, ROMDATA_W) ),
std_logic_vector( to_signed(FM+EP, ROMDATA_W) ),
std_logic_vector( to_signed(FM+EP+DM, ROMDATA_W) ),
std_logic_vector( to_signed(GP, ROMDATA_W) ),
std_logic_vector( to_signed(GP+DM, ROMDATA_W) ),
std_logic_vector( to_signed(GP+EP, ROMDATA_W) ),
std_logic_vector( to_signed(GP+EP+DM, ROMDATA_W) ),
std_logic_vector( to_signed(GP+FM, ROMDATA_W) ),
std_logic_vector( to_signed(GP+FM+DM, ROMDATA_W) ),
std_logic_vector( to_signed(GP+FM+EP, ROMDATA_W) ),
std_logic_vector( to_signed(GP+FM+EP+DM, ROMDATA_W) )
);
begin
process(clk)
begin
if clk = '1' and clk'event then
datao <= rom( to_integer(unsigned(addr)) );
end if;
end process;
end RTL;
|
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
--
-- Title : DCT
-- Design : MDCT Core
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : ROMO.VHD
-- Created : Sat Mar 5 7:37 2006
-- Modified : Dez. 30 2008 - Andreas Bergmann
-- Libs and Typeconversion fixed due Xilinx Synthesis errors
--
--------------------------------------------------------------------------------
--
-- Description : ROM for DCT matrix constant cosine coefficients (odd part)
--
--------------------------------------------------------------------------------
-- //////////////////////////////////////////////////////////////////////////////
-- /// Copyright (c) 2013, Jahanzeb Ahmad
-- /// All rights reserved.
-- ///
-- /// Redistribution and use in source and binary forms, with or without modification,
-- /// are permitted provided that the following conditions are met:
-- ///
-- /// * Redistributions of source code must retain the above copyright notice,
-- /// this list of conditions and the following disclaimer.
-- /// * Redistributions in binary form must reproduce the above copyright notice,
-- /// this list of conditions and the following disclaimer in the documentation and/or
-- /// other materials provided with the distribution.
-- ///
-- /// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- /// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-- /// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
-- /// SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- /// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- /// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-- /// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- /// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- /// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- /// POSSIBILITY OF SUCH DAMAGE.
-- ///
-- ///
-- /// * http://opensource.org/licenses/MIT
-- /// * http://copyfree.org/licenses/mit/license.txt
-- ///
-- //////////////////////////////////////////////////////////////////////////////
-- 5:0
-- 5:4 = select matrix row (1 out of 4)
-- 3:0 = select precomputed MAC ( 1 out of 16)
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
use WORK.MDCT_PKG.all;
entity ROMO is
port(
addr : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
clk : in STD_LOGIC;
datao : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0)
);
end ROMO;
architecture RTL of ROMO is
type ROM_TYPE is array (0 to 2**ROMADDR_W-1)
of STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
constant rom : ROM_TYPE :=
(
(others => '0'),
std_logic_vector( to_signed(GP, ROMDATA_W) ),
std_logic_vector( to_signed(FP, ROMDATA_W) ),
std_logic_vector( to_signed(FP+GP, ROMDATA_W) ),
std_logic_vector( to_signed(EP, ROMDATA_W) ),
std_logic_vector( to_signed(EP+GP, ROMDATA_W) ),
std_logic_vector( to_signed(EP+FP, ROMDATA_W) ),
std_logic_vector( to_signed(EP+FP+GP, ROMDATA_W) ),
std_logic_vector( to_signed(DP, ROMDATA_W) ),
std_logic_vector( to_signed(DP+GP, ROMDATA_W) ),
std_logic_vector( to_signed(DP+FP, ROMDATA_W) ),
std_logic_vector( to_signed(DP+FP+GP, ROMDATA_W) ),
std_logic_vector( to_signed(DP+EP, ROMDATA_W) ),
std_logic_vector( to_signed(DP+EP+GP, ROMDATA_W) ),
std_logic_vector( to_signed(DP+EP+FP, ROMDATA_W) ),
std_logic_vector( to_signed(DP+EP+FP+GP,ROMDATA_W) ),
(others => '0'),
std_logic_vector( to_signed(FM, ROMDATA_W) ),
std_logic_vector( to_signed(DM, ROMDATA_W) ),
std_logic_vector( to_signed(DM+FM, ROMDATA_W) ),
std_logic_vector( to_signed(GM, ROMDATA_W) ),
std_logic_vector( to_signed(GM+FM, ROMDATA_W) ),
std_logic_vector( to_signed(GM+DM, ROMDATA_W) ),
std_logic_vector( to_signed(GM+DM+FM, ROMDATA_W) ),
std_logic_vector( to_signed(EP, ROMDATA_W) ),
std_logic_vector( to_signed(EP+FM, ROMDATA_W) ),
std_logic_vector( to_signed(EP+DM, ROMDATA_W) ),
std_logic_vector( to_signed(EP+DM+FM, ROMDATA_W) ),
std_logic_vector( to_signed(EP+GM, ROMDATA_W) ),
std_logic_vector( to_signed(EP+GM+FM, ROMDATA_W) ),
std_logic_vector( to_signed(EP+GM+DM, ROMDATA_W) ),
std_logic_vector( to_signed(EP+GM+DM+FM, ROMDATA_W) ),
(others => '0'),
std_logic_vector( to_signed(EP, ROMDATA_W) ),
std_logic_vector( to_signed(GP, ROMDATA_W) ),
std_logic_vector( to_signed(EP+GP, ROMDATA_W) ),
std_logic_vector( to_signed(DM, ROMDATA_W) ),
std_logic_vector( to_signed(DM+EP, ROMDATA_W) ),
std_logic_vector( to_signed(DM+GP, ROMDATA_W) ),
std_logic_vector( to_signed(DM+GP+EP, ROMDATA_W) ),
std_logic_vector( to_signed(FP, ROMDATA_W) ),
std_logic_vector( to_signed(FP+EP, ROMDATA_W) ),
std_logic_vector( to_signed(FP+GP, ROMDATA_W) ),
std_logic_vector( to_signed(FP+GP+EP, ROMDATA_W) ),
std_logic_vector( to_signed(FP+DM, ROMDATA_W) ),
std_logic_vector( to_signed(FP+DM+EP, ROMDATA_W) ),
std_logic_vector( to_signed(FP+DM+GP, ROMDATA_W) ),
std_logic_vector( to_signed(FP+DM+GP+EP, ROMDATA_W) ),
(others => '0'),
std_logic_vector( to_signed(DM, ROMDATA_W) ),
std_logic_vector( to_signed(EP, ROMDATA_W) ),
std_logic_vector( to_signed(EP+DM, ROMDATA_W) ),
std_logic_vector( to_signed(FM, ROMDATA_W) ),
std_logic_vector( to_signed(FM+DM, ROMDATA_W) ),
std_logic_vector( to_signed(FM+EP, ROMDATA_W) ),
std_logic_vector( to_signed(FM+EP+DM, ROMDATA_W) ),
std_logic_vector( to_signed(GP, ROMDATA_W) ),
std_logic_vector( to_signed(GP+DM, ROMDATA_W) ),
std_logic_vector( to_signed(GP+EP, ROMDATA_W) ),
std_logic_vector( to_signed(GP+EP+DM, ROMDATA_W) ),
std_logic_vector( to_signed(GP+FM, ROMDATA_W) ),
std_logic_vector( to_signed(GP+FM+DM, ROMDATA_W) ),
std_logic_vector( to_signed(GP+FM+EP, ROMDATA_W) ),
std_logic_vector( to_signed(GP+FM+EP+DM, ROMDATA_W) )
);
begin
process(clk)
begin
if clk = '1' and clk'event then
datao <= rom( to_integer(unsigned(addr)) );
end if;
end process;
end RTL;
|
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: clk_10mhz.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 11.1 Build 173 11/01/2011 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2011 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY clk_10mhz IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC
);
END clk_10mhz;
ARCHITECTURE SYN OF clk_10mhz IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire4_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire4 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
width_clock : NATURAL
);
PORT (
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire4_bv(0 DOWNTO 0) <= "0";
sub_wire4 <= To_stdlogicvector(sub_wire4_bv);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
sub_wire2 <= inclk0;
sub_wire3 <= sub_wire4(0 DOWNTO 0) & sub_wire2;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 5,
clk0_duty_cycle => 50,
clk0_multiply_by => 1,
clk0_phase_shift => "0",
compensate_clock => "CLK0",
inclk0_input_frequency => 20000,
intended_device_family => "Cyclone IV E",
lpm_hint => "CBX_MODULE_PREFIX=clk_10mhz",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_UNUSED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_UNUSED",
port_clk2 => "PORT_UNUSED",
port_clk3 => "PORT_UNUSED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
width_clock => 5
)
PORT MAP (
inclk => sub_wire3,
clk => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "10.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "clk_10mhz.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_10mhz.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_10mhz.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_10mhz.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_10mhz.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_10mhz.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clk_10mhz_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
package xilnames is
type state is (state1, state2, state3);
end xilnames;
use work.xilnames.all;
package xilname1 is
constant state1 : state := state1;
end xilname1;
|
package xilnames is
type state is (state1, state2, state3);
end xilnames;
use work.xilnames.all;
package xilname1 is
constant state1 : state := state1;
end xilname1;
|
package xilnames is
type state is (state1, state2, state3);
end xilnames;
use work.xilnames.all;
package xilname1 is
constant state1 : state := state1;
end xilname1;
|
-------------------------------------------------------------------------------
-- ____ _____ __ __ ________ _______
-- | | \ \ | \ | | |__ __| | __ \
-- |____| \____\ | \| | | | | |__> )
-- ____ ____ | |\ \ | | | | __ <
-- | | | | | | \ | | | | |__> )
-- |____| |____| |__| \__| |__| |_______/
--
-- NTB University of Applied Sciences in Technology
--
-- Campus Buchs - Werdenbergstrasse 4 - 9471 Buchs - Switzerland
-- Campus Waldau - Schoenauweg 4 - 9013 St. Gallen - Switzerland
--
-- Web http://www.ntb.ch Tel. +41 81 755 33 11
--
-------------------------------------------------------------------------------
-- Copyright 2013 NTB University of Applied Sciences in Technology
-------------------------------------------------------------------------------
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.i2c_master_pkg.ALL;
ENTITY i2c_master_rtl_tb IS
END ENTITY i2c_master_rtl_tb;
ARCHITECTURE sim OF i2c_master_rtl_tb IS
--Sumulation Parameter:
CONSTANT main_period : TIME := 30.3 ns; -- 250MHz
SIGNAL sl_clk : STD_LOGIC := '0';
SIGNAL sl_reset_n : STD_LOGIC := '0';
SIGNAL osl_scl : STD_LOGIC;
SIGNAL oisl_sda : STD_LOGIC := '0';
SIGNAL islv_dev_address : STD_LOGIC_VECTOR(DEV_ADDRESS_WIDTH-1 DOWNTO 0) := "1010101";
SIGNAL islv_register_address : STD_LOGIC_VECTOR(REGISTER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL islv_write_data : STD_LOGIC_VECTOR(REGISTER_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL oslv_read_data : STD_LOGIC_VECTOR(REGISTER_WIDTH-1 DOWNTO 0);
SIGNAL isl_start_transfer : STD_LOGIC := '0';
SIGNAL isl_write_n_read : STD_LOGIC := '0';
SIGNAL isl_enable_burst_transfer : STD_LOGIC := '1';
SIGNAL osl_transfer_done : STD_LOGIC;
BEGIN
--create component
my_unit_under_test : i2c_master
GENERIC MAP(
BASE_CLK => 250000000
)
PORT MAP(
isl_clk => sl_clk,
isl_reset_n => sl_reset_n,
osl_scl => osl_scl,
oisl_sda => oisl_sda,
--internal signals
islv_dev_address => islv_dev_address,
islv_register_address => islv_register_address,
islv_write_data => islv_write_data,
oslv_read_data => oslv_read_data,
isl_start_transfer => isl_start_transfer,
isl_write_n_read => isl_write_n_read,
isl_enable_burst_transfer => isl_enable_burst_transfer,
osl_transfer_done => osl_transfer_done
);
sl_clk <= NOT sl_clk after main_period/2;
tb_main_proc : PROCESS
BEGIN
sl_reset_n <= '0';
WAIT FOR 20*main_period;
sl_reset_n <= '1';
WAIT FOR 10*main_period;
isl_start_transfer <= '1';
WAIT FOR 10*main_period;
isl_start_transfer <= '0';
WAIT FOR 1ms;
ASSERT false REPORT "End of simulation" SEVERITY FAILURE;
END PROCESS tb_main_proc;
END ARCHITECTURE sim;
|
-- -----------------------------------------------------------------------
--
-- Syntiac VHDL support files.
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2009 by Peter Wendrich ([email protected])
-- http://www.syntiac.com
--
-- This source file is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This source file is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- -----------------------------------------------------------------------
--
-- Video dither block. Converts high precision video signal to
-- lower precision by dithering. The dither input can for example
-- come from the current X and Y coordinates or a pseudo random source.
--
-- Improved version of the video_dither.vhd using a multiplier and scaler
-- to have a more linear output range. The original has a tendency to clip
-- at higher output levels.
--
-- If bypass input is 1 the dither algorithm is disabled and the output
-- is equal to the input.
--
-- This component has a delay of one clock cycle.
--
-- -----------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- -----------------------------------------------------------------------
entity video_dither is
generic (
dBits : integer := 8;
qBits : integer := 5;
ditherBits : integer := 4;
scaler_bits : integer := 9
);
port (
clk : in std_logic;
clkEna : in std_logic := '1';
bypass : in std_logic := '0';
dither : in unsigned(ditherBits-1 downto 0);
d : in unsigned(dBits-1 downto 0);
q : out unsigned(qBits-1 downto 0)
);
end entity;
-- -----------------------------------------------------------------------
architecture rtl of video_dither is
constant input_bits : integer := dBits + 1;
constant output_bits : integer := scaler_bits + input_bits;
constant scaler_const : integer := (2**(output_bits-1)-1) / ((2**dBits)+(2**ditherBits)-2);
signal q_reg : unsigned(q'range) := (others => '0');
begin
assert(dither'length <= d'length);
q <= q_reg;
process(clk)
variable input : unsigned(input_bits-1 downto 0);
variable scaler : unsigned(scaler_bits-1 downto 0);
variable output : unsigned(output_bits-1 downto 0);
begin
input := ("0" & d) + dither;
scaler := to_unsigned(scaler_const, scaler_bits);
output := input * scaler;
if rising_edge(clk) then
if clkEna = '1' then
q_reg <= output(output'high-1 downto output'high-q'length);
if bypass = '1' then
q_reg <= d(d'high downto (d'high-q'high));
end if;
end if;
end if;
end process;
end architecture;
|
-------------------------------------------------------------------------------
-- Title : Shared clocking and resets
-- Project : 10GBASE-R
-------------------------------------------------------------------------------
-- File : ten_gig_eth_pcs_pma_0_shared_clock_and_reset.vhd
-------------------------------------------------------------------------------
-- Description: This file contains the
-- 10GBASE-R clocking and reset logic which can be shared between multiple cores
-------------------------------------------------------------------------------
-- (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ten_gig_eth_pcs_pma_0_shared_clock_and_reset is
port
(
areset : in std_logic;
refclk_p : in std_logic;
refclk_n : in std_logic;
refclk : out std_logic;
txoutclk : in std_logic;
coreclk : out std_logic;
dclk : out std_logic; -- ymei
qplllock : in std_logic;
areset_coreclk : out std_logic;
gttxreset : out std_logic;
gtrxreset : out std_logic;
txuserrdy : out std_logic := '0';
txusrclk : out std_logic;
txusrclk2 : out std_logic;
qpllreset : out std_logic;
reset_counter_done : out std_logic
);
end entity ten_gig_eth_pcs_pma_0_shared_clock_and_reset;
architecture wrapper of ten_gig_eth_pcs_pma_0_shared_clock_and_reset is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of wrapper : architecture is "yes";
component ten_gig_eth_pcs_pma_0_ff_synchronizer_rst2
generic
(
C_NUM_SYNC_REGS : integer := 3;
C_RVAL : std_logic := '0'
);
port
(
clk : in std_logic;
rst : in std_logic;
data_in : in std_logic;
data_out : out std_logic
);
end component;
signal coreclk_buf : std_logic;
signal coreclk_int : std_logic;
signal refclk_i : std_logic;
signal txusrclk_i : std_logic;
signal txusrclk2_i : std_logic;
signal gttxreset_i : std_logic;
signal reset_i : std_logic;
signal areset_coreclk_i : std_logic;
signal qplllock_txusrclk2_rst : std_logic;
signal qplllock_txusrclk2_i : std_logic;
signal gttxreset_txusrclk2_i : std_logic;
signal reset_counter : std_logic_vector(8 downto 0) := "000000000";
signal reset_pulse : std_logic_vector(3 downto 0) := "1110";
begin
reset_counter_done <= reset_counter(8);
-- ymei
-- ibufds_inst : IBUFDS
-- GENERIC MAP (
-- DIFF_TERM => true, -- Differential Termination
-- IBUF_LOW_PWR => false, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
-- IOSTANDARD => "LVDS"
-- )
-- PORT MAP (
-- O => refclk_i, -- Buffer output
-- I => refclk_p, -- Diff_p buffer input (connect directly to top-level port)
-- IB => refclk_n -- Diff_n buffer input (connect directly to top-level port)
-- );
ibufds_inst : IBUFDS_GTE2
port map
(
O => refclk_i,
ODIV2 => open,
CEB => '0',
I => refclk_p,
IB => refclk_n
);
refclk <= refclk_i;
txoutclk_bufg_i : BUFG
port map
(
I => txoutclk,
O => txusrclk_i
);
coreclk_bufg_i : BUFG
port map
(
I => refclk_i,
O => coreclk_int
);
dclk <= coreclk_int; -- ymei
txusrclk2 <= txusrclk_i;
txusrclk2_i <= txusrclk_i;
coreclk <= coreclk_int;
txusrclk <= txusrclk_i;
reset_i <= not qplllock ;
areset_coreclk <= areset_coreclk_i;
-- Asynch reset synchronizers...
areset_coreclk_sync_i : ten_gig_eth_pcs_pma_0_ff_synchronizer_rst2
generic map(
C_NUM_SYNC_REGS => 5,
C_RVAL => '1')
port map(
clk => coreclk_int,
rst => areset,
data_in => '0',
data_out => areset_coreclk_i
);
qplllock_txusrclk2_rst <= not(qplllock);
qplllock_txusrclk2_sync_i : ten_gig_eth_pcs_pma_0_ff_synchronizer_rst2
generic map(
C_NUM_SYNC_REGS => 5,
C_RVAL => '0')
port map(
clk => txusrclk2_i,
rst => qplllock_txusrclk2_rst,
data_in => '1',
data_out => qplllock_txusrclk2_i
);
gttxreset_txusrclk2_sync_i : ten_gig_eth_pcs_pma_0_ff_synchronizer_rst2
generic map(
C_NUM_SYNC_REGS => 5,
C_RVAL => '1')
port map(
clk => txusrclk2_i,
rst => gttxreset_i,
data_in => '0',
data_out => gttxreset_txusrclk2_i
);
-- Hold off release the GT resets until 500ns after configuration.
-- 256 ticks at the minimum possible 2.56ns period (390MHz) will be >> 500 ns.
reset_proc1: process (coreclk_int)
begin
if(coreclk_int'event and coreclk_int = '1') then
if(reset_counter(8) = '0') then
reset_counter <= reset_counter + 1;
else
reset_counter <= reset_counter;
end if;
end if;
end process;
reset_proc2: process (coreclk_int)
begin
if(coreclk_int'event and coreclk_int = '1') then
if(areset_coreclk_i = '1') then
reset_pulse <= "1110";
elsif(reset_counter(8) = '1') then
reset_pulse(3) <= '0';
reset_pulse(2 downto 0) <= reset_pulse(3 downto 1);
end if;
end if;
end process;
gttxreset_i <= reset_pulse(0);
gttxreset <= gttxreset_i;
gtrxreset <= reset_pulse(0);
qpllreset <= reset_pulse(0);
reset_proc5 : process (txusrclk2_i, gttxreset_txusrclk2_i)
begin
if(gttxreset_txusrclk2_i = '1') then
txuserrdy <= '0';
elsif(txusrclk2_i'event and txusrclk2_i = '1') then
txuserrdy <= qplllock_txusrclk2_i;
end if;
end process;
end wrapper;
|
-------------------------------------------------------------------------------
-- Title : Shared clocking and resets
-- Project : 10GBASE-R
-------------------------------------------------------------------------------
-- File : ten_gig_eth_pcs_pma_0_shared_clock_and_reset.vhd
-------------------------------------------------------------------------------
-- Description: This file contains the
-- 10GBASE-R clocking and reset logic which can be shared between multiple cores
-------------------------------------------------------------------------------
-- (c) Copyright 2009 - 2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity ten_gig_eth_pcs_pma_0_shared_clock_and_reset is
port
(
areset : in std_logic;
refclk_p : in std_logic;
refclk_n : in std_logic;
refclk : out std_logic;
txoutclk : in std_logic;
coreclk : out std_logic;
dclk : out std_logic; -- ymei
qplllock : in std_logic;
areset_coreclk : out std_logic;
gttxreset : out std_logic;
gtrxreset : out std_logic;
txuserrdy : out std_logic := '0';
txusrclk : out std_logic;
txusrclk2 : out std_logic;
qpllreset : out std_logic;
reset_counter_done : out std_logic
);
end entity ten_gig_eth_pcs_pma_0_shared_clock_and_reset;
architecture wrapper of ten_gig_eth_pcs_pma_0_shared_clock_and_reset is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of wrapper : architecture is "yes";
component ten_gig_eth_pcs_pma_0_ff_synchronizer_rst2
generic
(
C_NUM_SYNC_REGS : integer := 3;
C_RVAL : std_logic := '0'
);
port
(
clk : in std_logic;
rst : in std_logic;
data_in : in std_logic;
data_out : out std_logic
);
end component;
signal coreclk_buf : std_logic;
signal coreclk_int : std_logic;
signal refclk_i : std_logic;
signal txusrclk_i : std_logic;
signal txusrclk2_i : std_logic;
signal gttxreset_i : std_logic;
signal reset_i : std_logic;
signal areset_coreclk_i : std_logic;
signal qplllock_txusrclk2_rst : std_logic;
signal qplllock_txusrclk2_i : std_logic;
signal gttxreset_txusrclk2_i : std_logic;
signal reset_counter : std_logic_vector(8 downto 0) := "000000000";
signal reset_pulse : std_logic_vector(3 downto 0) := "1110";
begin
reset_counter_done <= reset_counter(8);
-- ymei
-- ibufds_inst : IBUFDS
-- GENERIC MAP (
-- DIFF_TERM => true, -- Differential Termination
-- IBUF_LOW_PWR => false, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
-- IOSTANDARD => "LVDS"
-- )
-- PORT MAP (
-- O => refclk_i, -- Buffer output
-- I => refclk_p, -- Diff_p buffer input (connect directly to top-level port)
-- IB => refclk_n -- Diff_n buffer input (connect directly to top-level port)
-- );
ibufds_inst : IBUFDS_GTE2
port map
(
O => refclk_i,
ODIV2 => open,
CEB => '0',
I => refclk_p,
IB => refclk_n
);
refclk <= refclk_i;
txoutclk_bufg_i : BUFG
port map
(
I => txoutclk,
O => txusrclk_i
);
coreclk_bufg_i : BUFG
port map
(
I => refclk_i,
O => coreclk_int
);
dclk <= coreclk_int; -- ymei
txusrclk2 <= txusrclk_i;
txusrclk2_i <= txusrclk_i;
coreclk <= coreclk_int;
txusrclk <= txusrclk_i;
reset_i <= not qplllock ;
areset_coreclk <= areset_coreclk_i;
-- Asynch reset synchronizers...
areset_coreclk_sync_i : ten_gig_eth_pcs_pma_0_ff_synchronizer_rst2
generic map(
C_NUM_SYNC_REGS => 5,
C_RVAL => '1')
port map(
clk => coreclk_int,
rst => areset,
data_in => '0',
data_out => areset_coreclk_i
);
qplllock_txusrclk2_rst <= not(qplllock);
qplllock_txusrclk2_sync_i : ten_gig_eth_pcs_pma_0_ff_synchronizer_rst2
generic map(
C_NUM_SYNC_REGS => 5,
C_RVAL => '0')
port map(
clk => txusrclk2_i,
rst => qplllock_txusrclk2_rst,
data_in => '1',
data_out => qplllock_txusrclk2_i
);
gttxreset_txusrclk2_sync_i : ten_gig_eth_pcs_pma_0_ff_synchronizer_rst2
generic map(
C_NUM_SYNC_REGS => 5,
C_RVAL => '1')
port map(
clk => txusrclk2_i,
rst => gttxreset_i,
data_in => '0',
data_out => gttxreset_txusrclk2_i
);
-- Hold off release the GT resets until 500ns after configuration.
-- 256 ticks at the minimum possible 2.56ns period (390MHz) will be >> 500 ns.
reset_proc1: process (coreclk_int)
begin
if(coreclk_int'event and coreclk_int = '1') then
if(reset_counter(8) = '0') then
reset_counter <= reset_counter + 1;
else
reset_counter <= reset_counter;
end if;
end if;
end process;
reset_proc2: process (coreclk_int)
begin
if(coreclk_int'event and coreclk_int = '1') then
if(areset_coreclk_i = '1') then
reset_pulse <= "1110";
elsif(reset_counter(8) = '1') then
reset_pulse(3) <= '0';
reset_pulse(2 downto 0) <= reset_pulse(3 downto 1);
end if;
end if;
end process;
gttxreset_i <= reset_pulse(0);
gttxreset <= gttxreset_i;
gtrxreset <= reset_pulse(0);
qpllreset <= reset_pulse(0);
reset_proc5 : process (txusrclk2_i, gttxreset_txusrclk2_i)
begin
if(gttxreset_txusrclk2_i = '1') then
txuserrdy <= '0';
elsif(txusrclk2_i'event and txusrclk2_i = '1') then
txuserrdy <= qplllock_txusrclk2_i;
end if;
end process;
end wrapper;
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY ram0 IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ram0;
ARCHITECTURE ram0_arch OF ram0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF ram0_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF ram0_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF ram0_arch : ARCHITECTURE IS "ram0,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF ram0_arch: ARCHITECTURE IS "ram0,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=ram0.mem,C_USE_DEFAULT_DATA=1,C_DEFAULT_DATA=bf,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=2048,C_READ_DEPTH_A=2048,C_ADDRA_WIDTH=11,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=2048,C_READ_DEPTH_B=2048,C_ADDRB_WIDTH=11,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=0,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 1.3396 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "ram0.mem",
C_USE_DEFAULT_DATA => 1,
C_DEFAULT_DATA => "bf",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 8,
C_READ_WIDTH_A => 8,
C_WRITE_DEPTH_A => 2048,
C_READ_DEPTH_A => 2048,
C_ADDRA_WIDTH => 11,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 8,
C_READ_WIDTH_B => 8,
C_WRITE_DEPTH_B => 2048,
C_READ_DEPTH_B => 2048,
C_ADDRB_WIDTH => 11,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "0",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 1.3396 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => '0',
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 11)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END ram0_arch;
|
-- NEED RESULT: ENT00250: Open scalar inout ports with static subtypes passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00250
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 1.1.1.2 (3)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00250(ARCH00250)
-- ENT00250_Test_Bench(ARCH00250_Test_Bench)
--
-- REVISION HISTORY:
--
-- 25-JUN-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00250 is
port (
toggle : inout switch ;
i_boolean_1, i_boolean_2 : inout boolean
:= c_boolean_1
;
i_bit_1, i_bit_2 : inout bit
:= c_bit_1
;
i_severity_level_1, i_severity_level_2 : inout severity_level
:= c_severity_level_1
;
i_character_1, i_character_2 : inout character
:= c_character_1
;
i_t_enum1_1, i_t_enum1_2 : inout t_enum1
:= c_t_enum1_1
;
i_st_enum1_1, i_st_enum1_2 : inout st_enum1
:= c_st_enum1_1
;
i_integer_1, i_integer_2 : inout integer
:= c_integer_1
;
i_t_int1_1, i_t_int1_2 : inout t_int1
:= c_t_int1_1
;
i_st_int1_1, i_st_int1_2 : inout st_int1
:= c_st_int1_1
;
i_time_1, i_time_2 : inout time
:= c_time_1
;
i_t_phys1_1, i_t_phys1_2 : inout t_phys1
:= c_t_phys1_1
;
i_st_phys1_1, i_st_phys1_2 : inout st_phys1
:= c_st_phys1_1
;
i_real_1, i_real_2 : inout real
:= c_real_1
;
i_t_real1_1, i_t_real1_2 : inout t_real1
:= c_t_real1_1
;
i_st_real1_1, i_st_real1_2 : inout st_real1
:= c_st_real1_1
) ;
begin
end ENT00250 ;
--
architecture ARCH00250 of ENT00250 is
begin
process
variable correct : boolean := true ;
begin
--
toggle <= up ;
i_boolean_1 <= c_boolean_2 ;
i_boolean_2 <= c_boolean_2 ;
i_bit_1 <= c_bit_2 ;
i_bit_2 <= c_bit_2 ;
i_severity_level_1 <= c_severity_level_2 ;
i_severity_level_2 <= c_severity_level_2 ;
i_character_1 <= c_character_2 ;
i_character_2 <= c_character_2 ;
i_t_enum1_1 <= c_t_enum1_2 ;
i_t_enum1_2 <= c_t_enum1_2 ;
i_st_enum1_1 <= c_st_enum1_2 ;
i_st_enum1_2 <= c_st_enum1_2 ;
i_integer_1 <= c_integer_2 ;
i_integer_2 <= c_integer_2 ;
i_t_int1_1 <= c_t_int1_2 ;
i_t_int1_2 <= c_t_int1_2 ;
i_st_int1_1 <= c_st_int1_2 ;
i_st_int1_2 <= c_st_int1_2 ;
i_time_1 <= c_time_2 ;
i_time_2 <= c_time_2 ;
i_t_phys1_1 <= c_t_phys1_2 ;
i_t_phys1_2 <= c_t_phys1_2 ;
i_st_phys1_1 <= c_st_phys1_2 ;
i_st_phys1_2 <= c_st_phys1_2 ;
i_real_1 <= c_real_2 ;
i_real_2 <= c_real_2 ;
i_t_real1_1 <= c_t_real1_2 ;
i_t_real1_2 <= c_t_real1_2 ;
i_st_real1_1 <= c_st_real1_2 ;
i_st_real1_2 <= c_st_real1_2 ;
test_report ( "ENT00250" ,
"Open scalar inout ports with static subtypes" ,
correct) ;
wait ;
end process ;
end ARCH00250 ;
--
use WORK.STANDARD_TYPES.all ;
entity ENT00250_Test_Bench is
end ENT00250_Test_Bench ;
--
architecture ARCH00250_Test_Bench of ENT00250_Test_Bench is
begin
L1:
block
--
signal toggle : switch ;
--
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.ENT00250 ( ARCH00250 )
port map (
toggle ,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open,
open, open
) ;
--
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00250_Test_Bench ;
|
--------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2014
-- Entity: usb_test1
-- Date:2015-01-27
-- Author: Gideon
-- Description: Testcase 1 for USB host
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_bfm_pkg.all;
use work.tl_sctb_pkg.all;
use work.usb_cmd_pkg.all;
entity usb_test1 is
end entity;
architecture arch of usb_test1 is
signal clocks_stopped : boolean := false;
begin
i_harness: entity work.usb_harness
port map (
clocks_stopped => clocks_stopped );
process
variable io : p_io_bus_bfm_object;
variable data : std_logic_vector(15 downto 0);
begin
bind_io_bus_bfm("io", io);
sctb_open_simulation("path:path", "usb_test1.tcr");
sctb_open_region("Testing In request", 0);
sctb_set_log_level(c_log_level_trace);
wait for 70 ns;
io_write(io => io, addr => X"017fe", data => X"01" ); -- set nano to simulation mode
io_write(io => io, addr => X"017fc", data => X"02" ); -- set bus speed to HS
io_write(io => io, addr => X"01800", data => X"01" ); -- enable nano
wait for 4 us;
io_write(io => io, addr => X"00006", data => X"00" ); -- data buffer control BufIdx(2) ND TOG - - len(2)
io_write(io => io, addr => X"00007", data => X"00" ); -- data buffer control Len(8)
io_write(io => io, addr => X"0000A", data => X"01" ); -- DEV=1
io_write(io => io, addr => X"0000B", data => X"04" ); -- EP=4
io_write(io => io, addr => X"00001", data => X"42" ); -- DoSplit=0, DoData=1, Cmd=2 (setup, out_data, in_request, ping, bus_reset)
L1: while true loop
io_read(io => io, addr => X"00000", data => data(15 downto 8) );
if data(15) = '1' then
exit L1;
end if;
end loop;
io_read(io => io, addr => X"00001", data => data(7 downto 0) );
sctb_trace("Command result: " & t_usb_result'image(t_usb_result'val(to_integer(unsigned(data(14 downto 12))))) &
", length: " & integer'image(to_integer(unsigned(data(9 downto 0)))) );
io_write(io => io, addr => X"00006", data => X"01" ); -- data buffer control BufIdx(2) ND TOG - - len(2)
io_write(io => io, addr => X"00007", data => X"00" ); -- data buffer control Len(8)
io_write(io => io, addr => X"0000B", data => X"01" ); -- EP=1
io_write(io => io, addr => X"00001", data => X"41" ); -- DoSplit=0, DoData=1, Cmd=1 (setup, out_data, in_request, ping, bus_reset)
L2: while true loop
io_read(io => io, addr => X"00000", data => data(15 downto 8) );
if data(15) = '1' then
exit L2;
end if;
end loop;
io_read(io => io, addr => X"00001", data => data(7 downto 0) );
sctb_trace("Command result: " & t_usb_result'image(t_usb_result'val(to_integer(unsigned(data(14 downto 12))))) &
", length: " & integer'image(to_integer(unsigned(data(9 downto 0)))) );
wait;
end process;
end arch;
|
--------------------------------------------------------------------------------
-- Gideon's Logic Architectures - Copyright 2014
-- Entity: usb_test1
-- Date:2015-01-27
-- Author: Gideon
-- Description: Testcase 1 for USB host
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.io_bus_bfm_pkg.all;
use work.tl_sctb_pkg.all;
use work.usb_cmd_pkg.all;
entity usb_test1 is
end entity;
architecture arch of usb_test1 is
signal clocks_stopped : boolean := false;
begin
i_harness: entity work.usb_harness
port map (
clocks_stopped => clocks_stopped );
process
variable io : p_io_bus_bfm_object;
variable data : std_logic_vector(15 downto 0);
begin
bind_io_bus_bfm("io", io);
sctb_open_simulation("path:path", "usb_test1.tcr");
sctb_open_region("Testing In request", 0);
sctb_set_log_level(c_log_level_trace);
wait for 70 ns;
io_write(io => io, addr => X"017fe", data => X"01" ); -- set nano to simulation mode
io_write(io => io, addr => X"017fc", data => X"02" ); -- set bus speed to HS
io_write(io => io, addr => X"01800", data => X"01" ); -- enable nano
wait for 4 us;
io_write(io => io, addr => X"00006", data => X"00" ); -- data buffer control BufIdx(2) ND TOG - - len(2)
io_write(io => io, addr => X"00007", data => X"00" ); -- data buffer control Len(8)
io_write(io => io, addr => X"0000A", data => X"01" ); -- DEV=1
io_write(io => io, addr => X"0000B", data => X"04" ); -- EP=4
io_write(io => io, addr => X"00001", data => X"42" ); -- DoSplit=0, DoData=1, Cmd=2 (setup, out_data, in_request, ping, bus_reset)
L1: while true loop
io_read(io => io, addr => X"00000", data => data(15 downto 8) );
if data(15) = '1' then
exit L1;
end if;
end loop;
io_read(io => io, addr => X"00001", data => data(7 downto 0) );
sctb_trace("Command result: " & t_usb_result'image(t_usb_result'val(to_integer(unsigned(data(14 downto 12))))) &
", length: " & integer'image(to_integer(unsigned(data(9 downto 0)))) );
io_write(io => io, addr => X"00006", data => X"01" ); -- data buffer control BufIdx(2) ND TOG - - len(2)
io_write(io => io, addr => X"00007", data => X"00" ); -- data buffer control Len(8)
io_write(io => io, addr => X"0000B", data => X"01" ); -- EP=1
io_write(io => io, addr => X"00001", data => X"41" ); -- DoSplit=0, DoData=1, Cmd=1 (setup, out_data, in_request, ping, bus_reset)
L2: while true loop
io_read(io => io, addr => X"00000", data => data(15 downto 8) );
if data(15) = '1' then
exit L2;
end if;
end loop;
io_read(io => io, addr => X"00001", data => data(7 downto 0) );
sctb_trace("Command result: " & t_usb_result'image(t_usb_result'val(to_integer(unsigned(data(14 downto 12))))) &
", length: " & integer'image(to_integer(unsigned(data(9 downto 0)))) );
wait;
end process;
end arch;
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 09:40:17 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/embedded_lab_2/embedded_lab_2.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_auto_pc_1/zynq_design_1_auto_pc_1_sim_netlist.vhdl
-- Design : zynq_design_1_auto_pc_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 12;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "yes";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "axi_protocol_converter_v2_1_13_axi_protocol_converter";
attribute P_AXI3 : integer;
attribute P_AXI3 of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute P_DECERR : string;
attribute P_DECERR of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b11";
attribute P_INCR : string;
attribute P_INCR of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b10";
end zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter;
architecture STRUCTURE of zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter is
signal \<const0>\ : STD_LOGIC;
signal \^m_axi_arready\ : STD_LOGIC;
signal \^m_axi_awready\ : STD_LOGIC;
signal \^m_axi_bid\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^m_axi_bresp\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_buser\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_axi_bvalid\ : STD_LOGIC;
signal \^m_axi_rdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^m_axi_rid\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^m_axi_rlast\ : STD_LOGIC;
signal \^m_axi_rresp\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^m_axi_ruser\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^m_axi_rvalid\ : STD_LOGIC;
signal \^m_axi_wready\ : STD_LOGIC;
signal \^s_axi_araddr\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_arburst\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_arid\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^s_axi_arlen\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_arlock\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_arprot\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^s_axi_arqos\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_arsize\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^s_axi_aruser\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_arvalid\ : STD_LOGIC;
signal \^s_axi_awaddr\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_awburst\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_awid\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^s_axi_awlen\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_awlock\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^s_axi_awprot\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^s_axi_awqos\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_awsize\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \^s_axi_awuser\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_awvalid\ : STD_LOGIC;
signal \^s_axi_bready\ : STD_LOGIC;
signal \^s_axi_rready\ : STD_LOGIC;
signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_wlast\ : STD_LOGIC;
signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_wuser\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^s_axi_wvalid\ : STD_LOGIC;
begin
\^m_axi_arready\ <= m_axi_arready;
\^m_axi_awready\ <= m_axi_awready;
\^m_axi_bid\(11 downto 0) <= m_axi_bid(11 downto 0);
\^m_axi_bresp\(1 downto 0) <= m_axi_bresp(1 downto 0);
\^m_axi_buser\(0) <= m_axi_buser(0);
\^m_axi_bvalid\ <= m_axi_bvalid;
\^m_axi_rdata\(31 downto 0) <= m_axi_rdata(31 downto 0);
\^m_axi_rid\(11 downto 0) <= m_axi_rid(11 downto 0);
\^m_axi_rlast\ <= m_axi_rlast;
\^m_axi_rresp\(1 downto 0) <= m_axi_rresp(1 downto 0);
\^m_axi_ruser\(0) <= m_axi_ruser(0);
\^m_axi_rvalid\ <= m_axi_rvalid;
\^m_axi_wready\ <= m_axi_wready;
\^s_axi_araddr\(31 downto 0) <= s_axi_araddr(31 downto 0);
\^s_axi_arburst\(1 downto 0) <= s_axi_arburst(1 downto 0);
\^s_axi_arcache\(3 downto 0) <= s_axi_arcache(3 downto 0);
\^s_axi_arid\(11 downto 0) <= s_axi_arid(11 downto 0);
\^s_axi_arlen\(3 downto 0) <= s_axi_arlen(3 downto 0);
\^s_axi_arlock\(0) <= s_axi_arlock(0);
\^s_axi_arprot\(2 downto 0) <= s_axi_arprot(2 downto 0);
\^s_axi_arqos\(3 downto 0) <= s_axi_arqos(3 downto 0);
\^s_axi_arsize\(2 downto 0) <= s_axi_arsize(2 downto 0);
\^s_axi_aruser\(0) <= s_axi_aruser(0);
\^s_axi_arvalid\ <= s_axi_arvalid;
\^s_axi_awaddr\(31 downto 0) <= s_axi_awaddr(31 downto 0);
\^s_axi_awburst\(1 downto 0) <= s_axi_awburst(1 downto 0);
\^s_axi_awcache\(3 downto 0) <= s_axi_awcache(3 downto 0);
\^s_axi_awid\(11 downto 0) <= s_axi_awid(11 downto 0);
\^s_axi_awlen\(3 downto 0) <= s_axi_awlen(3 downto 0);
\^s_axi_awlock\(0) <= s_axi_awlock(0);
\^s_axi_awprot\(2 downto 0) <= s_axi_awprot(2 downto 0);
\^s_axi_awqos\(3 downto 0) <= s_axi_awqos(3 downto 0);
\^s_axi_awsize\(2 downto 0) <= s_axi_awsize(2 downto 0);
\^s_axi_awuser\(0) <= s_axi_awuser(0);
\^s_axi_awvalid\ <= s_axi_awvalid;
\^s_axi_bready\ <= s_axi_bready;
\^s_axi_rready\ <= s_axi_rready;
\^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0);
\^s_axi_wlast\ <= s_axi_wlast;
\^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0);
\^s_axi_wuser\(0) <= s_axi_wuser(0);
\^s_axi_wvalid\ <= s_axi_wvalid;
m_axi_araddr(31 downto 0) <= \^s_axi_araddr\(31 downto 0);
m_axi_arburst(1 downto 0) <= \^s_axi_arburst\(1 downto 0);
m_axi_arcache(3 downto 0) <= \^s_axi_arcache\(3 downto 0);
m_axi_arid(11 downto 0) <= \^s_axi_arid\(11 downto 0);
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3 downto 0) <= \^s_axi_arlen\(3 downto 0);
m_axi_arlock(0) <= \^s_axi_arlock\(0);
m_axi_arprot(2 downto 0) <= \^s_axi_arprot\(2 downto 0);
m_axi_arqos(3 downto 0) <= \^s_axi_arqos\(3 downto 0);
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2 downto 0) <= \^s_axi_arsize\(2 downto 0);
m_axi_aruser(0) <= \^s_axi_aruser\(0);
m_axi_arvalid <= \^s_axi_arvalid\;
m_axi_awaddr(31 downto 0) <= \^s_axi_awaddr\(31 downto 0);
m_axi_awburst(1 downto 0) <= \^s_axi_awburst\(1 downto 0);
m_axi_awcache(3 downto 0) <= \^s_axi_awcache\(3 downto 0);
m_axi_awid(11 downto 0) <= \^s_axi_awid\(11 downto 0);
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3 downto 0) <= \^s_axi_awlen\(3 downto 0);
m_axi_awlock(0) <= \^s_axi_awlock\(0);
m_axi_awprot(2 downto 0) <= \^s_axi_awprot\(2 downto 0);
m_axi_awqos(3 downto 0) <= \^s_axi_awqos\(3 downto 0);
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2 downto 0) <= \^s_axi_awsize\(2 downto 0);
m_axi_awuser(0) <= \^s_axi_awuser\(0);
m_axi_awvalid <= \^s_axi_awvalid\;
m_axi_bready <= \^s_axi_bready\;
m_axi_rready <= \^s_axi_rready\;
m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0);
m_axi_wid(11) <= \<const0>\;
m_axi_wid(10) <= \<const0>\;
m_axi_wid(9) <= \<const0>\;
m_axi_wid(8) <= \<const0>\;
m_axi_wid(7) <= \<const0>\;
m_axi_wid(6) <= \<const0>\;
m_axi_wid(5) <= \<const0>\;
m_axi_wid(4) <= \<const0>\;
m_axi_wid(3) <= \<const0>\;
m_axi_wid(2) <= \<const0>\;
m_axi_wid(1) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \^s_axi_wlast\;
m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wuser(0) <= \^s_axi_wuser\(0);
m_axi_wvalid <= \^s_axi_wvalid\;
s_axi_arready <= \^m_axi_arready\;
s_axi_awready <= \^m_axi_awready\;
s_axi_bid(11 downto 0) <= \^m_axi_bid\(11 downto 0);
s_axi_bresp(1 downto 0) <= \^m_axi_bresp\(1 downto 0);
s_axi_buser(0) <= \^m_axi_buser\(0);
s_axi_bvalid <= \^m_axi_bvalid\;
s_axi_rdata(31 downto 0) <= \^m_axi_rdata\(31 downto 0);
s_axi_rid(11 downto 0) <= \^m_axi_rid\(11 downto 0);
s_axi_rlast <= \^m_axi_rlast\;
s_axi_rresp(1 downto 0) <= \^m_axi_rresp\(1 downto 0);
s_axi_ruser(0) <= \^m_axi_ruser\(0);
s_axi_rvalid <= \^m_axi_rvalid\;
s_axi_wready <= \^m_axi_wready\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_auto_pc_1 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of zynq_design_1_auto_pc_1 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of zynq_design_1_auto_pc_1 : entity is "zynq_design_1_auto_pc_1,axi_protocol_converter_v2_1_13_axi_protocol_converter,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of zynq_design_1_auto_pc_1 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of zynq_design_1_auto_pc_1 : entity is "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2";
end zynq_design_1_auto_pc_1;
architecture STRUCTURE of zynq_design_1_auto_pc_1 is
signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of inst : label is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of inst : label is 12;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of inst : label is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of inst : label is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of inst : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of inst : label is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of inst : label is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of inst : label is 0;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of inst : label is 1;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of inst : label is 2;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of inst : label is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of inst : label is 2;
attribute P_DECERR : string;
attribute P_DECERR of inst : label is "2'b11";
attribute P_INCR : string;
attribute P_INCR of inst : label is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of inst : label is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of inst : label is "2'b10";
begin
inst: entity work.zynq_design_1_auto_pc_1_axi_protocol_converter_v2_1_13_axi_protocol_converter
port map (
aclk => aclk,
aresetn => aresetn,
m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0),
m_axi_arcache(3 downto 0) => m_axi_arcache(3 downto 0),
m_axi_arid(11 downto 0) => m_axi_arid(11 downto 0),
m_axi_arlen(7 downto 0) => m_axi_arlen(7 downto 0),
m_axi_arlock(0) => m_axi_arlock(0),
m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
m_axi_arqos(3 downto 0) => m_axi_arqos(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arregion(3 downto 0) => m_axi_arregion(3 downto 0),
m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0),
m_axi_aruser(0) => NLW_inst_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0),
m_axi_awburst(1 downto 0) => m_axi_awburst(1 downto 0),
m_axi_awcache(3 downto 0) => m_axi_awcache(3 downto 0),
m_axi_awid(11 downto 0) => m_axi_awid(11 downto 0),
m_axi_awlen(7 downto 0) => m_axi_awlen(7 downto 0),
m_axi_awlock(0) => m_axi_awlock(0),
m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
m_axi_awqos(3 downto 0) => m_axi_awqos(3 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awregion(3 downto 0) => m_axi_awregion(3 downto 0),
m_axi_awsize(2 downto 0) => m_axi_awsize(2 downto 0),
m_axi_awuser(0) => NLW_inst_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => m_axi_awvalid,
m_axi_bid(11 downto 0) => m_axi_bid(11 downto 0),
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_buser(0) => '0',
m_axi_bvalid => m_axi_bvalid,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => m_axi_rid(11 downto 0),
m_axi_rlast => m_axi_rlast,
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_ruser(0) => '0',
m_axi_rvalid => m_axi_rvalid,
m_axi_wdata(31 downto 0) => m_axi_wdata(31 downto 0),
m_axi_wid(11 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(11 downto 0),
m_axi_wlast => m_axi_wlast,
m_axi_wready => m_axi_wready,
m_axi_wstrb(3 downto 0) => m_axi_wstrb(3 downto 0),
m_axi_wuser(0) => NLW_inst_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => m_axi_wvalid,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(3 downto 0) => s_axi_arlen(3 downto 0),
s_axi_arlock(1 downto 0) => s_axi_arlock(1 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_aruser(0) => '0',
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(3 downto 0) => s_axi_awlen(3 downto 0),
s_axi_awlock(1 downto 0) => s_axi_awlock(1 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awregion(3 downto 0) => B"0000",
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awuser(0) => '0',
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wid(11 downto 0) => s_axi_wid(11 downto 0),
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1456.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s07b00x00p04n01i01456ent IS
END c08s07b00x00p04n01i01456ent;
ARCHITECTURE c08s07b00x00p04n01i01456arch OF c08s07b00x00p04n01i01456ent IS
begin
transmit: process
variable delay : integer := 1;
variable k : integer := 0;
variable m : integer := 0;
variable n : integer := 0;
begin
if delay = 1 then
k := 1;
elsif delay = 0 then
m := 1;
else
n := 1;
end if;
assert NOT((k = 1) and (m = 0) and (n = 0))
report "***PASSED TEST: c08s07b00x00p04n01i01456"
severity NOTE;
assert (k = 1) and (m = 0) and (n = 0)
report "***FAILED TEST: c08s07b00x00p04n01i01456 - only the condition after the IF statement is TRUE, all others are evaluated to be FALSE"
severity ERROR;
wait;
end process transmit;
END c08s07b00x00p04n01i01456arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1456.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s07b00x00p04n01i01456ent IS
END c08s07b00x00p04n01i01456ent;
ARCHITECTURE c08s07b00x00p04n01i01456arch OF c08s07b00x00p04n01i01456ent IS
begin
transmit: process
variable delay : integer := 1;
variable k : integer := 0;
variable m : integer := 0;
variable n : integer := 0;
begin
if delay = 1 then
k := 1;
elsif delay = 0 then
m := 1;
else
n := 1;
end if;
assert NOT((k = 1) and (m = 0) and (n = 0))
report "***PASSED TEST: c08s07b00x00p04n01i01456"
severity NOTE;
assert (k = 1) and (m = 0) and (n = 0)
report "***FAILED TEST: c08s07b00x00p04n01i01456 - only the condition after the IF statement is TRUE, all others are evaluated to be FALSE"
severity ERROR;
wait;
end process transmit;
END c08s07b00x00p04n01i01456arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1456.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s07b00x00p04n01i01456ent IS
END c08s07b00x00p04n01i01456ent;
ARCHITECTURE c08s07b00x00p04n01i01456arch OF c08s07b00x00p04n01i01456ent IS
begin
transmit: process
variable delay : integer := 1;
variable k : integer := 0;
variable m : integer := 0;
variable n : integer := 0;
begin
if delay = 1 then
k := 1;
elsif delay = 0 then
m := 1;
else
n := 1;
end if;
assert NOT((k = 1) and (m = 0) and (n = 0))
report "***PASSED TEST: c08s07b00x00p04n01i01456"
severity NOTE;
assert (k = 1) and (m = 0) and (n = 0)
report "***FAILED TEST: c08s07b00x00p04n01i01456 - only the condition after the IF statement is TRUE, all others are evaluated to be FALSE"
severity ERROR;
wait;
end process transmit;
END c08s07b00x00p04n01i01456arch;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_misc.all;
-- ******************************************************************************
-- * License Agreement *
-- * *
-- * Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
-- * All rights reserved. *
-- * *
-- * Any megafunction design, and related net list (encrypted or decrypted), *
-- * support information, device programming or simulation file, and any other *
-- * associated documentation or information provided by Altera or a partner *
-- * under Altera's Megafunction Partnership Program may be used only to *
-- * program PLD devices (but not masked PLD devices) from Altera. Any other *
-- * use of such megafunction design, net list, support information, device *
-- * programming or simulation file, or any other related documentation or *
-- * information is prohibited for any other purpose, including, but not *
-- * limited to modification, reverse engineering, de-compiling, or use with *
-- * any other silicon devices, unless such use is explicitly licensed under *
-- * a separate agreement with Altera or a megafunction partner. Title to *
-- * the intellectual property, including patents, copyrights, trademarks, *
-- * trade secrets, or maskworks, embodied in any such megafunction design, *
-- * net list, support information, device programming or simulation file, or *
-- * any other related documentation or information provided by Altera or a *
-- * megafunction partner, remains with Altera, the megafunction partner, or *
-- * their respective licensors. No other licenses, including any licenses *
-- * needed under any third party's intellectual property, are provided herein.*
-- * Copying or modifying any file, or portion thereof, to which this notice *
-- * is attached violates this copyright. *
-- * *
-- * THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
-- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
-- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
-- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
-- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
-- * FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
-- * IN THIS FILE. *
-- * *
-- * This agreement shall be governed in all respects by the laws of the State *
-- * of California and by the laws of the United States of America. *
-- * *
-- ******************************************************************************
-- ******************************************************************************
-- * *
-- * This module converts video streams between RGB color formats. *
-- * *
-- ******************************************************************************
ENTITY Video_System_Pixel_RGB_Resampler IS
-- *****************************************************************************
-- * Generic Declarations *
-- *****************************************************************************
GENERIC (
IDW :INTEGER := 15;
ODW :INTEGER := 29;
IEW :INTEGER := 0;
OEW :INTEGER := 1;
ALPHA :STD_LOGIC_VECTOR( 9 DOWNTO 0) := B"1111111111"
);
-- *****************************************************************************
-- * Port Declarations *
-- *****************************************************************************
PORT (
-- Inputs
clk :IN STD_LOGIC;
reset :IN STD_LOGIC;
stream_in_data :IN STD_LOGIC_VECTOR(IDW DOWNTO 0);
stream_in_startofpacket :IN STD_LOGIC;
stream_in_endofpacket :IN STD_LOGIC;
stream_in_empty :IN STD_LOGIC_VECTOR(IEW DOWNTO 0);
stream_in_valid :IN STD_LOGIC;
stream_out_ready :IN STD_LOGIC;
-- Bidirectional
-- Outputs
stream_in_ready :BUFFER STD_LOGIC;
stream_out_data :BUFFER STD_LOGIC_VECTOR(ODW DOWNTO 0);
stream_out_startofpacket :BUFFER STD_LOGIC;
stream_out_endofpacket :BUFFER STD_LOGIC;
stream_out_empty :BUFFER STD_LOGIC_VECTOR(OEW DOWNTO 0);
stream_out_valid :BUFFER STD_LOGIC
);
END Video_System_Pixel_RGB_Resampler;
ARCHITECTURE Behaviour OF Video_System_Pixel_RGB_Resampler IS
-- *****************************************************************************
-- * Constant Declarations *
-- *****************************************************************************
-- *****************************************************************************
-- * Internal Signals Declarations *
-- *****************************************************************************
-- Internal Wires
SIGNAL r :STD_LOGIC_VECTOR( 9 DOWNTO 0);
SIGNAL g :STD_LOGIC_VECTOR( 9 DOWNTO 0);
SIGNAL b :STD_LOGIC_VECTOR( 9 DOWNTO 0);
SIGNAL a :STD_LOGIC_VECTOR( 9 DOWNTO 0);
SIGNAL converted_data :STD_LOGIC_VECTOR(ODW DOWNTO 0);
-- Internal Registers
-- State Machine Registers
-- Integers
-- *****************************************************************************
-- * Component Declarations *
-- *****************************************************************************
BEGIN
-- *****************************************************************************
-- * Finite State Machine(s) *
-- *****************************************************************************
-- *****************************************************************************
-- * Sequential Logic *
-- *****************************************************************************
-- Output Registers
PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
IF (reset = '1') THEN
stream_out_data <= (OTHERS => '0');
stream_out_startofpacket <= '0';
stream_out_endofpacket <= '0';
stream_out_empty <= (OTHERS => '0');
stream_out_valid <= '0';
ELSIF ((stream_out_ready = '1') OR (stream_out_valid = '0')) THEN
stream_out_data <= converted_data;
stream_out_startofpacket <= stream_in_startofpacket;
stream_out_endofpacket <= stream_in_endofpacket;
-- stream_out_empty <= stream_in_empty;
stream_out_empty <= (OTHERS => '0');
stream_out_valid <= stream_in_valid;
END IF;
END IF;
END PROCESS;
-- Internal Registers
-- *****************************************************************************
-- * Combinational Logic *
-- *****************************************************************************
-- Output Assignments
stream_in_ready <= stream_out_ready OR NOT stream_out_valid;
-- Internal Assignments
r <= (stream_in_data(15 DOWNTO 11) & stream_in_data(15 DOWNTO 11));
g <= (stream_in_data(10 DOWNTO 5) & stream_in_data(10 DOWNTO 7));
b <= (stream_in_data( 4 DOWNTO 0) & stream_in_data( 4 DOWNTO 0));
a <= ALPHA;
converted_data(29 DOWNTO 20) <= r( 9 DOWNTO 0);
converted_data(19 DOWNTO 10) <= g( 9 DOWNTO 0);
converted_data( 9 DOWNTO 0) <= b( 9 DOWNTO 0);
-- *****************************************************************************
-- * Component Instantiations *
-- *****************************************************************************
END Behaviour;
|
-------------------------------------------------------------------------------
-- --
-- Module : BRAM_S144_S144.vhd Last Update: --
-- --
-- Project : Parameterizable LocalLink FIFO --
-- --
-- Description : BRAM Macro with Dual Port, two data widths (128 and 128) --
-- made for LL_FIFO. --
-- --
-- Designer : Wen Ying Wei, Davy Huang --
-- --
-- Company : Xilinx, Inc. --
-- --
-- Disclaimer : THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY --
-- WHATSOEVER and XILinX SPECifICALLY DISCLAIMS ANY --
-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS For --
-- A PARTICULAR PURPOSE, or AGAinST inFRinGEMENT. --
-- THEY ARE ONLY inTENDED TO BE USED BY XILinX --
-- CUSTOMERS, and WITHin XILinX DEVICES. --
-- --
-- Copyright (c) 2003 Xilinx, Inc. --
-- All rights reserved --
-- --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity BRAM_S144_S144 is
port (ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
DIA : in std_logic_vector (127 downto 0);
DIPA : in std_logic_vector (15 downto 0);
DIB : in std_logic_vector (127 downto 0);
DIPB : in std_logic_vector (15 downto 0);
WEA : in std_logic;
WEB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
ENA : in std_logic;
ENB : in std_logic;
DOA : out std_logic_vector (127 downto 0);
DOPA : out std_logic_vector(15 downto 0);
DOB : out std_logic_vector (127 downto 0);
DOPB : out std_logic_vector(15 downto 0));
end entity BRAM_S144_S144;
architecture BRAM_S144_S144_arch of BRAM_S144_S144 is
component BRAM_S72_S72
port (ADDRA : in std_logic_vector (8 downto 0);
ADDRB : in std_logic_vector (8 downto 0);
DIA : in std_logic_vector (63 downto 0);
DIPA : in std_logic_vector (7 downto 0);
DIB : in std_logic_vector (63 downto 0);
DIPB : in std_logic_vector (7 downto 0);
WEA : in std_logic;
WEB : in std_logic;
CLKA : in std_logic;
CLKB : in std_logic;
SSRA : in std_logic;
SSRB : in std_logic;
ENA : in std_logic;
ENB : in std_logic;
DOA : out std_logic_vector (63 downto 0);
DOPA : out std_logic_vector(7 downto 0);
DOB : out std_logic_vector (63 downto 0);
DOPB : out std_logic_vector(7 downto 0));
END component;
signal doa1 : std_logic_vector (63 downto 0);
signal dob1 : std_logic_vector (63 downto 0);
signal doa2 : std_logic_vector (63 downto 0);
signal dob2 : std_logic_vector (63 downto 0);
signal dia1 : std_logic_vector (63 downto 0);
signal dib1 : std_logic_vector (63 downto 0);
signal dia2 : std_logic_vector (63 downto 0);
signal dib2 : std_logic_vector (63 downto 0);
signal dipa1: std_logic_vector(7 downto 0);
signal dipa2: std_logic_vector(7 downto 0);
signal dipb1: std_logic_vector(7 downto 0);
signal dipb2: std_logic_vector(7 downto 0);
signal dopa1: std_logic_vector(7 downto 0);
signal dopa2: std_logic_vector(7 downto 0);
signal dopb1: std_logic_vector(7 downto 0);
signal dopb2: std_logic_vector(7 downto 0);
begin
dia1(31 downto 0) <= DIA(31 downto 0);
dia2(31 downto 0) <= DIA(63 downto 32);
dia1(63 downto 32) <= DIA(95 downto 64);
dia2(63 downto 32) <= DIA(127 downto 96);
dib1 <= DIB(63 downto 0);
dib2 <= DIB(127 downto 64);
DOA(63 downto 0) <= doa1;
DOA(127 downto 64) <= doa2;
DOB(63 downto 0) <= dob1;
DOB(127 downto 64) <= dob2;
dipa1 <= dipa(7 downto 0);
dipa2 <= dipa(15 downto 8);
dopa(7 downto 0) <= dopa1;
dopa(15 downto 8) <= dopa2;
dipb1 <= dipb(7 downto 0);
dipb2 <= dipb(15 downto 8);
dopb(7 downto 0) <= dopb1;
dopb(15 downto 8) <= dopb2;
bram1: BRAM_S72_S72
port map (
ADDRA => addra(8 downto 0),
ADDRB => addrb(8 downto 0),
DIA => dia1,
DIPA => dipa1,
DIB => dib1,
DIPB => dipb1,
WEA => wea,
WEB => web,
CLKA => clka,
CLKB => clkb,
SSRA => ssra,
SSRB => ssrb,
ENA => ena,
ENB => enb,
DOA => doa1,
DOPA => dopa1,
DOB => dob1,
DOPB => dopb1);
bram2: BRAM_S72_S72
port map (
ADDRA => addra(8 downto 0),
ADDRB => addrb(8 downto 0),
DIA => dia2,
DIPA => dipa2,
DIB => dib2,
DIPB => dipb2,
WEA => wea,
WEB => web,
CLKA => clka,
CLKB => clkb,
SSRA => ssra,
SSRB => ssrb,
ENA => ena,
ENB => enb,
DOA => doa2,
DOPA => dopa2,
DOB => dob2,
DOPB => dopb2);
end BRAM_S144_S144_arch;
|
-- file: obstacles/obst_regbank.vhd
-- authors: Alexandre Medeiros and Gabriel Lopes
--
-- A Flappy bird implementation in VHDL for a Digital Circuits course at
-- Unicamp.
--
-- Set of n registers to save the obstacles positions (2 integers for each
-- obstacle), when an obstacle reaches the horizontal position 0, it is
-- automatically discarded and a new one is read from in_{low,high}.
library ieee ;
use ieee.std_logic_1164.all ;
entity obst_regbank is
generic (
H_RES : natural := 128 ; -- Horizontal Resolution
V_RES : natural := 96 ; -- Vertical Resolution
N_OBST : natural := 4 -- Number of obstacles
) ;
port (
-- New obstacles input
in_low : in integer range 0 to V_RES - 1 ;
in_high : in integer range 0 to V_RES - 1 ;
up_clk : in std_logic ; -- Update clock
-- Read current values
id : in integer range 0 to N_OBST - 1 ;
low : out integer range 0 to V_RES - 1 ;
high : out integer range 0 to V_RES - 1 ;
pos : out integer range 0 to H_RES / N_OBST - 1 ;
f_low : out integer range 0 to V_RES - 1 ;
f_high : out integer range 0 to V_RES - 1 ;
-- Control signal
clock : in std_logic ;
enable : in std_logic ;
reset : in std_logic ;
obst_rem : out std_logic
) ;
end obst_regbank ;
architecture behavior of obst_regbank is
-- Declare a array type for the obstacles
type obst_t is array (0 to N_OBST - 1) of integer range 0 to V_RES - 1 ;
-- Obstacles array
signal obst_low : obst_t ;
signal obst_high : obst_t ;
signal updating : std_logic ;
signal tmp_pos : integer range 0 to H_RES / N_OBST - 1 := H_RES / N_OBST - 1 ;
signal tmp_obst_rem : std_logic ;
begin
-- Reading values process
process(clock)
begin
if rising_edge(clock) and updating = '0' then
low <= obst_low(id) ;
high <= obst_high(id) ;
f_low <= obst_low(0) ;
f_high <= obst_high(0) ;
pos <= tmp_pos ;
if tmp_pos = 0 then
obst_rem <= '1' ;
else
obst_rem <= '0' ;
end if ;
end if ;
end process ;
-- Update obstacle values
process(up_clk, reset, enable)
begin
if reset = '1' then
updating <= '1' ;
-- Reset
tmp_pos <= 0 ; -- H_RES / N_OBST - 1 ;
for i in 0 to N_OBST - 1 loop
obst_low(i) <= 0 ;
obst_high(i) <= 0 ;
end loop ;
updating <= '0' ;
elsif rising_edge(up_clk) and enable = '1' then
updating <= '1' ;
if tmp_pos = 0 then
-- Shift obstacles and read next obstacle
tmp_obst_rem <= '1' ;
tmp_pos <= H_RES / N_OBST - 1 ;
for i in 1 to N_OBST - 1 loop
obst_low(i-1) <= obst_low(i) ;
obst_high(i-1) <= obst_high(i) ;
end loop ;
obst_low(N_OBST - 1) <= in_low ;
obst_high(N_OBST - 1) <= in_high ;
else
tmp_obst_rem <= '0' ;
tmp_pos <= tmp_pos - 1 ;
end if ;
updating <= '0' ;
end if ;
end process ;
end behavior ;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2140.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p21n01i02140ent IS
END c07s02b04x00p21n01i02140ent;
ARCHITECTURE c07s02b04x00p21n01i02140arch OF c07s02b04x00p21n01i02140ent IS
TYPE positive_v is array (integer range <>) of positive;
SUBTYPE positive_4 is positive_v (1 to 4);
SUBTYPE positive_null is positive_v (1 to 0);
BEGIN
TESTING: PROCESS
variable result : positive_4;
variable l_operand : positive_4 := ( 1 , 89 , 1 , 89 );
variable r_operand : positive_null;
BEGIN
result := l_operand & r_operand;
wait for 5 ns;
assert NOT( result = ( 1, 89, 1, 89 ) )
report "***PASSED TEST: c07s02b04x00p21n01i02140"
severity NOTE;
assert ( result = ( 1, 89, 1, 89 ) )
report "***FAILED TEST: c07s02b04x00p21n01i02140 - Concatenation of null and POSITIVE arrays failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p21n01i02140arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2140.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p21n01i02140ent IS
END c07s02b04x00p21n01i02140ent;
ARCHITECTURE c07s02b04x00p21n01i02140arch OF c07s02b04x00p21n01i02140ent IS
TYPE positive_v is array (integer range <>) of positive;
SUBTYPE positive_4 is positive_v (1 to 4);
SUBTYPE positive_null is positive_v (1 to 0);
BEGIN
TESTING: PROCESS
variable result : positive_4;
variable l_operand : positive_4 := ( 1 , 89 , 1 , 89 );
variable r_operand : positive_null;
BEGIN
result := l_operand & r_operand;
wait for 5 ns;
assert NOT( result = ( 1, 89, 1, 89 ) )
report "***PASSED TEST: c07s02b04x00p21n01i02140"
severity NOTE;
assert ( result = ( 1, 89, 1, 89 ) )
report "***FAILED TEST: c07s02b04x00p21n01i02140 - Concatenation of null and POSITIVE arrays failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p21n01i02140arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2140.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p21n01i02140ent IS
END c07s02b04x00p21n01i02140ent;
ARCHITECTURE c07s02b04x00p21n01i02140arch OF c07s02b04x00p21n01i02140ent IS
TYPE positive_v is array (integer range <>) of positive;
SUBTYPE positive_4 is positive_v (1 to 4);
SUBTYPE positive_null is positive_v (1 to 0);
BEGIN
TESTING: PROCESS
variable result : positive_4;
variable l_operand : positive_4 := ( 1 , 89 , 1 , 89 );
variable r_operand : positive_null;
BEGIN
result := l_operand & r_operand;
wait for 5 ns;
assert NOT( result = ( 1, 89, 1, 89 ) )
report "***PASSED TEST: c07s02b04x00p21n01i02140"
severity NOTE;
assert ( result = ( 1, 89, 1, 89 ) )
report "***FAILED TEST: c07s02b04x00p21n01i02140 - Concatenation of null and POSITIVE arrays failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p21n01i02140arch;
|
--
-- Audio mixer
--
-- Copyright 2011 TRSi
--
-- Version: 0.1
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- Changelog:
--
-- 0.1: First version
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
entity AUDIO_zpuino_sa_audiomixer is
port (
clk: in std_logic;
rst: in std_logic;
ena: in std_logic;
data_in1: in std_logic_vector(17 downto 0);
data_in2: in std_logic_vector(17 downto 0);
data_in3: in std_logic_vector(17 downto 0);
audio_out: out std_logic
);
end entity AUDIO_zpuino_sa_audiomixer;
architecture behave of AUDIO_zpuino_sa_audiomixer is
-- divier per input
signal cnt_div: std_logic_vector(1 downto 0) := (others => '0');
-- accumulator for each input, on 9 bits, enough for 3 inputs@8bits
signal audio_mix: std_logic_vector(19 downto 0) := (others => '0');
-- to store final accumulator value
signal audio_final: std_logic_vector(19 downto 0) := (others => '0');
signal current_input: std_logic_vector(17 downto 0) := (others => '0');
signal data_out: std_logic_vector(17 downto 0) := (others => '0');
-- DAC
component AUDIO_zpuino_sa_sigmadeltaDAC is
generic (
BITS: integer := 18
);
port (
clk_96Mhz: in std_logic;
--rst: in std_logic;
data_in: in std_logic_vector(BITS-1 downto 0);
audio_out: out std_logic
);
end component AUDIO_zpuino_sa_sigmadeltaDAC;
begin
sdo: AUDIO_zpuino_sa_sigmadeltaDAC
generic map (
BITS => 18
)
port map (
clk_96Mhz => clk,
--rst => rst,
data_in => data_out,
audio_out => audio_out
);
-- divide clock by input channels number
p_divider : process
begin
wait until rising_edge(clk);
if (ena = '1') then
if (cnt_div = "00") then
cnt_div <= "11";
else
cnt_div <= cnt_div - "1";
end if;
end if;
end process;
-- assign an input
p_chan_mixer : process(cnt_div, data_in1, data_in2, data_in3)
begin
current_input <= (others => DontCareValue);
case cnt_div(1 downto 0) is
when "11" =>
current_input <= data_in1;
when "10" =>
current_input <= data_in2;
when "01" =>
current_input <= data_in3;
when "00" => null; -- mix outputs become valid on this clock
when others => null;
end case;
end process;
-- mixer process, input by input
p_op_mixer : process
begin
wait until rising_edge(clk);
if (ena = '1') then
if (cnt_div(1 downto 0) = "00") then
audio_mix <= (others => '0');
audio_final <= audio_mix;
else
audio_mix <= audio_mix + ("00" & current_input);
end if;
end if;
if (rst='1') then
data_out(17 downto 0) <= (others => '0');
else
if (audio_final(19) = '0') then
data_out(17 downto 0) <= audio_final(18 downto 1);
else -- clip
data_out(17 downto 0) <= "111111111111111111";
end if;
end if;
end process;
end behave;
|
--
-- Audio mixer
--
-- Copyright 2011 TRSi
--
-- Version: 0.1
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- Changelog:
--
-- 0.1: First version
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
entity AUDIO_zpuino_sa_audiomixer is
port (
clk: in std_logic;
rst: in std_logic;
ena: in std_logic;
data_in1: in std_logic_vector(17 downto 0);
data_in2: in std_logic_vector(17 downto 0);
data_in3: in std_logic_vector(17 downto 0);
audio_out: out std_logic
);
end entity AUDIO_zpuino_sa_audiomixer;
architecture behave of AUDIO_zpuino_sa_audiomixer is
-- divier per input
signal cnt_div: std_logic_vector(1 downto 0) := (others => '0');
-- accumulator for each input, on 9 bits, enough for 3 inputs@8bits
signal audio_mix: std_logic_vector(19 downto 0) := (others => '0');
-- to store final accumulator value
signal audio_final: std_logic_vector(19 downto 0) := (others => '0');
signal current_input: std_logic_vector(17 downto 0) := (others => '0');
signal data_out: std_logic_vector(17 downto 0) := (others => '0');
-- DAC
component AUDIO_zpuino_sa_sigmadeltaDAC is
generic (
BITS: integer := 18
);
port (
clk_96Mhz: in std_logic;
--rst: in std_logic;
data_in: in std_logic_vector(BITS-1 downto 0);
audio_out: out std_logic
);
end component AUDIO_zpuino_sa_sigmadeltaDAC;
begin
sdo: AUDIO_zpuino_sa_sigmadeltaDAC
generic map (
BITS => 18
)
port map (
clk_96Mhz => clk,
--rst => rst,
data_in => data_out,
audio_out => audio_out
);
-- divide clock by input channels number
p_divider : process
begin
wait until rising_edge(clk);
if (ena = '1') then
if (cnt_div = "00") then
cnt_div <= "11";
else
cnt_div <= cnt_div - "1";
end if;
end if;
end process;
-- assign an input
p_chan_mixer : process(cnt_div, data_in1, data_in2, data_in3)
begin
current_input <= (others => DontCareValue);
case cnt_div(1 downto 0) is
when "11" =>
current_input <= data_in1;
when "10" =>
current_input <= data_in2;
when "01" =>
current_input <= data_in3;
when "00" => null; -- mix outputs become valid on this clock
when others => null;
end case;
end process;
-- mixer process, input by input
p_op_mixer : process
begin
wait until rising_edge(clk);
if (ena = '1') then
if (cnt_div(1 downto 0) = "00") then
audio_mix <= (others => '0');
audio_final <= audio_mix;
else
audio_mix <= audio_mix + ("00" & current_input);
end if;
end if;
if (rst='1') then
data_out(17 downto 0) <= (others => '0');
else
if (audio_final(19) = '0') then
data_out(17 downto 0) <= audio_final(18 downto 1);
else -- clip
data_out(17 downto 0) <= "111111111111111111";
end if;
end if;
end process;
end behave;
|
--
-- Audio mixer
--
-- Copyright 2011 TRSi
--
-- Version: 0.1
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- Changelog:
--
-- 0.1: First version
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
entity AUDIO_zpuino_sa_audiomixer is
port (
clk: in std_logic;
rst: in std_logic;
ena: in std_logic;
data_in1: in std_logic_vector(17 downto 0);
data_in2: in std_logic_vector(17 downto 0);
data_in3: in std_logic_vector(17 downto 0);
audio_out: out std_logic
);
end entity AUDIO_zpuino_sa_audiomixer;
architecture behave of AUDIO_zpuino_sa_audiomixer is
-- divier per input
signal cnt_div: std_logic_vector(1 downto 0) := (others => '0');
-- accumulator for each input, on 9 bits, enough for 3 inputs@8bits
signal audio_mix: std_logic_vector(19 downto 0) := (others => '0');
-- to store final accumulator value
signal audio_final: std_logic_vector(19 downto 0) := (others => '0');
signal current_input: std_logic_vector(17 downto 0) := (others => '0');
signal data_out: std_logic_vector(17 downto 0) := (others => '0');
-- DAC
component AUDIO_zpuino_sa_sigmadeltaDAC is
generic (
BITS: integer := 18
);
port (
clk_96Mhz: in std_logic;
--rst: in std_logic;
data_in: in std_logic_vector(BITS-1 downto 0);
audio_out: out std_logic
);
end component AUDIO_zpuino_sa_sigmadeltaDAC;
begin
sdo: AUDIO_zpuino_sa_sigmadeltaDAC
generic map (
BITS => 18
)
port map (
clk_96Mhz => clk,
--rst => rst,
data_in => data_out,
audio_out => audio_out
);
-- divide clock by input channels number
p_divider : process
begin
wait until rising_edge(clk);
if (ena = '1') then
if (cnt_div = "00") then
cnt_div <= "11";
else
cnt_div <= cnt_div - "1";
end if;
end if;
end process;
-- assign an input
p_chan_mixer : process(cnt_div, data_in1, data_in2, data_in3)
begin
current_input <= (others => DontCareValue);
case cnt_div(1 downto 0) is
when "11" =>
current_input <= data_in1;
when "10" =>
current_input <= data_in2;
when "01" =>
current_input <= data_in3;
when "00" => null; -- mix outputs become valid on this clock
when others => null;
end case;
end process;
-- mixer process, input by input
p_op_mixer : process
begin
wait until rising_edge(clk);
if (ena = '1') then
if (cnt_div(1 downto 0) = "00") then
audio_mix <= (others => '0');
audio_final <= audio_mix;
else
audio_mix <= audio_mix + ("00" & current_input);
end if;
end if;
if (rst='1') then
data_out(17 downto 0) <= (others => '0');
else
if (audio_final(19) = '0') then
data_out(17 downto 0) <= audio_final(18 downto 1);
else -- clip
data_out(17 downto 0) <= "111111111111111111";
end if;
end if;
end process;
end behave;
|
--
-- Audio mixer
--
-- Copyright 2011 TRSi
--
-- Version: 0.1
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- Changelog:
--
-- 0.1: First version
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
entity AUDIO_zpuino_sa_audiomixer is
port (
clk: in std_logic;
rst: in std_logic;
ena: in std_logic;
data_in1: in std_logic_vector(17 downto 0);
data_in2: in std_logic_vector(17 downto 0);
data_in3: in std_logic_vector(17 downto 0);
audio_out: out std_logic
);
end entity AUDIO_zpuino_sa_audiomixer;
architecture behave of AUDIO_zpuino_sa_audiomixer is
-- divier per input
signal cnt_div: std_logic_vector(1 downto 0) := (others => '0');
-- accumulator for each input, on 9 bits, enough for 3 inputs@8bits
signal audio_mix: std_logic_vector(19 downto 0) := (others => '0');
-- to store final accumulator value
signal audio_final: std_logic_vector(19 downto 0) := (others => '0');
signal current_input: std_logic_vector(17 downto 0) := (others => '0');
signal data_out: std_logic_vector(17 downto 0) := (others => '0');
-- DAC
component AUDIO_zpuino_sa_sigmadeltaDAC is
generic (
BITS: integer := 18
);
port (
clk_96Mhz: in std_logic;
--rst: in std_logic;
data_in: in std_logic_vector(BITS-1 downto 0);
audio_out: out std_logic
);
end component AUDIO_zpuino_sa_sigmadeltaDAC;
begin
sdo: AUDIO_zpuino_sa_sigmadeltaDAC
generic map (
BITS => 18
)
port map (
clk_96Mhz => clk,
--rst => rst,
data_in => data_out,
audio_out => audio_out
);
-- divide clock by input channels number
p_divider : process
begin
wait until rising_edge(clk);
if (ena = '1') then
if (cnt_div = "00") then
cnt_div <= "11";
else
cnt_div <= cnt_div - "1";
end if;
end if;
end process;
-- assign an input
p_chan_mixer : process(cnt_div, data_in1, data_in2, data_in3)
begin
current_input <= (others => DontCareValue);
case cnt_div(1 downto 0) is
when "11" =>
current_input <= data_in1;
when "10" =>
current_input <= data_in2;
when "01" =>
current_input <= data_in3;
when "00" => null; -- mix outputs become valid on this clock
when others => null;
end case;
end process;
-- mixer process, input by input
p_op_mixer : process
begin
wait until rising_edge(clk);
if (ena = '1') then
if (cnt_div(1 downto 0) = "00") then
audio_mix <= (others => '0');
audio_final <= audio_mix;
else
audio_mix <= audio_mix + ("00" & current_input);
end if;
end if;
if (rst='1') then
data_out(17 downto 0) <= (others => '0');
else
if (audio_final(19) = '0') then
data_out(17 downto 0) <= audio_final(18 downto 1);
else -- clip
data_out(17 downto 0) <= "111111111111111111";
end if;
end if;
end process;
end behave;
|
--
-- Audio mixer
--
-- Copyright 2011 TRSi
--
-- Version: 0.1
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- Changelog:
--
-- 0.1: First version
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
entity AUDIO_zpuino_sa_audiomixer is
port (
clk: in std_logic;
rst: in std_logic;
ena: in std_logic;
data_in1: in std_logic_vector(17 downto 0);
data_in2: in std_logic_vector(17 downto 0);
data_in3: in std_logic_vector(17 downto 0);
audio_out: out std_logic
);
end entity AUDIO_zpuino_sa_audiomixer;
architecture behave of AUDIO_zpuino_sa_audiomixer is
-- divier per input
signal cnt_div: std_logic_vector(1 downto 0) := (others => '0');
-- accumulator for each input, on 9 bits, enough for 3 inputs@8bits
signal audio_mix: std_logic_vector(19 downto 0) := (others => '0');
-- to store final accumulator value
signal audio_final: std_logic_vector(19 downto 0) := (others => '0');
signal current_input: std_logic_vector(17 downto 0) := (others => '0');
signal data_out: std_logic_vector(17 downto 0) := (others => '0');
-- DAC
component AUDIO_zpuino_sa_sigmadeltaDAC is
generic (
BITS: integer := 18
);
port (
clk_96Mhz: in std_logic;
--rst: in std_logic;
data_in: in std_logic_vector(BITS-1 downto 0);
audio_out: out std_logic
);
end component AUDIO_zpuino_sa_sigmadeltaDAC;
begin
sdo: AUDIO_zpuino_sa_sigmadeltaDAC
generic map (
BITS => 18
)
port map (
clk_96Mhz => clk,
--rst => rst,
data_in => data_out,
audio_out => audio_out
);
-- divide clock by input channels number
p_divider : process
begin
wait until rising_edge(clk);
if (ena = '1') then
if (cnt_div = "00") then
cnt_div <= "11";
else
cnt_div <= cnt_div - "1";
end if;
end if;
end process;
-- assign an input
p_chan_mixer : process(cnt_div, data_in1, data_in2, data_in3)
begin
current_input <= (others => DontCareValue);
case cnt_div(1 downto 0) is
when "11" =>
current_input <= data_in1;
when "10" =>
current_input <= data_in2;
when "01" =>
current_input <= data_in3;
when "00" => null; -- mix outputs become valid on this clock
when others => null;
end case;
end process;
-- mixer process, input by input
p_op_mixer : process
begin
wait until rising_edge(clk);
if (ena = '1') then
if (cnt_div(1 downto 0) = "00") then
audio_mix <= (others => '0');
audio_final <= audio_mix;
else
audio_mix <= audio_mix + ("00" & current_input);
end if;
end if;
if (rst='1') then
data_out(17 downto 0) <= (others => '0');
else
if (audio_final(19) = '0') then
data_out(17 downto 0) <= audio_final(18 downto 1);
else -- clip
data_out(17 downto 0) <= "111111111111111111";
end if;
end if;
end process;
end behave;
|
--
-- Audio mixer
--
-- Copyright 2011 TRSi
--
-- Version: 0.1
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- Changelog:
--
-- 0.1: First version
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
entity AUDIO_zpuino_sa_audiomixer is
port (
clk: in std_logic;
rst: in std_logic;
ena: in std_logic;
data_in1: in std_logic_vector(17 downto 0);
data_in2: in std_logic_vector(17 downto 0);
data_in3: in std_logic_vector(17 downto 0);
audio_out: out std_logic
);
end entity AUDIO_zpuino_sa_audiomixer;
architecture behave of AUDIO_zpuino_sa_audiomixer is
-- divier per input
signal cnt_div: std_logic_vector(1 downto 0) := (others => '0');
-- accumulator for each input, on 9 bits, enough for 3 inputs@8bits
signal audio_mix: std_logic_vector(19 downto 0) := (others => '0');
-- to store final accumulator value
signal audio_final: std_logic_vector(19 downto 0) := (others => '0');
signal current_input: std_logic_vector(17 downto 0) := (others => '0');
signal data_out: std_logic_vector(17 downto 0) := (others => '0');
-- DAC
component AUDIO_zpuino_sa_sigmadeltaDAC is
generic (
BITS: integer := 18
);
port (
clk_96Mhz: in std_logic;
--rst: in std_logic;
data_in: in std_logic_vector(BITS-1 downto 0);
audio_out: out std_logic
);
end component AUDIO_zpuino_sa_sigmadeltaDAC;
begin
sdo: AUDIO_zpuino_sa_sigmadeltaDAC
generic map (
BITS => 18
)
port map (
clk_96Mhz => clk,
--rst => rst,
data_in => data_out,
audio_out => audio_out
);
-- divide clock by input channels number
p_divider : process
begin
wait until rising_edge(clk);
if (ena = '1') then
if (cnt_div = "00") then
cnt_div <= "11";
else
cnt_div <= cnt_div - "1";
end if;
end if;
end process;
-- assign an input
p_chan_mixer : process(cnt_div, data_in1, data_in2, data_in3)
begin
current_input <= (others => DontCareValue);
case cnt_div(1 downto 0) is
when "11" =>
current_input <= data_in1;
when "10" =>
current_input <= data_in2;
when "01" =>
current_input <= data_in3;
when "00" => null; -- mix outputs become valid on this clock
when others => null;
end case;
end process;
-- mixer process, input by input
p_op_mixer : process
begin
wait until rising_edge(clk);
if (ena = '1') then
if (cnt_div(1 downto 0) = "00") then
audio_mix <= (others => '0');
audio_final <= audio_mix;
else
audio_mix <= audio_mix + ("00" & current_input);
end if;
end if;
if (rst='1') then
data_out(17 downto 0) <= (others => '0');
else
if (audio_final(19) = '0') then
data_out(17 downto 0) <= audio_final(18 downto 1);
else -- clip
data_out(17 downto 0) <= "111111111111111111";
end if;
end if;
end process;
end behave;
|
--
-- Audio mixer
--
-- Copyright 2011 TRSi
--
-- Version: 0.1
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- Changelog:
--
-- 0.1: First version
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
entity AUDIO_zpuino_sa_audiomixer is
port (
clk: in std_logic;
rst: in std_logic;
ena: in std_logic;
data_in1: in std_logic_vector(17 downto 0);
data_in2: in std_logic_vector(17 downto 0);
data_in3: in std_logic_vector(17 downto 0);
audio_out: out std_logic
);
end entity AUDIO_zpuino_sa_audiomixer;
architecture behave of AUDIO_zpuino_sa_audiomixer is
-- divier per input
signal cnt_div: std_logic_vector(1 downto 0) := (others => '0');
-- accumulator for each input, on 9 bits, enough for 3 inputs@8bits
signal audio_mix: std_logic_vector(19 downto 0) := (others => '0');
-- to store final accumulator value
signal audio_final: std_logic_vector(19 downto 0) := (others => '0');
signal current_input: std_logic_vector(17 downto 0) := (others => '0');
signal data_out: std_logic_vector(17 downto 0) := (others => '0');
-- DAC
component AUDIO_zpuino_sa_sigmadeltaDAC is
generic (
BITS: integer := 18
);
port (
clk_96Mhz: in std_logic;
--rst: in std_logic;
data_in: in std_logic_vector(BITS-1 downto 0);
audio_out: out std_logic
);
end component AUDIO_zpuino_sa_sigmadeltaDAC;
begin
sdo: AUDIO_zpuino_sa_sigmadeltaDAC
generic map (
BITS => 18
)
port map (
clk_96Mhz => clk,
--rst => rst,
data_in => data_out,
audio_out => audio_out
);
-- divide clock by input channels number
p_divider : process
begin
wait until rising_edge(clk);
if (ena = '1') then
if (cnt_div = "00") then
cnt_div <= "11";
else
cnt_div <= cnt_div - "1";
end if;
end if;
end process;
-- assign an input
p_chan_mixer : process(cnt_div, data_in1, data_in2, data_in3)
begin
current_input <= (others => DontCareValue);
case cnt_div(1 downto 0) is
when "11" =>
current_input <= data_in1;
when "10" =>
current_input <= data_in2;
when "01" =>
current_input <= data_in3;
when "00" => null; -- mix outputs become valid on this clock
when others => null;
end case;
end process;
-- mixer process, input by input
p_op_mixer : process
begin
wait until rising_edge(clk);
if (ena = '1') then
if (cnt_div(1 downto 0) = "00") then
audio_mix <= (others => '0');
audio_final <= audio_mix;
else
audio_mix <= audio_mix + ("00" & current_input);
end if;
end if;
if (rst='1') then
data_out(17 downto 0) <= (others => '0');
else
if (audio_final(19) = '0') then
data_out(17 downto 0) <= audio_final(18 downto 1);
else -- clip
data_out(17 downto 0) <= "111111111111111111";
end if;
end if;
end process;
end behave;
|
--
-- Audio mixer
--
-- Copyright 2011 TRSi
--
-- Version: 0.1
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- Changelog:
--
-- 0.1: First version
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
entity AUDIO_zpuino_sa_audiomixer is
port (
clk: in std_logic;
rst: in std_logic;
ena: in std_logic;
data_in1: in std_logic_vector(17 downto 0);
data_in2: in std_logic_vector(17 downto 0);
data_in3: in std_logic_vector(17 downto 0);
audio_out: out std_logic
);
end entity AUDIO_zpuino_sa_audiomixer;
architecture behave of AUDIO_zpuino_sa_audiomixer is
-- divier per input
signal cnt_div: std_logic_vector(1 downto 0) := (others => '0');
-- accumulator for each input, on 9 bits, enough for 3 inputs@8bits
signal audio_mix: std_logic_vector(19 downto 0) := (others => '0');
-- to store final accumulator value
signal audio_final: std_logic_vector(19 downto 0) := (others => '0');
signal current_input: std_logic_vector(17 downto 0) := (others => '0');
signal data_out: std_logic_vector(17 downto 0) := (others => '0');
-- DAC
component AUDIO_zpuino_sa_sigmadeltaDAC is
generic (
BITS: integer := 18
);
port (
clk_96Mhz: in std_logic;
--rst: in std_logic;
data_in: in std_logic_vector(BITS-1 downto 0);
audio_out: out std_logic
);
end component AUDIO_zpuino_sa_sigmadeltaDAC;
begin
sdo: AUDIO_zpuino_sa_sigmadeltaDAC
generic map (
BITS => 18
)
port map (
clk_96Mhz => clk,
--rst => rst,
data_in => data_out,
audio_out => audio_out
);
-- divide clock by input channels number
p_divider : process
begin
wait until rising_edge(clk);
if (ena = '1') then
if (cnt_div = "00") then
cnt_div <= "11";
else
cnt_div <= cnt_div - "1";
end if;
end if;
end process;
-- assign an input
p_chan_mixer : process(cnt_div, data_in1, data_in2, data_in3)
begin
current_input <= (others => DontCareValue);
case cnt_div(1 downto 0) is
when "11" =>
current_input <= data_in1;
when "10" =>
current_input <= data_in2;
when "01" =>
current_input <= data_in3;
when "00" => null; -- mix outputs become valid on this clock
when others => null;
end case;
end process;
-- mixer process, input by input
p_op_mixer : process
begin
wait until rising_edge(clk);
if (ena = '1') then
if (cnt_div(1 downto 0) = "00") then
audio_mix <= (others => '0');
audio_final <= audio_mix;
else
audio_mix <= audio_mix + ("00" & current_input);
end if;
end if;
if (rst='1') then
data_out(17 downto 0) <= (others => '0');
else
if (audio_final(19) = '0') then
data_out(17 downto 0) <= audio_final(18 downto 1);
else -- clip
data_out(17 downto 0) <= "111111111111111111";
end if;
end if;
end process;
end behave;
|
--
-- Audio mixer
--
-- Copyright 2011 TRSi
--
-- Version: 0.1
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- Changelog:
--
-- 0.1: First version
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
entity AUDIO_zpuino_sa_audiomixer is
port (
clk: in std_logic;
rst: in std_logic;
ena: in std_logic;
data_in1: in std_logic_vector(17 downto 0);
data_in2: in std_logic_vector(17 downto 0);
data_in3: in std_logic_vector(17 downto 0);
audio_out: out std_logic
);
end entity AUDIO_zpuino_sa_audiomixer;
architecture behave of AUDIO_zpuino_sa_audiomixer is
-- divier per input
signal cnt_div: std_logic_vector(1 downto 0) := (others => '0');
-- accumulator for each input, on 9 bits, enough for 3 inputs@8bits
signal audio_mix: std_logic_vector(19 downto 0) := (others => '0');
-- to store final accumulator value
signal audio_final: std_logic_vector(19 downto 0) := (others => '0');
signal current_input: std_logic_vector(17 downto 0) := (others => '0');
signal data_out: std_logic_vector(17 downto 0) := (others => '0');
-- DAC
component AUDIO_zpuino_sa_sigmadeltaDAC is
generic (
BITS: integer := 18
);
port (
clk_96Mhz: in std_logic;
--rst: in std_logic;
data_in: in std_logic_vector(BITS-1 downto 0);
audio_out: out std_logic
);
end component AUDIO_zpuino_sa_sigmadeltaDAC;
begin
sdo: AUDIO_zpuino_sa_sigmadeltaDAC
generic map (
BITS => 18
)
port map (
clk_96Mhz => clk,
--rst => rst,
data_in => data_out,
audio_out => audio_out
);
-- divide clock by input channels number
p_divider : process
begin
wait until rising_edge(clk);
if (ena = '1') then
if (cnt_div = "00") then
cnt_div <= "11";
else
cnt_div <= cnt_div - "1";
end if;
end if;
end process;
-- assign an input
p_chan_mixer : process(cnt_div, data_in1, data_in2, data_in3)
begin
current_input <= (others => DontCareValue);
case cnt_div(1 downto 0) is
when "11" =>
current_input <= data_in1;
when "10" =>
current_input <= data_in2;
when "01" =>
current_input <= data_in3;
when "00" => null; -- mix outputs become valid on this clock
when others => null;
end case;
end process;
-- mixer process, input by input
p_op_mixer : process
begin
wait until rising_edge(clk);
if (ena = '1') then
if (cnt_div(1 downto 0) = "00") then
audio_mix <= (others => '0');
audio_final <= audio_mix;
else
audio_mix <= audio_mix + ("00" & current_input);
end if;
end if;
if (rst='1') then
data_out(17 downto 0) <= (others => '0');
else
if (audio_final(19) = '0') then
data_out(17 downto 0) <= audio_final(18 downto 1);
else -- clip
data_out(17 downto 0) <= "111111111111111111";
end if;
end if;
end process;
end behave;
|
--
-- Audio mixer
--
-- Copyright 2011 TRSi
--
-- Version: 0.1
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- Changelog:
--
-- 0.1: First version
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
entity AUDIO_zpuino_sa_audiomixer is
port (
clk: in std_logic;
rst: in std_logic;
ena: in std_logic;
data_in1: in std_logic_vector(17 downto 0);
data_in2: in std_logic_vector(17 downto 0);
data_in3: in std_logic_vector(17 downto 0);
audio_out: out std_logic
);
end entity AUDIO_zpuino_sa_audiomixer;
architecture behave of AUDIO_zpuino_sa_audiomixer is
-- divier per input
signal cnt_div: std_logic_vector(1 downto 0) := (others => '0');
-- accumulator for each input, on 9 bits, enough for 3 inputs@8bits
signal audio_mix: std_logic_vector(19 downto 0) := (others => '0');
-- to store final accumulator value
signal audio_final: std_logic_vector(19 downto 0) := (others => '0');
signal current_input: std_logic_vector(17 downto 0) := (others => '0');
signal data_out: std_logic_vector(17 downto 0) := (others => '0');
-- DAC
component AUDIO_zpuino_sa_sigmadeltaDAC is
generic (
BITS: integer := 18
);
port (
clk_96Mhz: in std_logic;
--rst: in std_logic;
data_in: in std_logic_vector(BITS-1 downto 0);
audio_out: out std_logic
);
end component AUDIO_zpuino_sa_sigmadeltaDAC;
begin
sdo: AUDIO_zpuino_sa_sigmadeltaDAC
generic map (
BITS => 18
)
port map (
clk_96Mhz => clk,
--rst => rst,
data_in => data_out,
audio_out => audio_out
);
-- divide clock by input channels number
p_divider : process
begin
wait until rising_edge(clk);
if (ena = '1') then
if (cnt_div = "00") then
cnt_div <= "11";
else
cnt_div <= cnt_div - "1";
end if;
end if;
end process;
-- assign an input
p_chan_mixer : process(cnt_div, data_in1, data_in2, data_in3)
begin
current_input <= (others => DontCareValue);
case cnt_div(1 downto 0) is
when "11" =>
current_input <= data_in1;
when "10" =>
current_input <= data_in2;
when "01" =>
current_input <= data_in3;
when "00" => null; -- mix outputs become valid on this clock
when others => null;
end case;
end process;
-- mixer process, input by input
p_op_mixer : process
begin
wait until rising_edge(clk);
if (ena = '1') then
if (cnt_div(1 downto 0) = "00") then
audio_mix <= (others => '0');
audio_final <= audio_mix;
else
audio_mix <= audio_mix + ("00" & current_input);
end if;
end if;
if (rst='1') then
data_out(17 downto 0) <= (others => '0');
else
if (audio_final(19) = '0') then
data_out(17 downto 0) <= audio_final(18 downto 1);
else -- clip
data_out(17 downto 0) <= "111111111111111111";
end if;
end if;
end process;
end behave;
|
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