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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:11:48 12/23/2015
-- Design Name:
-- Module Name: datapath - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity datapath is
Port ( Clock : in STD_LOGIC;
S : IN std_logic_vector(1 downto 0);
S_t : IN std_logic_vector(1 downto 0);
EN125 : in STD_LOGIC;
EN346 : in STD_LOGIC;
EN78 : in STD_LOGIC;
X1 : IN std_logic_vector(15 downto 0);
X2 : IN std_logic_vector(15 downto 0);
X3 : IN std_logic_vector(15 downto 0);
X4 : IN std_logic_vector(15 downto 0);
Z1 : IN std_logic_vector(15 downto 0);
Z2 : IN std_logic_vector(15 downto 0);
Z3 : IN std_logic_vector(15 downto 0);
Z4 : IN std_logic_vector(15 downto 0);
Z5 : IN std_logic_vector(15 downto 0);
Z6 : IN std_logic_vector(15 downto 0);
Y1_trafo : OUT std_logic_vector(15 downto 0);
Y2_trafo : OUT std_logic_vector(15 downto 0);
Y3_trafo : OUT std_logic_vector(15 downto 0);
Y4_trafo : OUT std_logic_vector(15 downto 0);
Y1 : OUT std_logic_vector(15 downto 0);
Y2 : OUT std_logic_vector(15 downto 0);
Y3 : OUT std_logic_vector(15 downto 0);
Y4 : OUT std_logic_vector(15 downto 0));
end datapath;
architecture Behavioral of datapath is
COMPONENT register_16bit
PORT(
D : IN std_logic_vector(15 downto 0);
Q : OUT std_logic_vector(15 downto 0);
en : IN std_logic;
clk : IN std_logic
);
END COMPONENT;
COMPONENT multiplexer_4_to_1
PORT(
in1 : IN std_logic_vector(15 downto 0);
in2 : IN std_logic_vector(15 downto 0);
in3 : IN std_logic_vector(15 downto 0);
in4 : IN std_logic_vector(15 downto 0);
S : IN std_logic_vector(1 downto 0);
O : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT mulop
PORT(
X : IN std_logic_vector(15 downto 0);
Y : IN std_logic_vector(15 downto 0);
O : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT addop
PORT(
A : IN std_logic_vector(15 downto 0);
B : IN std_logic_vector(15 downto 0);
O : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT xorop
PORT(
A : IN std_logic_vector(15 downto 0);
B : IN std_logic_vector(15 downto 0);
O : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
SIGNAL MUL1_OUT : std_logic_vector(15 downto 0);
SIGNAL ADD1_OUT : std_logic_vector(15 downto 0);
SIGNAL XOR1_OUT : std_logic_vector(15 downto 0);
SIGNAL R1_OUT : std_logic_vector(15 downto 0);
SIGNAL R2_OUT : std_logic_vector(15 downto 0);
SIGNAL R3_OUT : std_logic_vector(15 downto 0);
SIGNAL R4_OUT : std_logic_vector(15 downto 0);
SIGNAL R5_OUT : std_logic_vector(15 downto 0);
SIGNAL R6_OUT : std_logic_vector(15 downto 0);
SIGNAL R7_OUT : std_logic_vector(15 downto 0);
SIGNAL R8_OUT : std_logic_vector(15 downto 0);
SIGNAL MUX1_OUT : std_logic_vector(15 downto 0);
SIGNAL MUX2_OUT : std_logic_vector(15 downto 0);
SIGNAL MUX3_OUT : std_logic_vector(15 downto 0);
SIGNAL MUX4_OUT : std_logic_vector(15 downto 0);
begin
Y3_trafo <= R3_OUT;
Y2_trafo <= R2_OUT;
Y4_trafo <= R4_OUT;
Y1_trafo <= R1_OUT;
REG_1: register_16bit PORT MAP (
D => MUL1_OUT,
Q => R1_OUT,
en => EN125,
clk => Clock
);
REG_2: register_16bit PORT MAP (
D => ADD1_OUT,
Q => R2_OUT,
en => EN125,
clk => Clock
);
REG_3: register_16bit PORT MAP (
D => ADD1_OUT,
Q => R3_OUT,
en => EN346,
clk => Clock
);
REG_4: register_16bit PORT MAP (
D => MUL1_OUT,
Q => R4_OUT,
en => EN346,
clk => Clock
);
REG_5: register_16bit PORT MAP (
D => XOR1_OUT,
Q => R5_OUT,
en => EN125,
clk => Clock
);
REG_6: register_16bit PORT MAP (
D => XOR1_OUT,
Q => R6_OUT,
en => EN346,
clk => Clock
);
REG_7: register_16bit PORT MAP (
D => MUL1_OUT,
Q => R7_OUT,
en => EN78,
clk => Clock
);
REG_8: register_16bit PORT MAP (
D => ADD1_OUT,
Q => R8_OUT,
en => EN78,
clk => Clock
);
XOR_1: xorop PORT MAP (
A => MUL1_OUT,
B => ADD1_OUT,
O => XOR1_OUT
);
XOR_2: xorop PORT MAP (
A => R3_OUT,
B => ADD1_OUT,
O => Y3
);
XOR_3: xorop PORT MAP (
A => R2_OUT,
B => MUL1_OUT,
O => Y2
);
XOR_4: xorop PORT MAP (
A => R4_OUT,
B => ADD1_OUT,
O => Y4
);
XOR_5: xorop PORT MAP (
A => R1_OUT,
B => MUL1_OUT,
O => Y1
);
ADDER1: addop PORT MAP (
A => MUX3_OUT,
B => MUX4_OUT,
O => ADD1_OUT
);
MUL1: mulop PORT MAP (
X => MUX1_OUT,
Y => MUX2_OUT,
O => MUL1_OUT
);
MUX1_4_to_1: multiplexer_4_to_1 PORT MAP (
in1 => X1,
in2 => X4,
in3 => Z5,
in4 => Z6,
S => S,
O => MUX1_OUT
);
MUX2_4_to_1: multiplexer_4_to_1 PORT MAP (
in1 => Z1,
in2 => Z4,
in3 => R5_OUT,
in4 => R8_OUT,
S => S,
O => MUX2_OUT
);
MUX3_4_to_1: multiplexer_4_to_1 PORT MAP (
in1 => X3,
in2 => X2,
in3 => R6_OUT,
in4 => R7_OUT,
S => S,
O => MUX3_OUT
);
MUX4_4_to_1: multiplexer_4_to_1 PORT MAP (
in1 => Z3,
in2 => Z2,
in3 => MUL1_OUT,
in4 => MUL1_OUT,
S => S_t,
O => MUX4_OUT
);
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:11:48 12/23/2015
-- Design Name:
-- Module Name: datapath - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity datapath is
Port ( Clock : in STD_LOGIC;
S : IN std_logic_vector(1 downto 0);
S_t : IN std_logic_vector(1 downto 0);
EN125 : in STD_LOGIC;
EN346 : in STD_LOGIC;
EN78 : in STD_LOGIC;
X1 : IN std_logic_vector(15 downto 0);
X2 : IN std_logic_vector(15 downto 0);
X3 : IN std_logic_vector(15 downto 0);
X4 : IN std_logic_vector(15 downto 0);
Z1 : IN std_logic_vector(15 downto 0);
Z2 : IN std_logic_vector(15 downto 0);
Z3 : IN std_logic_vector(15 downto 0);
Z4 : IN std_logic_vector(15 downto 0);
Z5 : IN std_logic_vector(15 downto 0);
Z6 : IN std_logic_vector(15 downto 0);
Y1_trafo : OUT std_logic_vector(15 downto 0);
Y2_trafo : OUT std_logic_vector(15 downto 0);
Y3_trafo : OUT std_logic_vector(15 downto 0);
Y4_trafo : OUT std_logic_vector(15 downto 0);
Y1 : OUT std_logic_vector(15 downto 0);
Y2 : OUT std_logic_vector(15 downto 0);
Y3 : OUT std_logic_vector(15 downto 0);
Y4 : OUT std_logic_vector(15 downto 0));
end datapath;
architecture Behavioral of datapath is
COMPONENT register_16bit
PORT(
D : IN std_logic_vector(15 downto 0);
Q : OUT std_logic_vector(15 downto 0);
en : IN std_logic;
clk : IN std_logic
);
END COMPONENT;
COMPONENT multiplexer_4_to_1
PORT(
in1 : IN std_logic_vector(15 downto 0);
in2 : IN std_logic_vector(15 downto 0);
in3 : IN std_logic_vector(15 downto 0);
in4 : IN std_logic_vector(15 downto 0);
S : IN std_logic_vector(1 downto 0);
O : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT mulop
PORT(
X : IN std_logic_vector(15 downto 0);
Y : IN std_logic_vector(15 downto 0);
O : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT addop
PORT(
A : IN std_logic_vector(15 downto 0);
B : IN std_logic_vector(15 downto 0);
O : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
COMPONENT xorop
PORT(
A : IN std_logic_vector(15 downto 0);
B : IN std_logic_vector(15 downto 0);
O : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
SIGNAL MUL1_OUT : std_logic_vector(15 downto 0);
SIGNAL ADD1_OUT : std_logic_vector(15 downto 0);
SIGNAL XOR1_OUT : std_logic_vector(15 downto 0);
SIGNAL R1_OUT : std_logic_vector(15 downto 0);
SIGNAL R2_OUT : std_logic_vector(15 downto 0);
SIGNAL R3_OUT : std_logic_vector(15 downto 0);
SIGNAL R4_OUT : std_logic_vector(15 downto 0);
SIGNAL R5_OUT : std_logic_vector(15 downto 0);
SIGNAL R6_OUT : std_logic_vector(15 downto 0);
SIGNAL R7_OUT : std_logic_vector(15 downto 0);
SIGNAL R8_OUT : std_logic_vector(15 downto 0);
SIGNAL MUX1_OUT : std_logic_vector(15 downto 0);
SIGNAL MUX2_OUT : std_logic_vector(15 downto 0);
SIGNAL MUX3_OUT : std_logic_vector(15 downto 0);
SIGNAL MUX4_OUT : std_logic_vector(15 downto 0);
begin
Y3_trafo <= R3_OUT;
Y2_trafo <= R2_OUT;
Y4_trafo <= R4_OUT;
Y1_trafo <= R1_OUT;
REG_1: register_16bit PORT MAP (
D => MUL1_OUT,
Q => R1_OUT,
en => EN125,
clk => Clock
);
REG_2: register_16bit PORT MAP (
D => ADD1_OUT,
Q => R2_OUT,
en => EN125,
clk => Clock
);
REG_3: register_16bit PORT MAP (
D => ADD1_OUT,
Q => R3_OUT,
en => EN346,
clk => Clock
);
REG_4: register_16bit PORT MAP (
D => MUL1_OUT,
Q => R4_OUT,
en => EN346,
clk => Clock
);
REG_5: register_16bit PORT MAP (
D => XOR1_OUT,
Q => R5_OUT,
en => EN125,
clk => Clock
);
REG_6: register_16bit PORT MAP (
D => XOR1_OUT,
Q => R6_OUT,
en => EN346,
clk => Clock
);
REG_7: register_16bit PORT MAP (
D => MUL1_OUT,
Q => R7_OUT,
en => EN78,
clk => Clock
);
REG_8: register_16bit PORT MAP (
D => ADD1_OUT,
Q => R8_OUT,
en => EN78,
clk => Clock
);
XOR_1: xorop PORT MAP (
A => MUL1_OUT,
B => ADD1_OUT,
O => XOR1_OUT
);
XOR_2: xorop PORT MAP (
A => R3_OUT,
B => ADD1_OUT,
O => Y3
);
XOR_3: xorop PORT MAP (
A => R2_OUT,
B => MUL1_OUT,
O => Y2
);
XOR_4: xorop PORT MAP (
A => R4_OUT,
B => ADD1_OUT,
O => Y4
);
XOR_5: xorop PORT MAP (
A => R1_OUT,
B => MUL1_OUT,
O => Y1
);
ADDER1: addop PORT MAP (
A => MUX3_OUT,
B => MUX4_OUT,
O => ADD1_OUT
);
MUL1: mulop PORT MAP (
X => MUX1_OUT,
Y => MUX2_OUT,
O => MUL1_OUT
);
MUX1_4_to_1: multiplexer_4_to_1 PORT MAP (
in1 => X1,
in2 => X4,
in3 => Z5,
in4 => Z6,
S => S,
O => MUX1_OUT
);
MUX2_4_to_1: multiplexer_4_to_1 PORT MAP (
in1 => Z1,
in2 => Z4,
in3 => R5_OUT,
in4 => R8_OUT,
S => S,
O => MUX2_OUT
);
MUX3_4_to_1: multiplexer_4_to_1 PORT MAP (
in1 => X3,
in2 => X2,
in3 => R6_OUT,
in4 => R7_OUT,
S => S,
O => MUX3_OUT
);
MUX4_4_to_1: multiplexer_4_to_1 PORT MAP (
in1 => Z3,
in2 => Z2,
in3 => MUL1_OUT,
in4 => MUL1_OUT,
S => S_t,
O => MUX4_OUT
);
end Behavioral;
|
use std.textio.all;
entity top_ent is
end entity;
architecture default of top_ent is
file fh : text;
begin
process
begin
if endfile(fh) then
null;
end if;
end process;
end architecture;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_t
--
-- Generated
-- by: wig
-- on: Tue Jul 4 05:34:51 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../configuration.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_t-rtl-a.vhd,v 1.5 2006/07/04 09:54:11 wig Exp $
-- $Date: 2006/07/04 09:54:11 $
-- $Log: ent_t-rtl-a.vhd,v $
-- Revision 1.5 2006/07/04 09:54:11 wig
-- Update more testcases, add configuration/cfgfile
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
-- modifiy vhdl_use_arch
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
typedef vhdl_use_arch_def std_ulogic_vector;
-- end of vhdl_use_arch
--
--
-- Start of Generated Architecture rtl of ent_t
--
architecture rtl of ent_t is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component ent_a
-- No Generated Generics
port (
-- Generated Port for Entity ent_a
p_mix_sig_01_go : out std_ulogic;
p_mix_sig_03_go : out std_ulogic;
p_mix_sig_04_gi : in std_ulogic;
p_mix_sig_05_2_1_go : out std_ulogic_vector(1 downto 0);
p_mix_sig_06_gi : in std_ulogic_vector(3 downto 0);
p_mix_sig_i_ae_gi : in std_ulogic_vector(6 downto 0);
p_mix_sig_o_ae_go : out std_ulogic_vector(7 downto 0);
port_i_a : in std_ulogic; -- Input Port
port_o_a : out std_ulogic; -- Output Port
sig_07 : in std_ulogic_vector(5 downto 0); -- Conflicting definition, IN false!
sig_08 : out std_ulogic_vector(8 downto 2); -- VHDL intermediate needed (port name)
sig_13 : out std_ulogic_vector(4 downto 0); -- Create internal signal name
sig_i_a2 : in std_ulogic; -- Input Port
sig_o_a2 : out std_ulogic -- Output Port
-- End of Generated Port for Entity ent_a
);
end component;
-- ---------
component ent_b
-- No Generated Generics
port (
-- Generated Port for Entity ent_b
port_b_1 : in std_ulogic; -- Will create p_mix_sig_1_go port
port_b_3 : in std_ulogic; -- Interhierachy link, will create p_mix_sig_3_go
port_b_4 : out std_ulogic; -- Interhierachy link, will create p_mix_sig_4_gi
port_b_5_1 : in std_ulogic; -- Bus, single bits go to outside, will create p_mix_sig_5_2_2_go __I_AUTO_REDUCED_BUS2SIGNAL
port_b_5_2 : in std_ulogic; -- Bus, single bits go to outside, will create P_MIX_sound_alarm_test5_1_1_GO __I_AUTO_REDUCED_BUS2SIGNAL
port_b_6i : in std_ulogic_vector(3 downto 0); -- Conflicting definition
port_b_6o : out std_ulogic_vector(3 downto 0); -- Conflicting definition
sig_07 : in std_ulogic_vector(5 downto 0); -- Conflicting definition, IN false!
sig_08 : in std_ulogic_vector(8 downto 2) -- VHDL intermediate needed (port name)
-- End of Generated Port for Entity ent_b
);
end component;
-- ---------
component ent_c
-- No Generated Generics
-- Generated Generics for Entity ent_c
-- End of Generated Generics for Entity ent_c
-- No Generated Port
end component;
-- ---------
--
-- Generated Signal List
--
signal sig_01 : std_ulogic;
signal sig_03 : std_ulogic;
signal sig_04 : std_ulogic;
signal sig_05 : std_ulogic_vector(3 downto 0);
signal sig_06 : std_ulogic_vector(3 downto 0);
signal sig_07 : std_ulogic_vector(5 downto 0);
signal sig_08 : std_ulogic_vector(8 downto 2);
-- __I_OUT_OPEN signal sig_13 : std_ulogic_vector(4 downto 0);
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_a
inst_a: ent_a
port map (
p_mix_sig_01_go => sig_01, -- Use internally test1Will create p_mix_sig_1_go port
p_mix_sig_03_go => sig_03, -- Interhierachy link, will create p_mix_sig_3_go
p_mix_sig_04_gi => sig_04, -- Interhierachy link, will create p_mix_sig_4_gi
p_mix_sig_05_2_1_go => sig_05(2 downto 1), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
p_mix_sig_06_gi => sig_06, -- Conflicting definition (X2)
p_mix_sig_i_ae_gi => sig_i_ae, -- Input Bus
p_mix_sig_o_ae_go => sig_o_ae, -- Output Bus
port_i_a => sig_i_a, -- Input Port
port_o_a => sig_o_a, -- Output Port
sig_07 => sig_07, -- Conflicting definition, IN false!
sig_08 => sig_08, -- VHDL intermediate needed (port name)
sig_13 => open, -- Create internal signal name -- __I_OUT_OPEN
sig_i_a2 => sig_i_a2, -- Input Port
sig_o_a2 => sig_o_a2 -- Output Port
);
-- End of Generated Instance Port Map for inst_a
-- Generated Instance Port Map for inst_b
inst_b: ent_b
port map (
port_b_1 => sig_01, -- Use internally test1Will create p_mix_sig_1_go port
port_b_3 => sig_03, -- Interhierachy link, will create p_mix_sig_3_go
port_b_4 => sig_04, -- Interhierachy link, will create p_mix_sig_4_gi
port_b_5_1 => sig_05(2), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
port_b_5_2 => sig_05(1), -- Bus, single bits go to outsideBus, single bits go to outside, will create p_mix_sig_5_2_2_goBu...
port_b_6i => sig_06, -- Conflicting definition (X2)
port_b_6o => sig_06, -- Conflicting definition (X2)
sig_07 => sig_07, -- Conflicting definition, IN false!
sig_08 => sig_08 -- VHDL intermediate needed (port name)
);
-- End of Generated Instance Port Map for inst_b
-- Generated Instance Port Map for inst_c
inst_c: ent_c
;
-- End of Generated Instance Port Map for inst_c
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library basic_library;
entity foo is
generic (
DIVIDER_A : integer := 10;
DIVIDER_B : integer := 20
);
port (
rst_a, clk_in_a : in std_logic;
clk_out_a : out std_logic;
rst_b, clk_in_b : in std_logic;
clk_out_b : out std_logic
);
end foo;
architecture foo of foo is
-- A signal declaration that generates a warning
signal neat_signal : std_logic_vector(DIVIDER_A + DIVIDER_B - 1 downto 0) := (others => '0');
begin
clk_div_a : entity basic_library.clock_divider
generic map (
DIVIDER => DIVIDER_A
)
port map (
reset => rst_a,
clk_input => clk_in_a,
clk_output => clk_out_a
);
clk_div_b : entity basic_library.clock_divider
generic map (
DIVIDER => DIVIDER_B
)
port map (
reset => rst_b,
clk_input => clk_in_b,
clk_output => clk_out_b
);
-----------------------------
-- Asynchronous asignments --
-----------------------------
end foo;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_a_e
--
-- Generated
-- by: wig
-- on: Wed Jul 19 05:22:48 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../logic.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_a_e-rtl-conf-c.vhd,v 1.4 2006/07/19 07:35:16 wig Exp $
-- $Date: 2006/07/19 07:35:16 $
-- $Log: inst_a_e-rtl-conf-c.vhd,v $
-- Revision 1.4 2006/07/19 07:35:16 wig
-- Updated testcases.
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.92 2006/07/12 15:23:40 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_a_e_rtl_conf / inst_a_e
--
configuration inst_a_e_rtl_conf of inst_a_e is
for rtl
-- Generated Configuration
-- __I_NO_CONF_LOGIC for inst_a_and : %AND%
-- __I_NO_CONF_LOGIC use configuration work.%AND%_rtl_conf;
-- __I_NO_CONF_LOGIC end for;
-- __I_NO_CONF_LOGIC for inst_a_and_1 : %AND%
-- __I_NO_CONF_LOGIC use configuration work.%AND%_rtl_conf;
-- __I_NO_CONF_LOGIC end for;
-- __I_NO_CONF_LOGIC for inst_a_or : %OR%
-- __I_NO_CONF_LOGIC use configuration work.%OR%_rtl_conf;
-- __I_NO_CONF_LOGIC end for;
-- __I_NO_CONF_LOGIC for inst_a_or_1 : %OR%
-- __I_NO_CONF_LOGIC use configuration work.%OR%_rtl_conf;
-- __I_NO_CONF_LOGIC end for;
-- __I_NO_CONF_LOGIC for inst_a_wire : %WIRE%
-- __I_NO_CONF_LOGIC use configuration work.%WIRE%_rtl_conf;
-- __I_NO_CONF_LOGIC end for;
-- __I_NO_CONF_LOGIC for inst_a_wire_1 : %WIRE%
-- __I_NO_CONF_LOGIC use configuration work.%WIRE%_rtl_conf;
-- __I_NO_CONF_LOGIC end for;
for inst_aa_i : inst_aa_e
use configuration work.inst_aa_e_rtl_conf;
end for;
for inst_ab_i : inst_ab_e
use configuration work.inst_ab_e_rtl_conf;
end for;
end for;
end inst_a_e_rtl_conf;
--
-- End of Generated Configuration inst_a_e_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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VKMV6Qy+Ng==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 26080)
`protect data_block
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`protect end_protected
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2356.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p02n02i02356ent IS
END c07s02b07x00p02n02i02356ent;
ARCHITECTURE c07s02b07x00p02n02i02356arch OF c07s02b07x00p02n02i02356ent IS
BEGIN
TESTING: PROCESS
type MEMORY is array(INTEGER range <>) of BIT;
type ADDRESS is access MEMORY;
variable ADDRESSV : ADDRESS;
variable INTV : INTEGER;
BEGIN
INTV := 2 ** ADDRESSV ;
assert FALSE
report "***FAILED TEST: c07s02b07x00p02n02i02356 - Exponent can only be of type Integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p02n02i02356arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2356.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p02n02i02356ent IS
END c07s02b07x00p02n02i02356ent;
ARCHITECTURE c07s02b07x00p02n02i02356arch OF c07s02b07x00p02n02i02356ent IS
BEGIN
TESTING: PROCESS
type MEMORY is array(INTEGER range <>) of BIT;
type ADDRESS is access MEMORY;
variable ADDRESSV : ADDRESS;
variable INTV : INTEGER;
BEGIN
INTV := 2 ** ADDRESSV ;
assert FALSE
report "***FAILED TEST: c07s02b07x00p02n02i02356 - Exponent can only be of type Integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p02n02i02356arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2356.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b07x00p02n02i02356ent IS
END c07s02b07x00p02n02i02356ent;
ARCHITECTURE c07s02b07x00p02n02i02356arch OF c07s02b07x00p02n02i02356ent IS
BEGIN
TESTING: PROCESS
type MEMORY is array(INTEGER range <>) of BIT;
type ADDRESS is access MEMORY;
variable ADDRESSV : ADDRESS;
variable INTV : INTEGER;
BEGIN
INTV := 2 ** ADDRESSV ;
assert FALSE
report "***FAILED TEST: c07s02b07x00p02n02i02356 - Exponent can only be of type Integer."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b07x00p02n02i02356arch;
|
library ieee;
-- Commonly imported packages:
-- STD_LOGIC and STD_LOGIC_VECTOR types, and relevant functions
use ieee.std_logic_1164.all;
-- SIGNED and UNSIGNED types, and relevant functions
use ieee.numeric_std.all;
-- Basic sequential functions and concurrent procedures
use ieee.VITAL_Primitives.all;
package DE2_CONSTANTS is
type DE2_SDRAM_ADDR_BUS is array(11 downto 0) of std_logic;
type DE2_SDRAM_DATA_BUS is array(15 downto 0) of std_logic;
type DE2_LCD_DATA_BUS is array(7 downto 0) of std_logic;
type DE2_LED_GREEN is array(7 downto 0) of std_logic;
type DE2_SRAM_ADDR_BUS is array(17 downto 0) of std_logic;
type DE2_SRAM_DATA_BUS is array(15 downto 0) of std_logic;
type DE2_SEVEN_SEGMENT is array (6 downto 0) of std_logic;
constant sev_seg_0 : std_logic_vector( 6 downto 0) := not b"0111111"; -- ~0x3f
constant sev_seg_1 : std_logic_vector( 6 downto 0) := not b"0000110"; -- ~0x06
constant sev_seg_2 : std_logic_vector( 6 downto 0) := not b"1011011"; -- ~0x5b
constant sev_seg_3 : std_logic_vector( 6 downto 0) := not b"1001111"; -- ~0x4f
constant sev_seg_4 : std_logic_vector( 6 downto 0) := not b"1100110"; -- ~0x66
constant sev_seg_5 : std_logic_vector( 6 downto 0) := not b"1101101"; -- ~0x6d
constant sev_seg_6 : std_logic_vector( 6 downto 0) := not b"1111101"; -- ~0x7D
constant sev_seg_7 : std_logic_vector( 6 downto 0) := not b"0000111"; -- ~0x07
constant sev_seg_8 : std_logic_vector( 6 downto 0) := not b"1111111"; -- ~0x7f
constant sev_seg_9 : std_logic_vector( 6 downto 0) := not b"1101111"; -- ~0x6f
constant sev_seg_a : std_logic_vector( 6 downto 0) := not b"1110111"; -- ~0x77
constant sev_seg_b : std_logic_vector( 6 downto 0) := not b"1111100"; -- ~0x7c
constant sev_seg_c : std_logic_vector( 6 downto 0) := not b"0111001"; -- ~0x39
constant sev_seg_d : std_logic_vector( 6 downto 0) := not b"1011110"; -- ~0x5e
constant sev_seg_e : std_logic_vector( 6 downto 0) := not b"1111001"; -- ~0x79
constant sev_seg_f : std_logic_vector( 6 downto 0) := not b"1110001"; -- ~0x71
end DE2_CONSTANTS; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1329.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b01x00p03n05i01329ent IS
END c08s04b01x00p03n05i01329ent;
ARCHITECTURE c08s04b01x00p03n05i01329arch OF c08s04b01x00p03n05i01329ent IS
signal S1, S2, S3 : Bit;
BEGIN
TESTING: PROCESS
BEGIN
S3 <= S1 after 10 ns, null after 100 ns, S2 after 150 ns;
assert FALSE
report "***FAILED TEST: c08s04b01x00p03n05i01329 - Null waveform can not be assigned to unguarded signals."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b01x00p03n05i01329arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1329.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b01x00p03n05i01329ent IS
END c08s04b01x00p03n05i01329ent;
ARCHITECTURE c08s04b01x00p03n05i01329arch OF c08s04b01x00p03n05i01329ent IS
signal S1, S2, S3 : Bit;
BEGIN
TESTING: PROCESS
BEGIN
S3 <= S1 after 10 ns, null after 100 ns, S2 after 150 ns;
assert FALSE
report "***FAILED TEST: c08s04b01x00p03n05i01329 - Null waveform can not be assigned to unguarded signals."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b01x00p03n05i01329arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1329.vhd,v 1.2 2001-10-26 16:30:09 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s04b01x00p03n05i01329ent IS
END c08s04b01x00p03n05i01329ent;
ARCHITECTURE c08s04b01x00p03n05i01329arch OF c08s04b01x00p03n05i01329ent IS
signal S1, S2, S3 : Bit;
BEGIN
TESTING: PROCESS
BEGIN
S3 <= S1 after 10 ns, null after 100 ns, S2 after 150 ns;
assert FALSE
report "***FAILED TEST: c08s04b01x00p03n05i01329 - Null waveform can not be assigned to unguarded signals."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s04b01x00p03n05i01329arch;
|
LIBRARY IEEE;
USE IEEE.std_logic_1164.all, IEEE.std_logic_arith.all, IEEE.std_logic_unsigned.all;
entity test is
generic(
rst_val : std_logic := '0';
thing_size: integer := 201;
bus_width : integer := 201 mod 32);
port(
clk, rstn : in std_logic;
en, start_dec : in std_logic;
addr : in std_logic_vector(2 downto 0);
din : in std_logic_vector(25 downto 0);
we : in std_logic;
pixel_in : in std_logic_vector(7 downto 0);
pix_req : in std_logic;
config, bip : in std_logic;
a, b : in std_logic_vector(7 downto 0);
c, load : in std_logic_vector(7 downto 0);
pack : in std_logic_vector(6 downto 0);
base : in std_logic_vector(2 downto 0);
qtd : in std_logic_vector(21 downto 0);
-- Outputs
dout : out std_logic_vector(25 downto 0);
pixel_out : out std_logic_vector(7 downto 0);
pixel_valid : out std_logic;
code : out std_logic_vector(9 downto 0);
complex : out std_logic_vector(23 downto 0);
eno : out std_logic
);
end test;
architecture rtl of test is
component dsp
generic(
rst_val : std_logic := '0';
thing_size: integer := 201;
bus_width : integer := 22);
port(
-- Inputs
clk, rstn : in std_logic;
-- Outputs
dout : out std_logic_vector(bus_width downto 0);
memaddr : out std_logic_vector(5 downto 0);
memdout : out std_logic_vector(13 downto 0)
);
end component;
signal param : std_logic_vector(7 downto 0);
signal selection : std_logic;
signal start, enf : std_logic; -- Start and enable signals
signal memdin : std_logic_vector(13 downto 0);
signal memaddr : std_logic_vector(5 downto 0);
signal memdout : std_logic_vector(13 downto 0);
signal colour : std_logic_vector(1 downto 0);
begin
dsp_inst0 : dsp
port map(
-- Inputs
clk => clk,
rstn => rstn,
-- Outputs
dout => dout,
memaddr => memaddr,
memdout => memdout
);
dsp_inst1 : dsp
generic map(
rst_val => '1',
bus_width => 16)
port map(
-- Inputs
clk => clk,
rstn => rstn,
-- Outputs
dout => dout,
memaddr => memaddr,
memdout => memdout
);
end rtl;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity bottom is
port ( -- . . . );
--
port_name : in bit := '0' );
--
end entity bottom;
--------------------------------------------------
architecture bottom_arch of bottom is
signal bot_sig : -- . . .; -- 5
--
bit;
--
procedure proc ( -- . . . ) is
--
param_name : in bit := '0' ) is
--
variable v : -- . . .; -- 6
--
bit;
--
begin
-- . . .
--
report "--6: " & v'path_name;
report "--6: " & v'instance_name;
--
end procedure proc;
begin
delays : block is
constant d : integer := 1; -- 7
begin
-- . . .
--
assert false report "--7: " & d'path_name;
assert false report "--7: " & d'instance_name;
--
end block delays;
func : block is
begin
process is
variable v : -- . . .; -- 8
--
bit;
--
begin
-- . . .
--
report "--5: " & bot_sig'path_name;
report "--5: " & bot_sig'instance_name;
report "--8: " & v'path_name;
report "--8: " & v'instance_name;
proc(param_name => open);
wait;
--
--
end process;
end block func;
end architecture bottom_arch;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity bottom is
port ( -- . . . );
--
port_name : in bit := '0' );
--
end entity bottom;
--------------------------------------------------
architecture bottom_arch of bottom is
signal bot_sig : -- . . .; -- 5
--
bit;
--
procedure proc ( -- . . . ) is
--
param_name : in bit := '0' ) is
--
variable v : -- . . .; -- 6
--
bit;
--
begin
-- . . .
--
report "--6: " & v'path_name;
report "--6: " & v'instance_name;
--
end procedure proc;
begin
delays : block is
constant d : integer := 1; -- 7
begin
-- . . .
--
assert false report "--7: " & d'path_name;
assert false report "--7: " & d'instance_name;
--
end block delays;
func : block is
begin
process is
variable v : -- . . .; -- 8
--
bit;
--
begin
-- . . .
--
report "--5: " & bot_sig'path_name;
report "--5: " & bot_sig'instance_name;
report "--8: " & v'path_name;
report "--8: " & v'instance_name;
proc(param_name => open);
wait;
--
--
end process;
end block func;
end architecture bottom_arch;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity bottom is
port ( -- . . . );
--
port_name : in bit := '0' );
--
end entity bottom;
--------------------------------------------------
architecture bottom_arch of bottom is
signal bot_sig : -- . . .; -- 5
--
bit;
--
procedure proc ( -- . . . ) is
--
param_name : in bit := '0' ) is
--
variable v : -- . . .; -- 6
--
bit;
--
begin
-- . . .
--
report "--6: " & v'path_name;
report "--6: " & v'instance_name;
--
end procedure proc;
begin
delays : block is
constant d : integer := 1; -- 7
begin
-- . . .
--
assert false report "--7: " & d'path_name;
assert false report "--7: " & d'instance_name;
--
end block delays;
func : block is
begin
process is
variable v : -- . . .; -- 8
--
bit;
--
begin
-- . . .
--
report "--5: " & bot_sig'path_name;
report "--5: " & bot_sig'instance_name;
report "--8: " & v'path_name;
report "--8: " & v'instance_name;
proc(param_name => open);
wait;
--
--
end process;
end block func;
end architecture bottom_arch;
|
----------------------------------------------------------------------------------
-- Company:LAAS-CNRS
-- Author:Jonathan Piat <[email protected]>
--
-- Create Date: 20:17:12 04/14/2012
-- Design Name:
-- Module Name: generic_latch - Behavioral
-- Project Name:
-- Target Devices: Spartan 6
-- Tool versions: ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity generic_latch is
generic(NBIT : positive := 8);
Port ( clk : in STD_LOGIC;
resetn : in STD_LOGIC;
sraz : in STD_LOGIC;
en : in STD_LOGIC;
d : in STD_LOGIC_VECTOR((NBIT - 1) downto 0);
q : out STD_LOGIC_VECTOR((NBIT - 1) downto 0));
end generic_latch;
architecture Behavioral of generic_latch is
signal Qp : std_logic_vector((NBIT - 1) downto 0);
begin
process(clk, resetn)
begin
if resetn = '0' then
Qp <= (others => '0');
elsif clk'event and clk = '1' then
if sraz = '1' then
Qp <= (others => '0');
elsif en = '1' then
Qp <= d ;
end if ;
end if ;
end process ;
q <= Qp;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:LAAS-CNRS
-- Author:Jonathan Piat <[email protected]>
--
-- Create Date: 20:17:12 04/14/2012
-- Design Name:
-- Module Name: generic_latch - Behavioral
-- Project Name:
-- Target Devices: Spartan 6
-- Tool versions: ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity generic_latch is
generic(NBIT : positive := 8);
Port ( clk : in STD_LOGIC;
resetn : in STD_LOGIC;
sraz : in STD_LOGIC;
en : in STD_LOGIC;
d : in STD_LOGIC_VECTOR((NBIT - 1) downto 0);
q : out STD_LOGIC_VECTOR((NBIT - 1) downto 0));
end generic_latch;
architecture Behavioral of generic_latch is
signal Qp : std_logic_vector((NBIT - 1) downto 0);
begin
process(clk, resetn)
begin
if resetn = '0' then
Qp <= (others => '0');
elsif clk'event and clk = '1' then
if sraz = '1' then
Qp <= (others => '0');
elsif en = '1' then
Qp <= d ;
end if ;
end if ;
end process ;
q <= Qp;
end Behavioral;
|
-- CTRL_TELEGRAM_CHECK
-- Profibus Telegramtyp ermitteln, aktuelle Laenge und Telegram komplett anzeigen
-- Projekt: PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 02.01.2013
-- Bearbeiter: mharndt
-- Geaendert: 28.01.2013
-- Umstellung auf: rising_edge(CLK) und falling_edge(CLK) und http://www.sigasi.com/content/clock-edge-detection
-- Optimierungen aus: http://www.lothar-miller.de/s9y/categories/37-FSM
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_TELEGRAM_CHECK is
Port (TELEGRAM_RUN : in std_logic; --Eingangsvariable, Naechstes Telegram
BYTE_IN : in std_logic_vector (7 downto 0); --Eingangsvariable, Byte, 8bit
PARITY_OK : in std_logic; --Eingangsvariable, Paritaet i.O.
BYTE_CMPLT : in std_logic; --Eingangsvariable, BYTE komplett empfangen
PAUSE_END : in std_logic; --Eingangsvariable, Pause erkannt und beendet
TELEGRAM_STOP : in std_logic; --Eingangsvariable, nach Telegramm stoppen
ERROR_CTRL : in std_logic; --Eingangsvariable, Fehlerkontrolle
T_END : out std_logic; --Ausgangsvariable, Telegramm zu Ende
T_LENGTH : out std_logic_vector (7 downto 0); --Ausgangsvariable, Telegramlaenge, 8bit
T_TYPE : out std_logic_vector (3 downto 0); --Ausgangsvariable, Telegramtyp, 4bit
SEND_OUT : out std_logic; --Ausgangsvariable, Senden
PARITY_FAIL : out std_logic; --Ausgangsvariable, Paritaetsprüfung fehlerhaft
NO_ED : out std_logic; --Ausgangsvariable, kein Enddelimiter festgestellt
WORKING : out std_logic; --Ausgangsvariable, TELEGRAM_CHECK arbeitet
KNOWN_T : out std_logic; --Ausgangsvariable, Telegramm erkannt
UNKNOWN_BYTE : out std_logic; --Ausgangsvariable, BYTE nicht erkannt
CLK : in std_logic; --Taktvariable
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
DISPL_COUNT : in std_logic; --Eingangsvariable, Zähler anzeigen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0)); --Folgezustand Zahl2, binärzahl
end CTRL_TELEGRAM_CHECK;
architecture Behavioral of CTRL_TELEGRAM_CHECK is
type TYPE_STATE is
(ST_TC_00, --Zustaende TELEGRAM_CHECK
ST_TC_01,
ST_TC_02,
ST_TC_03,
ST_TC_04,
ST_TC_05,
ST_TC_06,
ST_TC_07,
ST_TC_08,
ST_TC_09,
ST_TC_10,
ST_TC_11);
signal SV : TYPE_STATE := ST_TC_00; --Zustandsvariable
signal n_SV: TYPE_STATE := ST_TC_00; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE := ST_TC_00; --Zustandsvariable, Ausgang Master
signal COUNT : std_logic_vector (7 downto 0) := x"00"; -- Vektor, Telegrammlaenge, 8bit
signal n_COUNT : std_logic_vector (7 downto 0) := x"00"; -- Vektor, Telegrammlaenge, 8bit, neuer Wert
signal COUNT_M : std_logic_vector (7 downto 0) := x"00"; -- Vektor, Telegrammlaenge, 8bit, Ausgang Master
signal STATE_SV : std_logic_vector (7 downto 0) := x"00"; -- aktueller Zustand in 8 Bit, binär
signal STATE_n_SV : std_logic_vector (7 downto 0) := x"00"; -- Folgezustand in 8 Bit, binär
begin
SREG_M_PROC: process (RESET, n_SV, n_COUNT, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_TC_00;
COUNT_M <= x"00";
else
if rising_edge(CLK)
then
if (IN_NEXT_STATE = '1')
then
SV_M <= n_SV;
COUNT_M <= n_COUNT;
else
SV_M <= SV_M;
COUNT_M <= COUNT_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, CLK) --Slave
begin
if (RESET = '1')
then
SV <= ST_TC_00;
COUNT <= x"00";
else
if falling_edge(CLK)
then
SV <= SV_M;
COUNT <= COUNT_M;
end if;
end if;
end process;
TELEGRAM_CHECK_PROC: process (SV, COUNT, TELEGRAM_RUN, PAUSE_END, BYTE_CMPLT, PARITY_OK, BYTE_IN, TELEGRAM_STOP, ERROR_CTRL) --Telegramme erkennen und Ende Telegram erkennen und ausgeben
begin
case SV is
when ST_TC_00 =>
if (TELEGRAM_RUN = '1')
then
if (PAUSE_END = '1')
then
--TC01
n_COUNT <= COUNT; --Zaehler erhöhen
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --arbeitet
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_01; --Zustandsübergang
else
--TC00
n_COUNT <= x"00";
T_END <= '0';
T_LENGTH <= x"00";
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_00;
end if;
else --TELEGRAM_RUN = '0'
-- TC00
n_COUNT <= x"00";
T_END <= '0';
T_LENGTH <= x"00";
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_00;
end if;
when ST_TC_01 =>
if (BYTE_CMPLT = '1')
then
if (PARITY_OK = '1')
then
if (BYTE_IN = x"10") --SD1 erkannt
then
--TC02
n_COUNT <= COUNT+1; --Zaehler erhöhen
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0001"; --SD1
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --arbeitet
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_02; --Zustandsübergang
else
if (BYTE_IN = x"68") --SD2 erkannt
then
--TC05
n_COUNT <= COUNT+1; --Zaehler erhöhen
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0010"; --SD2
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --arbeitet
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_03; --Zustandsübergang
else
if (BYTE_IN = x"A2") --SD3 erkannt
then
--TC08
n_COUNT <= COUNT+1; --Zaehler erhöhen
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0011"; --SD3
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --arbeitet
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_04; --Zustandsübergang
else
if (BYTE_IN = x"DC") --SD4 erkannt
then
--TC11
n_COUNT <= COUNT+1; --Zaehler erhöhen
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0100"; --SD4
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --arbeitet
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_05; --Zustandsübergang
else
if (BYTE_IN = x"E5") --SC erkannt
then
--TC14
n_COUNT <= COUNT+1; --Zaehler erhöhen
T_END <= '1'; --Telgeram Ende
T_LENGTH <= COUNT;
T_TYPE <= "1000"; --SC
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --arbeitet
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_07; --Zustandsübergang
else
if (TELEGRAM_STOP = '1')
then
--TC15
n_COUNT <= COUNT; --Zaehler bleibt gleich
T_END <= '0'; --Telgeram Ende
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '1'; --Unbekanntes BYTE
n_SV <= ST_TC_06; --Zustandsübergang
else
--TC00
n_COUNT <= x"00";
T_END <= '0';
T_LENGTH <= x"00";
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_00;
end if; --TELEGRAM_STOP
end if; --BYTE_IN =x"E5"
end if; --BYTE_IN = x"DC"
end if; --BYTE_IN = x"A2"
end if; --BYTE_IN = x"68"
end if; --BYTE_IN = x"10"
else ----PARITY_OK = '0'
--TC17
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '1'; --Paritaets Fehler
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_08; --Zustandsuebergang
end if; --PARITY_OK = '1'
else --BYTE_CMPLT = '0'
--TC01
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_01;
end if; --BYTE_CMPLT = '1'
when ST_TC_02 =>
if (BYTE_CMPLT = '1')
then
if (PARITY_OK = '1')
then
if (COUNT = x"06")
then
if (BYTE_IN = x"16")
then
--TC04
n_COUNT <= COUNT;
T_END <= '1'; --Telegrammende erkannt
T_LENGTH <= COUNT;
T_TYPE <= "0001"; --SD1
SEND_OUT <= '1';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --arbeitet
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_07; --Zustandsuebergang
else
--TC18
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '1'; --kein Enddelimiter
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_10; --Zustandsuebergang
end if; --BYTE_IN = x"16"
else --not COUNT = x"06"
--TC02
n_COUNT <= COUNT+1;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0001"; --SD1
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --arbeitet
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_02;
end if; --COUNT = x"06"
else --PARITY_OK = '0'
--TC17
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '1'; --Paritaets Fehler
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_08; --Zustandsuebergang
end if; --PARITY_OK = '1'
else --BYTE_CMPLT = '0'
--TC03
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0001"; --SD1
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_02;
end if; --BYTE_CMPLT = '1'
when ST_TC_03 =>
if (BYTE_CMPLT = '1')
then
if (PARITY_OK = '1')
then
if (BYTE_IN = x"16")
then
--TC07
n_COUNT <= COUNT;
T_END <= '1'; --Telegrammende erkannt
T_LENGTH <= COUNT;
T_TYPE <= "0010"; --SD2
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_07; --Zustandsuebergang
else
if (COUNT = x"FF") --255
then
--TC18
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '1'; --kein Enddelimiter
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_10; --Zustandsuebergang
else --not COUNT = x"FF"
--TC05
n_COUNT <= COUNT+1;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0010"; --SD2
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_03;
end if; --COUNT = x"FF"
end if; --BYTE_IN = x"16"
else --PARITY_OK = '0'
--TC17
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '1'; --Paritaets Fehler
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_08; --Zustandsuebergang
end if; --PARITY_OK = '1'
else --BYTE_CMPLT = '0'
--TC06
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0010"; --SD2
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_03;
end if; --BYTE_CMPLT = '1'
when ST_TC_04 =>
if (BYTE_CMPLT = '1')
then
if (PARITY_OK = '1')
then
if (COUNT = x"0E") --14
then
if (BYTE_IN = x"16")
then
--TC10
n_COUNT <= COUNT;
T_END <= '1'; --Telegrammende erkannt
T_LENGTH <= COUNT;
T_TYPE <= "0011"; --SD3
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_07; --Zustandsuebergang
else --not BYTE_IN = x"16"
--TC18
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '1'; --kein Enddelimiter
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_10; --Zustandsuebergang
end if; --BYTE_IN = x"16"
else --not COUNT = x"0E"
--TC08
n_COUNT <= COUNT+1;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0011"; --SD3
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_04;
end if; --COUNT = x"0E"
else --PARITY_OK = '0'
--TC17
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '1'; --Paritaets Fehler
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_08; --Zustandsuebergang
end if; --PARITY_OK = '1'
else --BYTE_CMPLT = '0'
--TC09
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0011"; --SD3
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_04;
end if; --BYTE_CMPLT = '1'
when ST_TC_05 =>
if (BYTE_CMPLT = '1')
then
if (PARITY_OK = '1')
then
if (COUNT = x"03")
then
--TC13
n_COUNT <= COUNT;
T_END <= '1'; --Telegrammende erkannt
T_LENGTH <= COUNT;
T_TYPE <= "0100"; --SD4
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_07; --Zustandsuebergang
else --not COUNT = x"03"
--TC11
n_COUNT <= COUNT+1;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0100"; --SD4
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_05;
end if; --COUNT = x"03"
else --PARITY_OK = '0'
--TC17
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '1'; --Paritaets Fehler
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_08; --Zustandsuebergang
end if; --PARITY_OK = '1'
else --BYTE_CMPLT = '0'
--TC12
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0100"; --SD4
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_05;
end if; --BYTE_CMPLT = '1'
when ST_TC_06 =>
if (TELEGRAM_STOP = '1')
then
--TC15
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '1'; --Kein bekanntes Startdelimiter-Byte gefunden
n_SV <= ST_TC_06;
else
--TC00
n_COUNT <= x"00";
T_END <= '0';
T_LENGTH <= x"00";
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_00; --Zustandsuebergang
end if;
when ST_TC_07 =>
if (TELEGRAM_STOP = '1')
then
--TC16
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '1'; --Bekanntes Telegramm gefunden
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_07;
else
--TC00
n_COUNT <= x"00";
T_END <= '0';
T_LENGTH <= x"00";
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_00; --Zustandsuebergang
end if;
when ST_TC_08 =>
if (ERROR_CTRL = '1')
then
--TC17
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '1'; --Paritaetsfehler festgestellt
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_09; --Zustandsuebergang
else
--TC17
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '1'; --Paritaetsfehler festgestellt
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_08;
end if;
when ST_TC_09 =>
if (ERROR_CTRL = '1')
then
--TC17
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '1'; --Paritaetsfehler festgestellt
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_09;
else
-- TC00
n_COUNT <= x"00";
T_END <= '0';
T_LENGTH <= x"00";
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_00; --Zustandsuebergang
end if;
when ST_TC_10 =>
if (ERROR_CTRL = '1')
then
--TC18
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '1'; --Fehlendes Enddelimiter festgestellt
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_11; --Zustandsuebergang
else
--TC18
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '1'; --Fehlendes Enddelimiter festgestellt
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_10;
end if;
when ST_TC_11 =>
if (ERROR_CTRL = '1')
then
--TC18
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '1'; --Fehlendes Enddelimiter festgestellt
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_11;
else
-- TC00
n_COUNT <= x"00";
T_END <= '0';
T_LENGTH <= x"00";
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_00; --Zustandsuebergang
end if;
when others =>
-- TC00
n_COUNT <= x"00";
T_END <= '0';
T_LENGTH <= x"00";
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_00;
end case;
end process;
STATE_DISPL_PROC: process (SV, n_SV, STATE_SV, STATE_n_SV, DISPL_COUNT, COUNT) -- Zustandsanzeige
begin
STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
DISPL1_SV(0) <= STATE_SV(0); --Bit0
DISPL1_SV(1) <= STATE_SV(1); --Bit1
DISPL1_SV(2) <= STATE_SV(2); --Bit2
DISPL1_SV(3) <= STATE_SV(3); --Bit3
DISPL2_SV(0) <= STATE_SV(4); --usw.
DISPL2_SV(1) <= STATE_SV(5);
DISPL2_SV(2) <= STATE_SV(6);
DISPL2_SV(3) <= STATE_SV(7);
if (DISPL_COUNT = '1')
then
-- Zaehler anzeigen
DISPL1_n_SV(0) <= COUNT(0);
DISPL1_n_SV(1) <= COUNT(1);
DISPL1_n_SV(2) <= COUNT(2);
DISPL1_n_SV(3) <= COUNT(3);
DISPL2_n_SV(0) <= COUNT(4);
DISPL2_n_SV(1) <= COUNT(5);
DISPL2_n_SV(2) <= COUNT(6);
DISPL2_n_SV(3) <= COUNT(7);
else
--Folgezustand anzeigen
DISPL1_n_SV(0) <= STATE_n_SV(0);
DISPL1_n_SV(1) <= STATE_n_SV(1);
DISPL1_n_SV(2) <= STATE_n_SV(2);
DISPL1_n_SV(3) <= STATE_n_SV(3);
DISPL2_n_SV(0) <= STATE_n_SV(4);
DISPL2_n_SV(1) <= STATE_n_SV(5);
DISPL2_n_SV(2) <= STATE_n_SV(6);
DISPL2_n_SV(3) <= STATE_n_SV(7);
end if;
end process;
end Behavioral;
|
-- CTRL_TELEGRAM_CHECK
-- Profibus Telegramtyp ermitteln, aktuelle Laenge und Telegram komplett anzeigen
-- Projekt: PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 02.01.2013
-- Bearbeiter: mharndt
-- Geaendert: 28.01.2013
-- Umstellung auf: rising_edge(CLK) und falling_edge(CLK) und http://www.sigasi.com/content/clock-edge-detection
-- Optimierungen aus: http://www.lothar-miller.de/s9y/categories/37-FSM
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_TELEGRAM_CHECK is
Port (TELEGRAM_RUN : in std_logic; --Eingangsvariable, Naechstes Telegram
BYTE_IN : in std_logic_vector (7 downto 0); --Eingangsvariable, Byte, 8bit
PARITY_OK : in std_logic; --Eingangsvariable, Paritaet i.O.
BYTE_CMPLT : in std_logic; --Eingangsvariable, BYTE komplett empfangen
PAUSE_END : in std_logic; --Eingangsvariable, Pause erkannt und beendet
TELEGRAM_STOP : in std_logic; --Eingangsvariable, nach Telegramm stoppen
ERROR_CTRL : in std_logic; --Eingangsvariable, Fehlerkontrolle
T_END : out std_logic; --Ausgangsvariable, Telegramm zu Ende
T_LENGTH : out std_logic_vector (7 downto 0); --Ausgangsvariable, Telegramlaenge, 8bit
T_TYPE : out std_logic_vector (3 downto 0); --Ausgangsvariable, Telegramtyp, 4bit
SEND_OUT : out std_logic; --Ausgangsvariable, Senden
PARITY_FAIL : out std_logic; --Ausgangsvariable, Paritaetsprüfung fehlerhaft
NO_ED : out std_logic; --Ausgangsvariable, kein Enddelimiter festgestellt
WORKING : out std_logic; --Ausgangsvariable, TELEGRAM_CHECK arbeitet
KNOWN_T : out std_logic; --Ausgangsvariable, Telegramm erkannt
UNKNOWN_BYTE : out std_logic; --Ausgangsvariable, BYTE nicht erkannt
CLK : in std_logic; --Taktvariable
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
DISPL_COUNT : in std_logic; --Eingangsvariable, Zähler anzeigen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0)); --Folgezustand Zahl2, binärzahl
end CTRL_TELEGRAM_CHECK;
architecture Behavioral of CTRL_TELEGRAM_CHECK is
type TYPE_STATE is
(ST_TC_00, --Zustaende TELEGRAM_CHECK
ST_TC_01,
ST_TC_02,
ST_TC_03,
ST_TC_04,
ST_TC_05,
ST_TC_06,
ST_TC_07,
ST_TC_08,
ST_TC_09,
ST_TC_10,
ST_TC_11);
signal SV : TYPE_STATE := ST_TC_00; --Zustandsvariable
signal n_SV: TYPE_STATE := ST_TC_00; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE := ST_TC_00; --Zustandsvariable, Ausgang Master
signal COUNT : std_logic_vector (7 downto 0) := x"00"; -- Vektor, Telegrammlaenge, 8bit
signal n_COUNT : std_logic_vector (7 downto 0) := x"00"; -- Vektor, Telegrammlaenge, 8bit, neuer Wert
signal COUNT_M : std_logic_vector (7 downto 0) := x"00"; -- Vektor, Telegrammlaenge, 8bit, Ausgang Master
signal STATE_SV : std_logic_vector (7 downto 0) := x"00"; -- aktueller Zustand in 8 Bit, binär
signal STATE_n_SV : std_logic_vector (7 downto 0) := x"00"; -- Folgezustand in 8 Bit, binär
begin
SREG_M_PROC: process (RESET, n_SV, n_COUNT, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_TC_00;
COUNT_M <= x"00";
else
if rising_edge(CLK)
then
if (IN_NEXT_STATE = '1')
then
SV_M <= n_SV;
COUNT_M <= n_COUNT;
else
SV_M <= SV_M;
COUNT_M <= COUNT_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, CLK) --Slave
begin
if (RESET = '1')
then
SV <= ST_TC_00;
COUNT <= x"00";
else
if falling_edge(CLK)
then
SV <= SV_M;
COUNT <= COUNT_M;
end if;
end if;
end process;
TELEGRAM_CHECK_PROC: process (SV, COUNT, TELEGRAM_RUN, PAUSE_END, BYTE_CMPLT, PARITY_OK, BYTE_IN, TELEGRAM_STOP, ERROR_CTRL) --Telegramme erkennen und Ende Telegram erkennen und ausgeben
begin
case SV is
when ST_TC_00 =>
if (TELEGRAM_RUN = '1')
then
if (PAUSE_END = '1')
then
--TC01
n_COUNT <= COUNT; --Zaehler erhöhen
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --arbeitet
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_01; --Zustandsübergang
else
--TC00
n_COUNT <= x"00";
T_END <= '0';
T_LENGTH <= x"00";
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_00;
end if;
else --TELEGRAM_RUN = '0'
-- TC00
n_COUNT <= x"00";
T_END <= '0';
T_LENGTH <= x"00";
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_00;
end if;
when ST_TC_01 =>
if (BYTE_CMPLT = '1')
then
if (PARITY_OK = '1')
then
if (BYTE_IN = x"10") --SD1 erkannt
then
--TC02
n_COUNT <= COUNT+1; --Zaehler erhöhen
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0001"; --SD1
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --arbeitet
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_02; --Zustandsübergang
else
if (BYTE_IN = x"68") --SD2 erkannt
then
--TC05
n_COUNT <= COUNT+1; --Zaehler erhöhen
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0010"; --SD2
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --arbeitet
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_03; --Zustandsübergang
else
if (BYTE_IN = x"A2") --SD3 erkannt
then
--TC08
n_COUNT <= COUNT+1; --Zaehler erhöhen
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0011"; --SD3
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --arbeitet
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_04; --Zustandsübergang
else
if (BYTE_IN = x"DC") --SD4 erkannt
then
--TC11
n_COUNT <= COUNT+1; --Zaehler erhöhen
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0100"; --SD4
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --arbeitet
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_05; --Zustandsübergang
else
if (BYTE_IN = x"E5") --SC erkannt
then
--TC14
n_COUNT <= COUNT+1; --Zaehler erhöhen
T_END <= '1'; --Telgeram Ende
T_LENGTH <= COUNT;
T_TYPE <= "1000"; --SC
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --arbeitet
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_07; --Zustandsübergang
else
if (TELEGRAM_STOP = '1')
then
--TC15
n_COUNT <= COUNT; --Zaehler bleibt gleich
T_END <= '0'; --Telgeram Ende
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '1'; --Unbekanntes BYTE
n_SV <= ST_TC_06; --Zustandsübergang
else
--TC00
n_COUNT <= x"00";
T_END <= '0';
T_LENGTH <= x"00";
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_00;
end if; --TELEGRAM_STOP
end if; --BYTE_IN =x"E5"
end if; --BYTE_IN = x"DC"
end if; --BYTE_IN = x"A2"
end if; --BYTE_IN = x"68"
end if; --BYTE_IN = x"10"
else ----PARITY_OK = '0'
--TC17
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '1'; --Paritaets Fehler
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_08; --Zustandsuebergang
end if; --PARITY_OK = '1'
else --BYTE_CMPLT = '0'
--TC01
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_01;
end if; --BYTE_CMPLT = '1'
when ST_TC_02 =>
if (BYTE_CMPLT = '1')
then
if (PARITY_OK = '1')
then
if (COUNT = x"06")
then
if (BYTE_IN = x"16")
then
--TC04
n_COUNT <= COUNT;
T_END <= '1'; --Telegrammende erkannt
T_LENGTH <= COUNT;
T_TYPE <= "0001"; --SD1
SEND_OUT <= '1';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --arbeitet
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_07; --Zustandsuebergang
else
--TC18
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '1'; --kein Enddelimiter
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_10; --Zustandsuebergang
end if; --BYTE_IN = x"16"
else --not COUNT = x"06"
--TC02
n_COUNT <= COUNT+1;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0001"; --SD1
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --arbeitet
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_02;
end if; --COUNT = x"06"
else --PARITY_OK = '0'
--TC17
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '1'; --Paritaets Fehler
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_08; --Zustandsuebergang
end if; --PARITY_OK = '1'
else --BYTE_CMPLT = '0'
--TC03
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0001"; --SD1
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_02;
end if; --BYTE_CMPLT = '1'
when ST_TC_03 =>
if (BYTE_CMPLT = '1')
then
if (PARITY_OK = '1')
then
if (BYTE_IN = x"16")
then
--TC07
n_COUNT <= COUNT;
T_END <= '1'; --Telegrammende erkannt
T_LENGTH <= COUNT;
T_TYPE <= "0010"; --SD2
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_07; --Zustandsuebergang
else
if (COUNT = x"FF") --255
then
--TC18
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '1'; --kein Enddelimiter
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_10; --Zustandsuebergang
else --not COUNT = x"FF"
--TC05
n_COUNT <= COUNT+1;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0010"; --SD2
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_03;
end if; --COUNT = x"FF"
end if; --BYTE_IN = x"16"
else --PARITY_OK = '0'
--TC17
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '1'; --Paritaets Fehler
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_08; --Zustandsuebergang
end if; --PARITY_OK = '1'
else --BYTE_CMPLT = '0'
--TC06
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0010"; --SD2
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_03;
end if; --BYTE_CMPLT = '1'
when ST_TC_04 =>
if (BYTE_CMPLT = '1')
then
if (PARITY_OK = '1')
then
if (COUNT = x"0E") --14
then
if (BYTE_IN = x"16")
then
--TC10
n_COUNT <= COUNT;
T_END <= '1'; --Telegrammende erkannt
T_LENGTH <= COUNT;
T_TYPE <= "0011"; --SD3
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_07; --Zustandsuebergang
else --not BYTE_IN = x"16"
--TC18
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '1'; --kein Enddelimiter
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_10; --Zustandsuebergang
end if; --BYTE_IN = x"16"
else --not COUNT = x"0E"
--TC08
n_COUNT <= COUNT+1;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0011"; --SD3
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_04;
end if; --COUNT = x"0E"
else --PARITY_OK = '0'
--TC17
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '1'; --Paritaets Fehler
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_08; --Zustandsuebergang
end if; --PARITY_OK = '1'
else --BYTE_CMPLT = '0'
--TC09
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0011"; --SD3
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_04;
end if; --BYTE_CMPLT = '1'
when ST_TC_05 =>
if (BYTE_CMPLT = '1')
then
if (PARITY_OK = '1')
then
if (COUNT = x"03")
then
--TC13
n_COUNT <= COUNT;
T_END <= '1'; --Telegrammende erkannt
T_LENGTH <= COUNT;
T_TYPE <= "0100"; --SD4
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_07; --Zustandsuebergang
else --not COUNT = x"03"
--TC11
n_COUNT <= COUNT+1;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0100"; --SD4
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_05;
end if; --COUNT = x"03"
else --PARITY_OK = '0'
--TC17
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '1'; --Paritaets Fehler
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_08; --Zustandsuebergang
end if; --PARITY_OK = '1'
else --BYTE_CMPLT = '0'
--TC12
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0100"; --SD4
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_05;
end if; --BYTE_CMPLT = '1'
when ST_TC_06 =>
if (TELEGRAM_STOP = '1')
then
--TC15
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '1'; --Kein bekanntes Startdelimiter-Byte gefunden
n_SV <= ST_TC_06;
else
--TC00
n_COUNT <= x"00";
T_END <= '0';
T_LENGTH <= x"00";
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_00; --Zustandsuebergang
end if;
when ST_TC_07 =>
if (TELEGRAM_STOP = '1')
then
--TC16
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '1'; --Bekanntes Telegramm gefunden
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_07;
else
--TC00
n_COUNT <= x"00";
T_END <= '0';
T_LENGTH <= x"00";
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_00; --Zustandsuebergang
end if;
when ST_TC_08 =>
if (ERROR_CTRL = '1')
then
--TC17
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '1'; --Paritaetsfehler festgestellt
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_09; --Zustandsuebergang
else
--TC17
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '1'; --Paritaetsfehler festgestellt
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_08;
end if;
when ST_TC_09 =>
if (ERROR_CTRL = '1')
then
--TC17
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '1'; --Paritaetsfehler festgestellt
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_09;
else
-- TC00
n_COUNT <= x"00";
T_END <= '0';
T_LENGTH <= x"00";
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_00; --Zustandsuebergang
end if;
when ST_TC_10 =>
if (ERROR_CTRL = '1')
then
--TC18
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '1'; --Fehlendes Enddelimiter festgestellt
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_11; --Zustandsuebergang
else
--TC18
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '1'; --Fehlendes Enddelimiter festgestellt
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_10;
end if;
when ST_TC_11 =>
if (ERROR_CTRL = '1')
then
--TC18
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '1'; --Fehlendes Enddelimiter festgestellt
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_11;
else
-- TC00
n_COUNT <= x"00";
T_END <= '0';
T_LENGTH <= x"00";
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_00; --Zustandsuebergang
end if;
when others =>
-- TC00
n_COUNT <= x"00";
T_END <= '0';
T_LENGTH <= x"00";
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_00;
end case;
end process;
STATE_DISPL_PROC: process (SV, n_SV, STATE_SV, STATE_n_SV, DISPL_COUNT, COUNT) -- Zustandsanzeige
begin
STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
DISPL1_SV(0) <= STATE_SV(0); --Bit0
DISPL1_SV(1) <= STATE_SV(1); --Bit1
DISPL1_SV(2) <= STATE_SV(2); --Bit2
DISPL1_SV(3) <= STATE_SV(3); --Bit3
DISPL2_SV(0) <= STATE_SV(4); --usw.
DISPL2_SV(1) <= STATE_SV(5);
DISPL2_SV(2) <= STATE_SV(6);
DISPL2_SV(3) <= STATE_SV(7);
if (DISPL_COUNT = '1')
then
-- Zaehler anzeigen
DISPL1_n_SV(0) <= COUNT(0);
DISPL1_n_SV(1) <= COUNT(1);
DISPL1_n_SV(2) <= COUNT(2);
DISPL1_n_SV(3) <= COUNT(3);
DISPL2_n_SV(0) <= COUNT(4);
DISPL2_n_SV(1) <= COUNT(5);
DISPL2_n_SV(2) <= COUNT(6);
DISPL2_n_SV(3) <= COUNT(7);
else
--Folgezustand anzeigen
DISPL1_n_SV(0) <= STATE_n_SV(0);
DISPL1_n_SV(1) <= STATE_n_SV(1);
DISPL1_n_SV(2) <= STATE_n_SV(2);
DISPL1_n_SV(3) <= STATE_n_SV(3);
DISPL2_n_SV(0) <= STATE_n_SV(4);
DISPL2_n_SV(1) <= STATE_n_SV(5);
DISPL2_n_SV(2) <= STATE_n_SV(6);
DISPL2_n_SV(3) <= STATE_n_SV(7);
end if;
end process;
end Behavioral;
|
-- CTRL_TELEGRAM_CHECK
-- Profibus Telegramtyp ermitteln, aktuelle Laenge und Telegram komplett anzeigen
-- Projekt: PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 02.01.2013
-- Bearbeiter: mharndt
-- Geaendert: 28.01.2013
-- Umstellung auf: rising_edge(CLK) und falling_edge(CLK) und http://www.sigasi.com/content/clock-edge-detection
-- Optimierungen aus: http://www.lothar-miller.de/s9y/categories/37-FSM
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_TELEGRAM_CHECK is
Port (TELEGRAM_RUN : in std_logic; --Eingangsvariable, Naechstes Telegram
BYTE_IN : in std_logic_vector (7 downto 0); --Eingangsvariable, Byte, 8bit
PARITY_OK : in std_logic; --Eingangsvariable, Paritaet i.O.
BYTE_CMPLT : in std_logic; --Eingangsvariable, BYTE komplett empfangen
PAUSE_END : in std_logic; --Eingangsvariable, Pause erkannt und beendet
TELEGRAM_STOP : in std_logic; --Eingangsvariable, nach Telegramm stoppen
ERROR_CTRL : in std_logic; --Eingangsvariable, Fehlerkontrolle
T_END : out std_logic; --Ausgangsvariable, Telegramm zu Ende
T_LENGTH : out std_logic_vector (7 downto 0); --Ausgangsvariable, Telegramlaenge, 8bit
T_TYPE : out std_logic_vector (3 downto 0); --Ausgangsvariable, Telegramtyp, 4bit
SEND_OUT : out std_logic; --Ausgangsvariable, Senden
PARITY_FAIL : out std_logic; --Ausgangsvariable, Paritaetsprüfung fehlerhaft
NO_ED : out std_logic; --Ausgangsvariable, kein Enddelimiter festgestellt
WORKING : out std_logic; --Ausgangsvariable, TELEGRAM_CHECK arbeitet
KNOWN_T : out std_logic; --Ausgangsvariable, Telegramm erkannt
UNKNOWN_BYTE : out std_logic; --Ausgangsvariable, BYTE nicht erkannt
CLK : in std_logic; --Taktvariable
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
DISPL_COUNT : in std_logic; --Eingangsvariable, Zähler anzeigen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0)); --Folgezustand Zahl2, binärzahl
end CTRL_TELEGRAM_CHECK;
architecture Behavioral of CTRL_TELEGRAM_CHECK is
type TYPE_STATE is
(ST_TC_00, --Zustaende TELEGRAM_CHECK
ST_TC_01,
ST_TC_02,
ST_TC_03,
ST_TC_04,
ST_TC_05,
ST_TC_06,
ST_TC_07,
ST_TC_08,
ST_TC_09,
ST_TC_10,
ST_TC_11);
signal SV : TYPE_STATE := ST_TC_00; --Zustandsvariable
signal n_SV: TYPE_STATE := ST_TC_00; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE := ST_TC_00; --Zustandsvariable, Ausgang Master
signal COUNT : std_logic_vector (7 downto 0) := x"00"; -- Vektor, Telegrammlaenge, 8bit
signal n_COUNT : std_logic_vector (7 downto 0) := x"00"; -- Vektor, Telegrammlaenge, 8bit, neuer Wert
signal COUNT_M : std_logic_vector (7 downto 0) := x"00"; -- Vektor, Telegrammlaenge, 8bit, Ausgang Master
signal STATE_SV : std_logic_vector (7 downto 0) := x"00"; -- aktueller Zustand in 8 Bit, binär
signal STATE_n_SV : std_logic_vector (7 downto 0) := x"00"; -- Folgezustand in 8 Bit, binär
begin
SREG_M_PROC: process (RESET, n_SV, n_COUNT, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_TC_00;
COUNT_M <= x"00";
else
if rising_edge(CLK)
then
if (IN_NEXT_STATE = '1')
then
SV_M <= n_SV;
COUNT_M <= n_COUNT;
else
SV_M <= SV_M;
COUNT_M <= COUNT_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, CLK) --Slave
begin
if (RESET = '1')
then
SV <= ST_TC_00;
COUNT <= x"00";
else
if falling_edge(CLK)
then
SV <= SV_M;
COUNT <= COUNT_M;
end if;
end if;
end process;
TELEGRAM_CHECK_PROC: process (SV, COUNT, TELEGRAM_RUN, PAUSE_END, BYTE_CMPLT, PARITY_OK, BYTE_IN, TELEGRAM_STOP, ERROR_CTRL) --Telegramme erkennen und Ende Telegram erkennen und ausgeben
begin
case SV is
when ST_TC_00 =>
if (TELEGRAM_RUN = '1')
then
if (PAUSE_END = '1')
then
--TC01
n_COUNT <= COUNT; --Zaehler erhöhen
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --arbeitet
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_01; --Zustandsübergang
else
--TC00
n_COUNT <= x"00";
T_END <= '0';
T_LENGTH <= x"00";
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_00;
end if;
else --TELEGRAM_RUN = '0'
-- TC00
n_COUNT <= x"00";
T_END <= '0';
T_LENGTH <= x"00";
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_00;
end if;
when ST_TC_01 =>
if (BYTE_CMPLT = '1')
then
if (PARITY_OK = '1')
then
if (BYTE_IN = x"10") --SD1 erkannt
then
--TC02
n_COUNT <= COUNT+1; --Zaehler erhöhen
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0001"; --SD1
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --arbeitet
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_02; --Zustandsübergang
else
if (BYTE_IN = x"68") --SD2 erkannt
then
--TC05
n_COUNT <= COUNT+1; --Zaehler erhöhen
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0010"; --SD2
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --arbeitet
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_03; --Zustandsübergang
else
if (BYTE_IN = x"A2") --SD3 erkannt
then
--TC08
n_COUNT <= COUNT+1; --Zaehler erhöhen
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0011"; --SD3
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --arbeitet
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_04; --Zustandsübergang
else
if (BYTE_IN = x"DC") --SD4 erkannt
then
--TC11
n_COUNT <= COUNT+1; --Zaehler erhöhen
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0100"; --SD4
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --arbeitet
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_05; --Zustandsübergang
else
if (BYTE_IN = x"E5") --SC erkannt
then
--TC14
n_COUNT <= COUNT+1; --Zaehler erhöhen
T_END <= '1'; --Telgeram Ende
T_LENGTH <= COUNT;
T_TYPE <= "1000"; --SC
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --arbeitet
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_07; --Zustandsübergang
else
if (TELEGRAM_STOP = '1')
then
--TC15
n_COUNT <= COUNT; --Zaehler bleibt gleich
T_END <= '0'; --Telgeram Ende
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '1'; --Unbekanntes BYTE
n_SV <= ST_TC_06; --Zustandsübergang
else
--TC00
n_COUNT <= x"00";
T_END <= '0';
T_LENGTH <= x"00";
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_00;
end if; --TELEGRAM_STOP
end if; --BYTE_IN =x"E5"
end if; --BYTE_IN = x"DC"
end if; --BYTE_IN = x"A2"
end if; --BYTE_IN = x"68"
end if; --BYTE_IN = x"10"
else ----PARITY_OK = '0'
--TC17
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '1'; --Paritaets Fehler
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_08; --Zustandsuebergang
end if; --PARITY_OK = '1'
else --BYTE_CMPLT = '0'
--TC01
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_01;
end if; --BYTE_CMPLT = '1'
when ST_TC_02 =>
if (BYTE_CMPLT = '1')
then
if (PARITY_OK = '1')
then
if (COUNT = x"06")
then
if (BYTE_IN = x"16")
then
--TC04
n_COUNT <= COUNT;
T_END <= '1'; --Telegrammende erkannt
T_LENGTH <= COUNT;
T_TYPE <= "0001"; --SD1
SEND_OUT <= '1';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --arbeitet
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_07; --Zustandsuebergang
else
--TC18
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '1'; --kein Enddelimiter
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_10; --Zustandsuebergang
end if; --BYTE_IN = x"16"
else --not COUNT = x"06"
--TC02
n_COUNT <= COUNT+1;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0001"; --SD1
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --arbeitet
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_02;
end if; --COUNT = x"06"
else --PARITY_OK = '0'
--TC17
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '1'; --Paritaets Fehler
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_08; --Zustandsuebergang
end if; --PARITY_OK = '1'
else --BYTE_CMPLT = '0'
--TC03
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0001"; --SD1
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_02;
end if; --BYTE_CMPLT = '1'
when ST_TC_03 =>
if (BYTE_CMPLT = '1')
then
if (PARITY_OK = '1')
then
if (BYTE_IN = x"16")
then
--TC07
n_COUNT <= COUNT;
T_END <= '1'; --Telegrammende erkannt
T_LENGTH <= COUNT;
T_TYPE <= "0010"; --SD2
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_07; --Zustandsuebergang
else
if (COUNT = x"FF") --255
then
--TC18
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '1'; --kein Enddelimiter
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_10; --Zustandsuebergang
else --not COUNT = x"FF"
--TC05
n_COUNT <= COUNT+1;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0010"; --SD2
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_03;
end if; --COUNT = x"FF"
end if; --BYTE_IN = x"16"
else --PARITY_OK = '0'
--TC17
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '1'; --Paritaets Fehler
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_08; --Zustandsuebergang
end if; --PARITY_OK = '1'
else --BYTE_CMPLT = '0'
--TC06
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0010"; --SD2
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_03;
end if; --BYTE_CMPLT = '1'
when ST_TC_04 =>
if (BYTE_CMPLT = '1')
then
if (PARITY_OK = '1')
then
if (COUNT = x"0E") --14
then
if (BYTE_IN = x"16")
then
--TC10
n_COUNT <= COUNT;
T_END <= '1'; --Telegrammende erkannt
T_LENGTH <= COUNT;
T_TYPE <= "0011"; --SD3
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_07; --Zustandsuebergang
else --not BYTE_IN = x"16"
--TC18
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '1'; --kein Enddelimiter
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_10; --Zustandsuebergang
end if; --BYTE_IN = x"16"
else --not COUNT = x"0E"
--TC08
n_COUNT <= COUNT+1;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0011"; --SD3
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_04;
end if; --COUNT = x"0E"
else --PARITY_OK = '0'
--TC17
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '1'; --Paritaets Fehler
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_08; --Zustandsuebergang
end if; --PARITY_OK = '1'
else --BYTE_CMPLT = '0'
--TC09
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0011"; --SD3
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_04;
end if; --BYTE_CMPLT = '1'
when ST_TC_05 =>
if (BYTE_CMPLT = '1')
then
if (PARITY_OK = '1')
then
if (COUNT = x"03")
then
--TC13
n_COUNT <= COUNT;
T_END <= '1'; --Telegrammende erkannt
T_LENGTH <= COUNT;
T_TYPE <= "0100"; --SD4
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_07; --Zustandsuebergang
else --not COUNT = x"03"
--TC11
n_COUNT <= COUNT+1;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0100"; --SD4
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_05;
end if; --COUNT = x"03"
else --PARITY_OK = '0'
--TC17
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '1'; --Paritaets Fehler
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_08; --Zustandsuebergang
end if; --PARITY_OK = '1'
else --BYTE_CMPLT = '0'
--TC12
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0100"; --SD4
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_05;
end if; --BYTE_CMPLT = '1'
when ST_TC_06 =>
if (TELEGRAM_STOP = '1')
then
--TC15
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '1'; --Kein bekanntes Startdelimiter-Byte gefunden
n_SV <= ST_TC_06;
else
--TC00
n_COUNT <= x"00";
T_END <= '0';
T_LENGTH <= x"00";
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_00; --Zustandsuebergang
end if;
when ST_TC_07 =>
if (TELEGRAM_STOP = '1')
then
--TC16
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '1'; --Bekanntes Telegramm gefunden
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_07;
else
--TC00
n_COUNT <= x"00";
T_END <= '0';
T_LENGTH <= x"00";
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_00; --Zustandsuebergang
end if;
when ST_TC_08 =>
if (ERROR_CTRL = '1')
then
--TC17
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '1'; --Paritaetsfehler festgestellt
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_09; --Zustandsuebergang
else
--TC17
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '1'; --Paritaetsfehler festgestellt
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_08;
end if;
when ST_TC_09 =>
if (ERROR_CTRL = '1')
then
--TC17
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '1'; --Paritaetsfehler festgestellt
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_09;
else
-- TC00
n_COUNT <= x"00";
T_END <= '0';
T_LENGTH <= x"00";
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_00; --Zustandsuebergang
end if;
when ST_TC_10 =>
if (ERROR_CTRL = '1')
then
--TC18
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '1'; --Fehlendes Enddelimiter festgestellt
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_11; --Zustandsuebergang
else
--TC18
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '1'; --Fehlendes Enddelimiter festgestellt
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_10;
end if;
when ST_TC_11 =>
if (ERROR_CTRL = '1')
then
--TC18
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '1'; --Fehlendes Enddelimiter festgestellt
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_11;
else
-- TC00
n_COUNT <= x"00";
T_END <= '0';
T_LENGTH <= x"00";
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_00; --Zustandsuebergang
end if;
when others =>
-- TC00
n_COUNT <= x"00";
T_END <= '0';
T_LENGTH <= x"00";
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_00;
end case;
end process;
STATE_DISPL_PROC: process (SV, n_SV, STATE_SV, STATE_n_SV, DISPL_COUNT, COUNT) -- Zustandsanzeige
begin
STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
DISPL1_SV(0) <= STATE_SV(0); --Bit0
DISPL1_SV(1) <= STATE_SV(1); --Bit1
DISPL1_SV(2) <= STATE_SV(2); --Bit2
DISPL1_SV(3) <= STATE_SV(3); --Bit3
DISPL2_SV(0) <= STATE_SV(4); --usw.
DISPL2_SV(1) <= STATE_SV(5);
DISPL2_SV(2) <= STATE_SV(6);
DISPL2_SV(3) <= STATE_SV(7);
if (DISPL_COUNT = '1')
then
-- Zaehler anzeigen
DISPL1_n_SV(0) <= COUNT(0);
DISPL1_n_SV(1) <= COUNT(1);
DISPL1_n_SV(2) <= COUNT(2);
DISPL1_n_SV(3) <= COUNT(3);
DISPL2_n_SV(0) <= COUNT(4);
DISPL2_n_SV(1) <= COUNT(5);
DISPL2_n_SV(2) <= COUNT(6);
DISPL2_n_SV(3) <= COUNT(7);
else
--Folgezustand anzeigen
DISPL1_n_SV(0) <= STATE_n_SV(0);
DISPL1_n_SV(1) <= STATE_n_SV(1);
DISPL1_n_SV(2) <= STATE_n_SV(2);
DISPL1_n_SV(3) <= STATE_n_SV(3);
DISPL2_n_SV(0) <= STATE_n_SV(4);
DISPL2_n_SV(1) <= STATE_n_SV(5);
DISPL2_n_SV(2) <= STATE_n_SV(6);
DISPL2_n_SV(3) <= STATE_n_SV(7);
end if;
end process;
end Behavioral;
|
-- CTRL_TELEGRAM_CHECK
-- Profibus Telegramtyp ermitteln, aktuelle Laenge und Telegram komplett anzeigen
-- Projekt: PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 02.01.2013
-- Bearbeiter: mharndt
-- Geaendert: 28.01.2013
-- Umstellung auf: rising_edge(CLK) und falling_edge(CLK) und http://www.sigasi.com/content/clock-edge-detection
-- Optimierungen aus: http://www.lothar-miller.de/s9y/categories/37-FSM
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_TELEGRAM_CHECK is
Port (TELEGRAM_RUN : in std_logic; --Eingangsvariable, Naechstes Telegram
BYTE_IN : in std_logic_vector (7 downto 0); --Eingangsvariable, Byte, 8bit
PARITY_OK : in std_logic; --Eingangsvariable, Paritaet i.O.
BYTE_CMPLT : in std_logic; --Eingangsvariable, BYTE komplett empfangen
PAUSE_END : in std_logic; --Eingangsvariable, Pause erkannt und beendet
TELEGRAM_STOP : in std_logic; --Eingangsvariable, nach Telegramm stoppen
ERROR_CTRL : in std_logic; --Eingangsvariable, Fehlerkontrolle
T_END : out std_logic; --Ausgangsvariable, Telegramm zu Ende
T_LENGTH : out std_logic_vector (7 downto 0); --Ausgangsvariable, Telegramlaenge, 8bit
T_TYPE : out std_logic_vector (3 downto 0); --Ausgangsvariable, Telegramtyp, 4bit
SEND_OUT : out std_logic; --Ausgangsvariable, Senden
PARITY_FAIL : out std_logic; --Ausgangsvariable, Paritaetsprüfung fehlerhaft
NO_ED : out std_logic; --Ausgangsvariable, kein Enddelimiter festgestellt
WORKING : out std_logic; --Ausgangsvariable, TELEGRAM_CHECK arbeitet
KNOWN_T : out std_logic; --Ausgangsvariable, Telegramm erkannt
UNKNOWN_BYTE : out std_logic; --Ausgangsvariable, BYTE nicht erkannt
CLK : in std_logic; --Taktvariable
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
DISPL_COUNT : in std_logic; --Eingangsvariable, Zähler anzeigen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0)); --Folgezustand Zahl2, binärzahl
end CTRL_TELEGRAM_CHECK;
architecture Behavioral of CTRL_TELEGRAM_CHECK is
type TYPE_STATE is
(ST_TC_00, --Zustaende TELEGRAM_CHECK
ST_TC_01,
ST_TC_02,
ST_TC_03,
ST_TC_04,
ST_TC_05,
ST_TC_06,
ST_TC_07,
ST_TC_08,
ST_TC_09,
ST_TC_10,
ST_TC_11);
signal SV : TYPE_STATE := ST_TC_00; --Zustandsvariable
signal n_SV: TYPE_STATE := ST_TC_00; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE := ST_TC_00; --Zustandsvariable, Ausgang Master
signal COUNT : std_logic_vector (7 downto 0) := x"00"; -- Vektor, Telegrammlaenge, 8bit
signal n_COUNT : std_logic_vector (7 downto 0) := x"00"; -- Vektor, Telegrammlaenge, 8bit, neuer Wert
signal COUNT_M : std_logic_vector (7 downto 0) := x"00"; -- Vektor, Telegrammlaenge, 8bit, Ausgang Master
signal STATE_SV : std_logic_vector (7 downto 0) := x"00"; -- aktueller Zustand in 8 Bit, binär
signal STATE_n_SV : std_logic_vector (7 downto 0) := x"00"; -- Folgezustand in 8 Bit, binär
begin
SREG_M_PROC: process (RESET, n_SV, n_COUNT, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_TC_00;
COUNT_M <= x"00";
else
if rising_edge(CLK)
then
if (IN_NEXT_STATE = '1')
then
SV_M <= n_SV;
COUNT_M <= n_COUNT;
else
SV_M <= SV_M;
COUNT_M <= COUNT_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, CLK) --Slave
begin
if (RESET = '1')
then
SV <= ST_TC_00;
COUNT <= x"00";
else
if falling_edge(CLK)
then
SV <= SV_M;
COUNT <= COUNT_M;
end if;
end if;
end process;
TELEGRAM_CHECK_PROC: process (SV, COUNT, TELEGRAM_RUN, PAUSE_END, BYTE_CMPLT, PARITY_OK, BYTE_IN, TELEGRAM_STOP, ERROR_CTRL) --Telegramme erkennen und Ende Telegram erkennen und ausgeben
begin
case SV is
when ST_TC_00 =>
if (TELEGRAM_RUN = '1')
then
if (PAUSE_END = '1')
then
--TC01
n_COUNT <= COUNT; --Zaehler erhöhen
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --arbeitet
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_01; --Zustandsübergang
else
--TC00
n_COUNT <= x"00";
T_END <= '0';
T_LENGTH <= x"00";
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_00;
end if;
else --TELEGRAM_RUN = '0'
-- TC00
n_COUNT <= x"00";
T_END <= '0';
T_LENGTH <= x"00";
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_00;
end if;
when ST_TC_01 =>
if (BYTE_CMPLT = '1')
then
if (PARITY_OK = '1')
then
if (BYTE_IN = x"10") --SD1 erkannt
then
--TC02
n_COUNT <= COUNT+1; --Zaehler erhöhen
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0001"; --SD1
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --arbeitet
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_02; --Zustandsübergang
else
if (BYTE_IN = x"68") --SD2 erkannt
then
--TC05
n_COUNT <= COUNT+1; --Zaehler erhöhen
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0010"; --SD2
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --arbeitet
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_03; --Zustandsübergang
else
if (BYTE_IN = x"A2") --SD3 erkannt
then
--TC08
n_COUNT <= COUNT+1; --Zaehler erhöhen
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0011"; --SD3
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --arbeitet
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_04; --Zustandsübergang
else
if (BYTE_IN = x"DC") --SD4 erkannt
then
--TC11
n_COUNT <= COUNT+1; --Zaehler erhöhen
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0100"; --SD4
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --arbeitet
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_05; --Zustandsübergang
else
if (BYTE_IN = x"E5") --SC erkannt
then
--TC14
n_COUNT <= COUNT+1; --Zaehler erhöhen
T_END <= '1'; --Telgeram Ende
T_LENGTH <= COUNT;
T_TYPE <= "1000"; --SC
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --arbeitet
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_07; --Zustandsübergang
else
if (TELEGRAM_STOP = '1')
then
--TC15
n_COUNT <= COUNT; --Zaehler bleibt gleich
T_END <= '0'; --Telgeram Ende
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '1'; --Unbekanntes BYTE
n_SV <= ST_TC_06; --Zustandsübergang
else
--TC00
n_COUNT <= x"00";
T_END <= '0';
T_LENGTH <= x"00";
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_00;
end if; --TELEGRAM_STOP
end if; --BYTE_IN =x"E5"
end if; --BYTE_IN = x"DC"
end if; --BYTE_IN = x"A2"
end if; --BYTE_IN = x"68"
end if; --BYTE_IN = x"10"
else ----PARITY_OK = '0'
--TC17
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '1'; --Paritaets Fehler
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_08; --Zustandsuebergang
end if; --PARITY_OK = '1'
else --BYTE_CMPLT = '0'
--TC01
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_01;
end if; --BYTE_CMPLT = '1'
when ST_TC_02 =>
if (BYTE_CMPLT = '1')
then
if (PARITY_OK = '1')
then
if (COUNT = x"06")
then
if (BYTE_IN = x"16")
then
--TC04
n_COUNT <= COUNT;
T_END <= '1'; --Telegrammende erkannt
T_LENGTH <= COUNT;
T_TYPE <= "0001"; --SD1
SEND_OUT <= '1';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --arbeitet
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_07; --Zustandsuebergang
else
--TC18
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '1'; --kein Enddelimiter
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_10; --Zustandsuebergang
end if; --BYTE_IN = x"16"
else --not COUNT = x"06"
--TC02
n_COUNT <= COUNT+1;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0001"; --SD1
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --arbeitet
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_02;
end if; --COUNT = x"06"
else --PARITY_OK = '0'
--TC17
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '1'; --Paritaets Fehler
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_08; --Zustandsuebergang
end if; --PARITY_OK = '1'
else --BYTE_CMPLT = '0'
--TC03
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0001"; --SD1
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_02;
end if; --BYTE_CMPLT = '1'
when ST_TC_03 =>
if (BYTE_CMPLT = '1')
then
if (PARITY_OK = '1')
then
if (BYTE_IN = x"16")
then
--TC07
n_COUNT <= COUNT;
T_END <= '1'; --Telegrammende erkannt
T_LENGTH <= COUNT;
T_TYPE <= "0010"; --SD2
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_07; --Zustandsuebergang
else
if (COUNT = x"FF") --255
then
--TC18
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '1'; --kein Enddelimiter
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_10; --Zustandsuebergang
else --not COUNT = x"FF"
--TC05
n_COUNT <= COUNT+1;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0010"; --SD2
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_03;
end if; --COUNT = x"FF"
end if; --BYTE_IN = x"16"
else --PARITY_OK = '0'
--TC17
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '1'; --Paritaets Fehler
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_08; --Zustandsuebergang
end if; --PARITY_OK = '1'
else --BYTE_CMPLT = '0'
--TC06
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0010"; --SD2
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_03;
end if; --BYTE_CMPLT = '1'
when ST_TC_04 =>
if (BYTE_CMPLT = '1')
then
if (PARITY_OK = '1')
then
if (COUNT = x"0E") --14
then
if (BYTE_IN = x"16")
then
--TC10
n_COUNT <= COUNT;
T_END <= '1'; --Telegrammende erkannt
T_LENGTH <= COUNT;
T_TYPE <= "0011"; --SD3
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_07; --Zustandsuebergang
else --not BYTE_IN = x"16"
--TC18
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '1'; --kein Enddelimiter
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_10; --Zustandsuebergang
end if; --BYTE_IN = x"16"
else --not COUNT = x"0E"
--TC08
n_COUNT <= COUNT+1;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0011"; --SD3
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_04;
end if; --COUNT = x"0E"
else --PARITY_OK = '0'
--TC17
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '1'; --Paritaets Fehler
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_08; --Zustandsuebergang
end if; --PARITY_OK = '1'
else --BYTE_CMPLT = '0'
--TC09
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0011"; --SD3
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_04;
end if; --BYTE_CMPLT = '1'
when ST_TC_05 =>
if (BYTE_CMPLT = '1')
then
if (PARITY_OK = '1')
then
if (COUNT = x"03")
then
--TC13
n_COUNT <= COUNT;
T_END <= '1'; --Telegrammende erkannt
T_LENGTH <= COUNT;
T_TYPE <= "0100"; --SD4
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_07; --Zustandsuebergang
else --not COUNT = x"03"
--TC11
n_COUNT <= COUNT+1;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0100"; --SD4
SEND_OUT <= '1'; --senden
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_05;
end if; --COUNT = x"03"
else --PARITY_OK = '0'
--TC17
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '1'; --Paritaets Fehler
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_08; --Zustandsuebergang
end if; --PARITY_OK = '1'
else --BYTE_CMPLT = '0'
--TC12
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0100"; --SD4
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '1'; --laeuft
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_05;
end if; --BYTE_CMPLT = '1'
when ST_TC_06 =>
if (TELEGRAM_STOP = '1')
then
--TC15
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '1'; --Kein bekanntes Startdelimiter-Byte gefunden
n_SV <= ST_TC_06;
else
--TC00
n_COUNT <= x"00";
T_END <= '0';
T_LENGTH <= x"00";
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_00; --Zustandsuebergang
end if;
when ST_TC_07 =>
if (TELEGRAM_STOP = '1')
then
--TC16
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '1'; --Bekanntes Telegramm gefunden
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_07;
else
--TC00
n_COUNT <= x"00";
T_END <= '0';
T_LENGTH <= x"00";
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_00; --Zustandsuebergang
end if;
when ST_TC_08 =>
if (ERROR_CTRL = '1')
then
--TC17
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '1'; --Paritaetsfehler festgestellt
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_09; --Zustandsuebergang
else
--TC17
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '1'; --Paritaetsfehler festgestellt
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_08;
end if;
when ST_TC_09 =>
if (ERROR_CTRL = '1')
then
--TC17
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '1'; --Paritaetsfehler festgestellt
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_09;
else
-- TC00
n_COUNT <= x"00";
T_END <= '0';
T_LENGTH <= x"00";
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_00; --Zustandsuebergang
end if;
when ST_TC_10 =>
if (ERROR_CTRL = '1')
then
--TC18
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '1'; --Fehlendes Enddelimiter festgestellt
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_11; --Zustandsuebergang
else
--TC18
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '1'; --Fehlendes Enddelimiter festgestellt
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_10;
end if;
when ST_TC_11 =>
if (ERROR_CTRL = '1')
then
--TC18
n_COUNT <= COUNT;
T_END <= '0';
T_LENGTH <= COUNT;
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '1'; --Fehlendes Enddelimiter festgestellt
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_11;
else
-- TC00
n_COUNT <= x"00";
T_END <= '0';
T_LENGTH <= x"00";
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_00; --Zustandsuebergang
end if;
when others =>
-- TC00
n_COUNT <= x"00";
T_END <= '0';
T_LENGTH <= x"00";
T_TYPE <= "0000";
SEND_OUT <= '0';
PARITY_FAIL <= '0';
NO_ED <= '0';
WORKING <= '0';
KNOWN_T <= '0';
UNKNOWN_BYTE <= '0';
n_SV <= ST_TC_00;
end case;
end process;
STATE_DISPL_PROC: process (SV, n_SV, STATE_SV, STATE_n_SV, DISPL_COUNT, COUNT) -- Zustandsanzeige
begin
STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
DISPL1_SV(0) <= STATE_SV(0); --Bit0
DISPL1_SV(1) <= STATE_SV(1); --Bit1
DISPL1_SV(2) <= STATE_SV(2); --Bit2
DISPL1_SV(3) <= STATE_SV(3); --Bit3
DISPL2_SV(0) <= STATE_SV(4); --usw.
DISPL2_SV(1) <= STATE_SV(5);
DISPL2_SV(2) <= STATE_SV(6);
DISPL2_SV(3) <= STATE_SV(7);
if (DISPL_COUNT = '1')
then
-- Zaehler anzeigen
DISPL1_n_SV(0) <= COUNT(0);
DISPL1_n_SV(1) <= COUNT(1);
DISPL1_n_SV(2) <= COUNT(2);
DISPL1_n_SV(3) <= COUNT(3);
DISPL2_n_SV(0) <= COUNT(4);
DISPL2_n_SV(1) <= COUNT(5);
DISPL2_n_SV(2) <= COUNT(6);
DISPL2_n_SV(3) <= COUNT(7);
else
--Folgezustand anzeigen
DISPL1_n_SV(0) <= STATE_n_SV(0);
DISPL1_n_SV(1) <= STATE_n_SV(1);
DISPL1_n_SV(2) <= STATE_n_SV(2);
DISPL1_n_SV(3) <= STATE_n_SV(3);
DISPL2_n_SV(0) <= STATE_n_SV(4);
DISPL2_n_SV(1) <= STATE_n_SV(5);
DISPL2_n_SV(2) <= STATE_n_SV(6);
DISPL2_n_SV(3) <= STATE_n_SV(7);
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
--! @project Unrolled (factor 2) hardware implementation of Asconv128128
--! @author Michael Fivez
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is an hardware implementation made for my graduation thesis
--! at the KULeuven, in the COSIC department (year 2015-2016)
--! The thesis is titled 'Energy efficient hardware implementations of CAESAR submissions',
--! and can be found on the COSIC website (www.esat.kuleuven.be/cosic/publications)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity OutputGenerator is
port(
In0 : in std_logic_vector(63 downto 0);
In1 : in std_logic_vector(63 downto 0);
DataIn : in std_logic_vector(127 downto 0);
Size : in std_logic_vector(3 downto 0);
Activate : in std_logic;
Out0 : out std_logic_vector(63 downto 0);
Out1 : out std_logic_vector(63 downto 0);
DataOut : out std_logic_vector(127 downto 0));
end entity OutputGenerator;
architecture structural of OutputGenerator is
constant ALLZERO : std_logic_vector(127 downto 0) := (others => '0');
signal Temp0,Temp1,Temp2 : std_logic_vector(127 downto 0);
begin
Gen: process(In0,In1,DataIn,Size,Activate,Temp0,Temp1,Temp2) is
-- Truncator0&1
procedure doTruncate0 ( -- Truncate block 0 and 1 together
signal Input : in std_logic_vector(127 downto 0);
signal Size : in std_logic_vector(3 downto 0);
signal Activate : in std_logic;
signal Output : out std_logic_vector(127 downto 0)) is
variable ActSize : std_logic_vector(4 downto 0);
begin
ActSize(4) := Activate;
ActSize(3 downto 0) := Size;
-- if inactive it lets everything trough, if active it lets the first blocksize bits trough
logic: case ActSize is
when "10001" =>
Output(127 downto 120) <= Input(127 downto 120);
Output(119) <= '1';
Output(118 downto 0) <= ALLZERO(118 downto 0);
when "10010" =>
Output(127 downto 112) <= Input(127 downto 112);
Output(111) <= '1';
Output(110 downto 0) <= ALLZERO(110 downto 0);
when "10011" =>
Output(127 downto 104) <= Input(127 downto 104);
Output(103) <= '1';
Output(102 downto 0) <= ALLZERO(102 downto 0);
when "10100" =>
Output(127 downto 96) <= Input(127 downto 96);
Output(95) <= '1';
Output(94 downto 0) <= ALLZERO(94 downto 0);
when "10101" =>
Output(127 downto 88) <= Input(127 downto 88);
Output(87) <= '1';
Output(86 downto 0) <= ALLZERO(86 downto 0);
when "10110" =>
Output(127 downto 80) <= Input(127 downto 80);
Output(79) <= '1';
Output(78 downto 0) <= ALLZERO(78 downto 0);
when "10111" =>
Output(127 downto 72) <= Input(127 downto 72);
Output(71) <= '1';
Output(70 downto 0) <= ALLZERO(70 downto 0);
when "11000" =>
Output(127 downto 64) <= Input(127 downto 64);
Output(63) <= '1';
Output(62 downto 0) <= ALLZERO(62 downto 0);
when "11001" =>
Output(127 downto 56) <= Input(127 downto 56);
Output(55) <= '1';
Output(54 downto 0) <= ALLZERO(54 downto 0);
when "11010" =>
Output(127 downto 48) <= Input(127 downto 48);
Output(47) <= '1';
Output(46 downto 0) <= ALLZERO(46 downto 0);
when "11011" =>
Output(127 downto 40) <= Input(127 downto 40);
Output(39) <= '1';
Output(38 downto 0) <= ALLZERO(38 downto 0);
when "11100" =>
Output(127 downto 32) <= Input(127 downto 32);
Output(31) <= '1';
Output(30 downto 0) <= ALLZERO(30 downto 0);
when "11101" =>
Output(127 downto 24) <= Input(127 downto 24);
Output(23) <= '1';
Output(22 downto 0) <= ALLZERO(22 downto 0);
when "11110" =>
Output(127 downto 16) <= Input(127 downto 16);
Output(15) <= '1';
Output(14 downto 0) <= ALLZERO(14 downto 0);
when "11111" =>
Output(127 downto 8) <= Input(127 downto 8);
Output(7) <= '1';
Output(6 downto 0) <= ALLZERO(6 downto 0);
when others => -- deactivate or blocksize max or invalid input (cas 0xxxx or 10000)
Output <= Input;
end case logic;
end procedure doTruncate0;
-- Truncator2
procedure doTruncate2 ( -- Truncate block 0 and 1 together
signal Input : in std_logic_vector(127 downto 0);
signal Size : in std_logic_vector(3 downto 0);
signal Activate : in std_logic;
signal Output : out std_logic_vector(127 downto 0)) is
variable ActSize : std_logic_vector(4 downto 0);
begin
ActSize(4) := Activate;
ActSize(3 downto 0) := Size;
-- if inactive it lets everything trough, if active it blocks the first blocksize bits
logic: case ActSize is
when "10000" =>
Output <= ALLZERO;
when "10001" =>
Output(127 downto 120) <= ALLZERO(127 downto 120);
Output(119 downto 0) <= Input(119 downto 0);
when "10010" =>
Output(127 downto 112) <= ALLZERO(127 downto 112);
Output(111 downto 0) <= Input(111 downto 0);
when "10011" =>
Output(127 downto 104) <= ALLZERO(127 downto 104);
Output(103 downto 0) <= Input(103 downto 0);
when "10100" =>
Output(127 downto 96) <= ALLZERO(127 downto 96);
Output(95 downto 0) <= Input(95 downto 0);
when "10101" =>
Output(127 downto 88) <= ALLZERO(127 downto 88);
Output(87 downto 0) <= Input(87 downto 0);
when "10110" =>
Output(127 downto 80) <= ALLZERO(127 downto 80);
Output(79 downto 0) <= Input(79 downto 0);
when "10111" =>
Output(127 downto 72) <= ALLZERO(127 downto 72);
Output(71 downto 0) <= Input(71 downto 0);
when "11000" =>
Output(127 downto 64) <= ALLZERO(127 downto 64);
Output(63 downto 0) <= Input(63 downto 0);
when "11001" =>
Output(127 downto 56) <= ALLZERO(127 downto 56);
Output(55 downto 0) <= Input(55 downto 0);
when "11010" =>
Output(127 downto 48) <= ALLZERO(127 downto 48);
Output(47 downto 0) <= Input(47 downto 0);
when "11011" =>
Output(127 downto 40) <= ALLZERO(127 downto 40);
Output(39 downto 0) <= Input(39 downto 0);
when "11100" =>
Output(127 downto 32) <= ALLZERO(127 downto 32);
Output(31 downto 0) <= Input(31 downto 0);
when "11101" =>
Output(127 downto 24) <= ALLZERO(127 downto 24);
Output(23 downto 0) <= Input(23 downto 0);
when "11110" =>
Output(127 downto 16) <= ALLZERO(127 downto 16);
Output(15 downto 0) <= Input(15 downto 0);
when "11111" =>
Output(127 downto 8) <= ALLZERO(127 downto 8);
Output(7 downto 0) <= Input(7 downto 0);
when others => -- deactivate or blocksize max or invalid input (cas 0xxxx or 10000)
Output <= Input;
end case logic;
end procedure doTruncate2;
begin
-- DataOut
DataOut(127 downto 64) <= In0 xor DataIn(127 downto 64);
DataOut(63 downto 0) <= In1 xor DataIn(63 downto 0);
-- Stateupdate
doTruncate0(DataIn,Size,Activate,Temp0);
Temp1(127 downto 64) <= In0;
Temp1(63 downto 0) <= In1;
doTruncate2(Temp1,Size,Activate,Temp2);
Out0 <= Temp0(127 downto 64) xor Temp2(127 downto 64);
Out1 <= Temp0(63 downto 0) xor Temp2(63 downto 0);
end process Gen;
end architecture structural;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 13
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0_13;
USE axi_gpio_v2_0_13.axi_gpio;
ENTITY design_1_axi_gpio_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END design_1_axi_gpio_0_0;
ARCHITECTURE design_1_axi_gpio_0_0_arch OF design_1_axi_gpio_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_gpio_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
ATTRIBUTE X_INTERFACE_INFO OF gpio2_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO2 TRI_I";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 4,
C_GPIO2_WIDTH => 4,
C_ALL_INPUTS => 1,
C_ALL_INPUTS_2 => 1,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 1,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
gpio_io_i => gpio_io_i,
gpio2_io_i => gpio2_io_i
);
END design_1_axi_gpio_0_0_arch;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: i2c2ahbx
-- File: i2c2ahbx.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- Contact: [email protected]
-- Description: Simple I2C-slave providing a bridge to AMBA AHB
-- This entity is typically wrapped with i2c2ahb or i2c2ahb_apb
-- before use.
-------------------------------------------------------------------------------
--
-- Short core documentation, for additional information see the GRLIB IP
-- Library User's Manual (GRIP):
--
-- The core functions as a I2C memory device. To write to the core, issue the
-- following I2C bus sequence:
--
-- 0. START condition
-- 1. Send core's I2C address with direction = write
-- 2. Send 32-bit address to be used for AMBA bus
-- 3. Send data to be written
--
-- The core will expect 32-bits of data and write these as a word. This can be
-- changed by writing to the core's control register. See documentation further
-- down. When the core's internal FIFO is full, the core will use clock
-- stretching to stall the transfer.
--
-- To write to the core, issue the following I2C bus sequence:
--
-- 0. START condition
-- 1. Send core's I2C address with direction = write
-- 2. Send 32-bit address to be used for AMBA bus
-- 3. Send repeated start condition
-- 4. Send core's I2C address with direction = read
-- 5. Read bytes
--
-- The core will perform 32-bit data accesses to fill its internal buffer. This
-- can be changed by writing to the core's control register (see documentation
-- further down). When the buffer is empty the core will use clock stretching
-- to stall the transfer.
--
-- The cores control/status register is accessed via address i2caddr + 1. The
-- register has the following layout:
--
-- +--------+-----------------------------------------------------------------+
-- | Bit(s) | Description |
-- +--------+-----------------------------------------------------------------+
-- | 7:6 | Reserved, always zero (RO) |
-- | 5 | PROT: Memory protection triggered. Last access was outside |
-- | | range. Updated after each AMBA access (RO) |
-- | 4 | MEXC: Memory exception. Gets set if core receives AMBA ERROR |
-- | | response. Updated after each AMBA access. (RO) |
-- | 3 | DMAACT: Core is currently performing DMA (RO) |
-- | 2 | NACK: NACK instead of using clock stretching (RW) |
-- | 1:0 | HSIZE: Controls the access size core will use for AMBA accesses |
-- | | Default is HSIZE = WORD. HSIZE 11 is illegal (RW) |
-- +--------+-----------------------------------------------------------------+
--
-- Documentation of generics:
--
-- [hindex] AHB master index
--
-- [oepol] Output enable polarity
--
-- [filter] Length of filters used on SCL and SDA
--
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.i2c.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
entity i2c2ahbx is
generic (
-- AHB configuration
hindex : integer := 0;
oepol : integer range 0 to 1 := 0;
filter : integer range 2 to 512 := 2
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
-- I2C signals
i2ci : in i2c_in_type;
i2co : out i2c_out_type;
--
i2c2ahbi : in i2c2ahb_in_type;
i2c2ahbo : out i2c2ahb_out_type
);
end entity i2c2ahbx;
architecture rtl of i2c2ahbx is
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
constant OEPOL_LEVEL : std_ulogic := conv_std_logic(oepol = 1);
constant I2C_LOW : std_ulogic := OEPOL_LEVEL; -- OE
constant I2C_HIZ : std_ulogic := not OEPOL_LEVEL;
constant I2C_ACK : std_ulogic := '0';
-----------------------------------------------------------------------------
-- Types
-----------------------------------------------------------------------------
type i2c_in_array is array (filter downto 0) of i2c_in_type;
type state_type is (idle, checkaddr, sclhold, movebyte, handshake);
type i2c2ahb_reg_type is record
state : state_type;
--
haddr : std_logic_vector(31 downto 0);
hdata : std_logic_vector(31 downto 0);
hsize : std_logic_vector(1 downto 0);
hwrite : std_ulogic;
mexc : std_ulogic;
dodma : std_ulogic;
nack : std_ulogic;
prot : std_ulogic;
-- Transfer phase
i2caddr : std_ulogic;
ahbacc : std_ulogic;
ahbadd : std_ulogic;
rec : std_ulogic;
bcnt : std_logic_vector(1 downto 0);
-- Shift register
sreg : std_logic_vector(7 downto 0);
cnt : std_logic_vector(2 downto 0);
-- Synchronizers for inputs SCL and SDA
scl : std_ulogic;
sda : std_ulogic;
i2ci : i2c_in_array;
-- Output enables
scloen : std_ulogic;
sdaoen : std_ulogic;
end record;
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal ami : ahb_dma_in_type;
signal amo : ahb_dma_out_type;
signal r, rin : i2c2ahb_reg_type;
begin
-- Generic AHB master interface
ahbmst0 : ahbmst
generic map (hindex => hindex, hirq => 0, venid => VENDOR_GAISLER,
devid => GAISLER_I2C2AHB, version => 0,
chprot => 3, incaddr => 0)
port map (rstn, clk, ami, amo, ahbi, ahbo);
comb: process (r, rstn, i2ci, amo, i2c2ahbi)
variable v : i2c2ahb_reg_type;
variable sclfilt : std_logic_vector(filter-1 downto 0);
variable sdafilt : std_logic_vector(filter-1 downto 0);
variable hrdata : std_logic_vector(31 downto 0);
variable ahbreq : std_ulogic;
variable slv : std_ulogic;
variable cfg : std_ulogic;
variable lb : std_ulogic;
begin
v := r; ahbreq := '0'; slv := '0'; cfg := '0'; lb := '0';
hrdata := (others => '0');
v.i2ci(0) := i2ci; v.i2ci(filter downto 1) := r.i2ci(filter-1 downto 0);
----------------------------------------------------------------------------
-- Bus filtering
----------------------------------------------------------------------------
for i in 0 to filter-1 loop
sclfilt(i) := r.i2ci(i+1).scl; sdafilt(i) := r.i2ci(i+1).sda;
end loop; -- i
if andv(sclfilt) = '1' then v.scl := '1'; end if;
if orv(sclfilt) = '0' then v.scl := '0'; end if;
if andv(sdafilt) = '1' then v.sda := '1'; end if;
if orv(sdafilt) = '0' then v.sda := '0'; end if;
---------------------------------------------------------------------------
-- DMA control
---------------------------------------------------------------------------
if r.dodma = '1' then
if amo.active = '1' then
if amo.ready = '1' then
hrdata := ahbreadword(amo.rdata);
case r.hsize is
when "00" =>
v.haddr := r.haddr + 1;
for i in 1 to 3 loop
if i = conv_integer(r.haddr(1 downto 0)) then
hrdata(31 downto 24) := hrdata(31-8*i downto 24-8*i);
end if;
end loop;
when "01" =>
v.haddr := r.haddr + 2;
if r.haddr(1) = '1' then
hrdata(31 downto 16) := hrdata(15 downto 0);
end if;
when others =>
v.haddr := r.haddr + 4;
end case;
v.sreg := hrdata(31 downto 24);
v.hdata(31 downto 8) := hrdata(23 downto 0);
v.mexc := '0';
v.dodma := '0';
end if;
if amo.mexc = '1' then
v.mexc := '1';
v.dodma := '0';
end if;
else
ahbreq := '1';
end if;
end if;
---------------------------------------------------------------------------
-- I2C slave control FSM
---------------------------------------------------------------------------
case r.state is
when idle =>
-- Release bus
if (r.scl and not v.scl) = '1' then
v.sdaoen := I2C_HIZ;
end if;
when checkaddr =>
if r.sreg(7 downto 1) = i2c2ahbi.slvaddr then slv := '1'; end if;
if r.sreg(7 downto 1) = i2c2ahbi.cfgaddr then cfg := '1'; end if;
v.rec := not r.sreg(0);
if (slv or cfg) = '1' then
if (slv and r.dodma) = '1' then
-- Core is busy performing DMA
if r.nack = '1' then v.state := idle;
else v.state := sclhold; end if;
else
v.state := handshake;
end if;
else
-- Slave address did not match
v.state := idle;
end if;
v.hwrite := v.rec;
if (slv and not r.dodma) = '1' then v.dodma := not v.rec; end if;
v.ahbacc := slv; v.bcnt := "00"; v.ahbadd := '0';
when sclhold =>
-- This state is used when the device has been addressed to see if SCL
-- should be kept low until the core is ready to process another
-- transfer. It is also used when a data byte has been transmitted or
-- received to keep SCL low until a DMA operation has completed.
-- In the transmit case we keep SCL low before the rising edge of the
-- first byte, so we go directly to move byte. In the receive case we
-- stretch the ACK cycle so we jump to handshake next.
if (r.scl and not v.scl) = '1' then
v.scloen := I2C_LOW;
v.sdaoen := I2C_HIZ;
end if;
if r.dodma = '0' then
if (not r.rec and not r.i2caddr) = '1' then
v.state := movebyte;
else
v.state := handshake;
end if;
v.scloen := I2C_HIZ;
-- Falling edge that should be detected in movebyte may have passed
if (r.i2caddr or r.rec or v.scl) = '0' then
v.sdaoen := r.sreg(7) xor OEPOL_LEVEL;
end if;
end if;
when movebyte =>
if (r.scl and not v.scl) = '1' then
if (r.i2caddr or r.rec) = '0' then
v.sdaoen := r.sreg(7) xor OEPOL_LEVEL;
else
v.sdaoen := I2C_HIZ;
end if;
end if;
if (not r.scl and v.scl) = '1' then
v.sreg := r.sreg(6 downto 0) & r.sda;
if r.cnt = "111" then
if r.i2caddr = '1' then
v.state := checkaddr;
else
v.state := handshake;
end if;
v.cnt := (others => '0');
else
v.cnt := r.cnt + 1;
end if;
end if;
when handshake =>
if ((r.hsize = "00") or ((r.hsize(0) and r.bcnt(0)) = '1') or
(r.bcnt = "11")) then
lb := '1';
end if;
-- Falling edge
if (r.scl and not v.scl) = '1' then
if (r.i2caddr or not r.ahbacc) = '1' then
-- Also handles first byte on AHB read access
if (r.rec or r.i2caddr) = '1' then
v.sdaoen := I2C_LOW;
else
v.sdaoen := I2C_HIZ;
end if;
if (not r.i2caddr and r.rec) = '1' then
-- Control register access
v.nack := r.sreg(2);
v.hsize := r.sreg(1 downto 0);
end if;
else
-- AHB access
if r.rec = '1' then
-- First we need a 4 byte address, then we handle data.
v.bcnt := r.bcnt + 1;
if r.ahbadd = '0' then
-- We could check if the address is within the allowed memory
-- area here, and nack otherwise, but we do it when the access
-- is performed instead, to have one check for all cases.
v.haddr := r.haddr(23 downto 0) & r.sreg;
if r.bcnt = "11" then v.ahbadd := '1'; end if;
v.sdaoen := I2C_LOW;
elsif r.dodma = '0' then
if r.bcnt = "00" then v.hdata(31 downto 24) := r.sreg; end if;
if r.bcnt(1) = '0' then v.hdata(23 downto 16) := r.sreg; end if;
if r.bcnt(0) = '0' then v.hdata(15 downto 8) := r.sreg; end if;
v.hdata(7 downto 0) := r.sreg;
if lb = '1' then v.dodma := '1'; v.bcnt := "00"; end if;
v.sdaoen := I2C_LOW;
end if;
else
-- Transmit, release bus
v.sdaoen := I2C_HIZ;
end if;
end if;
-- Previous DMA is not finished yet
if (r.dodma and r.ahbacc) = '1' then
if r.nack = '0' then
-- Hold clock low and handle data when DMA is finished
v.state := sclhold;
v.scloen := I2C_LOW;
else
-- NAK byte
v.sdaoen := I2C_HIZ;
v.state := idle;
end if;
end if;
end if;
-- Risinge edge
if (not r.scl and v.scl) = '1' then
if (r.i2caddr or not r.ahbacc) = '1' then
if r.sda = I2C_ACK then
v.state := movebyte;
else
v.state := idle;
end if;
else
if r.rec = '1' then
v.state := movebyte;
else
-- Transmit, check ACK/NAK from master
-- If the master NAKs the transmitted byte the transfer has ended
-- and we should wait for the master's next action. If the master
-- ACKs the byte the core we will continue to transmit data until
-- we reach the last available byte. When the last byte has been
-- transmitted we will act depending on if we are allowed to enter
-- sclhold. If we can, we enter sclhold and start a new DMA
-- operation, otherwise we stop communicating until the next start
-- condition.
v.bcnt := r.bcnt + 1;
if r.sda = I2C_ACK then
if lb = '1' then
if r.nack = '1' then
v.state := idle;
else
v.dodma := '1'; v.bcnt := "00";
v.state := sclhold;
end if;
else
v.state := movebyte;
end if;
else
v.state := idle;
end if;
v.hdata(31 downto 8) := r.hdata(23 downto 0);
v.sreg := r.hdata(31 downto 24);
end if;
end if;
v.i2caddr := '0';
if r.ahbacc = '0' then
-- Control register access
v.sreg := zero32(7 downto 6) & r.prot & r.mexc &
r.dodma & r.nack & r.hsize;
end if;
end if;
end case;
if i2c2ahbi.hmask /= zero32 then
if v.dodma = '1' then
if ((i2c2ahbi.haddr xor r.haddr) and i2c2ahbi.hmask) /= zero32 then
v.dodma := '0';
v.prot := '1';
v.state := idle;
else
v.prot := '0';
end if;
end if;
else
v.prot := '0';
end if;
if i2c2ahbi.en = '1' then
-- STOP condition
if (r.scl and v.scl and not r.sda and v.sda) = '1' then
v.state := idle;
end if;
-- START or repeated START condition
if (r.scl and v.scl and r.sda and not v.sda) = '1' then
v.state := movebyte;
v.cnt := (others => '0');
v.i2caddr := '1';
end if;
end if;
----------------------------------------------------------------------------
-- Reset
----------------------------------------------------------------------------
if rstn = '0' then
v.state := idle;
v.hsize := HSIZE_WORD(1 downto 0);
v.mexc := '0';
v.dodma := '0';
v.nack := '0';
v.prot := '0';
v.scl := '0';
v.scloen := I2C_HIZ; v.sdaoen := I2C_HIZ;
end if;
if i2c2ahbi.hmask = zero32 then v.prot := '0'; end if;
----------------------------------------------------------------------------
-- Signal assignments
----------------------------------------------------------------------------
-- Core registers
rin <= v;
-- AHB master control
ami.address <= r.haddr;
ami.wdata <= ahbdrivedata(r.hdata);
ami.start <= ahbreq;
ami.burst <= '0';
ami.write <= r.hwrite;
ami.busy <= '0';
ami.irq <= '0';
ami.size <= '0' & r.hsize;
-- Update outputs
i2c2ahbo.dma <= r.dodma;
i2c2ahbo.wr <= r.hwrite;
i2c2ahbo.prot <= r.prot;
i2co.scl <= '0';
i2co.scloen <= r.scloen;
i2co.sda <= '0';
i2co.sdaoen <= r.sdaoen;
i2co.enable <= i2c2ahbi.en;
end process comb;
reg: process (clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process reg;
-- Boot message
-- pragma translate_off
bootmsg : report_version
generic map ("i2c2ahb" & tost(hindex) & ": I2C to AHB bridge");
-- pragma translate_on
end architecture rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2715.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s04b02x00p01n01i02715ent IS
END c13s04b02x00p01n01i02715ent;
ARCHITECTURE c13s04b02x00p01n01i02715arch OF c13s04b02x00p01n01i02715ent IS
BEGIN
TESTING: PROCESS
variable I : INTEGER;
variable R : REAL;
BEGIN
I := 0#121#E2; -- ERROR : invalid base
assert FALSE
report "***FAILED TEST: c13s04b02x00p01n01i02715 - No base less than '2' or greater than '16' is allowed."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s04b02x00p01n01i02715arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2715.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s04b02x00p01n01i02715ent IS
END c13s04b02x00p01n01i02715ent;
ARCHITECTURE c13s04b02x00p01n01i02715arch OF c13s04b02x00p01n01i02715ent IS
BEGIN
TESTING: PROCESS
variable I : INTEGER;
variable R : REAL;
BEGIN
I := 0#121#E2; -- ERROR : invalid base
assert FALSE
report "***FAILED TEST: c13s04b02x00p01n01i02715 - No base less than '2' or greater than '16' is allowed."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s04b02x00p01n01i02715arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2715.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s04b02x00p01n01i02715ent IS
END c13s04b02x00p01n01i02715ent;
ARCHITECTURE c13s04b02x00p01n01i02715arch OF c13s04b02x00p01n01i02715ent IS
BEGIN
TESTING: PROCESS
variable I : INTEGER;
variable R : REAL;
BEGIN
I := 0#121#E2; -- ERROR : invalid base
assert FALSE
report "***FAILED TEST: c13s04b02x00p01n01i02715 - No base less than '2' or greater than '16' is allowed."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s04b02x00p01n01i02715arch;
|
-- 500 variable assigns in 2 processes. GHC works here.
entity main is
end entity main;
architecture arch of main is
signal clk : integer := 0;
constant CYCLES : integer := 1000;
begin
main: process(clk)
--{{{
variable a0502 : integer;
variable a0503 : integer;
variable a0504 : integer;
variable a0505 : integer;
variable a0506 : integer;
variable a0507 : integer;
variable a0508 : integer;
variable a0509 : integer;
variable a0510 : integer;
variable a0511 : integer;
variable a0512 : integer;
variable a0513 : integer;
variable a0514 : integer;
variable a0515 : integer;
variable a0516 : integer;
variable a0517 : integer;
variable a0518 : integer;
variable a0519 : integer;
variable a0520 : integer;
variable a0521 : integer;
variable a0522 : integer;
variable a0523 : integer;
variable a0524 : integer;
variable a0525 : integer;
variable a0526 : integer;
variable a0527 : integer;
variable a0528 : integer;
variable a0529 : integer;
variable a0530 : integer;
variable a0531 : integer;
variable a0532 : integer;
variable a0533 : integer;
variable a0534 : integer;
variable a0535 : integer;
variable a0536 : integer;
variable a0537 : integer;
variable a0538 : integer;
variable a0539 : integer;
variable a0540 : integer;
variable a0541 : integer;
variable a0542 : integer;
variable a0543 : integer;
variable a0544 : integer;
variable a0545 : integer;
variable a0546 : integer;
variable a0547 : integer;
variable a0548 : integer;
variable a0549 : integer;
variable a0550 : integer;
variable a0551 : integer;
variable a0552 : integer;
variable a0553 : integer;
variable a0554 : integer;
variable a0555 : integer;
variable a0556 : integer;
variable a0557 : integer;
variable a0558 : integer;
variable a0559 : integer;
variable a0560 : integer;
variable a0561 : integer;
variable a0562 : integer;
variable a0563 : integer;
variable a0564 : integer;
variable a0565 : integer;
variable a0566 : integer;
variable a0567 : integer;
variable a0568 : integer;
variable a0569 : integer;
variable a0570 : integer;
variable a0571 : integer;
variable a0572 : integer;
variable a0573 : integer;
variable a0574 : integer;
variable a0575 : integer;
variable a0576 : integer;
variable a0577 : integer;
variable a0578 : integer;
variable a0579 : integer;
variable a0580 : integer;
variable a0581 : integer;
variable a0582 : integer;
variable a0583 : integer;
variable a0584 : integer;
variable a0585 : integer;
variable a0586 : integer;
variable a0587 : integer;
variable a0588 : integer;
variable a0589 : integer;
variable a0590 : integer;
variable a0591 : integer;
variable a0592 : integer;
variable a0593 : integer;
variable a0594 : integer;
variable a0595 : integer;
variable a0596 : integer;
variable a0597 : integer;
variable a0598 : integer;
variable a0599 : integer;
variable a0600 : integer;
variable a0601 : integer;
variable a0602 : integer;
variable a0603 : integer;
variable a0604 : integer;
variable a0605 : integer;
variable a0606 : integer;
variable a0607 : integer;
variable a0608 : integer;
variable a0609 : integer;
variable a0610 : integer;
variable a0611 : integer;
variable a0612 : integer;
variable a0613 : integer;
variable a0614 : integer;
variable a0615 : integer;
variable a0616 : integer;
variable a0617 : integer;
variable a0618 : integer;
variable a0619 : integer;
variable a0620 : integer;
variable a0621 : integer;
variable a0622 : integer;
variable a0623 : integer;
variable a0624 : integer;
variable a0625 : integer;
variable a0626 : integer;
variable a0627 : integer;
variable a0628 : integer;
variable a0629 : integer;
variable a0630 : integer;
variable a0631 : integer;
variable a0632 : integer;
variable a0633 : integer;
variable a0634 : integer;
variable a0635 : integer;
variable a0636 : integer;
variable a0637 : integer;
variable a0638 : integer;
variable a0639 : integer;
variable a0640 : integer;
variable a0641 : integer;
variable a0642 : integer;
variable a0643 : integer;
variable a0644 : integer;
variable a0645 : integer;
variable a0646 : integer;
variable a0647 : integer;
variable a0648 : integer;
variable a0649 : integer;
variable a0650 : integer;
variable a0651 : integer;
variable a0652 : integer;
variable a0653 : integer;
variable a0654 : integer;
variable a0655 : integer;
variable a0656 : integer;
variable a0657 : integer;
variable a0658 : integer;
variable a0659 : integer;
variable a0660 : integer;
variable a0661 : integer;
variable a0662 : integer;
variable a0663 : integer;
variable a0664 : integer;
variable a0665 : integer;
variable a0666 : integer;
variable a0667 : integer;
variable a0668 : integer;
variable a0669 : integer;
variable a0670 : integer;
variable a0671 : integer;
variable a0672 : integer;
variable a0673 : integer;
variable a0674 : integer;
variable a0675 : integer;
variable a0676 : integer;
variable a0677 : integer;
variable a0678 : integer;
variable a0679 : integer;
variable a0680 : integer;
variable a0681 : integer;
variable a0682 : integer;
variable a0683 : integer;
variable a0684 : integer;
variable a0685 : integer;
variable a0686 : integer;
variable a0687 : integer;
variable a0688 : integer;
variable a0689 : integer;
variable a0690 : integer;
variable a0691 : integer;
variable a0692 : integer;
variable a0693 : integer;
variable a0694 : integer;
variable a0695 : integer;
variable a0696 : integer;
variable a0697 : integer;
variable a0698 : integer;
variable a0699 : integer;
variable a0700 : integer;
variable a0701 : integer;
variable a0702 : integer;
variable a0703 : integer;
variable a0704 : integer;
variable a0705 : integer;
variable a0706 : integer;
variable a0707 : integer;
variable a0708 : integer;
variable a0709 : integer;
variable a0710 : integer;
variable a0711 : integer;
variable a0712 : integer;
variable a0713 : integer;
variable a0714 : integer;
variable a0715 : integer;
variable a0716 : integer;
variable a0717 : integer;
variable a0718 : integer;
variable a0719 : integer;
variable a0720 : integer;
variable a0721 : integer;
variable a0722 : integer;
variable a0723 : integer;
variable a0724 : integer;
variable a0725 : integer;
variable a0726 : integer;
variable a0727 : integer;
variable a0728 : integer;
variable a0729 : integer;
variable a0730 : integer;
variable a0731 : integer;
variable a0732 : integer;
variable a0733 : integer;
variable a0734 : integer;
variable a0735 : integer;
variable a0736 : integer;
variable a0737 : integer;
variable a0738 : integer;
variable a0739 : integer;
variable a0740 : integer;
variable a0741 : integer;
variable a0742 : integer;
variable a0743 : integer;
variable a0744 : integer;
variable a0745 : integer;
variable a0746 : integer;
variable a0747 : integer;
variable a0748 : integer;
variable a0749 : integer;
variable a0750 : integer;
variable a0751 : integer;
variable a0752 : integer;
variable a0753 : integer;
variable a0754 : integer;
variable a0755 : integer;
variable a0756 : integer;
variable a0757 : integer;
variable a0758 : integer;
variable a0759 : integer;
variable a0760 : integer;
variable a0761 : integer;
variable a0762 : integer;
variable a0763 : integer;
variable a0764 : integer;
variable a0765 : integer;
variable a0766 : integer;
variable a0767 : integer;
variable a0768 : integer;
variable a0769 : integer;
variable a0770 : integer;
variable a0771 : integer;
variable a0772 : integer;
variable a0773 : integer;
variable a0774 : integer;
variable a0775 : integer;
variable a0776 : integer;
variable a0777 : integer;
variable a0778 : integer;
variable a0779 : integer;
variable a0780 : integer;
variable a0781 : integer;
variable a0782 : integer;
variable a0783 : integer;
variable a0784 : integer;
variable a0785 : integer;
variable a0786 : integer;
variable a0787 : integer;
variable a0788 : integer;
variable a0789 : integer;
variable a0790 : integer;
variable a0791 : integer;
variable a0792 : integer;
variable a0793 : integer;
variable a0794 : integer;
variable a0795 : integer;
variable a0796 : integer;
variable a0797 : integer;
variable a0798 : integer;
variable a0799 : integer;
variable a0800 : integer;
variable a0801 : integer;
variable a0802 : integer;
variable a0803 : integer;
variable a0804 : integer;
variable a0805 : integer;
variable a0806 : integer;
variable a0807 : integer;
variable a0808 : integer;
variable a0809 : integer;
variable a0810 : integer;
variable a0811 : integer;
variable a0812 : integer;
variable a0813 : integer;
variable a0814 : integer;
variable a0815 : integer;
variable a0816 : integer;
variable a0817 : integer;
variable a0818 : integer;
variable a0819 : integer;
variable a0820 : integer;
variable a0821 : integer;
variable a0822 : integer;
variable a0823 : integer;
variable a0824 : integer;
variable a0825 : integer;
variable a0826 : integer;
variable a0827 : integer;
variable a0828 : integer;
variable a0829 : integer;
variable a0830 : integer;
variable a0831 : integer;
variable a0832 : integer;
variable a0833 : integer;
variable a0834 : integer;
variable a0835 : integer;
variable a0836 : integer;
variable a0837 : integer;
variable a0838 : integer;
variable a0839 : integer;
variable a0840 : integer;
variable a0841 : integer;
variable a0842 : integer;
variable a0843 : integer;
variable a0844 : integer;
variable a0845 : integer;
variable a0846 : integer;
variable a0847 : integer;
variable a0848 : integer;
variable a0849 : integer;
variable a0850 : integer;
variable a0851 : integer;
variable a0852 : integer;
variable a0853 : integer;
variable a0854 : integer;
variable a0855 : integer;
variable a0856 : integer;
variable a0857 : integer;
variable a0858 : integer;
variable a0859 : integer;
variable a0860 : integer;
variable a0861 : integer;
variable a0862 : integer;
variable a0863 : integer;
variable a0864 : integer;
variable a0865 : integer;
variable a0866 : integer;
variable a0867 : integer;
variable a0868 : integer;
variable a0869 : integer;
variable a0870 : integer;
variable a0871 : integer;
variable a0872 : integer;
variable a0873 : integer;
variable a0874 : integer;
variable a0875 : integer;
variable a0876 : integer;
variable a0877 : integer;
variable a0878 : integer;
variable a0879 : integer;
variable a0880 : integer;
variable a0881 : integer;
variable a0882 : integer;
variable a0883 : integer;
variable a0884 : integer;
variable a0885 : integer;
variable a0886 : integer;
variable a0887 : integer;
variable a0888 : integer;
variable a0889 : integer;
variable a0890 : integer;
variable a0891 : integer;
variable a0892 : integer;
variable a0893 : integer;
variable a0894 : integer;
variable a0895 : integer;
variable a0896 : integer;
variable a0897 : integer;
variable a0898 : integer;
variable a0899 : integer;
variable a0900 : integer;
variable a0901 : integer;
variable a0902 : integer;
variable a0903 : integer;
variable a0904 : integer;
variable a0905 : integer;
variable a0906 : integer;
variable a0907 : integer;
variable a0908 : integer;
variable a0909 : integer;
variable a0910 : integer;
variable a0911 : integer;
variable a0912 : integer;
variable a0913 : integer;
variable a0914 : integer;
variable a0915 : integer;
variable a0916 : integer;
variable a0917 : integer;
variable a0918 : integer;
variable a0919 : integer;
variable a0920 : integer;
variable a0921 : integer;
variable a0922 : integer;
variable a0923 : integer;
variable a0924 : integer;
variable a0925 : integer;
variable a0926 : integer;
variable a0927 : integer;
variable a0928 : integer;
variable a0929 : integer;
variable a0930 : integer;
variable a0931 : integer;
variable a0932 : integer;
variable a0933 : integer;
variable a0934 : integer;
variable a0935 : integer;
variable a0936 : integer;
variable a0937 : integer;
variable a0938 : integer;
variable a0939 : integer;
variable a0940 : integer;
variable a0941 : integer;
variable a0942 : integer;
variable a0943 : integer;
variable a0944 : integer;
variable a0945 : integer;
variable a0946 : integer;
variable a0947 : integer;
variable a0948 : integer;
variable a0949 : integer;
variable a0950 : integer;
variable a0951 : integer;
variable a0952 : integer;
variable a0953 : integer;
variable a0954 : integer;
variable a0955 : integer;
variable a0956 : integer;
variable a0957 : integer;
variable a0958 : integer;
variable a0959 : integer;
variable a0960 : integer;
variable a0961 : integer;
variable a0962 : integer;
variable a0963 : integer;
variable a0964 : integer;
variable a0965 : integer;
variable a0966 : integer;
variable a0967 : integer;
variable a0968 : integer;
variable a0969 : integer;
variable a0970 : integer;
variable a0971 : integer;
variable a0972 : integer;
variable a0973 : integer;
variable a0974 : integer;
variable a0975 : integer;
variable a0976 : integer;
variable a0977 : integer;
variable a0978 : integer;
variable a0979 : integer;
variable a0980 : integer;
variable a0981 : integer;
variable a0982 : integer;
variable a0983 : integer;
variable a0984 : integer;
variable a0985 : integer;
variable a0986 : integer;
variable a0987 : integer;
variable a0988 : integer;
variable a0989 : integer;
variable a0990 : integer;
variable a0991 : integer;
variable a0992 : integer;
variable a0993 : integer;
variable a0994 : integer;
variable a0995 : integer;
variable a0996 : integer;
variable a0997 : integer;
variable a0998 : integer;
variable a0999 : integer;
variable a1000 : integer;
begin
a0502 := 502;
a0503 := 503;
a0504 := 504;
a0505 := 505;
a0506 := 506;
a0507 := 507;
a0508 := 508;
a0509 := 509;
a0510 := 510;
a0511 := 511;
a0512 := 512;
a0513 := 513;
a0514 := 514;
a0515 := 515;
a0516 := 516;
a0517 := 517;
a0518 := 518;
a0519 := 519;
a0520 := 520;
a0521 := 521;
a0522 := 522;
a0523 := 523;
a0524 := 524;
a0525 := 525;
a0526 := 526;
a0527 := 527;
a0528 := 528;
a0529 := 529;
a0530 := 530;
a0531 := 531;
a0532 := 532;
a0533 := 533;
a0534 := 534;
a0535 := 535;
a0536 := 536;
a0537 := 537;
a0538 := 538;
a0539 := 539;
a0540 := 540;
a0541 := 541;
a0542 := 542;
a0543 := 543;
a0544 := 544;
a0545 := 545;
a0546 := 546;
a0547 := 547;
a0548 := 548;
a0549 := 549;
a0550 := 550;
a0551 := 551;
a0552 := 552;
a0553 := 553;
a0554 := 554;
a0555 := 555;
a0556 := 556;
a0557 := 557;
a0558 := 558;
a0559 := 559;
a0560 := 560;
a0561 := 561;
a0562 := 562;
a0563 := 563;
a0564 := 564;
a0565 := 565;
a0566 := 566;
a0567 := 567;
a0568 := 568;
a0569 := 569;
a0570 := 570;
a0571 := 571;
a0572 := 572;
a0573 := 573;
a0574 := 574;
a0575 := 575;
a0576 := 576;
a0577 := 577;
a0578 := 578;
a0579 := 579;
a0580 := 580;
a0581 := 581;
a0582 := 582;
a0583 := 583;
a0584 := 584;
a0585 := 585;
a0586 := 586;
a0587 := 587;
a0588 := 588;
a0589 := 589;
a0590 := 590;
a0591 := 591;
a0592 := 592;
a0593 := 593;
a0594 := 594;
a0595 := 595;
a0596 := 596;
a0597 := 597;
a0598 := 598;
a0599 := 599;
a0600 := 600;
a0601 := 601;
a0602 := 602;
a0603 := 603;
a0604 := 604;
a0605 := 605;
a0606 := 606;
a0607 := 607;
a0608 := 608;
a0609 := 609;
a0610 := 610;
a0611 := 611;
a0612 := 612;
a0613 := 613;
a0614 := 614;
a0615 := 615;
a0616 := 616;
a0617 := 617;
a0618 := 618;
a0619 := 619;
a0620 := 620;
a0621 := 621;
a0622 := 622;
a0623 := 623;
a0624 := 624;
a0625 := 625;
a0626 := 626;
a0627 := 627;
a0628 := 628;
a0629 := 629;
a0630 := 630;
a0631 := 631;
a0632 := 632;
a0633 := 633;
a0634 := 634;
a0635 := 635;
a0636 := 636;
a0637 := 637;
a0638 := 638;
a0639 := 639;
a0640 := 640;
a0641 := 641;
a0642 := 642;
a0643 := 643;
a0644 := 644;
a0645 := 645;
a0646 := 646;
a0647 := 647;
a0648 := 648;
a0649 := 649;
a0650 := 650;
a0651 := 651;
a0652 := 652;
a0653 := 653;
a0654 := 654;
a0655 := 655;
a0656 := 656;
a0657 := 657;
a0658 := 658;
a0659 := 659;
a0660 := 660;
a0661 := 661;
a0662 := 662;
a0663 := 663;
a0664 := 664;
a0665 := 665;
a0666 := 666;
a0667 := 667;
a0668 := 668;
a0669 := 669;
a0670 := 670;
a0671 := 671;
a0672 := 672;
a0673 := 673;
a0674 := 674;
a0675 := 675;
a0676 := 676;
a0677 := 677;
a0678 := 678;
a0679 := 679;
a0680 := 680;
a0681 := 681;
a0682 := 682;
a0683 := 683;
a0684 := 684;
a0685 := 685;
a0686 := 686;
a0687 := 687;
a0688 := 688;
a0689 := 689;
a0690 := 690;
a0691 := 691;
a0692 := 692;
a0693 := 693;
a0694 := 694;
a0695 := 695;
a0696 := 696;
a0697 := 697;
a0698 := 698;
a0699 := 699;
a0700 := 700;
a0701 := 701;
a0702 := 702;
a0703 := 703;
a0704 := 704;
a0705 := 705;
a0706 := 706;
a0707 := 707;
a0708 := 708;
a0709 := 709;
a0710 := 710;
a0711 := 711;
a0712 := 712;
a0713 := 713;
a0714 := 714;
a0715 := 715;
a0716 := 716;
a0717 := 717;
a0718 := 718;
a0719 := 719;
a0720 := 720;
a0721 := 721;
a0722 := 722;
a0723 := 723;
a0724 := 724;
a0725 := 725;
a0726 := 726;
a0727 := 727;
a0728 := 728;
a0729 := 729;
a0730 := 730;
a0731 := 731;
a0732 := 732;
a0733 := 733;
a0734 := 734;
a0735 := 735;
a0736 := 736;
a0737 := 737;
a0738 := 738;
a0739 := 739;
a0740 := 740;
a0741 := 741;
a0742 := 742;
a0743 := 743;
a0744 := 744;
a0745 := 745;
a0746 := 746;
a0747 := 747;
a0748 := 748;
a0749 := 749;
a0750 := 750;
a0751 := 751;
a0752 := 752;
a0753 := 753;
a0754 := 754;
a0755 := 755;
a0756 := 756;
a0757 := 757;
a0758 := 758;
a0759 := 759;
a0760 := 760;
a0761 := 761;
a0762 := 762;
a0763 := 763;
a0764 := 764;
a0765 := 765;
a0766 := 766;
a0767 := 767;
a0768 := 768;
a0769 := 769;
a0770 := 770;
a0771 := 771;
a0772 := 772;
a0773 := 773;
a0774 := 774;
a0775 := 775;
a0776 := 776;
a0777 := 777;
a0778 := 778;
a0779 := 779;
a0780 := 780;
a0781 := 781;
a0782 := 782;
a0783 := 783;
a0784 := 784;
a0785 := 785;
a0786 := 786;
a0787 := 787;
a0788 := 788;
a0789 := 789;
a0790 := 790;
a0791 := 791;
a0792 := 792;
a0793 := 793;
a0794 := 794;
a0795 := 795;
a0796 := 796;
a0797 := 797;
a0798 := 798;
a0799 := 799;
a0800 := 800;
a0801 := 801;
a0802 := 802;
a0803 := 803;
a0804 := 804;
a0805 := 805;
a0806 := 806;
a0807 := 807;
a0808 := 808;
a0809 := 809;
a0810 := 810;
a0811 := 811;
a0812 := 812;
a0813 := 813;
a0814 := 814;
a0815 := 815;
a0816 := 816;
a0817 := 817;
a0818 := 818;
a0819 := 819;
a0820 := 820;
a0821 := 821;
a0822 := 822;
a0823 := 823;
a0824 := 824;
a0825 := 825;
a0826 := 826;
a0827 := 827;
a0828 := 828;
a0829 := 829;
a0830 := 830;
a0831 := 831;
a0832 := 832;
a0833 := 833;
a0834 := 834;
a0835 := 835;
a0836 := 836;
a0837 := 837;
a0838 := 838;
a0839 := 839;
a0840 := 840;
a0841 := 841;
a0842 := 842;
a0843 := 843;
a0844 := 844;
a0845 := 845;
a0846 := 846;
a0847 := 847;
a0848 := 848;
a0849 := 849;
a0850 := 850;
a0851 := 851;
a0852 := 852;
a0853 := 853;
a0854 := 854;
a0855 := 855;
a0856 := 856;
a0857 := 857;
a0858 := 858;
a0859 := 859;
a0860 := 860;
a0861 := 861;
a0862 := 862;
a0863 := 863;
a0864 := 864;
a0865 := 865;
a0866 := 866;
a0867 := 867;
a0868 := 868;
a0869 := 869;
a0870 := 870;
a0871 := 871;
a0872 := 872;
a0873 := 873;
a0874 := 874;
a0875 := 875;
a0876 := 876;
a0877 := 877;
a0878 := 878;
a0879 := 879;
a0880 := 880;
a0881 := 881;
a0882 := 882;
a0883 := 883;
a0884 := 884;
a0885 := 885;
a0886 := 886;
a0887 := 887;
a0888 := 888;
a0889 := 889;
a0890 := 890;
a0891 := 891;
a0892 := 892;
a0893 := 893;
a0894 := 894;
a0895 := 895;
a0896 := 896;
a0897 := 897;
a0898 := 898;
a0899 := 899;
a0900 := 900;
a0901 := 901;
a0902 := 902;
a0903 := 903;
a0904 := 904;
a0905 := 905;
a0906 := 906;
a0907 := 907;
a0908 := 908;
a0909 := 909;
a0910 := 910;
a0911 := 911;
a0912 := 912;
a0913 := 913;
a0914 := 914;
a0915 := 915;
a0916 := 916;
a0917 := 917;
a0918 := 918;
a0919 := 919;
a0920 := 920;
a0921 := 921;
a0922 := 922;
a0923 := 923;
a0924 := 924;
a0925 := 925;
a0926 := 926;
a0927 := 927;
a0928 := 928;
a0929 := 929;
a0930 := 930;
a0931 := 931;
a0932 := 932;
a0933 := 933;
a0934 := 934;
a0935 := 935;
a0936 := 936;
a0937 := 937;
a0938 := 938;
a0939 := 939;
a0940 := 940;
a0941 := 941;
a0942 := 942;
a0943 := 943;
a0944 := 944;
a0945 := 945;
a0946 := 946;
a0947 := 947;
a0948 := 948;
a0949 := 949;
a0950 := 950;
a0951 := 951;
a0952 := 952;
a0953 := 953;
a0954 := 954;
a0955 := 955;
a0956 := 956;
a0957 := 957;
a0958 := 958;
a0959 := 959;
a0960 := 960;
a0961 := 961;
a0962 := 962;
a0963 := 963;
a0964 := 964;
a0965 := 965;
a0966 := 966;
a0967 := 967;
a0968 := 968;
a0969 := 969;
a0970 := 970;
a0971 := 971;
a0972 := 972;
a0973 := 973;
a0974 := 974;
a0975 := 975;
a0976 := 976;
a0977 := 977;
a0978 := 978;
a0979 := 979;
a0980 := 980;
a0981 := 981;
a0982 := 982;
a0983 := 983;
a0984 := 984;
a0985 := 985;
a0986 := 986;
a0987 := 987;
a0988 := 988;
a0989 := 989;
a0990 := 990;
a0991 := 991;
a0992 := 992;
a0993 := 993;
a0994 := 994;
a0995 := 995;
a0996 := 996;
a0997 := 997;
a0998 := 998;
a0999 := 999;
a1000 := 1000;
-- report "tick";
--}}}
end process;
main2: process(clk)
--{{{
variable a0502 : integer;
variable a0503 : integer;
variable a0504 : integer;
variable a0505 : integer;
variable a0506 : integer;
variable a0507 : integer;
variable a0508 : integer;
variable a0509 : integer;
variable a0510 : integer;
variable a0511 : integer;
variable a0512 : integer;
variable a0513 : integer;
variable a0514 : integer;
variable a0515 : integer;
variable a0516 : integer;
variable a0517 : integer;
variable a0518 : integer;
variable a0519 : integer;
variable a0520 : integer;
variable a0521 : integer;
variable a0522 : integer;
variable a0523 : integer;
variable a0524 : integer;
variable a0525 : integer;
variable a0526 : integer;
variable a0527 : integer;
variable a0528 : integer;
variable a0529 : integer;
variable a0530 : integer;
variable a0531 : integer;
variable a0532 : integer;
variable a0533 : integer;
variable a0534 : integer;
variable a0535 : integer;
variable a0536 : integer;
variable a0537 : integer;
variable a0538 : integer;
variable a0539 : integer;
variable a0540 : integer;
variable a0541 : integer;
variable a0542 : integer;
variable a0543 : integer;
variable a0544 : integer;
variable a0545 : integer;
variable a0546 : integer;
variable a0547 : integer;
variable a0548 : integer;
variable a0549 : integer;
variable a0550 : integer;
variable a0551 : integer;
variable a0552 : integer;
variable a0553 : integer;
variable a0554 : integer;
variable a0555 : integer;
variable a0556 : integer;
variable a0557 : integer;
variable a0558 : integer;
variable a0559 : integer;
variable a0560 : integer;
variable a0561 : integer;
variable a0562 : integer;
variable a0563 : integer;
variable a0564 : integer;
variable a0565 : integer;
variable a0566 : integer;
variable a0567 : integer;
variable a0568 : integer;
variable a0569 : integer;
variable a0570 : integer;
variable a0571 : integer;
variable a0572 : integer;
variable a0573 : integer;
variable a0574 : integer;
variable a0575 : integer;
variable a0576 : integer;
variable a0577 : integer;
variable a0578 : integer;
variable a0579 : integer;
variable a0580 : integer;
variable a0581 : integer;
variable a0582 : integer;
variable a0583 : integer;
variable a0584 : integer;
variable a0585 : integer;
variable a0586 : integer;
variable a0587 : integer;
variable a0588 : integer;
variable a0589 : integer;
variable a0590 : integer;
variable a0591 : integer;
variable a0592 : integer;
variable a0593 : integer;
variable a0594 : integer;
variable a0595 : integer;
variable a0596 : integer;
variable a0597 : integer;
variable a0598 : integer;
variable a0599 : integer;
variable a0600 : integer;
variable a0601 : integer;
variable a0602 : integer;
variable a0603 : integer;
variable a0604 : integer;
variable a0605 : integer;
variable a0606 : integer;
variable a0607 : integer;
variable a0608 : integer;
variable a0609 : integer;
variable a0610 : integer;
variable a0611 : integer;
variable a0612 : integer;
variable a0613 : integer;
variable a0614 : integer;
variable a0615 : integer;
variable a0616 : integer;
variable a0617 : integer;
variable a0618 : integer;
variable a0619 : integer;
variable a0620 : integer;
variable a0621 : integer;
variable a0622 : integer;
variable a0623 : integer;
variable a0624 : integer;
variable a0625 : integer;
variable a0626 : integer;
variable a0627 : integer;
variable a0628 : integer;
variable a0629 : integer;
variable a0630 : integer;
variable a0631 : integer;
variable a0632 : integer;
variable a0633 : integer;
variable a0634 : integer;
variable a0635 : integer;
variable a0636 : integer;
variable a0637 : integer;
variable a0638 : integer;
variable a0639 : integer;
variable a0640 : integer;
variable a0641 : integer;
variable a0642 : integer;
variable a0643 : integer;
variable a0644 : integer;
variable a0645 : integer;
variable a0646 : integer;
variable a0647 : integer;
variable a0648 : integer;
variable a0649 : integer;
variable a0650 : integer;
variable a0651 : integer;
variable a0652 : integer;
variable a0653 : integer;
variable a0654 : integer;
variable a0655 : integer;
variable a0656 : integer;
variable a0657 : integer;
variable a0658 : integer;
variable a0659 : integer;
variable a0660 : integer;
variable a0661 : integer;
variable a0662 : integer;
variable a0663 : integer;
variable a0664 : integer;
variable a0665 : integer;
variable a0666 : integer;
variable a0667 : integer;
variable a0668 : integer;
variable a0669 : integer;
variable a0670 : integer;
variable a0671 : integer;
variable a0672 : integer;
variable a0673 : integer;
variable a0674 : integer;
variable a0675 : integer;
variable a0676 : integer;
variable a0677 : integer;
variable a0678 : integer;
variable a0679 : integer;
variable a0680 : integer;
variable a0681 : integer;
variable a0682 : integer;
variable a0683 : integer;
variable a0684 : integer;
variable a0685 : integer;
variable a0686 : integer;
variable a0687 : integer;
variable a0688 : integer;
variable a0689 : integer;
variable a0690 : integer;
variable a0691 : integer;
variable a0692 : integer;
variable a0693 : integer;
variable a0694 : integer;
variable a0695 : integer;
variable a0696 : integer;
variable a0697 : integer;
variable a0698 : integer;
variable a0699 : integer;
variable a0700 : integer;
variable a0701 : integer;
variable a0702 : integer;
variable a0703 : integer;
variable a0704 : integer;
variable a0705 : integer;
variable a0706 : integer;
variable a0707 : integer;
variable a0708 : integer;
variable a0709 : integer;
variable a0710 : integer;
variable a0711 : integer;
variable a0712 : integer;
variable a0713 : integer;
variable a0714 : integer;
variable a0715 : integer;
variable a0716 : integer;
variable a0717 : integer;
variable a0718 : integer;
variable a0719 : integer;
variable a0720 : integer;
variable a0721 : integer;
variable a0722 : integer;
variable a0723 : integer;
variable a0724 : integer;
variable a0725 : integer;
variable a0726 : integer;
variable a0727 : integer;
variable a0728 : integer;
variable a0729 : integer;
variable a0730 : integer;
variable a0731 : integer;
variable a0732 : integer;
variable a0733 : integer;
variable a0734 : integer;
variable a0735 : integer;
variable a0736 : integer;
variable a0737 : integer;
variable a0738 : integer;
variable a0739 : integer;
variable a0740 : integer;
variable a0741 : integer;
variable a0742 : integer;
variable a0743 : integer;
variable a0744 : integer;
variable a0745 : integer;
variable a0746 : integer;
variable a0747 : integer;
variable a0748 : integer;
variable a0749 : integer;
variable a0750 : integer;
variable a0751 : integer;
variable a0752 : integer;
variable a0753 : integer;
variable a0754 : integer;
variable a0755 : integer;
variable a0756 : integer;
variable a0757 : integer;
variable a0758 : integer;
variable a0759 : integer;
variable a0760 : integer;
variable a0761 : integer;
variable a0762 : integer;
variable a0763 : integer;
variable a0764 : integer;
variable a0765 : integer;
variable a0766 : integer;
variable a0767 : integer;
variable a0768 : integer;
variable a0769 : integer;
variable a0770 : integer;
variable a0771 : integer;
variable a0772 : integer;
variable a0773 : integer;
variable a0774 : integer;
variable a0775 : integer;
variable a0776 : integer;
variable a0777 : integer;
variable a0778 : integer;
variable a0779 : integer;
variable a0780 : integer;
variable a0781 : integer;
variable a0782 : integer;
variable a0783 : integer;
variable a0784 : integer;
variable a0785 : integer;
variable a0786 : integer;
variable a0787 : integer;
variable a0788 : integer;
variable a0789 : integer;
variable a0790 : integer;
variable a0791 : integer;
variable a0792 : integer;
variable a0793 : integer;
variable a0794 : integer;
variable a0795 : integer;
variable a0796 : integer;
variable a0797 : integer;
variable a0798 : integer;
variable a0799 : integer;
variable a0800 : integer;
variable a0801 : integer;
variable a0802 : integer;
variable a0803 : integer;
variable a0804 : integer;
variable a0805 : integer;
variable a0806 : integer;
variable a0807 : integer;
variable a0808 : integer;
variable a0809 : integer;
variable a0810 : integer;
variable a0811 : integer;
variable a0812 : integer;
variable a0813 : integer;
variable a0814 : integer;
variable a0815 : integer;
variable a0816 : integer;
variable a0817 : integer;
variable a0818 : integer;
variable a0819 : integer;
variable a0820 : integer;
variable a0821 : integer;
variable a0822 : integer;
variable a0823 : integer;
variable a0824 : integer;
variable a0825 : integer;
variable a0826 : integer;
variable a0827 : integer;
variable a0828 : integer;
variable a0829 : integer;
variable a0830 : integer;
variable a0831 : integer;
variable a0832 : integer;
variable a0833 : integer;
variable a0834 : integer;
variable a0835 : integer;
variable a0836 : integer;
variable a0837 : integer;
variable a0838 : integer;
variable a0839 : integer;
variable a0840 : integer;
variable a0841 : integer;
variable a0842 : integer;
variable a0843 : integer;
variable a0844 : integer;
variable a0845 : integer;
variable a0846 : integer;
variable a0847 : integer;
variable a0848 : integer;
variable a0849 : integer;
variable a0850 : integer;
variable a0851 : integer;
variable a0852 : integer;
variable a0853 : integer;
variable a0854 : integer;
variable a0855 : integer;
variable a0856 : integer;
variable a0857 : integer;
variable a0858 : integer;
variable a0859 : integer;
variable a0860 : integer;
variable a0861 : integer;
variable a0862 : integer;
variable a0863 : integer;
variable a0864 : integer;
variable a0865 : integer;
variable a0866 : integer;
variable a0867 : integer;
variable a0868 : integer;
variable a0869 : integer;
variable a0870 : integer;
variable a0871 : integer;
variable a0872 : integer;
variable a0873 : integer;
variable a0874 : integer;
variable a0875 : integer;
variable a0876 : integer;
variable a0877 : integer;
variable a0878 : integer;
variable a0879 : integer;
variable a0880 : integer;
variable a0881 : integer;
variable a0882 : integer;
variable a0883 : integer;
variable a0884 : integer;
variable a0885 : integer;
variable a0886 : integer;
variable a0887 : integer;
variable a0888 : integer;
variable a0889 : integer;
variable a0890 : integer;
variable a0891 : integer;
variable a0892 : integer;
variable a0893 : integer;
variable a0894 : integer;
variable a0895 : integer;
variable a0896 : integer;
variable a0897 : integer;
variable a0898 : integer;
variable a0899 : integer;
variable a0900 : integer;
variable a0901 : integer;
variable a0902 : integer;
variable a0903 : integer;
variable a0904 : integer;
variable a0905 : integer;
variable a0906 : integer;
variable a0907 : integer;
variable a0908 : integer;
variable a0909 : integer;
variable a0910 : integer;
variable a0911 : integer;
variable a0912 : integer;
variable a0913 : integer;
variable a0914 : integer;
variable a0915 : integer;
variable a0916 : integer;
variable a0917 : integer;
variable a0918 : integer;
variable a0919 : integer;
variable a0920 : integer;
variable a0921 : integer;
variable a0922 : integer;
variable a0923 : integer;
variable a0924 : integer;
variable a0925 : integer;
variable a0926 : integer;
variable a0927 : integer;
variable a0928 : integer;
variable a0929 : integer;
variable a0930 : integer;
variable a0931 : integer;
variable a0932 : integer;
variable a0933 : integer;
variable a0934 : integer;
variable a0935 : integer;
variable a0936 : integer;
variable a0937 : integer;
variable a0938 : integer;
variable a0939 : integer;
variable a0940 : integer;
variable a0941 : integer;
variable a0942 : integer;
variable a0943 : integer;
variable a0944 : integer;
variable a0945 : integer;
variable a0946 : integer;
variable a0947 : integer;
variable a0948 : integer;
variable a0949 : integer;
variable a0950 : integer;
variable a0951 : integer;
variable a0952 : integer;
variable a0953 : integer;
variable a0954 : integer;
variable a0955 : integer;
variable a0956 : integer;
variable a0957 : integer;
variable a0958 : integer;
variable a0959 : integer;
variable a0960 : integer;
variable a0961 : integer;
variable a0962 : integer;
variable a0963 : integer;
variable a0964 : integer;
variable a0965 : integer;
variable a0966 : integer;
variable a0967 : integer;
variable a0968 : integer;
variable a0969 : integer;
variable a0970 : integer;
variable a0971 : integer;
variable a0972 : integer;
variable a0973 : integer;
variable a0974 : integer;
variable a0975 : integer;
variable a0976 : integer;
variable a0977 : integer;
variable a0978 : integer;
variable a0979 : integer;
variable a0980 : integer;
variable a0981 : integer;
variable a0982 : integer;
variable a0983 : integer;
variable a0984 : integer;
variable a0985 : integer;
variable a0986 : integer;
variable a0987 : integer;
variable a0988 : integer;
variable a0989 : integer;
variable a0990 : integer;
variable a0991 : integer;
variable a0992 : integer;
variable a0993 : integer;
variable a0994 : integer;
variable a0995 : integer;
variable a0996 : integer;
variable a0997 : integer;
variable a0998 : integer;
variable a0999 : integer;
variable a1000 : integer;
begin
a0502 := 502;
a0503 := 503;
a0504 := 504;
a0505 := 505;
a0506 := 506;
a0507 := 507;
a0508 := 508;
a0509 := 509;
a0510 := 510;
a0511 := 511;
a0512 := 512;
a0513 := 513;
a0514 := 514;
a0515 := 515;
a0516 := 516;
a0517 := 517;
a0518 := 518;
a0519 := 519;
a0520 := 520;
a0521 := 521;
a0522 := 522;
a0523 := 523;
a0524 := 524;
a0525 := 525;
a0526 := 526;
a0527 := 527;
a0528 := 528;
a0529 := 529;
a0530 := 530;
a0531 := 531;
a0532 := 532;
a0533 := 533;
a0534 := 534;
a0535 := 535;
a0536 := 536;
a0537 := 537;
a0538 := 538;
a0539 := 539;
a0540 := 540;
a0541 := 541;
a0542 := 542;
a0543 := 543;
a0544 := 544;
a0545 := 545;
a0546 := 546;
a0547 := 547;
a0548 := 548;
a0549 := 549;
a0550 := 550;
a0551 := 551;
a0552 := 552;
a0553 := 553;
a0554 := 554;
a0555 := 555;
a0556 := 556;
a0557 := 557;
a0558 := 558;
a0559 := 559;
a0560 := 560;
a0561 := 561;
a0562 := 562;
a0563 := 563;
a0564 := 564;
a0565 := 565;
a0566 := 566;
a0567 := 567;
a0568 := 568;
a0569 := 569;
a0570 := 570;
a0571 := 571;
a0572 := 572;
a0573 := 573;
a0574 := 574;
a0575 := 575;
a0576 := 576;
a0577 := 577;
a0578 := 578;
a0579 := 579;
a0580 := 580;
a0581 := 581;
a0582 := 582;
a0583 := 583;
a0584 := 584;
a0585 := 585;
a0586 := 586;
a0587 := 587;
a0588 := 588;
a0589 := 589;
a0590 := 590;
a0591 := 591;
a0592 := 592;
a0593 := 593;
a0594 := 594;
a0595 := 595;
a0596 := 596;
a0597 := 597;
a0598 := 598;
a0599 := 599;
a0600 := 600;
a0601 := 601;
a0602 := 602;
a0603 := 603;
a0604 := 604;
a0605 := 605;
a0606 := 606;
a0607 := 607;
a0608 := 608;
a0609 := 609;
a0610 := 610;
a0611 := 611;
a0612 := 612;
a0613 := 613;
a0614 := 614;
a0615 := 615;
a0616 := 616;
a0617 := 617;
a0618 := 618;
a0619 := 619;
a0620 := 620;
a0621 := 621;
a0622 := 622;
a0623 := 623;
a0624 := 624;
a0625 := 625;
a0626 := 626;
a0627 := 627;
a0628 := 628;
a0629 := 629;
a0630 := 630;
a0631 := 631;
a0632 := 632;
a0633 := 633;
a0634 := 634;
a0635 := 635;
a0636 := 636;
a0637 := 637;
a0638 := 638;
a0639 := 639;
a0640 := 640;
a0641 := 641;
a0642 := 642;
a0643 := 643;
a0644 := 644;
a0645 := 645;
a0646 := 646;
a0647 := 647;
a0648 := 648;
a0649 := 649;
a0650 := 650;
a0651 := 651;
a0652 := 652;
a0653 := 653;
a0654 := 654;
a0655 := 655;
a0656 := 656;
a0657 := 657;
a0658 := 658;
a0659 := 659;
a0660 := 660;
a0661 := 661;
a0662 := 662;
a0663 := 663;
a0664 := 664;
a0665 := 665;
a0666 := 666;
a0667 := 667;
a0668 := 668;
a0669 := 669;
a0670 := 670;
a0671 := 671;
a0672 := 672;
a0673 := 673;
a0674 := 674;
a0675 := 675;
a0676 := 676;
a0677 := 677;
a0678 := 678;
a0679 := 679;
a0680 := 680;
a0681 := 681;
a0682 := 682;
a0683 := 683;
a0684 := 684;
a0685 := 685;
a0686 := 686;
a0687 := 687;
a0688 := 688;
a0689 := 689;
a0690 := 690;
a0691 := 691;
a0692 := 692;
a0693 := 693;
a0694 := 694;
a0695 := 695;
a0696 := 696;
a0697 := 697;
a0698 := 698;
a0699 := 699;
a0700 := 700;
a0701 := 701;
a0702 := 702;
a0703 := 703;
a0704 := 704;
a0705 := 705;
a0706 := 706;
a0707 := 707;
a0708 := 708;
a0709 := 709;
a0710 := 710;
a0711 := 711;
a0712 := 712;
a0713 := 713;
a0714 := 714;
a0715 := 715;
a0716 := 716;
a0717 := 717;
a0718 := 718;
a0719 := 719;
a0720 := 720;
a0721 := 721;
a0722 := 722;
a0723 := 723;
a0724 := 724;
a0725 := 725;
a0726 := 726;
a0727 := 727;
a0728 := 728;
a0729 := 729;
a0730 := 730;
a0731 := 731;
a0732 := 732;
a0733 := 733;
a0734 := 734;
a0735 := 735;
a0736 := 736;
a0737 := 737;
a0738 := 738;
a0739 := 739;
a0740 := 740;
a0741 := 741;
a0742 := 742;
a0743 := 743;
a0744 := 744;
a0745 := 745;
a0746 := 746;
a0747 := 747;
a0748 := 748;
a0749 := 749;
a0750 := 750;
a0751 := 751;
a0752 := 752;
a0753 := 753;
a0754 := 754;
a0755 := 755;
a0756 := 756;
a0757 := 757;
a0758 := 758;
a0759 := 759;
a0760 := 760;
a0761 := 761;
a0762 := 762;
a0763 := 763;
a0764 := 764;
a0765 := 765;
a0766 := 766;
a0767 := 767;
a0768 := 768;
a0769 := 769;
a0770 := 770;
a0771 := 771;
a0772 := 772;
a0773 := 773;
a0774 := 774;
a0775 := 775;
a0776 := 776;
a0777 := 777;
a0778 := 778;
a0779 := 779;
a0780 := 780;
a0781 := 781;
a0782 := 782;
a0783 := 783;
a0784 := 784;
a0785 := 785;
a0786 := 786;
a0787 := 787;
a0788 := 788;
a0789 := 789;
a0790 := 790;
a0791 := 791;
a0792 := 792;
a0793 := 793;
a0794 := 794;
a0795 := 795;
a0796 := 796;
a0797 := 797;
a0798 := 798;
a0799 := 799;
a0800 := 800;
a0801 := 801;
a0802 := 802;
a0803 := 803;
a0804 := 804;
a0805 := 805;
a0806 := 806;
a0807 := 807;
a0808 := 808;
a0809 := 809;
a0810 := 810;
a0811 := 811;
a0812 := 812;
a0813 := 813;
a0814 := 814;
a0815 := 815;
a0816 := 816;
a0817 := 817;
a0818 := 818;
a0819 := 819;
a0820 := 820;
a0821 := 821;
a0822 := 822;
a0823 := 823;
a0824 := 824;
a0825 := 825;
a0826 := 826;
a0827 := 827;
a0828 := 828;
a0829 := 829;
a0830 := 830;
a0831 := 831;
a0832 := 832;
a0833 := 833;
a0834 := 834;
a0835 := 835;
a0836 := 836;
a0837 := 837;
a0838 := 838;
a0839 := 839;
a0840 := 840;
a0841 := 841;
a0842 := 842;
a0843 := 843;
a0844 := 844;
a0845 := 845;
a0846 := 846;
a0847 := 847;
a0848 := 848;
a0849 := 849;
a0850 := 850;
a0851 := 851;
a0852 := 852;
a0853 := 853;
a0854 := 854;
a0855 := 855;
a0856 := 856;
a0857 := 857;
a0858 := 858;
a0859 := 859;
a0860 := 860;
a0861 := 861;
a0862 := 862;
a0863 := 863;
a0864 := 864;
a0865 := 865;
a0866 := 866;
a0867 := 867;
a0868 := 868;
a0869 := 869;
a0870 := 870;
a0871 := 871;
a0872 := 872;
a0873 := 873;
a0874 := 874;
a0875 := 875;
a0876 := 876;
a0877 := 877;
a0878 := 878;
a0879 := 879;
a0880 := 880;
a0881 := 881;
a0882 := 882;
a0883 := 883;
a0884 := 884;
a0885 := 885;
a0886 := 886;
a0887 := 887;
a0888 := 888;
a0889 := 889;
a0890 := 890;
a0891 := 891;
a0892 := 892;
a0893 := 893;
a0894 := 894;
a0895 := 895;
a0896 := 896;
a0897 := 897;
a0898 := 898;
a0899 := 899;
a0900 := 900;
a0901 := 901;
a0902 := 902;
a0903 := 903;
a0904 := 904;
a0905 := 905;
a0906 := 906;
a0907 := 907;
a0908 := 908;
a0909 := 909;
a0910 := 910;
a0911 := 911;
a0912 := 912;
a0913 := 913;
a0914 := 914;
a0915 := 915;
a0916 := 916;
a0917 := 917;
a0918 := 918;
a0919 := 919;
a0920 := 920;
a0921 := 921;
a0922 := 922;
a0923 := 923;
a0924 := 924;
a0925 := 925;
a0926 := 926;
a0927 := 927;
a0928 := 928;
a0929 := 929;
a0930 := 930;
a0931 := 931;
a0932 := 932;
a0933 := 933;
a0934 := 934;
a0935 := 935;
a0936 := 936;
a0937 := 937;
a0938 := 938;
a0939 := 939;
a0940 := 940;
a0941 := 941;
a0942 := 942;
a0943 := 943;
a0944 := 944;
a0945 := 945;
a0946 := 946;
a0947 := 947;
a0948 := 948;
a0949 := 949;
a0950 := 950;
a0951 := 951;
a0952 := 952;
a0953 := 953;
a0954 := 954;
a0955 := 955;
a0956 := 956;
a0957 := 957;
a0958 := 958;
a0959 := 959;
a0960 := 960;
a0961 := 961;
a0962 := 962;
a0963 := 963;
a0964 := 964;
a0965 := 965;
a0966 := 966;
a0967 := 967;
a0968 := 968;
a0969 := 969;
a0970 := 970;
a0971 := 971;
a0972 := 972;
a0973 := 973;
a0974 := 974;
a0975 := 975;
a0976 := 976;
a0977 := 977;
a0978 := 978;
a0979 := 979;
a0980 := 980;
a0981 := 981;
a0982 := 982;
a0983 := 983;
a0984 := 984;
a0985 := 985;
a0986 := 986;
a0987 := 987;
a0988 := 988;
a0989 := 989;
a0990 := 990;
a0991 := 991;
a0992 := 992;
a0993 := 993;
a0994 := 994;
a0995 := 995;
a0996 := 996;
a0997 := 997;
a0998 := 998;
a0999 := 999;
a1000 := 1000;
-- report "tick";
--}}}
end process;
terminator : process(clk)
begin
if clk >= CYCLES then
assert false report "end of simulation" severity failure;
-- else
-- report "tick";
end if;
end process;
clk <= (clk+1) after 1 us;
end;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:03:22 11/13/2015
-- Design Name:
-- Module Name: C:/Users/Gham/Desktop/Actual files/IDE/IDE3_final/IDE_READ/read_tb.vhd
-- Project Name: IDE_READ
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: read_circuit
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY read_tb IS
END read_tb;
ARCHITECTURE behavior OF read_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT read_circuit
PORT(
clk : IN std_logic;
reset : IN std_logic;
pa : IN std_logic;
sc : IN std_logic;
rd_cpu : IN std_logic;
rdy : OUT std_logic;
IOR : OUT std_logic;
data_bus : IN std_logic_vector(15 downto 0);
data_out_cpu : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal pa : std_logic := '0';
signal sc : std_logic := '0';
signal rd_cpu : std_logic := '0';
signal data_bus : std_logic_vector(15 downto 0) := (others => '0');
--Outputs
signal rdy : std_logic;
signal IOR : std_logic;
signal data_out_cpu : std_logic_vector(3 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: read_circuit PORT MAP (
clk => clk,
reset => reset,
pa => pa,
sc => sc,
rd_cpu => rd_cpu,
rdy => rdy,
IOR => IOR,
data_bus => data_bus,
data_out_cpu => data_out_cpu
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 10 ns;
reset <= '1';
wait for 10 ns;
reset <= '0';
wait for 10 ns;
pa <= '1';
sc <= '1';
wait for 10 ns;
rd_cpu<= '1';
wait for 10 ns;
data_bus<= "0001001000110100";
wait for 10 ns;
rd_cpu<= '0';
-- wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
|
-- megafunction wizard: %RAM: 2-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: RAM_1.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 14.0.0 Build 200 06/17/2014 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, the Altera Quartus II License Agreement,
--the Altera MegaCore Function License Agreement, or other
--applicable license agreement, including, without limitation,
--that your use is for the sole purpose of programming logic
--devices manufactured by Altera and sold by Altera or its
--authorized distributors. Please refer to the applicable
--agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY RAM_1 IS
PORT
(
aclr : IN STD_LOGIC := '0';
address_a : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (9 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END RAM_1;
ARCHITECTURE SYN OF ram_1 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (31 DOWNTO 0);
BEGIN
q_a <= sub_wire0(31 DOWNTO 0);
q_b <= sub_wire1(31 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
address_reg_b => "CLOCK0",
clock_enable_input_a => "BYPASS",
clock_enable_input_b => "BYPASS",
clock_enable_output_a => "BYPASS",
clock_enable_output_b => "BYPASS",
indata_reg_b => "CLOCK0",
init_file => "RAM_1.mif",
intended_device_family => "Cyclone IV E",
lpm_type => "altsyncram",
numwords_a => 1024,
numwords_b => 1024,
operation_mode => "BIDIR_DUAL_PORT",
outdata_aclr_a => "CLEAR0",
outdata_aclr_b => "CLEAR0",
outdata_reg_a => "UNREGISTERED",
outdata_reg_b => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_mixed_ports => "OLD_DATA",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
widthad_a => 10,
widthad_b => 10,
width_a => 32,
width_b => 32,
width_byteena_a => 1,
width_byteena_b => 1,
wrcontrol_wraddress_reg_b => "CLOCK0"
)
PORT MAP (
aclr0 => aclr,
address_a => address_a,
address_b => address_b,
clock0 => clock,
data_a => data_a,
data_b => data_b,
wren_a => wren_a,
wren_b => wren_b,
q_a => sub_wire0,
q_b => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
-- Retrieval info: PRIVATE: CLRq NUMERIC "1"
-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "32768"
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "RAM_1.mif"
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "1"
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "1"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
-- Retrieval info: PRIVATE: REGq NUMERIC "0"
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
-- Retrieval info: PRIVATE: REGrren NUMERIC "0"
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
-- Retrieval info: PRIVATE: VarWidth NUMERIC "0"
-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
-- Retrieval info: PRIVATE: enable NUMERIC "0"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
-- Retrieval info: CONSTANT: INIT_FILE STRING "RAM_1.mif"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "1024"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "CLEAR0"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "CLEAR0"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "OLD_DATA"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "10"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
-- Retrieval info: USED_PORT: address_a 0 0 10 0 INPUT NODEFVAL "address_a[9..0]"
-- Retrieval info: USED_PORT: address_b 0 0 10 0 INPUT NODEFVAL "address_b[9..0]"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data_a 0 0 32 0 INPUT NODEFVAL "data_a[31..0]"
-- Retrieval info: USED_PORT: data_b 0 0 32 0 INPUT NODEFVAL "data_b[31..0]"
-- Retrieval info: USED_PORT: q_a 0 0 32 0 OUTPUT NODEFVAL "q_a[31..0]"
-- Retrieval info: USED_PORT: q_b 0 0 32 0 OUTPUT NODEFVAL "q_b[31..0]"
-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
-- Retrieval info: CONNECT: @aclr0 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: CONNECT: @address_a 0 0 10 0 address_a 0 0 10 0
-- Retrieval info: CONNECT: @address_b 0 0 10 0 address_b 0 0 10 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 32 0 data_a 0 0 32 0
-- Retrieval info: CONNECT: @data_b 0 0 32 0 data_b 0 0 32 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
-- Retrieval info: CONNECT: q_a 0 0 32 0 @q_a 0 0 32 0
-- Retrieval info: CONNECT: q_b 0 0 32 0 @q_b 0 0 32 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_1.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_1.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL RAM_1_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
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|
-- Copyright (C) 1991-2011 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Quartus II 11.0 Build 157 04/27/2011
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Timing.all;
use work.hardcopyii_atom_pack.all;
package hardcopyii_components is
--
-- hardcopyii_ram_block
--
COMPONENT hardcopyii_ram_block
GENERIC (
operation_mode : STRING := "single_port";
mixed_port_feed_through_mode : STRING := "dont_care";
ram_block_type : STRING := "auto";
logical_ram_name : STRING := "ram_name";
init_file : STRING := "init_file.hex";
init_file_layout : STRING := "none";
data_interleave_width_in_bits : INTEGER := 1;
data_interleave_offset_in_bits : INTEGER := 1;
port_a_logical_ram_depth : INTEGER := 0;
port_a_logical_ram_width : INTEGER := 0;
port_a_first_address : INTEGER := 0;
port_a_last_address : INTEGER := 0;
port_a_first_bit_number : INTEGER := 0;
port_a_data_in_clear : STRING := "none";
port_a_address_clear : STRING := "none";
port_a_write_enable_clear : STRING := "none";
port_a_data_out_clear : STRING := "none";
port_a_byte_enable_clear : STRING := "none";
port_a_data_in_clock : STRING := "clock0";
port_a_address_clock : STRING := "clock0";
port_a_write_enable_clock : STRING := "clock0";
port_a_byte_enable_clock : STRING := "clock0";
port_a_data_out_clock : STRING := "none";
port_a_data_width : INTEGER := 1;
port_a_address_width : INTEGER := 1;
port_a_byte_enable_mask_width : INTEGER := 1;
port_b_logical_ram_depth : INTEGER := 0;
port_b_logical_ram_width : INTEGER := 0;
port_b_first_address : INTEGER := 0;
port_b_last_address : INTEGER := 0;
port_b_first_bit_number : INTEGER := 0;
port_b_data_in_clear : STRING := "none";
port_b_address_clear : STRING := "none";
port_b_read_enable_write_enable_clear: STRING := "none";
port_b_byte_enable_clear : STRING := "none";
port_b_data_out_clear : STRING := "none";
port_b_data_in_clock : STRING := "clock1";
port_b_address_clock : STRING := "clock1";
port_b_read_enable_write_enable_clock: STRING := "clock1";
port_b_byte_enable_clock : STRING := "clock1";
port_b_data_out_clock : STRING := "none";
port_b_data_width : INTEGER := 1;
port_b_address_width : INTEGER := 1;
port_b_byte_enable_mask_width : INTEGER := 1;
power_up_uninitialized : STRING := "false";
port_b_disable_ce_on_output_registers : STRING := "off";
port_b_disable_ce_on_input_registers : STRING := "off";
port_b_byte_size : INTEGER := 0;
port_a_disable_ce_on_output_registers : STRING := "off";
port_a_disable_ce_on_input_registers : STRING := "off";
port_a_byte_size : INTEGER := 0;
lpm_type : string := "hardcopyii_ram_block";
lpm_hint : string := "true";
mem_init0 : BIT_VECTOR := X"0";
mem_init1 : BIT_VECTOR := X"0";
connectivity_checking : string := "off"
);
PORT (
portadatain : IN STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portaaddr : IN STD_LOGIC_VECTOR(port_a_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portawe : IN STD_LOGIC := '0';
portbdatain : IN STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0) := (OTHERS => '0');
portbaddr : IN STD_LOGIC_VECTOR(port_b_address_width - 1 DOWNTO 0) := (OTHERS => '0');
portbrewe : IN STD_LOGIC := '0';
clk0 : IN STD_LOGIC := '0';
clk1 : IN STD_LOGIC := '0';
ena0 : IN STD_LOGIC := '1';
ena1 : IN STD_LOGIC := '1';
clr0 : IN STD_LOGIC := '0';
clr1 : IN STD_LOGIC := '0';
portabyteenamasks : IN STD_LOGIC_VECTOR(port_a_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
portbbyteenamasks : IN STD_LOGIC_VECTOR(port_b_byte_enable_mask_width - 1 DOWNTO 0) := (OTHERS => '1');
devclrn : IN STD_LOGIC := '1';
devpor : IN STD_LOGIC := '1';
portaaddrstall : IN STD_LOGIC := '0';
portbaddrstall : IN STD_LOGIC := '0';
portadataout : OUT STD_LOGIC_VECTOR(port_a_data_width - 1 DOWNTO 0);
portbdataout : OUT STD_LOGIC_VECTOR(port_b_data_width - 1 DOWNTO 0)
);
END COMPONENT;
--
-- hardcopyii_routing_wire
--
COMPONENT hardcopyii_routing_wire
generic (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
tpd_datain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_datainglitch_dataout : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01
);
PORT (
datain : in std_logic;
dataout : out std_logic
);
END COMPONENT;
--
-- hardcopyii_jtag
--
COMPONENT hardcopyii_jtag
generic (
lpm_type : string := "hardcopyii_jtag"
);
port (
tms : in std_logic := '0';
tck : in std_logic := '0';
tdi : in std_logic := '0';
ntrst : in std_logic := '0';
tdoutap : in std_logic := '0';
tdouser : in std_logic := '0';
tdo: out std_logic;
tmsutap: out std_logic;
tckutap: out std_logic;
tdiutap: out std_logic;
shiftuser: out std_logic;
clkdruser: out std_logic;
updateuser: out std_logic;
runidleuser: out std_logic;
usr1user: out std_logic
);
END COMPONENT;
--
-- hardcopyii_lcell_ff
--
COMPONENT hardcopyii_lcell_ff
generic (
x_on_violation : string := "on";
lpm_type : string := "hardcopyii_lcell_ff";
tsetup_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_adatasdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_datain_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_adatasdata_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sclr_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_sload_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_ena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aclr_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_aload_regout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_adatasdata_regout: VitalDelayType01 := DefPropDelay01;
tipd_clk : VitalDelayType01 := DefPropDelay01;
tipd_datain : VitalDelayType01 := DefPropDelay01;
tipd_adatasdata : VitalDelayType01 := DefPropDelay01;
tipd_sclr : VitalDelayType01 := DefPropDelay01;
tipd_sload : VitalDelayType01 := DefPropDelay01;
tipd_aclr : VitalDelayType01 := DefPropDelay01;
tipd_aload : VitalDelayType01 := DefPropDelay01;
tipd_ena : VitalDelayType01 := DefPropDelay01;
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*"
);
port (
datain : in std_logic := '0';
clk : in std_logic := '0';
aclr : in std_logic := '0';
aload : in std_logic := '0';
sclr : in std_logic := '0';
sload : in std_logic := '0';
ena : in std_logic := '1';
adatasdata : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
regout : out std_logic
);
END COMPONENT;
--
-- hardcopyii_lcell_comb
--
COMPONENT hardcopyii_lcell_comb
generic (
lut_mask : std_logic_vector(63 downto 0) := (OTHERS => '1');
shared_arith : string := "off";
extended_lut : string := "off";
lpm_type : string := "hardcopyii_lcell_comb";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_combout : VitalDelayType01 := DefPropDelay01;
tpd_datab_combout : VitalDelayType01 := DefPropDelay01;
tpd_datac_combout : VitalDelayType01 := DefPropDelay01;
tpd_datad_combout : VitalDelayType01 := DefPropDelay01;
tpd_datae_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_combout : VitalDelayType01 := DefPropDelay01;
tpd_datag_combout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datab_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datac_sumout : VitalDelayType01 := DefPropDelay01;
tpd_datad_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_sumout : VitalDelayType01 := DefPropDelay01;
tpd_cin_sumout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_sumout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataf_cout : VitalDelayType01 := DefPropDelay01;
tpd_cin_cout : VitalDelayType01 := DefPropDelay01;
tpd_sharein_cout : VitalDelayType01 := DefPropDelay01;
tpd_dataa_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datab_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datac_shareout : VitalDelayType01 := DefPropDelay01;
tpd_datad_shareout : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_datae : VitalDelayType01 := DefPropDelay01;
tipd_dataf : VitalDelayType01 := DefPropDelay01;
tipd_datag : VitalDelayType01 := DefPropDelay01;
tipd_cin : VitalDelayType01 := DefPropDelay01;
tipd_sharein : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '0';
datab : in std_logic := '0';
datac : in std_logic := '0';
datad : in std_logic := '0';
datae : in std_logic := '0';
dataf : in std_logic := '0';
datag : in std_logic := '0';
cin : in std_logic := '0';
sharein : in std_logic := '0';
combout : out std_logic;
sumout : out std_logic;
cout : out std_logic;
shareout : out std_logic
);
END COMPONENT;
--
-- hardcopyii_clkctrl
--
COMPONENT hardcopyii_clkctrl
generic (
clock_type : STRING := "Auto";
lpm_type : STRING := "hardcopyii_clkctrl";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(3 downto 0) := (OTHERS => DefPropDelay01);
tipd_clkselect : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01
);
port (
inclk : in std_logic_vector(3 downto 0) := "0000";
clkselect : in std_logic_vector(1 downto 0) := "00";
ena : in std_logic := '1';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
outclk : out std_logic
);
END COMPONENT;
--
-- hardcopyii_io
--
COMPONENT hardcopyii_io
generic (
operation_mode : string := "input";
ddio_mode : string := "none";
open_drain_output : string := "false";
bus_hold : string := "false";
output_register_mode : string := "none";
output_async_reset : string := "none";
output_power_up : string := "low";
output_sync_reset : string := "none";
tie_off_output_clock_enable : string := "false";
oe_register_mode : string := "none";
oe_async_reset : string := "none";
oe_power_up : string := "low";
oe_sync_reset : string := "none";
tie_off_oe_clock_enable : string := "false";
input_register_mode : string := "none";
input_async_reset : string := "none";
input_power_up : string := "low";
input_sync_reset : string := "none";
extend_oe_disable : string := "false";
dqs_input_frequency : string := "10000 ps";
dqs_out_mode : string := "none";
dqs_delay_buffer_mode : string := "low";
dqs_phase_shift : integer := 0;
inclk_input : string := "normal";
ddioinclk_input : string := "negated_inclk";
dqs_offsetctrl_enable : string := "false";
dqs_ctrl_latches_enable : string := "false";
dqs_edge_detect_enable : string := "false";
gated_dqs : string := "false";
sim_dqs_intrinsic_delay : integer := 0;
sim_dqs_delay_increment : integer := 0;
sim_dqs_offset_increment : integer := 0;
lpm_type : string := "hardcopyii_io"
);
port (
datain : in std_logic := '0';
ddiodatain : in std_logic := '0';
oe : in std_logic := '1';
outclk : in std_logic := '0';
outclkena : in std_logic := '1';
inclk : in std_logic := '0';
inclkena : in std_logic := '1';
areset : in std_logic := '0';
sreset : in std_logic := '0';
ddioinclk : in std_logic := '0';
delayctrlin : in std_logic_vector(5 downto 0) := "000000";
offsetctrlin : in std_logic_vector(5 downto 0) := "000000";
dqsupdateen : in std_logic := '0';
linkin : in std_logic := '0';
terminationcontrol : in std_logic_vector(13 downto 0) := "00000000000000";
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
devoe : in std_logic := '0';
padio : inout std_logic;
combout : out std_logic;
regout : out std_logic;
ddioregout : out std_logic;
dqsbusout : out std_logic;
linkout : out std_logic
);
END COMPONENT;
--
-- hardcopyii_pll
--
COMPONENT hardcopyii_pll
GENERIC (
operation_mode : string := "normal";
pll_type : string := "auto"; -- EGPP/FAST/AUTO
compensate_clock : string := "clk0";
feedback_source : string := "clk0";
qualify_conf_done : string := "off";
test_input_comp_delay : integer := 0;
test_feedback_comp_delay : integer := 0;
inclk0_input_frequency : integer := 10000;
inclk1_input_frequency : integer := 10000;
gate_lock_signal : string := "no";
gate_lock_counter : integer := 1;
self_reset_on_gated_loss_lock : string := "off";
valid_lock_multiplier : integer := 1;
invalid_lock_multiplier : integer := 5;
sim_gate_lock_device_behavior : string := "off";
switch_over_type : string := "auto";
switch_over_on_lossclk : string := "off";
switch_over_on_gated_lock : string := "off";
switch_over_counter : integer := 1;
enable_switch_over_counter : string := "on";
bandwidth : integer := 0;
bandwidth_type : string := "auto";
down_spread : string := "0.0";
spread_frequency : integer := 0;
clk0_output_frequency : integer := 0;
clk0_multiply_by : integer := 1;
clk0_divide_by : integer := 1;
clk0_phase_shift : string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency : integer := 0;
clk1_multiply_by : integer := 1;
clk1_divide_by : integer := 1;
clk1_phase_shift : string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency : integer := 0;
clk2_multiply_by : integer := 1;
clk2_divide_by : integer := 1;
clk2_phase_shift : string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency : integer := 0;
clk3_multiply_by : integer := 1;
clk3_divide_by : integer := 1;
clk3_phase_shift : string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency : integer := 0;
clk4_multiply_by : integer := 1;
clk4_divide_by : integer := 1;
clk4_phase_shift : string := "0";
clk4_duty_cycle : integer := 50;
clk5_output_frequency : integer := 0;
clk5_multiply_by : integer := 1;
clk5_divide_by : integer := 1;
clk5_phase_shift : string := "0";
clk5_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
m2 : integer := 1;
n2 : integer := 1;
ss : integer := 0;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
c5_high : integer := 1;
c5_low : integer := 1;
c5_initial : integer := 1;
c5_mode : string := "bypass";
c5_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "c0";
clk1_counter : string := "c1";
clk2_counter : string := "c2";
clk3_counter : string := "c3";
clk4_counter : string := "c4";
clk5_counter : string := "c5";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
c5_use_casc_in : string := "off";
m_test_source : integer := 5;
c0_test_source : integer := 5;
c1_test_source : integer := 5;
c2_test_source : integer := 5;
c3_test_source : integer := 5;
c4_test_source : integer := 5;
c5_test_source : integer := 5;
enable0_counter : string := "c0";
enable1_counter : string := "c1";
sclkout0_phase_shift : string := "0";
sclkout1_phase_shift : string := "0";
charge_pump_current : integer := 52;
loop_filter_r : string := " 1.000000";
loop_filter_c : integer := 16;
common_rx_tx : string := "off";
use_vco_bypass : string := "false";
use_dc_coupling : string := "false";
pll_compensation_delay : integer := 0;
simulation_type : string := "functional";
lpm_type : string := "hardcopyii_pll";
family_name : string := "StratixII";
clk0_use_even_counter_mode : string := "off";
clk1_use_even_counter_mode : string := "off";
clk2_use_even_counter_mode : string := "off";
clk3_use_even_counter_mode : string := "off";
clk4_use_even_counter_mode : string := "off";
clk5_use_even_counter_mode : string := "off";
clk0_use_even_counter_value : string := "off";
clk1_use_even_counter_value : string := "off";
clk2_use_even_counter_value : string := "off";
clk3_use_even_counter_value : string := "off";
clk4_use_even_counter_value : string := "off";
clk5_use_even_counter_value : string := "off";
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
scan_chain_mif_file : string := "";
vco_post_scale : integer := 1;
XOn : Boolean := DefGlitchXOn;
MsgOn : Boolean := DefGlitchMsgOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
TimingChecksOn : Boolean := true;
InstancePath : STRING := "*";
tipd_inclk : VitalDelayArrayType01(1 downto 0) := (OTHERS => DefPropDelay01);
tipd_ena : VitalDelayType01 := DefPropDelay01;
tipd_pfdena : VitalDelayType01 := DefPropDelay01;
tipd_areset : VitalDelayType01 := DefPropDelay01;
tipd_fbin : VitalDelayType01 := DefPropDelay01;
tipd_scanclk : VitalDelayType01 := DefPropDelay01;
tipd_scanread : VitalDelayType01 := DefPropDelay01;
tipd_scandata : VitalDelayType01 := DefPropDelay01;
tipd_scanwrite : VitalDelayType01 := DefPropDelay01;
tipd_clkswitch : VitalDelayType01 := DefPropDelay01;
tsetup_scandata_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_scandata_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanread_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_scanread_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_scanwrite_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_scanwrite_scanclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst
);
PORT
(
inclk : in std_logic_vector(1 downto 0);
fbin : in std_logic := '0';
ena : in std_logic := '1';
clkswitch : in std_logic := '0';
areset : in std_logic := '0';
pfdena : in std_logic := '1';
scanread : in std_logic := '0';
scanwrite : in std_logic := '0';
scandata : in std_logic := '0';
scanclk : in std_logic := '0';
testin : in std_logic_vector(3 downto 0) := "0000";
clk : out std_logic_vector(5 downto 0);
clkbad : out std_logic_vector(1 downto 0);
activeclock : out std_logic;
locked : out std_logic;
clkloss : out std_logic;
scandataout : out std_logic;
scandone : out std_logic;
testupout : out std_logic;
testdownout : out std_logic;
enable0 : out std_logic;
enable1 : out std_logic;
sclkout : out std_logic_vector(1 downto 0)
);
END COMPONENT;
--
-- hardcopyii_mac_mult
--
COMPONENT hardcopyii_mac_mult
GENERIC (
dataa_width : integer := 18;
datab_width : integer := 18;
dataa_clock : string := "none";
datab_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
round_clock : string := "none";
saturate_clock : string := "none";
output_clock : string := "none";
round_clear : string := "none";
saturate_clear : string := "none";
dataa_clear : string := "none";
datab_clear : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
output_clear : string := "none";
bypass_multiplier : string := "no";
mode_clock : string := "none";
zeroacc_clock : string := "none";
mode_clear : string := "none";
zeroacc_clear : string := "none";
signa_internally_grounded : string := "false";
signb_internally_grounded : string := "false";
lpm_hint : string := "true";
lpm_type : string := "hardcopyii_mac_mult";
dynamic_mode : string := "no");
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '1');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (others => '1');
scanina : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');
scaninb : IN std_logic_vector(datab_width-1 DOWNTO 0) := (others => '0');
sourcea : IN std_logic := '0';
sourceb : IN std_logic := '0';
signa : IN std_logic := '1';
signb : IN std_logic := '1';
round : IN std_logic := '0';
saturate : IN std_logic := '0';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
dataout : OUT std_logic_vector((dataa_width+datab_width)-1 DOWNTO 0) := (others => '0');
scanouta : OUT std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '0');
scanoutb : OUT std_logic_vector(datab_width-1 DOWNTO 0) := (others => '0');
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- hardcopyii_mac_out
--
COMPONENT hardcopyii_mac_out
GENERIC (
operation_mode : string := "output_only";
dataa_width : integer := 1;
datab_width : integer := 1;
datac_width : integer := 1;
datad_width : integer := 1;
dataout_width : integer := 144;
tmp_width : integer := 144;
addnsub0_clock : string := "none";
addnsub1_clock : string := "none";
zeroacc_clock : string := "none";
round0_clock : string := "none";
round1_clock : string := "none";
saturate_clock : string := "none";
multabsaturate_clock : string := "none";
multcdsaturate_clock : string := "none";
signa_clock : string := "none";
signb_clock : string := "none";
output_clock : string := "none";
addnsub0_clear : string := "none";
addnsub1_clear : string := "none";
zeroacc_clear : string := "none";
round0_clear : string := "none";
round1_clear : string := "none";
saturate_clear : string := "none";
multabsaturate_clear : string := "none";
multcdsaturate_clear : string := "none";
signa_clear : string := "none";
signb_clear : string := "none";
output_clear : string := "none";
addnsub0_pipeline_clock : string := "none";
addnsub1_pipeline_clock : string := "none";
round0_pipeline_clock : string := "none";
round1_pipeline_clock : string := "none";
saturate_pipeline_clock : string := "none";
multabsaturate_pipeline_clock : string := "none";
multcdsaturate_pipeline_clock : string := "none";
zeroacc_pipeline_clock : string := "none";
signa_pipeline_clock : string := "none";
signb_pipeline_clock : string := "none";
addnsub0_pipeline_clear : string := "none";
addnsub1_pipeline_clear : string := "none";
round0_pipeline_clear : string := "none";
round1_pipeline_clear : string := "none";
saturate_pipeline_clear : string := "none";
multabsaturate_pipeline_clear : string := "none";
multcdsaturate_pipeline_clear : string := "none";
zeroacc_pipeline_clear : string := "none";
signa_pipeline_clear : string := "none";
signb_pipeline_clear : string := "none";
mode0_clock : string := "none";
mode1_clock : string := "none";
zeroacc1_clock : string := "none";
saturate1_clock : string := "none";
output1_clock : string := "none";
output2_clock : string := "none";
output3_clock : string := "none";
output4_clock : string := "none";
output5_clock : string := "none";
output6_clock : string := "none";
output7_clock : string := "none";
mode0_clear : string := "none";
mode1_clear : string := "none";
zeroacc1_clear : string := "none";
saturate1_clear : string := "none";
output1_clear : string := "none";
output2_clear : string := "none";
output3_clear : string := "none";
output4_clear : string := "none";
output5_clear : string := "none";
output6_clear : string := "none";
output7_clear : string := "none";
mode0_pipeline_clock : string := "none";
mode1_pipeline_clock : string := "none";
zeroacc1_pipeline_clock : string := "none";
saturate1_pipeline_clock : string := "none";
mode0_pipeline_clear : string := "none";
mode1_pipeline_clear : string := "none";
zeroacc1_pipeline_clear : string := "none";
saturate1_pipeline_clear : string := "none";
dataa_forced_to_zero : string := "no";
datac_forced_to_zero : string := "no";
lpm_hint : string := "true";
lpm_type : string := "hardcopyii_mac_out");
PORT (
dataa : IN std_logic_vector(dataa_width-1 DOWNTO 0) := (others => '1');
datab : IN std_logic_vector(datab_width-1 DOWNTO 0) := (others => '1');
datac : IN std_logic_vector(datac_width-1 DOWNTO 0) := (others => '1');
datad : IN std_logic_vector(datad_width-1 DOWNTO 0) := (others => '1');
zeroacc : IN std_logic := '0';
addnsub0 : IN std_logic := '1';
addnsub1 : IN std_logic := '1';
round0 : IN std_logic := '0';
round1 : IN std_logic := '0';
saturate : IN std_logic := '0';
multabsaturate : IN std_logic := '0';
multcdsaturate : IN std_logic := '0';
signa : IN std_logic := '1';
signb : IN std_logic := '1';
clk : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
aclr : IN std_logic_vector(3 DOWNTO 0) := (others => '0');
ena : IN std_logic_vector(3 DOWNTO 0) := (others => '1');
dataout : OUT std_logic_vector(dataout_width -1 DOWNTO 0) := (others => '0');
accoverflow : OUT std_logic := '0';
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- hardcopyii_lvds_transmitter
--
COMPONENT hardcopyii_lvds_transmitter
GENERIC ( channel_width : integer := 10;
bypass_serializer : String := "false";
invert_clock : String := "false";
use_falling_clock_edge : String := "false";
use_serial_data_input : String := "false";
use_post_dpa_serial_data_input : String := "false";
preemphasis_setting : integer := 0;
vod_setting : integer := 0;
differential_drive : integer := 0;
lpm_type : string := "hardcopyii_lvds_transmitter";
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_clk0_dataout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_clk0_dataout_negedge : VitalDelayType01 := DefPropDelay01;
tpd_serialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tpd_postdpaserialdatain_dataout : VitalDelayType01 := DefPropDelay01;
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayArrayType01(9 downto 0) := (OTHERS => DefpropDelay01);
tipd_serialdatain : VitalDelayType01 := DefpropDelay01;
tipd_postdpaserialdatain : VitalDelayType01 := DefpropDelay01
);
PORT ( clk0 : in std_logic;
enable0 : in std_logic := '0';
datain : in std_logic_vector(channel_width - 1 downto 0) := (OTHERS => '0');
serialdatain : in std_logic := '0';
postdpaserialdatain : in std_logic := '0';
devclrn : in std_logic := '1';
devpor : in std_logic := '1';
dataout : out std_logic;
serialfdbkout : out std_logic
);
END COMPONENT;
--
-- hardcopyii_lvds_receiver
--
COMPONENT hardcopyii_lvds_receiver
GENERIC ( channel_width : integer := 10;
data_align_rollover : integer := 2;
enable_dpa : string := "off";
lose_lock_on_one_change : string := "off";
reset_fifo_at_first_lock : string := "on";
align_to_rising_edge_only : string := "on";
use_serial_feedback_input : string := "off";
dpa_debug : string := "off";
x_on_bitslip : string := "on";
lpm_type : string := "hardcopyii_lvds_receiver";
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tipd_clk0 : VitalDelayType01 := DefpropDelay01;
tipd_datain : VitalDelayType01 := DefpropDelay01;
tipd_enable0 : VitalDelayType01 := DefpropDelay01;
tipd_dpareset : VitalDelayType01 := DefpropDelay01;
tipd_dpahold : VitalDelayType01 := DefpropDelay01;
tipd_dpaswitch : VitalDelayType01 := DefpropDelay01;
tipd_fiforeset : VitalDelayType01 := DefpropDelay01;
tipd_bitslip : VitalDelayType01 := DefpropDelay01;
tipd_bitslipreset : VitalDelayType01 := DefpropDelay01;
tipd_serialfbk : VitalDelayType01 := DefpropDelay01;
tpd_clk0_dpalock_posedge : VitalDelayType01 := DefPropDelay01
);
PORT ( clk0 : IN std_logic;
datain : IN std_logic := '0';
enable0 : IN std_logic := '0';
dpareset : IN std_logic := '0';
dpahold : IN std_logic := '0';
dpaswitch : IN std_logic := '0';
fiforeset : IN std_logic := '0';
bitslip : IN std_logic := '0';
bitslipreset : IN std_logic := '0';
serialfbk : IN std_logic := '0';
dataout : OUT std_logic_vector(channel_width - 1 DOWNTO 0);
dpalock : OUT std_logic;
bitslipmax : OUT std_logic;
serialdataout : OUT std_logic;
postdpaserialdataout : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- hardcopyii_dll
--
COMPONENT hardcopyii_dll
GENERIC (
input_frequency : string := "10000 ps";
delay_chain_length : integer := 16;
delay_buffer_mode : string := "low";
delayctrlout_mode : string := "normal";
static_delay_ctrl : integer := 0;
offsetctrlout_mode : string := "static";
static_offset : string := "0";
jitter_reduction : string := "false";
use_upndnin : string := "false";
use_upndninclkena : string := "false";
sim_valid_lock : integer := 1;
sim_loop_intrinsic_delay : integer := 1000;
sim_loop_delay_increment : integer := 100;
sim_valid_lockcount : integer := 90; -- 10000 = 1000 + 100*dllcounter
lpm_type : string := "hardcopyii_dll";
tipd_clk : VitalDelayType01 := DefpropDelay01;
tipd_aload : VitalDelayType01 := DefpropDelay01;
tipd_offset : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01);
tipd_upndnin : VitalDelayType01 := DefpropDelay01;
tipd_upndninclkena : VitalDelayType01 := DefpropDelay01;
tipd_addnsub : VitalDelayType01 := DefpropDelay01;
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_offset_delayctrlout : VitalDelayType01 := DefPropDelay01;
tpd_clk_upndnout_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
thold_offset_clk_noedge_posedge : VitalDelayArrayType(5 downto 0) := (OTHERS => DefSetupHoldCnst);
tsetup_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndnin_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_upndninclkena_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_addnsub_clk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tpd_clk_delayctrlout_posedge : VitalDelayArrayType01(5 downto 0) := (OTHERS => DefPropDelay01)
);
PORT ( clk : IN std_logic := '0';
aload : IN std_logic := '0';
offset : IN std_logic_vector(5 DOWNTO 0) := "000000";
upndnin : IN std_logic := '1';
upndninclkena : IN std_logic := '1';
addnsub : IN std_logic := '1';
delayctrlout : OUT std_logic_vector(5 DOWNTO 0);
offsetctrlout : OUT std_logic_vector(5 DOWNTO 0);
dqsupdate : OUT std_logic;
upndnout : OUT std_logic;
devclrn : IN std_logic := '1';
devpor : IN std_logic := '1'
);
END COMPONENT;
--
-- hardcopyii_termination
--
COMPONENT hardcopyii_termination
GENERIC (
runtime_control : string := "false";
use_core_control : string := "false";
pullup_control_to_core : string := "true";
use_high_voltage_compare : string := "true";
use_both_compares : string := "false";
pullup_adder : integer := 0;
pulldown_adder : integer := 0;
half_rate_clock : string := "false";
power_down : string := "true";
left_shift : string := "false";
test_mode : string := "false";
lpm_type : string := "hardcopyii_termination";
tipd_rup : VitalDelayType01 := DefpropDelay01;
tipd_rdn : VitalDelayType01 := DefpropDelay01;
tipd_terminationclock : VitalDelayType01 := DefpropDelay01;
tipd_terminationclear : VitalDelayType01 := DefpropDelay01;
tipd_terminationenable : VitalDelayType01 := DefpropDelay01;
tipd_terminationpullup : VitalDelayArrayType01(6 downto 0) := (OTHERS => DefPropDelay01);
tipd_terminationpulldown : VitalDelayArrayType01(6 downto 0) := (OTHERS => DefPropDelay01);
TimingChecksOn : Boolean := True;
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
tpd_terminationclock_terminationcontrol_posedge : VitalDelayArrayType01(13 downto 0) := (OTHERS => DefPropDelay01);
tpd_terminationclock_terminationcontrolprobe_posedge : VitalDelayArrayType01(6 downto 0) := (OTHERS => DefPropDelay01)
);
PORT (
rup : IN std_logic := '0';
rdn : IN std_logic := '0';
terminationclock : IN std_logic := '0';
terminationclear : IN std_logic := '0';
terminationenable : IN std_logic := '1';
terminationpullup : IN std_logic_vector(6 DOWNTO 0) := "0000000";
terminationpulldown : IN std_logic_vector(6 DOWNTO 0) := "0000000";
devclrn : IN std_logic := '1';
devpor : IN std_logic := '0';
incrup : OUT std_logic;
incrdn : OUT std_logic;
terminationcontrol : OUT std_logic_vector(13 DOWNTO 0);
terminationcontrolprobe : OUT std_logic_vector(6 DOWNTO 0)
);
END COMPONENT;
--
-- hardcopyii_lcell_hsadder
--
COMPONENT hardcopyii_lcell_hsadder
generic (
use_cin1_for_sumout : string := "on";
lpm_type : string := "hardcopyii_lcell_hsadder";
TimingChecksOn: Boolean := True;
MsgOn: Boolean := DefGlitchMsgOn;
XOn: Boolean := DefGlitchXOn;
MsgOnChecks: Boolean := DefMsgOnChecks;
XOnChecks: Boolean := DefXOnChecks;
InstancePath: STRING := "*";
tpd_dataa_sumout0 : VitalDelayType01 := DefPropDelay01;
tpd_datab_sumout0 : VitalDelayType01 := DefPropDelay01;
tpd_cin0_sumout0 : VitalDelayType01 := DefPropDelay01;
tpd_cin1_sumout0 : VitalDelayType01 := DefPropDelay01;
tpd_dataa_sumout1 : VitalDelayType01 := DefPropDelay01;
tpd_datab_sumout1 : VitalDelayType01 := DefPropDelay01;
tpd_datac_sumout1 : VitalDelayType01 := DefPropDelay01;
tpd_datad_sumout1 : VitalDelayType01 := DefPropDelay01;
tpd_cin0_sumout1 : VitalDelayType01 := DefPropDelay01;
tpd_cin1_sumout1 : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_cin0_cout0 : VitalDelayType01 := DefPropDelay01;
tpd_dataa_cout1 : VitalDelayType01 := DefPropDelay01;
tpd_datab_cout1 : VitalDelayType01 := DefPropDelay01;
tpd_datac_cout1 : VitalDelayType01 := DefPropDelay01;
tpd_datad_cout1 : VitalDelayType01 := DefPropDelay01;
tpd_cin0_cout1 : VitalDelayType01 := DefPropDelay01;
tipd_dataa : VitalDelayType01 := DefPropDelay01;
tipd_datab : VitalDelayType01 := DefPropDelay01;
tipd_datac : VitalDelayType01 := DefPropDelay01;
tipd_datad : VitalDelayType01 := DefPropDelay01;
tipd_cin0 : VitalDelayType01 := DefPropDelay01;
tipd_cin1 : VitalDelayType01 := DefPropDelay01
);
port (
dataa : in std_logic := '0';
datab : in std_logic := '0';
datac : in std_logic := '0';
datad : in std_logic := '0';
cin0 : in std_logic := '0';
cin1 : in std_logic := '0';
sumout0 : out std_logic;
sumout1 : out std_logic;
cout0 : out std_logic;
cout1 : out std_logic
);
END COMPONENT;
end hardcopyii_components;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.ddrpkg.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.net.all;
use gaisler.jtag.all;
library esa;
use esa.memoryctrl.all;
use work.ft245.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
-- RESET, CLK, ERROR
resetn : in std_ulogic;
clk : in std_ulogic;
errorn : out std_ulogic;
-- combined flash/SSRAM/IO bus (fs_...)
fs_addr : out std_logic_vector(24 downto 0);
fs_data : inout std_logic_vector(31 downto 0);
-- IO chip enable
io_cen : out std_logic;
io_wen : out std_logic;
-- separate flash signals (flash_...)
flash_cen : out std_ulogic;
flash_oen : out std_logic;
flash_wen : out std_logic;
-- separate SSRAM signals (ssram_...)
ssram_cen : out std_logic;
ssram_wen : out std_logic;
ssram_bw : out std_logic_vector (3 downto 0);
ssram_oen : out std_ulogic;
ssram_clk : out std_ulogic;
ssram_adscn : out std_ulogic;
ssram_adspn : out std_ulogic;
ssram_advn : out std_ulogic;
-- DDR2
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_odt : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (7 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (7 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (63 downto 0); -- ddr data
-- ETHERNET PHY
phy_gtx_clk : out std_logic;
phy_mii_data: inout std_logic; -- ethernet PHY interface
phy_tx_clk : in std_ulogic;
phy_rx_clk : in std_ulogic;
phy_rx_data : in std_logic_vector(7 downto 0);
phy_dv : in std_ulogic;
phy_rx_er : in std_ulogic;
phy_col : in std_ulogic;
phy_crs : in std_ulogic;
phy_tx_data : out std_logic_vector(7 downto 0);
phy_tx_en : out std_ulogic;
phy_tx_er : out std_ulogic;
phy_mii_clk : out std_ulogic;
-- debug support unit
dsuact : out std_ulogic;
-- console/debug UART
rxd1 : in std_logic;
txd1 : out std_logic;
-- FT245 UART
ft245_data : inout std_logic_vector (7 downto 0);
ft245_rdn : out std_logic;
ft245_wr : out std_logic;
ft245_rxfn : in std_logic;
ft245_txen : in std_logic;
ft245_pwrenn : in std_logic;
-- GPIO
gpio : inout std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0)
);
end;
architecture rtl of leon3mp is
constant maxahbm : integer := NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH;
signal vcc, gnd : std_logic_vector(7 downto 0);
signal memi, smemi : memory_in_type;
signal memo, smemo : memory_out_type;
signal wpo : wprot_out_type;
signal ddrclkfb, ssrclkfb, ddr_clkl, ddr_clk90l, ddr_clknl, ddr_clk270l : std_ulogic;
signal ddr_clkv : std_logic_vector(2 downto 0);
signal ddr_clkbv : std_logic_vector(2 downto 0);
signal ddr_ckev : std_logic_vector(1 downto 0);
signal ddr_csbv : std_logic_vector(1 downto 0);
signal ddr_adl : std_logic_vector (13 downto 0);
signal clklock, lock, clkml, rst, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal ddrclk, ddrrst : std_ulogic;
-- attribute syn_keep : boolean;
-- attribute syn_preserve : boolean;
-- attribute syn_keep of clkml : signal is true;
-- attribute syn_preserve of clkml : signal is true;
signal extd : std_logic_vector(31 downto 0);
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector;
signal clkm, rstn, ssram_clkl : std_ulogic;
signal cgi : clkgen_in_type;
signal cgo : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi : eth_in_type;
signal etho : eth_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal ft245i : ft245_in_type;
signal ft245o : ft245_out_type;
signal ft245_vbdrive : std_logic_vector(7 downto 0);
constant IOAEN : integer := 1;
constant BOARD_FREQ : integer := 100000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= not resetn; cgi.pllref <= '0';
clklock <= cgo.clklock and lock;
clkgen0 : clkgen -- clock generator for main clock
generic map (tech => CFG_CLKTECH, clk_mul => CFG_CLKMUL, clk_div => CFG_CLKDIV,
sdramen => CFG_MCTRL_SDEN, pcien => 0, pcidll => 0,
freq => BOARD_FREQ, clk2xen => 0, clksel => 0, clk_odiv => 0)
port map (clkin => clk, pciclkin => gnd(0), clk => clkm, clkn => ssram_clkl,
clk2x => open, sdclk => open, pciclk => open,
cgi => cgi, cgo => cgo);
-- ssram_clkl <= not clkm;
ssrclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (ssram_clk, ssram_clkl);
rst0 : rstgen -- reset generator
port map (resetn, clkm, clklock, rstn);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsui.break <= '0';
dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0 : ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 4, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(4), ahbmi, ahbmo(NCPU));
dsurx_pad : inpad generic map (tech => padtech) port map (rxd1, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech) port map (txd1, duo.txd);
end generate;
nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
mctrl0 : if CFG_MCTRL_LEON2 = 1 generate
mctrl0 : mctrl generic map (hindex => 0, pindex => 0,
romaddr => 16#000#, rommask => 16#E00#,
ioaddr => 16#200#, iomask => 16#E00#,
ramaddr => 16#C00#, rammask => 16#F00#,
paddr => 0, pmask => 16#FFF#,
srbanks => 1, wprot => 0,
ram8 => CFG_MCTRL_RAM8BIT, ram16 => CFG_MCTRL_RAM16BIT,
sden => CFG_MCTRL_SDEN,
invclk => CFG_MCTRL_INVCLK, sepbus => CFG_MCTRL_SEPBUS)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, open);
end generate;
memi.brdyn <= '1'; memi.bexcn <= '1';
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
mg0 : if CFG_MCTRL_LEON2 = 0 generate -- no prom/sram pads
apbo(0) <= apb_none; ahbso(0) <= ahbs_none;
rom_sel_pad : outpad generic map (tech => padtech)
port map (flash_cen, vcc(0));
ssram_sel_pad : outpad generic map (tech => padtech)
port map (ssram_cen, vcc(0));
io_sel_pad : outpad generic map (tech => padtech)
port map (io_cen, vcc(0));
end generate;
mgpads : if CFG_MCTRL_LEON2 = 1 generate
-- flash/ssram data/address pads
fsaddr_pad : outpadv generic map (width => 25, tech => padtech)
port map (fs_addr, memo.address(25 downto 1));
fsdata_pad : iopadvv generic map (width => 32, tech => padtech)
port map (fs_data, memo.data, memo.vbdrive, memi.data);
-- flash only pads
rom_sel_pad : outpad generic map (tech => padtech)
port map (flash_cen, memo.romsn(0));
rom_oen_pad : outpad generic map (tech => padtech)
port map (flash_oen, memo.oen);
rom_wri_pad : outpad generic map (tech => padtech)
port map (flash_wen, memo.writen);
-- ssram only pads
ssram_adv_n_pad : outpad generic map (tech => padtech)
port map (ssram_advn, vcc(0));
ssram_adsp_n_pad : outpad generic map (tech => padtech)
port map (ssram_adspn, vcc(0));
ssram_adscn_pad : outpad generic map (tech => padtech)
port map (ssram_adscn, gnd(0));
ssram_sel_pad : outpad generic map ( tech => padtech)
port map (ssram_cen, memo.ramsn(0));
ssram_oen_pad : outpad generic map (tech => padtech)
port map (ssram_oen, memo.ramoen(0));
ssram_wen_pad : outpad generic map (tech => padtech)
port map (ssram_wen, memo.wrn(0));
ssram_bw_pad : outpadv generic map (width => 4, tech => padtech)
port map (ssram_bw, memo.mben);
-- io data
io_sel_pad : outpad generic map (tech => padtech)
port map (io_cen, memo.iosn);
io_wri_pad : outpad generic map (tech => padtech)
port map (io_wen, memo.writen);
end generate;
ddrsp0 : if (CFG_DDR2SP /= 0) generate
ddrc0 : ddr2spa generic map ( fabtech => fabtech, memtech => memtech,
hindex => 3, haddr => 16#400#, hmask => 16#C00#, ioaddr => 1,
pwron => CFG_DDR2SP_INIT, MHz => BOARD_FREQ/1000,
clkmul => CFG_DDR2SP_FREQ/10, clkdiv => BOARD_FREQ/10000,
ahbfreq => CPU_FREQ/1000, col => CFG_DDR2SP_COL,
Mbyte => CFG_DDR2SP_SIZE, ddrbits => 64, readdly => 1,
ddelayb0 => CFG_DDR2SP_DELAY0, ddelayb1 => CFG_DDR2SP_DELAY1,
ddelayb2 => CFG_DDR2SP_DELAY2, ddelayb3 => CFG_DDR2SP_DELAY3,
ddelayb4 => CFG_DDR2SP_DELAY4, ddelayb5 => CFG_DDR2SP_DELAY5,
ddelayb6 => CFG_DDR2SP_DELAY6, ddelayb7 => CFG_DDR2SP_DELAY7,
numidelctrl => 3, norefclk => 1, odten => 1, dqsse => 1)
port map ( rst_ddr => resetn, rst_ahb => rstn, clk_ddr => clk, clk_ahb => clkm, clkref200 => gnd(0),
lock => lock, clkddro => clkml, clkddri => clkml, ahbsi => ahbsi, ahbso => ahbso(3),
ddr_clk => ddr_clkv, ddr_clkb => ddr_clkbv, ddr_clk_fb => gnd(0), ddr_cke => ddr_ckev,
ddr_csb => ddr_csbv, ddr_web => ddr_web, ddr_rasb => ddr_rasb, ddr_casb => ddr_casb,
ddr_dm => ddr_dm, ddr_dqs => ddr_dqs, ddr_dqsn => open, ddr_ad => ddr_ad, ddr_ba => ddr_ba,
ddr_dq => ddr_dq, ddr_odt => ddr_odt);
ddr_clk <= ddr_clkv(2 downto 0); ddr_clkb <= ddr_clkbv(2 downto 0);
ddr_cke <= ddr_ckev(1 downto 0); ddr_csb <= ddr_csbv(1 downto 0);
end generate;
noddr : if (CFG_DDR2SP = 0) generate
ddr_cke <= (others => '0'); ddr_csb <= (others => '1'); lock <= '1';
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth1 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(hindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
pindex => 11, paddr => 11, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 18,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG),
apbi => apbi, apbo => apbo(11), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (phy_mii_data, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : inpad generic map (tech => padtech)
port map (phy_tx_clk, ethi.tx_clk);
erxc_pad : inpad generic map (tech => padtech)
port map (phy_rx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 8)
port map (phy_rx_data, ethi.rxd(7 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (phy_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (phy_rx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (phy_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (phy_crs, ethi.rx_crs);
etxd_pad : outpadv generic map (tech => padtech, width => 8)
port map (phy_tx_data, etho.txd(7 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( phy_tx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (phy_tx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (phy_mii_clk, etho.mdc);
end generate;
----------------------------------------------------------------------
--- APB Bridge and various peripherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
ua1 : if CFG_UART1_ENABLE = 1 generate
uart1 : ft245uart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart)
port map (rstn, clkm, apbi, apbo(1), ft245i, ft245o);
ft245_vbdrive <= (others => ft245o.oen);
ft245_data_pad : iopadvv generic map (width => 8, tech => padtech)
port map (ft245_data, ft245o.wrdata, ft245_vbdrive, ft245i.rddata);
ft245_rdn_pad : outpad generic map (tech => padtech)
port map (ft245_rdn, ft245o.rdn);
ft245_wr_pad : outpad generic map (tech => padtech)
port map (ft245_wr, ft245o.wr);
ft245_rxfn_pad : inpad generic map (tech => padtech)
port map (ft245_rxfn, ft245i.rxfn);
ft245_txen_pad : inpad generic map (tech => padtech)
port map (ft245_txen, ft245i.txen);
ft245_pwrenn_pad : inpad generic map (tech => padtech)
port map (ft245_pwrenn, ft245i.pwrenn);
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti <= gpti_dhalt_drive(dsuo.tstop);
end generate;
notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 5, paddr => 5, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(5),
gpioi => gpioi, gpioo => gpioo);
pio_pads : for i in 0 to CFG_GRGPIO_WIDTH-1 generate
pio_pad : iopad generic map (tech => padtech)
port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
nobpromgen : if CFG_AHBROMEN = 0 generate
ahbso(6) <= ahbs_none;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ahbramgen : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ,
pipe => CFG_AHBRPIPE)
port map (rstn, clkm, ahbsi, ahbso(7));
end generate;
nram : if CFG_AHBRAMEN = 0 generate ahbso(7) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_GRETH) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-- nap0 : for i in 6 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 7 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Altera EP2SGX90 SSRAM/DDR Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library ftl;
use ftl.ftlbase.all;
use work.comp_tslink_ct.all;
entity tslink is
port (
clk : in std_ulogic;
rst : in std_ulogic;
LinkIn : in std_ulogic;
IValid : in std_ulogic;
QAck : in std_ulogic;
IData : in std_logic_vector(7 downto 0);
IAck : out std_ulogic;
QData : out std_logic_vector(7 downto 0);
LinkOut : out std_ulogic;
QValid : out std_ulogic
);
end entity;
architecture rtl of tslink is
signal ShiftEnable : std_ulogic;
signal s_qdata : std_logic_vector(7 downto 0);
begin
ct: tslink_ct
port map (
clk, -- : in std_ulogic;
rst, -- : in std_ulogic;
LinkIn, -- : in std_ulogic;
IValid, -- : in std_ulogic;
QAck, -- : in std_ulogic;
IData, -- : in std_logic_vector(7 downto 0);
IAck, -- : out std_ulogic;
ShiftEnable, -- : out std_ulogic;
LinkOut, -- : out std_ulogic;
QValid -- : out std_ulogic
);
shifter: process (clk)
begin
if rising_edge(clk) then
if rst='1' then
s_qdata <= (others => '0');
else
if ShiftEnable='1' then
s_qdata <= LinkIn & s_qdata(7 downto 1);
end if;
end if;
end if;
end process;
QData <= s_qdata;
end architecture rtl;
------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library ftl;
use ftl.ftlbase.all;
use work.comp_tslink_ct.all;
entity tb2 is
end entity;
architecture arch of tb2 is
component tslink is
port (
clk : in std_ulogic;
rst : in std_ulogic;
LinkIn : in std_ulogic;
IValid : in std_ulogic;
QAck : in std_ulogic;
IData : in std_logic_vector(7 downto 0);
IAck : out std_ulogic;
QData : out std_logic_vector(7 downto 0);
LinkOut : out std_ulogic;
QValid : out std_ulogic
);
end component;
signal eos : boolean := false;
signal clk : std_ulogic;
signal rst : std_ulogic;
signal LinkIn : std_ulogic;
signal LinkOut : std_ulogic;
signal IValid_1 : std_ulogic;
signal QAck_1 : std_ulogic;
signal IData_1 : std_logic_vector(7 downto 0);
signal IAck_1 : std_ulogic;
signal QData_1 : std_logic_vector(7 downto 0);
signal QValid_1 : std_ulogic;
signal IValid_2 : std_ulogic;
signal QAck_2 : std_ulogic;
signal IData_2 : std_logic_vector(7 downto 0);
signal IAck_2 : std_ulogic;
signal QData_2 : std_logic_vector(7 downto 0);
signal QValid_2 : std_ulogic;
begin
dut1: tslink
port map (
clk, -- : in std_ulogic;
rst, -- : in std_ulogic;
LinkIn, -- : in std_ulogic;
IValid_1, -- : in std_ulogic;
QAck_1, -- : in std_ulogic;
IData_1, -- : in std_logic_vector(7 downto 0);
IAck_1, -- : out std_ulogic;
QData_1,
LinkOut, -- : out std_ulogic;
QValid_1 -- : out std_ulogic
);
dut2: tslink
port map (
clk, -- : in std_ulogic;
rst, -- : in std_ulogic;
LinkOut, -- : in std_ulogic;
IValid_2, -- : in std_ulogic;
QAck_2, -- : in std_ulogic;
IData_2, -- : in std_logic_vector(7 downto 0);
IAck_2, -- : out std_ulogic;
QData_2,
LinkIn, -- : out std_ulogic;
QValid_2 -- : out std_ulogic
);
clkgen: process
begin
clk <= '0'; wait for 5 ns; clk <= '1'; wait for 5 ns; clk <= '0';
if eos then
wait;
end if;
end process;
tb1: process
begin
rst <= '1';
IValid_1 <= '0';
QAck_1 <= '0';
IData_1 <= x"00";
wait until rising_edge(clk);
rst <= '0';
wait until rising_edge(clk);
IData_1 <= x"A5";
IValid_1 <= '1';
wait until rising_edge(clk) and IAck_1='1';
IValid_1 <= '0';
wait until rising_edge(clk) and QValid_1='1';
QAck_1 <= '1';
wait until rising_edge(clk);
QAck_1 <= '0';
wait until rising_edge(clk);
IData_1 <= x"12";
IValid_1 <= '1';
wait until rising_edge(clk) and QValid_1='1';
QAck_1 <= '1';
wait until rising_edge(clk) and IAck_1='1';
IValid_1 <= '0';
QAck_1 <= '0';
wait for 30 ns;
eos <= true;
wait;
end process;
tb2: process
begin
IValid_2 <= '0';
QAck_2 <= '0';
IData_2 <= x"00";
wait until rising_edge(clk);
wait until rising_edge(clk);
wait until rising_edge(clk) and QValid_2='1';
QAck_2 <= '1';
wait until rising_edge(clk);
QAck_2 <= '0';
IData_2 <= x"5A";
IValid_2 <= '1';
wait until rising_edge(clk) and IAck_2='1';
IValid_2 <= '0';
wait until rising_edge(clk);
IData_2 <= x"23";
IValid_2 <= '1';
wait until rising_edge(clk) and QValid_2='1';
QAck_2 <= '1';
wait until rising_edge(clk) and IAck_2='1';
IValid_2 <= '0';
QAck_2 <= '0';
wait;
end process;
end architecture ; -- arch
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_eda_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:43 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_eda_e-rtl-a.vhd,v 1.1 2004/04/06 10:50:08 wig Exp $
-- $Date: 2004/04/06 10:50:08 $
-- $Log: inst_eda_e-rtl-a.vhd,v $
-- Revision 1.1 2004/04/06 10:50:08 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Revision: 1.26 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_eda_e
--
architecture rtl of inst_eda_e is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
--
-- Nets
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
-- NEED RESULT: ARCH00367.P1: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00367: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00367: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: P1: Transport transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00367
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (2)
-- 9.5.2 (1)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00367(ARCH00367)
-- ENT00367_Test_Bench(ARCH00367_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00367 is
end ENT00367 ;
--
--
architecture ARCH00367 of ENT00367 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
--
subtype chk_time_type is Time ;
signal s_st_rec3_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_rec3_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 3 ;
signal st_rec3_select : select_type := 1 ;
--
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
--
begin
CHG1 :
process ( s_st_rec3 )
variable correct : boolean ;
begin
case s_st_rec3_cnt is
when 0
=> null ;
-- s_st_rec3.f3(lowb,true) <= transport
-- c_st_rec3_2.f3(lowb,true) after 10 ns,
-- c_st_rec3_1.f3(lowb,true) after 20 ns ;
--
when 1
=> correct :=
s_st_rec3.f3(lowb,true) =
c_st_rec3_2.f3(lowb,true) and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3.f3(lowb,true) =
c_st_rec3_1.f3(lowb,true) and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00367.P1" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec3_select <= transport 2 ;
-- s_st_rec3.f3(lowb,true) <= transport
-- c_st_rec3_2.f3(lowb,true) after 10 ns ,
-- c_st_rec3_1.f3(lowb,true) after 20 ns ,
-- c_st_rec3_2.f3(lowb,true) after 30 ns ,
-- c_st_rec3_1.f3(lowb,true) after 40 ns ;
--
when 3
=> correct :=
s_st_rec3.f3(lowb,true) =
c_st_rec3_2.f3(lowb,true) and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
st_rec3_select <= transport 3 ;
-- s_st_rec3.f3(lowb,true) <= transport
-- c_st_rec3_1.f3(lowb,true) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3.f3(lowb,true) =
c_st_rec3_1.f3(lowb,true) and
(s_st_rec3_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00367" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00367" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00367" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_rec3_savt <= transport Std.Standard.Now ;
chk_st_rec3 <= transport s_st_rec3_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec3_cnt <= transport s_st_rec3_cnt + 1 ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions completed entirely",
chk_st_rec3 = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
with st_rec3_select select
s_st_rec3.f3(lowb,true) <= transport
c_st_rec3_2.f3(lowb,true) after 10 ns,
c_st_rec3_1.f3(lowb,true) after 20 ns
when 1,
--
c_st_rec3_2.f3(lowb,true) after 10 ns ,
c_st_rec3_1.f3(lowb,true) after 20 ns ,
c_st_rec3_2.f3(lowb,true) after 30 ns ,
c_st_rec3_1.f3(lowb,true) after 40 ns
when 2,
--
c_st_rec3_1.f3(lowb,true) after 5 ns when 3 ;
--
end ARCH00367 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00367_Test_Bench is
end ENT00367_Test_Bench ;
--
--
architecture ARCH00367_Test_Bench of ENT00367_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.ENT00367 ( ARCH00367 ) ;
begin
CIS1 : UUT
;
end block L1 ;
end ARCH00367_Test_Bench ;
|
library verilog;
use verilog.vl_types.all;
entity finalproject_cpu_nios2_oci_debug is
port(
clk : in vl_logic;
dbrk_break : in vl_logic;
debugreq : in vl_logic;
hbreak_enabled : in vl_logic;
jdo : in vl_logic_vector(37 downto 0);
jrst_n : in vl_logic;
ocireg_ers : in vl_logic;
ocireg_mrs : in vl_logic;
reset : in vl_logic;
st_ready_test_idle: in vl_logic;
take_action_ocimem_a: in vl_logic;
take_action_ocireg: in vl_logic;
xbrk_break : in vl_logic;
debugack : out vl_logic;
monitor_error : out vl_logic;
monitor_go : out vl_logic;
monitor_ready : out vl_logic;
oci_hbreak_req : out vl_logic;
resetlatch : out vl_logic;
resetrequest : out vl_logic
);
end finalproject_cpu_nios2_oci_debug;
|
--
--ROMsUsingBlockRAMResources.
--VHDLcodeforaROMwithregisteredoutput(template2)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity os8 is
port(
clock:in std_logic;
address:in std_logic_vector(12 downto 0);
q:out std_logic_vector(7 downto 0)
);
end os8;
architecture syn of os8 is
type rom_type is array(0 to 8191) of std_logic_vector(7 downto 0);
signal ROM:rom_type:=
(
X"00",
X"00",
X"00",
X"00",
X"00",
X"00",
X"00",
X"00",
X"00",
X"18",
X"18",
X"18",
X"18",
X"00",
X"18",
X"00",
X"00",
X"66",
X"66",
X"66",
X"00",
X"00",
X"00",
X"00",
X"00",
X"66",
X"ff",
X"66",
X"66",
X"ff",
X"66",
X"00",
X"18",
X"3e",
X"60",
X"3c",
X"06",
X"7c",
X"18",
X"00",
X"00",
X"66",
X"6c",
X"18",
X"30",
X"66",
X"46",
X"00",
X"1c",
X"36",
X"1c",
X"38",
X"6f",
X"66",
X"3b",
X"00",
X"00",
X"18",
X"18",
X"18",
X"00",
X"00",
X"00",
X"00",
X"00",
X"0e",
X"1c",
X"18",
X"18",
X"1c",
X"0e",
X"00",
X"00",
X"70",
X"38",
X"18",
X"18",
X"38",
X"70",
X"00",
X"00",
X"66",
X"3c",
X"ff",
X"3c",
X"66",
X"00",
X"00",
X"00",
X"18",
X"18",
X"7e",
X"18",
X"18",
X"00",
X"00",
X"00",
X"00",
X"00",
X"00",
X"00",
X"18",
X"18",
X"30",
X"00",
X"00",
X"00",
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X"ff",
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X"e6",
X"91",
X"e7",
X"25",
X"f1",
X"f3",
X"e6"
);
signal rdata:std_logic_vector(7 downto 0);
begin
rdata<=ROM(conv_integer(address));
process(clock)
begin
if(clock'event and clock='1')then
q<=rdata;
end if;
end process;
end syn;
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity op is
port (
terminal in1: electrical;
terminal in2: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical);
end op;
architecture simple of op is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of in2:terminal is "input";
attribute SigType of in2:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
begin
subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => net1,
G => in1,
S => net2
);
subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
W => Wdiff_0,
scope => private
)
port map(
D => out1,
G => in2,
S => net2
);
subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
W => W_0
)
port map(
D => net2,
G => vbias4,
S => gnd
);
subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcm_1,
scope => private
)
port map(
D => net1,
G => net1,
S => vdd
);
subnet0_subnet1_m2 : entity pmos(behave)
generic map(
L => Lcm_1,
W => Wcmout_1,
scope => private
)
port map(
D => out1,
G => net1,
S => vdd
);
subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
W => (pfak)*(WBias)
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
W => (pfak)*(WBias)
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet1_subnet0_i1 : entity idc(behave)
generic map(
dc => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
W => WBias
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias2,
G => vbias3,
S => net3
);
subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
W => WBias
)
port map(
D => net3,
G => vbias4,
S => gnd
);
end simple;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: greth_tx
-- File: greth_tx.vhd
-- Author: Marko Isomaki
-- Description: Ethernet transmitter
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library eth;
use eth.grethpkg.all;
entity greth_tx is
generic(
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
nsync : integer range 1 to 2 := 2;
rmii : integer range 0 to 1 := 0;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
txi : in host_tx_type;
txo : out tx_host_type
);
attribute sync_set_reset of rst : signal is "true";
end entity;
architecture rtl of greth_tx is
function mirror2(din : in std_logic_vector(3 downto 0))
return std_logic_vector is
variable do : std_logic_vector(3 downto 0);
begin
do(3) := din(0); do(2) := din(1);
do(1) := din(2); do(0) := din(3);
return do;
end function;
function init_ifg(
ifg_gap : in integer;
rmii : in integer)
return integer is
begin
if rmii = 0 then
return log2(ifg_gap);
else
return log2(ifg_gap*20);
end if;
end function;
constant maxattempts : std_logic_vector(4 downto 0) :=
conv_std_logic_vector(attempt_limit, 5);
--transmitter constants
constant ifg_bits : integer := init_ifg(ifg_gap, rmii);
constant ifg_p1 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector((ifg_gap)/3, ifg_bits);
constant ifg_p2 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector((ifg_gap*2)/3, ifg_bits);
constant ifg_p1_r100 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector((ifg_gap*2)/3, ifg_bits);
constant ifg_p2_r100 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector(rmii*(ifg_gap*4)/3, ifg_bits);
constant ifg_p1_r10 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector(rmii*(ifg_gap*20)/3, ifg_bits);
constant ifg_p2_r10 : std_logic_vector(ifg_bits-1 downto 0) :=
conv_std_logic_vector(rmii*(ifg_gap*40)/3, ifg_bits);
function ifg_sel(
rmii : in integer;
p1 : in integer;
speed : in std_ulogic)
return std_logic_vector is
begin
if p1 = 1 then
if rmii = 0 then
return ifg_p1;
else
if speed = '1' then
return ifg_p1_r100;
else
return ifg_p1_r10;
end if;
end if;
else
if rmii = 0 then
return ifg_p2;
else
if speed = '1' then
return ifg_p2_r100;
else
return ifg_p2_r10;
end if;
end if;
end if;
end function;
--transmitter types
type tx_state_type is (idle, preamble, sfd, data1, data2, pad1, pad2, fcs,
fcs2, finish, calc_backoff, wait_backoff, send_jam, send_jam2,
check_attempts);
type def_state_type is (monitor, def_on, ifg1, ifg2, frame_waitingst);
type tx_reg_type is record
--deference process
def_state : def_state_type;
ifg_cycls : std_logic_vector(ifg_bits-1 downto 0);
deferring : std_ulogic;
was_transmitting : std_ulogic;
--tx process
main_state : tx_state_type;
transmitting : std_ulogic;
tx_en : std_ulogic;
txd : std_logic_vector(3 downto 0);
cnt : std_logic_vector(3 downto 0);
icnt : std_logic_vector(1 downto 0);
crc : std_logic_vector(31 downto 0);
crc_en : std_ulogic;
byte_count : std_logic_vector(10 downto 0);
slot_count : std_logic_vector(6 downto 0);
random : std_logic_vector(9 downto 0);
delay_val : std_logic_vector(9 downto 0);
retry_cnt : std_logic_vector(4 downto 0);
status : std_logic_vector(1 downto 0);
data : std_logic_vector(31 downto 0);
--synchronization
read : std_ulogic;
done : std_ulogic;
restart : std_ulogic;
start : std_logic_vector(nsync downto 0);
read_ack : std_logic_vector(nsync-1 downto 0);
crs : std_logic_vector(1 downto 0);
col : std_logic_vector(1 downto 0);
fullduplex : std_logic_vector(1 downto 0);
--rmii
crs_act : std_ulogic;
crs_prev : std_ulogic;
speed : std_logic_vector(1 downto 0);
rcnt : std_logic_vector(3 downto 0);
switch : std_ulogic;
txd_msb : std_logic_vector(1 downto 0);
zero : std_ulogic;
rmii_crc_en : std_ulogic;
end record;
--transmitter signals
signal r, rin : tx_reg_type;
signal txrst : std_ulogic;
signal vcc : std_ulogic;
--attribute sync_set_reset : string;
attribute sync_set_reset of txrst : signal is "true";
begin
vcc <= '1';
tx_rst : eth_rstgen
port map(rst, clk, vcc, txrst, open);
tx : process(txrst, r, txi) is
variable collision : std_ulogic;
variable frame_waiting : std_ulogic;
variable index : integer range 0 to 7;
variable start : std_ulogic;
variable read_ack : std_ulogic;
variable v : tx_reg_type;
variable crs : std_ulogic;
variable col : std_ulogic;
variable tx_done : std_ulogic;
begin
v := r; frame_waiting := '0'; tx_done := '0'; v.rmii_crc_en := '0';
--synchronization
v.col(1) := r.col(0); v.col(0) := txi.rx_col;
v.crs(1) := r.crs(0); v.crs(0) := txi.rx_crs;
v.fullduplex(0) := txi.full_duplex;
v.fullduplex(1) := r.fullduplex(0);
v.start(0) := txi.start;
v.read_ack(0) := txi.readack;
if nsync = 2 then
v.start(1) := r.start(0);
v.read_ack(1) := r.read_ack(0);
end if;
start := r.start(nsync) xor r.start(nsync-1);
read_ack := not (r.read xor r.read_ack(nsync-1));
--crc generation
if (r.crc_en = '1') and ((rmii = 0) or (r.rmii_crc_en = '1')) then
v.crc := calccrc(r.txd, r.crc);
end if;
--rmii
if rmii = 0 then
col := r.col(1); crs := r.crs(1);
tx_done := '1';
else
v.crs_prev := r.crs(1);
if (r.crs(0) and not r.crs_act) = '1' then
v.crs_act := '1';
end if;
if (r.crs(1) or r.crs(0)) = '0' then
v.crs_act := '0';
end if;
crs := r.crs(1) and not ((not r.crs_prev) and r.crs_act);
col := crs and r.tx_en;
v.speed(1) := r.speed(0); v.speed(0) := txi.speed;
if r.tx_en = '1' then
v.rcnt := r.rcnt - 1;
if r.speed(1) = '1' then
v.switch := not r.switch;
if r.switch = '1' then
tx_done := '1'; v.rmii_crc_en := '1';
end if;
if r.switch = '0' then
v.txd(1 downto 0) := r.txd_msb;
end if;
else
v.zero := '0';
if r.rcnt = "0001" then
v.zero := '1';
end if;
if r.zero = '1' then
v.switch := not r.switch;
v.rcnt := "1001";
if r.switch = '0' then
v.txd(1 downto 0) := r.txd_msb;
end if;
end if;
if (r.switch and r.zero) = '1' then
tx_done := '1'; v.rmii_crc_en := '1';
end if;
end if;
end if;
end if;
collision := col and not r.fullduplex(1);
--main fsm
case r.main_state is
when idle =>
v.transmitting := '0';
if rmii = 1 then
v.rcnt := "1001"; v.switch := '0';
end if;
if (start and not r.deferring) = '1' then
v.main_state := preamble; v.transmitting := '1'; v.tx_en := '1';
v.byte_count := (others => '1'); v.status := (others => '0');
v.read := not r.read; v.start(nsync) := r.start(nsync-1);
elsif start = '1' then
frame_waiting := '1';
end if;
v.txd := "0101"; v.cnt := "1110";
when preamble =>
if tx_done = '1' then
v.cnt := r.cnt - 1;
if r.cnt = "0000" then
v.txd := "1101"; v.main_state := sfd;
end if;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when sfd =>
if tx_done = '1' then
v.main_state := data1; v.icnt := (others => '0'); v.crc_en := '1';
v.crc := (others => '1'); v.byte_count := (others => '0');
v.txd := txi.data(27 downto 24);
if (read_ack and txi.valid) = '0' then
v.status(0) := '1'; v.main_state := finish; v.tx_en := '0';
else
v.data := txi.data; v.read := not r.read;
end if;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when data1 =>
index := conv_integer(r.icnt);
if tx_done = '1' then
v.byte_count := r.byte_count + 1;
v.main_state := data2; v.icnt := r.icnt + 1;
case index is
when 0 => v.txd := r.data(31 downto 28);
when 1 => v.txd := r.data(23 downto 20);
when 2 => v.txd := r.data(15 downto 12);
when 3 => v.txd := r.data(7 downto 4);
when others => null;
end case;
if v.byte_count = txi.len then
v.tx_en := '1';
if conv_integer(v.byte_count) >= 60 then
v.main_state := fcs; v.cnt := (others => '0');
else
v.main_state := pad1;
end if;
elsif index = 3 then
if (read_ack and txi.valid) = '0' then
v.status(0) := '1'; v.main_state := finish; v.tx_en := '0';
else
v.data := txi.data; v.read := not r.read;
end if;
end if;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when data2 =>
index := conv_integer(r.icnt);
if tx_done = '1' then
v.main_state := data1;
case index is
when 0 => v.txd := r.data(27 downto 24);
when 1 => v.txd := r.data(19 downto 16);
when 2 => v.txd := r.data(11 downto 8);
when 3 => v.txd := r.data(3 downto 0);
when others => null;
end case;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when pad1 =>
if tx_done = '1' then
v.main_state := pad2;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when pad2 =>
if tx_done = '1' then
v.byte_count := r.byte_count + 1;
if conv_integer(v.byte_count) = 60 then
v.main_state := fcs; v.cnt := (others => '0');
else
v.main_state := pad1;
end if;
if collision = '1' then v.main_state := send_jam; end if;
end if;
when fcs =>
if tx_done = '1' then
v.cnt := r.cnt + 1; v.crc_en := '0'; index := conv_integer(r.cnt);
case index is
when 0 => v.txd := mirror2(not v.crc(31 downto 28));
when 1 => v.txd := mirror2(not r.crc(27 downto 24));
when 2 => v.txd := mirror2(not r.crc(23 downto 20));
when 3 => v.txd := mirror2(not r.crc(19 downto 16));
when 4 => v.txd := mirror2(not r.crc(15 downto 12));
when 5 => v.txd := mirror2(not r.crc(11 downto 8));
when 6 => v.txd := mirror2(not r.crc(7 downto 4));
when 7 => v.txd := mirror2(not r.crc(3 downto 0));
v.main_state := fcs2;
when others => null;
end case;
end if;
when fcs2 =>
if tx_done = '1' then
v.main_state := finish; v.tx_en := '0';
end if;
when finish =>
v.tx_en := '0'; v.transmitting := '0'; v.main_state := idle;
v.retry_cnt := (others => '0'); v.done := not r.done;
when send_jam =>
if tx_done = '1' then
v.cnt := "0110"; v.main_state := send_jam2; v.crc_en := '0';
end if;
when send_jam2 =>
if tx_done = '1' then
v.cnt := r.cnt - 1;
if r.cnt = "0000" then
v.main_state := check_attempts; v.retry_cnt := r.retry_cnt + 1;
v.tx_en := '0';
end if;
end if;
when check_attempts =>
v.transmitting := '0';
if r.retry_cnt = maxattempts then
v.main_state := finish; v.status(1) := '1';
else
v.main_state := calc_backoff; v.restart := not r.restart;
end if;
v.tx_en := '0';
when calc_backoff =>
v.delay_val := (others => '0');
for i in 1 to backoff_limit-1 loop
if i < conv_integer(r.retry_cnt)+1 then
v.delay_val(i) := r.random(i);
end if;
end loop;
v.main_state := wait_backoff; v.slot_count := (others => '1');
when wait_backoff =>
if conv_integer(r.delay_val) = 0 then
v.main_state := idle;
end if;
v.slot_count := r.slot_count - 1;
if conv_integer(r.slot_count) = 0 then
v.slot_count := (others => '1'); v.delay_val := r.delay_val - 1;
end if;
when others =>
v.main_state := idle;
end case;
--random values;
v.random := r.random(8 downto 0) & (not (r.random(2) xor r.random(9)));
--deference
case r.def_state is
when monitor =>
v.was_transmitting := '0';
if ( (crs and not r.fullduplex(1)) or
(r.transmitting and r.fullduplex(1)) ) = '1' then
v.deferring := '1'; v.def_state := def_on;
v.was_transmitting := r.transmitting;
end if;
when def_on =>
v.was_transmitting := r.was_transmitting or r.transmitting;
if r.fullduplex(1) = '1' then
if r.transmitting = '0' then v.def_state := ifg1; end if;
v.ifg_cycls := ifg_sel(rmii, 1, r.speed(1));
else
if (r.transmitting or crs) = '0' then
v.def_state := ifg1; v.ifg_cycls := ifg_sel(rmii, 1, r.speed(1));
end if;
end if;
when ifg1 =>
v.ifg_cycls := r.ifg_cycls - 1;
if r.ifg_cycls = zero32(ifg_bits-1 downto 0) then
v.def_state := ifg2;
v.ifg_cycls := ifg_sel(rmii, 0, r.speed(1));
elsif (crs and not r.fullduplex(1)) = '1' then
v.ifg_cycls := ifg_sel(rmii, 1, r.speed(1));
end if;
when ifg2 =>
v.ifg_cycls := r.ifg_cycls - 1;
if r.ifg_cycls = zero32(ifg_bits-1 downto 0) then
v.deferring := '0';
if (r.fullduplex(1) or not frame_waiting) = '1' then
v.def_state := monitor;
elsif frame_waiting = '1' then
v.def_state := frame_waitingst;
end if;
end if;
when frame_waitingst =>
if frame_waiting = '0' then v.def_state := monitor; end if;
when others => v.def_state := monitor;
end case;
if rmii = 1 then
v.txd_msb := v.txd(3 downto 2);
end if;
if txrst = '0' then
v.main_state := idle; v.random := (others => '0');
v.def_state := monitor; v.deferring := '0'; v.tx_en := '0';
v.done := '0'; v.restart := '0'; v.read := '0';
v.start := (others => '0'); v.read_ack := (others => '0');
v.icnt := (others => '0'); v.delay_val := (others => '0');
v.ifg_cycls := (others => '0');
v.crs_act := '0';
v.slot_count := (others => '1');
v.retry_cnt := (others => '0');
v.cnt := (others => '0');
end if;
rin <= v;
txo.tx_er <= '0';
txo.tx_en <= r.tx_en;
txo.txd <= r.txd;
txo.done <= r.done;
txo.read <= r.read;
txo.restart <= r.restart;
txo.status <= r.status;
end process;
gmiimode0 : if gmiimode = 0 generate
txregs0 : process(clk) is
begin
if rising_edge(clk) then
r <= rin;
if txrst = '0' then
r.icnt <= (others => '0'); r.delay_val <= (others => '0');
r.cnt <= (others => '0');
else
r.icnt <= rin.icnt; r.delay_val <= rin.delay_val;
r.cnt <= rin.cnt;
end if;
end if;
end process;
end generate;
gmiimode1 : if gmiimode = 1 generate
txregs0 : process(clk) is
begin
if rising_edge(clk) then
if (txi.datavalid = '1' or txrst = '0') then r <= rin; end if;
if txrst = '0' then
r.icnt <= (others => '0'); r.delay_val <= (others => '0');
r.cnt <= (others => '0');
else
if txi.datavalid = '1' then
r.icnt <= rin.icnt; r.delay_val <= rin.delay_val;
r.cnt <= rin.cnt;
end if;
end if;
end if;
end process;
end generate;
end architecture;
|
-- Returns the sine of a value from 0 to 1 (scaled as - to sine_addr_max)
--
-- The lookup table actually stores the first quarter of each sine wave, so
-- this entity transforms the stored first quarter to be able to calculate the
-- sine of any quarter of the wave. The following graph shoes the relation
-- between inputs to the entity (x axis) and outputs from the module (y axis)
--
-- y=1.0
-- | -------------
-- | / \
-- | / \
-- | / \
-- |/ \
-- |--------------------------------------------
-- | \ /
-- | \ /
-- | \ /
-- | \-------------/
-- |<---a---->|<---b---->|<---c---->|<---d---->|
-- x=0 0.25 0.5 0.75 1
-- y=-1
--
-- In Section a, the output value is directly read from the LUT.
-- In Section b, the output value is directly read but the LUT is indexed by 0.25-x
-- In Section c, the LUT output is negates and the LUT is indexed by x-0.5
-- In Section d, the LUT output is negates and the LUT is indexed by 0.75-x
--
-- The implementation is gently pipelined.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library virtual_button_lib;
use virtual_button_lib.constants.all;
use virtual_button_lib.sine_lut_pkg.all;
use virtual_button_lib.utils.all;
entity sine_rom is
port(
ctrl : in ctrl_t;
read_address_d0 : in integer range 0 to sine_addr_max;
read_out_d1 : out signed(15 downto 0)
);
end;
architecture rtl of sine_rom is
signal sine_rom : sine_lut_arr := calc_sine_lut;
attribute ram_style : string;
attribute ram_style of sine_rom : signal is "block";
constant address_width : integer := integer(ceil(log2(real(sine_addr_max))));
signal read_address_d1 : integer range 0 to sine_addr_max;
signal read_address_int_d0 : integer range 0 to sine_lut_bram_depth - 1;
signal negative_read_out_int_d1 : signed(lut_width - 1 downto 0);
signal read_out_int_d1 : signed(lut_width - 1 downto 0);
type modes is (normal_inc, normal_dec, inv_inc, inv_dec);
--signal mode : modes;
function calc_mode(read_address : in integer range 0 to sine_addr_max) return modes is
begin
if read_address < sine_lut_bram_depth then
return normal_inc;
elsif read_address < 2 * sine_lut_bram_depth then
return normal_dec;
elsif read_address < 3 * sine_lut_bram_depth then
return inv_inc;
else
return inv_dec;
end if;
end;
begin
negative_read_out_int_d1 <= -read_out_int_d1;
delay_read_address : process(ctrl.clk) is
begin
if rising_edge(ctrl.clk) then
read_address_d1 <= read_address_d0;
end if;
end process;
ram_proc : process (read_address_d0) is
--variable mode : modes;
begin
--if rising_edge(ctrl.clk) then
if calc_mode(read_address_d0) = normal_inc then
read_address_int_d0 <= read_address_d0;
elsif calc_mode(read_address_d0) = normal_dec then
read_address_int_d0 <= (sine_lut_bram_depth * 2) - 1 - read_address_d0;
elsif calc_mode(read_address_d0) = inv_inc then
read_address_int_d0 <= read_address_d0 - (2 * sine_lut_bram_depth);
else
read_address_int_d0 <= (sine_lut_bram_depth * 4) - 1 - read_address_d0;
end if;
--end if;
end process;
ram_read_proc : process (ctrl.clk) is
begin
if rising_edge(ctrl.clk) then
read_out_int_d1 <= sine_rom(read_address_int_d0);
end if;
end process;
assign_outputs : process(read_address_d1, read_out_int_d1, negative_read_out_int_d1)
variable mode : modes;
begin
mode := calc_mode(read_address_d1);
if mode = normal_inc or mode = normal_dec then
read_out_d1 <= read_out_int_d1;
else
read_out_d1 <= negative_read_out_int_d1;
end if;
end process;
end;
|
entity proc8 is
end entity;
architecture test of proc8 is
type int_vec is array (integer range <>) of integer;
subtype int_vec4 is int_vec(1 to 4);
procedure p1(signal y : in int_vec) is
begin
for i in y'range loop
report integer'image(y(i));
end loop;
end procedure;
procedure p1b(variable y : in int_vec4) is
begin
for i in y'range loop
report integer'image(y(i));
end loop;
end procedure;
procedure p2(signal x : in int_vec4) is
begin
p1(x);
end procedure;
procedure p3(signal x : out int_vec) is
begin
x <= (6, 7, 8, 9);
end procedure;
signal s : int_vec4 := (1, 2, 3, 4);
begin
process is
variable k : int_vec4 := (-1, -2, -3, -4);
begin
p2(s);
p3(s);
wait for 1 ns;
assert s = (6, 7, 8, 9);
p1b(k);
wait;
end process;
end architecture;
|
entity proc8 is
end entity;
architecture test of proc8 is
type int_vec is array (integer range <>) of integer;
subtype int_vec4 is int_vec(1 to 4);
procedure p1(signal y : in int_vec) is
begin
for i in y'range loop
report integer'image(y(i));
end loop;
end procedure;
procedure p1b(variable y : in int_vec4) is
begin
for i in y'range loop
report integer'image(y(i));
end loop;
end procedure;
procedure p2(signal x : in int_vec4) is
begin
p1(x);
end procedure;
procedure p3(signal x : out int_vec) is
begin
x <= (6, 7, 8, 9);
end procedure;
signal s : int_vec4 := (1, 2, 3, 4);
begin
process is
variable k : int_vec4 := (-1, -2, -3, -4);
begin
p2(s);
p3(s);
wait for 1 ns;
assert s = (6, 7, 8, 9);
p1b(k);
wait;
end process;
end architecture;
|
entity proc8 is
end entity;
architecture test of proc8 is
type int_vec is array (integer range <>) of integer;
subtype int_vec4 is int_vec(1 to 4);
procedure p1(signal y : in int_vec) is
begin
for i in y'range loop
report integer'image(y(i));
end loop;
end procedure;
procedure p1b(variable y : in int_vec4) is
begin
for i in y'range loop
report integer'image(y(i));
end loop;
end procedure;
procedure p2(signal x : in int_vec4) is
begin
p1(x);
end procedure;
procedure p3(signal x : out int_vec) is
begin
x <= (6, 7, 8, 9);
end procedure;
signal s : int_vec4 := (1, 2, 3, 4);
begin
process is
variable k : int_vec4 := (-1, -2, -3, -4);
begin
p2(s);
p3(s);
wait for 1 ns;
assert s = (6, 7, 8, 9);
p1b(k);
wait;
end process;
end architecture;
|
entity proc8 is
end entity;
architecture test of proc8 is
type int_vec is array (integer range <>) of integer;
subtype int_vec4 is int_vec(1 to 4);
procedure p1(signal y : in int_vec) is
begin
for i in y'range loop
report integer'image(y(i));
end loop;
end procedure;
procedure p1b(variable y : in int_vec4) is
begin
for i in y'range loop
report integer'image(y(i));
end loop;
end procedure;
procedure p2(signal x : in int_vec4) is
begin
p1(x);
end procedure;
procedure p3(signal x : out int_vec) is
begin
x <= (6, 7, 8, 9);
end procedure;
signal s : int_vec4 := (1, 2, 3, 4);
begin
process is
variable k : int_vec4 := (-1, -2, -3, -4);
begin
p2(s);
p3(s);
wait for 1 ns;
assert s = (6, 7, 8, 9);
p1b(k);
wait;
end process;
end architecture;
|
entity proc8 is
end entity;
architecture test of proc8 is
type int_vec is array (integer range <>) of integer;
subtype int_vec4 is int_vec(1 to 4);
procedure p1(signal y : in int_vec) is
begin
for i in y'range loop
report integer'image(y(i));
end loop;
end procedure;
procedure p1b(variable y : in int_vec4) is
begin
for i in y'range loop
report integer'image(y(i));
end loop;
end procedure;
procedure p2(signal x : in int_vec4) is
begin
p1(x);
end procedure;
procedure p3(signal x : out int_vec) is
begin
x <= (6, 7, 8, 9);
end procedure;
signal s : int_vec4 := (1, 2, 3, 4);
begin
process is
variable k : int_vec4 := (-1, -2, -3, -4);
begin
p2(s);
p3(s);
wait for 1 ns;
assert s = (6, 7, 8, 9);
p1b(k);
wait;
end process;
end architecture;
|
----------------------------------------------------------------------
---- ----
---- WISHBONE SPDIF IP Core ----
---- ----
---- This file is part of the SPDIF project ----
---- http://www.opencores.org/cores/spdif_interface/ ----
---- ----
---- Description ----
---- Generic control register. ----
---- ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author(s): ----
---- - Geir Drange, [email protected] ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2004 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
--
-- CVS Revision History
--
-- $Log: not supported by cvs2svn $
-- Revision 1.3 2004/06/06 15:42:19 gedra
-- Cleaned up lint warnings.
--
-- Revision 1.2 2004/06/04 15:55:07 gedra
-- Cleaned up lint warnings.
--
-- Revision 1.1 2004/06/03 17:47:17 gedra
-- Generic control register. Used in both recevier and transmitter.
--
--
library ieee;
use ieee.std_logic_1164.all;
entity gen_control_reg is
generic (DATA_WIDTH: integer;
-- note that this vector is (0 to xx), reverse order
ACTIVE_BIT_MASK: std_logic_vector);
port (
clk: in std_logic; -- clock
rst: in std_logic; -- reset
ctrl_wr: in std_logic; -- control register write
ctrl_rd: in std_logic; -- control register read
ctrl_din: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- write data
ctrl_dout: out std_logic_vector(DATA_WIDTH - 1 downto 0); -- read data
ctrl_bits: out std_logic_vector(DATA_WIDTH - 1 downto 0)); -- control bits
end gen_control_reg;
architecture rtl of gen_control_reg is
signal ctrl_internal: std_logic_vector(DATA_WIDTH - 1 downto 0);
begin
ctrl_dout <= ctrl_internal when ctrl_rd = '1' else (others => '0');
ctrl_bits <= ctrl_internal;
-- control register generation
CTRLREG: for k in ctrl_din'range generate
-- active bits can be written to
ACTIVE: if ACTIVE_BIT_MASK(k) = '1' generate
CBIT: process (clk, rst)
begin
if rst = '1' then
ctrl_internal(k) <= '0';
else
if rising_edge(clk) then
if ctrl_wr = '1' then
ctrl_internal(k) <= ctrl_din(k);
end if;
end if;
end if;
end process CBIT;
end generate ACTIVE;
-- inactive bits are always 0
INACTIVE: if ACTIVE_BIT_MASK(k) = '0' generate
ctrl_internal(k) <= '0';
end generate INACTIVE;
end generate CTRLREG;
end rtl;
|
-- NEED RESULT: ARCH00072.P1: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00072.P2: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00072.P3: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00072.P4: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00072.P5: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00072.P6: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00072.P7: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00072.P8: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00072.P9: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00072.P10: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00072.P11: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00072.P12: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00072.P13: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00072.P14: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00072.P15: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00072.P16: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00072.P17: Multi transport transactions occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00072: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00072: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00072: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00072: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00072: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00072: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00072: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00072: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00072: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00072: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00072: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00072: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00072: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00072: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00072: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00072: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00072: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00072: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00072: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00072: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00072: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00072: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00072: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00072: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00072: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00072: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00072: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00072: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00072: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00072: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00072: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00072: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00072: One transport transaction occurred on signal asg with simple name on LHS passed
-- NEED RESULT: ARCH00072: Old transactions were removed on signal asg with simple name on LHS passed
-- NEED RESULT: P17: Transport transactions entirely completed passed
-- NEED RESULT: P16: Transport transactions entirely completed passed
-- NEED RESULT: P15: Transport transactions entirely completed passed
-- NEED RESULT: P14: Transport transactions entirely completed passed
-- NEED RESULT: P13: Transport transactions entirely completed passed
-- NEED RESULT: P12: Transport transactions entirely completed passed
-- NEED RESULT: P11: Transport transactions entirely completed passed
-- NEED RESULT: P10: Transport transactions entirely completed passed
-- NEED RESULT: P9: Transport transactions entirely completed passed
-- NEED RESULT: P8: Transport transactions entirely completed passed
-- NEED RESULT: P7: Transport transactions entirely completed passed
-- NEED RESULT: P6: Transport transactions entirely completed passed
-- NEED RESULT: P5: Transport transactions entirely completed passed
-- NEED RESULT: P4: Transport transactions entirely completed passed
-- NEED RESULT: P3: Transport transactions entirely completed passed
-- NEED RESULT: P2: Transport transactions entirely completed passed
-- NEED RESULT: P1: Transport transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00072
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (2)
-- 8.3 (3)
-- 8.3 (5)
-- 8.3.1 (3)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00072)
-- ENT00072_Test_Bench(ARCH00072_Test_Bench)
--
-- REVISION HISTORY:
--
-- 06-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00072 of E00000 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_boolean : chk_sig_type := -1 ;
signal chk_bit : chk_sig_type := -1 ;
signal chk_severity_level : chk_sig_type := -1 ;
signal chk_character : chk_sig_type := -1 ;
signal chk_st_enum1 : chk_sig_type := -1 ;
signal chk_integer : chk_sig_type := -1 ;
signal chk_st_int1 : chk_sig_type := -1 ;
signal chk_time : chk_sig_type := -1 ;
signal chk_st_phys1 : chk_sig_type := -1 ;
signal chk_real : chk_sig_type := -1 ;
signal chk_st_real1 : chk_sig_type := -1 ;
signal chk_st_rec1 : chk_sig_type := -1 ;
signal chk_st_rec2 : chk_sig_type := -1 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
signal chk_st_arr1 : chk_sig_type := -1 ;
signal chk_st_arr2 : chk_sig_type := -1 ;
signal chk_st_arr3 : chk_sig_type := -1 ;
--
signal s_boolean : boolean
:= c_boolean_1 ;
signal s_bit : bit
:= c_bit_1 ;
signal s_severity_level : severity_level
:= c_severity_level_1 ;
signal s_character : character
:= c_character_1 ;
signal s_st_enum1 : st_enum1
:= c_st_enum1_1 ;
signal s_integer : integer
:= c_integer_1 ;
signal s_st_int1 : st_int1
:= c_st_int1_1 ;
signal s_time : time
:= c_time_1 ;
signal s_st_phys1 : st_phys1
:= c_st_phys1_1 ;
signal s_real : real
:= c_real_1 ;
signal s_st_real1 : st_real1
:= c_st_real1_1 ;
signal s_st_rec1 : st_rec1
:= c_st_rec1_1 ;
signal s_st_rec2 : st_rec2
:= c_st_rec2_1 ;
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
signal s_st_arr1 : st_arr1
:= c_st_arr1_1 ;
signal s_st_arr2 : st_arr2
:= c_st_arr2_1 ;
signal s_st_arr3 : st_arr3
:= c_st_arr3_1 ;
--
begin
PGEN_CHKP_1 :
process ( chk_boolean )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions entirely completed",
chk_boolean = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P1 :
process ( s_boolean )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_boolean <= transport
c_boolean_2 after 10 ns,
c_boolean_1 after 20 ns ;
--
when 1
=> correct :=
s_boolean = c_boolean_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_boolean = c_boolean_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00072.P1" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_boolean <= transport
c_boolean_2 after 10 ns ,
c_boolean_1 after 20 ns ,
c_boolean_2 after 30 ns ,
c_boolean_1 after 40 ns ;
--
when 3
=> correct :=
s_boolean = c_boolean_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_boolean <= transport c_boolean_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_boolean = c_boolean_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00072" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00072" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00072" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_boolean <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P1 ;
--
PGEN_CHKP_2 :
process ( chk_bit )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions entirely completed",
chk_bit = 4 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
P2 :
process ( s_bit )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_bit <= transport
c_bit_2 after 10 ns,
c_bit_1 after 20 ns ;
--
when 1
=> correct :=
s_bit = c_bit_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_bit = c_bit_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00072.P2" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_bit <= transport
c_bit_2 after 10 ns ,
c_bit_1 after 20 ns ,
c_bit_2 after 30 ns ,
c_bit_1 after 40 ns ;
--
when 3
=> correct :=
s_bit = c_bit_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_bit <= transport c_bit_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_bit = c_bit_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00072" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00072" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00072" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_bit <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P2 ;
--
PGEN_CHKP_3 :
process ( chk_severity_level )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Transport transactions entirely completed",
chk_severity_level = 4 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
P3 :
process ( s_severity_level )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_severity_level <= transport
c_severity_level_2 after 10 ns,
c_severity_level_1 after 20 ns ;
--
when 1
=> correct :=
s_severity_level = c_severity_level_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_severity_level = c_severity_level_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00072.P3" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_severity_level <= transport
c_severity_level_2 after 10 ns ,
c_severity_level_1 after 20 ns ,
c_severity_level_2 after 30 ns ,
c_severity_level_1 after 40 ns ;
--
when 3
=> correct :=
s_severity_level = c_severity_level_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_severity_level <= transport c_severity_level_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_severity_level = c_severity_level_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00072" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00072" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00072" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_severity_level <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P3 ;
--
PGEN_CHKP_4 :
process ( chk_character )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Transport transactions entirely completed",
chk_character = 4 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
P4 :
process ( s_character )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_character <= transport
c_character_2 after 10 ns,
c_character_1 after 20 ns ;
--
when 1
=> correct :=
s_character = c_character_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_character = c_character_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00072.P4" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_character <= transport
c_character_2 after 10 ns ,
c_character_1 after 20 ns ,
c_character_2 after 30 ns ,
c_character_1 after 40 ns ;
--
when 3
=> correct :=
s_character = c_character_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_character <= transport c_character_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_character = c_character_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00072" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00072" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00072" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_character <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P4 ;
--
PGEN_CHKP_5 :
process ( chk_st_enum1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Transport transactions entirely completed",
chk_st_enum1 = 4 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
P5 :
process ( s_st_enum1 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_enum1 <= transport
c_st_enum1_2 after 10 ns,
c_st_enum1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_enum1 = c_st_enum1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_enum1 = c_st_enum1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00072.P5" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_enum1 <= transport
c_st_enum1_2 after 10 ns ,
c_st_enum1_1 after 20 ns ,
c_st_enum1_2 after 30 ns ,
c_st_enum1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_enum1 = c_st_enum1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_enum1 <= transport c_st_enum1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_enum1 = c_st_enum1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00072" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00072" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00072" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_enum1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P5 ;
--
PGEN_CHKP_6 :
process ( chk_integer )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Transport transactions entirely completed",
chk_integer = 4 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
P6 :
process ( s_integer )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_integer <= transport
c_integer_2 after 10 ns,
c_integer_1 after 20 ns ;
--
when 1
=> correct :=
s_integer = c_integer_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_integer = c_integer_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00072.P6" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_integer <= transport
c_integer_2 after 10 ns ,
c_integer_1 after 20 ns ,
c_integer_2 after 30 ns ,
c_integer_1 after 40 ns ;
--
when 3
=> correct :=
s_integer = c_integer_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_integer <= transport c_integer_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_integer = c_integer_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00072" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00072" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00072" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_integer <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P6 ;
--
PGEN_CHKP_7 :
process ( chk_st_int1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P7" ,
"Transport transactions entirely completed",
chk_st_int1 = 4 ) ;
end if ;
end process PGEN_CHKP_7 ;
--
P7 :
process ( s_st_int1 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_int1 <= transport
c_st_int1_2 after 10 ns,
c_st_int1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_int1 = c_st_int1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_int1 = c_st_int1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00072.P7" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_int1 <= transport
c_st_int1_2 after 10 ns ,
c_st_int1_1 after 20 ns ,
c_st_int1_2 after 30 ns ,
c_st_int1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_int1 = c_st_int1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_int1 <= transport c_st_int1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_int1 = c_st_int1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00072" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00072" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00072" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_int1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P7 ;
--
PGEN_CHKP_8 :
process ( chk_time )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P8" ,
"Transport transactions entirely completed",
chk_time = 4 ) ;
end if ;
end process PGEN_CHKP_8 ;
--
P8 :
process ( s_time )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_time <= transport
c_time_2 after 10 ns,
c_time_1 after 20 ns ;
--
when 1
=> correct :=
s_time = c_time_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_time = c_time_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00072.P8" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_time <= transport
c_time_2 after 10 ns ,
c_time_1 after 20 ns ,
c_time_2 after 30 ns ,
c_time_1 after 40 ns ;
--
when 3
=> correct :=
s_time = c_time_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_time <= transport c_time_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_time = c_time_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00072" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00072" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00072" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_time <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P8 ;
--
PGEN_CHKP_9 :
process ( chk_st_phys1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P9" ,
"Transport transactions entirely completed",
chk_st_phys1 = 4 ) ;
end if ;
end process PGEN_CHKP_9 ;
--
P9 :
process ( s_st_phys1 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_phys1 <= transport
c_st_phys1_2 after 10 ns,
c_st_phys1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_phys1 = c_st_phys1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_phys1 = c_st_phys1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00072.P9" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_phys1 <= transport
c_st_phys1_2 after 10 ns ,
c_st_phys1_1 after 20 ns ,
c_st_phys1_2 after 30 ns ,
c_st_phys1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_phys1 = c_st_phys1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_phys1 <= transport c_st_phys1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_phys1 = c_st_phys1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00072" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00072" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00072" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_phys1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P9 ;
--
PGEN_CHKP_10 :
process ( chk_real )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P10" ,
"Transport transactions entirely completed",
chk_real = 4 ) ;
end if ;
end process PGEN_CHKP_10 ;
--
P10 :
process ( s_real )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_real <= transport
c_real_2 after 10 ns,
c_real_1 after 20 ns ;
--
when 1
=> correct :=
s_real = c_real_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_real = c_real_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00072.P10" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_real <= transport
c_real_2 after 10 ns ,
c_real_1 after 20 ns ,
c_real_2 after 30 ns ,
c_real_1 after 40 ns ;
--
when 3
=> correct :=
s_real = c_real_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_real <= transport c_real_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_real = c_real_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00072" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00072" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00072" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_real <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P10 ;
--
PGEN_CHKP_11 :
process ( chk_st_real1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P11" ,
"Transport transactions entirely completed",
chk_st_real1 = 4 ) ;
end if ;
end process PGEN_CHKP_11 ;
--
P11 :
process ( s_st_real1 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_real1 <= transport
c_st_real1_2 after 10 ns,
c_st_real1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_real1 = c_st_real1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real1 = c_st_real1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00072.P11" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_real1 <= transport
c_st_real1_2 after 10 ns ,
c_st_real1_1 after 20 ns ,
c_st_real1_2 after 30 ns ,
c_st_real1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_real1 = c_st_real1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_real1 <= transport c_st_real1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real1 = c_st_real1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00072" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00072" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00072" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_real1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P11 ;
--
PGEN_CHKP_12 :
process ( chk_st_rec1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P12" ,
"Transport transactions entirely completed",
chk_st_rec1 = 4 ) ;
end if ;
end process PGEN_CHKP_12 ;
--
P12 :
process ( s_st_rec1 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_rec1 <= transport
c_st_rec1_2 after 10 ns,
c_st_rec1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec1 = c_st_rec1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1 = c_st_rec1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00072.P12" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec1 <= transport
c_st_rec1_2 after 10 ns ,
c_st_rec1_1 after 20 ns ,
c_st_rec1_2 after 30 ns ,
c_st_rec1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec1 = c_st_rec1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec1 <= transport c_st_rec1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1 = c_st_rec1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00072" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00072" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00072" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P12 ;
--
PGEN_CHKP_13 :
process ( chk_st_rec2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P13" ,
"Transport transactions entirely completed",
chk_st_rec2 = 4 ) ;
end if ;
end process PGEN_CHKP_13 ;
--
P13 :
process ( s_st_rec2 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_rec2 <= transport
c_st_rec2_2 after 10 ns,
c_st_rec2_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec2 = c_st_rec2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2 = c_st_rec2_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00072.P13" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec2 <= transport
c_st_rec2_2 after 10 ns ,
c_st_rec2_1 after 20 ns ,
c_st_rec2_2 after 30 ns ,
c_st_rec2_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec2 = c_st_rec2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec2 <= transport c_st_rec2_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2 = c_st_rec2_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00072" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00072" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00072" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec2 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P13 ;
--
PGEN_CHKP_14 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P14" ,
"Transport transactions entirely completed",
chk_st_rec3 = 4 ) ;
end if ;
end process PGEN_CHKP_14 ;
--
P14 :
process ( s_st_rec3 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_rec3 <= transport
c_st_rec3_2 after 10 ns,
c_st_rec3_1 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3 = c_st_rec3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3 = c_st_rec3_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00072.P14" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_rec3 <= transport
c_st_rec3_2 after 10 ns ,
c_st_rec3_1 after 20 ns ,
c_st_rec3_2 after 30 ns ,
c_st_rec3_1 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3 = c_st_rec3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec3 <= transport c_st_rec3_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3 = c_st_rec3_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00072" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00072" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00072" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P14 ;
--
PGEN_CHKP_15 :
process ( chk_st_arr1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P15" ,
"Transport transactions entirely completed",
chk_st_arr1 = 4 ) ;
end if ;
end process PGEN_CHKP_15 ;
--
P15 :
process ( s_st_arr1 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_arr1 <= transport
c_st_arr1_2 after 10 ns,
c_st_arr1_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr1 = c_st_arr1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr1 = c_st_arr1_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00072.P15" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr1 <= transport
c_st_arr1_2 after 10 ns ,
c_st_arr1_1 after 20 ns ,
c_st_arr1_2 after 30 ns ,
c_st_arr1_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr1 = c_st_arr1_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr1 <= transport c_st_arr1_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr1 = c_st_arr1_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00072" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00072" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00072" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P15 ;
--
PGEN_CHKP_16 :
process ( chk_st_arr2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P16" ,
"Transport transactions entirely completed",
chk_st_arr2 = 4 ) ;
end if ;
end process PGEN_CHKP_16 ;
--
P16 :
process ( s_st_arr2 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_arr2 <= transport
c_st_arr2_2 after 10 ns,
c_st_arr2_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr2 = c_st_arr2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2 = c_st_arr2_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00072.P16" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr2 <= transport
c_st_arr2_2 after 10 ns ,
c_st_arr2_1 after 20 ns ,
c_st_arr2_2 after 30 ns ,
c_st_arr2_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr2 = c_st_arr2_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr2 <= transport c_st_arr2_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2 = c_st_arr2_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00072" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00072" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00072" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr2 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P16 ;
--
PGEN_CHKP_17 :
process ( chk_st_arr3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P17" ,
"Transport transactions entirely completed",
chk_st_arr3 = 4 ) ;
end if ;
end process PGEN_CHKP_17 ;
--
P17 :
process ( s_st_arr3 )
variable correct : boolean ;
variable counter : integer := 0 ;
variable savtime : time ;
--
procedure Proc1 is
begin
case counter is
when 0
=> s_st_arr3 <= transport
c_st_arr3_2 after 10 ns,
c_st_arr3_1 after 20 ns ;
--
when 1
=> correct :=
s_st_arr3 = c_st_arr3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr3 = c_st_arr3_1 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00072.P17" ,
"Multi transport transactions occurred on signal " &
"asg with simple name on LHS",
correct ) ;
s_st_arr3 <= transport
c_st_arr3_2 after 10 ns ,
c_st_arr3_1 after 20 ns ,
c_st_arr3_2 after 30 ns ,
c_st_arr3_1 after 40 ns ;
--
when 3
=> correct :=
s_st_arr3 = c_st_arr3_2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr3 <= transport c_st_arr3_1 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr3 = c_st_arr3_1 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00072" ,
"One transport transaction occurred on signal " &
"asg with simple name on LHS",
correct ) ;
test_report ( "ARCH00072" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00072" ,
"Old transactions were removed on signal " &
"asg with simple name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
Proc1 ;
end process P17 ;
--
--
end ARCH00072 ;
--
entity ENT00072_Test_Bench is
end ENT00072_Test_Bench ;
--
architecture ARCH00072_Test_Bench of ENT00072_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00072 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00072_Test_Bench ;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of a_clk
--
-- Generated
-- by: wig
-- on: Mon Jul 18 15:46:40 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: a_clk-rtl-a.vhd,v 1.2 2005/07/19 07:13:15 wig Exp $
-- $Date: 2005/07/19 07:13:15 $
-- $Log: a_clk-rtl-a.vhd,v $
-- Revision 1.2 2005/07/19 07:13:15 wig
-- Update testcases. Added highlow/nolowbus
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of a_clk
--
architecture rtl of a_clk is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component a_fsm --
-- No Generated Generics
port (
-- Generated Port for Entity a_fsm
alarm_button : in std_ulogic;
clk : in std_ulogic;
d9_core_di : in std_ulogic_vector(1 downto 0);
d9_core_en : in std_ulogic_vector(1 downto 0);
d9_core_pu : in std_ulogic_vector(1 downto 0);
data_core_do : out std_ulogic_vector(1 downto 0);
data_core_i33 : in std_ulogic_vector(7 downto 0);
data_core_i34 : in std_ulogic_vector(7 downto 0);
data_core_o35 : out std_ulogic_vector(7 downto 0);
data_core_o36 : out std_ulogic_vector(7 downto 0);
data_i1 : in std_ulogic_vector(7 downto 0);
data_o1 : out std_ulogic_vector(7 downto 0);
di : in std_ulogic_vector(7 downto 0);
di2 : in std_ulogic_vector(8 downto 0);
disp2_en : in std_ulogic_vector(7 downto 0);
disp_ls_port : out std_ulogic;
disp_ms_port : out std_ulogic;
iosel_bus : out std_ulogic_vector(7 downto 0);
iosel_bus_disp : out std_ulogic;
iosel_bus_ls_hr : out std_ulogic;
iosel_bus_ls_min : out std_ulogic;
iosel_bus_ms_hr : out std_ulogic;
iosel_bus_ms_min : out std_ulogic;
iosel_bus_nosel : out std_ulogic;
iosel_bus_port : out std_ulogic_vector(7 downto 0);
key : in std_ulogic_vector(3 downto 0);
load_new_a : out std_ulogic;
load_new_c : out std_ulogic;
one_second : in std_ulogic;
reset : in std_ulogic;
shift : out std_ulogic;
show_a : out std_ulogic;
show_new_time : out std_ulogic;
time_button : in std_ulogic
-- End of Generated Port for Entity a_fsm
);
end component;
-- ---------
component ios_e --
-- No Generated Generics
port (
-- Generated Port for Entity ios_e
p_mix_d9_di_go : out std_ulogic_vector(1 downto 0);
p_mix_d9_do_gi : in std_ulogic_vector(1 downto 0);
p_mix_d9_en_gi : in std_ulogic_vector(1 downto 0);
p_mix_d9_pu_gi : in std_ulogic_vector(1 downto 0);
p_mix_data_i1_go : out std_ulogic_vector(7 downto 0);
p_mix_data_i33_go : out std_ulogic_vector(7 downto 0);
p_mix_data_i34_go : out std_ulogic_vector(7 downto 0);
p_mix_data_o1_gi : in std_ulogic_vector(7 downto 0);
p_mix_data_o35_gi : in std_ulogic_vector(7 downto 0);
p_mix_data_o36_gi : in std_ulogic_vector(7 downto 0);
p_mix_di2_1_0_go : out std_ulogic_vector(1 downto 0);
p_mix_di2_7_3_go : out std_ulogic_vector(4 downto 0);
p_mix_disp2_1_0_gi : in std_ulogic_vector(1 downto 0);
p_mix_disp2_7_3_gi : in std_ulogic_vector(4 downto 0);
p_mix_disp2_en_1_0_gi : in std_ulogic_vector(1 downto 0);
p_mix_disp2_en_7_3_gi : in std_ulogic_vector(4 downto 0);
p_mix_display_ls_en_gi : in std_ulogic;
p_mix_display_ls_hr_gi : in std_ulogic_vector(6 downto 0);
p_mix_display_ls_min_gi : in std_ulogic_vector(6 downto 0);
p_mix_display_ms_en_gi : in std_ulogic;
p_mix_display_ms_hr_gi : in std_ulogic_vector(6 downto 0);
p_mix_display_ms_min_gi : in std_ulogic_vector(6 downto 0);
p_mix_iosel_0_gi : in std_ulogic;
p_mix_iosel_1_gi : in std_ulogic;
p_mix_iosel_2_gi : in std_ulogic;
p_mix_iosel_3_gi : in std_ulogic;
p_mix_iosel_4_gi : in std_ulogic;
p_mix_iosel_5_gi : in std_ulogic;
p_mix_iosel_bus_gi : in std_ulogic_vector(7 downto 0);
p_mix_iosel_disp_gi : in std_ulogic;
p_mix_iosel_ls_hr_gi : in std_ulogic;
p_mix_iosel_ls_min_gi : in std_ulogic;
p_mix_iosel_ms_hr_gi : in std_ulogic;
p_mix_nand_dir_gi : in std_ulogic;
p_mix_pad_di_12_gi : in std_ulogic;
p_mix_pad_di_13_gi : in std_ulogic;
p_mix_pad_di_14_gi : in std_ulogic;
p_mix_pad_di_15_gi : in std_ulogic;
p_mix_pad_di_16_gi : in std_ulogic;
p_mix_pad_di_17_gi : in std_ulogic;
p_mix_pad_di_18_gi : in std_ulogic;
p_mix_pad_di_1_gi : in std_ulogic;
p_mix_pad_di_31_gi : in std_ulogic;
p_mix_pad_di_32_gi : in std_ulogic;
p_mix_pad_di_33_gi : in std_ulogic;
p_mix_pad_di_34_gi : in std_ulogic;
p_mix_pad_di_39_gi : in std_ulogic;
p_mix_pad_di_40_gi : in std_ulogic;
p_mix_pad_do_12_go : out std_ulogic;
p_mix_pad_do_13_go : out std_ulogic;
p_mix_pad_do_14_go : out std_ulogic;
p_mix_pad_do_15_go : out std_ulogic;
p_mix_pad_do_16_go : out std_ulogic;
p_mix_pad_do_17_go : out std_ulogic;
p_mix_pad_do_18_go : out std_ulogic;
p_mix_pad_do_2_go : out std_ulogic;
p_mix_pad_do_31_go : out std_ulogic;
p_mix_pad_do_32_go : out std_ulogic;
p_mix_pad_do_35_go : out std_ulogic;
p_mix_pad_do_36_go : out std_ulogic;
p_mix_pad_do_39_go : out std_ulogic;
p_mix_pad_do_40_go : out std_ulogic;
p_mix_pad_en_12_go : out std_ulogic;
p_mix_pad_en_13_go : out std_ulogic;
p_mix_pad_en_14_go : out std_ulogic;
p_mix_pad_en_15_go : out std_ulogic;
p_mix_pad_en_16_go : out std_ulogic;
p_mix_pad_en_17_go : out std_ulogic;
p_mix_pad_en_18_go : out std_ulogic;
p_mix_pad_en_2_go : out std_ulogic;
p_mix_pad_en_31_go : out std_ulogic;
p_mix_pad_en_32_go : out std_ulogic;
p_mix_pad_en_35_go : out std_ulogic;
p_mix_pad_en_36_go : out std_ulogic;
p_mix_pad_en_39_go : out std_ulogic;
p_mix_pad_en_40_go : out std_ulogic;
p_mix_pad_pu_31_go : out std_ulogic;
p_mix_pad_pu_32_go : out std_ulogic
-- End of Generated Port for Entity ios_e
);
end component;
-- ---------
component pad_pads_e --
-- No Generated Generics
port (
-- Generated Port for Entity pad_pads_e
p_mix_pad_di_12_go : out std_ulogic;
p_mix_pad_di_13_go : out std_ulogic;
p_mix_pad_di_14_go : out std_ulogic;
p_mix_pad_di_15_go : out std_ulogic;
p_mix_pad_di_16_go : out std_ulogic;
p_mix_pad_di_17_go : out std_ulogic;
p_mix_pad_di_18_go : out std_ulogic;
p_mix_pad_di_1_go : out std_ulogic;
p_mix_pad_di_31_go : out std_ulogic;
p_mix_pad_di_32_go : out std_ulogic;
p_mix_pad_di_33_go : out std_ulogic;
p_mix_pad_di_34_go : out std_ulogic;
p_mix_pad_di_39_go : out std_ulogic;
p_mix_pad_di_40_go : out std_ulogic;
p_mix_pad_do_12_gi : in std_ulogic;
p_mix_pad_do_13_gi : in std_ulogic;
p_mix_pad_do_14_gi : in std_ulogic;
p_mix_pad_do_15_gi : in std_ulogic;
p_mix_pad_do_16_gi : in std_ulogic;
p_mix_pad_do_17_gi : in std_ulogic;
p_mix_pad_do_18_gi : in std_ulogic;
p_mix_pad_do_2_gi : in std_ulogic;
p_mix_pad_do_31_gi : in std_ulogic;
p_mix_pad_do_32_gi : in std_ulogic;
p_mix_pad_do_35_gi : in std_ulogic;
p_mix_pad_do_36_gi : in std_ulogic;
p_mix_pad_do_39_gi : in std_ulogic;
p_mix_pad_do_40_gi : in std_ulogic;
p_mix_pad_en_12_gi : in std_ulogic;
p_mix_pad_en_13_gi : in std_ulogic;
p_mix_pad_en_14_gi : in std_ulogic;
p_mix_pad_en_15_gi : in std_ulogic;
p_mix_pad_en_16_gi : in std_ulogic;
p_mix_pad_en_17_gi : in std_ulogic;
p_mix_pad_en_18_gi : in std_ulogic;
p_mix_pad_en_2_gi : in std_ulogic;
p_mix_pad_en_31_gi : in std_ulogic;
p_mix_pad_en_32_gi : in std_ulogic;
p_mix_pad_en_35_gi : in std_ulogic;
p_mix_pad_en_36_gi : in std_ulogic;
p_mix_pad_en_39_gi : in std_ulogic;
p_mix_pad_en_40_gi : in std_ulogic;
p_mix_pad_pu_31_gi : in std_ulogic;
p_mix_pad_pu_32_gi : in std_ulogic
-- End of Generated Port for Entity pad_pads_e
);
end component;
-- ---------
component testctrl_e --
-- No Generated Generics
port (
-- Generated Port for Entity testctrl_e
nand_dir : out std_ulogic;
nand_en : out std_ulogic
-- End of Generated Port for Entity testctrl_e
);
end component;
-- ---------
component alreg --
-- No Generated Generics
port (
-- Generated Port for Entity alreg
alarm_time : out std_ulogic_vector(3 downto 0);
load_new_a : in std_ulogic;
new_alarm_time : in std_ulogic_vector(3 downto 0)
-- End of Generated Port for Entity alreg
);
end component;
-- ---------
component count4 --
-- No Generated Generics
port (
-- Generated Port for Entity count4
current_time_ls_hr : out std_ulogic_vector(3 downto 0);
current_time_ls_min : out std_ulogic_vector(3 downto 0);
current_time_ms_hr : out std_ulogic_vector(3 downto 0);
current_time_ms_min : out std_ulogic_vector(3 downto 0);
load_new_c : in std_ulogic;
new_current_time_ls_hr : in std_ulogic_vector(3 downto 0);
new_current_time_ls_min : in std_ulogic_vector(3 downto 0);
new_current_time_ms_hr : in std_ulogic_vector(3 downto 0);
new_current_time_ms_min : in std_ulogic_vector(3 downto 0);
one_minute : in std_ulogic
-- End of Generated Port for Entity count4
);
end component;
-- ---------
component ddrv4 --
-- No Generated Generics
port (
-- Generated Port for Entity ddrv4
alarm_time_ls_hr : in std_ulogic_vector(3 downto 0);
alarm_time_ls_min : in std_ulogic_vector(3 downto 0);
alarm_time_ms_hr : in std_ulogic_vector(3 downto 0);
alarm_time_ms_min : in std_ulogic_vector(3 downto 0);
current_time_ls_hr : in std_ulogic_vector(3 downto 0);
current_time_ls_min : in std_ulogic_vector(3 downto 0);
current_time_ms_hr : in std_ulogic_vector(3 downto 0);
current_time_ms_min : in std_ulogic_vector(3 downto 0);
key_buffer_0 : in std_ulogic_vector(3 downto 0);
key_buffer_1 : in std_ulogic_vector(3 downto 0);
key_buffer_2 : in std_ulogic_vector(3 downto 0);
key_buffer_3 : in std_ulogic_vector(3 downto 0);
p_mix_display_ls_hr_go : out std_ulogic_vector(6 downto 0);
p_mix_display_ls_min_go : out std_ulogic_vector(6 downto 0);
p_mix_display_ms_hr_go : out std_ulogic_vector(6 downto 0);
p_mix_display_ms_min_go : out std_ulogic_vector(6 downto 0);
p_mix_sound_alarm_go : out std_ulogic;
show_a : in std_ulogic;
show_new_time : in std_ulogic
-- End of Generated Port for Entity ddrv4
);
end component;
-- ---------
component keypad --
-- No Generated Generics
port (
-- Generated Port for Entity keypad
columns : in std_ulogic_vector(2 downto 0);
rows : out std_ulogic_vector(3 downto 0)
-- End of Generated Port for Entity keypad
);
end component;
-- ---------
component keyscan --
-- No Generated Generics
port (
-- Generated Port for Entity keyscan
alarm_button : out std_ulogic;
columns : out std_ulogic_vector(2 downto 0);
key : out std_ulogic_vector(3 downto 0);
key_buffer_0 : out std_ulogic_vector(3 downto 0);
key_buffer_1 : out std_ulogic_vector(3 downto 0);
key_buffer_2 : out std_ulogic_vector(3 downto 0);
key_buffer_3 : out std_ulogic_vector(3 downto 0);
rows : in std_ulogic_vector(3 downto 0);
shift : in std_ulogic;
time_button : out std_ulogic
-- End of Generated Port for Entity keyscan
);
end component;
-- ---------
component timegen --
-- No Generated Generics
port (
-- Generated Port for Entity timegen
one_minute : out std_ulogic;
one_second : out std_ulogic;
stopwatch : in std_ulogic
-- End of Generated Port for Entity timegen
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal alarm_button : std_ulogic;
signal s_int_alarm_time_ls_hr : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_alarm_time_ls_min : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_alarm_time_ms_hr : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_alarm_time_ms_min : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal columns : std_ulogic_vector(2 downto 0);
signal s_int_current_time_ls_hr : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_current_time_ls_min : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_current_time_ms_hr : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_current_time_ms_min : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal d9_di : std_ulogic_vector(1 downto 0);
signal d9_do : std_ulogic_vector(1 downto 0);
signal d9_en : std_ulogic_vector(1 downto 0);
signal d9_pu : std_ulogic_vector(1 downto 0);
signal data_i1 : std_ulogic_vector(7 downto 0);
signal data_i33 : std_ulogic_vector(7 downto 0);
signal data_i34 : std_ulogic_vector(7 downto 0);
signal data_o1 : std_ulogic_vector(7 downto 0);
signal data_o35 : std_ulogic_vector(7 downto 0);
signal data_o36 : std_ulogic_vector(7 downto 0);
signal di2 : std_ulogic_vector(8 downto 0);
signal disp2 : std_ulogic_vector(7 downto 0);
signal disp2_en : std_ulogic_vector(7 downto 0);
signal display_ls_en : std_ulogic;
signal s_int_display_ls_hr : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_display_ls_min : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_en : std_ulogic;
signal s_int_display_ms_hr : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_display_ms_min : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_0 : std_ulogic;
signal iosel_1 : std_ulogic;
signal iosel_2 : std_ulogic;
signal iosel_3 : std_ulogic;
signal iosel_4 : std_ulogic;
signal iosel_5 : std_ulogic;
-- __I_OUT_OPEN signal iosel_6 : std_ulogic;
-- __I_OUT_OPEN signal iosel_7 : std_ulogic;
signal iosel_bus : std_ulogic_vector(7 downto 0);
signal iosel_disp : std_ulogic;
signal iosel_ls_hr : std_ulogic;
signal iosel_ls_min : std_ulogic;
signal iosel_ms_hr : std_ulogic;
-- __I_OUT_OPEN signal iosel_ms_min : std_ulogic;
-- __I_OUT_OPEN signal iosel_nosel : std_ulogic;
signal key : std_ulogic_vector(3 downto 0);
signal s_int_key_buffer_0 : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_key_buffer_1 : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_key_buffer_2 : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_key_buffer_3 : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal load_new_a : std_ulogic;
signal load_new_c : std_ulogic;
signal nand_dir : std_ulogic;
-- __I_OUT_OPEN signal nand_en : std_ulogic;
signal one_minute : std_ulogic;
signal one_sec_pulse : std_ulogic;
signal pad_di_1 : std_ulogic;
signal pad_di_12 : std_ulogic;
signal pad_di_13 : std_ulogic;
signal pad_di_14 : std_ulogic;
signal pad_di_15 : std_ulogic;
signal pad_di_16 : std_ulogic;
signal pad_di_17 : std_ulogic;
signal pad_di_18 : std_ulogic;
signal pad_di_31 : std_ulogic;
signal pad_di_32 : std_ulogic;
signal pad_di_33 : std_ulogic;
signal pad_di_34 : std_ulogic;
signal pad_di_39 : std_ulogic;
signal pad_di_40 : std_ulogic;
signal pad_do_12 : std_ulogic;
signal pad_do_13 : std_ulogic;
signal pad_do_14 : std_ulogic;
signal pad_do_15 : std_ulogic;
signal pad_do_16 : std_ulogic;
signal pad_do_17 : std_ulogic;
signal pad_do_18 : std_ulogic;
signal pad_do_2 : std_ulogic;
signal pad_do_31 : std_ulogic;
signal pad_do_32 : std_ulogic;
signal pad_do_35 : std_ulogic;
signal pad_do_36 : std_ulogic;
signal pad_do_39 : std_ulogic;
signal pad_do_40 : std_ulogic;
signal pad_en_12 : std_ulogic;
signal pad_en_13 : std_ulogic;
signal pad_en_14 : std_ulogic;
signal pad_en_15 : std_ulogic;
signal pad_en_16 : std_ulogic;
signal pad_en_17 : std_ulogic;
signal pad_en_18 : std_ulogic;
signal pad_en_2 : std_ulogic;
signal pad_en_31 : std_ulogic;
signal pad_en_32 : std_ulogic;
signal pad_en_35 : std_ulogic;
signal pad_en_36 : std_ulogic;
signal pad_en_39 : std_ulogic;
signal pad_en_40 : std_ulogic;
signal pad_pu_31 : std_ulogic;
signal pad_pu_32 : std_ulogic;
signal rows : std_ulogic_vector(3 downto 0);
signal shift : std_ulogic;
signal s_int_show_a : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_show_new_time : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal time_button : std_ulogic;
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
s_int_alarm_time_ls_hr <= alarm_time_ls_hr; -- __I_I_BUS_PORT
s_int_alarm_time_ls_min <= alarm_time_ls_min; -- __I_I_BUS_PORT
s_int_alarm_time_ms_hr <= alarm_time_ms_hr; -- __I_I_BUS_PORT
s_int_alarm_time_ms_min <= alarm_time_ms_min; -- __I_I_BUS_PORT
s_int_current_time_ls_hr <= current_time_ls_hr; -- __I_I_BUS_PORT
s_int_current_time_ls_min <= current_time_ls_min; -- __I_I_BUS_PORT
s_int_current_time_ms_hr <= current_time_ms_hr; -- __I_I_BUS_PORT
s_int_current_time_ms_min <= current_time_ms_min; -- __I_I_BUS_PORT
display_ls_hr <= s_int_display_ls_hr; -- __I_O_BUS_PORT
display_ls_min <= s_int_display_ls_min; -- __I_O_BUS_PORT
display_ms_hr <= s_int_display_ms_hr; -- __I_O_BUS_PORT
display_ms_min <= s_int_display_ms_min; -- __I_O_BUS_PORT
s_int_key_buffer_0 <= key_buffer_0; -- __I_I_BUS_PORT
s_int_key_buffer_1 <= key_buffer_1; -- __I_I_BUS_PORT
s_int_key_buffer_2 <= key_buffer_2; -- __I_I_BUS_PORT
s_int_key_buffer_3 <= key_buffer_3; -- __I_I_BUS_PORT
s_int_show_a <= show_a; -- __I_I_BIT_PORT
s_int_show_new_time <= show_new_time; -- __I_I_BIT_PORT
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for control
control: a_fsm
port map (
alarm_button => alarm_button,
clk => clk,
d9_core_di => d9_di, -- d9io
d9_core_en => d9_en, -- d9io
d9_core_pu => d9_pu, -- d9io
data_core_do => d9_do, -- d9io
data_core_i33 => data_i33, -- io data
data_core_i34 => data_i34, -- io data
data_core_o35 => data_o35, -- io data
data_core_o36 => data_o36, -- io data
data_i1 => data_i1, -- io data
data_o1 => data_o1, -- io data
di => disp2, -- io data
di2 => di2, -- io data
disp2_en => disp2_en, -- io data
disp_ls_port => display_ls_en, -- io_enable
disp_ms_port => display_ms_en, -- io_enable
iosel_bus(0) => iosel_0, -- __I_BIT_TO_BUSPORT -- IO_Select
iosel_bus(1) => iosel_1, -- __I_BIT_TO_BUSPORT -- IO_Select
iosel_bus(2) => iosel_2, -- __I_BIT_TO_BUSPORT -- IO_Select
iosel_bus(3) => iosel_3, -- __I_BIT_TO_BUSPORT -- IO_Select
iosel_bus(4) => iosel_4, -- __I_BIT_TO_BUSPORT -- IO_Select
iosel_bus(5) => iosel_5, -- __I_BIT_TO_BUSPORT -- IO_Select
iosel_bus(6) => open, -- __I_BIT_TO_BUSPORT -- IO_Select -- __I_OUT_OPEN
iosel_bus(7) => open, -- __I_BIT_TO_BUSPORT -- IO_Select -- __I_OUT_OPEN
iosel_bus_disp => iosel_disp, -- IO_Select
iosel_bus_ls_hr => iosel_ls_hr, -- IO_Select
iosel_bus_ls_min => iosel_ls_min, -- IO_Select
iosel_bus_ms_hr => iosel_ms_hr, -- IO_Select
iosel_bus_ms_min => open, -- IO_Select -- __I_OUT_OPEN
iosel_bus_nosel => open, -- IO_Select -- __I_OUT_OPEN
iosel_bus_port => iosel_bus, -- io data
key => key,
load_new_a => load_new_a,
load_new_c => load_new_c,
one_second => one_sec_pulse,
reset => reset,
shift => shift,
show_a => s_int_show_a,
show_new_time => s_int_show_new_time,
time_button => time_button
);
-- End of Generated Instance Port Map for control
-- Generated Instance Port Map for ios
ios: ios_e
port map (
p_mix_d9_di_go => d9_di, -- d9io
p_mix_d9_do_gi => d9_do, -- d9io
p_mix_d9_en_gi => d9_en, -- d9io
p_mix_d9_pu_gi => d9_pu, -- d9io
p_mix_data_i1_go => data_i1, -- io data
p_mix_data_i33_go => data_i33, -- io data
p_mix_data_i34_go => data_i34, -- io data
p_mix_data_o1_gi => data_o1, -- io data
p_mix_data_o35_gi => data_o35, -- io data
p_mix_data_o36_gi => data_o36, -- io data
p_mix_di2_1_0_go => di2(1 downto 0), -- io data
p_mix_di2_7_3_go => di2(7 downto 3), -- io data
p_mix_disp2_1_0_gi => disp2(1 downto 0), -- io data
p_mix_disp2_7_3_gi => disp2(7 downto 3), -- io data
p_mix_disp2_en_1_0_gi => disp2_en(1 downto 0), -- io data
p_mix_disp2_en_7_3_gi => disp2_en(7 downto 3), -- io data
p_mix_display_ls_en_gi => display_ls_en, -- io_enable
p_mix_display_ls_hr_gi => s_int_display_ls_hr, -- Display storage buffer 2 ls_hr
p_mix_display_ls_min_gi => s_int_display_ls_min, -- Display storage buffer 0 ls_min
p_mix_display_ms_en_gi => display_ms_en, -- io_enable
p_mix_display_ms_hr_gi => s_int_display_ms_hr, -- Display storage buffer 3 ms_hr
p_mix_display_ms_min_gi => s_int_display_ms_min, -- Display storage buffer 1 ms_min
p_mix_iosel_0_gi => iosel_0, -- IO_Select
p_mix_iosel_1_gi => iosel_1, -- IO_Select
p_mix_iosel_2_gi => iosel_2, -- IO_Select
p_mix_iosel_3_gi => iosel_3, -- IO_Select
p_mix_iosel_4_gi => iosel_4, -- IO_Select
p_mix_iosel_5_gi => iosel_5, -- IO_Select
p_mix_iosel_bus_gi => iosel_bus, -- io data
p_mix_iosel_disp_gi => iosel_disp, -- IO_Select
p_mix_iosel_ls_hr_gi => iosel_ls_hr, -- IO_Select
p_mix_iosel_ls_min_gi => iosel_ls_min, -- IO_Select
p_mix_iosel_ms_hr_gi => iosel_ms_hr, -- IO_Select
p_mix_nand_dir_gi => nand_dir, -- Direction (X17)
p_mix_pad_di_12_gi => pad_di_12, -- data in from pad
p_mix_pad_di_13_gi => pad_di_13, -- data in from pad
p_mix_pad_di_14_gi => pad_di_14, -- data in from pad
p_mix_pad_di_15_gi => pad_di_15, -- data in from pad
p_mix_pad_di_16_gi => pad_di_16, -- data in from pad
p_mix_pad_di_17_gi => pad_di_17, -- data in from pad
p_mix_pad_di_18_gi => pad_di_18, -- data in from pad
p_mix_pad_di_1_gi => pad_di_1, -- data in from pad
p_mix_pad_di_31_gi => pad_di_31, -- data in from pad
p_mix_pad_di_32_gi => pad_di_32, -- data in from pad
p_mix_pad_di_33_gi => pad_di_33, -- data in from pad
p_mix_pad_di_34_gi => pad_di_34, -- data in from pad
p_mix_pad_di_39_gi => pad_di_39, -- data in from pad
p_mix_pad_di_40_gi => pad_di_40, -- data in from pad
p_mix_pad_do_12_go => pad_do_12, -- data out to pad
p_mix_pad_do_13_go => pad_do_13, -- data out to pad
p_mix_pad_do_14_go => pad_do_14, -- data out to pad
p_mix_pad_do_15_go => pad_do_15, -- data out to pad
p_mix_pad_do_16_go => pad_do_16, -- data out to pad
p_mix_pad_do_17_go => pad_do_17, -- data out to pad
p_mix_pad_do_18_go => pad_do_18, -- data out to pad
p_mix_pad_do_2_go => pad_do_2, -- data out to pad
p_mix_pad_do_31_go => pad_do_31, -- data out to pad
p_mix_pad_do_32_go => pad_do_32, -- data out to pad
p_mix_pad_do_35_go => pad_do_35, -- data out to pad
p_mix_pad_do_36_go => pad_do_36, -- data out to pad
p_mix_pad_do_39_go => pad_do_39, -- data out to pad
p_mix_pad_do_40_go => pad_do_40, -- data out to pad
p_mix_pad_en_12_go => pad_en_12, -- pad output enable
p_mix_pad_en_13_go => pad_en_13, -- pad output enable
p_mix_pad_en_14_go => pad_en_14, -- pad output enable
p_mix_pad_en_15_go => pad_en_15, -- pad output enable
p_mix_pad_en_16_go => pad_en_16, -- pad output enable
p_mix_pad_en_17_go => pad_en_17, -- pad output enable
p_mix_pad_en_18_go => pad_en_18, -- pad output enable
p_mix_pad_en_2_go => pad_en_2, -- pad output enable
p_mix_pad_en_31_go => pad_en_31, -- pad output enable
p_mix_pad_en_32_go => pad_en_32, -- pad output enable
p_mix_pad_en_35_go => pad_en_35, -- pad output enable
p_mix_pad_en_36_go => pad_en_36, -- pad output enable
p_mix_pad_en_39_go => pad_en_39, -- pad output enable
p_mix_pad_en_40_go => pad_en_40, -- pad output enable
p_mix_pad_pu_31_go => pad_pu_31, -- pull-up control
p_mix_pad_pu_32_go => pad_pu_32 -- pull-up control
);
-- End of Generated Instance Port Map for ios
-- Generated Instance Port Map for pad_pads
pad_pads: pad_pads_e
port map (
p_mix_pad_di_12_go => pad_di_12, -- data in from pad
p_mix_pad_di_13_go => pad_di_13, -- data in from pad
p_mix_pad_di_14_go => pad_di_14, -- data in from pad
p_mix_pad_di_15_go => pad_di_15, -- data in from pad
p_mix_pad_di_16_go => pad_di_16, -- data in from pad
p_mix_pad_di_17_go => pad_di_17, -- data in from pad
p_mix_pad_di_18_go => pad_di_18, -- data in from pad
p_mix_pad_di_1_go => pad_di_1, -- data in from pad
p_mix_pad_di_31_go => pad_di_31, -- data in from pad
p_mix_pad_di_32_go => pad_di_32, -- data in from pad
p_mix_pad_di_33_go => pad_di_33, -- data in from pad
p_mix_pad_di_34_go => pad_di_34, -- data in from pad
p_mix_pad_di_39_go => pad_di_39, -- data in from pad
p_mix_pad_di_40_go => pad_di_40, -- data in from pad
p_mix_pad_do_12_gi => pad_do_12, -- data out to pad
p_mix_pad_do_13_gi => pad_do_13, -- data out to pad
p_mix_pad_do_14_gi => pad_do_14, -- data out to pad
p_mix_pad_do_15_gi => pad_do_15, -- data out to pad
p_mix_pad_do_16_gi => pad_do_16, -- data out to pad
p_mix_pad_do_17_gi => pad_do_17, -- data out to pad
p_mix_pad_do_18_gi => pad_do_18, -- data out to pad
p_mix_pad_do_2_gi => pad_do_2, -- data out to pad
p_mix_pad_do_31_gi => pad_do_31, -- data out to pad
p_mix_pad_do_32_gi => pad_do_32, -- data out to pad
p_mix_pad_do_35_gi => pad_do_35, -- data out to pad
p_mix_pad_do_36_gi => pad_do_36, -- data out to pad
p_mix_pad_do_39_gi => pad_do_39, -- data out to pad
p_mix_pad_do_40_gi => pad_do_40, -- data out to pad
p_mix_pad_en_12_gi => pad_en_12, -- pad output enable
p_mix_pad_en_13_gi => pad_en_13, -- pad output enable
p_mix_pad_en_14_gi => pad_en_14, -- pad output enable
p_mix_pad_en_15_gi => pad_en_15, -- pad output enable
p_mix_pad_en_16_gi => pad_en_16, -- pad output enable
p_mix_pad_en_17_gi => pad_en_17, -- pad output enable
p_mix_pad_en_18_gi => pad_en_18, -- pad output enable
p_mix_pad_en_2_gi => pad_en_2, -- pad output enable
p_mix_pad_en_31_gi => pad_en_31, -- pad output enable
p_mix_pad_en_32_gi => pad_en_32, -- pad output enable
p_mix_pad_en_35_gi => pad_en_35, -- pad output enable
p_mix_pad_en_36_gi => pad_en_36, -- pad output enable
p_mix_pad_en_39_gi => pad_en_39, -- pad output enable
p_mix_pad_en_40_gi => pad_en_40, -- pad output enable
p_mix_pad_pu_31_gi => pad_pu_31, -- pull-up control
p_mix_pad_pu_32_gi => pad_pu_32 -- pull-up control
);
-- End of Generated Instance Port Map for pad_pads
-- Generated Instance Port Map for test_ctrl
test_ctrl: testctrl_e
port map (
nand_dir => nand_dir, -- Direction (X17)
nand_en => open -- Enable (X17) -- __I_OUT_OPEN
);
-- End of Generated Instance Port Map for test_ctrl
-- Generated Instance Port Map for u0_alreg
u0_alreg: alreg
port map (
alarm_time => s_int_alarm_time_ls_min, -- Display storage buffer 0 ls_min
load_new_a => load_new_a,
new_alarm_time => s_int_key_buffer_0 -- Display storage buffer 0 ls_min
);
-- End of Generated Instance Port Map for u0_alreg
-- Generated Instance Port Map for u1_alreg
u1_alreg: alreg
port map (
alarm_time => s_int_alarm_time_ms_min, -- Display storage buffer 1 ms_min
load_new_a => load_new_a,
new_alarm_time => s_int_key_buffer_1 -- Display storage buffer 1 ms_min
);
-- End of Generated Instance Port Map for u1_alreg
-- Generated Instance Port Map for u2_alreg
u2_alreg: alreg
port map (
alarm_time => s_int_alarm_time_ls_hr, -- Display storage buffer 2 ls_hr
load_new_a => load_new_a,
new_alarm_time => s_int_key_buffer_2 -- Display storage buffer 2 ls_hr
);
-- End of Generated Instance Port Map for u2_alreg
-- Generated Instance Port Map for u3_alreg
u3_alreg: alreg
port map (
alarm_time => s_int_alarm_time_ms_hr, -- Display storage buffer 3 ms_hr
load_new_a => load_new_a,
new_alarm_time => s_int_key_buffer_3 -- Display storage buffer 3 ms_hr
);
-- End of Generated Instance Port Map for u3_alreg
-- Generated Instance Port Map for u_counter
u_counter: count4
port map (
current_time_ls_hr => s_int_current_time_ls_hr, -- Display storage buffer 2 ls_hr
current_time_ls_min => s_int_current_time_ls_min, -- Display storage buffer 0 ls_min
current_time_ms_hr => s_int_current_time_ms_hr, -- Display storage buffer 3 ms_hr
current_time_ms_min => s_int_current_time_ms_min, -- Display storage buffer 1 ms_min
load_new_c => load_new_c,
new_current_time_ls_hr => s_int_key_buffer_2, -- Display storage buffer 2 ls_hr
new_current_time_ls_min => s_int_key_buffer_0, -- Display storage buffer 0 ls_min
new_current_time_ms_hr => s_int_key_buffer_3, -- Display storage buffer 3 ms_hr
new_current_time_ms_min => s_int_key_buffer_1, -- Display storage buffer 1 ms_min
one_minute => one_minute
);
-- End of Generated Instance Port Map for u_counter
-- Generated Instance Port Map for u_ddrv4
u_ddrv4: ddrv4
port map (
alarm_time_ls_hr => s_int_alarm_time_ls_hr, -- Display storage buffer 2 ls_hr
alarm_time_ls_min => s_int_alarm_time_ls_min, -- Display storage buffer 0 ls_min
alarm_time_ms_hr => s_int_alarm_time_ms_hr, -- Display storage buffer 3 ms_hr
alarm_time_ms_min => s_int_alarm_time_ms_min, -- Display storage buffer 1 ms_min
current_time_ls_hr => s_int_current_time_ls_hr, -- Display storage buffer 2 ls_hr
current_time_ls_min => s_int_current_time_ls_min, -- Display storage buffer 0 ls_min
current_time_ms_hr => s_int_current_time_ms_hr, -- Display storage buffer 3 ms_hr
current_time_ms_min => s_int_current_time_ms_min, -- Display storage buffer 1 ms_min
key_buffer_0 => s_int_key_buffer_0, -- Display storage buffer 0 ls_min
key_buffer_1 => s_int_key_buffer_1, -- Display storage buffer 1 ms_min
key_buffer_2 => s_int_key_buffer_2, -- Display storage buffer 2 ls_hr
key_buffer_3 => s_int_key_buffer_3, -- Display storage buffer 3 ms_hr
p_mix_display_ls_hr_go => s_int_display_ls_hr, -- Display storage buffer 2 ls_hr
p_mix_display_ls_min_go => s_int_display_ls_min, -- Display storage buffer 0 ls_min
p_mix_display_ms_hr_go => s_int_display_ms_hr, -- Display storage buffer 3 ms_hr
p_mix_display_ms_min_go => s_int_display_ms_min, -- Display storage buffer 1 ms_min
p_mix_sound_alarm_go => sound_alarm,
show_a => s_int_show_a,
show_new_time => s_int_show_new_time
);
-- End of Generated Instance Port Map for u_ddrv4
-- Generated Instance Port Map for u_keypad
u_keypad: keypad
port map (
columns => columns,
rows => rows -- Keypad Output
);
-- End of Generated Instance Port Map for u_keypad
-- Generated Instance Port Map for u_keyscan
u_keyscan: keyscan
port map (
alarm_button => alarm_button,
columns => columns,
key => key,
key_buffer_0 => s_int_key_buffer_0, -- Display storage buffer 0 ls_min
key_buffer_1 => s_int_key_buffer_1, -- Display storage buffer 1 ms_min
key_buffer_2 => s_int_key_buffer_2, -- Display storage buffer 2 ls_hr
key_buffer_3 => s_int_key_buffer_3, -- Display storage buffer 3 ms_hr
rows => rows, -- Keypad Output
shift => shift,
time_button => time_button
);
-- End of Generated Instance Port Map for u_keyscan
-- Generated Instance Port Map for u_timegen
u_timegen: timegen
port map (
one_minute => one_minute,
one_second => one_sec_pulse,
stopwatch => stopwatch -- Driven by reset
);
-- End of Generated Instance Port Map for u_timegen
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
-------------------------------------------------------------------------------
--! @file hostInterface.vhd
--
--! @brief toplevel of host interface
--
--! @details The toplevel instantiates the necessary components for the
--! host interface like the Dynamic Bridge and the Status-/Control Registers.
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2012
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! use global library
use work.global.all;
--! use host interface package for specific types
use work.hostInterfacePkg.all;
entity hostInterface is
generic (
--! Version major
gVersionMajor : natural := 16#FF#;
--! Version minor
gVersionMinor : natural := 16#FF#;
--! Version revision
gVersionRevision : natural := 16#FF#;
--! Version count
gVersionCount : natural := 0;
--! Use memory blocks or registers for translation address storage (registers = 0, memory blocks /= 0)
gBridgeUseMemBlock : natural := 0;
-- Base address mapping
--! Base address Dynamic Buffer 0
gBaseDynBuf0 : natural := 16#00800#;
--! Base address Dynamic Buffer 1
gBaseDynBuf1 : natural := 16#01000#;
--! Base address Error Counter
gBaseErrCntr : natural := 16#01800#;
--! Base address TX NMT Queue
gBaseTxNmtQ : natural := 16#02800#;
--! Base address TX Generic Queue
gBaseTxGenQ : natural := 16#03800#;
--! Base address TX SyncRequest Queue
gBaseTxSynQ : natural := 16#04800#;
--! Base address TX Virtual Ethernet Queue
gBaseTxVetQ : natural := 16#05800#;
--! Base address RX Virtual Ethernet Queue
gBaseRxVetQ : natural := 16#06800#;
--! Base address Kernel-to-User Queue
gBaseK2UQ : natural := 16#07000#;
--! Base address User-to-Kernel Queue
gBaseU2KQ : natural := 16#09000#;
--! Base address Tpdo
gBaseTpdo : natural := 16#0B000#;
--! Base address Rpdo
gBaseRpdo : natural := 16#0E000#;
--! Base address Reserved (-1 = high address of Rpdo)
gBaseRes : natural := 16#14000#
);
port (
--! Clock Source input
iClk : in std_logic;
--! Reset Source input
iRst : in std_logic;
-- Memory Mapped Slave for Host
--! MM slave host address
iHostAddress : in std_logic_vector(16 downto 2);
--! MM slave host byteenable
iHostByteenable : in std_logic_vector(3 downto 0);
--! MM slave host read
iHostRead : in std_logic;
--! MM slave host readdata
oHostReaddata : out std_logic_vector(31 downto 0);
--! MM slave host write
iHostWrite : in std_logic;
--! MM slave host writedata
iHostWritedata : in std_logic_vector(31 downto 0);
--! MM slave host waitrequest
oHostWaitrequest : out std_logic;
-- Memory Mapped Slave for PCP
--! MM slave pcp address
iPcpAddress : in std_logic_vector(10 downto 2);
--! MM slave pcp byteenable
iPcpByteenable : in std_logic_vector(3 downto 0);
--! MM slave pcp read
iPcpRead : in std_logic;
--! MM slave pcp readdata
oPcpReaddata : out std_logic_vector(31 downto 0);
--! MM slave pcp write
iPcpWrite : in std_logic;
--! MM slave pcp writedata
iPcpWritedata : in std_logic_vector(31 downto 0);
--! MM slave pcp waitrequest
oPcpWaitrequest : out std_logic;
-- Memory Mapped Master for Host via Dynamic Bridge
--! MM master hostBridge address
oHostBridgeAddress : out std_logic_vector(29 downto 0);
--! MM master hostBridge byteenable
oHostBridgeByteenable : out std_logic_vector(3 downto 0);
--! MM master hostBridge read
oHostBridgeRead : out std_logic;
--! MM master hostBridge readdata
iHostBridgeReaddata : in std_logic_vector(31 downto 0);
--! MM master hostBridge write
oHostBridgeWrite : out std_logic;
--! MM master hostBridge writedata
oHostBridgeWritedata : out std_logic_vector(31 downto 0);
--! MM master hostBridge waitrequest
iHostBridgeWaitrequest : in std_logic;
--! Interrupt internal sync signal (from openMAC)
iIrqIntSync : in std_logic;
--! External sync source
iIrqExtSync : in std_logic;
--! Interrupt output signal
oIrq : out std_logic;
--! Node Id
iNodeId : in std_logic_vector(7 downto 0);
--! POWERLINK Error LED
oPlkLedError : out std_logic;
--! POWERLINK Status LED
oPlkLedStatus : out std_logic
);
end hostInterface;
architecture Rtl of hostInterface is
--! Magic
constant cMagic : natural := 16#504C4B00#;
--! Base address array
constant cBaseAddressArray : tArrayStd32 := (
std_logic_vector(to_unsigned(gBaseDynBuf0, cArrayStd32ElementSize)),
std_logic_vector(to_unsigned(gBaseDynBuf1, cArrayStd32ElementSize)),
std_logic_vector(to_unsigned(gBaseErrCntr, cArrayStd32ElementSize)),
std_logic_vector(to_unsigned(gBaseTxNmtQ, cArrayStd32ElementSize)),
std_logic_vector(to_unsigned(gBaseTxGenQ, cArrayStd32ElementSize)),
std_logic_vector(to_unsigned(gBaseTxSynQ, cArrayStd32ElementSize)),
std_logic_vector(to_unsigned(gBaseTxVetQ, cArrayStd32ElementSize)),
std_logic_vector(to_unsigned(gBaseRxVetQ, cArrayStd32ElementSize)),
std_logic_vector(to_unsigned(gBaseK2UQ, cArrayStd32ElementSize)),
std_logic_vector(to_unsigned(gBaseU2KQ, cArrayStd32ElementSize)),
std_logic_vector(to_unsigned(gBaseTpdo, cArrayStd32ElementSize)),
std_logic_vector(to_unsigned(gBaseRpdo, cArrayStd32ElementSize)),
std_logic_vector(to_unsigned(gBaseRes, cArrayStd32ElementSize))
);
--! Base address array count
constant cBaseAddressArrayCount : natural := cBaseAddressArray'length;
--! Base address set by host
constant cBaseAddressHostCount : natural := 2;
--! Base address set by pcp
constant cBaseAddressPcpCount : natural := cBaseAddressArrayCount-cBaseAddressHostCount;
--! Number of interrupt sources (sync not included)
constant cIrqSourceCount : natural := 3;
--! Bridge fsm type
type tFsm is (
sIdle,
sReqAddr,
sAccess,
sDone
);
--! select the bridge logic
signal bridgeSel : std_logic;
--! invalid address range selected
signal invalidSel : std_logic;
--! select status control registers
signal statCtrlSel : std_logic;
--! write status control register
signal statCtrlWrite : std_logic;
--! read status control register
signal statCtrlRead : std_logic;
--! waitrequest from status/control
signal statCtrlWaitrequest : std_logic;
--! readdata from status/control
signal statCtrlReaddata : std_logic_vector(oHostReaddata'range);
--! Bridge request signal
signal bridgeRequest : std_logic;
--! Bridge enable control
signal bridgeEnable : std_logic;
--! Bridge address is valid
signal bridgeAddrValid : std_logic;
--! LED from status/control registers
signal statCtrlLed : std_logic_vector(1 downto 0);
--! The magic bridge outputs the dword address
signal hostBridgeAddress_dword : std_logic_vector(oHostBridgeAddress'length-1 downto 2);
--! Bridge transfer done strobe
signal bridgeTfDone : std_logic;
--! Bridge read data
signal bridgeReaddata : std_logic_vector(iHostBridgeReaddata'range);
--! Bridge state machine
signal fsm : tFsm;
--! Bridge state machine, next state
signal fsm_next : tFsm;
-- base set signals
--! BaseSet Write
signal baseSetWrite : std_logic;
--! BaseSet Read
signal baseSetRead : std_logic;
--! BaseSet byteenable
signal baseSetByteenable : std_logic_vector(3 downto 0);
--! BaseSet Writedata
signal baseSetWritedata : std_logic_vector(hostBridgeAddress_dword'range);
--! BaseSet Readdata
signal baseSetReaddata : std_logic_vector(hostBridgeAddress_dword'range);
--! BaseSet Address
signal baseSetAddress : std_logic_vector(logDualis(cBaseAddressArrayCount)-1 downto 0);
--! BaseSet acknowledge
signal baseSetAck : std_logic;
-- interrupt signals
--! Irq master enable
signal irqMasterEnable : std_logic;
--! Irq source enable
signal irqSourceEnable : std_logic_vector(cIrqSourceCount downto 0);
--! Irq acknowledge
signal irqAcknowledge : std_logic_vector(cIrqSourceCount downto 0);
--! Irq source pending
signal irqSourcePending : std_logic_vector(cIrqSourceCount downto 0);
--! Irq source set (no sync!)
signal irqSourceSet : std_logic_vector(cIrqSourceCount downto 1);
--! sync signal
signal syncSig : std_logic;
--! synchronized ext sync
signal extSync_sync : std_logic;
--! external sync signal
signal extSyncEnable : std_logic;
--! external sync config
signal extSyncConfig : std_logic_vector(cExtSyncEdgeConfigWidth-1 downto 0);
--! external sync signal detected rising edge
signal extSync_rising : std_logic;
--! external sync signal detected falling edge
signal extSync_falling : std_logic;
--! external sync signal detected any edge
signal extSync_any : std_logic;
begin
-- select status/control registers if host address is below 2 kB
statCtrlSel <= cActivated when iHostAddress < cBaseAddressArray(0)(iHostAddress'range) else
cInactivated;
-- select invalid address
invalidSel <= cActivated when iHostAddress >= cBaseAddressArray(cBaseAddressArrayCount-1)(iHostAddress'range) else
cInactivated;
-- bridge is selected if status/control registers are not accessed
bridgeSel <= cInactivated when bridgeEnable = cInactivated else
cInactivated when invalidSel = cActivated else
cInactivated when statCtrlSel = cActivated else
cActivated;
-- create write and read strobe for status/control registers
statCtrlWrite <= iHostWrite and statCtrlSel;
statCtrlRead <= iHostRead and statCtrlSel;
-- host waitrequest from status/control, bridge or invalid
oHostWaitrequest <= statCtrlWaitrequest when statCtrlSel = cActivated else
cInactivated when bridgeEnable = cInactivated else
not bridgeTfDone when bridgeSel = cActivated else
not invalidSel;
-- host readdata from status/control or bridge
oHostReaddata <= bridgeReaddata when bridgeSel = cActivated else
statCtrlReaddata when statCtrlSel = cActivated else
(others => cInactivated);
-- select external sync if enabled, otherwise rx irq signal
syncSig <= iIrqIntSync when extSyncEnable /= cActivated else
extSync_rising when extSyncConfig = cExtSyncEdgeRis else
extSync_falling when extSyncConfig = cExtSyncEdgeFal else
extSync_any when extSyncConfig = cExtSyncEdgeAny else
cInactivated;
--! The bridge state machine handles the address translation of
--! dynamicBridge and finalizes the access to the host bridge master.
theFsmCom : process (
fsm,
bridgeSel,
bridgeAddrValid,
iHostRead,
iHostWrite,
iHostBridgeWaitrequest
)
begin
--default
fsm_next <= fsm;
case fsm is
when sIdle =>
if ( (iHostRead = cActivated or iHostWrite = cActivated) and
bridgeSel = cActivated) then
fsm_next <= sReqAddr;
end if;
when sReqAddr =>
if bridgeAddrValid = cActivated then
fsm_next <= sAccess;
end if;
when sAccess =>
if iHostBridgeWaitrequest = cInactivated then
fsm_next <= sDone;
end if;
when sDone =>
fsm_next <= sIdle;
end case;
end process;
bridgeRequest <= cActivated when fsm = sReqAddr else cInactivated;
bridgeTfDone <= cActivated when fsm = sDone else cInactivated;
--! Clock process to assign registers.
theClkPro : process(iRst, iClk)
begin
if iRst = cActivated then
fsm <= sIdle;
oHostBridgeAddress <= (others => cInactivated);
oHostBridgeByteenable <= (others => cInactivated);
oHostBridgeRead <= cInactivated;
oHostBridgeWrite <= cInactivated;
oHostBridgeWritedata <= (others => cInactivated);
elsif rising_edge(iClk) then
fsm <= fsm_next;
if iHostBridgeWaitrequest = cInactivated then
oHostBridgeRead <= cInactivated;
oHostBridgeWrite <= cInactivated;
bridgeReaddata <= iHostBridgeReaddata;
end if;
if bridgeAddrValid = cActivated then
oHostBridgeAddress <= hostBridgeAddress_dword & "00";
oHostBridgeByteenable <= iHostByteenable;
oHostBridgeRead <= iHostRead;
oHostBridgeWrite <= iHostWrite;
oHostBridgeWritedata <= iHostWritedata;
end if;
end if;
end process;
--! The synchronizer which protects us from crazy effects!
theSynchronizer : entity work.synchronizer
generic map (
gStages => 2,
gInit => cInactivated
)
port map (
iArst => iRst,
iClk => iClk,
iAsync => iIrqExtSync,
oSync => extSync_sync
);
--! The Edge Detector for external sync
theExtSyncEdgeDet : entity work.edgedetector
port map (
iArst => iRst,
iClk => iClk,
iEnable => cActivated,
iData => extSync_sync,
oRising => extSync_rising,
oFalling => extSync_falling,
oAny => extSync_any
);
--! The Dynamic Bridge
theDynamicBridge : entity work.dynamicBridge
generic map (
gAddressSpaceCount => cBaseAddressArrayCount-1,
gUseMemBlock => gBridgeUseMemBlock,
gBaseAddressArray => cBaseAddressArray
)
port map (
iClk => iClk,
iRst => iRst,
iBridgeAddress => iHostAddress,
iBridgeRequest => bridgeRequest,
oBridgeAddress => hostBridgeAddress_dword,
oBridgeSelectAny => open,
oBridgeSelect => open,
oBridgeValid => bridgeAddrValid,
iBaseSetWrite => baseSetWrite,
iBaseSetRead => baseSetRead,
iBaseSetByteenable => baseSetByteenable,
iBaseSetAddress => baseSetAddress,
iBaseSetData => baseSetWritedata,
oBaseSetData => baseSetReaddata,
oBaseSetAck => basesetAck
);
--! The Irq Generator
theIrqGen : entity work.irqGen
generic map (
gIrqSourceCount => cIrqSourceCount
)
port map (
iClk => iClk,
iRst => iRst,
iSync => syncSig,
iIrqSource => irqSourceSet,
oIrq => oIrq,
iIrqMasterEnable => irqMasterEnable,
iIrqSourceEnable => irqSourceEnable,
iIrqAcknowledge => irqAcknowledge,
oIrgPending => irqSourcePending
);
--! The Status-/Control Registers
theStCtrlReg : entity work.statusControlReg
generic map (
gMagic => cMagic,
gVersionMajor => gVersionMajor,
gVersionMinor => gVersionMinor,
gVersionRevision => gVersionRevision,
gVersionCount => gVersionCount,
gHostBaseSet => cBaseAddressHostCount,
gPcpBaseSet => cBaseAddressPcpCount,
gIrqSourceCount => cIrqSourceCount
)
port map (
iClk => iClk,
iRst => iRst,
iHostRead => statCtrlRead,
iHostWrite => statCtrlWrite,
iHostByteenable => iHostByteenable,
iHostAddress => iHostAddress(10 downto 2),
oHostReaddata => statCtrlReaddata,
iHostWritedata => iHostWritedata,
oHostWaitrequest => statCtrlWaitrequest,
iPcpRead => iPcpRead,
iPcpWrite => iPcpWrite,
iPcpByteenable => iPcpByteenable,
iPcpAddress => iPcpAddress,
oPcpReaddata => oPcpReaddata,
iPcpWritedata => iPcpWritedata,
oPcpWaitrequest => oPcpWaitrequest,
oBaseSetWrite => baseSetWrite,
oBaseSetRead => baseSetRead,
oBaseSetByteenable => baseSetByteenable,
oBaseSetAddress => baseSetAddress,
iBaseSetData => baseSetReaddata,
oBaseSetData => baseSetWritedata,
iBaseSetAck => basesetAck,
oIrqMasterEnable => irqMasterEnable,
oIrqSourceEnable => irqSourceEnable,
oIrqAcknowledge => irqAcknowledge,
oIrqSet => irqSourceSet,
iIrqPending => irqSourcePending,
oExtSyncEnable => extSyncEnable,
oExtSyncConfig => extSyncConfig,
iNodeId => iNodeId,
oPLed => statCtrlLed,
oBridgeEnable => bridgeEnable
);
oPlkLedStatus <= statCtrlLed(0);
oPlkLedError <= statCtrlLed(1);
end Rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tuberom_pdp11 is
port (
CLK : in std_logic;
ADDR : in std_logic_vector(9 downto 0);
DATA : out std_logic_vector(15 downto 0)
);
end;
architecture RTL of tuberom_pdp11 is
signal rom_addr : std_logic_vector(11 downto 0);
begin
p_addr : process(ADDR)
begin
rom_addr <= (others => '0');
rom_addr(9 downto 0) <= ADDR;
end process;
p_rom : process
begin
wait until rising_edge(CLK);
DATA <= (others => '0');
case rom_addr is
when x"000" => DATA <= x"0077";
when x"001" => DATA <= x"0018";
when x"002" => DATA <= x"500D";
when x"003" => DATA <= x"5044";
when x"004" => DATA <= x"3131";
when x"005" => DATA <= x"5420";
when x"006" => DATA <= x"4255";
when x"007" => DATA <= x"2045";
when x"008" => DATA <= x"3436";
when x"009" => DATA <= x"204B";
when x"00a" => DATA <= x"2E30";
when x"00b" => DATA <= x"3732";
when x"00c" => DATA <= x"0D61";
when x"00d" => DATA <= x"000D";
when x"00e" => DATA <= x"15C6";
when x"00f" => DATA <= x"F5D8";
when x"010" => DATA <= x"17E6";
when x"011" => DATA <= x"F5FC";
when x"012" => DATA <= x"09F7";
when x"013" => DATA <= x"0572";
when x"014" => DATA <= x"159F";
when x"015" => DATA <= x"F5F8";
when x"016" => DATA <= x"15C1";
when x"017" => DATA <= x"F804";
when x"018" => DATA <= x"09F7";
when x"019" => DATA <= x"0084";
when x"01a" => DATA <= x"09F7";
when x"01b" => DATA <= x"048E";
when x"01c" => DATA <= x"00A1";
when x"01d" => DATA <= x"09F7";
when x"01e" => DATA <= x"0124";
when x"01f" => DATA <= x"17C6";
when x"020" => DATA <= x"F5F6";
when x"021" => DATA <= x"15DF";
when x"022" => DATA <= x"F83E";
when x"023" => DATA <= x"F5FC";
when x"024" => DATA <= x"15C1";
when x"025" => DATA <= x"F860";
when x"026" => DATA <= x"09F7";
when x"027" => DATA <= x"0068";
when x"028" => DATA <= x"09F7";
when x"029" => DATA <= x"0280";
when x"02a" => DATA <= x"870C";
when x"02b" => DATA <= x"17C0";
when x"02c" => DATA <= x"F868";
when x"02d" => DATA <= x"09F7";
when x"02e" => DATA <= x"0076";
when x"02f" => DATA <= x"01F4";
when x"030" => DATA <= x"4450";
when x"031" => DATA <= x"3150";
when x"032" => DATA <= x"3E31";
when x"033" => DATA <= x"002A";
when x"034" => DATA <= x"F500";
when x"035" => DATA <= x"20B8";
when x"036" => DATA <= x"00FF";
when x"037" => DATA <= x"15C0";
when x"038" => DATA <= x"007E";
when x"039" => DATA <= x"09F7";
when x"03a" => DATA <= x"01E0";
when x"03b" => DATA <= x"880F";
when x"03c" => DATA <= x"4511";
when x"03d" => DATA <= x"6373";
when x"03e" => DATA <= x"7061";
when x"03f" => DATA <= x"0065";
when x"040" => DATA <= x"17C6";
when x"041" => DATA <= x"F5F6";
when x"042" => DATA <= x"1001";
when x"043" => DATA <= x"0A81";
when x"044" => DATA <= x"09F7";
when x"045" => DATA <= x"042E";
when x"046" => DATA <= x"09F7";
when x"047" => DATA <= x"0028";
when x"048" => DATA <= x"09F7";
when x"049" => DATA <= x"0426";
when x"04a" => DATA <= x"01D4";
when x"04b" => DATA <= x"6000";
when x"04c" => DATA <= x"903F";
when x"04d" => DATA <= x"FD42";
when x"04e" => DATA <= x"0087";
when x"04f" => DATA <= x"E5C1";
when x"050" => DATA <= x"0002";
when x"051" => DATA <= x"9440";
when x"052" => DATA <= x"45C0";
when x"053" => DATA <= x"FF00";
when x"054" => DATA <= x"9241";
when x"055" => DATA <= x"45C1";
when x"056" => DATA <= x"FF00";
when x"057" => DATA <= x"00C1";
when x"058" => DATA <= x"5001";
when x"059" => DATA <= x"0087";
when x"05a" => DATA <= x"09F7";
when x"05b" => DATA <= x"03FC";
when x"05c" => DATA <= x"9440";
when x"05d" => DATA <= x"02FC";
when x"05e" => DATA <= x"0087";
when x"05f" => DATA <= x"A417";
when x"060" => DATA <= x"0021";
when x"061" => DATA <= x"86FD";
when x"062" => DATA <= x"0AC0";
when x"063" => DATA <= x"A417";
when x"064" => DATA <= x"0020";
when x"065" => DATA <= x"03FD";
when x"066" => DATA <= x"0AC0";
when x"067" => DATA <= x"0087";
when x"068" => DATA <= x"7572";
when x"069" => DATA <= x"006E";
when x"06a" => DATA <= x"1066";
when x"06b" => DATA <= x"10A6";
when x"06c" => DATA <= x"10E6";
when x"06d" => DATA <= x"1126";
when x"06e" => DATA <= x"1166";
when x"06f" => DATA <= x"1185";
when x"070" => DATA <= x"2157";
when x"071" => DATA <= x"F500";
when x"072" => DATA <= x"8602";
when x"073" => DATA <= x"15C6";
when x"074" => DATA <= x"F5D8";
when x"075" => DATA <= x"1166";
when x"076" => DATA <= x"17E6";
when x"077" => DATA <= x"F5F6";
when x"078" => DATA <= x"17E6";
when x"079" => DATA <= x"F5FC";
when x"07a" => DATA <= x"09F7";
when x"07b" => DATA <= x"0018";
when x"07c" => DATA <= x"159F";
when x"07d" => DATA <= x"F5FC";
when x"07e" => DATA <= x"159F";
when x"07f" => DATA <= x"F5F6";
when x"080" => DATA <= x"1386";
when x"081" => DATA <= x"1585";
when x"082" => DATA <= x"1584";
when x"083" => DATA <= x"1583";
when x"084" => DATA <= x"1582";
when x"085" => DATA <= x"1581";
when x"086" => DATA <= x"0A00";
when x"087" => DATA <= x"0087";
when x"088" => DATA <= x"09F7";
when x"089" => DATA <= x"FFB2";
when x"08a" => DATA <= x"A417";
when x"08b" => DATA <= x"002A";
when x"08c" => DATA <= x"03FB";
when x"08d" => DATA <= x"0AC0";
when x"08e" => DATA <= x"1001";
when x"08f" => DATA <= x"1004";
when x"090" => DATA <= x"A417";
when x"091" => DATA <= x"002F";
when x"092" => DATA <= x"030F";
when x"093" => DATA <= x"0AC0";
when x"094" => DATA <= x"15C2";
when x"095" => DATA <= x"F8D0";
when x"096" => DATA <= x"9403";
when x"097" => DATA <= x"55C3";
when x"098" => DATA <= x"0020";
when x"099" => DATA <= x"A483";
when x"09a" => DATA <= x"03FB";
when x"09b" => DATA <= x"0AC0";
when x"09c" => DATA <= x"0AC2";
when x"09d" => DATA <= x"A217";
when x"09e" => DATA <= x"0021";
when x"09f" => DATA <= x"8605";
when x"0a0" => DATA <= x"8BCA";
when x"0a1" => DATA <= x"0203";
when x"0a2" => DATA <= x"09F7";
when x"0a3" => DATA <= x"FF7E";
when x"0a4" => DATA <= x"1004";
when x"0a5" => DATA <= x"1100";
when x"0a6" => DATA <= x"09F7";
when x"0a7" => DATA <= x"FF6E";
when x"0a8" => DATA <= x"1037";
when x"0a9" => DATA <= x"FC9C";
when x"0aa" => DATA <= x"15C0";
when x"0ab" => DATA <= x"0002";
when x"0ac" => DATA <= x"09F7";
when x"0ad" => DATA <= x"0518";
when x"0ae" => DATA <= x"09F7";
when x"0af" => DATA <= x"04E4";
when x"0b0" => DATA <= x"00B1";
when x"0b1" => DATA <= x"09F7";
when x"0b2" => DATA <= x"032A";
when x"0b3" => DATA <= x"80D3";
when x"0b4" => DATA <= x"17C1";
when x"0b5" => DATA <= x"F5F8";
when x"0b6" => DATA <= x"15C5";
when x"0b7" => DATA <= x"0000";
when x"0b8" => DATA <= x"0C45";
when x"0b9" => DATA <= x"1066";
when x"0ba" => DATA <= x"9C42";
when x"0bb" => DATA <= x"0007";
when x"0bc" => DATA <= x"45C2";
when x"0bd" => DATA <= x"FF00";
when x"0be" => DATA <= x"6081";
when x"0bf" => DATA <= x"8BD1";
when x"0c0" => DATA <= x"0226";
when x"0c1" => DATA <= x"A457";
when x"0c2" => DATA <= x"0028";
when x"0c3" => DATA <= x"0223";
when x"0c4" => DATA <= x"A457";
when x"0c5" => DATA <= x"0043";
when x"0c6" => DATA <= x"0220";
when x"0c7" => DATA <= x"A457";
when x"0c8" => DATA <= x"0029";
when x"0c9" => DATA <= x"021D";
when x"0ca" => DATA <= x"1381";
when x"0cb" => DATA <= x"9C42";
when x"0cc" => DATA <= x"0006";
when x"0cd" => DATA <= x"45C2";
when x"0ce" => DATA <= x"FFB0";
when x"0cf" => DATA <= x"2097";
when x"0d0" => DATA <= x"0047";
when x"0d1" => DATA <= x"0246";
when x"0d2" => DATA <= x"9C42";
when x"0d3" => DATA <= x"0006";
when x"0d4" => DATA <= x"35C2";
when x"0d5" => DATA <= x"0020";
when x"0d6" => DATA <= x"030E";
when x"0d7" => DATA <= x"9C42";
when x"0d8" => DATA <= x"0007";
when x"0d9" => DATA <= x"45C2";
when x"0da" => DATA <= x"FF00";
when x"0db" => DATA <= x"6081";
when x"0dc" => DATA <= x"0A81";
when x"0dd" => DATA <= x"8BD1";
when x"0de" => DATA <= x"02FE";
when x"0df" => DATA <= x"65C1";
when x"0e0" => DATA <= x"0004";
when x"0e1" => DATA <= x"09F7";
when x"0e2" => DATA <= x"FEDC";
when x"0e3" => DATA <= x"6581";
when x"0e4" => DATA <= x"1066";
when x"0e5" => DATA <= x"55C5";
when x"0e6" => DATA <= x"0002";
when x"0e7" => DATA <= x"1581";
when x"0e8" => DATA <= x"45C1";
when x"0e9" => DATA <= x"0001";
when x"0ea" => DATA <= x"1242";
when x"0eb" => DATA <= x"2097";
when x"0ec" => DATA <= x"0105";
when x"0ed" => DATA <= x"871A";
when x"0ee" => DATA <= x"2097";
when x"0ef" => DATA <= x"0109";
when x"0f0" => DATA <= x"8617";
when x"0f1" => DATA <= x"0BD1";
when x"0f2" => DATA <= x"1443";
when x"0f3" => DATA <= x"1444";
when x"0f4" => DATA <= x"6103";
when x"0f5" => DATA <= x"1444";
when x"0f6" => DATA <= x"17C2";
when x"0f7" => DATA <= x"F5F4";
when x"0f8" => DATA <= x"65C1";
when x"0f9" => DATA <= x"0008";
when x"0fa" => DATA <= x"0C83";
when x"0fb" => DATA <= x"1452";
when x"0fc" => DATA <= x"0AC3";
when x"0fd" => DATA <= x"02FD";
when x"0fe" => DATA <= x"0C84";
when x"0ff" => DATA <= x"0303";
when x"100" => DATA <= x"0A12";
when x"101" => DATA <= x"0AC4";
when x"102" => DATA <= x"02FD";
when x"103" => DATA <= x"17C1";
when x"104" => DATA <= x"F5F4";
when x"105" => DATA <= x"0A26";
when x"106" => DATA <= x"0A26";
when x"107" => DATA <= x"0A26";
when x"108" => DATA <= x"1066";
when x"109" => DATA <= x"1140";
when x"10a" => DATA <= x"15C5";
when x"10b" => DATA <= x"0BBC";
when x"10c" => DATA <= x"0A04";
when x"10d" => DATA <= x"0A03";
when x"10e" => DATA <= x"0A02";
when x"10f" => DATA <= x"17C1";
when x"110" => DATA <= x"F5F0";
when x"111" => DATA <= x"139F";
when x"112" => DATA <= x"F5FA";
when x"113" => DATA <= x"8002";
when x"114" => DATA <= x"139F";
when x"115" => DATA <= x"F5F6";
when x"116" => DATA <= x"0C80";
when x"117" => DATA <= x"0087";
when x"118" => DATA <= x"0C85";
when x"119" => DATA <= x"860B";
when x"11a" => DATA <= x"09F7";
when x"11b" => DATA <= x"0396";
when x"11c" => DATA <= x"880F";
when x"11d" => DATA <= x"4EF9";
when x"11e" => DATA <= x"746F";
when x"11f" => DATA <= x"5020";
when x"120" => DATA <= x"5044";
when x"121" => DATA <= x"3131";
when x"122" => DATA <= x"6320";
when x"123" => DATA <= x"646F";
when x"124" => DATA <= x"0065";
when x"125" => DATA <= x"0077";
when x"126" => DATA <= x"FDF0";
when x"127" => DATA <= x"15F7";
when x"128" => DATA <= x"F804";
when x"129" => DATA <= x"FB9C";
when x"12a" => DATA <= x"0185";
when x"12b" => DATA <= x"1026";
when x"12c" => DATA <= x"8BC0";
when x"12d" => DATA <= x"810B";
when x"12e" => DATA <= x"15C0";
when x"12f" => DATA <= x"0004";
when x"130" => DATA <= x"09F7";
when x"131" => DATA <= x"040A";
when x"132" => DATA <= x"1380";
when x"133" => DATA <= x"09F7";
when x"134" => DATA <= x"040A";
when x"135" => DATA <= x"09F7";
when x"136" => DATA <= x"0222";
when x"137" => DATA <= x"1001";
when x"138" => DATA <= x"012F";
when x"139" => DATA <= x"2017";
when x"13a" => DATA <= x"0082";
when x"13b" => DATA <= x"8703";
when x"13c" => DATA <= x"2017";
when x"13d" => DATA <= x"0085";
when x"13e" => DATA <= x"8722";
when x"13f" => DATA <= x"15C0";
when x"140" => DATA <= x"0006";
when x"141" => DATA <= x"09F7";
when x"142" => DATA <= x"03E8";
when x"143" => DATA <= x"1080";
when x"144" => DATA <= x"09F7";
when x"145" => DATA <= x"03E8";
when x"146" => DATA <= x"1580";
when x"147" => DATA <= x"09F7";
when x"148" => DATA <= x"03E2";
when x"149" => DATA <= x"2017";
when x"14a" => DATA <= x"009D";
when x"14b" => DATA <= x"031D";
when x"14c" => DATA <= x"2017";
when x"14d" => DATA <= x"008E";
when x"14e" => DATA <= x"03D8";
when x"14f" => DATA <= x"1026";
when x"150" => DATA <= x"09F7";
when x"151" => DATA <= x"01EC";
when x"152" => DATA <= x"65C0";
when x"153" => DATA <= x"FF80";
when x"154" => DATA <= x"09F7";
when x"155" => DATA <= x"01E4";
when x"156" => DATA <= x"45C0";
when x"157" => DATA <= x"FF00";
when x"158" => DATA <= x"1002";
when x"159" => DATA <= x"00C0";
when x"15a" => DATA <= x"1001";
when x"15b" => DATA <= x"09F7";
when x"15c" => DATA <= x"01D6";
when x"15d" => DATA <= x"45C0";
when x"15e" => DATA <= x"FF00";
when x"15f" => DATA <= x"5001";
when x"160" => DATA <= x"0107";
when x"161" => DATA <= x"0CC0";
when x"162" => DATA <= x"1C01";
when x"163" => DATA <= x"F4EE";
when x"164" => DATA <= x"1042";
when x"165" => DATA <= x"00C2";
when x"166" => DATA <= x"45C2";
when x"167" => DATA <= x"FF00";
when x"168" => DATA <= x"1580";
when x"169" => DATA <= x"0087";
when x"16a" => DATA <= x"0BC0";
when x"16b" => DATA <= x"034D";
when x"16c" => DATA <= x"10E6";
when x"16d" => DATA <= x"10A6";
when x"16e" => DATA <= x"1026";
when x"16f" => DATA <= x"15C0";
when x"170" => DATA <= x"0008";
when x"171" => DATA <= x"09F7";
when x"172" => DATA <= x"038E";
when x"173" => DATA <= x"1380";
when x"174" => DATA <= x"09F7";
when x"175" => DATA <= x"0388";
when x"176" => DATA <= x"8BC0";
when x"177" => DATA <= x"8003";
when x"178" => DATA <= x"9442";
when x"179" => DATA <= x"9243";
when x"17a" => DATA <= x"010C";
when x"17b" => DATA <= x"15C2";
when x"17c" => DATA <= x"0010";
when x"17d" => DATA <= x"15C3";
when x"17e" => DATA <= x"0010";
when x"17f" => DATA <= x"2017";
when x"180" => DATA <= x"0015";
when x"181" => DATA <= x"8605";
when x"182" => DATA <= x"6000";
when x"183" => DATA <= x"65C0";
when x"184" => DATA <= x"FB48";
when x"185" => DATA <= x"9402";
when x"186" => DATA <= x"9203";
when x"187" => DATA <= x"1080";
when x"188" => DATA <= x"09F7";
when x"189" => DATA <= x"0360";
when x"18a" => DATA <= x"6081";
when x"18b" => DATA <= x"0AC2";
when x"18c" => DATA <= x"2097";
when x"18d" => DATA <= x"0080";
when x"18e" => DATA <= x"8605";
when x"18f" => DATA <= x"9840";
when x"190" => DATA <= x"09F7";
when x"191" => DATA <= x"0350";
when x"192" => DATA <= x"0AC2";
when x"193" => DATA <= x"80FB";
when x"194" => DATA <= x"10C0";
when x"195" => DATA <= x"09F7";
when x"196" => DATA <= x"0346";
when x"197" => DATA <= x"60C1";
when x"198" => DATA <= x"0AC3";
when x"199" => DATA <= x"20D7";
when x"19a" => DATA <= x"0080";
when x"19b" => DATA <= x"8605";
when x"19c" => DATA <= x"09F7";
when x"19d" => DATA <= x"0154";
when x"19e" => DATA <= x"9021";
when x"19f" => DATA <= x"0AC3";
when x"1a0" => DATA <= x"80FB";
when x"1a1" => DATA <= x"1580";
when x"1a2" => DATA <= x"1582";
when x"1a3" => DATA <= x"1583";
when x"1a4" => DATA <= x"0087";
when x"1a5" => DATA <= x"0500";
when x"1a6" => DATA <= x"0005";
when x"1a7" => DATA <= x"0500";
when x"1a8" => DATA <= x"0005";
when x"1a9" => DATA <= x"0504";
when x"1aa" => DATA <= x"0005";
when x"1ab" => DATA <= x"0008";
when x"1ac" => DATA <= x"000E";
when x"1ad" => DATA <= x"0504";
when x"1ae" => DATA <= x"0901";
when x"1af" => DATA <= x"0501";
when x"1b0" => DATA <= x"0005";
when x"1b1" => DATA <= x"0800";
when x"1b2" => DATA <= x"1910";
when x"1b3" => DATA <= x"0020";
when x"1b4" => DATA <= x"0110";
when x"1b5" => DATA <= x"0D0D";
when x"1b6" => DATA <= x"8000";
when x"1b7" => DATA <= x"0808";
when x"1b8" => DATA <= x"8080";
when x"1b9" => DATA <= x"15C0";
when x"1ba" => DATA <= x"000A";
when x"1bb" => DATA <= x"09F7";
when x"1bc" => DATA <= x"02FA";
when x"1bd" => DATA <= x"65C1";
when x"1be" => DATA <= x"0002";
when x"1bf" => DATA <= x"15C2";
when x"1c0" => DATA <= x"0003";
when x"1c1" => DATA <= x"09F7";
when x"1c2" => DATA <= x"02CC";
when x"1c3" => DATA <= x"15C0";
when x"1c4" => DATA <= x"0007";
when x"1c5" => DATA <= x"09F7";
when x"1c6" => DATA <= x"02E6";
when x"1c7" => DATA <= x"0A00";
when x"1c8" => DATA <= x"09F7";
when x"1c9" => DATA <= x"02E0";
when x"1ca" => DATA <= x"09F7";
when x"1cb" => DATA <= x"00F8";
when x"1cc" => DATA <= x"65C0";
when x"1cd" => DATA <= x"FF80";
when x"1ce" => DATA <= x"870B";
when x"1cf" => DATA <= x"09F7";
when x"1d0" => DATA <= x"FCFC";
when x"1d1" => DATA <= x"0A02";
when x"1d2" => DATA <= x"09F7";
when x"1d3" => DATA <= x"00E8";
when x"1d4" => DATA <= x"9011";
when x"1d5" => DATA <= x"0A82";
when x"1d6" => DATA <= x"2017";
when x"1d7" => DATA <= x"000D";
when x"1d8" => DATA <= x"02F9";
when x"1d9" => DATA <= x"0AC2";
when x"1da" => DATA <= x"0087";
when x"1db" => DATA <= x"10A6";
when x"1dc" => DATA <= x"1066";
when x"1dd" => DATA <= x"1026";
when x"1de" => DATA <= x"15C0";
when x"1df" => DATA <= x"000C";
when x"1e0" => DATA <= x"09F7";
when x"1e1" => DATA <= x"02AA";
when x"1e2" => DATA <= x"1081";
when x"1e3" => DATA <= x"15C2";
when x"1e4" => DATA <= x"0004";
when x"1e5" => DATA <= x"09F7";
when x"1e6" => DATA <= x"0284";
when x"1e7" => DATA <= x"1580";
when x"1e8" => DATA <= x"09F7";
when x"1e9" => DATA <= x"02A0";
when x"1ea" => DATA <= x"09F7";
when x"1eb" => DATA <= x"00B8";
when x"1ec" => DATA <= x"1026";
when x"1ed" => DATA <= x"15C2";
when x"1ee" => DATA <= x"0004";
when x"1ef" => DATA <= x"0133";
when x"1f0" => DATA <= x"1026";
when x"1f1" => DATA <= x"15C0";
when x"1f2" => DATA <= x"0012";
when x"1f3" => DATA <= x"09F7";
when x"1f4" => DATA <= x"028A";
when x"1f5" => DATA <= x"1580";
when x"1f6" => DATA <= x"09F7";
when x"1f7" => DATA <= x"0284";
when x"1f8" => DATA <= x"0BC0";
when x"1f9" => DATA <= x"0206";
when x"1fa" => DATA <= x"09F7";
when x"1fb" => DATA <= x"027A";
when x"1fc" => DATA <= x"09F7";
when x"1fd" => DATA <= x"0094";
when x"1fe" => DATA <= x"0A00";
when x"1ff" => DATA <= x"0087";
when x"200" => DATA <= x"1066";
when x"201" => DATA <= x"09F7";
when x"202" => DATA <= x"023E";
when x"203" => DATA <= x"09F7";
when x"204" => DATA <= x"0086";
when x"205" => DATA <= x"1581";
when x"206" => DATA <= x"0087";
when x"207" => DATA <= x"10A6";
when x"208" => DATA <= x"1066";
when x"209" => DATA <= x"1026";
when x"20a" => DATA <= x"15C0";
when x"20b" => DATA <= x"0014";
when x"20c" => DATA <= x"09F7";
when x"20d" => DATA <= x"0258";
when x"20e" => DATA <= x"65C1";
when x"20f" => DATA <= x"0002";
when x"210" => DATA <= x"15C2";
when x"211" => DATA <= x"0010";
when x"212" => DATA <= x"09F7";
when x"213" => DATA <= x"022A";
when x"214" => DATA <= x"09F7";
when x"215" => DATA <= x"FC72";
when x"216" => DATA <= x"09F7";
when x"217" => DATA <= x"0214";
when x"218" => DATA <= x"1580";
when x"219" => DATA <= x"09F7";
when x"21a" => DATA <= x"023E";
when x"21b" => DATA <= x"09F7";
when x"21c" => DATA <= x"0056";
when x"21d" => DATA <= x"1381";
when x"21e" => DATA <= x"1026";
when x"21f" => DATA <= x"65C1";
when x"220" => DATA <= x"0002";
when x"221" => DATA <= x"15C2";
when x"222" => DATA <= x"0010";
when x"223" => DATA <= x"09F7";
when x"224" => DATA <= x"0216";
when x"225" => DATA <= x"1580";
when x"226" => DATA <= x"1581";
when x"227" => DATA <= x"1582";
when x"228" => DATA <= x"0087";
when x"229" => DATA <= x"10A6";
when x"22a" => DATA <= x"1026";
when x"22b" => DATA <= x"15C0";
when x"22c" => DATA <= x"0016";
when x"22d" => DATA <= x"09F7";
when x"22e" => DATA <= x"0216";
when x"22f" => DATA <= x"15C2";
when x"230" => DATA <= x"000D";
when x"231" => DATA <= x"09F7";
when x"232" => DATA <= x"01EC";
when x"233" => DATA <= x"1580";
when x"234" => DATA <= x"09F7";
when x"235" => DATA <= x"0208";
when x"236" => DATA <= x"15C2";
when x"237" => DATA <= x"000D";
when x"238" => DATA <= x"09F7";
when x"239" => DATA <= x"01EC";
when x"23a" => DATA <= x"1582";
when x"23b" => DATA <= x"0108";
when x"23c" => DATA <= x"15C0";
when x"23d" => DATA <= x"000E";
when x"23e" => DATA <= x"09F7";
when x"23f" => DATA <= x"01EE";
when x"240" => DATA <= x"0103";
when x"241" => DATA <= x"0A00";
when x"242" => DATA <= x"09F7";
when x"243" => DATA <= x"01EC";
when x"244" => DATA <= x"09F7";
when x"245" => DATA <= x"0004";
when x"246" => DATA <= x"65C0";
when x"247" => DATA <= x"FF80";
when x"248" => DATA <= x"97C0";
when x"249" => DATA <= x"FFF4";
when x"24a" => DATA <= x"80FD";
when x"24b" => DATA <= x"97C0";
when x"24c" => DATA <= x"FFF6";
when x"24d" => DATA <= x"0087";
when x"24e" => DATA <= x"1026";
when x"24f" => DATA <= x"15C0";
when x"250" => DATA <= x"0010";
when x"251" => DATA <= x"09F7";
when x"252" => DATA <= x"01C8";
when x"253" => DATA <= x"1380";
when x"254" => DATA <= x"09F7";
when x"255" => DATA <= x"01C8";
when x"256" => DATA <= x"09F7";
when x"257" => DATA <= x"FFE0";
when x"258" => DATA <= x"1580";
when x"259" => DATA <= x"0087";
when x"25a" => DATA <= x"25C0";
when x"25b" => DATA <= x"000D";
when x"25c" => DATA <= x"0206";
when x"25d" => DATA <= x"15C0";
when x"25e" => DATA <= x"000A";
when x"25f" => DATA <= x"09F7";
when x"260" => DATA <= x"0004";
when x"261" => DATA <= x"15C0";
when x"262" => DATA <= x"000D";
when x"263" => DATA <= x"35DF";
when x"264" => DATA <= x"0040";
when x"265" => DATA <= x"FFF0";
when x"266" => DATA <= x"03FC";
when x"267" => DATA <= x"901F";
when x"268" => DATA <= x"FFF2";
when x"269" => DATA <= x"0087";
when x"26a" => DATA <= x"880F";
when x"26b" => DATA <= x"42FF";
when x"26c" => DATA <= x"6461";
when x"26d" => DATA <= x"0000";
when x"26e" => DATA <= x"45F6";
when x"26f" => DATA <= x"FFF0";
when x"270" => DATA <= x"0002";
when x"271" => DATA <= x"17E6";
when x"272" => DATA <= x"F5E0";
when x"273" => DATA <= x"17E6";
when x"274" => DATA <= x"F5EC";
when x"275" => DATA <= x"119F";
when x"276" => DATA <= x"F5EC";
when x"277" => DATA <= x"15DF";
when x"278" => DATA <= x"FD12";
when x"279" => DATA <= x"F5E0";
when x"27a" => DATA <= x"0BE6";
when x"27b" => DATA <= x"1026";
when x"27c" => DATA <= x"1D80";
when x"27d" => DATA <= x"0008";
when x"27e" => DATA <= x"1800";
when x"27f" => DATA <= x"45C0";
when x"280" => DATA <= x"FF00";
when x"281" => DATA <= x"6000";
when x"282" => DATA <= x"67C0";
when x"283" => DATA <= x"F5EE";
when x"284" => DATA <= x"1236";
when x"285" => DATA <= x"0002";
when x"286" => DATA <= x"1580";
when x"287" => DATA <= x"09DE";
when x"288" => DATA <= x"8405";
when x"289" => DATA <= x"17C6";
when x"28a" => DATA <= x"F5EC";
when x"28b" => DATA <= x"55F6";
when x"28c" => DATA <= x"0002";
when x"28d" => DATA <= x"0006";
when x"28e" => DATA <= x"8603";
when x"28f" => DATA <= x"55F6";
when x"290" => DATA <= x"0001";
when x"291" => DATA <= x"0006";
when x"292" => DATA <= x"159F";
when x"293" => DATA <= x"F5EC";
when x"294" => DATA <= x"159F";
when x"295" => DATA <= x"F5E0";
when x"296" => DATA <= x"0002";
when x"297" => DATA <= x"1D80";
when x"298" => DATA <= x"0006";
when x"299" => DATA <= x"1DB6";
when x"29a" => DATA <= x"0004";
when x"29b" => DATA <= x"0006";
when x"29c" => DATA <= x"0087";
when x"29d" => DATA <= x"0BD6";
when x"29e" => DATA <= x"159F";
when x"29f" => DATA <= x"F5EC";
when x"2a0" => DATA <= x"159F";
when x"2a1" => DATA <= x"F5E0";
when x"2a2" => DATA <= x"1026";
when x"2a3" => DATA <= x"810B";
when x"2a4" => DATA <= x"2017";
when x"2a5" => DATA <= x"0100";
when x"2a6" => DATA <= x"861B";
when x"2a7" => DATA <= x"6000";
when x"2a8" => DATA <= x"67C0";
when x"2a9" => DATA <= x"F5EE";
when x"2aa" => DATA <= x"1226";
when x"2ab" => DATA <= x"0BC1";
when x"2ac" => DATA <= x"0314";
when x"2ad" => DATA <= x"1048";
when x"2ae" => DATA <= x"0112";
when x"2af" => DATA <= x"0A40";
when x"2b0" => DATA <= x"2017";
when x"2b1" => DATA <= x"000A";
when x"2b2" => DATA <= x"860F";
when x"2b3" => DATA <= x"6000";
when x"2b4" => DATA <= x"6000";
when x"2b5" => DATA <= x"65C0";
when x"2b6" => DATA <= x"F5D8";
when x"2b7" => DATA <= x"1226";
when x"2b8" => DATA <= x"0BC1";
when x"2b9" => DATA <= x"0301";
when x"2ba" => DATA <= x"1048";
when x"2bb" => DATA <= x"0BD0";
when x"2bc" => DATA <= x"1226";
when x"2bd" => DATA <= x"0BC2";
when x"2be" => DATA <= x"0301";
when x"2bf" => DATA <= x"1088";
when x"2c0" => DATA <= x"1582";
when x"2c1" => DATA <= x"1581";
when x"2c2" => DATA <= x"1580";
when x"2c3" => DATA <= x"0002";
when x"2c4" => DATA <= x"0BC0";
when x"2c5" => DATA <= x"0304";
when x"2c6" => DATA <= x"2017";
when x"2c7" => DATA <= x"0003";
when x"2c8" => DATA <= x"871D";
when x"2c9" => DATA <= x"0303";
when x"2ca" => DATA <= x"0087";
when x"2cb" => DATA <= x"007F";
when x"2cc" => DATA <= x"F83E";
when x"2cd" => DATA <= x"0A00";
when x"2ce" => DATA <= x"15D0";
when x"2cf" => DATA <= x"FFC0";
when x"2d0" => DATA <= x"0A10";
when x"2d1" => DATA <= x"2017";
when x"2d2" => DATA <= x"0100";
when x"2d3" => DATA <= x"02FA";
when x"2d4" => DATA <= x"15DF";
when x"2d5" => DATA <= x"FCD4";
when x"2d6" => DATA <= x"001C";
when x"2d7" => DATA <= x"15DF";
when x"2d8" => DATA <= x"FCDC";
when x"2d9" => DATA <= x"0018";
when x"2da" => DATA <= x"15DF";
when x"2db" => DATA <= x"FFBC";
when x"2dc" => DATA <= x"0080";
when x"2dd" => DATA <= x"15DF";
when x"2de" => DATA <= x"00E0";
when x"2df" => DATA <= x"0082";
when x"2e0" => DATA <= x"15DF";
when x"2e1" => DATA <= x"FE9A";
when x"2e2" => DATA <= x"0084";
when x"2e3" => DATA <= x"15DF";
when x"2e4" => DATA <= x"00C0";
when x"2e5" => DATA <= x"0086";
when x"2e6" => DATA <= x"0C00";
when x"2e7" => DATA <= x"17DF";
when x"2e8" => DATA <= x"F5FA";
when x"2e9" => DATA <= x"F5FC";
when x"2ea" => DATA <= x"15C0";
when x"2eb" => DATA <= x"000C";
when x"2ec" => DATA <= x"15C1";
when x"2ed" => DATA <= x"FDFA";
when x"2ee" => DATA <= x"15C2";
when x"2ef" => DATA <= x"F5D8";
when x"2f0" => DATA <= x"8702";
when x"2f1" => DATA <= x"65C0";
when x"2f2" => DATA <= x"0018";
when x"2f3" => DATA <= x"1452";
when x"2f4" => DATA <= x"0AC0";
when x"2f5" => DATA <= x"02FD";
when x"2f6" => DATA <= x"8705";
when x"2f7" => DATA <= x"15C0";
when x"2f8" => DATA <= x"00F0";
when x"2f9" => DATA <= x"1252";
when x"2fa" => DATA <= x"0AC0";
when x"2fb" => DATA <= x"02FD";
when x"2fc" => DATA <= x"0087";
when x"2fd" => DATA <= x"F83E";
when x"2fe" => DATA <= x"0027";
when x"2ff" => DATA <= x"F896";
when x"300" => DATA <= x"F5FF";
when x"301" => DATA <= x"F880";
when x"302" => DATA <= x"F500";
when x"303" => DATA <= x"FD94";
when x"304" => DATA <= x"0000";
when x"305" => DATA <= x"FFC0";
when x"306" => DATA <= x"0000";
when x"307" => DATA <= x"0000";
when x"308" => DATA <= x"F600";
when x"309" => DATA <= x"F804";
when x"30a" => DATA <= x"0000";
when x"30b" => DATA <= x"0100";
when x"30c" => DATA <= x"F500";
when x"30d" => DATA <= x"F83E";
when x"30e" => DATA <= x"F83E";
when x"30f" => DATA <= x"F83E";
when x"310" => DATA <= x"0000";
when x"311" => DATA <= x"FD96";
when x"312" => DATA <= x"F8D4";
when x"313" => DATA <= x"FA56";
when x"314" => DATA <= x"FAD4";
when x"315" => DATA <= x"FCC6";
when x"316" => DATA <= x"FCBA";
when x"317" => DATA <= x"FC82";
when x"318" => DATA <= x"FC0E";
when x"319" => DATA <= x"FBB6";
when x"31a" => DATA <= x"FC78";
when x"31b" => DATA <= x"FC9C";
when x"31c" => DATA <= x"FC52";
when x"31d" => DATA <= x"FBE0";
when x"31e" => DATA <= x"FD88";
when x"31f" => DATA <= x"FD3A";
when x"320" => DATA <= x"FD2E";
when x"321" => DATA <= x"FD94";
when x"322" => DATA <= x"9440";
when x"323" => DATA <= x"09F7";
when x"324" => DATA <= x"002A";
when x"325" => DATA <= x"2017";
when x"326" => DATA <= x"000D";
when x"327" => DATA <= x"02FA";
when x"328" => DATA <= x"0087";
when x"329" => DATA <= x"6081";
when x"32a" => DATA <= x"9840";
when x"32b" => DATA <= x"09F7";
when x"32c" => DATA <= x"001A";
when x"32d" => DATA <= x"0AC2";
when x"32e" => DATA <= x"02FB";
when x"32f" => DATA <= x"0087";
when x"330" => DATA <= x"6081";
when x"331" => DATA <= x"09F7";
when x"332" => DATA <= x"FE2A";
when x"333" => DATA <= x"9021";
when x"334" => DATA <= x"0AC2";
when x"335" => DATA <= x"02FB";
when x"336" => DATA <= x"0087";
when x"337" => DATA <= x"09F7";
when x"338" => DATA <= x"0002";
when x"339" => DATA <= x"1040";
when x"33a" => DATA <= x"35DF";
when x"33b" => DATA <= x"0040";
when x"33c" => DATA <= x"FFF4";
when x"33d" => DATA <= x"03FC";
when x"33e" => DATA <= x"901F";
when x"33f" => DATA <= x"FFF6";
when x"340" => DATA <= x"0087";
when x"341" => DATA <= x"97C0";
when x"342" => DATA <= x"FFF0";
when x"343" => DATA <= x"80FD";
when x"344" => DATA <= x"97C0";
when x"345" => DATA <= x"FFF2";
when x"346" => DATA <= x"0087";
when x"347" => DATA <= x"97C0";
when x"348" => DATA <= x"FFFC";
when x"349" => DATA <= x"80FD";
when x"34a" => DATA <= x"97C0";
when x"34b" => DATA <= x"FFFE";
when x"34c" => DATA <= x"0087";
when x"34d" => DATA <= x"1026";
when x"34e" => DATA <= x"97C0";
when x"34f" => DATA <= x"FFFC";
when x"350" => DATA <= x"811C";
when x"351" => DATA <= x"97C0";
when x"352" => DATA <= x"FFF0";
when x"353" => DATA <= x"8103";
when x"354" => DATA <= x"1580";
when x"355" => DATA <= x"007F";
when x"356" => DATA <= x"F73A";
when x"357" => DATA <= x"97C0";
when x"358" => DATA <= x"FFF2";
when x"359" => DATA <= x"8110";
when x"35a" => DATA <= x"1066";
when x"35b" => DATA <= x"10A6";
when x"35c" => DATA <= x"09F7";
when x"35d" => DATA <= x"FFC6";
when x"35e" => DATA <= x"1002";
when x"35f" => DATA <= x"09F7";
when x"360" => DATA <= x"FFC0";
when x"361" => DATA <= x"1001";
when x"362" => DATA <= x"09F7";
when x"363" => DATA <= x"FFBA";
when x"364" => DATA <= x"09FF";
when x"365" => DATA <= x"F718";
when x"366" => DATA <= x"1582";
when x"367" => DATA <= x"1581";
when x"368" => DATA <= x"1580";
when x"369" => DATA <= x"0002";
when x"36a" => DATA <= x"09FF";
when x"36b" => DATA <= x"F704";
when x"36c" => DATA <= x"01FB";
when x"36d" => DATA <= x"1066";
when x"36e" => DATA <= x"97C0";
when x"36f" => DATA <= x"FFFE";
when x"370" => DATA <= x"8012";
when x"371" => DATA <= x"09F7";
when x"372" => DATA <= x"FDAA";
when x"373" => DATA <= x"17C1";
when x"374" => DATA <= x"F5E2";
when x"375" => DATA <= x"09F7";
when x"376" => DATA <= x"FDA2";
when x"377" => DATA <= x"9011";
when x"378" => DATA <= x"09F7";
when x"379" => DATA <= x"FD9C";
when x"37a" => DATA <= x"9011";
when x"37b" => DATA <= x"02FC";
when x"37c" => DATA <= x"1581";
when x"37d" => DATA <= x"1580";
when x"37e" => DATA <= x"17C0";
when x"37f" => DATA <= x"F5E2";
when x"380" => DATA <= x"17CE";
when x"381" => DATA <= x"F5E0";
when x"382" => DATA <= x"0002";
when x"383" => DATA <= x"1001";
when x"384" => DATA <= x"09F7";
when x"385" => DATA <= x"FF82";
when x"386" => DATA <= x"2057";
when x"387" => DATA <= x"0005";
when x"388" => DATA <= x"03DE";
when x"389" => DATA <= x"09F7";
when x"38a" => DATA <= x"FF78";
when x"38b" => DATA <= x"09F7";
when x"38c" => DATA <= x"FF74";
when x"38d" => DATA <= x"09F7";
when x"38e" => DATA <= x"FF70";
when x"38f" => DATA <= x"901F";
when x"390" => DATA <= x"F5EB";
when x"391" => DATA <= x"09F7";
when x"392" => DATA <= x"FF68";
when x"393" => DATA <= x"901F";
when x"394" => DATA <= x"F5EA";
when x"395" => DATA <= x"6041";
when x"396" => DATA <= x"1C5F";
when x"397" => DATA <= x"FFC2";
when x"398" => DATA <= x"0080";
when x"399" => DATA <= x"09F7";
when x"39a" => DATA <= x"FF58";
when x"39b" => DATA <= x"17C0";
when x"39c" => DATA <= x"F5EA";
when x"39d" => DATA <= x"2057";
when x"39e" => DATA <= x"0008";
when x"39f" => DATA <= x"031D";
when x"3a0" => DATA <= x"2057";
when x"3a1" => DATA <= x"000C";
when x"3a2" => DATA <= x"87C4";
when x"3a3" => DATA <= x"030A";
when x"3a4" => DATA <= x"15C1";
when x"3a5" => DATA <= x"0100";
when x"3a6" => DATA <= x"8BDF";
when x"3a7" => DATA <= x"FFF8";
when x"3a8" => DATA <= x"80FD";
when x"3a9" => DATA <= x"97D0";
when x"3aa" => DATA <= x"FFFA";
when x"3ab" => DATA <= x"0AC1";
when x"3ac" => DATA <= x"02F9";
when x"3ad" => DATA <= x"01B9";
when x"3ae" => DATA <= x"15C1";
when x"3af" => DATA <= x"0100";
when x"3b0" => DATA <= x"8BDF";
when x"3b1" => DATA <= x"FFF8";
when x"3b2" => DATA <= x"80FD";
when x"3b3" => DATA <= x"941F";
when x"3b4" => DATA <= x"FFFA";
when x"3b5" => DATA <= x"0AC1";
when x"3b6" => DATA <= x"02F9";
when x"3b7" => DATA <= x"8BDF";
when x"3b8" => DATA <= x"FFF8";
when x"3b9" => DATA <= x"80FD";
when x"3ba" => DATA <= x"8A1F";
when x"3bb" => DATA <= x"FFFA";
when x"3bc" => DATA <= x"01AA";
when x"3bd" => DATA <= x"101F";
when x"3be" => DATA <= x"F5F8";
when x"3bf" => DATA <= x"01A7";
when x"3c0" => DATA <= x"1026";
when x"3c1" => DATA <= x"17C0";
when x"3c2" => DATA <= x"F5EA";
when x"3c3" => DATA <= x"97D0";
when x"3c4" => DATA <= x"FFFA";
when x"3c5" => DATA <= x"97D0";
when x"3c6" => DATA <= x"FFFA";
when x"3c7" => DATA <= x"0113";
when x"3c8" => DATA <= x"1026";
when x"3c9" => DATA <= x"17C0";
when x"3ca" => DATA <= x"F5EA";
when x"3cb" => DATA <= x"941F";
when x"3cc" => DATA <= x"FFFA";
when x"3cd" => DATA <= x"941F";
when x"3ce" => DATA <= x"FFFA";
when x"3cf" => DATA <= x"010B";
when x"3d0" => DATA <= x"1026";
when x"3d1" => DATA <= x"17C0";
when x"3d2" => DATA <= x"F5EA";
when x"3d3" => DATA <= x"97D0";
when x"3d4" => DATA <= x"FFFA";
when x"3d5" => DATA <= x"0105";
when x"3d6" => DATA <= x"1026";
when x"3d7" => DATA <= x"17C0";
when x"3d8" => DATA <= x"F5EA";
when x"3d9" => DATA <= x"941F";
when x"3da" => DATA <= x"FFFA";
when x"3db" => DATA <= x"101F";
when x"3dc" => DATA <= x"F5EA";
when x"3dd" => DATA <= x"018A";
when x"3de" => DATA <= x"8A1F";
when x"3df" => DATA <= x"FFFA";
when x"3e0" => DATA <= x"0002";
when x"3e1" => DATA <= x"FFAC";
when x"3e2" => DATA <= x"FFA0";
when x"3e3" => DATA <= x"FF90";
when x"3e4" => DATA <= x"FF80";
when x"3e5" => DATA <= x"FFBC";
when x"3e6" => DATA <= x"FFBC";
when x"3e7" => DATA <= x"FFBC";
when x"3e8" => DATA <= x"FFBC";
when x"3e9" => DATA <= x"0000";
when x"3ea" => DATA <= x"0000";
when x"3eb" => DATA <= x"0000";
when x"3ec" => DATA <= x"0000";
when x"3ed" => DATA <= x"0000";
when x"3ee" => DATA <= x"0000";
when x"3ef" => DATA <= x"0000";
when x"3f0" => DATA <= x"0000";
when x"3f1" => DATA <= x"0000";
when x"3f2" => DATA <= x"0000";
when x"3f3" => DATA <= x"0000";
when x"3f4" => DATA <= x"0000";
when x"3f5" => DATA <= x"0000";
when x"3f6" => DATA <= x"0000";
when x"3f7" => DATA <= x"0000";
when x"3f8" => DATA <= x"0000";
when x"3f9" => DATA <= x"0000";
when x"3fa" => DATA <= x"0000";
when x"3fb" => DATA <= x"0000";
when x"3fc" => DATA <= x"0000";
when x"3fd" => DATA <= x"0000";
when x"3fe" => DATA <= x"0000";
when x"3ff" => DATA <= x"0000";
when others => DATA <= (others => '0');
end case;
end process;
end RTL;
|
-- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 2; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 1;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 8;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant LMEM_IMPLEMENT : natural := 1;
-- implement local scratchpad
constant N_TAG_MANAGERS_W : natural := N_CU_W+1; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant RD_CACHE_N_WORDS_W : natural := 1;
constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 8;
constant FLOAT_IMPLEMENT : natural := 0;
constant FADD_IMPLEMENT : integer := 1;
constant FMUL_IMPLEMENT : integer := 1;
constant FDIV_IMPLEMENT : integer := 0;
constant FSQRT_IMPLEMENT : integer := 0;
constant UITOFP_IMPLEMENT : integer := 0;
constant FSLT_IMPLEMENT : integer := 0;
constant FRSQRT_IMPLEMENT : integer := 0;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant FRSQRT_DELAY : integer := 28;
constant FSLT_DELAY : integer := 2;
constant MAX_FPU_DELAY : integer := FADD_DELAY;
constant CACHE_N_BANKS_W : natural := 2;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 20912)
`protect data_block
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|
`protect begin_protected
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect end_protected
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Tue May 30 11:58:28 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/ZyboIP/general_ip/svd_2x2/svd_2x2.runs/arctan_synth_1/arctan_stub.vhdl
-- Design : arctan
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity arctan is
Port (
aclk : in STD_LOGIC;
s_axis_cartesian_tvalid : in STD_LOGIC;
s_axis_cartesian_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_dout_tvalid : out STD_LOGIC;
m_axis_dout_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
end arctan;
architecture stub of arctan is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "aclk,s_axis_cartesian_tvalid,s_axis_cartesian_tdata[31:0],m_axis_dout_tvalid,m_axis_dout_tdata[15:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "cordic_v6_0_11,Vivado 2016.4";
begin
end;
|
-- nios_dut_rst_controller.vhd
-- Generated using ACDS version 15.1 185
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nios_dut_rst_controller is
generic (
NUM_RESET_INPUTS : integer := 1;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 1;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := '0'; -- reset_in0.reset
clk : in std_logic := '0'; -- clk.clk
reset_out : out std_logic; -- reset_out.reset
reset_req : out std_logic; -- .reset_req
reset_in1 : in std_logic := '0';
reset_in10 : in std_logic := '0';
reset_in11 : in std_logic := '0';
reset_in12 : in std_logic := '0';
reset_in13 : in std_logic := '0';
reset_in14 : in std_logic := '0';
reset_in15 : in std_logic := '0';
reset_in2 : in std_logic := '0';
reset_in3 : in std_logic := '0';
reset_in4 : in std_logic := '0';
reset_in5 : in std_logic := '0';
reset_in6 : in std_logic := '0';
reset_in7 : in std_logic := '0';
reset_in8 : in std_logic := '0';
reset_in9 : in std_logic := '0';
reset_req_in0 : in std_logic := '0';
reset_req_in1 : in std_logic := '0';
reset_req_in10 : in std_logic := '0';
reset_req_in11 : in std_logic := '0';
reset_req_in12 : in std_logic := '0';
reset_req_in13 : in std_logic := '0';
reset_req_in14 : in std_logic := '0';
reset_req_in15 : in std_logic := '0';
reset_req_in2 : in std_logic := '0';
reset_req_in3 : in std_logic := '0';
reset_req_in4 : in std_logic := '0';
reset_req_in5 : in std_logic := '0';
reset_req_in6 : in std_logic := '0';
reset_req_in7 : in std_logic := '0';
reset_req_in8 : in std_logic := '0';
reset_req_in9 : in std_logic := '0'
);
end entity nios_dut_rst_controller;
architecture rtl of nios_dut_rst_controller is
component altera_reset_controller is
generic (
NUM_RESET_INPUTS : integer := 6;
OUTPUT_RESET_SYNC_EDGES : string := "deassert";
SYNC_DEPTH : integer := 2;
RESET_REQUEST_PRESENT : integer := 0;
RESET_REQ_WAIT_TIME : integer := 1;
MIN_RST_ASSERTION_TIME : integer := 3;
RESET_REQ_EARLY_DSRT_TIME : integer := 1;
USE_RESET_REQUEST_IN0 : integer := 0;
USE_RESET_REQUEST_IN1 : integer := 0;
USE_RESET_REQUEST_IN2 : integer := 0;
USE_RESET_REQUEST_IN3 : integer := 0;
USE_RESET_REQUEST_IN4 : integer := 0;
USE_RESET_REQUEST_IN5 : integer := 0;
USE_RESET_REQUEST_IN6 : integer := 0;
USE_RESET_REQUEST_IN7 : integer := 0;
USE_RESET_REQUEST_IN8 : integer := 0;
USE_RESET_REQUEST_IN9 : integer := 0;
USE_RESET_REQUEST_IN10 : integer := 0;
USE_RESET_REQUEST_IN11 : integer := 0;
USE_RESET_REQUEST_IN12 : integer := 0;
USE_RESET_REQUEST_IN13 : integer := 0;
USE_RESET_REQUEST_IN14 : integer := 0;
USE_RESET_REQUEST_IN15 : integer := 0;
ADAPT_RESET_REQUEST : integer := 0
);
port (
reset_in0 : in std_logic := 'X'; -- reset
clk : in std_logic := 'X'; -- clk
reset_out : out std_logic; -- reset
reset_req : out std_logic; -- reset_req
reset_req_in0 : in std_logic := 'X'; -- reset_req
reset_in1 : in std_logic := 'X'; -- reset
reset_req_in1 : in std_logic := 'X'; -- reset_req
reset_in2 : in std_logic := 'X'; -- reset
reset_req_in2 : in std_logic := 'X'; -- reset_req
reset_in3 : in std_logic := 'X'; -- reset
reset_req_in3 : in std_logic := 'X'; -- reset_req
reset_in4 : in std_logic := 'X'; -- reset
reset_req_in4 : in std_logic := 'X'; -- reset_req
reset_in5 : in std_logic := 'X'; -- reset
reset_req_in5 : in std_logic := 'X'; -- reset_req
reset_in6 : in std_logic := 'X'; -- reset
reset_req_in6 : in std_logic := 'X'; -- reset_req
reset_in7 : in std_logic := 'X'; -- reset
reset_req_in7 : in std_logic := 'X'; -- reset_req
reset_in8 : in std_logic := 'X'; -- reset
reset_req_in8 : in std_logic := 'X'; -- reset_req
reset_in9 : in std_logic := 'X'; -- reset
reset_req_in9 : in std_logic := 'X'; -- reset_req
reset_in10 : in std_logic := 'X'; -- reset
reset_req_in10 : in std_logic := 'X'; -- reset_req
reset_in11 : in std_logic := 'X'; -- reset
reset_req_in11 : in std_logic := 'X'; -- reset_req
reset_in12 : in std_logic := 'X'; -- reset
reset_req_in12 : in std_logic := 'X'; -- reset_req
reset_in13 : in std_logic := 'X'; -- reset
reset_req_in13 : in std_logic := 'X'; -- reset_req
reset_in14 : in std_logic := 'X'; -- reset
reset_req_in14 : in std_logic := 'X'; -- reset_req
reset_in15 : in std_logic := 'X'; -- reset
reset_req_in15 : in std_logic := 'X' -- reset_req
);
end component altera_reset_controller;
begin
rst_controller : component altera_reset_controller
generic map (
NUM_RESET_INPUTS => NUM_RESET_INPUTS,
OUTPUT_RESET_SYNC_EDGES => OUTPUT_RESET_SYNC_EDGES,
SYNC_DEPTH => SYNC_DEPTH,
RESET_REQUEST_PRESENT => RESET_REQUEST_PRESENT,
RESET_REQ_WAIT_TIME => RESET_REQ_WAIT_TIME,
MIN_RST_ASSERTION_TIME => MIN_RST_ASSERTION_TIME,
RESET_REQ_EARLY_DSRT_TIME => RESET_REQ_EARLY_DSRT_TIME,
USE_RESET_REQUEST_IN0 => USE_RESET_REQUEST_IN0,
USE_RESET_REQUEST_IN1 => USE_RESET_REQUEST_IN1,
USE_RESET_REQUEST_IN2 => USE_RESET_REQUEST_IN2,
USE_RESET_REQUEST_IN3 => USE_RESET_REQUEST_IN3,
USE_RESET_REQUEST_IN4 => USE_RESET_REQUEST_IN4,
USE_RESET_REQUEST_IN5 => USE_RESET_REQUEST_IN5,
USE_RESET_REQUEST_IN6 => USE_RESET_REQUEST_IN6,
USE_RESET_REQUEST_IN7 => USE_RESET_REQUEST_IN7,
USE_RESET_REQUEST_IN8 => USE_RESET_REQUEST_IN8,
USE_RESET_REQUEST_IN9 => USE_RESET_REQUEST_IN9,
USE_RESET_REQUEST_IN10 => USE_RESET_REQUEST_IN10,
USE_RESET_REQUEST_IN11 => USE_RESET_REQUEST_IN11,
USE_RESET_REQUEST_IN12 => USE_RESET_REQUEST_IN12,
USE_RESET_REQUEST_IN13 => USE_RESET_REQUEST_IN13,
USE_RESET_REQUEST_IN14 => USE_RESET_REQUEST_IN14,
USE_RESET_REQUEST_IN15 => USE_RESET_REQUEST_IN15,
ADAPT_RESET_REQUEST => ADAPT_RESET_REQUEST
)
port map (
reset_in0 => reset_in0, -- reset_in0.reset
clk => clk, -- clk.clk
reset_out => reset_out, -- reset_out.reset
reset_req => reset_req, -- .reset_req
reset_req_in0 => '0', -- (terminated)
reset_in1 => '0', -- (terminated)
reset_req_in1 => '0', -- (terminated)
reset_in2 => '0', -- (terminated)
reset_req_in2 => '0', -- (terminated)
reset_in3 => '0', -- (terminated)
reset_req_in3 => '0', -- (terminated)
reset_in4 => '0', -- (terminated)
reset_req_in4 => '0', -- (terminated)
reset_in5 => '0', -- (terminated)
reset_req_in5 => '0', -- (terminated)
reset_in6 => '0', -- (terminated)
reset_req_in6 => '0', -- (terminated)
reset_in7 => '0', -- (terminated)
reset_req_in7 => '0', -- (terminated)
reset_in8 => '0', -- (terminated)
reset_req_in8 => '0', -- (terminated)
reset_in9 => '0', -- (terminated)
reset_req_in9 => '0', -- (terminated)
reset_in10 => '0', -- (terminated)
reset_req_in10 => '0', -- (terminated)
reset_in11 => '0', -- (terminated)
reset_req_in11 => '0', -- (terminated)
reset_in12 => '0', -- (terminated)
reset_req_in12 => '0', -- (terminated)
reset_in13 => '0', -- (terminated)
reset_req_in13 => '0', -- (terminated)
reset_in14 => '0', -- (terminated)
reset_req_in14 => '0', -- (terminated)
reset_in15 => '0', -- (terminated)
reset_req_in15 => '0' -- (terminated)
);
end architecture rtl; -- of nios_dut_rst_controller
|
--
-- sort8k.vhd
-- eCos hardware thread using the bubble_sort module and mailboxes to
-- sort 8k-sized blocks of data in main memory. The incoming messages
-- on C_MB_START contain the addresses of the blocks, and an arbitrary
-- message sent to C_MB_DONE signals completion of the sorting process.
--
-- Author: Enno Luebbers <[email protected]>
-- Date: 28.09.2007
--
-- This file is part of the ReconOS project <http://www.reconos.de>.
-- University of Paderborn, Computer Engineering Group.
--
-- (C) Copyright University of Paderborn 2007.
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.NUMERIC_STD.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.all;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity sort8kinv is
generic (
C_BURST_AWIDTH : integer := 11;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
i_osif : in osif_os2task_t;
o_osif : out osif_task2os_t;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic
);
end sort8kinv;
architecture Behavioral of sort8kinv is
component bubble_sorter is
generic (
G_LEN : integer := 2048; -- number of words to sort
G_AWIDTH : integer := 11; -- in bits
G_DWIDTH : integer := 32 -- in bits
);
port (
clk : in std_logic;
reset : in std_logic;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to G_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to G_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to G_DWIDTH-1);
o_RAMWE : out std_logic;
start : in std_logic;
done : out std_logic
);
end component;
-- ReconOS thread-local mailbox handles
constant C_MB_START : std_logic_vector(0 to 31) := X"00000000";
constant C_MB_DONE : std_logic_vector(0 to 31) := X"00000001";
-- OS synchronization state machine states
type t_state is (STATE_GET, STATE_READ, STATE_SORT, STATE_WAIT, STATE_WRITE, STATE_PUT);
signal state : t_state := STATE_GET;
-- address of data to sort in main memory
signal address : std_logic_vector(0 to C_OSIF_DATA_WIDTH-1) := (others => '0');
-- handshaking signals
signal sort_start : std_logic := '0';
signal sort_done : std_logic;
-- RAM address
signal RAMAddr : std_logic_vector(0 to C_BURST_AWIDTH-1);
begin
-- instantiate bubble_sorter module
sorter_i : bubble_sorter
generic map (
G_LEN => 2048,
G_AWIDTH => C_BURST_AWIDTH,
G_DWIDTH => C_BURST_DWIDTH
)
port map (
clk => clk,
reset => reset,
o_RAMAddr => RAMAddr,
o_RAMData => o_RAMData,
i_RAMData => i_RAMData,
o_RAMWE => o_RAMWE,
start => sort_start,
done => sort_done
);
-- hook up RAM signals
o_RAMClk <= clk;
o_RAMAddr <= RAMAddr(0 to C_BURST_AWIDTH-2) & not RAMAddr(C_BURST_AWIDTH-1); -- invert LSB of address to get the word ordering right
-- OS synchronization state machine
state_proc : process(clk, reset)
variable done : boolean;
variable success : boolean;
variable burst_counter : natural range 0 to 8192/128 - 1;
begin
if reset = '1' then
reconos_reset(o_osif, i_osif);
sort_start <= '0';
state <= STATE_GET;
elsif rising_edge(clk) then
reconos_begin(o_osif, i_osif);
if reconos_ready(i_osif) then
case state is
-- wait for/get data address. No error checking is done here.
when STATE_GET =>
reconos_mbox_get_s(done, success, o_osif, i_osif, C_MB_START, address);
if done then
burst_counter := 0;
state <= STATE_READ;
end if;
-- read data from main memory into local burst RAM.
when STATE_READ =>
reconos_read_burst (done, o_osif, i_osif, std_logic_vector(TO_UNSIGNED(burst_counter*128, C_OSIF_DATA_WIDTH)), address+(burst_counter*128));
if done then
if burst_counter = 8192/128 - 1 then
state <= STATE_SORT;
else
burst_counter := burst_counter + 1;
end if;
end if;
-- start sorting module
when STATE_SORT =>
sort_start <= '1';
state <= STATE_WAIT;
-- wait for sort completion
when STATE_WAIT =>
sort_start <= '0';
if sort_done = '1' then
burst_counter := 0;
state <= STATE_WRITE;
end if;
-- write sorted data back to main memory
when STATE_WRITE =>
reconos_write_burst (done, o_osif, i_osif, std_logic_vector(TO_UNSIGNED(burst_counter*128, C_OSIF_DATA_WIDTH)), address+(burst_counter*128));
if done then
if burst_counter = 8192/128 - 1 then
state <= STATE_PUT;
else
burst_counter := burst_counter + 1;
end if;
end if;
-- write message to DONE mailbox
when STATE_PUT =>
reconos_mbox_put(done, success, o_osif, i_osif, C_MB_DONE, address);
if done then
state <= STATE_GET;
end if;
when others =>
state <= STATE_GET;
end case;
end if;
end if;
end process;
end Behavioral;
|
architecture RTL of ENTITY_NAME is
type T_FLAG_TYPE is protected body -- protected type declaration
procedure init (foo : real);
impure function myfunct return boolean;
constant c_con1 : std_logic;
variable v_var1 : integer;
end protected body T_FLAG_TYPE;
begin
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.myTypes.all;
entity mux41 is
generic (
MUX_SIZE : integer := 32
);
port (
IN0 : in std_logic_vector(MUX_SIZE - 1 downto 0);
IN1 : in std_logic_vector(MUX_SIZE - 1 downto 0);
IN2 : in std_logic_vector(MUX_SIZE - 1 downto 0);
IN3 : in std_logic_vector(MUX_SIZE - 1 downto 0);
CTRL : in std_logic_vector(1 downto 0);
OUT1 : out std_logic_vector(MUX_SIZE - 1 downto 0)
);
end mux41;
architecture bhe of mux41 is
begin
process ( CTRL, IN0, IN1, IN2, IN3)
begin
case CTRL is
when "00" => OUT1 <= IN0;
when "01" => OUT1 <= IN1;
when "10" => OUT1 <= IN2;
when "11" => OUT1 <= IN3;
when others => OUT1 <= (others => 'X'); -- should never appear
end case;
end process;
end bhe;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.myTypes.all;
entity mux41 is
generic (
MUX_SIZE : integer := 32
);
port (
IN0 : in std_logic_vector(MUX_SIZE - 1 downto 0);
IN1 : in std_logic_vector(MUX_SIZE - 1 downto 0);
IN2 : in std_logic_vector(MUX_SIZE - 1 downto 0);
IN3 : in std_logic_vector(MUX_SIZE - 1 downto 0);
CTRL : in std_logic_vector(1 downto 0);
OUT1 : out std_logic_vector(MUX_SIZE - 1 downto 0)
);
end mux41;
architecture bhe of mux41 is
begin
process ( CTRL, IN0, IN1, IN2, IN3)
begin
case CTRL is
when "00" => OUT1 <= IN0;
when "01" => OUT1 <= IN1;
when "10" => OUT1 <= IN2;
when "11" => OUT1 <= IN3;
when others => OUT1 <= (others => 'X'); -- should never appear
end case;
end process;
end bhe;
|
----------------------------------------------------------------------------------
-- Company: University of Queensland
-- Engineer: MDS
--
-- Create Date: 25/07/2014
-- Design Name:
-- Module Name: pracTop - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity practop_asynchro is
Port ( ssegAnode : out STD_LOGIC_VECTOR (7 downto 0);
ssegCathode : out STD_LOGIC_VECTOR (7 downto 0);
slideSwitches : in STD_LOGIC_VECTOR (15 downto 0);
pushButtons : in STD_LOGIC_VECTOR (4 downto 0);
LEDs : out STD_LOGIC_VECTOR (15 downto 0);
clk100mhz : in STD_LOGIC;
logic_analyzer : out STD_LOGIC_VECTOR (7 downto 0)
);
end practop_asynchro;
architecture Behavioral of practop_asynchro is
component ssegDriver port (
clk : in std_logic;
rst : in std_logic;
cathode_p : out std_logic_vector(7 downto 0);
anode_p : out std_logic_vector(7 downto 0);
digit1_p : in std_logic_vector(3 downto 0);
digit2_p : in std_logic_vector(3 downto 0);
digit3_p : in std_logic_vector(3 downto 0);
digit4_p : in std_logic_vector(3 downto 0);
digit5_p : in std_logic_vector(3 downto 0);
digit6_p : in std_logic_vector(3 downto 0);
digit7_p : in std_logic_vector(3 downto 0);
digit8_p : in std_logic_vector(3 downto 0)
);
end component;
component clockedRegister port (
D : in STD_LOGIC_VECTOR (15 downto 0);
E : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (15 downto 0)
);
end component;
signal masterReset : std_logic;
signal button1 : std_logic;
signal button2 : std_logic;
signal submitButton : std_logic;
signal currentState : std_logic_vector(2 downto 0);
signal openLock : std_logic := '0';
signal closeLock : std_logic := '0';
signal correctAttempts : std_logic_vector(7 downto 0) := (others => '0');
signal incorrectAttempts : std_logic_vector(7 downto 0) := (others => '0');
signal displayKey : std_logic_vector(15 downto 0);
signal upperKey : std_logic_vector(7 downto 0);
signal lowerKey : std_logic_vector(7 downto 0);
signal checkKey : std_logic_vector(15 downto 0);
signal regEnable : std_logic;
signal digit5 : std_logic_vector(3 downto 0);
signal digit6 : std_logic_vector(3 downto 0);
signal digit7 : std_logic_vector(3 downto 0);
signal digit8 : std_logic_vector(3 downto 0);
signal clockScalers : std_logic_vector (26 downto 0);
BEGIN
u1 : ssegDriver port map (
clk => clockScalers(11),
rst => masterReset,
cathode_p => ssegCathode,
anode_p => ssegAnode,
digit1_p => displayKey (3 downto 0),
digit2_p => displayKey (7 downto 4),
digit3_p => displayKey (11 downto 8),
digit4_p => displayKey (15 downto 12),
digit5_p => digit5,
digit6_p => digit6,
digit7_p => digit7,
digit8_p => digit8
);
u2 : clockedRegister port map (
D (7 downto 0) => lowerKey,
D (15 downto 8) => upperKey,
E => regEnable,
clk => clk100mhz,
reset => masterReset,
Q => checkKey
);
masterReset <= pushButtons(3);
submitButton <= pushButtons(2);
button1 <= pushButtons(1);
button2 <= pushButtons(0);
logic_analyzer <= clockScalers(26 downto 19);
process (clk100mhz, masterReset) begin
if (masterReset = '1') then
clockScalers <= "000000000000000000000000000";
elsif (clk100mhz'event and clk100mhz = '1')then
clockScalers <= clockScalers + '1';
end if;
end process;
regEnable <= '1';
process (masterReset, button1, displayKey) begin
if (masterReset = '1') then
lowerKey <= (others => '0');
displayKey(7 downto 0) <= "00000000";
elsif (button1'event and button1 = '1') then
displayKey(7 downto 0) <= slideSwitches(7 downto 0);
lowerKey <= slideSwitches(7 downto 0);
end if;
end process;
process (masterReset, button2, displayKey) begin
if (masterReset = '1') then
upperKey <= (others => '0');
displayKey (15 downto 8) <= "00000000";
elsif (button2'event and button2 = '1') then
displayKey (15 downto 8) <= slideSwitches(7 downto 0);
upperKey <= slideSwitches(7 downto 0);
end if;
end process;
--digit6 <= lowerKey(7 downto 4);
--digit5 <= lowerKey(3 downto 0);
--digit8 <= lowerKey(7 downto 4);
--digit7 <= lowerKey(3 downto 0);
process (masterReset, submitButton, button1, button2, displayKey) begin
if (masterReset = '1' or button1 = '1' or button2 = '1') then
openLock <= '0';
closeLock <= '0';
elsif (submitButton'event and submitButton = '1') then
if (lowerKey = "11111111" and upperKey = "11111110") then
openLock <= '1';
closeLock <= '0';
else
openLock <= '0';
closeLock <= '1';
end if;
end if;
end process;
process (openLock , clockScalers) begin
LEDs (15 downto 2) <= clockScalers(26 downto 13);
if(openLock = '1') then
LEDs(0) <= '0';
LEDs(1) <= '1';
else
LEDs(0) <= '1';
LEDs(1) <= '0';
end if;
end process;
digit6 <= incorrectAttempts(7 downto 4);
digit5 <= incorrectAttempts(3 downto 0);
digit8 <= correctAttempts(7 downto 4);
digit7 <= correctAttempts(3 downto 0);
process (masterReset, openlock) begin
if (masterReset = '1') then
correctAttempts <= (others => '0');
elsif (openLock'event and openLock = '1' ) then
correctAttempts <= correctAttempts + '1';
end if;
end process;
process (masterReset, closelock) begin
if (masterReset = '1') then
incorrectAttempts <= (others => '0');
elsif (closeLock'event and closeLock = '1' ) then
incorrectAttempts <= incorrectAttempts + '1';
end if;
end process;
end Behavioral;
|
-- NEED RESULT: This should only come out once
-- NEED RESULT: *** An assertion with report = 'This should only come out once' and severity level = 'Note'
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00327
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.4 (7)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00327_Test_Bench(ARCH00327_Test_Bench)
--
-- REVISION HISTORY:
--
-- 29-JUL-1987 - initial revision
--
-- NOTES:
--
-- Verify that assertion messages match comment messages output
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00327_Test_Bench is
end ENT00327_Test_Bench ;
architecture ARCH00327_Test_Bench of ENT00327_Test_Bench is
begin
assert False
report "This should only come out once"
severity Note ;
process
begin
print ( "*** An assertion with report = "&
"'This should only come out once' and severity level = "&
"'Note'" ) ;
wait ;
end process ;
end ARCH00327_Test_Bench ;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity b is
port(
clk : in std_logic;
din_enable : in std_logic;
din_value : in unsigned(15 downto 0);
dout_enable : out std_logic;
dout_value : out unsigned(15 downto 0)
);
end b;
architecture b_archi1 of b is
begin
proc_add : process(clk)
begin
if rising_edge(clk) then
dout_enable <= din_enable;
if din_enable = '1' then
dout_value <= resize(din_value * 2,dout_value'length);
end if;
end if;
end process proc_add;
end b_archi1;
architecture b_archi2 of b is
begin
proc_add : process(clk)
begin
if rising_edge(clk) then
dout_enable <= din_enable;
if din_enable = '1' then
dout_value <= resize(din_value * 3,dout_value'length);
end if;
end if;
end process proc_add;
end b_archi2;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL srst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(32-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
SIGNAL rst_sync_rd1 : STD_LOGIC := '0';
SIGNAL rst_sync_rd2 : STD_LOGIC := '0';
SIGNAL rst_sync_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Synchronous reset generation for FIFO core
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_sync_rd1 <= RESET;
rst_sync_rd2 <= rst_sync_rd1;
rst_sync_rd3 <= rst_sync_rd2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
clk_buf: bufg
PORT map(
i => CLK,
o => clk_i
);
------------------
srst <= rst_sync_rd3 OR rst_s_rd AFTER 24 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 32,
C_DOUT_WIDTH => 32,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 32,
C_DIN_WIDTH => 32,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 32,
C_DIN_WIDTH => 32,
C_WR_PNTR_WIDTH => 4,
C_RD_PNTR_WIDTH => 4,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : RX_RECV_FIFO_top
PORT MAP (
CLK => clk_i,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cpu6502 is
port (
cpu_clk : in std_logic;
cpu_clk_en : in std_logic;
cpu_reset : in std_logic;
cpu_write : out std_logic;
cpu_wdata : out std_logic_vector(7 downto 0);
cpu_rdata : in std_logic_vector(7 downto 0);
cpu_addr : out std_logic_vector(16 downto 0);
cpu_pc : out std_logic_vector(15 downto 0);
IRQn : in std_logic; -- IRQ interrupt (level sensitive)
NMIn : in std_logic; -- NMI interrupt (edge sensitive)
SOn : in std_logic -- set Overflow flag
);
attribute optimize : string;
attribute optimize of cpu6502 : entity is "SPEED";
end cpu6502;
architecture cycle_exact of cpu6502 is
signal read_write_n : std_logic;
begin
core: entity work.proc_core
generic map (
support_bcd => true )
port map(
clock => cpu_clk,
clock_en => cpu_clk_en,
reset => cpu_reset,
irq_n => IRQn,
nmi_n => NMIn,
so_n => SOn,
pc_out => cpu_pc,
addr_out => cpu_addr,
data_in => cpu_rdata,
data_out => cpu_wdata,
read_write_n => read_write_n );
cpu_write <= not read_write_n;
end cycle_exact;
|
-------------------------------------------------------------------------------
--! @file AEAD.vhd
--! @brief Top-level template of authenticated encryption unit.
--!
--! @project CAESAR Candidate Evaluation
--! @author Ekawat (ice) Homsirikamol
--! @copyright Copyright (c) 2015 Cryptographic Engineering Research Group
--! ECE Department, George Mason University Fairfax, VA, U.S.A.
--! All rights Reserved.
--! @license This project is released under the GNU Public License.
--! The license and distribution terms for this file may be
--! found in the file LICENSE in this distribution or at
--! http://www.gnu.org/licenses/gpl-3.0.txt
--! @note This is publicly available encryption source code that falls
--! under the License Exception TSU (Technology and software-
--! —unrestricted)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity AEAD is
generic (
--! I/O size (bits)
G_W : integer := 32; --! Public data input
G_SW : integer := 32 --! Secret data input
);
port (
--! Global ports
clk : in std_logic;
rst : in std_logic;
--! Publica data ports
pdi : in std_logic_vector(G_W -1 downto 0);
pdi_valid : in std_logic;
pdi_ready : out std_logic;
--! Secret data ports
sdi : in std_logic_vector(G_SW -1 downto 0);
sdi_valid : in std_logic;
sdi_ready : out std_logic;
--! Data out ports
do : out std_logic_vector(G_W -1 downto 0);
do_ready : in std_logic;
do_valid : out std_logic
);
end AEAD;
-------------------------------------------------------------------------------
--! @brief Architecture definition of AEAD
-------------------------------------------------------------------------------
architecture structure of AEAD is
begin
end architecture structure; |
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
package zpupkg is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := maxAddrBitBRAM;
constant ioBit : integer := maxAddrBitIncIO;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
type zpu_dbg_out_type is record
pc: std_logic_vector(maxAddrBit downto 0);
opcode: std_logic_vector(7 downto 0);
sp: std_logic_vector(10 downto 2);
brk: std_logic;
ready: std_logic;
idim: std_logic;
stacka: std_logic_vector(wordSize-1 downto 0);
stackb: std_logic_vector(wordSize-1 downto 0);
valid: std_logic;
end record;
type zpu_dbg_in_type is record
step: std_logic;
freeze: std_logic;
inject: std_logic;
injectmode: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
component zpu_core_extreme is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
--cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_b_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
constant OpCode_NA : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6));
constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6));
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6));
constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6));
constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
constant OpCode_Size : integer := 8;
end zpupkg;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
package zpupkg is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := maxAddrBitBRAM;
constant ioBit : integer := maxAddrBitIncIO;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
type zpu_dbg_out_type is record
pc: std_logic_vector(maxAddrBit downto 0);
opcode: std_logic_vector(7 downto 0);
sp: std_logic_vector(10 downto 2);
brk: std_logic;
ready: std_logic;
idim: std_logic;
stacka: std_logic_vector(wordSize-1 downto 0);
stackb: std_logic_vector(wordSize-1 downto 0);
valid: std_logic;
end record;
type zpu_dbg_in_type is record
step: std_logic;
freeze: std_logic;
inject: std_logic;
injectmode: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
component zpu_core_extreme is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
--cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_b_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
constant OpCode_NA : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6));
constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6));
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6));
constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6));
constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
constant OpCode_Size : integer := 8;
end zpupkg;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
package zpupkg is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := maxAddrBitBRAM;
constant ioBit : integer := maxAddrBitIncIO;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
type zpu_dbg_out_type is record
pc: std_logic_vector(maxAddrBit downto 0);
opcode: std_logic_vector(7 downto 0);
sp: std_logic_vector(10 downto 2);
brk: std_logic;
ready: std_logic;
idim: std_logic;
stacka: std_logic_vector(wordSize-1 downto 0);
stackb: std_logic_vector(wordSize-1 downto 0);
valid: std_logic;
end record;
type zpu_dbg_in_type is record
step: std_logic;
freeze: std_logic;
inject: std_logic;
injectmode: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
component zpu_core_extreme is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
--cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_b_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
constant OpCode_NA : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6));
constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6));
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6));
constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6));
constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
constant OpCode_Size : integer := 8;
end zpupkg;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
package zpupkg is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := maxAddrBitBRAM;
constant ioBit : integer := maxAddrBitIncIO;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
type zpu_dbg_out_type is record
pc: std_logic_vector(maxAddrBit downto 0);
opcode: std_logic_vector(7 downto 0);
sp: std_logic_vector(10 downto 2);
brk: std_logic;
ready: std_logic;
idim: std_logic;
stacka: std_logic_vector(wordSize-1 downto 0);
stackb: std_logic_vector(wordSize-1 downto 0);
valid: std_logic;
end record;
type zpu_dbg_in_type is record
step: std_logic;
freeze: std_logic;
inject: std_logic;
injectmode: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
component zpu_core_extreme is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
--cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_b_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
constant OpCode_NA : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6));
constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6));
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6));
constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6));
constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
constant OpCode_Size : integer := 8;
end zpupkg;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
package zpupkg is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := maxAddrBitBRAM;
constant ioBit : integer := maxAddrBitIncIO;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
type zpu_dbg_out_type is record
pc: std_logic_vector(maxAddrBit downto 0);
opcode: std_logic_vector(7 downto 0);
sp: std_logic_vector(10 downto 2);
brk: std_logic;
ready: std_logic;
idim: std_logic;
stacka: std_logic_vector(wordSize-1 downto 0);
stackb: std_logic_vector(wordSize-1 downto 0);
valid: std_logic;
end record;
type zpu_dbg_in_type is record
step: std_logic;
freeze: std_logic;
inject: std_logic;
injectmode: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
component zpu_core_extreme is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
--cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_b_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
constant OpCode_NA : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6));
constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6));
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6));
constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6));
constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
constant OpCode_Size : integer := 8;
end zpupkg;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
package zpupkg is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := maxAddrBitBRAM;
constant ioBit : integer := maxAddrBitIncIO;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
type zpu_dbg_out_type is record
pc: std_logic_vector(maxAddrBit downto 0);
opcode: std_logic_vector(7 downto 0);
sp: std_logic_vector(10 downto 2);
brk: std_logic;
ready: std_logic;
idim: std_logic;
stacka: std_logic_vector(wordSize-1 downto 0);
stackb: std_logic_vector(wordSize-1 downto 0);
valid: std_logic;
end record;
type zpu_dbg_in_type is record
step: std_logic;
freeze: std_logic;
inject: std_logic;
injectmode: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
component zpu_core_extreme is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
--cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_b_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
constant OpCode_NA : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6));
constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6));
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6));
constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6));
constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
constant OpCode_Size : integer := 8;
end zpupkg;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
package zpupkg is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := maxAddrBitBRAM;
constant ioBit : integer := maxAddrBitIncIO;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
type zpu_dbg_out_type is record
pc: std_logic_vector(maxAddrBit downto 0);
opcode: std_logic_vector(7 downto 0);
sp: std_logic_vector(10 downto 2);
brk: std_logic;
ready: std_logic;
idim: std_logic;
stacka: std_logic_vector(wordSize-1 downto 0);
stackb: std_logic_vector(wordSize-1 downto 0);
valid: std_logic;
end record;
type zpu_dbg_in_type is record
step: std_logic;
freeze: std_logic;
inject: std_logic;
injectmode: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
component zpu_core_extreme is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
--cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_b_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
constant OpCode_NA : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6));
constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6));
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6));
constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6));
constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
constant OpCode_Size : integer := 8;
end zpupkg;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
package zpupkg is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := maxAddrBitBRAM;
constant ioBit : integer := maxAddrBitIncIO;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
type zpu_dbg_out_type is record
pc: std_logic_vector(maxAddrBit downto 0);
opcode: std_logic_vector(7 downto 0);
sp: std_logic_vector(10 downto 2);
brk: std_logic;
ready: std_logic;
idim: std_logic;
stacka: std_logic_vector(wordSize-1 downto 0);
stackb: std_logic_vector(wordSize-1 downto 0);
valid: std_logic;
end record;
type zpu_dbg_in_type is record
step: std_logic;
freeze: std_logic;
inject: std_logic;
injectmode: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
component zpu_core_extreme is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
--cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_b_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
constant OpCode_NA : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6));
constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6));
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6));
constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6));
constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
constant OpCode_Size : integer := 8;
end zpupkg;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
package zpupkg is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := maxAddrBitBRAM;
constant ioBit : integer := maxAddrBitIncIO;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
type zpu_dbg_out_type is record
pc: std_logic_vector(maxAddrBit downto 0);
opcode: std_logic_vector(7 downto 0);
sp: std_logic_vector(10 downto 2);
brk: std_logic;
ready: std_logic;
idim: std_logic;
stacka: std_logic_vector(wordSize-1 downto 0);
stackb: std_logic_vector(wordSize-1 downto 0);
valid: std_logic;
end record;
type zpu_dbg_in_type is record
step: std_logic;
freeze: std_logic;
inject: std_logic;
injectmode: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
component zpu_core_extreme is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
--cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_b_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
constant OpCode_NA : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6));
constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6));
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6));
constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6));
constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
constant OpCode_Size : integer := 8;
end zpupkg;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
package zpupkg is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := maxAddrBitBRAM;
constant ioBit : integer := maxAddrBitIncIO;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
type zpu_dbg_out_type is record
pc: std_logic_vector(maxAddrBit downto 0);
opcode: std_logic_vector(7 downto 0);
sp: std_logic_vector(10 downto 2);
brk: std_logic;
ready: std_logic;
idim: std_logic;
stacka: std_logic_vector(wordSize-1 downto 0);
stackb: std_logic_vector(wordSize-1 downto 0);
valid: std_logic;
end record;
type zpu_dbg_in_type is record
step: std_logic;
freeze: std_logic;
inject: std_logic;
injectmode: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
component zpu_core_extreme is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
--cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_b_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
constant OpCode_NA : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6));
constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6));
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6));
constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6));
constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
constant OpCode_Size : integer := 8;
end zpupkg;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
package zpupkg is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := maxAddrBitBRAM;
constant ioBit : integer := maxAddrBitIncIO;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
type zpu_dbg_out_type is record
pc: std_logic_vector(maxAddrBit downto 0);
opcode: std_logic_vector(7 downto 0);
sp: std_logic_vector(10 downto 2);
brk: std_logic;
ready: std_logic;
idim: std_logic;
stacka: std_logic_vector(wordSize-1 downto 0);
stackb: std_logic_vector(wordSize-1 downto 0);
valid: std_logic;
end record;
type zpu_dbg_in_type is record
step: std_logic;
freeze: std_logic;
inject: std_logic;
injectmode: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
component zpu_core_extreme is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
--cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_b_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
constant OpCode_NA : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6));
constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6));
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6));
constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6));
constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
constant OpCode_Size : integer := 8;
end zpupkg;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
package zpupkg is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := maxAddrBitBRAM;
constant ioBit : integer := maxAddrBitIncIO;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
type zpu_dbg_out_type is record
pc: std_logic_vector(maxAddrBit downto 0);
opcode: std_logic_vector(7 downto 0);
sp: std_logic_vector(10 downto 2);
brk: std_logic;
ready: std_logic;
idim: std_logic;
stacka: std_logic_vector(wordSize-1 downto 0);
stackb: std_logic_vector(wordSize-1 downto 0);
valid: std_logic;
end record;
type zpu_dbg_in_type is record
step: std_logic;
freeze: std_logic;
inject: std_logic;
injectmode: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
component zpu_core_extreme is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
--cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_b_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
constant OpCode_NA : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6));
constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6));
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6));
constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6));
constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
constant OpCode_Size : integer := 8;
end zpupkg;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
package zpupkg is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := maxAddrBitBRAM;
constant ioBit : integer := maxAddrBitIncIO;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
type zpu_dbg_out_type is record
pc: std_logic_vector(maxAddrBit downto 0);
opcode: std_logic_vector(7 downto 0);
sp: std_logic_vector(10 downto 2);
brk: std_logic;
ready: std_logic;
idim: std_logic;
stacka: std_logic_vector(wordSize-1 downto 0);
stackb: std_logic_vector(wordSize-1 downto 0);
valid: std_logic;
end record;
type zpu_dbg_in_type is record
step: std_logic;
freeze: std_logic;
inject: std_logic;
injectmode: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
component zpu_core_extreme is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
--cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_b_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
constant OpCode_NA : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6));
constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6));
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6));
constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6));
constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
constant OpCode_Size : integer := 8;
end zpupkg;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
package zpupkg is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := maxAddrBitBRAM;
constant ioBit : integer := maxAddrBitIncIO;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
type zpu_dbg_out_type is record
pc: std_logic_vector(maxAddrBit downto 0);
opcode: std_logic_vector(7 downto 0);
sp: std_logic_vector(10 downto 2);
brk: std_logic;
ready: std_logic;
idim: std_logic;
stacka: std_logic_vector(wordSize-1 downto 0);
stackb: std_logic_vector(wordSize-1 downto 0);
valid: std_logic;
end record;
type zpu_dbg_in_type is record
step: std_logic;
freeze: std_logic;
inject: std_logic;
injectmode: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
component zpu_core_extreme is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
--cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_b_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
constant OpCode_NA : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6));
constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6));
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6));
constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6));
constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
constant OpCode_Size : integer := 8;
end zpupkg;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
package zpupkg is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := maxAddrBitBRAM;
constant ioBit : integer := maxAddrBitIncIO;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
type zpu_dbg_out_type is record
pc: std_logic_vector(maxAddrBit downto 0);
opcode: std_logic_vector(7 downto 0);
sp: std_logic_vector(10 downto 2);
brk: std_logic;
ready: std_logic;
idim: std_logic;
stacka: std_logic_vector(wordSize-1 downto 0);
stackb: std_logic_vector(wordSize-1 downto 0);
valid: std_logic;
end record;
type zpu_dbg_in_type is record
step: std_logic;
freeze: std_logic;
inject: std_logic;
injectmode: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
component zpu_core_extreme is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
--cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_b_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
constant OpCode_NA : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6));
constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6));
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6));
constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6));
constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
constant OpCode_Size : integer := 8;
end zpupkg;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
package zpupkg is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := maxAddrBitBRAM;
constant ioBit : integer := maxAddrBitIncIO;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
type zpu_dbg_out_type is record
pc: std_logic_vector(maxAddrBit downto 0);
opcode: std_logic_vector(7 downto 0);
sp: std_logic_vector(10 downto 2);
brk: std_logic;
ready: std_logic;
idim: std_logic;
stacka: std_logic_vector(wordSize-1 downto 0);
stackb: std_logic_vector(wordSize-1 downto 0);
valid: std_logic;
end record;
type zpu_dbg_in_type is record
step: std_logic;
freeze: std_logic;
inject: std_logic;
injectmode: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
component zpu_core_extreme is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
--cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_b_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
constant OpCode_NA : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6));
constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6));
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6));
constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6));
constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
constant OpCode_Size : integer := 8;
end zpupkg;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
package zpupkg is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := maxAddrBitBRAM;
constant ioBit : integer := maxAddrBitIncIO;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
type zpu_dbg_out_type is record
pc: std_logic_vector(maxAddrBit downto 0);
opcode: std_logic_vector(7 downto 0);
sp: std_logic_vector(10 downto 2);
brk: std_logic;
ready: std_logic;
idim: std_logic;
stacka: std_logic_vector(wordSize-1 downto 0);
stackb: std_logic_vector(wordSize-1 downto 0);
valid: std_logic;
end record;
type zpu_dbg_in_type is record
step: std_logic;
freeze: std_logic;
inject: std_logic;
injectmode: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
component zpu_core_extreme is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
--cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_b_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
constant OpCode_NA : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6));
constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6));
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6));
constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6));
constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
constant OpCode_Size : integer := 8;
end zpupkg;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
package zpupkg is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := maxAddrBitBRAM;
constant ioBit : integer := maxAddrBitIncIO;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
type zpu_dbg_out_type is record
pc: std_logic_vector(maxAddrBit downto 0);
opcode: std_logic_vector(7 downto 0);
sp: std_logic_vector(10 downto 2);
brk: std_logic;
ready: std_logic;
idim: std_logic;
stacka: std_logic_vector(wordSize-1 downto 0);
stackb: std_logic_vector(wordSize-1 downto 0);
valid: std_logic;
end record;
type zpu_dbg_in_type is record
step: std_logic;
freeze: std_logic;
inject: std_logic;
injectmode: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
component zpu_core_extreme is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
--cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_b_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
constant OpCode_NA : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6));
constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6));
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6));
constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6));
constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
constant OpCode_Size : integer := 8;
end zpupkg;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
package zpupkg is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := maxAddrBitBRAM;
constant ioBit : integer := maxAddrBitIncIO;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
type zpu_dbg_out_type is record
pc: std_logic_vector(maxAddrBit downto 0);
opcode: std_logic_vector(7 downto 0);
sp: std_logic_vector(10 downto 2);
brk: std_logic;
ready: std_logic;
idim: std_logic;
stacka: std_logic_vector(wordSize-1 downto 0);
stackb: std_logic_vector(wordSize-1 downto 0);
valid: std_logic;
end record;
type zpu_dbg_in_type is record
step: std_logic;
freeze: std_logic;
inject: std_logic;
injectmode: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
component zpu_core_extreme is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
--cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_b_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
constant OpCode_NA : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6));
constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6));
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6));
constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6));
constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
constant OpCode_Size : integer := 8;
end zpupkg;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
package zpupkg is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := maxAddrBitBRAM;
constant ioBit : integer := maxAddrBitIncIO;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
type zpu_dbg_out_type is record
pc: std_logic_vector(maxAddrBit downto 0);
opcode: std_logic_vector(7 downto 0);
sp: std_logic_vector(10 downto 2);
brk: std_logic;
ready: std_logic;
idim: std_logic;
stacka: std_logic_vector(wordSize-1 downto 0);
stackb: std_logic_vector(wordSize-1 downto 0);
valid: std_logic;
end record;
type zpu_dbg_in_type is record
step: std_logic;
freeze: std_logic;
inject: std_logic;
injectmode: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
component zpu_core_extreme is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
--cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_b_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
constant OpCode_NA : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6));
constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6));
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6));
constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6));
constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
constant OpCode_Size : integer := 8;
end zpupkg;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
package zpupkg is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := maxAddrBitBRAM;
constant ioBit : integer := maxAddrBitIncIO;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
type zpu_dbg_out_type is record
pc: std_logic_vector(maxAddrBit downto 0);
opcode: std_logic_vector(7 downto 0);
sp: std_logic_vector(10 downto 2);
brk: std_logic;
ready: std_logic;
idim: std_logic;
stacka: std_logic_vector(wordSize-1 downto 0);
stackb: std_logic_vector(wordSize-1 downto 0);
valid: std_logic;
end record;
type zpu_dbg_in_type is record
step: std_logic;
freeze: std_logic;
inject: std_logic;
injectmode: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
component zpu_core_extreme is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
--cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_b_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
constant OpCode_NA : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6));
constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6));
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6));
constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6));
constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
constant OpCode_Size : integer := 8;
end zpupkg;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
package zpupkg is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := maxAddrBitBRAM;
constant ioBit : integer := maxAddrBitIncIO;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
type zpu_dbg_out_type is record
pc: std_logic_vector(maxAddrBit downto 0);
opcode: std_logic_vector(7 downto 0);
sp: std_logic_vector(10 downto 2);
brk: std_logic;
ready: std_logic;
idim: std_logic;
stacka: std_logic_vector(wordSize-1 downto 0);
stackb: std_logic_vector(wordSize-1 downto 0);
valid: std_logic;
end record;
type zpu_dbg_in_type is record
step: std_logic;
freeze: std_logic;
inject: std_logic;
injectmode: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
component zpu_core_extreme is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
--cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_b_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
constant OpCode_NA : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6));
constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6));
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6));
constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6));
constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
constant OpCode_Size : integer := 8;
end zpupkg;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
package zpupkg is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := maxAddrBitBRAM;
constant ioBit : integer := maxAddrBitIncIO;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
type zpu_dbg_out_type is record
pc: std_logic_vector(maxAddrBit downto 0);
opcode: std_logic_vector(7 downto 0);
sp: std_logic_vector(10 downto 2);
brk: std_logic;
ready: std_logic;
idim: std_logic;
stacka: std_logic_vector(wordSize-1 downto 0);
stackb: std_logic_vector(wordSize-1 downto 0);
valid: std_logic;
end record;
type zpu_dbg_in_type is record
step: std_logic;
freeze: std_logic;
inject: std_logic;
injectmode: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
component zpu_core_extreme is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
--cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_b_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
constant OpCode_NA : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6));
constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6));
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6));
constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6));
constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
constant OpCode_Size : integer := 8;
end zpupkg;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
package zpupkg is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := maxAddrBitBRAM;
constant ioBit : integer := maxAddrBitIncIO;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
type zpu_dbg_out_type is record
pc: std_logic_vector(maxAddrBit downto 0);
opcode: std_logic_vector(7 downto 0);
sp: std_logic_vector(10 downto 2);
brk: std_logic;
ready: std_logic;
idim: std_logic;
stacka: std_logic_vector(wordSize-1 downto 0);
stackb: std_logic_vector(wordSize-1 downto 0);
valid: std_logic;
end record;
type zpu_dbg_in_type is record
step: std_logic;
freeze: std_logic;
inject: std_logic;
injectmode: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
component zpu_core_extreme is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
--cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_b_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
constant OpCode_NA : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6));
constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6));
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6));
constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6));
constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
constant OpCode_Size : integer := 8;
end zpupkg;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
package zpupkg is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := maxAddrBitBRAM;
constant ioBit : integer := maxAddrBitIncIO;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
type zpu_dbg_out_type is record
pc: std_logic_vector(maxAddrBit downto 0);
opcode: std_logic_vector(7 downto 0);
sp: std_logic_vector(10 downto 2);
brk: std_logic;
ready: std_logic;
idim: std_logic;
stacka: std_logic_vector(wordSize-1 downto 0);
stackb: std_logic_vector(wordSize-1 downto 0);
valid: std_logic;
end record;
type zpu_dbg_in_type is record
step: std_logic;
freeze: std_logic;
inject: std_logic;
injectmode: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
component zpu_core_extreme is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
--cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_b_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
constant OpCode_NA : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6));
constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6));
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6));
constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6));
constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
constant OpCode_Size : integer := 8;
end zpupkg;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
package zpupkg is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := maxAddrBitBRAM;
constant ioBit : integer := maxAddrBitIncIO;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
type zpu_dbg_out_type is record
pc: std_logic_vector(maxAddrBit downto 0);
opcode: std_logic_vector(7 downto 0);
sp: std_logic_vector(10 downto 2);
brk: std_logic;
ready: std_logic;
idim: std_logic;
stacka: std_logic_vector(wordSize-1 downto 0);
stackb: std_logic_vector(wordSize-1 downto 0);
valid: std_logic;
end record;
type zpu_dbg_in_type is record
step: std_logic;
freeze: std_logic;
inject: std_logic;
injectmode: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
component zpu_core_extreme is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
--cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_b_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
constant OpCode_NA : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6));
constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6));
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6));
constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6));
constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
constant OpCode_Size : integer := 8;
end zpupkg;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
package zpupkg is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := maxAddrBitBRAM;
constant ioBit : integer := maxAddrBitIncIO;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
type zpu_dbg_out_type is record
pc: std_logic_vector(maxAddrBit downto 0);
opcode: std_logic_vector(7 downto 0);
sp: std_logic_vector(10 downto 2);
brk: std_logic;
ready: std_logic;
idim: std_logic;
stacka: std_logic_vector(wordSize-1 downto 0);
stackb: std_logic_vector(wordSize-1 downto 0);
valid: std_logic;
end record;
type zpu_dbg_in_type is record
step: std_logic;
freeze: std_logic;
inject: std_logic;
injectmode: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
component zpu_core_extreme is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
--cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_b_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
constant OpCode_NA : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6));
constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6));
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6));
constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6));
constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
constant OpCode_Size : integer := 8;
end zpupkg;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
package zpupkg is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := maxAddrBitBRAM;
constant ioBit : integer := maxAddrBitIncIO;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
type zpu_dbg_out_type is record
pc: std_logic_vector(maxAddrBit downto 0);
opcode: std_logic_vector(7 downto 0);
sp: std_logic_vector(10 downto 2);
brk: std_logic;
ready: std_logic;
idim: std_logic;
stacka: std_logic_vector(wordSize-1 downto 0);
stackb: std_logic_vector(wordSize-1 downto 0);
valid: std_logic;
end record;
type zpu_dbg_in_type is record
step: std_logic;
freeze: std_logic;
inject: std_logic;
injectmode: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
component zpu_core_extreme is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
--cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_b_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
constant OpCode_NA : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6));
constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6));
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6));
constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6));
constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
constant OpCode_Size : integer := 8;
end zpupkg;
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