content
stringlengths 1
1.04M
⌀ |
|---|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
package zpupkg is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := maxAddrBitBRAM;
constant ioBit : integer := maxAddrBitIncIO;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
type zpu_dbg_out_type is record
pc: std_logic_vector(maxAddrBit downto 0);
opcode: std_logic_vector(7 downto 0);
sp: std_logic_vector(10 downto 2);
brk: std_logic;
ready: std_logic;
idim: std_logic;
stacka: std_logic_vector(wordSize-1 downto 0);
stackb: std_logic_vector(wordSize-1 downto 0);
valid: std_logic;
end record;
type zpu_dbg_in_type is record
step: std_logic;
freeze: std_logic;
inject: std_logic;
injectmode: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
component zpu_core_extreme is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
--cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_b_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
constant OpCode_NA : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6));
constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6));
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6));
constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6));
constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
constant OpCode_Size : integer := 8;
end zpupkg;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
package zpupkg is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := maxAddrBitBRAM;
constant ioBit : integer := maxAddrBitIncIO;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
type zpu_dbg_out_type is record
pc: std_logic_vector(maxAddrBit downto 0);
opcode: std_logic_vector(7 downto 0);
sp: std_logic_vector(10 downto 2);
brk: std_logic;
ready: std_logic;
idim: std_logic;
stacka: std_logic_vector(wordSize-1 downto 0);
stackb: std_logic_vector(wordSize-1 downto 0);
valid: std_logic;
end record;
type zpu_dbg_in_type is record
step: std_logic;
freeze: std_logic;
inject: std_logic;
injectmode: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
component zpu_core_extreme is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
--cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_b_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
constant OpCode_NA : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6));
constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6));
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6));
constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6));
constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
constant OpCode_Size : integer := 8;
end zpupkg;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
package zpupkg is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := maxAddrBitBRAM;
constant ioBit : integer := maxAddrBitIncIO;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
type zpu_dbg_out_type is record
pc: std_logic_vector(maxAddrBit downto 0);
opcode: std_logic_vector(7 downto 0);
sp: std_logic_vector(10 downto 2);
brk: std_logic;
ready: std_logic;
idim: std_logic;
stacka: std_logic_vector(wordSize-1 downto 0);
stackb: std_logic_vector(wordSize-1 downto 0);
valid: std_logic;
end record;
type zpu_dbg_in_type is record
step: std_logic;
freeze: std_logic;
inject: std_logic;
injectmode: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
component zpu_core_extreme is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
--cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_b_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
constant OpCode_NA : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6));
constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6));
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6));
constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6));
constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
constant OpCode_Size : integer := 8;
end zpupkg;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
package zpupkg is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := maxAddrBitBRAM;
constant ioBit : integer := maxAddrBitIncIO;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
type zpu_dbg_out_type is record
pc: std_logic_vector(maxAddrBit downto 0);
opcode: std_logic_vector(7 downto 0);
sp: std_logic_vector(10 downto 2);
brk: std_logic;
ready: std_logic;
idim: std_logic;
stacka: std_logic_vector(wordSize-1 downto 0);
stackb: std_logic_vector(wordSize-1 downto 0);
valid: std_logic;
end record;
type zpu_dbg_in_type is record
step: std_logic;
freeze: std_logic;
inject: std_logic;
injectmode: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
component zpu_core_extreme is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
--cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_b_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
constant OpCode_NA : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6));
constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6));
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6));
constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6));
constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
constant OpCode_Size : integer := 8;
end zpupkg;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
package zpupkg is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := maxAddrBitBRAM;
constant ioBit : integer := maxAddrBitIncIO;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
type zpu_dbg_out_type is record
pc: std_logic_vector(maxAddrBit downto 0);
opcode: std_logic_vector(7 downto 0);
sp: std_logic_vector(10 downto 2);
brk: std_logic;
ready: std_logic;
idim: std_logic;
stacka: std_logic_vector(wordSize-1 downto 0);
stackb: std_logic_vector(wordSize-1 downto 0);
valid: std_logic;
end record;
type zpu_dbg_in_type is record
step: std_logic;
freeze: std_logic;
inject: std_logic;
injectmode: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
component zpu_core_extreme is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
--cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_b_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
constant OpCode_NA : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6));
constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6));
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6));
constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6));
constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
constant OpCode_Size : integer := 8;
end zpupkg;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
package zpupkg is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := maxAddrBitBRAM;
constant ioBit : integer := maxAddrBitIncIO;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
type zpu_dbg_out_type is record
pc: std_logic_vector(maxAddrBit downto 0);
opcode: std_logic_vector(7 downto 0);
sp: std_logic_vector(10 downto 2);
brk: std_logic;
ready: std_logic;
idim: std_logic;
stacka: std_logic_vector(wordSize-1 downto 0);
stackb: std_logic_vector(wordSize-1 downto 0);
valid: std_logic;
end record;
type zpu_dbg_in_type is record
step: std_logic;
freeze: std_logic;
inject: std_logic;
injectmode: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
component zpu_core_extreme is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
--cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_b_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
constant OpCode_NA : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6));
constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6));
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6));
constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6));
constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
constant OpCode_Size : integer := 8;
end zpupkg;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
package zpupkg is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := maxAddrBitBRAM;
constant ioBit : integer := maxAddrBitIncIO;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
type zpu_dbg_out_type is record
pc: std_logic_vector(maxAddrBit downto 0);
opcode: std_logic_vector(7 downto 0);
sp: std_logic_vector(10 downto 2);
brk: std_logic;
ready: std_logic;
idim: std_logic;
stacka: std_logic_vector(wordSize-1 downto 0);
stackb: std_logic_vector(wordSize-1 downto 0);
valid: std_logic;
end record;
type zpu_dbg_in_type is record
step: std_logic;
freeze: std_logic;
inject: std_logic;
injectmode: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
component zpu_core_extreme is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
--cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_b_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
constant OpCode_NA : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6));
constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6));
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6));
constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6));
constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
constant OpCode_Size : integer := 8;
end zpupkg;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
package zpupkg is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := maxAddrBitBRAM;
constant ioBit : integer := maxAddrBitIncIO;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
type zpu_dbg_out_type is record
pc: std_logic_vector(maxAddrBit downto 0);
opcode: std_logic_vector(7 downto 0);
sp: std_logic_vector(10 downto 2);
brk: std_logic;
ready: std_logic;
idim: std_logic;
stacka: std_logic_vector(wordSize-1 downto 0);
stackb: std_logic_vector(wordSize-1 downto 0);
valid: std_logic;
end record;
type zpu_dbg_in_type is record
step: std_logic;
freeze: std_logic;
inject: std_logic;
injectmode: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
component zpu_core_extreme is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
--cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_b_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
constant OpCode_NA : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6));
constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6));
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6));
constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6));
constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
constant OpCode_Size : integer := 8;
end zpupkg;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
package zpupkg is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := maxAddrBitBRAM;
constant ioBit : integer := maxAddrBitIncIO;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
type zpu_dbg_out_type is record
pc: std_logic_vector(maxAddrBit downto 0);
opcode: std_logic_vector(7 downto 0);
sp: std_logic_vector(10 downto 2);
brk: std_logic;
ready: std_logic;
idim: std_logic;
stacka: std_logic_vector(wordSize-1 downto 0);
stackb: std_logic_vector(wordSize-1 downto 0);
valid: std_logic;
end record;
type zpu_dbg_in_type is record
step: std_logic;
freeze: std_logic;
inject: std_logic;
injectmode: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
component zpu_core_extreme is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
--cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_b_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
constant OpCode_NA : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6));
constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6));
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6));
constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6));
constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
constant OpCode_Size : integer := 8;
end zpupkg;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
package zpupkg is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := maxAddrBitBRAM;
constant ioBit : integer := maxAddrBitIncIO;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
type zpu_dbg_out_type is record
pc: std_logic_vector(maxAddrBit downto 0);
opcode: std_logic_vector(7 downto 0);
sp: std_logic_vector(10 downto 2);
brk: std_logic;
ready: std_logic;
idim: std_logic;
stacka: std_logic_vector(wordSize-1 downto 0);
stackb: std_logic_vector(wordSize-1 downto 0);
valid: std_logic;
end record;
type zpu_dbg_in_type is record
step: std_logic;
freeze: std_logic;
inject: std_logic;
injectmode: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
component zpu_core_extreme is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
--cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_b_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
constant OpCode_NA : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6));
constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6));
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6));
constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6));
constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
constant OpCode_Size : integer := 8;
end zpupkg;
|
-- ZPU
--
-- Copyright 2004-2008 oharboe - Øyvind Harboe - [email protected]
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library board;
use board.zpu_config.all;
package zpupkg is
-- This bit is set for read/writes to IO
-- FIX!!! eventually this should be set to wordSize-1 so as to
-- to make the address of IO independent of amount of memory
-- reserved for CPU. Requires trivial tweaks in toolchain/runtime
-- libraries.
constant byteBits : integer := wordPower-3; -- # of bits in a word that addresses bytes
constant maxAddrBit : integer := maxAddrBitBRAM;
constant ioBit : integer := maxAddrBitIncIO;
constant wordSize : integer := 2**wordPower;
constant wordBytes : integer := wordSize/8;
constant minAddrBit : integer := byteBits;
-- configurable internal stack size. Probably going to be 16 after toolchain is done
constant stack_bits : integer := 5;
constant stack_size : integer := 2**stack_bits;
type zpu_dbg_out_type is record
pc: std_logic_vector(maxAddrBit downto 0);
opcode: std_logic_vector(7 downto 0);
sp: std_logic_vector(10 downto 2);
brk: std_logic;
ready: std_logic;
idim: std_logic;
stacka: std_logic_vector(wordSize-1 downto 0);
stackb: std_logic_vector(wordSize-1 downto 0);
valid: std_logic;
end record;
type zpu_dbg_in_type is record
step: std_logic;
freeze: std_logic;
inject: std_logic;
injectmode: std_logic;
flush: std_logic;
opcode: std_logic_vector(7 downto 0);
end record;
component trace is
port(
clk : in std_logic;
begin_inst : in std_logic;
pc : in std_logic_vector(maxAddrBitIncIO downto 0);
opcode : in std_logic_vector(7 downto 0);
sp : in std_logic_vector(maxAddrBitIncIO downto minAddrBit);
memA : in std_logic_vector(wordSize-1 downto 0);
memB : in std_logic_vector(wordSize-1 downto 0);
busy : in std_logic;
intSp : in std_logic_vector(stack_bits-1 downto 0)
);
end component;
component zpu_core_extreme_icache is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_sel_o: out std_logic_vector(3 downto 0);
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic_vector(3 downto 0);
stack_b_writeenable: out std_logic_vector(3 downto 0);
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits-1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
component zpu_core_extreme is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master wishbone interface
wb_ack_i: in std_logic;
wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
wb_dat_o: out std_logic_vector(wordSize-1 downto 0);
wb_adr_o: out std_logic_vector(maxAddrBitIncIO downto 0);
wb_cyc_o: out std_logic;
wb_stb_o: out std_logic;
wb_we_o: out std_logic;
wb_inta_i: in std_logic;
poppc_inst: out std_logic;
--cache_flush: in std_logic;
break: out std_logic;
stack_a_read: in std_logic_vector(wordSize-1 downto 0);
stack_b_read: in std_logic_vector(wordSize-1 downto 0);
stack_a_write: out std_logic_vector(wordSize-1 downto 0);
stack_b_write: out std_logic_vector(wordSize-1 downto 0);
stack_a_writeenable: out std_logic;
stack_b_writeenable: out std_logic;
stack_a_enable: out std_logic;
stack_b_enable: out std_logic;
stack_a_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_b_addr: out std_logic_vector(stackSize_bits+1 downto 2);
stack_clk: out std_logic;
-- ROM wb interface
rom_wb_ack_i: in std_logic;
rom_wb_dat_i: in std_logic_vector(wordSize-1 downto 0);
rom_wb_adr_o: out std_logic_vector(maxAddrBit downto 0);
rom_wb_cyc_o: out std_logic;
rom_wb_stb_o: out std_logic;
rom_wb_cti_o: out std_logic_vector(2 downto 0);
rom_wb_stall_i: in std_logic;
-- Debug interface
dbg_out: out zpu_dbg_out_type;
dbg_in: in zpu_dbg_in_type
);
end component;
-- opcode decode constants
constant OpCode_Im : std_logic_vector(7 downto 7) := "1";
constant OpCode_StoreSP : std_logic_vector(7 downto 5) := "010";
constant OpCode_LoadSP : std_logic_vector(7 downto 5) := "011";
constant OpCode_Emulate : std_logic_vector(7 downto 5) := "001";
constant OpCode_AddSP : std_logic_vector(7 downto 4) := "0001";
constant OpCode_Short : std_logic_vector(7 downto 4) := "0000";
constant OpCode_Break : std_logic_vector(3 downto 0) := "0000";
constant OpCode_NA4 : std_logic_vector(3 downto 0) := "0001";
constant OpCode_PushSP : std_logic_vector(3 downto 0) := "0010";
constant OpCode_NA3 : std_logic_vector(3 downto 0) := "0011";
constant OpCode_PopPC : std_logic_vector(3 downto 0) := "0100";
constant OpCode_Add : std_logic_vector(3 downto 0) := "0101";
constant OpCode_And : std_logic_vector(3 downto 0) := "0110";
constant OpCode_Or : std_logic_vector(3 downto 0) := "0111";
constant OpCode_Load : std_logic_vector(3 downto 0) := "1000";
constant OpCode_Not : std_logic_vector(3 downto 0) := "1001";
constant OpCode_Flip : std_logic_vector(3 downto 0) := "1010";
constant OpCode_Nop : std_logic_vector(3 downto 0) := "1011";
constant OpCode_Store : std_logic_vector(3 downto 0) := "1100";
constant OpCode_PopSP : std_logic_vector(3 downto 0) := "1101";
constant OpCode_NA2 : std_logic_vector(3 downto 0) := "1110";
constant OpCode_NA : std_logic_vector(3 downto 0) := "1111";
constant OpCode_Loadh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(34, 6));
constant OpCode_Storeh : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(35, 6));
constant OpCode_Lessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(36, 6));
constant OpCode_Lessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(37, 6));
constant OpCode_Ulessthan : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(38, 6));
constant OpCode_Ulessthanorequal : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(39, 6));
constant OpCode_Swap : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(40, 6));
constant OpCode_Mult : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(41, 6));
constant OpCode_Lshiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(42, 6));
constant OpCode_Ashiftleft : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(43, 6));
constant OpCode_Ashiftright : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(44, 6));
constant OpCode_Call : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(45, 6));
constant OpCode_Eq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(46, 6));
constant OpCode_Neq : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(47, 6));
constant OpCode_Neg : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(48, 6));
constant OpCode_Sub : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(49, 6));
constant OpCode_Xor : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(50, 6));
constant OpCode_Loadb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(51, 6));
constant OpCode_Storeb : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(52, 6));
constant OpCode_Eqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(55, 6));
constant OpCode_Neqbranch : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(56, 6));
constant OpCode_Poppcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(57, 6));
constant OpCode_Pushspadd : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(61, 6));
constant OpCode_Mult16x16 : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(62, 6));
constant OpCode_Callpcrel : std_logic_vector(5 downto 0) := std_logic_vector(to_unsigned(63, 6));
constant OpCode_Size : integer := 8;
end zpupkg;
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.35e-06,
W => Wdiff_0,
Wdiff_0init => 4.25e-06,
scope => private
)
port map(
D => net3,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.35e-06,
W => Wdiff_0,
Wdiff_0init => 4.25e-06,
scope => private
)
port map(
D => net2,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 2.85e-06,
W => W_0,
W_0init => 2.95e-06
)
port map(
D => net5,
G => vbias4,
S => gnd
);
subnet0_subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 8.5e-07,
W => Wcm_2,
Wcm_2init => 5.5e-07,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net2,
G => net2,
S => vdd
);
subnet0_subnet0_subnet1_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 8.5e-07,
W => Wcmout_2,
Wcmout_2init => 6.095e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net4,
G => net2,
S => vdd
);
subnet0_subnet0_subnet1_c1 : entity cap(behave)
generic map(
C => Ccurmir_2,
scope => private,
symmetry_scope => sym_5
)
port map(
P => net4,
N => net2
);
subnet0_subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 8.5e-07,
W => Wcm_2,
Wcm_2init => 5.5e-07,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net3,
G => net3,
S => vdd
);
subnet0_subnet0_subnet2_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 8.5e-07,
W => Wcmout_2,
Wcmout_2init => 6.095e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => out1,
G => net3,
S => vdd
);
subnet0_subnet0_subnet2_c1 : entity cap(behave)
generic map(
C => Ccurmir_2,
scope => private,
symmetry_scope => sym_5
)
port map(
P => out1,
N => net3
);
subnet0_subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 8.45e-06,
W => Wcm_1,
Wcm_1init => 1.135e-05,
scope => private
)
port map(
D => net4,
G => net4,
S => gnd
);
subnet0_subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 8.45e-06,
W => Wcmcout_1,
Wcmcout_1init => 1.15e-05,
scope => private
)
port map(
D => out1,
G => net4,
S => gnd
);
subnet0_subnet0_subnet3_c1 : entity cap(behave)
generic map(
C => Ccurmir_1,
scope => private
)
port map(
P => out1,
N => net4
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 2.85e-06,
W => (pfak)*(WBias),
WBiasinit => 2.6e-05
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 2.85e-06,
W => (pfak)*(WBias),
WBiasinit => 2.6e-05
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 2.85e-06,
W => WBias,
WBiasinit => 2.6e-05
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 2.85e-06,
W => WBias,
WBiasinit => 2.6e-05
)
port map(
D => vbias2,
G => vbias3,
S => net6
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 2.85e-06,
W => WBias,
WBiasinit => 2.6e-05
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 2.85e-06,
W => WBias,
WBiasinit => 2.6e-05
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net7,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net7,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net7,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
|
--
-- Copyright (C) 2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mem_ctrl_pkg.all;
entity mem_ctrl is
generic (
INIT_COUNT : unsigned(12 downto 0) := "1" & x"2C0"; -- cycles to wait during init
REFRESH_DELAY : unsigned(12 downto 0) := "0" & x"300"; -- gap between refresh cycles
REFRESH_LENGTH : unsigned(12 downto 0) := "0" & x"002" -- length of a refresh cycle
);
port(
clk_in : in std_logic;
reset_in : in std_logic;
-- Client interface
mcAutoMode_in : in std_logic;
mcCmd_in : in MCCmdType;
mcAddr_in : in std_logic_vector(22 downto 0);
mcData_in : in std_logic_vector(15 downto 0);
mcData_out : out std_logic_vector(15 downto 0);
mcRDV_out : out std_logic;
mcReady_out : out std_logic;
-- SDRAM interface
ramCmd_out : out std_logic_vector(2 downto 0);
ramBank_out : out std_logic_vector(1 downto 0);
ramAddr_out : out std_logic_vector(11 downto 0);
ramData_io : inout std_logic_vector(15 downto 0);
ramLDQM_out : out std_logic;
ramUDQM_out : out std_logic
);
end entity;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTFTOL.VHD ***
--*** ***
--*** Function: Cast IEEE754 Single Format to ***
--*** Long ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castftol IS
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_castftol;
ARCHITECTURE rtl OF hcc_castftol IS
signal xvector : STD_LOGIC_VECTOR (42 DOWNTO 1);
signal xvectorsat, xvectorzip : STD_LOGIC;
component hcc_castftox
GENERIC (
target : integer := 1; -- 0 (internal), 1 (multiplier), 2 (divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_castxtol
GENERIC (
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aazip, aasat : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
BEGIN
corein: hcc_castftox
GENERIC MAP (target=>0,roundconvert=>roundconvert,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>xvector,ccsat=>xvectorsat,cczip=>xvectorzip);
coreout: hcc_castxtol
GENERIC MAP (normspeed=>normspeed,mantissa=>32)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xvector,aasat=>xvectorsat,aazip=>xvectorzip,
cc=>cc);
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTFTOL.VHD ***
--*** ***
--*** Function: Cast IEEE754 Single Format to ***
--*** Long ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castftol IS
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_castftol;
ARCHITECTURE rtl OF hcc_castftol IS
signal xvector : STD_LOGIC_VECTOR (42 DOWNTO 1);
signal xvectorsat, xvectorzip : STD_LOGIC;
component hcc_castftox
GENERIC (
target : integer := 1; -- 0 (internal), 1 (multiplier), 2 (divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_castxtol
GENERIC (
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aazip, aasat : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
BEGIN
corein: hcc_castftox
GENERIC MAP (target=>0,roundconvert=>roundconvert,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>xvector,ccsat=>xvectorsat,cczip=>xvectorzip);
coreout: hcc_castxtol
GENERIC MAP (normspeed=>normspeed,mantissa=>32)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xvector,aasat=>xvectorsat,aazip=>xvectorzip,
cc=>cc);
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTFTOL.VHD ***
--*** ***
--*** Function: Cast IEEE754 Single Format to ***
--*** Long ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castftol IS
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_castftol;
ARCHITECTURE rtl OF hcc_castftol IS
signal xvector : STD_LOGIC_VECTOR (42 DOWNTO 1);
signal xvectorsat, xvectorzip : STD_LOGIC;
component hcc_castftox
GENERIC (
target : integer := 1; -- 0 (internal), 1 (multiplier), 2 (divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_castxtol
GENERIC (
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aazip, aasat : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
BEGIN
corein: hcc_castftox
GENERIC MAP (target=>0,roundconvert=>roundconvert,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>xvector,ccsat=>xvectorsat,cczip=>xvectorzip);
coreout: hcc_castxtol
GENERIC MAP (normspeed=>normspeed,mantissa=>32)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xvector,aasat=>xvectorsat,aazip=>xvectorzip,
cc=>cc);
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTFTOL.VHD ***
--*** ***
--*** Function: Cast IEEE754 Single Format to ***
--*** Long ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castftol IS
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_castftol;
ARCHITECTURE rtl OF hcc_castftol IS
signal xvector : STD_LOGIC_VECTOR (42 DOWNTO 1);
signal xvectorsat, xvectorzip : STD_LOGIC;
component hcc_castftox
GENERIC (
target : integer := 1; -- 0 (internal), 1 (multiplier), 2 (divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_castxtol
GENERIC (
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aazip, aasat : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
BEGIN
corein: hcc_castftox
GENERIC MAP (target=>0,roundconvert=>roundconvert,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>xvector,ccsat=>xvectorsat,cczip=>xvectorzip);
coreout: hcc_castxtol
GENERIC MAP (normspeed=>normspeed,mantissa=>32)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xvector,aasat=>xvectorsat,aazip=>xvectorzip,
cc=>cc);
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTFTOL.VHD ***
--*** ***
--*** Function: Cast IEEE754 Single Format to ***
--*** Long ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castftol IS
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_castftol;
ARCHITECTURE rtl OF hcc_castftol IS
signal xvector : STD_LOGIC_VECTOR (42 DOWNTO 1);
signal xvectorsat, xvectorzip : STD_LOGIC;
component hcc_castftox
GENERIC (
target : integer := 1; -- 0 (internal), 1 (multiplier), 2 (divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_castxtol
GENERIC (
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aazip, aasat : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
BEGIN
corein: hcc_castftox
GENERIC MAP (target=>0,roundconvert=>roundconvert,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>xvector,ccsat=>xvectorsat,cczip=>xvectorzip);
coreout: hcc_castxtol
GENERIC MAP (normspeed=>normspeed,mantissa=>32)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xvector,aasat=>xvectorsat,aazip=>xvectorzip,
cc=>cc);
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTFTOL.VHD ***
--*** ***
--*** Function: Cast IEEE754 Single Format to ***
--*** Long ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castftol IS
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_castftol;
ARCHITECTURE rtl OF hcc_castftol IS
signal xvector : STD_LOGIC_VECTOR (42 DOWNTO 1);
signal xvectorsat, xvectorzip : STD_LOGIC;
component hcc_castftox
GENERIC (
target : integer := 1; -- 0 (internal), 1 (multiplier), 2 (divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_castxtol
GENERIC (
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aazip, aasat : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
BEGIN
corein: hcc_castftox
GENERIC MAP (target=>0,roundconvert=>roundconvert,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>xvector,ccsat=>xvectorsat,cczip=>xvectorzip);
coreout: hcc_castxtol
GENERIC MAP (normspeed=>normspeed,mantissa=>32)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xvector,aasat=>xvectorsat,aazip=>xvectorzip,
cc=>cc);
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTFTOL.VHD ***
--*** ***
--*** Function: Cast IEEE754 Single Format to ***
--*** Long ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castftol IS
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_castftol;
ARCHITECTURE rtl OF hcc_castftol IS
signal xvector : STD_LOGIC_VECTOR (42 DOWNTO 1);
signal xvectorsat, xvectorzip : STD_LOGIC;
component hcc_castftox
GENERIC (
target : integer := 1; -- 0 (internal), 1 (multiplier), 2 (divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_castxtol
GENERIC (
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aazip, aasat : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
BEGIN
corein: hcc_castftox
GENERIC MAP (target=>0,roundconvert=>roundconvert,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>xvector,ccsat=>xvectorsat,cczip=>xvectorzip);
coreout: hcc_castxtol
GENERIC MAP (normspeed=>normspeed,mantissa=>32)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xvector,aasat=>xvectorsat,aazip=>xvectorzip,
cc=>cc);
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTFTOL.VHD ***
--*** ***
--*** Function: Cast IEEE754 Single Format to ***
--*** Long ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castftol IS
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_castftol;
ARCHITECTURE rtl OF hcc_castftol IS
signal xvector : STD_LOGIC_VECTOR (42 DOWNTO 1);
signal xvectorsat, xvectorzip : STD_LOGIC;
component hcc_castftox
GENERIC (
target : integer := 1; -- 0 (internal), 1 (multiplier), 2 (divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_castxtol
GENERIC (
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aazip, aasat : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
BEGIN
corein: hcc_castftox
GENERIC MAP (target=>0,roundconvert=>roundconvert,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>xvector,ccsat=>xvectorsat,cczip=>xvectorzip);
coreout: hcc_castxtol
GENERIC MAP (normspeed=>normspeed,mantissa=>32)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xvector,aasat=>xvectorsat,aazip=>xvectorzip,
cc=>cc);
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTFTOL.VHD ***
--*** ***
--*** Function: Cast IEEE754 Single Format to ***
--*** Long ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castftol IS
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_castftol;
ARCHITECTURE rtl OF hcc_castftol IS
signal xvector : STD_LOGIC_VECTOR (42 DOWNTO 1);
signal xvectorsat, xvectorzip : STD_LOGIC;
component hcc_castftox
GENERIC (
target : integer := 1; -- 0 (internal), 1 (multiplier), 2 (divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_castxtol
GENERIC (
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aazip, aasat : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
BEGIN
corein: hcc_castftox
GENERIC MAP (target=>0,roundconvert=>roundconvert,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>xvector,ccsat=>xvectorsat,cczip=>xvectorzip);
coreout: hcc_castxtol
GENERIC MAP (normspeed=>normspeed,mantissa=>32)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xvector,aasat=>xvectorsat,aazip=>xvectorzip,
cc=>cc);
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTFTOL.VHD ***
--*** ***
--*** Function: Cast IEEE754 Single Format to ***
--*** Long ***
--*** ***
--*** 13/12/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_castftol IS
GENERIC (
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
END hcc_castftol;
ARCHITECTURE rtl OF hcc_castftol IS
signal xvector : STD_LOGIC_VECTOR (42 DOWNTO 1);
signal xvectorsat, xvectorzip : STD_LOGIC;
component hcc_castftox
GENERIC (
target : integer := 1; -- 0 (internal), 1 (multiplier), 2 (divider)
roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1'
mantissa : positive := 32;
outputpipe : integer := 1 -- 0 no pipe, 1 output always registered
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (32 DOWNTO 1);
cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
ccsat, cczip : OUT STD_LOGIC
);
end component;
component hcc_castxtol
GENERIC (
normspeed : positive := 2; -- 1,2 pipes for conversion
mantissa : integer := 36
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1);
aazip, aasat : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1)
);
end component;
BEGIN
corein: hcc_castftox
GENERIC MAP (target=>0,roundconvert=>roundconvert,mantissa=>32,outputpipe=>1)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,
cc=>xvector,ccsat=>xvectorsat,cczip=>xvectorzip);
coreout: hcc_castxtol
GENERIC MAP (normspeed=>normspeed,mantissa=>32)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>xvector,aasat=>xvectorsat,aazip=>xvectorzip,
cc=>cc);
END rtl;
|
--------------------------------------------------------------------------
-- Logical
--------------------------------------------------------------------------
-- 0,00,000 NOP
-- 0,00,001 AND
-- 0,00,010 OR
-- 0,00,011 XOR
-- 0,00,100 NOR
--------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.ALL;
entity logic is
Port (
Control : in STD_LOGIC_VECTOR ( 2 downto 0);
Operand1 : in STD_LOGIC_VECTOR (31 downto 0);
Operand2 : in STD_LOGIC_VECTOR (31 downto 0);
Result1 : out STD_LOGIC_VECTOR (31 downto 0);
Result2 : out STD_LOGIC_VECTOR (31 downto 0);
Debug : out STD_LOGIC_VECTOR (27 downto 0));
end logic;
architecture beh_logic of logic is
begin
process (Control, Operand1, Operand2)
variable temp : STD_LOGIC_VECTOR (31 downto 0);
begin
case Control is
when "000" => -- NOP
Result1 <= Operand1;
Result2 <= Operand2;
Debug <= X"0000000";
when "001" => -- AND
Result1 <= Operand1 and Operand2;
Result2 <= X"00000000";
Debug <= X"0000000";
when "010" => -- OR
Result1 <= Operand1 or Operand2;
Result2 <= X"00000000";
Debug <= X"0000000";
when "011" => -- XOR
Result1 <= Operand1 xor Operand2;
Result2 <= X"00000000";
Debug <= X"0000000";
when "100" => -- NOR
Result1 <= Operand1 nor Operand2;
Result2 <= X"00000000";
Debug <= X"0000000";
when others =>
Result1 <= X"FFFFFFFF";
Result2 <= X"FFFFFFFF";
Debug <= X"FFFFFFF";
end case;
end process;
end beh_logic;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package prog_mem_content is
-- content of p_0 ----------------------------------------------------------------------------------
constant p0_00 : BIT_VECTOR := X"C002E0E0E6A0BFCDE0D4BE1FC01BC01DC01FC021C023C025C027C029C02BC012";
constant p0_01 : BIT_VECTOR := X"0FE82FE201C0C007E0E081AA306393DFCFD1D1EE07B1921DE0B1E01107B1920D";
constant p0_02 : BIT_VECTOR := X"93DF950891DFE090C002E680E0F023229611539024110293E03A81BDF7B1912C";
constant p0_03 : BIT_VECTOR := X"B7CDE783B7FED000D000912CE0B02322963153A0241102A3E03A2DE080023062";
constant p0_04 : BIT_VECTOR := X"E04A2DE08002F00901FC91CFD20CE78ABF8DBF9EB60FB79ED513832483B3839A";
constant p0_05 : BIT_VECTOR := X"BF8DBF9EB60FB79EB548E08ABD87B568E0889530273323339631532024110224";
constant p0_06 : BIT_VECTOR := X"D1C0E982BF8DBF9EB60FB79ED4C78740835683648333938E9612B7ADE884B7FE";
constant p0_07 : BIT_VECTOR := X"C00924FF91FC961423229631531024110213E03A971391EDC0663064931F92FF";
constant p0_08 : BIT_VECTOR := X"D531D4DF23229631530024110203E03A971791EDF7A181200EF82EF924110243";
constant p0_09 : BIT_VECTOR := X"821582139711939CB7BEE0909631B7EDBE0F94F8970AB78DD529D52BD4D9D52F";
constant p0_0A : BIT_VECTOR := X"971391EDC0583064931F92FF90FF911FE090C003BE0F94F8960AB78D86118217";
constant p0_0B : BIT_VECTOR := X"F7B181200F082F0201C0C007E00091FC9614232296310EF2ED4001C02D4FE03A";
constant p0_0C : BIT_VECTOR := X"D0002F18E090D4B7D465D4BBD4BDD46B23229631531024110213E03A971791ED";
constant p0_0D : BIT_VECTOR := X"931F92FF92DF90FF911FE090C003900F900F82139711939CB7BEE0909631B7ED";
constant p0_0E : BIT_VECTOR := X"F35032C083005FEAF049300D0511D0B0F3D13F0F018CE0D0C002E0C02EE993DF";
constant p0_0F : BIT_VECTOR := X"01FC939C4F9E01C9238832804F3F921195702777E050E03001D92D9E82185FCA";
constant p0_10 : BIT_VECTOR := X"92DF92BF950890EF910F91CF2F844FFE01F9075796125F4F2388F01981805F2F";
constant p0_11 : BIT_VECTOR := X"2ED52EC51CF194082EB62EA6D396E090D06BE881BE0F94F89760B7CD93DF92FF";
constant p0_12 : BIT_VECTOR := X"C01134893583358281FAF754900FD34982D2B7ED2F18E068900FD35582B2B7ED";
constant p0_13 : BIT_VECTOR := X"2F61CFC22F61CFC6F641F021F0518181DDEE01C7DDC401C7DE2F01C7F6E1F039";
constant p0_14 : BIT_VECTOR := X"95089380939001C92F28C003EF2FFC009508E090CFFDB400DFFAF4112F18CFBE";
constant p0_15 : BIT_VECTOR := X"971191ED950891DF019CE08A238891F091E09509C00CEF2F2B899190918093DF";
constant p0_16 : BIT_VECTOR := X"9508932E96155F2F1FF3F44C1728919C9616913C9614973091FC96129509F019";
constant p0_17 : BIT_VECTOR := X"F04C070A16E881AE818C810A80E805710551F121859E01E993DF931F92FF92DF";
constant p0_18 : BIT_VECTOR := X"926F924F922F90CF90EF910F91CFF37C070A16E881AE818C1D011CE1DFB801C6";
constant p0_19 : BIT_VECTOR := X"920DE181EFE401DE0169012CBE0F94F897E1B7CD93DF930F92EF92CF92AF928F";
constant p0_1A : BIT_VECTOR := X"01B71E9D2C91E1922422017A2C31E0210B061AE424FFC00BF46904C116A8F7E1";
constant p0_1B : BIT_VECTOR := X"9381E28D2823051104F1018D01DAD36B019501C8938D81800FE60FECE0E101A6";
constant p0_1C : BIT_VECTOR := X"E070E050F4218990E070E05083B3839101F3E0A01B8E01CD200001DF01FE01D4";
constant p0_1D : BIT_VECTOR := X"94F896E101932F76FD57895001F3051F4010DF0E01D8C0040EEC2EE801840193";
constant p0_1E : BIT_VECTOR := X"92BF929F927F925F923F9508903F905F907F909F90BF90DF90FF911F91CFBE0F";
constant p0_1F : BIT_VECTOR := X"861F01C432651C5194082C31E0E1017ABFCDBFDEB60FB7DE93CF931F92FF92DF";
constant p0_20 : BIT_VECTOR := X"1461F0085380916C1CB194082E67C003246624CC87AB8789E0A0EF8FE2808A19";
constant p0_21 : BIT_VECTOR := X"1CB194081F4A0F2895A027AA9590279901ACD290E040E02A01CAE050E030F149";
constant p0_22 : BIT_VECTOR := X"9590279901ACD264E040E02A01CAE050E030876D3360875C873AF30853808110";
constant p0_23 : BIT_VECTOR := X"27335481CF9908A1862E8758833EF3085380911C1CB194081F4A0F2895A027AA";
constant p0_24 : BIT_VECTOR := X"C0BA0591C026F009F13132850591CF800591F4BC3685059101C99680F4189530";
constant p0_25 : BIT_VECTOR := X"E265CF572EC6C02FF0093788F4093783C0C80591F42C3781F4093780C0D40591";
constant p0_26 : BIT_VECTOR := X"2F76FD57915C01D70CCE2EC4C00C816281401CDF2CD1E054346428CD8A28C0B6";
constant p0_27 : BIT_VECTOR := X"F7E9900D911C01D7E030E01001C4816281401CDF2CD1E03401760172E020E00A";
constant p0_28 : BIT_VECTOR := X"01D801C49161C0050192E070E050F4218999E070E05083BC839AE0B00B919701";
constant p0_29 : BIT_VECTOR := X"1B8001CD200001D80EEEE0E205B197001DA187BC879A09B1970185AB85892388";
constant p0_2A : BIT_VECTOR := X"F491F41CF069C01EDD6401F74F1F0187DD9001C495602766894883AB8389E0A0";
constant p0_2B : BIT_VECTOR := X"CE7B236601D51CA1CE9D1CA1DD48C00101C4E06DC00701C4E067C0063762366E";
constant p0_2C : BIT_VECTOR := X"9728B7CD93DF902F904F906F908F90AF90CF90EF910F91DFBFCDBFDEB60FE090";
constant p0_2D : BIT_VECTOR := X"019C01A9856D01CE8618821E821C839A5F21C012E020970091909180BE0F94F8";
constant p0_2E : BIT_VECTOR := X"B5832F322F542B4A2B28E0A0B5842F322F54E040B525950891CFBE0F94F89628";
constant p0_2F : BIT_VECTOR := X"BD89B589BF81B781708C950801B92B4A2B28E0A0B5822F322F542B4A2B28E0A0";
constant p0_30 : BIT_VECTOR := X"9601E090BD89B58905919601E090BD89B589E081FC02F7D9308A0000E0807F87";
constant p0_31 : BIT_VECTOR := X"E0807F8BF7D9308A0000E0806088BD89B589E08005919601E090BD89B5890591";
constant p0_32 : BIT_VECTOR := X"0000000000006088C002B589FF372F38F7D9308A0000E0807F87F7D9308A0000";
constant p0_33 : BIT_VECTOR := X"0000E0807F8BBD89B5890F3330280000000000006084F7D9308A0000E0807F8B";
constant p0_34 : BIT_VECTOR := X"E090BD89B589E0307081952A9596E090F7D1302A5F2FE030BD89B589F7D9308A";
constant p0_35 : BIT_VECTOR := X"01D09508F6F95F3F05919601E090BD89B5897081954A9596E090B78005919601";
constant p0_36 : BIT_VECTOR := X"1BAAE2A1241101BD1DE19F631DE19F720DF00DF00DF00DF01DF19F640DE001F0";
constant p0_37 : BIT_VECTOR := X"94F801CF01AC95909570F7691F991F770BF50BB3F02007E417A21FEE1FAA01FD";
constant p0_38 : BIT_VECTOR := X"250067693A72000A20646425642564643A72000A3D6465757620646172724B4F";
constant p0_39 : BIT_VECTOR := X"316C2031646172720A643A645200617672642031762064643A72000A3D646425";
constant p0_3A : BIT_VECTOR := X"FFFFFFFFFFFFFFFFFFFFFFFF000044433938353431303E0A203E213841006464";
constant p0_3B : BIT_VECTOR := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
constant p0_3C : BIT_VECTOR := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
constant p0_3D : BIT_VECTOR := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
constant p0_3E : BIT_VECTOR := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
constant p0_3F : BIT_VECTOR := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
-- content of p_1 ----------------------------------------------------------------------------------
constant p1_00 : BIT_VECTOR := X"9005E0FEE0B0E011BFDEE5CF2411C01CC01EC020C022C024C026C028C02AC02C";
constant p1_01 : BIT_VECTOR := X"961153E0241102E3E03A81BBF51901EC93CFC6D0F7E132A8C001E0A6F7D930A6";
constant p1_02 : BIT_VECTOR := X"01FC93CF91CFD245E683E090A390F7B1912C0F982F9201C0C007E09081AC2322";
constant p1_03 : BIT_VECTOR := X"B7DEE0909631B7EDD00097909690F7B181200FA82FA201C0C007E0A081F3F571";
constant p1_04 : BIT_VECTOR := X"C007E02081F3C0423062950891DFE090C003BE0F94F89606B78D821583A28389";
constant p1_05 : BIT_VECTOR := X"B7EDBE0F94F8970AB78DBD87B558E089BD87BD26FD27F7B181300F282F2301C0";
constant p1_06 : BIT_VECTOR := X"9508E0909508BE0F94F8960AB78D86118217821583229711939CB7BEE0909631";
constant p1_07 : BIT_VECTOR := X"2D4FE03A971591EDF7B181200F182F1201C0C007E01091FC9612F00901DC930F";
constant p1_08 : BIT_VECTOR := X"2D8F2F81F7B181200F082F0201C0C007E00091FC9616232296310EF2ED9001C0";
constant p1_09 : BIT_VECTOR := X"831682F48312938E9612B7ADE98DB7FEBF8DBF9EB60FB79ED5062F802F81D50C";
constant p1_0A : BIT_VECTOR := X"24FF91FC9612F00901DC930F9508910FD14FEA8ABF8DBF9EB60FB79ED4568700";
constant p1_0B : BIT_VECTOR := X"961623229631530024110203E03A971591EDF7A181200EF82EF424110243C009";
constant p1_0C : BIT_VECTOR := X"D000D490D4FCE0802F81D4982F802D8FF7B181200F182F1201C0C007E01091FC";
constant p1_0D : BIT_VECTOR := X"93CF930F92EF9508910FD0E9EC8F900F900FD3EC8312938E9612B7ADEC85B7FE";
constant p1_0E : BIT_VECTOR := X"CFE705D196214FFE01FE0511F061300A2F800718EF8FD0C5E1CFE0D02ED62EF8";
constant p1_0F : BIT_VECTOR := X"C002938E96115F8AF0D1F3D181805F2FC01BFD672D6DE040E020019C2D8F4FDE";
constant p1_10 : BIT_VECTOR := X"92EF92CF92AF90DF90FF911F91DFCFE15FEAF42417464F5FF7C1963132804F3F";
constant p1_11 : BIT_VECTOR := X"D000E050EE5F1CE1017EE060EE6BD06DEE85E092BFCDBFDEB60FB7DE93CF931F";
constant p1_12 : BIT_VECTOR := X"3587F709F41CF051818081E91611900F82C1B7FED000DF7001C7900F82A1B7FE";
constant p1_13 : BIT_VECTOR := X"DED401C7DE6401C7D37D348935873582CFCF2F61CFD32F61CFD72F61C0083588";
constant p1_14 : BIT_VECTOR := X"93CF012601279508E030B581EF3FC003B400911FE080FC03BD11E08D308A931F";
constant p1_15 : BIT_VECTOR := X"973091FC01DC91CF01C99509F7B90127012681889621EF3FF4290127012601EC";
constant p1_16 : BIT_VECTOR := X"92CF9714933C4F3F83600FE207399717918D9715912DF0A1971391ED95082F86";
constant p1_17 : BIT_VECTOR := X"C011071B06F981BF819D811B80F9F0F9056115412B89858D016C93CF930F92EF";
constant p1_18 : BIT_VECTOR := X"927F925F923F950890DF90FF911F91DF071B06F981BF819D1D111CF19408856C";
constant p1_19 : BIT_VECTOR := X"50819001E0F0961101370158BFCDBFDEB60FB7DE93CF931F92FF92DF92BF929F";
constant p1_1A : BIT_VECTOR := X"019501C80E8C2E892433018BC0042E220B170AF5018724EEFF7704D104B1E08A";
constant p1_1B : BIT_VECTOR := X"014F01F4F021F719050114E1017C01C901A601B7014D01D41FF71FFDE0F0D37A";
constant p1_1C : BIT_VECTOR := X"01C2E060E0412B898587E060E04083A28380E0B00B9F9701F7E9900D9672921C";
constant p1_1D : BIT_VECTOR := X"BFDEB60FDF2301C2956027668547F7B8150E5001916C01C21EFD2CF1E182DF3D";
constant p1_1E : BIT_VECTOR := X"92CF92AF928F926F924F922F902F904F906F908F90AF90CF90EF910F91DFBFCD";
constant p1_1F : BIT_VECTOR := X"861EC0C1F011C1801C41012E2E2E015B014CBE0F94F89761B7CD93DF930F92EF";
constant p1_20 : BIT_VECTOR := X"0471C05D308A2F8601D51CA12C71E071247724DD87BC879AE0B0E79F878D8A18";
constant p1_21 : BIT_VECTOR := X"01F51CA11F5B1F392FBAFD9797C0FD872F81019BE050E03001B9C019E040E020";
constant p1_22 : BIT_VECTOR := X"97C0FD872F81019BE050E03001B9C019E040E020F409C02D874B8729308A2F81";
constant p1_23 : BIT_VECTOR := X"FD272F262F8608B19408863F834F832D308A2F8101D51CA11F5B1F392FBAFD97";
constant p1_24 : BIT_VECTOR := X"3683F409358CC0DD978D0591F43C328FF409328E0591F1D13684C00101C9318A";
constant p1_25 : BIT_VECTOR := X"DDFB01C42CD1E061C0BF0591C0440591C009F009368C0591C0400591C0ACF009";
constant p1_26 : BIT_VECTOR := X"01C495602766914D1CDF2CD1E0428173815101F70CCE2EC5F459F411CF508A39";
constant p1_27 : BIT_VECTOR := X"01CD200001D8910DCFECE020E1008173815101F70CCE2EC3C08FDE34E030E010";
constant p1_28 : BIT_VECTOR := X"918CDD9D018F01F8DDC701C4E060E0412B898988E060E04083AB8389E0A01B80";
constant p1_29 : BIT_VECTOR := X"0B919701F7E9900D1EFFE0F0F72905A11DB1960187AB878909A185BC859AF091";
constant p1_2A : BIT_VECTOR := X"C0053661366936680178816001C45F0CC02701922F76FD57895983BC839AE0B0";
constant p1_2B : BIT_VECTOR := X"E080F009916C1CB194081CB1940801C4E06AC00401C4E068C00A01C4F469F061";
constant p1_2C : BIT_VECTOR := X"B60FB7DE93CF9508903F905F907F909F90BF90DF90FF911F91CFBE0F94F89661";
constant p1_2D : BIT_VECTOR := X"01C9DE17857E9601821F821D821B83894F3F019EE030F41901270126BFCDBFDE";
constant p1_2E : BIT_VECTOR := X"E09027222F432B5B2B39E0B0E09027222F43E050E030BC1291DFBFCDBFDEB60F";
constant p1_2F : BIT_VECTOR := X"B5897F8B9508708CBD89B58901CA2B5B2B39E0B0E09027222F432B5B2B39E0B0";
constant p1_30 : BIT_VECTOR := X"308A0000E0806084F7D9308A0000E08060889508C002B60005919601E090BD89";
constant p1_31 : BIT_VECTOR := X"E090BD89B58905919601E090BD89B58960849508F7D9308A0000E0807F87F7D9";
constant p1_32 : BIT_VECTOR := X"B58900000000BD89B5897F87C003E020950805919601E090BD89B58905919601";
constant p1_33 : BIT_VECTOR := X"9601E090BD89B5897F87CFDCF0115F2F00000000BD89B58905919601E090BD89";
constant p1_34 : BIT_VECTOR := X"0000E0807F8BE0209508F7E19587E0232F8905314F3F0000E0206084B7900591";
constant p1_35 : BIT_VECTOR := X"9F739F622F823038F7D9308A0000E08060842B28F7E19587E0430F22F7D9308A";
constant p1_36 : BIT_VECTOR := X"1BBB2E1A950801CF1FF90DB01FF90DB027999F659F749F839F920DE01DF19F82";
constant p1_37 : BIT_VECTOR := X"CFFF950801BD019B95809560941A1F881F660BE41BA207F507B31FFF1FBBC00D";
constant p1_38 : BIT_VECTOR := X"3D6474686C20726564252520203A007261207265642525006C617264203A6500";
constant p1_39 : BIT_VECTOR := X"612061767264203A650025206165326C203264616C6131726120726564252520";
constant p1_3A : BIT_VECTOR := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFF464542413736333200200D000A0052563272";
constant p1_3B : BIT_VECTOR := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
constant p1_3C : BIT_VECTOR := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
constant p1_3D : BIT_VECTOR := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
constant p1_3E : BIT_VECTOR := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
constant p1_3F : BIT_VECTOR := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
end prog_mem_content;
|
-------------------------------------------------------------------------------
-- lmb_bram_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library lmb_bram_elaborate_v1_00_a;
use lmb_bram_elaborate_v1_00_a.all;
entity lmb_bram_wrapper is
port (
BRAM_Rst_A : in std_logic;
BRAM_Clk_A : in std_logic;
BRAM_EN_A : in std_logic;
BRAM_WEN_A : in std_logic_vector(0 to 3);
BRAM_Addr_A : in std_logic_vector(0 to 31);
BRAM_Din_A : out std_logic_vector(0 to 31);
BRAM_Dout_A : in std_logic_vector(0 to 31);
BRAM_Rst_B : in std_logic;
BRAM_Clk_B : in std_logic;
BRAM_EN_B : in std_logic;
BRAM_WEN_B : in std_logic_vector(0 to 3);
BRAM_Addr_B : in std_logic_vector(0 to 31);
BRAM_Din_B : out std_logic_vector(0 to 31);
BRAM_Dout_B : in std_logic_vector(0 to 31)
);
attribute x_core_info : STRING;
attribute keep_hierarchy : STRING;
attribute x_core_info of lmb_bram_wrapper : entity is "lmb_bram_elaborate_v1_00_a";
attribute keep_hierarchy of lmb_bram_wrapper : entity is "yes";
end lmb_bram_wrapper;
architecture STRUCTURE of lmb_bram_wrapper is
component lmb_bram_elaborate is
generic (
C_MEMSIZE : integer;
C_PORT_DWIDTH : integer;
C_PORT_AWIDTH : integer;
C_NUM_WE : integer;
C_FAMILY : string
);
port (
BRAM_Rst_A : in std_logic;
BRAM_Clk_A : in std_logic;
BRAM_EN_A : in std_logic;
BRAM_WEN_A : in std_logic_vector(0 to C_NUM_WE-1);
BRAM_Addr_A : in std_logic_vector(0 to C_PORT_AWIDTH-1);
BRAM_Din_A : out std_logic_vector(0 to C_PORT_DWIDTH-1);
BRAM_Dout_A : in std_logic_vector(0 to C_PORT_DWIDTH-1);
BRAM_Rst_B : in std_logic;
BRAM_Clk_B : in std_logic;
BRAM_EN_B : in std_logic;
BRAM_WEN_B : in std_logic_vector(0 to C_NUM_WE-1);
BRAM_Addr_B : in std_logic_vector(0 to C_PORT_AWIDTH-1);
BRAM_Din_B : out std_logic_vector(0 to C_PORT_DWIDTH-1);
BRAM_Dout_B : in std_logic_vector(0 to C_PORT_DWIDTH-1)
);
end component;
begin
lmb_bram : lmb_bram_elaborate
generic map (
C_MEMSIZE => 16#8000#,
C_PORT_DWIDTH => 32,
C_PORT_AWIDTH => 32,
C_NUM_WE => 4,
C_FAMILY => "spartan3a"
)
port map (
BRAM_Rst_A => BRAM_Rst_A,
BRAM_Clk_A => BRAM_Clk_A,
BRAM_EN_A => BRAM_EN_A,
BRAM_WEN_A => BRAM_WEN_A,
BRAM_Addr_A => BRAM_Addr_A,
BRAM_Din_A => BRAM_Din_A,
BRAM_Dout_A => BRAM_Dout_A,
BRAM_Rst_B => BRAM_Rst_B,
BRAM_Clk_B => BRAM_Clk_B,
BRAM_EN_B => BRAM_EN_B,
BRAM_WEN_B => BRAM_WEN_B,
BRAM_Addr_B => BRAM_Addr_B,
BRAM_Din_B => BRAM_Din_B,
BRAM_Dout_B => BRAM_Dout_B
);
end architecture STRUCTURE;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc802.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b03x00p03n01i00802ent IS
begin
exit; -- illegal location for exit statement
END c01s01b03x00p03n01i00802ent;
ARCHITECTURE c01s01b03x00p03n01i00802arch OF c01s01b03x00p03n01i00802ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s01b03x00p03n01i00802 - Exit statement can not appear in entity statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b03x00p03n01i00802arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc802.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b03x00p03n01i00802ent IS
begin
exit; -- illegal location for exit statement
END c01s01b03x00p03n01i00802ent;
ARCHITECTURE c01s01b03x00p03n01i00802arch OF c01s01b03x00p03n01i00802ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s01b03x00p03n01i00802 - Exit statement can not appear in entity statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b03x00p03n01i00802arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc802.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b03x00p03n01i00802ent IS
begin
exit; -- illegal location for exit statement
END c01s01b03x00p03n01i00802ent;
ARCHITECTURE c01s01b03x00p03n01i00802arch OF c01s01b03x00p03n01i00802ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s01b03x00p03n01i00802 - Exit statement can not appear in entity statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b03x00p03n01i00802arch;
|
library IEEE;
use IEEE.Std_Logic_1164.all;
entity myOr16_tb is
end myOr16_tb;
architecture behavioral of myOr16_tb is
component myOr16
port(a: in std_logic_vector(15 downto 0); b: in std_logic_vector(15 downto 0); s: out std_logic_vector(15 downto 0));
end component;
-- signals used for testing
signal s1: std_logic_vector(15 downto 0);
signal s2: std_logic_vector(15 downto 0);
signal o1: std_logic_vector(15 downto 0);
begin
-- component instantiation
myOr16_1: myOr16 port map(a => s1, b => s2, s => o1);
process
begin
s1 <= "0000000000000000";
s2 <= "0000000000000000";
wait for 1 ns;
assert o1 = "0000000000000000" report "or('0000000000000000', '0000000000000000') was not '0000000000000000'" severity error;
s1 <= "1111111100000000";
s2 <= "0000000011111111";
wait for 1 ns;
assert o1 = "1111111111111111" report "or('1111111100000000', '0000000011111111') was not '1111111111111111'" severity error;
s1 <= "0000111100001111";
s2 <= "0000111111110000";
wait for 1 ns;
assert o1 = "0000111111111111" report "or('0000111100001111', '0000111111110000') was not '0000111111111111'" severity error;
assert false report "test complete" severity note;
wait;
end process;
end behavioral;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
lz3B4KHX5z7HJK6kHiZGMmcEnUqLtTRT/n7HdY7szClNEEBtVq2UQW/wdwwMN27AnOLZPVfuS67c
Y2O4fk1xOw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
OUoXLY9rVEqAKiJgtR19Q8FIQUm9wPmLFXF2sem6w9gJVRflCYIHWjOAqv6eppRvqeqcjaja3KKN
iRxsDXzkmdVb18CNyYXYPgZU4MySqAPoAE8BZ3alC446EKqG5bo3Faah4iFiaQ2fsSYQDhznQFWV
FIedseAJGSJjdgeT43M=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
bHuGx6phwwi065A2gw0E1Tqc2OLDUoohEHY7mOoJcUQwvr9OEJ4yz01Uls3wx2UOc24N+ANXe8aM
YdyfwspjYSBviz8nI/XUT5fPMjNbtL8HFChLorcX+K00Sc+A9m1I9+5W+Wd6GLSKBCVYKnWRn9Os
rc68y/GTowadTW08aEEccqOavDD8XG+R6gQqGpi5C8xq75oqBRmE5yNpxpBXxQRz9mmAsJcZ773H
BpObF8UUngkYlRzDjfxz3vzf6lVAPrLm55l1zEsel1LRtdqlRT8kBTrz1kke43v4c6xNv0u+i1Y0
dvxmNCEmLNrwBuVbcA8l6Jjp0k0WZScEgrEOCA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
4sCk5d4E+rPjLUhUiUrzCNkXo2ztvWgfU4Ic3n3YDGHZzWC7cjzTKSJroiCXwtIaQEIL5FpdrGOo
eHf9JlqikZvG/pLSpSZr6BTZioOpsjgI4CJq9n0wGhpyClKm24hGzYEPH8AkBs4wVmgt4sOHvyYc
mYqTUQDFFlehrx6Wh0E=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
cjjanW9F+fseEMt2SDd6R3KYZVrfLHKeq8ULFHbP0E7BiwY4Vkec6zVJkc5FOAAhZdR5Ywc2FOnS
jk9bJ37QuAeSdAcrSzysHiIJYxA3kbMVuIa63kiSn3dKlLmPc1gZ2/UtM3HTBff0RPQzxl944kH8
SUid8bQM/bx+7wxLnTLuo6uTok/+c8ipzvZZ5iJ9DgzZyHiiuOtKu8JWNRVw1P5d1QqQT3EZ7Q8j
fnqcUNAmoR2w1hlmAhXTJgZbpiKUcMF+Y9/twpUzFl3rdEE6PKGzb5YQ/Re4uf+MJU96/KSTzmBR
Xfe8WjI4zLk+NlEm8eNku5cgYGTA1pkwApl+6w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 10960)
`protect data_block
PKlpisMKFINH4hoELw81Ae+vpIr0xr/BIQZISQh02QmAYRngfWchi+A+2gXJ0ErM+PWm3fbvLHaf
UADT/opvnHMCrmwuOuQX48J/a1y0sztlHgsA7XTu3se9+qgRV127lwvsMJp+UlinF11bhqOX4xmc
4cYuCuf0n1/UfLTSpbM+jwT6zHUTrOrKh7f9OpJ+QCgxfJhkQxcPhKOYBR3a8Dp06gydZjpwqjDq
tqPAaV6ta7+zR4nsr7KhZDk0KvhrrDa7oKo7kF4Yqt8L46maaQdVtdKjhVsrAGajIcZixhbXQBXC
KIPnejYm8Voo/+fTzj4QhGK3xFz3k3FowUtO5jGrPfd10F2QpBcb+lzujW5qHzaitTgU8nENP5TD
2NCNNxhTryKnoZbirc+DlOTjiUeVqWXdhzIhVjQE761Nzmz2eLo6N0V6ZXAbZPpb45msiAC4kCui
Sh4oKuCxBlkGt9/ew/UKSOYs4g/rPAUgxU5UJis2mhTgn8B70nZ6oe1lMoUjefiqYazyfy9m8vGS
EyNCpU32r32DOXi66vBKX3STS4MASUJIfYG+NpdusXHx8iM0GvteA1gnO9XlVeVucLuGO2H2TpmK
kNtPxJkOMbqjBOLbcw6u1MfDpAw0zM4S/xxxpD0m3R8p0n3wQdhT+VT41nAFYGTXHcj0UD1nlYk9
ZhVQDKcQaWJYd3lsXf/TNyrTovAkCZATosXG9/gmmkHeRoSaekH316l0DfUCazpMcUrE0gKAEV+2
bPeURMasKa3i1v3Q9v1COQBKJH2YL4cb4uW9dGdif1tBUmYddIAkEGs7ArxKb3pNxjuKy6V1DIMJ
XIpowUU4bXINHZzoB/7c/RgpIB6iGgafVpQoETmW/+DssTNucVCW8Kwh+UZiLWZ5G5mGaXr7TXxh
l0iz2gOWz3X8AT7JgFq6ItruuJBZ/ra5bWk//+vOxFoUCKV1+koz4Rlv7wpt7HJSSSICSO/akPPG
krhxjHXmtbWJG3FH017k263NKG9Ns/2xRZl8U4axgQLNB0HbhVWF0OYZ+XETB8sBwRGDNZEckCm9
Aw3jiTTqNStuhVhWvtAIv10Jys0Nc+/e3rHA9dM/mxvv3KhE21lKKzJQUi7wsX7SNfWjATofF63K
NWnw+8I7ds1IXKySwdS6BLd/OmygPsMAsrbK20V5vdtmT/W53scFA/dxCZlC4YOR5CkYnSs/jVpm
gZvD6tch6dfuDnLWz+E3D92qtGvA7i4MfEVC5e8ytxTrYjZFjTJyn8vA59PyMoPl+9YFy7afcqzl
aOvFPqWociBJgUDxdsRCC2+mgvRiJk+2m1vY7XgdaHH9I3WQjYYj9LzjD5Y7fozc7Pi4RLDETEyS
mxqQorH22rFzv/TOZPEwRLMD3o15g86d0S3yb2WlbPyN82LadclZ6/wlye7yVQo2MIlTZndWo3Pg
gGU3mPslBappcqCOJvD7U1JaXduNOMJ2wiR9hAR3UQn2FgdOP+snD5GiOqHRMMGBrBXL+IuOjDMK
aWoWzIJzTdx6Xn5VuLBp9ipme33V9FgzSzpWZV2TSRojdgbTHizXzQ0Mdy+VVfwDjdGZEcfrcgN9
jCG2vrSEqt0rjpFzjtQP9Z6txZqBSNuNRey2GvgfIP8fFmSL2fnhETfisPC/IHL/7XcUgD8AjU38
Wg70qui3u3p1R23i3EyXQvmt2mZG24g5gUR3QzJOh5OmpEUB16lF4rNxOLrT1IeCfqBVvWjzn7P1
F34PUqycxwmZhtbQSQbLIR1jUH5PLZzBC7gbXhDhTFW+tiM+HULrLfoYNLldm7LNPp+ky6qhN0B/
JlE2dsQKP4csNk61aq4pEAEfMgnXU5aYzNcK4NKuaOVAL1GWs+KIueLA+CGGft99LN/jEONqXEHs
VKeaLuijPqOX9aQi4aT3vBZK9mFkdNgb5SyXUzKY9FNevgM1hpT4vhjNK9U2fR2Y/H6ZSwl3RhND
+/S8Bl+byOrKBEXZ0J8MumniLa8f95UPXCIZjoK1vwoHjzMp1s5zx85kE5zgNnfH4Z0ZXwjG+rZL
esHmkBHf+58ZPZhC2mGNqZRsiDFbh4YW9Lmsxk5HuMKn4sixehuyLhv0YBEU/fWtAkrUM++gzgzz
8TZ1Ohg+yRaGpvTl3/SIXQrB+7lckwhHNTz9X9Jv4Kxgyz65E5odgHekq8x4oXEjfmg/f4iLDNez
0+ZF5IBM4XaFpkCvu3tEUpCBGBMyrlsCCpRtsDM72wgS6HvQ3vbpuwnSGOKr0tyFiHmn9SKRHYD4
cKrAr3epFd42s7HmNkWeBa5YaWvYhB+UxP/Ts5eahPKqvrGfVTEaNHCDjcoyQcCRybwEgt3eRnaO
bMj90rFhrCiG+i64aD2Vt1b8vyXy9/PCcKdkVsqNZIQB5mSaaK32i4tjULtMi3J3fbI/RGxkwwOB
TNyj2qkSAS0lO86+XU5DgcOeccIWC2Wh/CQmZg+03pXjqSTBxpPOjDhLK8xRI97F3jl7clYDwDkD
1Tk+czl1eG9ppfrFFOxloZrnANo+Q3iECpJGm2JUKLGfKuPZ8/wkuv4ZD7BrfB2Fubok3NUbs1s7
1A1FySkrL5P7ZJ9qukri8c/CPVWgcCaxqLzMDQp5iQfK85GlT/nj/IIX9+3XOm5YJRuEdQHnLqR/
SaHM/E6Mip3DNo9Ky8rFUhEu8YsTlg4rM7JIYTjReJE1+0PrwzG9mbOrzyuCQKonWCOeOxoEFMku
8T+TNqmafP3eFfg98fBOeFLFqvT02DO7XYXd3E53R/wjVoaiafIRw/hMKoOhDOsWcnn1tFicT2IG
/7P/Bg1Yg8/2yja22rQEa3m9gVlAhZHDQ5hER7kVxmzjrHlXIicasttA80b58eF/Yv2aYfyiLlg8
wIH4VyL+Af9Q/vgENpJBPQDhXAri0ZMGmwADU0FO2m92r1e5KYWcEyziZobv6yIClxuhoizCa6T+
hdH0OhLbgvd41Ox6j1TYJ5LX2WQRWXY/fa+NpnOKEWnR56S1oc/oKkiE0aj3WnenGnzgtYA1F5fQ
5lRBF7zzl5lfSS39xW4W7sDA7xB/AaC/uJLWR3HtyA/VwlEW/9bS87E79LbInytGvzcq0Yv3bMKy
wvt3lpHZUdUAYP9MRrMLIx87EHus5pa+vgLx5VIdGBXNOM+joU9Lz0ad1hNidgdL3x3Er+NyKTk3
rKcHwuMitlmMYGeUKM+0rQknIxD1oYz90AXE9GhZOYf+hwzsmFXgd/yNJKkxMTOYg/hUveuFjvjG
BlzjE+t4rs7QDwxHERt+RFxHQVC957Iyj/6GDXI302DCJHq1XLRz5UrFp+f7ZNtDyznJ5YJEkGd7
DpBGBmN2NEMe/Cay9og/1hQaatJ+95ueLNOJ2KmxiMKza4zsyiC36gF8JqXDj0YFZErM23T/qT/6
KPohLaYf2MoFetLzYCWPTs2/2zcF21VE2bfz26vGngL7YLxu/LmhoYMfoM4cyd/82JZSjwHRMrgM
+PMu5U6X7Ve/eFW2IMgxaUVOC2KrKbwT1/kMp3x2AFn1co4M4AglpGAZXnbJtpRD7otzyRuq1ehx
NjZFzzW4ltcaEnFI4ZtmhZ5LsHMVKKsYr7JkLFoNpVdOBOQRBR41UmYbI40j7xIz8xPcpQFRYLup
+FyJSf02AEjmTfuAcy4CfCSAnu28xxVj8zVnjKUuVfSy976CWwhl2L9aJHDSyEDmTwqRORriCgDg
nRtSNRdZNbDoY//6NqWZQrgxNpWQ3QLnJ1oNyHe/OkmoH5UwhFv8hxjUO+mYgZZXIBMkGAHE91qR
clEwV7vqi3lthQ8Z6jQaBeoPvgVaso2IOaP8jfJxPnz1wb83NvQ/5Cdkc3Ma7vhxBwCqvpsEOtnF
fYnvVZnuLKbs48vGloDR+o+JTkGCl3ApgQi/NoPxPVSkeUbwD4AAKrx+RkXxjdeqXEZqb5/hjlaU
XPc9WNziDhXZf0GKHRiPfYumoA7H0WtnpgSl/l9+8RIoBialvJuKA+93pkYWf+NhN2/YdtUVgM5m
Qke0RFt5ObsyT/GmsAdmucExDH3Ak0rB9pvgSFfNPDg+2ENl6a9zkWzh3kDNtxk5HgRgNUYrTV5e
6LNjoQ2Yk+y2K2oCG1iP50k+l1d96K6nkH6pG3S48irVuPIf200qWwN6ZSVvy4NgO5aklrn8/8w5
rbR3obr//OUT+5tGxaR/qYFMCVelp+6vbne4lGn6uygyLH9opDIcfCax2cJpJAedUQtJ7NgY+AwJ
vQDGVvC0fDV+ugGsS57+3fa5PNdzZs0GP6ftUJv7LNx1Fm3BIPFaW8brdqZOjLODAl518p/XSrqb
eI8KK+Mp4PuBC8uQd2QFZSb3qkxNir3YUWg1Kdfy4pCRPcsUBbSeGtrNKj4QvndOnojROIvEye8w
HhQqRjUxGs1eahR56q0S1wqIV68LgORIl9y7FGCfmu1DBSAIsTmWGiaShhDepXlwL+4WV97LP2JL
8XVdXQmbE2RMEhUhePmWCe74boG2BYSzth/uWyDumWgL2zYB+7fAXlH7Qvg1lm85Fkyy33sQuE9h
084Dak9V/q/G7WmTaTvCCXn+z+LBq7yAQz/BLL8BjbB7E1azlHQLKIIBT6W/5gtEsshlzcggXOqQ
RxZm53EHMBt12MOe8CA9tAWyX8BHsTpUavTvqQ3m+OLdKhVGIuD6kp+9htscDJSiqgpimLHFUyiZ
gnahr1x/tAiFAR0SOw/T40EK5v67CnJKdXk29xSGfvnIlzv1qd1WR4cGe6AGZPe95zPrQGHv/xUW
X5ufM1q+Dchcl1xOtkC/IwSnaHMjJWBE2q/8FDiKbEFRxV4HCerSEk6VsMHxhLgbdDWh3c7dFJ31
GIa+17B+U3eaog6sbtQSFEmOweZ24z28T9BNkrjSZyAzm62YsKttB0c7Z6JMyvIYhm0p23FIJyme
eYHT1YoPp5L/vLkZ/bjApX4Wt2iwIqsqTcuBGqqlWXcY8xyDhjlPAY3LHqs4pTTFVU/oWepXLQtn
rlu9kW4xqN8b5kdrjAi99pIG8z06r9b+CY7F3tQGg2fsSJrc0fpl8+LcV7rzdgVwXCT1PJDZWQtV
GeUkPsCQECyuQyiacqcYqnIq/+dPN29wM9CX56u5bFwn04oobN5ENOxdA9BP0pKl1cuzUTDgRRKY
qfSKu4iypVhqMIBgYCepT/VUsoxcdnFS380dituJ0e5SsNncVArtc7Pt7YNL31+cAyuQuwufnLcy
5yP0kWN+SDmpYYRZdJqItxvaaxVFy4w7yW7jbaJ8kZ8B4DmU2LIp14mEW2ScO2rWUNzKCUkuYJat
HnFteXKs6+vin2PKOp9EQX09nxNgB3aZod8LQgH3FDVEgPE9FjaG0OsTApIHfxIYypdlcRlaMJLA
UnhLgZAyUDhuqxi00yM4t+ySfakwHo6i+8d9WVbRbdcOZ7bSBNyaJ+b6lY1JoYBENkid+EpuJUqN
DYykchE6wzDdtu69rmN3IfYlgiVdCK3i4lTvk3hjb86vekhNivgVe14pV6pO3KgMpkE0b8Ctmhub
r81ILwkWyx5irNh/XGrw/mRfox5uUOPOBOJXrmwgm0K0ukuCyq+wLI08FW/lmpS0MBOO2OAOTyuX
J2v3Pvm2GyGF9I8yDfys38ytrPmz5Mgf0QJ1LcDWVYvYCGbftUrwIRqlMgv6fIjv8YfrvV6Ui8Jp
V8m92xMI5gNx0GfoolaHkllT+Dw7Z58QuAgCtDWtmBKzFEq6ZO2VBn8qlt5n3xMr0/IGXigfeHXQ
GgUuPmCla2kCWcylvDezgPIfF/ZMcq7lawUgu4i5Ew4t11yLb2FvWP0FWh6jRjzpXfZbJvK1fQvX
IF3C9w7AkzipStAkUybzG7E1jWfNh09JCjsqNBxKypW8PgArNf8h2pGxkHN0Kvhz7xcW/oTV4sxe
5QGixaoPS/EwqfXQQ9h4eMfN/XdgpO5hwHAcM/1c5qCHwSCEiBhoSOcXZRkHD2JEhWEjjup2Ymkh
Z0qZvJY0xEk52L/5bsqa9p0cgiv5nPPKV6vjBekVUVy/FQiBJ4mfEUZcW5hc1N6ifC7JcLYUS+c6
qvHQXRD4MUVO1CyVdLcP5ktObTDNR4omJCWAtcrUot+EbP0wTIEqaC1DwEhGwu/BR6KWuT3zocxz
aeRW2ZoaAFRcBuIp9ie0UN5x5A2lf1aqS4RE6giI3QWoRLlTlFBfb6Pst/UcFHCrtlTOWzmbhAvY
J0j8TGf4BJDrqtRq1go9ZaYezWuAvE4sTj8Hjw218/kJ/T3LmUNioSk7O2yLpoeIxwwz1Ktw1w1F
BRgWE2KoX7n5LrUIfk5oir7koUnuxLou0ourhd2NifpxTW6T8OSHLqGQIj+vS9/EjnDJMNCh3GIh
57GpdvYsx2x/BV9EMyCQ8z5ifledbJP6nt7sAhHtfZK/PGO/pfSRrbH8x0X/9qxWKs6fR7mNNzcE
l7UMw5wI11oqRrDg7aWQ1I1/RZHdNe/TWyy3CyLx2JTGGSiLqivGOYKlVdbQ3l4bV5LcUGz11Ksv
T3ewZ3joiDsbCscmqAmt39wDe6QRBsGgooSbjuJat4tXMqyZwfRFSv/MAEDhz/udrv2F3+Rd4VLU
cz11wRIYJYZjr69yJGjEIbQBs7nL/CgAruJZm7ObjDeZZWloeklL8igWN5jvu4vyMQuyETE7cyNE
erPqRzNY5odRKGtu/giHe1aBv9oTPLEIGgSdAnMLLNS3cIJUCRUI0ncWWvWTMpYU6XxFUqjvAaro
1hiRh5+v9nkIO/S6SXpGyJ3hA3ZwplUIARC2hVCnU+vydP90p+wSYtrt7/3gnu9N8w2tfUXSIWc0
7e2ZzjvfJsRsv+YD2gsqYxXLK1733I2JnweP9wiRyWOW+RIPv2DlTbLbURC3BeK4DAQLJBoOeijp
jK6yPjuizvcwNRRVRPFZI0XtkB/v6jBaqLHhgXlwQ1UBFbyrdq1B9Yj4dTV3Rb9pPz/N8TtuyEbR
wkWEX9IWZKgfdEe48EyU+zKNlb+SMyJGwYB50kBziMH4xTpWPb3CF3Imbs55TGpAcAf4GWGVXSrj
cvVDQPjTwaXBLN6EJWwQm6HEP4hHuuqhX5r15J71qc8rohYKb+0mUwcRlMm7H0CqQe38Gaov+wKD
cbtQQoN8bnI2PSLRGsfaRyS77jFiR6mU/WPmCKeSgBdUiHDkq/viPctOdkSmELw0u/usGtD1km3f
QWtBgDUPjPZPQ15Mlm3VY8wcadCwlZOwCWJO/gIyRBC/W3f0mt7POk4vs/lA3kJ6eOI/tJh+C5gs
wGyr+thLtXP2p91fGlRdq4Qp2l//8dSN6p8H7Q2cz1M8uQZ/Ld8Htwc9belyE9F7WuOSx0waZ8pX
bNlGhG6tFFqSB56/fKsQkRsBBFioULd/OGdOOhvorZImkr7je197GfT0u5rqwxhORdyXPXmC6ZKL
yW0aYS8I4vdHsRO3+jGG1yA67xz8AGr8hf+6Y6+qH4YNkvL73hvfJwd8xX9MfzhdtEm35iu9loEx
ACI/+oijas4IRx1NNMRhzmYxyhm5tcnp9u6jdsSoa1qtxGfUsxVm5qjH3QH95bYzKfucT4r4lSaG
EHhkg/EfU7Y2Jzb0f2TVBXrRkEREcx0EL4laXGYv63vNlRzF3mblbec0AdLf53rQuZw1UhLlom+u
q96kO2uk8cBZuD4gJQ/efNeddiuQ8MfXdgd0dE0Woy7dPsObYVsakLnRwbHuC42gpR6lzVF0JPcG
wBSTef5WhJvqLH0+z+sdlfmRGSNDd+aYsaipkxjFzhyfuehlGQJUC9qAt9Bjzc4kwoadfnpQOv7t
M553X54NHdSCfSON9OsaGB3r/nuN0/DxNannACHqWLJe0mC6/rdB3TBL5KgrL4DV6WAz2FNVoQit
llOHGd9IHx8dq8cyRF2vpODUf0phH2C4m/w1jvSzFj6n7J+lECZ86+m56GQuIQwxLIgfpJwX/JBi
WtCzhESNE3eghLiWy25fdpwA5VDbbrpqjp/R7uB2ZmBth1739kayuB0cCYulv/H7z+iUWH/XplPQ
bhC2jH4iY3uCFsSr94/j6aeMBbl+yW0PHz6rv1bh70//ogonITU9SQKVSNzDlL+hwLoEZHVvjydV
7BbwYYvnV592lnK9gkA12sgBMKccTooCh8vOLFgT7MbJCiFk3N9oTT2ehUhmJENHguCSbrFTcf+j
NbIg8W7CtKkzDGUjVp74chbN5m6L0WBXPMG0E0yfRGUDIBEHNSjEMvxqChpVw8wQj3svpG095R+D
H626lgq/S1HMSJ+h/RB07Ueow2zQHmGmldLt7fXWDeboQKWidXX7RreXQD6gOhn1u2zA91wIYRUW
7jGqhFhr+3GeuXShjBSqsjntf4tMMI0XvlaaqXsTsjeNWejOb3Ew1WS1f9gAmvfLB9D+noTdRByg
MueMATiiyOAr/QBFPKHIDcqcajamoq7Ct3bEBgUcCv3U85C7vhp2XhBStkrrpg7zZbyrSw4BCobT
cCCOJpil6P/p+B3c5B8uRRGkTakvEqYi+dUBZXCBaWFvnLYdAIWUcm4J8hhk2RhQF5LURnXtJI9x
DW7hpZFoRb60TCVCq7nlglEv7/ij20atlk6063XIg2LDKboea5301V6xJYGL8tUDTkYzsNVheWEJ
Tl0zbVaFs0KjDVBBEX27mLDscnx/NV9N5nXVxTBxPSGqujI56BEbAjxCDA+ovYD9OX0SGXV+NHbE
5DD1XflyovsD7kPYH2e77gRrrII/+eAysylOASvZdorSrmSLgyjg234TLiH+zHHCFYFG9Dchp1we
T+lrYmcBBwmGexrRHCFBLo8mOJOGA2u1A5PQAQ1GAndc6ujv6dp6dvQ+TfWSHV73BhZFi7/2eps7
40SaN1NMh8X4cqPupeyd+1eQx2D9oQLLPQIDQ2uCSE81u0hBVFhCgh99JejX/mNpPj7mo8o4oI5R
l+f+bCaBq6Rkr4e+OYLGFavsh7on4pxyiZDCdk90yzNeHusEwSRwJ/uPON43rXS/rTE03ZvJ8592
6hLcXJTdypAszOSSn2dHh73nRyq3XBBZMXdwXWCs3cvD7+A9b/YDNf2pISZuC84pRl1zO6c3fzQS
yVaIm2AgfEPuaavbbzopuAnUifHKZpMwQ+beSaxrjNCmBu2mhtfY/q0nTqW7OrUOVZ0nrUp+VuJD
H+sq9iWa6ja28a0wE1ua5ZjPqhhSA1/5SPfmg8L2b0JiKVhyMBDRpf6DILd1SzINrzfBnyaYAetu
pNipTsT0WPracGVC44OU+6gG772lESl2+qkaXQ70aRSxHEX24Jn3zDlH+HfCDwY+1hd4pNFDBWER
gPr+59hVrbx2HQ69CyVutbk6hEZT2DhbG8egJwWexQ25MdpPWCLDxgzI+8aDXsFWd2Apbf8uvb6V
0jLOwIKTZpbrUb+W4lggjirrEVib/8EtnYLwEdIb25QRuQHB1fXVvysgwRvGiauKexwNwynriXTM
qfN2HoGhjZdpqLAlMht3JU+/lksjBO/En7us2Y37gZ2rSIdED3b77jGFXkOEd8tbQRgxqBPDVqCz
Y9yqqSF964YyE1s3f4AMobJ1/05t2zR4v7i7/kXXnozUtSiBSMbUQOF4y9wZkA91sveIg1FqpKrs
R7YE7CX/Kx0vyAKGTfT0myGtWlL6e8UXfKwTK9TchNgNsm+9SCvUGxKnbUUrwmBqOOk4m7ou+mv2
K5mJd1dVvGl35Jse9qMeLc3YT3/bnhWp6SDFXu1yK/vzciDPdq0j3Au5QqXDyxW1iG7aPG0d8mys
8/Yz6CwvPSH0mGXIztphFuNRjZD8k0C5eFzlXPWA+7MdO99D0PaBmem5YIkndK5LSHKtKrS41X3p
Moiveo1CyLn8taaqEgV7Brun8tupPoCQpvrggiPhWrEPKkvpLk9OCIXs//RGJ+SPcA81+ju8Y/aE
JL0dpPrZly5DVcw4fzHgdaQvd2x0ybGfGSgH4ZLxrIOZem91guNF7KJSa7Gino17BAIsSZfmBiEk
mSF5K6hSdogwLAAtnvlng0kOjKQ9uMQAvmKymI16XFvkA74auzFG3faT3Rr4NvQx5SmVrGEqMUYU
K8tDFIFbzUiym8KOTGbpDggXV+QOATPk8ibZwxGRaMMwfc8sWvALcj5Wz13JyYaRdo88uJeZaroi
0l1JL3sDSfc9jVCX7reBWN1+vZn7cITA1eMK1Gb1O36va8EXJda+TqWTQZlNvzZN8kQp2CIx/TEM
wCoLD4K6utBVGXiH6rjOAY6N04popuI0XjVzGU7aj7vt1Cup0+BXM+/x8PflGD8R+s+ikkUmaM1H
wY8VmV4k8lKBNpslYp7OBXjX6YHlP05R0q4WSTM1dSKULddby7dynXWtgscexOqjIF5DwugnfxDD
VK/0xkLCjACQIl9a2ZHKYlHcZCbGBupoUSZmVWEoxzuTeZD2VDNfC+HZqHV1nJXxLrS8+l0TgaRn
P4xn/Syt6pcmOWustVWKZj8pnryKhfHltFcz9gdVoFNP9WZ+89ScqAZ3XEBUdpLnGnhBmnHuTU40
gocoxNVuXxjjvE9TsUcZFCBpaq8Q4dfnkK1LIfvLQvDsva8RtZcpxvWY/uMktMH1sTakPWlBeNKh
1+kV5nB4l0abx3umSsE455ndxAmPbFNc0NB/KcvqxK7w1YESlL4+LAK0+rZYxHFju0lH40XuYlBA
u4ItbtNPY8qP8NLR10BxUio+KC4Pl3yUoW1+0y2KfboQVgsn5TE1kzwZsuMvpCBUCiXis7UjUUC3
ukYyqeRjLunvcHARpvjUky2JxiVTN2gBbXpihny5aEac4F/J3RDISf3dfVEH+euX4cIB4YFIZ12U
Mu5m1SosnwfWE15Vckunjv48Aws9UmPlinW6Z6YBobgG7RtSfZBlN6KiuKHXwIhhOnV9Pk51x1P2
ien62lbp63nEPT4zREm5k+UEpHQNYu8TD8pZ2ziZ0uULcmlq8V1VXpvsuzCDjCIAVKpuAONhF6db
5xf5iTcCa31WbB+9tzRn5fPxYmf1JlB1Db7PAgAuowWbNUA8qUlm48m9+15MFgPJ71lnO80TR7/F
YrYXpJIrdd0r0XvsTVyWag8JuEtMe9wF2xxGi3yfwG9yYDedoBrdT8muhe35R0P/AlClHNvvQLm+
toSeViEsLphU3Q6mbsLd3selKA9yxlkkW0WdMe5qP47SbgpP9mJafJRTrvbdvVFpO+Bo5EGKSXY0
g+xtYrc8pZz20T9g0AZAT5kR26urWbjWVQRx9haThrUSM1cH8uF8dRv70Ary6qo+skBn2G0Fl8Zc
WegXXE9rEFlsetJ2iHB36ft2UEomSo8cou5yhXaejCqHaYW/fvTzaql5WbsStZrgiQ+K8xQFNfjJ
NLpFbcSQmN4TFrjGWkvvmvMJBIp3t6vOEjxbXMQCHz6sRl+3md+y1u6cQWKZMNksN66juJWrifXh
qZ9POb3YYfwlLo9BXHytbsrh4UxasdszyO9finWuRMOfESk/T2OIRRhap9eSgWWeuO/qzvMOnAu3
qe5bwyHeXH24XXa+rBeNbp9Dg6AdFWOV2bV6+2EdyW2eEx4U+gL+Fo4Kn1putFOCU+sOzgDrxOyy
ymOxC/ldmRP2DlkzcLedswyhkT2JWrrkxLMxtrfQjbcqEN9bMoZanygxScK8nUi8WO1j1GolEN0d
ARjC10GAnGTJWJyGu8ygM37P/xgso0cAI0eZrhAQQhiNqmeqSo89AcYJcYE+6lhyxqVT4UDPABop
Rmnv6sI6wOzqkEVaNZioamQ086DR45y2VWSdxuWr0snXt1OQb73qZHDPTopmsy5UbjbjeYNGVOk+
aEbroV1Jjuz2SbQlfO2KhYD8O6ARFvqf1QZywAFtoTFogsnyjmJG8DMmjXKN9AI0QoMP2XSJeOsJ
B36DHtf0Sjuo4i8g3jKFL1lJJcPdvFvaS8IjIMocR1L3rpajih4Q0yQMIlJhua9jEGSSLPBdf4/+
14N/QIVFypsQcF5GVjqz39sVj9sdU8wZnbZyOzmsi9fmOc6Q18dqh1HjMdgO0mnK9hUMBChjTr0C
cm/OvX0Z3eRy7ygbmP49loQq8ur7RzzoUCDZV0sYMqCGutELkXQOoFWFDNyRrlU1F8P9H1gMZl1X
Nxm8o1KPyWlJW4QvC0m/UEgZtwyXnEuZo/hOb86T8Z5MUciyYu4kGrUKXlvuVDkCe5vzscmbCh1w
bYYRqvGZkFODdM+5FHJ2Y62HOzcsPVYt3c9TWLMuHovGtUMgV6wb5xmNKTnE4SX8e6EHqntsgtZj
WdaYrEKZ/cWxLqTUxMqJxlW7GDAdw2hGrgrgwB1so4GHIpTx0IZX0MDiWbCcMy/KJvj5xgQRIgK3
vXYHUx/gC8a9P4gGgs3LgAHvdB2izugj1kGYatH2yKvijjf+h5ZoUQVbzh5akl1n38GpFr4THdHD
Dti8a6oeKGKIexKsKva8OSWKmIrssX0698xbofuaJxMd0//mdvOvq42uLtcV7b+vDsYF7vT4TGmT
uB+hWUuJpxE8zeOkvCOLe0/xdYXdwjCSMLIqZgnh+OS2T4kPOSUitFEk5XxKfrddvEZ8m4PWBZli
Cu91XGqmYyM6fUvo++M7PktrpHLaiG4KG3J5HfHhlGMMs821j/Eqmlm/TEUKo56L4LPirFuJTmC7
Zu1qR96GMJ2Jm1bLCqwv5CUEmakwg+WReLvEiUXSroilhQ0yPB0uQ5FtqE5oPZ7025m5sgiJEHb8
J6TCgNA8Y6PTt7aud5cF7gUUiCOU5vpPD+96si2qUjUQPgLCz+w5SvS8Daep9JqHQImIeidQfkLS
IDo9A0S3YlD92lFhtb7QB075YS6vUttNd6tSpMXxrCvos/xsNRFWPHKD94ORf1y4FTM1pqhhg+82
/K6U+6RQEKDsfCxqWhDwvijz1nAuP8p5LCcR2lDPjfIMg/2kpz9ixrfSmsS9+NRNht2vF81xDDgF
EGaiWjGalIGjOCYJYBLmvaeLkG2EM0rRahPaDsXmZqm03x6hrBFkKaCv4z/vG9xiYt1R+z5U3PFC
Bm4De65ly9OJrax4PLoMrqSDY1KGOIbe49WWxPlxazBWp3EEtu/hncC7kZkNmlvMPgjOoxK5zxpb
1rkczZ3tvJyN9Hq11h9GGA/EIHtD6JPhESyg/dHKgF23NplGVN08W37JlceAR/ZcnY0nMewkSKBY
9kSovzAZTkvY7O8HrMbq7Q+02qp+MR9FMBOpaGPh4HXuerJKHAcyLIIn9rz2aLo4I/sm5IeqNCSo
MD2aAxbaEqmbds59edaN5g8j6/KFtOia2f4+/RvN1nL2oR85VX8ANVbKJaLeCL5r7B17P8qmIGLz
NQweh39StjJy/7kCcZ2776DPOHRekRRv2yq7XkYNHk9SliqrTBMC9JYrFQn72pY4A/9yIrheGzBZ
7UWV2a/INBYy7g5VE01tcB5BPLOBDZtDiiDki9cw/dTnoDLdSgqNA2FCeBJoAOFAgRqYZ0LUw/qj
Uej/OhPbuNlHYTx4FBxjeGkK4iAmGATcP/af3EAuB3c8i7VTK+6n45M7XFamxeDVO9Z0AcE/dUfs
5E9V0H9SD5mFel97df+V4fzhPcjVLugVlBM9p4slPmRytqZmRqGuVz7GoqntDEBkLqLjQDnc2/7E
EKa7Z+yn4XrqX5sY0chZ97r934SY/6QqPgMAZvbOWg6wFZjjLvIjWFOfoBrPMvit4R6wkg/Ay5Sh
SbMqHR8Q/VXNz7ToD9zuxzHUkWQSRSchT5gMEQcdCVlgun40ar6y6+V9xOHOFftO5k1VpLMC6Qum
xXLVx5E0OvpF8PIBySwUDst7XfpfI1Vh0FRS3WeP9dYYp8cNTc89g37vvOQmt+503SRwh5lqrwSr
+oNY/KU/DU3RpWZ8pFkxODwlwcZHlUaZYinvaKW6qEJ5viQrIl+rA6JD3mdOZ8CfkMH6ynsoeyYc
JHIrvmOR3YIzwkg2KZcqJBSX9EiBNv6dmKsFHygJe8p6wwjPiQQ7k6EEvAMqIYC/48LG4vyYE2BW
CvU/HFLhqysWtzPG0/stG+EFn7RTQWREV3p4Phh65uuqh+xDK8u8LDn2PwGDoLjpaZfwJbAi2Pr4
Sf6jXdzd6rTGYIhPBxUFuH4H/27xgkjtLhmSF7dMoNTabGj0Y8hZNx4+K3jTKg30cUWAKvHJvYwo
NE5JQY3YipnmADfBhEPlXdwRrE7u5smwbkhBpTcWKLvOcq/3ilniKwhso9LHqDx4jSX8f122CZVQ
Hnk2+LGnjJn/BkRfDntLKaNTHnSqWaaVmzyrUpu7uPi2iDnyZg0QoD7dE1zePWtl52AtlfuugZol
N8jmdWSdmzIh1+cAFbtOhVLc96qSPYJncREPlAjEsL4HNHlYDNd5AFFCoRGn9fpYN9pqbOxV13Sj
fWss9zN44N3OhK3o5Z8CqVmtjHbMEVYavgHnVbMtuDzXMEnbYqRbEwEuU2624z3pM8XCc5hcZBul
xnaCQqFjFRmOziUvPCINhbvQjiQigOewb0QvTkg9b/G8JCjr+WBHIjMHv2orVT7ccwn4ga4h+XWl
O3oKeGlIBQsNSZehOqK/iQ==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
lz3B4KHX5z7HJK6kHiZGMmcEnUqLtTRT/n7HdY7szClNEEBtVq2UQW/wdwwMN27AnOLZPVfuS67c
Y2O4fk1xOw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
OUoXLY9rVEqAKiJgtR19Q8FIQUm9wPmLFXF2sem6w9gJVRflCYIHWjOAqv6eppRvqeqcjaja3KKN
iRxsDXzkmdVb18CNyYXYPgZU4MySqAPoAE8BZ3alC446EKqG5bo3Faah4iFiaQ2fsSYQDhznQFWV
FIedseAJGSJjdgeT43M=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
bHuGx6phwwi065A2gw0E1Tqc2OLDUoohEHY7mOoJcUQwvr9OEJ4yz01Uls3wx2UOc24N+ANXe8aM
YdyfwspjYSBviz8nI/XUT5fPMjNbtL8HFChLorcX+K00Sc+A9m1I9+5W+Wd6GLSKBCVYKnWRn9Os
rc68y/GTowadTW08aEEccqOavDD8XG+R6gQqGpi5C8xq75oqBRmE5yNpxpBXxQRz9mmAsJcZ773H
BpObF8UUngkYlRzDjfxz3vzf6lVAPrLm55l1zEsel1LRtdqlRT8kBTrz1kke43v4c6xNv0u+i1Y0
dvxmNCEmLNrwBuVbcA8l6Jjp0k0WZScEgrEOCA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
4sCk5d4E+rPjLUhUiUrzCNkXo2ztvWgfU4Ic3n3YDGHZzWC7cjzTKSJroiCXwtIaQEIL5FpdrGOo
eHf9JlqikZvG/pLSpSZr6BTZioOpsjgI4CJq9n0wGhpyClKm24hGzYEPH8AkBs4wVmgt4sOHvyYc
mYqTUQDFFlehrx6Wh0E=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
cjjanW9F+fseEMt2SDd6R3KYZVrfLHKeq8ULFHbP0E7BiwY4Vkec6zVJkc5FOAAhZdR5Ywc2FOnS
jk9bJ37QuAeSdAcrSzysHiIJYxA3kbMVuIa63kiSn3dKlLmPc1gZ2/UtM3HTBff0RPQzxl944kH8
SUid8bQM/bx+7wxLnTLuo6uTok/+c8ipzvZZ5iJ9DgzZyHiiuOtKu8JWNRVw1P5d1QqQT3EZ7Q8j
fnqcUNAmoR2w1hlmAhXTJgZbpiKUcMF+Y9/twpUzFl3rdEE6PKGzb5YQ/Re4uf+MJU96/KSTzmBR
Xfe8WjI4zLk+NlEm8eNku5cgYGTA1pkwApl+6w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 10960)
`protect data_block
PKlpisMKFINH4hoELw81Ae+vpIr0xr/BIQZISQh02QmAYRngfWchi+A+2gXJ0ErM+PWm3fbvLHaf
UADT/opvnHMCrmwuOuQX48J/a1y0sztlHgsA7XTu3se9+qgRV127lwvsMJp+UlinF11bhqOX4xmc
4cYuCuf0n1/UfLTSpbM+jwT6zHUTrOrKh7f9OpJ+QCgxfJhkQxcPhKOYBR3a8Dp06gydZjpwqjDq
tqPAaV6ta7+zR4nsr7KhZDk0KvhrrDa7oKo7kF4Yqt8L46maaQdVtdKjhVsrAGajIcZixhbXQBXC
KIPnejYm8Voo/+fTzj4QhGK3xFz3k3FowUtO5jGrPfd10F2QpBcb+lzujW5qHzaitTgU8nENP5TD
2NCNNxhTryKnoZbirc+DlOTjiUeVqWXdhzIhVjQE761Nzmz2eLo6N0V6ZXAbZPpb45msiAC4kCui
Sh4oKuCxBlkGt9/ew/UKSOYs4g/rPAUgxU5UJis2mhTgn8B70nZ6oe1lMoUjefiqYazyfy9m8vGS
EyNCpU32r32DOXi66vBKX3STS4MASUJIfYG+NpdusXHx8iM0GvteA1gnO9XlVeVucLuGO2H2TpmK
kNtPxJkOMbqjBOLbcw6u1MfDpAw0zM4S/xxxpD0m3R8p0n3wQdhT+VT41nAFYGTXHcj0UD1nlYk9
ZhVQDKcQaWJYd3lsXf/TNyrTovAkCZATosXG9/gmmkHeRoSaekH316l0DfUCazpMcUrE0gKAEV+2
bPeURMasKa3i1v3Q9v1COQBKJH2YL4cb4uW9dGdif1tBUmYddIAkEGs7ArxKb3pNxjuKy6V1DIMJ
XIpowUU4bXINHZzoB/7c/RgpIB6iGgafVpQoETmW/+DssTNucVCW8Kwh+UZiLWZ5G5mGaXr7TXxh
l0iz2gOWz3X8AT7JgFq6ItruuJBZ/ra5bWk//+vOxFoUCKV1+koz4Rlv7wpt7HJSSSICSO/akPPG
krhxjHXmtbWJG3FH017k263NKG9Ns/2xRZl8U4axgQLNB0HbhVWF0OYZ+XETB8sBwRGDNZEckCm9
Aw3jiTTqNStuhVhWvtAIv10Jys0Nc+/e3rHA9dM/mxvv3KhE21lKKzJQUi7wsX7SNfWjATofF63K
NWnw+8I7ds1IXKySwdS6BLd/OmygPsMAsrbK20V5vdtmT/W53scFA/dxCZlC4YOR5CkYnSs/jVpm
gZvD6tch6dfuDnLWz+E3D92qtGvA7i4MfEVC5e8ytxTrYjZFjTJyn8vA59PyMoPl+9YFy7afcqzl
aOvFPqWociBJgUDxdsRCC2+mgvRiJk+2m1vY7XgdaHH9I3WQjYYj9LzjD5Y7fozc7Pi4RLDETEyS
mxqQorH22rFzv/TOZPEwRLMD3o15g86d0S3yb2WlbPyN82LadclZ6/wlye7yVQo2MIlTZndWo3Pg
gGU3mPslBappcqCOJvD7U1JaXduNOMJ2wiR9hAR3UQn2FgdOP+snD5GiOqHRMMGBrBXL+IuOjDMK
aWoWzIJzTdx6Xn5VuLBp9ipme33V9FgzSzpWZV2TSRojdgbTHizXzQ0Mdy+VVfwDjdGZEcfrcgN9
jCG2vrSEqt0rjpFzjtQP9Z6txZqBSNuNRey2GvgfIP8fFmSL2fnhETfisPC/IHL/7XcUgD8AjU38
Wg70qui3u3p1R23i3EyXQvmt2mZG24g5gUR3QzJOh5OmpEUB16lF4rNxOLrT1IeCfqBVvWjzn7P1
F34PUqycxwmZhtbQSQbLIR1jUH5PLZzBC7gbXhDhTFW+tiM+HULrLfoYNLldm7LNPp+ky6qhN0B/
JlE2dsQKP4csNk61aq4pEAEfMgnXU5aYzNcK4NKuaOVAL1GWs+KIueLA+CGGft99LN/jEONqXEHs
VKeaLuijPqOX9aQi4aT3vBZK9mFkdNgb5SyXUzKY9FNevgM1hpT4vhjNK9U2fR2Y/H6ZSwl3RhND
+/S8Bl+byOrKBEXZ0J8MumniLa8f95UPXCIZjoK1vwoHjzMp1s5zx85kE5zgNnfH4Z0ZXwjG+rZL
esHmkBHf+58ZPZhC2mGNqZRsiDFbh4YW9Lmsxk5HuMKn4sixehuyLhv0YBEU/fWtAkrUM++gzgzz
8TZ1Ohg+yRaGpvTl3/SIXQrB+7lckwhHNTz9X9Jv4Kxgyz65E5odgHekq8x4oXEjfmg/f4iLDNez
0+ZF5IBM4XaFpkCvu3tEUpCBGBMyrlsCCpRtsDM72wgS6HvQ3vbpuwnSGOKr0tyFiHmn9SKRHYD4
cKrAr3epFd42s7HmNkWeBa5YaWvYhB+UxP/Ts5eahPKqvrGfVTEaNHCDjcoyQcCRybwEgt3eRnaO
bMj90rFhrCiG+i64aD2Vt1b8vyXy9/PCcKdkVsqNZIQB5mSaaK32i4tjULtMi3J3fbI/RGxkwwOB
TNyj2qkSAS0lO86+XU5DgcOeccIWC2Wh/CQmZg+03pXjqSTBxpPOjDhLK8xRI97F3jl7clYDwDkD
1Tk+czl1eG9ppfrFFOxloZrnANo+Q3iECpJGm2JUKLGfKuPZ8/wkuv4ZD7BrfB2Fubok3NUbs1s7
1A1FySkrL5P7ZJ9qukri8c/CPVWgcCaxqLzMDQp5iQfK85GlT/nj/IIX9+3XOm5YJRuEdQHnLqR/
SaHM/E6Mip3DNo9Ky8rFUhEu8YsTlg4rM7JIYTjReJE1+0PrwzG9mbOrzyuCQKonWCOeOxoEFMku
8T+TNqmafP3eFfg98fBOeFLFqvT02DO7XYXd3E53R/wjVoaiafIRw/hMKoOhDOsWcnn1tFicT2IG
/7P/Bg1Yg8/2yja22rQEa3m9gVlAhZHDQ5hER7kVxmzjrHlXIicasttA80b58eF/Yv2aYfyiLlg8
wIH4VyL+Af9Q/vgENpJBPQDhXAri0ZMGmwADU0FO2m92r1e5KYWcEyziZobv6yIClxuhoizCa6T+
hdH0OhLbgvd41Ox6j1TYJ5LX2WQRWXY/fa+NpnOKEWnR56S1oc/oKkiE0aj3WnenGnzgtYA1F5fQ
5lRBF7zzl5lfSS39xW4W7sDA7xB/AaC/uJLWR3HtyA/VwlEW/9bS87E79LbInytGvzcq0Yv3bMKy
wvt3lpHZUdUAYP9MRrMLIx87EHus5pa+vgLx5VIdGBXNOM+joU9Lz0ad1hNidgdL3x3Er+NyKTk3
rKcHwuMitlmMYGeUKM+0rQknIxD1oYz90AXE9GhZOYf+hwzsmFXgd/yNJKkxMTOYg/hUveuFjvjG
BlzjE+t4rs7QDwxHERt+RFxHQVC957Iyj/6GDXI302DCJHq1XLRz5UrFp+f7ZNtDyznJ5YJEkGd7
DpBGBmN2NEMe/Cay9og/1hQaatJ+95ueLNOJ2KmxiMKza4zsyiC36gF8JqXDj0YFZErM23T/qT/6
KPohLaYf2MoFetLzYCWPTs2/2zcF21VE2bfz26vGngL7YLxu/LmhoYMfoM4cyd/82JZSjwHRMrgM
+PMu5U6X7Ve/eFW2IMgxaUVOC2KrKbwT1/kMp3x2AFn1co4M4AglpGAZXnbJtpRD7otzyRuq1ehx
NjZFzzW4ltcaEnFI4ZtmhZ5LsHMVKKsYr7JkLFoNpVdOBOQRBR41UmYbI40j7xIz8xPcpQFRYLup
+FyJSf02AEjmTfuAcy4CfCSAnu28xxVj8zVnjKUuVfSy976CWwhl2L9aJHDSyEDmTwqRORriCgDg
nRtSNRdZNbDoY//6NqWZQrgxNpWQ3QLnJ1oNyHe/OkmoH5UwhFv8hxjUO+mYgZZXIBMkGAHE91qR
clEwV7vqi3lthQ8Z6jQaBeoPvgVaso2IOaP8jfJxPnz1wb83NvQ/5Cdkc3Ma7vhxBwCqvpsEOtnF
fYnvVZnuLKbs48vGloDR+o+JTkGCl3ApgQi/NoPxPVSkeUbwD4AAKrx+RkXxjdeqXEZqb5/hjlaU
XPc9WNziDhXZf0GKHRiPfYumoA7H0WtnpgSl/l9+8RIoBialvJuKA+93pkYWf+NhN2/YdtUVgM5m
Qke0RFt5ObsyT/GmsAdmucExDH3Ak0rB9pvgSFfNPDg+2ENl6a9zkWzh3kDNtxk5HgRgNUYrTV5e
6LNjoQ2Yk+y2K2oCG1iP50k+l1d96K6nkH6pG3S48irVuPIf200qWwN6ZSVvy4NgO5aklrn8/8w5
rbR3obr//OUT+5tGxaR/qYFMCVelp+6vbne4lGn6uygyLH9opDIcfCax2cJpJAedUQtJ7NgY+AwJ
vQDGVvC0fDV+ugGsS57+3fa5PNdzZs0GP6ftUJv7LNx1Fm3BIPFaW8brdqZOjLODAl518p/XSrqb
eI8KK+Mp4PuBC8uQd2QFZSb3qkxNir3YUWg1Kdfy4pCRPcsUBbSeGtrNKj4QvndOnojROIvEye8w
HhQqRjUxGs1eahR56q0S1wqIV68LgORIl9y7FGCfmu1DBSAIsTmWGiaShhDepXlwL+4WV97LP2JL
8XVdXQmbE2RMEhUhePmWCe74boG2BYSzth/uWyDumWgL2zYB+7fAXlH7Qvg1lm85Fkyy33sQuE9h
084Dak9V/q/G7WmTaTvCCXn+z+LBq7yAQz/BLL8BjbB7E1azlHQLKIIBT6W/5gtEsshlzcggXOqQ
RxZm53EHMBt12MOe8CA9tAWyX8BHsTpUavTvqQ3m+OLdKhVGIuD6kp+9htscDJSiqgpimLHFUyiZ
gnahr1x/tAiFAR0SOw/T40EK5v67CnJKdXk29xSGfvnIlzv1qd1WR4cGe6AGZPe95zPrQGHv/xUW
X5ufM1q+Dchcl1xOtkC/IwSnaHMjJWBE2q/8FDiKbEFRxV4HCerSEk6VsMHxhLgbdDWh3c7dFJ31
GIa+17B+U3eaog6sbtQSFEmOweZ24z28T9BNkrjSZyAzm62YsKttB0c7Z6JMyvIYhm0p23FIJyme
eYHT1YoPp5L/vLkZ/bjApX4Wt2iwIqsqTcuBGqqlWXcY8xyDhjlPAY3LHqs4pTTFVU/oWepXLQtn
rlu9kW4xqN8b5kdrjAi99pIG8z06r9b+CY7F3tQGg2fsSJrc0fpl8+LcV7rzdgVwXCT1PJDZWQtV
GeUkPsCQECyuQyiacqcYqnIq/+dPN29wM9CX56u5bFwn04oobN5ENOxdA9BP0pKl1cuzUTDgRRKY
qfSKu4iypVhqMIBgYCepT/VUsoxcdnFS380dituJ0e5SsNncVArtc7Pt7YNL31+cAyuQuwufnLcy
5yP0kWN+SDmpYYRZdJqItxvaaxVFy4w7yW7jbaJ8kZ8B4DmU2LIp14mEW2ScO2rWUNzKCUkuYJat
HnFteXKs6+vin2PKOp9EQX09nxNgB3aZod8LQgH3FDVEgPE9FjaG0OsTApIHfxIYypdlcRlaMJLA
UnhLgZAyUDhuqxi00yM4t+ySfakwHo6i+8d9WVbRbdcOZ7bSBNyaJ+b6lY1JoYBENkid+EpuJUqN
DYykchE6wzDdtu69rmN3IfYlgiVdCK3i4lTvk3hjb86vekhNivgVe14pV6pO3KgMpkE0b8Ctmhub
r81ILwkWyx5irNh/XGrw/mRfox5uUOPOBOJXrmwgm0K0ukuCyq+wLI08FW/lmpS0MBOO2OAOTyuX
J2v3Pvm2GyGF9I8yDfys38ytrPmz5Mgf0QJ1LcDWVYvYCGbftUrwIRqlMgv6fIjv8YfrvV6Ui8Jp
V8m92xMI5gNx0GfoolaHkllT+Dw7Z58QuAgCtDWtmBKzFEq6ZO2VBn8qlt5n3xMr0/IGXigfeHXQ
GgUuPmCla2kCWcylvDezgPIfF/ZMcq7lawUgu4i5Ew4t11yLb2FvWP0FWh6jRjzpXfZbJvK1fQvX
IF3C9w7AkzipStAkUybzG7E1jWfNh09JCjsqNBxKypW8PgArNf8h2pGxkHN0Kvhz7xcW/oTV4sxe
5QGixaoPS/EwqfXQQ9h4eMfN/XdgpO5hwHAcM/1c5qCHwSCEiBhoSOcXZRkHD2JEhWEjjup2Ymkh
Z0qZvJY0xEk52L/5bsqa9p0cgiv5nPPKV6vjBekVUVy/FQiBJ4mfEUZcW5hc1N6ifC7JcLYUS+c6
qvHQXRD4MUVO1CyVdLcP5ktObTDNR4omJCWAtcrUot+EbP0wTIEqaC1DwEhGwu/BR6KWuT3zocxz
aeRW2ZoaAFRcBuIp9ie0UN5x5A2lf1aqS4RE6giI3QWoRLlTlFBfb6Pst/UcFHCrtlTOWzmbhAvY
J0j8TGf4BJDrqtRq1go9ZaYezWuAvE4sTj8Hjw218/kJ/T3LmUNioSk7O2yLpoeIxwwz1Ktw1w1F
BRgWE2KoX7n5LrUIfk5oir7koUnuxLou0ourhd2NifpxTW6T8OSHLqGQIj+vS9/EjnDJMNCh3GIh
57GpdvYsx2x/BV9EMyCQ8z5ifledbJP6nt7sAhHtfZK/PGO/pfSRrbH8x0X/9qxWKs6fR7mNNzcE
l7UMw5wI11oqRrDg7aWQ1I1/RZHdNe/TWyy3CyLx2JTGGSiLqivGOYKlVdbQ3l4bV5LcUGz11Ksv
T3ewZ3joiDsbCscmqAmt39wDe6QRBsGgooSbjuJat4tXMqyZwfRFSv/MAEDhz/udrv2F3+Rd4VLU
cz11wRIYJYZjr69yJGjEIbQBs7nL/CgAruJZm7ObjDeZZWloeklL8igWN5jvu4vyMQuyETE7cyNE
erPqRzNY5odRKGtu/giHe1aBv9oTPLEIGgSdAnMLLNS3cIJUCRUI0ncWWvWTMpYU6XxFUqjvAaro
1hiRh5+v9nkIO/S6SXpGyJ3hA3ZwplUIARC2hVCnU+vydP90p+wSYtrt7/3gnu9N8w2tfUXSIWc0
7e2ZzjvfJsRsv+YD2gsqYxXLK1733I2JnweP9wiRyWOW+RIPv2DlTbLbURC3BeK4DAQLJBoOeijp
jK6yPjuizvcwNRRVRPFZI0XtkB/v6jBaqLHhgXlwQ1UBFbyrdq1B9Yj4dTV3Rb9pPz/N8TtuyEbR
wkWEX9IWZKgfdEe48EyU+zKNlb+SMyJGwYB50kBziMH4xTpWPb3CF3Imbs55TGpAcAf4GWGVXSrj
cvVDQPjTwaXBLN6EJWwQm6HEP4hHuuqhX5r15J71qc8rohYKb+0mUwcRlMm7H0CqQe38Gaov+wKD
cbtQQoN8bnI2PSLRGsfaRyS77jFiR6mU/WPmCKeSgBdUiHDkq/viPctOdkSmELw0u/usGtD1km3f
QWtBgDUPjPZPQ15Mlm3VY8wcadCwlZOwCWJO/gIyRBC/W3f0mt7POk4vs/lA3kJ6eOI/tJh+C5gs
wGyr+thLtXP2p91fGlRdq4Qp2l//8dSN6p8H7Q2cz1M8uQZ/Ld8Htwc9belyE9F7WuOSx0waZ8pX
bNlGhG6tFFqSB56/fKsQkRsBBFioULd/OGdOOhvorZImkr7je197GfT0u5rqwxhORdyXPXmC6ZKL
yW0aYS8I4vdHsRO3+jGG1yA67xz8AGr8hf+6Y6+qH4YNkvL73hvfJwd8xX9MfzhdtEm35iu9loEx
ACI/+oijas4IRx1NNMRhzmYxyhm5tcnp9u6jdsSoa1qtxGfUsxVm5qjH3QH95bYzKfucT4r4lSaG
EHhkg/EfU7Y2Jzb0f2TVBXrRkEREcx0EL4laXGYv63vNlRzF3mblbec0AdLf53rQuZw1UhLlom+u
q96kO2uk8cBZuD4gJQ/efNeddiuQ8MfXdgd0dE0Woy7dPsObYVsakLnRwbHuC42gpR6lzVF0JPcG
wBSTef5WhJvqLH0+z+sdlfmRGSNDd+aYsaipkxjFzhyfuehlGQJUC9qAt9Bjzc4kwoadfnpQOv7t
M553X54NHdSCfSON9OsaGB3r/nuN0/DxNannACHqWLJe0mC6/rdB3TBL5KgrL4DV6WAz2FNVoQit
llOHGd9IHx8dq8cyRF2vpODUf0phH2C4m/w1jvSzFj6n7J+lECZ86+m56GQuIQwxLIgfpJwX/JBi
WtCzhESNE3eghLiWy25fdpwA5VDbbrpqjp/R7uB2ZmBth1739kayuB0cCYulv/H7z+iUWH/XplPQ
bhC2jH4iY3uCFsSr94/j6aeMBbl+yW0PHz6rv1bh70//ogonITU9SQKVSNzDlL+hwLoEZHVvjydV
7BbwYYvnV592lnK9gkA12sgBMKccTooCh8vOLFgT7MbJCiFk3N9oTT2ehUhmJENHguCSbrFTcf+j
NbIg8W7CtKkzDGUjVp74chbN5m6L0WBXPMG0E0yfRGUDIBEHNSjEMvxqChpVw8wQj3svpG095R+D
H626lgq/S1HMSJ+h/RB07Ueow2zQHmGmldLt7fXWDeboQKWidXX7RreXQD6gOhn1u2zA91wIYRUW
7jGqhFhr+3GeuXShjBSqsjntf4tMMI0XvlaaqXsTsjeNWejOb3Ew1WS1f9gAmvfLB9D+noTdRByg
MueMATiiyOAr/QBFPKHIDcqcajamoq7Ct3bEBgUcCv3U85C7vhp2XhBStkrrpg7zZbyrSw4BCobT
cCCOJpil6P/p+B3c5B8uRRGkTakvEqYi+dUBZXCBaWFvnLYdAIWUcm4J8hhk2RhQF5LURnXtJI9x
DW7hpZFoRb60TCVCq7nlglEv7/ij20atlk6063XIg2LDKboea5301V6xJYGL8tUDTkYzsNVheWEJ
Tl0zbVaFs0KjDVBBEX27mLDscnx/NV9N5nXVxTBxPSGqujI56BEbAjxCDA+ovYD9OX0SGXV+NHbE
5DD1XflyovsD7kPYH2e77gRrrII/+eAysylOASvZdorSrmSLgyjg234TLiH+zHHCFYFG9Dchp1we
T+lrYmcBBwmGexrRHCFBLo8mOJOGA2u1A5PQAQ1GAndc6ujv6dp6dvQ+TfWSHV73BhZFi7/2eps7
40SaN1NMh8X4cqPupeyd+1eQx2D9oQLLPQIDQ2uCSE81u0hBVFhCgh99JejX/mNpPj7mo8o4oI5R
l+f+bCaBq6Rkr4e+OYLGFavsh7on4pxyiZDCdk90yzNeHusEwSRwJ/uPON43rXS/rTE03ZvJ8592
6hLcXJTdypAszOSSn2dHh73nRyq3XBBZMXdwXWCs3cvD7+A9b/YDNf2pISZuC84pRl1zO6c3fzQS
yVaIm2AgfEPuaavbbzopuAnUifHKZpMwQ+beSaxrjNCmBu2mhtfY/q0nTqW7OrUOVZ0nrUp+VuJD
H+sq9iWa6ja28a0wE1ua5ZjPqhhSA1/5SPfmg8L2b0JiKVhyMBDRpf6DILd1SzINrzfBnyaYAetu
pNipTsT0WPracGVC44OU+6gG772lESl2+qkaXQ70aRSxHEX24Jn3zDlH+HfCDwY+1hd4pNFDBWER
gPr+59hVrbx2HQ69CyVutbk6hEZT2DhbG8egJwWexQ25MdpPWCLDxgzI+8aDXsFWd2Apbf8uvb6V
0jLOwIKTZpbrUb+W4lggjirrEVib/8EtnYLwEdIb25QRuQHB1fXVvysgwRvGiauKexwNwynriXTM
qfN2HoGhjZdpqLAlMht3JU+/lksjBO/En7us2Y37gZ2rSIdED3b77jGFXkOEd8tbQRgxqBPDVqCz
Y9yqqSF964YyE1s3f4AMobJ1/05t2zR4v7i7/kXXnozUtSiBSMbUQOF4y9wZkA91sveIg1FqpKrs
R7YE7CX/Kx0vyAKGTfT0myGtWlL6e8UXfKwTK9TchNgNsm+9SCvUGxKnbUUrwmBqOOk4m7ou+mv2
K5mJd1dVvGl35Jse9qMeLc3YT3/bnhWp6SDFXu1yK/vzciDPdq0j3Au5QqXDyxW1iG7aPG0d8mys
8/Yz6CwvPSH0mGXIztphFuNRjZD8k0C5eFzlXPWA+7MdO99D0PaBmem5YIkndK5LSHKtKrS41X3p
Moiveo1CyLn8taaqEgV7Brun8tupPoCQpvrggiPhWrEPKkvpLk9OCIXs//RGJ+SPcA81+ju8Y/aE
JL0dpPrZly5DVcw4fzHgdaQvd2x0ybGfGSgH4ZLxrIOZem91guNF7KJSa7Gino17BAIsSZfmBiEk
mSF5K6hSdogwLAAtnvlng0kOjKQ9uMQAvmKymI16XFvkA74auzFG3faT3Rr4NvQx5SmVrGEqMUYU
K8tDFIFbzUiym8KOTGbpDggXV+QOATPk8ibZwxGRaMMwfc8sWvALcj5Wz13JyYaRdo88uJeZaroi
0l1JL3sDSfc9jVCX7reBWN1+vZn7cITA1eMK1Gb1O36va8EXJda+TqWTQZlNvzZN8kQp2CIx/TEM
wCoLD4K6utBVGXiH6rjOAY6N04popuI0XjVzGU7aj7vt1Cup0+BXM+/x8PflGD8R+s+ikkUmaM1H
wY8VmV4k8lKBNpslYp7OBXjX6YHlP05R0q4WSTM1dSKULddby7dynXWtgscexOqjIF5DwugnfxDD
VK/0xkLCjACQIl9a2ZHKYlHcZCbGBupoUSZmVWEoxzuTeZD2VDNfC+HZqHV1nJXxLrS8+l0TgaRn
P4xn/Syt6pcmOWustVWKZj8pnryKhfHltFcz9gdVoFNP9WZ+89ScqAZ3XEBUdpLnGnhBmnHuTU40
gocoxNVuXxjjvE9TsUcZFCBpaq8Q4dfnkK1LIfvLQvDsva8RtZcpxvWY/uMktMH1sTakPWlBeNKh
1+kV5nB4l0abx3umSsE455ndxAmPbFNc0NB/KcvqxK7w1YESlL4+LAK0+rZYxHFju0lH40XuYlBA
u4ItbtNPY8qP8NLR10BxUio+KC4Pl3yUoW1+0y2KfboQVgsn5TE1kzwZsuMvpCBUCiXis7UjUUC3
ukYyqeRjLunvcHARpvjUky2JxiVTN2gBbXpihny5aEac4F/J3RDISf3dfVEH+euX4cIB4YFIZ12U
Mu5m1SosnwfWE15Vckunjv48Aws9UmPlinW6Z6YBobgG7RtSfZBlN6KiuKHXwIhhOnV9Pk51x1P2
ien62lbp63nEPT4zREm5k+UEpHQNYu8TD8pZ2ziZ0uULcmlq8V1VXpvsuzCDjCIAVKpuAONhF6db
5xf5iTcCa31WbB+9tzRn5fPxYmf1JlB1Db7PAgAuowWbNUA8qUlm48m9+15MFgPJ71lnO80TR7/F
YrYXpJIrdd0r0XvsTVyWag8JuEtMe9wF2xxGi3yfwG9yYDedoBrdT8muhe35R0P/AlClHNvvQLm+
toSeViEsLphU3Q6mbsLd3selKA9yxlkkW0WdMe5qP47SbgpP9mJafJRTrvbdvVFpO+Bo5EGKSXY0
g+xtYrc8pZz20T9g0AZAT5kR26urWbjWVQRx9haThrUSM1cH8uF8dRv70Ary6qo+skBn2G0Fl8Zc
WegXXE9rEFlsetJ2iHB36ft2UEomSo8cou5yhXaejCqHaYW/fvTzaql5WbsStZrgiQ+K8xQFNfjJ
NLpFbcSQmN4TFrjGWkvvmvMJBIp3t6vOEjxbXMQCHz6sRl+3md+y1u6cQWKZMNksN66juJWrifXh
qZ9POb3YYfwlLo9BXHytbsrh4UxasdszyO9finWuRMOfESk/T2OIRRhap9eSgWWeuO/qzvMOnAu3
qe5bwyHeXH24XXa+rBeNbp9Dg6AdFWOV2bV6+2EdyW2eEx4U+gL+Fo4Kn1putFOCU+sOzgDrxOyy
ymOxC/ldmRP2DlkzcLedswyhkT2JWrrkxLMxtrfQjbcqEN9bMoZanygxScK8nUi8WO1j1GolEN0d
ARjC10GAnGTJWJyGu8ygM37P/xgso0cAI0eZrhAQQhiNqmeqSo89AcYJcYE+6lhyxqVT4UDPABop
Rmnv6sI6wOzqkEVaNZioamQ086DR45y2VWSdxuWr0snXt1OQb73qZHDPTopmsy5UbjbjeYNGVOk+
aEbroV1Jjuz2SbQlfO2KhYD8O6ARFvqf1QZywAFtoTFogsnyjmJG8DMmjXKN9AI0QoMP2XSJeOsJ
B36DHtf0Sjuo4i8g3jKFL1lJJcPdvFvaS8IjIMocR1L3rpajih4Q0yQMIlJhua9jEGSSLPBdf4/+
14N/QIVFypsQcF5GVjqz39sVj9sdU8wZnbZyOzmsi9fmOc6Q18dqh1HjMdgO0mnK9hUMBChjTr0C
cm/OvX0Z3eRy7ygbmP49loQq8ur7RzzoUCDZV0sYMqCGutELkXQOoFWFDNyRrlU1F8P9H1gMZl1X
Nxm8o1KPyWlJW4QvC0m/UEgZtwyXnEuZo/hOb86T8Z5MUciyYu4kGrUKXlvuVDkCe5vzscmbCh1w
bYYRqvGZkFODdM+5FHJ2Y62HOzcsPVYt3c9TWLMuHovGtUMgV6wb5xmNKTnE4SX8e6EHqntsgtZj
WdaYrEKZ/cWxLqTUxMqJxlW7GDAdw2hGrgrgwB1so4GHIpTx0IZX0MDiWbCcMy/KJvj5xgQRIgK3
vXYHUx/gC8a9P4gGgs3LgAHvdB2izugj1kGYatH2yKvijjf+h5ZoUQVbzh5akl1n38GpFr4THdHD
Dti8a6oeKGKIexKsKva8OSWKmIrssX0698xbofuaJxMd0//mdvOvq42uLtcV7b+vDsYF7vT4TGmT
uB+hWUuJpxE8zeOkvCOLe0/xdYXdwjCSMLIqZgnh+OS2T4kPOSUitFEk5XxKfrddvEZ8m4PWBZli
Cu91XGqmYyM6fUvo++M7PktrpHLaiG4KG3J5HfHhlGMMs821j/Eqmlm/TEUKo56L4LPirFuJTmC7
Zu1qR96GMJ2Jm1bLCqwv5CUEmakwg+WReLvEiUXSroilhQ0yPB0uQ5FtqE5oPZ7025m5sgiJEHb8
J6TCgNA8Y6PTt7aud5cF7gUUiCOU5vpPD+96si2qUjUQPgLCz+w5SvS8Daep9JqHQImIeidQfkLS
IDo9A0S3YlD92lFhtb7QB075YS6vUttNd6tSpMXxrCvos/xsNRFWPHKD94ORf1y4FTM1pqhhg+82
/K6U+6RQEKDsfCxqWhDwvijz1nAuP8p5LCcR2lDPjfIMg/2kpz9ixrfSmsS9+NRNht2vF81xDDgF
EGaiWjGalIGjOCYJYBLmvaeLkG2EM0rRahPaDsXmZqm03x6hrBFkKaCv4z/vG9xiYt1R+z5U3PFC
Bm4De65ly9OJrax4PLoMrqSDY1KGOIbe49WWxPlxazBWp3EEtu/hncC7kZkNmlvMPgjOoxK5zxpb
1rkczZ3tvJyN9Hq11h9GGA/EIHtD6JPhESyg/dHKgF23NplGVN08W37JlceAR/ZcnY0nMewkSKBY
9kSovzAZTkvY7O8HrMbq7Q+02qp+MR9FMBOpaGPh4HXuerJKHAcyLIIn9rz2aLo4I/sm5IeqNCSo
MD2aAxbaEqmbds59edaN5g8j6/KFtOia2f4+/RvN1nL2oR85VX8ANVbKJaLeCL5r7B17P8qmIGLz
NQweh39StjJy/7kCcZ2776DPOHRekRRv2yq7XkYNHk9SliqrTBMC9JYrFQn72pY4A/9yIrheGzBZ
7UWV2a/INBYy7g5VE01tcB5BPLOBDZtDiiDki9cw/dTnoDLdSgqNA2FCeBJoAOFAgRqYZ0LUw/qj
Uej/OhPbuNlHYTx4FBxjeGkK4iAmGATcP/af3EAuB3c8i7VTK+6n45M7XFamxeDVO9Z0AcE/dUfs
5E9V0H9SD5mFel97df+V4fzhPcjVLugVlBM9p4slPmRytqZmRqGuVz7GoqntDEBkLqLjQDnc2/7E
EKa7Z+yn4XrqX5sY0chZ97r934SY/6QqPgMAZvbOWg6wFZjjLvIjWFOfoBrPMvit4R6wkg/Ay5Sh
SbMqHR8Q/VXNz7ToD9zuxzHUkWQSRSchT5gMEQcdCVlgun40ar6y6+V9xOHOFftO5k1VpLMC6Qum
xXLVx5E0OvpF8PIBySwUDst7XfpfI1Vh0FRS3WeP9dYYp8cNTc89g37vvOQmt+503SRwh5lqrwSr
+oNY/KU/DU3RpWZ8pFkxODwlwcZHlUaZYinvaKW6qEJ5viQrIl+rA6JD3mdOZ8CfkMH6ynsoeyYc
JHIrvmOR3YIzwkg2KZcqJBSX9EiBNv6dmKsFHygJe8p6wwjPiQQ7k6EEvAMqIYC/48LG4vyYE2BW
CvU/HFLhqysWtzPG0/stG+EFn7RTQWREV3p4Phh65uuqh+xDK8u8LDn2PwGDoLjpaZfwJbAi2Pr4
Sf6jXdzd6rTGYIhPBxUFuH4H/27xgkjtLhmSF7dMoNTabGj0Y8hZNx4+K3jTKg30cUWAKvHJvYwo
NE5JQY3YipnmADfBhEPlXdwRrE7u5smwbkhBpTcWKLvOcq/3ilniKwhso9LHqDx4jSX8f122CZVQ
Hnk2+LGnjJn/BkRfDntLKaNTHnSqWaaVmzyrUpu7uPi2iDnyZg0QoD7dE1zePWtl52AtlfuugZol
N8jmdWSdmzIh1+cAFbtOhVLc96qSPYJncREPlAjEsL4HNHlYDNd5AFFCoRGn9fpYN9pqbOxV13Sj
fWss9zN44N3OhK3o5Z8CqVmtjHbMEVYavgHnVbMtuDzXMEnbYqRbEwEuU2624z3pM8XCc5hcZBul
xnaCQqFjFRmOziUvPCINhbvQjiQigOewb0QvTkg9b/G8JCjr+WBHIjMHv2orVT7ccwn4ga4h+XWl
O3oKeGlIBQsNSZehOqK/iQ==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
lz3B4KHX5z7HJK6kHiZGMmcEnUqLtTRT/n7HdY7szClNEEBtVq2UQW/wdwwMN27AnOLZPVfuS67c
Y2O4fk1xOw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
OUoXLY9rVEqAKiJgtR19Q8FIQUm9wPmLFXF2sem6w9gJVRflCYIHWjOAqv6eppRvqeqcjaja3KKN
iRxsDXzkmdVb18CNyYXYPgZU4MySqAPoAE8BZ3alC446EKqG5bo3Faah4iFiaQ2fsSYQDhznQFWV
FIedseAJGSJjdgeT43M=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
bHuGx6phwwi065A2gw0E1Tqc2OLDUoohEHY7mOoJcUQwvr9OEJ4yz01Uls3wx2UOc24N+ANXe8aM
YdyfwspjYSBviz8nI/XUT5fPMjNbtL8HFChLorcX+K00Sc+A9m1I9+5W+Wd6GLSKBCVYKnWRn9Os
rc68y/GTowadTW08aEEccqOavDD8XG+R6gQqGpi5C8xq75oqBRmE5yNpxpBXxQRz9mmAsJcZ773H
BpObF8UUngkYlRzDjfxz3vzf6lVAPrLm55l1zEsel1LRtdqlRT8kBTrz1kke43v4c6xNv0u+i1Y0
dvxmNCEmLNrwBuVbcA8l6Jjp0k0WZScEgrEOCA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
4sCk5d4E+rPjLUhUiUrzCNkXo2ztvWgfU4Ic3n3YDGHZzWC7cjzTKSJroiCXwtIaQEIL5FpdrGOo
eHf9JlqikZvG/pLSpSZr6BTZioOpsjgI4CJq9n0wGhpyClKm24hGzYEPH8AkBs4wVmgt4sOHvyYc
mYqTUQDFFlehrx6Wh0E=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
cjjanW9F+fseEMt2SDd6R3KYZVrfLHKeq8ULFHbP0E7BiwY4Vkec6zVJkc5FOAAhZdR5Ywc2FOnS
jk9bJ37QuAeSdAcrSzysHiIJYxA3kbMVuIa63kiSn3dKlLmPc1gZ2/UtM3HTBff0RPQzxl944kH8
SUid8bQM/bx+7wxLnTLuo6uTok/+c8ipzvZZ5iJ9DgzZyHiiuOtKu8JWNRVw1P5d1QqQT3EZ7Q8j
fnqcUNAmoR2w1hlmAhXTJgZbpiKUcMF+Y9/twpUzFl3rdEE6PKGzb5YQ/Re4uf+MJU96/KSTzmBR
Xfe8WjI4zLk+NlEm8eNku5cgYGTA1pkwApl+6w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 10960)
`protect data_block
PKlpisMKFINH4hoELw81Ae+vpIr0xr/BIQZISQh02QmAYRngfWchi+A+2gXJ0ErM+PWm3fbvLHaf
UADT/opvnHMCrmwuOuQX48J/a1y0sztlHgsA7XTu3se9+qgRV127lwvsMJp+UlinF11bhqOX4xmc
4cYuCuf0n1/UfLTSpbM+jwT6zHUTrOrKh7f9OpJ+QCgxfJhkQxcPhKOYBR3a8Dp06gydZjpwqjDq
tqPAaV6ta7+zR4nsr7KhZDk0KvhrrDa7oKo7kF4Yqt8L46maaQdVtdKjhVsrAGajIcZixhbXQBXC
KIPnejYm8Voo/+fTzj4QhGK3xFz3k3FowUtO5jGrPfd10F2QpBcb+lzujW5qHzaitTgU8nENP5TD
2NCNNxhTryKnoZbirc+DlOTjiUeVqWXdhzIhVjQE761Nzmz2eLo6N0V6ZXAbZPpb45msiAC4kCui
Sh4oKuCxBlkGt9/ew/UKSOYs4g/rPAUgxU5UJis2mhTgn8B70nZ6oe1lMoUjefiqYazyfy9m8vGS
EyNCpU32r32DOXi66vBKX3STS4MASUJIfYG+NpdusXHx8iM0GvteA1gnO9XlVeVucLuGO2H2TpmK
kNtPxJkOMbqjBOLbcw6u1MfDpAw0zM4S/xxxpD0m3R8p0n3wQdhT+VT41nAFYGTXHcj0UD1nlYk9
ZhVQDKcQaWJYd3lsXf/TNyrTovAkCZATosXG9/gmmkHeRoSaekH316l0DfUCazpMcUrE0gKAEV+2
bPeURMasKa3i1v3Q9v1COQBKJH2YL4cb4uW9dGdif1tBUmYddIAkEGs7ArxKb3pNxjuKy6V1DIMJ
XIpowUU4bXINHZzoB/7c/RgpIB6iGgafVpQoETmW/+DssTNucVCW8Kwh+UZiLWZ5G5mGaXr7TXxh
l0iz2gOWz3X8AT7JgFq6ItruuJBZ/ra5bWk//+vOxFoUCKV1+koz4Rlv7wpt7HJSSSICSO/akPPG
krhxjHXmtbWJG3FH017k263NKG9Ns/2xRZl8U4axgQLNB0HbhVWF0OYZ+XETB8sBwRGDNZEckCm9
Aw3jiTTqNStuhVhWvtAIv10Jys0Nc+/e3rHA9dM/mxvv3KhE21lKKzJQUi7wsX7SNfWjATofF63K
NWnw+8I7ds1IXKySwdS6BLd/OmygPsMAsrbK20V5vdtmT/W53scFA/dxCZlC4YOR5CkYnSs/jVpm
gZvD6tch6dfuDnLWz+E3D92qtGvA7i4MfEVC5e8ytxTrYjZFjTJyn8vA59PyMoPl+9YFy7afcqzl
aOvFPqWociBJgUDxdsRCC2+mgvRiJk+2m1vY7XgdaHH9I3WQjYYj9LzjD5Y7fozc7Pi4RLDETEyS
mxqQorH22rFzv/TOZPEwRLMD3o15g86d0S3yb2WlbPyN82LadclZ6/wlye7yVQo2MIlTZndWo3Pg
gGU3mPslBappcqCOJvD7U1JaXduNOMJ2wiR9hAR3UQn2FgdOP+snD5GiOqHRMMGBrBXL+IuOjDMK
aWoWzIJzTdx6Xn5VuLBp9ipme33V9FgzSzpWZV2TSRojdgbTHizXzQ0Mdy+VVfwDjdGZEcfrcgN9
jCG2vrSEqt0rjpFzjtQP9Z6txZqBSNuNRey2GvgfIP8fFmSL2fnhETfisPC/IHL/7XcUgD8AjU38
Wg70qui3u3p1R23i3EyXQvmt2mZG24g5gUR3QzJOh5OmpEUB16lF4rNxOLrT1IeCfqBVvWjzn7P1
F34PUqycxwmZhtbQSQbLIR1jUH5PLZzBC7gbXhDhTFW+tiM+HULrLfoYNLldm7LNPp+ky6qhN0B/
JlE2dsQKP4csNk61aq4pEAEfMgnXU5aYzNcK4NKuaOVAL1GWs+KIueLA+CGGft99LN/jEONqXEHs
VKeaLuijPqOX9aQi4aT3vBZK9mFkdNgb5SyXUzKY9FNevgM1hpT4vhjNK9U2fR2Y/H6ZSwl3RhND
+/S8Bl+byOrKBEXZ0J8MumniLa8f95UPXCIZjoK1vwoHjzMp1s5zx85kE5zgNnfH4Z0ZXwjG+rZL
esHmkBHf+58ZPZhC2mGNqZRsiDFbh4YW9Lmsxk5HuMKn4sixehuyLhv0YBEU/fWtAkrUM++gzgzz
8TZ1Ohg+yRaGpvTl3/SIXQrB+7lckwhHNTz9X9Jv4Kxgyz65E5odgHekq8x4oXEjfmg/f4iLDNez
0+ZF5IBM4XaFpkCvu3tEUpCBGBMyrlsCCpRtsDM72wgS6HvQ3vbpuwnSGOKr0tyFiHmn9SKRHYD4
cKrAr3epFd42s7HmNkWeBa5YaWvYhB+UxP/Ts5eahPKqvrGfVTEaNHCDjcoyQcCRybwEgt3eRnaO
bMj90rFhrCiG+i64aD2Vt1b8vyXy9/PCcKdkVsqNZIQB5mSaaK32i4tjULtMi3J3fbI/RGxkwwOB
TNyj2qkSAS0lO86+XU5DgcOeccIWC2Wh/CQmZg+03pXjqSTBxpPOjDhLK8xRI97F3jl7clYDwDkD
1Tk+czl1eG9ppfrFFOxloZrnANo+Q3iECpJGm2JUKLGfKuPZ8/wkuv4ZD7BrfB2Fubok3NUbs1s7
1A1FySkrL5P7ZJ9qukri8c/CPVWgcCaxqLzMDQp5iQfK85GlT/nj/IIX9+3XOm5YJRuEdQHnLqR/
SaHM/E6Mip3DNo9Ky8rFUhEu8YsTlg4rM7JIYTjReJE1+0PrwzG9mbOrzyuCQKonWCOeOxoEFMku
8T+TNqmafP3eFfg98fBOeFLFqvT02DO7XYXd3E53R/wjVoaiafIRw/hMKoOhDOsWcnn1tFicT2IG
/7P/Bg1Yg8/2yja22rQEa3m9gVlAhZHDQ5hER7kVxmzjrHlXIicasttA80b58eF/Yv2aYfyiLlg8
wIH4VyL+Af9Q/vgENpJBPQDhXAri0ZMGmwADU0FO2m92r1e5KYWcEyziZobv6yIClxuhoizCa6T+
hdH0OhLbgvd41Ox6j1TYJ5LX2WQRWXY/fa+NpnOKEWnR56S1oc/oKkiE0aj3WnenGnzgtYA1F5fQ
5lRBF7zzl5lfSS39xW4W7sDA7xB/AaC/uJLWR3HtyA/VwlEW/9bS87E79LbInytGvzcq0Yv3bMKy
wvt3lpHZUdUAYP9MRrMLIx87EHus5pa+vgLx5VIdGBXNOM+joU9Lz0ad1hNidgdL3x3Er+NyKTk3
rKcHwuMitlmMYGeUKM+0rQknIxD1oYz90AXE9GhZOYf+hwzsmFXgd/yNJKkxMTOYg/hUveuFjvjG
BlzjE+t4rs7QDwxHERt+RFxHQVC957Iyj/6GDXI302DCJHq1XLRz5UrFp+f7ZNtDyznJ5YJEkGd7
DpBGBmN2NEMe/Cay9og/1hQaatJ+95ueLNOJ2KmxiMKza4zsyiC36gF8JqXDj0YFZErM23T/qT/6
KPohLaYf2MoFetLzYCWPTs2/2zcF21VE2bfz26vGngL7YLxu/LmhoYMfoM4cyd/82JZSjwHRMrgM
+PMu5U6X7Ve/eFW2IMgxaUVOC2KrKbwT1/kMp3x2AFn1co4M4AglpGAZXnbJtpRD7otzyRuq1ehx
NjZFzzW4ltcaEnFI4ZtmhZ5LsHMVKKsYr7JkLFoNpVdOBOQRBR41UmYbI40j7xIz8xPcpQFRYLup
+FyJSf02AEjmTfuAcy4CfCSAnu28xxVj8zVnjKUuVfSy976CWwhl2L9aJHDSyEDmTwqRORriCgDg
nRtSNRdZNbDoY//6NqWZQrgxNpWQ3QLnJ1oNyHe/OkmoH5UwhFv8hxjUO+mYgZZXIBMkGAHE91qR
clEwV7vqi3lthQ8Z6jQaBeoPvgVaso2IOaP8jfJxPnz1wb83NvQ/5Cdkc3Ma7vhxBwCqvpsEOtnF
fYnvVZnuLKbs48vGloDR+o+JTkGCl3ApgQi/NoPxPVSkeUbwD4AAKrx+RkXxjdeqXEZqb5/hjlaU
XPc9WNziDhXZf0GKHRiPfYumoA7H0WtnpgSl/l9+8RIoBialvJuKA+93pkYWf+NhN2/YdtUVgM5m
Qke0RFt5ObsyT/GmsAdmucExDH3Ak0rB9pvgSFfNPDg+2ENl6a9zkWzh3kDNtxk5HgRgNUYrTV5e
6LNjoQ2Yk+y2K2oCG1iP50k+l1d96K6nkH6pG3S48irVuPIf200qWwN6ZSVvy4NgO5aklrn8/8w5
rbR3obr//OUT+5tGxaR/qYFMCVelp+6vbne4lGn6uygyLH9opDIcfCax2cJpJAedUQtJ7NgY+AwJ
vQDGVvC0fDV+ugGsS57+3fa5PNdzZs0GP6ftUJv7LNx1Fm3BIPFaW8brdqZOjLODAl518p/XSrqb
eI8KK+Mp4PuBC8uQd2QFZSb3qkxNir3YUWg1Kdfy4pCRPcsUBbSeGtrNKj4QvndOnojROIvEye8w
HhQqRjUxGs1eahR56q0S1wqIV68LgORIl9y7FGCfmu1DBSAIsTmWGiaShhDepXlwL+4WV97LP2JL
8XVdXQmbE2RMEhUhePmWCe74boG2BYSzth/uWyDumWgL2zYB+7fAXlH7Qvg1lm85Fkyy33sQuE9h
084Dak9V/q/G7WmTaTvCCXn+z+LBq7yAQz/BLL8BjbB7E1azlHQLKIIBT6W/5gtEsshlzcggXOqQ
RxZm53EHMBt12MOe8CA9tAWyX8BHsTpUavTvqQ3m+OLdKhVGIuD6kp+9htscDJSiqgpimLHFUyiZ
gnahr1x/tAiFAR0SOw/T40EK5v67CnJKdXk29xSGfvnIlzv1qd1WR4cGe6AGZPe95zPrQGHv/xUW
X5ufM1q+Dchcl1xOtkC/IwSnaHMjJWBE2q/8FDiKbEFRxV4HCerSEk6VsMHxhLgbdDWh3c7dFJ31
GIa+17B+U3eaog6sbtQSFEmOweZ24z28T9BNkrjSZyAzm62YsKttB0c7Z6JMyvIYhm0p23FIJyme
eYHT1YoPp5L/vLkZ/bjApX4Wt2iwIqsqTcuBGqqlWXcY8xyDhjlPAY3LHqs4pTTFVU/oWepXLQtn
rlu9kW4xqN8b5kdrjAi99pIG8z06r9b+CY7F3tQGg2fsSJrc0fpl8+LcV7rzdgVwXCT1PJDZWQtV
GeUkPsCQECyuQyiacqcYqnIq/+dPN29wM9CX56u5bFwn04oobN5ENOxdA9BP0pKl1cuzUTDgRRKY
qfSKu4iypVhqMIBgYCepT/VUsoxcdnFS380dituJ0e5SsNncVArtc7Pt7YNL31+cAyuQuwufnLcy
5yP0kWN+SDmpYYRZdJqItxvaaxVFy4w7yW7jbaJ8kZ8B4DmU2LIp14mEW2ScO2rWUNzKCUkuYJat
HnFteXKs6+vin2PKOp9EQX09nxNgB3aZod8LQgH3FDVEgPE9FjaG0OsTApIHfxIYypdlcRlaMJLA
UnhLgZAyUDhuqxi00yM4t+ySfakwHo6i+8d9WVbRbdcOZ7bSBNyaJ+b6lY1JoYBENkid+EpuJUqN
DYykchE6wzDdtu69rmN3IfYlgiVdCK3i4lTvk3hjb86vekhNivgVe14pV6pO3KgMpkE0b8Ctmhub
r81ILwkWyx5irNh/XGrw/mRfox5uUOPOBOJXrmwgm0K0ukuCyq+wLI08FW/lmpS0MBOO2OAOTyuX
J2v3Pvm2GyGF9I8yDfys38ytrPmz5Mgf0QJ1LcDWVYvYCGbftUrwIRqlMgv6fIjv8YfrvV6Ui8Jp
V8m92xMI5gNx0GfoolaHkllT+Dw7Z58QuAgCtDWtmBKzFEq6ZO2VBn8qlt5n3xMr0/IGXigfeHXQ
GgUuPmCla2kCWcylvDezgPIfF/ZMcq7lawUgu4i5Ew4t11yLb2FvWP0FWh6jRjzpXfZbJvK1fQvX
IF3C9w7AkzipStAkUybzG7E1jWfNh09JCjsqNBxKypW8PgArNf8h2pGxkHN0Kvhz7xcW/oTV4sxe
5QGixaoPS/EwqfXQQ9h4eMfN/XdgpO5hwHAcM/1c5qCHwSCEiBhoSOcXZRkHD2JEhWEjjup2Ymkh
Z0qZvJY0xEk52L/5bsqa9p0cgiv5nPPKV6vjBekVUVy/FQiBJ4mfEUZcW5hc1N6ifC7JcLYUS+c6
qvHQXRD4MUVO1CyVdLcP5ktObTDNR4omJCWAtcrUot+EbP0wTIEqaC1DwEhGwu/BR6KWuT3zocxz
aeRW2ZoaAFRcBuIp9ie0UN5x5A2lf1aqS4RE6giI3QWoRLlTlFBfb6Pst/UcFHCrtlTOWzmbhAvY
J0j8TGf4BJDrqtRq1go9ZaYezWuAvE4sTj8Hjw218/kJ/T3LmUNioSk7O2yLpoeIxwwz1Ktw1w1F
BRgWE2KoX7n5LrUIfk5oir7koUnuxLou0ourhd2NifpxTW6T8OSHLqGQIj+vS9/EjnDJMNCh3GIh
57GpdvYsx2x/BV9EMyCQ8z5ifledbJP6nt7sAhHtfZK/PGO/pfSRrbH8x0X/9qxWKs6fR7mNNzcE
l7UMw5wI11oqRrDg7aWQ1I1/RZHdNe/TWyy3CyLx2JTGGSiLqivGOYKlVdbQ3l4bV5LcUGz11Ksv
T3ewZ3joiDsbCscmqAmt39wDe6QRBsGgooSbjuJat4tXMqyZwfRFSv/MAEDhz/udrv2F3+Rd4VLU
cz11wRIYJYZjr69yJGjEIbQBs7nL/CgAruJZm7ObjDeZZWloeklL8igWN5jvu4vyMQuyETE7cyNE
erPqRzNY5odRKGtu/giHe1aBv9oTPLEIGgSdAnMLLNS3cIJUCRUI0ncWWvWTMpYU6XxFUqjvAaro
1hiRh5+v9nkIO/S6SXpGyJ3hA3ZwplUIARC2hVCnU+vydP90p+wSYtrt7/3gnu9N8w2tfUXSIWc0
7e2ZzjvfJsRsv+YD2gsqYxXLK1733I2JnweP9wiRyWOW+RIPv2DlTbLbURC3BeK4DAQLJBoOeijp
jK6yPjuizvcwNRRVRPFZI0XtkB/v6jBaqLHhgXlwQ1UBFbyrdq1B9Yj4dTV3Rb9pPz/N8TtuyEbR
wkWEX9IWZKgfdEe48EyU+zKNlb+SMyJGwYB50kBziMH4xTpWPb3CF3Imbs55TGpAcAf4GWGVXSrj
cvVDQPjTwaXBLN6EJWwQm6HEP4hHuuqhX5r15J71qc8rohYKb+0mUwcRlMm7H0CqQe38Gaov+wKD
cbtQQoN8bnI2PSLRGsfaRyS77jFiR6mU/WPmCKeSgBdUiHDkq/viPctOdkSmELw0u/usGtD1km3f
QWtBgDUPjPZPQ15Mlm3VY8wcadCwlZOwCWJO/gIyRBC/W3f0mt7POk4vs/lA3kJ6eOI/tJh+C5gs
wGyr+thLtXP2p91fGlRdq4Qp2l//8dSN6p8H7Q2cz1M8uQZ/Ld8Htwc9belyE9F7WuOSx0waZ8pX
bNlGhG6tFFqSB56/fKsQkRsBBFioULd/OGdOOhvorZImkr7je197GfT0u5rqwxhORdyXPXmC6ZKL
yW0aYS8I4vdHsRO3+jGG1yA67xz8AGr8hf+6Y6+qH4YNkvL73hvfJwd8xX9MfzhdtEm35iu9loEx
ACI/+oijas4IRx1NNMRhzmYxyhm5tcnp9u6jdsSoa1qtxGfUsxVm5qjH3QH95bYzKfucT4r4lSaG
EHhkg/EfU7Y2Jzb0f2TVBXrRkEREcx0EL4laXGYv63vNlRzF3mblbec0AdLf53rQuZw1UhLlom+u
q96kO2uk8cBZuD4gJQ/efNeddiuQ8MfXdgd0dE0Woy7dPsObYVsakLnRwbHuC42gpR6lzVF0JPcG
wBSTef5WhJvqLH0+z+sdlfmRGSNDd+aYsaipkxjFzhyfuehlGQJUC9qAt9Bjzc4kwoadfnpQOv7t
M553X54NHdSCfSON9OsaGB3r/nuN0/DxNannACHqWLJe0mC6/rdB3TBL5KgrL4DV6WAz2FNVoQit
llOHGd9IHx8dq8cyRF2vpODUf0phH2C4m/w1jvSzFj6n7J+lECZ86+m56GQuIQwxLIgfpJwX/JBi
WtCzhESNE3eghLiWy25fdpwA5VDbbrpqjp/R7uB2ZmBth1739kayuB0cCYulv/H7z+iUWH/XplPQ
bhC2jH4iY3uCFsSr94/j6aeMBbl+yW0PHz6rv1bh70//ogonITU9SQKVSNzDlL+hwLoEZHVvjydV
7BbwYYvnV592lnK9gkA12sgBMKccTooCh8vOLFgT7MbJCiFk3N9oTT2ehUhmJENHguCSbrFTcf+j
NbIg8W7CtKkzDGUjVp74chbN5m6L0WBXPMG0E0yfRGUDIBEHNSjEMvxqChpVw8wQj3svpG095R+D
H626lgq/S1HMSJ+h/RB07Ueow2zQHmGmldLt7fXWDeboQKWidXX7RreXQD6gOhn1u2zA91wIYRUW
7jGqhFhr+3GeuXShjBSqsjntf4tMMI0XvlaaqXsTsjeNWejOb3Ew1WS1f9gAmvfLB9D+noTdRByg
MueMATiiyOAr/QBFPKHIDcqcajamoq7Ct3bEBgUcCv3U85C7vhp2XhBStkrrpg7zZbyrSw4BCobT
cCCOJpil6P/p+B3c5B8uRRGkTakvEqYi+dUBZXCBaWFvnLYdAIWUcm4J8hhk2RhQF5LURnXtJI9x
DW7hpZFoRb60TCVCq7nlglEv7/ij20atlk6063XIg2LDKboea5301V6xJYGL8tUDTkYzsNVheWEJ
Tl0zbVaFs0KjDVBBEX27mLDscnx/NV9N5nXVxTBxPSGqujI56BEbAjxCDA+ovYD9OX0SGXV+NHbE
5DD1XflyovsD7kPYH2e77gRrrII/+eAysylOASvZdorSrmSLgyjg234TLiH+zHHCFYFG9Dchp1we
T+lrYmcBBwmGexrRHCFBLo8mOJOGA2u1A5PQAQ1GAndc6ujv6dp6dvQ+TfWSHV73BhZFi7/2eps7
40SaN1NMh8X4cqPupeyd+1eQx2D9oQLLPQIDQ2uCSE81u0hBVFhCgh99JejX/mNpPj7mo8o4oI5R
l+f+bCaBq6Rkr4e+OYLGFavsh7on4pxyiZDCdk90yzNeHusEwSRwJ/uPON43rXS/rTE03ZvJ8592
6hLcXJTdypAszOSSn2dHh73nRyq3XBBZMXdwXWCs3cvD7+A9b/YDNf2pISZuC84pRl1zO6c3fzQS
yVaIm2AgfEPuaavbbzopuAnUifHKZpMwQ+beSaxrjNCmBu2mhtfY/q0nTqW7OrUOVZ0nrUp+VuJD
H+sq9iWa6ja28a0wE1ua5ZjPqhhSA1/5SPfmg8L2b0JiKVhyMBDRpf6DILd1SzINrzfBnyaYAetu
pNipTsT0WPracGVC44OU+6gG772lESl2+qkaXQ70aRSxHEX24Jn3zDlH+HfCDwY+1hd4pNFDBWER
gPr+59hVrbx2HQ69CyVutbk6hEZT2DhbG8egJwWexQ25MdpPWCLDxgzI+8aDXsFWd2Apbf8uvb6V
0jLOwIKTZpbrUb+W4lggjirrEVib/8EtnYLwEdIb25QRuQHB1fXVvysgwRvGiauKexwNwynriXTM
qfN2HoGhjZdpqLAlMht3JU+/lksjBO/En7us2Y37gZ2rSIdED3b77jGFXkOEd8tbQRgxqBPDVqCz
Y9yqqSF964YyE1s3f4AMobJ1/05t2zR4v7i7/kXXnozUtSiBSMbUQOF4y9wZkA91sveIg1FqpKrs
R7YE7CX/Kx0vyAKGTfT0myGtWlL6e8UXfKwTK9TchNgNsm+9SCvUGxKnbUUrwmBqOOk4m7ou+mv2
K5mJd1dVvGl35Jse9qMeLc3YT3/bnhWp6SDFXu1yK/vzciDPdq0j3Au5QqXDyxW1iG7aPG0d8mys
8/Yz6CwvPSH0mGXIztphFuNRjZD8k0C5eFzlXPWA+7MdO99D0PaBmem5YIkndK5LSHKtKrS41X3p
Moiveo1CyLn8taaqEgV7Brun8tupPoCQpvrggiPhWrEPKkvpLk9OCIXs//RGJ+SPcA81+ju8Y/aE
JL0dpPrZly5DVcw4fzHgdaQvd2x0ybGfGSgH4ZLxrIOZem91guNF7KJSa7Gino17BAIsSZfmBiEk
mSF5K6hSdogwLAAtnvlng0kOjKQ9uMQAvmKymI16XFvkA74auzFG3faT3Rr4NvQx5SmVrGEqMUYU
K8tDFIFbzUiym8KOTGbpDggXV+QOATPk8ibZwxGRaMMwfc8sWvALcj5Wz13JyYaRdo88uJeZaroi
0l1JL3sDSfc9jVCX7reBWN1+vZn7cITA1eMK1Gb1O36va8EXJda+TqWTQZlNvzZN8kQp2CIx/TEM
wCoLD4K6utBVGXiH6rjOAY6N04popuI0XjVzGU7aj7vt1Cup0+BXM+/x8PflGD8R+s+ikkUmaM1H
wY8VmV4k8lKBNpslYp7OBXjX6YHlP05R0q4WSTM1dSKULddby7dynXWtgscexOqjIF5DwugnfxDD
VK/0xkLCjACQIl9a2ZHKYlHcZCbGBupoUSZmVWEoxzuTeZD2VDNfC+HZqHV1nJXxLrS8+l0TgaRn
P4xn/Syt6pcmOWustVWKZj8pnryKhfHltFcz9gdVoFNP9WZ+89ScqAZ3XEBUdpLnGnhBmnHuTU40
gocoxNVuXxjjvE9TsUcZFCBpaq8Q4dfnkK1LIfvLQvDsva8RtZcpxvWY/uMktMH1sTakPWlBeNKh
1+kV5nB4l0abx3umSsE455ndxAmPbFNc0NB/KcvqxK7w1YESlL4+LAK0+rZYxHFju0lH40XuYlBA
u4ItbtNPY8qP8NLR10BxUio+KC4Pl3yUoW1+0y2KfboQVgsn5TE1kzwZsuMvpCBUCiXis7UjUUC3
ukYyqeRjLunvcHARpvjUky2JxiVTN2gBbXpihny5aEac4F/J3RDISf3dfVEH+euX4cIB4YFIZ12U
Mu5m1SosnwfWE15Vckunjv48Aws9UmPlinW6Z6YBobgG7RtSfZBlN6KiuKHXwIhhOnV9Pk51x1P2
ien62lbp63nEPT4zREm5k+UEpHQNYu8TD8pZ2ziZ0uULcmlq8V1VXpvsuzCDjCIAVKpuAONhF6db
5xf5iTcCa31WbB+9tzRn5fPxYmf1JlB1Db7PAgAuowWbNUA8qUlm48m9+15MFgPJ71lnO80TR7/F
YrYXpJIrdd0r0XvsTVyWag8JuEtMe9wF2xxGi3yfwG9yYDedoBrdT8muhe35R0P/AlClHNvvQLm+
toSeViEsLphU3Q6mbsLd3selKA9yxlkkW0WdMe5qP47SbgpP9mJafJRTrvbdvVFpO+Bo5EGKSXY0
g+xtYrc8pZz20T9g0AZAT5kR26urWbjWVQRx9haThrUSM1cH8uF8dRv70Ary6qo+skBn2G0Fl8Zc
WegXXE9rEFlsetJ2iHB36ft2UEomSo8cou5yhXaejCqHaYW/fvTzaql5WbsStZrgiQ+K8xQFNfjJ
NLpFbcSQmN4TFrjGWkvvmvMJBIp3t6vOEjxbXMQCHz6sRl+3md+y1u6cQWKZMNksN66juJWrifXh
qZ9POb3YYfwlLo9BXHytbsrh4UxasdszyO9finWuRMOfESk/T2OIRRhap9eSgWWeuO/qzvMOnAu3
qe5bwyHeXH24XXa+rBeNbp9Dg6AdFWOV2bV6+2EdyW2eEx4U+gL+Fo4Kn1putFOCU+sOzgDrxOyy
ymOxC/ldmRP2DlkzcLedswyhkT2JWrrkxLMxtrfQjbcqEN9bMoZanygxScK8nUi8WO1j1GolEN0d
ARjC10GAnGTJWJyGu8ygM37P/xgso0cAI0eZrhAQQhiNqmeqSo89AcYJcYE+6lhyxqVT4UDPABop
Rmnv6sI6wOzqkEVaNZioamQ086DR45y2VWSdxuWr0snXt1OQb73qZHDPTopmsy5UbjbjeYNGVOk+
aEbroV1Jjuz2SbQlfO2KhYD8O6ARFvqf1QZywAFtoTFogsnyjmJG8DMmjXKN9AI0QoMP2XSJeOsJ
B36DHtf0Sjuo4i8g3jKFL1lJJcPdvFvaS8IjIMocR1L3rpajih4Q0yQMIlJhua9jEGSSLPBdf4/+
14N/QIVFypsQcF5GVjqz39sVj9sdU8wZnbZyOzmsi9fmOc6Q18dqh1HjMdgO0mnK9hUMBChjTr0C
cm/OvX0Z3eRy7ygbmP49loQq8ur7RzzoUCDZV0sYMqCGutELkXQOoFWFDNyRrlU1F8P9H1gMZl1X
Nxm8o1KPyWlJW4QvC0m/UEgZtwyXnEuZo/hOb86T8Z5MUciyYu4kGrUKXlvuVDkCe5vzscmbCh1w
bYYRqvGZkFODdM+5FHJ2Y62HOzcsPVYt3c9TWLMuHovGtUMgV6wb5xmNKTnE4SX8e6EHqntsgtZj
WdaYrEKZ/cWxLqTUxMqJxlW7GDAdw2hGrgrgwB1so4GHIpTx0IZX0MDiWbCcMy/KJvj5xgQRIgK3
vXYHUx/gC8a9P4gGgs3LgAHvdB2izugj1kGYatH2yKvijjf+h5ZoUQVbzh5akl1n38GpFr4THdHD
Dti8a6oeKGKIexKsKva8OSWKmIrssX0698xbofuaJxMd0//mdvOvq42uLtcV7b+vDsYF7vT4TGmT
uB+hWUuJpxE8zeOkvCOLe0/xdYXdwjCSMLIqZgnh+OS2T4kPOSUitFEk5XxKfrddvEZ8m4PWBZli
Cu91XGqmYyM6fUvo++M7PktrpHLaiG4KG3J5HfHhlGMMs821j/Eqmlm/TEUKo56L4LPirFuJTmC7
Zu1qR96GMJ2Jm1bLCqwv5CUEmakwg+WReLvEiUXSroilhQ0yPB0uQ5FtqE5oPZ7025m5sgiJEHb8
J6TCgNA8Y6PTt7aud5cF7gUUiCOU5vpPD+96si2qUjUQPgLCz+w5SvS8Daep9JqHQImIeidQfkLS
IDo9A0S3YlD92lFhtb7QB075YS6vUttNd6tSpMXxrCvos/xsNRFWPHKD94ORf1y4FTM1pqhhg+82
/K6U+6RQEKDsfCxqWhDwvijz1nAuP8p5LCcR2lDPjfIMg/2kpz9ixrfSmsS9+NRNht2vF81xDDgF
EGaiWjGalIGjOCYJYBLmvaeLkG2EM0rRahPaDsXmZqm03x6hrBFkKaCv4z/vG9xiYt1R+z5U3PFC
Bm4De65ly9OJrax4PLoMrqSDY1KGOIbe49WWxPlxazBWp3EEtu/hncC7kZkNmlvMPgjOoxK5zxpb
1rkczZ3tvJyN9Hq11h9GGA/EIHtD6JPhESyg/dHKgF23NplGVN08W37JlceAR/ZcnY0nMewkSKBY
9kSovzAZTkvY7O8HrMbq7Q+02qp+MR9FMBOpaGPh4HXuerJKHAcyLIIn9rz2aLo4I/sm5IeqNCSo
MD2aAxbaEqmbds59edaN5g8j6/KFtOia2f4+/RvN1nL2oR85VX8ANVbKJaLeCL5r7B17P8qmIGLz
NQweh39StjJy/7kCcZ2776DPOHRekRRv2yq7XkYNHk9SliqrTBMC9JYrFQn72pY4A/9yIrheGzBZ
7UWV2a/INBYy7g5VE01tcB5BPLOBDZtDiiDki9cw/dTnoDLdSgqNA2FCeBJoAOFAgRqYZ0LUw/qj
Uej/OhPbuNlHYTx4FBxjeGkK4iAmGATcP/af3EAuB3c8i7VTK+6n45M7XFamxeDVO9Z0AcE/dUfs
5E9V0H9SD5mFel97df+V4fzhPcjVLugVlBM9p4slPmRytqZmRqGuVz7GoqntDEBkLqLjQDnc2/7E
EKa7Z+yn4XrqX5sY0chZ97r934SY/6QqPgMAZvbOWg6wFZjjLvIjWFOfoBrPMvit4R6wkg/Ay5Sh
SbMqHR8Q/VXNz7ToD9zuxzHUkWQSRSchT5gMEQcdCVlgun40ar6y6+V9xOHOFftO5k1VpLMC6Qum
xXLVx5E0OvpF8PIBySwUDst7XfpfI1Vh0FRS3WeP9dYYp8cNTc89g37vvOQmt+503SRwh5lqrwSr
+oNY/KU/DU3RpWZ8pFkxODwlwcZHlUaZYinvaKW6qEJ5viQrIl+rA6JD3mdOZ8CfkMH6ynsoeyYc
JHIrvmOR3YIzwkg2KZcqJBSX9EiBNv6dmKsFHygJe8p6wwjPiQQ7k6EEvAMqIYC/48LG4vyYE2BW
CvU/HFLhqysWtzPG0/stG+EFn7RTQWREV3p4Phh65uuqh+xDK8u8LDn2PwGDoLjpaZfwJbAi2Pr4
Sf6jXdzd6rTGYIhPBxUFuH4H/27xgkjtLhmSF7dMoNTabGj0Y8hZNx4+K3jTKg30cUWAKvHJvYwo
NE5JQY3YipnmADfBhEPlXdwRrE7u5smwbkhBpTcWKLvOcq/3ilniKwhso9LHqDx4jSX8f122CZVQ
Hnk2+LGnjJn/BkRfDntLKaNTHnSqWaaVmzyrUpu7uPi2iDnyZg0QoD7dE1zePWtl52AtlfuugZol
N8jmdWSdmzIh1+cAFbtOhVLc96qSPYJncREPlAjEsL4HNHlYDNd5AFFCoRGn9fpYN9pqbOxV13Sj
fWss9zN44N3OhK3o5Z8CqVmtjHbMEVYavgHnVbMtuDzXMEnbYqRbEwEuU2624z3pM8XCc5hcZBul
xnaCQqFjFRmOziUvPCINhbvQjiQigOewb0QvTkg9b/G8JCjr+WBHIjMHv2orVT7ccwn4ga4h+XWl
O3oKeGlIBQsNSZehOqK/iQ==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
lz3B4KHX5z7HJK6kHiZGMmcEnUqLtTRT/n7HdY7szClNEEBtVq2UQW/wdwwMN27AnOLZPVfuS67c
Y2O4fk1xOw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
OUoXLY9rVEqAKiJgtR19Q8FIQUm9wPmLFXF2sem6w9gJVRflCYIHWjOAqv6eppRvqeqcjaja3KKN
iRxsDXzkmdVb18CNyYXYPgZU4MySqAPoAE8BZ3alC446EKqG5bo3Faah4iFiaQ2fsSYQDhznQFWV
FIedseAJGSJjdgeT43M=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
bHuGx6phwwi065A2gw0E1Tqc2OLDUoohEHY7mOoJcUQwvr9OEJ4yz01Uls3wx2UOc24N+ANXe8aM
YdyfwspjYSBviz8nI/XUT5fPMjNbtL8HFChLorcX+K00Sc+A9m1I9+5W+Wd6GLSKBCVYKnWRn9Os
rc68y/GTowadTW08aEEccqOavDD8XG+R6gQqGpi5C8xq75oqBRmE5yNpxpBXxQRz9mmAsJcZ773H
BpObF8UUngkYlRzDjfxz3vzf6lVAPrLm55l1zEsel1LRtdqlRT8kBTrz1kke43v4c6xNv0u+i1Y0
dvxmNCEmLNrwBuVbcA8l6Jjp0k0WZScEgrEOCA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
4sCk5d4E+rPjLUhUiUrzCNkXo2ztvWgfU4Ic3n3YDGHZzWC7cjzTKSJroiCXwtIaQEIL5FpdrGOo
eHf9JlqikZvG/pLSpSZr6BTZioOpsjgI4CJq9n0wGhpyClKm24hGzYEPH8AkBs4wVmgt4sOHvyYc
mYqTUQDFFlehrx6Wh0E=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
cjjanW9F+fseEMt2SDd6R3KYZVrfLHKeq8ULFHbP0E7BiwY4Vkec6zVJkc5FOAAhZdR5Ywc2FOnS
jk9bJ37QuAeSdAcrSzysHiIJYxA3kbMVuIa63kiSn3dKlLmPc1gZ2/UtM3HTBff0RPQzxl944kH8
SUid8bQM/bx+7wxLnTLuo6uTok/+c8ipzvZZ5iJ9DgzZyHiiuOtKu8JWNRVw1P5d1QqQT3EZ7Q8j
fnqcUNAmoR2w1hlmAhXTJgZbpiKUcMF+Y9/twpUzFl3rdEE6PKGzb5YQ/Re4uf+MJU96/KSTzmBR
Xfe8WjI4zLk+NlEm8eNku5cgYGTA1pkwApl+6w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 10960)
`protect data_block
PKlpisMKFINH4hoELw81Ae+vpIr0xr/BIQZISQh02QmAYRngfWchi+A+2gXJ0ErM+PWm3fbvLHaf
UADT/opvnHMCrmwuOuQX48J/a1y0sztlHgsA7XTu3se9+qgRV127lwvsMJp+UlinF11bhqOX4xmc
4cYuCuf0n1/UfLTSpbM+jwT6zHUTrOrKh7f9OpJ+QCgxfJhkQxcPhKOYBR3a8Dp06gydZjpwqjDq
tqPAaV6ta7+zR4nsr7KhZDk0KvhrrDa7oKo7kF4Yqt8L46maaQdVtdKjhVsrAGajIcZixhbXQBXC
KIPnejYm8Voo/+fTzj4QhGK3xFz3k3FowUtO5jGrPfd10F2QpBcb+lzujW5qHzaitTgU8nENP5TD
2NCNNxhTryKnoZbirc+DlOTjiUeVqWXdhzIhVjQE761Nzmz2eLo6N0V6ZXAbZPpb45msiAC4kCui
Sh4oKuCxBlkGt9/ew/UKSOYs4g/rPAUgxU5UJis2mhTgn8B70nZ6oe1lMoUjefiqYazyfy9m8vGS
EyNCpU32r32DOXi66vBKX3STS4MASUJIfYG+NpdusXHx8iM0GvteA1gnO9XlVeVucLuGO2H2TpmK
kNtPxJkOMbqjBOLbcw6u1MfDpAw0zM4S/xxxpD0m3R8p0n3wQdhT+VT41nAFYGTXHcj0UD1nlYk9
ZhVQDKcQaWJYd3lsXf/TNyrTovAkCZATosXG9/gmmkHeRoSaekH316l0DfUCazpMcUrE0gKAEV+2
bPeURMasKa3i1v3Q9v1COQBKJH2YL4cb4uW9dGdif1tBUmYddIAkEGs7ArxKb3pNxjuKy6V1DIMJ
XIpowUU4bXINHZzoB/7c/RgpIB6iGgafVpQoETmW/+DssTNucVCW8Kwh+UZiLWZ5G5mGaXr7TXxh
l0iz2gOWz3X8AT7JgFq6ItruuJBZ/ra5bWk//+vOxFoUCKV1+koz4Rlv7wpt7HJSSSICSO/akPPG
krhxjHXmtbWJG3FH017k263NKG9Ns/2xRZl8U4axgQLNB0HbhVWF0OYZ+XETB8sBwRGDNZEckCm9
Aw3jiTTqNStuhVhWvtAIv10Jys0Nc+/e3rHA9dM/mxvv3KhE21lKKzJQUi7wsX7SNfWjATofF63K
NWnw+8I7ds1IXKySwdS6BLd/OmygPsMAsrbK20V5vdtmT/W53scFA/dxCZlC4YOR5CkYnSs/jVpm
gZvD6tch6dfuDnLWz+E3D92qtGvA7i4MfEVC5e8ytxTrYjZFjTJyn8vA59PyMoPl+9YFy7afcqzl
aOvFPqWociBJgUDxdsRCC2+mgvRiJk+2m1vY7XgdaHH9I3WQjYYj9LzjD5Y7fozc7Pi4RLDETEyS
mxqQorH22rFzv/TOZPEwRLMD3o15g86d0S3yb2WlbPyN82LadclZ6/wlye7yVQo2MIlTZndWo3Pg
gGU3mPslBappcqCOJvD7U1JaXduNOMJ2wiR9hAR3UQn2FgdOP+snD5GiOqHRMMGBrBXL+IuOjDMK
aWoWzIJzTdx6Xn5VuLBp9ipme33V9FgzSzpWZV2TSRojdgbTHizXzQ0Mdy+VVfwDjdGZEcfrcgN9
jCG2vrSEqt0rjpFzjtQP9Z6txZqBSNuNRey2GvgfIP8fFmSL2fnhETfisPC/IHL/7XcUgD8AjU38
Wg70qui3u3p1R23i3EyXQvmt2mZG24g5gUR3QzJOh5OmpEUB16lF4rNxOLrT1IeCfqBVvWjzn7P1
F34PUqycxwmZhtbQSQbLIR1jUH5PLZzBC7gbXhDhTFW+tiM+HULrLfoYNLldm7LNPp+ky6qhN0B/
JlE2dsQKP4csNk61aq4pEAEfMgnXU5aYzNcK4NKuaOVAL1GWs+KIueLA+CGGft99LN/jEONqXEHs
VKeaLuijPqOX9aQi4aT3vBZK9mFkdNgb5SyXUzKY9FNevgM1hpT4vhjNK9U2fR2Y/H6ZSwl3RhND
+/S8Bl+byOrKBEXZ0J8MumniLa8f95UPXCIZjoK1vwoHjzMp1s5zx85kE5zgNnfH4Z0ZXwjG+rZL
esHmkBHf+58ZPZhC2mGNqZRsiDFbh4YW9Lmsxk5HuMKn4sixehuyLhv0YBEU/fWtAkrUM++gzgzz
8TZ1Ohg+yRaGpvTl3/SIXQrB+7lckwhHNTz9X9Jv4Kxgyz65E5odgHekq8x4oXEjfmg/f4iLDNez
0+ZF5IBM4XaFpkCvu3tEUpCBGBMyrlsCCpRtsDM72wgS6HvQ3vbpuwnSGOKr0tyFiHmn9SKRHYD4
cKrAr3epFd42s7HmNkWeBa5YaWvYhB+UxP/Ts5eahPKqvrGfVTEaNHCDjcoyQcCRybwEgt3eRnaO
bMj90rFhrCiG+i64aD2Vt1b8vyXy9/PCcKdkVsqNZIQB5mSaaK32i4tjULtMi3J3fbI/RGxkwwOB
TNyj2qkSAS0lO86+XU5DgcOeccIWC2Wh/CQmZg+03pXjqSTBxpPOjDhLK8xRI97F3jl7clYDwDkD
1Tk+czl1eG9ppfrFFOxloZrnANo+Q3iECpJGm2JUKLGfKuPZ8/wkuv4ZD7BrfB2Fubok3NUbs1s7
1A1FySkrL5P7ZJ9qukri8c/CPVWgcCaxqLzMDQp5iQfK85GlT/nj/IIX9+3XOm5YJRuEdQHnLqR/
SaHM/E6Mip3DNo9Ky8rFUhEu8YsTlg4rM7JIYTjReJE1+0PrwzG9mbOrzyuCQKonWCOeOxoEFMku
8T+TNqmafP3eFfg98fBOeFLFqvT02DO7XYXd3E53R/wjVoaiafIRw/hMKoOhDOsWcnn1tFicT2IG
/7P/Bg1Yg8/2yja22rQEa3m9gVlAhZHDQ5hER7kVxmzjrHlXIicasttA80b58eF/Yv2aYfyiLlg8
wIH4VyL+Af9Q/vgENpJBPQDhXAri0ZMGmwADU0FO2m92r1e5KYWcEyziZobv6yIClxuhoizCa6T+
hdH0OhLbgvd41Ox6j1TYJ5LX2WQRWXY/fa+NpnOKEWnR56S1oc/oKkiE0aj3WnenGnzgtYA1F5fQ
5lRBF7zzl5lfSS39xW4W7sDA7xB/AaC/uJLWR3HtyA/VwlEW/9bS87E79LbInytGvzcq0Yv3bMKy
wvt3lpHZUdUAYP9MRrMLIx87EHus5pa+vgLx5VIdGBXNOM+joU9Lz0ad1hNidgdL3x3Er+NyKTk3
rKcHwuMitlmMYGeUKM+0rQknIxD1oYz90AXE9GhZOYf+hwzsmFXgd/yNJKkxMTOYg/hUveuFjvjG
BlzjE+t4rs7QDwxHERt+RFxHQVC957Iyj/6GDXI302DCJHq1XLRz5UrFp+f7ZNtDyznJ5YJEkGd7
DpBGBmN2NEMe/Cay9og/1hQaatJ+95ueLNOJ2KmxiMKza4zsyiC36gF8JqXDj0YFZErM23T/qT/6
KPohLaYf2MoFetLzYCWPTs2/2zcF21VE2bfz26vGngL7YLxu/LmhoYMfoM4cyd/82JZSjwHRMrgM
+PMu5U6X7Ve/eFW2IMgxaUVOC2KrKbwT1/kMp3x2AFn1co4M4AglpGAZXnbJtpRD7otzyRuq1ehx
NjZFzzW4ltcaEnFI4ZtmhZ5LsHMVKKsYr7JkLFoNpVdOBOQRBR41UmYbI40j7xIz8xPcpQFRYLup
+FyJSf02AEjmTfuAcy4CfCSAnu28xxVj8zVnjKUuVfSy976CWwhl2L9aJHDSyEDmTwqRORriCgDg
nRtSNRdZNbDoY//6NqWZQrgxNpWQ3QLnJ1oNyHe/OkmoH5UwhFv8hxjUO+mYgZZXIBMkGAHE91qR
clEwV7vqi3lthQ8Z6jQaBeoPvgVaso2IOaP8jfJxPnz1wb83NvQ/5Cdkc3Ma7vhxBwCqvpsEOtnF
fYnvVZnuLKbs48vGloDR+o+JTkGCl3ApgQi/NoPxPVSkeUbwD4AAKrx+RkXxjdeqXEZqb5/hjlaU
XPc9WNziDhXZf0GKHRiPfYumoA7H0WtnpgSl/l9+8RIoBialvJuKA+93pkYWf+NhN2/YdtUVgM5m
Qke0RFt5ObsyT/GmsAdmucExDH3Ak0rB9pvgSFfNPDg+2ENl6a9zkWzh3kDNtxk5HgRgNUYrTV5e
6LNjoQ2Yk+y2K2oCG1iP50k+l1d96K6nkH6pG3S48irVuPIf200qWwN6ZSVvy4NgO5aklrn8/8w5
rbR3obr//OUT+5tGxaR/qYFMCVelp+6vbne4lGn6uygyLH9opDIcfCax2cJpJAedUQtJ7NgY+AwJ
vQDGVvC0fDV+ugGsS57+3fa5PNdzZs0GP6ftUJv7LNx1Fm3BIPFaW8brdqZOjLODAl518p/XSrqb
eI8KK+Mp4PuBC8uQd2QFZSb3qkxNir3YUWg1Kdfy4pCRPcsUBbSeGtrNKj4QvndOnojROIvEye8w
HhQqRjUxGs1eahR56q0S1wqIV68LgORIl9y7FGCfmu1DBSAIsTmWGiaShhDepXlwL+4WV97LP2JL
8XVdXQmbE2RMEhUhePmWCe74boG2BYSzth/uWyDumWgL2zYB+7fAXlH7Qvg1lm85Fkyy33sQuE9h
084Dak9V/q/G7WmTaTvCCXn+z+LBq7yAQz/BLL8BjbB7E1azlHQLKIIBT6W/5gtEsshlzcggXOqQ
RxZm53EHMBt12MOe8CA9tAWyX8BHsTpUavTvqQ3m+OLdKhVGIuD6kp+9htscDJSiqgpimLHFUyiZ
gnahr1x/tAiFAR0SOw/T40EK5v67CnJKdXk29xSGfvnIlzv1qd1WR4cGe6AGZPe95zPrQGHv/xUW
X5ufM1q+Dchcl1xOtkC/IwSnaHMjJWBE2q/8FDiKbEFRxV4HCerSEk6VsMHxhLgbdDWh3c7dFJ31
GIa+17B+U3eaog6sbtQSFEmOweZ24z28T9BNkrjSZyAzm62YsKttB0c7Z6JMyvIYhm0p23FIJyme
eYHT1YoPp5L/vLkZ/bjApX4Wt2iwIqsqTcuBGqqlWXcY8xyDhjlPAY3LHqs4pTTFVU/oWepXLQtn
rlu9kW4xqN8b5kdrjAi99pIG8z06r9b+CY7F3tQGg2fsSJrc0fpl8+LcV7rzdgVwXCT1PJDZWQtV
GeUkPsCQECyuQyiacqcYqnIq/+dPN29wM9CX56u5bFwn04oobN5ENOxdA9BP0pKl1cuzUTDgRRKY
qfSKu4iypVhqMIBgYCepT/VUsoxcdnFS380dituJ0e5SsNncVArtc7Pt7YNL31+cAyuQuwufnLcy
5yP0kWN+SDmpYYRZdJqItxvaaxVFy4w7yW7jbaJ8kZ8B4DmU2LIp14mEW2ScO2rWUNzKCUkuYJat
HnFteXKs6+vin2PKOp9EQX09nxNgB3aZod8LQgH3FDVEgPE9FjaG0OsTApIHfxIYypdlcRlaMJLA
UnhLgZAyUDhuqxi00yM4t+ySfakwHo6i+8d9WVbRbdcOZ7bSBNyaJ+b6lY1JoYBENkid+EpuJUqN
DYykchE6wzDdtu69rmN3IfYlgiVdCK3i4lTvk3hjb86vekhNivgVe14pV6pO3KgMpkE0b8Ctmhub
r81ILwkWyx5irNh/XGrw/mRfox5uUOPOBOJXrmwgm0K0ukuCyq+wLI08FW/lmpS0MBOO2OAOTyuX
J2v3Pvm2GyGF9I8yDfys38ytrPmz5Mgf0QJ1LcDWVYvYCGbftUrwIRqlMgv6fIjv8YfrvV6Ui8Jp
V8m92xMI5gNx0GfoolaHkllT+Dw7Z58QuAgCtDWtmBKzFEq6ZO2VBn8qlt5n3xMr0/IGXigfeHXQ
GgUuPmCla2kCWcylvDezgPIfF/ZMcq7lawUgu4i5Ew4t11yLb2FvWP0FWh6jRjzpXfZbJvK1fQvX
IF3C9w7AkzipStAkUybzG7E1jWfNh09JCjsqNBxKypW8PgArNf8h2pGxkHN0Kvhz7xcW/oTV4sxe
5QGixaoPS/EwqfXQQ9h4eMfN/XdgpO5hwHAcM/1c5qCHwSCEiBhoSOcXZRkHD2JEhWEjjup2Ymkh
Z0qZvJY0xEk52L/5bsqa9p0cgiv5nPPKV6vjBekVUVy/FQiBJ4mfEUZcW5hc1N6ifC7JcLYUS+c6
qvHQXRD4MUVO1CyVdLcP5ktObTDNR4omJCWAtcrUot+EbP0wTIEqaC1DwEhGwu/BR6KWuT3zocxz
aeRW2ZoaAFRcBuIp9ie0UN5x5A2lf1aqS4RE6giI3QWoRLlTlFBfb6Pst/UcFHCrtlTOWzmbhAvY
J0j8TGf4BJDrqtRq1go9ZaYezWuAvE4sTj8Hjw218/kJ/T3LmUNioSk7O2yLpoeIxwwz1Ktw1w1F
BRgWE2KoX7n5LrUIfk5oir7koUnuxLou0ourhd2NifpxTW6T8OSHLqGQIj+vS9/EjnDJMNCh3GIh
57GpdvYsx2x/BV9EMyCQ8z5ifledbJP6nt7sAhHtfZK/PGO/pfSRrbH8x0X/9qxWKs6fR7mNNzcE
l7UMw5wI11oqRrDg7aWQ1I1/RZHdNe/TWyy3CyLx2JTGGSiLqivGOYKlVdbQ3l4bV5LcUGz11Ksv
T3ewZ3joiDsbCscmqAmt39wDe6QRBsGgooSbjuJat4tXMqyZwfRFSv/MAEDhz/udrv2F3+Rd4VLU
cz11wRIYJYZjr69yJGjEIbQBs7nL/CgAruJZm7ObjDeZZWloeklL8igWN5jvu4vyMQuyETE7cyNE
erPqRzNY5odRKGtu/giHe1aBv9oTPLEIGgSdAnMLLNS3cIJUCRUI0ncWWvWTMpYU6XxFUqjvAaro
1hiRh5+v9nkIO/S6SXpGyJ3hA3ZwplUIARC2hVCnU+vydP90p+wSYtrt7/3gnu9N8w2tfUXSIWc0
7e2ZzjvfJsRsv+YD2gsqYxXLK1733I2JnweP9wiRyWOW+RIPv2DlTbLbURC3BeK4DAQLJBoOeijp
jK6yPjuizvcwNRRVRPFZI0XtkB/v6jBaqLHhgXlwQ1UBFbyrdq1B9Yj4dTV3Rb9pPz/N8TtuyEbR
wkWEX9IWZKgfdEe48EyU+zKNlb+SMyJGwYB50kBziMH4xTpWPb3CF3Imbs55TGpAcAf4GWGVXSrj
cvVDQPjTwaXBLN6EJWwQm6HEP4hHuuqhX5r15J71qc8rohYKb+0mUwcRlMm7H0CqQe38Gaov+wKD
cbtQQoN8bnI2PSLRGsfaRyS77jFiR6mU/WPmCKeSgBdUiHDkq/viPctOdkSmELw0u/usGtD1km3f
QWtBgDUPjPZPQ15Mlm3VY8wcadCwlZOwCWJO/gIyRBC/W3f0mt7POk4vs/lA3kJ6eOI/tJh+C5gs
wGyr+thLtXP2p91fGlRdq4Qp2l//8dSN6p8H7Q2cz1M8uQZ/Ld8Htwc9belyE9F7WuOSx0waZ8pX
bNlGhG6tFFqSB56/fKsQkRsBBFioULd/OGdOOhvorZImkr7je197GfT0u5rqwxhORdyXPXmC6ZKL
yW0aYS8I4vdHsRO3+jGG1yA67xz8AGr8hf+6Y6+qH4YNkvL73hvfJwd8xX9MfzhdtEm35iu9loEx
ACI/+oijas4IRx1NNMRhzmYxyhm5tcnp9u6jdsSoa1qtxGfUsxVm5qjH3QH95bYzKfucT4r4lSaG
EHhkg/EfU7Y2Jzb0f2TVBXrRkEREcx0EL4laXGYv63vNlRzF3mblbec0AdLf53rQuZw1UhLlom+u
q96kO2uk8cBZuD4gJQ/efNeddiuQ8MfXdgd0dE0Woy7dPsObYVsakLnRwbHuC42gpR6lzVF0JPcG
wBSTef5WhJvqLH0+z+sdlfmRGSNDd+aYsaipkxjFzhyfuehlGQJUC9qAt9Bjzc4kwoadfnpQOv7t
M553X54NHdSCfSON9OsaGB3r/nuN0/DxNannACHqWLJe0mC6/rdB3TBL5KgrL4DV6WAz2FNVoQit
llOHGd9IHx8dq8cyRF2vpODUf0phH2C4m/w1jvSzFj6n7J+lECZ86+m56GQuIQwxLIgfpJwX/JBi
WtCzhESNE3eghLiWy25fdpwA5VDbbrpqjp/R7uB2ZmBth1739kayuB0cCYulv/H7z+iUWH/XplPQ
bhC2jH4iY3uCFsSr94/j6aeMBbl+yW0PHz6rv1bh70//ogonITU9SQKVSNzDlL+hwLoEZHVvjydV
7BbwYYvnV592lnK9gkA12sgBMKccTooCh8vOLFgT7MbJCiFk3N9oTT2ehUhmJENHguCSbrFTcf+j
NbIg8W7CtKkzDGUjVp74chbN5m6L0WBXPMG0E0yfRGUDIBEHNSjEMvxqChpVw8wQj3svpG095R+D
H626lgq/S1HMSJ+h/RB07Ueow2zQHmGmldLt7fXWDeboQKWidXX7RreXQD6gOhn1u2zA91wIYRUW
7jGqhFhr+3GeuXShjBSqsjntf4tMMI0XvlaaqXsTsjeNWejOb3Ew1WS1f9gAmvfLB9D+noTdRByg
MueMATiiyOAr/QBFPKHIDcqcajamoq7Ct3bEBgUcCv3U85C7vhp2XhBStkrrpg7zZbyrSw4BCobT
cCCOJpil6P/p+B3c5B8uRRGkTakvEqYi+dUBZXCBaWFvnLYdAIWUcm4J8hhk2RhQF5LURnXtJI9x
DW7hpZFoRb60TCVCq7nlglEv7/ij20atlk6063XIg2LDKboea5301V6xJYGL8tUDTkYzsNVheWEJ
Tl0zbVaFs0KjDVBBEX27mLDscnx/NV9N5nXVxTBxPSGqujI56BEbAjxCDA+ovYD9OX0SGXV+NHbE
5DD1XflyovsD7kPYH2e77gRrrII/+eAysylOASvZdorSrmSLgyjg234TLiH+zHHCFYFG9Dchp1we
T+lrYmcBBwmGexrRHCFBLo8mOJOGA2u1A5PQAQ1GAndc6ujv6dp6dvQ+TfWSHV73BhZFi7/2eps7
40SaN1NMh8X4cqPupeyd+1eQx2D9oQLLPQIDQ2uCSE81u0hBVFhCgh99JejX/mNpPj7mo8o4oI5R
l+f+bCaBq6Rkr4e+OYLGFavsh7on4pxyiZDCdk90yzNeHusEwSRwJ/uPON43rXS/rTE03ZvJ8592
6hLcXJTdypAszOSSn2dHh73nRyq3XBBZMXdwXWCs3cvD7+A9b/YDNf2pISZuC84pRl1zO6c3fzQS
yVaIm2AgfEPuaavbbzopuAnUifHKZpMwQ+beSaxrjNCmBu2mhtfY/q0nTqW7OrUOVZ0nrUp+VuJD
H+sq9iWa6ja28a0wE1ua5ZjPqhhSA1/5SPfmg8L2b0JiKVhyMBDRpf6DILd1SzINrzfBnyaYAetu
pNipTsT0WPracGVC44OU+6gG772lESl2+qkaXQ70aRSxHEX24Jn3zDlH+HfCDwY+1hd4pNFDBWER
gPr+59hVrbx2HQ69CyVutbk6hEZT2DhbG8egJwWexQ25MdpPWCLDxgzI+8aDXsFWd2Apbf8uvb6V
0jLOwIKTZpbrUb+W4lggjirrEVib/8EtnYLwEdIb25QRuQHB1fXVvysgwRvGiauKexwNwynriXTM
qfN2HoGhjZdpqLAlMht3JU+/lksjBO/En7us2Y37gZ2rSIdED3b77jGFXkOEd8tbQRgxqBPDVqCz
Y9yqqSF964YyE1s3f4AMobJ1/05t2zR4v7i7/kXXnozUtSiBSMbUQOF4y9wZkA91sveIg1FqpKrs
R7YE7CX/Kx0vyAKGTfT0myGtWlL6e8UXfKwTK9TchNgNsm+9SCvUGxKnbUUrwmBqOOk4m7ou+mv2
K5mJd1dVvGl35Jse9qMeLc3YT3/bnhWp6SDFXu1yK/vzciDPdq0j3Au5QqXDyxW1iG7aPG0d8mys
8/Yz6CwvPSH0mGXIztphFuNRjZD8k0C5eFzlXPWA+7MdO99D0PaBmem5YIkndK5LSHKtKrS41X3p
Moiveo1CyLn8taaqEgV7Brun8tupPoCQpvrggiPhWrEPKkvpLk9OCIXs//RGJ+SPcA81+ju8Y/aE
JL0dpPrZly5DVcw4fzHgdaQvd2x0ybGfGSgH4ZLxrIOZem91guNF7KJSa7Gino17BAIsSZfmBiEk
mSF5K6hSdogwLAAtnvlng0kOjKQ9uMQAvmKymI16XFvkA74auzFG3faT3Rr4NvQx5SmVrGEqMUYU
K8tDFIFbzUiym8KOTGbpDggXV+QOATPk8ibZwxGRaMMwfc8sWvALcj5Wz13JyYaRdo88uJeZaroi
0l1JL3sDSfc9jVCX7reBWN1+vZn7cITA1eMK1Gb1O36va8EXJda+TqWTQZlNvzZN8kQp2CIx/TEM
wCoLD4K6utBVGXiH6rjOAY6N04popuI0XjVzGU7aj7vt1Cup0+BXM+/x8PflGD8R+s+ikkUmaM1H
wY8VmV4k8lKBNpslYp7OBXjX6YHlP05R0q4WSTM1dSKULddby7dynXWtgscexOqjIF5DwugnfxDD
VK/0xkLCjACQIl9a2ZHKYlHcZCbGBupoUSZmVWEoxzuTeZD2VDNfC+HZqHV1nJXxLrS8+l0TgaRn
P4xn/Syt6pcmOWustVWKZj8pnryKhfHltFcz9gdVoFNP9WZ+89ScqAZ3XEBUdpLnGnhBmnHuTU40
gocoxNVuXxjjvE9TsUcZFCBpaq8Q4dfnkK1LIfvLQvDsva8RtZcpxvWY/uMktMH1sTakPWlBeNKh
1+kV5nB4l0abx3umSsE455ndxAmPbFNc0NB/KcvqxK7w1YESlL4+LAK0+rZYxHFju0lH40XuYlBA
u4ItbtNPY8qP8NLR10BxUio+KC4Pl3yUoW1+0y2KfboQVgsn5TE1kzwZsuMvpCBUCiXis7UjUUC3
ukYyqeRjLunvcHARpvjUky2JxiVTN2gBbXpihny5aEac4F/J3RDISf3dfVEH+euX4cIB4YFIZ12U
Mu5m1SosnwfWE15Vckunjv48Aws9UmPlinW6Z6YBobgG7RtSfZBlN6KiuKHXwIhhOnV9Pk51x1P2
ien62lbp63nEPT4zREm5k+UEpHQNYu8TD8pZ2ziZ0uULcmlq8V1VXpvsuzCDjCIAVKpuAONhF6db
5xf5iTcCa31WbB+9tzRn5fPxYmf1JlB1Db7PAgAuowWbNUA8qUlm48m9+15MFgPJ71lnO80TR7/F
YrYXpJIrdd0r0XvsTVyWag8JuEtMe9wF2xxGi3yfwG9yYDedoBrdT8muhe35R0P/AlClHNvvQLm+
toSeViEsLphU3Q6mbsLd3selKA9yxlkkW0WdMe5qP47SbgpP9mJafJRTrvbdvVFpO+Bo5EGKSXY0
g+xtYrc8pZz20T9g0AZAT5kR26urWbjWVQRx9haThrUSM1cH8uF8dRv70Ary6qo+skBn2G0Fl8Zc
WegXXE9rEFlsetJ2iHB36ft2UEomSo8cou5yhXaejCqHaYW/fvTzaql5WbsStZrgiQ+K8xQFNfjJ
NLpFbcSQmN4TFrjGWkvvmvMJBIp3t6vOEjxbXMQCHz6sRl+3md+y1u6cQWKZMNksN66juJWrifXh
qZ9POb3YYfwlLo9BXHytbsrh4UxasdszyO9finWuRMOfESk/T2OIRRhap9eSgWWeuO/qzvMOnAu3
qe5bwyHeXH24XXa+rBeNbp9Dg6AdFWOV2bV6+2EdyW2eEx4U+gL+Fo4Kn1putFOCU+sOzgDrxOyy
ymOxC/ldmRP2DlkzcLedswyhkT2JWrrkxLMxtrfQjbcqEN9bMoZanygxScK8nUi8WO1j1GolEN0d
ARjC10GAnGTJWJyGu8ygM37P/xgso0cAI0eZrhAQQhiNqmeqSo89AcYJcYE+6lhyxqVT4UDPABop
Rmnv6sI6wOzqkEVaNZioamQ086DR45y2VWSdxuWr0snXt1OQb73qZHDPTopmsy5UbjbjeYNGVOk+
aEbroV1Jjuz2SbQlfO2KhYD8O6ARFvqf1QZywAFtoTFogsnyjmJG8DMmjXKN9AI0QoMP2XSJeOsJ
B36DHtf0Sjuo4i8g3jKFL1lJJcPdvFvaS8IjIMocR1L3rpajih4Q0yQMIlJhua9jEGSSLPBdf4/+
14N/QIVFypsQcF5GVjqz39sVj9sdU8wZnbZyOzmsi9fmOc6Q18dqh1HjMdgO0mnK9hUMBChjTr0C
cm/OvX0Z3eRy7ygbmP49loQq8ur7RzzoUCDZV0sYMqCGutELkXQOoFWFDNyRrlU1F8P9H1gMZl1X
Nxm8o1KPyWlJW4QvC0m/UEgZtwyXnEuZo/hOb86T8Z5MUciyYu4kGrUKXlvuVDkCe5vzscmbCh1w
bYYRqvGZkFODdM+5FHJ2Y62HOzcsPVYt3c9TWLMuHovGtUMgV6wb5xmNKTnE4SX8e6EHqntsgtZj
WdaYrEKZ/cWxLqTUxMqJxlW7GDAdw2hGrgrgwB1so4GHIpTx0IZX0MDiWbCcMy/KJvj5xgQRIgK3
vXYHUx/gC8a9P4gGgs3LgAHvdB2izugj1kGYatH2yKvijjf+h5ZoUQVbzh5akl1n38GpFr4THdHD
Dti8a6oeKGKIexKsKva8OSWKmIrssX0698xbofuaJxMd0//mdvOvq42uLtcV7b+vDsYF7vT4TGmT
uB+hWUuJpxE8zeOkvCOLe0/xdYXdwjCSMLIqZgnh+OS2T4kPOSUitFEk5XxKfrddvEZ8m4PWBZli
Cu91XGqmYyM6fUvo++M7PktrpHLaiG4KG3J5HfHhlGMMs821j/Eqmlm/TEUKo56L4LPirFuJTmC7
Zu1qR96GMJ2Jm1bLCqwv5CUEmakwg+WReLvEiUXSroilhQ0yPB0uQ5FtqE5oPZ7025m5sgiJEHb8
J6TCgNA8Y6PTt7aud5cF7gUUiCOU5vpPD+96si2qUjUQPgLCz+w5SvS8Daep9JqHQImIeidQfkLS
IDo9A0S3YlD92lFhtb7QB075YS6vUttNd6tSpMXxrCvos/xsNRFWPHKD94ORf1y4FTM1pqhhg+82
/K6U+6RQEKDsfCxqWhDwvijz1nAuP8p5LCcR2lDPjfIMg/2kpz9ixrfSmsS9+NRNht2vF81xDDgF
EGaiWjGalIGjOCYJYBLmvaeLkG2EM0rRahPaDsXmZqm03x6hrBFkKaCv4z/vG9xiYt1R+z5U3PFC
Bm4De65ly9OJrax4PLoMrqSDY1KGOIbe49WWxPlxazBWp3EEtu/hncC7kZkNmlvMPgjOoxK5zxpb
1rkczZ3tvJyN9Hq11h9GGA/EIHtD6JPhESyg/dHKgF23NplGVN08W37JlceAR/ZcnY0nMewkSKBY
9kSovzAZTkvY7O8HrMbq7Q+02qp+MR9FMBOpaGPh4HXuerJKHAcyLIIn9rz2aLo4I/sm5IeqNCSo
MD2aAxbaEqmbds59edaN5g8j6/KFtOia2f4+/RvN1nL2oR85VX8ANVbKJaLeCL5r7B17P8qmIGLz
NQweh39StjJy/7kCcZ2776DPOHRekRRv2yq7XkYNHk9SliqrTBMC9JYrFQn72pY4A/9yIrheGzBZ
7UWV2a/INBYy7g5VE01tcB5BPLOBDZtDiiDki9cw/dTnoDLdSgqNA2FCeBJoAOFAgRqYZ0LUw/qj
Uej/OhPbuNlHYTx4FBxjeGkK4iAmGATcP/af3EAuB3c8i7VTK+6n45M7XFamxeDVO9Z0AcE/dUfs
5E9V0H9SD5mFel97df+V4fzhPcjVLugVlBM9p4slPmRytqZmRqGuVz7GoqntDEBkLqLjQDnc2/7E
EKa7Z+yn4XrqX5sY0chZ97r934SY/6QqPgMAZvbOWg6wFZjjLvIjWFOfoBrPMvit4R6wkg/Ay5Sh
SbMqHR8Q/VXNz7ToD9zuxzHUkWQSRSchT5gMEQcdCVlgun40ar6y6+V9xOHOFftO5k1VpLMC6Qum
xXLVx5E0OvpF8PIBySwUDst7XfpfI1Vh0FRS3WeP9dYYp8cNTc89g37vvOQmt+503SRwh5lqrwSr
+oNY/KU/DU3RpWZ8pFkxODwlwcZHlUaZYinvaKW6qEJ5viQrIl+rA6JD3mdOZ8CfkMH6ynsoeyYc
JHIrvmOR3YIzwkg2KZcqJBSX9EiBNv6dmKsFHygJe8p6wwjPiQQ7k6EEvAMqIYC/48LG4vyYE2BW
CvU/HFLhqysWtzPG0/stG+EFn7RTQWREV3p4Phh65uuqh+xDK8u8LDn2PwGDoLjpaZfwJbAi2Pr4
Sf6jXdzd6rTGYIhPBxUFuH4H/27xgkjtLhmSF7dMoNTabGj0Y8hZNx4+K3jTKg30cUWAKvHJvYwo
NE5JQY3YipnmADfBhEPlXdwRrE7u5smwbkhBpTcWKLvOcq/3ilniKwhso9LHqDx4jSX8f122CZVQ
Hnk2+LGnjJn/BkRfDntLKaNTHnSqWaaVmzyrUpu7uPi2iDnyZg0QoD7dE1zePWtl52AtlfuugZol
N8jmdWSdmzIh1+cAFbtOhVLc96qSPYJncREPlAjEsL4HNHlYDNd5AFFCoRGn9fpYN9pqbOxV13Sj
fWss9zN44N3OhK3o5Z8CqVmtjHbMEVYavgHnVbMtuDzXMEnbYqRbEwEuU2624z3pM8XCc5hcZBul
xnaCQqFjFRmOziUvPCINhbvQjiQigOewb0QvTkg9b/G8JCjr+WBHIjMHv2orVT7ccwn4ga4h+XWl
O3oKeGlIBQsNSZehOqK/iQ==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
lz3B4KHX5z7HJK6kHiZGMmcEnUqLtTRT/n7HdY7szClNEEBtVq2UQW/wdwwMN27AnOLZPVfuS67c
Y2O4fk1xOw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
OUoXLY9rVEqAKiJgtR19Q8FIQUm9wPmLFXF2sem6w9gJVRflCYIHWjOAqv6eppRvqeqcjaja3KKN
iRxsDXzkmdVb18CNyYXYPgZU4MySqAPoAE8BZ3alC446EKqG5bo3Faah4iFiaQ2fsSYQDhznQFWV
FIedseAJGSJjdgeT43M=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
bHuGx6phwwi065A2gw0E1Tqc2OLDUoohEHY7mOoJcUQwvr9OEJ4yz01Uls3wx2UOc24N+ANXe8aM
YdyfwspjYSBviz8nI/XUT5fPMjNbtL8HFChLorcX+K00Sc+A9m1I9+5W+Wd6GLSKBCVYKnWRn9Os
rc68y/GTowadTW08aEEccqOavDD8XG+R6gQqGpi5C8xq75oqBRmE5yNpxpBXxQRz9mmAsJcZ773H
BpObF8UUngkYlRzDjfxz3vzf6lVAPrLm55l1zEsel1LRtdqlRT8kBTrz1kke43v4c6xNv0u+i1Y0
dvxmNCEmLNrwBuVbcA8l6Jjp0k0WZScEgrEOCA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
4sCk5d4E+rPjLUhUiUrzCNkXo2ztvWgfU4Ic3n3YDGHZzWC7cjzTKSJroiCXwtIaQEIL5FpdrGOo
eHf9JlqikZvG/pLSpSZr6BTZioOpsjgI4CJq9n0wGhpyClKm24hGzYEPH8AkBs4wVmgt4sOHvyYc
mYqTUQDFFlehrx6Wh0E=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
cjjanW9F+fseEMt2SDd6R3KYZVrfLHKeq8ULFHbP0E7BiwY4Vkec6zVJkc5FOAAhZdR5Ywc2FOnS
jk9bJ37QuAeSdAcrSzysHiIJYxA3kbMVuIa63kiSn3dKlLmPc1gZ2/UtM3HTBff0RPQzxl944kH8
SUid8bQM/bx+7wxLnTLuo6uTok/+c8ipzvZZ5iJ9DgzZyHiiuOtKu8JWNRVw1P5d1QqQT3EZ7Q8j
fnqcUNAmoR2w1hlmAhXTJgZbpiKUcMF+Y9/twpUzFl3rdEE6PKGzb5YQ/Re4uf+MJU96/KSTzmBR
Xfe8WjI4zLk+NlEm8eNku5cgYGTA1pkwApl+6w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 10960)
`protect data_block
PKlpisMKFINH4hoELw81Ae+vpIr0xr/BIQZISQh02QmAYRngfWchi+A+2gXJ0ErM+PWm3fbvLHaf
UADT/opvnHMCrmwuOuQX48J/a1y0sztlHgsA7XTu3se9+qgRV127lwvsMJp+UlinF11bhqOX4xmc
4cYuCuf0n1/UfLTSpbM+jwT6zHUTrOrKh7f9OpJ+QCgxfJhkQxcPhKOYBR3a8Dp06gydZjpwqjDq
tqPAaV6ta7+zR4nsr7KhZDk0KvhrrDa7oKo7kF4Yqt8L46maaQdVtdKjhVsrAGajIcZixhbXQBXC
KIPnejYm8Voo/+fTzj4QhGK3xFz3k3FowUtO5jGrPfd10F2QpBcb+lzujW5qHzaitTgU8nENP5TD
2NCNNxhTryKnoZbirc+DlOTjiUeVqWXdhzIhVjQE761Nzmz2eLo6N0V6ZXAbZPpb45msiAC4kCui
Sh4oKuCxBlkGt9/ew/UKSOYs4g/rPAUgxU5UJis2mhTgn8B70nZ6oe1lMoUjefiqYazyfy9m8vGS
EyNCpU32r32DOXi66vBKX3STS4MASUJIfYG+NpdusXHx8iM0GvteA1gnO9XlVeVucLuGO2H2TpmK
kNtPxJkOMbqjBOLbcw6u1MfDpAw0zM4S/xxxpD0m3R8p0n3wQdhT+VT41nAFYGTXHcj0UD1nlYk9
ZhVQDKcQaWJYd3lsXf/TNyrTovAkCZATosXG9/gmmkHeRoSaekH316l0DfUCazpMcUrE0gKAEV+2
bPeURMasKa3i1v3Q9v1COQBKJH2YL4cb4uW9dGdif1tBUmYddIAkEGs7ArxKb3pNxjuKy6V1DIMJ
XIpowUU4bXINHZzoB/7c/RgpIB6iGgafVpQoETmW/+DssTNucVCW8Kwh+UZiLWZ5G5mGaXr7TXxh
l0iz2gOWz3X8AT7JgFq6ItruuJBZ/ra5bWk//+vOxFoUCKV1+koz4Rlv7wpt7HJSSSICSO/akPPG
krhxjHXmtbWJG3FH017k263NKG9Ns/2xRZl8U4axgQLNB0HbhVWF0OYZ+XETB8sBwRGDNZEckCm9
Aw3jiTTqNStuhVhWvtAIv10Jys0Nc+/e3rHA9dM/mxvv3KhE21lKKzJQUi7wsX7SNfWjATofF63K
NWnw+8I7ds1IXKySwdS6BLd/OmygPsMAsrbK20V5vdtmT/W53scFA/dxCZlC4YOR5CkYnSs/jVpm
gZvD6tch6dfuDnLWz+E3D92qtGvA7i4MfEVC5e8ytxTrYjZFjTJyn8vA59PyMoPl+9YFy7afcqzl
aOvFPqWociBJgUDxdsRCC2+mgvRiJk+2m1vY7XgdaHH9I3WQjYYj9LzjD5Y7fozc7Pi4RLDETEyS
mxqQorH22rFzv/TOZPEwRLMD3o15g86d0S3yb2WlbPyN82LadclZ6/wlye7yVQo2MIlTZndWo3Pg
gGU3mPslBappcqCOJvD7U1JaXduNOMJ2wiR9hAR3UQn2FgdOP+snD5GiOqHRMMGBrBXL+IuOjDMK
aWoWzIJzTdx6Xn5VuLBp9ipme33V9FgzSzpWZV2TSRojdgbTHizXzQ0Mdy+VVfwDjdGZEcfrcgN9
jCG2vrSEqt0rjpFzjtQP9Z6txZqBSNuNRey2GvgfIP8fFmSL2fnhETfisPC/IHL/7XcUgD8AjU38
Wg70qui3u3p1R23i3EyXQvmt2mZG24g5gUR3QzJOh5OmpEUB16lF4rNxOLrT1IeCfqBVvWjzn7P1
F34PUqycxwmZhtbQSQbLIR1jUH5PLZzBC7gbXhDhTFW+tiM+HULrLfoYNLldm7LNPp+ky6qhN0B/
JlE2dsQKP4csNk61aq4pEAEfMgnXU5aYzNcK4NKuaOVAL1GWs+KIueLA+CGGft99LN/jEONqXEHs
VKeaLuijPqOX9aQi4aT3vBZK9mFkdNgb5SyXUzKY9FNevgM1hpT4vhjNK9U2fR2Y/H6ZSwl3RhND
+/S8Bl+byOrKBEXZ0J8MumniLa8f95UPXCIZjoK1vwoHjzMp1s5zx85kE5zgNnfH4Z0ZXwjG+rZL
esHmkBHf+58ZPZhC2mGNqZRsiDFbh4YW9Lmsxk5HuMKn4sixehuyLhv0YBEU/fWtAkrUM++gzgzz
8TZ1Ohg+yRaGpvTl3/SIXQrB+7lckwhHNTz9X9Jv4Kxgyz65E5odgHekq8x4oXEjfmg/f4iLDNez
0+ZF5IBM4XaFpkCvu3tEUpCBGBMyrlsCCpRtsDM72wgS6HvQ3vbpuwnSGOKr0tyFiHmn9SKRHYD4
cKrAr3epFd42s7HmNkWeBa5YaWvYhB+UxP/Ts5eahPKqvrGfVTEaNHCDjcoyQcCRybwEgt3eRnaO
bMj90rFhrCiG+i64aD2Vt1b8vyXy9/PCcKdkVsqNZIQB5mSaaK32i4tjULtMi3J3fbI/RGxkwwOB
TNyj2qkSAS0lO86+XU5DgcOeccIWC2Wh/CQmZg+03pXjqSTBxpPOjDhLK8xRI97F3jl7clYDwDkD
1Tk+czl1eG9ppfrFFOxloZrnANo+Q3iECpJGm2JUKLGfKuPZ8/wkuv4ZD7BrfB2Fubok3NUbs1s7
1A1FySkrL5P7ZJ9qukri8c/CPVWgcCaxqLzMDQp5iQfK85GlT/nj/IIX9+3XOm5YJRuEdQHnLqR/
SaHM/E6Mip3DNo9Ky8rFUhEu8YsTlg4rM7JIYTjReJE1+0PrwzG9mbOrzyuCQKonWCOeOxoEFMku
8T+TNqmafP3eFfg98fBOeFLFqvT02DO7XYXd3E53R/wjVoaiafIRw/hMKoOhDOsWcnn1tFicT2IG
/7P/Bg1Yg8/2yja22rQEa3m9gVlAhZHDQ5hER7kVxmzjrHlXIicasttA80b58eF/Yv2aYfyiLlg8
wIH4VyL+Af9Q/vgENpJBPQDhXAri0ZMGmwADU0FO2m92r1e5KYWcEyziZobv6yIClxuhoizCa6T+
hdH0OhLbgvd41Ox6j1TYJ5LX2WQRWXY/fa+NpnOKEWnR56S1oc/oKkiE0aj3WnenGnzgtYA1F5fQ
5lRBF7zzl5lfSS39xW4W7sDA7xB/AaC/uJLWR3HtyA/VwlEW/9bS87E79LbInytGvzcq0Yv3bMKy
wvt3lpHZUdUAYP9MRrMLIx87EHus5pa+vgLx5VIdGBXNOM+joU9Lz0ad1hNidgdL3x3Er+NyKTk3
rKcHwuMitlmMYGeUKM+0rQknIxD1oYz90AXE9GhZOYf+hwzsmFXgd/yNJKkxMTOYg/hUveuFjvjG
BlzjE+t4rs7QDwxHERt+RFxHQVC957Iyj/6GDXI302DCJHq1XLRz5UrFp+f7ZNtDyznJ5YJEkGd7
DpBGBmN2NEMe/Cay9og/1hQaatJ+95ueLNOJ2KmxiMKza4zsyiC36gF8JqXDj0YFZErM23T/qT/6
KPohLaYf2MoFetLzYCWPTs2/2zcF21VE2bfz26vGngL7YLxu/LmhoYMfoM4cyd/82JZSjwHRMrgM
+PMu5U6X7Ve/eFW2IMgxaUVOC2KrKbwT1/kMp3x2AFn1co4M4AglpGAZXnbJtpRD7otzyRuq1ehx
NjZFzzW4ltcaEnFI4ZtmhZ5LsHMVKKsYr7JkLFoNpVdOBOQRBR41UmYbI40j7xIz8xPcpQFRYLup
+FyJSf02AEjmTfuAcy4CfCSAnu28xxVj8zVnjKUuVfSy976CWwhl2L9aJHDSyEDmTwqRORriCgDg
nRtSNRdZNbDoY//6NqWZQrgxNpWQ3QLnJ1oNyHe/OkmoH5UwhFv8hxjUO+mYgZZXIBMkGAHE91qR
clEwV7vqi3lthQ8Z6jQaBeoPvgVaso2IOaP8jfJxPnz1wb83NvQ/5Cdkc3Ma7vhxBwCqvpsEOtnF
fYnvVZnuLKbs48vGloDR+o+JTkGCl3ApgQi/NoPxPVSkeUbwD4AAKrx+RkXxjdeqXEZqb5/hjlaU
XPc9WNziDhXZf0GKHRiPfYumoA7H0WtnpgSl/l9+8RIoBialvJuKA+93pkYWf+NhN2/YdtUVgM5m
Qke0RFt5ObsyT/GmsAdmucExDH3Ak0rB9pvgSFfNPDg+2ENl6a9zkWzh3kDNtxk5HgRgNUYrTV5e
6LNjoQ2Yk+y2K2oCG1iP50k+l1d96K6nkH6pG3S48irVuPIf200qWwN6ZSVvy4NgO5aklrn8/8w5
rbR3obr//OUT+5tGxaR/qYFMCVelp+6vbne4lGn6uygyLH9opDIcfCax2cJpJAedUQtJ7NgY+AwJ
vQDGVvC0fDV+ugGsS57+3fa5PNdzZs0GP6ftUJv7LNx1Fm3BIPFaW8brdqZOjLODAl518p/XSrqb
eI8KK+Mp4PuBC8uQd2QFZSb3qkxNir3YUWg1Kdfy4pCRPcsUBbSeGtrNKj4QvndOnojROIvEye8w
HhQqRjUxGs1eahR56q0S1wqIV68LgORIl9y7FGCfmu1DBSAIsTmWGiaShhDepXlwL+4WV97LP2JL
8XVdXQmbE2RMEhUhePmWCe74boG2BYSzth/uWyDumWgL2zYB+7fAXlH7Qvg1lm85Fkyy33sQuE9h
084Dak9V/q/G7WmTaTvCCXn+z+LBq7yAQz/BLL8BjbB7E1azlHQLKIIBT6W/5gtEsshlzcggXOqQ
RxZm53EHMBt12MOe8CA9tAWyX8BHsTpUavTvqQ3m+OLdKhVGIuD6kp+9htscDJSiqgpimLHFUyiZ
gnahr1x/tAiFAR0SOw/T40EK5v67CnJKdXk29xSGfvnIlzv1qd1WR4cGe6AGZPe95zPrQGHv/xUW
X5ufM1q+Dchcl1xOtkC/IwSnaHMjJWBE2q/8FDiKbEFRxV4HCerSEk6VsMHxhLgbdDWh3c7dFJ31
GIa+17B+U3eaog6sbtQSFEmOweZ24z28T9BNkrjSZyAzm62YsKttB0c7Z6JMyvIYhm0p23FIJyme
eYHT1YoPp5L/vLkZ/bjApX4Wt2iwIqsqTcuBGqqlWXcY8xyDhjlPAY3LHqs4pTTFVU/oWepXLQtn
rlu9kW4xqN8b5kdrjAi99pIG8z06r9b+CY7F3tQGg2fsSJrc0fpl8+LcV7rzdgVwXCT1PJDZWQtV
GeUkPsCQECyuQyiacqcYqnIq/+dPN29wM9CX56u5bFwn04oobN5ENOxdA9BP0pKl1cuzUTDgRRKY
qfSKu4iypVhqMIBgYCepT/VUsoxcdnFS380dituJ0e5SsNncVArtc7Pt7YNL31+cAyuQuwufnLcy
5yP0kWN+SDmpYYRZdJqItxvaaxVFy4w7yW7jbaJ8kZ8B4DmU2LIp14mEW2ScO2rWUNzKCUkuYJat
HnFteXKs6+vin2PKOp9EQX09nxNgB3aZod8LQgH3FDVEgPE9FjaG0OsTApIHfxIYypdlcRlaMJLA
UnhLgZAyUDhuqxi00yM4t+ySfakwHo6i+8d9WVbRbdcOZ7bSBNyaJ+b6lY1JoYBENkid+EpuJUqN
DYykchE6wzDdtu69rmN3IfYlgiVdCK3i4lTvk3hjb86vekhNivgVe14pV6pO3KgMpkE0b8Ctmhub
r81ILwkWyx5irNh/XGrw/mRfox5uUOPOBOJXrmwgm0K0ukuCyq+wLI08FW/lmpS0MBOO2OAOTyuX
J2v3Pvm2GyGF9I8yDfys38ytrPmz5Mgf0QJ1LcDWVYvYCGbftUrwIRqlMgv6fIjv8YfrvV6Ui8Jp
V8m92xMI5gNx0GfoolaHkllT+Dw7Z58QuAgCtDWtmBKzFEq6ZO2VBn8qlt5n3xMr0/IGXigfeHXQ
GgUuPmCla2kCWcylvDezgPIfF/ZMcq7lawUgu4i5Ew4t11yLb2FvWP0FWh6jRjzpXfZbJvK1fQvX
IF3C9w7AkzipStAkUybzG7E1jWfNh09JCjsqNBxKypW8PgArNf8h2pGxkHN0Kvhz7xcW/oTV4sxe
5QGixaoPS/EwqfXQQ9h4eMfN/XdgpO5hwHAcM/1c5qCHwSCEiBhoSOcXZRkHD2JEhWEjjup2Ymkh
Z0qZvJY0xEk52L/5bsqa9p0cgiv5nPPKV6vjBekVUVy/FQiBJ4mfEUZcW5hc1N6ifC7JcLYUS+c6
qvHQXRD4MUVO1CyVdLcP5ktObTDNR4omJCWAtcrUot+EbP0wTIEqaC1DwEhGwu/BR6KWuT3zocxz
aeRW2ZoaAFRcBuIp9ie0UN5x5A2lf1aqS4RE6giI3QWoRLlTlFBfb6Pst/UcFHCrtlTOWzmbhAvY
J0j8TGf4BJDrqtRq1go9ZaYezWuAvE4sTj8Hjw218/kJ/T3LmUNioSk7O2yLpoeIxwwz1Ktw1w1F
BRgWE2KoX7n5LrUIfk5oir7koUnuxLou0ourhd2NifpxTW6T8OSHLqGQIj+vS9/EjnDJMNCh3GIh
57GpdvYsx2x/BV9EMyCQ8z5ifledbJP6nt7sAhHtfZK/PGO/pfSRrbH8x0X/9qxWKs6fR7mNNzcE
l7UMw5wI11oqRrDg7aWQ1I1/RZHdNe/TWyy3CyLx2JTGGSiLqivGOYKlVdbQ3l4bV5LcUGz11Ksv
T3ewZ3joiDsbCscmqAmt39wDe6QRBsGgooSbjuJat4tXMqyZwfRFSv/MAEDhz/udrv2F3+Rd4VLU
cz11wRIYJYZjr69yJGjEIbQBs7nL/CgAruJZm7ObjDeZZWloeklL8igWN5jvu4vyMQuyETE7cyNE
erPqRzNY5odRKGtu/giHe1aBv9oTPLEIGgSdAnMLLNS3cIJUCRUI0ncWWvWTMpYU6XxFUqjvAaro
1hiRh5+v9nkIO/S6SXpGyJ3hA3ZwplUIARC2hVCnU+vydP90p+wSYtrt7/3gnu9N8w2tfUXSIWc0
7e2ZzjvfJsRsv+YD2gsqYxXLK1733I2JnweP9wiRyWOW+RIPv2DlTbLbURC3BeK4DAQLJBoOeijp
jK6yPjuizvcwNRRVRPFZI0XtkB/v6jBaqLHhgXlwQ1UBFbyrdq1B9Yj4dTV3Rb9pPz/N8TtuyEbR
wkWEX9IWZKgfdEe48EyU+zKNlb+SMyJGwYB50kBziMH4xTpWPb3CF3Imbs55TGpAcAf4GWGVXSrj
cvVDQPjTwaXBLN6EJWwQm6HEP4hHuuqhX5r15J71qc8rohYKb+0mUwcRlMm7H0CqQe38Gaov+wKD
cbtQQoN8bnI2PSLRGsfaRyS77jFiR6mU/WPmCKeSgBdUiHDkq/viPctOdkSmELw0u/usGtD1km3f
QWtBgDUPjPZPQ15Mlm3VY8wcadCwlZOwCWJO/gIyRBC/W3f0mt7POk4vs/lA3kJ6eOI/tJh+C5gs
wGyr+thLtXP2p91fGlRdq4Qp2l//8dSN6p8H7Q2cz1M8uQZ/Ld8Htwc9belyE9F7WuOSx0waZ8pX
bNlGhG6tFFqSB56/fKsQkRsBBFioULd/OGdOOhvorZImkr7je197GfT0u5rqwxhORdyXPXmC6ZKL
yW0aYS8I4vdHsRO3+jGG1yA67xz8AGr8hf+6Y6+qH4YNkvL73hvfJwd8xX9MfzhdtEm35iu9loEx
ACI/+oijas4IRx1NNMRhzmYxyhm5tcnp9u6jdsSoa1qtxGfUsxVm5qjH3QH95bYzKfucT4r4lSaG
EHhkg/EfU7Y2Jzb0f2TVBXrRkEREcx0EL4laXGYv63vNlRzF3mblbec0AdLf53rQuZw1UhLlom+u
q96kO2uk8cBZuD4gJQ/efNeddiuQ8MfXdgd0dE0Woy7dPsObYVsakLnRwbHuC42gpR6lzVF0JPcG
wBSTef5WhJvqLH0+z+sdlfmRGSNDd+aYsaipkxjFzhyfuehlGQJUC9qAt9Bjzc4kwoadfnpQOv7t
M553X54NHdSCfSON9OsaGB3r/nuN0/DxNannACHqWLJe0mC6/rdB3TBL5KgrL4DV6WAz2FNVoQit
llOHGd9IHx8dq8cyRF2vpODUf0phH2C4m/w1jvSzFj6n7J+lECZ86+m56GQuIQwxLIgfpJwX/JBi
WtCzhESNE3eghLiWy25fdpwA5VDbbrpqjp/R7uB2ZmBth1739kayuB0cCYulv/H7z+iUWH/XplPQ
bhC2jH4iY3uCFsSr94/j6aeMBbl+yW0PHz6rv1bh70//ogonITU9SQKVSNzDlL+hwLoEZHVvjydV
7BbwYYvnV592lnK9gkA12sgBMKccTooCh8vOLFgT7MbJCiFk3N9oTT2ehUhmJENHguCSbrFTcf+j
NbIg8W7CtKkzDGUjVp74chbN5m6L0WBXPMG0E0yfRGUDIBEHNSjEMvxqChpVw8wQj3svpG095R+D
H626lgq/S1HMSJ+h/RB07Ueow2zQHmGmldLt7fXWDeboQKWidXX7RreXQD6gOhn1u2zA91wIYRUW
7jGqhFhr+3GeuXShjBSqsjntf4tMMI0XvlaaqXsTsjeNWejOb3Ew1WS1f9gAmvfLB9D+noTdRByg
MueMATiiyOAr/QBFPKHIDcqcajamoq7Ct3bEBgUcCv3U85C7vhp2XhBStkrrpg7zZbyrSw4BCobT
cCCOJpil6P/p+B3c5B8uRRGkTakvEqYi+dUBZXCBaWFvnLYdAIWUcm4J8hhk2RhQF5LURnXtJI9x
DW7hpZFoRb60TCVCq7nlglEv7/ij20atlk6063XIg2LDKboea5301V6xJYGL8tUDTkYzsNVheWEJ
Tl0zbVaFs0KjDVBBEX27mLDscnx/NV9N5nXVxTBxPSGqujI56BEbAjxCDA+ovYD9OX0SGXV+NHbE
5DD1XflyovsD7kPYH2e77gRrrII/+eAysylOASvZdorSrmSLgyjg234TLiH+zHHCFYFG9Dchp1we
T+lrYmcBBwmGexrRHCFBLo8mOJOGA2u1A5PQAQ1GAndc6ujv6dp6dvQ+TfWSHV73BhZFi7/2eps7
40SaN1NMh8X4cqPupeyd+1eQx2D9oQLLPQIDQ2uCSE81u0hBVFhCgh99JejX/mNpPj7mo8o4oI5R
l+f+bCaBq6Rkr4e+OYLGFavsh7on4pxyiZDCdk90yzNeHusEwSRwJ/uPON43rXS/rTE03ZvJ8592
6hLcXJTdypAszOSSn2dHh73nRyq3XBBZMXdwXWCs3cvD7+A9b/YDNf2pISZuC84pRl1zO6c3fzQS
yVaIm2AgfEPuaavbbzopuAnUifHKZpMwQ+beSaxrjNCmBu2mhtfY/q0nTqW7OrUOVZ0nrUp+VuJD
H+sq9iWa6ja28a0wE1ua5ZjPqhhSA1/5SPfmg8L2b0JiKVhyMBDRpf6DILd1SzINrzfBnyaYAetu
pNipTsT0WPracGVC44OU+6gG772lESl2+qkaXQ70aRSxHEX24Jn3zDlH+HfCDwY+1hd4pNFDBWER
gPr+59hVrbx2HQ69CyVutbk6hEZT2DhbG8egJwWexQ25MdpPWCLDxgzI+8aDXsFWd2Apbf8uvb6V
0jLOwIKTZpbrUb+W4lggjirrEVib/8EtnYLwEdIb25QRuQHB1fXVvysgwRvGiauKexwNwynriXTM
qfN2HoGhjZdpqLAlMht3JU+/lksjBO/En7us2Y37gZ2rSIdED3b77jGFXkOEd8tbQRgxqBPDVqCz
Y9yqqSF964YyE1s3f4AMobJ1/05t2zR4v7i7/kXXnozUtSiBSMbUQOF4y9wZkA91sveIg1FqpKrs
R7YE7CX/Kx0vyAKGTfT0myGtWlL6e8UXfKwTK9TchNgNsm+9SCvUGxKnbUUrwmBqOOk4m7ou+mv2
K5mJd1dVvGl35Jse9qMeLc3YT3/bnhWp6SDFXu1yK/vzciDPdq0j3Au5QqXDyxW1iG7aPG0d8mys
8/Yz6CwvPSH0mGXIztphFuNRjZD8k0C5eFzlXPWA+7MdO99D0PaBmem5YIkndK5LSHKtKrS41X3p
Moiveo1CyLn8taaqEgV7Brun8tupPoCQpvrggiPhWrEPKkvpLk9OCIXs//RGJ+SPcA81+ju8Y/aE
JL0dpPrZly5DVcw4fzHgdaQvd2x0ybGfGSgH4ZLxrIOZem91guNF7KJSa7Gino17BAIsSZfmBiEk
mSF5K6hSdogwLAAtnvlng0kOjKQ9uMQAvmKymI16XFvkA74auzFG3faT3Rr4NvQx5SmVrGEqMUYU
K8tDFIFbzUiym8KOTGbpDggXV+QOATPk8ibZwxGRaMMwfc8sWvALcj5Wz13JyYaRdo88uJeZaroi
0l1JL3sDSfc9jVCX7reBWN1+vZn7cITA1eMK1Gb1O36va8EXJda+TqWTQZlNvzZN8kQp2CIx/TEM
wCoLD4K6utBVGXiH6rjOAY6N04popuI0XjVzGU7aj7vt1Cup0+BXM+/x8PflGD8R+s+ikkUmaM1H
wY8VmV4k8lKBNpslYp7OBXjX6YHlP05R0q4WSTM1dSKULddby7dynXWtgscexOqjIF5DwugnfxDD
VK/0xkLCjACQIl9a2ZHKYlHcZCbGBupoUSZmVWEoxzuTeZD2VDNfC+HZqHV1nJXxLrS8+l0TgaRn
P4xn/Syt6pcmOWustVWKZj8pnryKhfHltFcz9gdVoFNP9WZ+89ScqAZ3XEBUdpLnGnhBmnHuTU40
gocoxNVuXxjjvE9TsUcZFCBpaq8Q4dfnkK1LIfvLQvDsva8RtZcpxvWY/uMktMH1sTakPWlBeNKh
1+kV5nB4l0abx3umSsE455ndxAmPbFNc0NB/KcvqxK7w1YESlL4+LAK0+rZYxHFju0lH40XuYlBA
u4ItbtNPY8qP8NLR10BxUio+KC4Pl3yUoW1+0y2KfboQVgsn5TE1kzwZsuMvpCBUCiXis7UjUUC3
ukYyqeRjLunvcHARpvjUky2JxiVTN2gBbXpihny5aEac4F/J3RDISf3dfVEH+euX4cIB4YFIZ12U
Mu5m1SosnwfWE15Vckunjv48Aws9UmPlinW6Z6YBobgG7RtSfZBlN6KiuKHXwIhhOnV9Pk51x1P2
ien62lbp63nEPT4zREm5k+UEpHQNYu8TD8pZ2ziZ0uULcmlq8V1VXpvsuzCDjCIAVKpuAONhF6db
5xf5iTcCa31WbB+9tzRn5fPxYmf1JlB1Db7PAgAuowWbNUA8qUlm48m9+15MFgPJ71lnO80TR7/F
YrYXpJIrdd0r0XvsTVyWag8JuEtMe9wF2xxGi3yfwG9yYDedoBrdT8muhe35R0P/AlClHNvvQLm+
toSeViEsLphU3Q6mbsLd3selKA9yxlkkW0WdMe5qP47SbgpP9mJafJRTrvbdvVFpO+Bo5EGKSXY0
g+xtYrc8pZz20T9g0AZAT5kR26urWbjWVQRx9haThrUSM1cH8uF8dRv70Ary6qo+skBn2G0Fl8Zc
WegXXE9rEFlsetJ2iHB36ft2UEomSo8cou5yhXaejCqHaYW/fvTzaql5WbsStZrgiQ+K8xQFNfjJ
NLpFbcSQmN4TFrjGWkvvmvMJBIp3t6vOEjxbXMQCHz6sRl+3md+y1u6cQWKZMNksN66juJWrifXh
qZ9POb3YYfwlLo9BXHytbsrh4UxasdszyO9finWuRMOfESk/T2OIRRhap9eSgWWeuO/qzvMOnAu3
qe5bwyHeXH24XXa+rBeNbp9Dg6AdFWOV2bV6+2EdyW2eEx4U+gL+Fo4Kn1putFOCU+sOzgDrxOyy
ymOxC/ldmRP2DlkzcLedswyhkT2JWrrkxLMxtrfQjbcqEN9bMoZanygxScK8nUi8WO1j1GolEN0d
ARjC10GAnGTJWJyGu8ygM37P/xgso0cAI0eZrhAQQhiNqmeqSo89AcYJcYE+6lhyxqVT4UDPABop
Rmnv6sI6wOzqkEVaNZioamQ086DR45y2VWSdxuWr0snXt1OQb73qZHDPTopmsy5UbjbjeYNGVOk+
aEbroV1Jjuz2SbQlfO2KhYD8O6ARFvqf1QZywAFtoTFogsnyjmJG8DMmjXKN9AI0QoMP2XSJeOsJ
B36DHtf0Sjuo4i8g3jKFL1lJJcPdvFvaS8IjIMocR1L3rpajih4Q0yQMIlJhua9jEGSSLPBdf4/+
14N/QIVFypsQcF5GVjqz39sVj9sdU8wZnbZyOzmsi9fmOc6Q18dqh1HjMdgO0mnK9hUMBChjTr0C
cm/OvX0Z3eRy7ygbmP49loQq8ur7RzzoUCDZV0sYMqCGutELkXQOoFWFDNyRrlU1F8P9H1gMZl1X
Nxm8o1KPyWlJW4QvC0m/UEgZtwyXnEuZo/hOb86T8Z5MUciyYu4kGrUKXlvuVDkCe5vzscmbCh1w
bYYRqvGZkFODdM+5FHJ2Y62HOzcsPVYt3c9TWLMuHovGtUMgV6wb5xmNKTnE4SX8e6EHqntsgtZj
WdaYrEKZ/cWxLqTUxMqJxlW7GDAdw2hGrgrgwB1so4GHIpTx0IZX0MDiWbCcMy/KJvj5xgQRIgK3
vXYHUx/gC8a9P4gGgs3LgAHvdB2izugj1kGYatH2yKvijjf+h5ZoUQVbzh5akl1n38GpFr4THdHD
Dti8a6oeKGKIexKsKva8OSWKmIrssX0698xbofuaJxMd0//mdvOvq42uLtcV7b+vDsYF7vT4TGmT
uB+hWUuJpxE8zeOkvCOLe0/xdYXdwjCSMLIqZgnh+OS2T4kPOSUitFEk5XxKfrddvEZ8m4PWBZli
Cu91XGqmYyM6fUvo++M7PktrpHLaiG4KG3J5HfHhlGMMs821j/Eqmlm/TEUKo56L4LPirFuJTmC7
Zu1qR96GMJ2Jm1bLCqwv5CUEmakwg+WReLvEiUXSroilhQ0yPB0uQ5FtqE5oPZ7025m5sgiJEHb8
J6TCgNA8Y6PTt7aud5cF7gUUiCOU5vpPD+96si2qUjUQPgLCz+w5SvS8Daep9JqHQImIeidQfkLS
IDo9A0S3YlD92lFhtb7QB075YS6vUttNd6tSpMXxrCvos/xsNRFWPHKD94ORf1y4FTM1pqhhg+82
/K6U+6RQEKDsfCxqWhDwvijz1nAuP8p5LCcR2lDPjfIMg/2kpz9ixrfSmsS9+NRNht2vF81xDDgF
EGaiWjGalIGjOCYJYBLmvaeLkG2EM0rRahPaDsXmZqm03x6hrBFkKaCv4z/vG9xiYt1R+z5U3PFC
Bm4De65ly9OJrax4PLoMrqSDY1KGOIbe49WWxPlxazBWp3EEtu/hncC7kZkNmlvMPgjOoxK5zxpb
1rkczZ3tvJyN9Hq11h9GGA/EIHtD6JPhESyg/dHKgF23NplGVN08W37JlceAR/ZcnY0nMewkSKBY
9kSovzAZTkvY7O8HrMbq7Q+02qp+MR9FMBOpaGPh4HXuerJKHAcyLIIn9rz2aLo4I/sm5IeqNCSo
MD2aAxbaEqmbds59edaN5g8j6/KFtOia2f4+/RvN1nL2oR85VX8ANVbKJaLeCL5r7B17P8qmIGLz
NQweh39StjJy/7kCcZ2776DPOHRekRRv2yq7XkYNHk9SliqrTBMC9JYrFQn72pY4A/9yIrheGzBZ
7UWV2a/INBYy7g5VE01tcB5BPLOBDZtDiiDki9cw/dTnoDLdSgqNA2FCeBJoAOFAgRqYZ0LUw/qj
Uej/OhPbuNlHYTx4FBxjeGkK4iAmGATcP/af3EAuB3c8i7VTK+6n45M7XFamxeDVO9Z0AcE/dUfs
5E9V0H9SD5mFel97df+V4fzhPcjVLugVlBM9p4slPmRytqZmRqGuVz7GoqntDEBkLqLjQDnc2/7E
EKa7Z+yn4XrqX5sY0chZ97r934SY/6QqPgMAZvbOWg6wFZjjLvIjWFOfoBrPMvit4R6wkg/Ay5Sh
SbMqHR8Q/VXNz7ToD9zuxzHUkWQSRSchT5gMEQcdCVlgun40ar6y6+V9xOHOFftO5k1VpLMC6Qum
xXLVx5E0OvpF8PIBySwUDst7XfpfI1Vh0FRS3WeP9dYYp8cNTc89g37vvOQmt+503SRwh5lqrwSr
+oNY/KU/DU3RpWZ8pFkxODwlwcZHlUaZYinvaKW6qEJ5viQrIl+rA6JD3mdOZ8CfkMH6ynsoeyYc
JHIrvmOR3YIzwkg2KZcqJBSX9EiBNv6dmKsFHygJe8p6wwjPiQQ7k6EEvAMqIYC/48LG4vyYE2BW
CvU/HFLhqysWtzPG0/stG+EFn7RTQWREV3p4Phh65uuqh+xDK8u8LDn2PwGDoLjpaZfwJbAi2Pr4
Sf6jXdzd6rTGYIhPBxUFuH4H/27xgkjtLhmSF7dMoNTabGj0Y8hZNx4+K3jTKg30cUWAKvHJvYwo
NE5JQY3YipnmADfBhEPlXdwRrE7u5smwbkhBpTcWKLvOcq/3ilniKwhso9LHqDx4jSX8f122CZVQ
Hnk2+LGnjJn/BkRfDntLKaNTHnSqWaaVmzyrUpu7uPi2iDnyZg0QoD7dE1zePWtl52AtlfuugZol
N8jmdWSdmzIh1+cAFbtOhVLc96qSPYJncREPlAjEsL4HNHlYDNd5AFFCoRGn9fpYN9pqbOxV13Sj
fWss9zN44N3OhK3o5Z8CqVmtjHbMEVYavgHnVbMtuDzXMEnbYqRbEwEuU2624z3pM8XCc5hcZBul
xnaCQqFjFRmOziUvPCINhbvQjiQigOewb0QvTkg9b/G8JCjr+WBHIjMHv2orVT7ccwn4ga4h+XWl
O3oKeGlIBQsNSZehOqK/iQ==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
lz3B4KHX5z7HJK6kHiZGMmcEnUqLtTRT/n7HdY7szClNEEBtVq2UQW/wdwwMN27AnOLZPVfuS67c
Y2O4fk1xOw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
OUoXLY9rVEqAKiJgtR19Q8FIQUm9wPmLFXF2sem6w9gJVRflCYIHWjOAqv6eppRvqeqcjaja3KKN
iRxsDXzkmdVb18CNyYXYPgZU4MySqAPoAE8BZ3alC446EKqG5bo3Faah4iFiaQ2fsSYQDhznQFWV
FIedseAJGSJjdgeT43M=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
bHuGx6phwwi065A2gw0E1Tqc2OLDUoohEHY7mOoJcUQwvr9OEJ4yz01Uls3wx2UOc24N+ANXe8aM
YdyfwspjYSBviz8nI/XUT5fPMjNbtL8HFChLorcX+K00Sc+A9m1I9+5W+Wd6GLSKBCVYKnWRn9Os
rc68y/GTowadTW08aEEccqOavDD8XG+R6gQqGpi5C8xq75oqBRmE5yNpxpBXxQRz9mmAsJcZ773H
BpObF8UUngkYlRzDjfxz3vzf6lVAPrLm55l1zEsel1LRtdqlRT8kBTrz1kke43v4c6xNv0u+i1Y0
dvxmNCEmLNrwBuVbcA8l6Jjp0k0WZScEgrEOCA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
4sCk5d4E+rPjLUhUiUrzCNkXo2ztvWgfU4Ic3n3YDGHZzWC7cjzTKSJroiCXwtIaQEIL5FpdrGOo
eHf9JlqikZvG/pLSpSZr6BTZioOpsjgI4CJq9n0wGhpyClKm24hGzYEPH8AkBs4wVmgt4sOHvyYc
mYqTUQDFFlehrx6Wh0E=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
cjjanW9F+fseEMt2SDd6R3KYZVrfLHKeq8ULFHbP0E7BiwY4Vkec6zVJkc5FOAAhZdR5Ywc2FOnS
jk9bJ37QuAeSdAcrSzysHiIJYxA3kbMVuIa63kiSn3dKlLmPc1gZ2/UtM3HTBff0RPQzxl944kH8
SUid8bQM/bx+7wxLnTLuo6uTok/+c8ipzvZZ5iJ9DgzZyHiiuOtKu8JWNRVw1P5d1QqQT3EZ7Q8j
fnqcUNAmoR2w1hlmAhXTJgZbpiKUcMF+Y9/twpUzFl3rdEE6PKGzb5YQ/Re4uf+MJU96/KSTzmBR
Xfe8WjI4zLk+NlEm8eNku5cgYGTA1pkwApl+6w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 10960)
`protect data_block
PKlpisMKFINH4hoELw81Ae+vpIr0xr/BIQZISQh02QmAYRngfWchi+A+2gXJ0ErM+PWm3fbvLHaf
UADT/opvnHMCrmwuOuQX48J/a1y0sztlHgsA7XTu3se9+qgRV127lwvsMJp+UlinF11bhqOX4xmc
4cYuCuf0n1/UfLTSpbM+jwT6zHUTrOrKh7f9OpJ+QCgxfJhkQxcPhKOYBR3a8Dp06gydZjpwqjDq
tqPAaV6ta7+zR4nsr7KhZDk0KvhrrDa7oKo7kF4Yqt8L46maaQdVtdKjhVsrAGajIcZixhbXQBXC
KIPnejYm8Voo/+fTzj4QhGK3xFz3k3FowUtO5jGrPfd10F2QpBcb+lzujW5qHzaitTgU8nENP5TD
2NCNNxhTryKnoZbirc+DlOTjiUeVqWXdhzIhVjQE761Nzmz2eLo6N0V6ZXAbZPpb45msiAC4kCui
Sh4oKuCxBlkGt9/ew/UKSOYs4g/rPAUgxU5UJis2mhTgn8B70nZ6oe1lMoUjefiqYazyfy9m8vGS
EyNCpU32r32DOXi66vBKX3STS4MASUJIfYG+NpdusXHx8iM0GvteA1gnO9XlVeVucLuGO2H2TpmK
kNtPxJkOMbqjBOLbcw6u1MfDpAw0zM4S/xxxpD0m3R8p0n3wQdhT+VT41nAFYGTXHcj0UD1nlYk9
ZhVQDKcQaWJYd3lsXf/TNyrTovAkCZATosXG9/gmmkHeRoSaekH316l0DfUCazpMcUrE0gKAEV+2
bPeURMasKa3i1v3Q9v1COQBKJH2YL4cb4uW9dGdif1tBUmYddIAkEGs7ArxKb3pNxjuKy6V1DIMJ
XIpowUU4bXINHZzoB/7c/RgpIB6iGgafVpQoETmW/+DssTNucVCW8Kwh+UZiLWZ5G5mGaXr7TXxh
l0iz2gOWz3X8AT7JgFq6ItruuJBZ/ra5bWk//+vOxFoUCKV1+koz4Rlv7wpt7HJSSSICSO/akPPG
krhxjHXmtbWJG3FH017k263NKG9Ns/2xRZl8U4axgQLNB0HbhVWF0OYZ+XETB8sBwRGDNZEckCm9
Aw3jiTTqNStuhVhWvtAIv10Jys0Nc+/e3rHA9dM/mxvv3KhE21lKKzJQUi7wsX7SNfWjATofF63K
NWnw+8I7ds1IXKySwdS6BLd/OmygPsMAsrbK20V5vdtmT/W53scFA/dxCZlC4YOR5CkYnSs/jVpm
gZvD6tch6dfuDnLWz+E3D92qtGvA7i4MfEVC5e8ytxTrYjZFjTJyn8vA59PyMoPl+9YFy7afcqzl
aOvFPqWociBJgUDxdsRCC2+mgvRiJk+2m1vY7XgdaHH9I3WQjYYj9LzjD5Y7fozc7Pi4RLDETEyS
mxqQorH22rFzv/TOZPEwRLMD3o15g86d0S3yb2WlbPyN82LadclZ6/wlye7yVQo2MIlTZndWo3Pg
gGU3mPslBappcqCOJvD7U1JaXduNOMJ2wiR9hAR3UQn2FgdOP+snD5GiOqHRMMGBrBXL+IuOjDMK
aWoWzIJzTdx6Xn5VuLBp9ipme33V9FgzSzpWZV2TSRojdgbTHizXzQ0Mdy+VVfwDjdGZEcfrcgN9
jCG2vrSEqt0rjpFzjtQP9Z6txZqBSNuNRey2GvgfIP8fFmSL2fnhETfisPC/IHL/7XcUgD8AjU38
Wg70qui3u3p1R23i3EyXQvmt2mZG24g5gUR3QzJOh5OmpEUB16lF4rNxOLrT1IeCfqBVvWjzn7P1
F34PUqycxwmZhtbQSQbLIR1jUH5PLZzBC7gbXhDhTFW+tiM+HULrLfoYNLldm7LNPp+ky6qhN0B/
JlE2dsQKP4csNk61aq4pEAEfMgnXU5aYzNcK4NKuaOVAL1GWs+KIueLA+CGGft99LN/jEONqXEHs
VKeaLuijPqOX9aQi4aT3vBZK9mFkdNgb5SyXUzKY9FNevgM1hpT4vhjNK9U2fR2Y/H6ZSwl3RhND
+/S8Bl+byOrKBEXZ0J8MumniLa8f95UPXCIZjoK1vwoHjzMp1s5zx85kE5zgNnfH4Z0ZXwjG+rZL
esHmkBHf+58ZPZhC2mGNqZRsiDFbh4YW9Lmsxk5HuMKn4sixehuyLhv0YBEU/fWtAkrUM++gzgzz
8TZ1Ohg+yRaGpvTl3/SIXQrB+7lckwhHNTz9X9Jv4Kxgyz65E5odgHekq8x4oXEjfmg/f4iLDNez
0+ZF5IBM4XaFpkCvu3tEUpCBGBMyrlsCCpRtsDM72wgS6HvQ3vbpuwnSGOKr0tyFiHmn9SKRHYD4
cKrAr3epFd42s7HmNkWeBa5YaWvYhB+UxP/Ts5eahPKqvrGfVTEaNHCDjcoyQcCRybwEgt3eRnaO
bMj90rFhrCiG+i64aD2Vt1b8vyXy9/PCcKdkVsqNZIQB5mSaaK32i4tjULtMi3J3fbI/RGxkwwOB
TNyj2qkSAS0lO86+XU5DgcOeccIWC2Wh/CQmZg+03pXjqSTBxpPOjDhLK8xRI97F3jl7clYDwDkD
1Tk+czl1eG9ppfrFFOxloZrnANo+Q3iECpJGm2JUKLGfKuPZ8/wkuv4ZD7BrfB2Fubok3NUbs1s7
1A1FySkrL5P7ZJ9qukri8c/CPVWgcCaxqLzMDQp5iQfK85GlT/nj/IIX9+3XOm5YJRuEdQHnLqR/
SaHM/E6Mip3DNo9Ky8rFUhEu8YsTlg4rM7JIYTjReJE1+0PrwzG9mbOrzyuCQKonWCOeOxoEFMku
8T+TNqmafP3eFfg98fBOeFLFqvT02DO7XYXd3E53R/wjVoaiafIRw/hMKoOhDOsWcnn1tFicT2IG
/7P/Bg1Yg8/2yja22rQEa3m9gVlAhZHDQ5hER7kVxmzjrHlXIicasttA80b58eF/Yv2aYfyiLlg8
wIH4VyL+Af9Q/vgENpJBPQDhXAri0ZMGmwADU0FO2m92r1e5KYWcEyziZobv6yIClxuhoizCa6T+
hdH0OhLbgvd41Ox6j1TYJ5LX2WQRWXY/fa+NpnOKEWnR56S1oc/oKkiE0aj3WnenGnzgtYA1F5fQ
5lRBF7zzl5lfSS39xW4W7sDA7xB/AaC/uJLWR3HtyA/VwlEW/9bS87E79LbInytGvzcq0Yv3bMKy
wvt3lpHZUdUAYP9MRrMLIx87EHus5pa+vgLx5VIdGBXNOM+joU9Lz0ad1hNidgdL3x3Er+NyKTk3
rKcHwuMitlmMYGeUKM+0rQknIxD1oYz90AXE9GhZOYf+hwzsmFXgd/yNJKkxMTOYg/hUveuFjvjG
BlzjE+t4rs7QDwxHERt+RFxHQVC957Iyj/6GDXI302DCJHq1XLRz5UrFp+f7ZNtDyznJ5YJEkGd7
DpBGBmN2NEMe/Cay9og/1hQaatJ+95ueLNOJ2KmxiMKza4zsyiC36gF8JqXDj0YFZErM23T/qT/6
KPohLaYf2MoFetLzYCWPTs2/2zcF21VE2bfz26vGngL7YLxu/LmhoYMfoM4cyd/82JZSjwHRMrgM
+PMu5U6X7Ve/eFW2IMgxaUVOC2KrKbwT1/kMp3x2AFn1co4M4AglpGAZXnbJtpRD7otzyRuq1ehx
NjZFzzW4ltcaEnFI4ZtmhZ5LsHMVKKsYr7JkLFoNpVdOBOQRBR41UmYbI40j7xIz8xPcpQFRYLup
+FyJSf02AEjmTfuAcy4CfCSAnu28xxVj8zVnjKUuVfSy976CWwhl2L9aJHDSyEDmTwqRORriCgDg
nRtSNRdZNbDoY//6NqWZQrgxNpWQ3QLnJ1oNyHe/OkmoH5UwhFv8hxjUO+mYgZZXIBMkGAHE91qR
clEwV7vqi3lthQ8Z6jQaBeoPvgVaso2IOaP8jfJxPnz1wb83NvQ/5Cdkc3Ma7vhxBwCqvpsEOtnF
fYnvVZnuLKbs48vGloDR+o+JTkGCl3ApgQi/NoPxPVSkeUbwD4AAKrx+RkXxjdeqXEZqb5/hjlaU
XPc9WNziDhXZf0GKHRiPfYumoA7H0WtnpgSl/l9+8RIoBialvJuKA+93pkYWf+NhN2/YdtUVgM5m
Qke0RFt5ObsyT/GmsAdmucExDH3Ak0rB9pvgSFfNPDg+2ENl6a9zkWzh3kDNtxk5HgRgNUYrTV5e
6LNjoQ2Yk+y2K2oCG1iP50k+l1d96K6nkH6pG3S48irVuPIf200qWwN6ZSVvy4NgO5aklrn8/8w5
rbR3obr//OUT+5tGxaR/qYFMCVelp+6vbne4lGn6uygyLH9opDIcfCax2cJpJAedUQtJ7NgY+AwJ
vQDGVvC0fDV+ugGsS57+3fa5PNdzZs0GP6ftUJv7LNx1Fm3BIPFaW8brdqZOjLODAl518p/XSrqb
eI8KK+Mp4PuBC8uQd2QFZSb3qkxNir3YUWg1Kdfy4pCRPcsUBbSeGtrNKj4QvndOnojROIvEye8w
HhQqRjUxGs1eahR56q0S1wqIV68LgORIl9y7FGCfmu1DBSAIsTmWGiaShhDepXlwL+4WV97LP2JL
8XVdXQmbE2RMEhUhePmWCe74boG2BYSzth/uWyDumWgL2zYB+7fAXlH7Qvg1lm85Fkyy33sQuE9h
084Dak9V/q/G7WmTaTvCCXn+z+LBq7yAQz/BLL8BjbB7E1azlHQLKIIBT6W/5gtEsshlzcggXOqQ
RxZm53EHMBt12MOe8CA9tAWyX8BHsTpUavTvqQ3m+OLdKhVGIuD6kp+9htscDJSiqgpimLHFUyiZ
gnahr1x/tAiFAR0SOw/T40EK5v67CnJKdXk29xSGfvnIlzv1qd1WR4cGe6AGZPe95zPrQGHv/xUW
X5ufM1q+Dchcl1xOtkC/IwSnaHMjJWBE2q/8FDiKbEFRxV4HCerSEk6VsMHxhLgbdDWh3c7dFJ31
GIa+17B+U3eaog6sbtQSFEmOweZ24z28T9BNkrjSZyAzm62YsKttB0c7Z6JMyvIYhm0p23FIJyme
eYHT1YoPp5L/vLkZ/bjApX4Wt2iwIqsqTcuBGqqlWXcY8xyDhjlPAY3LHqs4pTTFVU/oWepXLQtn
rlu9kW4xqN8b5kdrjAi99pIG8z06r9b+CY7F3tQGg2fsSJrc0fpl8+LcV7rzdgVwXCT1PJDZWQtV
GeUkPsCQECyuQyiacqcYqnIq/+dPN29wM9CX56u5bFwn04oobN5ENOxdA9BP0pKl1cuzUTDgRRKY
qfSKu4iypVhqMIBgYCepT/VUsoxcdnFS380dituJ0e5SsNncVArtc7Pt7YNL31+cAyuQuwufnLcy
5yP0kWN+SDmpYYRZdJqItxvaaxVFy4w7yW7jbaJ8kZ8B4DmU2LIp14mEW2ScO2rWUNzKCUkuYJat
HnFteXKs6+vin2PKOp9EQX09nxNgB3aZod8LQgH3FDVEgPE9FjaG0OsTApIHfxIYypdlcRlaMJLA
UnhLgZAyUDhuqxi00yM4t+ySfakwHo6i+8d9WVbRbdcOZ7bSBNyaJ+b6lY1JoYBENkid+EpuJUqN
DYykchE6wzDdtu69rmN3IfYlgiVdCK3i4lTvk3hjb86vekhNivgVe14pV6pO3KgMpkE0b8Ctmhub
r81ILwkWyx5irNh/XGrw/mRfox5uUOPOBOJXrmwgm0K0ukuCyq+wLI08FW/lmpS0MBOO2OAOTyuX
J2v3Pvm2GyGF9I8yDfys38ytrPmz5Mgf0QJ1LcDWVYvYCGbftUrwIRqlMgv6fIjv8YfrvV6Ui8Jp
V8m92xMI5gNx0GfoolaHkllT+Dw7Z58QuAgCtDWtmBKzFEq6ZO2VBn8qlt5n3xMr0/IGXigfeHXQ
GgUuPmCla2kCWcylvDezgPIfF/ZMcq7lawUgu4i5Ew4t11yLb2FvWP0FWh6jRjzpXfZbJvK1fQvX
IF3C9w7AkzipStAkUybzG7E1jWfNh09JCjsqNBxKypW8PgArNf8h2pGxkHN0Kvhz7xcW/oTV4sxe
5QGixaoPS/EwqfXQQ9h4eMfN/XdgpO5hwHAcM/1c5qCHwSCEiBhoSOcXZRkHD2JEhWEjjup2Ymkh
Z0qZvJY0xEk52L/5bsqa9p0cgiv5nPPKV6vjBekVUVy/FQiBJ4mfEUZcW5hc1N6ifC7JcLYUS+c6
qvHQXRD4MUVO1CyVdLcP5ktObTDNR4omJCWAtcrUot+EbP0wTIEqaC1DwEhGwu/BR6KWuT3zocxz
aeRW2ZoaAFRcBuIp9ie0UN5x5A2lf1aqS4RE6giI3QWoRLlTlFBfb6Pst/UcFHCrtlTOWzmbhAvY
J0j8TGf4BJDrqtRq1go9ZaYezWuAvE4sTj8Hjw218/kJ/T3LmUNioSk7O2yLpoeIxwwz1Ktw1w1F
BRgWE2KoX7n5LrUIfk5oir7koUnuxLou0ourhd2NifpxTW6T8OSHLqGQIj+vS9/EjnDJMNCh3GIh
57GpdvYsx2x/BV9EMyCQ8z5ifledbJP6nt7sAhHtfZK/PGO/pfSRrbH8x0X/9qxWKs6fR7mNNzcE
l7UMw5wI11oqRrDg7aWQ1I1/RZHdNe/TWyy3CyLx2JTGGSiLqivGOYKlVdbQ3l4bV5LcUGz11Ksv
T3ewZ3joiDsbCscmqAmt39wDe6QRBsGgooSbjuJat4tXMqyZwfRFSv/MAEDhz/udrv2F3+Rd4VLU
cz11wRIYJYZjr69yJGjEIbQBs7nL/CgAruJZm7ObjDeZZWloeklL8igWN5jvu4vyMQuyETE7cyNE
erPqRzNY5odRKGtu/giHe1aBv9oTPLEIGgSdAnMLLNS3cIJUCRUI0ncWWvWTMpYU6XxFUqjvAaro
1hiRh5+v9nkIO/S6SXpGyJ3hA3ZwplUIARC2hVCnU+vydP90p+wSYtrt7/3gnu9N8w2tfUXSIWc0
7e2ZzjvfJsRsv+YD2gsqYxXLK1733I2JnweP9wiRyWOW+RIPv2DlTbLbURC3BeK4DAQLJBoOeijp
jK6yPjuizvcwNRRVRPFZI0XtkB/v6jBaqLHhgXlwQ1UBFbyrdq1B9Yj4dTV3Rb9pPz/N8TtuyEbR
wkWEX9IWZKgfdEe48EyU+zKNlb+SMyJGwYB50kBziMH4xTpWPb3CF3Imbs55TGpAcAf4GWGVXSrj
cvVDQPjTwaXBLN6EJWwQm6HEP4hHuuqhX5r15J71qc8rohYKb+0mUwcRlMm7H0CqQe38Gaov+wKD
cbtQQoN8bnI2PSLRGsfaRyS77jFiR6mU/WPmCKeSgBdUiHDkq/viPctOdkSmELw0u/usGtD1km3f
QWtBgDUPjPZPQ15Mlm3VY8wcadCwlZOwCWJO/gIyRBC/W3f0mt7POk4vs/lA3kJ6eOI/tJh+C5gs
wGyr+thLtXP2p91fGlRdq4Qp2l//8dSN6p8H7Q2cz1M8uQZ/Ld8Htwc9belyE9F7WuOSx0waZ8pX
bNlGhG6tFFqSB56/fKsQkRsBBFioULd/OGdOOhvorZImkr7je197GfT0u5rqwxhORdyXPXmC6ZKL
yW0aYS8I4vdHsRO3+jGG1yA67xz8AGr8hf+6Y6+qH4YNkvL73hvfJwd8xX9MfzhdtEm35iu9loEx
ACI/+oijas4IRx1NNMRhzmYxyhm5tcnp9u6jdsSoa1qtxGfUsxVm5qjH3QH95bYzKfucT4r4lSaG
EHhkg/EfU7Y2Jzb0f2TVBXrRkEREcx0EL4laXGYv63vNlRzF3mblbec0AdLf53rQuZw1UhLlom+u
q96kO2uk8cBZuD4gJQ/efNeddiuQ8MfXdgd0dE0Woy7dPsObYVsakLnRwbHuC42gpR6lzVF0JPcG
wBSTef5WhJvqLH0+z+sdlfmRGSNDd+aYsaipkxjFzhyfuehlGQJUC9qAt9Bjzc4kwoadfnpQOv7t
M553X54NHdSCfSON9OsaGB3r/nuN0/DxNannACHqWLJe0mC6/rdB3TBL5KgrL4DV6WAz2FNVoQit
llOHGd9IHx8dq8cyRF2vpODUf0phH2C4m/w1jvSzFj6n7J+lECZ86+m56GQuIQwxLIgfpJwX/JBi
WtCzhESNE3eghLiWy25fdpwA5VDbbrpqjp/R7uB2ZmBth1739kayuB0cCYulv/H7z+iUWH/XplPQ
bhC2jH4iY3uCFsSr94/j6aeMBbl+yW0PHz6rv1bh70//ogonITU9SQKVSNzDlL+hwLoEZHVvjydV
7BbwYYvnV592lnK9gkA12sgBMKccTooCh8vOLFgT7MbJCiFk3N9oTT2ehUhmJENHguCSbrFTcf+j
NbIg8W7CtKkzDGUjVp74chbN5m6L0WBXPMG0E0yfRGUDIBEHNSjEMvxqChpVw8wQj3svpG095R+D
H626lgq/S1HMSJ+h/RB07Ueow2zQHmGmldLt7fXWDeboQKWidXX7RreXQD6gOhn1u2zA91wIYRUW
7jGqhFhr+3GeuXShjBSqsjntf4tMMI0XvlaaqXsTsjeNWejOb3Ew1WS1f9gAmvfLB9D+noTdRByg
MueMATiiyOAr/QBFPKHIDcqcajamoq7Ct3bEBgUcCv3U85C7vhp2XhBStkrrpg7zZbyrSw4BCobT
cCCOJpil6P/p+B3c5B8uRRGkTakvEqYi+dUBZXCBaWFvnLYdAIWUcm4J8hhk2RhQF5LURnXtJI9x
DW7hpZFoRb60TCVCq7nlglEv7/ij20atlk6063XIg2LDKboea5301V6xJYGL8tUDTkYzsNVheWEJ
Tl0zbVaFs0KjDVBBEX27mLDscnx/NV9N5nXVxTBxPSGqujI56BEbAjxCDA+ovYD9OX0SGXV+NHbE
5DD1XflyovsD7kPYH2e77gRrrII/+eAysylOASvZdorSrmSLgyjg234TLiH+zHHCFYFG9Dchp1we
T+lrYmcBBwmGexrRHCFBLo8mOJOGA2u1A5PQAQ1GAndc6ujv6dp6dvQ+TfWSHV73BhZFi7/2eps7
40SaN1NMh8X4cqPupeyd+1eQx2D9oQLLPQIDQ2uCSE81u0hBVFhCgh99JejX/mNpPj7mo8o4oI5R
l+f+bCaBq6Rkr4e+OYLGFavsh7on4pxyiZDCdk90yzNeHusEwSRwJ/uPON43rXS/rTE03ZvJ8592
6hLcXJTdypAszOSSn2dHh73nRyq3XBBZMXdwXWCs3cvD7+A9b/YDNf2pISZuC84pRl1zO6c3fzQS
yVaIm2AgfEPuaavbbzopuAnUifHKZpMwQ+beSaxrjNCmBu2mhtfY/q0nTqW7OrUOVZ0nrUp+VuJD
H+sq9iWa6ja28a0wE1ua5ZjPqhhSA1/5SPfmg8L2b0JiKVhyMBDRpf6DILd1SzINrzfBnyaYAetu
pNipTsT0WPracGVC44OU+6gG772lESl2+qkaXQ70aRSxHEX24Jn3zDlH+HfCDwY+1hd4pNFDBWER
gPr+59hVrbx2HQ69CyVutbk6hEZT2DhbG8egJwWexQ25MdpPWCLDxgzI+8aDXsFWd2Apbf8uvb6V
0jLOwIKTZpbrUb+W4lggjirrEVib/8EtnYLwEdIb25QRuQHB1fXVvysgwRvGiauKexwNwynriXTM
qfN2HoGhjZdpqLAlMht3JU+/lksjBO/En7us2Y37gZ2rSIdED3b77jGFXkOEd8tbQRgxqBPDVqCz
Y9yqqSF964YyE1s3f4AMobJ1/05t2zR4v7i7/kXXnozUtSiBSMbUQOF4y9wZkA91sveIg1FqpKrs
R7YE7CX/Kx0vyAKGTfT0myGtWlL6e8UXfKwTK9TchNgNsm+9SCvUGxKnbUUrwmBqOOk4m7ou+mv2
K5mJd1dVvGl35Jse9qMeLc3YT3/bnhWp6SDFXu1yK/vzciDPdq0j3Au5QqXDyxW1iG7aPG0d8mys
8/Yz6CwvPSH0mGXIztphFuNRjZD8k0C5eFzlXPWA+7MdO99D0PaBmem5YIkndK5LSHKtKrS41X3p
Moiveo1CyLn8taaqEgV7Brun8tupPoCQpvrggiPhWrEPKkvpLk9OCIXs//RGJ+SPcA81+ju8Y/aE
JL0dpPrZly5DVcw4fzHgdaQvd2x0ybGfGSgH4ZLxrIOZem91guNF7KJSa7Gino17BAIsSZfmBiEk
mSF5K6hSdogwLAAtnvlng0kOjKQ9uMQAvmKymI16XFvkA74auzFG3faT3Rr4NvQx5SmVrGEqMUYU
K8tDFIFbzUiym8KOTGbpDggXV+QOATPk8ibZwxGRaMMwfc8sWvALcj5Wz13JyYaRdo88uJeZaroi
0l1JL3sDSfc9jVCX7reBWN1+vZn7cITA1eMK1Gb1O36va8EXJda+TqWTQZlNvzZN8kQp2CIx/TEM
wCoLD4K6utBVGXiH6rjOAY6N04popuI0XjVzGU7aj7vt1Cup0+BXM+/x8PflGD8R+s+ikkUmaM1H
wY8VmV4k8lKBNpslYp7OBXjX6YHlP05R0q4WSTM1dSKULddby7dynXWtgscexOqjIF5DwugnfxDD
VK/0xkLCjACQIl9a2ZHKYlHcZCbGBupoUSZmVWEoxzuTeZD2VDNfC+HZqHV1nJXxLrS8+l0TgaRn
P4xn/Syt6pcmOWustVWKZj8pnryKhfHltFcz9gdVoFNP9WZ+89ScqAZ3XEBUdpLnGnhBmnHuTU40
gocoxNVuXxjjvE9TsUcZFCBpaq8Q4dfnkK1LIfvLQvDsva8RtZcpxvWY/uMktMH1sTakPWlBeNKh
1+kV5nB4l0abx3umSsE455ndxAmPbFNc0NB/KcvqxK7w1YESlL4+LAK0+rZYxHFju0lH40XuYlBA
u4ItbtNPY8qP8NLR10BxUio+KC4Pl3yUoW1+0y2KfboQVgsn5TE1kzwZsuMvpCBUCiXis7UjUUC3
ukYyqeRjLunvcHARpvjUky2JxiVTN2gBbXpihny5aEac4F/J3RDISf3dfVEH+euX4cIB4YFIZ12U
Mu5m1SosnwfWE15Vckunjv48Aws9UmPlinW6Z6YBobgG7RtSfZBlN6KiuKHXwIhhOnV9Pk51x1P2
ien62lbp63nEPT4zREm5k+UEpHQNYu8TD8pZ2ziZ0uULcmlq8V1VXpvsuzCDjCIAVKpuAONhF6db
5xf5iTcCa31WbB+9tzRn5fPxYmf1JlB1Db7PAgAuowWbNUA8qUlm48m9+15MFgPJ71lnO80TR7/F
YrYXpJIrdd0r0XvsTVyWag8JuEtMe9wF2xxGi3yfwG9yYDedoBrdT8muhe35R0P/AlClHNvvQLm+
toSeViEsLphU3Q6mbsLd3selKA9yxlkkW0WdMe5qP47SbgpP9mJafJRTrvbdvVFpO+Bo5EGKSXY0
g+xtYrc8pZz20T9g0AZAT5kR26urWbjWVQRx9haThrUSM1cH8uF8dRv70Ary6qo+skBn2G0Fl8Zc
WegXXE9rEFlsetJ2iHB36ft2UEomSo8cou5yhXaejCqHaYW/fvTzaql5WbsStZrgiQ+K8xQFNfjJ
NLpFbcSQmN4TFrjGWkvvmvMJBIp3t6vOEjxbXMQCHz6sRl+3md+y1u6cQWKZMNksN66juJWrifXh
qZ9POb3YYfwlLo9BXHytbsrh4UxasdszyO9finWuRMOfESk/T2OIRRhap9eSgWWeuO/qzvMOnAu3
qe5bwyHeXH24XXa+rBeNbp9Dg6AdFWOV2bV6+2EdyW2eEx4U+gL+Fo4Kn1putFOCU+sOzgDrxOyy
ymOxC/ldmRP2DlkzcLedswyhkT2JWrrkxLMxtrfQjbcqEN9bMoZanygxScK8nUi8WO1j1GolEN0d
ARjC10GAnGTJWJyGu8ygM37P/xgso0cAI0eZrhAQQhiNqmeqSo89AcYJcYE+6lhyxqVT4UDPABop
Rmnv6sI6wOzqkEVaNZioamQ086DR45y2VWSdxuWr0snXt1OQb73qZHDPTopmsy5UbjbjeYNGVOk+
aEbroV1Jjuz2SbQlfO2KhYD8O6ARFvqf1QZywAFtoTFogsnyjmJG8DMmjXKN9AI0QoMP2XSJeOsJ
B36DHtf0Sjuo4i8g3jKFL1lJJcPdvFvaS8IjIMocR1L3rpajih4Q0yQMIlJhua9jEGSSLPBdf4/+
14N/QIVFypsQcF5GVjqz39sVj9sdU8wZnbZyOzmsi9fmOc6Q18dqh1HjMdgO0mnK9hUMBChjTr0C
cm/OvX0Z3eRy7ygbmP49loQq8ur7RzzoUCDZV0sYMqCGutELkXQOoFWFDNyRrlU1F8P9H1gMZl1X
Nxm8o1KPyWlJW4QvC0m/UEgZtwyXnEuZo/hOb86T8Z5MUciyYu4kGrUKXlvuVDkCe5vzscmbCh1w
bYYRqvGZkFODdM+5FHJ2Y62HOzcsPVYt3c9TWLMuHovGtUMgV6wb5xmNKTnE4SX8e6EHqntsgtZj
WdaYrEKZ/cWxLqTUxMqJxlW7GDAdw2hGrgrgwB1so4GHIpTx0IZX0MDiWbCcMy/KJvj5xgQRIgK3
vXYHUx/gC8a9P4gGgs3LgAHvdB2izugj1kGYatH2yKvijjf+h5ZoUQVbzh5akl1n38GpFr4THdHD
Dti8a6oeKGKIexKsKva8OSWKmIrssX0698xbofuaJxMd0//mdvOvq42uLtcV7b+vDsYF7vT4TGmT
uB+hWUuJpxE8zeOkvCOLe0/xdYXdwjCSMLIqZgnh+OS2T4kPOSUitFEk5XxKfrddvEZ8m4PWBZli
Cu91XGqmYyM6fUvo++M7PktrpHLaiG4KG3J5HfHhlGMMs821j/Eqmlm/TEUKo56L4LPirFuJTmC7
Zu1qR96GMJ2Jm1bLCqwv5CUEmakwg+WReLvEiUXSroilhQ0yPB0uQ5FtqE5oPZ7025m5sgiJEHb8
J6TCgNA8Y6PTt7aud5cF7gUUiCOU5vpPD+96si2qUjUQPgLCz+w5SvS8Daep9JqHQImIeidQfkLS
IDo9A0S3YlD92lFhtb7QB075YS6vUttNd6tSpMXxrCvos/xsNRFWPHKD94ORf1y4FTM1pqhhg+82
/K6U+6RQEKDsfCxqWhDwvijz1nAuP8p5LCcR2lDPjfIMg/2kpz9ixrfSmsS9+NRNht2vF81xDDgF
EGaiWjGalIGjOCYJYBLmvaeLkG2EM0rRahPaDsXmZqm03x6hrBFkKaCv4z/vG9xiYt1R+z5U3PFC
Bm4De65ly9OJrax4PLoMrqSDY1KGOIbe49WWxPlxazBWp3EEtu/hncC7kZkNmlvMPgjOoxK5zxpb
1rkczZ3tvJyN9Hq11h9GGA/EIHtD6JPhESyg/dHKgF23NplGVN08W37JlceAR/ZcnY0nMewkSKBY
9kSovzAZTkvY7O8HrMbq7Q+02qp+MR9FMBOpaGPh4HXuerJKHAcyLIIn9rz2aLo4I/sm5IeqNCSo
MD2aAxbaEqmbds59edaN5g8j6/KFtOia2f4+/RvN1nL2oR85VX8ANVbKJaLeCL5r7B17P8qmIGLz
NQweh39StjJy/7kCcZ2776DPOHRekRRv2yq7XkYNHk9SliqrTBMC9JYrFQn72pY4A/9yIrheGzBZ
7UWV2a/INBYy7g5VE01tcB5BPLOBDZtDiiDki9cw/dTnoDLdSgqNA2FCeBJoAOFAgRqYZ0LUw/qj
Uej/OhPbuNlHYTx4FBxjeGkK4iAmGATcP/af3EAuB3c8i7VTK+6n45M7XFamxeDVO9Z0AcE/dUfs
5E9V0H9SD5mFel97df+V4fzhPcjVLugVlBM9p4slPmRytqZmRqGuVz7GoqntDEBkLqLjQDnc2/7E
EKa7Z+yn4XrqX5sY0chZ97r934SY/6QqPgMAZvbOWg6wFZjjLvIjWFOfoBrPMvit4R6wkg/Ay5Sh
SbMqHR8Q/VXNz7ToD9zuxzHUkWQSRSchT5gMEQcdCVlgun40ar6y6+V9xOHOFftO5k1VpLMC6Qum
xXLVx5E0OvpF8PIBySwUDst7XfpfI1Vh0FRS3WeP9dYYp8cNTc89g37vvOQmt+503SRwh5lqrwSr
+oNY/KU/DU3RpWZ8pFkxODwlwcZHlUaZYinvaKW6qEJ5viQrIl+rA6JD3mdOZ8CfkMH6ynsoeyYc
JHIrvmOR3YIzwkg2KZcqJBSX9EiBNv6dmKsFHygJe8p6wwjPiQQ7k6EEvAMqIYC/48LG4vyYE2BW
CvU/HFLhqysWtzPG0/stG+EFn7RTQWREV3p4Phh65uuqh+xDK8u8LDn2PwGDoLjpaZfwJbAi2Pr4
Sf6jXdzd6rTGYIhPBxUFuH4H/27xgkjtLhmSF7dMoNTabGj0Y8hZNx4+K3jTKg30cUWAKvHJvYwo
NE5JQY3YipnmADfBhEPlXdwRrE7u5smwbkhBpTcWKLvOcq/3ilniKwhso9LHqDx4jSX8f122CZVQ
Hnk2+LGnjJn/BkRfDntLKaNTHnSqWaaVmzyrUpu7uPi2iDnyZg0QoD7dE1zePWtl52AtlfuugZol
N8jmdWSdmzIh1+cAFbtOhVLc96qSPYJncREPlAjEsL4HNHlYDNd5AFFCoRGn9fpYN9pqbOxV13Sj
fWss9zN44N3OhK3o5Z8CqVmtjHbMEVYavgHnVbMtuDzXMEnbYqRbEwEuU2624z3pM8XCc5hcZBul
xnaCQqFjFRmOziUvPCINhbvQjiQigOewb0QvTkg9b/G8JCjr+WBHIjMHv2orVT7ccwn4ga4h+XWl
O3oKeGlIBQsNSZehOqK/iQ==
`protect end_protected
|
-- $Id: cmoda7lib.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: cmoda7lib
-- Description: CmodA7 components
--
-- Dependencies: -
-- Tool versions: viv 2016.4-2017.1; ghdl 0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2017-06-11 912 1.1 add c7_sram_memctl
-- 2017-06-04 906 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package cmoda7lib is
component cmoda7_aif is -- CmodA7, abstract iface, base
port (
I_CLK12 : in slbit; -- 12 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_BTN : in slv2; -- c7 buttons
O_LED : out slv2; -- c7 leds
O_RGBLED0_N: out slv3 -- c7 rgb-led 0 (act.low)
);
end component;
component cmoda7_sram_aif is -- CmodA7, abstract iface, base+sram
port (
I_CLK12 : in slbit; -- 12 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_BTN : in slv2; -- c7 buttons
O_LED : out slv2; -- c7 leds
O_RGBLED0_N: out slv3; -- c7 rgb-led 0 (act.low)
O_MEM_CE_N : out slbit; -- sram: chip enable (act.low)
O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
O_MEM_ADDR : out slv19; -- sram: address lines
IO_MEM_DATA : inout slv8 -- sram: data lines
);
end component;
component c7_sram_memctl is -- SRAM controller
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
REQ : in slbit; -- request
WE : in slbit; -- write enable
BUSY : out slbit; -- controller busy
ACK_R : out slbit; -- acknowledge read
ACK_W : out slbit; -- acknowledge write
ACT_R : out slbit; -- signal active read
ACT_W : out slbit; -- signal active write
ADDR : in slv17; -- address
BE : in slv4; -- byte enable
DI : in slv32; -- data in (memory view)
DO : out slv32; -- data out (memory view)
O_MEM_CE_N : out slbit; -- sram: chip enable (act.low)
O_MEM_WE_N : out slbit; -- sram: write enable (act.low)
O_MEM_OE_N : out slbit; -- sram: output enable (act.low)
O_MEM_ADDR : out slv19; -- sram: address lines
IO_MEM_DATA : inout slv8 -- sram: data lines
);
end component;
end package cmoda7lib;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity if01 is
port (c0, c1 : std_logic;
r : out std_logic);
end if01;
architecture behav of if01 is
begin
process (c0, c1)
begin
r <= '0';
if c0 = '1' then
if c1 = '1' then
r <= '1';
end if;
end if;
end process;
end behav;
|
entity vhpi4 is
end entity;
library ieee;
use ieee.std_logic_1164.all;
architecture test of vhpi4 is
function sum (x, y : integer) return integer;
attribute foreign of sum : function is "VHPIDIRECT __vhpi_sum";
type int_vec is array (natural range <>) of integer;
function sum_array (a : int_vec; len : integer) return integer;
attribute foreign of sum_array : function is "VHPIDIRECT __vhpi_sum_array";
function my_not (x : std_logic) return std_logic;
attribute foreign of my_not : function is "VHPIDIRECT __vhpi_my_not";
procedure test_proc (x : out integer; arr : out int_vec);
attribute foreign of test_proc : procedure is "VHPIDIRECT __vhpi_test_proc";
begin
main: process is
variable i : integer;
variable v : int_vec(1 to 3);
begin
assert sum(2, 3) = 5;
assert sum_array(int_vec'(1, 2, 3, 4, 5), 5) = 15;
assert my_not('1') = '0';
assert my_not('0') = '1';
assert my_not('U') = 'U';
test_proc(i, v);
assert i = 42;
assert v = (integer'left, 5, integer'left);
wait;
end process;
end architecture;
|
-- $Id: sys_conf_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2016- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_rlink_arty (for simulation)
--
-- Dependencies: -
-- Tool versions: viv 2015.4-2016.2; ghdl 0.33
-- Revision History:
-- Date Rev Version Comment
-- 2016-03-12 741 1.1 add sysmon_rbus
-- 2016-02-14 731 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
-- configure clocks --------------------------------------------------------
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 1; -- vco --- MHz
constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
-- single clock design, clkser = clksys
constant sys_conf_clkser_vcodivide : positive := sys_conf_clksys_vcodivide;
constant sys_conf_clkser_vcomultiply : positive := sys_conf_clksys_vcomultiply;
constant sys_conf_clkser_outdivide : positive := sys_conf_clksys_outdivide;
constant sys_conf_clkser_gentype : string := sys_conf_clksys_gentype;
-- configure rlink and hio interfaces --------------------------------------
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
-- configure further units -------------------------------------------------
constant sys_conf_rbd_sysmon : boolean := true; -- SYSMON(XADC)
-- derived constants =======================================================
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
end package sys_conf;
|
-------------------------------------------------------------------------------
--
-- Title : 8b/10b Encoder
-- Design : 8-bit to 10-bit Encoder
-- Project : 8000 - 8b10b_encdec
-- Author : Ken Boyette
-- Company : Critia Computer, Inc.
--
-------------------------------------------------------------------------------
--
-- File : 8b10b_enc.vhd
-- Version : 1.0
-- Generated : 09.15.2006
-- By : Itf2Vhdl ver. 1.20
--
-------------------------------------------------------------------------------
--
-- Description :
-- This module provides 8-bit to 10-bit encoding.
-- It accepts 8-bit parallel data input and generates 10-bit encoded data
-- output in accordance with the 8b/10b standard. This coding method was
-- described in the 1983 IBM publication "A DC-Balanced, Partitioned-Block,
-- 8B/10B Transmission Code" by A.X. Widmer and P.A. Franaszek and was granted
-- a U.S. Patent #4,486,739 in 1984 which has now expired.
--
-- The parallel 8-bit Binary input represent 256 possible values, called
-- characters.
-- The bits are identified as:
-- HI, GI, FI, EI, DI, CI, BI, AI (Most Significant to Least)
-- The output is a 10-bit encoded character whose bits are identified as:
-- AO, BO, CO, DO, EO, IO, FO, GO, HO, AJO (Least Significant to Most)
-- An additional 12 output characters, K, are defined for command and
-- synchronization use.
-- KI, is used to indicate that the input is for a special character.
-- All inputs and outputs are synchronous with an externally supplied
-- byte rate clock BYTECLK.
-- The encoded output is valid one clock after the input.
-- There is a reset input, RESET, to reset the logic. The next rising
-- BYTECLK after RESET is deasserted latches valid input data.
--
-- Note: This VHDL structure closely follows the discrete logic defined
-- in the original article and the subsequent patent.
-- The Figures referenced are those in the patent.
-------------------------------------------------------------------------------
-- This program is licensed under the GPL.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity enc_8b10b is
port(
RESET : in std_logic ; -- Global asynchronous reset (active high)
clk : in std_logic ;
ena : in std_logic ;
--enaFall : in std_logic ;
--SBYTECLK : in std_logic ; -- Master synchronous send byte clock
KI : in std_logic ; -- Control (K) input(active high)
AI, BI, CI, DI, EI, FI, GI, HI : in std_logic ; -- Unencoded input data
JO, HO, GO, FO, IO, EO, DO, CO, BO, AO : out std_logic -- Encoded out
);
end enc_8b10b;
architecture behavioral of enc_8b10b is
-- Signals to tie things together
signal XLRESET, LRESET : std_logic ; -- Local synchronized RESET
signal L40, L04, L13, L31, L22 : std_logic ; -- Figure 3 Signals
signal F4, G4, H4, K4, S, FNEG : std_logic ; -- Figure 4 Signals
signal PD1S6, ND1S6, PD0S6, ND0S6 : std_logic ; -- Figure 5 Signals
signal ND1S4, ND0S4, PD1S4, PD0S4 : std_logic ; -- ...Figure 5
signal COMPLS4, COMPLS6, NDL6 : std_logic ; -- Figure 6 Signals
signal PDL6, LPDL6, PDL4, LPDL4 : std_logic ; -- Figure 6
signal NAO, NBO, NCO, NDO, NEO, NIO : std_logic ; -- Figure 7 Signals
signal NFO, NGO, NHO, NJO, SINT : std_logic ; -- Figure 8
begin
-- PROCESS: SYNCRST; Synchronize and delay RESET one clock for startup
SYNCRST1: process (clk)--(RESET, SBYTECLK)
begin
if clk'event and clk = '1' then --if SBYTECLK'event and SBYTECLK = '1' then
if ena = '1' then
XLRESET <= RESET ;
end if ;
end if ;
end process SYNCRST1 ;
SYNCRST2: process (clk)--(XLRESET, SBYTECLK)
begin
if clk'event and clk = '0' then --if SBYTECLK'event and SBYTECLK = '0' then
if ena = '1' then
LRESET <= XLRESET ;
end if ;
end if ;
end process SYNCRST2 ;
--
-- 5b Input Function (Reference: Figure 3)
--
-- Four 1's
L40 <= AI and BI and CI and DI ; -- 1,1,1,1
-- Four 0's
L04 <= not AI and not BI and not CI and not DI ; -- 0,0,0,0
-- One 1 and three 0's
L13 <= (not AI and not BI and not CI and DI) -- 0,0,0,1
or (not AI and not BI and CI and not DI) -- 0,0,1,0
or (not AI and BI and not CI and not DI) -- 0,1,0,0
or (AI and not BI and not CI and not DI) ; -- 1,0,0,0
-- Three 1's and one 0
L31 <= (AI and BI and CI and not DI) -- 1,1,1,0
or (AI and BI and not CI and DI) -- 1,1,0,1
or (AI and not BI and CI and DI) -- 1,0,1,1
or (not AI and BI and CI and DI) ; -- 0,1,1,1
-- Two 1's and two 0's
L22 <= (not AI and not BI and CI and DI) -- 0,0,1,1
or (not AI and BI and CI and not DI) -- 0,1,1,0
or (AI and BI and not CI and not DI) -- 1,1,0,0
or (AI and not BI and not CI and DI) -- 1,0,0,1
or (not AI and BI and not CI and DI) -- 0,1,0,1
or (AI and not BI and CI and not DI) ; -- 1,0,1,0
--
-- 3b Input Function (Reference: Figure 4)
--
-- PROCESS: FN3B; Latch 3b and K inputs
FN3B: process (clk)--(SBYTECLK, FI, GI, HI, KI)
begin -- Falling edge of clock latches F,G,H,K inputs
if clk'event and clk = '0' then --if SBYTECLK'event and SBYTECLK = '0' then
if ena = '1' then
F4 <= FI ;
G4 <= GI ;
H4 <= HI ;
K4 <= KI ;
end if;
end if;
end process FN3B;
-- PROCESS: FNS; Create and latch "S" function
FNS: process (clk, LRESET)--(LRESET, SBYTECLK, PDL6, L31, DI, EI, NDL6, L13)
begin
if LRESET = '1' then
S <= '0' ;
elsif clk'event and clk = '1' then --elsif SBYTECLK'event and SBYTECLK = '1' then
if ena = '1' then
S <= (PDL6 and L31 and DI and not EI)
or (NDL6 and L13 and EI and not DI) ;
end if;
end if;
end process FNS ;
-- Intermediate term for "F4 is Not Equal to G4"
FNEG <= F4 xor G4 ;
--
-- Disparity Control - Figure 5
--
PD1S6 <= (not L22 and not L31 and not EI)
or (L13 and DI and EI) ;
ND1S6 <= (L31 and not DI and not EI)
or (EI and not L22 and not L13)
or K4 ;
PD0S6 <= (not L22 and not L13 and EI)
or K4 ;
ND0S6 <= (not L22 and not L31 and not EI)
or (L13 and DI and EI) ;
ND1S4 <= (F4 and G4);
ND0S4 <= (not F4 and not G4);
PD1S4 <= (not F4 and not G4)
or (FNEG and K4) ;
PD0S4 <= (F4 and G4 and H4) ;
--
-- Disparity Control - Figure 6
--
PDL6 <= (PD0S6 and not COMPLS6)
or (COMPLS6 and ND0S6)
or (not ND0S6 and not PD0S6 and LPDL4) ;
NDL6 <= not PDL6 ;
PDL4 <= (LPDL6 and not PD0S4 and not ND0S4)
or (ND0S4 and COMPLS4)
or (not COMPLS4 and PD0S4) ;
-- PROCESS: CMPLS4; Disparity determines complimenting S4
CMPLS4: process (clk, LRESET)--(LRESET, SBYTECLK, PDL6)
begin
if LRESET = '1' then
LPDL6 <= '0' ;
elsif clk'event and clk = '1' then --elsif SBYTECLK'event and SBYTECLK = '1' then -- Rising edge
if ena = '1' then
LPDL6 <= PDL6 ; -- .. latches S4
end if;
end if;
end process CMPLS4 ;
COMPLS4 <= (PD1S4 and not LPDL6)
xor (ND1S4 and LPDL6) ;
-- PROCESS: CMPLS6; Disparity determines complimenting S6
CMPLS6: process (clk, LRESET)--(LRESET, SBYTECLK, PDL4)
begin
if LRESET = '1' then
LPDL4 <= '0' ;
elsif clk'event and clk = '0' then --elsif SBYTECLK'event and SBYTECLK = '0' then -- Falling edge
if ena = '1' then
LPDL4 <= PDL4 ; -- .. latches S6
end if;
end if;
end process CMPLS6;
COMPLS6 <= (ND1S6 and LPDL4)
xor (PD1S6 and not LPDL4) ;
--
-- 5b/6b Encoder - Figure 7
--
-- Logic for non-complimented (Normal) A,B,C,D,E,I outputs
NAO <= AI ;
NBO <= L04
or (BI and not L40) ;
NCO <= CI
or L04
or (L13 and DI and EI) ;
NDO <= (DI and not L40) ;
NEO <= (EI and not (L13 and DI and EI))
or (L13 and not EI) ;
NIO <= (L22 and not EI)
or (L04 and EI)
or (L13 and not DI and EI)
or (L40 and EI)
or (L22 and KI) ;
-- PROCESS: ENC5B6B; Generate and latch LS 6 encoded bits
ENC5B6B: process (clk, LRESET)--(LRESET, SBYTECLK, COMPLS6, NAO, NBO, NCO, NDO, NEO, NIO)
begin
if LRESET = '1' then
AO <= '0' ;
BO <= '0' ;
CO <= '0' ;
DO <= '0' ;
EO <= '0' ;
IO <= '0' ;
elsif clk'event and clk = '1' then --elsif SBYTECLK'event and SBYTECLK = '1' then
if ena = '1' then
AO <= COMPLS6 XOR NAO ; -- Least significant bit 0
BO <= COMPLS6 XOR NBO ;
CO <= COMPLS6 XOR NCO ;
DO <= COMPLS6 XOR NDO ;
EO <= COMPLS6 XOR NEO ;
IO <= COMPLS6 XOR NIO ; -- Most significant bit 6
end if;
end if;
end process ENC5B6B;
--
-- 3b/4b Encoder - Figure 8
--
-- Logic for the non-complimented F,G,H,J outputs
SINT <= (S and F4 and G4 and H4)
or (K4 and F4 and G4 and H4) ;
NFO <= (F4 and not SINT) ;
NGO <= G4
or (not F4 and not G4 and not H4) ;
NHO <= H4 ;
NJO <= SINT
or (FNEG and not H4) ;
-- PROCESS: ENC3B4B; Generate and latch MS 4 encoded bits
ENC3B4B: process (clk, LRESET)--(LRESET, SBYTECLK, COMPLS4, NFO, NGO, NHO, NJO)
begin
if LRESET = '1' then
FO <= '0' ;
GO <= '0' ;
HO <= '0' ;
JO <= '0' ;
elsif clk'event and clk = '0' then --elsif SBYTECLK'event and SBYTECLK ='0' then
if ena = '1' then
FO <= COMPLS4 XOR NFO ; -- Least significant bit 7
GO <= COMPLS4 XOR NGO ;
HO <= COMPLS4 XOR NHO ;
JO <= COMPLS4 XOR NJO ; -- Most significant bit 10
end if;
end if;
end process ENC3B4B ;
end behavioral; |
-------------------------------------------------------------------------------
--
-- Title : 8b/10b Encoder
-- Design : 8-bit to 10-bit Encoder
-- Project : 8000 - 8b10b_encdec
-- Author : Ken Boyette
-- Company : Critia Computer, Inc.
--
-------------------------------------------------------------------------------
--
-- File : 8b10b_enc.vhd
-- Version : 1.0
-- Generated : 09.15.2006
-- By : Itf2Vhdl ver. 1.20
--
-------------------------------------------------------------------------------
--
-- Description :
-- This module provides 8-bit to 10-bit encoding.
-- It accepts 8-bit parallel data input and generates 10-bit encoded data
-- output in accordance with the 8b/10b standard. This coding method was
-- described in the 1983 IBM publication "A DC-Balanced, Partitioned-Block,
-- 8B/10B Transmission Code" by A.X. Widmer and P.A. Franaszek and was granted
-- a U.S. Patent #4,486,739 in 1984 which has now expired.
--
-- The parallel 8-bit Binary input represent 256 possible values, called
-- characters.
-- The bits are identified as:
-- HI, GI, FI, EI, DI, CI, BI, AI (Most Significant to Least)
-- The output is a 10-bit encoded character whose bits are identified as:
-- AO, BO, CO, DO, EO, IO, FO, GO, HO, AJO (Least Significant to Most)
-- An additional 12 output characters, K, are defined for command and
-- synchronization use.
-- KI, is used to indicate that the input is for a special character.
-- All inputs and outputs are synchronous with an externally supplied
-- byte rate clock BYTECLK.
-- The encoded output is valid one clock after the input.
-- There is a reset input, RESET, to reset the logic. The next rising
-- BYTECLK after RESET is deasserted latches valid input data.
--
-- Note: This VHDL structure closely follows the discrete logic defined
-- in the original article and the subsequent patent.
-- The Figures referenced are those in the patent.
-------------------------------------------------------------------------------
-- This program is licensed under the GPL.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity enc_8b10b is
port(
RESET : in std_logic ; -- Global asynchronous reset (active high)
clk : in std_logic ;
ena : in std_logic ;
--enaFall : in std_logic ;
--SBYTECLK : in std_logic ; -- Master synchronous send byte clock
KI : in std_logic ; -- Control (K) input(active high)
AI, BI, CI, DI, EI, FI, GI, HI : in std_logic ; -- Unencoded input data
JO, HO, GO, FO, IO, EO, DO, CO, BO, AO : out std_logic -- Encoded out
);
end enc_8b10b;
architecture behavioral of enc_8b10b is
-- Signals to tie things together
signal XLRESET, LRESET : std_logic ; -- Local synchronized RESET
signal L40, L04, L13, L31, L22 : std_logic ; -- Figure 3 Signals
signal F4, G4, H4, K4, S, FNEG : std_logic ; -- Figure 4 Signals
signal PD1S6, ND1S6, PD0S6, ND0S6 : std_logic ; -- Figure 5 Signals
signal ND1S4, ND0S4, PD1S4, PD0S4 : std_logic ; -- ...Figure 5
signal COMPLS4, COMPLS6, NDL6 : std_logic ; -- Figure 6 Signals
signal PDL6, LPDL6, PDL4, LPDL4 : std_logic ; -- Figure 6
signal NAO, NBO, NCO, NDO, NEO, NIO : std_logic ; -- Figure 7 Signals
signal NFO, NGO, NHO, NJO, SINT : std_logic ; -- Figure 8
begin
-- PROCESS: SYNCRST; Synchronize and delay RESET one clock for startup
SYNCRST1: process (clk)--(RESET, SBYTECLK)
begin
if clk'event and clk = '1' then --if SBYTECLK'event and SBYTECLK = '1' then
if ena = '1' then
XLRESET <= RESET ;
end if ;
end if ;
end process SYNCRST1 ;
SYNCRST2: process (clk)--(XLRESET, SBYTECLK)
begin
if clk'event and clk = '0' then --if SBYTECLK'event and SBYTECLK = '0' then
if ena = '1' then
LRESET <= XLRESET ;
end if ;
end if ;
end process SYNCRST2 ;
--
-- 5b Input Function (Reference: Figure 3)
--
-- Four 1's
L40 <= AI and BI and CI and DI ; -- 1,1,1,1
-- Four 0's
L04 <= not AI and not BI and not CI and not DI ; -- 0,0,0,0
-- One 1 and three 0's
L13 <= (not AI and not BI and not CI and DI) -- 0,0,0,1
or (not AI and not BI and CI and not DI) -- 0,0,1,0
or (not AI and BI and not CI and not DI) -- 0,1,0,0
or (AI and not BI and not CI and not DI) ; -- 1,0,0,0
-- Three 1's and one 0
L31 <= (AI and BI and CI and not DI) -- 1,1,1,0
or (AI and BI and not CI and DI) -- 1,1,0,1
or (AI and not BI and CI and DI) -- 1,0,1,1
or (not AI and BI and CI and DI) ; -- 0,1,1,1
-- Two 1's and two 0's
L22 <= (not AI and not BI and CI and DI) -- 0,0,1,1
or (not AI and BI and CI and not DI) -- 0,1,1,0
or (AI and BI and not CI and not DI) -- 1,1,0,0
or (AI and not BI and not CI and DI) -- 1,0,0,1
or (not AI and BI and not CI and DI) -- 0,1,0,1
or (AI and not BI and CI and not DI) ; -- 1,0,1,0
--
-- 3b Input Function (Reference: Figure 4)
--
-- PROCESS: FN3B; Latch 3b and K inputs
FN3B: process (clk)--(SBYTECLK, FI, GI, HI, KI)
begin -- Falling edge of clock latches F,G,H,K inputs
if clk'event and clk = '0' then --if SBYTECLK'event and SBYTECLK = '0' then
if ena = '1' then
F4 <= FI ;
G4 <= GI ;
H4 <= HI ;
K4 <= KI ;
end if;
end if;
end process FN3B;
-- PROCESS: FNS; Create and latch "S" function
FNS: process (clk, LRESET)--(LRESET, SBYTECLK, PDL6, L31, DI, EI, NDL6, L13)
begin
if LRESET = '1' then
S <= '0' ;
elsif clk'event and clk = '1' then --elsif SBYTECLK'event and SBYTECLK = '1' then
if ena = '1' then
S <= (PDL6 and L31 and DI and not EI)
or (NDL6 and L13 and EI and not DI) ;
end if;
end if;
end process FNS ;
-- Intermediate term for "F4 is Not Equal to G4"
FNEG <= F4 xor G4 ;
--
-- Disparity Control - Figure 5
--
PD1S6 <= (not L22 and not L31 and not EI)
or (L13 and DI and EI) ;
ND1S6 <= (L31 and not DI and not EI)
or (EI and not L22 and not L13)
or K4 ;
PD0S6 <= (not L22 and not L13 and EI)
or K4 ;
ND0S6 <= (not L22 and not L31 and not EI)
or (L13 and DI and EI) ;
ND1S4 <= (F4 and G4);
ND0S4 <= (not F4 and not G4);
PD1S4 <= (not F4 and not G4)
or (FNEG and K4) ;
PD0S4 <= (F4 and G4 and H4) ;
--
-- Disparity Control - Figure 6
--
PDL6 <= (PD0S6 and not COMPLS6)
or (COMPLS6 and ND0S6)
or (not ND0S6 and not PD0S6 and LPDL4) ;
NDL6 <= not PDL6 ;
PDL4 <= (LPDL6 and not PD0S4 and not ND0S4)
or (ND0S4 and COMPLS4)
or (not COMPLS4 and PD0S4) ;
-- PROCESS: CMPLS4; Disparity determines complimenting S4
CMPLS4: process (clk, LRESET)--(LRESET, SBYTECLK, PDL6)
begin
if LRESET = '1' then
LPDL6 <= '0' ;
elsif clk'event and clk = '1' then --elsif SBYTECLK'event and SBYTECLK = '1' then -- Rising edge
if ena = '1' then
LPDL6 <= PDL6 ; -- .. latches S4
end if;
end if;
end process CMPLS4 ;
COMPLS4 <= (PD1S4 and not LPDL6)
xor (ND1S4 and LPDL6) ;
-- PROCESS: CMPLS6; Disparity determines complimenting S6
CMPLS6: process (clk, LRESET)--(LRESET, SBYTECLK, PDL4)
begin
if LRESET = '1' then
LPDL4 <= '0' ;
elsif clk'event and clk = '0' then --elsif SBYTECLK'event and SBYTECLK = '0' then -- Falling edge
if ena = '1' then
LPDL4 <= PDL4 ; -- .. latches S6
end if;
end if;
end process CMPLS6;
COMPLS6 <= (ND1S6 and LPDL4)
xor (PD1S6 and not LPDL4) ;
--
-- 5b/6b Encoder - Figure 7
--
-- Logic for non-complimented (Normal) A,B,C,D,E,I outputs
NAO <= AI ;
NBO <= L04
or (BI and not L40) ;
NCO <= CI
or L04
or (L13 and DI and EI) ;
NDO <= (DI and not L40) ;
NEO <= (EI and not (L13 and DI and EI))
or (L13 and not EI) ;
NIO <= (L22 and not EI)
or (L04 and EI)
or (L13 and not DI and EI)
or (L40 and EI)
or (L22 and KI) ;
-- PROCESS: ENC5B6B; Generate and latch LS 6 encoded bits
ENC5B6B: process (clk, LRESET)--(LRESET, SBYTECLK, COMPLS6, NAO, NBO, NCO, NDO, NEO, NIO)
begin
if LRESET = '1' then
AO <= '0' ;
BO <= '0' ;
CO <= '0' ;
DO <= '0' ;
EO <= '0' ;
IO <= '0' ;
elsif clk'event and clk = '1' then --elsif SBYTECLK'event and SBYTECLK = '1' then
if ena = '1' then
AO <= COMPLS6 XOR NAO ; -- Least significant bit 0
BO <= COMPLS6 XOR NBO ;
CO <= COMPLS6 XOR NCO ;
DO <= COMPLS6 XOR NDO ;
EO <= COMPLS6 XOR NEO ;
IO <= COMPLS6 XOR NIO ; -- Most significant bit 6
end if;
end if;
end process ENC5B6B;
--
-- 3b/4b Encoder - Figure 8
--
-- Logic for the non-complimented F,G,H,J outputs
SINT <= (S and F4 and G4 and H4)
or (K4 and F4 and G4 and H4) ;
NFO <= (F4 and not SINT) ;
NGO <= G4
or (not F4 and not G4 and not H4) ;
NHO <= H4 ;
NJO <= SINT
or (FNEG and not H4) ;
-- PROCESS: ENC3B4B; Generate and latch MS 4 encoded bits
ENC3B4B: process (clk, LRESET)--(LRESET, SBYTECLK, COMPLS4, NFO, NGO, NHO, NJO)
begin
if LRESET = '1' then
FO <= '0' ;
GO <= '0' ;
HO <= '0' ;
JO <= '0' ;
elsif clk'event and clk = '0' then --elsif SBYTECLK'event and SBYTECLK ='0' then
if ena = '1' then
FO <= COMPLS4 XOR NFO ; -- Least significant bit 7
GO <= COMPLS4 XOR NGO ;
HO <= COMPLS4 XOR NHO ;
JO <= COMPLS4 XOR NJO ; -- Most significant bit 10
end if;
end if;
end process ENC3B4B ;
end behavioral; |
-------------------------------------------------------------------------------
--
-- Title : 8b/10b Encoder
-- Design : 8-bit to 10-bit Encoder
-- Project : 8000 - 8b10b_encdec
-- Author : Ken Boyette
-- Company : Critia Computer, Inc.
--
-------------------------------------------------------------------------------
--
-- File : 8b10b_enc.vhd
-- Version : 1.0
-- Generated : 09.15.2006
-- By : Itf2Vhdl ver. 1.20
--
-------------------------------------------------------------------------------
--
-- Description :
-- This module provides 8-bit to 10-bit encoding.
-- It accepts 8-bit parallel data input and generates 10-bit encoded data
-- output in accordance with the 8b/10b standard. This coding method was
-- described in the 1983 IBM publication "A DC-Balanced, Partitioned-Block,
-- 8B/10B Transmission Code" by A.X. Widmer and P.A. Franaszek and was granted
-- a U.S. Patent #4,486,739 in 1984 which has now expired.
--
-- The parallel 8-bit Binary input represent 256 possible values, called
-- characters.
-- The bits are identified as:
-- HI, GI, FI, EI, DI, CI, BI, AI (Most Significant to Least)
-- The output is a 10-bit encoded character whose bits are identified as:
-- AO, BO, CO, DO, EO, IO, FO, GO, HO, AJO (Least Significant to Most)
-- An additional 12 output characters, K, are defined for command and
-- synchronization use.
-- KI, is used to indicate that the input is for a special character.
-- All inputs and outputs are synchronous with an externally supplied
-- byte rate clock BYTECLK.
-- The encoded output is valid one clock after the input.
-- There is a reset input, RESET, to reset the logic. The next rising
-- BYTECLK after RESET is deasserted latches valid input data.
--
-- Note: This VHDL structure closely follows the discrete logic defined
-- in the original article and the subsequent patent.
-- The Figures referenced are those in the patent.
-------------------------------------------------------------------------------
-- This program is licensed under the GPL.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity enc_8b10b is
port(
RESET : in std_logic ; -- Global asynchronous reset (active high)
clk : in std_logic ;
ena : in std_logic ;
--enaFall : in std_logic ;
--SBYTECLK : in std_logic ; -- Master synchronous send byte clock
KI : in std_logic ; -- Control (K) input(active high)
AI, BI, CI, DI, EI, FI, GI, HI : in std_logic ; -- Unencoded input data
JO, HO, GO, FO, IO, EO, DO, CO, BO, AO : out std_logic -- Encoded out
);
end enc_8b10b;
architecture behavioral of enc_8b10b is
-- Signals to tie things together
signal XLRESET, LRESET : std_logic ; -- Local synchronized RESET
signal L40, L04, L13, L31, L22 : std_logic ; -- Figure 3 Signals
signal F4, G4, H4, K4, S, FNEG : std_logic ; -- Figure 4 Signals
signal PD1S6, ND1S6, PD0S6, ND0S6 : std_logic ; -- Figure 5 Signals
signal ND1S4, ND0S4, PD1S4, PD0S4 : std_logic ; -- ...Figure 5
signal COMPLS4, COMPLS6, NDL6 : std_logic ; -- Figure 6 Signals
signal PDL6, LPDL6, PDL4, LPDL4 : std_logic ; -- Figure 6
signal NAO, NBO, NCO, NDO, NEO, NIO : std_logic ; -- Figure 7 Signals
signal NFO, NGO, NHO, NJO, SINT : std_logic ; -- Figure 8
begin
-- PROCESS: SYNCRST; Synchronize and delay RESET one clock for startup
SYNCRST1: process (clk)--(RESET, SBYTECLK)
begin
if clk'event and clk = '1' then --if SBYTECLK'event and SBYTECLK = '1' then
if ena = '1' then
XLRESET <= RESET ;
end if ;
end if ;
end process SYNCRST1 ;
SYNCRST2: process (clk)--(XLRESET, SBYTECLK)
begin
if clk'event and clk = '0' then --if SBYTECLK'event and SBYTECLK = '0' then
if ena = '1' then
LRESET <= XLRESET ;
end if ;
end if ;
end process SYNCRST2 ;
--
-- 5b Input Function (Reference: Figure 3)
--
-- Four 1's
L40 <= AI and BI and CI and DI ; -- 1,1,1,1
-- Four 0's
L04 <= not AI and not BI and not CI and not DI ; -- 0,0,0,0
-- One 1 and three 0's
L13 <= (not AI and not BI and not CI and DI) -- 0,0,0,1
or (not AI and not BI and CI and not DI) -- 0,0,1,0
or (not AI and BI and not CI and not DI) -- 0,1,0,0
or (AI and not BI and not CI and not DI) ; -- 1,0,0,0
-- Three 1's and one 0
L31 <= (AI and BI and CI and not DI) -- 1,1,1,0
or (AI and BI and not CI and DI) -- 1,1,0,1
or (AI and not BI and CI and DI) -- 1,0,1,1
or (not AI and BI and CI and DI) ; -- 0,1,1,1
-- Two 1's and two 0's
L22 <= (not AI and not BI and CI and DI) -- 0,0,1,1
or (not AI and BI and CI and not DI) -- 0,1,1,0
or (AI and BI and not CI and not DI) -- 1,1,0,0
or (AI and not BI and not CI and DI) -- 1,0,0,1
or (not AI and BI and not CI and DI) -- 0,1,0,1
or (AI and not BI and CI and not DI) ; -- 1,0,1,0
--
-- 3b Input Function (Reference: Figure 4)
--
-- PROCESS: FN3B; Latch 3b and K inputs
FN3B: process (clk)--(SBYTECLK, FI, GI, HI, KI)
begin -- Falling edge of clock latches F,G,H,K inputs
if clk'event and clk = '0' then --if SBYTECLK'event and SBYTECLK = '0' then
if ena = '1' then
F4 <= FI ;
G4 <= GI ;
H4 <= HI ;
K4 <= KI ;
end if;
end if;
end process FN3B;
-- PROCESS: FNS; Create and latch "S" function
FNS: process (clk, LRESET)--(LRESET, SBYTECLK, PDL6, L31, DI, EI, NDL6, L13)
begin
if LRESET = '1' then
S <= '0' ;
elsif clk'event and clk = '1' then --elsif SBYTECLK'event and SBYTECLK = '1' then
if ena = '1' then
S <= (PDL6 and L31 and DI and not EI)
or (NDL6 and L13 and EI and not DI) ;
end if;
end if;
end process FNS ;
-- Intermediate term for "F4 is Not Equal to G4"
FNEG <= F4 xor G4 ;
--
-- Disparity Control - Figure 5
--
PD1S6 <= (not L22 and not L31 and not EI)
or (L13 and DI and EI) ;
ND1S6 <= (L31 and not DI and not EI)
or (EI and not L22 and not L13)
or K4 ;
PD0S6 <= (not L22 and not L13 and EI)
or K4 ;
ND0S6 <= (not L22 and not L31 and not EI)
or (L13 and DI and EI) ;
ND1S4 <= (F4 and G4);
ND0S4 <= (not F4 and not G4);
PD1S4 <= (not F4 and not G4)
or (FNEG and K4) ;
PD0S4 <= (F4 and G4 and H4) ;
--
-- Disparity Control - Figure 6
--
PDL6 <= (PD0S6 and not COMPLS6)
or (COMPLS6 and ND0S6)
or (not ND0S6 and not PD0S6 and LPDL4) ;
NDL6 <= not PDL6 ;
PDL4 <= (LPDL6 and not PD0S4 and not ND0S4)
or (ND0S4 and COMPLS4)
or (not COMPLS4 and PD0S4) ;
-- PROCESS: CMPLS4; Disparity determines complimenting S4
CMPLS4: process (clk, LRESET)--(LRESET, SBYTECLK, PDL6)
begin
if LRESET = '1' then
LPDL6 <= '0' ;
elsif clk'event and clk = '1' then --elsif SBYTECLK'event and SBYTECLK = '1' then -- Rising edge
if ena = '1' then
LPDL6 <= PDL6 ; -- .. latches S4
end if;
end if;
end process CMPLS4 ;
COMPLS4 <= (PD1S4 and not LPDL6)
xor (ND1S4 and LPDL6) ;
-- PROCESS: CMPLS6; Disparity determines complimenting S6
CMPLS6: process (clk, LRESET)--(LRESET, SBYTECLK, PDL4)
begin
if LRESET = '1' then
LPDL4 <= '0' ;
elsif clk'event and clk = '0' then --elsif SBYTECLK'event and SBYTECLK = '0' then -- Falling edge
if ena = '1' then
LPDL4 <= PDL4 ; -- .. latches S6
end if;
end if;
end process CMPLS6;
COMPLS6 <= (ND1S6 and LPDL4)
xor (PD1S6 and not LPDL4) ;
--
-- 5b/6b Encoder - Figure 7
--
-- Logic for non-complimented (Normal) A,B,C,D,E,I outputs
NAO <= AI ;
NBO <= L04
or (BI and not L40) ;
NCO <= CI
or L04
or (L13 and DI and EI) ;
NDO <= (DI and not L40) ;
NEO <= (EI and not (L13 and DI and EI))
or (L13 and not EI) ;
NIO <= (L22 and not EI)
or (L04 and EI)
or (L13 and not DI and EI)
or (L40 and EI)
or (L22 and KI) ;
-- PROCESS: ENC5B6B; Generate and latch LS 6 encoded bits
ENC5B6B: process (clk, LRESET)--(LRESET, SBYTECLK, COMPLS6, NAO, NBO, NCO, NDO, NEO, NIO)
begin
if LRESET = '1' then
AO <= '0' ;
BO <= '0' ;
CO <= '0' ;
DO <= '0' ;
EO <= '0' ;
IO <= '0' ;
elsif clk'event and clk = '1' then --elsif SBYTECLK'event and SBYTECLK = '1' then
if ena = '1' then
AO <= COMPLS6 XOR NAO ; -- Least significant bit 0
BO <= COMPLS6 XOR NBO ;
CO <= COMPLS6 XOR NCO ;
DO <= COMPLS6 XOR NDO ;
EO <= COMPLS6 XOR NEO ;
IO <= COMPLS6 XOR NIO ; -- Most significant bit 6
end if;
end if;
end process ENC5B6B;
--
-- 3b/4b Encoder - Figure 8
--
-- Logic for the non-complimented F,G,H,J outputs
SINT <= (S and F4 and G4 and H4)
or (K4 and F4 and G4 and H4) ;
NFO <= (F4 and not SINT) ;
NGO <= G4
or (not F4 and not G4 and not H4) ;
NHO <= H4 ;
NJO <= SINT
or (FNEG and not H4) ;
-- PROCESS: ENC3B4B; Generate and latch MS 4 encoded bits
ENC3B4B: process (clk, LRESET)--(LRESET, SBYTECLK, COMPLS4, NFO, NGO, NHO, NJO)
begin
if LRESET = '1' then
FO <= '0' ;
GO <= '0' ;
HO <= '0' ;
JO <= '0' ;
elsif clk'event and clk = '0' then --elsif SBYTECLK'event and SBYTECLK ='0' then
if ena = '1' then
FO <= COMPLS4 XOR NFO ; -- Least significant bit 7
GO <= COMPLS4 XOR NGO ;
HO <= COMPLS4 XOR NHO ;
JO <= COMPLS4 XOR NJO ; -- Most significant bit 10
end if;
end if;
end process ENC3B4B ;
end behavioral; |
-------------------------------------------------------------------------------
--
-- Title : 8b/10b Encoder
-- Design : 8-bit to 10-bit Encoder
-- Project : 8000 - 8b10b_encdec
-- Author : Ken Boyette
-- Company : Critia Computer, Inc.
--
-------------------------------------------------------------------------------
--
-- File : 8b10b_enc.vhd
-- Version : 1.0
-- Generated : 09.15.2006
-- By : Itf2Vhdl ver. 1.20
--
-------------------------------------------------------------------------------
--
-- Description :
-- This module provides 8-bit to 10-bit encoding.
-- It accepts 8-bit parallel data input and generates 10-bit encoded data
-- output in accordance with the 8b/10b standard. This coding method was
-- described in the 1983 IBM publication "A DC-Balanced, Partitioned-Block,
-- 8B/10B Transmission Code" by A.X. Widmer and P.A. Franaszek and was granted
-- a U.S. Patent #4,486,739 in 1984 which has now expired.
--
-- The parallel 8-bit Binary input represent 256 possible values, called
-- characters.
-- The bits are identified as:
-- HI, GI, FI, EI, DI, CI, BI, AI (Most Significant to Least)
-- The output is a 10-bit encoded character whose bits are identified as:
-- AO, BO, CO, DO, EO, IO, FO, GO, HO, AJO (Least Significant to Most)
-- An additional 12 output characters, K, are defined for command and
-- synchronization use.
-- KI, is used to indicate that the input is for a special character.
-- All inputs and outputs are synchronous with an externally supplied
-- byte rate clock BYTECLK.
-- The encoded output is valid one clock after the input.
-- There is a reset input, RESET, to reset the logic. The next rising
-- BYTECLK after RESET is deasserted latches valid input data.
--
-- Note: This VHDL structure closely follows the discrete logic defined
-- in the original article and the subsequent patent.
-- The Figures referenced are those in the patent.
-------------------------------------------------------------------------------
-- This program is licensed under the GPL.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity enc_8b10b is
port(
RESET : in std_logic ; -- Global asynchronous reset (active high)
clk : in std_logic ;
ena : in std_logic ;
--enaFall : in std_logic ;
--SBYTECLK : in std_logic ; -- Master synchronous send byte clock
KI : in std_logic ; -- Control (K) input(active high)
AI, BI, CI, DI, EI, FI, GI, HI : in std_logic ; -- Unencoded input data
JO, HO, GO, FO, IO, EO, DO, CO, BO, AO : out std_logic -- Encoded out
);
end enc_8b10b;
architecture behavioral of enc_8b10b is
-- Signals to tie things together
signal XLRESET, LRESET : std_logic ; -- Local synchronized RESET
signal L40, L04, L13, L31, L22 : std_logic ; -- Figure 3 Signals
signal F4, G4, H4, K4, S, FNEG : std_logic ; -- Figure 4 Signals
signal PD1S6, ND1S6, PD0S6, ND0S6 : std_logic ; -- Figure 5 Signals
signal ND1S4, ND0S4, PD1S4, PD0S4 : std_logic ; -- ...Figure 5
signal COMPLS4, COMPLS6, NDL6 : std_logic ; -- Figure 6 Signals
signal PDL6, LPDL6, PDL4, LPDL4 : std_logic ; -- Figure 6
signal NAO, NBO, NCO, NDO, NEO, NIO : std_logic ; -- Figure 7 Signals
signal NFO, NGO, NHO, NJO, SINT : std_logic ; -- Figure 8
begin
-- PROCESS: SYNCRST; Synchronize and delay RESET one clock for startup
SYNCRST1: process (clk)--(RESET, SBYTECLK)
begin
if clk'event and clk = '1' then --if SBYTECLK'event and SBYTECLK = '1' then
if ena = '1' then
XLRESET <= RESET ;
end if ;
end if ;
end process SYNCRST1 ;
SYNCRST2: process (clk)--(XLRESET, SBYTECLK)
begin
if clk'event and clk = '0' then --if SBYTECLK'event and SBYTECLK = '0' then
if ena = '1' then
LRESET <= XLRESET ;
end if ;
end if ;
end process SYNCRST2 ;
--
-- 5b Input Function (Reference: Figure 3)
--
-- Four 1's
L40 <= AI and BI and CI and DI ; -- 1,1,1,1
-- Four 0's
L04 <= not AI and not BI and not CI and not DI ; -- 0,0,0,0
-- One 1 and three 0's
L13 <= (not AI and not BI and not CI and DI) -- 0,0,0,1
or (not AI and not BI and CI and not DI) -- 0,0,1,0
or (not AI and BI and not CI and not DI) -- 0,1,0,0
or (AI and not BI and not CI and not DI) ; -- 1,0,0,0
-- Three 1's and one 0
L31 <= (AI and BI and CI and not DI) -- 1,1,1,0
or (AI and BI and not CI and DI) -- 1,1,0,1
or (AI and not BI and CI and DI) -- 1,0,1,1
or (not AI and BI and CI and DI) ; -- 0,1,1,1
-- Two 1's and two 0's
L22 <= (not AI and not BI and CI and DI) -- 0,0,1,1
or (not AI and BI and CI and not DI) -- 0,1,1,0
or (AI and BI and not CI and not DI) -- 1,1,0,0
or (AI and not BI and not CI and DI) -- 1,0,0,1
or (not AI and BI and not CI and DI) -- 0,1,0,1
or (AI and not BI and CI and not DI) ; -- 1,0,1,0
--
-- 3b Input Function (Reference: Figure 4)
--
-- PROCESS: FN3B; Latch 3b and K inputs
FN3B: process (clk)--(SBYTECLK, FI, GI, HI, KI)
begin -- Falling edge of clock latches F,G,H,K inputs
if clk'event and clk = '0' then --if SBYTECLK'event and SBYTECLK = '0' then
if ena = '1' then
F4 <= FI ;
G4 <= GI ;
H4 <= HI ;
K4 <= KI ;
end if;
end if;
end process FN3B;
-- PROCESS: FNS; Create and latch "S" function
FNS: process (clk, LRESET)--(LRESET, SBYTECLK, PDL6, L31, DI, EI, NDL6, L13)
begin
if LRESET = '1' then
S <= '0' ;
elsif clk'event and clk = '1' then --elsif SBYTECLK'event and SBYTECLK = '1' then
if ena = '1' then
S <= (PDL6 and L31 and DI and not EI)
or (NDL6 and L13 and EI and not DI) ;
end if;
end if;
end process FNS ;
-- Intermediate term for "F4 is Not Equal to G4"
FNEG <= F4 xor G4 ;
--
-- Disparity Control - Figure 5
--
PD1S6 <= (not L22 and not L31 and not EI)
or (L13 and DI and EI) ;
ND1S6 <= (L31 and not DI and not EI)
or (EI and not L22 and not L13)
or K4 ;
PD0S6 <= (not L22 and not L13 and EI)
or K4 ;
ND0S6 <= (not L22 and not L31 and not EI)
or (L13 and DI and EI) ;
ND1S4 <= (F4 and G4);
ND0S4 <= (not F4 and not G4);
PD1S4 <= (not F4 and not G4)
or (FNEG and K4) ;
PD0S4 <= (F4 and G4 and H4) ;
--
-- Disparity Control - Figure 6
--
PDL6 <= (PD0S6 and not COMPLS6)
or (COMPLS6 and ND0S6)
or (not ND0S6 and not PD0S6 and LPDL4) ;
NDL6 <= not PDL6 ;
PDL4 <= (LPDL6 and not PD0S4 and not ND0S4)
or (ND0S4 and COMPLS4)
or (not COMPLS4 and PD0S4) ;
-- PROCESS: CMPLS4; Disparity determines complimenting S4
CMPLS4: process (clk, LRESET)--(LRESET, SBYTECLK, PDL6)
begin
if LRESET = '1' then
LPDL6 <= '0' ;
elsif clk'event and clk = '1' then --elsif SBYTECLK'event and SBYTECLK = '1' then -- Rising edge
if ena = '1' then
LPDL6 <= PDL6 ; -- .. latches S4
end if;
end if;
end process CMPLS4 ;
COMPLS4 <= (PD1S4 and not LPDL6)
xor (ND1S4 and LPDL6) ;
-- PROCESS: CMPLS6; Disparity determines complimenting S6
CMPLS6: process (clk, LRESET)--(LRESET, SBYTECLK, PDL4)
begin
if LRESET = '1' then
LPDL4 <= '0' ;
elsif clk'event and clk = '0' then --elsif SBYTECLK'event and SBYTECLK = '0' then -- Falling edge
if ena = '1' then
LPDL4 <= PDL4 ; -- .. latches S6
end if;
end if;
end process CMPLS6;
COMPLS6 <= (ND1S6 and LPDL4)
xor (PD1S6 and not LPDL4) ;
--
-- 5b/6b Encoder - Figure 7
--
-- Logic for non-complimented (Normal) A,B,C,D,E,I outputs
NAO <= AI ;
NBO <= L04
or (BI and not L40) ;
NCO <= CI
or L04
or (L13 and DI and EI) ;
NDO <= (DI and not L40) ;
NEO <= (EI and not (L13 and DI and EI))
or (L13 and not EI) ;
NIO <= (L22 and not EI)
or (L04 and EI)
or (L13 and not DI and EI)
or (L40 and EI)
or (L22 and KI) ;
-- PROCESS: ENC5B6B; Generate and latch LS 6 encoded bits
ENC5B6B: process (clk, LRESET)--(LRESET, SBYTECLK, COMPLS6, NAO, NBO, NCO, NDO, NEO, NIO)
begin
if LRESET = '1' then
AO <= '0' ;
BO <= '0' ;
CO <= '0' ;
DO <= '0' ;
EO <= '0' ;
IO <= '0' ;
elsif clk'event and clk = '1' then --elsif SBYTECLK'event and SBYTECLK = '1' then
if ena = '1' then
AO <= COMPLS6 XOR NAO ; -- Least significant bit 0
BO <= COMPLS6 XOR NBO ;
CO <= COMPLS6 XOR NCO ;
DO <= COMPLS6 XOR NDO ;
EO <= COMPLS6 XOR NEO ;
IO <= COMPLS6 XOR NIO ; -- Most significant bit 6
end if;
end if;
end process ENC5B6B;
--
-- 3b/4b Encoder - Figure 8
--
-- Logic for the non-complimented F,G,H,J outputs
SINT <= (S and F4 and G4 and H4)
or (K4 and F4 and G4 and H4) ;
NFO <= (F4 and not SINT) ;
NGO <= G4
or (not F4 and not G4 and not H4) ;
NHO <= H4 ;
NJO <= SINT
or (FNEG and not H4) ;
-- PROCESS: ENC3B4B; Generate and latch MS 4 encoded bits
ENC3B4B: process (clk, LRESET)--(LRESET, SBYTECLK, COMPLS4, NFO, NGO, NHO, NJO)
begin
if LRESET = '1' then
FO <= '0' ;
GO <= '0' ;
HO <= '0' ;
JO <= '0' ;
elsif clk'event and clk = '0' then --elsif SBYTECLK'event and SBYTECLK ='0' then
if ena = '1' then
FO <= COMPLS4 XOR NFO ; -- Least significant bit 7
GO <= COMPLS4 XOR NGO ;
HO <= COMPLS4 XOR NHO ;
JO <= COMPLS4 XOR NJO ; -- Most significant bit 10
end if;
end if;
end process ENC3B4B ;
end behavioral; |
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
-- Date : Tue Sep 17 19:44:37 2019
-- Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ gcd_zynq_snick_rst_ps7_0_49M_0_sim_netlist.vhdl
-- Design : gcd_zynq_snick_rst_ps7_0_49M_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg400-3
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync is
port (
lpf_asr_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
lpf_asr : in STD_LOGIC;
p_1_in : in STD_LOGIC;
p_2_in : in STD_LOGIC;
asr_lpf : in STD_LOGIC_VECTOR ( 0 to 0 );
aux_reset_in : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync is
signal asr_d1 : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => asr_d1,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aux_reset_in,
O => asr_d1
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d3,
Q => \^scndry_out\,
R => '0'
);
lpf_asr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EAAAAAA8"
)
port map (
I0 => lpf_asr,
I1 => p_1_in,
I2 => p_2_in,
I3 => \^scndry_out\,
I4 => asr_lpf(0),
O => lpf_asr_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 is
port (
lpf_exr_reg : out STD_LOGIC;
scndry_out : out STD_LOGIC;
lpf_exr : in STD_LOGIC;
p_3_out : in STD_LOGIC_VECTOR ( 2 downto 0 );
mb_debug_sys_rst : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 : entity is "cdc_sync";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 is
signal exr_d1 : STD_LOGIC;
signal s_level_out_d1_cdc_to : STD_LOGIC;
signal s_level_out_d2 : STD_LOGIC;
signal s_level_out_d3 : STD_LOGIC;
signal \^scndry_out\ : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\ : label is "PRIMITIVE";
begin
scndry_out <= \^scndry_out\;
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => exr_d1,
Q => s_level_out_d1_cdc_to,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => mb_debug_sys_rst,
I1 => ext_reset_in,
O => exr_d1
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d1_cdc_to,
Q => s_level_out_d2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d2,
Q => s_level_out_d3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => s_level_out_d3,
Q => \^scndry_out\,
R => '0'
);
lpf_exr_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"EAAAAAA8"
)
port map (
I0 => lpf_exr,
I1 => p_3_out(1),
I2 => p_3_out(2),
I3 => \^scndry_out\,
I4 => p_3_out(0),
O => lpf_exr_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n is
port (
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
seq_clr : in STD_LOGIC;
seq_cnt_en : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n is
signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 );
signal clear : STD_LOGIC;
signal q_int0 : STD_LOGIC_VECTOR ( 5 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \q_int[1]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \q_int[2]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \q_int[3]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \q_int[4]_i_1\ : label is "soft_lutpair0";
begin
Q(5 downto 0) <= \^q\(5 downto 0);
\q_int[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => q_int0(0)
);
\q_int[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => q_int0(1)
);
\q_int[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
I2 => \^q\(2),
O => q_int0(2)
);
\q_int[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
I3 => \^q\(3),
O => q_int0(3)
);
\q_int[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"7FFF8000"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
I4 => \^q\(4),
O => q_int0(4)
);
\q_int[5]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => seq_clr,
O => clear
);
\q_int[5]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"7FFFFFFF80000000"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \^q\(2),
I4 => \^q\(4),
I5 => \^q\(5),
O => q_int0(5)
);
\q_int_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(0),
Q => \^q\(0),
R => clear
);
\q_int_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(1),
Q => \^q\(1),
R => clear
);
\q_int_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(2),
Q => \^q\(2),
R => clear
);
\q_int_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(3),
Q => \^q\(3),
R => clear
);
\q_int_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(4),
Q => \^q\(4),
R => clear
);
\q_int_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => seq_cnt_en,
D => q_int0(5),
Q => \^q\(5),
R => clear
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf is
port (
lpf_int : out STD_LOGIC;
slowest_sync_clk : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf is
signal \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\ : STD_LOGIC;
signal \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\ : STD_LOGIC;
signal Q : STD_LOGIC;
signal asr_lpf : STD_LOGIC_VECTOR ( 0 to 0 );
signal lpf_asr : STD_LOGIC;
signal lpf_exr : STD_LOGIC;
signal \lpf_int0__0\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal p_2_in : STD_LOGIC;
signal p_3_in1_in : STD_LOGIC;
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of POR_SRL_I : label is "SRL16";
attribute box_type : string;
attribute box_type of POR_SRL_I : label is "PRIMITIVE";
attribute srl_name : string;
attribute srl_name of POR_SRL_I : label is "U0/\EXT_LPF/POR_SRL_I ";
begin
\ACTIVE_LOW_AUX.ACT_LO_AUX\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync
port map (
asr_lpf(0) => asr_lpf(0),
aux_reset_in => aux_reset_in,
lpf_asr => lpf_asr,
lpf_asr_reg => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\,
p_1_in => p_1_in,
p_2_in => p_2_in,
scndry_out => p_3_in1_in,
slowest_sync_clk => slowest_sync_clk
);
\ACTIVE_LOW_EXT.ACT_LO_EXT\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0
port map (
ext_reset_in => ext_reset_in,
lpf_exr => lpf_exr,
lpf_exr_reg => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\,
mb_debug_sys_rst => mb_debug_sys_rst,
p_3_out(2 downto 0) => p_3_out(2 downto 0),
scndry_out => p_3_out(3),
slowest_sync_clk => slowest_sync_clk
);
\AUX_LPF[1].asr_lpf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_in1_in,
Q => p_2_in,
R => '0'
);
\AUX_LPF[2].asr_lpf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_2_in,
Q => p_1_in,
R => '0'
);
\AUX_LPF[3].asr_lpf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_1_in,
Q => asr_lpf(0),
R => '0'
);
\EXT_LPF[1].exr_lpf_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(3),
Q => p_3_out(2),
R => '0'
);
\EXT_LPF[2].exr_lpf_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(2),
Q => p_3_out(1),
R => '0'
);
\EXT_LPF[3].exr_lpf_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(1),
Q => p_3_out(0),
R => '0'
);
POR_SRL_I: unisim.vcomponents.SRL16E
generic map(
INIT => X"FFFF"
)
port map (
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
CE => '1',
CLK => slowest_sync_clk,
D => '0',
Q => Q
);
lpf_asr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0\,
Q => lpf_asr,
R => '0'
);
lpf_exr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0\,
Q => lpf_exr,
R => '0'
);
lpf_int0: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFD"
)
port map (
I0 => dcm_locked,
I1 => lpf_exr,
I2 => lpf_asr,
I3 => Q,
O => \lpf_int0__0\
);
lpf_int_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \lpf_int0__0\,
Q => lpf_int,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr is
port (
MB_out : out STD_LOGIC;
Bsr_out : out STD_LOGIC;
Pr_out : out STD_LOGIC;
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ : out STD_LOGIC;
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ : out STD_LOGIC;
lpf_int : in STD_LOGIC;
slowest_sync_clk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr is
signal \^bsr_out\ : STD_LOGIC;
signal Core_i_1_n_0 : STD_LOGIC;
signal \^mb_out\ : STD_LOGIC;
signal \^pr_out\ : STD_LOGIC;
signal \bsr_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \bsr_dec_reg_n_0_[2]\ : STD_LOGIC;
signal bsr_i_1_n_0 : STD_LOGIC;
signal \core_dec[0]_i_1_n_0\ : STD_LOGIC;
signal \core_dec[2]_i_1_n_0\ : STD_LOGIC;
signal \core_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \core_dec_reg_n_0_[1]\ : STD_LOGIC;
signal from_sys_i_1_n_0 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal p_3_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \pr_dec0__0\ : STD_LOGIC;
signal \pr_dec_reg_n_0_[0]\ : STD_LOGIC;
signal \pr_dec_reg_n_0_[2]\ : STD_LOGIC;
signal pr_i_1_n_0 : STD_LOGIC;
signal seq_clr : STD_LOGIC;
signal seq_cnt : STD_LOGIC_VECTOR ( 5 downto 0 );
signal seq_cnt_en : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of Core_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \bsr_dec[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of bsr_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \core_dec[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \core_dec[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of from_sys_i_1 : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \pr_dec[0]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of pr_i_1 : label is "soft_lutpair4";
begin
Bsr_out <= \^bsr_out\;
MB_out <= \^mb_out\;
Pr_out <= \^pr_out\;
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^bsr_out\,
O => \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\
);
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^pr_out\,
O => \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\
);
Core_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^mb_out\,
I1 => p_0_in,
O => Core_i_1_n_0
);
Core_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Core_i_1_n_0,
Q => \^mb_out\,
S => lpf_int
);
SEQ_COUNTER: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n
port map (
Q(5 downto 0) => seq_cnt(5 downto 0),
seq_clr => seq_clr,
seq_cnt_en => seq_cnt_en,
slowest_sync_clk => slowest_sync_clk
);
\bsr_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0090"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(4),
I2 => seq_cnt(3),
I3 => seq_cnt(5),
O => p_5_out(0)
);
\bsr_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \bsr_dec_reg_n_0_[0]\,
O => p_5_out(2)
);
\bsr_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_5_out(0),
Q => \bsr_dec_reg_n_0_[0]\,
R => '0'
);
\bsr_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_5_out(2),
Q => \bsr_dec_reg_n_0_[2]\,
R => '0'
);
bsr_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^bsr_out\,
I1 => \bsr_dec_reg_n_0_[2]\,
O => bsr_i_1_n_0
);
bsr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => bsr_i_1_n_0,
Q => \^bsr_out\,
S => lpf_int
);
\core_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9000"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(4),
I2 => seq_cnt(3),
I3 => seq_cnt(5),
O => \core_dec[0]_i_1_n_0\
);
\core_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \core_dec_reg_n_0_[0]\,
O => \core_dec[2]_i_1_n_0\
);
\core_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \core_dec[0]_i_1_n_0\,
Q => \core_dec_reg_n_0_[0]\,
R => '0'
);
\core_dec_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \pr_dec0__0\,
Q => \core_dec_reg_n_0_[1]\,
R => '0'
);
\core_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => \core_dec[2]_i_1_n_0\,
Q => p_0_in,
R => '0'
);
from_sys_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^mb_out\,
I1 => seq_cnt_en,
O => from_sys_i_1_n_0
);
from_sys_reg: unisim.vcomponents.FDSE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => from_sys_i_1_n_0,
Q => seq_cnt_en,
S => lpf_int
);
pr_dec0: unisim.vcomponents.LUT4
generic map(
INIT => X"0018"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(0),
I2 => seq_cnt(2),
I3 => seq_cnt(1),
O => \pr_dec0__0\
);
\pr_dec[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0480"
)
port map (
I0 => seq_cnt_en,
I1 => seq_cnt(3),
I2 => seq_cnt(5),
I3 => seq_cnt(4),
O => p_3_out(0)
);
\pr_dec[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \core_dec_reg_n_0_[1]\,
I1 => \pr_dec_reg_n_0_[0]\,
O => p_3_out(2)
);
\pr_dec_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(0),
Q => \pr_dec_reg_n_0_[0]\,
R => '0'
);
\pr_dec_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => p_3_out(2),
Q => \pr_dec_reg_n_0_[2]\,
R => '0'
);
pr_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^pr_out\,
I1 => \pr_dec_reg_n_0_[2]\,
O => pr_i_1_n_0
);
pr_reg: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => pr_i_1_n_0,
Q => \^pr_out\,
S => lpf_int
);
seq_clr_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => '1',
Q => seq_clr,
R => lpf_int
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute C_AUX_RESET_HIGH : string;
attribute C_AUX_RESET_HIGH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is "1'b0";
attribute C_AUX_RST_WIDTH : integer;
attribute C_AUX_RST_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 4;
attribute C_EXT_RESET_HIGH : string;
attribute C_EXT_RESET_HIGH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is "1'b0";
attribute C_EXT_RST_WIDTH : integer;
attribute C_EXT_RST_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 4;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is "zynq";
attribute C_NUM_BUS_RST : integer;
attribute C_NUM_BUS_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1;
attribute C_NUM_INTERCONNECT_ARESETN : integer;
attribute C_NUM_INTERCONNECT_ARESETN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1;
attribute C_NUM_PERP_ARESETN : integer;
attribute C_NUM_PERP_ARESETN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1;
attribute C_NUM_PERP_RST : integer;
attribute C_NUM_PERP_RST of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset : entity is 1;
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset is
signal Bsr_out : STD_LOGIC;
signal MB_out : STD_LOGIC;
signal Pr_out : STD_LOGIC;
signal SEQ_n_3 : STD_LOGIC;
signal SEQ_n_4 : STD_LOGIC;
signal lpf_int : STD_LOGIC;
attribute box_type : string;
attribute box_type of \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ : label is "PRIMITIVE";
attribute box_type of \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ : label is "PRIMITIVE";
attribute box_type of \BSR_OUT_DFF[0].FDRE_BSR\ : label is "PRIMITIVE";
attribute box_type of FDRE_inst : label is "PRIMITIVE";
attribute box_type of \PR_OUT_DFF[0].FDRE_PER\ : label is "PRIMITIVE";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of bus_struct_reset : signal is "no";
attribute equivalent_register_removal of interconnect_aresetn : signal is "no";
attribute equivalent_register_removal of peripheral_aresetn : signal is "no";
attribute equivalent_register_removal of peripheral_reset : signal is "no";
begin
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => SEQ_n_3,
Q => interconnect_aresetn(0),
R => '0'
);
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\: unisim.vcomponents.FDRE
generic map(
INIT => '0',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => SEQ_n_4,
Q => peripheral_aresetn(0),
R => '0'
);
\BSR_OUT_DFF[0].FDRE_BSR\: unisim.vcomponents.FDRE
generic map(
INIT => '1',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Bsr_out,
Q => bus_struct_reset(0),
R => '0'
);
EXT_LPF: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf
port map (
aux_reset_in => aux_reset_in,
dcm_locked => dcm_locked,
ext_reset_in => ext_reset_in,
lpf_int => lpf_int,
mb_debug_sys_rst => mb_debug_sys_rst,
slowest_sync_clk => slowest_sync_clk
);
FDRE_inst: unisim.vcomponents.FDRE
generic map(
INIT => '1',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => MB_out,
Q => mb_reset,
R => '0'
);
\PR_OUT_DFF[0].FDRE_PER\: unisim.vcomponents.FDRE
generic map(
INIT => '1',
IS_C_INVERTED => '0',
IS_D_INVERTED => '0',
IS_R_INVERTED => '0'
)
port map (
C => slowest_sync_clk,
CE => '1',
D => Pr_out,
Q => peripheral_reset(0),
R => '0'
);
SEQ: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr
port map (
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N\ => SEQ_n_3,
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N\ => SEQ_n_4,
Bsr_out => Bsr_out,
MB_out => MB_out,
Pr_out => Pr_out,
lpf_int => lpf_int,
slowest_sync_clk => slowest_sync_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "gcd_zynq_snick_rst_ps7_0_49M_0,proc_sys_reset,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "proc_sys_reset,Vivado 2018.2";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute C_AUX_RESET_HIGH : string;
attribute C_AUX_RESET_HIGH of U0 : label is "1'b0";
attribute C_AUX_RST_WIDTH : integer;
attribute C_AUX_RST_WIDTH of U0 : label is 4;
attribute C_EXT_RESET_HIGH : string;
attribute C_EXT_RESET_HIGH of U0 : label is "1'b0";
attribute C_EXT_RST_WIDTH : integer;
attribute C_EXT_RST_WIDTH of U0 : label is 4;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_NUM_BUS_RST : integer;
attribute C_NUM_BUS_RST of U0 : label is 1;
attribute C_NUM_INTERCONNECT_ARESETN : integer;
attribute C_NUM_INTERCONNECT_ARESETN of U0 : label is 1;
attribute C_NUM_PERP_ARESETN : integer;
attribute C_NUM_PERP_ARESETN of U0 : label is 1;
attribute C_NUM_PERP_RST : integer;
attribute C_NUM_PERP_RST of U0 : label is 1;
attribute x_interface_info : string;
attribute x_interface_info of aux_reset_in : signal is "xilinx.com:signal:reset:1.0 aux_reset RST";
attribute x_interface_parameter : string;
attribute x_interface_parameter of aux_reset_in : signal is "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW";
attribute x_interface_info of ext_reset_in : signal is "xilinx.com:signal:reset:1.0 ext_reset RST";
attribute x_interface_parameter of ext_reset_in : signal is "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW";
attribute x_interface_info of mb_debug_sys_rst : signal is "xilinx.com:signal:reset:1.0 dbg_reset RST";
attribute x_interface_parameter of mb_debug_sys_rst : signal is "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH";
attribute x_interface_info of mb_reset : signal is "xilinx.com:signal:reset:1.0 mb_rst RST";
attribute x_interface_parameter of mb_reset : signal is "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR";
attribute x_interface_info of slowest_sync_clk : signal is "xilinx.com:signal:clock:1.0 clock CLK";
attribute x_interface_parameter of slowest_sync_clk : signal is "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 49999947, PHASE 0.000, CLK_DOMAIN gcd_zynq_snick_processing_system7_0_0_FCLK_CLK0";
attribute x_interface_info of bus_struct_reset : signal is "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
attribute x_interface_parameter of bus_struct_reset : signal is "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT";
attribute x_interface_info of interconnect_aresetn : signal is "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
attribute x_interface_parameter of interconnect_aresetn : signal is "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT";
attribute x_interface_info of peripheral_aresetn : signal is "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
attribute x_interface_parameter of peripheral_aresetn : signal is "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL";
attribute x_interface_info of peripheral_reset : signal is "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
attribute x_interface_parameter of peripheral_reset : signal is "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL";
begin
U0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset
port map (
aux_reset_in => aux_reset_in,
bus_struct_reset(0) => bus_struct_reset(0),
dcm_locked => dcm_locked,
ext_reset_in => ext_reset_in,
interconnect_aresetn(0) => interconnect_aresetn(0),
mb_debug_sys_rst => mb_debug_sys_rst,
mb_reset => mb_reset,
peripheral_aresetn(0) => peripheral_aresetn(0),
peripheral_reset(0) => peripheral_reset(0),
slowest_sync_clk => slowest_sync_clk
);
end STRUCTURE;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--library floatfixlib;
--use floatfixlib.float_pkg.all;
entity tp4 is
port (
clk_i : in std_logic; -- Clock general
data_i : in std_logic; -- Entrada de datos (UART)
-- Controles:
write_rst_i : in std_logic;
read_rst_i : in std_logic;
speed : in std_logic_vector(1 downto 0);
rot_switches_i : in std_logic_vector(5 downto 0);
-- Salidas
hs, vs: out std_logic; -- Output para el display VGA
red_o: out std_logic_vector(2 downto 0);
grn_o: out std_logic_vector(2 downto 0);
blu_o: out std_logic_vector(1 downto 0);
a,b,c,d,e,f,g,dp: out std_logic; -- Segmentos del display de 7 segmentos
-- Para controlar la memoria externa:
clock_out : out STD_LOGIC;
ADDRESS : out STD_LOGIC_VECTOR (22 downto 0);
ADV : out STD_LOGIC;
CRE : out STD_LOGIC;
CE : out STD_LOGIC;
OE : out STD_LOGIC;
WE : out STD_LOGIC;
LB : out STD_LOGIC;
UB : out STD_LOGIC;
DATA : inout STD_LOGIC_VECTOR (15 downto 0)
);
attribute loc: string;
--attribute CLOCK_DEDICATED_ROUTE: string;
--attribute CLOCK_DEDICATED_ROUTE of rst_i: signal is "false";
-- Mapeo de pines para el kit Nexys 2 (spartan 3E)
-- https://reference.digilentinc.com/_media/nexys:nexys2:nexys2_rm.pdf
attribute loc of clk_i: signal is "B8";
attribute loc of data_i: signal is "L15"; -- Pin físico de entrada de datos
-- VGA
attribute loc of hs: signal is "T4";
attribute loc of vs: signal is "U3";
attribute loc of red_o: signal is "R8 T8 R9";
attribute loc of grn_o: signal is "P6 P8 N8";
attribute loc of blu_o: signal is "U4 U5";
-- Switches
-- attribute loc of rot_on: signal is "R17"; -- Prender rotación constante
-- attribute loc of rot_vel: signal is "N17"; -- Velocidad lenta o rápida
-- attribute loc of rot_x_on: signal is "L13"; -- Rotación en x
-- attribute loc of rot_y_on: signal is "K17"; -- Rotación en y
-- attribute loc of rot_z_on: signal is "H18"; -- Rotación en z
attribute loc of speed: signal is "R17 N17";
attribute loc of rot_switches_i: signal is "L13 L14 K17 K18 H18 G18";
---attribute loc of rot_x_ng: signal is "L14"; -- Rotación negativa en x
---attribute loc of rot_y_ng: signal is "K18"; -- Rotación negativa en y
---attribute loc of rot_z_ng: signal is "G18"; -- Rotación negativa en z
-- Botones
--attribute loc of rst_i: signal is "B18"; -- Botón para resetear todo
attribute loc of write_rst_i: signal is "H13";
attribute loc of read_rst_i: signal is "E18";
--attribute loc of inc_alfa: signal is "H13";
--attribute loc of inc_beta: signal is "E18";
--attribute loc of inc_gama: signal is "D18";
-- attribute loc of rst_angs_i: signal is "B18"; -- Reseteo a posición inicial
-- Segmentos del display (por ahora simplemente se apagan)
attribute loc of a: signal is "L18";
attribute loc of b: signal is "F18";
attribute loc of c: signal is "D17";
attribute loc of d: signal is "D16";
attribute loc of e: signal is "G14";
attribute loc of f: signal is "J17";
attribute loc of g: signal is "H14";
attribute loc of dp: signal is "C17";
-- External RAM
attribute loc of clock_out : signal is "H5";
attribute loc of ADDRESS : signal is "K6 D1 K3 D2 C1 C2 E2 M5 E1 F2 G4 G5 G6 G3 F1 H6 H3 J5 H2 H1 H4 J2 J1";
attribute loc of ADV : signal is "J4";
attribute loc of CRE : signal is "P7";
attribute loc of CE : signal is "R6";
attribute loc of OE : signal is "T2";
attribute loc of WE : signal is "N7";
attribute loc of LB : signal is "K5";
attribute loc of UB : signal is "K4";
attribute loc of DATA : signal is "T1 R3 N4 L2 M6 M3 L5 L3 R2 P2 P1 N5 M4 L6 L4 L1";
end;
architecture tp4_arq of tp4 is
constant Nangle : natural := 16;
constant Nxy : natural := 16;
constant Nits : natural := Nxy-2;
constant N_bits_row : natural := 6;
constant N_bits_col : natural := N_bits_row;
constant N_ROWS : natural := 2**N_bits_row;
constant N_COLS : natural := 2**N_bits_col;
constant CENTER_ROW : natural := N_ROWS/2;
constant CENTER_COL : natural := N_COLS/2;
constant TOP_MARGIN : natural := 200;
constant LEFT_MARGIN : natural := 300;
constant memo_size : integer := N_rows * N_cols;
constant N_ROWS_VEC : std_logic_vector(N_bits_row-1 downto 0) := std_logic_vector(to_unsigned(N_ROWS, N_bits_row));
constant N_COLS_VEC : std_logic_vector(N_bits_col-1 downto 0) := std_logic_vector(to_unsigned(N_COLS, N_bits_col));
-- Video RAM
signal A_row : std_logic_vector(N_bits_row-1 downto 0) := (others => '0');
signal B_row : std_logic_vector(N_bits_row-1 downto 0) := (others => '0');
signal A_col : std_logic_vector(N_bits_col-1 downto 0) := (others => '0');
signal B_col : std_logic_vector(N_bits_col-1 downto 0) := (others => '0');
signal A_row_aux : std_logic_vector(N_bits_row-1 downto 0) := (others => '0');
signal A_col_aux : std_logic_vector(N_bits_col-1 downto 0) := (others => '0');
signal data_A : std_logic := '0';
signal data_B : std_logic := '0';
signal video_write_enable : std_logic := '0';
-- Limpieza de video RAM
signal row_counter : std_logic_vector(N_bits_row-1 downto 0) := (others => '0');
signal col_counter : std_logic_vector(N_bits_col-1 downto 0) := (others => '0');
-- VGA
signal pixel_row : std_logic_vector(10-1 downto 0) := (others => '0');
signal pixel_col : std_logic_vector(10-1 downto 0) := (others => '0');
signal enable_vga : std_logic := '0';
signal enable_vga_delay : std_logic := '0';
signal vga_pixel_in : std_logic := '0';
signal vga_start : std_logic := '0';
signal vga_stop : std_logic := '0';
-- RAM externa
signal data_out_ram : std_logic_vector(15 downto 0) := (others => '0');
signal data_in_ram : std_logic_vector(15 downto 0) := (others => '0');
signal address_in_ram : std_logic_vector(22 downto 0) := (others => '0');
signal go_in_ram : std_logic := '0';
signal write_in_ram : std_logic := '0';
signal busy_ram : std_logic := '0';
signal RxRdy_ram : std_logic := '0';
signal extRam_reset : std_logic := '0';
-- global control
signal delta_angle: std_logic_vector(Nangle-1 downto 0) := (others => '0');
signal alfa: std_logic_vector(Nangle-1 downto 0) := (others => '0');
signal beta: std_logic_vector(Nangle-1 downto 0) := (others => '0');
signal gama: std_logic_vector(Nangle-1 downto 0) := (others => '0');
signal clear_enable: std_logic := '0';
signal clear_stop: std_logic := '0';
signal clear_reset: std_logic := '0';
signal read_start: std_logic := '0';
signal read_stop: std_logic := '0';
signal read_stop_delay: std_logic := '0';
signal read_reset_out: std_logic := '0';
signal write_reset_out: std_logic := '0';
-- UART
constant Divisor : std_logic_vector := "000000011011"; -- Para 115200 baudios divido por 27
signal sig_Din : std_logic_vector(7 downto 0) := (others => '0');
signal uart_Dout : std_logic_vector(7 downto 0) := (others => '0');
signal sig_RxErr : std_logic := '0';
signal uart_RxRdy : std_logic := '0';
signal sig_TxBusy : std_logic := '0';
signal sig_StartTx : std_logic := '0';
signal rx, tx : std_logic := '0';
-- ExtRam Loader
signal loader_RxRdy : std_logic := '0';
signal loader_RxRdy_delay : std_logic := '0';
-- pos loader
signal reset_xyz : std_logic := '0';
signal enable_xyz : std_logic := '0';
signal RxRdy_xyz : std_logic := '0';
signal x0 : std_logic_vector(Nxy-1 downto 0) := (others => '0');
signal y0 : std_logic_vector(Nxy-1 downto 0) := (others => '0');
signal z0 : std_logic_vector(Nxy-1 downto 0) := (others => '0');
-- Rotador de posiciones
signal x : std_logic_vector(Nxy-1 downto 0) := (others => '0');
signal y : std_logic_vector(Nxy-1 downto 0) := (others => '0');
signal z : std_logic_vector(Nxy-1 downto 0) := (others => '0');
signal rotator_RxRdy : std_logic := '0';
signal x_screen : std_logic_vector((Nxy+N_bits_col)-1 downto 0) := (others => '0');
signal y_screen : std_logic_vector((Nxy+N_bits_row)-1 downto 0) := (others => '0');
signal x_screen_aux : std_logic_vector((Nxy+N_bits_col)-1 downto 0) := (others => '0');
signal y_screen_aux : std_logic_vector((Nxy+N_bits_row)-1 downto 0) := (others => '0');
-- Interconexiones
signal reset_read_extram_counter : std_logic := '0';
signal write_address_ram_counter : std_logic_vector(22 downto 0) := (others => '0');
signal read_address_ram_counter : std_logic_vector(22 downto 0) := (others => '0');
signal read_ram_ctrl : std_logic := '0';
signal pixel_row_aux : std_logic_vector(N_bits_row-1 downto 0) := (others => '0');
signal pixel_col_aux : std_logic_vector(N_bits_col-1 downto 0) := (others => '0');
signal button_down : std_logic := '0';
begin
---button_down <= ( (rot_switches_i(5) XOR rot_switches_i(4)) OR
--- (rot_switches_i(3) XOR rot_switches_i(2)) OR
--- (rot_switches_i(1) XOR rot_switches_i(0)) OR
--- write_rst_i OR
--- read_rst_i );
--button_down <= ( (not (rot_switches_i = (rot_switches_i'range => '0')))
-- write_rst_i OR
-- read_rst_i );
-- Si estoy apretando algún botón o algún switch está prendido
button_down <= (rot_switches_i(5) or rot_switches_i(4) or rot_switches_i(3) or
rot_switches_i(2) or rot_switches_i(1) or rot_switches_i(0) or
write_rst_i or read_rst_i);
control_global: entity work.global_ctrl
generic map(Nangle)
port map(
clock => clk_i,
write_rst_i => write_rst_i,
read_rst_i => read_rst_i,
sw_x_pos => rot_switches_i(0),
sw_x_neg => rot_switches_i(1),
sw_y_pos => rot_switches_i(2),
sw_y_neg => rot_switches_i(3),
sw_z_pos => rot_switches_i(4),
sw_z_neg => rot_switches_i(5),
delta_angle => delta_angle,
alfa => alfa,
beta => beta,
gama => gama,
clear_reset => clear_reset,
clear_enable => clear_enable,
clear_stop => clear_stop,
read_start => read_start,
read_stop => read_stop,
read_reset_out => read_reset_out,
write_reset_out => write_reset_out,
vga_start => vga_start,
vga_stop => vga_stop
);
-- Decido la velocidad de giro en base a los selectores de velocidad
delta_angle <= std_logic_vector(to_unsigned( 4, Nangle)) when speed = "00" else
std_logic_vector(to_unsigned( 18, Nangle)) when speed = "01" else
std_logic_vector(to_unsigned( 55, Nangle)) when speed = "10" else
std_logic_vector(to_unsigned(128, Nangle)) when speed = "11";
read_stop <= '1' when (unsigned(read_address_ram_counter) = unsigned(write_address_ram_counter))
else '0';
-------------------------------------------------------------------
-- CLEAR VIDEO RAM
-------------------------------------------------------------------
clear_inst: entity work.clear_video_ram
generic map(
N_bits_row => N_bits_row,
N_bits_col => N_bits_col,
N_ROWS => N_ROWS,
N_COLS => N_COLS
) port map(
clock => clk_i,
reset => clear_reset,
enable => clear_enable,
row_counter => row_counter,
col_counter => col_counter,
carry_out => clear_stop
);
-------------------------------------------------------------------
-------------------------------------------------------------------
-- UART 8bits --> 16bits
-------------------------------------------------------------------
data_loader: entity work.extRam_loader
port map(
clock => clk_i,
reset => write_reset_out,
data_in => uart_Dout,
RxRdy_in => uart_RxRdy,
data_out => data_in_ram,
RxRdy_out => loader_RxRdy
);
-- Lo recibido por la UART se almacena en la RAM externa
go_in_ram <= loader_RxRdy OR (read_ram_ctrl and (not read_stop));
write_in_ram <= loader_RxRdy;
address_in_ram <= write_address_ram_counter when loader_RxRdy = '1' else
read_address_ram_counter;
------------------------------------
-- Retardo para RxRdy
------------------------------------
RdRdy_delay: entity work.ffd_serie
generic map(N => 5)
port map(
clock => clk_i,
reset => write_reset_out,
enable => '1',
D => loader_RxRdy,
Q => loader_RxRdy_delay
);
-------------------------------------------------------------------
-- Contador de escritura de la RAM Externa
-------------------------------------------------------------------
write_extram_counter: entity work.counter
generic map(
N_bits => 23,
MAX_COUNT => 2**23-1
)
port map(
clock => clk_i,
reset => write_reset_out,
enable => loader_RxRdy_delay,
counter_output => write_address_ram_counter,
carry_out => open
);
-------------------------------------------------------------------
-- Contador de lectura de la RAM Externa
-------------------------------------------------------------------
reset_read_extram_counter <= loader_RxRdy_delay OR read_reset_out;
read_extram_counter: entity work.counter
generic map(
N_bits => 23,
MAX_COUNT => 2**23
) port map(
clock => clk_i,
reset => reset_read_extram_counter,
-- enable => read_ram_ctrl_delay,
enable => RxRdy_ram,
counter_output => read_address_ram_counter,
carry_out => open
);
-------------------------------------------------------------------
-- Lectura de la RAM externa
-------------------------------------------------------------------
pos_loader_inst: entity work.pos_loader
port map(
clock => clk_i,
reset => read_stop_delay,
enable => enable_xyz,
start => read_start,
data_in => data_out_ram,
go_ram => read_ram_ctrl,
RxRdy_ram => RxRdy_ram,
busy_ram => busy_ram,
RxRdy_out => RxRdy_xyz,
x => x0,
y => y0,
z => z0
);
enable_xyz <= '1';
read_stop_ffd: entity work.ffd
port map(
clk => clk_i,
rst => '0',
ena => '1',
d => read_stop,
q => read_stop_delay
);
-------------------------------------------------------------------
-- Rotador de posiciones
-------------------------------------------------------------------
rotator: entity work.pos_rotator
generic map(
Nxy => Nxy,
Nangle => Nangle,
Nits => Nits
) port map(
clock => clk_i,
reset => read_reset_out,
load => RxRdy_xyz,
RxRdy => rotator_RxRdy,
alfa => alfa,
beta => beta,
gama => gama,
x0 => x0,
y0 => y0,
z0 => z0,
x1 => x,
y1 => y,
z1 => z
);
-------------------------------------------------------------------
-- Escalado de la salida del rotador
-------------------------------------------------------------------
-- Version para N_ROWS = 2**N_bits_row
-- Multiplico por 2**N_bits_row
x_screen_aux <= x & (N_bits_col-1 downto 0 => '0');-- when bypass_cordic = '0' else
--x0 & (N_bits_col-1 downto 0 => '0') ;
y_screen_aux <= y & (N_bits_row-1 downto 0 => '0');-- when bypass_cordic = '0' else
--y0 & (N_bits_col-1 downto 0 => '0') ;
---- test martín
-- Dividir por 2**(Nxy-1) es equivalente a desplazar a derecha en Nxy-1, que equivale a tomar los segundos Nxy-1 bits
-- x_screen <= (Nxy-3 downto 0 => '0') & x_screen_aux((Nxy+N_bits_col)-1 downto Nxy) when bypass_scale = '0' else
-- (N_bits_col-1 downto 0 => '0') & x when bypass_cordic = '0' else
-- (N_bits_col-1 downto 0 => '0') & x0;
-- y_screen <= (Nxy-3 downto 0 => '0') & y_screen_aux((Nxy+N_bits_row)-1 downto Nxy) when bypass_scale = '0' else
-- (N_bits_row-1 downto 0 => '0') & y when bypass_cordic = '0' else
-- (N_bits_row-1 downto 0 => '0') & y0;
-- Dividir por 2**(Nxy-1) es equivalente a desplazar a derecha en Nxy-1, que equivale a tomar los segundos Nxy-1 bits
x_screen <= (Nxy-2 downto 0 => '0') & x_screen_aux((Nxy+N_bits_col)-1 downto Nxy-1); --when bypass_scale = '0' else
--(N_bits_col-1 downto 0 => '0') & x when bypass_cordic = '0' else
--(N_bits_col-1 downto 0 => '0') & x0;
y_screen <= (Nxy-2 downto 0 => '0') & y_screen_aux((Nxy+N_bits_row)-1 downto Nxy-1); --when bypass_scale = '0' else
--(N_bits_row-1 downto 0 => '0') & y when bypass_cordic = '0' else
--(N_bits_row-1 downto 0 => '0') & y0;
-- v que shiftea antes y solo se queda con los N_bits_row
A_row_aux <= std_logic_vector(CENTER_ROW - signed(y_screen((N_bits_row)-1 downto 0)));
A_col_aux <= std_logic_vector(CENTER_COL + signed(x_screen((N_bits_col)-1 downto 0)));
-------------------------------------------------------------------
-- Video RAM
-------------------------------------------------------------------
video_RAM_inst : entity work.video_ram
generic map (
N_bits_row => N_bits_row,
N_bits_col => N_bits_col,
N_rows => N_rows,
N_cols => N_cols
) port map(
clock => clk_i,
write_enable => video_write_enable,
A_row => A_row,
B_row => B_row,
A_col => A_col,
B_col => B_col,
data_A => data_A,
data_B => data_B
);
-- Escritura
-- row/col_counter: del CLEAR
-- A_row/col_aux: de x,y,z, luego de transformarlos y escalarlos
A_row <= row_counter when clear_enable = '1' else A_row_aux;
A_col <= col_counter when clear_enable = '1' else A_col_aux;
data_A <= '0' when clear_enable = '1' else '1';
video_write_enable <= rotator_RxRdy OR clear_enable;-- when bypass_cordic = '0' else
--RxRdy_xyz OR clear_enable;
-- Lectura: con el contador de salida de la VGA, leo la video ram,
-- solo cuando está habilitada la escritura.
B_row <= pixel_row_aux when enable_vga = '1' else (others => '0');
B_col <= pixel_col_aux when enable_vga = '1' else (others => '0');
-------------------------------------------------------------------
-- VGA
-------------------------------------------------------------------
-- Señales para avisar cuando empieza a barrer la pantalla
vga_start<= '1' when (unsigned(B_row) = 0) and (unsigned(B_col) = 0) and (enable_vga = '1')
else '0';
-- Avisa cuando se terminó una barrida completa de la pantalla.
vga_stop <= '1' when (unsigned(B_row) = N_ROWS-1) and (unsigned(B_col) = N_COLS-1)
else '0';
-- Entrada de color de la VGA.
vga_pixel_in <= not (data_B and enable_vga_delay); ---cambio color mnm
-- Retraso enable_vga en 1 ciclo de clock
delay_vga: entity work.ffd
port map(
clk => clk_i,
rst => '0',
ena => '1',
d => enable_vga,
q => enable_vga_delay
);
-- Resto el offset de los contadores de filas y columnas de VGA
pixel_row_aux <= std_logic_vector(unsigned(pixel_row(N_bits_row-1 downto 0)) - TOP_MARGIN);
pixel_col_aux <= std_logic_vector(unsigned(pixel_col(N_bits_col-1 downto 0)) - LEFT_MARGIN);
-- Habilito la escritura en la VGA solo cuando me encuentro
-- entre los márgenes permitidos para imprimir en pantalla.
process(pixel_row, pixel_col)
begin
if (TOP_MARGIN - 1 < unsigned(pixel_row) and -- Superior
unsigned(pixel_row) < TOP_MARGIN + N_rows and -- Inferior
LEFT_MARGIN - 1 < unsigned(pixel_col) and -- Izquierdo
unsigned(pixel_col) < LEFT_MARGIN + N_cols) then -- Derecho
enable_vga <= '1';
else
enable_vga <= '0';
end if;
end process;
-- Control de VGA
vga: entity work.vga_ctrl
port map(
mclk => clk_i,
red_i => vga_pixel_in,
grn_i => vga_pixel_in, ---Testear colores
blu_i => vga_pixel_in,
hs => hs,
vs => vs,
red_o => red_o,
grn_o => grn_o,
blu_o => blu_o,
pixel_row => pixel_row,
pixel_col => pixel_col
);
-------------------------------------------------------------------
-- UART
-------------------------------------------------------------------
rx <= data_i;
UART_receiver : entity work.uart
generic map (
F => 50000,
min_baud => 1200,
num_data_bits => 8
) port map (
clk => clk_i,
Rx => rx,
Tx => tx,
Din => sig_Din,
StartTx => sig_StartTx,
TxBusy => sig_TxBusy,
Dout => uart_Dout,
RxRdy => uart_RxRdy,
RxErr => sig_RxErr,
Divisor => Divisor,
rst => write_reset_out
);
-------------------------------------------------------------------
-- Controlador de la RAM Externa
-------------------------------------------------------------------
ext_RAM: entity work.MemoryController
generic map (
clock_frec => 50
) port map(
clock => clk_i,
reset => '0',
address_in => address_in_ram,
go_in => go_in_ram,
write_in => write_in_ram,
data_in => data_in_ram,
data_out => data_out_ram,
read_ready_out => RxRdy_ram,
busy => busy_ram,
---- Conexiones con la ram externa de la placa:
clock_out => clock_out,
ADDRESS => ADDRESS,
ADV => ADV,
CRE => CRE,
CE => CE,
OE => OE,
WE => WE,
LB => LB,
UB => UB,
DATA => DATA
);
-- Apago todos los segmentos del display de 7 segmentos
a <= '1';
b <= '1';
c <= '1';
d <= '1';
e <= '1';
f <= '1';
g <= '1';
dp <= '1';
end;
|
-------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User interface is 16 bit (burst of 4), externally 8x 8 bit.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity fpga_mem_test_v7 is
port (
CLOCK_50 : in std_logic;
SDRAM_CLK : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CSn : out std_logic := '1';
SDRAM_RASn : out std_logic := '1';
SDRAM_CASn : out std_logic := '1';
SDRAM_WEn : out std_logic := '1';
SDRAM_DQM : out std_logic := '0';
SDRAM_A : out std_logic_vector(14 downto 0);
SDRAM_DQ : inout std_logic_vector(7 downto 0) := (others => 'Z');
MOTOR_LEDn : out std_logic;
ACT_LEDn : out std_logic );
end fpga_mem_test_v7;
architecture tb of fpga_mem_test_v7 is
signal clock : std_logic := '1';
signal clk_2x : std_logic := '1';
signal reset : std_logic := '0';
signal inhibit : std_logic := '0';
signal is_idle : std_logic := '0';
signal req : t_mem_burst_32_req := c_mem_burst_32_req_init;
signal resp : t_mem_burst_32_resp;
signal okay : std_logic;
begin
i_clk: entity work.s3a_clockgen
port map (
clk_50 => CLOCK_50,
reset_in => '0',
dcm_lock => open,
sys_clock => clock, -- 50 MHz
sys_reset => reset,
sys_clock_2x => clk_2x );
i_checker: entity work.ext_mem_test_32
port map (
clock => clock,
reset => reset,
req => req,
resp => resp,
okay => ACT_LEDn );
i_mem_ctrl: entity work.ext_mem_ctrl_v7
generic map (
q_tcko_data => 5 ns,
g_simulation => false )
port map (
clock => clock,
clk_2x => clk_2x,
reset => reset,
inhibit => inhibit,
is_idle => is_idle,
req => req,
resp => resp,
SDRAM_CLK => SDRAM_CLK,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_DQM => SDRAM_DQM,
SDRAM_BA => SDRAM_A(14 downto 13),
SDRAM_A => SDRAM_A(12 downto 0),
SDRAM_DQ => SDRAM_DQ );
MOTOR_LEDn <= 'Z';
end;
|
-------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User interface is 16 bit (burst of 4), externally 8x 8 bit.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity fpga_mem_test_v7 is
port (
CLOCK_50 : in std_logic;
SDRAM_CLK : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CSn : out std_logic := '1';
SDRAM_RASn : out std_logic := '1';
SDRAM_CASn : out std_logic := '1';
SDRAM_WEn : out std_logic := '1';
SDRAM_DQM : out std_logic := '0';
SDRAM_A : out std_logic_vector(14 downto 0);
SDRAM_DQ : inout std_logic_vector(7 downto 0) := (others => 'Z');
MOTOR_LEDn : out std_logic;
ACT_LEDn : out std_logic );
end fpga_mem_test_v7;
architecture tb of fpga_mem_test_v7 is
signal clock : std_logic := '1';
signal clk_2x : std_logic := '1';
signal reset : std_logic := '0';
signal inhibit : std_logic := '0';
signal is_idle : std_logic := '0';
signal req : t_mem_burst_32_req := c_mem_burst_32_req_init;
signal resp : t_mem_burst_32_resp;
signal okay : std_logic;
begin
i_clk: entity work.s3a_clockgen
port map (
clk_50 => CLOCK_50,
reset_in => '0',
dcm_lock => open,
sys_clock => clock, -- 50 MHz
sys_reset => reset,
sys_clock_2x => clk_2x );
i_checker: entity work.ext_mem_test_32
port map (
clock => clock,
reset => reset,
req => req,
resp => resp,
okay => ACT_LEDn );
i_mem_ctrl: entity work.ext_mem_ctrl_v7
generic map (
q_tcko_data => 5 ns,
g_simulation => false )
port map (
clock => clock,
clk_2x => clk_2x,
reset => reset,
inhibit => inhibit,
is_idle => is_idle,
req => req,
resp => resp,
SDRAM_CLK => SDRAM_CLK,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_DQM => SDRAM_DQM,
SDRAM_BA => SDRAM_A(14 downto 13),
SDRAM_A => SDRAM_A(12 downto 0),
SDRAM_DQ => SDRAM_DQ );
MOTOR_LEDn <= 'Z';
end;
|
-------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User interface is 16 bit (burst of 4), externally 8x 8 bit.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity fpga_mem_test_v7 is
port (
CLOCK_50 : in std_logic;
SDRAM_CLK : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CSn : out std_logic := '1';
SDRAM_RASn : out std_logic := '1';
SDRAM_CASn : out std_logic := '1';
SDRAM_WEn : out std_logic := '1';
SDRAM_DQM : out std_logic := '0';
SDRAM_A : out std_logic_vector(14 downto 0);
SDRAM_DQ : inout std_logic_vector(7 downto 0) := (others => 'Z');
MOTOR_LEDn : out std_logic;
ACT_LEDn : out std_logic );
end fpga_mem_test_v7;
architecture tb of fpga_mem_test_v7 is
signal clock : std_logic := '1';
signal clk_2x : std_logic := '1';
signal reset : std_logic := '0';
signal inhibit : std_logic := '0';
signal is_idle : std_logic := '0';
signal req : t_mem_burst_32_req := c_mem_burst_32_req_init;
signal resp : t_mem_burst_32_resp;
signal okay : std_logic;
begin
i_clk: entity work.s3a_clockgen
port map (
clk_50 => CLOCK_50,
reset_in => '0',
dcm_lock => open,
sys_clock => clock, -- 50 MHz
sys_reset => reset,
sys_clock_2x => clk_2x );
i_checker: entity work.ext_mem_test_32
port map (
clock => clock,
reset => reset,
req => req,
resp => resp,
okay => ACT_LEDn );
i_mem_ctrl: entity work.ext_mem_ctrl_v7
generic map (
q_tcko_data => 5 ns,
g_simulation => false )
port map (
clock => clock,
clk_2x => clk_2x,
reset => reset,
inhibit => inhibit,
is_idle => is_idle,
req => req,
resp => resp,
SDRAM_CLK => SDRAM_CLK,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_DQM => SDRAM_DQM,
SDRAM_BA => SDRAM_A(14 downto 13),
SDRAM_A => SDRAM_A(12 downto 0),
SDRAM_DQ => SDRAM_DQ );
MOTOR_LEDn <= 'Z';
end;
|
-------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User interface is 16 bit (burst of 4), externally 8x 8 bit.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity fpga_mem_test_v7 is
port (
CLOCK_50 : in std_logic;
SDRAM_CLK : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CSn : out std_logic := '1';
SDRAM_RASn : out std_logic := '1';
SDRAM_CASn : out std_logic := '1';
SDRAM_WEn : out std_logic := '1';
SDRAM_DQM : out std_logic := '0';
SDRAM_A : out std_logic_vector(14 downto 0);
SDRAM_DQ : inout std_logic_vector(7 downto 0) := (others => 'Z');
MOTOR_LEDn : out std_logic;
ACT_LEDn : out std_logic );
end fpga_mem_test_v7;
architecture tb of fpga_mem_test_v7 is
signal clock : std_logic := '1';
signal clk_2x : std_logic := '1';
signal reset : std_logic := '0';
signal inhibit : std_logic := '0';
signal is_idle : std_logic := '0';
signal req : t_mem_burst_32_req := c_mem_burst_32_req_init;
signal resp : t_mem_burst_32_resp;
signal okay : std_logic;
begin
i_clk: entity work.s3a_clockgen
port map (
clk_50 => CLOCK_50,
reset_in => '0',
dcm_lock => open,
sys_clock => clock, -- 50 MHz
sys_reset => reset,
sys_clock_2x => clk_2x );
i_checker: entity work.ext_mem_test_32
port map (
clock => clock,
reset => reset,
req => req,
resp => resp,
okay => ACT_LEDn );
i_mem_ctrl: entity work.ext_mem_ctrl_v7
generic map (
q_tcko_data => 5 ns,
g_simulation => false )
port map (
clock => clock,
clk_2x => clk_2x,
reset => reset,
inhibit => inhibit,
is_idle => is_idle,
req => req,
resp => resp,
SDRAM_CLK => SDRAM_CLK,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_DQM => SDRAM_DQM,
SDRAM_BA => SDRAM_A(14 downto 13),
SDRAM_A => SDRAM_A(12 downto 0),
SDRAM_DQ => SDRAM_DQ );
MOTOR_LEDn <= 'Z';
end;
|
-------------------------------------------------------------------------------
-- Title : External Memory controller for SDRAM
-------------------------------------------------------------------------------
-- Description: This module implements a simple, single burst memory controller.
-- User interface is 16 bit (burst of 4), externally 8x 8 bit.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.mem_bus_pkg.all;
entity fpga_mem_test_v7 is
port (
CLOCK_50 : in std_logic;
SDRAM_CLK : out std_logic;
SDRAM_CKE : out std_logic;
SDRAM_CSn : out std_logic := '1';
SDRAM_RASn : out std_logic := '1';
SDRAM_CASn : out std_logic := '1';
SDRAM_WEn : out std_logic := '1';
SDRAM_DQM : out std_logic := '0';
SDRAM_A : out std_logic_vector(14 downto 0);
SDRAM_DQ : inout std_logic_vector(7 downto 0) := (others => 'Z');
MOTOR_LEDn : out std_logic;
ACT_LEDn : out std_logic );
end fpga_mem_test_v7;
architecture tb of fpga_mem_test_v7 is
signal clock : std_logic := '1';
signal clk_2x : std_logic := '1';
signal reset : std_logic := '0';
signal inhibit : std_logic := '0';
signal is_idle : std_logic := '0';
signal req : t_mem_burst_32_req := c_mem_burst_32_req_init;
signal resp : t_mem_burst_32_resp;
signal okay : std_logic;
begin
i_clk: entity work.s3a_clockgen
port map (
clk_50 => CLOCK_50,
reset_in => '0',
dcm_lock => open,
sys_clock => clock, -- 50 MHz
sys_reset => reset,
sys_clock_2x => clk_2x );
i_checker: entity work.ext_mem_test_32
port map (
clock => clock,
reset => reset,
req => req,
resp => resp,
okay => ACT_LEDn );
i_mem_ctrl: entity work.ext_mem_ctrl_v7
generic map (
q_tcko_data => 5 ns,
g_simulation => false )
port map (
clock => clock,
clk_2x => clk_2x,
reset => reset,
inhibit => inhibit,
is_idle => is_idle,
req => req,
resp => resp,
SDRAM_CLK => SDRAM_CLK,
SDRAM_CKE => SDRAM_CKE,
SDRAM_CSn => SDRAM_CSn,
SDRAM_RASn => SDRAM_RASn,
SDRAM_CASn => SDRAM_CASn,
SDRAM_WEn => SDRAM_WEn,
SDRAM_DQM => SDRAM_DQM,
SDRAM_BA => SDRAM_A(14 downto 13),
SDRAM_A => SDRAM_A(12 downto 0),
SDRAM_DQ => SDRAM_DQ );
MOTOR_LEDn <= 'Z';
end;
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
architecture rtl of addsub is
begin
addsub : entity work.addsub_inferred(rtl)
generic map (
src_bits => src_bits
)
port map (
sub => sub,
carryin => carryin,
src1 => src1,
src2 => src2,
result => result,
carryout => carryout,
overflow => overflow
);
end;
|
--ENTITY_TAG
-------------------------------------------------------------------------------
-- $Id: direct_path_cntr.vhd,v 1.1.4.1 2010/09/14 22:35:46 dougt Exp $
-------------------------------------------------------------------------------
-- direct_path_cntr.vhd - entity/arch
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2003-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: direct_path_cntr.vhd
--
-- Description: This is an up counter with a combinatorial direct pass-
-- through mode. The passed-through value also serves as
-- the initial "loaded" value when the counter switches to
-- count mode. In pass-though mode, Dout <= Din.
--
-- The mode is controlled by two signals, Load_n and Cnt_en.
-- The counter is in direct pass-through mode any time Load_n
-- is true (low) and up to the first cycle where Cnt_en is
-- true after Load_n goes false. When Load_n is false,
-- Dout increments by one each time Cnt_en is true at
-- the positive edge of Clk.
--
-- The implementation has a one-LUT delay (via the XORCY)
-- in direct pass-through mode and the same delay plus
-- carry-chain propogation in count mode.
-------------------------------------------------------------------------------
-- Structure: direct_path_cntr.vhd
-------------------------------------------------------------------------------
-- Author: FLO
-- History:
-- FLO 05/30/2003 -- First version
--
-- <initials> <date>
-- ^^^^^^
-- Description of changes. If multiple lines are needed to fully describe
-- the changes made to the design, these lines should align with each other.
-- ~~~~~~
--
-- DET 1/17/2008 v3_00_a
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity direct_path_cntr is
generic (
C_WIDTH : natural := 8
);
port (
Clk : in std_logic;
Din : in std_logic_vector(0 to C_WIDTH-1);
Dout : out std_logic_vector(0 to C_WIDTH-1);
Load_n : in std_logic;
Cnt_en : in std_logic
);
end direct_path_cntr;
library unisim;
use unisim.all;
architecture imp of direct_path_cntr is
component MULT_AND
port(
LO : out std_ulogic;
I1 : in std_ulogic;
I0 : in std_ulogic);
end component;
component MUXCY is
port (
DI : in std_logic;
CI : in std_logic;
S : in std_logic;
O : out std_logic);
end component MUXCY;
component XORCY is
port (
LI : in std_logic;
CI : in std_logic;
O : out std_logic);
end component XORCY;
component FDRE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
R : in std_logic
);
end component FDRE;
component FDSE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic;
S : in std_logic
);
end component FDSE;
component FDE is
port (
Q : out std_logic;
C : in std_logic;
CE : in std_logic;
D : in std_logic
);
end component FDE;
signal q_i,
lut_out,
q_i_ns : std_logic_vector(0 to C_WIDTH-1);
signal cry : std_logic_vector(0 to C_WIDTH);
signal sel_cntr : std_logic;
begin
----------------------------------------------------------------------------
-- Load_n takes effect combinatorially, causing Dout to be directly driven
-- from Din when Load_n is asserted. When Load_n is not asserted, then the
-- first clocking of asserted Cnt_en switches modes so that Dout is driven
-- by the register value plus one. The value of Dout is clocked into the
-- register with each Cnt_en, thus realizing the counting behavior.
-- The combinatorial override of Load_n takes place in the LUT and covers
-- the cycle that it takes for the mode to recover (since the mode FF has a
-- synchronous reset). Use of an asynchronous reset is rejected as an
-- option to avoid the requirement that Load_n be generated glitch free.
----------------------------------------------------------------------------
I_MODE_SELECTION : process(Clk)
begin
if Clk'event and Clk='1' then
if Load_n = '0' then
sel_cntr <= '0';
elsif Cnt_en = '1' then
sel_cntr <= '1';
end if;
end if;
end process;
Dout <= q_i_ns;
cry(C_WIDTH) <= '0';
PERBIT_GEN: for j in C_WIDTH-1 downto 0 generate
signal gen_cry: std_logic;
begin
gen_cry <= '1' when j = C_WIDTH-1 else '0'; -- cntrl increments
-- at LSB
------------------------------------------------------------------------
-- LUT output generation.
------------------------------------------------------------------------
LSB_LUT_GEN: if j = C_WIDTH-1 generate
begin
lut_out(j) <= not q_i(j) when (sel_cntr and Load_n)='1' else Din(j);
end generate;
--
NON_LSB_LUT_GEN: if j /= C_WIDTH-1 generate
begin
lut_out(j) <= q_i(j) when (sel_cntr and Load_n)='1' else Din(j);
end generate;
------------------------------------------------------------------------
-- Propagate the carry out.
------------------------------------------------------------------------
LSB_MUXCY_GEN: if j = C_WIDTH-1 generate
signal sel_cntr_and_Load_n : std_logic;
begin
I_MULT_AND : MULT_AND
port map (
LO => sel_cntr_and_Load_n,
I1 => sel_cntr,
I0 => Load_n
);
MUXCY_i1: MUXCY
port map (
DI => sel_cntr_and_Load_n,
CI => cry(j+1),
S => lut_out(j),
O => cry(j)
);
end generate;
--
NON_LSB_MUXCY_GEN: if j /= C_WIDTH-1 generate
begin
MUXCY_i1: MUXCY
port map (
DI => '0',
CI => cry(j+1),
S => lut_out(j),
O => cry(j)
);
end generate;
------------------------------------------------------------------------
-- Apply the effect of carry in.
------------------------------------------------------------------------
XORCY_i1: XORCY
port map (
LI => lut_out(j),
CI => cry(j+1),
O => q_i_ns(j)
);
FDRE_i1: FDE
port map (
Q => q_i(j),
C => Clk,
CE => Cnt_en,
D => q_i_ns(j)
);
end generate;
end imp;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: grsysmon
-- File: grsysmon.vhd
-- Author: Jan Andersson - Gaisler Research AB
-- Description: Provides GRLIB AMBA AHB slave interface to Xilinx SYSMON
library ieee;
use ieee.std_logic_1164.all;
library grlib, gaisler;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
use gaisler.misc.all;
library techmap;
use techmap.gencomp.all;
entity grsysmon is
generic (
-- GRLIB generics
tech : integer := DEFFABTECH;
hindex : integer := 0; -- AHB slave index
hirq : integer := 0; -- Interrupt line
caddr : integer := 16#000#; -- Base address for configuration area
cmask : integer := 16#fff#; -- Area mask
saddr : integer := 16#001#; -- Base address for sysmon register area
smask : integer := 16#fff#; -- Area mask
split : integer := 0; -- Enable AMBA SPLIT support
extconvst : integer := 0; -- Use external CONVST signal
wrdalign : integer := 0; -- Word align System Monitor registers
-- Virtex 5 SYSMON generics
INIT_40 : bit_vector := X"0000";
INIT_41 : bit_vector := X"0000";
INIT_42 : bit_vector := X"0800";
INIT_43 : bit_vector := X"0000";
INIT_44 : bit_vector := X"0000";
INIT_45 : bit_vector := X"0000";
INIT_46 : bit_vector := X"0000";
INIT_47 : bit_vector := X"0000";
INIT_48 : bit_vector := X"0000";
INIT_49 : bit_vector := X"0000";
INIT_4A : bit_vector := X"0000";
INIT_4B : bit_vector := X"0000";
INIT_4C : bit_vector := X"0000";
INIT_4D : bit_vector := X"0000";
INIT_4E : bit_vector := X"0000";
INIT_4F : bit_vector := X"0000";
INIT_50 : bit_vector := X"0000";
INIT_51 : bit_vector := X"0000";
INIT_52 : bit_vector := X"0000";
INIT_53 : bit_vector := X"0000";
INIT_54 : bit_vector := X"0000";
INIT_55 : bit_vector := X"0000";
INIT_56 : bit_vector := X"0000";
INIT_57 : bit_vector := X"0000";
SIM_MONITOR_FILE : string := "sysmon.txt");
port (
rstn : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sysmoni : in grsysmon_in_type;
sysmono : out grsysmon_out_type
);
end grsysmon;
architecture rtl of grsysmon is
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
constant REVISION : amba_version_type := 0;
constant HCONFIG : ahb_config_type := (
0 => ahb_device_reg(VENDOR_GAISLER, GAISLER_GRSYSMON, 0, REVISION, hirq),
4 => ahb_iobar(caddr, cmask), 5 => ahb_iobar(saddr, smask),
others => zero32);
-- BANKs
constant CONF_BANK : integer := 0;
constant SYSMON_BANK : integer := 1;
-- Registers
constant CONF_REG_OFF : std_ulogic := '0';
constant STAT_REG_OFF : std_ulogic := '1';
-----------------------------------------------------------------------------
-- Types
-----------------------------------------------------------------------------
type sysmon_out_type is record
alm : std_logic_vector(2 downto 0);
busy : std_ulogic;
channel : std_logic_vector(4 downto 0);
do : std_logic_vector(15 downto 0);
drdy : std_ulogic;
eoc : std_ulogic;
eos : std_ulogic;
jtagbusy : std_ulogic;
jtaglocked : std_ulogic;
jtagmodified : std_ulogic;
ot : std_ulogic;
end record;
type sysmon_in_type is record
daddr : std_logic_vector(6 downto 0);
den : std_ulogic;
di : std_logic_vector(15 downto 0);
dwe : std_ulogic;
end record;
type grsysmon_conf_reg_type is record
ot_ien : std_ulogic;
alm_ien : std_logic_vector(2 downto 0);
convst : std_ulogic;
eos_ien : std_ulogic;
eoc_ien : std_ulogic;
busy_ien : std_ulogic;
jb_ien : std_ulogic;
jl_ien : std_ulogic;
jm_ien : std_ulogic;
end record;
type grsysmon_reg_type is record
cfgreg : grsysmon_conf_reg_type;
-- SYSMON
den : std_ulogic; -- System monitor data enable
sma : std_ulogic; -- System monitor access
smr : std_ulogic; -- System monitor access ready
-- AHB
insplit : std_ulogic; -- SPLIT response issued
unsplit : std_ulogic; -- SPLIT complete not issued
irq : std_ulogic; -- Interrupt request
hwrite : std_ulogic;
hsel : std_ulogic;
hmbsel : std_logic_vector(0 to 1);
haddr : std_logic_vector(6 downto 0);
hready : std_ulogic;
srdata : std_logic_vector(15 downto 0); -- SYSMON response data
rrdata : std_logic_vector(12 downto 0); -- Register response data
hresp : std_logic_vector(1 downto 0);
splmst : std_logic_vector(log2(NAHBMST)-1 downto 0); -- SPLIT:ed master
hsplit : std_logic_vector(NAHBMST-1 downto 0); -- Other SPLIT:ed masters
ahbcancel : std_ulogic; -- Locked access cancels ongoing SPLIT
-- response
end record;
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal r, rin : grsysmon_reg_type;
signal syso : sysmon_out_type;
signal sysi : sysmon_in_type;
signal sysmon_rst : std_ulogic;
signal lconvst : std_ulogic;
begin -- rtl
sysmon_rst <= not rstn;
convstint: if extconvst = 0 generate
lconvst <= r.cfgreg.convst;
end generate convstint;
convstext: if extconvst /= 0 generate
lconvst <= sysmoni.convst;
end generate convstext;
-----------------------------------------------------------------------------
-- System monitor
-----------------------------------------------------------------------------
macro0 : system_monitor
generic map (tech => tech,
INIT_40 => INIT_40, INIT_41 => INIT_41, INIT_42 => INIT_42,
INIT_43 => INIT_43, INIT_44 => INIT_44, INIT_45 => INIT_45,
INIT_46 => INIT_46, INIT_47 => INIT_47, INIT_48 => INIT_48,
INIT_49 => INIT_49, INIT_4A => INIT_4A, INIT_4B => INIT_4B,
INIT_4C => INIT_4C, INIT_4D => INIT_4D, INIT_4E => INIT_4E,
INIT_4F => INIT_4F, INIT_50 => INIT_50, INIT_51 => INIT_51,
INIT_52 => INIT_52, INIT_53 => INIT_53, INIT_54 => INIT_54,
INIT_55 => INIT_55, INIT_56 => INIT_56, INIT_57 => INIT_57,
SIM_MONITOR_FILE => SIM_MONITOR_FILE)
port map (alm => syso.alm, busy => syso.busy, channel => syso.channel,
do => syso.do, drdy => syso.drdy, eoc => syso.eoc,
eos => syso.eos, jtagbusy => syso.jtagbusy,
jtaglocked => syso.jtaglocked, jtagmodified => syso.jtagmodified,
ot => syso.ot, convst => lconvst, convstclk => sysmoni.convstclk,
daddr => sysi.daddr, dclk => clk, den => sysi.den,
di => sysi.di, dwe => sysi.dwe, reset => sysmon_rst,
vauxn => sysmoni.vauxn, vauxp => sysmoni.vauxp,
vn => sysmoni.vn, vp => sysmoni.vp);
-----------------------------------------------------------------------------
-- AMBA and control i/f
-----------------------------------------------------------------------------
comb: process (r, rstn, ahbsi, syso)
variable v : grsysmon_reg_type;
variable irq : std_logic_vector((NAHBIRQ-1) downto 0);
variable addr : std_logic_vector(7 downto 0);
variable hsplit : std_logic_vector(NAHBMST-1 downto 0);
variable regaddr : std_ulogic;
variable hrdata : std_logic_vector(31 downto 0);
variable hwdata : std_logic_vector(31 downto 0);
begin -- process comb
v := r; v.irq := '0'; irq := (others => '0'); irq(hirq) := r.irq;
v.hresp := HRESP_OKAY; v.hready := '1'; v.den := '0';
regaddr := r.haddr(1-wrdalign); hsplit := (others => '0');
v.cfgreg.convst := '0';
hwdata := ahbreadword(ahbsi.hwdata, r.haddr(4 downto 2));
-- AHB communication
if ahbsi.hready = '1' then
if (ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '1' then
v.hmbsel := ahbsi.hmbsel(r.hmbsel'range);
if split = 0 or (not r.sma or ahbsi.hmbsel(CONF_BANK) or
ahbsi.hmastlock) = '1' then
v.hready := ahbsi.hmbsel(CONF_BANK) and ahbsi.hwrite;
v.hwrite := ahbsi.hwrite;
v.haddr := ahbsi.haddr((7+wrdalign) downto (1+wrdalign));
v.hsel := '1';
if ahbsi.hmbsel(SYSMON_BANK) = '1' then
v.den := not r.insplit; v.sma := '1';
if split /= 0 then
if ahbsi.hmastlock = '0' then
v.hresp := HRESP_SPLIT;
v.splmst := ahbsi.hmaster;
v.unsplit := '1';
else
v.ahbcancel := r.insplit;
end if;
v.insplit := not ahbsi.hmastlock;
end if;
end if;
else
-- Core is busy, transfer is not locked and access was to sysmon
-- registers. Respond with SPLIT or insert wait states
v.hready := '0';
if split /= 0 then
v.hresp := HRESP_SPLIT;
v.hsplit(conv_integer(ahbsi.hmaster)) := '1';
end if;
end if;
else
v.hsel := '0';
end if;
end if;
if (r.hready = '0') then
if (r.hresp = HRESP_OKAY) then v.hready := '0';
else v.hresp := r.hresp; end if;
end if;
-- Read access to conf registers
if (r.hsel and r.hmbsel(CONF_BANK)) = '1' then
v.rrdata := (others => '0');
if r.hwrite = '0' then
v.hready := '1';
v.hsel := '0';
end if;
case regaddr is
when CONF_REG_OFF =>
v.rrdata(12) := r.cfgreg.ot_ien;
v.rrdata(11 downto 9) := r.cfgreg.alm_ien;
if extconvst = 0 then
v.rrdata(6) := r.cfgreg.convst;
end if;
v.rrdata(5) := r.cfgreg.eos_ien;
v.rrdata(4) := r.cfgreg.eoc_ien;
v.rrdata(3) := r.cfgreg.busy_ien;
v.rrdata(2) := r.cfgreg.jb_ien;
v.rrdata(1) := r.cfgreg.jl_ien;
v.rrdata(0) := r.cfgreg.jm_ien;
if r.hwrite = '1' then
v.cfgreg.ot_ien := hwdata(12);
v.cfgreg.alm_ien := hwdata(11 downto 9);
if extconvst = 0 then
v.cfgreg.convst := hwdata(6);
end if;
v.cfgreg.eos_ien := hwdata(5);
v.cfgreg.eoc_ien := hwdata(4);
v.cfgreg.busy_ien := hwdata(3);
v.cfgreg.jb_ien := hwdata(2);
v.cfgreg.jl_ien := hwdata(1);
v.cfgreg.jm_ien := hwdata(0);
end if;
when STAT_REG_OFF =>
v.rrdata(12) := syso.ot;
v.rrdata(11 downto 9) := syso.alm;
v.rrdata(8 downto 4) := syso.channel;
v.rrdata(3) := syso.busy;
v.rrdata(2) := syso.jtagbusy;
v.rrdata(1) := syso.jtaglocked;
v.rrdata(0) := syso.jtagmodified;
when others => null;
end case;
end if;
-- SYSMON access finished
if syso.drdy = '1' then
v.srdata := syso.do;
v.smr := '1';
end if;
if (syso.drdy or r.smr) = '1' then
if split /= 0 and r.unsplit = '1' then
hsplit(conv_integer(r.splmst)) := '1';
v.unsplit := '0';
end if;
if ((split = 0 or v.ahbcancel = '0') and
(split = 0 or ahbsi.hmaster = r.splmst or r.insplit = '0') and
-- (((split = 0 or r.insplit = '0') and r.hmbsel(SYSMON_BANK) = '1') or
-- (split = 1 and ahbsi.hmbsel(SYSMON_BANK) = '1')) and
(((ahbsi.hsel(hindex) and ahbsi.hready and ahbsi.htrans(1)) = '1') or
((split = 0 or r.insplit = '0') and r.hready = '0' and r.hresp = HRESP_OKAY))) then
v.hresp := HRESP_OKAY;
if split /= 0 then
v.insplit := '0';
v.hsplit := r.hsplit;
end if;
v.hready := '1';
v.hsel := '0';
v.smr := '0';
v.sma := '0';
elsif split /= 0 and v.ahbcancel = '1' then
v.den := '1'; v.smr := '0';
v.ahbcancel := '0';
end if;
end if;
-- Interrupts
if (syso.ot and v.cfgreg.ot_ien) = '1' then
v.irq := '1';
v.cfgreg.ot_ien := '0';
end if;
for i in r.cfgreg.alm_ien'range loop
if (syso.alm(i) and r.cfgreg.alm_ien(i)) = '1' then
v.irq := '1';
v.cfgreg.alm_ien(i) := '0';
end if;
end loop; -- i
if (syso.eos and v.cfgreg.eos_ien) = '1' then
v.irq := '1';
v.cfgreg.eos_ien := '0';
end if;
if (syso.eoc and v.cfgreg.eoc_ien) = '1' then
v.irq := '1';
v.cfgreg.eoc_ien := '0';
end if;
if (syso.busy and v.cfgreg.busy_ien) = '1' then
v.irq := '1';
v.cfgreg.busy_ien := '0';
end if;
if (syso.jtagbusy and v.cfgreg.jb_ien) = '1' then
v.irq := '1';
v.cfgreg.jb_ien := '0';
end if;
if (syso.jtaglocked and v.cfgreg.jl_ien) = '1' then
v.irq := '1';
v.cfgreg.jl_ien := '0';
end if;
if (syso.jtagmodified and v.cfgreg.jm_ien) = '1' then
v.irq := '1';
v.cfgreg.jm_ien := '0';
end if;
-- Reset
if rstn = '0' then
v.cfgreg.ot_ien := '0';
v.cfgreg.alm_ien := (others => '0');
v.cfgreg.eos_ien := '0';
v.cfgreg.eoc_ien := '0';
v.cfgreg.busy_ien := '0';
v.cfgreg.jb_ien := '0';
v.cfgreg.jl_ien := '0';
v.cfgreg.jm_ien := '0';
v.sma := '0';
v.smr := '0';
v.insplit := '0';
v.unsplit := '0';
v.hready := '1';
v.hwrite := '0';
v.hsel := '0';
v.hmbsel := (others => '0');
v.ahbcancel := '0';
end if;
if split = 0 then
v.insplit := '0';
v.unsplit := '0';
v.splmst := (others => '0');
v.hsplit := (others => '0');
v.ahbcancel := '0';
end if;
-- Update registers
rin <= v;
-- AHB slave output
ahbso.hready <= r.hready;
ahbso.hresp <= r.hresp;
if r.hmbsel(CONF_BANK) = '1' then
if wrdalign = 0 then hrdata := zero32(31 downto 13) & r.rrdata;
else hrdata := '1' & zero32(30 downto 13) & r.rrdata; end if;
else
if wrdalign = 0 then hrdata := r.srdata & r.srdata;
else hrdata := zero32(31 downto 16) & r.srdata;
end if;
end if;
ahbso.hrdata <= ahbdrivedata(hrdata);
ahbso.hconfig <= HCONFIG;
ahbso.hirq <= irq;
ahbso.hindex <= hindex;
ahbso.hsplit <= hsplit;
-- Signals to system monitor
sysi.daddr <= r.haddr;
sysi.den <= r.den;
sysi.dwe <= r.hwrite;
if wrdalign = 0 then
if r.haddr(0) = '0' then sysi.di <= hwdata(31 downto 16);
else sysi.di <= hwdata(15 downto 0); end if;
else
sysi.di <= hwdata(15 downto 0);
end if;
-- Signals from system monitor to core outputs
sysmono.alm <= syso.alm;
sysmono.ot <= syso.ot;
sysmono.eoc <= syso.eoc;
sysmono.eos <= syso.eos;
sysmono.channel <= syso.channel;
end process comb;
reg: process (clk)
begin -- process reg
if rising_edge(clk) then
r <= rin;
end if;
end process reg;
-- Boot message
-- pragma translate_off
bootmsg : report_version
generic map (
"grsysmon" & tost(hindex) & ": AMBA wrapper for System Monitor, rev " &
tost(REVISION) & ", irq " & tost(hirq));
-- pragma translate_on
end rtl;
|
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: ROM_GAUSS_COE_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY ROM_GAUSS_COE_tb IS
END ENTITY;
ARCHITECTURE ROM_GAUSS_COE_tb_ARCH OF ROM_GAUSS_COE_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
ROM_GAUSS_COE_tb_synth_inst:ENTITY work.ROM_GAUSS_COE_tb_synth
GENERIC MAP (C_ROM_SYNTH => 0)
PORT MAP(
CLK_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: read_data_path.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This is top level of read path and also consist of comparison logic
-- for read data.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
entity read_data_path is
generic (
TCQ : time := 100 ps;
FAMILY : string := "VIRTEX6";
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : integer := 32;
CMP_DATA_PIPE_STAGES : integer := 3;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
DQ_ERROR_WIDTH : integer := 1;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
MEM_COL_WIDTH : integer := 10
);
port (
clk_i : in std_logic;
manual_clear_error : in std_logic;
rst_i : in std_logic_vector(9 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
cmd_sent : in std_logic_vector(2 downto 0);
bl_sent : in std_logic_vector(5 downto 0);
cmd_en_i : in std_logic;
-- m_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(31 downto 0);
bl_i : in std_logic_vector(5 downto 0);
-- input [5:0] port_data_counts_i,// connect to data port fifo counts
data_rdy_o : out std_logic;
data_valid_i : in std_logic;
data_i : in std_logic_vector(DWIDTH - 1 downto 0);
last_word_rd_o : out std_logic;
data_error_o : out std_logic;
cmp_data_o : out std_logic_vector(DWIDTH - 1 downto 0);
rd_mdata_o : out std_logic_vector(DWIDTH - 1 downto 0);
cmp_data_valid : out std_logic;
cmp_addr_o : out std_logic_vector(31 downto 0);
cmp_bl_o : out std_logic_vector(5 downto 0);
force_wrcmd_gen_o : out std_logic;
rd_buff_avail_o : out std_logic_vector(6 downto 0);
dq_error_bytelane_cmp : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
cumlative_dq_lane_error_r : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0)
);
end entity read_data_path;
architecture trans of read_data_path is
function REDUCTION_OR( A: in std_logic_vector) return std_logic is
variable tmp : std_logic := '0';
begin
for i in A'range loop
tmp := tmp or A(i);
end loop;
return tmp;
end function REDUCTION_OR;
COMPONENT read_posted_fifo IS
GENERIC (
TCQ : time := 100 ps;
MEM_BURST_LEN : integer := 4;
FAMILY : STRING := "SPARTAN6";
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
data_valid_i : IN STD_LOGIC;
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
user_bl_cnt_is_1 : IN STD_LOGIC;
cmd_sent : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
bl_sent : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
cmd_en_i : IN STD_LOGIC;
gen_rdy_i : IN STD_LOGIC;
gen_valid_o : OUT STD_LOGIC;
gen_addr_o : OUT STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
gen_bl_o : OUT STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
rd_buff_avail_o : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
rd_mdata_fifo_empty : IN STD_LOGIC;
rd_mdata_en : OUT STD_LOGIC
);
END COMPONENT;
component rd_data_gen is
generic (
FAMILY : string := "SPARTAN6";
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : integer := 32;
BL_WIDTH : integer := 6;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_PRBS";
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3;
COLUMN_WIDTH : integer := 10
);
port (
clk_i : in std_logic;
rst_i : in std_logic_vector(4 downto 0);
prbs_fseed_i : in std_logic_vector(31 downto 0);
rd_mdata_en : in std_logic;
data_mode_i : in std_logic_vector(3 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
last_word_o : out std_logic;
-- m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
bl_i : in std_logic_vector(BL_WIDTH - 1 downto 0);
user_bl_cnt_is_1_o : out std_logic;
data_rdy_i : in std_logic;
data_valid_o : out std_logic;
data_o : out std_logic_vector(DWIDTH - 1 downto 0)
);
end component;
component afifo IS
GENERIC (
DSIZE : INTEGER := 32;
FIFO_DEPTH : INTEGER := 16;
ASIZE : INTEGER := 5;
SYNC : INTEGER := 1
);
PORT (
wr_clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
wr_en : IN STD_LOGIC;
wr_data : IN STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
rd_en : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_data : OUT STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
almost_full : OUT STD_LOGIC;
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END component;
signal gen_rdy : std_logic;
signal gen_valid : std_logic;
signal gen_addr : std_logic_vector(31 downto 0);
signal gen_bl : std_logic_vector(5 downto 0);
signal cmp_rdy : std_logic;
signal cmp_valid : std_logic;
signal cmp_addr : std_logic_vector(31 downto 0);
signal cmp_bl : std_logic_vector(5 downto 0);
signal data_error : std_logic;
signal cmp_data : std_logic_vector(DWIDTH - 1 downto 0);
signal last_word_rd : std_logic;
signal bl_counter : std_logic_vector(5 downto 0);
signal cmd_rdy : std_logic;
signal user_bl_cnt_is_1 : std_logic;
signal data_rdy : std_logic;
signal delayed_data : std_logic_vector(DWIDTH downto 0);
-- signal cmp_data_piped : std_logic_vector(DWIDTH downto 0);
signal cmp_data_r : std_logic_vector(DWIDTH-1 downto 0);
signal rd_mdata_en : std_logic;
signal rd_data_r : std_logic_vector(DWIDTH - 1 downto 0);
signal force_wrcmd_gen : std_logic;
signal wait_bl_end : std_logic;
signal wait_bl_end_r1 : std_logic;
signal v6_data_cmp_valid : std_logic;
signal rd_v6_mdata : std_logic_vector(DWIDTH-1 downto 0);
signal cmpdata_r : std_logic_vector(DWIDTH-1 downto 0);
signal rd_mdata : std_logic_vector(DWIDTH-1 downto 0);
signal l_data_error : std_logic;
signal u_data_error : std_logic;
signal cmp_data_en : std_logic;
signal force_wrcmd_timeout_cnts : std_logic_vector(7 downto 0);
signal error_byte : std_logic_vector(NUM_DQ_PINS / 2 - 1 downto 0);
signal error_byte_r1 : std_logic_vector(NUM_DQ_PINS / 2 - 1 downto 0);
signal dq_lane_error : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal dq_lane_error_r1 : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal dq_lane_error_r2 : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cum_dq_lane_error_mask : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cumlative_dq_lane_error_reg : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cumlative_dq_lane_error_c : std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
signal rd_mdata_fifo_empty : std_logic;
signal data_valid_r : std_logic;
-- Declare intermediate signals for referenced outputs
-- SIGNAL xhdl2 : STD_LOGIC_VECTOR(DWIDTH DOWNTO 0);
-- SIGNAL tmp_sig : STD_LOGIC;
signal last_word_rd_o_xhdl0 : std_logic;
signal rd_buff_avail_o_xhdl1 : std_logic_vector(6 downto 0);
begin
-- Drive referenced outputs
last_word_rd_o <= last_word_rd_o_xhdl0;
rd_buff_avail_o <= rd_buff_avail_o_xhdl1;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
wait_bl_end_r1 <= wait_bl_end;
rd_data_r <= data_i;
end if;
end process;
force_wrcmd_gen_o <= force_wrcmd_gen;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
force_wrcmd_gen <= '0';
elsif ((wait_bl_end = '0' and wait_bl_end_r1 = '1') or force_wrcmd_timeout_cnts = "11111111") then
force_wrcmd_gen <= '0';
elsif ((cmd_valid_i = '1' and bl_i > "010000") or wait_bl_end = '1') then
force_wrcmd_gen <= '1';
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
force_wrcmd_timeout_cnts <= "00000000";
elsif (wait_bl_end = '0' and wait_bl_end_r1 = '1') then
force_wrcmd_timeout_cnts <= "00000000";
elsif (force_wrcmd_gen = '1') then
force_wrcmd_timeout_cnts <= force_wrcmd_timeout_cnts + "00000001";
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
wait_bl_end <= '0';
elsif (force_wrcmd_timeout_cnts = "11111111") then
wait_bl_end <= '0';
elsif ((gen_rdy and gen_valid) = '1' and gen_bl > "010000") then
wait_bl_end <= '1';
elsif ((wait_bl_end and user_bl_cnt_is_1) = '1') then
wait_bl_end <= '0';
end if;
end if;
end process;
cmd_rdy_o <= cmd_rdy;
read_postedfifo : read_posted_fifo
GENERIC MAP (
TCQ => TCQ,
FAMILY => FAMILY,
MEM_BURST_LEN => MEM_BURST_LEN,
ADDR_WIDTH => 32,
BL_WIDTH => 6
)
port map (
clk_i => clk_i,
rst_i => rst_i(0),
cmd_rdy_o => cmd_rdy,
cmd_valid_i => cmd_valid_i,
data_valid_i => data_rdy,
addr_i => addr_i,
bl_i => bl_i,
cmd_sent => cmd_sent,
bl_sent => bl_sent,
cmd_en_i => cmd_en_i,
user_bl_cnt_is_1 => user_bl_cnt_is_1,
gen_rdy_i => gen_rdy,
gen_valid_o => gen_valid,
gen_addr_o => gen_addr,
gen_bl_o => gen_bl,
rd_buff_avail_o => rd_buff_avail_o_xhdl1,
rd_mdata_fifo_empty => rd_mdata_fifo_empty,
rd_mdata_en => rd_mdata_en
);
rd_datagen : rd_data_gen
generic map (
FAMILY => FAMILY,
MEM_BURST_LEN => MEM_BURST_LEN,
NUM_DQ_PINS => NUM_DQ_PINS,
SEL_VICTIM_LINE => SEL_VICTIM_LINE,
DATA_PATTERN => DATA_PATTERN,
DWIDTH => DWIDTH,
COLUMN_WIDTH => MEM_COL_WIDTH
)
port map (
clk_i => clk_i,
rst_i => rst_i(4 downto 0),
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_rdy_o => gen_rdy,
cmd_valid_i => gen_valid,
last_word_o => last_word_rd_o_xhdl0,
-- m_addr_i => m_addr_i,
fixed_data_i => fixed_data_i,
addr_i => gen_addr,
bl_i => gen_bl,
user_bl_cnt_is_1_o => user_bl_cnt_is_1,
data_rdy_i => data_valid_i,
data_valid_o => cmp_valid,
data_o => cmp_data,
rd_mdata_en => rd_mdata_en
);
rd_mdata_fifo : afifo
GENERIC MAP (
DSIZE => DWIDTH,
FIFO_DEPTH => 32,
ASIZE => 5,
SYNC => 1
)
PORT MAP (
wr_clk => clk_i,
rst => rst_i(0),
wr_en => data_valid_i,
wr_data => data_i,
rd_en => rd_mdata_en,
rd_clk => clk_i,
rd_data => rd_v6_mdata,
full => open,
empty => rd_mdata_fifo_empty,
almost_full => open
);
-- tmp_sig <= cmp_valid AND data_valid_i;
-- xhdl2 <= ( tmp_sig & cmp_data);
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
-- delayed_data <= (tmp_sig & cmp_data);
cmp_data_r <= cmp_data;
end if;
end process;
rd_mdata_o <= rd_mdata;
rd_mdata <= rd_data_r WHEN (FAMILY = "SPARTAN6") ELSE rd_v6_mdata
WHEN ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) ELSE data_i;
cmp_data_valid <= cmp_data_en WHEN (FAMILY = "SPARTAN6") ELSE v6_data_cmp_valid
WHEN ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) ELSE data_valid_i;
cmp_data_o <= cmp_data_r;
cmp_addr_o <= gen_addr;
cmp_bl_o <= gen_bl;
-- xhdl4 : if (FAMILY = "SPARTAN6") generate
-- rd_data_o <= rd_data_r;
-- end generate;
-- xhdl5 : if (FAMILY /= "SPARTAN6") generate
-- rd_data_o <= data_i;
-- end generate;
data_rdy_o <= data_rdy;
data_rdy <= cmp_valid and data_valid_i;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
v6_data_cmp_valid <= rd_mdata_en;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
cmp_data_en <= data_rdy;
end if;
end process;
xhdl6 : if (FAMILY = "SPARTAN6") generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (cmp_data_en = '1') then
IF ((rd_data_r(DWIDTH / 2 - 1 downto 0) /= cmp_data_r(DWIDTH / 2 - 1 downto 0))) then
l_data_error <= '1' ;
ELSE
l_data_error <= '0' ;
END IF;
else
l_data_error <= '0' ;
end if;
if (cmp_data_en = '1') then
IF ((rd_data_r(DWIDTH - 1 downto DWIDTH / 2) /= cmp_data_r(DWIDTH - 1 downto DWIDTH / 2))) then
u_data_error <= '1' ;
ELSE
u_data_error <= '0' ;
END IF;
else
u_data_error <= '0' ;
end if;
data_error <= l_data_error or u_data_error;
--synthesis translate_off
if (data_error = '1') then
report ("DATA ERROR");
end if;
--synthesis translate_on
end if;
end process;
end generate;
gen_error_2 : if ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) generate
gen_cmp : FOR i IN 0 TO NUM_DQ_PINS / 2 - 1 GENERATE
error_byte(i) <= '1' WHEN (rd_mdata_fifo_empty = '0' AND rd_mdata_en = '1' AND (rd_v6_mdata(8 * (i + 1) - 1 DOWNTO 8 * i) /= cmp_data(8 * (i + 1) - 1 DOWNTO 8 * i))) ELSE '0';
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
error_byte_r1 <= (others => '0');
data_error <= '0';
ELSE
error_byte_r1 <= error_byte;
-- FOR i IN 0 TO DWIDTH - 1 LOOP
data_error <= REDUCTION_OR(error_byte_r1);--error_byte_r1(i) OR data_error;
-- END LOOP;
END IF;
end if;
end process;
process (data_error)
begin
--synthesis translate_off
IF (data_error = '1') THEN
report "DATA ERROR"; -- severity ERROR;
END IF;
--synthesis translate_on
end process;
gen_dq_error_map: FOR i IN 0 to DQ_ERROR_WIDTH - 1 generate
dq_lane_error(i) <= (error_byte_r1(i) OR error_byte_r1(i+DQ_ERROR_WIDTH) OR
error_byte_r1(i+ (NUM_DQ_PINS*2/8)) OR
error_byte_r1(i+ (NUM_DQ_PINS*3/8)));
cumlative_dq_lane_error_c(i) <= cumlative_dq_lane_error_reg(i) OR dq_lane_error_r1(i);
end generate;
process (clk_i)
begin
IF (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
dq_lane_error_r1 <= (others => '0');
dq_lane_error_r2 <= (others => '0');
data_valid_r <= '0';
cumlative_dq_lane_error_reg <= (others => '0');
ELSE
data_valid_r <= data_valid_i;
dq_lane_error_r1 <= dq_lane_error;
cumlative_dq_lane_error_reg <= cumlative_dq_lane_error_c;
END IF;
END IF;
end process;
end generate;
xhdl8 : if ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 8)) generate
gen_cmp_8 : FOR i IN 0 TO NUM_DQ_PINS / 2 - 1 GENERATE
error_byte(i) <= '1' WHEN (data_valid_i = '1' AND (data_i(8 * (i + 1) - 1 DOWNTO 8 * i) /= cmp_data(8 * (i + 1) - 1 DOWNTO 8 * i))) ELSE '0';
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
error_byte_r1 <= (others => '0');
data_error <= '0';
ELSE
error_byte_r1 <= error_byte;
--FOR i IN 0 TO DWIDTH - 1 LOOP
-- data_error <= error_byte_r1(i) OR data_error;
--END LOOP;
data_error <= REDUCTION_OR(error_byte_r1);--error_byte_r1(i) OR data_error;
--synthesis translate_off
IF (data_error = '1') THEN
report "DATA ERROR"; -- severity ERROR;
end if;
--synthesis translate_on
END IF;
end if;
end process;
gen_dq_error_map: FOR i IN 0 to DQ_ERROR_WIDTH - 1 generate
dq_lane_error(i) <= (error_byte_r1(i) OR error_byte_r1(i+DQ_ERROR_WIDTH) OR
error_byte_r1(i+ (NUM_DQ_PINS*2/8)) OR
error_byte_r1(i+ (NUM_DQ_PINS*3/8)));
cumlative_dq_lane_error_c(i) <= cumlative_dq_lane_error_reg(i) OR dq_lane_error_r1(i);
end generate;
process (clk_i)
begin
IF (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
dq_lane_error_r1 <= (others => '0');
dq_lane_error_r2 <= (others => '0');
data_valid_r <= '0';
cumlative_dq_lane_error_reg <= (others => '0');
ELSE
data_valid_r <= data_valid_i;
dq_lane_error_r1 <= dq_lane_error;
cumlative_dq_lane_error_reg <= cumlative_dq_lane_error_c;
END IF;
END IF;
end process;
end generate;
cumlative_dq_lane_error_r <= cumlative_dq_lane_error_reg;
dq_error_bytelane_cmp <= dq_lane_error_r1;
data_error_o <= data_error;
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: read_data_path.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This is top level of read path and also consist of comparison logic
-- for read data.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
entity read_data_path is
generic (
TCQ : time := 100 ps;
FAMILY : string := "VIRTEX6";
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : integer := 32;
CMP_DATA_PIPE_STAGES : integer := 3;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
DQ_ERROR_WIDTH : integer := 1;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
MEM_COL_WIDTH : integer := 10
);
port (
clk_i : in std_logic;
manual_clear_error : in std_logic;
rst_i : in std_logic_vector(9 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
cmd_sent : in std_logic_vector(2 downto 0);
bl_sent : in std_logic_vector(5 downto 0);
cmd_en_i : in std_logic;
-- m_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(31 downto 0);
bl_i : in std_logic_vector(5 downto 0);
-- input [5:0] port_data_counts_i,// connect to data port fifo counts
data_rdy_o : out std_logic;
data_valid_i : in std_logic;
data_i : in std_logic_vector(DWIDTH - 1 downto 0);
last_word_rd_o : out std_logic;
data_error_o : out std_logic;
cmp_data_o : out std_logic_vector(DWIDTH - 1 downto 0);
rd_mdata_o : out std_logic_vector(DWIDTH - 1 downto 0);
cmp_data_valid : out std_logic;
cmp_addr_o : out std_logic_vector(31 downto 0);
cmp_bl_o : out std_logic_vector(5 downto 0);
force_wrcmd_gen_o : out std_logic;
rd_buff_avail_o : out std_logic_vector(6 downto 0);
dq_error_bytelane_cmp : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
cumlative_dq_lane_error_r : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0)
);
end entity read_data_path;
architecture trans of read_data_path is
function REDUCTION_OR( A: in std_logic_vector) return std_logic is
variable tmp : std_logic := '0';
begin
for i in A'range loop
tmp := tmp or A(i);
end loop;
return tmp;
end function REDUCTION_OR;
COMPONENT read_posted_fifo IS
GENERIC (
TCQ : time := 100 ps;
MEM_BURST_LEN : integer := 4;
FAMILY : STRING := "SPARTAN6";
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
data_valid_i : IN STD_LOGIC;
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
user_bl_cnt_is_1 : IN STD_LOGIC;
cmd_sent : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
bl_sent : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
cmd_en_i : IN STD_LOGIC;
gen_rdy_i : IN STD_LOGIC;
gen_valid_o : OUT STD_LOGIC;
gen_addr_o : OUT STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
gen_bl_o : OUT STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
rd_buff_avail_o : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
rd_mdata_fifo_empty : IN STD_LOGIC;
rd_mdata_en : OUT STD_LOGIC
);
END COMPONENT;
component rd_data_gen is
generic (
FAMILY : string := "SPARTAN6";
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : integer := 32;
BL_WIDTH : integer := 6;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_PRBS";
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3;
COLUMN_WIDTH : integer := 10
);
port (
clk_i : in std_logic;
rst_i : in std_logic_vector(4 downto 0);
prbs_fseed_i : in std_logic_vector(31 downto 0);
rd_mdata_en : in std_logic;
data_mode_i : in std_logic_vector(3 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
last_word_o : out std_logic;
-- m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
bl_i : in std_logic_vector(BL_WIDTH - 1 downto 0);
user_bl_cnt_is_1_o : out std_logic;
data_rdy_i : in std_logic;
data_valid_o : out std_logic;
data_o : out std_logic_vector(DWIDTH - 1 downto 0)
);
end component;
component afifo IS
GENERIC (
DSIZE : INTEGER := 32;
FIFO_DEPTH : INTEGER := 16;
ASIZE : INTEGER := 5;
SYNC : INTEGER := 1
);
PORT (
wr_clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
wr_en : IN STD_LOGIC;
wr_data : IN STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
rd_en : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_data : OUT STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
almost_full : OUT STD_LOGIC;
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END component;
signal gen_rdy : std_logic;
signal gen_valid : std_logic;
signal gen_addr : std_logic_vector(31 downto 0);
signal gen_bl : std_logic_vector(5 downto 0);
signal cmp_rdy : std_logic;
signal cmp_valid : std_logic;
signal cmp_addr : std_logic_vector(31 downto 0);
signal cmp_bl : std_logic_vector(5 downto 0);
signal data_error : std_logic;
signal cmp_data : std_logic_vector(DWIDTH - 1 downto 0);
signal last_word_rd : std_logic;
signal bl_counter : std_logic_vector(5 downto 0);
signal cmd_rdy : std_logic;
signal user_bl_cnt_is_1 : std_logic;
signal data_rdy : std_logic;
signal delayed_data : std_logic_vector(DWIDTH downto 0);
-- signal cmp_data_piped : std_logic_vector(DWIDTH downto 0);
signal cmp_data_r : std_logic_vector(DWIDTH-1 downto 0);
signal rd_mdata_en : std_logic;
signal rd_data_r : std_logic_vector(DWIDTH - 1 downto 0);
signal force_wrcmd_gen : std_logic;
signal wait_bl_end : std_logic;
signal wait_bl_end_r1 : std_logic;
signal v6_data_cmp_valid : std_logic;
signal rd_v6_mdata : std_logic_vector(DWIDTH-1 downto 0);
signal cmpdata_r : std_logic_vector(DWIDTH-1 downto 0);
signal rd_mdata : std_logic_vector(DWIDTH-1 downto 0);
signal l_data_error : std_logic;
signal u_data_error : std_logic;
signal cmp_data_en : std_logic;
signal force_wrcmd_timeout_cnts : std_logic_vector(7 downto 0);
signal error_byte : std_logic_vector(NUM_DQ_PINS / 2 - 1 downto 0);
signal error_byte_r1 : std_logic_vector(NUM_DQ_PINS / 2 - 1 downto 0);
signal dq_lane_error : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal dq_lane_error_r1 : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal dq_lane_error_r2 : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cum_dq_lane_error_mask : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cumlative_dq_lane_error_reg : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cumlative_dq_lane_error_c : std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
signal rd_mdata_fifo_empty : std_logic;
signal data_valid_r : std_logic;
-- Declare intermediate signals for referenced outputs
-- SIGNAL xhdl2 : STD_LOGIC_VECTOR(DWIDTH DOWNTO 0);
-- SIGNAL tmp_sig : STD_LOGIC;
signal last_word_rd_o_xhdl0 : std_logic;
signal rd_buff_avail_o_xhdl1 : std_logic_vector(6 downto 0);
begin
-- Drive referenced outputs
last_word_rd_o <= last_word_rd_o_xhdl0;
rd_buff_avail_o <= rd_buff_avail_o_xhdl1;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
wait_bl_end_r1 <= wait_bl_end;
rd_data_r <= data_i;
end if;
end process;
force_wrcmd_gen_o <= force_wrcmd_gen;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
force_wrcmd_gen <= '0';
elsif ((wait_bl_end = '0' and wait_bl_end_r1 = '1') or force_wrcmd_timeout_cnts = "11111111") then
force_wrcmd_gen <= '0';
elsif ((cmd_valid_i = '1' and bl_i > "010000") or wait_bl_end = '1') then
force_wrcmd_gen <= '1';
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
force_wrcmd_timeout_cnts <= "00000000";
elsif (wait_bl_end = '0' and wait_bl_end_r1 = '1') then
force_wrcmd_timeout_cnts <= "00000000";
elsif (force_wrcmd_gen = '1') then
force_wrcmd_timeout_cnts <= force_wrcmd_timeout_cnts + "00000001";
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
wait_bl_end <= '0';
elsif (force_wrcmd_timeout_cnts = "11111111") then
wait_bl_end <= '0';
elsif ((gen_rdy and gen_valid) = '1' and gen_bl > "010000") then
wait_bl_end <= '1';
elsif ((wait_bl_end and user_bl_cnt_is_1) = '1') then
wait_bl_end <= '0';
end if;
end if;
end process;
cmd_rdy_o <= cmd_rdy;
read_postedfifo : read_posted_fifo
GENERIC MAP (
TCQ => TCQ,
FAMILY => FAMILY,
MEM_BURST_LEN => MEM_BURST_LEN,
ADDR_WIDTH => 32,
BL_WIDTH => 6
)
port map (
clk_i => clk_i,
rst_i => rst_i(0),
cmd_rdy_o => cmd_rdy,
cmd_valid_i => cmd_valid_i,
data_valid_i => data_rdy,
addr_i => addr_i,
bl_i => bl_i,
cmd_sent => cmd_sent,
bl_sent => bl_sent,
cmd_en_i => cmd_en_i,
user_bl_cnt_is_1 => user_bl_cnt_is_1,
gen_rdy_i => gen_rdy,
gen_valid_o => gen_valid,
gen_addr_o => gen_addr,
gen_bl_o => gen_bl,
rd_buff_avail_o => rd_buff_avail_o_xhdl1,
rd_mdata_fifo_empty => rd_mdata_fifo_empty,
rd_mdata_en => rd_mdata_en
);
rd_datagen : rd_data_gen
generic map (
FAMILY => FAMILY,
MEM_BURST_LEN => MEM_BURST_LEN,
NUM_DQ_PINS => NUM_DQ_PINS,
SEL_VICTIM_LINE => SEL_VICTIM_LINE,
DATA_PATTERN => DATA_PATTERN,
DWIDTH => DWIDTH,
COLUMN_WIDTH => MEM_COL_WIDTH
)
port map (
clk_i => clk_i,
rst_i => rst_i(4 downto 0),
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_rdy_o => gen_rdy,
cmd_valid_i => gen_valid,
last_word_o => last_word_rd_o_xhdl0,
-- m_addr_i => m_addr_i,
fixed_data_i => fixed_data_i,
addr_i => gen_addr,
bl_i => gen_bl,
user_bl_cnt_is_1_o => user_bl_cnt_is_1,
data_rdy_i => data_valid_i,
data_valid_o => cmp_valid,
data_o => cmp_data,
rd_mdata_en => rd_mdata_en
);
rd_mdata_fifo : afifo
GENERIC MAP (
DSIZE => DWIDTH,
FIFO_DEPTH => 32,
ASIZE => 5,
SYNC => 1
)
PORT MAP (
wr_clk => clk_i,
rst => rst_i(0),
wr_en => data_valid_i,
wr_data => data_i,
rd_en => rd_mdata_en,
rd_clk => clk_i,
rd_data => rd_v6_mdata,
full => open,
empty => rd_mdata_fifo_empty,
almost_full => open
);
-- tmp_sig <= cmp_valid AND data_valid_i;
-- xhdl2 <= ( tmp_sig & cmp_data);
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
-- delayed_data <= (tmp_sig & cmp_data);
cmp_data_r <= cmp_data;
end if;
end process;
rd_mdata_o <= rd_mdata;
rd_mdata <= rd_data_r WHEN (FAMILY = "SPARTAN6") ELSE rd_v6_mdata
WHEN ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) ELSE data_i;
cmp_data_valid <= cmp_data_en WHEN (FAMILY = "SPARTAN6") ELSE v6_data_cmp_valid
WHEN ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) ELSE data_valid_i;
cmp_data_o <= cmp_data_r;
cmp_addr_o <= gen_addr;
cmp_bl_o <= gen_bl;
-- xhdl4 : if (FAMILY = "SPARTAN6") generate
-- rd_data_o <= rd_data_r;
-- end generate;
-- xhdl5 : if (FAMILY /= "SPARTAN6") generate
-- rd_data_o <= data_i;
-- end generate;
data_rdy_o <= data_rdy;
data_rdy <= cmp_valid and data_valid_i;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
v6_data_cmp_valid <= rd_mdata_en;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
cmp_data_en <= data_rdy;
end if;
end process;
xhdl6 : if (FAMILY = "SPARTAN6") generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (cmp_data_en = '1') then
IF ((rd_data_r(DWIDTH / 2 - 1 downto 0) /= cmp_data_r(DWIDTH / 2 - 1 downto 0))) then
l_data_error <= '1' ;
ELSE
l_data_error <= '0' ;
END IF;
else
l_data_error <= '0' ;
end if;
if (cmp_data_en = '1') then
IF ((rd_data_r(DWIDTH - 1 downto DWIDTH / 2) /= cmp_data_r(DWIDTH - 1 downto DWIDTH / 2))) then
u_data_error <= '1' ;
ELSE
u_data_error <= '0' ;
END IF;
else
u_data_error <= '0' ;
end if;
data_error <= l_data_error or u_data_error;
--synthesis translate_off
if (data_error = '1') then
report ("DATA ERROR");
end if;
--synthesis translate_on
end if;
end process;
end generate;
gen_error_2 : if ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) generate
gen_cmp : FOR i IN 0 TO NUM_DQ_PINS / 2 - 1 GENERATE
error_byte(i) <= '1' WHEN (rd_mdata_fifo_empty = '0' AND rd_mdata_en = '1' AND (rd_v6_mdata(8 * (i + 1) - 1 DOWNTO 8 * i) /= cmp_data(8 * (i + 1) - 1 DOWNTO 8 * i))) ELSE '0';
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
error_byte_r1 <= (others => '0');
data_error <= '0';
ELSE
error_byte_r1 <= error_byte;
-- FOR i IN 0 TO DWIDTH - 1 LOOP
data_error <= REDUCTION_OR(error_byte_r1);--error_byte_r1(i) OR data_error;
-- END LOOP;
END IF;
end if;
end process;
process (data_error)
begin
--synthesis translate_off
IF (data_error = '1') THEN
report "DATA ERROR"; -- severity ERROR;
END IF;
--synthesis translate_on
end process;
gen_dq_error_map: FOR i IN 0 to DQ_ERROR_WIDTH - 1 generate
dq_lane_error(i) <= (error_byte_r1(i) OR error_byte_r1(i+DQ_ERROR_WIDTH) OR
error_byte_r1(i+ (NUM_DQ_PINS*2/8)) OR
error_byte_r1(i+ (NUM_DQ_PINS*3/8)));
cumlative_dq_lane_error_c(i) <= cumlative_dq_lane_error_reg(i) OR dq_lane_error_r1(i);
end generate;
process (clk_i)
begin
IF (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
dq_lane_error_r1 <= (others => '0');
dq_lane_error_r2 <= (others => '0');
data_valid_r <= '0';
cumlative_dq_lane_error_reg <= (others => '0');
ELSE
data_valid_r <= data_valid_i;
dq_lane_error_r1 <= dq_lane_error;
cumlative_dq_lane_error_reg <= cumlative_dq_lane_error_c;
END IF;
END IF;
end process;
end generate;
xhdl8 : if ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 8)) generate
gen_cmp_8 : FOR i IN 0 TO NUM_DQ_PINS / 2 - 1 GENERATE
error_byte(i) <= '1' WHEN (data_valid_i = '1' AND (data_i(8 * (i + 1) - 1 DOWNTO 8 * i) /= cmp_data(8 * (i + 1) - 1 DOWNTO 8 * i))) ELSE '0';
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
error_byte_r1 <= (others => '0');
data_error <= '0';
ELSE
error_byte_r1 <= error_byte;
--FOR i IN 0 TO DWIDTH - 1 LOOP
-- data_error <= error_byte_r1(i) OR data_error;
--END LOOP;
data_error <= REDUCTION_OR(error_byte_r1);--error_byte_r1(i) OR data_error;
--synthesis translate_off
IF (data_error = '1') THEN
report "DATA ERROR"; -- severity ERROR;
end if;
--synthesis translate_on
END IF;
end if;
end process;
gen_dq_error_map: FOR i IN 0 to DQ_ERROR_WIDTH - 1 generate
dq_lane_error(i) <= (error_byte_r1(i) OR error_byte_r1(i+DQ_ERROR_WIDTH) OR
error_byte_r1(i+ (NUM_DQ_PINS*2/8)) OR
error_byte_r1(i+ (NUM_DQ_PINS*3/8)));
cumlative_dq_lane_error_c(i) <= cumlative_dq_lane_error_reg(i) OR dq_lane_error_r1(i);
end generate;
process (clk_i)
begin
IF (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
dq_lane_error_r1 <= (others => '0');
dq_lane_error_r2 <= (others => '0');
data_valid_r <= '0';
cumlative_dq_lane_error_reg <= (others => '0');
ELSE
data_valid_r <= data_valid_i;
dq_lane_error_r1 <= dq_lane_error;
cumlative_dq_lane_error_reg <= cumlative_dq_lane_error_c;
END IF;
END IF;
end process;
end generate;
cumlative_dq_lane_error_r <= cumlative_dq_lane_error_reg;
dq_error_bytelane_cmp <= dq_lane_error_r1;
data_error_o <= data_error;
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: read_data_path.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This is top level of read path and also consist of comparison logic
-- for read data.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
entity read_data_path is
generic (
TCQ : time := 100 ps;
FAMILY : string := "VIRTEX6";
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : integer := 32;
CMP_DATA_PIPE_STAGES : integer := 3;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
DQ_ERROR_WIDTH : integer := 1;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
MEM_COL_WIDTH : integer := 10
);
port (
clk_i : in std_logic;
manual_clear_error : in std_logic;
rst_i : in std_logic_vector(9 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
cmd_sent : in std_logic_vector(2 downto 0);
bl_sent : in std_logic_vector(5 downto 0);
cmd_en_i : in std_logic;
-- m_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(31 downto 0);
bl_i : in std_logic_vector(5 downto 0);
-- input [5:0] port_data_counts_i,// connect to data port fifo counts
data_rdy_o : out std_logic;
data_valid_i : in std_logic;
data_i : in std_logic_vector(DWIDTH - 1 downto 0);
last_word_rd_o : out std_logic;
data_error_o : out std_logic;
cmp_data_o : out std_logic_vector(DWIDTH - 1 downto 0);
rd_mdata_o : out std_logic_vector(DWIDTH - 1 downto 0);
cmp_data_valid : out std_logic;
cmp_addr_o : out std_logic_vector(31 downto 0);
cmp_bl_o : out std_logic_vector(5 downto 0);
force_wrcmd_gen_o : out std_logic;
rd_buff_avail_o : out std_logic_vector(6 downto 0);
dq_error_bytelane_cmp : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
cumlative_dq_lane_error_r : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0)
);
end entity read_data_path;
architecture trans of read_data_path is
function REDUCTION_OR( A: in std_logic_vector) return std_logic is
variable tmp : std_logic := '0';
begin
for i in A'range loop
tmp := tmp or A(i);
end loop;
return tmp;
end function REDUCTION_OR;
COMPONENT read_posted_fifo IS
GENERIC (
TCQ : time := 100 ps;
MEM_BURST_LEN : integer := 4;
FAMILY : STRING := "SPARTAN6";
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
data_valid_i : IN STD_LOGIC;
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
user_bl_cnt_is_1 : IN STD_LOGIC;
cmd_sent : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
bl_sent : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
cmd_en_i : IN STD_LOGIC;
gen_rdy_i : IN STD_LOGIC;
gen_valid_o : OUT STD_LOGIC;
gen_addr_o : OUT STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
gen_bl_o : OUT STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
rd_buff_avail_o : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
rd_mdata_fifo_empty : IN STD_LOGIC;
rd_mdata_en : OUT STD_LOGIC
);
END COMPONENT;
component rd_data_gen is
generic (
FAMILY : string := "SPARTAN6";
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : integer := 32;
BL_WIDTH : integer := 6;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_PRBS";
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3;
COLUMN_WIDTH : integer := 10
);
port (
clk_i : in std_logic;
rst_i : in std_logic_vector(4 downto 0);
prbs_fseed_i : in std_logic_vector(31 downto 0);
rd_mdata_en : in std_logic;
data_mode_i : in std_logic_vector(3 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
last_word_o : out std_logic;
-- m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
bl_i : in std_logic_vector(BL_WIDTH - 1 downto 0);
user_bl_cnt_is_1_o : out std_logic;
data_rdy_i : in std_logic;
data_valid_o : out std_logic;
data_o : out std_logic_vector(DWIDTH - 1 downto 0)
);
end component;
component afifo IS
GENERIC (
DSIZE : INTEGER := 32;
FIFO_DEPTH : INTEGER := 16;
ASIZE : INTEGER := 5;
SYNC : INTEGER := 1
);
PORT (
wr_clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
wr_en : IN STD_LOGIC;
wr_data : IN STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
rd_en : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_data : OUT STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
almost_full : OUT STD_LOGIC;
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END component;
signal gen_rdy : std_logic;
signal gen_valid : std_logic;
signal gen_addr : std_logic_vector(31 downto 0);
signal gen_bl : std_logic_vector(5 downto 0);
signal cmp_rdy : std_logic;
signal cmp_valid : std_logic;
signal cmp_addr : std_logic_vector(31 downto 0);
signal cmp_bl : std_logic_vector(5 downto 0);
signal data_error : std_logic;
signal cmp_data : std_logic_vector(DWIDTH - 1 downto 0);
signal last_word_rd : std_logic;
signal bl_counter : std_logic_vector(5 downto 0);
signal cmd_rdy : std_logic;
signal user_bl_cnt_is_1 : std_logic;
signal data_rdy : std_logic;
signal delayed_data : std_logic_vector(DWIDTH downto 0);
-- signal cmp_data_piped : std_logic_vector(DWIDTH downto 0);
signal cmp_data_r : std_logic_vector(DWIDTH-1 downto 0);
signal rd_mdata_en : std_logic;
signal rd_data_r : std_logic_vector(DWIDTH - 1 downto 0);
signal force_wrcmd_gen : std_logic;
signal wait_bl_end : std_logic;
signal wait_bl_end_r1 : std_logic;
signal v6_data_cmp_valid : std_logic;
signal rd_v6_mdata : std_logic_vector(DWIDTH-1 downto 0);
signal cmpdata_r : std_logic_vector(DWIDTH-1 downto 0);
signal rd_mdata : std_logic_vector(DWIDTH-1 downto 0);
signal l_data_error : std_logic;
signal u_data_error : std_logic;
signal cmp_data_en : std_logic;
signal force_wrcmd_timeout_cnts : std_logic_vector(7 downto 0);
signal error_byte : std_logic_vector(NUM_DQ_PINS / 2 - 1 downto 0);
signal error_byte_r1 : std_logic_vector(NUM_DQ_PINS / 2 - 1 downto 0);
signal dq_lane_error : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal dq_lane_error_r1 : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal dq_lane_error_r2 : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cum_dq_lane_error_mask : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cumlative_dq_lane_error_reg : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cumlative_dq_lane_error_c : std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
signal rd_mdata_fifo_empty : std_logic;
signal data_valid_r : std_logic;
-- Declare intermediate signals for referenced outputs
-- SIGNAL xhdl2 : STD_LOGIC_VECTOR(DWIDTH DOWNTO 0);
-- SIGNAL tmp_sig : STD_LOGIC;
signal last_word_rd_o_xhdl0 : std_logic;
signal rd_buff_avail_o_xhdl1 : std_logic_vector(6 downto 0);
begin
-- Drive referenced outputs
last_word_rd_o <= last_word_rd_o_xhdl0;
rd_buff_avail_o <= rd_buff_avail_o_xhdl1;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
wait_bl_end_r1 <= wait_bl_end;
rd_data_r <= data_i;
end if;
end process;
force_wrcmd_gen_o <= force_wrcmd_gen;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
force_wrcmd_gen <= '0';
elsif ((wait_bl_end = '0' and wait_bl_end_r1 = '1') or force_wrcmd_timeout_cnts = "11111111") then
force_wrcmd_gen <= '0';
elsif ((cmd_valid_i = '1' and bl_i > "010000") or wait_bl_end = '1') then
force_wrcmd_gen <= '1';
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
force_wrcmd_timeout_cnts <= "00000000";
elsif (wait_bl_end = '0' and wait_bl_end_r1 = '1') then
force_wrcmd_timeout_cnts <= "00000000";
elsif (force_wrcmd_gen = '1') then
force_wrcmd_timeout_cnts <= force_wrcmd_timeout_cnts + "00000001";
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
wait_bl_end <= '0';
elsif (force_wrcmd_timeout_cnts = "11111111") then
wait_bl_end <= '0';
elsif ((gen_rdy and gen_valid) = '1' and gen_bl > "010000") then
wait_bl_end <= '1';
elsif ((wait_bl_end and user_bl_cnt_is_1) = '1') then
wait_bl_end <= '0';
end if;
end if;
end process;
cmd_rdy_o <= cmd_rdy;
read_postedfifo : read_posted_fifo
GENERIC MAP (
TCQ => TCQ,
FAMILY => FAMILY,
MEM_BURST_LEN => MEM_BURST_LEN,
ADDR_WIDTH => 32,
BL_WIDTH => 6
)
port map (
clk_i => clk_i,
rst_i => rst_i(0),
cmd_rdy_o => cmd_rdy,
cmd_valid_i => cmd_valid_i,
data_valid_i => data_rdy,
addr_i => addr_i,
bl_i => bl_i,
cmd_sent => cmd_sent,
bl_sent => bl_sent,
cmd_en_i => cmd_en_i,
user_bl_cnt_is_1 => user_bl_cnt_is_1,
gen_rdy_i => gen_rdy,
gen_valid_o => gen_valid,
gen_addr_o => gen_addr,
gen_bl_o => gen_bl,
rd_buff_avail_o => rd_buff_avail_o_xhdl1,
rd_mdata_fifo_empty => rd_mdata_fifo_empty,
rd_mdata_en => rd_mdata_en
);
rd_datagen : rd_data_gen
generic map (
FAMILY => FAMILY,
MEM_BURST_LEN => MEM_BURST_LEN,
NUM_DQ_PINS => NUM_DQ_PINS,
SEL_VICTIM_LINE => SEL_VICTIM_LINE,
DATA_PATTERN => DATA_PATTERN,
DWIDTH => DWIDTH,
COLUMN_WIDTH => MEM_COL_WIDTH
)
port map (
clk_i => clk_i,
rst_i => rst_i(4 downto 0),
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_rdy_o => gen_rdy,
cmd_valid_i => gen_valid,
last_word_o => last_word_rd_o_xhdl0,
-- m_addr_i => m_addr_i,
fixed_data_i => fixed_data_i,
addr_i => gen_addr,
bl_i => gen_bl,
user_bl_cnt_is_1_o => user_bl_cnt_is_1,
data_rdy_i => data_valid_i,
data_valid_o => cmp_valid,
data_o => cmp_data,
rd_mdata_en => rd_mdata_en
);
rd_mdata_fifo : afifo
GENERIC MAP (
DSIZE => DWIDTH,
FIFO_DEPTH => 32,
ASIZE => 5,
SYNC => 1
)
PORT MAP (
wr_clk => clk_i,
rst => rst_i(0),
wr_en => data_valid_i,
wr_data => data_i,
rd_en => rd_mdata_en,
rd_clk => clk_i,
rd_data => rd_v6_mdata,
full => open,
empty => rd_mdata_fifo_empty,
almost_full => open
);
-- tmp_sig <= cmp_valid AND data_valid_i;
-- xhdl2 <= ( tmp_sig & cmp_data);
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
-- delayed_data <= (tmp_sig & cmp_data);
cmp_data_r <= cmp_data;
end if;
end process;
rd_mdata_o <= rd_mdata;
rd_mdata <= rd_data_r WHEN (FAMILY = "SPARTAN6") ELSE rd_v6_mdata
WHEN ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) ELSE data_i;
cmp_data_valid <= cmp_data_en WHEN (FAMILY = "SPARTAN6") ELSE v6_data_cmp_valid
WHEN ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) ELSE data_valid_i;
cmp_data_o <= cmp_data_r;
cmp_addr_o <= gen_addr;
cmp_bl_o <= gen_bl;
-- xhdl4 : if (FAMILY = "SPARTAN6") generate
-- rd_data_o <= rd_data_r;
-- end generate;
-- xhdl5 : if (FAMILY /= "SPARTAN6") generate
-- rd_data_o <= data_i;
-- end generate;
data_rdy_o <= data_rdy;
data_rdy <= cmp_valid and data_valid_i;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
v6_data_cmp_valid <= rd_mdata_en;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
cmp_data_en <= data_rdy;
end if;
end process;
xhdl6 : if (FAMILY = "SPARTAN6") generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (cmp_data_en = '1') then
IF ((rd_data_r(DWIDTH / 2 - 1 downto 0) /= cmp_data_r(DWIDTH / 2 - 1 downto 0))) then
l_data_error <= '1' ;
ELSE
l_data_error <= '0' ;
END IF;
else
l_data_error <= '0' ;
end if;
if (cmp_data_en = '1') then
IF ((rd_data_r(DWIDTH - 1 downto DWIDTH / 2) /= cmp_data_r(DWIDTH - 1 downto DWIDTH / 2))) then
u_data_error <= '1' ;
ELSE
u_data_error <= '0' ;
END IF;
else
u_data_error <= '0' ;
end if;
data_error <= l_data_error or u_data_error;
--synthesis translate_off
if (data_error = '1') then
report ("DATA ERROR");
end if;
--synthesis translate_on
end if;
end process;
end generate;
gen_error_2 : if ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) generate
gen_cmp : FOR i IN 0 TO NUM_DQ_PINS / 2 - 1 GENERATE
error_byte(i) <= '1' WHEN (rd_mdata_fifo_empty = '0' AND rd_mdata_en = '1' AND (rd_v6_mdata(8 * (i + 1) - 1 DOWNTO 8 * i) /= cmp_data(8 * (i + 1) - 1 DOWNTO 8 * i))) ELSE '0';
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
error_byte_r1 <= (others => '0');
data_error <= '0';
ELSE
error_byte_r1 <= error_byte;
-- FOR i IN 0 TO DWIDTH - 1 LOOP
data_error <= REDUCTION_OR(error_byte_r1);--error_byte_r1(i) OR data_error;
-- END LOOP;
END IF;
end if;
end process;
process (data_error)
begin
--synthesis translate_off
IF (data_error = '1') THEN
report "DATA ERROR"; -- severity ERROR;
END IF;
--synthesis translate_on
end process;
gen_dq_error_map: FOR i IN 0 to DQ_ERROR_WIDTH - 1 generate
dq_lane_error(i) <= (error_byte_r1(i) OR error_byte_r1(i+DQ_ERROR_WIDTH) OR
error_byte_r1(i+ (NUM_DQ_PINS*2/8)) OR
error_byte_r1(i+ (NUM_DQ_PINS*3/8)));
cumlative_dq_lane_error_c(i) <= cumlative_dq_lane_error_reg(i) OR dq_lane_error_r1(i);
end generate;
process (clk_i)
begin
IF (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
dq_lane_error_r1 <= (others => '0');
dq_lane_error_r2 <= (others => '0');
data_valid_r <= '0';
cumlative_dq_lane_error_reg <= (others => '0');
ELSE
data_valid_r <= data_valid_i;
dq_lane_error_r1 <= dq_lane_error;
cumlative_dq_lane_error_reg <= cumlative_dq_lane_error_c;
END IF;
END IF;
end process;
end generate;
xhdl8 : if ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 8)) generate
gen_cmp_8 : FOR i IN 0 TO NUM_DQ_PINS / 2 - 1 GENERATE
error_byte(i) <= '1' WHEN (data_valid_i = '1' AND (data_i(8 * (i + 1) - 1 DOWNTO 8 * i) /= cmp_data(8 * (i + 1) - 1 DOWNTO 8 * i))) ELSE '0';
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
error_byte_r1 <= (others => '0');
data_error <= '0';
ELSE
error_byte_r1 <= error_byte;
--FOR i IN 0 TO DWIDTH - 1 LOOP
-- data_error <= error_byte_r1(i) OR data_error;
--END LOOP;
data_error <= REDUCTION_OR(error_byte_r1);--error_byte_r1(i) OR data_error;
--synthesis translate_off
IF (data_error = '1') THEN
report "DATA ERROR"; -- severity ERROR;
end if;
--synthesis translate_on
END IF;
end if;
end process;
gen_dq_error_map: FOR i IN 0 to DQ_ERROR_WIDTH - 1 generate
dq_lane_error(i) <= (error_byte_r1(i) OR error_byte_r1(i+DQ_ERROR_WIDTH) OR
error_byte_r1(i+ (NUM_DQ_PINS*2/8)) OR
error_byte_r1(i+ (NUM_DQ_PINS*3/8)));
cumlative_dq_lane_error_c(i) <= cumlative_dq_lane_error_reg(i) OR dq_lane_error_r1(i);
end generate;
process (clk_i)
begin
IF (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
dq_lane_error_r1 <= (others => '0');
dq_lane_error_r2 <= (others => '0');
data_valid_r <= '0';
cumlative_dq_lane_error_reg <= (others => '0');
ELSE
data_valid_r <= data_valid_i;
dq_lane_error_r1 <= dq_lane_error;
cumlative_dq_lane_error_reg <= cumlative_dq_lane_error_c;
END IF;
END IF;
end process;
end generate;
cumlative_dq_lane_error_r <= cumlative_dq_lane_error_reg;
dq_error_bytelane_cmp <= dq_lane_error_r1;
data_error_o <= data_error;
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: read_data_path.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This is top level of read path and also consist of comparison logic
-- for read data.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
entity read_data_path is
generic (
TCQ : time := 100 ps;
FAMILY : string := "VIRTEX6";
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : integer := 32;
CMP_DATA_PIPE_STAGES : integer := 3;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
DQ_ERROR_WIDTH : integer := 1;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
MEM_COL_WIDTH : integer := 10
);
port (
clk_i : in std_logic;
manual_clear_error : in std_logic;
rst_i : in std_logic_vector(9 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
cmd_sent : in std_logic_vector(2 downto 0);
bl_sent : in std_logic_vector(5 downto 0);
cmd_en_i : in std_logic;
-- m_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(31 downto 0);
bl_i : in std_logic_vector(5 downto 0);
-- input [5:0] port_data_counts_i,// connect to data port fifo counts
data_rdy_o : out std_logic;
data_valid_i : in std_logic;
data_i : in std_logic_vector(DWIDTH - 1 downto 0);
last_word_rd_o : out std_logic;
data_error_o : out std_logic;
cmp_data_o : out std_logic_vector(DWIDTH - 1 downto 0);
rd_mdata_o : out std_logic_vector(DWIDTH - 1 downto 0);
cmp_data_valid : out std_logic;
cmp_addr_o : out std_logic_vector(31 downto 0);
cmp_bl_o : out std_logic_vector(5 downto 0);
force_wrcmd_gen_o : out std_logic;
rd_buff_avail_o : out std_logic_vector(6 downto 0);
dq_error_bytelane_cmp : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
cumlative_dq_lane_error_r : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0)
);
end entity read_data_path;
architecture trans of read_data_path is
function REDUCTION_OR( A: in std_logic_vector) return std_logic is
variable tmp : std_logic := '0';
begin
for i in A'range loop
tmp := tmp or A(i);
end loop;
return tmp;
end function REDUCTION_OR;
COMPONENT read_posted_fifo IS
GENERIC (
TCQ : time := 100 ps;
MEM_BURST_LEN : integer := 4;
FAMILY : STRING := "SPARTAN6";
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
data_valid_i : IN STD_LOGIC;
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
user_bl_cnt_is_1 : IN STD_LOGIC;
cmd_sent : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
bl_sent : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
cmd_en_i : IN STD_LOGIC;
gen_rdy_i : IN STD_LOGIC;
gen_valid_o : OUT STD_LOGIC;
gen_addr_o : OUT STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
gen_bl_o : OUT STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
rd_buff_avail_o : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
rd_mdata_fifo_empty : IN STD_LOGIC;
rd_mdata_en : OUT STD_LOGIC
);
END COMPONENT;
component rd_data_gen is
generic (
FAMILY : string := "SPARTAN6";
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : integer := 32;
BL_WIDTH : integer := 6;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_PRBS";
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3;
COLUMN_WIDTH : integer := 10
);
port (
clk_i : in std_logic;
rst_i : in std_logic_vector(4 downto 0);
prbs_fseed_i : in std_logic_vector(31 downto 0);
rd_mdata_en : in std_logic;
data_mode_i : in std_logic_vector(3 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
last_word_o : out std_logic;
-- m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
bl_i : in std_logic_vector(BL_WIDTH - 1 downto 0);
user_bl_cnt_is_1_o : out std_logic;
data_rdy_i : in std_logic;
data_valid_o : out std_logic;
data_o : out std_logic_vector(DWIDTH - 1 downto 0)
);
end component;
component afifo IS
GENERIC (
DSIZE : INTEGER := 32;
FIFO_DEPTH : INTEGER := 16;
ASIZE : INTEGER := 5;
SYNC : INTEGER := 1
);
PORT (
wr_clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
wr_en : IN STD_LOGIC;
wr_data : IN STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
rd_en : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_data : OUT STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
almost_full : OUT STD_LOGIC;
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END component;
signal gen_rdy : std_logic;
signal gen_valid : std_logic;
signal gen_addr : std_logic_vector(31 downto 0);
signal gen_bl : std_logic_vector(5 downto 0);
signal cmp_rdy : std_logic;
signal cmp_valid : std_logic;
signal cmp_addr : std_logic_vector(31 downto 0);
signal cmp_bl : std_logic_vector(5 downto 0);
signal data_error : std_logic;
signal cmp_data : std_logic_vector(DWIDTH - 1 downto 0);
signal last_word_rd : std_logic;
signal bl_counter : std_logic_vector(5 downto 0);
signal cmd_rdy : std_logic;
signal user_bl_cnt_is_1 : std_logic;
signal data_rdy : std_logic;
signal delayed_data : std_logic_vector(DWIDTH downto 0);
-- signal cmp_data_piped : std_logic_vector(DWIDTH downto 0);
signal cmp_data_r : std_logic_vector(DWIDTH-1 downto 0);
signal rd_mdata_en : std_logic;
signal rd_data_r : std_logic_vector(DWIDTH - 1 downto 0);
signal force_wrcmd_gen : std_logic;
signal wait_bl_end : std_logic;
signal wait_bl_end_r1 : std_logic;
signal v6_data_cmp_valid : std_logic;
signal rd_v6_mdata : std_logic_vector(DWIDTH-1 downto 0);
signal cmpdata_r : std_logic_vector(DWIDTH-1 downto 0);
signal rd_mdata : std_logic_vector(DWIDTH-1 downto 0);
signal l_data_error : std_logic;
signal u_data_error : std_logic;
signal cmp_data_en : std_logic;
signal force_wrcmd_timeout_cnts : std_logic_vector(7 downto 0);
signal error_byte : std_logic_vector(NUM_DQ_PINS / 2 - 1 downto 0);
signal error_byte_r1 : std_logic_vector(NUM_DQ_PINS / 2 - 1 downto 0);
signal dq_lane_error : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal dq_lane_error_r1 : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal dq_lane_error_r2 : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cum_dq_lane_error_mask : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cumlative_dq_lane_error_reg : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cumlative_dq_lane_error_c : std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
signal rd_mdata_fifo_empty : std_logic;
signal data_valid_r : std_logic;
-- Declare intermediate signals for referenced outputs
-- SIGNAL xhdl2 : STD_LOGIC_VECTOR(DWIDTH DOWNTO 0);
-- SIGNAL tmp_sig : STD_LOGIC;
signal last_word_rd_o_xhdl0 : std_logic;
signal rd_buff_avail_o_xhdl1 : std_logic_vector(6 downto 0);
begin
-- Drive referenced outputs
last_word_rd_o <= last_word_rd_o_xhdl0;
rd_buff_avail_o <= rd_buff_avail_o_xhdl1;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
wait_bl_end_r1 <= wait_bl_end;
rd_data_r <= data_i;
end if;
end process;
force_wrcmd_gen_o <= force_wrcmd_gen;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
force_wrcmd_gen <= '0';
elsif ((wait_bl_end = '0' and wait_bl_end_r1 = '1') or force_wrcmd_timeout_cnts = "11111111") then
force_wrcmd_gen <= '0';
elsif ((cmd_valid_i = '1' and bl_i > "010000") or wait_bl_end = '1') then
force_wrcmd_gen <= '1';
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
force_wrcmd_timeout_cnts <= "00000000";
elsif (wait_bl_end = '0' and wait_bl_end_r1 = '1') then
force_wrcmd_timeout_cnts <= "00000000";
elsif (force_wrcmd_gen = '1') then
force_wrcmd_timeout_cnts <= force_wrcmd_timeout_cnts + "00000001";
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
wait_bl_end <= '0';
elsif (force_wrcmd_timeout_cnts = "11111111") then
wait_bl_end <= '0';
elsif ((gen_rdy and gen_valid) = '1' and gen_bl > "010000") then
wait_bl_end <= '1';
elsif ((wait_bl_end and user_bl_cnt_is_1) = '1') then
wait_bl_end <= '0';
end if;
end if;
end process;
cmd_rdy_o <= cmd_rdy;
read_postedfifo : read_posted_fifo
GENERIC MAP (
TCQ => TCQ,
FAMILY => FAMILY,
MEM_BURST_LEN => MEM_BURST_LEN,
ADDR_WIDTH => 32,
BL_WIDTH => 6
)
port map (
clk_i => clk_i,
rst_i => rst_i(0),
cmd_rdy_o => cmd_rdy,
cmd_valid_i => cmd_valid_i,
data_valid_i => data_rdy,
addr_i => addr_i,
bl_i => bl_i,
cmd_sent => cmd_sent,
bl_sent => bl_sent,
cmd_en_i => cmd_en_i,
user_bl_cnt_is_1 => user_bl_cnt_is_1,
gen_rdy_i => gen_rdy,
gen_valid_o => gen_valid,
gen_addr_o => gen_addr,
gen_bl_o => gen_bl,
rd_buff_avail_o => rd_buff_avail_o_xhdl1,
rd_mdata_fifo_empty => rd_mdata_fifo_empty,
rd_mdata_en => rd_mdata_en
);
rd_datagen : rd_data_gen
generic map (
FAMILY => FAMILY,
MEM_BURST_LEN => MEM_BURST_LEN,
NUM_DQ_PINS => NUM_DQ_PINS,
SEL_VICTIM_LINE => SEL_VICTIM_LINE,
DATA_PATTERN => DATA_PATTERN,
DWIDTH => DWIDTH,
COLUMN_WIDTH => MEM_COL_WIDTH
)
port map (
clk_i => clk_i,
rst_i => rst_i(4 downto 0),
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_rdy_o => gen_rdy,
cmd_valid_i => gen_valid,
last_word_o => last_word_rd_o_xhdl0,
-- m_addr_i => m_addr_i,
fixed_data_i => fixed_data_i,
addr_i => gen_addr,
bl_i => gen_bl,
user_bl_cnt_is_1_o => user_bl_cnt_is_1,
data_rdy_i => data_valid_i,
data_valid_o => cmp_valid,
data_o => cmp_data,
rd_mdata_en => rd_mdata_en
);
rd_mdata_fifo : afifo
GENERIC MAP (
DSIZE => DWIDTH,
FIFO_DEPTH => 32,
ASIZE => 5,
SYNC => 1
)
PORT MAP (
wr_clk => clk_i,
rst => rst_i(0),
wr_en => data_valid_i,
wr_data => data_i,
rd_en => rd_mdata_en,
rd_clk => clk_i,
rd_data => rd_v6_mdata,
full => open,
empty => rd_mdata_fifo_empty,
almost_full => open
);
-- tmp_sig <= cmp_valid AND data_valid_i;
-- xhdl2 <= ( tmp_sig & cmp_data);
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
-- delayed_data <= (tmp_sig & cmp_data);
cmp_data_r <= cmp_data;
end if;
end process;
rd_mdata_o <= rd_mdata;
rd_mdata <= rd_data_r WHEN (FAMILY = "SPARTAN6") ELSE rd_v6_mdata
WHEN ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) ELSE data_i;
cmp_data_valid <= cmp_data_en WHEN (FAMILY = "SPARTAN6") ELSE v6_data_cmp_valid
WHEN ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) ELSE data_valid_i;
cmp_data_o <= cmp_data_r;
cmp_addr_o <= gen_addr;
cmp_bl_o <= gen_bl;
-- xhdl4 : if (FAMILY = "SPARTAN6") generate
-- rd_data_o <= rd_data_r;
-- end generate;
-- xhdl5 : if (FAMILY /= "SPARTAN6") generate
-- rd_data_o <= data_i;
-- end generate;
data_rdy_o <= data_rdy;
data_rdy <= cmp_valid and data_valid_i;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
v6_data_cmp_valid <= rd_mdata_en;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
cmp_data_en <= data_rdy;
end if;
end process;
xhdl6 : if (FAMILY = "SPARTAN6") generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (cmp_data_en = '1') then
IF ((rd_data_r(DWIDTH / 2 - 1 downto 0) /= cmp_data_r(DWIDTH / 2 - 1 downto 0))) then
l_data_error <= '1' ;
ELSE
l_data_error <= '0' ;
END IF;
else
l_data_error <= '0' ;
end if;
if (cmp_data_en = '1') then
IF ((rd_data_r(DWIDTH - 1 downto DWIDTH / 2) /= cmp_data_r(DWIDTH - 1 downto DWIDTH / 2))) then
u_data_error <= '1' ;
ELSE
u_data_error <= '0' ;
END IF;
else
u_data_error <= '0' ;
end if;
data_error <= l_data_error or u_data_error;
--synthesis translate_off
if (data_error = '1') then
report ("DATA ERROR");
end if;
--synthesis translate_on
end if;
end process;
end generate;
gen_error_2 : if ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) generate
gen_cmp : FOR i IN 0 TO NUM_DQ_PINS / 2 - 1 GENERATE
error_byte(i) <= '1' WHEN (rd_mdata_fifo_empty = '0' AND rd_mdata_en = '1' AND (rd_v6_mdata(8 * (i + 1) - 1 DOWNTO 8 * i) /= cmp_data(8 * (i + 1) - 1 DOWNTO 8 * i))) ELSE '0';
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
error_byte_r1 <= (others => '0');
data_error <= '0';
ELSE
error_byte_r1 <= error_byte;
-- FOR i IN 0 TO DWIDTH - 1 LOOP
data_error <= REDUCTION_OR(error_byte_r1);--error_byte_r1(i) OR data_error;
-- END LOOP;
END IF;
end if;
end process;
process (data_error)
begin
--synthesis translate_off
IF (data_error = '1') THEN
report "DATA ERROR"; -- severity ERROR;
END IF;
--synthesis translate_on
end process;
gen_dq_error_map: FOR i IN 0 to DQ_ERROR_WIDTH - 1 generate
dq_lane_error(i) <= (error_byte_r1(i) OR error_byte_r1(i+DQ_ERROR_WIDTH) OR
error_byte_r1(i+ (NUM_DQ_PINS*2/8)) OR
error_byte_r1(i+ (NUM_DQ_PINS*3/8)));
cumlative_dq_lane_error_c(i) <= cumlative_dq_lane_error_reg(i) OR dq_lane_error_r1(i);
end generate;
process (clk_i)
begin
IF (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
dq_lane_error_r1 <= (others => '0');
dq_lane_error_r2 <= (others => '0');
data_valid_r <= '0';
cumlative_dq_lane_error_reg <= (others => '0');
ELSE
data_valid_r <= data_valid_i;
dq_lane_error_r1 <= dq_lane_error;
cumlative_dq_lane_error_reg <= cumlative_dq_lane_error_c;
END IF;
END IF;
end process;
end generate;
xhdl8 : if ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 8)) generate
gen_cmp_8 : FOR i IN 0 TO NUM_DQ_PINS / 2 - 1 GENERATE
error_byte(i) <= '1' WHEN (data_valid_i = '1' AND (data_i(8 * (i + 1) - 1 DOWNTO 8 * i) /= cmp_data(8 * (i + 1) - 1 DOWNTO 8 * i))) ELSE '0';
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
error_byte_r1 <= (others => '0');
data_error <= '0';
ELSE
error_byte_r1 <= error_byte;
--FOR i IN 0 TO DWIDTH - 1 LOOP
-- data_error <= error_byte_r1(i) OR data_error;
--END LOOP;
data_error <= REDUCTION_OR(error_byte_r1);--error_byte_r1(i) OR data_error;
--synthesis translate_off
IF (data_error = '1') THEN
report "DATA ERROR"; -- severity ERROR;
end if;
--synthesis translate_on
END IF;
end if;
end process;
gen_dq_error_map: FOR i IN 0 to DQ_ERROR_WIDTH - 1 generate
dq_lane_error(i) <= (error_byte_r1(i) OR error_byte_r1(i+DQ_ERROR_WIDTH) OR
error_byte_r1(i+ (NUM_DQ_PINS*2/8)) OR
error_byte_r1(i+ (NUM_DQ_PINS*3/8)));
cumlative_dq_lane_error_c(i) <= cumlative_dq_lane_error_reg(i) OR dq_lane_error_r1(i);
end generate;
process (clk_i)
begin
IF (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
dq_lane_error_r1 <= (others => '0');
dq_lane_error_r2 <= (others => '0');
data_valid_r <= '0';
cumlative_dq_lane_error_reg <= (others => '0');
ELSE
data_valid_r <= data_valid_i;
dq_lane_error_r1 <= dq_lane_error;
cumlative_dq_lane_error_reg <= cumlative_dq_lane_error_c;
END IF;
END IF;
end process;
end generate;
cumlative_dq_lane_error_r <= cumlative_dq_lane_error_reg;
dq_error_bytelane_cmp <= dq_lane_error_r1;
data_error_o <= data_error;
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: read_data_path.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This is top level of read path and also consist of comparison logic
-- for read data.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
entity read_data_path is
generic (
TCQ : time := 100 ps;
FAMILY : string := "VIRTEX6";
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : integer := 32;
CMP_DATA_PIPE_STAGES : integer := 3;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
DQ_ERROR_WIDTH : integer := 1;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
MEM_COL_WIDTH : integer := 10
);
port (
clk_i : in std_logic;
manual_clear_error : in std_logic;
rst_i : in std_logic_vector(9 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
cmd_sent : in std_logic_vector(2 downto 0);
bl_sent : in std_logic_vector(5 downto 0);
cmd_en_i : in std_logic;
-- m_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(31 downto 0);
bl_i : in std_logic_vector(5 downto 0);
-- input [5:0] port_data_counts_i,// connect to data port fifo counts
data_rdy_o : out std_logic;
data_valid_i : in std_logic;
data_i : in std_logic_vector(DWIDTH - 1 downto 0);
last_word_rd_o : out std_logic;
data_error_o : out std_logic;
cmp_data_o : out std_logic_vector(DWIDTH - 1 downto 0);
rd_mdata_o : out std_logic_vector(DWIDTH - 1 downto 0);
cmp_data_valid : out std_logic;
cmp_addr_o : out std_logic_vector(31 downto 0);
cmp_bl_o : out std_logic_vector(5 downto 0);
force_wrcmd_gen_o : out std_logic;
rd_buff_avail_o : out std_logic_vector(6 downto 0);
dq_error_bytelane_cmp : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
cumlative_dq_lane_error_r : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0)
);
end entity read_data_path;
architecture trans of read_data_path is
function REDUCTION_OR( A: in std_logic_vector) return std_logic is
variable tmp : std_logic := '0';
begin
for i in A'range loop
tmp := tmp or A(i);
end loop;
return tmp;
end function REDUCTION_OR;
COMPONENT read_posted_fifo IS
GENERIC (
TCQ : time := 100 ps;
MEM_BURST_LEN : integer := 4;
FAMILY : STRING := "SPARTAN6";
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
data_valid_i : IN STD_LOGIC;
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
user_bl_cnt_is_1 : IN STD_LOGIC;
cmd_sent : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
bl_sent : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
cmd_en_i : IN STD_LOGIC;
gen_rdy_i : IN STD_LOGIC;
gen_valid_o : OUT STD_LOGIC;
gen_addr_o : OUT STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
gen_bl_o : OUT STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
rd_buff_avail_o : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
rd_mdata_fifo_empty : IN STD_LOGIC;
rd_mdata_en : OUT STD_LOGIC
);
END COMPONENT;
component rd_data_gen is
generic (
FAMILY : string := "SPARTAN6";
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : integer := 32;
BL_WIDTH : integer := 6;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_PRBS";
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3;
COLUMN_WIDTH : integer := 10
);
port (
clk_i : in std_logic;
rst_i : in std_logic_vector(4 downto 0);
prbs_fseed_i : in std_logic_vector(31 downto 0);
rd_mdata_en : in std_logic;
data_mode_i : in std_logic_vector(3 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
last_word_o : out std_logic;
-- m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
bl_i : in std_logic_vector(BL_WIDTH - 1 downto 0);
user_bl_cnt_is_1_o : out std_logic;
data_rdy_i : in std_logic;
data_valid_o : out std_logic;
data_o : out std_logic_vector(DWIDTH - 1 downto 0)
);
end component;
component afifo IS
GENERIC (
DSIZE : INTEGER := 32;
FIFO_DEPTH : INTEGER := 16;
ASIZE : INTEGER := 5;
SYNC : INTEGER := 1
);
PORT (
wr_clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
wr_en : IN STD_LOGIC;
wr_data : IN STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
rd_en : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_data : OUT STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
almost_full : OUT STD_LOGIC;
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END component;
signal gen_rdy : std_logic;
signal gen_valid : std_logic;
signal gen_addr : std_logic_vector(31 downto 0);
signal gen_bl : std_logic_vector(5 downto 0);
signal cmp_rdy : std_logic;
signal cmp_valid : std_logic;
signal cmp_addr : std_logic_vector(31 downto 0);
signal cmp_bl : std_logic_vector(5 downto 0);
signal data_error : std_logic;
signal cmp_data : std_logic_vector(DWIDTH - 1 downto 0);
signal last_word_rd : std_logic;
signal bl_counter : std_logic_vector(5 downto 0);
signal cmd_rdy : std_logic;
signal user_bl_cnt_is_1 : std_logic;
signal data_rdy : std_logic;
signal delayed_data : std_logic_vector(DWIDTH downto 0);
-- signal cmp_data_piped : std_logic_vector(DWIDTH downto 0);
signal cmp_data_r : std_logic_vector(DWIDTH-1 downto 0);
signal rd_mdata_en : std_logic;
signal rd_data_r : std_logic_vector(DWIDTH - 1 downto 0);
signal force_wrcmd_gen : std_logic;
signal wait_bl_end : std_logic;
signal wait_bl_end_r1 : std_logic;
signal v6_data_cmp_valid : std_logic;
signal rd_v6_mdata : std_logic_vector(DWIDTH-1 downto 0);
signal cmpdata_r : std_logic_vector(DWIDTH-1 downto 0);
signal rd_mdata : std_logic_vector(DWIDTH-1 downto 0);
signal l_data_error : std_logic;
signal u_data_error : std_logic;
signal cmp_data_en : std_logic;
signal force_wrcmd_timeout_cnts : std_logic_vector(7 downto 0);
signal error_byte : std_logic_vector(NUM_DQ_PINS / 2 - 1 downto 0);
signal error_byte_r1 : std_logic_vector(NUM_DQ_PINS / 2 - 1 downto 0);
signal dq_lane_error : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal dq_lane_error_r1 : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal dq_lane_error_r2 : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cum_dq_lane_error_mask : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cumlative_dq_lane_error_reg : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cumlative_dq_lane_error_c : std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
signal rd_mdata_fifo_empty : std_logic;
signal data_valid_r : std_logic;
-- Declare intermediate signals for referenced outputs
-- SIGNAL xhdl2 : STD_LOGIC_VECTOR(DWIDTH DOWNTO 0);
-- SIGNAL tmp_sig : STD_LOGIC;
signal last_word_rd_o_xhdl0 : std_logic;
signal rd_buff_avail_o_xhdl1 : std_logic_vector(6 downto 0);
begin
-- Drive referenced outputs
last_word_rd_o <= last_word_rd_o_xhdl0;
rd_buff_avail_o <= rd_buff_avail_o_xhdl1;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
wait_bl_end_r1 <= wait_bl_end;
rd_data_r <= data_i;
end if;
end process;
force_wrcmd_gen_o <= force_wrcmd_gen;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
force_wrcmd_gen <= '0';
elsif ((wait_bl_end = '0' and wait_bl_end_r1 = '1') or force_wrcmd_timeout_cnts = "11111111") then
force_wrcmd_gen <= '0';
elsif ((cmd_valid_i = '1' and bl_i > "010000") or wait_bl_end = '1') then
force_wrcmd_gen <= '1';
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
force_wrcmd_timeout_cnts <= "00000000";
elsif (wait_bl_end = '0' and wait_bl_end_r1 = '1') then
force_wrcmd_timeout_cnts <= "00000000";
elsif (force_wrcmd_gen = '1') then
force_wrcmd_timeout_cnts <= force_wrcmd_timeout_cnts + "00000001";
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
wait_bl_end <= '0';
elsif (force_wrcmd_timeout_cnts = "11111111") then
wait_bl_end <= '0';
elsif ((gen_rdy and gen_valid) = '1' and gen_bl > "010000") then
wait_bl_end <= '1';
elsif ((wait_bl_end and user_bl_cnt_is_1) = '1') then
wait_bl_end <= '0';
end if;
end if;
end process;
cmd_rdy_o <= cmd_rdy;
read_postedfifo : read_posted_fifo
GENERIC MAP (
TCQ => TCQ,
FAMILY => FAMILY,
MEM_BURST_LEN => MEM_BURST_LEN,
ADDR_WIDTH => 32,
BL_WIDTH => 6
)
port map (
clk_i => clk_i,
rst_i => rst_i(0),
cmd_rdy_o => cmd_rdy,
cmd_valid_i => cmd_valid_i,
data_valid_i => data_rdy,
addr_i => addr_i,
bl_i => bl_i,
cmd_sent => cmd_sent,
bl_sent => bl_sent,
cmd_en_i => cmd_en_i,
user_bl_cnt_is_1 => user_bl_cnt_is_1,
gen_rdy_i => gen_rdy,
gen_valid_o => gen_valid,
gen_addr_o => gen_addr,
gen_bl_o => gen_bl,
rd_buff_avail_o => rd_buff_avail_o_xhdl1,
rd_mdata_fifo_empty => rd_mdata_fifo_empty,
rd_mdata_en => rd_mdata_en
);
rd_datagen : rd_data_gen
generic map (
FAMILY => FAMILY,
MEM_BURST_LEN => MEM_BURST_LEN,
NUM_DQ_PINS => NUM_DQ_PINS,
SEL_VICTIM_LINE => SEL_VICTIM_LINE,
DATA_PATTERN => DATA_PATTERN,
DWIDTH => DWIDTH,
COLUMN_WIDTH => MEM_COL_WIDTH
)
port map (
clk_i => clk_i,
rst_i => rst_i(4 downto 0),
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_rdy_o => gen_rdy,
cmd_valid_i => gen_valid,
last_word_o => last_word_rd_o_xhdl0,
-- m_addr_i => m_addr_i,
fixed_data_i => fixed_data_i,
addr_i => gen_addr,
bl_i => gen_bl,
user_bl_cnt_is_1_o => user_bl_cnt_is_1,
data_rdy_i => data_valid_i,
data_valid_o => cmp_valid,
data_o => cmp_data,
rd_mdata_en => rd_mdata_en
);
rd_mdata_fifo : afifo
GENERIC MAP (
DSIZE => DWIDTH,
FIFO_DEPTH => 32,
ASIZE => 5,
SYNC => 1
)
PORT MAP (
wr_clk => clk_i,
rst => rst_i(0),
wr_en => data_valid_i,
wr_data => data_i,
rd_en => rd_mdata_en,
rd_clk => clk_i,
rd_data => rd_v6_mdata,
full => open,
empty => rd_mdata_fifo_empty,
almost_full => open
);
-- tmp_sig <= cmp_valid AND data_valid_i;
-- xhdl2 <= ( tmp_sig & cmp_data);
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
-- delayed_data <= (tmp_sig & cmp_data);
cmp_data_r <= cmp_data;
end if;
end process;
rd_mdata_o <= rd_mdata;
rd_mdata <= rd_data_r WHEN (FAMILY = "SPARTAN6") ELSE rd_v6_mdata
WHEN ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) ELSE data_i;
cmp_data_valid <= cmp_data_en WHEN (FAMILY = "SPARTAN6") ELSE v6_data_cmp_valid
WHEN ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) ELSE data_valid_i;
cmp_data_o <= cmp_data_r;
cmp_addr_o <= gen_addr;
cmp_bl_o <= gen_bl;
-- xhdl4 : if (FAMILY = "SPARTAN6") generate
-- rd_data_o <= rd_data_r;
-- end generate;
-- xhdl5 : if (FAMILY /= "SPARTAN6") generate
-- rd_data_o <= data_i;
-- end generate;
data_rdy_o <= data_rdy;
data_rdy <= cmp_valid and data_valid_i;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
v6_data_cmp_valid <= rd_mdata_en;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
cmp_data_en <= data_rdy;
end if;
end process;
xhdl6 : if (FAMILY = "SPARTAN6") generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (cmp_data_en = '1') then
IF ((rd_data_r(DWIDTH / 2 - 1 downto 0) /= cmp_data_r(DWIDTH / 2 - 1 downto 0))) then
l_data_error <= '1' ;
ELSE
l_data_error <= '0' ;
END IF;
else
l_data_error <= '0' ;
end if;
if (cmp_data_en = '1') then
IF ((rd_data_r(DWIDTH - 1 downto DWIDTH / 2) /= cmp_data_r(DWIDTH - 1 downto DWIDTH / 2))) then
u_data_error <= '1' ;
ELSE
u_data_error <= '0' ;
END IF;
else
u_data_error <= '0' ;
end if;
data_error <= l_data_error or u_data_error;
--synthesis translate_off
if (data_error = '1') then
report ("DATA ERROR");
end if;
--synthesis translate_on
end if;
end process;
end generate;
gen_error_2 : if ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) generate
gen_cmp : FOR i IN 0 TO NUM_DQ_PINS / 2 - 1 GENERATE
error_byte(i) <= '1' WHEN (rd_mdata_fifo_empty = '0' AND rd_mdata_en = '1' AND (rd_v6_mdata(8 * (i + 1) - 1 DOWNTO 8 * i) /= cmp_data(8 * (i + 1) - 1 DOWNTO 8 * i))) ELSE '0';
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
error_byte_r1 <= (others => '0');
data_error <= '0';
ELSE
error_byte_r1 <= error_byte;
-- FOR i IN 0 TO DWIDTH - 1 LOOP
data_error <= REDUCTION_OR(error_byte_r1);--error_byte_r1(i) OR data_error;
-- END LOOP;
END IF;
end if;
end process;
process (data_error)
begin
--synthesis translate_off
IF (data_error = '1') THEN
report "DATA ERROR"; -- severity ERROR;
END IF;
--synthesis translate_on
end process;
gen_dq_error_map: FOR i IN 0 to DQ_ERROR_WIDTH - 1 generate
dq_lane_error(i) <= (error_byte_r1(i) OR error_byte_r1(i+DQ_ERROR_WIDTH) OR
error_byte_r1(i+ (NUM_DQ_PINS*2/8)) OR
error_byte_r1(i+ (NUM_DQ_PINS*3/8)));
cumlative_dq_lane_error_c(i) <= cumlative_dq_lane_error_reg(i) OR dq_lane_error_r1(i);
end generate;
process (clk_i)
begin
IF (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
dq_lane_error_r1 <= (others => '0');
dq_lane_error_r2 <= (others => '0');
data_valid_r <= '0';
cumlative_dq_lane_error_reg <= (others => '0');
ELSE
data_valid_r <= data_valid_i;
dq_lane_error_r1 <= dq_lane_error;
cumlative_dq_lane_error_reg <= cumlative_dq_lane_error_c;
END IF;
END IF;
end process;
end generate;
xhdl8 : if ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 8)) generate
gen_cmp_8 : FOR i IN 0 TO NUM_DQ_PINS / 2 - 1 GENERATE
error_byte(i) <= '1' WHEN (data_valid_i = '1' AND (data_i(8 * (i + 1) - 1 DOWNTO 8 * i) /= cmp_data(8 * (i + 1) - 1 DOWNTO 8 * i))) ELSE '0';
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
error_byte_r1 <= (others => '0');
data_error <= '0';
ELSE
error_byte_r1 <= error_byte;
--FOR i IN 0 TO DWIDTH - 1 LOOP
-- data_error <= error_byte_r1(i) OR data_error;
--END LOOP;
data_error <= REDUCTION_OR(error_byte_r1);--error_byte_r1(i) OR data_error;
--synthesis translate_off
IF (data_error = '1') THEN
report "DATA ERROR"; -- severity ERROR;
end if;
--synthesis translate_on
END IF;
end if;
end process;
gen_dq_error_map: FOR i IN 0 to DQ_ERROR_WIDTH - 1 generate
dq_lane_error(i) <= (error_byte_r1(i) OR error_byte_r1(i+DQ_ERROR_WIDTH) OR
error_byte_r1(i+ (NUM_DQ_PINS*2/8)) OR
error_byte_r1(i+ (NUM_DQ_PINS*3/8)));
cumlative_dq_lane_error_c(i) <= cumlative_dq_lane_error_reg(i) OR dq_lane_error_r1(i);
end generate;
process (clk_i)
begin
IF (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
dq_lane_error_r1 <= (others => '0');
dq_lane_error_r2 <= (others => '0');
data_valid_r <= '0';
cumlative_dq_lane_error_reg <= (others => '0');
ELSE
data_valid_r <= data_valid_i;
dq_lane_error_r1 <= dq_lane_error;
cumlative_dq_lane_error_reg <= cumlative_dq_lane_error_c;
END IF;
END IF;
end process;
end generate;
cumlative_dq_lane_error_r <= cumlative_dq_lane_error_reg;
dq_error_bytelane_cmp <= dq_lane_error_r1;
data_error_o <= data_error;
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: read_data_path.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This is top level of read path and also consist of comparison logic
-- for read data.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
entity read_data_path is
generic (
TCQ : time := 100 ps;
FAMILY : string := "VIRTEX6";
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : integer := 32;
CMP_DATA_PIPE_STAGES : integer := 3;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
DQ_ERROR_WIDTH : integer := 1;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
MEM_COL_WIDTH : integer := 10
);
port (
clk_i : in std_logic;
manual_clear_error : in std_logic;
rst_i : in std_logic_vector(9 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
cmd_sent : in std_logic_vector(2 downto 0);
bl_sent : in std_logic_vector(5 downto 0);
cmd_en_i : in std_logic;
-- m_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(31 downto 0);
bl_i : in std_logic_vector(5 downto 0);
-- input [5:0] port_data_counts_i,// connect to data port fifo counts
data_rdy_o : out std_logic;
data_valid_i : in std_logic;
data_i : in std_logic_vector(DWIDTH - 1 downto 0);
last_word_rd_o : out std_logic;
data_error_o : out std_logic;
cmp_data_o : out std_logic_vector(DWIDTH - 1 downto 0);
rd_mdata_o : out std_logic_vector(DWIDTH - 1 downto 0);
cmp_data_valid : out std_logic;
cmp_addr_o : out std_logic_vector(31 downto 0);
cmp_bl_o : out std_logic_vector(5 downto 0);
force_wrcmd_gen_o : out std_logic;
rd_buff_avail_o : out std_logic_vector(6 downto 0);
dq_error_bytelane_cmp : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
cumlative_dq_lane_error_r : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0)
);
end entity read_data_path;
architecture trans of read_data_path is
function REDUCTION_OR( A: in std_logic_vector) return std_logic is
variable tmp : std_logic := '0';
begin
for i in A'range loop
tmp := tmp or A(i);
end loop;
return tmp;
end function REDUCTION_OR;
COMPONENT read_posted_fifo IS
GENERIC (
TCQ : time := 100 ps;
MEM_BURST_LEN : integer := 4;
FAMILY : STRING := "SPARTAN6";
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
data_valid_i : IN STD_LOGIC;
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
user_bl_cnt_is_1 : IN STD_LOGIC;
cmd_sent : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
bl_sent : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
cmd_en_i : IN STD_LOGIC;
gen_rdy_i : IN STD_LOGIC;
gen_valid_o : OUT STD_LOGIC;
gen_addr_o : OUT STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
gen_bl_o : OUT STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
rd_buff_avail_o : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
rd_mdata_fifo_empty : IN STD_LOGIC;
rd_mdata_en : OUT STD_LOGIC
);
END COMPONENT;
component rd_data_gen is
generic (
FAMILY : string := "SPARTAN6";
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : integer := 32;
BL_WIDTH : integer := 6;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_PRBS";
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3;
COLUMN_WIDTH : integer := 10
);
port (
clk_i : in std_logic;
rst_i : in std_logic_vector(4 downto 0);
prbs_fseed_i : in std_logic_vector(31 downto 0);
rd_mdata_en : in std_logic;
data_mode_i : in std_logic_vector(3 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
last_word_o : out std_logic;
-- m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
bl_i : in std_logic_vector(BL_WIDTH - 1 downto 0);
user_bl_cnt_is_1_o : out std_logic;
data_rdy_i : in std_logic;
data_valid_o : out std_logic;
data_o : out std_logic_vector(DWIDTH - 1 downto 0)
);
end component;
component afifo IS
GENERIC (
DSIZE : INTEGER := 32;
FIFO_DEPTH : INTEGER := 16;
ASIZE : INTEGER := 5;
SYNC : INTEGER := 1
);
PORT (
wr_clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
wr_en : IN STD_LOGIC;
wr_data : IN STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
rd_en : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_data : OUT STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
almost_full : OUT STD_LOGIC;
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END component;
signal gen_rdy : std_logic;
signal gen_valid : std_logic;
signal gen_addr : std_logic_vector(31 downto 0);
signal gen_bl : std_logic_vector(5 downto 0);
signal cmp_rdy : std_logic;
signal cmp_valid : std_logic;
signal cmp_addr : std_logic_vector(31 downto 0);
signal cmp_bl : std_logic_vector(5 downto 0);
signal data_error : std_logic;
signal cmp_data : std_logic_vector(DWIDTH - 1 downto 0);
signal last_word_rd : std_logic;
signal bl_counter : std_logic_vector(5 downto 0);
signal cmd_rdy : std_logic;
signal user_bl_cnt_is_1 : std_logic;
signal data_rdy : std_logic;
signal delayed_data : std_logic_vector(DWIDTH downto 0);
-- signal cmp_data_piped : std_logic_vector(DWIDTH downto 0);
signal cmp_data_r : std_logic_vector(DWIDTH-1 downto 0);
signal rd_mdata_en : std_logic;
signal rd_data_r : std_logic_vector(DWIDTH - 1 downto 0);
signal force_wrcmd_gen : std_logic;
signal wait_bl_end : std_logic;
signal wait_bl_end_r1 : std_logic;
signal v6_data_cmp_valid : std_logic;
signal rd_v6_mdata : std_logic_vector(DWIDTH-1 downto 0);
signal cmpdata_r : std_logic_vector(DWIDTH-1 downto 0);
signal rd_mdata : std_logic_vector(DWIDTH-1 downto 0);
signal l_data_error : std_logic;
signal u_data_error : std_logic;
signal cmp_data_en : std_logic;
signal force_wrcmd_timeout_cnts : std_logic_vector(7 downto 0);
signal error_byte : std_logic_vector(NUM_DQ_PINS / 2 - 1 downto 0);
signal error_byte_r1 : std_logic_vector(NUM_DQ_PINS / 2 - 1 downto 0);
signal dq_lane_error : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal dq_lane_error_r1 : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal dq_lane_error_r2 : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cum_dq_lane_error_mask : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cumlative_dq_lane_error_reg : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cumlative_dq_lane_error_c : std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
signal rd_mdata_fifo_empty : std_logic;
signal data_valid_r : std_logic;
-- Declare intermediate signals for referenced outputs
-- SIGNAL xhdl2 : STD_LOGIC_VECTOR(DWIDTH DOWNTO 0);
-- SIGNAL tmp_sig : STD_LOGIC;
signal last_word_rd_o_xhdl0 : std_logic;
signal rd_buff_avail_o_xhdl1 : std_logic_vector(6 downto 0);
begin
-- Drive referenced outputs
last_word_rd_o <= last_word_rd_o_xhdl0;
rd_buff_avail_o <= rd_buff_avail_o_xhdl1;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
wait_bl_end_r1 <= wait_bl_end;
rd_data_r <= data_i;
end if;
end process;
force_wrcmd_gen_o <= force_wrcmd_gen;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
force_wrcmd_gen <= '0';
elsif ((wait_bl_end = '0' and wait_bl_end_r1 = '1') or force_wrcmd_timeout_cnts = "11111111") then
force_wrcmd_gen <= '0';
elsif ((cmd_valid_i = '1' and bl_i > "010000") or wait_bl_end = '1') then
force_wrcmd_gen <= '1';
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
force_wrcmd_timeout_cnts <= "00000000";
elsif (wait_bl_end = '0' and wait_bl_end_r1 = '1') then
force_wrcmd_timeout_cnts <= "00000000";
elsif (force_wrcmd_gen = '1') then
force_wrcmd_timeout_cnts <= force_wrcmd_timeout_cnts + "00000001";
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
wait_bl_end <= '0';
elsif (force_wrcmd_timeout_cnts = "11111111") then
wait_bl_end <= '0';
elsif ((gen_rdy and gen_valid) = '1' and gen_bl > "010000") then
wait_bl_end <= '1';
elsif ((wait_bl_end and user_bl_cnt_is_1) = '1') then
wait_bl_end <= '0';
end if;
end if;
end process;
cmd_rdy_o <= cmd_rdy;
read_postedfifo : read_posted_fifo
GENERIC MAP (
TCQ => TCQ,
FAMILY => FAMILY,
MEM_BURST_LEN => MEM_BURST_LEN,
ADDR_WIDTH => 32,
BL_WIDTH => 6
)
port map (
clk_i => clk_i,
rst_i => rst_i(0),
cmd_rdy_o => cmd_rdy,
cmd_valid_i => cmd_valid_i,
data_valid_i => data_rdy,
addr_i => addr_i,
bl_i => bl_i,
cmd_sent => cmd_sent,
bl_sent => bl_sent,
cmd_en_i => cmd_en_i,
user_bl_cnt_is_1 => user_bl_cnt_is_1,
gen_rdy_i => gen_rdy,
gen_valid_o => gen_valid,
gen_addr_o => gen_addr,
gen_bl_o => gen_bl,
rd_buff_avail_o => rd_buff_avail_o_xhdl1,
rd_mdata_fifo_empty => rd_mdata_fifo_empty,
rd_mdata_en => rd_mdata_en
);
rd_datagen : rd_data_gen
generic map (
FAMILY => FAMILY,
MEM_BURST_LEN => MEM_BURST_LEN,
NUM_DQ_PINS => NUM_DQ_PINS,
SEL_VICTIM_LINE => SEL_VICTIM_LINE,
DATA_PATTERN => DATA_PATTERN,
DWIDTH => DWIDTH,
COLUMN_WIDTH => MEM_COL_WIDTH
)
port map (
clk_i => clk_i,
rst_i => rst_i(4 downto 0),
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_rdy_o => gen_rdy,
cmd_valid_i => gen_valid,
last_word_o => last_word_rd_o_xhdl0,
-- m_addr_i => m_addr_i,
fixed_data_i => fixed_data_i,
addr_i => gen_addr,
bl_i => gen_bl,
user_bl_cnt_is_1_o => user_bl_cnt_is_1,
data_rdy_i => data_valid_i,
data_valid_o => cmp_valid,
data_o => cmp_data,
rd_mdata_en => rd_mdata_en
);
rd_mdata_fifo : afifo
GENERIC MAP (
DSIZE => DWIDTH,
FIFO_DEPTH => 32,
ASIZE => 5,
SYNC => 1
)
PORT MAP (
wr_clk => clk_i,
rst => rst_i(0),
wr_en => data_valid_i,
wr_data => data_i,
rd_en => rd_mdata_en,
rd_clk => clk_i,
rd_data => rd_v6_mdata,
full => open,
empty => rd_mdata_fifo_empty,
almost_full => open
);
-- tmp_sig <= cmp_valid AND data_valid_i;
-- xhdl2 <= ( tmp_sig & cmp_data);
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
-- delayed_data <= (tmp_sig & cmp_data);
cmp_data_r <= cmp_data;
end if;
end process;
rd_mdata_o <= rd_mdata;
rd_mdata <= rd_data_r WHEN (FAMILY = "SPARTAN6") ELSE rd_v6_mdata
WHEN ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) ELSE data_i;
cmp_data_valid <= cmp_data_en WHEN (FAMILY = "SPARTAN6") ELSE v6_data_cmp_valid
WHEN ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) ELSE data_valid_i;
cmp_data_o <= cmp_data_r;
cmp_addr_o <= gen_addr;
cmp_bl_o <= gen_bl;
-- xhdl4 : if (FAMILY = "SPARTAN6") generate
-- rd_data_o <= rd_data_r;
-- end generate;
-- xhdl5 : if (FAMILY /= "SPARTAN6") generate
-- rd_data_o <= data_i;
-- end generate;
data_rdy_o <= data_rdy;
data_rdy <= cmp_valid and data_valid_i;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
v6_data_cmp_valid <= rd_mdata_en;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
cmp_data_en <= data_rdy;
end if;
end process;
xhdl6 : if (FAMILY = "SPARTAN6") generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (cmp_data_en = '1') then
IF ((rd_data_r(DWIDTH / 2 - 1 downto 0) /= cmp_data_r(DWIDTH / 2 - 1 downto 0))) then
l_data_error <= '1' ;
ELSE
l_data_error <= '0' ;
END IF;
else
l_data_error <= '0' ;
end if;
if (cmp_data_en = '1') then
IF ((rd_data_r(DWIDTH - 1 downto DWIDTH / 2) /= cmp_data_r(DWIDTH - 1 downto DWIDTH / 2))) then
u_data_error <= '1' ;
ELSE
u_data_error <= '0' ;
END IF;
else
u_data_error <= '0' ;
end if;
data_error <= l_data_error or u_data_error;
--synthesis translate_off
if (data_error = '1') then
report ("DATA ERROR");
end if;
--synthesis translate_on
end if;
end process;
end generate;
gen_error_2 : if ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) generate
gen_cmp : FOR i IN 0 TO NUM_DQ_PINS / 2 - 1 GENERATE
error_byte(i) <= '1' WHEN (rd_mdata_fifo_empty = '0' AND rd_mdata_en = '1' AND (rd_v6_mdata(8 * (i + 1) - 1 DOWNTO 8 * i) /= cmp_data(8 * (i + 1) - 1 DOWNTO 8 * i))) ELSE '0';
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
error_byte_r1 <= (others => '0');
data_error <= '0';
ELSE
error_byte_r1 <= error_byte;
-- FOR i IN 0 TO DWIDTH - 1 LOOP
data_error <= REDUCTION_OR(error_byte_r1);--error_byte_r1(i) OR data_error;
-- END LOOP;
END IF;
end if;
end process;
process (data_error)
begin
--synthesis translate_off
IF (data_error = '1') THEN
report "DATA ERROR"; -- severity ERROR;
END IF;
--synthesis translate_on
end process;
gen_dq_error_map: FOR i IN 0 to DQ_ERROR_WIDTH - 1 generate
dq_lane_error(i) <= (error_byte_r1(i) OR error_byte_r1(i+DQ_ERROR_WIDTH) OR
error_byte_r1(i+ (NUM_DQ_PINS*2/8)) OR
error_byte_r1(i+ (NUM_DQ_PINS*3/8)));
cumlative_dq_lane_error_c(i) <= cumlative_dq_lane_error_reg(i) OR dq_lane_error_r1(i);
end generate;
process (clk_i)
begin
IF (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
dq_lane_error_r1 <= (others => '0');
dq_lane_error_r2 <= (others => '0');
data_valid_r <= '0';
cumlative_dq_lane_error_reg <= (others => '0');
ELSE
data_valid_r <= data_valid_i;
dq_lane_error_r1 <= dq_lane_error;
cumlative_dq_lane_error_reg <= cumlative_dq_lane_error_c;
END IF;
END IF;
end process;
end generate;
xhdl8 : if ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 8)) generate
gen_cmp_8 : FOR i IN 0 TO NUM_DQ_PINS / 2 - 1 GENERATE
error_byte(i) <= '1' WHEN (data_valid_i = '1' AND (data_i(8 * (i + 1) - 1 DOWNTO 8 * i) /= cmp_data(8 * (i + 1) - 1 DOWNTO 8 * i))) ELSE '0';
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
error_byte_r1 <= (others => '0');
data_error <= '0';
ELSE
error_byte_r1 <= error_byte;
--FOR i IN 0 TO DWIDTH - 1 LOOP
-- data_error <= error_byte_r1(i) OR data_error;
--END LOOP;
data_error <= REDUCTION_OR(error_byte_r1);--error_byte_r1(i) OR data_error;
--synthesis translate_off
IF (data_error = '1') THEN
report "DATA ERROR"; -- severity ERROR;
end if;
--synthesis translate_on
END IF;
end if;
end process;
gen_dq_error_map: FOR i IN 0 to DQ_ERROR_WIDTH - 1 generate
dq_lane_error(i) <= (error_byte_r1(i) OR error_byte_r1(i+DQ_ERROR_WIDTH) OR
error_byte_r1(i+ (NUM_DQ_PINS*2/8)) OR
error_byte_r1(i+ (NUM_DQ_PINS*3/8)));
cumlative_dq_lane_error_c(i) <= cumlative_dq_lane_error_reg(i) OR dq_lane_error_r1(i);
end generate;
process (clk_i)
begin
IF (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
dq_lane_error_r1 <= (others => '0');
dq_lane_error_r2 <= (others => '0');
data_valid_r <= '0';
cumlative_dq_lane_error_reg <= (others => '0');
ELSE
data_valid_r <= data_valid_i;
dq_lane_error_r1 <= dq_lane_error;
cumlative_dq_lane_error_reg <= cumlative_dq_lane_error_c;
END IF;
END IF;
end process;
end generate;
cumlative_dq_lane_error_r <= cumlative_dq_lane_error_reg;
dq_error_bytelane_cmp <= dq_lane_error_r1;
data_error_o <= data_error;
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: read_data_path.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This is top level of read path and also consist of comparison logic
-- for read data.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
entity read_data_path is
generic (
TCQ : time := 100 ps;
FAMILY : string := "VIRTEX6";
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : integer := 32;
CMP_DATA_PIPE_STAGES : integer := 3;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
DQ_ERROR_WIDTH : integer := 1;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
MEM_COL_WIDTH : integer := 10
);
port (
clk_i : in std_logic;
manual_clear_error : in std_logic;
rst_i : in std_logic_vector(9 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
cmd_sent : in std_logic_vector(2 downto 0);
bl_sent : in std_logic_vector(5 downto 0);
cmd_en_i : in std_logic;
-- m_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(31 downto 0);
bl_i : in std_logic_vector(5 downto 0);
-- input [5:0] port_data_counts_i,// connect to data port fifo counts
data_rdy_o : out std_logic;
data_valid_i : in std_logic;
data_i : in std_logic_vector(DWIDTH - 1 downto 0);
last_word_rd_o : out std_logic;
data_error_o : out std_logic;
cmp_data_o : out std_logic_vector(DWIDTH - 1 downto 0);
rd_mdata_o : out std_logic_vector(DWIDTH - 1 downto 0);
cmp_data_valid : out std_logic;
cmp_addr_o : out std_logic_vector(31 downto 0);
cmp_bl_o : out std_logic_vector(5 downto 0);
force_wrcmd_gen_o : out std_logic;
rd_buff_avail_o : out std_logic_vector(6 downto 0);
dq_error_bytelane_cmp : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
cumlative_dq_lane_error_r : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0)
);
end entity read_data_path;
architecture trans of read_data_path is
function REDUCTION_OR( A: in std_logic_vector) return std_logic is
variable tmp : std_logic := '0';
begin
for i in A'range loop
tmp := tmp or A(i);
end loop;
return tmp;
end function REDUCTION_OR;
COMPONENT read_posted_fifo IS
GENERIC (
TCQ : time := 100 ps;
MEM_BURST_LEN : integer := 4;
FAMILY : STRING := "SPARTAN6";
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
data_valid_i : IN STD_LOGIC;
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
user_bl_cnt_is_1 : IN STD_LOGIC;
cmd_sent : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
bl_sent : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
cmd_en_i : IN STD_LOGIC;
gen_rdy_i : IN STD_LOGIC;
gen_valid_o : OUT STD_LOGIC;
gen_addr_o : OUT STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
gen_bl_o : OUT STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
rd_buff_avail_o : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
rd_mdata_fifo_empty : IN STD_LOGIC;
rd_mdata_en : OUT STD_LOGIC
);
END COMPONENT;
component rd_data_gen is
generic (
FAMILY : string := "SPARTAN6";
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : integer := 32;
BL_WIDTH : integer := 6;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_PRBS";
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3;
COLUMN_WIDTH : integer := 10
);
port (
clk_i : in std_logic;
rst_i : in std_logic_vector(4 downto 0);
prbs_fseed_i : in std_logic_vector(31 downto 0);
rd_mdata_en : in std_logic;
data_mode_i : in std_logic_vector(3 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
last_word_o : out std_logic;
-- m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
bl_i : in std_logic_vector(BL_WIDTH - 1 downto 0);
user_bl_cnt_is_1_o : out std_logic;
data_rdy_i : in std_logic;
data_valid_o : out std_logic;
data_o : out std_logic_vector(DWIDTH - 1 downto 0)
);
end component;
component afifo IS
GENERIC (
DSIZE : INTEGER := 32;
FIFO_DEPTH : INTEGER := 16;
ASIZE : INTEGER := 5;
SYNC : INTEGER := 1
);
PORT (
wr_clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
wr_en : IN STD_LOGIC;
wr_data : IN STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
rd_en : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_data : OUT STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
almost_full : OUT STD_LOGIC;
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END component;
signal gen_rdy : std_logic;
signal gen_valid : std_logic;
signal gen_addr : std_logic_vector(31 downto 0);
signal gen_bl : std_logic_vector(5 downto 0);
signal cmp_rdy : std_logic;
signal cmp_valid : std_logic;
signal cmp_addr : std_logic_vector(31 downto 0);
signal cmp_bl : std_logic_vector(5 downto 0);
signal data_error : std_logic;
signal cmp_data : std_logic_vector(DWIDTH - 1 downto 0);
signal last_word_rd : std_logic;
signal bl_counter : std_logic_vector(5 downto 0);
signal cmd_rdy : std_logic;
signal user_bl_cnt_is_1 : std_logic;
signal data_rdy : std_logic;
signal delayed_data : std_logic_vector(DWIDTH downto 0);
-- signal cmp_data_piped : std_logic_vector(DWIDTH downto 0);
signal cmp_data_r : std_logic_vector(DWIDTH-1 downto 0);
signal rd_mdata_en : std_logic;
signal rd_data_r : std_logic_vector(DWIDTH - 1 downto 0);
signal force_wrcmd_gen : std_logic;
signal wait_bl_end : std_logic;
signal wait_bl_end_r1 : std_logic;
signal v6_data_cmp_valid : std_logic;
signal rd_v6_mdata : std_logic_vector(DWIDTH-1 downto 0);
signal cmpdata_r : std_logic_vector(DWIDTH-1 downto 0);
signal rd_mdata : std_logic_vector(DWIDTH-1 downto 0);
signal l_data_error : std_logic;
signal u_data_error : std_logic;
signal cmp_data_en : std_logic;
signal force_wrcmd_timeout_cnts : std_logic_vector(7 downto 0);
signal error_byte : std_logic_vector(NUM_DQ_PINS / 2 - 1 downto 0);
signal error_byte_r1 : std_logic_vector(NUM_DQ_PINS / 2 - 1 downto 0);
signal dq_lane_error : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal dq_lane_error_r1 : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal dq_lane_error_r2 : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cum_dq_lane_error_mask : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cumlative_dq_lane_error_reg : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cumlative_dq_lane_error_c : std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
signal rd_mdata_fifo_empty : std_logic;
signal data_valid_r : std_logic;
-- Declare intermediate signals for referenced outputs
-- SIGNAL xhdl2 : STD_LOGIC_VECTOR(DWIDTH DOWNTO 0);
-- SIGNAL tmp_sig : STD_LOGIC;
signal last_word_rd_o_xhdl0 : std_logic;
signal rd_buff_avail_o_xhdl1 : std_logic_vector(6 downto 0);
begin
-- Drive referenced outputs
last_word_rd_o <= last_word_rd_o_xhdl0;
rd_buff_avail_o <= rd_buff_avail_o_xhdl1;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
wait_bl_end_r1 <= wait_bl_end;
rd_data_r <= data_i;
end if;
end process;
force_wrcmd_gen_o <= force_wrcmd_gen;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
force_wrcmd_gen <= '0';
elsif ((wait_bl_end = '0' and wait_bl_end_r1 = '1') or force_wrcmd_timeout_cnts = "11111111") then
force_wrcmd_gen <= '0';
elsif ((cmd_valid_i = '1' and bl_i > "010000") or wait_bl_end = '1') then
force_wrcmd_gen <= '1';
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
force_wrcmd_timeout_cnts <= "00000000";
elsif (wait_bl_end = '0' and wait_bl_end_r1 = '1') then
force_wrcmd_timeout_cnts <= "00000000";
elsif (force_wrcmd_gen = '1') then
force_wrcmd_timeout_cnts <= force_wrcmd_timeout_cnts + "00000001";
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
wait_bl_end <= '0';
elsif (force_wrcmd_timeout_cnts = "11111111") then
wait_bl_end <= '0';
elsif ((gen_rdy and gen_valid) = '1' and gen_bl > "010000") then
wait_bl_end <= '1';
elsif ((wait_bl_end and user_bl_cnt_is_1) = '1') then
wait_bl_end <= '0';
end if;
end if;
end process;
cmd_rdy_o <= cmd_rdy;
read_postedfifo : read_posted_fifo
GENERIC MAP (
TCQ => TCQ,
FAMILY => FAMILY,
MEM_BURST_LEN => MEM_BURST_LEN,
ADDR_WIDTH => 32,
BL_WIDTH => 6
)
port map (
clk_i => clk_i,
rst_i => rst_i(0),
cmd_rdy_o => cmd_rdy,
cmd_valid_i => cmd_valid_i,
data_valid_i => data_rdy,
addr_i => addr_i,
bl_i => bl_i,
cmd_sent => cmd_sent,
bl_sent => bl_sent,
cmd_en_i => cmd_en_i,
user_bl_cnt_is_1 => user_bl_cnt_is_1,
gen_rdy_i => gen_rdy,
gen_valid_o => gen_valid,
gen_addr_o => gen_addr,
gen_bl_o => gen_bl,
rd_buff_avail_o => rd_buff_avail_o_xhdl1,
rd_mdata_fifo_empty => rd_mdata_fifo_empty,
rd_mdata_en => rd_mdata_en
);
rd_datagen : rd_data_gen
generic map (
FAMILY => FAMILY,
MEM_BURST_LEN => MEM_BURST_LEN,
NUM_DQ_PINS => NUM_DQ_PINS,
SEL_VICTIM_LINE => SEL_VICTIM_LINE,
DATA_PATTERN => DATA_PATTERN,
DWIDTH => DWIDTH,
COLUMN_WIDTH => MEM_COL_WIDTH
)
port map (
clk_i => clk_i,
rst_i => rst_i(4 downto 0),
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_rdy_o => gen_rdy,
cmd_valid_i => gen_valid,
last_word_o => last_word_rd_o_xhdl0,
-- m_addr_i => m_addr_i,
fixed_data_i => fixed_data_i,
addr_i => gen_addr,
bl_i => gen_bl,
user_bl_cnt_is_1_o => user_bl_cnt_is_1,
data_rdy_i => data_valid_i,
data_valid_o => cmp_valid,
data_o => cmp_data,
rd_mdata_en => rd_mdata_en
);
rd_mdata_fifo : afifo
GENERIC MAP (
DSIZE => DWIDTH,
FIFO_DEPTH => 32,
ASIZE => 5,
SYNC => 1
)
PORT MAP (
wr_clk => clk_i,
rst => rst_i(0),
wr_en => data_valid_i,
wr_data => data_i,
rd_en => rd_mdata_en,
rd_clk => clk_i,
rd_data => rd_v6_mdata,
full => open,
empty => rd_mdata_fifo_empty,
almost_full => open
);
-- tmp_sig <= cmp_valid AND data_valid_i;
-- xhdl2 <= ( tmp_sig & cmp_data);
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
-- delayed_data <= (tmp_sig & cmp_data);
cmp_data_r <= cmp_data;
end if;
end process;
rd_mdata_o <= rd_mdata;
rd_mdata <= rd_data_r WHEN (FAMILY = "SPARTAN6") ELSE rd_v6_mdata
WHEN ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) ELSE data_i;
cmp_data_valid <= cmp_data_en WHEN (FAMILY = "SPARTAN6") ELSE v6_data_cmp_valid
WHEN ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) ELSE data_valid_i;
cmp_data_o <= cmp_data_r;
cmp_addr_o <= gen_addr;
cmp_bl_o <= gen_bl;
-- xhdl4 : if (FAMILY = "SPARTAN6") generate
-- rd_data_o <= rd_data_r;
-- end generate;
-- xhdl5 : if (FAMILY /= "SPARTAN6") generate
-- rd_data_o <= data_i;
-- end generate;
data_rdy_o <= data_rdy;
data_rdy <= cmp_valid and data_valid_i;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
v6_data_cmp_valid <= rd_mdata_en;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
cmp_data_en <= data_rdy;
end if;
end process;
xhdl6 : if (FAMILY = "SPARTAN6") generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (cmp_data_en = '1') then
IF ((rd_data_r(DWIDTH / 2 - 1 downto 0) /= cmp_data_r(DWIDTH / 2 - 1 downto 0))) then
l_data_error <= '1' ;
ELSE
l_data_error <= '0' ;
END IF;
else
l_data_error <= '0' ;
end if;
if (cmp_data_en = '1') then
IF ((rd_data_r(DWIDTH - 1 downto DWIDTH / 2) /= cmp_data_r(DWIDTH - 1 downto DWIDTH / 2))) then
u_data_error <= '1' ;
ELSE
u_data_error <= '0' ;
END IF;
else
u_data_error <= '0' ;
end if;
data_error <= l_data_error or u_data_error;
--synthesis translate_off
if (data_error = '1') then
report ("DATA ERROR");
end if;
--synthesis translate_on
end if;
end process;
end generate;
gen_error_2 : if ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) generate
gen_cmp : FOR i IN 0 TO NUM_DQ_PINS / 2 - 1 GENERATE
error_byte(i) <= '1' WHEN (rd_mdata_fifo_empty = '0' AND rd_mdata_en = '1' AND (rd_v6_mdata(8 * (i + 1) - 1 DOWNTO 8 * i) /= cmp_data(8 * (i + 1) - 1 DOWNTO 8 * i))) ELSE '0';
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
error_byte_r1 <= (others => '0');
data_error <= '0';
ELSE
error_byte_r1 <= error_byte;
-- FOR i IN 0 TO DWIDTH - 1 LOOP
data_error <= REDUCTION_OR(error_byte_r1);--error_byte_r1(i) OR data_error;
-- END LOOP;
END IF;
end if;
end process;
process (data_error)
begin
--synthesis translate_off
IF (data_error = '1') THEN
report "DATA ERROR"; -- severity ERROR;
END IF;
--synthesis translate_on
end process;
gen_dq_error_map: FOR i IN 0 to DQ_ERROR_WIDTH - 1 generate
dq_lane_error(i) <= (error_byte_r1(i) OR error_byte_r1(i+DQ_ERROR_WIDTH) OR
error_byte_r1(i+ (NUM_DQ_PINS*2/8)) OR
error_byte_r1(i+ (NUM_DQ_PINS*3/8)));
cumlative_dq_lane_error_c(i) <= cumlative_dq_lane_error_reg(i) OR dq_lane_error_r1(i);
end generate;
process (clk_i)
begin
IF (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
dq_lane_error_r1 <= (others => '0');
dq_lane_error_r2 <= (others => '0');
data_valid_r <= '0';
cumlative_dq_lane_error_reg <= (others => '0');
ELSE
data_valid_r <= data_valid_i;
dq_lane_error_r1 <= dq_lane_error;
cumlative_dq_lane_error_reg <= cumlative_dq_lane_error_c;
END IF;
END IF;
end process;
end generate;
xhdl8 : if ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 8)) generate
gen_cmp_8 : FOR i IN 0 TO NUM_DQ_PINS / 2 - 1 GENERATE
error_byte(i) <= '1' WHEN (data_valid_i = '1' AND (data_i(8 * (i + 1) - 1 DOWNTO 8 * i) /= cmp_data(8 * (i + 1) - 1 DOWNTO 8 * i))) ELSE '0';
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
error_byte_r1 <= (others => '0');
data_error <= '0';
ELSE
error_byte_r1 <= error_byte;
--FOR i IN 0 TO DWIDTH - 1 LOOP
-- data_error <= error_byte_r1(i) OR data_error;
--END LOOP;
data_error <= REDUCTION_OR(error_byte_r1);--error_byte_r1(i) OR data_error;
--synthesis translate_off
IF (data_error = '1') THEN
report "DATA ERROR"; -- severity ERROR;
end if;
--synthesis translate_on
END IF;
end if;
end process;
gen_dq_error_map: FOR i IN 0 to DQ_ERROR_WIDTH - 1 generate
dq_lane_error(i) <= (error_byte_r1(i) OR error_byte_r1(i+DQ_ERROR_WIDTH) OR
error_byte_r1(i+ (NUM_DQ_PINS*2/8)) OR
error_byte_r1(i+ (NUM_DQ_PINS*3/8)));
cumlative_dq_lane_error_c(i) <= cumlative_dq_lane_error_reg(i) OR dq_lane_error_r1(i);
end generate;
process (clk_i)
begin
IF (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
dq_lane_error_r1 <= (others => '0');
dq_lane_error_r2 <= (others => '0');
data_valid_r <= '0';
cumlative_dq_lane_error_reg <= (others => '0');
ELSE
data_valid_r <= data_valid_i;
dq_lane_error_r1 <= dq_lane_error;
cumlative_dq_lane_error_reg <= cumlative_dq_lane_error_c;
END IF;
END IF;
end process;
end generate;
cumlative_dq_lane_error_r <= cumlative_dq_lane_error_reg;
dq_error_bytelane_cmp <= dq_lane_error_r1;
data_error_o <= data_error;
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: read_data_path.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This is top level of read path and also consist of comparison logic
-- for read data.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
entity read_data_path is
generic (
TCQ : time := 100 ps;
FAMILY : string := "VIRTEX6";
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : integer := 32;
CMP_DATA_PIPE_STAGES : integer := 3;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
DQ_ERROR_WIDTH : integer := 1;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
MEM_COL_WIDTH : integer := 10
);
port (
clk_i : in std_logic;
manual_clear_error : in std_logic;
rst_i : in std_logic_vector(9 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
cmd_sent : in std_logic_vector(2 downto 0);
bl_sent : in std_logic_vector(5 downto 0);
cmd_en_i : in std_logic;
-- m_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(31 downto 0);
bl_i : in std_logic_vector(5 downto 0);
-- input [5:0] port_data_counts_i,// connect to data port fifo counts
data_rdy_o : out std_logic;
data_valid_i : in std_logic;
data_i : in std_logic_vector(DWIDTH - 1 downto 0);
last_word_rd_o : out std_logic;
data_error_o : out std_logic;
cmp_data_o : out std_logic_vector(DWIDTH - 1 downto 0);
rd_mdata_o : out std_logic_vector(DWIDTH - 1 downto 0);
cmp_data_valid : out std_logic;
cmp_addr_o : out std_logic_vector(31 downto 0);
cmp_bl_o : out std_logic_vector(5 downto 0);
force_wrcmd_gen_o : out std_logic;
rd_buff_avail_o : out std_logic_vector(6 downto 0);
dq_error_bytelane_cmp : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
cumlative_dq_lane_error_r : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0)
);
end entity read_data_path;
architecture trans of read_data_path is
function REDUCTION_OR( A: in std_logic_vector) return std_logic is
variable tmp : std_logic := '0';
begin
for i in A'range loop
tmp := tmp or A(i);
end loop;
return tmp;
end function REDUCTION_OR;
COMPONENT read_posted_fifo IS
GENERIC (
TCQ : time := 100 ps;
MEM_BURST_LEN : integer := 4;
FAMILY : STRING := "SPARTAN6";
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
data_valid_i : IN STD_LOGIC;
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
user_bl_cnt_is_1 : IN STD_LOGIC;
cmd_sent : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
bl_sent : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
cmd_en_i : IN STD_LOGIC;
gen_rdy_i : IN STD_LOGIC;
gen_valid_o : OUT STD_LOGIC;
gen_addr_o : OUT STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
gen_bl_o : OUT STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
rd_buff_avail_o : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
rd_mdata_fifo_empty : IN STD_LOGIC;
rd_mdata_en : OUT STD_LOGIC
);
END COMPONENT;
component rd_data_gen is
generic (
FAMILY : string := "SPARTAN6";
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : integer := 32;
BL_WIDTH : integer := 6;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_PRBS";
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3;
COLUMN_WIDTH : integer := 10
);
port (
clk_i : in std_logic;
rst_i : in std_logic_vector(4 downto 0);
prbs_fseed_i : in std_logic_vector(31 downto 0);
rd_mdata_en : in std_logic;
data_mode_i : in std_logic_vector(3 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
last_word_o : out std_logic;
-- m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
bl_i : in std_logic_vector(BL_WIDTH - 1 downto 0);
user_bl_cnt_is_1_o : out std_logic;
data_rdy_i : in std_logic;
data_valid_o : out std_logic;
data_o : out std_logic_vector(DWIDTH - 1 downto 0)
);
end component;
component afifo IS
GENERIC (
DSIZE : INTEGER := 32;
FIFO_DEPTH : INTEGER := 16;
ASIZE : INTEGER := 5;
SYNC : INTEGER := 1
);
PORT (
wr_clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
wr_en : IN STD_LOGIC;
wr_data : IN STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
rd_en : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_data : OUT STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
almost_full : OUT STD_LOGIC;
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END component;
signal gen_rdy : std_logic;
signal gen_valid : std_logic;
signal gen_addr : std_logic_vector(31 downto 0);
signal gen_bl : std_logic_vector(5 downto 0);
signal cmp_rdy : std_logic;
signal cmp_valid : std_logic;
signal cmp_addr : std_logic_vector(31 downto 0);
signal cmp_bl : std_logic_vector(5 downto 0);
signal data_error : std_logic;
signal cmp_data : std_logic_vector(DWIDTH - 1 downto 0);
signal last_word_rd : std_logic;
signal bl_counter : std_logic_vector(5 downto 0);
signal cmd_rdy : std_logic;
signal user_bl_cnt_is_1 : std_logic;
signal data_rdy : std_logic;
signal delayed_data : std_logic_vector(DWIDTH downto 0);
-- signal cmp_data_piped : std_logic_vector(DWIDTH downto 0);
signal cmp_data_r : std_logic_vector(DWIDTH-1 downto 0);
signal rd_mdata_en : std_logic;
signal rd_data_r : std_logic_vector(DWIDTH - 1 downto 0);
signal force_wrcmd_gen : std_logic;
signal wait_bl_end : std_logic;
signal wait_bl_end_r1 : std_logic;
signal v6_data_cmp_valid : std_logic;
signal rd_v6_mdata : std_logic_vector(DWIDTH-1 downto 0);
signal cmpdata_r : std_logic_vector(DWIDTH-1 downto 0);
signal rd_mdata : std_logic_vector(DWIDTH-1 downto 0);
signal l_data_error : std_logic;
signal u_data_error : std_logic;
signal cmp_data_en : std_logic;
signal force_wrcmd_timeout_cnts : std_logic_vector(7 downto 0);
signal error_byte : std_logic_vector(NUM_DQ_PINS / 2 - 1 downto 0);
signal error_byte_r1 : std_logic_vector(NUM_DQ_PINS / 2 - 1 downto 0);
signal dq_lane_error : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal dq_lane_error_r1 : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal dq_lane_error_r2 : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cum_dq_lane_error_mask : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cumlative_dq_lane_error_reg : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cumlative_dq_lane_error_c : std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
signal rd_mdata_fifo_empty : std_logic;
signal data_valid_r : std_logic;
-- Declare intermediate signals for referenced outputs
-- SIGNAL xhdl2 : STD_LOGIC_VECTOR(DWIDTH DOWNTO 0);
-- SIGNAL tmp_sig : STD_LOGIC;
signal last_word_rd_o_xhdl0 : std_logic;
signal rd_buff_avail_o_xhdl1 : std_logic_vector(6 downto 0);
begin
-- Drive referenced outputs
last_word_rd_o <= last_word_rd_o_xhdl0;
rd_buff_avail_o <= rd_buff_avail_o_xhdl1;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
wait_bl_end_r1 <= wait_bl_end;
rd_data_r <= data_i;
end if;
end process;
force_wrcmd_gen_o <= force_wrcmd_gen;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
force_wrcmd_gen <= '0';
elsif ((wait_bl_end = '0' and wait_bl_end_r1 = '1') or force_wrcmd_timeout_cnts = "11111111") then
force_wrcmd_gen <= '0';
elsif ((cmd_valid_i = '1' and bl_i > "010000") or wait_bl_end = '1') then
force_wrcmd_gen <= '1';
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
force_wrcmd_timeout_cnts <= "00000000";
elsif (wait_bl_end = '0' and wait_bl_end_r1 = '1') then
force_wrcmd_timeout_cnts <= "00000000";
elsif (force_wrcmd_gen = '1') then
force_wrcmd_timeout_cnts <= force_wrcmd_timeout_cnts + "00000001";
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
wait_bl_end <= '0';
elsif (force_wrcmd_timeout_cnts = "11111111") then
wait_bl_end <= '0';
elsif ((gen_rdy and gen_valid) = '1' and gen_bl > "010000") then
wait_bl_end <= '1';
elsif ((wait_bl_end and user_bl_cnt_is_1) = '1') then
wait_bl_end <= '0';
end if;
end if;
end process;
cmd_rdy_o <= cmd_rdy;
read_postedfifo : read_posted_fifo
GENERIC MAP (
TCQ => TCQ,
FAMILY => FAMILY,
MEM_BURST_LEN => MEM_BURST_LEN,
ADDR_WIDTH => 32,
BL_WIDTH => 6
)
port map (
clk_i => clk_i,
rst_i => rst_i(0),
cmd_rdy_o => cmd_rdy,
cmd_valid_i => cmd_valid_i,
data_valid_i => data_rdy,
addr_i => addr_i,
bl_i => bl_i,
cmd_sent => cmd_sent,
bl_sent => bl_sent,
cmd_en_i => cmd_en_i,
user_bl_cnt_is_1 => user_bl_cnt_is_1,
gen_rdy_i => gen_rdy,
gen_valid_o => gen_valid,
gen_addr_o => gen_addr,
gen_bl_o => gen_bl,
rd_buff_avail_o => rd_buff_avail_o_xhdl1,
rd_mdata_fifo_empty => rd_mdata_fifo_empty,
rd_mdata_en => rd_mdata_en
);
rd_datagen : rd_data_gen
generic map (
FAMILY => FAMILY,
MEM_BURST_LEN => MEM_BURST_LEN,
NUM_DQ_PINS => NUM_DQ_PINS,
SEL_VICTIM_LINE => SEL_VICTIM_LINE,
DATA_PATTERN => DATA_PATTERN,
DWIDTH => DWIDTH,
COLUMN_WIDTH => MEM_COL_WIDTH
)
port map (
clk_i => clk_i,
rst_i => rst_i(4 downto 0),
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_rdy_o => gen_rdy,
cmd_valid_i => gen_valid,
last_word_o => last_word_rd_o_xhdl0,
-- m_addr_i => m_addr_i,
fixed_data_i => fixed_data_i,
addr_i => gen_addr,
bl_i => gen_bl,
user_bl_cnt_is_1_o => user_bl_cnt_is_1,
data_rdy_i => data_valid_i,
data_valid_o => cmp_valid,
data_o => cmp_data,
rd_mdata_en => rd_mdata_en
);
rd_mdata_fifo : afifo
GENERIC MAP (
DSIZE => DWIDTH,
FIFO_DEPTH => 32,
ASIZE => 5,
SYNC => 1
)
PORT MAP (
wr_clk => clk_i,
rst => rst_i(0),
wr_en => data_valid_i,
wr_data => data_i,
rd_en => rd_mdata_en,
rd_clk => clk_i,
rd_data => rd_v6_mdata,
full => open,
empty => rd_mdata_fifo_empty,
almost_full => open
);
-- tmp_sig <= cmp_valid AND data_valid_i;
-- xhdl2 <= ( tmp_sig & cmp_data);
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
-- delayed_data <= (tmp_sig & cmp_data);
cmp_data_r <= cmp_data;
end if;
end process;
rd_mdata_o <= rd_mdata;
rd_mdata <= rd_data_r WHEN (FAMILY = "SPARTAN6") ELSE rd_v6_mdata
WHEN ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) ELSE data_i;
cmp_data_valid <= cmp_data_en WHEN (FAMILY = "SPARTAN6") ELSE v6_data_cmp_valid
WHEN ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) ELSE data_valid_i;
cmp_data_o <= cmp_data_r;
cmp_addr_o <= gen_addr;
cmp_bl_o <= gen_bl;
-- xhdl4 : if (FAMILY = "SPARTAN6") generate
-- rd_data_o <= rd_data_r;
-- end generate;
-- xhdl5 : if (FAMILY /= "SPARTAN6") generate
-- rd_data_o <= data_i;
-- end generate;
data_rdy_o <= data_rdy;
data_rdy <= cmp_valid and data_valid_i;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
v6_data_cmp_valid <= rd_mdata_en;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
cmp_data_en <= data_rdy;
end if;
end process;
xhdl6 : if (FAMILY = "SPARTAN6") generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (cmp_data_en = '1') then
IF ((rd_data_r(DWIDTH / 2 - 1 downto 0) /= cmp_data_r(DWIDTH / 2 - 1 downto 0))) then
l_data_error <= '1' ;
ELSE
l_data_error <= '0' ;
END IF;
else
l_data_error <= '0' ;
end if;
if (cmp_data_en = '1') then
IF ((rd_data_r(DWIDTH - 1 downto DWIDTH / 2) /= cmp_data_r(DWIDTH - 1 downto DWIDTH / 2))) then
u_data_error <= '1' ;
ELSE
u_data_error <= '0' ;
END IF;
else
u_data_error <= '0' ;
end if;
data_error <= l_data_error or u_data_error;
--synthesis translate_off
if (data_error = '1') then
report ("DATA ERROR");
end if;
--synthesis translate_on
end if;
end process;
end generate;
gen_error_2 : if ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) generate
gen_cmp : FOR i IN 0 TO NUM_DQ_PINS / 2 - 1 GENERATE
error_byte(i) <= '1' WHEN (rd_mdata_fifo_empty = '0' AND rd_mdata_en = '1' AND (rd_v6_mdata(8 * (i + 1) - 1 DOWNTO 8 * i) /= cmp_data(8 * (i + 1) - 1 DOWNTO 8 * i))) ELSE '0';
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
error_byte_r1 <= (others => '0');
data_error <= '0';
ELSE
error_byte_r1 <= error_byte;
-- FOR i IN 0 TO DWIDTH - 1 LOOP
data_error <= REDUCTION_OR(error_byte_r1);--error_byte_r1(i) OR data_error;
-- END LOOP;
END IF;
end if;
end process;
process (data_error)
begin
--synthesis translate_off
IF (data_error = '1') THEN
report "DATA ERROR"; -- severity ERROR;
END IF;
--synthesis translate_on
end process;
gen_dq_error_map: FOR i IN 0 to DQ_ERROR_WIDTH - 1 generate
dq_lane_error(i) <= (error_byte_r1(i) OR error_byte_r1(i+DQ_ERROR_WIDTH) OR
error_byte_r1(i+ (NUM_DQ_PINS*2/8)) OR
error_byte_r1(i+ (NUM_DQ_PINS*3/8)));
cumlative_dq_lane_error_c(i) <= cumlative_dq_lane_error_reg(i) OR dq_lane_error_r1(i);
end generate;
process (clk_i)
begin
IF (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
dq_lane_error_r1 <= (others => '0');
dq_lane_error_r2 <= (others => '0');
data_valid_r <= '0';
cumlative_dq_lane_error_reg <= (others => '0');
ELSE
data_valid_r <= data_valid_i;
dq_lane_error_r1 <= dq_lane_error;
cumlative_dq_lane_error_reg <= cumlative_dq_lane_error_c;
END IF;
END IF;
end process;
end generate;
xhdl8 : if ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 8)) generate
gen_cmp_8 : FOR i IN 0 TO NUM_DQ_PINS / 2 - 1 GENERATE
error_byte(i) <= '1' WHEN (data_valid_i = '1' AND (data_i(8 * (i + 1) - 1 DOWNTO 8 * i) /= cmp_data(8 * (i + 1) - 1 DOWNTO 8 * i))) ELSE '0';
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
error_byte_r1 <= (others => '0');
data_error <= '0';
ELSE
error_byte_r1 <= error_byte;
--FOR i IN 0 TO DWIDTH - 1 LOOP
-- data_error <= error_byte_r1(i) OR data_error;
--END LOOP;
data_error <= REDUCTION_OR(error_byte_r1);--error_byte_r1(i) OR data_error;
--synthesis translate_off
IF (data_error = '1') THEN
report "DATA ERROR"; -- severity ERROR;
end if;
--synthesis translate_on
END IF;
end if;
end process;
gen_dq_error_map: FOR i IN 0 to DQ_ERROR_WIDTH - 1 generate
dq_lane_error(i) <= (error_byte_r1(i) OR error_byte_r1(i+DQ_ERROR_WIDTH) OR
error_byte_r1(i+ (NUM_DQ_PINS*2/8)) OR
error_byte_r1(i+ (NUM_DQ_PINS*3/8)));
cumlative_dq_lane_error_c(i) <= cumlative_dq_lane_error_reg(i) OR dq_lane_error_r1(i);
end generate;
process (clk_i)
begin
IF (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
dq_lane_error_r1 <= (others => '0');
dq_lane_error_r2 <= (others => '0');
data_valid_r <= '0';
cumlative_dq_lane_error_reg <= (others => '0');
ELSE
data_valid_r <= data_valid_i;
dq_lane_error_r1 <= dq_lane_error;
cumlative_dq_lane_error_reg <= cumlative_dq_lane_error_c;
END IF;
END IF;
end process;
end generate;
cumlative_dq_lane_error_r <= cumlative_dq_lane_error_reg;
dq_error_bytelane_cmp <= dq_lane_error_r1;
data_error_o <= data_error;
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: read_data_path.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This is top level of read path and also consist of comparison logic
-- for read data.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
entity read_data_path is
generic (
TCQ : time := 100 ps;
FAMILY : string := "VIRTEX6";
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : integer := 32;
CMP_DATA_PIPE_STAGES : integer := 3;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
DQ_ERROR_WIDTH : integer := 1;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
MEM_COL_WIDTH : integer := 10
);
port (
clk_i : in std_logic;
manual_clear_error : in std_logic;
rst_i : in std_logic_vector(9 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
cmd_sent : in std_logic_vector(2 downto 0);
bl_sent : in std_logic_vector(5 downto 0);
cmd_en_i : in std_logic;
-- m_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(31 downto 0);
bl_i : in std_logic_vector(5 downto 0);
-- input [5:0] port_data_counts_i,// connect to data port fifo counts
data_rdy_o : out std_logic;
data_valid_i : in std_logic;
data_i : in std_logic_vector(DWIDTH - 1 downto 0);
last_word_rd_o : out std_logic;
data_error_o : out std_logic;
cmp_data_o : out std_logic_vector(DWIDTH - 1 downto 0);
rd_mdata_o : out std_logic_vector(DWIDTH - 1 downto 0);
cmp_data_valid : out std_logic;
cmp_addr_o : out std_logic_vector(31 downto 0);
cmp_bl_o : out std_logic_vector(5 downto 0);
force_wrcmd_gen_o : out std_logic;
rd_buff_avail_o : out std_logic_vector(6 downto 0);
dq_error_bytelane_cmp : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
cumlative_dq_lane_error_r : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0)
);
end entity read_data_path;
architecture trans of read_data_path is
function REDUCTION_OR( A: in std_logic_vector) return std_logic is
variable tmp : std_logic := '0';
begin
for i in A'range loop
tmp := tmp or A(i);
end loop;
return tmp;
end function REDUCTION_OR;
COMPONENT read_posted_fifo IS
GENERIC (
TCQ : time := 100 ps;
MEM_BURST_LEN : integer := 4;
FAMILY : STRING := "SPARTAN6";
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
data_valid_i : IN STD_LOGIC;
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
user_bl_cnt_is_1 : IN STD_LOGIC;
cmd_sent : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
bl_sent : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
cmd_en_i : IN STD_LOGIC;
gen_rdy_i : IN STD_LOGIC;
gen_valid_o : OUT STD_LOGIC;
gen_addr_o : OUT STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
gen_bl_o : OUT STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
rd_buff_avail_o : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
rd_mdata_fifo_empty : IN STD_LOGIC;
rd_mdata_en : OUT STD_LOGIC
);
END COMPONENT;
component rd_data_gen is
generic (
FAMILY : string := "SPARTAN6";
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : integer := 32;
BL_WIDTH : integer := 6;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_PRBS";
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3;
COLUMN_WIDTH : integer := 10
);
port (
clk_i : in std_logic;
rst_i : in std_logic_vector(4 downto 0);
prbs_fseed_i : in std_logic_vector(31 downto 0);
rd_mdata_en : in std_logic;
data_mode_i : in std_logic_vector(3 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
last_word_o : out std_logic;
-- m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
bl_i : in std_logic_vector(BL_WIDTH - 1 downto 0);
user_bl_cnt_is_1_o : out std_logic;
data_rdy_i : in std_logic;
data_valid_o : out std_logic;
data_o : out std_logic_vector(DWIDTH - 1 downto 0)
);
end component;
component afifo IS
GENERIC (
DSIZE : INTEGER := 32;
FIFO_DEPTH : INTEGER := 16;
ASIZE : INTEGER := 5;
SYNC : INTEGER := 1
);
PORT (
wr_clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
wr_en : IN STD_LOGIC;
wr_data : IN STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
rd_en : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_data : OUT STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
almost_full : OUT STD_LOGIC;
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END component;
signal gen_rdy : std_logic;
signal gen_valid : std_logic;
signal gen_addr : std_logic_vector(31 downto 0);
signal gen_bl : std_logic_vector(5 downto 0);
signal cmp_rdy : std_logic;
signal cmp_valid : std_logic;
signal cmp_addr : std_logic_vector(31 downto 0);
signal cmp_bl : std_logic_vector(5 downto 0);
signal data_error : std_logic;
signal cmp_data : std_logic_vector(DWIDTH - 1 downto 0);
signal last_word_rd : std_logic;
signal bl_counter : std_logic_vector(5 downto 0);
signal cmd_rdy : std_logic;
signal user_bl_cnt_is_1 : std_logic;
signal data_rdy : std_logic;
signal delayed_data : std_logic_vector(DWIDTH downto 0);
-- signal cmp_data_piped : std_logic_vector(DWIDTH downto 0);
signal cmp_data_r : std_logic_vector(DWIDTH-1 downto 0);
signal rd_mdata_en : std_logic;
signal rd_data_r : std_logic_vector(DWIDTH - 1 downto 0);
signal force_wrcmd_gen : std_logic;
signal wait_bl_end : std_logic;
signal wait_bl_end_r1 : std_logic;
signal v6_data_cmp_valid : std_logic;
signal rd_v6_mdata : std_logic_vector(DWIDTH-1 downto 0);
signal cmpdata_r : std_logic_vector(DWIDTH-1 downto 0);
signal rd_mdata : std_logic_vector(DWIDTH-1 downto 0);
signal l_data_error : std_logic;
signal u_data_error : std_logic;
signal cmp_data_en : std_logic;
signal force_wrcmd_timeout_cnts : std_logic_vector(7 downto 0);
signal error_byte : std_logic_vector(NUM_DQ_PINS / 2 - 1 downto 0);
signal error_byte_r1 : std_logic_vector(NUM_DQ_PINS / 2 - 1 downto 0);
signal dq_lane_error : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal dq_lane_error_r1 : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal dq_lane_error_r2 : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cum_dq_lane_error_mask : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cumlative_dq_lane_error_reg : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cumlative_dq_lane_error_c : std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
signal rd_mdata_fifo_empty : std_logic;
signal data_valid_r : std_logic;
-- Declare intermediate signals for referenced outputs
-- SIGNAL xhdl2 : STD_LOGIC_VECTOR(DWIDTH DOWNTO 0);
-- SIGNAL tmp_sig : STD_LOGIC;
signal last_word_rd_o_xhdl0 : std_logic;
signal rd_buff_avail_o_xhdl1 : std_logic_vector(6 downto 0);
begin
-- Drive referenced outputs
last_word_rd_o <= last_word_rd_o_xhdl0;
rd_buff_avail_o <= rd_buff_avail_o_xhdl1;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
wait_bl_end_r1 <= wait_bl_end;
rd_data_r <= data_i;
end if;
end process;
force_wrcmd_gen_o <= force_wrcmd_gen;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
force_wrcmd_gen <= '0';
elsif ((wait_bl_end = '0' and wait_bl_end_r1 = '1') or force_wrcmd_timeout_cnts = "11111111") then
force_wrcmd_gen <= '0';
elsif ((cmd_valid_i = '1' and bl_i > "010000") or wait_bl_end = '1') then
force_wrcmd_gen <= '1';
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
force_wrcmd_timeout_cnts <= "00000000";
elsif (wait_bl_end = '0' and wait_bl_end_r1 = '1') then
force_wrcmd_timeout_cnts <= "00000000";
elsif (force_wrcmd_gen = '1') then
force_wrcmd_timeout_cnts <= force_wrcmd_timeout_cnts + "00000001";
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
wait_bl_end <= '0';
elsif (force_wrcmd_timeout_cnts = "11111111") then
wait_bl_end <= '0';
elsif ((gen_rdy and gen_valid) = '1' and gen_bl > "010000") then
wait_bl_end <= '1';
elsif ((wait_bl_end and user_bl_cnt_is_1) = '1') then
wait_bl_end <= '0';
end if;
end if;
end process;
cmd_rdy_o <= cmd_rdy;
read_postedfifo : read_posted_fifo
GENERIC MAP (
TCQ => TCQ,
FAMILY => FAMILY,
MEM_BURST_LEN => MEM_BURST_LEN,
ADDR_WIDTH => 32,
BL_WIDTH => 6
)
port map (
clk_i => clk_i,
rst_i => rst_i(0),
cmd_rdy_o => cmd_rdy,
cmd_valid_i => cmd_valid_i,
data_valid_i => data_rdy,
addr_i => addr_i,
bl_i => bl_i,
cmd_sent => cmd_sent,
bl_sent => bl_sent,
cmd_en_i => cmd_en_i,
user_bl_cnt_is_1 => user_bl_cnt_is_1,
gen_rdy_i => gen_rdy,
gen_valid_o => gen_valid,
gen_addr_o => gen_addr,
gen_bl_o => gen_bl,
rd_buff_avail_o => rd_buff_avail_o_xhdl1,
rd_mdata_fifo_empty => rd_mdata_fifo_empty,
rd_mdata_en => rd_mdata_en
);
rd_datagen : rd_data_gen
generic map (
FAMILY => FAMILY,
MEM_BURST_LEN => MEM_BURST_LEN,
NUM_DQ_PINS => NUM_DQ_PINS,
SEL_VICTIM_LINE => SEL_VICTIM_LINE,
DATA_PATTERN => DATA_PATTERN,
DWIDTH => DWIDTH,
COLUMN_WIDTH => MEM_COL_WIDTH
)
port map (
clk_i => clk_i,
rst_i => rst_i(4 downto 0),
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_rdy_o => gen_rdy,
cmd_valid_i => gen_valid,
last_word_o => last_word_rd_o_xhdl0,
-- m_addr_i => m_addr_i,
fixed_data_i => fixed_data_i,
addr_i => gen_addr,
bl_i => gen_bl,
user_bl_cnt_is_1_o => user_bl_cnt_is_1,
data_rdy_i => data_valid_i,
data_valid_o => cmp_valid,
data_o => cmp_data,
rd_mdata_en => rd_mdata_en
);
rd_mdata_fifo : afifo
GENERIC MAP (
DSIZE => DWIDTH,
FIFO_DEPTH => 32,
ASIZE => 5,
SYNC => 1
)
PORT MAP (
wr_clk => clk_i,
rst => rst_i(0),
wr_en => data_valid_i,
wr_data => data_i,
rd_en => rd_mdata_en,
rd_clk => clk_i,
rd_data => rd_v6_mdata,
full => open,
empty => rd_mdata_fifo_empty,
almost_full => open
);
-- tmp_sig <= cmp_valid AND data_valid_i;
-- xhdl2 <= ( tmp_sig & cmp_data);
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
-- delayed_data <= (tmp_sig & cmp_data);
cmp_data_r <= cmp_data;
end if;
end process;
rd_mdata_o <= rd_mdata;
rd_mdata <= rd_data_r WHEN (FAMILY = "SPARTAN6") ELSE rd_v6_mdata
WHEN ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) ELSE data_i;
cmp_data_valid <= cmp_data_en WHEN (FAMILY = "SPARTAN6") ELSE v6_data_cmp_valid
WHEN ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) ELSE data_valid_i;
cmp_data_o <= cmp_data_r;
cmp_addr_o <= gen_addr;
cmp_bl_o <= gen_bl;
-- xhdl4 : if (FAMILY = "SPARTAN6") generate
-- rd_data_o <= rd_data_r;
-- end generate;
-- xhdl5 : if (FAMILY /= "SPARTAN6") generate
-- rd_data_o <= data_i;
-- end generate;
data_rdy_o <= data_rdy;
data_rdy <= cmp_valid and data_valid_i;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
v6_data_cmp_valid <= rd_mdata_en;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
cmp_data_en <= data_rdy;
end if;
end process;
xhdl6 : if (FAMILY = "SPARTAN6") generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (cmp_data_en = '1') then
IF ((rd_data_r(DWIDTH / 2 - 1 downto 0) /= cmp_data_r(DWIDTH / 2 - 1 downto 0))) then
l_data_error <= '1' ;
ELSE
l_data_error <= '0' ;
END IF;
else
l_data_error <= '0' ;
end if;
if (cmp_data_en = '1') then
IF ((rd_data_r(DWIDTH - 1 downto DWIDTH / 2) /= cmp_data_r(DWIDTH - 1 downto DWIDTH / 2))) then
u_data_error <= '1' ;
ELSE
u_data_error <= '0' ;
END IF;
else
u_data_error <= '0' ;
end if;
data_error <= l_data_error or u_data_error;
--synthesis translate_off
if (data_error = '1') then
report ("DATA ERROR");
end if;
--synthesis translate_on
end if;
end process;
end generate;
gen_error_2 : if ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) generate
gen_cmp : FOR i IN 0 TO NUM_DQ_PINS / 2 - 1 GENERATE
error_byte(i) <= '1' WHEN (rd_mdata_fifo_empty = '0' AND rd_mdata_en = '1' AND (rd_v6_mdata(8 * (i + 1) - 1 DOWNTO 8 * i) /= cmp_data(8 * (i + 1) - 1 DOWNTO 8 * i))) ELSE '0';
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
error_byte_r1 <= (others => '0');
data_error <= '0';
ELSE
error_byte_r1 <= error_byte;
-- FOR i IN 0 TO DWIDTH - 1 LOOP
data_error <= REDUCTION_OR(error_byte_r1);--error_byte_r1(i) OR data_error;
-- END LOOP;
END IF;
end if;
end process;
process (data_error)
begin
--synthesis translate_off
IF (data_error = '1') THEN
report "DATA ERROR"; -- severity ERROR;
END IF;
--synthesis translate_on
end process;
gen_dq_error_map: FOR i IN 0 to DQ_ERROR_WIDTH - 1 generate
dq_lane_error(i) <= (error_byte_r1(i) OR error_byte_r1(i+DQ_ERROR_WIDTH) OR
error_byte_r1(i+ (NUM_DQ_PINS*2/8)) OR
error_byte_r1(i+ (NUM_DQ_PINS*3/8)));
cumlative_dq_lane_error_c(i) <= cumlative_dq_lane_error_reg(i) OR dq_lane_error_r1(i);
end generate;
process (clk_i)
begin
IF (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
dq_lane_error_r1 <= (others => '0');
dq_lane_error_r2 <= (others => '0');
data_valid_r <= '0';
cumlative_dq_lane_error_reg <= (others => '0');
ELSE
data_valid_r <= data_valid_i;
dq_lane_error_r1 <= dq_lane_error;
cumlative_dq_lane_error_reg <= cumlative_dq_lane_error_c;
END IF;
END IF;
end process;
end generate;
xhdl8 : if ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 8)) generate
gen_cmp_8 : FOR i IN 0 TO NUM_DQ_PINS / 2 - 1 GENERATE
error_byte(i) <= '1' WHEN (data_valid_i = '1' AND (data_i(8 * (i + 1) - 1 DOWNTO 8 * i) /= cmp_data(8 * (i + 1) - 1 DOWNTO 8 * i))) ELSE '0';
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
error_byte_r1 <= (others => '0');
data_error <= '0';
ELSE
error_byte_r1 <= error_byte;
--FOR i IN 0 TO DWIDTH - 1 LOOP
-- data_error <= error_byte_r1(i) OR data_error;
--END LOOP;
data_error <= REDUCTION_OR(error_byte_r1);--error_byte_r1(i) OR data_error;
--synthesis translate_off
IF (data_error = '1') THEN
report "DATA ERROR"; -- severity ERROR;
end if;
--synthesis translate_on
END IF;
end if;
end process;
gen_dq_error_map: FOR i IN 0 to DQ_ERROR_WIDTH - 1 generate
dq_lane_error(i) <= (error_byte_r1(i) OR error_byte_r1(i+DQ_ERROR_WIDTH) OR
error_byte_r1(i+ (NUM_DQ_PINS*2/8)) OR
error_byte_r1(i+ (NUM_DQ_PINS*3/8)));
cumlative_dq_lane_error_c(i) <= cumlative_dq_lane_error_reg(i) OR dq_lane_error_r1(i);
end generate;
process (clk_i)
begin
IF (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
dq_lane_error_r1 <= (others => '0');
dq_lane_error_r2 <= (others => '0');
data_valid_r <= '0';
cumlative_dq_lane_error_reg <= (others => '0');
ELSE
data_valid_r <= data_valid_i;
dq_lane_error_r1 <= dq_lane_error;
cumlative_dq_lane_error_reg <= cumlative_dq_lane_error_c;
END IF;
END IF;
end process;
end generate;
cumlative_dq_lane_error_r <= cumlative_dq_lane_error_reg;
dq_error_bytelane_cmp <= dq_lane_error_r1;
data_error_o <= data_error;
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: read_data_path.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This is top level of read path and also consist of comparison logic
-- for read data.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
entity read_data_path is
generic (
TCQ : time := 100 ps;
FAMILY : string := "VIRTEX6";
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : integer := 32;
CMP_DATA_PIPE_STAGES : integer := 3;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
DQ_ERROR_WIDTH : integer := 1;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
MEM_COL_WIDTH : integer := 10
);
port (
clk_i : in std_logic;
manual_clear_error : in std_logic;
rst_i : in std_logic_vector(9 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
cmd_sent : in std_logic_vector(2 downto 0);
bl_sent : in std_logic_vector(5 downto 0);
cmd_en_i : in std_logic;
-- m_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(31 downto 0);
bl_i : in std_logic_vector(5 downto 0);
-- input [5:0] port_data_counts_i,// connect to data port fifo counts
data_rdy_o : out std_logic;
data_valid_i : in std_logic;
data_i : in std_logic_vector(DWIDTH - 1 downto 0);
last_word_rd_o : out std_logic;
data_error_o : out std_logic;
cmp_data_o : out std_logic_vector(DWIDTH - 1 downto 0);
rd_mdata_o : out std_logic_vector(DWIDTH - 1 downto 0);
cmp_data_valid : out std_logic;
cmp_addr_o : out std_logic_vector(31 downto 0);
cmp_bl_o : out std_logic_vector(5 downto 0);
force_wrcmd_gen_o : out std_logic;
rd_buff_avail_o : out std_logic_vector(6 downto 0);
dq_error_bytelane_cmp : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
cumlative_dq_lane_error_r : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0)
);
end entity read_data_path;
architecture trans of read_data_path is
function REDUCTION_OR( A: in std_logic_vector) return std_logic is
variable tmp : std_logic := '0';
begin
for i in A'range loop
tmp := tmp or A(i);
end loop;
return tmp;
end function REDUCTION_OR;
COMPONENT read_posted_fifo IS
GENERIC (
TCQ : time := 100 ps;
MEM_BURST_LEN : integer := 4;
FAMILY : STRING := "SPARTAN6";
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
data_valid_i : IN STD_LOGIC;
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
user_bl_cnt_is_1 : IN STD_LOGIC;
cmd_sent : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
bl_sent : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
cmd_en_i : IN STD_LOGIC;
gen_rdy_i : IN STD_LOGIC;
gen_valid_o : OUT STD_LOGIC;
gen_addr_o : OUT STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
gen_bl_o : OUT STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
rd_buff_avail_o : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
rd_mdata_fifo_empty : IN STD_LOGIC;
rd_mdata_en : OUT STD_LOGIC
);
END COMPONENT;
component rd_data_gen is
generic (
FAMILY : string := "SPARTAN6";
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : integer := 32;
BL_WIDTH : integer := 6;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_PRBS";
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3;
COLUMN_WIDTH : integer := 10
);
port (
clk_i : in std_logic;
rst_i : in std_logic_vector(4 downto 0);
prbs_fseed_i : in std_logic_vector(31 downto 0);
rd_mdata_en : in std_logic;
data_mode_i : in std_logic_vector(3 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
last_word_o : out std_logic;
-- m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
bl_i : in std_logic_vector(BL_WIDTH - 1 downto 0);
user_bl_cnt_is_1_o : out std_logic;
data_rdy_i : in std_logic;
data_valid_o : out std_logic;
data_o : out std_logic_vector(DWIDTH - 1 downto 0)
);
end component;
component afifo IS
GENERIC (
DSIZE : INTEGER := 32;
FIFO_DEPTH : INTEGER := 16;
ASIZE : INTEGER := 5;
SYNC : INTEGER := 1
);
PORT (
wr_clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
wr_en : IN STD_LOGIC;
wr_data : IN STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
rd_en : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_data : OUT STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
almost_full : OUT STD_LOGIC;
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END component;
signal gen_rdy : std_logic;
signal gen_valid : std_logic;
signal gen_addr : std_logic_vector(31 downto 0);
signal gen_bl : std_logic_vector(5 downto 0);
signal cmp_rdy : std_logic;
signal cmp_valid : std_logic;
signal cmp_addr : std_logic_vector(31 downto 0);
signal cmp_bl : std_logic_vector(5 downto 0);
signal data_error : std_logic;
signal cmp_data : std_logic_vector(DWIDTH - 1 downto 0);
signal last_word_rd : std_logic;
signal bl_counter : std_logic_vector(5 downto 0);
signal cmd_rdy : std_logic;
signal user_bl_cnt_is_1 : std_logic;
signal data_rdy : std_logic;
signal delayed_data : std_logic_vector(DWIDTH downto 0);
-- signal cmp_data_piped : std_logic_vector(DWIDTH downto 0);
signal cmp_data_r : std_logic_vector(DWIDTH-1 downto 0);
signal rd_mdata_en : std_logic;
signal rd_data_r : std_logic_vector(DWIDTH - 1 downto 0);
signal force_wrcmd_gen : std_logic;
signal wait_bl_end : std_logic;
signal wait_bl_end_r1 : std_logic;
signal v6_data_cmp_valid : std_logic;
signal rd_v6_mdata : std_logic_vector(DWIDTH-1 downto 0);
signal cmpdata_r : std_logic_vector(DWIDTH-1 downto 0);
signal rd_mdata : std_logic_vector(DWIDTH-1 downto 0);
signal l_data_error : std_logic;
signal u_data_error : std_logic;
signal cmp_data_en : std_logic;
signal force_wrcmd_timeout_cnts : std_logic_vector(7 downto 0);
signal error_byte : std_logic_vector(NUM_DQ_PINS / 2 - 1 downto 0);
signal error_byte_r1 : std_logic_vector(NUM_DQ_PINS / 2 - 1 downto 0);
signal dq_lane_error : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal dq_lane_error_r1 : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal dq_lane_error_r2 : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cum_dq_lane_error_mask : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cumlative_dq_lane_error_reg : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cumlative_dq_lane_error_c : std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
signal rd_mdata_fifo_empty : std_logic;
signal data_valid_r : std_logic;
-- Declare intermediate signals for referenced outputs
-- SIGNAL xhdl2 : STD_LOGIC_VECTOR(DWIDTH DOWNTO 0);
-- SIGNAL tmp_sig : STD_LOGIC;
signal last_word_rd_o_xhdl0 : std_logic;
signal rd_buff_avail_o_xhdl1 : std_logic_vector(6 downto 0);
begin
-- Drive referenced outputs
last_word_rd_o <= last_word_rd_o_xhdl0;
rd_buff_avail_o <= rd_buff_avail_o_xhdl1;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
wait_bl_end_r1 <= wait_bl_end;
rd_data_r <= data_i;
end if;
end process;
force_wrcmd_gen_o <= force_wrcmd_gen;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
force_wrcmd_gen <= '0';
elsif ((wait_bl_end = '0' and wait_bl_end_r1 = '1') or force_wrcmd_timeout_cnts = "11111111") then
force_wrcmd_gen <= '0';
elsif ((cmd_valid_i = '1' and bl_i > "010000") or wait_bl_end = '1') then
force_wrcmd_gen <= '1';
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
force_wrcmd_timeout_cnts <= "00000000";
elsif (wait_bl_end = '0' and wait_bl_end_r1 = '1') then
force_wrcmd_timeout_cnts <= "00000000";
elsif (force_wrcmd_gen = '1') then
force_wrcmd_timeout_cnts <= force_wrcmd_timeout_cnts + "00000001";
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
wait_bl_end <= '0';
elsif (force_wrcmd_timeout_cnts = "11111111") then
wait_bl_end <= '0';
elsif ((gen_rdy and gen_valid) = '1' and gen_bl > "010000") then
wait_bl_end <= '1';
elsif ((wait_bl_end and user_bl_cnt_is_1) = '1') then
wait_bl_end <= '0';
end if;
end if;
end process;
cmd_rdy_o <= cmd_rdy;
read_postedfifo : read_posted_fifo
GENERIC MAP (
TCQ => TCQ,
FAMILY => FAMILY,
MEM_BURST_LEN => MEM_BURST_LEN,
ADDR_WIDTH => 32,
BL_WIDTH => 6
)
port map (
clk_i => clk_i,
rst_i => rst_i(0),
cmd_rdy_o => cmd_rdy,
cmd_valid_i => cmd_valid_i,
data_valid_i => data_rdy,
addr_i => addr_i,
bl_i => bl_i,
cmd_sent => cmd_sent,
bl_sent => bl_sent,
cmd_en_i => cmd_en_i,
user_bl_cnt_is_1 => user_bl_cnt_is_1,
gen_rdy_i => gen_rdy,
gen_valid_o => gen_valid,
gen_addr_o => gen_addr,
gen_bl_o => gen_bl,
rd_buff_avail_o => rd_buff_avail_o_xhdl1,
rd_mdata_fifo_empty => rd_mdata_fifo_empty,
rd_mdata_en => rd_mdata_en
);
rd_datagen : rd_data_gen
generic map (
FAMILY => FAMILY,
MEM_BURST_LEN => MEM_BURST_LEN,
NUM_DQ_PINS => NUM_DQ_PINS,
SEL_VICTIM_LINE => SEL_VICTIM_LINE,
DATA_PATTERN => DATA_PATTERN,
DWIDTH => DWIDTH,
COLUMN_WIDTH => MEM_COL_WIDTH
)
port map (
clk_i => clk_i,
rst_i => rst_i(4 downto 0),
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_rdy_o => gen_rdy,
cmd_valid_i => gen_valid,
last_word_o => last_word_rd_o_xhdl0,
-- m_addr_i => m_addr_i,
fixed_data_i => fixed_data_i,
addr_i => gen_addr,
bl_i => gen_bl,
user_bl_cnt_is_1_o => user_bl_cnt_is_1,
data_rdy_i => data_valid_i,
data_valid_o => cmp_valid,
data_o => cmp_data,
rd_mdata_en => rd_mdata_en
);
rd_mdata_fifo : afifo
GENERIC MAP (
DSIZE => DWIDTH,
FIFO_DEPTH => 32,
ASIZE => 5,
SYNC => 1
)
PORT MAP (
wr_clk => clk_i,
rst => rst_i(0),
wr_en => data_valid_i,
wr_data => data_i,
rd_en => rd_mdata_en,
rd_clk => clk_i,
rd_data => rd_v6_mdata,
full => open,
empty => rd_mdata_fifo_empty,
almost_full => open
);
-- tmp_sig <= cmp_valid AND data_valid_i;
-- xhdl2 <= ( tmp_sig & cmp_data);
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
-- delayed_data <= (tmp_sig & cmp_data);
cmp_data_r <= cmp_data;
end if;
end process;
rd_mdata_o <= rd_mdata;
rd_mdata <= rd_data_r WHEN (FAMILY = "SPARTAN6") ELSE rd_v6_mdata
WHEN ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) ELSE data_i;
cmp_data_valid <= cmp_data_en WHEN (FAMILY = "SPARTAN6") ELSE v6_data_cmp_valid
WHEN ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) ELSE data_valid_i;
cmp_data_o <= cmp_data_r;
cmp_addr_o <= gen_addr;
cmp_bl_o <= gen_bl;
-- xhdl4 : if (FAMILY = "SPARTAN6") generate
-- rd_data_o <= rd_data_r;
-- end generate;
-- xhdl5 : if (FAMILY /= "SPARTAN6") generate
-- rd_data_o <= data_i;
-- end generate;
data_rdy_o <= data_rdy;
data_rdy <= cmp_valid and data_valid_i;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
v6_data_cmp_valid <= rd_mdata_en;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
cmp_data_en <= data_rdy;
end if;
end process;
xhdl6 : if (FAMILY = "SPARTAN6") generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (cmp_data_en = '1') then
IF ((rd_data_r(DWIDTH / 2 - 1 downto 0) /= cmp_data_r(DWIDTH / 2 - 1 downto 0))) then
l_data_error <= '1' ;
ELSE
l_data_error <= '0' ;
END IF;
else
l_data_error <= '0' ;
end if;
if (cmp_data_en = '1') then
IF ((rd_data_r(DWIDTH - 1 downto DWIDTH / 2) /= cmp_data_r(DWIDTH - 1 downto DWIDTH / 2))) then
u_data_error <= '1' ;
ELSE
u_data_error <= '0' ;
END IF;
else
u_data_error <= '0' ;
end if;
data_error <= l_data_error or u_data_error;
--synthesis translate_off
if (data_error = '1') then
report ("DATA ERROR");
end if;
--synthesis translate_on
end if;
end process;
end generate;
gen_error_2 : if ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) generate
gen_cmp : FOR i IN 0 TO NUM_DQ_PINS / 2 - 1 GENERATE
error_byte(i) <= '1' WHEN (rd_mdata_fifo_empty = '0' AND rd_mdata_en = '1' AND (rd_v6_mdata(8 * (i + 1) - 1 DOWNTO 8 * i) /= cmp_data(8 * (i + 1) - 1 DOWNTO 8 * i))) ELSE '0';
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
error_byte_r1 <= (others => '0');
data_error <= '0';
ELSE
error_byte_r1 <= error_byte;
-- FOR i IN 0 TO DWIDTH - 1 LOOP
data_error <= REDUCTION_OR(error_byte_r1);--error_byte_r1(i) OR data_error;
-- END LOOP;
END IF;
end if;
end process;
process (data_error)
begin
--synthesis translate_off
IF (data_error = '1') THEN
report "DATA ERROR"; -- severity ERROR;
END IF;
--synthesis translate_on
end process;
gen_dq_error_map: FOR i IN 0 to DQ_ERROR_WIDTH - 1 generate
dq_lane_error(i) <= (error_byte_r1(i) OR error_byte_r1(i+DQ_ERROR_WIDTH) OR
error_byte_r1(i+ (NUM_DQ_PINS*2/8)) OR
error_byte_r1(i+ (NUM_DQ_PINS*3/8)));
cumlative_dq_lane_error_c(i) <= cumlative_dq_lane_error_reg(i) OR dq_lane_error_r1(i);
end generate;
process (clk_i)
begin
IF (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
dq_lane_error_r1 <= (others => '0');
dq_lane_error_r2 <= (others => '0');
data_valid_r <= '0';
cumlative_dq_lane_error_reg <= (others => '0');
ELSE
data_valid_r <= data_valid_i;
dq_lane_error_r1 <= dq_lane_error;
cumlative_dq_lane_error_reg <= cumlative_dq_lane_error_c;
END IF;
END IF;
end process;
end generate;
xhdl8 : if ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 8)) generate
gen_cmp_8 : FOR i IN 0 TO NUM_DQ_PINS / 2 - 1 GENERATE
error_byte(i) <= '1' WHEN (data_valid_i = '1' AND (data_i(8 * (i + 1) - 1 DOWNTO 8 * i) /= cmp_data(8 * (i + 1) - 1 DOWNTO 8 * i))) ELSE '0';
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
error_byte_r1 <= (others => '0');
data_error <= '0';
ELSE
error_byte_r1 <= error_byte;
--FOR i IN 0 TO DWIDTH - 1 LOOP
-- data_error <= error_byte_r1(i) OR data_error;
--END LOOP;
data_error <= REDUCTION_OR(error_byte_r1);--error_byte_r1(i) OR data_error;
--synthesis translate_off
IF (data_error = '1') THEN
report "DATA ERROR"; -- severity ERROR;
end if;
--synthesis translate_on
END IF;
end if;
end process;
gen_dq_error_map: FOR i IN 0 to DQ_ERROR_WIDTH - 1 generate
dq_lane_error(i) <= (error_byte_r1(i) OR error_byte_r1(i+DQ_ERROR_WIDTH) OR
error_byte_r1(i+ (NUM_DQ_PINS*2/8)) OR
error_byte_r1(i+ (NUM_DQ_PINS*3/8)));
cumlative_dq_lane_error_c(i) <= cumlative_dq_lane_error_reg(i) OR dq_lane_error_r1(i);
end generate;
process (clk_i)
begin
IF (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
dq_lane_error_r1 <= (others => '0');
dq_lane_error_r2 <= (others => '0');
data_valid_r <= '0';
cumlative_dq_lane_error_reg <= (others => '0');
ELSE
data_valid_r <= data_valid_i;
dq_lane_error_r1 <= dq_lane_error;
cumlative_dq_lane_error_reg <= cumlative_dq_lane_error_c;
END IF;
END IF;
end process;
end generate;
cumlative_dq_lane_error_r <= cumlative_dq_lane_error_reg;
dq_error_bytelane_cmp <= dq_lane_error_r1;
data_error_o <= data_error;
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: read_data_path.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This is top level of read path and also consist of comparison logic
-- for read data.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
entity read_data_path is
generic (
TCQ : time := 100 ps;
FAMILY : string := "VIRTEX6";
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : integer := 32;
CMP_DATA_PIPE_STAGES : integer := 3;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
DQ_ERROR_WIDTH : integer := 1;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
MEM_COL_WIDTH : integer := 10
);
port (
clk_i : in std_logic;
manual_clear_error : in std_logic;
rst_i : in std_logic_vector(9 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
cmd_sent : in std_logic_vector(2 downto 0);
bl_sent : in std_logic_vector(5 downto 0);
cmd_en_i : in std_logic;
-- m_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(31 downto 0);
bl_i : in std_logic_vector(5 downto 0);
-- input [5:0] port_data_counts_i,// connect to data port fifo counts
data_rdy_o : out std_logic;
data_valid_i : in std_logic;
data_i : in std_logic_vector(DWIDTH - 1 downto 0);
last_word_rd_o : out std_logic;
data_error_o : out std_logic;
cmp_data_o : out std_logic_vector(DWIDTH - 1 downto 0);
rd_mdata_o : out std_logic_vector(DWIDTH - 1 downto 0);
cmp_data_valid : out std_logic;
cmp_addr_o : out std_logic_vector(31 downto 0);
cmp_bl_o : out std_logic_vector(5 downto 0);
force_wrcmd_gen_o : out std_logic;
rd_buff_avail_o : out std_logic_vector(6 downto 0);
dq_error_bytelane_cmp : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
cumlative_dq_lane_error_r : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0)
);
end entity read_data_path;
architecture trans of read_data_path is
function REDUCTION_OR( A: in std_logic_vector) return std_logic is
variable tmp : std_logic := '0';
begin
for i in A'range loop
tmp := tmp or A(i);
end loop;
return tmp;
end function REDUCTION_OR;
COMPONENT read_posted_fifo IS
GENERIC (
TCQ : time := 100 ps;
MEM_BURST_LEN : integer := 4;
FAMILY : STRING := "SPARTAN6";
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
data_valid_i : IN STD_LOGIC;
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
user_bl_cnt_is_1 : IN STD_LOGIC;
cmd_sent : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
bl_sent : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
cmd_en_i : IN STD_LOGIC;
gen_rdy_i : IN STD_LOGIC;
gen_valid_o : OUT STD_LOGIC;
gen_addr_o : OUT STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
gen_bl_o : OUT STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
rd_buff_avail_o : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
rd_mdata_fifo_empty : IN STD_LOGIC;
rd_mdata_en : OUT STD_LOGIC
);
END COMPONENT;
component rd_data_gen is
generic (
FAMILY : string := "SPARTAN6";
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : integer := 32;
BL_WIDTH : integer := 6;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_PRBS";
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3;
COLUMN_WIDTH : integer := 10
);
port (
clk_i : in std_logic;
rst_i : in std_logic_vector(4 downto 0);
prbs_fseed_i : in std_logic_vector(31 downto 0);
rd_mdata_en : in std_logic;
data_mode_i : in std_logic_vector(3 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
last_word_o : out std_logic;
-- m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
bl_i : in std_logic_vector(BL_WIDTH - 1 downto 0);
user_bl_cnt_is_1_o : out std_logic;
data_rdy_i : in std_logic;
data_valid_o : out std_logic;
data_o : out std_logic_vector(DWIDTH - 1 downto 0)
);
end component;
component afifo IS
GENERIC (
DSIZE : INTEGER := 32;
FIFO_DEPTH : INTEGER := 16;
ASIZE : INTEGER := 5;
SYNC : INTEGER := 1
);
PORT (
wr_clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
wr_en : IN STD_LOGIC;
wr_data : IN STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
rd_en : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_data : OUT STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
almost_full : OUT STD_LOGIC;
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END component;
signal gen_rdy : std_logic;
signal gen_valid : std_logic;
signal gen_addr : std_logic_vector(31 downto 0);
signal gen_bl : std_logic_vector(5 downto 0);
signal cmp_rdy : std_logic;
signal cmp_valid : std_logic;
signal cmp_addr : std_logic_vector(31 downto 0);
signal cmp_bl : std_logic_vector(5 downto 0);
signal data_error : std_logic;
signal cmp_data : std_logic_vector(DWIDTH - 1 downto 0);
signal last_word_rd : std_logic;
signal bl_counter : std_logic_vector(5 downto 0);
signal cmd_rdy : std_logic;
signal user_bl_cnt_is_1 : std_logic;
signal data_rdy : std_logic;
signal delayed_data : std_logic_vector(DWIDTH downto 0);
-- signal cmp_data_piped : std_logic_vector(DWIDTH downto 0);
signal cmp_data_r : std_logic_vector(DWIDTH-1 downto 0);
signal rd_mdata_en : std_logic;
signal rd_data_r : std_logic_vector(DWIDTH - 1 downto 0);
signal force_wrcmd_gen : std_logic;
signal wait_bl_end : std_logic;
signal wait_bl_end_r1 : std_logic;
signal v6_data_cmp_valid : std_logic;
signal rd_v6_mdata : std_logic_vector(DWIDTH-1 downto 0);
signal cmpdata_r : std_logic_vector(DWIDTH-1 downto 0);
signal rd_mdata : std_logic_vector(DWIDTH-1 downto 0);
signal l_data_error : std_logic;
signal u_data_error : std_logic;
signal cmp_data_en : std_logic;
signal force_wrcmd_timeout_cnts : std_logic_vector(7 downto 0);
signal error_byte : std_logic_vector(NUM_DQ_PINS / 2 - 1 downto 0);
signal error_byte_r1 : std_logic_vector(NUM_DQ_PINS / 2 - 1 downto 0);
signal dq_lane_error : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal dq_lane_error_r1 : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal dq_lane_error_r2 : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cum_dq_lane_error_mask : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cumlative_dq_lane_error_reg : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cumlative_dq_lane_error_c : std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
signal rd_mdata_fifo_empty : std_logic;
signal data_valid_r : std_logic;
-- Declare intermediate signals for referenced outputs
-- SIGNAL xhdl2 : STD_LOGIC_VECTOR(DWIDTH DOWNTO 0);
-- SIGNAL tmp_sig : STD_LOGIC;
signal last_word_rd_o_xhdl0 : std_logic;
signal rd_buff_avail_o_xhdl1 : std_logic_vector(6 downto 0);
begin
-- Drive referenced outputs
last_word_rd_o <= last_word_rd_o_xhdl0;
rd_buff_avail_o <= rd_buff_avail_o_xhdl1;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
wait_bl_end_r1 <= wait_bl_end;
rd_data_r <= data_i;
end if;
end process;
force_wrcmd_gen_o <= force_wrcmd_gen;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
force_wrcmd_gen <= '0';
elsif ((wait_bl_end = '0' and wait_bl_end_r1 = '1') or force_wrcmd_timeout_cnts = "11111111") then
force_wrcmd_gen <= '0';
elsif ((cmd_valid_i = '1' and bl_i > "010000") or wait_bl_end = '1') then
force_wrcmd_gen <= '1';
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
force_wrcmd_timeout_cnts <= "00000000";
elsif (wait_bl_end = '0' and wait_bl_end_r1 = '1') then
force_wrcmd_timeout_cnts <= "00000000";
elsif (force_wrcmd_gen = '1') then
force_wrcmd_timeout_cnts <= force_wrcmd_timeout_cnts + "00000001";
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
wait_bl_end <= '0';
elsif (force_wrcmd_timeout_cnts = "11111111") then
wait_bl_end <= '0';
elsif ((gen_rdy and gen_valid) = '1' and gen_bl > "010000") then
wait_bl_end <= '1';
elsif ((wait_bl_end and user_bl_cnt_is_1) = '1') then
wait_bl_end <= '0';
end if;
end if;
end process;
cmd_rdy_o <= cmd_rdy;
read_postedfifo : read_posted_fifo
GENERIC MAP (
TCQ => TCQ,
FAMILY => FAMILY,
MEM_BURST_LEN => MEM_BURST_LEN,
ADDR_WIDTH => 32,
BL_WIDTH => 6
)
port map (
clk_i => clk_i,
rst_i => rst_i(0),
cmd_rdy_o => cmd_rdy,
cmd_valid_i => cmd_valid_i,
data_valid_i => data_rdy,
addr_i => addr_i,
bl_i => bl_i,
cmd_sent => cmd_sent,
bl_sent => bl_sent,
cmd_en_i => cmd_en_i,
user_bl_cnt_is_1 => user_bl_cnt_is_1,
gen_rdy_i => gen_rdy,
gen_valid_o => gen_valid,
gen_addr_o => gen_addr,
gen_bl_o => gen_bl,
rd_buff_avail_o => rd_buff_avail_o_xhdl1,
rd_mdata_fifo_empty => rd_mdata_fifo_empty,
rd_mdata_en => rd_mdata_en
);
rd_datagen : rd_data_gen
generic map (
FAMILY => FAMILY,
MEM_BURST_LEN => MEM_BURST_LEN,
NUM_DQ_PINS => NUM_DQ_PINS,
SEL_VICTIM_LINE => SEL_VICTIM_LINE,
DATA_PATTERN => DATA_PATTERN,
DWIDTH => DWIDTH,
COLUMN_WIDTH => MEM_COL_WIDTH
)
port map (
clk_i => clk_i,
rst_i => rst_i(4 downto 0),
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_rdy_o => gen_rdy,
cmd_valid_i => gen_valid,
last_word_o => last_word_rd_o_xhdl0,
-- m_addr_i => m_addr_i,
fixed_data_i => fixed_data_i,
addr_i => gen_addr,
bl_i => gen_bl,
user_bl_cnt_is_1_o => user_bl_cnt_is_1,
data_rdy_i => data_valid_i,
data_valid_o => cmp_valid,
data_o => cmp_data,
rd_mdata_en => rd_mdata_en
);
rd_mdata_fifo : afifo
GENERIC MAP (
DSIZE => DWIDTH,
FIFO_DEPTH => 32,
ASIZE => 5,
SYNC => 1
)
PORT MAP (
wr_clk => clk_i,
rst => rst_i(0),
wr_en => data_valid_i,
wr_data => data_i,
rd_en => rd_mdata_en,
rd_clk => clk_i,
rd_data => rd_v6_mdata,
full => open,
empty => rd_mdata_fifo_empty,
almost_full => open
);
-- tmp_sig <= cmp_valid AND data_valid_i;
-- xhdl2 <= ( tmp_sig & cmp_data);
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
-- delayed_data <= (tmp_sig & cmp_data);
cmp_data_r <= cmp_data;
end if;
end process;
rd_mdata_o <= rd_mdata;
rd_mdata <= rd_data_r WHEN (FAMILY = "SPARTAN6") ELSE rd_v6_mdata
WHEN ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) ELSE data_i;
cmp_data_valid <= cmp_data_en WHEN (FAMILY = "SPARTAN6") ELSE v6_data_cmp_valid
WHEN ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) ELSE data_valid_i;
cmp_data_o <= cmp_data_r;
cmp_addr_o <= gen_addr;
cmp_bl_o <= gen_bl;
-- xhdl4 : if (FAMILY = "SPARTAN6") generate
-- rd_data_o <= rd_data_r;
-- end generate;
-- xhdl5 : if (FAMILY /= "SPARTAN6") generate
-- rd_data_o <= data_i;
-- end generate;
data_rdy_o <= data_rdy;
data_rdy <= cmp_valid and data_valid_i;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
v6_data_cmp_valid <= rd_mdata_en;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
cmp_data_en <= data_rdy;
end if;
end process;
xhdl6 : if (FAMILY = "SPARTAN6") generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (cmp_data_en = '1') then
IF ((rd_data_r(DWIDTH / 2 - 1 downto 0) /= cmp_data_r(DWIDTH / 2 - 1 downto 0))) then
l_data_error <= '1' ;
ELSE
l_data_error <= '0' ;
END IF;
else
l_data_error <= '0' ;
end if;
if (cmp_data_en = '1') then
IF ((rd_data_r(DWIDTH - 1 downto DWIDTH / 2) /= cmp_data_r(DWIDTH - 1 downto DWIDTH / 2))) then
u_data_error <= '1' ;
ELSE
u_data_error <= '0' ;
END IF;
else
u_data_error <= '0' ;
end if;
data_error <= l_data_error or u_data_error;
--synthesis translate_off
if (data_error = '1') then
report ("DATA ERROR");
end if;
--synthesis translate_on
end if;
end process;
end generate;
gen_error_2 : if ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) generate
gen_cmp : FOR i IN 0 TO NUM_DQ_PINS / 2 - 1 GENERATE
error_byte(i) <= '1' WHEN (rd_mdata_fifo_empty = '0' AND rd_mdata_en = '1' AND (rd_v6_mdata(8 * (i + 1) - 1 DOWNTO 8 * i) /= cmp_data(8 * (i + 1) - 1 DOWNTO 8 * i))) ELSE '0';
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
error_byte_r1 <= (others => '0');
data_error <= '0';
ELSE
error_byte_r1 <= error_byte;
-- FOR i IN 0 TO DWIDTH - 1 LOOP
data_error <= REDUCTION_OR(error_byte_r1);--error_byte_r1(i) OR data_error;
-- END LOOP;
END IF;
end if;
end process;
process (data_error)
begin
--synthesis translate_off
IF (data_error = '1') THEN
report "DATA ERROR"; -- severity ERROR;
END IF;
--synthesis translate_on
end process;
gen_dq_error_map: FOR i IN 0 to DQ_ERROR_WIDTH - 1 generate
dq_lane_error(i) <= (error_byte_r1(i) OR error_byte_r1(i+DQ_ERROR_WIDTH) OR
error_byte_r1(i+ (NUM_DQ_PINS*2/8)) OR
error_byte_r1(i+ (NUM_DQ_PINS*3/8)));
cumlative_dq_lane_error_c(i) <= cumlative_dq_lane_error_reg(i) OR dq_lane_error_r1(i);
end generate;
process (clk_i)
begin
IF (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
dq_lane_error_r1 <= (others => '0');
dq_lane_error_r2 <= (others => '0');
data_valid_r <= '0';
cumlative_dq_lane_error_reg <= (others => '0');
ELSE
data_valid_r <= data_valid_i;
dq_lane_error_r1 <= dq_lane_error;
cumlative_dq_lane_error_reg <= cumlative_dq_lane_error_c;
END IF;
END IF;
end process;
end generate;
xhdl8 : if ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 8)) generate
gen_cmp_8 : FOR i IN 0 TO NUM_DQ_PINS / 2 - 1 GENERATE
error_byte(i) <= '1' WHEN (data_valid_i = '1' AND (data_i(8 * (i + 1) - 1 DOWNTO 8 * i) /= cmp_data(8 * (i + 1) - 1 DOWNTO 8 * i))) ELSE '0';
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
error_byte_r1 <= (others => '0');
data_error <= '0';
ELSE
error_byte_r1 <= error_byte;
--FOR i IN 0 TO DWIDTH - 1 LOOP
-- data_error <= error_byte_r1(i) OR data_error;
--END LOOP;
data_error <= REDUCTION_OR(error_byte_r1);--error_byte_r1(i) OR data_error;
--synthesis translate_off
IF (data_error = '1') THEN
report "DATA ERROR"; -- severity ERROR;
end if;
--synthesis translate_on
END IF;
end if;
end process;
gen_dq_error_map: FOR i IN 0 to DQ_ERROR_WIDTH - 1 generate
dq_lane_error(i) <= (error_byte_r1(i) OR error_byte_r1(i+DQ_ERROR_WIDTH) OR
error_byte_r1(i+ (NUM_DQ_PINS*2/8)) OR
error_byte_r1(i+ (NUM_DQ_PINS*3/8)));
cumlative_dq_lane_error_c(i) <= cumlative_dq_lane_error_reg(i) OR dq_lane_error_r1(i);
end generate;
process (clk_i)
begin
IF (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
dq_lane_error_r1 <= (others => '0');
dq_lane_error_r2 <= (others => '0');
data_valid_r <= '0';
cumlative_dq_lane_error_reg <= (others => '0');
ELSE
data_valid_r <= data_valid_i;
dq_lane_error_r1 <= dq_lane_error;
cumlative_dq_lane_error_reg <= cumlative_dq_lane_error_c;
END IF;
END IF;
end process;
end generate;
cumlative_dq_lane_error_r <= cumlative_dq_lane_error_reg;
dq_error_bytelane_cmp <= dq_lane_error_r1;
data_error_o <= data_error;
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: read_data_path.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This is top level of read path and also consist of comparison logic
-- for read data.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
entity read_data_path is
generic (
TCQ : time := 100 ps;
FAMILY : string := "VIRTEX6";
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : integer := 32;
CMP_DATA_PIPE_STAGES : integer := 3;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
DQ_ERROR_WIDTH : integer := 1;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
MEM_COL_WIDTH : integer := 10
);
port (
clk_i : in std_logic;
manual_clear_error : in std_logic;
rst_i : in std_logic_vector(9 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
cmd_sent : in std_logic_vector(2 downto 0);
bl_sent : in std_logic_vector(5 downto 0);
cmd_en_i : in std_logic;
-- m_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(31 downto 0);
bl_i : in std_logic_vector(5 downto 0);
-- input [5:0] port_data_counts_i,// connect to data port fifo counts
data_rdy_o : out std_logic;
data_valid_i : in std_logic;
data_i : in std_logic_vector(DWIDTH - 1 downto 0);
last_word_rd_o : out std_logic;
data_error_o : out std_logic;
cmp_data_o : out std_logic_vector(DWIDTH - 1 downto 0);
rd_mdata_o : out std_logic_vector(DWIDTH - 1 downto 0);
cmp_data_valid : out std_logic;
cmp_addr_o : out std_logic_vector(31 downto 0);
cmp_bl_o : out std_logic_vector(5 downto 0);
force_wrcmd_gen_o : out std_logic;
rd_buff_avail_o : out std_logic_vector(6 downto 0);
dq_error_bytelane_cmp : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
cumlative_dq_lane_error_r : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0)
);
end entity read_data_path;
architecture trans of read_data_path is
function REDUCTION_OR( A: in std_logic_vector) return std_logic is
variable tmp : std_logic := '0';
begin
for i in A'range loop
tmp := tmp or A(i);
end loop;
return tmp;
end function REDUCTION_OR;
COMPONENT read_posted_fifo IS
GENERIC (
TCQ : time := 100 ps;
MEM_BURST_LEN : integer := 4;
FAMILY : STRING := "SPARTAN6";
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
data_valid_i : IN STD_LOGIC;
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
user_bl_cnt_is_1 : IN STD_LOGIC;
cmd_sent : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
bl_sent : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
cmd_en_i : IN STD_LOGIC;
gen_rdy_i : IN STD_LOGIC;
gen_valid_o : OUT STD_LOGIC;
gen_addr_o : OUT STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
gen_bl_o : OUT STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
rd_buff_avail_o : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
rd_mdata_fifo_empty : IN STD_LOGIC;
rd_mdata_en : OUT STD_LOGIC
);
END COMPONENT;
component rd_data_gen is
generic (
FAMILY : string := "SPARTAN6";
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : integer := 32;
BL_WIDTH : integer := 6;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_PRBS";
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3;
COLUMN_WIDTH : integer := 10
);
port (
clk_i : in std_logic;
rst_i : in std_logic_vector(4 downto 0);
prbs_fseed_i : in std_logic_vector(31 downto 0);
rd_mdata_en : in std_logic;
data_mode_i : in std_logic_vector(3 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
last_word_o : out std_logic;
-- m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
bl_i : in std_logic_vector(BL_WIDTH - 1 downto 0);
user_bl_cnt_is_1_o : out std_logic;
data_rdy_i : in std_logic;
data_valid_o : out std_logic;
data_o : out std_logic_vector(DWIDTH - 1 downto 0)
);
end component;
component afifo IS
GENERIC (
DSIZE : INTEGER := 32;
FIFO_DEPTH : INTEGER := 16;
ASIZE : INTEGER := 5;
SYNC : INTEGER := 1
);
PORT (
wr_clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
wr_en : IN STD_LOGIC;
wr_data : IN STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
rd_en : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_data : OUT STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
almost_full : OUT STD_LOGIC;
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END component;
signal gen_rdy : std_logic;
signal gen_valid : std_logic;
signal gen_addr : std_logic_vector(31 downto 0);
signal gen_bl : std_logic_vector(5 downto 0);
signal cmp_rdy : std_logic;
signal cmp_valid : std_logic;
signal cmp_addr : std_logic_vector(31 downto 0);
signal cmp_bl : std_logic_vector(5 downto 0);
signal data_error : std_logic;
signal cmp_data : std_logic_vector(DWIDTH - 1 downto 0);
signal last_word_rd : std_logic;
signal bl_counter : std_logic_vector(5 downto 0);
signal cmd_rdy : std_logic;
signal user_bl_cnt_is_1 : std_logic;
signal data_rdy : std_logic;
signal delayed_data : std_logic_vector(DWIDTH downto 0);
-- signal cmp_data_piped : std_logic_vector(DWIDTH downto 0);
signal cmp_data_r : std_logic_vector(DWIDTH-1 downto 0);
signal rd_mdata_en : std_logic;
signal rd_data_r : std_logic_vector(DWIDTH - 1 downto 0);
signal force_wrcmd_gen : std_logic;
signal wait_bl_end : std_logic;
signal wait_bl_end_r1 : std_logic;
signal v6_data_cmp_valid : std_logic;
signal rd_v6_mdata : std_logic_vector(DWIDTH-1 downto 0);
signal cmpdata_r : std_logic_vector(DWIDTH-1 downto 0);
signal rd_mdata : std_logic_vector(DWIDTH-1 downto 0);
signal l_data_error : std_logic;
signal u_data_error : std_logic;
signal cmp_data_en : std_logic;
signal force_wrcmd_timeout_cnts : std_logic_vector(7 downto 0);
signal error_byte : std_logic_vector(NUM_DQ_PINS / 2 - 1 downto 0);
signal error_byte_r1 : std_logic_vector(NUM_DQ_PINS / 2 - 1 downto 0);
signal dq_lane_error : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal dq_lane_error_r1 : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal dq_lane_error_r2 : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cum_dq_lane_error_mask : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cumlative_dq_lane_error_reg : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cumlative_dq_lane_error_c : std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
signal rd_mdata_fifo_empty : std_logic;
signal data_valid_r : std_logic;
-- Declare intermediate signals for referenced outputs
-- SIGNAL xhdl2 : STD_LOGIC_VECTOR(DWIDTH DOWNTO 0);
-- SIGNAL tmp_sig : STD_LOGIC;
signal last_word_rd_o_xhdl0 : std_logic;
signal rd_buff_avail_o_xhdl1 : std_logic_vector(6 downto 0);
begin
-- Drive referenced outputs
last_word_rd_o <= last_word_rd_o_xhdl0;
rd_buff_avail_o <= rd_buff_avail_o_xhdl1;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
wait_bl_end_r1 <= wait_bl_end;
rd_data_r <= data_i;
end if;
end process;
force_wrcmd_gen_o <= force_wrcmd_gen;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
force_wrcmd_gen <= '0';
elsif ((wait_bl_end = '0' and wait_bl_end_r1 = '1') or force_wrcmd_timeout_cnts = "11111111") then
force_wrcmd_gen <= '0';
elsif ((cmd_valid_i = '1' and bl_i > "010000") or wait_bl_end = '1') then
force_wrcmd_gen <= '1';
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
force_wrcmd_timeout_cnts <= "00000000";
elsif (wait_bl_end = '0' and wait_bl_end_r1 = '1') then
force_wrcmd_timeout_cnts <= "00000000";
elsif (force_wrcmd_gen = '1') then
force_wrcmd_timeout_cnts <= force_wrcmd_timeout_cnts + "00000001";
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
wait_bl_end <= '0';
elsif (force_wrcmd_timeout_cnts = "11111111") then
wait_bl_end <= '0';
elsif ((gen_rdy and gen_valid) = '1' and gen_bl > "010000") then
wait_bl_end <= '1';
elsif ((wait_bl_end and user_bl_cnt_is_1) = '1') then
wait_bl_end <= '0';
end if;
end if;
end process;
cmd_rdy_o <= cmd_rdy;
read_postedfifo : read_posted_fifo
GENERIC MAP (
TCQ => TCQ,
FAMILY => FAMILY,
MEM_BURST_LEN => MEM_BURST_LEN,
ADDR_WIDTH => 32,
BL_WIDTH => 6
)
port map (
clk_i => clk_i,
rst_i => rst_i(0),
cmd_rdy_o => cmd_rdy,
cmd_valid_i => cmd_valid_i,
data_valid_i => data_rdy,
addr_i => addr_i,
bl_i => bl_i,
cmd_sent => cmd_sent,
bl_sent => bl_sent,
cmd_en_i => cmd_en_i,
user_bl_cnt_is_1 => user_bl_cnt_is_1,
gen_rdy_i => gen_rdy,
gen_valid_o => gen_valid,
gen_addr_o => gen_addr,
gen_bl_o => gen_bl,
rd_buff_avail_o => rd_buff_avail_o_xhdl1,
rd_mdata_fifo_empty => rd_mdata_fifo_empty,
rd_mdata_en => rd_mdata_en
);
rd_datagen : rd_data_gen
generic map (
FAMILY => FAMILY,
MEM_BURST_LEN => MEM_BURST_LEN,
NUM_DQ_PINS => NUM_DQ_PINS,
SEL_VICTIM_LINE => SEL_VICTIM_LINE,
DATA_PATTERN => DATA_PATTERN,
DWIDTH => DWIDTH,
COLUMN_WIDTH => MEM_COL_WIDTH
)
port map (
clk_i => clk_i,
rst_i => rst_i(4 downto 0),
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_rdy_o => gen_rdy,
cmd_valid_i => gen_valid,
last_word_o => last_word_rd_o_xhdl0,
-- m_addr_i => m_addr_i,
fixed_data_i => fixed_data_i,
addr_i => gen_addr,
bl_i => gen_bl,
user_bl_cnt_is_1_o => user_bl_cnt_is_1,
data_rdy_i => data_valid_i,
data_valid_o => cmp_valid,
data_o => cmp_data,
rd_mdata_en => rd_mdata_en
);
rd_mdata_fifo : afifo
GENERIC MAP (
DSIZE => DWIDTH,
FIFO_DEPTH => 32,
ASIZE => 5,
SYNC => 1
)
PORT MAP (
wr_clk => clk_i,
rst => rst_i(0),
wr_en => data_valid_i,
wr_data => data_i,
rd_en => rd_mdata_en,
rd_clk => clk_i,
rd_data => rd_v6_mdata,
full => open,
empty => rd_mdata_fifo_empty,
almost_full => open
);
-- tmp_sig <= cmp_valid AND data_valid_i;
-- xhdl2 <= ( tmp_sig & cmp_data);
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
-- delayed_data <= (tmp_sig & cmp_data);
cmp_data_r <= cmp_data;
end if;
end process;
rd_mdata_o <= rd_mdata;
rd_mdata <= rd_data_r WHEN (FAMILY = "SPARTAN6") ELSE rd_v6_mdata
WHEN ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) ELSE data_i;
cmp_data_valid <= cmp_data_en WHEN (FAMILY = "SPARTAN6") ELSE v6_data_cmp_valid
WHEN ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) ELSE data_valid_i;
cmp_data_o <= cmp_data_r;
cmp_addr_o <= gen_addr;
cmp_bl_o <= gen_bl;
-- xhdl4 : if (FAMILY = "SPARTAN6") generate
-- rd_data_o <= rd_data_r;
-- end generate;
-- xhdl5 : if (FAMILY /= "SPARTAN6") generate
-- rd_data_o <= data_i;
-- end generate;
data_rdy_o <= data_rdy;
data_rdy <= cmp_valid and data_valid_i;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
v6_data_cmp_valid <= rd_mdata_en;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
cmp_data_en <= data_rdy;
end if;
end process;
xhdl6 : if (FAMILY = "SPARTAN6") generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (cmp_data_en = '1') then
IF ((rd_data_r(DWIDTH / 2 - 1 downto 0) /= cmp_data_r(DWIDTH / 2 - 1 downto 0))) then
l_data_error <= '1' ;
ELSE
l_data_error <= '0' ;
END IF;
else
l_data_error <= '0' ;
end if;
if (cmp_data_en = '1') then
IF ((rd_data_r(DWIDTH - 1 downto DWIDTH / 2) /= cmp_data_r(DWIDTH - 1 downto DWIDTH / 2))) then
u_data_error <= '1' ;
ELSE
u_data_error <= '0' ;
END IF;
else
u_data_error <= '0' ;
end if;
data_error <= l_data_error or u_data_error;
--synthesis translate_off
if (data_error = '1') then
report ("DATA ERROR");
end if;
--synthesis translate_on
end if;
end process;
end generate;
gen_error_2 : if ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) generate
gen_cmp : FOR i IN 0 TO NUM_DQ_PINS / 2 - 1 GENERATE
error_byte(i) <= '1' WHEN (rd_mdata_fifo_empty = '0' AND rd_mdata_en = '1' AND (rd_v6_mdata(8 * (i + 1) - 1 DOWNTO 8 * i) /= cmp_data(8 * (i + 1) - 1 DOWNTO 8 * i))) ELSE '0';
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
error_byte_r1 <= (others => '0');
data_error <= '0';
ELSE
error_byte_r1 <= error_byte;
-- FOR i IN 0 TO DWIDTH - 1 LOOP
data_error <= REDUCTION_OR(error_byte_r1);--error_byte_r1(i) OR data_error;
-- END LOOP;
END IF;
end if;
end process;
process (data_error)
begin
--synthesis translate_off
IF (data_error = '1') THEN
report "DATA ERROR"; -- severity ERROR;
END IF;
--synthesis translate_on
end process;
gen_dq_error_map: FOR i IN 0 to DQ_ERROR_WIDTH - 1 generate
dq_lane_error(i) <= (error_byte_r1(i) OR error_byte_r1(i+DQ_ERROR_WIDTH) OR
error_byte_r1(i+ (NUM_DQ_PINS*2/8)) OR
error_byte_r1(i+ (NUM_DQ_PINS*3/8)));
cumlative_dq_lane_error_c(i) <= cumlative_dq_lane_error_reg(i) OR dq_lane_error_r1(i);
end generate;
process (clk_i)
begin
IF (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
dq_lane_error_r1 <= (others => '0');
dq_lane_error_r2 <= (others => '0');
data_valid_r <= '0';
cumlative_dq_lane_error_reg <= (others => '0');
ELSE
data_valid_r <= data_valid_i;
dq_lane_error_r1 <= dq_lane_error;
cumlative_dq_lane_error_reg <= cumlative_dq_lane_error_c;
END IF;
END IF;
end process;
end generate;
xhdl8 : if ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 8)) generate
gen_cmp_8 : FOR i IN 0 TO NUM_DQ_PINS / 2 - 1 GENERATE
error_byte(i) <= '1' WHEN (data_valid_i = '1' AND (data_i(8 * (i + 1) - 1 DOWNTO 8 * i) /= cmp_data(8 * (i + 1) - 1 DOWNTO 8 * i))) ELSE '0';
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
error_byte_r1 <= (others => '0');
data_error <= '0';
ELSE
error_byte_r1 <= error_byte;
--FOR i IN 0 TO DWIDTH - 1 LOOP
-- data_error <= error_byte_r1(i) OR data_error;
--END LOOP;
data_error <= REDUCTION_OR(error_byte_r1);--error_byte_r1(i) OR data_error;
--synthesis translate_off
IF (data_error = '1') THEN
report "DATA ERROR"; -- severity ERROR;
end if;
--synthesis translate_on
END IF;
end if;
end process;
gen_dq_error_map: FOR i IN 0 to DQ_ERROR_WIDTH - 1 generate
dq_lane_error(i) <= (error_byte_r1(i) OR error_byte_r1(i+DQ_ERROR_WIDTH) OR
error_byte_r1(i+ (NUM_DQ_PINS*2/8)) OR
error_byte_r1(i+ (NUM_DQ_PINS*3/8)));
cumlative_dq_lane_error_c(i) <= cumlative_dq_lane_error_reg(i) OR dq_lane_error_r1(i);
end generate;
process (clk_i)
begin
IF (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
dq_lane_error_r1 <= (others => '0');
dq_lane_error_r2 <= (others => '0');
data_valid_r <= '0';
cumlative_dq_lane_error_reg <= (others => '0');
ELSE
data_valid_r <= data_valid_i;
dq_lane_error_r1 <= dq_lane_error;
cumlative_dq_lane_error_reg <= cumlative_dq_lane_error_c;
END IF;
END IF;
end process;
end generate;
cumlative_dq_lane_error_r <= cumlative_dq_lane_error_reg;
dq_error_bytelane_cmp <= dq_lane_error_r1;
data_error_o <= data_error;
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: read_data_path.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This is top level of read path and also consist of comparison logic
-- for read data.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
entity read_data_path is
generic (
TCQ : time := 100 ps;
FAMILY : string := "VIRTEX6";
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : integer := 32;
CMP_DATA_PIPE_STAGES : integer := 3;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
DQ_ERROR_WIDTH : integer := 1;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
MEM_COL_WIDTH : integer := 10
);
port (
clk_i : in std_logic;
manual_clear_error : in std_logic;
rst_i : in std_logic_vector(9 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
cmd_sent : in std_logic_vector(2 downto 0);
bl_sent : in std_logic_vector(5 downto 0);
cmd_en_i : in std_logic;
-- m_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(31 downto 0);
bl_i : in std_logic_vector(5 downto 0);
-- input [5:0] port_data_counts_i,// connect to data port fifo counts
data_rdy_o : out std_logic;
data_valid_i : in std_logic;
data_i : in std_logic_vector(DWIDTH - 1 downto 0);
last_word_rd_o : out std_logic;
data_error_o : out std_logic;
cmp_data_o : out std_logic_vector(DWIDTH - 1 downto 0);
rd_mdata_o : out std_logic_vector(DWIDTH - 1 downto 0);
cmp_data_valid : out std_logic;
cmp_addr_o : out std_logic_vector(31 downto 0);
cmp_bl_o : out std_logic_vector(5 downto 0);
force_wrcmd_gen_o : out std_logic;
rd_buff_avail_o : out std_logic_vector(6 downto 0);
dq_error_bytelane_cmp : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
cumlative_dq_lane_error_r : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0)
);
end entity read_data_path;
architecture trans of read_data_path is
function REDUCTION_OR( A: in std_logic_vector) return std_logic is
variable tmp : std_logic := '0';
begin
for i in A'range loop
tmp := tmp or A(i);
end loop;
return tmp;
end function REDUCTION_OR;
COMPONENT read_posted_fifo IS
GENERIC (
TCQ : time := 100 ps;
MEM_BURST_LEN : integer := 4;
FAMILY : STRING := "SPARTAN6";
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
data_valid_i : IN STD_LOGIC;
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
user_bl_cnt_is_1 : IN STD_LOGIC;
cmd_sent : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
bl_sent : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
cmd_en_i : IN STD_LOGIC;
gen_rdy_i : IN STD_LOGIC;
gen_valid_o : OUT STD_LOGIC;
gen_addr_o : OUT STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
gen_bl_o : OUT STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
rd_buff_avail_o : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
rd_mdata_fifo_empty : IN STD_LOGIC;
rd_mdata_en : OUT STD_LOGIC
);
END COMPONENT;
component rd_data_gen is
generic (
FAMILY : string := "SPARTAN6";
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : integer := 32;
BL_WIDTH : integer := 6;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_PRBS";
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3;
COLUMN_WIDTH : integer := 10
);
port (
clk_i : in std_logic;
rst_i : in std_logic_vector(4 downto 0);
prbs_fseed_i : in std_logic_vector(31 downto 0);
rd_mdata_en : in std_logic;
data_mode_i : in std_logic_vector(3 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
last_word_o : out std_logic;
-- m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
bl_i : in std_logic_vector(BL_WIDTH - 1 downto 0);
user_bl_cnt_is_1_o : out std_logic;
data_rdy_i : in std_logic;
data_valid_o : out std_logic;
data_o : out std_logic_vector(DWIDTH - 1 downto 0)
);
end component;
component afifo IS
GENERIC (
DSIZE : INTEGER := 32;
FIFO_DEPTH : INTEGER := 16;
ASIZE : INTEGER := 5;
SYNC : INTEGER := 1
);
PORT (
wr_clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
wr_en : IN STD_LOGIC;
wr_data : IN STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
rd_en : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_data : OUT STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
almost_full : OUT STD_LOGIC;
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END component;
signal gen_rdy : std_logic;
signal gen_valid : std_logic;
signal gen_addr : std_logic_vector(31 downto 0);
signal gen_bl : std_logic_vector(5 downto 0);
signal cmp_rdy : std_logic;
signal cmp_valid : std_logic;
signal cmp_addr : std_logic_vector(31 downto 0);
signal cmp_bl : std_logic_vector(5 downto 0);
signal data_error : std_logic;
signal cmp_data : std_logic_vector(DWIDTH - 1 downto 0);
signal last_word_rd : std_logic;
signal bl_counter : std_logic_vector(5 downto 0);
signal cmd_rdy : std_logic;
signal user_bl_cnt_is_1 : std_logic;
signal data_rdy : std_logic;
signal delayed_data : std_logic_vector(DWIDTH downto 0);
-- signal cmp_data_piped : std_logic_vector(DWIDTH downto 0);
signal cmp_data_r : std_logic_vector(DWIDTH-1 downto 0);
signal rd_mdata_en : std_logic;
signal rd_data_r : std_logic_vector(DWIDTH - 1 downto 0);
signal force_wrcmd_gen : std_logic;
signal wait_bl_end : std_logic;
signal wait_bl_end_r1 : std_logic;
signal v6_data_cmp_valid : std_logic;
signal rd_v6_mdata : std_logic_vector(DWIDTH-1 downto 0);
signal cmpdata_r : std_logic_vector(DWIDTH-1 downto 0);
signal rd_mdata : std_logic_vector(DWIDTH-1 downto 0);
signal l_data_error : std_logic;
signal u_data_error : std_logic;
signal cmp_data_en : std_logic;
signal force_wrcmd_timeout_cnts : std_logic_vector(7 downto 0);
signal error_byte : std_logic_vector(NUM_DQ_PINS / 2 - 1 downto 0);
signal error_byte_r1 : std_logic_vector(NUM_DQ_PINS / 2 - 1 downto 0);
signal dq_lane_error : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal dq_lane_error_r1 : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal dq_lane_error_r2 : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cum_dq_lane_error_mask : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cumlative_dq_lane_error_reg : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cumlative_dq_lane_error_c : std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
signal rd_mdata_fifo_empty : std_logic;
signal data_valid_r : std_logic;
-- Declare intermediate signals for referenced outputs
-- SIGNAL xhdl2 : STD_LOGIC_VECTOR(DWIDTH DOWNTO 0);
-- SIGNAL tmp_sig : STD_LOGIC;
signal last_word_rd_o_xhdl0 : std_logic;
signal rd_buff_avail_o_xhdl1 : std_logic_vector(6 downto 0);
begin
-- Drive referenced outputs
last_word_rd_o <= last_word_rd_o_xhdl0;
rd_buff_avail_o <= rd_buff_avail_o_xhdl1;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
wait_bl_end_r1 <= wait_bl_end;
rd_data_r <= data_i;
end if;
end process;
force_wrcmd_gen_o <= force_wrcmd_gen;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
force_wrcmd_gen <= '0';
elsif ((wait_bl_end = '0' and wait_bl_end_r1 = '1') or force_wrcmd_timeout_cnts = "11111111") then
force_wrcmd_gen <= '0';
elsif ((cmd_valid_i = '1' and bl_i > "010000") or wait_bl_end = '1') then
force_wrcmd_gen <= '1';
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
force_wrcmd_timeout_cnts <= "00000000";
elsif (wait_bl_end = '0' and wait_bl_end_r1 = '1') then
force_wrcmd_timeout_cnts <= "00000000";
elsif (force_wrcmd_gen = '1') then
force_wrcmd_timeout_cnts <= force_wrcmd_timeout_cnts + "00000001";
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
wait_bl_end <= '0';
elsif (force_wrcmd_timeout_cnts = "11111111") then
wait_bl_end <= '0';
elsif ((gen_rdy and gen_valid) = '1' and gen_bl > "010000") then
wait_bl_end <= '1';
elsif ((wait_bl_end and user_bl_cnt_is_1) = '1') then
wait_bl_end <= '0';
end if;
end if;
end process;
cmd_rdy_o <= cmd_rdy;
read_postedfifo : read_posted_fifo
GENERIC MAP (
TCQ => TCQ,
FAMILY => FAMILY,
MEM_BURST_LEN => MEM_BURST_LEN,
ADDR_WIDTH => 32,
BL_WIDTH => 6
)
port map (
clk_i => clk_i,
rst_i => rst_i(0),
cmd_rdy_o => cmd_rdy,
cmd_valid_i => cmd_valid_i,
data_valid_i => data_rdy,
addr_i => addr_i,
bl_i => bl_i,
cmd_sent => cmd_sent,
bl_sent => bl_sent,
cmd_en_i => cmd_en_i,
user_bl_cnt_is_1 => user_bl_cnt_is_1,
gen_rdy_i => gen_rdy,
gen_valid_o => gen_valid,
gen_addr_o => gen_addr,
gen_bl_o => gen_bl,
rd_buff_avail_o => rd_buff_avail_o_xhdl1,
rd_mdata_fifo_empty => rd_mdata_fifo_empty,
rd_mdata_en => rd_mdata_en
);
rd_datagen : rd_data_gen
generic map (
FAMILY => FAMILY,
MEM_BURST_LEN => MEM_BURST_LEN,
NUM_DQ_PINS => NUM_DQ_PINS,
SEL_VICTIM_LINE => SEL_VICTIM_LINE,
DATA_PATTERN => DATA_PATTERN,
DWIDTH => DWIDTH,
COLUMN_WIDTH => MEM_COL_WIDTH
)
port map (
clk_i => clk_i,
rst_i => rst_i(4 downto 0),
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_rdy_o => gen_rdy,
cmd_valid_i => gen_valid,
last_word_o => last_word_rd_o_xhdl0,
-- m_addr_i => m_addr_i,
fixed_data_i => fixed_data_i,
addr_i => gen_addr,
bl_i => gen_bl,
user_bl_cnt_is_1_o => user_bl_cnt_is_1,
data_rdy_i => data_valid_i,
data_valid_o => cmp_valid,
data_o => cmp_data,
rd_mdata_en => rd_mdata_en
);
rd_mdata_fifo : afifo
GENERIC MAP (
DSIZE => DWIDTH,
FIFO_DEPTH => 32,
ASIZE => 5,
SYNC => 1
)
PORT MAP (
wr_clk => clk_i,
rst => rst_i(0),
wr_en => data_valid_i,
wr_data => data_i,
rd_en => rd_mdata_en,
rd_clk => clk_i,
rd_data => rd_v6_mdata,
full => open,
empty => rd_mdata_fifo_empty,
almost_full => open
);
-- tmp_sig <= cmp_valid AND data_valid_i;
-- xhdl2 <= ( tmp_sig & cmp_data);
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
-- delayed_data <= (tmp_sig & cmp_data);
cmp_data_r <= cmp_data;
end if;
end process;
rd_mdata_o <= rd_mdata;
rd_mdata <= rd_data_r WHEN (FAMILY = "SPARTAN6") ELSE rd_v6_mdata
WHEN ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) ELSE data_i;
cmp_data_valid <= cmp_data_en WHEN (FAMILY = "SPARTAN6") ELSE v6_data_cmp_valid
WHEN ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) ELSE data_valid_i;
cmp_data_o <= cmp_data_r;
cmp_addr_o <= gen_addr;
cmp_bl_o <= gen_bl;
-- xhdl4 : if (FAMILY = "SPARTAN6") generate
-- rd_data_o <= rd_data_r;
-- end generate;
-- xhdl5 : if (FAMILY /= "SPARTAN6") generate
-- rd_data_o <= data_i;
-- end generate;
data_rdy_o <= data_rdy;
data_rdy <= cmp_valid and data_valid_i;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
v6_data_cmp_valid <= rd_mdata_en;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
cmp_data_en <= data_rdy;
end if;
end process;
xhdl6 : if (FAMILY = "SPARTAN6") generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (cmp_data_en = '1') then
IF ((rd_data_r(DWIDTH / 2 - 1 downto 0) /= cmp_data_r(DWIDTH / 2 - 1 downto 0))) then
l_data_error <= '1' ;
ELSE
l_data_error <= '0' ;
END IF;
else
l_data_error <= '0' ;
end if;
if (cmp_data_en = '1') then
IF ((rd_data_r(DWIDTH - 1 downto DWIDTH / 2) /= cmp_data_r(DWIDTH - 1 downto DWIDTH / 2))) then
u_data_error <= '1' ;
ELSE
u_data_error <= '0' ;
END IF;
else
u_data_error <= '0' ;
end if;
data_error <= l_data_error or u_data_error;
--synthesis translate_off
if (data_error = '1') then
report ("DATA ERROR");
end if;
--synthesis translate_on
end if;
end process;
end generate;
gen_error_2 : if ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) generate
gen_cmp : FOR i IN 0 TO NUM_DQ_PINS / 2 - 1 GENERATE
error_byte(i) <= '1' WHEN (rd_mdata_fifo_empty = '0' AND rd_mdata_en = '1' AND (rd_v6_mdata(8 * (i + 1) - 1 DOWNTO 8 * i) /= cmp_data(8 * (i + 1) - 1 DOWNTO 8 * i))) ELSE '0';
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
error_byte_r1 <= (others => '0');
data_error <= '0';
ELSE
error_byte_r1 <= error_byte;
-- FOR i IN 0 TO DWIDTH - 1 LOOP
data_error <= REDUCTION_OR(error_byte_r1);--error_byte_r1(i) OR data_error;
-- END LOOP;
END IF;
end if;
end process;
process (data_error)
begin
--synthesis translate_off
IF (data_error = '1') THEN
report "DATA ERROR"; -- severity ERROR;
END IF;
--synthesis translate_on
end process;
gen_dq_error_map: FOR i IN 0 to DQ_ERROR_WIDTH - 1 generate
dq_lane_error(i) <= (error_byte_r1(i) OR error_byte_r1(i+DQ_ERROR_WIDTH) OR
error_byte_r1(i+ (NUM_DQ_PINS*2/8)) OR
error_byte_r1(i+ (NUM_DQ_PINS*3/8)));
cumlative_dq_lane_error_c(i) <= cumlative_dq_lane_error_reg(i) OR dq_lane_error_r1(i);
end generate;
process (clk_i)
begin
IF (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
dq_lane_error_r1 <= (others => '0');
dq_lane_error_r2 <= (others => '0');
data_valid_r <= '0';
cumlative_dq_lane_error_reg <= (others => '0');
ELSE
data_valid_r <= data_valid_i;
dq_lane_error_r1 <= dq_lane_error;
cumlative_dq_lane_error_reg <= cumlative_dq_lane_error_c;
END IF;
END IF;
end process;
end generate;
xhdl8 : if ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 8)) generate
gen_cmp_8 : FOR i IN 0 TO NUM_DQ_PINS / 2 - 1 GENERATE
error_byte(i) <= '1' WHEN (data_valid_i = '1' AND (data_i(8 * (i + 1) - 1 DOWNTO 8 * i) /= cmp_data(8 * (i + 1) - 1 DOWNTO 8 * i))) ELSE '0';
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
error_byte_r1 <= (others => '0');
data_error <= '0';
ELSE
error_byte_r1 <= error_byte;
--FOR i IN 0 TO DWIDTH - 1 LOOP
-- data_error <= error_byte_r1(i) OR data_error;
--END LOOP;
data_error <= REDUCTION_OR(error_byte_r1);--error_byte_r1(i) OR data_error;
--synthesis translate_off
IF (data_error = '1') THEN
report "DATA ERROR"; -- severity ERROR;
end if;
--synthesis translate_on
END IF;
end if;
end process;
gen_dq_error_map: FOR i IN 0 to DQ_ERROR_WIDTH - 1 generate
dq_lane_error(i) <= (error_byte_r1(i) OR error_byte_r1(i+DQ_ERROR_WIDTH) OR
error_byte_r1(i+ (NUM_DQ_PINS*2/8)) OR
error_byte_r1(i+ (NUM_DQ_PINS*3/8)));
cumlative_dq_lane_error_c(i) <= cumlative_dq_lane_error_reg(i) OR dq_lane_error_r1(i);
end generate;
process (clk_i)
begin
IF (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
dq_lane_error_r1 <= (others => '0');
dq_lane_error_r2 <= (others => '0');
data_valid_r <= '0';
cumlative_dq_lane_error_reg <= (others => '0');
ELSE
data_valid_r <= data_valid_i;
dq_lane_error_r1 <= dq_lane_error;
cumlative_dq_lane_error_reg <= cumlative_dq_lane_error_c;
END IF;
END IF;
end process;
end generate;
cumlative_dq_lane_error_r <= cumlative_dq_lane_error_reg;
dq_error_bytelane_cmp <= dq_lane_error_r1;
data_error_o <= data_error;
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: read_data_path.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This is top level of read path and also consist of comparison logic
-- for read data.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
entity read_data_path is
generic (
TCQ : time := 100 ps;
FAMILY : string := "VIRTEX6";
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : integer := 32;
CMP_DATA_PIPE_STAGES : integer := 3;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
DQ_ERROR_WIDTH : integer := 1;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
MEM_COL_WIDTH : integer := 10
);
port (
clk_i : in std_logic;
manual_clear_error : in std_logic;
rst_i : in std_logic_vector(9 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
cmd_sent : in std_logic_vector(2 downto 0);
bl_sent : in std_logic_vector(5 downto 0);
cmd_en_i : in std_logic;
-- m_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(31 downto 0);
bl_i : in std_logic_vector(5 downto 0);
-- input [5:0] port_data_counts_i,// connect to data port fifo counts
data_rdy_o : out std_logic;
data_valid_i : in std_logic;
data_i : in std_logic_vector(DWIDTH - 1 downto 0);
last_word_rd_o : out std_logic;
data_error_o : out std_logic;
cmp_data_o : out std_logic_vector(DWIDTH - 1 downto 0);
rd_mdata_o : out std_logic_vector(DWIDTH - 1 downto 0);
cmp_data_valid : out std_logic;
cmp_addr_o : out std_logic_vector(31 downto 0);
cmp_bl_o : out std_logic_vector(5 downto 0);
force_wrcmd_gen_o : out std_logic;
rd_buff_avail_o : out std_logic_vector(6 downto 0);
dq_error_bytelane_cmp : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
cumlative_dq_lane_error_r : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0)
);
end entity read_data_path;
architecture trans of read_data_path is
function REDUCTION_OR( A: in std_logic_vector) return std_logic is
variable tmp : std_logic := '0';
begin
for i in A'range loop
tmp := tmp or A(i);
end loop;
return tmp;
end function REDUCTION_OR;
COMPONENT read_posted_fifo IS
GENERIC (
TCQ : time := 100 ps;
MEM_BURST_LEN : integer := 4;
FAMILY : STRING := "SPARTAN6";
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
data_valid_i : IN STD_LOGIC;
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
user_bl_cnt_is_1 : IN STD_LOGIC;
cmd_sent : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
bl_sent : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
cmd_en_i : IN STD_LOGIC;
gen_rdy_i : IN STD_LOGIC;
gen_valid_o : OUT STD_LOGIC;
gen_addr_o : OUT STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
gen_bl_o : OUT STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
rd_buff_avail_o : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
rd_mdata_fifo_empty : IN STD_LOGIC;
rd_mdata_en : OUT STD_LOGIC
);
END COMPONENT;
component rd_data_gen is
generic (
FAMILY : string := "SPARTAN6";
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : integer := 32;
BL_WIDTH : integer := 6;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_PRBS";
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3;
COLUMN_WIDTH : integer := 10
);
port (
clk_i : in std_logic;
rst_i : in std_logic_vector(4 downto 0);
prbs_fseed_i : in std_logic_vector(31 downto 0);
rd_mdata_en : in std_logic;
data_mode_i : in std_logic_vector(3 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
last_word_o : out std_logic;
-- m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
bl_i : in std_logic_vector(BL_WIDTH - 1 downto 0);
user_bl_cnt_is_1_o : out std_logic;
data_rdy_i : in std_logic;
data_valid_o : out std_logic;
data_o : out std_logic_vector(DWIDTH - 1 downto 0)
);
end component;
component afifo IS
GENERIC (
DSIZE : INTEGER := 32;
FIFO_DEPTH : INTEGER := 16;
ASIZE : INTEGER := 5;
SYNC : INTEGER := 1
);
PORT (
wr_clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
wr_en : IN STD_LOGIC;
wr_data : IN STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
rd_en : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_data : OUT STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
almost_full : OUT STD_LOGIC;
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END component;
signal gen_rdy : std_logic;
signal gen_valid : std_logic;
signal gen_addr : std_logic_vector(31 downto 0);
signal gen_bl : std_logic_vector(5 downto 0);
signal cmp_rdy : std_logic;
signal cmp_valid : std_logic;
signal cmp_addr : std_logic_vector(31 downto 0);
signal cmp_bl : std_logic_vector(5 downto 0);
signal data_error : std_logic;
signal cmp_data : std_logic_vector(DWIDTH - 1 downto 0);
signal last_word_rd : std_logic;
signal bl_counter : std_logic_vector(5 downto 0);
signal cmd_rdy : std_logic;
signal user_bl_cnt_is_1 : std_logic;
signal data_rdy : std_logic;
signal delayed_data : std_logic_vector(DWIDTH downto 0);
-- signal cmp_data_piped : std_logic_vector(DWIDTH downto 0);
signal cmp_data_r : std_logic_vector(DWIDTH-1 downto 0);
signal rd_mdata_en : std_logic;
signal rd_data_r : std_logic_vector(DWIDTH - 1 downto 0);
signal force_wrcmd_gen : std_logic;
signal wait_bl_end : std_logic;
signal wait_bl_end_r1 : std_logic;
signal v6_data_cmp_valid : std_logic;
signal rd_v6_mdata : std_logic_vector(DWIDTH-1 downto 0);
signal cmpdata_r : std_logic_vector(DWIDTH-1 downto 0);
signal rd_mdata : std_logic_vector(DWIDTH-1 downto 0);
signal l_data_error : std_logic;
signal u_data_error : std_logic;
signal cmp_data_en : std_logic;
signal force_wrcmd_timeout_cnts : std_logic_vector(7 downto 0);
signal error_byte : std_logic_vector(NUM_DQ_PINS / 2 - 1 downto 0);
signal error_byte_r1 : std_logic_vector(NUM_DQ_PINS / 2 - 1 downto 0);
signal dq_lane_error : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal dq_lane_error_r1 : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal dq_lane_error_r2 : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cum_dq_lane_error_mask : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cumlative_dq_lane_error_reg : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cumlative_dq_lane_error_c : std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
signal rd_mdata_fifo_empty : std_logic;
signal data_valid_r : std_logic;
-- Declare intermediate signals for referenced outputs
-- SIGNAL xhdl2 : STD_LOGIC_VECTOR(DWIDTH DOWNTO 0);
-- SIGNAL tmp_sig : STD_LOGIC;
signal last_word_rd_o_xhdl0 : std_logic;
signal rd_buff_avail_o_xhdl1 : std_logic_vector(6 downto 0);
begin
-- Drive referenced outputs
last_word_rd_o <= last_word_rd_o_xhdl0;
rd_buff_avail_o <= rd_buff_avail_o_xhdl1;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
wait_bl_end_r1 <= wait_bl_end;
rd_data_r <= data_i;
end if;
end process;
force_wrcmd_gen_o <= force_wrcmd_gen;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
force_wrcmd_gen <= '0';
elsif ((wait_bl_end = '0' and wait_bl_end_r1 = '1') or force_wrcmd_timeout_cnts = "11111111") then
force_wrcmd_gen <= '0';
elsif ((cmd_valid_i = '1' and bl_i > "010000") or wait_bl_end = '1') then
force_wrcmd_gen <= '1';
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
force_wrcmd_timeout_cnts <= "00000000";
elsif (wait_bl_end = '0' and wait_bl_end_r1 = '1') then
force_wrcmd_timeout_cnts <= "00000000";
elsif (force_wrcmd_gen = '1') then
force_wrcmd_timeout_cnts <= force_wrcmd_timeout_cnts + "00000001";
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
wait_bl_end <= '0';
elsif (force_wrcmd_timeout_cnts = "11111111") then
wait_bl_end <= '0';
elsif ((gen_rdy and gen_valid) = '1' and gen_bl > "010000") then
wait_bl_end <= '1';
elsif ((wait_bl_end and user_bl_cnt_is_1) = '1') then
wait_bl_end <= '0';
end if;
end if;
end process;
cmd_rdy_o <= cmd_rdy;
read_postedfifo : read_posted_fifo
GENERIC MAP (
TCQ => TCQ,
FAMILY => FAMILY,
MEM_BURST_LEN => MEM_BURST_LEN,
ADDR_WIDTH => 32,
BL_WIDTH => 6
)
port map (
clk_i => clk_i,
rst_i => rst_i(0),
cmd_rdy_o => cmd_rdy,
cmd_valid_i => cmd_valid_i,
data_valid_i => data_rdy,
addr_i => addr_i,
bl_i => bl_i,
cmd_sent => cmd_sent,
bl_sent => bl_sent,
cmd_en_i => cmd_en_i,
user_bl_cnt_is_1 => user_bl_cnt_is_1,
gen_rdy_i => gen_rdy,
gen_valid_o => gen_valid,
gen_addr_o => gen_addr,
gen_bl_o => gen_bl,
rd_buff_avail_o => rd_buff_avail_o_xhdl1,
rd_mdata_fifo_empty => rd_mdata_fifo_empty,
rd_mdata_en => rd_mdata_en
);
rd_datagen : rd_data_gen
generic map (
FAMILY => FAMILY,
MEM_BURST_LEN => MEM_BURST_LEN,
NUM_DQ_PINS => NUM_DQ_PINS,
SEL_VICTIM_LINE => SEL_VICTIM_LINE,
DATA_PATTERN => DATA_PATTERN,
DWIDTH => DWIDTH,
COLUMN_WIDTH => MEM_COL_WIDTH
)
port map (
clk_i => clk_i,
rst_i => rst_i(4 downto 0),
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_rdy_o => gen_rdy,
cmd_valid_i => gen_valid,
last_word_o => last_word_rd_o_xhdl0,
-- m_addr_i => m_addr_i,
fixed_data_i => fixed_data_i,
addr_i => gen_addr,
bl_i => gen_bl,
user_bl_cnt_is_1_o => user_bl_cnt_is_1,
data_rdy_i => data_valid_i,
data_valid_o => cmp_valid,
data_o => cmp_data,
rd_mdata_en => rd_mdata_en
);
rd_mdata_fifo : afifo
GENERIC MAP (
DSIZE => DWIDTH,
FIFO_DEPTH => 32,
ASIZE => 5,
SYNC => 1
)
PORT MAP (
wr_clk => clk_i,
rst => rst_i(0),
wr_en => data_valid_i,
wr_data => data_i,
rd_en => rd_mdata_en,
rd_clk => clk_i,
rd_data => rd_v6_mdata,
full => open,
empty => rd_mdata_fifo_empty,
almost_full => open
);
-- tmp_sig <= cmp_valid AND data_valid_i;
-- xhdl2 <= ( tmp_sig & cmp_data);
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
-- delayed_data <= (tmp_sig & cmp_data);
cmp_data_r <= cmp_data;
end if;
end process;
rd_mdata_o <= rd_mdata;
rd_mdata <= rd_data_r WHEN (FAMILY = "SPARTAN6") ELSE rd_v6_mdata
WHEN ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) ELSE data_i;
cmp_data_valid <= cmp_data_en WHEN (FAMILY = "SPARTAN6") ELSE v6_data_cmp_valid
WHEN ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) ELSE data_valid_i;
cmp_data_o <= cmp_data_r;
cmp_addr_o <= gen_addr;
cmp_bl_o <= gen_bl;
-- xhdl4 : if (FAMILY = "SPARTAN6") generate
-- rd_data_o <= rd_data_r;
-- end generate;
-- xhdl5 : if (FAMILY /= "SPARTAN6") generate
-- rd_data_o <= data_i;
-- end generate;
data_rdy_o <= data_rdy;
data_rdy <= cmp_valid and data_valid_i;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
v6_data_cmp_valid <= rd_mdata_en;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
cmp_data_en <= data_rdy;
end if;
end process;
xhdl6 : if (FAMILY = "SPARTAN6") generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (cmp_data_en = '1') then
IF ((rd_data_r(DWIDTH / 2 - 1 downto 0) /= cmp_data_r(DWIDTH / 2 - 1 downto 0))) then
l_data_error <= '1' ;
ELSE
l_data_error <= '0' ;
END IF;
else
l_data_error <= '0' ;
end if;
if (cmp_data_en = '1') then
IF ((rd_data_r(DWIDTH - 1 downto DWIDTH / 2) /= cmp_data_r(DWIDTH - 1 downto DWIDTH / 2))) then
u_data_error <= '1' ;
ELSE
u_data_error <= '0' ;
END IF;
else
u_data_error <= '0' ;
end if;
data_error <= l_data_error or u_data_error;
--synthesis translate_off
if (data_error = '1') then
report ("DATA ERROR");
end if;
--synthesis translate_on
end if;
end process;
end generate;
gen_error_2 : if ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) generate
gen_cmp : FOR i IN 0 TO NUM_DQ_PINS / 2 - 1 GENERATE
error_byte(i) <= '1' WHEN (rd_mdata_fifo_empty = '0' AND rd_mdata_en = '1' AND (rd_v6_mdata(8 * (i + 1) - 1 DOWNTO 8 * i) /= cmp_data(8 * (i + 1) - 1 DOWNTO 8 * i))) ELSE '0';
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
error_byte_r1 <= (others => '0');
data_error <= '0';
ELSE
error_byte_r1 <= error_byte;
-- FOR i IN 0 TO DWIDTH - 1 LOOP
data_error <= REDUCTION_OR(error_byte_r1);--error_byte_r1(i) OR data_error;
-- END LOOP;
END IF;
end if;
end process;
process (data_error)
begin
--synthesis translate_off
IF (data_error = '1') THEN
report "DATA ERROR"; -- severity ERROR;
END IF;
--synthesis translate_on
end process;
gen_dq_error_map: FOR i IN 0 to DQ_ERROR_WIDTH - 1 generate
dq_lane_error(i) <= (error_byte_r1(i) OR error_byte_r1(i+DQ_ERROR_WIDTH) OR
error_byte_r1(i+ (NUM_DQ_PINS*2/8)) OR
error_byte_r1(i+ (NUM_DQ_PINS*3/8)));
cumlative_dq_lane_error_c(i) <= cumlative_dq_lane_error_reg(i) OR dq_lane_error_r1(i);
end generate;
process (clk_i)
begin
IF (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
dq_lane_error_r1 <= (others => '0');
dq_lane_error_r2 <= (others => '0');
data_valid_r <= '0';
cumlative_dq_lane_error_reg <= (others => '0');
ELSE
data_valid_r <= data_valid_i;
dq_lane_error_r1 <= dq_lane_error;
cumlative_dq_lane_error_reg <= cumlative_dq_lane_error_c;
END IF;
END IF;
end process;
end generate;
xhdl8 : if ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 8)) generate
gen_cmp_8 : FOR i IN 0 TO NUM_DQ_PINS / 2 - 1 GENERATE
error_byte(i) <= '1' WHEN (data_valid_i = '1' AND (data_i(8 * (i + 1) - 1 DOWNTO 8 * i) /= cmp_data(8 * (i + 1) - 1 DOWNTO 8 * i))) ELSE '0';
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
error_byte_r1 <= (others => '0');
data_error <= '0';
ELSE
error_byte_r1 <= error_byte;
--FOR i IN 0 TO DWIDTH - 1 LOOP
-- data_error <= error_byte_r1(i) OR data_error;
--END LOOP;
data_error <= REDUCTION_OR(error_byte_r1);--error_byte_r1(i) OR data_error;
--synthesis translate_off
IF (data_error = '1') THEN
report "DATA ERROR"; -- severity ERROR;
end if;
--synthesis translate_on
END IF;
end if;
end process;
gen_dq_error_map: FOR i IN 0 to DQ_ERROR_WIDTH - 1 generate
dq_lane_error(i) <= (error_byte_r1(i) OR error_byte_r1(i+DQ_ERROR_WIDTH) OR
error_byte_r1(i+ (NUM_DQ_PINS*2/8)) OR
error_byte_r1(i+ (NUM_DQ_PINS*3/8)));
cumlative_dq_lane_error_c(i) <= cumlative_dq_lane_error_reg(i) OR dq_lane_error_r1(i);
end generate;
process (clk_i)
begin
IF (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
dq_lane_error_r1 <= (others => '0');
dq_lane_error_r2 <= (others => '0');
data_valid_r <= '0';
cumlative_dq_lane_error_reg <= (others => '0');
ELSE
data_valid_r <= data_valid_i;
dq_lane_error_r1 <= dq_lane_error;
cumlative_dq_lane_error_reg <= cumlative_dq_lane_error_c;
END IF;
END IF;
end process;
end generate;
cumlative_dq_lane_error_r <= cumlative_dq_lane_error_reg;
dq_error_bytelane_cmp <= dq_lane_error_r1;
data_error_o <= data_error;
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: read_data_path.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This is top level of read path and also consist of comparison logic
-- for read data.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
entity read_data_path is
generic (
TCQ : time := 100 ps;
FAMILY : string := "VIRTEX6";
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : integer := 32;
CMP_DATA_PIPE_STAGES : integer := 3;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
DQ_ERROR_WIDTH : integer := 1;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
MEM_COL_WIDTH : integer := 10
);
port (
clk_i : in std_logic;
manual_clear_error : in std_logic;
rst_i : in std_logic_vector(9 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
cmd_sent : in std_logic_vector(2 downto 0);
bl_sent : in std_logic_vector(5 downto 0);
cmd_en_i : in std_logic;
-- m_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(31 downto 0);
bl_i : in std_logic_vector(5 downto 0);
-- input [5:0] port_data_counts_i,// connect to data port fifo counts
data_rdy_o : out std_logic;
data_valid_i : in std_logic;
data_i : in std_logic_vector(DWIDTH - 1 downto 0);
last_word_rd_o : out std_logic;
data_error_o : out std_logic;
cmp_data_o : out std_logic_vector(DWIDTH - 1 downto 0);
rd_mdata_o : out std_logic_vector(DWIDTH - 1 downto 0);
cmp_data_valid : out std_logic;
cmp_addr_o : out std_logic_vector(31 downto 0);
cmp_bl_o : out std_logic_vector(5 downto 0);
force_wrcmd_gen_o : out std_logic;
rd_buff_avail_o : out std_logic_vector(6 downto 0);
dq_error_bytelane_cmp : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
cumlative_dq_lane_error_r : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0)
);
end entity read_data_path;
architecture trans of read_data_path is
function REDUCTION_OR( A: in std_logic_vector) return std_logic is
variable tmp : std_logic := '0';
begin
for i in A'range loop
tmp := tmp or A(i);
end loop;
return tmp;
end function REDUCTION_OR;
COMPONENT read_posted_fifo IS
GENERIC (
TCQ : time := 100 ps;
MEM_BURST_LEN : integer := 4;
FAMILY : STRING := "SPARTAN6";
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
data_valid_i : IN STD_LOGIC;
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
user_bl_cnt_is_1 : IN STD_LOGIC;
cmd_sent : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
bl_sent : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
cmd_en_i : IN STD_LOGIC;
gen_rdy_i : IN STD_LOGIC;
gen_valid_o : OUT STD_LOGIC;
gen_addr_o : OUT STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
gen_bl_o : OUT STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
rd_buff_avail_o : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
rd_mdata_fifo_empty : IN STD_LOGIC;
rd_mdata_en : OUT STD_LOGIC
);
END COMPONENT;
component rd_data_gen is
generic (
FAMILY : string := "SPARTAN6";
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : integer := 32;
BL_WIDTH : integer := 6;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_PRBS";
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3;
COLUMN_WIDTH : integer := 10
);
port (
clk_i : in std_logic;
rst_i : in std_logic_vector(4 downto 0);
prbs_fseed_i : in std_logic_vector(31 downto 0);
rd_mdata_en : in std_logic;
data_mode_i : in std_logic_vector(3 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
last_word_o : out std_logic;
-- m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
bl_i : in std_logic_vector(BL_WIDTH - 1 downto 0);
user_bl_cnt_is_1_o : out std_logic;
data_rdy_i : in std_logic;
data_valid_o : out std_logic;
data_o : out std_logic_vector(DWIDTH - 1 downto 0)
);
end component;
component afifo IS
GENERIC (
DSIZE : INTEGER := 32;
FIFO_DEPTH : INTEGER := 16;
ASIZE : INTEGER := 5;
SYNC : INTEGER := 1
);
PORT (
wr_clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
wr_en : IN STD_LOGIC;
wr_data : IN STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
rd_en : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_data : OUT STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
almost_full : OUT STD_LOGIC;
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END component;
signal gen_rdy : std_logic;
signal gen_valid : std_logic;
signal gen_addr : std_logic_vector(31 downto 0);
signal gen_bl : std_logic_vector(5 downto 0);
signal cmp_rdy : std_logic;
signal cmp_valid : std_logic;
signal cmp_addr : std_logic_vector(31 downto 0);
signal cmp_bl : std_logic_vector(5 downto 0);
signal data_error : std_logic;
signal cmp_data : std_logic_vector(DWIDTH - 1 downto 0);
signal last_word_rd : std_logic;
signal bl_counter : std_logic_vector(5 downto 0);
signal cmd_rdy : std_logic;
signal user_bl_cnt_is_1 : std_logic;
signal data_rdy : std_logic;
signal delayed_data : std_logic_vector(DWIDTH downto 0);
-- signal cmp_data_piped : std_logic_vector(DWIDTH downto 0);
signal cmp_data_r : std_logic_vector(DWIDTH-1 downto 0);
signal rd_mdata_en : std_logic;
signal rd_data_r : std_logic_vector(DWIDTH - 1 downto 0);
signal force_wrcmd_gen : std_logic;
signal wait_bl_end : std_logic;
signal wait_bl_end_r1 : std_logic;
signal v6_data_cmp_valid : std_logic;
signal rd_v6_mdata : std_logic_vector(DWIDTH-1 downto 0);
signal cmpdata_r : std_logic_vector(DWIDTH-1 downto 0);
signal rd_mdata : std_logic_vector(DWIDTH-1 downto 0);
signal l_data_error : std_logic;
signal u_data_error : std_logic;
signal cmp_data_en : std_logic;
signal force_wrcmd_timeout_cnts : std_logic_vector(7 downto 0);
signal error_byte : std_logic_vector(NUM_DQ_PINS / 2 - 1 downto 0);
signal error_byte_r1 : std_logic_vector(NUM_DQ_PINS / 2 - 1 downto 0);
signal dq_lane_error : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal dq_lane_error_r1 : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal dq_lane_error_r2 : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cum_dq_lane_error_mask : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cumlative_dq_lane_error_reg : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cumlative_dq_lane_error_c : std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
signal rd_mdata_fifo_empty : std_logic;
signal data_valid_r : std_logic;
-- Declare intermediate signals for referenced outputs
-- SIGNAL xhdl2 : STD_LOGIC_VECTOR(DWIDTH DOWNTO 0);
-- SIGNAL tmp_sig : STD_LOGIC;
signal last_word_rd_o_xhdl0 : std_logic;
signal rd_buff_avail_o_xhdl1 : std_logic_vector(6 downto 0);
begin
-- Drive referenced outputs
last_word_rd_o <= last_word_rd_o_xhdl0;
rd_buff_avail_o <= rd_buff_avail_o_xhdl1;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
wait_bl_end_r1 <= wait_bl_end;
rd_data_r <= data_i;
end if;
end process;
force_wrcmd_gen_o <= force_wrcmd_gen;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
force_wrcmd_gen <= '0';
elsif ((wait_bl_end = '0' and wait_bl_end_r1 = '1') or force_wrcmd_timeout_cnts = "11111111") then
force_wrcmd_gen <= '0';
elsif ((cmd_valid_i = '1' and bl_i > "010000") or wait_bl_end = '1') then
force_wrcmd_gen <= '1';
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
force_wrcmd_timeout_cnts <= "00000000";
elsif (wait_bl_end = '0' and wait_bl_end_r1 = '1') then
force_wrcmd_timeout_cnts <= "00000000";
elsif (force_wrcmd_gen = '1') then
force_wrcmd_timeout_cnts <= force_wrcmd_timeout_cnts + "00000001";
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
wait_bl_end <= '0';
elsif (force_wrcmd_timeout_cnts = "11111111") then
wait_bl_end <= '0';
elsif ((gen_rdy and gen_valid) = '1' and gen_bl > "010000") then
wait_bl_end <= '1';
elsif ((wait_bl_end and user_bl_cnt_is_1) = '1') then
wait_bl_end <= '0';
end if;
end if;
end process;
cmd_rdy_o <= cmd_rdy;
read_postedfifo : read_posted_fifo
GENERIC MAP (
TCQ => TCQ,
FAMILY => FAMILY,
MEM_BURST_LEN => MEM_BURST_LEN,
ADDR_WIDTH => 32,
BL_WIDTH => 6
)
port map (
clk_i => clk_i,
rst_i => rst_i(0),
cmd_rdy_o => cmd_rdy,
cmd_valid_i => cmd_valid_i,
data_valid_i => data_rdy,
addr_i => addr_i,
bl_i => bl_i,
cmd_sent => cmd_sent,
bl_sent => bl_sent,
cmd_en_i => cmd_en_i,
user_bl_cnt_is_1 => user_bl_cnt_is_1,
gen_rdy_i => gen_rdy,
gen_valid_o => gen_valid,
gen_addr_o => gen_addr,
gen_bl_o => gen_bl,
rd_buff_avail_o => rd_buff_avail_o_xhdl1,
rd_mdata_fifo_empty => rd_mdata_fifo_empty,
rd_mdata_en => rd_mdata_en
);
rd_datagen : rd_data_gen
generic map (
FAMILY => FAMILY,
MEM_BURST_LEN => MEM_BURST_LEN,
NUM_DQ_PINS => NUM_DQ_PINS,
SEL_VICTIM_LINE => SEL_VICTIM_LINE,
DATA_PATTERN => DATA_PATTERN,
DWIDTH => DWIDTH,
COLUMN_WIDTH => MEM_COL_WIDTH
)
port map (
clk_i => clk_i,
rst_i => rst_i(4 downto 0),
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_rdy_o => gen_rdy,
cmd_valid_i => gen_valid,
last_word_o => last_word_rd_o_xhdl0,
-- m_addr_i => m_addr_i,
fixed_data_i => fixed_data_i,
addr_i => gen_addr,
bl_i => gen_bl,
user_bl_cnt_is_1_o => user_bl_cnt_is_1,
data_rdy_i => data_valid_i,
data_valid_o => cmp_valid,
data_o => cmp_data,
rd_mdata_en => rd_mdata_en
);
rd_mdata_fifo : afifo
GENERIC MAP (
DSIZE => DWIDTH,
FIFO_DEPTH => 32,
ASIZE => 5,
SYNC => 1
)
PORT MAP (
wr_clk => clk_i,
rst => rst_i(0),
wr_en => data_valid_i,
wr_data => data_i,
rd_en => rd_mdata_en,
rd_clk => clk_i,
rd_data => rd_v6_mdata,
full => open,
empty => rd_mdata_fifo_empty,
almost_full => open
);
-- tmp_sig <= cmp_valid AND data_valid_i;
-- xhdl2 <= ( tmp_sig & cmp_data);
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
-- delayed_data <= (tmp_sig & cmp_data);
cmp_data_r <= cmp_data;
end if;
end process;
rd_mdata_o <= rd_mdata;
rd_mdata <= rd_data_r WHEN (FAMILY = "SPARTAN6") ELSE rd_v6_mdata
WHEN ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) ELSE data_i;
cmp_data_valid <= cmp_data_en WHEN (FAMILY = "SPARTAN6") ELSE v6_data_cmp_valid
WHEN ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) ELSE data_valid_i;
cmp_data_o <= cmp_data_r;
cmp_addr_o <= gen_addr;
cmp_bl_o <= gen_bl;
-- xhdl4 : if (FAMILY = "SPARTAN6") generate
-- rd_data_o <= rd_data_r;
-- end generate;
-- xhdl5 : if (FAMILY /= "SPARTAN6") generate
-- rd_data_o <= data_i;
-- end generate;
data_rdy_o <= data_rdy;
data_rdy <= cmp_valid and data_valid_i;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
v6_data_cmp_valid <= rd_mdata_en;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
cmp_data_en <= data_rdy;
end if;
end process;
xhdl6 : if (FAMILY = "SPARTAN6") generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (cmp_data_en = '1') then
IF ((rd_data_r(DWIDTH / 2 - 1 downto 0) /= cmp_data_r(DWIDTH / 2 - 1 downto 0))) then
l_data_error <= '1' ;
ELSE
l_data_error <= '0' ;
END IF;
else
l_data_error <= '0' ;
end if;
if (cmp_data_en = '1') then
IF ((rd_data_r(DWIDTH - 1 downto DWIDTH / 2) /= cmp_data_r(DWIDTH - 1 downto DWIDTH / 2))) then
u_data_error <= '1' ;
ELSE
u_data_error <= '0' ;
END IF;
else
u_data_error <= '0' ;
end if;
data_error <= l_data_error or u_data_error;
--synthesis translate_off
if (data_error = '1') then
report ("DATA ERROR");
end if;
--synthesis translate_on
end if;
end process;
end generate;
gen_error_2 : if ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) generate
gen_cmp : FOR i IN 0 TO NUM_DQ_PINS / 2 - 1 GENERATE
error_byte(i) <= '1' WHEN (rd_mdata_fifo_empty = '0' AND rd_mdata_en = '1' AND (rd_v6_mdata(8 * (i + 1) - 1 DOWNTO 8 * i) /= cmp_data(8 * (i + 1) - 1 DOWNTO 8 * i))) ELSE '0';
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
error_byte_r1 <= (others => '0');
data_error <= '0';
ELSE
error_byte_r1 <= error_byte;
-- FOR i IN 0 TO DWIDTH - 1 LOOP
data_error <= REDUCTION_OR(error_byte_r1);--error_byte_r1(i) OR data_error;
-- END LOOP;
END IF;
end if;
end process;
process (data_error)
begin
--synthesis translate_off
IF (data_error = '1') THEN
report "DATA ERROR"; -- severity ERROR;
END IF;
--synthesis translate_on
end process;
gen_dq_error_map: FOR i IN 0 to DQ_ERROR_WIDTH - 1 generate
dq_lane_error(i) <= (error_byte_r1(i) OR error_byte_r1(i+DQ_ERROR_WIDTH) OR
error_byte_r1(i+ (NUM_DQ_PINS*2/8)) OR
error_byte_r1(i+ (NUM_DQ_PINS*3/8)));
cumlative_dq_lane_error_c(i) <= cumlative_dq_lane_error_reg(i) OR dq_lane_error_r1(i);
end generate;
process (clk_i)
begin
IF (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
dq_lane_error_r1 <= (others => '0');
dq_lane_error_r2 <= (others => '0');
data_valid_r <= '0';
cumlative_dq_lane_error_reg <= (others => '0');
ELSE
data_valid_r <= data_valid_i;
dq_lane_error_r1 <= dq_lane_error;
cumlative_dq_lane_error_reg <= cumlative_dq_lane_error_c;
END IF;
END IF;
end process;
end generate;
xhdl8 : if ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 8)) generate
gen_cmp_8 : FOR i IN 0 TO NUM_DQ_PINS / 2 - 1 GENERATE
error_byte(i) <= '1' WHEN (data_valid_i = '1' AND (data_i(8 * (i + 1) - 1 DOWNTO 8 * i) /= cmp_data(8 * (i + 1) - 1 DOWNTO 8 * i))) ELSE '0';
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
error_byte_r1 <= (others => '0');
data_error <= '0';
ELSE
error_byte_r1 <= error_byte;
--FOR i IN 0 TO DWIDTH - 1 LOOP
-- data_error <= error_byte_r1(i) OR data_error;
--END LOOP;
data_error <= REDUCTION_OR(error_byte_r1);--error_byte_r1(i) OR data_error;
--synthesis translate_off
IF (data_error = '1') THEN
report "DATA ERROR"; -- severity ERROR;
end if;
--synthesis translate_on
END IF;
end if;
end process;
gen_dq_error_map: FOR i IN 0 to DQ_ERROR_WIDTH - 1 generate
dq_lane_error(i) <= (error_byte_r1(i) OR error_byte_r1(i+DQ_ERROR_WIDTH) OR
error_byte_r1(i+ (NUM_DQ_PINS*2/8)) OR
error_byte_r1(i+ (NUM_DQ_PINS*3/8)));
cumlative_dq_lane_error_c(i) <= cumlative_dq_lane_error_reg(i) OR dq_lane_error_r1(i);
end generate;
process (clk_i)
begin
IF (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
dq_lane_error_r1 <= (others => '0');
dq_lane_error_r2 <= (others => '0');
data_valid_r <= '0';
cumlative_dq_lane_error_reg <= (others => '0');
ELSE
data_valid_r <= data_valid_i;
dq_lane_error_r1 <= dq_lane_error;
cumlative_dq_lane_error_reg <= cumlative_dq_lane_error_c;
END IF;
END IF;
end process;
end generate;
cumlative_dq_lane_error_r <= cumlative_dq_lane_error_reg;
dq_error_bytelane_cmp <= dq_lane_error_r1;
data_error_o <= data_error;
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: read_data_path.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This is top level of read path and also consist of comparison logic
-- for read data.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
entity read_data_path is
generic (
TCQ : time := 100 ps;
FAMILY : string := "VIRTEX6";
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : integer := 32;
CMP_DATA_PIPE_STAGES : integer := 3;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
DQ_ERROR_WIDTH : integer := 1;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
MEM_COL_WIDTH : integer := 10
);
port (
clk_i : in std_logic;
manual_clear_error : in std_logic;
rst_i : in std_logic_vector(9 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
cmd_sent : in std_logic_vector(2 downto 0);
bl_sent : in std_logic_vector(5 downto 0);
cmd_en_i : in std_logic;
-- m_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(31 downto 0);
bl_i : in std_logic_vector(5 downto 0);
-- input [5:0] port_data_counts_i,// connect to data port fifo counts
data_rdy_o : out std_logic;
data_valid_i : in std_logic;
data_i : in std_logic_vector(DWIDTH - 1 downto 0);
last_word_rd_o : out std_logic;
data_error_o : out std_logic;
cmp_data_o : out std_logic_vector(DWIDTH - 1 downto 0);
rd_mdata_o : out std_logic_vector(DWIDTH - 1 downto 0);
cmp_data_valid : out std_logic;
cmp_addr_o : out std_logic_vector(31 downto 0);
cmp_bl_o : out std_logic_vector(5 downto 0);
force_wrcmd_gen_o : out std_logic;
rd_buff_avail_o : out std_logic_vector(6 downto 0);
dq_error_bytelane_cmp : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
cumlative_dq_lane_error_r : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0)
);
end entity read_data_path;
architecture trans of read_data_path is
function REDUCTION_OR( A: in std_logic_vector) return std_logic is
variable tmp : std_logic := '0';
begin
for i in A'range loop
tmp := tmp or A(i);
end loop;
return tmp;
end function REDUCTION_OR;
COMPONENT read_posted_fifo IS
GENERIC (
TCQ : time := 100 ps;
MEM_BURST_LEN : integer := 4;
FAMILY : STRING := "SPARTAN6";
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
data_valid_i : IN STD_LOGIC;
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
user_bl_cnt_is_1 : IN STD_LOGIC;
cmd_sent : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
bl_sent : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
cmd_en_i : IN STD_LOGIC;
gen_rdy_i : IN STD_LOGIC;
gen_valid_o : OUT STD_LOGIC;
gen_addr_o : OUT STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
gen_bl_o : OUT STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
rd_buff_avail_o : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
rd_mdata_fifo_empty : IN STD_LOGIC;
rd_mdata_en : OUT STD_LOGIC
);
END COMPONENT;
component rd_data_gen is
generic (
FAMILY : string := "SPARTAN6";
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : integer := 32;
BL_WIDTH : integer := 6;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_PRBS";
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3;
COLUMN_WIDTH : integer := 10
);
port (
clk_i : in std_logic;
rst_i : in std_logic_vector(4 downto 0);
prbs_fseed_i : in std_logic_vector(31 downto 0);
rd_mdata_en : in std_logic;
data_mode_i : in std_logic_vector(3 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
last_word_o : out std_logic;
-- m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
bl_i : in std_logic_vector(BL_WIDTH - 1 downto 0);
user_bl_cnt_is_1_o : out std_logic;
data_rdy_i : in std_logic;
data_valid_o : out std_logic;
data_o : out std_logic_vector(DWIDTH - 1 downto 0)
);
end component;
component afifo IS
GENERIC (
DSIZE : INTEGER := 32;
FIFO_DEPTH : INTEGER := 16;
ASIZE : INTEGER := 5;
SYNC : INTEGER := 1
);
PORT (
wr_clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
wr_en : IN STD_LOGIC;
wr_data : IN STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
rd_en : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_data : OUT STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
almost_full : OUT STD_LOGIC;
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END component;
signal gen_rdy : std_logic;
signal gen_valid : std_logic;
signal gen_addr : std_logic_vector(31 downto 0);
signal gen_bl : std_logic_vector(5 downto 0);
signal cmp_rdy : std_logic;
signal cmp_valid : std_logic;
signal cmp_addr : std_logic_vector(31 downto 0);
signal cmp_bl : std_logic_vector(5 downto 0);
signal data_error : std_logic;
signal cmp_data : std_logic_vector(DWIDTH - 1 downto 0);
signal last_word_rd : std_logic;
signal bl_counter : std_logic_vector(5 downto 0);
signal cmd_rdy : std_logic;
signal user_bl_cnt_is_1 : std_logic;
signal data_rdy : std_logic;
signal delayed_data : std_logic_vector(DWIDTH downto 0);
-- signal cmp_data_piped : std_logic_vector(DWIDTH downto 0);
signal cmp_data_r : std_logic_vector(DWIDTH-1 downto 0);
signal rd_mdata_en : std_logic;
signal rd_data_r : std_logic_vector(DWIDTH - 1 downto 0);
signal force_wrcmd_gen : std_logic;
signal wait_bl_end : std_logic;
signal wait_bl_end_r1 : std_logic;
signal v6_data_cmp_valid : std_logic;
signal rd_v6_mdata : std_logic_vector(DWIDTH-1 downto 0);
signal cmpdata_r : std_logic_vector(DWIDTH-1 downto 0);
signal rd_mdata : std_logic_vector(DWIDTH-1 downto 0);
signal l_data_error : std_logic;
signal u_data_error : std_logic;
signal cmp_data_en : std_logic;
signal force_wrcmd_timeout_cnts : std_logic_vector(7 downto 0);
signal error_byte : std_logic_vector(NUM_DQ_PINS / 2 - 1 downto 0);
signal error_byte_r1 : std_logic_vector(NUM_DQ_PINS / 2 - 1 downto 0);
signal dq_lane_error : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal dq_lane_error_r1 : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal dq_lane_error_r2 : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cum_dq_lane_error_mask : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cumlative_dq_lane_error_reg : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cumlative_dq_lane_error_c : std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
signal rd_mdata_fifo_empty : std_logic;
signal data_valid_r : std_logic;
-- Declare intermediate signals for referenced outputs
-- SIGNAL xhdl2 : STD_LOGIC_VECTOR(DWIDTH DOWNTO 0);
-- SIGNAL tmp_sig : STD_LOGIC;
signal last_word_rd_o_xhdl0 : std_logic;
signal rd_buff_avail_o_xhdl1 : std_logic_vector(6 downto 0);
begin
-- Drive referenced outputs
last_word_rd_o <= last_word_rd_o_xhdl0;
rd_buff_avail_o <= rd_buff_avail_o_xhdl1;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
wait_bl_end_r1 <= wait_bl_end;
rd_data_r <= data_i;
end if;
end process;
force_wrcmd_gen_o <= force_wrcmd_gen;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
force_wrcmd_gen <= '0';
elsif ((wait_bl_end = '0' and wait_bl_end_r1 = '1') or force_wrcmd_timeout_cnts = "11111111") then
force_wrcmd_gen <= '0';
elsif ((cmd_valid_i = '1' and bl_i > "010000") or wait_bl_end = '1') then
force_wrcmd_gen <= '1';
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
force_wrcmd_timeout_cnts <= "00000000";
elsif (wait_bl_end = '0' and wait_bl_end_r1 = '1') then
force_wrcmd_timeout_cnts <= "00000000";
elsif (force_wrcmd_gen = '1') then
force_wrcmd_timeout_cnts <= force_wrcmd_timeout_cnts + "00000001";
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
wait_bl_end <= '0';
elsif (force_wrcmd_timeout_cnts = "11111111") then
wait_bl_end <= '0';
elsif ((gen_rdy and gen_valid) = '1' and gen_bl > "010000") then
wait_bl_end <= '1';
elsif ((wait_bl_end and user_bl_cnt_is_1) = '1') then
wait_bl_end <= '0';
end if;
end if;
end process;
cmd_rdy_o <= cmd_rdy;
read_postedfifo : read_posted_fifo
GENERIC MAP (
TCQ => TCQ,
FAMILY => FAMILY,
MEM_BURST_LEN => MEM_BURST_LEN,
ADDR_WIDTH => 32,
BL_WIDTH => 6
)
port map (
clk_i => clk_i,
rst_i => rst_i(0),
cmd_rdy_o => cmd_rdy,
cmd_valid_i => cmd_valid_i,
data_valid_i => data_rdy,
addr_i => addr_i,
bl_i => bl_i,
cmd_sent => cmd_sent,
bl_sent => bl_sent,
cmd_en_i => cmd_en_i,
user_bl_cnt_is_1 => user_bl_cnt_is_1,
gen_rdy_i => gen_rdy,
gen_valid_o => gen_valid,
gen_addr_o => gen_addr,
gen_bl_o => gen_bl,
rd_buff_avail_o => rd_buff_avail_o_xhdl1,
rd_mdata_fifo_empty => rd_mdata_fifo_empty,
rd_mdata_en => rd_mdata_en
);
rd_datagen : rd_data_gen
generic map (
FAMILY => FAMILY,
MEM_BURST_LEN => MEM_BURST_LEN,
NUM_DQ_PINS => NUM_DQ_PINS,
SEL_VICTIM_LINE => SEL_VICTIM_LINE,
DATA_PATTERN => DATA_PATTERN,
DWIDTH => DWIDTH,
COLUMN_WIDTH => MEM_COL_WIDTH
)
port map (
clk_i => clk_i,
rst_i => rst_i(4 downto 0),
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_rdy_o => gen_rdy,
cmd_valid_i => gen_valid,
last_word_o => last_word_rd_o_xhdl0,
-- m_addr_i => m_addr_i,
fixed_data_i => fixed_data_i,
addr_i => gen_addr,
bl_i => gen_bl,
user_bl_cnt_is_1_o => user_bl_cnt_is_1,
data_rdy_i => data_valid_i,
data_valid_o => cmp_valid,
data_o => cmp_data,
rd_mdata_en => rd_mdata_en
);
rd_mdata_fifo : afifo
GENERIC MAP (
DSIZE => DWIDTH,
FIFO_DEPTH => 32,
ASIZE => 5,
SYNC => 1
)
PORT MAP (
wr_clk => clk_i,
rst => rst_i(0),
wr_en => data_valid_i,
wr_data => data_i,
rd_en => rd_mdata_en,
rd_clk => clk_i,
rd_data => rd_v6_mdata,
full => open,
empty => rd_mdata_fifo_empty,
almost_full => open
);
-- tmp_sig <= cmp_valid AND data_valid_i;
-- xhdl2 <= ( tmp_sig & cmp_data);
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
-- delayed_data <= (tmp_sig & cmp_data);
cmp_data_r <= cmp_data;
end if;
end process;
rd_mdata_o <= rd_mdata;
rd_mdata <= rd_data_r WHEN (FAMILY = "SPARTAN6") ELSE rd_v6_mdata
WHEN ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) ELSE data_i;
cmp_data_valid <= cmp_data_en WHEN (FAMILY = "SPARTAN6") ELSE v6_data_cmp_valid
WHEN ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) ELSE data_valid_i;
cmp_data_o <= cmp_data_r;
cmp_addr_o <= gen_addr;
cmp_bl_o <= gen_bl;
-- xhdl4 : if (FAMILY = "SPARTAN6") generate
-- rd_data_o <= rd_data_r;
-- end generate;
-- xhdl5 : if (FAMILY /= "SPARTAN6") generate
-- rd_data_o <= data_i;
-- end generate;
data_rdy_o <= data_rdy;
data_rdy <= cmp_valid and data_valid_i;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
v6_data_cmp_valid <= rd_mdata_en;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
cmp_data_en <= data_rdy;
end if;
end process;
xhdl6 : if (FAMILY = "SPARTAN6") generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (cmp_data_en = '1') then
IF ((rd_data_r(DWIDTH / 2 - 1 downto 0) /= cmp_data_r(DWIDTH / 2 - 1 downto 0))) then
l_data_error <= '1' ;
ELSE
l_data_error <= '0' ;
END IF;
else
l_data_error <= '0' ;
end if;
if (cmp_data_en = '1') then
IF ((rd_data_r(DWIDTH - 1 downto DWIDTH / 2) /= cmp_data_r(DWIDTH - 1 downto DWIDTH / 2))) then
u_data_error <= '1' ;
ELSE
u_data_error <= '0' ;
END IF;
else
u_data_error <= '0' ;
end if;
data_error <= l_data_error or u_data_error;
--synthesis translate_off
if (data_error = '1') then
report ("DATA ERROR");
end if;
--synthesis translate_on
end if;
end process;
end generate;
gen_error_2 : if ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) generate
gen_cmp : FOR i IN 0 TO NUM_DQ_PINS / 2 - 1 GENERATE
error_byte(i) <= '1' WHEN (rd_mdata_fifo_empty = '0' AND rd_mdata_en = '1' AND (rd_v6_mdata(8 * (i + 1) - 1 DOWNTO 8 * i) /= cmp_data(8 * (i + 1) - 1 DOWNTO 8 * i))) ELSE '0';
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
error_byte_r1 <= (others => '0');
data_error <= '0';
ELSE
error_byte_r1 <= error_byte;
-- FOR i IN 0 TO DWIDTH - 1 LOOP
data_error <= REDUCTION_OR(error_byte_r1);--error_byte_r1(i) OR data_error;
-- END LOOP;
END IF;
end if;
end process;
process (data_error)
begin
--synthesis translate_off
IF (data_error = '1') THEN
report "DATA ERROR"; -- severity ERROR;
END IF;
--synthesis translate_on
end process;
gen_dq_error_map: FOR i IN 0 to DQ_ERROR_WIDTH - 1 generate
dq_lane_error(i) <= (error_byte_r1(i) OR error_byte_r1(i+DQ_ERROR_WIDTH) OR
error_byte_r1(i+ (NUM_DQ_PINS*2/8)) OR
error_byte_r1(i+ (NUM_DQ_PINS*3/8)));
cumlative_dq_lane_error_c(i) <= cumlative_dq_lane_error_reg(i) OR dq_lane_error_r1(i);
end generate;
process (clk_i)
begin
IF (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
dq_lane_error_r1 <= (others => '0');
dq_lane_error_r2 <= (others => '0');
data_valid_r <= '0';
cumlative_dq_lane_error_reg <= (others => '0');
ELSE
data_valid_r <= data_valid_i;
dq_lane_error_r1 <= dq_lane_error;
cumlative_dq_lane_error_reg <= cumlative_dq_lane_error_c;
END IF;
END IF;
end process;
end generate;
xhdl8 : if ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 8)) generate
gen_cmp_8 : FOR i IN 0 TO NUM_DQ_PINS / 2 - 1 GENERATE
error_byte(i) <= '1' WHEN (data_valid_i = '1' AND (data_i(8 * (i + 1) - 1 DOWNTO 8 * i) /= cmp_data(8 * (i + 1) - 1 DOWNTO 8 * i))) ELSE '0';
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
error_byte_r1 <= (others => '0');
data_error <= '0';
ELSE
error_byte_r1 <= error_byte;
--FOR i IN 0 TO DWIDTH - 1 LOOP
-- data_error <= error_byte_r1(i) OR data_error;
--END LOOP;
data_error <= REDUCTION_OR(error_byte_r1);--error_byte_r1(i) OR data_error;
--synthesis translate_off
IF (data_error = '1') THEN
report "DATA ERROR"; -- severity ERROR;
end if;
--synthesis translate_on
END IF;
end if;
end process;
gen_dq_error_map: FOR i IN 0 to DQ_ERROR_WIDTH - 1 generate
dq_lane_error(i) <= (error_byte_r1(i) OR error_byte_r1(i+DQ_ERROR_WIDTH) OR
error_byte_r1(i+ (NUM_DQ_PINS*2/8)) OR
error_byte_r1(i+ (NUM_DQ_PINS*3/8)));
cumlative_dq_lane_error_c(i) <= cumlative_dq_lane_error_reg(i) OR dq_lane_error_r1(i);
end generate;
process (clk_i)
begin
IF (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
dq_lane_error_r1 <= (others => '0');
dq_lane_error_r2 <= (others => '0');
data_valid_r <= '0';
cumlative_dq_lane_error_reg <= (others => '0');
ELSE
data_valid_r <= data_valid_i;
dq_lane_error_r1 <= dq_lane_error;
cumlative_dq_lane_error_reg <= cumlative_dq_lane_error_c;
END IF;
END IF;
end process;
end generate;
cumlative_dq_lane_error_r <= cumlative_dq_lane_error_reg;
dq_error_bytelane_cmp <= dq_lane_error_r1;
data_error_o <= data_error;
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: read_data_path.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This is top level of read path and also consist of comparison logic
-- for read data.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
entity read_data_path is
generic (
TCQ : time := 100 ps;
FAMILY : string := "VIRTEX6";
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : integer := 32;
CMP_DATA_PIPE_STAGES : integer := 3;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
DQ_ERROR_WIDTH : integer := 1;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
MEM_COL_WIDTH : integer := 10
);
port (
clk_i : in std_logic;
manual_clear_error : in std_logic;
rst_i : in std_logic_vector(9 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
cmd_sent : in std_logic_vector(2 downto 0);
bl_sent : in std_logic_vector(5 downto 0);
cmd_en_i : in std_logic;
-- m_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(31 downto 0);
bl_i : in std_logic_vector(5 downto 0);
-- input [5:0] port_data_counts_i,// connect to data port fifo counts
data_rdy_o : out std_logic;
data_valid_i : in std_logic;
data_i : in std_logic_vector(DWIDTH - 1 downto 0);
last_word_rd_o : out std_logic;
data_error_o : out std_logic;
cmp_data_o : out std_logic_vector(DWIDTH - 1 downto 0);
rd_mdata_o : out std_logic_vector(DWIDTH - 1 downto 0);
cmp_data_valid : out std_logic;
cmp_addr_o : out std_logic_vector(31 downto 0);
cmp_bl_o : out std_logic_vector(5 downto 0);
force_wrcmd_gen_o : out std_logic;
rd_buff_avail_o : out std_logic_vector(6 downto 0);
dq_error_bytelane_cmp : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
cumlative_dq_lane_error_r : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0)
);
end entity read_data_path;
architecture trans of read_data_path is
function REDUCTION_OR( A: in std_logic_vector) return std_logic is
variable tmp : std_logic := '0';
begin
for i in A'range loop
tmp := tmp or A(i);
end loop;
return tmp;
end function REDUCTION_OR;
COMPONENT read_posted_fifo IS
GENERIC (
TCQ : time := 100 ps;
MEM_BURST_LEN : integer := 4;
FAMILY : STRING := "SPARTAN6";
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
data_valid_i : IN STD_LOGIC;
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
user_bl_cnt_is_1 : IN STD_LOGIC;
cmd_sent : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
bl_sent : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
cmd_en_i : IN STD_LOGIC;
gen_rdy_i : IN STD_LOGIC;
gen_valid_o : OUT STD_LOGIC;
gen_addr_o : OUT STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
gen_bl_o : OUT STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
rd_buff_avail_o : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
rd_mdata_fifo_empty : IN STD_LOGIC;
rd_mdata_en : OUT STD_LOGIC
);
END COMPONENT;
component rd_data_gen is
generic (
FAMILY : string := "SPARTAN6";
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : integer := 32;
BL_WIDTH : integer := 6;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_PRBS";
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3;
COLUMN_WIDTH : integer := 10
);
port (
clk_i : in std_logic;
rst_i : in std_logic_vector(4 downto 0);
prbs_fseed_i : in std_logic_vector(31 downto 0);
rd_mdata_en : in std_logic;
data_mode_i : in std_logic_vector(3 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
last_word_o : out std_logic;
-- m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
bl_i : in std_logic_vector(BL_WIDTH - 1 downto 0);
user_bl_cnt_is_1_o : out std_logic;
data_rdy_i : in std_logic;
data_valid_o : out std_logic;
data_o : out std_logic_vector(DWIDTH - 1 downto 0)
);
end component;
component afifo IS
GENERIC (
DSIZE : INTEGER := 32;
FIFO_DEPTH : INTEGER := 16;
ASIZE : INTEGER := 5;
SYNC : INTEGER := 1
);
PORT (
wr_clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
wr_en : IN STD_LOGIC;
wr_data : IN STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
rd_en : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_data : OUT STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
almost_full : OUT STD_LOGIC;
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END component;
signal gen_rdy : std_logic;
signal gen_valid : std_logic;
signal gen_addr : std_logic_vector(31 downto 0);
signal gen_bl : std_logic_vector(5 downto 0);
signal cmp_rdy : std_logic;
signal cmp_valid : std_logic;
signal cmp_addr : std_logic_vector(31 downto 0);
signal cmp_bl : std_logic_vector(5 downto 0);
signal data_error : std_logic;
signal cmp_data : std_logic_vector(DWIDTH - 1 downto 0);
signal last_word_rd : std_logic;
signal bl_counter : std_logic_vector(5 downto 0);
signal cmd_rdy : std_logic;
signal user_bl_cnt_is_1 : std_logic;
signal data_rdy : std_logic;
signal delayed_data : std_logic_vector(DWIDTH downto 0);
-- signal cmp_data_piped : std_logic_vector(DWIDTH downto 0);
signal cmp_data_r : std_logic_vector(DWIDTH-1 downto 0);
signal rd_mdata_en : std_logic;
signal rd_data_r : std_logic_vector(DWIDTH - 1 downto 0);
signal force_wrcmd_gen : std_logic;
signal wait_bl_end : std_logic;
signal wait_bl_end_r1 : std_logic;
signal v6_data_cmp_valid : std_logic;
signal rd_v6_mdata : std_logic_vector(DWIDTH-1 downto 0);
signal cmpdata_r : std_logic_vector(DWIDTH-1 downto 0);
signal rd_mdata : std_logic_vector(DWIDTH-1 downto 0);
signal l_data_error : std_logic;
signal u_data_error : std_logic;
signal cmp_data_en : std_logic;
signal force_wrcmd_timeout_cnts : std_logic_vector(7 downto 0);
signal error_byte : std_logic_vector(NUM_DQ_PINS / 2 - 1 downto 0);
signal error_byte_r1 : std_logic_vector(NUM_DQ_PINS / 2 - 1 downto 0);
signal dq_lane_error : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal dq_lane_error_r1 : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal dq_lane_error_r2 : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cum_dq_lane_error_mask : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cumlative_dq_lane_error_reg : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cumlative_dq_lane_error_c : std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
signal rd_mdata_fifo_empty : std_logic;
signal data_valid_r : std_logic;
-- Declare intermediate signals for referenced outputs
-- SIGNAL xhdl2 : STD_LOGIC_VECTOR(DWIDTH DOWNTO 0);
-- SIGNAL tmp_sig : STD_LOGIC;
signal last_word_rd_o_xhdl0 : std_logic;
signal rd_buff_avail_o_xhdl1 : std_logic_vector(6 downto 0);
begin
-- Drive referenced outputs
last_word_rd_o <= last_word_rd_o_xhdl0;
rd_buff_avail_o <= rd_buff_avail_o_xhdl1;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
wait_bl_end_r1 <= wait_bl_end;
rd_data_r <= data_i;
end if;
end process;
force_wrcmd_gen_o <= force_wrcmd_gen;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
force_wrcmd_gen <= '0';
elsif ((wait_bl_end = '0' and wait_bl_end_r1 = '1') or force_wrcmd_timeout_cnts = "11111111") then
force_wrcmd_gen <= '0';
elsif ((cmd_valid_i = '1' and bl_i > "010000") or wait_bl_end = '1') then
force_wrcmd_gen <= '1';
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
force_wrcmd_timeout_cnts <= "00000000";
elsif (wait_bl_end = '0' and wait_bl_end_r1 = '1') then
force_wrcmd_timeout_cnts <= "00000000";
elsif (force_wrcmd_gen = '1') then
force_wrcmd_timeout_cnts <= force_wrcmd_timeout_cnts + "00000001";
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
wait_bl_end <= '0';
elsif (force_wrcmd_timeout_cnts = "11111111") then
wait_bl_end <= '0';
elsif ((gen_rdy and gen_valid) = '1' and gen_bl > "010000") then
wait_bl_end <= '1';
elsif ((wait_bl_end and user_bl_cnt_is_1) = '1') then
wait_bl_end <= '0';
end if;
end if;
end process;
cmd_rdy_o <= cmd_rdy;
read_postedfifo : read_posted_fifo
GENERIC MAP (
TCQ => TCQ,
FAMILY => FAMILY,
MEM_BURST_LEN => MEM_BURST_LEN,
ADDR_WIDTH => 32,
BL_WIDTH => 6
)
port map (
clk_i => clk_i,
rst_i => rst_i(0),
cmd_rdy_o => cmd_rdy,
cmd_valid_i => cmd_valid_i,
data_valid_i => data_rdy,
addr_i => addr_i,
bl_i => bl_i,
cmd_sent => cmd_sent,
bl_sent => bl_sent,
cmd_en_i => cmd_en_i,
user_bl_cnt_is_1 => user_bl_cnt_is_1,
gen_rdy_i => gen_rdy,
gen_valid_o => gen_valid,
gen_addr_o => gen_addr,
gen_bl_o => gen_bl,
rd_buff_avail_o => rd_buff_avail_o_xhdl1,
rd_mdata_fifo_empty => rd_mdata_fifo_empty,
rd_mdata_en => rd_mdata_en
);
rd_datagen : rd_data_gen
generic map (
FAMILY => FAMILY,
MEM_BURST_LEN => MEM_BURST_LEN,
NUM_DQ_PINS => NUM_DQ_PINS,
SEL_VICTIM_LINE => SEL_VICTIM_LINE,
DATA_PATTERN => DATA_PATTERN,
DWIDTH => DWIDTH,
COLUMN_WIDTH => MEM_COL_WIDTH
)
port map (
clk_i => clk_i,
rst_i => rst_i(4 downto 0),
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_rdy_o => gen_rdy,
cmd_valid_i => gen_valid,
last_word_o => last_word_rd_o_xhdl0,
-- m_addr_i => m_addr_i,
fixed_data_i => fixed_data_i,
addr_i => gen_addr,
bl_i => gen_bl,
user_bl_cnt_is_1_o => user_bl_cnt_is_1,
data_rdy_i => data_valid_i,
data_valid_o => cmp_valid,
data_o => cmp_data,
rd_mdata_en => rd_mdata_en
);
rd_mdata_fifo : afifo
GENERIC MAP (
DSIZE => DWIDTH,
FIFO_DEPTH => 32,
ASIZE => 5,
SYNC => 1
)
PORT MAP (
wr_clk => clk_i,
rst => rst_i(0),
wr_en => data_valid_i,
wr_data => data_i,
rd_en => rd_mdata_en,
rd_clk => clk_i,
rd_data => rd_v6_mdata,
full => open,
empty => rd_mdata_fifo_empty,
almost_full => open
);
-- tmp_sig <= cmp_valid AND data_valid_i;
-- xhdl2 <= ( tmp_sig & cmp_data);
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
-- delayed_data <= (tmp_sig & cmp_data);
cmp_data_r <= cmp_data;
end if;
end process;
rd_mdata_o <= rd_mdata;
rd_mdata <= rd_data_r WHEN (FAMILY = "SPARTAN6") ELSE rd_v6_mdata
WHEN ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) ELSE data_i;
cmp_data_valid <= cmp_data_en WHEN (FAMILY = "SPARTAN6") ELSE v6_data_cmp_valid
WHEN ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) ELSE data_valid_i;
cmp_data_o <= cmp_data_r;
cmp_addr_o <= gen_addr;
cmp_bl_o <= gen_bl;
-- xhdl4 : if (FAMILY = "SPARTAN6") generate
-- rd_data_o <= rd_data_r;
-- end generate;
-- xhdl5 : if (FAMILY /= "SPARTAN6") generate
-- rd_data_o <= data_i;
-- end generate;
data_rdy_o <= data_rdy;
data_rdy <= cmp_valid and data_valid_i;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
v6_data_cmp_valid <= rd_mdata_en;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
cmp_data_en <= data_rdy;
end if;
end process;
xhdl6 : if (FAMILY = "SPARTAN6") generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (cmp_data_en = '1') then
IF ((rd_data_r(DWIDTH / 2 - 1 downto 0) /= cmp_data_r(DWIDTH / 2 - 1 downto 0))) then
l_data_error <= '1' ;
ELSE
l_data_error <= '0' ;
END IF;
else
l_data_error <= '0' ;
end if;
if (cmp_data_en = '1') then
IF ((rd_data_r(DWIDTH - 1 downto DWIDTH / 2) /= cmp_data_r(DWIDTH - 1 downto DWIDTH / 2))) then
u_data_error <= '1' ;
ELSE
u_data_error <= '0' ;
END IF;
else
u_data_error <= '0' ;
end if;
data_error <= l_data_error or u_data_error;
--synthesis translate_off
if (data_error = '1') then
report ("DATA ERROR");
end if;
--synthesis translate_on
end if;
end process;
end generate;
gen_error_2 : if ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) generate
gen_cmp : FOR i IN 0 TO NUM_DQ_PINS / 2 - 1 GENERATE
error_byte(i) <= '1' WHEN (rd_mdata_fifo_empty = '0' AND rd_mdata_en = '1' AND (rd_v6_mdata(8 * (i + 1) - 1 DOWNTO 8 * i) /= cmp_data(8 * (i + 1) - 1 DOWNTO 8 * i))) ELSE '0';
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
error_byte_r1 <= (others => '0');
data_error <= '0';
ELSE
error_byte_r1 <= error_byte;
-- FOR i IN 0 TO DWIDTH - 1 LOOP
data_error <= REDUCTION_OR(error_byte_r1);--error_byte_r1(i) OR data_error;
-- END LOOP;
END IF;
end if;
end process;
process (data_error)
begin
--synthesis translate_off
IF (data_error = '1') THEN
report "DATA ERROR"; -- severity ERROR;
END IF;
--synthesis translate_on
end process;
gen_dq_error_map: FOR i IN 0 to DQ_ERROR_WIDTH - 1 generate
dq_lane_error(i) <= (error_byte_r1(i) OR error_byte_r1(i+DQ_ERROR_WIDTH) OR
error_byte_r1(i+ (NUM_DQ_PINS*2/8)) OR
error_byte_r1(i+ (NUM_DQ_PINS*3/8)));
cumlative_dq_lane_error_c(i) <= cumlative_dq_lane_error_reg(i) OR dq_lane_error_r1(i);
end generate;
process (clk_i)
begin
IF (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
dq_lane_error_r1 <= (others => '0');
dq_lane_error_r2 <= (others => '0');
data_valid_r <= '0';
cumlative_dq_lane_error_reg <= (others => '0');
ELSE
data_valid_r <= data_valid_i;
dq_lane_error_r1 <= dq_lane_error;
cumlative_dq_lane_error_reg <= cumlative_dq_lane_error_c;
END IF;
END IF;
end process;
end generate;
xhdl8 : if ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 8)) generate
gen_cmp_8 : FOR i IN 0 TO NUM_DQ_PINS / 2 - 1 GENERATE
error_byte(i) <= '1' WHEN (data_valid_i = '1' AND (data_i(8 * (i + 1) - 1 DOWNTO 8 * i) /= cmp_data(8 * (i + 1) - 1 DOWNTO 8 * i))) ELSE '0';
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
error_byte_r1 <= (others => '0');
data_error <= '0';
ELSE
error_byte_r1 <= error_byte;
--FOR i IN 0 TO DWIDTH - 1 LOOP
-- data_error <= error_byte_r1(i) OR data_error;
--END LOOP;
data_error <= REDUCTION_OR(error_byte_r1);--error_byte_r1(i) OR data_error;
--synthesis translate_off
IF (data_error = '1') THEN
report "DATA ERROR"; -- severity ERROR;
end if;
--synthesis translate_on
END IF;
end if;
end process;
gen_dq_error_map: FOR i IN 0 to DQ_ERROR_WIDTH - 1 generate
dq_lane_error(i) <= (error_byte_r1(i) OR error_byte_r1(i+DQ_ERROR_WIDTH) OR
error_byte_r1(i+ (NUM_DQ_PINS*2/8)) OR
error_byte_r1(i+ (NUM_DQ_PINS*3/8)));
cumlative_dq_lane_error_c(i) <= cumlative_dq_lane_error_reg(i) OR dq_lane_error_r1(i);
end generate;
process (clk_i)
begin
IF (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
dq_lane_error_r1 <= (others => '0');
dq_lane_error_r2 <= (others => '0');
data_valid_r <= '0';
cumlative_dq_lane_error_reg <= (others => '0');
ELSE
data_valid_r <= data_valid_i;
dq_lane_error_r1 <= dq_lane_error;
cumlative_dq_lane_error_reg <= cumlative_dq_lane_error_c;
END IF;
END IF;
end process;
end generate;
cumlative_dq_lane_error_r <= cumlative_dq_lane_error_reg;
dq_error_bytelane_cmp <= dq_lane_error_r1;
data_error_o <= data_error;
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: read_data_path.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This is top level of read path and also consist of comparison logic
-- for read data.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
entity read_data_path is
generic (
TCQ : time := 100 ps;
FAMILY : string := "VIRTEX6";
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : integer := 32;
CMP_DATA_PIPE_STAGES : integer := 3;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
DQ_ERROR_WIDTH : integer := 1;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
MEM_COL_WIDTH : integer := 10
);
port (
clk_i : in std_logic;
manual_clear_error : in std_logic;
rst_i : in std_logic_vector(9 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
cmd_sent : in std_logic_vector(2 downto 0);
bl_sent : in std_logic_vector(5 downto 0);
cmd_en_i : in std_logic;
-- m_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(31 downto 0);
bl_i : in std_logic_vector(5 downto 0);
-- input [5:0] port_data_counts_i,// connect to data port fifo counts
data_rdy_o : out std_logic;
data_valid_i : in std_logic;
data_i : in std_logic_vector(DWIDTH - 1 downto 0);
last_word_rd_o : out std_logic;
data_error_o : out std_logic;
cmp_data_o : out std_logic_vector(DWIDTH - 1 downto 0);
rd_mdata_o : out std_logic_vector(DWIDTH - 1 downto 0);
cmp_data_valid : out std_logic;
cmp_addr_o : out std_logic_vector(31 downto 0);
cmp_bl_o : out std_logic_vector(5 downto 0);
force_wrcmd_gen_o : out std_logic;
rd_buff_avail_o : out std_logic_vector(6 downto 0);
dq_error_bytelane_cmp : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
cumlative_dq_lane_error_r : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0)
);
end entity read_data_path;
architecture trans of read_data_path is
function REDUCTION_OR( A: in std_logic_vector) return std_logic is
variable tmp : std_logic := '0';
begin
for i in A'range loop
tmp := tmp or A(i);
end loop;
return tmp;
end function REDUCTION_OR;
COMPONENT read_posted_fifo IS
GENERIC (
TCQ : time := 100 ps;
MEM_BURST_LEN : integer := 4;
FAMILY : STRING := "SPARTAN6";
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
data_valid_i : IN STD_LOGIC;
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
user_bl_cnt_is_1 : IN STD_LOGIC;
cmd_sent : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
bl_sent : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
cmd_en_i : IN STD_LOGIC;
gen_rdy_i : IN STD_LOGIC;
gen_valid_o : OUT STD_LOGIC;
gen_addr_o : OUT STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
gen_bl_o : OUT STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
rd_buff_avail_o : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
rd_mdata_fifo_empty : IN STD_LOGIC;
rd_mdata_en : OUT STD_LOGIC
);
END COMPONENT;
component rd_data_gen is
generic (
FAMILY : string := "SPARTAN6";
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : integer := 32;
BL_WIDTH : integer := 6;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_PRBS";
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3;
COLUMN_WIDTH : integer := 10
);
port (
clk_i : in std_logic;
rst_i : in std_logic_vector(4 downto 0);
prbs_fseed_i : in std_logic_vector(31 downto 0);
rd_mdata_en : in std_logic;
data_mode_i : in std_logic_vector(3 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
last_word_o : out std_logic;
-- m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
bl_i : in std_logic_vector(BL_WIDTH - 1 downto 0);
user_bl_cnt_is_1_o : out std_logic;
data_rdy_i : in std_logic;
data_valid_o : out std_logic;
data_o : out std_logic_vector(DWIDTH - 1 downto 0)
);
end component;
component afifo IS
GENERIC (
DSIZE : INTEGER := 32;
FIFO_DEPTH : INTEGER := 16;
ASIZE : INTEGER := 5;
SYNC : INTEGER := 1
);
PORT (
wr_clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
wr_en : IN STD_LOGIC;
wr_data : IN STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
rd_en : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_data : OUT STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
almost_full : OUT STD_LOGIC;
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END component;
signal gen_rdy : std_logic;
signal gen_valid : std_logic;
signal gen_addr : std_logic_vector(31 downto 0);
signal gen_bl : std_logic_vector(5 downto 0);
signal cmp_rdy : std_logic;
signal cmp_valid : std_logic;
signal cmp_addr : std_logic_vector(31 downto 0);
signal cmp_bl : std_logic_vector(5 downto 0);
signal data_error : std_logic;
signal cmp_data : std_logic_vector(DWIDTH - 1 downto 0);
signal last_word_rd : std_logic;
signal bl_counter : std_logic_vector(5 downto 0);
signal cmd_rdy : std_logic;
signal user_bl_cnt_is_1 : std_logic;
signal data_rdy : std_logic;
signal delayed_data : std_logic_vector(DWIDTH downto 0);
-- signal cmp_data_piped : std_logic_vector(DWIDTH downto 0);
signal cmp_data_r : std_logic_vector(DWIDTH-1 downto 0);
signal rd_mdata_en : std_logic;
signal rd_data_r : std_logic_vector(DWIDTH - 1 downto 0);
signal force_wrcmd_gen : std_logic;
signal wait_bl_end : std_logic;
signal wait_bl_end_r1 : std_logic;
signal v6_data_cmp_valid : std_logic;
signal rd_v6_mdata : std_logic_vector(DWIDTH-1 downto 0);
signal cmpdata_r : std_logic_vector(DWIDTH-1 downto 0);
signal rd_mdata : std_logic_vector(DWIDTH-1 downto 0);
signal l_data_error : std_logic;
signal u_data_error : std_logic;
signal cmp_data_en : std_logic;
signal force_wrcmd_timeout_cnts : std_logic_vector(7 downto 0);
signal error_byte : std_logic_vector(NUM_DQ_PINS / 2 - 1 downto 0);
signal error_byte_r1 : std_logic_vector(NUM_DQ_PINS / 2 - 1 downto 0);
signal dq_lane_error : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal dq_lane_error_r1 : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal dq_lane_error_r2 : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cum_dq_lane_error_mask : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cumlative_dq_lane_error_reg : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cumlative_dq_lane_error_c : std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
signal rd_mdata_fifo_empty : std_logic;
signal data_valid_r : std_logic;
-- Declare intermediate signals for referenced outputs
-- SIGNAL xhdl2 : STD_LOGIC_VECTOR(DWIDTH DOWNTO 0);
-- SIGNAL tmp_sig : STD_LOGIC;
signal last_word_rd_o_xhdl0 : std_logic;
signal rd_buff_avail_o_xhdl1 : std_logic_vector(6 downto 0);
begin
-- Drive referenced outputs
last_word_rd_o <= last_word_rd_o_xhdl0;
rd_buff_avail_o <= rd_buff_avail_o_xhdl1;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
wait_bl_end_r1 <= wait_bl_end;
rd_data_r <= data_i;
end if;
end process;
force_wrcmd_gen_o <= force_wrcmd_gen;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
force_wrcmd_gen <= '0';
elsif ((wait_bl_end = '0' and wait_bl_end_r1 = '1') or force_wrcmd_timeout_cnts = "11111111") then
force_wrcmd_gen <= '0';
elsif ((cmd_valid_i = '1' and bl_i > "010000") or wait_bl_end = '1') then
force_wrcmd_gen <= '1';
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
force_wrcmd_timeout_cnts <= "00000000";
elsif (wait_bl_end = '0' and wait_bl_end_r1 = '1') then
force_wrcmd_timeout_cnts <= "00000000";
elsif (force_wrcmd_gen = '1') then
force_wrcmd_timeout_cnts <= force_wrcmd_timeout_cnts + "00000001";
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
wait_bl_end <= '0';
elsif (force_wrcmd_timeout_cnts = "11111111") then
wait_bl_end <= '0';
elsif ((gen_rdy and gen_valid) = '1' and gen_bl > "010000") then
wait_bl_end <= '1';
elsif ((wait_bl_end and user_bl_cnt_is_1) = '1') then
wait_bl_end <= '0';
end if;
end if;
end process;
cmd_rdy_o <= cmd_rdy;
read_postedfifo : read_posted_fifo
GENERIC MAP (
TCQ => TCQ,
FAMILY => FAMILY,
MEM_BURST_LEN => MEM_BURST_LEN,
ADDR_WIDTH => 32,
BL_WIDTH => 6
)
port map (
clk_i => clk_i,
rst_i => rst_i(0),
cmd_rdy_o => cmd_rdy,
cmd_valid_i => cmd_valid_i,
data_valid_i => data_rdy,
addr_i => addr_i,
bl_i => bl_i,
cmd_sent => cmd_sent,
bl_sent => bl_sent,
cmd_en_i => cmd_en_i,
user_bl_cnt_is_1 => user_bl_cnt_is_1,
gen_rdy_i => gen_rdy,
gen_valid_o => gen_valid,
gen_addr_o => gen_addr,
gen_bl_o => gen_bl,
rd_buff_avail_o => rd_buff_avail_o_xhdl1,
rd_mdata_fifo_empty => rd_mdata_fifo_empty,
rd_mdata_en => rd_mdata_en
);
rd_datagen : rd_data_gen
generic map (
FAMILY => FAMILY,
MEM_BURST_LEN => MEM_BURST_LEN,
NUM_DQ_PINS => NUM_DQ_PINS,
SEL_VICTIM_LINE => SEL_VICTIM_LINE,
DATA_PATTERN => DATA_PATTERN,
DWIDTH => DWIDTH,
COLUMN_WIDTH => MEM_COL_WIDTH
)
port map (
clk_i => clk_i,
rst_i => rst_i(4 downto 0),
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_rdy_o => gen_rdy,
cmd_valid_i => gen_valid,
last_word_o => last_word_rd_o_xhdl0,
-- m_addr_i => m_addr_i,
fixed_data_i => fixed_data_i,
addr_i => gen_addr,
bl_i => gen_bl,
user_bl_cnt_is_1_o => user_bl_cnt_is_1,
data_rdy_i => data_valid_i,
data_valid_o => cmp_valid,
data_o => cmp_data,
rd_mdata_en => rd_mdata_en
);
rd_mdata_fifo : afifo
GENERIC MAP (
DSIZE => DWIDTH,
FIFO_DEPTH => 32,
ASIZE => 5,
SYNC => 1
)
PORT MAP (
wr_clk => clk_i,
rst => rst_i(0),
wr_en => data_valid_i,
wr_data => data_i,
rd_en => rd_mdata_en,
rd_clk => clk_i,
rd_data => rd_v6_mdata,
full => open,
empty => rd_mdata_fifo_empty,
almost_full => open
);
-- tmp_sig <= cmp_valid AND data_valid_i;
-- xhdl2 <= ( tmp_sig & cmp_data);
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
-- delayed_data <= (tmp_sig & cmp_data);
cmp_data_r <= cmp_data;
end if;
end process;
rd_mdata_o <= rd_mdata;
rd_mdata <= rd_data_r WHEN (FAMILY = "SPARTAN6") ELSE rd_v6_mdata
WHEN ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) ELSE data_i;
cmp_data_valid <= cmp_data_en WHEN (FAMILY = "SPARTAN6") ELSE v6_data_cmp_valid
WHEN ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) ELSE data_valid_i;
cmp_data_o <= cmp_data_r;
cmp_addr_o <= gen_addr;
cmp_bl_o <= gen_bl;
-- xhdl4 : if (FAMILY = "SPARTAN6") generate
-- rd_data_o <= rd_data_r;
-- end generate;
-- xhdl5 : if (FAMILY /= "SPARTAN6") generate
-- rd_data_o <= data_i;
-- end generate;
data_rdy_o <= data_rdy;
data_rdy <= cmp_valid and data_valid_i;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
v6_data_cmp_valid <= rd_mdata_en;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
cmp_data_en <= data_rdy;
end if;
end process;
xhdl6 : if (FAMILY = "SPARTAN6") generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (cmp_data_en = '1') then
IF ((rd_data_r(DWIDTH / 2 - 1 downto 0) /= cmp_data_r(DWIDTH / 2 - 1 downto 0))) then
l_data_error <= '1' ;
ELSE
l_data_error <= '0' ;
END IF;
else
l_data_error <= '0' ;
end if;
if (cmp_data_en = '1') then
IF ((rd_data_r(DWIDTH - 1 downto DWIDTH / 2) /= cmp_data_r(DWIDTH - 1 downto DWIDTH / 2))) then
u_data_error <= '1' ;
ELSE
u_data_error <= '0' ;
END IF;
else
u_data_error <= '0' ;
end if;
data_error <= l_data_error or u_data_error;
--synthesis translate_off
if (data_error = '1') then
report ("DATA ERROR");
end if;
--synthesis translate_on
end if;
end process;
end generate;
gen_error_2 : if ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) generate
gen_cmp : FOR i IN 0 TO NUM_DQ_PINS / 2 - 1 GENERATE
error_byte(i) <= '1' WHEN (rd_mdata_fifo_empty = '0' AND rd_mdata_en = '1' AND (rd_v6_mdata(8 * (i + 1) - 1 DOWNTO 8 * i) /= cmp_data(8 * (i + 1) - 1 DOWNTO 8 * i))) ELSE '0';
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
error_byte_r1 <= (others => '0');
data_error <= '0';
ELSE
error_byte_r1 <= error_byte;
-- FOR i IN 0 TO DWIDTH - 1 LOOP
data_error <= REDUCTION_OR(error_byte_r1);--error_byte_r1(i) OR data_error;
-- END LOOP;
END IF;
end if;
end process;
process (data_error)
begin
--synthesis translate_off
IF (data_error = '1') THEN
report "DATA ERROR"; -- severity ERROR;
END IF;
--synthesis translate_on
end process;
gen_dq_error_map: FOR i IN 0 to DQ_ERROR_WIDTH - 1 generate
dq_lane_error(i) <= (error_byte_r1(i) OR error_byte_r1(i+DQ_ERROR_WIDTH) OR
error_byte_r1(i+ (NUM_DQ_PINS*2/8)) OR
error_byte_r1(i+ (NUM_DQ_PINS*3/8)));
cumlative_dq_lane_error_c(i) <= cumlative_dq_lane_error_reg(i) OR dq_lane_error_r1(i);
end generate;
process (clk_i)
begin
IF (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
dq_lane_error_r1 <= (others => '0');
dq_lane_error_r2 <= (others => '0');
data_valid_r <= '0';
cumlative_dq_lane_error_reg <= (others => '0');
ELSE
data_valid_r <= data_valid_i;
dq_lane_error_r1 <= dq_lane_error;
cumlative_dq_lane_error_reg <= cumlative_dq_lane_error_c;
END IF;
END IF;
end process;
end generate;
xhdl8 : if ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 8)) generate
gen_cmp_8 : FOR i IN 0 TO NUM_DQ_PINS / 2 - 1 GENERATE
error_byte(i) <= '1' WHEN (data_valid_i = '1' AND (data_i(8 * (i + 1) - 1 DOWNTO 8 * i) /= cmp_data(8 * (i + 1) - 1 DOWNTO 8 * i))) ELSE '0';
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
error_byte_r1 <= (others => '0');
data_error <= '0';
ELSE
error_byte_r1 <= error_byte;
--FOR i IN 0 TO DWIDTH - 1 LOOP
-- data_error <= error_byte_r1(i) OR data_error;
--END LOOP;
data_error <= REDUCTION_OR(error_byte_r1);--error_byte_r1(i) OR data_error;
--synthesis translate_off
IF (data_error = '1') THEN
report "DATA ERROR"; -- severity ERROR;
end if;
--synthesis translate_on
END IF;
end if;
end process;
gen_dq_error_map: FOR i IN 0 to DQ_ERROR_WIDTH - 1 generate
dq_lane_error(i) <= (error_byte_r1(i) OR error_byte_r1(i+DQ_ERROR_WIDTH) OR
error_byte_r1(i+ (NUM_DQ_PINS*2/8)) OR
error_byte_r1(i+ (NUM_DQ_PINS*3/8)));
cumlative_dq_lane_error_c(i) <= cumlative_dq_lane_error_reg(i) OR dq_lane_error_r1(i);
end generate;
process (clk_i)
begin
IF (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
dq_lane_error_r1 <= (others => '0');
dq_lane_error_r2 <= (others => '0');
data_valid_r <= '0';
cumlative_dq_lane_error_reg <= (others => '0');
ELSE
data_valid_r <= data_valid_i;
dq_lane_error_r1 <= dq_lane_error;
cumlative_dq_lane_error_reg <= cumlative_dq_lane_error_c;
END IF;
END IF;
end process;
end generate;
cumlative_dq_lane_error_r <= cumlative_dq_lane_error_reg;
dq_error_bytelane_cmp <= dq_lane_error_r1;
data_error_o <= data_error;
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: read_data_path.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This is top level of read path and also consist of comparison logic
-- for read data.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
entity read_data_path is
generic (
TCQ : time := 100 ps;
FAMILY : string := "VIRTEX6";
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : integer := 32;
CMP_DATA_PIPE_STAGES : integer := 3;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
DQ_ERROR_WIDTH : integer := 1;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
MEM_COL_WIDTH : integer := 10
);
port (
clk_i : in std_logic;
manual_clear_error : in std_logic;
rst_i : in std_logic_vector(9 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
cmd_sent : in std_logic_vector(2 downto 0);
bl_sent : in std_logic_vector(5 downto 0);
cmd_en_i : in std_logic;
-- m_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(31 downto 0);
bl_i : in std_logic_vector(5 downto 0);
-- input [5:0] port_data_counts_i,// connect to data port fifo counts
data_rdy_o : out std_logic;
data_valid_i : in std_logic;
data_i : in std_logic_vector(DWIDTH - 1 downto 0);
last_word_rd_o : out std_logic;
data_error_o : out std_logic;
cmp_data_o : out std_logic_vector(DWIDTH - 1 downto 0);
rd_mdata_o : out std_logic_vector(DWIDTH - 1 downto 0);
cmp_data_valid : out std_logic;
cmp_addr_o : out std_logic_vector(31 downto 0);
cmp_bl_o : out std_logic_vector(5 downto 0);
force_wrcmd_gen_o : out std_logic;
rd_buff_avail_o : out std_logic_vector(6 downto 0);
dq_error_bytelane_cmp : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
cumlative_dq_lane_error_r : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0)
);
end entity read_data_path;
architecture trans of read_data_path is
function REDUCTION_OR( A: in std_logic_vector) return std_logic is
variable tmp : std_logic := '0';
begin
for i in A'range loop
tmp := tmp or A(i);
end loop;
return tmp;
end function REDUCTION_OR;
COMPONENT read_posted_fifo IS
GENERIC (
TCQ : time := 100 ps;
MEM_BURST_LEN : integer := 4;
FAMILY : STRING := "SPARTAN6";
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
data_valid_i : IN STD_LOGIC;
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
user_bl_cnt_is_1 : IN STD_LOGIC;
cmd_sent : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
bl_sent : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
cmd_en_i : IN STD_LOGIC;
gen_rdy_i : IN STD_LOGIC;
gen_valid_o : OUT STD_LOGIC;
gen_addr_o : OUT STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
gen_bl_o : OUT STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
rd_buff_avail_o : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
rd_mdata_fifo_empty : IN STD_LOGIC;
rd_mdata_en : OUT STD_LOGIC
);
END COMPONENT;
component rd_data_gen is
generic (
FAMILY : string := "SPARTAN6";
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : integer := 32;
BL_WIDTH : integer := 6;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_PRBS";
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3;
COLUMN_WIDTH : integer := 10
);
port (
clk_i : in std_logic;
rst_i : in std_logic_vector(4 downto 0);
prbs_fseed_i : in std_logic_vector(31 downto 0);
rd_mdata_en : in std_logic;
data_mode_i : in std_logic_vector(3 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
last_word_o : out std_logic;
-- m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
bl_i : in std_logic_vector(BL_WIDTH - 1 downto 0);
user_bl_cnt_is_1_o : out std_logic;
data_rdy_i : in std_logic;
data_valid_o : out std_logic;
data_o : out std_logic_vector(DWIDTH - 1 downto 0)
);
end component;
component afifo IS
GENERIC (
DSIZE : INTEGER := 32;
FIFO_DEPTH : INTEGER := 16;
ASIZE : INTEGER := 5;
SYNC : INTEGER := 1
);
PORT (
wr_clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
wr_en : IN STD_LOGIC;
wr_data : IN STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
rd_en : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_data : OUT STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
almost_full : OUT STD_LOGIC;
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END component;
signal gen_rdy : std_logic;
signal gen_valid : std_logic;
signal gen_addr : std_logic_vector(31 downto 0);
signal gen_bl : std_logic_vector(5 downto 0);
signal cmp_rdy : std_logic;
signal cmp_valid : std_logic;
signal cmp_addr : std_logic_vector(31 downto 0);
signal cmp_bl : std_logic_vector(5 downto 0);
signal data_error : std_logic;
signal cmp_data : std_logic_vector(DWIDTH - 1 downto 0);
signal last_word_rd : std_logic;
signal bl_counter : std_logic_vector(5 downto 0);
signal cmd_rdy : std_logic;
signal user_bl_cnt_is_1 : std_logic;
signal data_rdy : std_logic;
signal delayed_data : std_logic_vector(DWIDTH downto 0);
-- signal cmp_data_piped : std_logic_vector(DWIDTH downto 0);
signal cmp_data_r : std_logic_vector(DWIDTH-1 downto 0);
signal rd_mdata_en : std_logic;
signal rd_data_r : std_logic_vector(DWIDTH - 1 downto 0);
signal force_wrcmd_gen : std_logic;
signal wait_bl_end : std_logic;
signal wait_bl_end_r1 : std_logic;
signal v6_data_cmp_valid : std_logic;
signal rd_v6_mdata : std_logic_vector(DWIDTH-1 downto 0);
signal cmpdata_r : std_logic_vector(DWIDTH-1 downto 0);
signal rd_mdata : std_logic_vector(DWIDTH-1 downto 0);
signal l_data_error : std_logic;
signal u_data_error : std_logic;
signal cmp_data_en : std_logic;
signal force_wrcmd_timeout_cnts : std_logic_vector(7 downto 0);
signal error_byte : std_logic_vector(NUM_DQ_PINS / 2 - 1 downto 0);
signal error_byte_r1 : std_logic_vector(NUM_DQ_PINS / 2 - 1 downto 0);
signal dq_lane_error : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal dq_lane_error_r1 : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal dq_lane_error_r2 : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cum_dq_lane_error_mask : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cumlative_dq_lane_error_reg : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cumlative_dq_lane_error_c : std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
signal rd_mdata_fifo_empty : std_logic;
signal data_valid_r : std_logic;
-- Declare intermediate signals for referenced outputs
-- SIGNAL xhdl2 : STD_LOGIC_VECTOR(DWIDTH DOWNTO 0);
-- SIGNAL tmp_sig : STD_LOGIC;
signal last_word_rd_o_xhdl0 : std_logic;
signal rd_buff_avail_o_xhdl1 : std_logic_vector(6 downto 0);
begin
-- Drive referenced outputs
last_word_rd_o <= last_word_rd_o_xhdl0;
rd_buff_avail_o <= rd_buff_avail_o_xhdl1;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
wait_bl_end_r1 <= wait_bl_end;
rd_data_r <= data_i;
end if;
end process;
force_wrcmd_gen_o <= force_wrcmd_gen;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
force_wrcmd_gen <= '0';
elsif ((wait_bl_end = '0' and wait_bl_end_r1 = '1') or force_wrcmd_timeout_cnts = "11111111") then
force_wrcmd_gen <= '0';
elsif ((cmd_valid_i = '1' and bl_i > "010000") or wait_bl_end = '1') then
force_wrcmd_gen <= '1';
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
force_wrcmd_timeout_cnts <= "00000000";
elsif (wait_bl_end = '0' and wait_bl_end_r1 = '1') then
force_wrcmd_timeout_cnts <= "00000000";
elsif (force_wrcmd_gen = '1') then
force_wrcmd_timeout_cnts <= force_wrcmd_timeout_cnts + "00000001";
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
wait_bl_end <= '0';
elsif (force_wrcmd_timeout_cnts = "11111111") then
wait_bl_end <= '0';
elsif ((gen_rdy and gen_valid) = '1' and gen_bl > "010000") then
wait_bl_end <= '1';
elsif ((wait_bl_end and user_bl_cnt_is_1) = '1') then
wait_bl_end <= '0';
end if;
end if;
end process;
cmd_rdy_o <= cmd_rdy;
read_postedfifo : read_posted_fifo
GENERIC MAP (
TCQ => TCQ,
FAMILY => FAMILY,
MEM_BURST_LEN => MEM_BURST_LEN,
ADDR_WIDTH => 32,
BL_WIDTH => 6
)
port map (
clk_i => clk_i,
rst_i => rst_i(0),
cmd_rdy_o => cmd_rdy,
cmd_valid_i => cmd_valid_i,
data_valid_i => data_rdy,
addr_i => addr_i,
bl_i => bl_i,
cmd_sent => cmd_sent,
bl_sent => bl_sent,
cmd_en_i => cmd_en_i,
user_bl_cnt_is_1 => user_bl_cnt_is_1,
gen_rdy_i => gen_rdy,
gen_valid_o => gen_valid,
gen_addr_o => gen_addr,
gen_bl_o => gen_bl,
rd_buff_avail_o => rd_buff_avail_o_xhdl1,
rd_mdata_fifo_empty => rd_mdata_fifo_empty,
rd_mdata_en => rd_mdata_en
);
rd_datagen : rd_data_gen
generic map (
FAMILY => FAMILY,
MEM_BURST_LEN => MEM_BURST_LEN,
NUM_DQ_PINS => NUM_DQ_PINS,
SEL_VICTIM_LINE => SEL_VICTIM_LINE,
DATA_PATTERN => DATA_PATTERN,
DWIDTH => DWIDTH,
COLUMN_WIDTH => MEM_COL_WIDTH
)
port map (
clk_i => clk_i,
rst_i => rst_i(4 downto 0),
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_rdy_o => gen_rdy,
cmd_valid_i => gen_valid,
last_word_o => last_word_rd_o_xhdl0,
-- m_addr_i => m_addr_i,
fixed_data_i => fixed_data_i,
addr_i => gen_addr,
bl_i => gen_bl,
user_bl_cnt_is_1_o => user_bl_cnt_is_1,
data_rdy_i => data_valid_i,
data_valid_o => cmp_valid,
data_o => cmp_data,
rd_mdata_en => rd_mdata_en
);
rd_mdata_fifo : afifo
GENERIC MAP (
DSIZE => DWIDTH,
FIFO_DEPTH => 32,
ASIZE => 5,
SYNC => 1
)
PORT MAP (
wr_clk => clk_i,
rst => rst_i(0),
wr_en => data_valid_i,
wr_data => data_i,
rd_en => rd_mdata_en,
rd_clk => clk_i,
rd_data => rd_v6_mdata,
full => open,
empty => rd_mdata_fifo_empty,
almost_full => open
);
-- tmp_sig <= cmp_valid AND data_valid_i;
-- xhdl2 <= ( tmp_sig & cmp_data);
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
-- delayed_data <= (tmp_sig & cmp_data);
cmp_data_r <= cmp_data;
end if;
end process;
rd_mdata_o <= rd_mdata;
rd_mdata <= rd_data_r WHEN (FAMILY = "SPARTAN6") ELSE rd_v6_mdata
WHEN ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) ELSE data_i;
cmp_data_valid <= cmp_data_en WHEN (FAMILY = "SPARTAN6") ELSE v6_data_cmp_valid
WHEN ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) ELSE data_valid_i;
cmp_data_o <= cmp_data_r;
cmp_addr_o <= gen_addr;
cmp_bl_o <= gen_bl;
-- xhdl4 : if (FAMILY = "SPARTAN6") generate
-- rd_data_o <= rd_data_r;
-- end generate;
-- xhdl5 : if (FAMILY /= "SPARTAN6") generate
-- rd_data_o <= data_i;
-- end generate;
data_rdy_o <= data_rdy;
data_rdy <= cmp_valid and data_valid_i;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
v6_data_cmp_valid <= rd_mdata_en;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
cmp_data_en <= data_rdy;
end if;
end process;
xhdl6 : if (FAMILY = "SPARTAN6") generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (cmp_data_en = '1') then
IF ((rd_data_r(DWIDTH / 2 - 1 downto 0) /= cmp_data_r(DWIDTH / 2 - 1 downto 0))) then
l_data_error <= '1' ;
ELSE
l_data_error <= '0' ;
END IF;
else
l_data_error <= '0' ;
end if;
if (cmp_data_en = '1') then
IF ((rd_data_r(DWIDTH - 1 downto DWIDTH / 2) /= cmp_data_r(DWIDTH - 1 downto DWIDTH / 2))) then
u_data_error <= '1' ;
ELSE
u_data_error <= '0' ;
END IF;
else
u_data_error <= '0' ;
end if;
data_error <= l_data_error or u_data_error;
--synthesis translate_off
if (data_error = '1') then
report ("DATA ERROR");
end if;
--synthesis translate_on
end if;
end process;
end generate;
gen_error_2 : if ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) generate
gen_cmp : FOR i IN 0 TO NUM_DQ_PINS / 2 - 1 GENERATE
error_byte(i) <= '1' WHEN (rd_mdata_fifo_empty = '0' AND rd_mdata_en = '1' AND (rd_v6_mdata(8 * (i + 1) - 1 DOWNTO 8 * i) /= cmp_data(8 * (i + 1) - 1 DOWNTO 8 * i))) ELSE '0';
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
error_byte_r1 <= (others => '0');
data_error <= '0';
ELSE
error_byte_r1 <= error_byte;
-- FOR i IN 0 TO DWIDTH - 1 LOOP
data_error <= REDUCTION_OR(error_byte_r1);--error_byte_r1(i) OR data_error;
-- END LOOP;
END IF;
end if;
end process;
process (data_error)
begin
--synthesis translate_off
IF (data_error = '1') THEN
report "DATA ERROR"; -- severity ERROR;
END IF;
--synthesis translate_on
end process;
gen_dq_error_map: FOR i IN 0 to DQ_ERROR_WIDTH - 1 generate
dq_lane_error(i) <= (error_byte_r1(i) OR error_byte_r1(i+DQ_ERROR_WIDTH) OR
error_byte_r1(i+ (NUM_DQ_PINS*2/8)) OR
error_byte_r1(i+ (NUM_DQ_PINS*3/8)));
cumlative_dq_lane_error_c(i) <= cumlative_dq_lane_error_reg(i) OR dq_lane_error_r1(i);
end generate;
process (clk_i)
begin
IF (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
dq_lane_error_r1 <= (others => '0');
dq_lane_error_r2 <= (others => '0');
data_valid_r <= '0';
cumlative_dq_lane_error_reg <= (others => '0');
ELSE
data_valid_r <= data_valid_i;
dq_lane_error_r1 <= dq_lane_error;
cumlative_dq_lane_error_reg <= cumlative_dq_lane_error_c;
END IF;
END IF;
end process;
end generate;
xhdl8 : if ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 8)) generate
gen_cmp_8 : FOR i IN 0 TO NUM_DQ_PINS / 2 - 1 GENERATE
error_byte(i) <= '1' WHEN (data_valid_i = '1' AND (data_i(8 * (i + 1) - 1 DOWNTO 8 * i) /= cmp_data(8 * (i + 1) - 1 DOWNTO 8 * i))) ELSE '0';
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
error_byte_r1 <= (others => '0');
data_error <= '0';
ELSE
error_byte_r1 <= error_byte;
--FOR i IN 0 TO DWIDTH - 1 LOOP
-- data_error <= error_byte_r1(i) OR data_error;
--END LOOP;
data_error <= REDUCTION_OR(error_byte_r1);--error_byte_r1(i) OR data_error;
--synthesis translate_off
IF (data_error = '1') THEN
report "DATA ERROR"; -- severity ERROR;
end if;
--synthesis translate_on
END IF;
end if;
end process;
gen_dq_error_map: FOR i IN 0 to DQ_ERROR_WIDTH - 1 generate
dq_lane_error(i) <= (error_byte_r1(i) OR error_byte_r1(i+DQ_ERROR_WIDTH) OR
error_byte_r1(i+ (NUM_DQ_PINS*2/8)) OR
error_byte_r1(i+ (NUM_DQ_PINS*3/8)));
cumlative_dq_lane_error_c(i) <= cumlative_dq_lane_error_reg(i) OR dq_lane_error_r1(i);
end generate;
process (clk_i)
begin
IF (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
dq_lane_error_r1 <= (others => '0');
dq_lane_error_r2 <= (others => '0');
data_valid_r <= '0';
cumlative_dq_lane_error_reg <= (others => '0');
ELSE
data_valid_r <= data_valid_i;
dq_lane_error_r1 <= dq_lane_error;
cumlative_dq_lane_error_reg <= cumlative_dq_lane_error_c;
END IF;
END IF;
end process;
end generate;
cumlative_dq_lane_error_r <= cumlative_dq_lane_error_reg;
dq_error_bytelane_cmp <= dq_lane_error_r1;
data_error_o <= data_error;
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: read_data_path.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This is top level of read path and also consist of comparison logic
-- for read data.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;
entity read_data_path is
generic (
TCQ : time := 100 ps;
FAMILY : string := "VIRTEX6";
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : integer := 32;
CMP_DATA_PIPE_STAGES : integer := 3;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
DQ_ERROR_WIDTH : integer := 1;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
MEM_COL_WIDTH : integer := 10
);
port (
clk_i : in std_logic;
manual_clear_error : in std_logic;
rst_i : in std_logic_vector(9 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
cmd_sent : in std_logic_vector(2 downto 0);
bl_sent : in std_logic_vector(5 downto 0);
cmd_en_i : in std_logic;
-- m_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(31 downto 0);
bl_i : in std_logic_vector(5 downto 0);
-- input [5:0] port_data_counts_i,// connect to data port fifo counts
data_rdy_o : out std_logic;
data_valid_i : in std_logic;
data_i : in std_logic_vector(DWIDTH - 1 downto 0);
last_word_rd_o : out std_logic;
data_error_o : out std_logic;
cmp_data_o : out std_logic_vector(DWIDTH - 1 downto 0);
rd_mdata_o : out std_logic_vector(DWIDTH - 1 downto 0);
cmp_data_valid : out std_logic;
cmp_addr_o : out std_logic_vector(31 downto 0);
cmp_bl_o : out std_logic_vector(5 downto 0);
force_wrcmd_gen_o : out std_logic;
rd_buff_avail_o : out std_logic_vector(6 downto 0);
dq_error_bytelane_cmp : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
cumlative_dq_lane_error_r : out std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0)
);
end entity read_data_path;
architecture trans of read_data_path is
function REDUCTION_OR( A: in std_logic_vector) return std_logic is
variable tmp : std_logic := '0';
begin
for i in A'range loop
tmp := tmp or A(i);
end loop;
return tmp;
end function REDUCTION_OR;
COMPONENT read_posted_fifo IS
GENERIC (
TCQ : time := 100 ps;
MEM_BURST_LEN : integer := 4;
FAMILY : STRING := "SPARTAN6";
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : IN STD_LOGIC;
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
data_valid_i : IN STD_LOGIC;
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
user_bl_cnt_is_1 : IN STD_LOGIC;
cmd_sent : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
bl_sent : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
cmd_en_i : IN STD_LOGIC;
gen_rdy_i : IN STD_LOGIC;
gen_valid_o : OUT STD_LOGIC;
gen_addr_o : OUT STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
gen_bl_o : OUT STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
rd_buff_avail_o : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
rd_mdata_fifo_empty : IN STD_LOGIC;
rd_mdata_en : OUT STD_LOGIC
);
END COMPONENT;
component rd_data_gen is
generic (
FAMILY : string := "SPARTAN6";
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : integer := 32;
BL_WIDTH : integer := 6;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_PRBS";
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3;
COLUMN_WIDTH : integer := 10
);
port (
clk_i : in std_logic;
rst_i : in std_logic_vector(4 downto 0);
prbs_fseed_i : in std_logic_vector(31 downto 0);
rd_mdata_en : in std_logic;
data_mode_i : in std_logic_vector(3 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
last_word_o : out std_logic;
-- m_addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH - 1 downto 0);
addr_i : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
bl_i : in std_logic_vector(BL_WIDTH - 1 downto 0);
user_bl_cnt_is_1_o : out std_logic;
data_rdy_i : in std_logic;
data_valid_o : out std_logic;
data_o : out std_logic_vector(DWIDTH - 1 downto 0)
);
end component;
component afifo IS
GENERIC (
DSIZE : INTEGER := 32;
FIFO_DEPTH : INTEGER := 16;
ASIZE : INTEGER := 5;
SYNC : INTEGER := 1
);
PORT (
wr_clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
wr_en : IN STD_LOGIC;
wr_data : IN STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
rd_en : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
rd_data : OUT STD_LOGIC_VECTOR(DSIZE - 1 DOWNTO 0);
almost_full : OUT STD_LOGIC;
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END component;
signal gen_rdy : std_logic;
signal gen_valid : std_logic;
signal gen_addr : std_logic_vector(31 downto 0);
signal gen_bl : std_logic_vector(5 downto 0);
signal cmp_rdy : std_logic;
signal cmp_valid : std_logic;
signal cmp_addr : std_logic_vector(31 downto 0);
signal cmp_bl : std_logic_vector(5 downto 0);
signal data_error : std_logic;
signal cmp_data : std_logic_vector(DWIDTH - 1 downto 0);
signal last_word_rd : std_logic;
signal bl_counter : std_logic_vector(5 downto 0);
signal cmd_rdy : std_logic;
signal user_bl_cnt_is_1 : std_logic;
signal data_rdy : std_logic;
signal delayed_data : std_logic_vector(DWIDTH downto 0);
-- signal cmp_data_piped : std_logic_vector(DWIDTH downto 0);
signal cmp_data_r : std_logic_vector(DWIDTH-1 downto 0);
signal rd_mdata_en : std_logic;
signal rd_data_r : std_logic_vector(DWIDTH - 1 downto 0);
signal force_wrcmd_gen : std_logic;
signal wait_bl_end : std_logic;
signal wait_bl_end_r1 : std_logic;
signal v6_data_cmp_valid : std_logic;
signal rd_v6_mdata : std_logic_vector(DWIDTH-1 downto 0);
signal cmpdata_r : std_logic_vector(DWIDTH-1 downto 0);
signal rd_mdata : std_logic_vector(DWIDTH-1 downto 0);
signal l_data_error : std_logic;
signal u_data_error : std_logic;
signal cmp_data_en : std_logic;
signal force_wrcmd_timeout_cnts : std_logic_vector(7 downto 0);
signal error_byte : std_logic_vector(NUM_DQ_PINS / 2 - 1 downto 0);
signal error_byte_r1 : std_logic_vector(NUM_DQ_PINS / 2 - 1 downto 0);
signal dq_lane_error : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal dq_lane_error_r1 : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal dq_lane_error_r2 : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cum_dq_lane_error_mask : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cumlative_dq_lane_error_reg : std_logic_vector(DQ_ERROR_WIDTH-1 downto 0);
signal cumlative_dq_lane_error_c : std_logic_vector(DQ_ERROR_WIDTH - 1 downto 0);
signal rd_mdata_fifo_empty : std_logic;
signal data_valid_r : std_logic;
-- Declare intermediate signals for referenced outputs
-- SIGNAL xhdl2 : STD_LOGIC_VECTOR(DWIDTH DOWNTO 0);
-- SIGNAL tmp_sig : STD_LOGIC;
signal last_word_rd_o_xhdl0 : std_logic;
signal rd_buff_avail_o_xhdl1 : std_logic_vector(6 downto 0);
begin
-- Drive referenced outputs
last_word_rd_o <= last_word_rd_o_xhdl0;
rd_buff_avail_o <= rd_buff_avail_o_xhdl1;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
wait_bl_end_r1 <= wait_bl_end;
rd_data_r <= data_i;
end if;
end process;
force_wrcmd_gen_o <= force_wrcmd_gen;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
force_wrcmd_gen <= '0';
elsif ((wait_bl_end = '0' and wait_bl_end_r1 = '1') or force_wrcmd_timeout_cnts = "11111111") then
force_wrcmd_gen <= '0';
elsif ((cmd_valid_i = '1' and bl_i > "010000") or wait_bl_end = '1') then
force_wrcmd_gen <= '1';
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
force_wrcmd_timeout_cnts <= "00000000";
elsif (wait_bl_end = '0' and wait_bl_end_r1 = '1') then
force_wrcmd_timeout_cnts <= "00000000";
elsif (force_wrcmd_gen = '1') then
force_wrcmd_timeout_cnts <= force_wrcmd_timeout_cnts + "00000001";
end if;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (rst_i(0) = '1') then
wait_bl_end <= '0';
elsif (force_wrcmd_timeout_cnts = "11111111") then
wait_bl_end <= '0';
elsif ((gen_rdy and gen_valid) = '1' and gen_bl > "010000") then
wait_bl_end <= '1';
elsif ((wait_bl_end and user_bl_cnt_is_1) = '1') then
wait_bl_end <= '0';
end if;
end if;
end process;
cmd_rdy_o <= cmd_rdy;
read_postedfifo : read_posted_fifo
GENERIC MAP (
TCQ => TCQ,
FAMILY => FAMILY,
MEM_BURST_LEN => MEM_BURST_LEN,
ADDR_WIDTH => 32,
BL_WIDTH => 6
)
port map (
clk_i => clk_i,
rst_i => rst_i(0),
cmd_rdy_o => cmd_rdy,
cmd_valid_i => cmd_valid_i,
data_valid_i => data_rdy,
addr_i => addr_i,
bl_i => bl_i,
cmd_sent => cmd_sent,
bl_sent => bl_sent,
cmd_en_i => cmd_en_i,
user_bl_cnt_is_1 => user_bl_cnt_is_1,
gen_rdy_i => gen_rdy,
gen_valid_o => gen_valid,
gen_addr_o => gen_addr,
gen_bl_o => gen_bl,
rd_buff_avail_o => rd_buff_avail_o_xhdl1,
rd_mdata_fifo_empty => rd_mdata_fifo_empty,
rd_mdata_en => rd_mdata_en
);
rd_datagen : rd_data_gen
generic map (
FAMILY => FAMILY,
MEM_BURST_LEN => MEM_BURST_LEN,
NUM_DQ_PINS => NUM_DQ_PINS,
SEL_VICTIM_LINE => SEL_VICTIM_LINE,
DATA_PATTERN => DATA_PATTERN,
DWIDTH => DWIDTH,
COLUMN_WIDTH => MEM_COL_WIDTH
)
port map (
clk_i => clk_i,
rst_i => rst_i(4 downto 0),
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_rdy_o => gen_rdy,
cmd_valid_i => gen_valid,
last_word_o => last_word_rd_o_xhdl0,
-- m_addr_i => m_addr_i,
fixed_data_i => fixed_data_i,
addr_i => gen_addr,
bl_i => gen_bl,
user_bl_cnt_is_1_o => user_bl_cnt_is_1,
data_rdy_i => data_valid_i,
data_valid_o => cmp_valid,
data_o => cmp_data,
rd_mdata_en => rd_mdata_en
);
rd_mdata_fifo : afifo
GENERIC MAP (
DSIZE => DWIDTH,
FIFO_DEPTH => 32,
ASIZE => 5,
SYNC => 1
)
PORT MAP (
wr_clk => clk_i,
rst => rst_i(0),
wr_en => data_valid_i,
wr_data => data_i,
rd_en => rd_mdata_en,
rd_clk => clk_i,
rd_data => rd_v6_mdata,
full => open,
empty => rd_mdata_fifo_empty,
almost_full => open
);
-- tmp_sig <= cmp_valid AND data_valid_i;
-- xhdl2 <= ( tmp_sig & cmp_data);
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
-- delayed_data <= (tmp_sig & cmp_data);
cmp_data_r <= cmp_data;
end if;
end process;
rd_mdata_o <= rd_mdata;
rd_mdata <= rd_data_r WHEN (FAMILY = "SPARTAN6") ELSE rd_v6_mdata
WHEN ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) ELSE data_i;
cmp_data_valid <= cmp_data_en WHEN (FAMILY = "SPARTAN6") ELSE v6_data_cmp_valid
WHEN ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) ELSE data_valid_i;
cmp_data_o <= cmp_data_r;
cmp_addr_o <= gen_addr;
cmp_bl_o <= gen_bl;
-- xhdl4 : if (FAMILY = "SPARTAN6") generate
-- rd_data_o <= rd_data_r;
-- end generate;
-- xhdl5 : if (FAMILY /= "SPARTAN6") generate
-- rd_data_o <= data_i;
-- end generate;
data_rdy_o <= data_rdy;
data_rdy <= cmp_valid and data_valid_i;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
v6_data_cmp_valid <= rd_mdata_en;
end if;
end process;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
cmp_data_en <= data_rdy;
end if;
end process;
xhdl6 : if (FAMILY = "SPARTAN6") generate
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
if (cmp_data_en = '1') then
IF ((rd_data_r(DWIDTH / 2 - 1 downto 0) /= cmp_data_r(DWIDTH / 2 - 1 downto 0))) then
l_data_error <= '1' ;
ELSE
l_data_error <= '0' ;
END IF;
else
l_data_error <= '0' ;
end if;
if (cmp_data_en = '1') then
IF ((rd_data_r(DWIDTH - 1 downto DWIDTH / 2) /= cmp_data_r(DWIDTH - 1 downto DWIDTH / 2))) then
u_data_error <= '1' ;
ELSE
u_data_error <= '0' ;
END IF;
else
u_data_error <= '0' ;
end if;
data_error <= l_data_error or u_data_error;
--synthesis translate_off
if (data_error = '1') then
report ("DATA ERROR");
end if;
--synthesis translate_on
end if;
end process;
end generate;
gen_error_2 : if ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 4)) generate
gen_cmp : FOR i IN 0 TO NUM_DQ_PINS / 2 - 1 GENERATE
error_byte(i) <= '1' WHEN (rd_mdata_fifo_empty = '0' AND rd_mdata_en = '1' AND (rd_v6_mdata(8 * (i + 1) - 1 DOWNTO 8 * i) /= cmp_data(8 * (i + 1) - 1 DOWNTO 8 * i))) ELSE '0';
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
error_byte_r1 <= (others => '0');
data_error <= '0';
ELSE
error_byte_r1 <= error_byte;
-- FOR i IN 0 TO DWIDTH - 1 LOOP
data_error <= REDUCTION_OR(error_byte_r1);--error_byte_r1(i) OR data_error;
-- END LOOP;
END IF;
end if;
end process;
process (data_error)
begin
--synthesis translate_off
IF (data_error = '1') THEN
report "DATA ERROR"; -- severity ERROR;
END IF;
--synthesis translate_on
end process;
gen_dq_error_map: FOR i IN 0 to DQ_ERROR_WIDTH - 1 generate
dq_lane_error(i) <= (error_byte_r1(i) OR error_byte_r1(i+DQ_ERROR_WIDTH) OR
error_byte_r1(i+ (NUM_DQ_PINS*2/8)) OR
error_byte_r1(i+ (NUM_DQ_PINS*3/8)));
cumlative_dq_lane_error_c(i) <= cumlative_dq_lane_error_reg(i) OR dq_lane_error_r1(i);
end generate;
process (clk_i)
begin
IF (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
dq_lane_error_r1 <= (others => '0');
dq_lane_error_r2 <= (others => '0');
data_valid_r <= '0';
cumlative_dq_lane_error_reg <= (others => '0');
ELSE
data_valid_r <= data_valid_i;
dq_lane_error_r1 <= dq_lane_error;
cumlative_dq_lane_error_reg <= cumlative_dq_lane_error_c;
END IF;
END IF;
end process;
end generate;
xhdl8 : if ((FAMILY = "VIRTEX6") and (MEM_BURST_LEN = 8)) generate
gen_cmp_8 : FOR i IN 0 TO NUM_DQ_PINS / 2 - 1 GENERATE
error_byte(i) <= '1' WHEN (data_valid_i = '1' AND (data_i(8 * (i + 1) - 1 DOWNTO 8 * i) /= cmp_data(8 * (i + 1) - 1 DOWNTO 8 * i))) ELSE '0';
end generate;
process (clk_i)
begin
if (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
error_byte_r1 <= (others => '0');
data_error <= '0';
ELSE
error_byte_r1 <= error_byte;
--FOR i IN 0 TO DWIDTH - 1 LOOP
-- data_error <= error_byte_r1(i) OR data_error;
--END LOOP;
data_error <= REDUCTION_OR(error_byte_r1);--error_byte_r1(i) OR data_error;
--synthesis translate_off
IF (data_error = '1') THEN
report "DATA ERROR"; -- severity ERROR;
end if;
--synthesis translate_on
END IF;
end if;
end process;
gen_dq_error_map: FOR i IN 0 to DQ_ERROR_WIDTH - 1 generate
dq_lane_error(i) <= (error_byte_r1(i) OR error_byte_r1(i+DQ_ERROR_WIDTH) OR
error_byte_r1(i+ (NUM_DQ_PINS*2/8)) OR
error_byte_r1(i+ (NUM_DQ_PINS*3/8)));
cumlative_dq_lane_error_c(i) <= cumlative_dq_lane_error_reg(i) OR dq_lane_error_r1(i);
end generate;
process (clk_i)
begin
IF (clk_i'event and clk_i = '1') then
IF (rst_i(1) = '1' or manual_clear_error = '1') THEN
dq_lane_error_r1 <= (others => '0');
dq_lane_error_r2 <= (others => '0');
data_valid_r <= '0';
cumlative_dq_lane_error_reg <= (others => '0');
ELSE
data_valid_r <= data_valid_i;
dq_lane_error_r1 <= dq_lane_error;
cumlative_dq_lane_error_reg <= cumlative_dq_lane_error_c;
END IF;
END IF;
end process;
end generate;
cumlative_dq_lane_error_r <= cumlative_dq_lane_error_reg;
dq_error_bytelane_cmp <= dq_lane_error_r1;
data_error_o <= data_error;
end architecture trans;
|
--
-- Knobs Galore - a free phase distortion synthesizer
-- Copyright (C) 2015 Ilmo Euro
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.common.all;
entity waveshaper_test is
end entity;
architecture waveshaper_test_impl of waveshaper_test is
begin
end architecture;
|
--
-- Knobs Galore - a free phase distortion synthesizer
-- Copyright (C) 2015 Ilmo Euro
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.common.all;
entity waveshaper_test is
end entity;
architecture waveshaper_test_impl of waveshaper_test is
begin
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.constants_pkg.all;
entity register_file is
generic (
REGISTER_SIZE : positive range 32 to 32;
REGISTER_NAME_SIZE : positive;
READ_PORTS : positive range 1 to 3;
WRITE_FIRST_SMALL_RAMS : boolean
);
port (
clk : in std_logic;
rs1_select : in std_logic_vector(REGISTER_NAME_SIZE-1 downto 0);
rs2_select : in std_logic_vector(REGISTER_NAME_SIZE-1 downto 0);
rs3_select : in std_logic_vector(REGISTER_NAME_SIZE-1 downto 0);
wb_select : in std_logic_vector(REGISTER_NAME_SIZE-1 downto 0);
wb_data : in std_logic_vector(REGISTER_SIZE-1 downto 0);
wb_enable : in std_logic;
rs1_data : out std_logic_vector(REGISTER_SIZE-1 downto 0);
rs2_data : out std_logic_vector(REGISTER_SIZE-1 downto 0);
rs3_data : out std_logic_vector(REGISTER_SIZE-1 downto 0)
);
end;
architecture rtl of register_file is
type register_vector is array(31 downto 0) of std_logic_vector(REGISTER_SIZE-1 downto 0);
signal registers : register_vector := (others => (others => '0'));
--These aliases are useful during simulation of software.
alias ra : std_logic_vector(REGISTER_SIZE-1 downto 0) is registers(to_integer(unsigned(REGISTER_RA)));
alias sp : std_logic_vector(REGISTER_SIZE-1 downto 0) is registers(to_integer(unsigned(REGISTER_SP)));
alias gp : std_logic_vector(REGISTER_SIZE-1 downto 0) is registers(to_integer(unsigned(REGISTER_GP)));
alias tp : std_logic_vector(REGISTER_SIZE-1 downto 0) is registers(to_integer(unsigned(REGISTER_TP)));
alias t0 : std_logic_vector(REGISTER_SIZE-1 downto 0) is registers(to_integer(unsigned(REGISTER_T0)));
alias t1 : std_logic_vector(REGISTER_SIZE-1 downto 0) is registers(to_integer(unsigned(REGISTER_T1)));
alias t2 : std_logic_vector(REGISTER_SIZE-1 downto 0) is registers(to_integer(unsigned(REGISTER_T2)));
alias s0 : std_logic_vector(REGISTER_SIZE-1 downto 0) is registers(to_integer(unsigned(REGISTER_S0)));
alias s1 : std_logic_vector(REGISTER_SIZE-1 downto 0) is registers(to_integer(unsigned(REGISTER_S1)));
alias a0 : std_logic_vector(REGISTER_SIZE-1 downto 0) is registers(to_integer(unsigned(REGISTER_A0)));
alias a1 : std_logic_vector(REGISTER_SIZE-1 downto 0) is registers(to_integer(unsigned(REGISTER_A1)));
alias a2 : std_logic_vector(REGISTER_SIZE-1 downto 0) is registers(to_integer(unsigned(REGISTER_A2)));
alias a3 : std_logic_vector(REGISTER_SIZE-1 downto 0) is registers(to_integer(unsigned(REGISTER_A3)));
alias a4 : std_logic_vector(REGISTER_SIZE-1 downto 0) is registers(to_integer(unsigned(REGISTER_A4)));
alias a5 : std_logic_vector(REGISTER_SIZE-1 downto 0) is registers(to_integer(unsigned(REGISTER_A5)));
alias a6 : std_logic_vector(REGISTER_SIZE-1 downto 0) is registers(to_integer(unsigned(REGISTER_A6)));
alias a7 : std_logic_vector(REGISTER_SIZE-1 downto 0) is registers(to_integer(unsigned(REGISTER_A7)));
alias s2 : std_logic_vector(REGISTER_SIZE-1 downto 0) is registers(to_integer(unsigned(REGISTER_S2)));
alias s3 : std_logic_vector(REGISTER_SIZE-1 downto 0) is registers(to_integer(unsigned(REGISTER_S3)));
alias s4 : std_logic_vector(REGISTER_SIZE-1 downto 0) is registers(to_integer(unsigned(REGISTER_S4)));
alias s5 : std_logic_vector(REGISTER_SIZE-1 downto 0) is registers(to_integer(unsigned(REGISTER_S5)));
alias s6 : std_logic_vector(REGISTER_SIZE-1 downto 0) is registers(to_integer(unsigned(REGISTER_S6)));
alias s7 : std_logic_vector(REGISTER_SIZE-1 downto 0) is registers(to_integer(unsigned(REGISTER_S7)));
alias s8 : std_logic_vector(REGISTER_SIZE-1 downto 0) is registers(to_integer(unsigned(REGISTER_S8)));
alias s9 : std_logic_vector(REGISTER_SIZE-1 downto 0) is registers(to_integer(unsigned(REGISTER_S9)));
alias s10 : std_logic_vector(REGISTER_SIZE-1 downto 0) is registers(to_integer(unsigned(REGISTER_S10)));
alias s11 : std_logic_vector(REGISTER_SIZE-1 downto 0) is registers(to_integer(unsigned(REGISTER_S11)));
alias t3 : std_logic_vector(REGISTER_SIZE-1 downto 0) is registers(to_integer(unsigned(REGISTER_T3)));
alias t4 : std_logic_vector(REGISTER_SIZE-1 downto 0) is registers(to_integer(unsigned(REGISTER_T4)));
alias t5 : std_logic_vector(REGISTER_SIZE-1 downto 0) is registers(to_integer(unsigned(REGISTER_T5)));
alias t6 : std_logic_vector(REGISTER_SIZE-1 downto 0) is registers(to_integer(unsigned(REGISTER_T6)));
begin
bypass_gen : if not WRITE_FIRST_SMALL_RAMS generate
signal out1 : std_logic_vector(REGISTER_SIZE-1 downto 0);
signal out2 : std_logic_vector(REGISTER_SIZE-1 downto 0);
signal out3 : std_logic_vector(REGISTER_SIZE-1 downto 0);
signal read_during_write1 : std_logic;
signal read_during_write2 : std_logic;
signal read_during_write3 : std_logic;
signal wb_data_latched : std_logic_vector(REGISTER_SIZE-1 downto 0);
begin
process (clk) is
begin
if rising_edge(clk) then
out1 <= registers(to_integer(unsigned(rs1_select)));
out2 <= registers(to_integer(unsigned(rs2_select)));
out3 <= registers(to_integer(unsigned(rs3_select)));
if wb_enable = '1' then
registers(to_integer(unsigned(wb_select))) <= wb_data;
end if;
end if;
end process;
--read during write logic
rs1_data <= wb_data_latched when read_during_write1 = '1' else out1;
rs2_data <= wb_data_latched when read_during_write2 = '1' else out2;
rs3_data <= (others => '-') when READ_PORTS < 3 else
wb_data_latched when read_during_write3 = '1' else out3;
process(clk) is
begin
if rising_edge(clk) then
read_during_write3 <= '0';
read_during_write2 <= '0';
read_during_write1 <= '0';
if rs1_select = wb_select and wb_enable = '1' then
read_during_write1 <= '1';
end if;
if rs2_select = wb_select and wb_enable = '1' then
read_during_write2 <= '1';
end if;
if rs3_select = wb_select and wb_enable = '1' then
read_during_write3 <= '1';
end if;
wb_data_latched <= wb_data;
end if;
end process;
end generate bypass_gen;
write_first_gen : if WRITE_FIRST_SMALL_RAMS generate
process (clk) is
variable registers_variable : register_vector := (others => (others => '0'));
begin
if rising_edge(clk) then
if wb_enable = '1' then
registers_variable(to_integer(unsigned(wb_select))) := wb_data;
end if;
rs1_data <= registers_variable(to_integer(unsigned(rs1_select)));
rs2_data <= registers_variable(to_integer(unsigned(rs2_select)));
rs3_data <= registers_variable(to_integer(unsigned(rs3_select)));
end if;
end process;
process (clk) is
begin
if rising_edge(clk) then
--Vivado simulator doesn't like tracing variables so this signal
--duplicates the register_file variable
if wb_enable = '1' then
registers(to_integer(unsigned(wb_select))) <= wb_data;
end if;
end if;
end process;
end generate write_first_gen;
end architecture;
|
--pragma translate_off
--------------------------------------------------------------------------------
-- File Name: idt7202.vhd
--------------------------------------------------------------------------------
-- Copyright (C) 2001 Free Model Foundry; http://www.FreeModelFoundry.com
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License version 2 as
-- published by the Free Software Foundation.
--
-- MODIFICATION HISTORY:
--
-- version: | author: | mod date: | changes made:
-- V1.0 R. Munden 01 Feb 10 Initial release
-- V1.1 D. Rambaud 01 OCT 24 fixed problem with RDPoint
-- V1.2 S. Habinc 06 Apr 18 fixed problem with RDPoint
--
--------------------------------------------------------------------------------
-- PART DESCRIPTION:
--
-- Library: FIFO
-- Technology: CMOS
-- Part: IDT7202
--
-- Description: Async FIFO 1,024 x 9
--------------------------------------------------------------------------------
LIBRARY IEEE; USE IEEE.std_logic_1164.ALL;
USE IEEE.VITAL_timing.ALL;
USE IEEE.VITAL_primitives.ALL;
LIBRARY FMF; USE FMF.gen_utils.ALL;
USE FMF.conversions.ALL;
--------------------------------------------------------------------------------
-- ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY idt7202 IS
GENERIC (
-- tipd delays: interconnect path delays
tipd_D0 : VitalDelayType01 := VitalZeroDelay01;
tipd_D1 : VitalDelayType01 := VitalZeroDelay01;
tipd_D2 : VitalDelayType01 := VitalZeroDelay01;
tipd_D3 : VitalDelayType01 := VitalZeroDelay01;
tipd_D4 : VitalDelayType01 := VitalZeroDelay01;
tipd_D5 : VitalDelayType01 := VitalZeroDelay01;
tipd_D6 : VitalDelayType01 := VitalZeroDelay01;
tipd_D7 : VitalDelayType01 := VitalZeroDelay01;
tipd_D8 : VitalDelayType01 := VitalZeroDelay01;
tipd_FLNeg : VitalDelayType01 := VitalZeroDelay01;
tipd_RNeg : VitalDelayType01 := VitalZeroDelay01;
tipd_RSNeg : VitalDelayType01 := VitalZeroDelay01;
tipd_WNeg : VitalDelayType01 := VitalZeroDelay01;
tipd_XINeg : VitalDelayType01 := VitalZeroDelay01;
-- tpd delays
tpd_FLNeg_EFNeg : VitalDelayType01 := UnitDelay01;
tpd_RNeg_Q0 : VitalDelayType01Z := UnitDelay01Z;
tpd_RNeg_EFNeg : VitalDelayType01 := UnitDelay01;
tpd_RNeg_FFNeg : VitalDelayType01 := UnitDelay01;
tpd_RNeg_XONeg : VitalDelayType01 := UnitDelay01;
tpd_RSNeg_EFNeg : VitalDelayType01 := UnitDelay01;
tpd_RSNeg_FFNeg : VitalDelayType01 := UnitDelay01;
tpd_RSNeg_XONeg : VitalDelayType01 := UnitDelay01;
tpd_WNeg_Q0 : VitalDelayType01Z := UnitDelay01Z;
tpd_WNeg_EFNeg : VitalDelayType01 := UnitDelay01;
tpd_WNeg_FFNeg : VitalDelayType01 := UnitDelay01;
tpd_WNeg_XONeg : VitalDelayType01 := UnitDelay01;
-- tpw values: pulse widths
tpw_RNeg_negedge : VitalDelayType := UnitDelay;
tpw_RNeg_posedge : VitalDelayType := UnitDelay;
tpw_WNeg_negedge : VitalDelayType := UnitDelay;
tpw_WNeg_posedge : VitalDelayType := UnitDelay;
tpw_RSNeg_negedge : VitalDelayType := UnitDelay;
tpw_FLNeg_negedge : VitalDelayType := UnitDelay;
tpw_FLNeg_posedge : VitalDelayType := UnitDelay;
tpw_XINeg_negedge : VitalDelayType := UnitDelay;
tpw_XINeg_posedge : VitalDelayType := UnitDelay;
-- tperiod_min: minimum clock period = 1/max freq
tperiod_RNeg : VitalDelayType := UnitDelay;
tperiod_WNeg : VitalDelayType := UnitDelay;
-- tsetup values: setup times
tsetup_D0_WNeg : VitalDelayType := UnitDelay;
tsetup_RNeg_RSNeg : VitalDelayType := UnitDelay;
tsetup_RNeg_FLNeg : VitalDelayType := UnitDelay;
tsetup_XINeg_RNeg : VitalDelayType := UnitDelay;
-- thold values: hold times
thold_D0_WNeg : VitalDelayType := UnitDelay;
thold_RNeg_RSNeg : VitalDelayType := UnitDelay;
thold_RNeg_FLNeg : VitalDelayType := UnitDelay;
-- generic control parameters
InstancePath : STRING := DefaultInstancePath;
TimingChecksOn : BOOLEAN := DefaultTimingChecks;
MsgOn : BOOLEAN := DefaultMsgOn;
XOn : BOOLEAN := DefaultXon;
-- For FMF SDF technology file usage
TimingModel : STRING := DefaultTimingModel
);
PORT (
D0 : IN std_ulogic := 'U';
D1 : IN std_ulogic := 'U';
D2 : IN std_ulogic := 'U';
D3 : IN std_ulogic := 'U';
D4 : IN std_ulogic := 'U';
D5 : IN std_ulogic := 'U';
D6 : IN std_ulogic := 'U';
D7 : IN std_ulogic := 'U';
D8 : IN std_ulogic := 'U';
Q0 : OUT std_ulogic := 'U';
Q1 : OUT std_ulogic := 'U';
Q2 : OUT std_ulogic := 'U';
Q3 : OUT std_ulogic := 'U';
Q4 : OUT std_ulogic := 'U';
Q5 : OUT std_ulogic := 'U';
Q6 : OUT std_ulogic := 'U';
Q7 : OUT std_ulogic := 'U';
Q8 : OUT std_ulogic := 'U';
EFNeg : OUT std_ulogic := 'U';
FFNeg : OUT std_ulogic := 'U';
FLNeg : IN std_ulogic := 'U';
RNeg : IN std_ulogic := 'U';
RSNeg : IN std_ulogic := 'U';
WNeg : IN std_ulogic := 'U';
XINeg : IN std_ulogic := 'U';
XONeg : OUT std_ulogic := 'U'
);
ATTRIBUTE VITAL_LEVEL0 of idt7202 : ENTITY IS TRUE;
END idt7202;
--------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of idt7202 IS
ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE;
CONSTANT partID : STRING := "IDT7202";
CONSTANT MaxData : NATURAL := 511;
CONSTANT TotalLOC : NATURAL := 1023;
CONSTANT Half : NATURAL := TotalLOC/2;
CONSTANT DataWidth : NATURAL := 9;
CONSTANT HiDbit : NATURAL := 8;
SIGNAL D0_ipd : std_ulogic := 'U';
SIGNAL D1_ipd : std_ulogic := 'U';
SIGNAL D2_ipd : std_ulogic := 'U';
SIGNAL D3_ipd : std_ulogic := 'U';
SIGNAL D4_ipd : std_ulogic := 'U';
SIGNAL D5_ipd : std_ulogic := 'U';
SIGNAL D6_ipd : std_ulogic := 'U';
SIGNAL D7_ipd : std_ulogic := 'U';
SIGNAL D8_ipd : std_ulogic := 'U';
SIGNAL FLNeg_ipd : std_ulogic := 'U';
SIGNAL RNeg_ipd : std_ulogic := 'U';
SIGNAL RSNeg_ipd : std_ulogic := 'U';
SIGNAL WNeg_ipd : std_ulogic := 'U';
SIGNAL XINeg_ipd : std_ulogic := 'U';
BEGIN
----------------------------------------------------------------------------
-- Wire Delays
----------------------------------------------------------------------------
WireDelay : BLOCK
BEGIN
w_1 : VitalWireDelay (D0_ipd, D0, tipd_D0);
w_2 : VitalWireDelay (D1_ipd, D1, tipd_D1);
w_3 : VitalWireDelay (D2_ipd, D2, tipd_D2);
w_4 : VitalWireDelay (D3_ipd, D3, tipd_D3);
w_5 : VitalWireDelay (D4_ipd, D4, tipd_D4);
w_6 : VitalWireDelay (D5_ipd, D5, tipd_D5);
w_7 : VitalWireDelay (D6_ipd, D6, tipd_D6);
w_8 : VitalWireDelay (D7_ipd, D7, tipd_D7);
w_9 : VitalWireDelay (D8_ipd, D8, tipd_D8);
w_21 : VitalWireDelay (FLNeg_ipd, FLNeg, tipd_FLNeg);
w_22 : VitalWireDelay (RNeg_ipd, RNeg, tipd_RNeg);
w_23 : VitalWireDelay (RSNeg_ipd, RSNeg, tipd_RSNeg);
w_24 : VitalWireDelay (WNeg_ipd, WNeg, tipd_WNeg);
w_25 : VitalWireDelay (XINeg_ipd, XINeg, tipd_XINeg);
END BLOCK;
----------------------------------------------------------------------------
-- Main Behavior Block
----------------------------------------------------------------------------
Behavior: BLOCK
PORT (
DIn : IN std_logic_vector(HiDbit downto 0);
QOut : OUT std_logic_vector(HiDbit downto 0);
FLNegIn : IN std_Ulogic := 'U';
RNegIn : IN std_Ulogic := 'U';
RSNegIn : IN std_Ulogic := 'U';
WNegIn : IN std_Ulogic := 'U';
XINegIn : IN std_Ulogic := 'U';
EFNegOut : OUT std_Ulogic := 'U';
FFNegOut : OUT std_Ulogic := 'U';
XONegOut : OUT std_Ulogic := 'U'
);
PORT MAP (
DIn(0) => D0_ipd,
DIn(1) => D1_ipd,
DIn(2) => D2_ipd,
DIn(3) => D3_ipd,
DIn(4) => D4_ipd,
DIn(5) => D5_ipd,
DIn(6) => D6_ipd,
DIn(7) => D7_ipd,
DIn(8) => D8_ipd,
QOut(0) => Q0,
QOut(1) => Q1,
QOut(2) => Q2,
QOut(3) => Q3,
QOut(4) => Q4,
QOut(5) => Q5,
QOut(6) => Q6,
QOut(7) => Q7,
QOut(8) => Q8,
FLNegIn => FLNeg_ipd,
RSNegIn => RSNeg_ipd,
XINegIn => XINeg_ipd,
RNegIn => RNeg_ipd,
WNegIn => WNeg_ipd,
EFNegOut => EFNeg,
FFNegOut => FFNeg,
XONegOut => XONeg
);
SIGNAL Q_zd : std_logic_vector(HiDbit downto 0) := (others => 'Z');
SIGNAL EF_pulse : std_ulogic := '0';
SIGNAL FF_pulse : std_ulogic := '0';
BEGIN
------------------------------------------------------------------------
-- Behavior Process
------------------------------------------------------------------------
Fifo : PROCESS (DIn, FLNegIn, RSNegIn, XINegIn, RNegIn, WNegIn,
EF_pulse, FF_pulse)
-- Timing Check Variables
VARIABLE Tviol_D0_WNeg : X01 := '0';
VARIABLE TD_D0_WNeg : VitalTimingDataType;
VARIABLE Tviol_RNeg_RSNeg : X01 := '0';
VARIABLE TD_RNeg_RSNeg : VitalTimingDataType;
VARIABLE Tviol_RNeg_FLNeg : X01 := '0';
VARIABLE TD_RNeg_FLNeg : VitalTimingDataType;
VARIABLE Tviol_XINeg_RNeg : X01 := '0';
VARIABLE TD_XINeg_RNeg : VitalTimingDataType;
VARIABLE Tviol_XINeg_WNeg : X01 := '0';
VARIABLE TD_XINeg_WNeg : VitalTimingDataType;
VARIABLE Pviol_RNeg : X01 := '0';
VARIABLE TD_RNeg : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE Pviol_WNeg : X01 := '0';
VARIABLE TD_WNeg : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE Pviol_RSNeg : X01 := '0';
VARIABLE TD_RSNeg : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE Pviol_FLNeg : X01 := '0';
VARIABLE TD_FLNeg : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE Pviol_XINeg : X01 := '0';
VARIABLE TD_XINeg : VitalPeriodDataType := VitalPeriodDataInit;
-- Memory array declaration
TYPE MemStore IS ARRAY (0 to TotalLOC) OF INTEGER
RANGE -2 TO MaxData;
-- Functionality Results Variables
VARIABLE Violation : X01 := '0';
TYPE mode_type IS (unk, single, first_exp, other_exp);
TYPE stat_type IS (inact, act);
VARIABLE mode : mode_type;
VARIABLE rd_stat : stat_type;
VARIABLE wr_stat : stat_type;
VARIABLE EFNeg_zd : std_ulogic;
VARIABLE FFNeg_zd : std_ulogic;
VARIABLE XONeg_zd : std_ulogic;
VARIABLE EF_pzd : std_ulogic;
VARIABLE FF_pzd : std_ulogic;
VARIABLE RDPoint : INTEGER RANGE 0 TO TotalLoc := 0;
VARIABLE WRPoint : INTEGER RANGE 0 TO TotalLoc := 0;
VARIABLE Count : INTEGER RANGE 0 TO TotalLoc := 0;
VARIABLE MemData : MemStore;
VARIABLE DataDrive : std_logic_vector(HiDbit DOWNTO 0)
:= (OTHERS => 'Z');
-- Output Glitch Detection Variables
VARIABLE FFNeg_GlitchData : VitalGlitchDataType;
VARIABLE EFNeg_GlitchData : VitalGlitchDataType;
VARIABLE XONeg_GlitchData : VitalGlitchDataType;
VARIABLE EFp_GlitchData : VitalGlitchDataType;
VARIABLE FFp_GlitchData : VitalGlitchDataType;
-- No Weak Values Variables
VARIABLE FLNeg_nwv : UX01 := 'U';
VARIABLE WNeg_nwv : UX01 := 'U';
VARIABLE RNeg_nwv : UX01 := 'U';
VARIABLE RSNeg_nwv : UX01 := 'U';
VARIABLE XINeg_nwv : UX01 := 'U';
BEGIN
FLNeg_nwv := To_UX01 (s => FLNegIn);
WNeg_nwv := To_UX01 (s => WNegIn);
RNeg_nwv := To_UX01 (s => RNegIn);
RSNeg_nwv := To_UX01 (s => RSNegIn);
XINeg_nwv := To_UX01 (s => XINegIn);
--------------------------------------------------------------------
-- Timing Check Section
--------------------------------------------------------------------
IF (TimingChecksOn) THEN
VitalSetupHoldCheck (
TestSignal => DIn,
TestSignalName => "D",
RefSignal => WNegIn,
RefSignalName => "WNeg",
SetupHigh => tsetup_D0_WNeg,
SetupLow => tsetup_D0_WNeg,
HoldHigh => thold_D0_WNeg,
HoldLow => thold_D0_WNeg,
CheckEnabled => (WNeg_nwv ='0'),
RefTransition => '/',
HeaderMsg => InstancePath & PartID,
TimingData => TD_D0_WNeg,
XOn => XOn,
MsgOn => MsgOn,
Violation => Tviol_D0_WNeg );
VitalSetupHoldCheck (
TestSignal => RNegIn,
TestSignalName => "RNeg",
RefSignal => RSNegIn,
RefSignalName => "RSNeg",
SetupHigh => tsetup_RNeg_RSNeg,
SetupLow => tsetup_RNeg_RSNeg,
HoldHigh => thold_RNeg_RSNeg,
HoldLow => thold_RNeg_RSNeg,
CheckEnabled => (RSNeg_nwv ='0'),
RefTransition => '/',
HeaderMsg => InstancePath & PartID,
TimingData => TD_RNeg_RSNeg,
XOn => XOn,
MsgOn => MsgOn,
Violation => Tviol_RNeg_RSNeg );
VitalSetupHoldCheck (
TestSignal => RNegIn,
TestSignalName => "RNeg",
RefSignal => FLNegIn,
RefSignalName => "FLNeg",
SetupHigh => tsetup_RNeg_FLNeg,
SetupLow => tsetup_RNeg_FLNeg,
HoldHigh => thold_RNeg_FLNeg,
HoldLow => thold_RNeg_FLNeg,
CheckEnabled => (FLNeg_nwv ='0'),
RefTransition => '/',
HeaderMsg => InstancePath & PartID,
TimingData => TD_RNeg_FLNeg,
XOn => XOn,
MsgOn => MsgOn,
Violation => Tviol_RNeg_FLNeg );
VitalSetupHoldCheck (
TestSignal => XINegIn,
TestSignalName => "XINeg",
RefSignal => RNegIn,
RefSignalName => "RNeg",
SetupHigh => tsetup_XINeg_RNeg,
SetupLow => tsetup_XINeg_RNeg,
CheckEnabled => true,
RefTransition => '/',
HeaderMsg => InstancePath & PartID,
TimingData => TD_XINeg_RNeg,
XOn => XOn,
MsgOn => MsgOn,
Violation => Tviol_XINeg_RNeg );
VitalSetupHoldCheck (
TestSignal => XINegIn,
TestSignalName => "XINeg",
RefSignal => WNegIn,
RefSignalName => "WNeg",
SetupHigh => tsetup_XINeg_RNeg,
SetupLow => tsetup_XINeg_RNeg,
CheckEnabled => true,
RefTransition => '/',
HeaderMsg => InstancePath & PartID,
TimingData => TD_XINeg_WNeg,
XOn => XOn,
MsgOn => MsgOn,
Violation => Tviol_XINeg_WNeg );
VitalPeriodPulseCheck (
TestSignal => RNegIn,
TestSignalName => "RNeg",
Period => tperiod_RNeg,
PulseWidthLow => tpw_RNeg_negedge,
PulseWidthHigh => tpw_RNeg_posedge,
PeriodData => TD_RNeg,
XOn => XOn,
MsgOn => MsgOn,
HeaderMsg => InstancePath & PartID,
CheckEnabled => TRUE,
Violation => Pviol_RNeg );
VitalPeriodPulseCheck (
TestSignal => WNegIn,
TestSignalName => "WNeg",
Period => tperiod_WNeg,
PulseWidthLow => tpw_WNeg_negedge,
PulseWidthHigh => tpw_WNeg_posedge,
PeriodData => TD_WNeg,
XOn => XOn,
MsgOn => MsgOn,
HeaderMsg => InstancePath & PartID,
CheckEnabled => TRUE,
Violation => Pviol_WNeg );
VitalPeriodPulseCheck (
TestSignal => XINegIn,
TestSignalName => "XINeg",
PulseWidthLow => tpw_XINeg_negedge,
PeriodData => TD_XINeg,
XOn => XOn,
MsgOn => MsgOn,
HeaderMsg => InstancePath & PartID,
CheckEnabled => TRUE,
Violation => Pviol_XINeg );
VitalPeriodPulseCheck (
TestSignal => FLNegIn,
TestSignalName => "FLNeg",
PulseWidthLow => tpw_FLNeg_negedge,
PulseWidthHigh => tpw_FLNeg_posedge,
PeriodData => TD_FLNeg,
XOn => XOn,
MsgOn => MsgOn,
HeaderMsg => InstancePath & PartID,
CheckEnabled => TRUE,
Violation => Pviol_FLNeg );
END IF; -- Timing Check Section
--------------------------------------------------------------------
-- Functional Section
--------------------------------------------------------------------
Violation := Tviol_D0_WNeg OR Tviol_RNeg_RSNeg OR Tviol_RNeg_FLNeg
OR Tviol_XINeg_RNeg OR Tviol_XINeg_WNeg OR Pviol_RNeg
OR Pviol_WNeg OR Pviol_RSNeg OR Pviol_FLNeg OR
Pviol_XINeg;
IF (Violation = 'X') THEN
DataDrive := (OTHERS => 'X');
FFNeg_zd := 'X';
EFNeg_zd := 'X';
XONeg_zd := 'X';
ELSIF falling_edge(RSNegIn) THEN
RDPoint := 0;
WRPoint := 0;
Count := 0;
ELSIF rising_edge(RSNegIn) THEN
FFNeg_zd := '1';
XONeg_zd := '1';
EFNeg_zd := '0';
IF XINeg_nwv = '0' THEN
mode := single;
rd_stat := act;
wr_stat := act;
ELSIF FLNeg_nwv = '0' THEN
mode := first_exp;
rd_stat := act;
wr_stat := act;
ELSE
mode := other_exp;
rd_stat := inact;
wr_stat := inact;
END IF;
END IF;
IF rising_edge(WNegIn) THEN
IF wr_stat = act AND FFNeg_zd = '1' THEN
IF Violation = '0' THEN
MemData(WRPoint) := To_Nat(DIn);
ELSE
MemData(WRPoint) := -1;
END IF;
Count := Count + 1;
IF WRPoint = TotalLoc THEN
WRPoint := 0;
ELSE
WRPoint := WRPoint + 1;
END IF;
IF Count > Half AND mode = single THEN
XONeg_zd := '0';
ELSE
XONeg_zd := '1';
END IF;
IF Count = TotalLoc THEN
FFNeg_zd := '0';
ELSE
FFNeg_zd := '1';
END IF;
IF EFNeg_zd = '0' AND RNeg_nwv = '0' THEN
DataDrive := To_X01(DIn);
EF_pzd := '1';
Count := Count - 1;
RDPoint := RDPoint + 1;
END IF;
EFNeg_zd := '1';
ELSE
IF mode /= single THEN
XONeg_zd := '1';
END IF;
END IF;
ELSIF falling_edge(WNegIn) AND mode /= single AND Count = TotalLoc THEN
XONeg_zd := '0';
wr_stat := inact;
END IF;
IF falling_edge(RNegIn) AND EFNeg_zd = '1' AND rd_stat = act THEN
IF Violation = '0' THEN
IF MemData(RDPoint) >= 0 THEN
DataDrive := To_slv(MemData(RDPoint), DataWidth);
ELSE
DataDrive := (OTHERS => 'X');
END IF;
ELSE
MemData(WRPoint) := -1;
END IF;
Count := Count - 1;
IF Count > Half AND mode = single THEN
XONeg_zd := '0';
ELSE
XONeg_zd := '1';
END IF;
IF Count = 0 THEN
EFNeg_zd := '0';
IF mode = other_exp THEN
XONeg_zd := '0';
END IF;
ELSE
EFNeg_zd := '1';
END IF;
if (RDPoint = WRPoint-1) or -- We must increment RDPoint if it
(WRPoint=0 and RDPoint=TotalLoc) then -- is the last element because...
IF RDPoint = TotalLoc THEN
RDPoint := 0;
ELSE
RDPoint := RDPoint + 1;
END IF;
end if;
ELSIF rising_edge(RNegIn) THEN
IF EFNeg_zd = '1' AND rd_stat = act THEN
IF FFNeg_zd = '0' AND WNeg_nwv = '0' THEN
FF_pzd := '1';
END IF;
FFNeg_zd := '1';
IF RDPoint = TotalLoc THEN
RDPoint := 0;
ELSE
RDPoint := RDPoint + 1;
END if;
END IF;
IF mode = other_exp AND Count = 0 THEN
XONeg_zd := '1';
rd_stat := inact;
END IF;
END IF;
IF falling_edge(FLNegIn) AND XINeg_nwv = '0' THEN
RDPoint := 0;
Count := WRPoint;
IF Count > Half THEN
XONeg_zd := '0';
ELSE
XONeg_zd := '1';
END IF;
IF Count = 0 THEN
EFNeg_zd := '0';
ELSE
EFNeg_zd := '1';
END IF;
IF Count = TotalLoc THEN
FFNeg_zd := '0';
ELSE
FFNeg_zd := '1';
END IF;
ELSIF falling_edge(XINegIn) AND mode = other_exp THEN
IF wr_stat = inact THEN
wr_stat := act;
ELSE
rd_stat := act;
END IF;
END IF;
IF rising_edge(EF_pulse) THEN
EFNeg_zd := '0';
EF_pulse <= '0';
ELSIF rising_edge(FF_pulse) THEN
FFNeg_zd := '0';
FF_pulse <= '0';
END IF;
IF rising_edge(RNegIn) THEN
DataDrive := (others => 'Z');
END IF;
Q_zd <= DataDrive;
--------------------------------------------------------------------
-- Path Delay Section
--------------------------------------------------------------------
VitalPathDelay01 (
OutSignal => EF_pulse,
OutSignalName => "EF_pulse",
OutTemp => EF_pzd,
GlitchData => EFp_GlitchData,
XOn => false,
MsgOn => false,
Paths => (
0 => (InputChangeTime => WNeg'LAST_EVENT,
PathDelay => tpd_RNeg_EFNeg,
PathCondition => true)
)
);
VitalPathDelay01 (
OutSignal => FF_pulse,
OutSignalName => "FF_pulse",
OutTemp => FF_pzd,
GlitchData => FFp_GlitchData,
XOn => false,
MsgOn => false,
Paths => (
0 => (InputChangeTime => RNeg'LAST_EVENT,
PathDelay => tpd_WNeg_FFNeg,
PathCondition => true)
)
);
VitalPathDelay01 (
OutSignal => EFNegOut,
OutSignalName => "EFNeg",
OutTemp => EFNeg_zd,
GlitchData => EFNeg_GlitchData,
XOn => XOn,
MsgOn => MsgOn,
Paths => (
0 => (InputChangeTime => FLNeg'LAST_EVENT,
PathDelay => tpd_FLNeg_EFNeg,
PathCondition => FLNeg_nwv = '0'),
1 => (InputChangeTime => RNeg'LAST_EVENT,
PathDelay => tpd_RNeg_EFNeg,
PathCondition => true),
2 => (InputChangeTime => WNeg'LAST_EVENT,
PathDelay => tpd_WNeg_EFNeg,
PathCondition => true),
3 => (InputChangeTime => RSNeg'LAST_EVENT,
PathDelay => tpd_RSNeg_EFNeg,
PathCondition => true),
4 => (InputChangeTime => EF_pulse'LAST_EVENT,
PathDelay => tpd_RNeg_EFNeg,
PathCondition => true)
)
);
VitalPathDelay01 (
OutSignal => FFNegOut,
OutSignalName => "FFNeg",
OutTemp => FFNeg_zd,
GlitchData => FFNeg_GlitchData,
XOn => XOn,
MsgOn => MsgOn,
Paths => (
0 => (InputChangeTime => FLNeg'LAST_EVENT,
PathDelay => tpd_FLNeg_EFNeg,
PathCondition => FLNeg_nwv = '0'),
1 => (InputChangeTime => RNeg'LAST_EVENT,
PathDelay => tpd_RNeg_FFNeg,
PathCondition => true),
2 => (InputChangeTime => WNeg'LAST_EVENT,
PathDelay => tpd_WNeg_FFNeg,
PathCondition => true),
3 => (InputChangeTime => RSNeg'LAST_EVENT,
PathDelay => tpd_RSNeg_FFNeg,
PathCondition => true),
4 => (InputChangeTime => FF_pulse'LAST_EVENT,
PathDelay => tpd_WNeg_EFNeg,
PathCondition => true)
)
);
VitalPathDelay01 (
OutSignal => XONegOut,
OutSignalName => "XONeg",
OutTemp => XONeg_zd,
GlitchData => XONeg_GlitchData,
XOn => XOn,
MsgOn => MsgOn,
Paths => (
0 => (InputChangeTime => FLNeg'LAST_EVENT,
PathDelay => tpd_FLNeg_EFNeg,
PathCondition => FLNeg_nwv = '0'),
1 => (InputChangeTime => RNeg'LAST_EVENT,
PathDelay => tpd_RNeg_XONeg,
PathCondition => true),
2 => (InputChangeTime => WNeg'LAST_EVENT,
PathDelay => tpd_WNeg_XONeg,
PathCondition => true),
3 => (InputChangeTime => RSNeg'LAST_EVENT,
PathDelay => tpd_RSNeg_XONeg,
PathCondition => true)
)
);
END PROCESS Fifo;
------------------------------------------------------------------------
-- Path Delay Processes generated as a function of data width
------------------------------------------------------------------------
DataOut_Width : FOR i IN HiDbit DOWNTO 0 GENERATE
DataOut_Delay : PROCESS (Q_zd(i))
VARIABLE Q_GlitchData:VitalGlitchDataArrayType(HiDbit Downto 0);
BEGIN
VitalPathDelay01Z (
OutSignal => QOut(i),
OutSignalName => "Q",
OutTemp => Q_zd(i),
Mode => VitalTransport,
GlitchData => Q_GlitchData(i),
Paths => (
0 => (InputChangeTime => RNegIn'LAST_EVENT,
PathDelay => tpd_RNeg_Q0,
PathCondition => TRUE),
1 => (InputChangeTime => WNegIn'LAST_EVENT,
PathDelay => tpd_WNeg_Q0,
PathCondition => TRUE)
)
);
END PROCESS;
END GENERATE;
END BLOCK;
END vhdl_behavioral;
--pragma translate_on
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
package plasoc_cpu_pack is
-- Default parameters.
constant default_cpu_mult_type : string := "DEFAULT";
constant default_cpu_shifter_type : string := "DEFAULT";
constant default_cpu_alu_type : string := "DEFAULT";
constant default_cache_address_width : integer := 25;
constant default_cache_way_width : integer := 1;
constant default_cache_index_width : integer := 6;
constant default_cache_offset_width : integer := 4;
constant default_cache_replace_strat : string := "rr";
constant default_cache_enable : boolean := True;
constant default_oper_base : std_logic_vector := X"ffffff";
constant default_oper_invalidate_offset : integer := 0;
constant default_oper_flush_offset : integer := 4;
-- AXI4-Full error constants.
constant error_axi_read_exokay : integer := 0;
constant error_axi_read_slverr : integer := 1;
constant error_axi_read_decerr : integer := 2;
constant error_axi_read_rlast : integer := 3;
constant error_axi_read_id : integer := 4;
-- AXI4-Full constants.
subtype axi_resp_type is std_logic_vector(1 downto 0);
constant axi_lock_normal_access : std_logic := '0';
constant axi_burst_incr : std_logic_vector(1 downto 0) := "01";
constant axi_resp_okay : axi_resp_type := "00";
constant axi_resp_exokay : axi_resp_type := "01";
constant axi_resp_slverr : axi_resp_type := "10";
constant axi_resp_decerr : axi_resp_type := "11";
constant axi_cache_device_nonbufferable : std_logic_vector(3 downto 0) := "0000";
constant axi_prot_priv : std_logic := '1';
constant axi_prot_sec : std_logic := '0';
constant axi_prot_instr : std_logic := '1';
-- Function declarations.
function clogb2(bit_depth : in integer ) return integer;
function add_offset2base( base_address : in std_logic_vector; offset : in integer ) return std_logic_vector;
-- Component declaration.
component plasoc_cpu is
generic(
cpu_mult_type : string := default_cpu_mult_type;
cpu_shifter_type : string := default_cpu_shifter_type;
cpu_alu_type : string := default_cpu_alu_type;
cache_address_width : integer := default_cache_address_width;
cache_way_width : integer := default_cache_way_width;
cache_index_width : integer := default_cache_index_width;
cache_offset_width : integer := default_cache_offset_width;
cache_replace_strat : string := default_cache_replace_strat;
cache_enable : boolean := default_cache_enable;
oper_base : std_logic_vector := default_oper_base;
oper_invalidate_offset : integer := default_oper_invalidate_offset;
oper_flush_offset : integer := default_oper_flush_offset );
port(
aclk : in std_logic;
aresetn : in std_logic;
axi_awid : out std_logic_vector(-1 downto 0);
axi_awaddr : out std_logic_vector(31 downto 0);
axi_awlen : out std_logic_vector(7 downto 0);
axi_awsize : out std_logic_vector(2 downto 0);
axi_awburst : out std_logic_vector(1 downto 0);
axi_awlock : out std_logic;
axi_awcache : out std_logic_vector(3 downto 0);
axi_awprot : out std_logic_vector(2 downto 0);
axi_awqos : out std_logic_vector(3 downto 0);
axi_awregion : out std_logic_vector(3 downto 0);
axi_awvalid : out std_logic;
axi_awready : in std_logic;
axi_wdata : out std_logic_vector(31 downto 0);
axi_wstrb : out std_logic_vector(3 downto 0);
axi_wlast : out std_logic;
axi_wvalid : out std_logic;
axi_wready : in std_logic;
axi_bid : in std_logic_vector(-1 downto 0);
axi_bresp : in std_logic_vector(1 downto 0);
axi_bvalid : in std_logic;
axi_bready : out std_logic;
axi_arid : out std_logic_vector(-1 downto 0);
axi_araddr : out std_logic_vector(31 downto 0);
axi_arlen : out std_logic_vector(7 downto 0);
axi_arsize : out std_logic_vector(2 downto 0);
axi_arburst : out std_logic_vector(1 downto 0);
axi_arlock : out std_logic;
axi_arcache : out std_logic_vector(3 downto 0);
axi_arprot : out std_logic_vector(2 downto 0);
axi_arqos : out std_logic_vector(3 downto 0);
axi_arregion : out std_logic_vector(3 downto 0);
axi_arvalid : out std_logic;
axi_arready : in std_logic;
axi_rid : in std_logic_vector(-1 downto 0);
axi_rdata : in std_logic_vector(31 downto 0);
axi_rresp : in std_logic_vector(1 downto 0);
axi_rlast : in std_logic;
axi_rvalid : in std_logic;
axi_rready : out std_logic;
intr_in : in std_logic);
end component;
end;
package body plasoc_cpu_pack is
function flogb2(bit_depth : in natural ) return integer is
variable result : integer := 0;
variable bit_depth_buff : integer := bit_depth;
begin
while bit_depth_buff>1 loop
bit_depth_buff := bit_depth_buff/2;
result := result+1;
end loop;
return result;
end function flogb2;
function clogb2 (bit_depth : in natural ) return natural is
variable result : integer := 0;
begin
result := flogb2(bit_depth);
if (bit_depth > (2**result)) then
return(result + 1);
else
return result;
end if;
end function clogb2;
function add_offset2base( base_address : in std_logic_vector; offset : in integer ) return std_logic_vector is
variable result : std_logic_vector(base_address'length-1 downto 0);
begin
result := std_logic_vector(to_unsigned(to_integer(unsigned(base_address))+offset,base_address'length));
return result;
end;
end;
|
library verilog;
use verilog.vl_types.all;
entity MF_stratixiii_pll is
generic(
operation_mode : string := "normal";
pll_type : string := "auto";
compensate_clock: string := "clock0";
inclk0_input_frequency: integer := 0;
inclk1_input_frequency: integer := 0;
self_reset_on_loss_lock: string := "off";
switch_over_type: string := "auto";
switch_over_counter: integer := 1;
enable_switch_over_counter: string := "off";
dpa_multiply_by : integer := 0;
dpa_divide_by : integer := 0;
dpa_divider : integer := 0;
bandwidth : integer := 0;
bandwidth_type : string := "auto";
use_dc_coupling : string := "false";
lock_high : integer := 0;
lock_low : integer := 0;
lock_window_ui : string := "0.05";
test_bypass_lock_detect: string := "off";
clk0_output_frequency: integer := 0;
clk0_multiply_by: integer := 0;
clk0_divide_by : integer := 0;
clk0_phase_shift: string := "0";
clk0_duty_cycle : integer := 50;
clk1_output_frequency: integer := 0;
clk1_multiply_by: integer := 0;
clk1_divide_by : integer := 0;
clk1_phase_shift: string := "0";
clk1_duty_cycle : integer := 50;
clk2_output_frequency: integer := 0;
clk2_multiply_by: integer := 0;
clk2_divide_by : integer := 0;
clk2_phase_shift: string := "0";
clk2_duty_cycle : integer := 50;
clk3_output_frequency: integer := 0;
clk3_multiply_by: integer := 0;
clk3_divide_by : integer := 0;
clk3_phase_shift: string := "0";
clk3_duty_cycle : integer := 50;
clk4_output_frequency: integer := 0;
clk4_multiply_by: integer := 0;
clk4_divide_by : integer := 0;
clk4_phase_shift: string := "0";
clk4_duty_cycle : integer := 50;
clk5_output_frequency: integer := 0;
clk5_multiply_by: integer := 0;
clk5_divide_by : integer := 0;
clk5_phase_shift: string := "0";
clk5_duty_cycle : integer := 50;
clk6_output_frequency: integer := 0;
clk6_multiply_by: integer := 0;
clk6_divide_by : integer := 0;
clk6_phase_shift: string := "0";
clk6_duty_cycle : integer := 50;
clk7_output_frequency: integer := 0;
clk7_multiply_by: integer := 0;
clk7_divide_by : integer := 0;
clk7_phase_shift: string := "0";
clk7_duty_cycle : integer := 50;
clk8_output_frequency: integer := 0;
clk8_multiply_by: integer := 0;
clk8_divide_by : integer := 0;
clk8_phase_shift: string := "0";
clk8_duty_cycle : integer := 50;
clk9_output_frequency: integer := 0;
clk9_multiply_by: integer := 0;
clk9_divide_by : integer := 0;
clk9_phase_shift: string := "0";
clk9_duty_cycle : integer := 50;
pfd_min : integer := 0;
pfd_max : integer := 0;
vco_min : integer := 0;
vco_max : integer := 0;
vco_center : integer := 0;
m_initial : integer := 1;
m : integer := 0;
n : integer := 1;
c0_high : integer := 1;
c0_low : integer := 1;
c0_initial : integer := 1;
c0_mode : string := "bypass";
c0_ph : integer := 0;
c1_high : integer := 1;
c1_low : integer := 1;
c1_initial : integer := 1;
c1_mode : string := "bypass";
c1_ph : integer := 0;
c2_high : integer := 1;
c2_low : integer := 1;
c2_initial : integer := 1;
c2_mode : string := "bypass";
c2_ph : integer := 0;
c3_high : integer := 1;
c3_low : integer := 1;
c3_initial : integer := 1;
c3_mode : string := "bypass";
c3_ph : integer := 0;
c4_high : integer := 1;
c4_low : integer := 1;
c4_initial : integer := 1;
c4_mode : string := "bypass";
c4_ph : integer := 0;
c5_high : integer := 1;
c5_low : integer := 1;
c5_initial : integer := 1;
c5_mode : string := "bypass";
c5_ph : integer := 0;
c6_high : integer := 1;
c6_low : integer := 1;
c6_initial : integer := 1;
c6_mode : string := "bypass";
c6_ph : integer := 0;
c7_high : integer := 1;
c7_low : integer := 1;
c7_initial : integer := 1;
c7_mode : string := "bypass";
c7_ph : integer := 0;
c8_high : integer := 1;
c8_low : integer := 1;
c8_initial : integer := 1;
c8_mode : string := "bypass";
c8_ph : integer := 0;
c9_high : integer := 1;
c9_low : integer := 1;
c9_initial : integer := 1;
c9_mode : string := "bypass";
c9_ph : integer := 0;
m_ph : integer := 0;
clk0_counter : string := "unused";
clk1_counter : string := "unused";
clk2_counter : string := "unused";
clk3_counter : string := "unused";
clk4_counter : string := "unused";
clk5_counter : string := "unused";
clk6_counter : string := "unused";
clk7_counter : string := "unused";
clk8_counter : string := "unused";
clk9_counter : string := "unused";
c1_use_casc_in : string := "off";
c2_use_casc_in : string := "off";
c3_use_casc_in : string := "off";
c4_use_casc_in : string := "off";
c5_use_casc_in : string := "off";
c6_use_casc_in : string := "off";
c7_use_casc_in : string := "off";
c8_use_casc_in : string := "off";
c9_use_casc_in : string := "off";
m_test_source : integer := -1;
c0_test_source : integer := -1;
c1_test_source : integer := -1;
c2_test_source : integer := -1;
c3_test_source : integer := -1;
c4_test_source : integer := -1;
c5_test_source : integer := -1;
c6_test_source : integer := -1;
c7_test_source : integer := -1;
c8_test_source : integer := -1;
c9_test_source : integer := -1;
vco_multiply_by : integer := 0;
vco_divide_by : integer := 0;
vco_post_scale : integer := 1;
vco_frequency_control: string := "auto";
vco_phase_shift_step: integer := 0;
charge_pump_current: integer := 10;
loop_filter_r : string := "1.0";
loop_filter_c : integer := 0;
pll_compensation_delay: integer := 0;
simulation_type : string := "functional";
down_spread : string := "0.0";
lock_c : integer := 4;
sim_gate_lock_device_behavior: string := "off";
clk0_phase_shift_num: integer := 0;
clk1_phase_shift_num: integer := 0;
clk2_phase_shift_num: integer := 0;
clk3_phase_shift_num: integer := 0;
clk4_phase_shift_num: integer := 0;
family_name : string := "StratixIII";
clk0_use_even_counter_mode: string := "off";
clk1_use_even_counter_mode: string := "off";
clk2_use_even_counter_mode: string := "off";
clk3_use_even_counter_mode: string := "off";
clk4_use_even_counter_mode: string := "off";
clk5_use_even_counter_mode: string := "off";
clk6_use_even_counter_mode: string := "off";
clk7_use_even_counter_mode: string := "off";
clk8_use_even_counter_mode: string := "off";
clk9_use_even_counter_mode: string := "off";
clk0_use_even_counter_value: string := "off";
clk1_use_even_counter_value: string := "off";
clk2_use_even_counter_value: string := "off";
clk3_use_even_counter_value: string := "off";
clk4_use_even_counter_value: string := "off";
clk5_use_even_counter_value: string := "off";
clk6_use_even_counter_value: string := "off";
clk7_use_even_counter_value: string := "off";
clk8_use_even_counter_value: string := "off";
clk9_use_even_counter_value: string := "off";
init_block_reset_a_count: integer := 1;
init_block_reset_b_count: integer := 1;
phase_counter_select_width: integer := 4;
lock_window : integer := 5;
inclk0_freq : vl_notype;
inclk1_freq : vl_notype;
charge_pump_current_bits: integer := 0;
lock_window_ui_bits: integer := 0;
loop_filter_c_bits: integer := 0;
loop_filter_r_bits: integer := 0;
test_counter_c0_delay_chain_bits: integer := 0;
test_counter_c1_delay_chain_bits: integer := 0;
test_counter_c2_delay_chain_bits: integer := 0;
test_counter_c3_delay_chain_bits: integer := 0;
test_counter_c4_delay_chain_bits: integer := 0;
test_counter_c5_delay_chain_bits: integer := 0;
test_counter_c6_delay_chain_bits: integer := 0;
test_counter_c7_delay_chain_bits: integer := 0;
test_counter_c8_delay_chain_bits: integer := 0;
test_counter_c9_delay_chain_bits: integer := 0;
test_counter_m_delay_chain_bits: integer := 0;
test_counter_n_delay_chain_bits: integer := 0;
test_feedback_comp_delay_chain_bits: integer := 0;
test_input_comp_delay_chain_bits: integer := 0;
test_volt_reg_output_mode_bits: integer := 0;
test_volt_reg_output_voltage_bits: integer := 0;
test_volt_reg_test_mode: string := "false";
vco_range_detector_high_bits: integer := -1;
vco_range_detector_low_bits: integer := -1;
scan_chain_mif_file: string := "";
test_counter_c3_sclk_delay_chain_bits: integer := -1;
test_counter_c4_sclk_delay_chain_bits: integer := -1;
test_counter_c5_lden_delay_chain_bits: integer := -1;
test_counter_c6_lden_delay_chain_bits: integer := -1;
auto_settings : string := "true";
SCAN_CHAIN : integer := 144;
GPP_SCAN_CHAIN : integer := 234;
FAST_SCAN_CHAIN : integer := 180;
num_phase_taps : integer := 8
);
port(
inclk : in vl_logic_vector(1 downto 0);
fbin : in vl_logic;
fbout : out vl_logic;
clkswitch : in vl_logic;
areset : in vl_logic;
pfdena : in vl_logic;
scanclk : in vl_logic;
scandata : in vl_logic;
scanclkena : in vl_logic;
configupdate : in vl_logic;
clk : out vl_logic_vector(9 downto 0);
phasecounterselect: in vl_logic_vector;
phaseupdown : in vl_logic;
phasestep : in vl_logic;
clkbad : out vl_logic_vector(1 downto 0);
activeclock : out vl_logic;
locked : out vl_logic;
scandataout : out vl_logic;
scandone : out vl_logic;
phasedone : out vl_logic;
vcooverrange : out vl_logic;
vcounderrange : out vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of operation_mode : constant is 1;
attribute mti_svvh_generic_type of pll_type : constant is 1;
attribute mti_svvh_generic_type of compensate_clock : constant is 1;
attribute mti_svvh_generic_type of inclk0_input_frequency : constant is 1;
attribute mti_svvh_generic_type of inclk1_input_frequency : constant is 1;
attribute mti_svvh_generic_type of self_reset_on_loss_lock : constant is 1;
attribute mti_svvh_generic_type of switch_over_type : constant is 1;
attribute mti_svvh_generic_type of switch_over_counter : constant is 1;
attribute mti_svvh_generic_type of enable_switch_over_counter : constant is 1;
attribute mti_svvh_generic_type of dpa_multiply_by : constant is 1;
attribute mti_svvh_generic_type of dpa_divide_by : constant is 1;
attribute mti_svvh_generic_type of dpa_divider : constant is 1;
attribute mti_svvh_generic_type of bandwidth : constant is 1;
attribute mti_svvh_generic_type of bandwidth_type : constant is 1;
attribute mti_svvh_generic_type of use_dc_coupling : constant is 1;
attribute mti_svvh_generic_type of lock_high : constant is 1;
attribute mti_svvh_generic_type of lock_low : constant is 1;
attribute mti_svvh_generic_type of lock_window_ui : constant is 1;
attribute mti_svvh_generic_type of test_bypass_lock_detect : constant is 1;
attribute mti_svvh_generic_type of clk0_output_frequency : constant is 1;
attribute mti_svvh_generic_type of clk0_multiply_by : constant is 1;
attribute mti_svvh_generic_type of clk0_divide_by : constant is 1;
attribute mti_svvh_generic_type of clk0_phase_shift : constant is 1;
attribute mti_svvh_generic_type of clk0_duty_cycle : constant is 1;
attribute mti_svvh_generic_type of clk1_output_frequency : constant is 1;
attribute mti_svvh_generic_type of clk1_multiply_by : constant is 1;
attribute mti_svvh_generic_type of clk1_divide_by : constant is 1;
attribute mti_svvh_generic_type of clk1_phase_shift : constant is 1;
attribute mti_svvh_generic_type of clk1_duty_cycle : constant is 1;
attribute mti_svvh_generic_type of clk2_output_frequency : constant is 1;
attribute mti_svvh_generic_type of clk2_multiply_by : constant is 1;
attribute mti_svvh_generic_type of clk2_divide_by : constant is 1;
attribute mti_svvh_generic_type of clk2_phase_shift : constant is 1;
attribute mti_svvh_generic_type of clk2_duty_cycle : constant is 1;
attribute mti_svvh_generic_type of clk3_output_frequency : constant is 1;
attribute mti_svvh_generic_type of clk3_multiply_by : constant is 1;
attribute mti_svvh_generic_type of clk3_divide_by : constant is 1;
attribute mti_svvh_generic_type of clk3_phase_shift : constant is 1;
attribute mti_svvh_generic_type of clk3_duty_cycle : constant is 1;
attribute mti_svvh_generic_type of clk4_output_frequency : constant is 1;
attribute mti_svvh_generic_type of clk4_multiply_by : constant is 1;
attribute mti_svvh_generic_type of clk4_divide_by : constant is 1;
attribute mti_svvh_generic_type of clk4_phase_shift : constant is 1;
attribute mti_svvh_generic_type of clk4_duty_cycle : constant is 1;
attribute mti_svvh_generic_type of clk5_output_frequency : constant is 1;
attribute mti_svvh_generic_type of clk5_multiply_by : constant is 1;
attribute mti_svvh_generic_type of clk5_divide_by : constant is 1;
attribute mti_svvh_generic_type of clk5_phase_shift : constant is 1;
attribute mti_svvh_generic_type of clk5_duty_cycle : constant is 1;
attribute mti_svvh_generic_type of clk6_output_frequency : constant is 1;
attribute mti_svvh_generic_type of clk6_multiply_by : constant is 1;
attribute mti_svvh_generic_type of clk6_divide_by : constant is 1;
attribute mti_svvh_generic_type of clk6_phase_shift : constant is 1;
attribute mti_svvh_generic_type of clk6_duty_cycle : constant is 1;
attribute mti_svvh_generic_type of clk7_output_frequency : constant is 1;
attribute mti_svvh_generic_type of clk7_multiply_by : constant is 1;
attribute mti_svvh_generic_type of clk7_divide_by : constant is 1;
attribute mti_svvh_generic_type of clk7_phase_shift : constant is 1;
attribute mti_svvh_generic_type of clk7_duty_cycle : constant is 1;
attribute mti_svvh_generic_type of clk8_output_frequency : constant is 1;
attribute mti_svvh_generic_type of clk8_multiply_by : constant is 1;
attribute mti_svvh_generic_type of clk8_divide_by : constant is 1;
attribute mti_svvh_generic_type of clk8_phase_shift : constant is 1;
attribute mti_svvh_generic_type of clk8_duty_cycle : constant is 1;
attribute mti_svvh_generic_type of clk9_output_frequency : constant is 1;
attribute mti_svvh_generic_type of clk9_multiply_by : constant is 1;
attribute mti_svvh_generic_type of clk9_divide_by : constant is 1;
attribute mti_svvh_generic_type of clk9_phase_shift : constant is 1;
attribute mti_svvh_generic_type of clk9_duty_cycle : constant is 1;
attribute mti_svvh_generic_type of pfd_min : constant is 1;
attribute mti_svvh_generic_type of pfd_max : constant is 1;
attribute mti_svvh_generic_type of vco_min : constant is 1;
attribute mti_svvh_generic_type of vco_max : constant is 1;
attribute mti_svvh_generic_type of vco_center : constant is 1;
attribute mti_svvh_generic_type of m_initial : constant is 1;
attribute mti_svvh_generic_type of m : constant is 1;
attribute mti_svvh_generic_type of n : constant is 1;
attribute mti_svvh_generic_type of c0_high : constant is 1;
attribute mti_svvh_generic_type of c0_low : constant is 1;
attribute mti_svvh_generic_type of c0_initial : constant is 1;
attribute mti_svvh_generic_type of c0_mode : constant is 1;
attribute mti_svvh_generic_type of c0_ph : constant is 1;
attribute mti_svvh_generic_type of c1_high : constant is 1;
attribute mti_svvh_generic_type of c1_low : constant is 1;
attribute mti_svvh_generic_type of c1_initial : constant is 1;
attribute mti_svvh_generic_type of c1_mode : constant is 1;
attribute mti_svvh_generic_type of c1_ph : constant is 1;
attribute mti_svvh_generic_type of c2_high : constant is 1;
attribute mti_svvh_generic_type of c2_low : constant is 1;
attribute mti_svvh_generic_type of c2_initial : constant is 1;
attribute mti_svvh_generic_type of c2_mode : constant is 1;
attribute mti_svvh_generic_type of c2_ph : constant is 1;
attribute mti_svvh_generic_type of c3_high : constant is 1;
attribute mti_svvh_generic_type of c3_low : constant is 1;
attribute mti_svvh_generic_type of c3_initial : constant is 1;
attribute mti_svvh_generic_type of c3_mode : constant is 1;
attribute mti_svvh_generic_type of c3_ph : constant is 1;
attribute mti_svvh_generic_type of c4_high : constant is 1;
attribute mti_svvh_generic_type of c4_low : constant is 1;
attribute mti_svvh_generic_type of c4_initial : constant is 1;
attribute mti_svvh_generic_type of c4_mode : constant is 1;
attribute mti_svvh_generic_type of c4_ph : constant is 1;
attribute mti_svvh_generic_type of c5_high : constant is 1;
attribute mti_svvh_generic_type of c5_low : constant is 1;
attribute mti_svvh_generic_type of c5_initial : constant is 1;
attribute mti_svvh_generic_type of c5_mode : constant is 1;
attribute mti_svvh_generic_type of c5_ph : constant is 1;
attribute mti_svvh_generic_type of c6_high : constant is 1;
attribute mti_svvh_generic_type of c6_low : constant is 1;
attribute mti_svvh_generic_type of c6_initial : constant is 1;
attribute mti_svvh_generic_type of c6_mode : constant is 1;
attribute mti_svvh_generic_type of c6_ph : constant is 1;
attribute mti_svvh_generic_type of c7_high : constant is 1;
attribute mti_svvh_generic_type of c7_low : constant is 1;
attribute mti_svvh_generic_type of c7_initial : constant is 1;
attribute mti_svvh_generic_type of c7_mode : constant is 1;
attribute mti_svvh_generic_type of c7_ph : constant is 1;
attribute mti_svvh_generic_type of c8_high : constant is 1;
attribute mti_svvh_generic_type of c8_low : constant is 1;
attribute mti_svvh_generic_type of c8_initial : constant is 1;
attribute mti_svvh_generic_type of c8_mode : constant is 1;
attribute mti_svvh_generic_type of c8_ph : constant is 1;
attribute mti_svvh_generic_type of c9_high : constant is 1;
attribute mti_svvh_generic_type of c9_low : constant is 1;
attribute mti_svvh_generic_type of c9_initial : constant is 1;
attribute mti_svvh_generic_type of c9_mode : constant is 1;
attribute mti_svvh_generic_type of c9_ph : constant is 1;
attribute mti_svvh_generic_type of m_ph : constant is 1;
attribute mti_svvh_generic_type of clk0_counter : constant is 1;
attribute mti_svvh_generic_type of clk1_counter : constant is 1;
attribute mti_svvh_generic_type of clk2_counter : constant is 1;
attribute mti_svvh_generic_type of clk3_counter : constant is 1;
attribute mti_svvh_generic_type of clk4_counter : constant is 1;
attribute mti_svvh_generic_type of clk5_counter : constant is 1;
attribute mti_svvh_generic_type of clk6_counter : constant is 1;
attribute mti_svvh_generic_type of clk7_counter : constant is 1;
attribute mti_svvh_generic_type of clk8_counter : constant is 1;
attribute mti_svvh_generic_type of clk9_counter : constant is 1;
attribute mti_svvh_generic_type of c1_use_casc_in : constant is 1;
attribute mti_svvh_generic_type of c2_use_casc_in : constant is 1;
attribute mti_svvh_generic_type of c3_use_casc_in : constant is 1;
attribute mti_svvh_generic_type of c4_use_casc_in : constant is 1;
attribute mti_svvh_generic_type of c5_use_casc_in : constant is 1;
attribute mti_svvh_generic_type of c6_use_casc_in : constant is 1;
attribute mti_svvh_generic_type of c7_use_casc_in : constant is 1;
attribute mti_svvh_generic_type of c8_use_casc_in : constant is 1;
attribute mti_svvh_generic_type of c9_use_casc_in : constant is 1;
attribute mti_svvh_generic_type of m_test_source : constant is 1;
attribute mti_svvh_generic_type of c0_test_source : constant is 1;
attribute mti_svvh_generic_type of c1_test_source : constant is 1;
attribute mti_svvh_generic_type of c2_test_source : constant is 1;
attribute mti_svvh_generic_type of c3_test_source : constant is 1;
attribute mti_svvh_generic_type of c4_test_source : constant is 1;
attribute mti_svvh_generic_type of c5_test_source : constant is 1;
attribute mti_svvh_generic_type of c6_test_source : constant is 1;
attribute mti_svvh_generic_type of c7_test_source : constant is 1;
attribute mti_svvh_generic_type of c8_test_source : constant is 1;
attribute mti_svvh_generic_type of c9_test_source : constant is 1;
attribute mti_svvh_generic_type of vco_multiply_by : constant is 1;
attribute mti_svvh_generic_type of vco_divide_by : constant is 1;
attribute mti_svvh_generic_type of vco_post_scale : constant is 1;
attribute mti_svvh_generic_type of vco_frequency_control : constant is 1;
attribute mti_svvh_generic_type of vco_phase_shift_step : constant is 1;
attribute mti_svvh_generic_type of charge_pump_current : constant is 1;
attribute mti_svvh_generic_type of loop_filter_r : constant is 1;
attribute mti_svvh_generic_type of loop_filter_c : constant is 1;
attribute mti_svvh_generic_type of pll_compensation_delay : constant is 1;
attribute mti_svvh_generic_type of simulation_type : constant is 1;
attribute mti_svvh_generic_type of down_spread : constant is 1;
attribute mti_svvh_generic_type of lock_c : constant is 1;
attribute mti_svvh_generic_type of sim_gate_lock_device_behavior : constant is 1;
attribute mti_svvh_generic_type of clk0_phase_shift_num : constant is 1;
attribute mti_svvh_generic_type of clk1_phase_shift_num : constant is 1;
attribute mti_svvh_generic_type of clk2_phase_shift_num : constant is 1;
attribute mti_svvh_generic_type of clk3_phase_shift_num : constant is 1;
attribute mti_svvh_generic_type of clk4_phase_shift_num : constant is 1;
attribute mti_svvh_generic_type of family_name : constant is 1;
attribute mti_svvh_generic_type of clk0_use_even_counter_mode : constant is 1;
attribute mti_svvh_generic_type of clk1_use_even_counter_mode : constant is 1;
attribute mti_svvh_generic_type of clk2_use_even_counter_mode : constant is 1;
attribute mti_svvh_generic_type of clk3_use_even_counter_mode : constant is 1;
attribute mti_svvh_generic_type of clk4_use_even_counter_mode : constant is 1;
attribute mti_svvh_generic_type of clk5_use_even_counter_mode : constant is 1;
attribute mti_svvh_generic_type of clk6_use_even_counter_mode : constant is 1;
attribute mti_svvh_generic_type of clk7_use_even_counter_mode : constant is 1;
attribute mti_svvh_generic_type of clk8_use_even_counter_mode : constant is 1;
attribute mti_svvh_generic_type of clk9_use_even_counter_mode : constant is 1;
attribute mti_svvh_generic_type of clk0_use_even_counter_value : constant is 1;
attribute mti_svvh_generic_type of clk1_use_even_counter_value : constant is 1;
attribute mti_svvh_generic_type of clk2_use_even_counter_value : constant is 1;
attribute mti_svvh_generic_type of clk3_use_even_counter_value : constant is 1;
attribute mti_svvh_generic_type of clk4_use_even_counter_value : constant is 1;
attribute mti_svvh_generic_type of clk5_use_even_counter_value : constant is 1;
attribute mti_svvh_generic_type of clk6_use_even_counter_value : constant is 1;
attribute mti_svvh_generic_type of clk7_use_even_counter_value : constant is 1;
attribute mti_svvh_generic_type of clk8_use_even_counter_value : constant is 1;
attribute mti_svvh_generic_type of clk9_use_even_counter_value : constant is 1;
attribute mti_svvh_generic_type of init_block_reset_a_count : constant is 1;
attribute mti_svvh_generic_type of init_block_reset_b_count : constant is 1;
attribute mti_svvh_generic_type of phase_counter_select_width : constant is 1;
attribute mti_svvh_generic_type of lock_window : constant is 1;
attribute mti_svvh_generic_type of inclk0_freq : constant is 3;
attribute mti_svvh_generic_type of inclk1_freq : constant is 3;
attribute mti_svvh_generic_type of charge_pump_current_bits : constant is 1;
attribute mti_svvh_generic_type of lock_window_ui_bits : constant is 1;
attribute mti_svvh_generic_type of loop_filter_c_bits : constant is 1;
attribute mti_svvh_generic_type of loop_filter_r_bits : constant is 1;
attribute mti_svvh_generic_type of test_counter_c0_delay_chain_bits : constant is 1;
attribute mti_svvh_generic_type of test_counter_c1_delay_chain_bits : constant is 1;
attribute mti_svvh_generic_type of test_counter_c2_delay_chain_bits : constant is 1;
attribute mti_svvh_generic_type of test_counter_c3_delay_chain_bits : constant is 1;
attribute mti_svvh_generic_type of test_counter_c4_delay_chain_bits : constant is 1;
attribute mti_svvh_generic_type of test_counter_c5_delay_chain_bits : constant is 1;
attribute mti_svvh_generic_type of test_counter_c6_delay_chain_bits : constant is 1;
attribute mti_svvh_generic_type of test_counter_c7_delay_chain_bits : constant is 1;
attribute mti_svvh_generic_type of test_counter_c8_delay_chain_bits : constant is 1;
attribute mti_svvh_generic_type of test_counter_c9_delay_chain_bits : constant is 1;
attribute mti_svvh_generic_type of test_counter_m_delay_chain_bits : constant is 1;
attribute mti_svvh_generic_type of test_counter_n_delay_chain_bits : constant is 1;
attribute mti_svvh_generic_type of test_feedback_comp_delay_chain_bits : constant is 1;
attribute mti_svvh_generic_type of test_input_comp_delay_chain_bits : constant is 1;
attribute mti_svvh_generic_type of test_volt_reg_output_mode_bits : constant is 1;
attribute mti_svvh_generic_type of test_volt_reg_output_voltage_bits : constant is 1;
attribute mti_svvh_generic_type of test_volt_reg_test_mode : constant is 1;
attribute mti_svvh_generic_type of vco_range_detector_high_bits : constant is 1;
attribute mti_svvh_generic_type of vco_range_detector_low_bits : constant is 1;
attribute mti_svvh_generic_type of scan_chain_mif_file : constant is 1;
attribute mti_svvh_generic_type of test_counter_c3_sclk_delay_chain_bits : constant is 1;
attribute mti_svvh_generic_type of test_counter_c4_sclk_delay_chain_bits : constant is 1;
attribute mti_svvh_generic_type of test_counter_c5_lden_delay_chain_bits : constant is 1;
attribute mti_svvh_generic_type of test_counter_c6_lden_delay_chain_bits : constant is 1;
attribute mti_svvh_generic_type of auto_settings : constant is 1;
attribute mti_svvh_generic_type of SCAN_CHAIN : constant is 1;
attribute mti_svvh_generic_type of GPP_SCAN_CHAIN : constant is 1;
attribute mti_svvh_generic_type of FAST_SCAN_CHAIN : constant is 1;
attribute mti_svvh_generic_type of num_phase_taps : constant is 1;
end MF_stratixiii_pll;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sin_taylor_series is
port (
x : IN STD_LOGIC_VECTOR (63 downto 0);
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_return : OUT STD_LOGIC_VECTOR (63 downto 0);
ap_done : OUT STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_ready : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC );
end;
architecture behav of sin_taylor_series is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"sin_taylor_series,hls_ip_2017_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=1,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=dataflow,HLS_SYN_CLOCK=8.621000,HLS_SYN_LAT=-1,HLS_SYN_TPT=-1,HLS_SYN_MEM=0,HLS_SYN_DSP=53,HLS_SYN_FF=10797,HLS_SYN_LUT=15153}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
constant ap_const_boolean_1 : BOOLEAN := true;
signal Loop_sum_loop_proc_U0_ap_start : STD_LOGIC;
signal Loop_sum_loop_proc_U0_ap_done : STD_LOGIC;
signal Loop_sum_loop_proc_U0_ap_continue : STD_LOGIC;
signal Loop_sum_loop_proc_U0_ap_idle : STD_LOGIC;
signal Loop_sum_loop_proc_U0_ap_ready : STD_LOGIC;
signal Loop_sum_loop_proc_U0_ap_return_0 : STD_LOGIC_VECTOR (63 downto 0);
signal Loop_sum_loop_proc_U0_ap_return_1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_channel_done_sum_negative_0_loc_l : STD_LOGIC;
signal sum_negative_0_loc_l_full_n : STD_LOGIC;
signal ap_sync_reg_channel_write_sum_negative_0_loc_l : STD_LOGIC := '0';
signal ap_sync_channel_write_sum_negative_0_loc_l : STD_LOGIC;
signal ap_channel_done_sum_positive_0_loc_l : STD_LOGIC;
signal sum_positive_0_loc_l_full_n : STD_LOGIC;
signal ap_sync_reg_channel_write_sum_positive_0_loc_l : STD_LOGIC := '0';
signal ap_sync_channel_write_sum_positive_0_loc_l : STD_LOGIC;
signal Block_sin_taylor_ser_U0_ap_start : STD_LOGIC;
signal Block_sin_taylor_ser_U0_ap_done : STD_LOGIC;
signal Block_sin_taylor_ser_U0_ap_continue : STD_LOGIC;
signal Block_sin_taylor_ser_U0_ap_idle : STD_LOGIC;
signal Block_sin_taylor_ser_U0_ap_ready : STD_LOGIC;
signal Block_sin_taylor_ser_U0_ap_return : STD_LOGIC_VECTOR (63 downto 0);
signal ap_channel_done_tmp_loc_channel : STD_LOGIC;
signal tmp_loc_channel_full_n : STD_LOGIC;
signal p_source_files_sr_U0_ap_start : STD_LOGIC;
signal p_source_files_sr_U0_ap_done : STD_LOGIC;
signal p_source_files_sr_U0_ap_continue : STD_LOGIC;
signal p_source_files_sr_U0_ap_idle : STD_LOGIC;
signal p_source_files_sr_U0_ap_ready : STD_LOGIC;
signal p_source_files_sr_U0_ap_return : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_p_source_files_sr_fu_42_ap_return : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sync_continue : STD_LOGIC;
signal sum_positive_0_loc_l_dout : STD_LOGIC_VECTOR (63 downto 0);
signal sum_positive_0_loc_l_empty_n : STD_LOGIC;
signal sum_negative_0_loc_l_dout : STD_LOGIC_VECTOR (63 downto 0);
signal sum_negative_0_loc_l_empty_n : STD_LOGIC;
signal tmp_loc_channel_dout : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_loc_channel_empty_n : STD_LOGIC;
signal ap_sync_done : STD_LOGIC;
signal ap_sync_ready : STD_LOGIC;
signal Loop_sum_loop_proc_U0_start_full_n : STD_LOGIC;
signal Loop_sum_loop_proc_U0_start_write : STD_LOGIC;
signal Block_sin_taylor_ser_U0_start_full_n : STD_LOGIC;
signal Block_sin_taylor_ser_U0_start_write : STD_LOGIC;
signal p_source_files_sr_U0_start_full_n : STD_LOGIC;
signal p_source_files_sr_U0_start_write : STD_LOGIC;
component Loop_sum_loop_proc IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
x : IN STD_LOGIC_VECTOR (63 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (63 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component Block_sin_taylor_ser IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
p_read : IN STD_LOGIC_VECTOR (63 downto 0);
p_read1 : IN STD_LOGIC_VECTOR (63 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component p_source_files_sr IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
p_read : IN STD_LOGIC_VECTOR (63 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component fifo_w64_d2_A IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (63 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (63 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
begin
Loop_sum_loop_proc_U0 : component Loop_sum_loop_proc
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => Loop_sum_loop_proc_U0_ap_start,
ap_done => Loop_sum_loop_proc_U0_ap_done,
ap_continue => Loop_sum_loop_proc_U0_ap_continue,
ap_idle => Loop_sum_loop_proc_U0_ap_idle,
ap_ready => Loop_sum_loop_proc_U0_ap_ready,
x => x,
ap_return_0 => Loop_sum_loop_proc_U0_ap_return_0,
ap_return_1 => Loop_sum_loop_proc_U0_ap_return_1);
Block_sin_taylor_ser_U0 : component Block_sin_taylor_ser
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => Block_sin_taylor_ser_U0_ap_start,
ap_done => Block_sin_taylor_ser_U0_ap_done,
ap_continue => Block_sin_taylor_ser_U0_ap_continue,
ap_idle => Block_sin_taylor_ser_U0_ap_idle,
ap_ready => Block_sin_taylor_ser_U0_ap_ready,
p_read => sum_positive_0_loc_l_dout,
p_read1 => sum_negative_0_loc_l_dout,
ap_return => Block_sin_taylor_ser_U0_ap_return);
p_source_files_sr_U0 : component p_source_files_sr
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => p_source_files_sr_U0_ap_start,
ap_done => p_source_files_sr_U0_ap_done,
ap_continue => p_source_files_sr_U0_ap_continue,
ap_idle => p_source_files_sr_U0_ap_idle,
ap_ready => p_source_files_sr_U0_ap_ready,
p_read => tmp_loc_channel_dout,
ap_return => p_source_files_sr_U0_ap_return);
sum_positive_0_loc_l_U : component fifo_w64_d2_A
port map (
clk => ap_clk,
reset => ap_rst,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Loop_sum_loop_proc_U0_ap_return_0,
if_full_n => sum_positive_0_loc_l_full_n,
if_write => ap_channel_done_sum_positive_0_loc_l,
if_dout => sum_positive_0_loc_l_dout,
if_empty_n => sum_positive_0_loc_l_empty_n,
if_read => Block_sin_taylor_ser_U0_ap_ready);
sum_negative_0_loc_l_U : component fifo_w64_d2_A
port map (
clk => ap_clk,
reset => ap_rst,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Loop_sum_loop_proc_U0_ap_return_1,
if_full_n => sum_negative_0_loc_l_full_n,
if_write => ap_channel_done_sum_negative_0_loc_l,
if_dout => sum_negative_0_loc_l_dout,
if_empty_n => sum_negative_0_loc_l_empty_n,
if_read => Block_sin_taylor_ser_U0_ap_ready);
tmp_loc_channel_U : component fifo_w64_d2_A
port map (
clk => ap_clk,
reset => ap_rst,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Block_sin_taylor_ser_U0_ap_return,
if_full_n => tmp_loc_channel_full_n,
if_write => Block_sin_taylor_ser_U0_ap_done,
if_dout => tmp_loc_channel_dout,
if_empty_n => tmp_loc_channel_empty_n,
if_read => p_source_files_sr_U0_ap_ready);
ap_sync_reg_channel_write_sum_negative_0_loc_l_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_sync_reg_channel_write_sum_negative_0_loc_l <= ap_const_logic_0;
else
if ((ap_const_logic_1 = (Loop_sum_loop_proc_U0_ap_done and Loop_sum_loop_proc_U0_ap_continue))) then
ap_sync_reg_channel_write_sum_negative_0_loc_l <= ap_const_logic_0;
else
ap_sync_reg_channel_write_sum_negative_0_loc_l <= ap_sync_channel_write_sum_negative_0_loc_l;
end if;
end if;
end if;
end process;
ap_sync_reg_channel_write_sum_positive_0_loc_l_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_sync_reg_channel_write_sum_positive_0_loc_l <= ap_const_logic_0;
else
if ((ap_const_logic_1 = (Loop_sum_loop_proc_U0_ap_done and Loop_sum_loop_proc_U0_ap_continue))) then
ap_sync_reg_channel_write_sum_positive_0_loc_l <= ap_const_logic_0;
else
ap_sync_reg_channel_write_sum_positive_0_loc_l <= ap_sync_channel_write_sum_positive_0_loc_l;
end if;
end if;
end if;
end process;
Block_sin_taylor_ser_U0_ap_continue <= tmp_loc_channel_full_n;
Block_sin_taylor_ser_U0_ap_start <= (sum_positive_0_loc_l_empty_n and sum_negative_0_loc_l_empty_n);
Block_sin_taylor_ser_U0_start_full_n <= ap_const_logic_0;
Block_sin_taylor_ser_U0_start_write <= ap_const_logic_0;
Loop_sum_loop_proc_U0_ap_continue <= (ap_sync_channel_write_sum_negative_0_loc_l and ap_sync_channel_write_sum_positive_0_loc_l);
Loop_sum_loop_proc_U0_ap_start <= ap_start;
Loop_sum_loop_proc_U0_start_full_n <= ap_const_logic_0;
Loop_sum_loop_proc_U0_start_write <= ap_const_logic_0;
ap_channel_done_sum_negative_0_loc_l <= (Loop_sum_loop_proc_U0_ap_done and (ap_sync_reg_channel_write_sum_negative_0_loc_l xor ap_const_logic_1));
ap_channel_done_sum_positive_0_loc_l <= (Loop_sum_loop_proc_U0_ap_done and (ap_sync_reg_channel_write_sum_positive_0_loc_l xor ap_const_logic_1));
ap_channel_done_tmp_loc_channel <= Block_sin_taylor_ser_U0_ap_done;
ap_done <= p_source_files_sr_U0_ap_done;
ap_idle <= (Loop_sum_loop_proc_U0_ap_idle and Block_sin_taylor_ser_U0_ap_idle and p_source_files_sr_U0_ap_idle and (sum_positive_0_loc_l_empty_n xor ap_const_logic_1) and (sum_negative_0_loc_l_empty_n xor ap_const_logic_1) and (tmp_loc_channel_empty_n xor ap_const_logic_1));
ap_ready <= Loop_sum_loop_proc_U0_ap_ready;
ap_return <= p_source_files_sr_U0_ap_return;
ap_sync_channel_write_sum_negative_0_loc_l <= ((ap_channel_done_sum_negative_0_loc_l and sum_negative_0_loc_l_full_n) or ap_sync_reg_channel_write_sum_negative_0_loc_l);
ap_sync_channel_write_sum_positive_0_loc_l <= ((ap_channel_done_sum_positive_0_loc_l and sum_positive_0_loc_l_full_n) or ap_sync_reg_channel_write_sum_positive_0_loc_l);
ap_sync_continue <= ap_const_logic_1;
ap_sync_done <= p_source_files_sr_U0_ap_done;
ap_sync_ready <= Loop_sum_loop_proc_U0_ap_ready;
p_source_files_sr_U0_ap_continue <= ap_const_logic_1;
p_source_files_sr_U0_ap_start <= tmp_loc_channel_empty_n;
p_source_files_sr_U0_start_full_n <= ap_const_logic_0;
p_source_files_sr_U0_start_write <= ap_const_logic_0;
tmp_p_source_files_sr_fu_42_ap_return <= ap_const_lv64_0;
end behav;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sin_taylor_series is
port (
x : IN STD_LOGIC_VECTOR (63 downto 0);
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_return : OUT STD_LOGIC_VECTOR (63 downto 0);
ap_done : OUT STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_ready : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC );
end;
architecture behav of sin_taylor_series is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"sin_taylor_series,hls_ip_2017_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=1,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=dataflow,HLS_SYN_CLOCK=8.621000,HLS_SYN_LAT=-1,HLS_SYN_TPT=-1,HLS_SYN_MEM=0,HLS_SYN_DSP=53,HLS_SYN_FF=10797,HLS_SYN_LUT=15153}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
constant ap_const_boolean_1 : BOOLEAN := true;
signal Loop_sum_loop_proc_U0_ap_start : STD_LOGIC;
signal Loop_sum_loop_proc_U0_ap_done : STD_LOGIC;
signal Loop_sum_loop_proc_U0_ap_continue : STD_LOGIC;
signal Loop_sum_loop_proc_U0_ap_idle : STD_LOGIC;
signal Loop_sum_loop_proc_U0_ap_ready : STD_LOGIC;
signal Loop_sum_loop_proc_U0_ap_return_0 : STD_LOGIC_VECTOR (63 downto 0);
signal Loop_sum_loop_proc_U0_ap_return_1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_channel_done_sum_negative_0_loc_l : STD_LOGIC;
signal sum_negative_0_loc_l_full_n : STD_LOGIC;
signal ap_sync_reg_channel_write_sum_negative_0_loc_l : STD_LOGIC := '0';
signal ap_sync_channel_write_sum_negative_0_loc_l : STD_LOGIC;
signal ap_channel_done_sum_positive_0_loc_l : STD_LOGIC;
signal sum_positive_0_loc_l_full_n : STD_LOGIC;
signal ap_sync_reg_channel_write_sum_positive_0_loc_l : STD_LOGIC := '0';
signal ap_sync_channel_write_sum_positive_0_loc_l : STD_LOGIC;
signal Block_sin_taylor_ser_U0_ap_start : STD_LOGIC;
signal Block_sin_taylor_ser_U0_ap_done : STD_LOGIC;
signal Block_sin_taylor_ser_U0_ap_continue : STD_LOGIC;
signal Block_sin_taylor_ser_U0_ap_idle : STD_LOGIC;
signal Block_sin_taylor_ser_U0_ap_ready : STD_LOGIC;
signal Block_sin_taylor_ser_U0_ap_return : STD_LOGIC_VECTOR (63 downto 0);
signal ap_channel_done_tmp_loc_channel : STD_LOGIC;
signal tmp_loc_channel_full_n : STD_LOGIC;
signal p_source_files_sr_U0_ap_start : STD_LOGIC;
signal p_source_files_sr_U0_ap_done : STD_LOGIC;
signal p_source_files_sr_U0_ap_continue : STD_LOGIC;
signal p_source_files_sr_U0_ap_idle : STD_LOGIC;
signal p_source_files_sr_U0_ap_ready : STD_LOGIC;
signal p_source_files_sr_U0_ap_return : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_p_source_files_sr_fu_42_ap_return : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sync_continue : STD_LOGIC;
signal sum_positive_0_loc_l_dout : STD_LOGIC_VECTOR (63 downto 0);
signal sum_positive_0_loc_l_empty_n : STD_LOGIC;
signal sum_negative_0_loc_l_dout : STD_LOGIC_VECTOR (63 downto 0);
signal sum_negative_0_loc_l_empty_n : STD_LOGIC;
signal tmp_loc_channel_dout : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_loc_channel_empty_n : STD_LOGIC;
signal ap_sync_done : STD_LOGIC;
signal ap_sync_ready : STD_LOGIC;
signal Loop_sum_loop_proc_U0_start_full_n : STD_LOGIC;
signal Loop_sum_loop_proc_U0_start_write : STD_LOGIC;
signal Block_sin_taylor_ser_U0_start_full_n : STD_LOGIC;
signal Block_sin_taylor_ser_U0_start_write : STD_LOGIC;
signal p_source_files_sr_U0_start_full_n : STD_LOGIC;
signal p_source_files_sr_U0_start_write : STD_LOGIC;
component Loop_sum_loop_proc IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
x : IN STD_LOGIC_VECTOR (63 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (63 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component Block_sin_taylor_ser IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
p_read : IN STD_LOGIC_VECTOR (63 downto 0);
p_read1 : IN STD_LOGIC_VECTOR (63 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component p_source_files_sr IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
p_read : IN STD_LOGIC_VECTOR (63 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component fifo_w64_d2_A IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (63 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (63 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
begin
Loop_sum_loop_proc_U0 : component Loop_sum_loop_proc
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => Loop_sum_loop_proc_U0_ap_start,
ap_done => Loop_sum_loop_proc_U0_ap_done,
ap_continue => Loop_sum_loop_proc_U0_ap_continue,
ap_idle => Loop_sum_loop_proc_U0_ap_idle,
ap_ready => Loop_sum_loop_proc_U0_ap_ready,
x => x,
ap_return_0 => Loop_sum_loop_proc_U0_ap_return_0,
ap_return_1 => Loop_sum_loop_proc_U0_ap_return_1);
Block_sin_taylor_ser_U0 : component Block_sin_taylor_ser
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => Block_sin_taylor_ser_U0_ap_start,
ap_done => Block_sin_taylor_ser_U0_ap_done,
ap_continue => Block_sin_taylor_ser_U0_ap_continue,
ap_idle => Block_sin_taylor_ser_U0_ap_idle,
ap_ready => Block_sin_taylor_ser_U0_ap_ready,
p_read => sum_positive_0_loc_l_dout,
p_read1 => sum_negative_0_loc_l_dout,
ap_return => Block_sin_taylor_ser_U0_ap_return);
p_source_files_sr_U0 : component p_source_files_sr
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => p_source_files_sr_U0_ap_start,
ap_done => p_source_files_sr_U0_ap_done,
ap_continue => p_source_files_sr_U0_ap_continue,
ap_idle => p_source_files_sr_U0_ap_idle,
ap_ready => p_source_files_sr_U0_ap_ready,
p_read => tmp_loc_channel_dout,
ap_return => p_source_files_sr_U0_ap_return);
sum_positive_0_loc_l_U : component fifo_w64_d2_A
port map (
clk => ap_clk,
reset => ap_rst,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Loop_sum_loop_proc_U0_ap_return_0,
if_full_n => sum_positive_0_loc_l_full_n,
if_write => ap_channel_done_sum_positive_0_loc_l,
if_dout => sum_positive_0_loc_l_dout,
if_empty_n => sum_positive_0_loc_l_empty_n,
if_read => Block_sin_taylor_ser_U0_ap_ready);
sum_negative_0_loc_l_U : component fifo_w64_d2_A
port map (
clk => ap_clk,
reset => ap_rst,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Loop_sum_loop_proc_U0_ap_return_1,
if_full_n => sum_negative_0_loc_l_full_n,
if_write => ap_channel_done_sum_negative_0_loc_l,
if_dout => sum_negative_0_loc_l_dout,
if_empty_n => sum_negative_0_loc_l_empty_n,
if_read => Block_sin_taylor_ser_U0_ap_ready);
tmp_loc_channel_U : component fifo_w64_d2_A
port map (
clk => ap_clk,
reset => ap_rst,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Block_sin_taylor_ser_U0_ap_return,
if_full_n => tmp_loc_channel_full_n,
if_write => Block_sin_taylor_ser_U0_ap_done,
if_dout => tmp_loc_channel_dout,
if_empty_n => tmp_loc_channel_empty_n,
if_read => p_source_files_sr_U0_ap_ready);
ap_sync_reg_channel_write_sum_negative_0_loc_l_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_sync_reg_channel_write_sum_negative_0_loc_l <= ap_const_logic_0;
else
if ((ap_const_logic_1 = (Loop_sum_loop_proc_U0_ap_done and Loop_sum_loop_proc_U0_ap_continue))) then
ap_sync_reg_channel_write_sum_negative_0_loc_l <= ap_const_logic_0;
else
ap_sync_reg_channel_write_sum_negative_0_loc_l <= ap_sync_channel_write_sum_negative_0_loc_l;
end if;
end if;
end if;
end process;
ap_sync_reg_channel_write_sum_positive_0_loc_l_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_sync_reg_channel_write_sum_positive_0_loc_l <= ap_const_logic_0;
else
if ((ap_const_logic_1 = (Loop_sum_loop_proc_U0_ap_done and Loop_sum_loop_proc_U0_ap_continue))) then
ap_sync_reg_channel_write_sum_positive_0_loc_l <= ap_const_logic_0;
else
ap_sync_reg_channel_write_sum_positive_0_loc_l <= ap_sync_channel_write_sum_positive_0_loc_l;
end if;
end if;
end if;
end process;
Block_sin_taylor_ser_U0_ap_continue <= tmp_loc_channel_full_n;
Block_sin_taylor_ser_U0_ap_start <= (sum_positive_0_loc_l_empty_n and sum_negative_0_loc_l_empty_n);
Block_sin_taylor_ser_U0_start_full_n <= ap_const_logic_0;
Block_sin_taylor_ser_U0_start_write <= ap_const_logic_0;
Loop_sum_loop_proc_U0_ap_continue <= (ap_sync_channel_write_sum_negative_0_loc_l and ap_sync_channel_write_sum_positive_0_loc_l);
Loop_sum_loop_proc_U0_ap_start <= ap_start;
Loop_sum_loop_proc_U0_start_full_n <= ap_const_logic_0;
Loop_sum_loop_proc_U0_start_write <= ap_const_logic_0;
ap_channel_done_sum_negative_0_loc_l <= (Loop_sum_loop_proc_U0_ap_done and (ap_sync_reg_channel_write_sum_negative_0_loc_l xor ap_const_logic_1));
ap_channel_done_sum_positive_0_loc_l <= (Loop_sum_loop_proc_U0_ap_done and (ap_sync_reg_channel_write_sum_positive_0_loc_l xor ap_const_logic_1));
ap_channel_done_tmp_loc_channel <= Block_sin_taylor_ser_U0_ap_done;
ap_done <= p_source_files_sr_U0_ap_done;
ap_idle <= (Loop_sum_loop_proc_U0_ap_idle and Block_sin_taylor_ser_U0_ap_idle and p_source_files_sr_U0_ap_idle and (sum_positive_0_loc_l_empty_n xor ap_const_logic_1) and (sum_negative_0_loc_l_empty_n xor ap_const_logic_1) and (tmp_loc_channel_empty_n xor ap_const_logic_1));
ap_ready <= Loop_sum_loop_proc_U0_ap_ready;
ap_return <= p_source_files_sr_U0_ap_return;
ap_sync_channel_write_sum_negative_0_loc_l <= ((ap_channel_done_sum_negative_0_loc_l and sum_negative_0_loc_l_full_n) or ap_sync_reg_channel_write_sum_negative_0_loc_l);
ap_sync_channel_write_sum_positive_0_loc_l <= ((ap_channel_done_sum_positive_0_loc_l and sum_positive_0_loc_l_full_n) or ap_sync_reg_channel_write_sum_positive_0_loc_l);
ap_sync_continue <= ap_const_logic_1;
ap_sync_done <= p_source_files_sr_U0_ap_done;
ap_sync_ready <= Loop_sum_loop_proc_U0_ap_ready;
p_source_files_sr_U0_ap_continue <= ap_const_logic_1;
p_source_files_sr_U0_ap_start <= tmp_loc_channel_empty_n;
p_source_files_sr_U0_start_full_n <= ap_const_logic_0;
p_source_files_sr_U0_start_write <= ap_const_logic_0;
tmp_p_source_files_sr_fu_42_ap_return <= ap_const_lv64_0;
end behav;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sin_taylor_series is
port (
x : IN STD_LOGIC_VECTOR (63 downto 0);
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_return : OUT STD_LOGIC_VECTOR (63 downto 0);
ap_done : OUT STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_ready : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC );
end;
architecture behav of sin_taylor_series is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"sin_taylor_series,hls_ip_2017_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=1,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=dataflow,HLS_SYN_CLOCK=8.621000,HLS_SYN_LAT=-1,HLS_SYN_TPT=-1,HLS_SYN_MEM=0,HLS_SYN_DSP=53,HLS_SYN_FF=10797,HLS_SYN_LUT=15153}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
constant ap_const_boolean_1 : BOOLEAN := true;
signal Loop_sum_loop_proc_U0_ap_start : STD_LOGIC;
signal Loop_sum_loop_proc_U0_ap_done : STD_LOGIC;
signal Loop_sum_loop_proc_U0_ap_continue : STD_LOGIC;
signal Loop_sum_loop_proc_U0_ap_idle : STD_LOGIC;
signal Loop_sum_loop_proc_U0_ap_ready : STD_LOGIC;
signal Loop_sum_loop_proc_U0_ap_return_0 : STD_LOGIC_VECTOR (63 downto 0);
signal Loop_sum_loop_proc_U0_ap_return_1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_channel_done_sum_negative_0_loc_l : STD_LOGIC;
signal sum_negative_0_loc_l_full_n : STD_LOGIC;
signal ap_sync_reg_channel_write_sum_negative_0_loc_l : STD_LOGIC := '0';
signal ap_sync_channel_write_sum_negative_0_loc_l : STD_LOGIC;
signal ap_channel_done_sum_positive_0_loc_l : STD_LOGIC;
signal sum_positive_0_loc_l_full_n : STD_LOGIC;
signal ap_sync_reg_channel_write_sum_positive_0_loc_l : STD_LOGIC := '0';
signal ap_sync_channel_write_sum_positive_0_loc_l : STD_LOGIC;
signal Block_sin_taylor_ser_U0_ap_start : STD_LOGIC;
signal Block_sin_taylor_ser_U0_ap_done : STD_LOGIC;
signal Block_sin_taylor_ser_U0_ap_continue : STD_LOGIC;
signal Block_sin_taylor_ser_U0_ap_idle : STD_LOGIC;
signal Block_sin_taylor_ser_U0_ap_ready : STD_LOGIC;
signal Block_sin_taylor_ser_U0_ap_return : STD_LOGIC_VECTOR (63 downto 0);
signal ap_channel_done_tmp_loc_channel : STD_LOGIC;
signal tmp_loc_channel_full_n : STD_LOGIC;
signal p_source_files_sr_U0_ap_start : STD_LOGIC;
signal p_source_files_sr_U0_ap_done : STD_LOGIC;
signal p_source_files_sr_U0_ap_continue : STD_LOGIC;
signal p_source_files_sr_U0_ap_idle : STD_LOGIC;
signal p_source_files_sr_U0_ap_ready : STD_LOGIC;
signal p_source_files_sr_U0_ap_return : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_p_source_files_sr_fu_42_ap_return : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sync_continue : STD_LOGIC;
signal sum_positive_0_loc_l_dout : STD_LOGIC_VECTOR (63 downto 0);
signal sum_positive_0_loc_l_empty_n : STD_LOGIC;
signal sum_negative_0_loc_l_dout : STD_LOGIC_VECTOR (63 downto 0);
signal sum_negative_0_loc_l_empty_n : STD_LOGIC;
signal tmp_loc_channel_dout : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_loc_channel_empty_n : STD_LOGIC;
signal ap_sync_done : STD_LOGIC;
signal ap_sync_ready : STD_LOGIC;
signal Loop_sum_loop_proc_U0_start_full_n : STD_LOGIC;
signal Loop_sum_loop_proc_U0_start_write : STD_LOGIC;
signal Block_sin_taylor_ser_U0_start_full_n : STD_LOGIC;
signal Block_sin_taylor_ser_U0_start_write : STD_LOGIC;
signal p_source_files_sr_U0_start_full_n : STD_LOGIC;
signal p_source_files_sr_U0_start_write : STD_LOGIC;
component Loop_sum_loop_proc IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
x : IN STD_LOGIC_VECTOR (63 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (63 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component Block_sin_taylor_ser IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
p_read : IN STD_LOGIC_VECTOR (63 downto 0);
p_read1 : IN STD_LOGIC_VECTOR (63 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component p_source_files_sr IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
p_read : IN STD_LOGIC_VECTOR (63 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component fifo_w64_d2_A IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (63 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (63 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
begin
Loop_sum_loop_proc_U0 : component Loop_sum_loop_proc
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => Loop_sum_loop_proc_U0_ap_start,
ap_done => Loop_sum_loop_proc_U0_ap_done,
ap_continue => Loop_sum_loop_proc_U0_ap_continue,
ap_idle => Loop_sum_loop_proc_U0_ap_idle,
ap_ready => Loop_sum_loop_proc_U0_ap_ready,
x => x,
ap_return_0 => Loop_sum_loop_proc_U0_ap_return_0,
ap_return_1 => Loop_sum_loop_proc_U0_ap_return_1);
Block_sin_taylor_ser_U0 : component Block_sin_taylor_ser
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => Block_sin_taylor_ser_U0_ap_start,
ap_done => Block_sin_taylor_ser_U0_ap_done,
ap_continue => Block_sin_taylor_ser_U0_ap_continue,
ap_idle => Block_sin_taylor_ser_U0_ap_idle,
ap_ready => Block_sin_taylor_ser_U0_ap_ready,
p_read => sum_positive_0_loc_l_dout,
p_read1 => sum_negative_0_loc_l_dout,
ap_return => Block_sin_taylor_ser_U0_ap_return);
p_source_files_sr_U0 : component p_source_files_sr
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => p_source_files_sr_U0_ap_start,
ap_done => p_source_files_sr_U0_ap_done,
ap_continue => p_source_files_sr_U0_ap_continue,
ap_idle => p_source_files_sr_U0_ap_idle,
ap_ready => p_source_files_sr_U0_ap_ready,
p_read => tmp_loc_channel_dout,
ap_return => p_source_files_sr_U0_ap_return);
sum_positive_0_loc_l_U : component fifo_w64_d2_A
port map (
clk => ap_clk,
reset => ap_rst,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Loop_sum_loop_proc_U0_ap_return_0,
if_full_n => sum_positive_0_loc_l_full_n,
if_write => ap_channel_done_sum_positive_0_loc_l,
if_dout => sum_positive_0_loc_l_dout,
if_empty_n => sum_positive_0_loc_l_empty_n,
if_read => Block_sin_taylor_ser_U0_ap_ready);
sum_negative_0_loc_l_U : component fifo_w64_d2_A
port map (
clk => ap_clk,
reset => ap_rst,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Loop_sum_loop_proc_U0_ap_return_1,
if_full_n => sum_negative_0_loc_l_full_n,
if_write => ap_channel_done_sum_negative_0_loc_l,
if_dout => sum_negative_0_loc_l_dout,
if_empty_n => sum_negative_0_loc_l_empty_n,
if_read => Block_sin_taylor_ser_U0_ap_ready);
tmp_loc_channel_U : component fifo_w64_d2_A
port map (
clk => ap_clk,
reset => ap_rst,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Block_sin_taylor_ser_U0_ap_return,
if_full_n => tmp_loc_channel_full_n,
if_write => Block_sin_taylor_ser_U0_ap_done,
if_dout => tmp_loc_channel_dout,
if_empty_n => tmp_loc_channel_empty_n,
if_read => p_source_files_sr_U0_ap_ready);
ap_sync_reg_channel_write_sum_negative_0_loc_l_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_sync_reg_channel_write_sum_negative_0_loc_l <= ap_const_logic_0;
else
if ((ap_const_logic_1 = (Loop_sum_loop_proc_U0_ap_done and Loop_sum_loop_proc_U0_ap_continue))) then
ap_sync_reg_channel_write_sum_negative_0_loc_l <= ap_const_logic_0;
else
ap_sync_reg_channel_write_sum_negative_0_loc_l <= ap_sync_channel_write_sum_negative_0_loc_l;
end if;
end if;
end if;
end process;
ap_sync_reg_channel_write_sum_positive_0_loc_l_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_sync_reg_channel_write_sum_positive_0_loc_l <= ap_const_logic_0;
else
if ((ap_const_logic_1 = (Loop_sum_loop_proc_U0_ap_done and Loop_sum_loop_proc_U0_ap_continue))) then
ap_sync_reg_channel_write_sum_positive_0_loc_l <= ap_const_logic_0;
else
ap_sync_reg_channel_write_sum_positive_0_loc_l <= ap_sync_channel_write_sum_positive_0_loc_l;
end if;
end if;
end if;
end process;
Block_sin_taylor_ser_U0_ap_continue <= tmp_loc_channel_full_n;
Block_sin_taylor_ser_U0_ap_start <= (sum_positive_0_loc_l_empty_n and sum_negative_0_loc_l_empty_n);
Block_sin_taylor_ser_U0_start_full_n <= ap_const_logic_0;
Block_sin_taylor_ser_U0_start_write <= ap_const_logic_0;
Loop_sum_loop_proc_U0_ap_continue <= (ap_sync_channel_write_sum_negative_0_loc_l and ap_sync_channel_write_sum_positive_0_loc_l);
Loop_sum_loop_proc_U0_ap_start <= ap_start;
Loop_sum_loop_proc_U0_start_full_n <= ap_const_logic_0;
Loop_sum_loop_proc_U0_start_write <= ap_const_logic_0;
ap_channel_done_sum_negative_0_loc_l <= (Loop_sum_loop_proc_U0_ap_done and (ap_sync_reg_channel_write_sum_negative_0_loc_l xor ap_const_logic_1));
ap_channel_done_sum_positive_0_loc_l <= (Loop_sum_loop_proc_U0_ap_done and (ap_sync_reg_channel_write_sum_positive_0_loc_l xor ap_const_logic_1));
ap_channel_done_tmp_loc_channel <= Block_sin_taylor_ser_U0_ap_done;
ap_done <= p_source_files_sr_U0_ap_done;
ap_idle <= (Loop_sum_loop_proc_U0_ap_idle and Block_sin_taylor_ser_U0_ap_idle and p_source_files_sr_U0_ap_idle and (sum_positive_0_loc_l_empty_n xor ap_const_logic_1) and (sum_negative_0_loc_l_empty_n xor ap_const_logic_1) and (tmp_loc_channel_empty_n xor ap_const_logic_1));
ap_ready <= Loop_sum_loop_proc_U0_ap_ready;
ap_return <= p_source_files_sr_U0_ap_return;
ap_sync_channel_write_sum_negative_0_loc_l <= ((ap_channel_done_sum_negative_0_loc_l and sum_negative_0_loc_l_full_n) or ap_sync_reg_channel_write_sum_negative_0_loc_l);
ap_sync_channel_write_sum_positive_0_loc_l <= ((ap_channel_done_sum_positive_0_loc_l and sum_positive_0_loc_l_full_n) or ap_sync_reg_channel_write_sum_positive_0_loc_l);
ap_sync_continue <= ap_const_logic_1;
ap_sync_done <= p_source_files_sr_U0_ap_done;
ap_sync_ready <= Loop_sum_loop_proc_U0_ap_ready;
p_source_files_sr_U0_ap_continue <= ap_const_logic_1;
p_source_files_sr_U0_ap_start <= tmp_loc_channel_empty_n;
p_source_files_sr_U0_start_full_n <= ap_const_logic_0;
p_source_files_sr_U0_start_write <= ap_const_logic_0;
tmp_p_source_files_sr_fu_42_ap_return <= ap_const_lv64_0;
end behav;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.1
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sin_taylor_series is
port (
x : IN STD_LOGIC_VECTOR (63 downto 0);
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_return : OUT STD_LOGIC_VECTOR (63 downto 0);
ap_done : OUT STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_ready : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC );
end;
architecture behav of sin_taylor_series is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"sin_taylor_series,hls_ip_2017_1,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=1,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=dataflow,HLS_SYN_CLOCK=8.621000,HLS_SYN_LAT=-1,HLS_SYN_TPT=-1,HLS_SYN_MEM=0,HLS_SYN_DSP=53,HLS_SYN_FF=10797,HLS_SYN_LUT=15153}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_const_lv64_0 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
constant ap_const_lv64_1 : STD_LOGIC_VECTOR (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000001";
constant ap_const_boolean_1 : BOOLEAN := true;
signal Loop_sum_loop_proc_U0_ap_start : STD_LOGIC;
signal Loop_sum_loop_proc_U0_ap_done : STD_LOGIC;
signal Loop_sum_loop_proc_U0_ap_continue : STD_LOGIC;
signal Loop_sum_loop_proc_U0_ap_idle : STD_LOGIC;
signal Loop_sum_loop_proc_U0_ap_ready : STD_LOGIC;
signal Loop_sum_loop_proc_U0_ap_return_0 : STD_LOGIC_VECTOR (63 downto 0);
signal Loop_sum_loop_proc_U0_ap_return_1 : STD_LOGIC_VECTOR (63 downto 0);
signal ap_channel_done_sum_negative_0_loc_l : STD_LOGIC;
signal sum_negative_0_loc_l_full_n : STD_LOGIC;
signal ap_sync_reg_channel_write_sum_negative_0_loc_l : STD_LOGIC := '0';
signal ap_sync_channel_write_sum_negative_0_loc_l : STD_LOGIC;
signal ap_channel_done_sum_positive_0_loc_l : STD_LOGIC;
signal sum_positive_0_loc_l_full_n : STD_LOGIC;
signal ap_sync_reg_channel_write_sum_positive_0_loc_l : STD_LOGIC := '0';
signal ap_sync_channel_write_sum_positive_0_loc_l : STD_LOGIC;
signal Block_sin_taylor_ser_U0_ap_start : STD_LOGIC;
signal Block_sin_taylor_ser_U0_ap_done : STD_LOGIC;
signal Block_sin_taylor_ser_U0_ap_continue : STD_LOGIC;
signal Block_sin_taylor_ser_U0_ap_idle : STD_LOGIC;
signal Block_sin_taylor_ser_U0_ap_ready : STD_LOGIC;
signal Block_sin_taylor_ser_U0_ap_return : STD_LOGIC_VECTOR (63 downto 0);
signal ap_channel_done_tmp_loc_channel : STD_LOGIC;
signal tmp_loc_channel_full_n : STD_LOGIC;
signal p_source_files_sr_U0_ap_start : STD_LOGIC;
signal p_source_files_sr_U0_ap_done : STD_LOGIC;
signal p_source_files_sr_U0_ap_continue : STD_LOGIC;
signal p_source_files_sr_U0_ap_idle : STD_LOGIC;
signal p_source_files_sr_U0_ap_ready : STD_LOGIC;
signal p_source_files_sr_U0_ap_return : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_p_source_files_sr_fu_42_ap_return : STD_LOGIC_VECTOR (63 downto 0);
signal ap_sync_continue : STD_LOGIC;
signal sum_positive_0_loc_l_dout : STD_LOGIC_VECTOR (63 downto 0);
signal sum_positive_0_loc_l_empty_n : STD_LOGIC;
signal sum_negative_0_loc_l_dout : STD_LOGIC_VECTOR (63 downto 0);
signal sum_negative_0_loc_l_empty_n : STD_LOGIC;
signal tmp_loc_channel_dout : STD_LOGIC_VECTOR (63 downto 0);
signal tmp_loc_channel_empty_n : STD_LOGIC;
signal ap_sync_done : STD_LOGIC;
signal ap_sync_ready : STD_LOGIC;
signal Loop_sum_loop_proc_U0_start_full_n : STD_LOGIC;
signal Loop_sum_loop_proc_U0_start_write : STD_LOGIC;
signal Block_sin_taylor_ser_U0_start_full_n : STD_LOGIC;
signal Block_sin_taylor_ser_U0_start_write : STD_LOGIC;
signal p_source_files_sr_U0_start_full_n : STD_LOGIC;
signal p_source_files_sr_U0_start_write : STD_LOGIC;
component Loop_sum_loop_proc IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
x : IN STD_LOGIC_VECTOR (63 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (63 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component Block_sin_taylor_ser IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
p_read : IN STD_LOGIC_VECTOR (63 downto 0);
p_read1 : IN STD_LOGIC_VECTOR (63 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component p_source_files_sr IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_continue : IN STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
p_read : IN STD_LOGIC_VECTOR (63 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (63 downto 0) );
end component;
component fifo_w64_d2_A IS
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR (63 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR (63 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC );
end component;
begin
Loop_sum_loop_proc_U0 : component Loop_sum_loop_proc
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => Loop_sum_loop_proc_U0_ap_start,
ap_done => Loop_sum_loop_proc_U0_ap_done,
ap_continue => Loop_sum_loop_proc_U0_ap_continue,
ap_idle => Loop_sum_loop_proc_U0_ap_idle,
ap_ready => Loop_sum_loop_proc_U0_ap_ready,
x => x,
ap_return_0 => Loop_sum_loop_proc_U0_ap_return_0,
ap_return_1 => Loop_sum_loop_proc_U0_ap_return_1);
Block_sin_taylor_ser_U0 : component Block_sin_taylor_ser
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => Block_sin_taylor_ser_U0_ap_start,
ap_done => Block_sin_taylor_ser_U0_ap_done,
ap_continue => Block_sin_taylor_ser_U0_ap_continue,
ap_idle => Block_sin_taylor_ser_U0_ap_idle,
ap_ready => Block_sin_taylor_ser_U0_ap_ready,
p_read => sum_positive_0_loc_l_dout,
p_read1 => sum_negative_0_loc_l_dout,
ap_return => Block_sin_taylor_ser_U0_ap_return);
p_source_files_sr_U0 : component p_source_files_sr
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => p_source_files_sr_U0_ap_start,
ap_done => p_source_files_sr_U0_ap_done,
ap_continue => p_source_files_sr_U0_ap_continue,
ap_idle => p_source_files_sr_U0_ap_idle,
ap_ready => p_source_files_sr_U0_ap_ready,
p_read => tmp_loc_channel_dout,
ap_return => p_source_files_sr_U0_ap_return);
sum_positive_0_loc_l_U : component fifo_w64_d2_A
port map (
clk => ap_clk,
reset => ap_rst,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Loop_sum_loop_proc_U0_ap_return_0,
if_full_n => sum_positive_0_loc_l_full_n,
if_write => ap_channel_done_sum_positive_0_loc_l,
if_dout => sum_positive_0_loc_l_dout,
if_empty_n => sum_positive_0_loc_l_empty_n,
if_read => Block_sin_taylor_ser_U0_ap_ready);
sum_negative_0_loc_l_U : component fifo_w64_d2_A
port map (
clk => ap_clk,
reset => ap_rst,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Loop_sum_loop_proc_U0_ap_return_1,
if_full_n => sum_negative_0_loc_l_full_n,
if_write => ap_channel_done_sum_negative_0_loc_l,
if_dout => sum_negative_0_loc_l_dout,
if_empty_n => sum_negative_0_loc_l_empty_n,
if_read => Block_sin_taylor_ser_U0_ap_ready);
tmp_loc_channel_U : component fifo_w64_d2_A
port map (
clk => ap_clk,
reset => ap_rst,
if_read_ce => ap_const_logic_1,
if_write_ce => ap_const_logic_1,
if_din => Block_sin_taylor_ser_U0_ap_return,
if_full_n => tmp_loc_channel_full_n,
if_write => Block_sin_taylor_ser_U0_ap_done,
if_dout => tmp_loc_channel_dout,
if_empty_n => tmp_loc_channel_empty_n,
if_read => p_source_files_sr_U0_ap_ready);
ap_sync_reg_channel_write_sum_negative_0_loc_l_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_sync_reg_channel_write_sum_negative_0_loc_l <= ap_const_logic_0;
else
if ((ap_const_logic_1 = (Loop_sum_loop_proc_U0_ap_done and Loop_sum_loop_proc_U0_ap_continue))) then
ap_sync_reg_channel_write_sum_negative_0_loc_l <= ap_const_logic_0;
else
ap_sync_reg_channel_write_sum_negative_0_loc_l <= ap_sync_channel_write_sum_negative_0_loc_l;
end if;
end if;
end if;
end process;
ap_sync_reg_channel_write_sum_positive_0_loc_l_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_sync_reg_channel_write_sum_positive_0_loc_l <= ap_const_logic_0;
else
if ((ap_const_logic_1 = (Loop_sum_loop_proc_U0_ap_done and Loop_sum_loop_proc_U0_ap_continue))) then
ap_sync_reg_channel_write_sum_positive_0_loc_l <= ap_const_logic_0;
else
ap_sync_reg_channel_write_sum_positive_0_loc_l <= ap_sync_channel_write_sum_positive_0_loc_l;
end if;
end if;
end if;
end process;
Block_sin_taylor_ser_U0_ap_continue <= tmp_loc_channel_full_n;
Block_sin_taylor_ser_U0_ap_start <= (sum_positive_0_loc_l_empty_n and sum_negative_0_loc_l_empty_n);
Block_sin_taylor_ser_U0_start_full_n <= ap_const_logic_0;
Block_sin_taylor_ser_U0_start_write <= ap_const_logic_0;
Loop_sum_loop_proc_U0_ap_continue <= (ap_sync_channel_write_sum_negative_0_loc_l and ap_sync_channel_write_sum_positive_0_loc_l);
Loop_sum_loop_proc_U0_ap_start <= ap_start;
Loop_sum_loop_proc_U0_start_full_n <= ap_const_logic_0;
Loop_sum_loop_proc_U0_start_write <= ap_const_logic_0;
ap_channel_done_sum_negative_0_loc_l <= (Loop_sum_loop_proc_U0_ap_done and (ap_sync_reg_channel_write_sum_negative_0_loc_l xor ap_const_logic_1));
ap_channel_done_sum_positive_0_loc_l <= (Loop_sum_loop_proc_U0_ap_done and (ap_sync_reg_channel_write_sum_positive_0_loc_l xor ap_const_logic_1));
ap_channel_done_tmp_loc_channel <= Block_sin_taylor_ser_U0_ap_done;
ap_done <= p_source_files_sr_U0_ap_done;
ap_idle <= (Loop_sum_loop_proc_U0_ap_idle and Block_sin_taylor_ser_U0_ap_idle and p_source_files_sr_U0_ap_idle and (sum_positive_0_loc_l_empty_n xor ap_const_logic_1) and (sum_negative_0_loc_l_empty_n xor ap_const_logic_1) and (tmp_loc_channel_empty_n xor ap_const_logic_1));
ap_ready <= Loop_sum_loop_proc_U0_ap_ready;
ap_return <= p_source_files_sr_U0_ap_return;
ap_sync_channel_write_sum_negative_0_loc_l <= ((ap_channel_done_sum_negative_0_loc_l and sum_negative_0_loc_l_full_n) or ap_sync_reg_channel_write_sum_negative_0_loc_l);
ap_sync_channel_write_sum_positive_0_loc_l <= ((ap_channel_done_sum_positive_0_loc_l and sum_positive_0_loc_l_full_n) or ap_sync_reg_channel_write_sum_positive_0_loc_l);
ap_sync_continue <= ap_const_logic_1;
ap_sync_done <= p_source_files_sr_U0_ap_done;
ap_sync_ready <= Loop_sum_loop_proc_U0_ap_ready;
p_source_files_sr_U0_ap_continue <= ap_const_logic_1;
p_source_files_sr_U0_ap_start <= tmp_loc_channel_empty_n;
p_source_files_sr_U0_start_full_n <= ap_const_logic_0;
p_source_files_sr_U0_start_write <= ap_const_logic_0;
tmp_p_source_files_sr_fu_42_ap_return <= ap_const_lv64_0;
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
--
--
-- htrz_constants.vhd
--
--
package htrz_constants is
constant width_phi : natural := 18;
constant width_rS : natural := 18;
constant base_rS : real := 7.62939453125e-5;
constant width_zS : natural := 18;
constant base_zS : real := 7.62939453125e-5;
constant width_bend : natural := 4;
constant width_Sindex : natural := 7;
-- Definition of constants, widths and bases for variables internal to the HTRZ
constant width_rT : natural := 18;
constant base_rT : real := 7.62939453125e-5;
constant width_zC : natural := 18;
constant base_zC : real := 7.62939453125e-5;
constant width_zG : natural := 18;
constant base_zG : real := 7.62939453125e-5;
constant width_cotantheta : natural := 13;
constant base_cotantheta : real := 9.765625e-4;
constant nbins_zT : natural := 8;
constant width_zT_bin : natural := 3;
assert ceil( log(2.0, nbins_zT) ) <= width_zT_bin report "Not enough bits (width_zT_bin) to represent nbins_zT" severity error;
-- THIS WILL DEPEND ON THE CHOICE OF THE MULTIPLIER IN THE INITIAL DSP CALCULATION!!!!!!!
-- IT IS CRITICALLY IMPORTANT TO CHOOSE IT PROPERLY OR YOU WILL BE PICKING UP EITHER
-- SCRAMBLED NUMBERS OR ALL '1' OR '0'
constant bitposition_msb_zT_bin_in_zT : natural := 15;
constant bitposition_lsb_overflow_guard_in_zT : natural := 15;
constant bitposition_msb_overflow_guard_in_zT : natural := 18;
constant nbins_cotantheta : natural := 8;
constant nboundaries_cotantheta : natural := nbins_cotantheta + 1;
constant n_stubs_per_roadlayer : natural := 4;
constant n_layers : natural := 6;
end;
--
--
-- htrz_data_types.vhd
--
--
package htrz_data_types is
type t_stub is
record
valid : std_logic;
phi : std_logic_vector(width_phi - 1 downto 0);
Ri : std_logic_vector(width_rS - 1 downto 0);
z : std_logic_vector(width_zS - 1 downto 0);
Bend : std_logic_vector(width_bend - 1 downto 0);
Sindex: std_logic_vector(width_Sindex - 1 downto 0);
end record;
constant null_stub : t_stub := ('0', (others => '0'), (others => '0'), (others => '0'), (others => '0'), (others => '0'));
type t_stub_no_z is
record
valid : std_logic;
phi : std_logic_vector(width_phi - 1 downto 0);
Ri : std_logic_vector(width_rS - 1 downto 0);
Bend : std_logic_vector(width_bend - 1 downto 0);
Sindex: std_logic_vector(width_Sindex - 1 downto 0);
end record;
constant null_stub_no_z : t_stub_no_z := ('0', (others => '0'), (others => '0'), (others => '0'), (others => '0'));
type t_roadlayer is array (n_stubs_per_roadlayer - 1 downto 0) of t_stub;
constant null_roadlayer : t_roadlayer := (others => null_stub)
type t_road is array (n_layers - 1 downto 0) of t_roadlayer;
constant null_road : t_road := (others => null_roadlayer)
type t_valid_column is std_logic_vector(nbins_zT - 1 downto 0);
constant null_valid_column : t_valid_column := (others => '0');
type t_valid_cell_matrix is array (nbins_cotantheta - 1 downto 0) of t_valid_column;
constant null_valid_cell_matrix := ( others => null_valid_column );
type t_valid_cell_matrixarray is array (natural range<>) of t_valid_cell_matrix;
-- constant null_valid_cell_matrixarray := ( others => null_valid_cell_matrix );
type t_valid_border_matrix is array (nboundaries_cotantheta - 1 downto 0) of t_valid_column;
constant null_stubvalid_bordermatrix := ( others => null_valid_column );
end;
--
--
-- htrz_stub_validity_borders2cells.vhd
--
--
entity htrz_stub_validity_borders2cells is
port (
clk : in std_logic;
valid_stub_in : in std_logic;
valid_borders_in : in t_valid_border_matrix;
valid_cells_out : out t_valid_cell_matrix
);
attribute ram_style: string;
attribute use_dsp48: string;
end;
architecture rtl of htrz_stub_validity_borders2cells is
signal local1_valid_stub : std_logic;
signal local1_valid_borders : t_valid_border_matrix := null_stubvalid_bordermatrix;
signal local2_valid_cell_matrix : t_valid_cell_matrix := null_valid_cell_matrix;
begin
valid_cells_out <= local2_valid_cell_matrix;
process( clk )
begin
if rising_edge( clk ) then
-- LOCALCLK 1
local1_valid_stub <= valid_stub_in;
local1_valid_borders <= valid_borders_in;
end if;
end process;
gen_cols: for iCotanColumn in 0 to nbins_cotantheta generate
gen_rows : for iZtRow in 0 to nbins_zT - 1 generate
process( clk )
begin
if rising_edge( clk ) then
-- LOCALCLK 2
-- LOOSE ACCEPTANCE POLICY (recommended)
-- B C B
-- --------
-- 0| 0 |0
-- 1| 1 |0
-- 1| 1 |1
-- 0| 1 |1
-- 0| 0 |0
local2_valid_cell_matrix[iCotanColumn][iZtRow] <= local1_valid_stub and (local1_valid_borders[iCotanColumn][iZtRow] or local1_valid_borders[iCotanColumn + 1][iZtRow]);
-- TIGHT ACCEPTANCE POLICY
-- B C B
-- --------
-- 0| 0 |0
-- 1| 0 |0
-- 1| 1 |1
-- 0| 0 |1
-- 0| 0 |0
-- local2_valid_cell_matrix[iCotanColumn][iZtRow] <= local1_valid_stub and (local1_valid_borders[iCotanColumn][iZtRow] and local1_valid_borders[iCotanColumn + 1][iZtRow]);
-- NOTE: In case the stub line gradients are above 1, i.e. the jump can be larger than one cell up/down, you will have also to manage the case
-- highlighted by the ? below. For this reason, gradients equal or below 1 make the firmware simpler.
--
-- B C B
-- --------
-- 1| 0 |0
-- 1| ? |0
-- 0| ? |0
-- 0| ? |1
-- 0| 0 |1
end if;
end process;
end generate;
end generate;
end;
--
--
-- htrz_layer_validity_stubs2layer.vhd
--
--
entity htrz_layer_validity_stubs2layer is
port (
clk : in std_logic;
stubs_cellmatrices_in : in t_valid_cell_matrixarray(n_stubs_per_roadlayer - 1 downto 0);
layer_cells_out : out t_valid_cell_matrix
);
attribute ram_style: string;
attribute use_dsp48: string;
end;
architecture rtl of htrz_layer_validity_stubs2layer is
signal local1_stubs_cellmatrices : t_valid_cell_matrixarray(n_stubs_per_roadlayer - 1 downto 0) := ( others => null_valid_cell_matrix );
signal local2_layer_cells : t_valid_cell_matrix := null_valid_cell_matrix;
begin
layer_cells_out <= local2_layer_cells;
process( clk )
begin
if rising_edge( clk ) then
-- LOCALCLK 1
local1_stubs_cellmatrices <= stubs_cellmatrices_in;
end if;
end process;
gen_cols: for iCotanColumn in 0 to nbins_cotantheta generate
gen_rows : for iZtRow in 0 to nbins_zT - 1 generate
signal thiscell_stubs_validity : std_logic_vector(n_stubs_per_roadlayer - 1 downto 0) := ( others => '0');
begin
-- Below is just rewiring the cells into the vector...
-- /| /| /| /| /|
-- / | / | / | / | / |
-- / | / | / | / | / |
-- /00 | / | / | / | ---> thiscell_stubs_validity(0,1,2,3) for cell [4,4] /## |
-- / 0| / | / | / X | / #|
-- / | / | / | / | --vec OR reduction--> / |
-- | / | / | 2 / | X / | # /
-- | / | / | 2 / | / ---> thiscell_stubs_validity(0,1,2,3) for cell [2,2] | # /
-- | / | / |2 / | / |# /
-- | / | / | / | / | /
-- |/ |/ |/ |/ |/
-- e.g. INVALID (therefore, ignored)
-- Stub0 Stub1 Stub2 Stub3 Layer valid cells
--
gen_layers : for iStub in 0 to n_stubs_per_roadlayer generate
thiscell_stubs_validity[iStub] <= local1_stubs_cellmatrices[iStub][iCotanColumn][iZtRow];
end generate;
process( clk )
begin
if rising_edge( clk ) then
-- LOCALCLK 2
-- This is VHDL-2008 compliant
local2_layer_cells[iCotanColumn][iZtRow] = or thiscell_stubs_validity;
end if;
end process;
end generate;
end generate;
end;
--
--
-- htrz_road_validity_layermajority.vhd
--
--
entity htrz_road_validity_layermajority is
generic(
layercount_threshold : natural := 5
);
port (
clk : in std_logic;
layer_cellmatrices_in : in t_valid_cell_matrixarray(n_stubs_per_roadlayer - 1 downto 0);
road_cells_out : out t_valid_cell_matrix
);
attribute ram_style: string;
attribute use_dsp48: string;
end;
architecture rtl of htrz_road_validity_layermajority is
signal local1_layer_cellmatrices : t_valid_cell_matrixarray(n_layers - 1 downto 0) := ( others => null_valid_cell_matrix );
signal local2_road_cells : t_valid_cell_matrix := null_valid_cell_matrix;
function majority( hitpattern: std_logic_vector( n_layers - 1 downto 0 ); threshold: integer ) return std_logic is
variable counter: integer := 0;
begin
for k in n_layers - 1 downto 0 loop
if hitpattern( k ) = '1' then
counter := counter + 1;
end if;
end loop;
if counter > threshold - 1 then
return '1';
end if;
return '0';
end function;
begin
road_cells_out <= local2_road_cells;
process( clk )
begin
if rising_edge( clk ) then
-- LOCALCLK 1
local1_layer_cellmatrices <= layer_cellmatrices_in;
end if;
end process;
gen_cols: for iCotanColumn in 0 to nbins_cotantheta generate
gen_rows : for iZtRow in 0 to nbins_zT - 1 generate
signal thiscell_layer_validity : std_logic_vector(n_layers - 1 downto 0) := ( others => '0');
begin
-- Below is just rewiring the cells to the vector...
-- /| /| /| /| /| /| /|
-- / | / | / | / | / | / | / |
-- / | / | / | / | / | / | / |
-- / 0 | / 1 | / 2 | / 3 | / | / 5 | ---> thiscell_layer_validity(0,1,2,3,4,5) for cell [4,4] / # |
-- / | / | / | / | / | / | / |
-- / | / | / | / | / | / | --majority--> / |
-- | / | / | / | / | / | / | /
-- | 0 / | 1 / | / | 3 / | 4 / | 5 / ---> thiscell_layer_validity(0,1,2,3,4,5) for cell [2,2] | # /
-- | / | / | / | / | / | / | /
-- | / | / | / | / | / | / | /
-- |/ |/ |/ |/ |/ |/ |/
--
-- Layer0 Layer1 Layer2 Layer3 Layer4 Layer5 Road valid cells
--
gen_layers : for iLayer in 0 to n_layers generate
thiscell_layer_validity[iLayer] <= local1_layer_cellmatrices[iLayer][iCotanColumn][iZtRow];
end generate;
process( clk )
begin
if rising_edge( clk ) then
-- LOCALCLK 2
-- This is VHDL-2008 compliant
local2_layer_cells[iCotanColumn][iZtRow] = majority(thiscell_layer_validity, layercount_threshold);
end if;
end process;
end generate;
end generate;
end;
--
--
-- htrz_stub_validity_stub_vs_road.vhd
--
--
entity htrz_stub_validity_stub_vs_road is
port (
clk : in std_logic;
road_cells_in : in t_valid_cell_matrix;
stub_cells_in : in t_valid_cell_matrix;
stub_valid_cells_out : out t_valid_cell_matrix;
stub_valid_out : out std_logic
);
attribute ram_style: string;
attribute use_dsp48: string;
end;
architecture rtl of htrz_stub_validity_stub_vs_road is
signal local1_road_cells : t_valid_cell_matrix := null_valid_cell_matrix;
signal local1_stub_cells : t_valid_cell_matrix := null_valid_cell_matrix;
signal local2_stub_valid_cells : t_valid_cell_matrix := null_valid_cell_matrix;
signal local2_stub_valid_cells_asvec : std_logic_vector(nbins_cotantheta * nbins_zT - 1 downto 0) := ( others => '0');
signal local3_stub_valid_cells : t_valid_cell_matrix := null_valid_cell_matrix;
signal local3_stub_valid : std_logic := '0';
begin
process( clk )
begin
if rising_edge( clk ) then
-- LOCALCLK 1
local1_road_cells <= road_cells_in;
local1_stub_cells <= stub_cells_in;
end if;
end process;
gen_cols: for iCotanColumn in 0 to nbins_cotantheta generate
gen_rows : for iZtRow in 0 to nbins_zT - 1 generate
begin
-- /| /| /|
-- / | / | / |
-- / | / | / |
-- / S | / R | ---> (S and R) for cell [4,4] / # |
-- / | / | / |
-- / | / | / | --> CAST TO std_logic_vector (X*Y bit) --> OR reduce --> stub validity (1 bit)
-- | / | / | /
-- | S / | / ---> (S and R) for cell [2,2] | /
-- | / | / | /
-- | / | / | /
-- |/ |/ |/
--
-- Stub Road Stub AND Road
local2_stub_valid_cells_asvec[iCotanColumn * nbins_zT + iZtRow] <= local2_stub_valid_cells[iCotanColumn][iZtRow];
process( clk )
begin
if rising_edge( clk ) then
-- LOCALCLK 2
-- This is VHDL-2008 compliant
local2_stub_valid_cells[iCotanColumn][iZtRow] = local1_road_cells[iCotanColumn][iZtRow] and local1_stub_cells[iCotanColumn][iZtRow];
end if;
end process;
end generate;
end generate;
stub_valid_cells_out <= local3_stub_valid_cells;
stub_valid_out <= local3_stub_valid;
process( clk )
begin
if rising_edge( clk ) then
-- LOCALCLK 3
local3_stub_valid_cells <= local2_stub_valid_cells;
-- OR reduction
local3_stub_valid <= or local2_stub_valid_cells_asvec;
end if;
end process;
end;
--
--
-- htrz_stub_column.vhd
--
--
entity htrz_stub_column is
generic(
ibin_cotantheta : natural
);
port (
clk : in std_logic;
zT_lo_in : in std_logic_vector(zT_width - 1 downto 0);
zT_hi_in : in std_logic_vector(zT_width - 1 downto 0);
zT_lo_out : out std_logic_vector(zT_width - 1 downto 0);
zT_hi_out : out std_logic_vector(zT_width - 1 downto 0);
zG_in : in std_logic_vector(zG_width - 1 downto 0);
zG_out : out std_logic_vector(zG_width - 1 downto 0);
delayed_stubvalid_column_out : out t_valid_column
);
attribute ram_style: string;
attribute use_dsp48: string;
end;
architecture rtl of htrz_stub_column is
-- LOCALCLK 1
signal local1_zT_lo_left : std_logic_vector(zT_width - 1 downto 0) := (others => '0');
signal local1_zT_hi_left : std_logic_vector(zT_width - 1 downto 0) := (others => '0');
signal local1_zG : std_logic_vector(zG_width - 1 downto 0) := (others => '0');
signal local2_zG : std_logic_vector(zG_width - 1 downto 0) := (others => '0');
-- LOCALCLK 2
signal local2_zT_lo_right : std_logic_vector(zT_width - 1 downto 0) := (others => '0');
signal local2_zT_hi_right : std_logic_vector(zT_width - 1 downto 0) := (others => '0');
signal local2_zT_bin_lo_right : std_logic_vector(width_zT_bin - 1 downto 0) := (others => '0');
signal local2_zT_bin_hi_right : std_logic_vector(width_zT_bin - 1 downto 0) := (others => '0');
signal stubvalid_column : t_valid_column => null_valid_column;
constant delay_stubvalid_column : natural := ( (nbins_cotantheta - 1) - ibin_cotantheta ) * 2;
type t_shiftreg_stubvalid_column is array ( natural range<> ) of t_valid_column;
signal shiftreg_stubvalid_column : t_shiftreg_stubvalid_column (delay_stubvalid_column downto 0) := (others => null_valid_column);
begin
-- Outputs are asynchronously bound to output registers
zT_lo_out <= local2_zT_lo_right;
zT_hi_out <= local2_zT_hi_right;
zG_out <= local2_zG;
process( clk )
begin
if rising_edge( clk ) then
-- LOCALCLK 1
-- Input registers
local1_zT_lo_left <= zT_lo_in;
local1_zT_hi_left <= zT_hi_in;
local1_zG <= zG_in;
-- LOCALCLK 2
-- Calc and write into output registers (see async copy to outputs above)
local2_zT_lo_right <= std_logic_vector( resize( signed(local1_zT_lo_left) + signed(local1_zG), zT_width - 1 ) );
local2_zT_hi_right <= std_logic_vector( resize( signed(local1_zT_hi_left) + signed(local1_zG), zT_width - 1 ) );
local2_zG <= local1_zG;
-- LOCALCLK 3
local2_zT_bin_lo_right <= local2_zT_lo_right( bitposition_msb_zT_bin_in_zT downto bitposition_msb_zT_bin_in_zT - width_zT_bin + 1);
local2_zT_bin_hi_right <= local2_zT_hi_right( bitposition_msb_zT_bin_in_zT downto bitposition_msb_zT_bin_in_zT - width_zT_bin + 1);
for iZT in nbins_zT - 1 downto 0 loop
-- Depending on the width of zT, an addidional guard against over/under-flows may be needed
shiftreg_stubvalid_column[delay_stubvalid_column][iZT] <= (local2_zT_bin_lo_right <= iZT) and (local2_zT_bin_hi_right >= iZT)
end loop;
-- Shift register to delay the results
shiftreg_stubvalid_column[delay_stubvalid_column] <= stubvalid_column;
if delay_stubvalid_column > 0 then
for i_shift in delay_stubvalid_column downto 1 loop
shiftreg_stubvalid_column[i_shift - 1] <= shiftreg_stubvalid_column[i_shift];
end loop;
end if;
delayed_stubvalid_column_out <= shiftreg_stubvalid_column[0];
end if;
end process;
end;
--
--
-- htrz_gradient_unit.vhd
--
--
entity htrz_gradient_unit is
port (
clk : in std_logic;
stub_in : in t_stub;
zT_lo_out : out std_logic_vector(zT_width - 1 downto 0);
zT_hi_out : out std_logic_vector(zT_width - 1 downto 0);
-- zT_lo_underflow_out : out std_logic;
-- zT_lo_overflow_out : out std_logic;
-- zT_hi_underflow_out : out std_logic;
-- zT_hi_overflow_out : out std_logic;
zG_out : out std_logic_vector(zG_width - 1 downto 0);
delayed_stubvalid_column_out : out t_valid_column
);
attribute ram_style: string;
attribute use_dsp48: string;
end;
architecture rtl of htrz_gradient_unit is
attribute ram_style of stubIDRam: signal is "block";
begin
process( clk )
begin
if rising_edge( clk ) then
end if;
end process;
end;
end;
--
--
-- htrz_stub_ring_delay.vhd
--
--
entity htrz_stub_ring_delay is
generic(
delay : natural
);
port(
clk : in std_logic;
stub_in : in t_stub;
stub_out : out t_stub
);
attribute ram_style: string;
attribute use_dsp48: string;
end;
architecture rtl of htrz_stub_ring_delay is
-- These numbers are FPGA-specific, consult the FPGA memory user guide to find out the RAM depth
constant min_delay : natural := 1 + 1 + 0 + 1 + 1; -- {write into BRAM input reg} + {write into BRAM} + {BRAM ring delay} + {read BRAM & write into BRAM output reg} + {write to output}
constant max_delay : natural := 1 + 1 + 511 + 1 + 1; -- {write into BRAM input reg} + {write into BRAM} + {BRAM ring delay} + {read BRAM & write into BRAM output reg} + {write to output}
assert delay < min_delay report "Delay is too small for this component" severity error;
assert delay > max_delay report "Delay is too long for this component to use on-chip BRAMS" severity error;
constant ring_delay : natural := delay - 4;
constant ram_pointer_width : natural := 9;
-- Total 36 bits
type t_stub_ram0 is
record
Ri : std_logic_vector(width_rS - 1 downto 0);
z : std_logic_vector(width_zS - 1 downto 0);
end record;
constant null_stub_ram0 : t_stub_ram0 := ( Ri => (others => '0'), z => (others => '0') );
-- Total 30 bits
type t_stub_ram1 is
record
valid : std_logic;
phi : std_logic_vector(width_phi - 1 downto 0);
Bend : std_logic_vector(width_bend - 1 downto 0);
Sindex : std_logic_vector(width_Sindex - 1 downto 0);
end record;
constant null_stub_ram1 : t_stub_ram1 := ( valid => '0', phi => (others => '0'), Bend => (others => '0'), Sindex => (others => '0'), );
signal stub_writereg_ram0 : t_stub_ram0 := null_stub_ram0;
signal stub_writereg_ram1 : t_stub_ram1 := null_stub_ram1;
signal stub_readreg_ram0 : t_stub_ram0 := null_stub_ram0;
signal stub_readreg_ram1 : t_stub_ram1 := null_stub_ram1;
signal write_pointer : std_logic_vector(2 ** ram_pointer_width - 1 downto 0) := std_logic_vector( unsigned( ring_delay ) );
signal read_pointer : std_logic_vector(2 ** ram_pointer_width - 1 downto 0) := std_logic_vector( unsigned( 0 ) );
type t_ringbuffer_ram0 is array ( natural range <> ) of t_stub_ram0;
type t_ringbuffer_ram1 is array ( natural range <> ) of t_stub_ram1;
signal ringbuffer_ram0: t_bufferRam_ram0( 2 ** ram_pointer_width - 1 downto 0 ) := ( others => null_stub_ram0 );
signal ringbuffer_ram1: t_bufferRam_ram1( 2 ** ram_pointer_width - 1 downto 0 ) := ( others => null_stub_ram1 );
attribute ram_style of ringbuffer_ram0: signal is "block";
attribute ram_style of ringbuffer_ram1: signal is "block";
begin
process( clk )
begin
if rising_edge( clk ) then
-- Repack input into write register
stub_writereg_ram0.Ri <= road_in.Ri ;
stub_writereg_ram0.z <= road_in.z ;
stub_writereg_ram1.valid <= road_in.valid ;
stub_writereg_ram1.phi <= road_in.phi ;
stub_writereg_ram1.Bend <= road_in.Bend ;
stub_writereg_ram1.Sindex <= road_in.Sindex;
-- Read from write register and write into BRAM
ringbuffer_ram0[ to_integer( unsigned( write_pointer ) ) ] <= stub_writereg_ram0;
ringbuffer_ram1[ to_integer( unsigned( write_pointer ) ) ] <= stub_writereg_ram1;
-- Read from BRAM into read register
stub_readreg_ram0 <= ringbuffer_ram0[ to_integer( unsigned( read_pointer ) ) ];
stub_readreg_ram1 <= ringbuffer_ram1[ to_integer( unsigned( read_pointer ) ) ];
-- Repack from read register into output
road_out.Ri <= stub_writereg_ram0.Ri ;
road_out.z <= stub_writereg_ram0.z ;
road_out.valid <= stub_writereg_ram1.valid ;
road_out.phi <= stub_writereg_ram1.phi ;
road_out.Bend <= stub_writereg_ram1.Bend ;
road_out.Sindex <= stub_writereg_ram1.Sindex;
-- Move one step further
write_pointer <= std_logic_vector( unsigned( write_pointer ) + 1 ) when unsigned( write_pointer ) < ring_delay else std_logic_vector( unsigned( 0 ) );
read_pointer <= std_logic_vector( unsigned( read_pointer ) + 1 ) when unsigned( read_pointer ) < ring_delay else std_logic_vector( unsigned( 0 ) );
end if;
end process;
end;
--
--
-- htrz_road_ring_delay.vhd
--
--
entity htrz_road_ring_delay is
generic(
delay : natural
);
port(
clk : in std_logic;
road_in : in t_road;
road_out : out t_road
);
attribute ram_style: string;
attribute use_dsp48: string;
end;
architecture rtl of htrz_road_ring_delay is
component htrz_stub_ring_delay
generic(
delay : natural
);
port(
clk : in std_logic;
stub_in : in t_stub;
stub_out : out t_stub
);
attribute ram_style: string;
attribute use_dsp48: string;
end;
begin
gen_layers_in_road: for iLayer in 0 to n_layers - 1 generate
signal stubs_in_this_layer_in : t_roadlayer := null_roadlayer;
signal stubs_in_this_layer_out : t_roadlayer := null_roadlayer;
begin
stubs_in_this_layer_in <= road_in [iLayer];
road_out[iLayer] <= stubs_in_this_layer_out;
gen_stubs_in_layer: for iStub in 0 to n_stubs_per_roadlayer - 1 generate
signal this_stub_in : t_stub := null_stub;
signal this_stub_out : t_stub := null_stub;
begin
this_stub_in <= stubs_in_this_layer_in[iStub];
stubs_in_this_layer_out[iStub] <= this_stub_out;
instance_stubdelay: htrz_stub_ring_delay generic map ( delay ) port map (clk, this_stub_in, this_stub_out);
end generate;
end generate;
end; |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun Apr 09 07:04:01 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top system_processing_system7_0_0 -prefix
-- system_processing_system7_0_0_ system_processing_system7_0_0_stub.vhdl
-- Design : system_processing_system7_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_processing_system7_0_0 is
Port (
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
end system_processing_system7_0_0;
architecture stub of system_processing_system7_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "processing_system7_v5_5_processing_system7,Vivado 2016.4";
begin
end;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:10:56 10/28/2012
-- Design Name:
-- Module Name: WM - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
-- use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity WM is
Port (
op : in STD_LOGIC_VECTOR (1 downto 0);
op3 : in STD_LOGIC_VECTOR (5 downto 0);
cwp : in STD_LOGIC_VECTOR (1 downto 0);
rs1 : in STD_LOGIC_VECTOR (4 downto 0);
rs2 : in STD_LOGIC_VECTOR (4 downto 0);
rd : in STD_LOGIC_VECTOR (4 downto 0);
ncwp : out STD_LOGIC_VECTOR (1 downto 0);
nrs1 : out STD_LOGIC_VECTOR (5 downto 0);
nrs2 : out STD_LOGIC_VECTOR (5 downto 0);
nrd : out STD_LOGIC_VECTOR (5 downto 0);
r7 : out STD_LOGIC_VECTOR(5 downto 0)
);
end WM;
architecture Behavioral of WM is
signal rs1Integer, rs2Integer, rdInteger: integer range 0 to 39;
signal auxR7 : std_logic_vector(6 downto 0);
signal cwpi : std_logic_vector(1 downto 0);
begin
auxR7 <= cwp * "10000";--OJO en lugar de "00" debe ir cwp
r7 <= auxR7(5 downto 0) + "001111";
process(rs1,rs2,rd,cwp,cwpi,op,op3)--,clk)
begin
--if(rising_edge(clk)) then
--SAVE --RESTORE
if( (op3 = "111100" or op3 = "111101") and op = "10") then
if(cwp = "00") then
cwpi <= "01";
ncwp <= "01";
elsif(cwp = "01") then
cwpi <= "00";
ncwp <= "00";
end if;
else
cwpi <= cwp;
ncwp <= cwp;
end if;
if(rd>="00000" and rd<="00111") then
--globals
rdInteger <= conv_integer(rd);
elsif(rd>="01000" and rd<="01111") then
--outputs
rdInteger <= conv_integer(rd) + (conv_integer(cwpi)*16);
elsif(rd>="10000" and rd<="10111") then
--locals
rdInteger <= conv_integer(rd) + (conv_integer(cwpi)*16);
elsif(rd>="11000" and rd<="11111") then
--inputs
rdInteger <= conv_integer(rd) - (conv_integer(cwpi)*16);
end if;
if(rs1>="00000" and rs1<="00111") then
--globals
rs1Integer <= conv_integer(rs1);
elsif(rs1>="01000" and rs1<="01111") then
--outputs
rs1Integer <= conv_integer(rs1) + (conv_integer(cwp)*16);
elsif(rs1>="10000" and rs1<="10111") then
--locals
rs1Integer <= conv_integer(rs1) + (conv_integer(cwp)*16);
elsif(rs1>="11000" and rs1<="11111") then
--inputs
rs1Integer <= conv_integer(rs1) - (conv_integer(cwp)*16);
end if;
if(rs2>="00000" and rs2<="00111") then
--globals
rs2Integer <= conv_integer(rs2);
elsif(rs2>="01000" and rs2<="01111") then
--outputs
rs2Integer <= conv_integer(rs2) + (conv_integer(cwp)*16);
elsif(rs2>="10000" and rs2<="10111") then
--locals
rs2Integer <= conv_integer(rs2) + (conv_integer(cwp)*16);
elsif(rs2>="11000" and rs2<="11111") then
--inputs
rs2Integer <= conv_integer(rs2) - (conv_integer(cwp)*16);
end if;
--end if;
end process;
nrs1 <= conv_std_logic_vector(rs1Integer, 6);
nrs2 <= conv_std_logic_vector(rs2Integer, 6);
nrd <= conv_std_logic_vector(rdInteger, 6);
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01:29:44 09/06/2013
-- Design Name:
-- Module Name: contador - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity contador is
end contador;
architecture Behavioral of contador is
begin
end Behavioral;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity nfa_finals_buckets_if is
generic(
MPMC_BASE_ADDRESS : std_logic_vector := X"00000000";
USER_DATA_WIDTH : integer := 32;
USER_ADDR_SHIFT : integer := 2 -- log2(byte_count_of_data_width)
);
port(
--///////////////////////////////////////////////////////////////////////////////
--// MPMC Port Interface - Bus is prefixed with NPI_
NPI_clk : in std_logic;
NPI_reset : in std_logic;
NPI_Addr : out std_logic_vector(31 downto 0);
NPI_AddrReq : out std_logic;
NPI_AddrAck : in std_logic;
NPI_RNW : out std_logic;
NPI_Size : out std_logic_vector(3 downto 0);
NPI_WrFIFO_Data : out std_logic_vector(63 downto 0);
NPI_WrFIFO_BE : out std_logic_vector(7 downto 0);
NPI_WrFIFO_Push : out std_logic;
NPI_RdFIFO_Data : in std_logic_vector(63 downto 0);
NPI_RdFIFO_Pop : out std_logic;
NPI_RdFIFO_RdWdAddr : in std_logic_vector(3 downto 0);
NPI_WrFIFO_Empty : in std_logic;
NPI_WrFIFO_AlmostFull : in std_logic;
NPI_WrFIFO_Flush : out std_logic;
NPI_RdFIFO_Empty : in std_logic;
NPI_RdFIFO_Flush : out std_logic;
NPI_RdFIFO_Latency : in std_logic_vector(1 downto 0);
NPI_RdModWr : out std_logic;
NPI_InitDone : in std_logic;
-- signals from user logic
ap_clk : in std_logic;
ap_reset : in std_logic;
USER_RdData : out std_logic_vector(USER_DATA_WIDTH - 1 downto 0); -- Bus read data to user_logic
USER_WrData : in std_logic_vector(USER_DATA_WIDTH - 1 downto 0); -- Bus write data
USER_address : in std_logic_vector(31 downto 0); -- word offset from BASE_ADDRESS
USER_size : in std_logic_vector(31 downto 0); -- burst size of word
USER_req_nRW : in std_logic; -- req type 0: Read, 1: write
USER_req_full_n : out std_logic; -- req Fifo full
USER_req_push : in std_logic; -- req Fifo push (new request in)
USER_rsp_empty_n: out std_logic; -- return data FIFO empty
USER_rsp_pop : in std_logic -- return data FIFO pop
);
end entity;
architecture arch_nfa_finals_buckets_if OF nfa_finals_buckets_if IS
component nfa_finals_buckets_if_async_fifo is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 3;
DEPTH : integer := 8);
port (
clk_w : IN STD_LOGIC;
clk_r : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC);
end component;
component nfa_finals_buckets_if_ap_fifo is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 3;
DEPTH : integer := 8);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC);
end component;
component nfa_finals_buckets_if_ap_fifo_af is
generic (
DATA_WIDTH : integer := 64;
ADDR_WIDTH : integer := 6;
DEPTH : integer := 64;
ALMOST_FULL_MARGIN : integer := 2);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC);
end component;
constant C_PI_ADDR_WIDTH : integer := 32;
constant C_PI_DATA_WIDTH : integer := 64;
constant C_PI_BE_WIDTH : integer := 8;
constant C_PI_RDWDADDR_WIDTH: integer := 4;
constant RSW : integer := 7; -- req size width
constant REQ_FIFO_DATA_WIDTH : integer := 1+32+RSW+USER_DATA_WIDTH; -- nRW+addr+size+wr_data
constant REQ_FIFO_ADDR_WIDTH : integer := 3;
constant REQ_FIFO_DEPTH : integer := 8;
type req_state_type is (RESET, FETCH_REQ, REQ, WD_SINGLE, WD_BURST1, WD_BURST2, WD_BURST_REQ);
signal req_cs, req_ns : req_state_type;
type rdata_state_type is (RESET, IDLE, RDATA);
signal rdata_cs, rdata_ns : rdata_state_type;
-- User interface
signal User_size_local : STD_LOGIC_VECTOR(RSW-1 downto 0);
signal User_address_local : STD_LOGIC_VECTOR(31 downto 0);
-- request FIFO
signal req_fifo_empty_n : STD_LOGIC;
signal req_fifo_pop : STD_LOGIC;
signal req_fifo_dout : STD_LOGIC_VECTOR(REQ_FIFO_DATA_WIDTH - 1 downto 0);
signal req_fifo_full_n : STD_LOGIC;
signal req_fifo_push : STD_LOGIC;
signal req_fifo_din : STD_LOGIC_VECTOR(REQ_FIFO_DATA_WIDTH - 1 downto 0);
signal req_fifo_dout_req_nRW : STD_LOGIC;
signal req_fifo_dout_req_address : STD_LOGIC_VECTOR(31 downto 0);
signal req_fifo_dout_req_size : STD_LOGIC_VECTOR(RSW-1 downto 0);
signal req_fifo_dout_wr_data : STD_LOGIC_VECTOR(USER_DATA_WIDTH-1 downto 0);
signal req_reg_en : STD_LOGIC;
signal nRW_reg : STD_LOGIC;
signal address_reg : STD_LOGIC_VECTOR(31 downto 0);
signal size_reg : STD_LOGIC_VECTOR(RSW-1 downto 0);
-- internal request information
signal req_nRW : STD_LOGIC;
signal req_address : STD_LOGIC_VECTOR(31 downto 0);
signal req_size : STD_LOGIC_VECTOR(RSW-1 downto 0);
signal req_BE : STD_LOGIC_VECTOR(C_PI_BE_WIDTH-1 downto 0);
signal req_WrData_low : STD_LOGIC_VECTOR(USER_DATA_WIDTH-1 downto 0);
signal req_WrData_wdAddr : STD_LOGIC;
signal req_WrData_reg_en : STD_LOGIC;
signal req_WrData_push : STD_LOGIC;
signal req_WrData_BE : STD_LOGIC_VECTOR(C_PI_BE_WIDTH-1 downto 0);
signal req_valid : STD_LOGIC;
-- burst write
signal burst_write_reg_en : STD_LOGIC;
signal burst_write_count : STD_LOGIC_VECTOR(5 downto 0); -- max 32 * 64 bits
-- burst read
signal burst_read_reg_en : STD_LOGIC;
signal burst_read_count : STD_LOGIC_VECTOR(RSW-1 downto 0);
signal burst_read_wdAddr : STD_LOGIC;
-- rsp FIFO
constant RSP_FIFO_DATA_WIDTH : integer := RSW + 1; -- req_size + addr(2)
constant RSP_FIFO_ADDR_WIDTH : integer := 2;
constant RSP_FIFO_DEPTH : integer := 4; -- MPMC limitation
signal rsp_fifo_empty_n : STD_LOGIC;
signal rsp_fifo_pop : STD_LOGIC;
signal rsp_fifo_dout : STD_LOGIC_VECTOR(RSP_FIFO_DATA_WIDTH-1 downto 0);
signal rsp_fifo_full_n : STD_LOGIC;
signal rsp_fifo_push : STD_LOGIC;
signal rsp_fifo_din : STD_LOGIC_VECTOR(RSP_FIFO_DATA_WIDTH-1 downto 0);
-- internal rdata pop logic
signal rdata_pop, rdata_pop_reg1, rdata_pop_reg2: STD_LOGIC;
-- rd FIFO: input: MPMC data out, output: user async fifo
signal rd_fifo_empty_n : STD_LOGIC;
signal rd_fifo_pop : STD_LOGIC;
signal rd_fifo_dout : STD_LOGIC_VECTOR(C_PI_DATA_WIDTH -1 downto 0);
signal rd_fifo_full_n : STD_LOGIC;
signal rd_fifo_push : STD_LOGIC;
signal rd_fifo_din : STD_LOGIC_VECTOR(C_PI_DATA_WIDTH -1 downto 0);
signal rd_fifo_dout_endian : STD_LOGIC_VECTOR(C_PI_DATA_WIDTH -1 downto 0);
-- rd user FIFO: async fifo to user
signal rd_user_fifo_empty_n : STD_LOGIC;
signal rd_user_fifo_pop : STD_LOGIC;
signal rd_user_fifo_dout : STD_LOGIC_VECTOR(USER_DATA_WIDTH -1 downto 0);
signal rd_user_fifo_full_n : STD_LOGIC;
signal rd_user_fifo_push : STD_LOGIC;
signal rd_user_fifo_din : STD_LOGIC_VECTOR(USER_DATA_WIDTH -1 downto 0);
begin
-- NPI interface
NPI_WrFIFO_Flush <= '0';
NPI_RdFIFO_Flush <= '0';
NPI_RdModWr <= '0';
NPI_AddrReq <= req_valid;
NPI_Addr <= address_reg;
NPI_RNW <= not nRW_reg;
NPI_WrFIFO_Push <= req_WrData_push;
NPI_WrFIFO_BE <= req_WrData_BE;
NPI_RdFIFO_Pop <= rdata_pop;
process (req_WrData_wdAddr, req_WrData_low, req_fifo_dout_wr_data)
begin
NPI_WrFIFO_Data <= (others => '0');
if (req_WrData_wdAddr = '0') then
NPI_WrFIFO_Data(C_PI_DATA_WIDTH-1 downto USER_DATA_WIDTH) <= req_fifo_dout_wr_data;
NPI_WrFIFO_Data(USER_DATA_WIDTH-1 downto 0) <= req_WrData_low;
else
NPI_WrFIFO_Data(C_PI_DATA_WIDTH-1 downto USER_DATA_WIDTH) <= req_WrData_low;
NPI_WrFIFO_Data(USER_DATA_WIDTH-1 downto 0) <= req_fifo_dout_wr_data;
end if;
end process;
process (size_reg)
begin
NPI_Size <= (others => '0');
if (size_reg = "0000100") then --4w
NPI_Size <= "0001";
elsif (size_reg = "0001000") then --8w
NPI_Size <= "0010";
elsif (size_reg = "0010000") then --16w
NPI_Size <= "0011";
elsif (size_reg = "0100000") then --32w
NPI_Size <= "0100";
elsif (size_reg = "1000000") then --64w
NPI_Size <= "0101";
end if;
end process;
-- User interface
USER_req_full_n <= req_fifo_full_n;
USER_rsp_empty_n <= rd_user_fifo_empty_n;
USER_RdData <= rd_user_fifo_dout;
rd_user_fifo_pop <= USER_rsp_pop;
USER_size_local <= User_size(RSW-1 downto 0) when
User_size(RSW-1 downto 0) /= CONV_STD_LOGIC_VECTOR(0,RSW) else CONV_STD_LOGIC_VECTOR(1,RSW);
USER_address_local(31 downto USER_ADDR_SHIFT) <= USER_address(31-USER_ADDR_SHIFT downto 0);
USER_address_local(USER_ADDR_SHIFT-1 downto 0) <= (others => '0');
-- reqest fifo logics
req_fifo_din(REQ_FIFO_DATA_WIDTH-1) <= USER_req_nRW;
req_fifo_din(REQ_FIFO_DATA_WIDTH-1-1 downto REQ_FIFO_DATA_WIDTH -1-32) <= USER_address_local+MPMC_BASE_ADDRESS;
req_fifo_din(REQ_FIFO_DATA_WIDTH-1-32-1 downto REQ_FIFO_DATA_WIDTH-1-32-RSW) <= USER_size_local(RSW-1 downto 0);
req_fifo_din(USER_DATA_WIDTH -1 downto 0) <= USER_WrData;
req_fifo_push <= USER_req_push;
U_nfa_finals_buckets_if_req_fifo: component nfa_finals_buckets_if_async_fifo
generic map(
DATA_WIDTH => REQ_FIFO_DATA_WIDTH,
ADDR_WIDTH => REQ_FIFO_ADDR_WIDTH,
DEPTH => REQ_FIFO_DEPTH)
port map(
clk_w => ap_clk,
clk_r => NPI_clk,
reset => NPI_reset,
if_empty_n => req_fifo_empty_n,
if_read => req_fifo_pop,
if_dout => req_fifo_dout,
if_full_n => req_fifo_full_n,
if_write => req_fifo_push,
if_din => req_fifo_din
);
req_fifo_dout_req_nRW <= req_fifo_dout(REQ_FIFO_DATA_WIDTH -1);
req_fifo_dout_req_address <= req_fifo_dout(REQ_FIFO_DATA_WIDTH-1-1 downto REQ_FIFO_DATA_WIDTH -1-32);
req_fifo_dout_req_size <= req_fifo_dout(REQ_FIFO_DATA_WIDTH-1-32-1 downto REQ_FIFO_DATA_WIDTH -1-32-RSW);
process(req_fifo_dout)
variable i,j: integer;
begin
-- change byte endian to big endian
for i in 0 to USER_DATA_WIDTH/8-1 loop
j := USER_DATA_WIDTH/8 -1 -i;
req_fifo_dout_wr_data(i*8+7 downto i*8) <= req_fifo_dout(j*8+7 downto j*8);
end loop;
end process;
p_req_fifo_out_reg: process (NPI_clk, NPI_reset)
variable i,j: integer;
begin
if (NPI_reset = '1') then
nRW_reg <= '0';
address_reg <= (others => '0');
size_reg <= (others => '0');
elsif (NPI_clk'event and NPI_clk = '1') then
if (req_reg_en = '1') then
nRW_reg <= req_fifo_dout_req_nRW;
address_reg <= req_fifo_dout_req_address;
size_reg <= req_fifo_dout_req_size;
end if;
end if;
end process;
-- write and burst write will be controlled by state machine due to MPMC limitation
-- read and burst read will have seperate return data phase logic for a pipelined access
p_state_trans: process (NPI_clk, NPI_reset)
begin
if (NPI_reset = '1') then
req_cs <= RESET;
elsif (NPI_clk'event and NPI_clk = '1') then
req_cs <= req_ns;
end if;
end process;
-- CAUTION: NPI_AddrAck is a combinational output of NPI_AddrReq
-- do not make NPI_AddrReq(req_valid) depends on NPI_AddrAck
p_state_output: process (req_cs, NPI_InitDone, req_fifo_empty_n, req_fifo_dout_req_nRW,
NPI_AddrAck, rsp_fifo_full_n, nRW_reg, size_reg, burst_write_count,
req_WrData_wdAddr, req_fifo_dout_req_size, NPI_WrFIFO_AlmostFull)
begin
req_ns <= FETCH_REQ;
req_reg_en <= '0';
req_fifo_pop <= '0';
rsp_fifo_push <= '0';
req_WrData_reg_en <= '0';
burst_write_reg_en <= '0';
req_valid <= '0';
req_WrData_push <= '0';
req_WrData_BE <= "11111111";
case req_cs is
when RESET =>
req_ns <= RESET;
if (NPI_InitDone = '1') then
req_ns <= FETCH_REQ;
end if;
when FETCH_REQ =>
req_ns <= FETCH_REQ;
if (req_fifo_empty_n = '1') then
if (req_fifo_dout_req_nRW = '1') then
req_reg_en <= '1';
req_ns <= REQ;
elsif (rsp_fifo_full_n = '1') then
req_reg_en <= '1';
req_fifo_pop <= '1';
rsp_fifo_push <= '1';
req_ns <= REQ;
end if;
end if;
when REQ =>
req_ns <= REQ;
if (nRW_reg = '0') then
req_valid <= '1';
if (NPI_AddrAck = '1') then
req_ns <= FETCH_REQ;
end if;
elsif (nRW_reg = '1' and size_reg = CONV_STD_LOGIC_VECTOR(1,RSW)) then
req_valid <= '1';
if (NPI_AddrAck = '1') then
req_WrData_reg_en <= '1';
req_ns <= WD_SINGLE;
end if;
elsif (nRW_reg = '1' and size_reg /= CONV_STD_LOGIC_VECTOR(1,RSW)) then
burst_write_reg_en <= '1';
req_ns <= WD_BURST1;
end if;
when WD_SINGLE =>
req_ns <= WD_SINGLE;
if (NPI_WrFIFO_AlmostFull = '0') then
req_WrData_push <= '1';
req_fifo_pop <= '1';
req_ns <= FETCH_REQ;
end if;
if (req_WrData_wdAddr = '0') then
req_WrData_BE <= "00001111";
else
req_WrData_BE <= "11110000";
end if;
when WD_BURST1 =>
req_ns <= WD_BURST1;
if (req_fifo_empty_n = '1') then
req_fifo_pop <= '1';
req_WrData_reg_en <= '1';
req_ns <= WD_BURST2;
end if;
when WD_BURST2 =>
req_ns <= WD_BURST2;
if (req_fifo_empty_n = '1' and NPI_WrFIFO_AlmostFull = '0') then
req_fifo_pop <= '1';
req_WrData_push <= '1';
if (burst_write_count /= "000001") then -- not last word
req_ns <= WD_BURST1;
else
req_ns <= WD_BURST_REQ;
end if;
end if;
when WD_BURST_REQ =>
req_ns <= WD_BURST_REQ;
req_valid <= '1';
if (NPI_AddrAck = '1') then
req_ns <= FETCH_REQ;
end if;
when others => null;
end case;
end process;
process (NPI_clk, NPI_reset)
begin
if (NPI_reset = '1') then
req_WrData_low <= (others =>'0');
req_WrData_wdAddr <= '0';
burst_write_count <= (others =>'0');
elsif (NPI_clk'event and NPI_clk = '1') then
if (req_WrData_reg_en = '1') then
req_WrData_low <= req_fifo_dout_wr_data;
req_WrData_wdAddr <= req_fifo_dout_req_address(2);
end if;
if (burst_write_reg_en = '1') then
burst_write_count <= req_fifo_dout_req_size(RSW-1 downto RSW-6);
elsif (req_WrData_push = '1') then
burst_write_count <= burst_write_count-1;
end if;
end if;
end process;
-- below is the response (read data) part
U_nfa_finals_buckets_if_rsp_fifo: component nfa_finals_buckets_if_ap_fifo
generic map(
DATA_WIDTH => RSP_FIFO_DATA_WIDTH,
ADDR_WIDTH => RSP_FIFO_ADDR_WIDTH,
DEPTH => RSP_FIFO_DEPTH)
port map(
clk => NPI_clk,
reset => NPI_reset,
if_empty_n => rsp_fifo_empty_n,
if_read => rsp_fifo_pop,
if_dout => rsp_fifo_dout,
if_full_n => rsp_fifo_full_n,
if_write => rsp_fifo_push,
if_din => rsp_fifo_din
);
rsp_fifo_din(RSP_FIFO_DATA_WIDTH-1 downto 1) <= req_fifo_dout_req_size;
rsp_fifo_din(0) <= req_fifo_dout_req_address(2);
rdata_pop <= (not NPI_RdFIFO_Empty) and rd_fifo_full_n;
process (NPI_clk, NPI_reset)
begin
if (NPI_reset = '1') then
rdata_pop_reg1 <= '0';
rdata_pop_reg2 <= '0';
elsif (NPI_clk'event and NPI_clk = '1') then
rdata_pop_reg1 <= rdata_pop;
rdata_pop_reg2 <= rdata_pop_reg1;
end if;
end process;
process (NPI_RdFIFO_Latency, rdata_pop, rdata_pop_reg1, rdata_pop_reg2)
begin
if (NPI_RdFIFO_Latency = "00") then
rd_fifo_push <= rdata_pop;
elsif (NPI_RdFIFO_Latency = "01") then
rd_fifo_push <= rdata_pop_reg1;
else
rd_fifo_push <= rdata_pop_reg2;
end if;
end process;
rd_fifo_din <= NPI_RdFIFO_Data;
-- 1. this fifo provide two 64w burst storage
-- 2. with almost full signal for MPMC has potential 2 latency from pop to data
-- 3. can't replace this fifo with asyn fifo which doesn't support almost_full
U_nfa_finals_buckets_if_rd_fifo: component nfa_finals_buckets_if_ap_fifo_af
generic map(
DATA_WIDTH => C_PI_DATA_WIDTH,
ADDR_WIDTH => 6,
DEPTH => 64,
ALMOST_FULL_MARGIN => 2)
port map(
clk => NPI_clk,
reset => NPI_reset,
if_empty_n => rd_fifo_empty_n,
if_read => rd_fifo_pop,
if_dout => rd_fifo_dout,
if_full_n => rd_fifo_full_n, -- this is almost_full signal
if_write => rd_fifo_push,
if_din => rd_fifo_din
);
process(rd_fifo_dout)
variable i,j : integer;
begin
-- change byte endian to big endian
for i in 0 to C_PI_BE_WIDTH-1 loop
j := C_PI_BE_WIDTH-1 -i;
rd_fifo_dout_endian(i*8+7 downto i*8) <= rd_fifo_dout(j*8+7 downto j*8);
end loop;
end process;
p_rdata_state_trans: process (NPI_clk, NPI_reset)
begin
if (NPI_reset = '1') then
rdata_cs <= RESET;
elsif (NPI_clk'event and NPI_clk = '1') then
rdata_cs <= rdata_ns;
end if;
end process;
p_rdata_ns_gen: process (rdata_cs, NPI_InitDone, rsp_fifo_empty_n, burst_read_count)
begin
rdata_ns <= RESET;
case rdata_cs is
when RESET =>
if (NPI_InitDone = '1') then
rdata_ns <= IDLE;
end if;
when IDLE =>
rdata_ns <= IDLE;
if (rsp_fifo_empty_n = '1') then
rdata_ns <= RDATA;
end if;
when RDATA =>
rdata_ns <= RDATA;
if (burst_read_count = CONV_STD_LOGIC_VECTOR(0,RSW)) then
rdata_ns <= IDLE;
end if;
when others => null;
end case;
end process;
p_rdata_state_output: process (rdata_cs, rsp_fifo_empty_n, burst_read_count,
rd_fifo_empty_n, rd_user_fifo_full_n)
begin
burst_read_reg_en <= '0';
rd_fifo_pop <= '0';
rd_user_fifo_push <= '0';
rsp_fifo_pop <= '0';
case rdata_cs is
when RESET => null;
when IDLE =>
if (rsp_fifo_empty_n = '1') then
burst_read_reg_en <= '1';
end if;
when RDATA =>
if (burst_read_count /= CONV_STD_LOGIC_VECTOR(0,RSW) and rd_fifo_empty_n = '1' and
rd_user_fifo_full_n = '1') then
if (burst_read_count(0) = '1') then
rd_fifo_pop <= '1';
end if;
rd_user_fifo_push <= '1';
end if;
if (burst_read_count = CONV_STD_LOGIC_VECTOR(0, RSW) ) then
rsp_fifo_pop <= '1';
end if;
when others => null;
end case;
end process;
process (NPI_clk, NPI_reset)
begin
if (NPI_reset = '1') then
burst_read_count <= (others =>'0');
elsif (NPI_clk'event and NPI_clk = '1') then
if (burst_read_reg_en = '1') then
burst_read_count <= rsp_fifo_dout(RSP_FIFO_DATA_WIDTH-1 downto RSP_FIFO_DATA_WIDTH-RSW);
burst_read_wdAddr <= rsp_fifo_dout(0);
elsif (rd_user_fifo_push = '1') then
burst_read_count <= burst_read_count -1;
burst_read_wdAddr <= not burst_read_wdAddr;
end if;
end if;
end process;
rd_user_fifo_din <= rd_fifo_dout_endian(USER_DATA_WIDTH-1 downto 0) when burst_read_wdAddr = '1' else
rd_fifo_dout_endian(C_PI_DATA_WIDTH-1 downto USER_DATA_WIDTH);
U_nfa_finals_buckets_if_rd_user_fifo: component nfa_finals_buckets_if_async_fifo
generic map(
DATA_WIDTH => USER_DATA_WIDTH,
ADDR_WIDTH => 3,
DEPTH => 8)
port map(
clk_w => NPI_clk,
clk_r => ap_clk,
reset => NPI_reset,
if_empty_n => rd_user_fifo_empty_n,
if_read => rd_user_fifo_pop,
if_dout => rd_user_fifo_dout,
if_full_n => rd_user_fifo_full_n,
if_write => rd_user_fifo_push,
if_din => rd_user_fifo_din
);
end arch_nfa_finals_buckets_if;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity nfa_finals_buckets_if is
generic(
MPMC_BASE_ADDRESS : std_logic_vector := X"00000000";
USER_DATA_WIDTH : integer := 32;
USER_ADDR_SHIFT : integer := 2 -- log2(byte_count_of_data_width)
);
port(
--///////////////////////////////////////////////////////////////////////////////
--// MPMC Port Interface - Bus is prefixed with NPI_
NPI_clk : in std_logic;
NPI_reset : in std_logic;
NPI_Addr : out std_logic_vector(31 downto 0);
NPI_AddrReq : out std_logic;
NPI_AddrAck : in std_logic;
NPI_RNW : out std_logic;
NPI_Size : out std_logic_vector(3 downto 0);
NPI_WrFIFO_Data : out std_logic_vector(63 downto 0);
NPI_WrFIFO_BE : out std_logic_vector(7 downto 0);
NPI_WrFIFO_Push : out std_logic;
NPI_RdFIFO_Data : in std_logic_vector(63 downto 0);
NPI_RdFIFO_Pop : out std_logic;
NPI_RdFIFO_RdWdAddr : in std_logic_vector(3 downto 0);
NPI_WrFIFO_Empty : in std_logic;
NPI_WrFIFO_AlmostFull : in std_logic;
NPI_WrFIFO_Flush : out std_logic;
NPI_RdFIFO_Empty : in std_logic;
NPI_RdFIFO_Flush : out std_logic;
NPI_RdFIFO_Latency : in std_logic_vector(1 downto 0);
NPI_RdModWr : out std_logic;
NPI_InitDone : in std_logic;
-- signals from user logic
ap_clk : in std_logic;
ap_reset : in std_logic;
USER_RdData : out std_logic_vector(USER_DATA_WIDTH - 1 downto 0); -- Bus read data to user_logic
USER_WrData : in std_logic_vector(USER_DATA_WIDTH - 1 downto 0); -- Bus write data
USER_address : in std_logic_vector(31 downto 0); -- word offset from BASE_ADDRESS
USER_size : in std_logic_vector(31 downto 0); -- burst size of word
USER_req_nRW : in std_logic; -- req type 0: Read, 1: write
USER_req_full_n : out std_logic; -- req Fifo full
USER_req_push : in std_logic; -- req Fifo push (new request in)
USER_rsp_empty_n: out std_logic; -- return data FIFO empty
USER_rsp_pop : in std_logic -- return data FIFO pop
);
end entity;
architecture arch_nfa_finals_buckets_if OF nfa_finals_buckets_if IS
component nfa_finals_buckets_if_async_fifo is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 3;
DEPTH : integer := 8);
port (
clk_w : IN STD_LOGIC;
clk_r : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC);
end component;
component nfa_finals_buckets_if_ap_fifo is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 3;
DEPTH : integer := 8);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC);
end component;
component nfa_finals_buckets_if_ap_fifo_af is
generic (
DATA_WIDTH : integer := 64;
ADDR_WIDTH : integer := 6;
DEPTH : integer := 64;
ALMOST_FULL_MARGIN : integer := 2);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC);
end component;
constant C_PI_ADDR_WIDTH : integer := 32;
constant C_PI_DATA_WIDTH : integer := 64;
constant C_PI_BE_WIDTH : integer := 8;
constant C_PI_RDWDADDR_WIDTH: integer := 4;
constant RSW : integer := 7; -- req size width
constant REQ_FIFO_DATA_WIDTH : integer := 1+32+RSW+USER_DATA_WIDTH; -- nRW+addr+size+wr_data
constant REQ_FIFO_ADDR_WIDTH : integer := 3;
constant REQ_FIFO_DEPTH : integer := 8;
type req_state_type is (RESET, FETCH_REQ, REQ, WD_SINGLE, WD_BURST1, WD_BURST2, WD_BURST_REQ);
signal req_cs, req_ns : req_state_type;
type rdata_state_type is (RESET, IDLE, RDATA);
signal rdata_cs, rdata_ns : rdata_state_type;
-- User interface
signal User_size_local : STD_LOGIC_VECTOR(RSW-1 downto 0);
signal User_address_local : STD_LOGIC_VECTOR(31 downto 0);
-- request FIFO
signal req_fifo_empty_n : STD_LOGIC;
signal req_fifo_pop : STD_LOGIC;
signal req_fifo_dout : STD_LOGIC_VECTOR(REQ_FIFO_DATA_WIDTH - 1 downto 0);
signal req_fifo_full_n : STD_LOGIC;
signal req_fifo_push : STD_LOGIC;
signal req_fifo_din : STD_LOGIC_VECTOR(REQ_FIFO_DATA_WIDTH - 1 downto 0);
signal req_fifo_dout_req_nRW : STD_LOGIC;
signal req_fifo_dout_req_address : STD_LOGIC_VECTOR(31 downto 0);
signal req_fifo_dout_req_size : STD_LOGIC_VECTOR(RSW-1 downto 0);
signal req_fifo_dout_wr_data : STD_LOGIC_VECTOR(USER_DATA_WIDTH-1 downto 0);
signal req_reg_en : STD_LOGIC;
signal nRW_reg : STD_LOGIC;
signal address_reg : STD_LOGIC_VECTOR(31 downto 0);
signal size_reg : STD_LOGIC_VECTOR(RSW-1 downto 0);
-- internal request information
signal req_nRW : STD_LOGIC;
signal req_address : STD_LOGIC_VECTOR(31 downto 0);
signal req_size : STD_LOGIC_VECTOR(RSW-1 downto 0);
signal req_BE : STD_LOGIC_VECTOR(C_PI_BE_WIDTH-1 downto 0);
signal req_WrData_low : STD_LOGIC_VECTOR(USER_DATA_WIDTH-1 downto 0);
signal req_WrData_wdAddr : STD_LOGIC;
signal req_WrData_reg_en : STD_LOGIC;
signal req_WrData_push : STD_LOGIC;
signal req_WrData_BE : STD_LOGIC_VECTOR(C_PI_BE_WIDTH-1 downto 0);
signal req_valid : STD_LOGIC;
-- burst write
signal burst_write_reg_en : STD_LOGIC;
signal burst_write_count : STD_LOGIC_VECTOR(5 downto 0); -- max 32 * 64 bits
-- burst read
signal burst_read_reg_en : STD_LOGIC;
signal burst_read_count : STD_LOGIC_VECTOR(RSW-1 downto 0);
signal burst_read_wdAddr : STD_LOGIC;
-- rsp FIFO
constant RSP_FIFO_DATA_WIDTH : integer := RSW + 1; -- req_size + addr(2)
constant RSP_FIFO_ADDR_WIDTH : integer := 2;
constant RSP_FIFO_DEPTH : integer := 4; -- MPMC limitation
signal rsp_fifo_empty_n : STD_LOGIC;
signal rsp_fifo_pop : STD_LOGIC;
signal rsp_fifo_dout : STD_LOGIC_VECTOR(RSP_FIFO_DATA_WIDTH-1 downto 0);
signal rsp_fifo_full_n : STD_LOGIC;
signal rsp_fifo_push : STD_LOGIC;
signal rsp_fifo_din : STD_LOGIC_VECTOR(RSP_FIFO_DATA_WIDTH-1 downto 0);
-- internal rdata pop logic
signal rdata_pop, rdata_pop_reg1, rdata_pop_reg2: STD_LOGIC;
-- rd FIFO: input: MPMC data out, output: user async fifo
signal rd_fifo_empty_n : STD_LOGIC;
signal rd_fifo_pop : STD_LOGIC;
signal rd_fifo_dout : STD_LOGIC_VECTOR(C_PI_DATA_WIDTH -1 downto 0);
signal rd_fifo_full_n : STD_LOGIC;
signal rd_fifo_push : STD_LOGIC;
signal rd_fifo_din : STD_LOGIC_VECTOR(C_PI_DATA_WIDTH -1 downto 0);
signal rd_fifo_dout_endian : STD_LOGIC_VECTOR(C_PI_DATA_WIDTH -1 downto 0);
-- rd user FIFO: async fifo to user
signal rd_user_fifo_empty_n : STD_LOGIC;
signal rd_user_fifo_pop : STD_LOGIC;
signal rd_user_fifo_dout : STD_LOGIC_VECTOR(USER_DATA_WIDTH -1 downto 0);
signal rd_user_fifo_full_n : STD_LOGIC;
signal rd_user_fifo_push : STD_LOGIC;
signal rd_user_fifo_din : STD_LOGIC_VECTOR(USER_DATA_WIDTH -1 downto 0);
begin
-- NPI interface
NPI_WrFIFO_Flush <= '0';
NPI_RdFIFO_Flush <= '0';
NPI_RdModWr <= '0';
NPI_AddrReq <= req_valid;
NPI_Addr <= address_reg;
NPI_RNW <= not nRW_reg;
NPI_WrFIFO_Push <= req_WrData_push;
NPI_WrFIFO_BE <= req_WrData_BE;
NPI_RdFIFO_Pop <= rdata_pop;
process (req_WrData_wdAddr, req_WrData_low, req_fifo_dout_wr_data)
begin
NPI_WrFIFO_Data <= (others => '0');
if (req_WrData_wdAddr = '0') then
NPI_WrFIFO_Data(C_PI_DATA_WIDTH-1 downto USER_DATA_WIDTH) <= req_fifo_dout_wr_data;
NPI_WrFIFO_Data(USER_DATA_WIDTH-1 downto 0) <= req_WrData_low;
else
NPI_WrFIFO_Data(C_PI_DATA_WIDTH-1 downto USER_DATA_WIDTH) <= req_WrData_low;
NPI_WrFIFO_Data(USER_DATA_WIDTH-1 downto 0) <= req_fifo_dout_wr_data;
end if;
end process;
process (size_reg)
begin
NPI_Size <= (others => '0');
if (size_reg = "0000100") then --4w
NPI_Size <= "0001";
elsif (size_reg = "0001000") then --8w
NPI_Size <= "0010";
elsif (size_reg = "0010000") then --16w
NPI_Size <= "0011";
elsif (size_reg = "0100000") then --32w
NPI_Size <= "0100";
elsif (size_reg = "1000000") then --64w
NPI_Size <= "0101";
end if;
end process;
-- User interface
USER_req_full_n <= req_fifo_full_n;
USER_rsp_empty_n <= rd_user_fifo_empty_n;
USER_RdData <= rd_user_fifo_dout;
rd_user_fifo_pop <= USER_rsp_pop;
USER_size_local <= User_size(RSW-1 downto 0) when
User_size(RSW-1 downto 0) /= CONV_STD_LOGIC_VECTOR(0,RSW) else CONV_STD_LOGIC_VECTOR(1,RSW);
USER_address_local(31 downto USER_ADDR_SHIFT) <= USER_address(31-USER_ADDR_SHIFT downto 0);
USER_address_local(USER_ADDR_SHIFT-1 downto 0) <= (others => '0');
-- reqest fifo logics
req_fifo_din(REQ_FIFO_DATA_WIDTH-1) <= USER_req_nRW;
req_fifo_din(REQ_FIFO_DATA_WIDTH-1-1 downto REQ_FIFO_DATA_WIDTH -1-32) <= USER_address_local+MPMC_BASE_ADDRESS;
req_fifo_din(REQ_FIFO_DATA_WIDTH-1-32-1 downto REQ_FIFO_DATA_WIDTH-1-32-RSW) <= USER_size_local(RSW-1 downto 0);
req_fifo_din(USER_DATA_WIDTH -1 downto 0) <= USER_WrData;
req_fifo_push <= USER_req_push;
U_nfa_finals_buckets_if_req_fifo: component nfa_finals_buckets_if_async_fifo
generic map(
DATA_WIDTH => REQ_FIFO_DATA_WIDTH,
ADDR_WIDTH => REQ_FIFO_ADDR_WIDTH,
DEPTH => REQ_FIFO_DEPTH)
port map(
clk_w => ap_clk,
clk_r => NPI_clk,
reset => NPI_reset,
if_empty_n => req_fifo_empty_n,
if_read => req_fifo_pop,
if_dout => req_fifo_dout,
if_full_n => req_fifo_full_n,
if_write => req_fifo_push,
if_din => req_fifo_din
);
req_fifo_dout_req_nRW <= req_fifo_dout(REQ_FIFO_DATA_WIDTH -1);
req_fifo_dout_req_address <= req_fifo_dout(REQ_FIFO_DATA_WIDTH-1-1 downto REQ_FIFO_DATA_WIDTH -1-32);
req_fifo_dout_req_size <= req_fifo_dout(REQ_FIFO_DATA_WIDTH-1-32-1 downto REQ_FIFO_DATA_WIDTH -1-32-RSW);
process(req_fifo_dout)
variable i,j: integer;
begin
-- change byte endian to big endian
for i in 0 to USER_DATA_WIDTH/8-1 loop
j := USER_DATA_WIDTH/8 -1 -i;
req_fifo_dout_wr_data(i*8+7 downto i*8) <= req_fifo_dout(j*8+7 downto j*8);
end loop;
end process;
p_req_fifo_out_reg: process (NPI_clk, NPI_reset)
variable i,j: integer;
begin
if (NPI_reset = '1') then
nRW_reg <= '0';
address_reg <= (others => '0');
size_reg <= (others => '0');
elsif (NPI_clk'event and NPI_clk = '1') then
if (req_reg_en = '1') then
nRW_reg <= req_fifo_dout_req_nRW;
address_reg <= req_fifo_dout_req_address;
size_reg <= req_fifo_dout_req_size;
end if;
end if;
end process;
-- write and burst write will be controlled by state machine due to MPMC limitation
-- read and burst read will have seperate return data phase logic for a pipelined access
p_state_trans: process (NPI_clk, NPI_reset)
begin
if (NPI_reset = '1') then
req_cs <= RESET;
elsif (NPI_clk'event and NPI_clk = '1') then
req_cs <= req_ns;
end if;
end process;
-- CAUTION: NPI_AddrAck is a combinational output of NPI_AddrReq
-- do not make NPI_AddrReq(req_valid) depends on NPI_AddrAck
p_state_output: process (req_cs, NPI_InitDone, req_fifo_empty_n, req_fifo_dout_req_nRW,
NPI_AddrAck, rsp_fifo_full_n, nRW_reg, size_reg, burst_write_count,
req_WrData_wdAddr, req_fifo_dout_req_size, NPI_WrFIFO_AlmostFull)
begin
req_ns <= FETCH_REQ;
req_reg_en <= '0';
req_fifo_pop <= '0';
rsp_fifo_push <= '0';
req_WrData_reg_en <= '0';
burst_write_reg_en <= '0';
req_valid <= '0';
req_WrData_push <= '0';
req_WrData_BE <= "11111111";
case req_cs is
when RESET =>
req_ns <= RESET;
if (NPI_InitDone = '1') then
req_ns <= FETCH_REQ;
end if;
when FETCH_REQ =>
req_ns <= FETCH_REQ;
if (req_fifo_empty_n = '1') then
if (req_fifo_dout_req_nRW = '1') then
req_reg_en <= '1';
req_ns <= REQ;
elsif (rsp_fifo_full_n = '1') then
req_reg_en <= '1';
req_fifo_pop <= '1';
rsp_fifo_push <= '1';
req_ns <= REQ;
end if;
end if;
when REQ =>
req_ns <= REQ;
if (nRW_reg = '0') then
req_valid <= '1';
if (NPI_AddrAck = '1') then
req_ns <= FETCH_REQ;
end if;
elsif (nRW_reg = '1' and size_reg = CONV_STD_LOGIC_VECTOR(1,RSW)) then
req_valid <= '1';
if (NPI_AddrAck = '1') then
req_WrData_reg_en <= '1';
req_ns <= WD_SINGLE;
end if;
elsif (nRW_reg = '1' and size_reg /= CONV_STD_LOGIC_VECTOR(1,RSW)) then
burst_write_reg_en <= '1';
req_ns <= WD_BURST1;
end if;
when WD_SINGLE =>
req_ns <= WD_SINGLE;
if (NPI_WrFIFO_AlmostFull = '0') then
req_WrData_push <= '1';
req_fifo_pop <= '1';
req_ns <= FETCH_REQ;
end if;
if (req_WrData_wdAddr = '0') then
req_WrData_BE <= "00001111";
else
req_WrData_BE <= "11110000";
end if;
when WD_BURST1 =>
req_ns <= WD_BURST1;
if (req_fifo_empty_n = '1') then
req_fifo_pop <= '1';
req_WrData_reg_en <= '1';
req_ns <= WD_BURST2;
end if;
when WD_BURST2 =>
req_ns <= WD_BURST2;
if (req_fifo_empty_n = '1' and NPI_WrFIFO_AlmostFull = '0') then
req_fifo_pop <= '1';
req_WrData_push <= '1';
if (burst_write_count /= "000001") then -- not last word
req_ns <= WD_BURST1;
else
req_ns <= WD_BURST_REQ;
end if;
end if;
when WD_BURST_REQ =>
req_ns <= WD_BURST_REQ;
req_valid <= '1';
if (NPI_AddrAck = '1') then
req_ns <= FETCH_REQ;
end if;
when others => null;
end case;
end process;
process (NPI_clk, NPI_reset)
begin
if (NPI_reset = '1') then
req_WrData_low <= (others =>'0');
req_WrData_wdAddr <= '0';
burst_write_count <= (others =>'0');
elsif (NPI_clk'event and NPI_clk = '1') then
if (req_WrData_reg_en = '1') then
req_WrData_low <= req_fifo_dout_wr_data;
req_WrData_wdAddr <= req_fifo_dout_req_address(2);
end if;
if (burst_write_reg_en = '1') then
burst_write_count <= req_fifo_dout_req_size(RSW-1 downto RSW-6);
elsif (req_WrData_push = '1') then
burst_write_count <= burst_write_count-1;
end if;
end if;
end process;
-- below is the response (read data) part
U_nfa_finals_buckets_if_rsp_fifo: component nfa_finals_buckets_if_ap_fifo
generic map(
DATA_WIDTH => RSP_FIFO_DATA_WIDTH,
ADDR_WIDTH => RSP_FIFO_ADDR_WIDTH,
DEPTH => RSP_FIFO_DEPTH)
port map(
clk => NPI_clk,
reset => NPI_reset,
if_empty_n => rsp_fifo_empty_n,
if_read => rsp_fifo_pop,
if_dout => rsp_fifo_dout,
if_full_n => rsp_fifo_full_n,
if_write => rsp_fifo_push,
if_din => rsp_fifo_din
);
rsp_fifo_din(RSP_FIFO_DATA_WIDTH-1 downto 1) <= req_fifo_dout_req_size;
rsp_fifo_din(0) <= req_fifo_dout_req_address(2);
rdata_pop <= (not NPI_RdFIFO_Empty) and rd_fifo_full_n;
process (NPI_clk, NPI_reset)
begin
if (NPI_reset = '1') then
rdata_pop_reg1 <= '0';
rdata_pop_reg2 <= '0';
elsif (NPI_clk'event and NPI_clk = '1') then
rdata_pop_reg1 <= rdata_pop;
rdata_pop_reg2 <= rdata_pop_reg1;
end if;
end process;
process (NPI_RdFIFO_Latency, rdata_pop, rdata_pop_reg1, rdata_pop_reg2)
begin
if (NPI_RdFIFO_Latency = "00") then
rd_fifo_push <= rdata_pop;
elsif (NPI_RdFIFO_Latency = "01") then
rd_fifo_push <= rdata_pop_reg1;
else
rd_fifo_push <= rdata_pop_reg2;
end if;
end process;
rd_fifo_din <= NPI_RdFIFO_Data;
-- 1. this fifo provide two 64w burst storage
-- 2. with almost full signal for MPMC has potential 2 latency from pop to data
-- 3. can't replace this fifo with asyn fifo which doesn't support almost_full
U_nfa_finals_buckets_if_rd_fifo: component nfa_finals_buckets_if_ap_fifo_af
generic map(
DATA_WIDTH => C_PI_DATA_WIDTH,
ADDR_WIDTH => 6,
DEPTH => 64,
ALMOST_FULL_MARGIN => 2)
port map(
clk => NPI_clk,
reset => NPI_reset,
if_empty_n => rd_fifo_empty_n,
if_read => rd_fifo_pop,
if_dout => rd_fifo_dout,
if_full_n => rd_fifo_full_n, -- this is almost_full signal
if_write => rd_fifo_push,
if_din => rd_fifo_din
);
process(rd_fifo_dout)
variable i,j : integer;
begin
-- change byte endian to big endian
for i in 0 to C_PI_BE_WIDTH-1 loop
j := C_PI_BE_WIDTH-1 -i;
rd_fifo_dout_endian(i*8+7 downto i*8) <= rd_fifo_dout(j*8+7 downto j*8);
end loop;
end process;
p_rdata_state_trans: process (NPI_clk, NPI_reset)
begin
if (NPI_reset = '1') then
rdata_cs <= RESET;
elsif (NPI_clk'event and NPI_clk = '1') then
rdata_cs <= rdata_ns;
end if;
end process;
p_rdata_ns_gen: process (rdata_cs, NPI_InitDone, rsp_fifo_empty_n, burst_read_count)
begin
rdata_ns <= RESET;
case rdata_cs is
when RESET =>
if (NPI_InitDone = '1') then
rdata_ns <= IDLE;
end if;
when IDLE =>
rdata_ns <= IDLE;
if (rsp_fifo_empty_n = '1') then
rdata_ns <= RDATA;
end if;
when RDATA =>
rdata_ns <= RDATA;
if (burst_read_count = CONV_STD_LOGIC_VECTOR(0,RSW)) then
rdata_ns <= IDLE;
end if;
when others => null;
end case;
end process;
p_rdata_state_output: process (rdata_cs, rsp_fifo_empty_n, burst_read_count,
rd_fifo_empty_n, rd_user_fifo_full_n)
begin
burst_read_reg_en <= '0';
rd_fifo_pop <= '0';
rd_user_fifo_push <= '0';
rsp_fifo_pop <= '0';
case rdata_cs is
when RESET => null;
when IDLE =>
if (rsp_fifo_empty_n = '1') then
burst_read_reg_en <= '1';
end if;
when RDATA =>
if (burst_read_count /= CONV_STD_LOGIC_VECTOR(0,RSW) and rd_fifo_empty_n = '1' and
rd_user_fifo_full_n = '1') then
if (burst_read_count(0) = '1') then
rd_fifo_pop <= '1';
end if;
rd_user_fifo_push <= '1';
end if;
if (burst_read_count = CONV_STD_LOGIC_VECTOR(0, RSW) ) then
rsp_fifo_pop <= '1';
end if;
when others => null;
end case;
end process;
process (NPI_clk, NPI_reset)
begin
if (NPI_reset = '1') then
burst_read_count <= (others =>'0');
elsif (NPI_clk'event and NPI_clk = '1') then
if (burst_read_reg_en = '1') then
burst_read_count <= rsp_fifo_dout(RSP_FIFO_DATA_WIDTH-1 downto RSP_FIFO_DATA_WIDTH-RSW);
burst_read_wdAddr <= rsp_fifo_dout(0);
elsif (rd_user_fifo_push = '1') then
burst_read_count <= burst_read_count -1;
burst_read_wdAddr <= not burst_read_wdAddr;
end if;
end if;
end process;
rd_user_fifo_din <= rd_fifo_dout_endian(USER_DATA_WIDTH-1 downto 0) when burst_read_wdAddr = '1' else
rd_fifo_dout_endian(C_PI_DATA_WIDTH-1 downto USER_DATA_WIDTH);
U_nfa_finals_buckets_if_rd_user_fifo: component nfa_finals_buckets_if_async_fifo
generic map(
DATA_WIDTH => USER_DATA_WIDTH,
ADDR_WIDTH => 3,
DEPTH => 8)
port map(
clk_w => NPI_clk,
clk_r => ap_clk,
reset => NPI_reset,
if_empty_n => rd_user_fifo_empty_n,
if_read => rd_user_fifo_pop,
if_dout => rd_user_fifo_dout,
if_full_n => rd_user_fifo_full_n,
if_write => rd_user_fifo_push,
if_din => rd_user_fifo_din
);
end arch_nfa_finals_buckets_if;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Tue Oct 31 12:11:23 2017
-- Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode synth_stub -rename_top dbg_ila -prefix
-- dbg_ila_ dbg_ila_stub.vhdl
-- Design : dbg_ila
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k325tffg676-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity dbg_ila is
Port (
clk : in STD_LOGIC;
probe0 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe1 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe2 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe3 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe4 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe5 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe6 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe7 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe8 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe9 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe10 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe11 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe12 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe13 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe14 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe15 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe16 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe17 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe18 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe19 : in STD_LOGIC_VECTOR ( 8 downto 0 );
probe20 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe21 : in STD_LOGIC_VECTOR ( 2 downto 0 );
probe22 : in STD_LOGIC_VECTOR ( 2 downto 0 );
probe23 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe24 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe25 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe26 : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end dbg_ila;
architecture stub of dbg_ila is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,probe0[63:0],probe1[63:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[63:0],probe8[0:0],probe9[0:0],probe10[0:0],probe11[0:0],probe12[63:0],probe13[0:0],probe14[0:0],probe15[0:0],probe16[0:0],probe17[0:0],probe18[0:0],probe19[8:0],probe20[7:0],probe21[2:0],probe22[2:0],probe23[0:0],probe24[0:0],probe25[7:0],probe26[3:0]";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2016.3";
begin
end;
|
architecture rtl of fifo is
begin
process
begin
var1 := '0' when (rd_en = '1') else'1';
var2 := '0' when (rd_en = '1') else '1';
wr_en_a <= force '0' when (rd_en = '1') else'1';
wr_en_b <= force '0' when (rd_en = '1') else '1';
end process;
concurrent_wr_en_a <= '0' when (rd_en = '1') else'1';
concurrent_wr_en_b <= '0' when (rd_en = '1') else '1';
end architecture rtl;
|
architecture rtl of fifo is
begin
process
begin
var1 := '0' when (rd_en = '1') else'1';
var2 := '0' when (rd_en = '1') else '1';
wr_en_a <= force '0' when (rd_en = '1') else'1';
wr_en_b <= force '0' when (rd_en = '1') else '1';
end process;
concurrent_wr_en_a <= '0' when (rd_en = '1') else'1';
concurrent_wr_en_b <= '0' when (rd_en = '1') else '1';
end architecture rtl;
|
---------------------------------------------------------------------------------------------------
-- PICO 1802 Tiny BASIC - GPIO module
---------------------------------------------------------------------------------------------------
-- 2 x 8-bit general purpose IO ports
-- Each port bit independently configurable as an input or output via the data direction regsiter
-- Occupies 16 bytes of contiguous memory
-- Full read / write access to data direction and port registers
-- Seperatate locations to set, reset or toggle data direction and port register bits
-- Reset leaves all bits configured as input
---------------------------------------------------------------------------------------------------
-- This file is part of the PICO 1802 Tiny BASIC Project
-- Copyright 2016, Steve Teal: [email protected]
--
-- This source file may be used and distributed without restriction provided that this copyright
-- statement is not removed from the file and that any derivative work contains the original
-- copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it and/or modify it under the terms
-- of the GNU Lesser General Public License as published by the Free Software Foundation,
-- either version 3 of the License, or (at your option) any later version.
--
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-3.0.en.html
---------------------------------------------------------------------------------------------------
-- Steve Teal, Northamptonshire, United Kingdom
---------------------------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
entity gpio is
port(
-- Processor interface
clock: in std_logic; -- Global clock
reset_n: in std_logic; -- Active low reset
data_in: in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0);
address: in std_logic_vector(3 downto 0);
rd_n: in std_logic;
wr_n: in std_logic;
cs_n: in std_logic;
-- GPIO Ports (for connection to the outside world)
pa: inout std_logic_vector(7 downto 0);
pb: inout std_logic_vector(7 downto 0));
end gpio;
architecture rtl of gpio is
signal porta : std_logic_vector(7 downto 0);
signal portb : std_logic_vector(7 downto 0);
signal ddra : std_logic_vector(7 downto 0);
signal ddrb : std_logic_vector(7 downto 0);
signal pina : std_logic_vector(7 downto 0);
signal pinb : std_logic_vector(7 downto 0);
begin
gen_port: for i in 0 to 7 generate
pa(i) <= porta(i) when ddra(i) = '0' else 'Z';
pb(i) <= portb(i) when ddrb(i) = '0' else 'Z';
end generate gen_port;
process(clock)
begin
if(rising_edge(clock))then
if(reset_n = '0')then
porta <= X"00";
portb <= X"00";
ddra <= X"FF";
ddrb <= X"FF";
elsif(wr_n = '0' and cs_n = '0')then
case address is
when "0000" => porta <= data_in;
when "0001" => porta <= data_in or porta;
when "0010" => porta <= (not data_in) and porta;
when "0011" => porta <= data_in xor porta;
when "0100" => ddra <= data_in;
when "0101" => ddra <= data_in or ddra;
when "0110" => ddra <= (not data_in) and ddra;
when "0111" => ddra <= data_in xor ddra;
when "1000" => portb <= data_in;
when "1001" => portb <= data_in or portb;
when "1010" => portb <= (not data_in) and portb;
when "1011" => portb <= data_in xor portb;
when "1100" => ddrb <= data_in;
when "1101" => ddrb <= data_in or ddrb;
when "1110" => ddrb <= (not data_in) and ddrb;
when "1111" => ddrb <= data_in xor ddrb;
when others => null;
end case;
end if;
end if;
end process;
process(address,pina,pinb,ddra,ddrb,rd_n,cs_n)
begin
if(rd_n = '0' and cs_n = '0')then
case address(3 downto 2) is
when "00" => data_out <= pina;
when "01" => data_out <= ddra;
when "10" => data_out <= pinb;
when "11" => data_out <= ddrb;
when others => data_out <= X"00";
end case;
else
data_out <= X"00";
end if;
end process;
process(clock)
begin
if(rising_edge(clock))then
pina <= pa;
pinb <= pb;
end if;
end process;
end rtl; |
-- author: Antonio Gutierrez
-- date: 03/10/13
-- description: dff with clk and clear
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--------------------------------------
entity dff is
--generic declarations
port (
d1, d2, clk, rst, clr: in std_logic;
q1, q2: out std_logic);
end entity dff;
--------------------------------------
architecture flipflops of dff is
--signals and declarations
begin
---- DFF figure 6.1(c)
with_reset: process (clk, rst)
--declarativepart
begin
if (rst = '1') then
q1 <= '0';
elsif (clk'event and clk = '1') then
q1 <= d1;
end if;
end process with_reset;
---- DFF figure 6.1(e)
with_clear: process (clk)
--declarativepart
begin
if (clk'event and clk = '1') then
if (clr = '1') then
q2 <= '0';
else
q2 <= d2;
end if;
end if;
end process with_clear;
end architecture flipflops;
--------------------------------------
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;
USE ieee.std_logic_unsigned.ALL;
--NOTE: The following link is a very helpful reference:
--http://cseweb.ucsd.edu/~tweng/cse143/VHDLReference/aa.pdf
entity moore_seq_detect is
port (
x : IN STD_LOGIC;
clock : IN STD_LOGIC;
z : OUT STD_LOGIC
);
end;
architecture Behavioural of moore_seq_detect is
--declare state vars (this is basically enumerating
--a list of the possible values that a type of
--"state_type" may hold)
type state_type is (sr, s0, s1, s2, s3, s4, s5, s6);
--declare internal signals and their type. At any
--given time, each state could be defined as any of
--the states enumerated above (sr, s0, ... , s6).
--current state defaults to sr
signal current_state: state_type := sr;
signal next_state: state_type;
--count tells us how many times the sequence has been
--detected
signal count : std_logic_vector(3 downto 0) := "0000";
--z_internal serves as a snooper for the output z. let's us
--check value of z during clock process to appropriately
--update count variable.
signal z_internal : std_logic;
BEGIN
--be sure to map z_internal back to the actual output z.
z <= z_internal;
--combinatorial portion
proc_cruncher: process(current_state, x)
begin
case current_state is
when sr =>
z_internal <= '0';
if x = '0' then
next_state <= sr;
else
next_state <= s0;
end if;
when s0 =>
z_internal <= '0';
if x = '0' then
next_state <= s1;
else
next_state <= s0;
end if;
when s1 =>
z_internal <= '0';
if x = '0' then
next_state <= sr;
else
next_state <= s2;
end if;
when s2 =>
z_internal <= '0';
if x = '0' then
next_state <= s1;
else
next_state <= s3;
end if;
when s3 =>
z_internal <= '0';
if x = '0' then
next_state <= s4;
else
next_state <= s0;
end if;
when s4 =>
z_internal <= '0';
if x = '0' then
next_state <= s5;
else
next_state <= s2;
end if;
when s5 =>
z_internal <= '0';
if x = '0' then
next_state <= sr;
else
next_state <= s6;
end if;
when s6 =>
z_internal <= '1';
if x = '0' then
next_state <= s1;
else
next_state <= s0;
end if;
when others =>
next_state <= sr;
end case;
end process;
--sync'd portion
--using wait directive precludes need to pass clock to process directly.
--(I think)
proc_clock: process
begin
wait until clock'event and clock = '1';
--I tried simply updating count within the combinatorial block,
--but it always double counted. Here, we only ever increment
--on the positive edge of the clock, so there's no chance for
--double counting the same z=1 signal (the z=1 signal drops
--by the next clock cycle).
if ( z_internal = '1' ) then
count <= std_logic_vector(unsigned(count) + 1);
end if;
current_state <= next_state;
end process;
end Behavioural;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1130.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p04n01i01130ent IS
END c06s05b00x00p04n01i01130ent;
ARCHITECTURE c06s05b00x00p04n01i01130arch OF c06s05b00x00p04n01i01130ent IS
BEGIN
TESTING: PROCESS
type ENUM1 is (M1, M2, M3, M4, M5);
type ENUM2 is (N1, N2, N3, N4, N5);
type FIVE1 is range 1 to 5;
type FIVE2 is range 1 to 5;
type A1B is array (ENUM1 range <>) of BOOLEAN;
subtype A1 is A1B(ENUM1);
variable V1: A1 ;
constant FIVE2_2: FIVE2 := 2;
constant FIVE2_4: FIVE2 := 4;
BEGIN
V1(M2 to M4) := V1(M1 to N5);
-- SEMANTIC ERROR: DISCRETE RANGE INCOMPATIBLE WITH INDEX TYPE
assert FALSE
report "***FAILED TEST: c06s05b00x00p04n01i01130 - Discrete range incompatible with index type."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p04n01i01130arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1130.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p04n01i01130ent IS
END c06s05b00x00p04n01i01130ent;
ARCHITECTURE c06s05b00x00p04n01i01130arch OF c06s05b00x00p04n01i01130ent IS
BEGIN
TESTING: PROCESS
type ENUM1 is (M1, M2, M3, M4, M5);
type ENUM2 is (N1, N2, N3, N4, N5);
type FIVE1 is range 1 to 5;
type FIVE2 is range 1 to 5;
type A1B is array (ENUM1 range <>) of BOOLEAN;
subtype A1 is A1B(ENUM1);
variable V1: A1 ;
constant FIVE2_2: FIVE2 := 2;
constant FIVE2_4: FIVE2 := 4;
BEGIN
V1(M2 to M4) := V1(M1 to N5);
-- SEMANTIC ERROR: DISCRETE RANGE INCOMPATIBLE WITH INDEX TYPE
assert FALSE
report "***FAILED TEST: c06s05b00x00p04n01i01130 - Discrete range incompatible with index type."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p04n01i01130arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1130.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p04n01i01130ent IS
END c06s05b00x00p04n01i01130ent;
ARCHITECTURE c06s05b00x00p04n01i01130arch OF c06s05b00x00p04n01i01130ent IS
BEGIN
TESTING: PROCESS
type ENUM1 is (M1, M2, M3, M4, M5);
type ENUM2 is (N1, N2, N3, N4, N5);
type FIVE1 is range 1 to 5;
type FIVE2 is range 1 to 5;
type A1B is array (ENUM1 range <>) of BOOLEAN;
subtype A1 is A1B(ENUM1);
variable V1: A1 ;
constant FIVE2_2: FIVE2 := 2;
constant FIVE2_4: FIVE2 := 4;
BEGIN
V1(M2 to M4) := V1(M1 to N5);
-- SEMANTIC ERROR: DISCRETE RANGE INCOMPATIBLE WITH INDEX TYPE
assert FALSE
report "***FAILED TEST: c06s05b00x00p04n01i01130 - Discrete range incompatible with index type."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p04n01i01130arch;
|
Subsets and Splits
No saved queries yet
Save your SQL queries to embed, download, and access them later. Queries will appear here once saved.