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----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Controller_Syndrome_Calculator_1
-- Module Name: Controller_Syndrome_Calculator_1
-- Project Name: McEliece Goppa Decoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The 1st step in Goppa Code Decoding.
--
-- This circuit is the state machine that controls the syndrome_calculator_1
--
-- Dependencies:
-- VHDL-93
--
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity controller_syndrome_calculator_1 is
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
limit_ctr_codeword_q : in STD_LOGIC;
limit_ctr_syndrome_q : in STD_LOGIC;
reg_first_syndrome_q : in STD_LOGIC_VECTOR(0 downto 0);
reg_codeword_q : in STD_LOGIC_VECTOR(0 downto 0);
syndrome_finalized : out STD_LOGIC;
write_enable_new_syndrome : out STD_LOGIC;
reg_L_ce : out STD_LOGIC;
square_h : out STD_LOGIC;
reg_h_ce : out STD_LOGIC;
sel_reg_h : out STD_LOGIC;
reg_syndrome_ce : out STD_LOGIC;
reg_syndrome_rst : out STD_LOGIC;
reg_codeword_ce : out STD_LOGIC;
reg_first_syndrome_ce : out STD_LOGIC;
reg_first_syndrome_rst : out STD_LOGIC;
ctr_syndrome_ce : out STD_LOGIC;
ctr_syndrome_rst : out STD_LOGIC;
ctr_codeword_ce : out STD_LOGIC;
ctr_codeword_rst : out STD_LOGIC
);
end controller_syndrome_calculator_1;
architecture Behavioral of controller_syndrome_calculator_1 is
type State is (reset, load_counters, prepare_values, load_values, jump_codeword, prepare_synd, load_synd, store_synd, final);
signal actual_state, next_state : State;
begin
Clock: process (clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
actual_state <= reset;
else
actual_state <= next_state;
end if;
end if;
end process;
Output: process (actual_state, limit_ctr_codeword_q, limit_ctr_syndrome_q, reg_first_syndrome_q, reg_codeword_q)
begin
case (actual_state) is
when reset =>
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
reg_L_ce <= '0';
square_h <= '0';
reg_h_ce <= '0';
sel_reg_h <= '0';
reg_syndrome_ce <= '0';
reg_syndrome_rst <= '1';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '1';
ctr_syndrome_ce <= '0';
ctr_syndrome_rst <= '1';
ctr_codeword_ce <= '0';
ctr_codeword_rst <= '1';
when load_counters =>
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
reg_L_ce <= '0';
square_h <= '0';
reg_h_ce <= '0';
sel_reg_h <= '0';
reg_syndrome_ce <= '0';
reg_syndrome_rst <= '1';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '1';
ctr_syndrome_ce <= '0';
ctr_syndrome_rst <= '1';
ctr_codeword_ce <= '0';
ctr_codeword_rst <= '1';
when prepare_values =>
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
reg_L_ce <= '0';
square_h <= '0';
square_h <= '0';
reg_h_ce <= '0';
sel_reg_h <= '0';
reg_syndrome_ce <= '0';
reg_syndrome_rst <= '0';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_syndrome_ce <= '0';
ctr_syndrome_rst <= '0';
ctr_codeword_ce <= '0';
ctr_codeword_rst <= '0';
when load_values =>
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
reg_L_ce <= '1';
square_h <= '0';
reg_h_ce <= '1';
sel_reg_h <= '0';
reg_syndrome_ce <= '1';
reg_syndrome_rst <= '0';
reg_codeword_ce <= '1';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_syndrome_ce <= '0';
ctr_syndrome_rst <= '0';
ctr_codeword_ce <= '0';
ctr_codeword_rst <= '0';
when jump_codeword =>
if(reg_codeword_q(0) = '1') then
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
reg_L_ce <= '0';
square_h <= '1';
reg_h_ce <= '1';
sel_reg_h <= '1';
reg_syndrome_ce <= '0';
reg_syndrome_rst <= '0';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_syndrome_ce <= '0';
ctr_syndrome_rst <= '1';
ctr_codeword_ce <= '0';
ctr_codeword_rst <= '0';
elsif(limit_ctr_codeword_q = '1') then
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
reg_L_ce <= '0';
square_h <= '1';
reg_h_ce <= '1';
sel_reg_h <= '1';
reg_syndrome_ce <= '0';
reg_syndrome_rst <= '0';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_syndrome_ce <= '0';
ctr_syndrome_rst <= '0';
ctr_codeword_ce <= '0';
ctr_codeword_rst <= '0';
else
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
reg_L_ce <= '0';
square_h <= '1';
reg_h_ce <= '1';
sel_reg_h <= '1';
reg_syndrome_ce <= '0';
reg_syndrome_rst <= '0';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_syndrome_ce <= '0';
ctr_syndrome_rst <= '0';
ctr_codeword_ce <= '1';
ctr_codeword_rst <= '0';
end if;
when prepare_synd =>
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
reg_L_ce <= '0';
square_h <= '0';
reg_h_ce <= '0';
sel_reg_h <= '1';
reg_syndrome_ce <= '0';
reg_syndrome_rst <= '0';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_syndrome_ce <= '0';
ctr_syndrome_rst <= '0';
ctr_codeword_ce <= '0';
ctr_codeword_rst <= '0';
when load_synd =>
if(reg_first_syndrome_q(0) = '1') then
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
reg_L_ce <= '0';
square_h <= '0';
reg_h_ce <= '0';
sel_reg_h <= '1';
reg_syndrome_ce <= '0';
reg_syndrome_rst <= '1';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_syndrome_ce <= '0';
ctr_syndrome_rst <= '0';
ctr_codeword_ce <= '0';
ctr_codeword_rst <= '0';
else
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
reg_L_ce <= '0';
square_h <= '0';
reg_h_ce <= '0';
sel_reg_h <= '1';
reg_syndrome_ce <= '1';
reg_syndrome_rst <= '0';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_syndrome_ce <= '0';
ctr_syndrome_rst <= '0';
ctr_codeword_ce <= '0';
ctr_codeword_rst <= '0';
end if;
when store_synd =>
if(limit_ctr_syndrome_q = '1') then
syndrome_finalized <= '0';
write_enable_new_syndrome <= '1';
reg_L_ce <= '0';
square_h <= '0';
reg_h_ce <= '1';
sel_reg_h <= '1';
reg_syndrome_ce <= '0';
reg_syndrome_rst <= '0';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '1';
reg_first_syndrome_rst <= '0';
ctr_syndrome_ce <= '0';
ctr_syndrome_rst <= '1';
ctr_codeword_ce <= '1';
ctr_codeword_rst <= '0';
else
syndrome_finalized <= '0';
write_enable_new_syndrome <= '1';
reg_L_ce <= '0';
square_h <= '0';
reg_h_ce <= '1';
sel_reg_h <= '1';
reg_syndrome_ce <= '0';
reg_syndrome_rst <= '0';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '0';
ctr_syndrome_ce <= '1';
ctr_syndrome_rst <= '0';
ctr_codeword_ce <= '0';
ctr_codeword_rst <= '0';
end if;
when final =>
syndrome_finalized <= '1';
write_enable_new_syndrome <= '0';
reg_L_ce <= '0';
square_h <= '0';
reg_h_ce <= '0';
sel_reg_h <= '0';
reg_syndrome_ce <= '0';
reg_syndrome_rst <= '1';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '1';
ctr_syndrome_ce <= '0';
ctr_syndrome_rst <= '1';
ctr_codeword_ce <= '0';
ctr_codeword_rst <= '1';
when others =>
syndrome_finalized <= '0';
write_enable_new_syndrome <= '0';
reg_L_ce <= '0';
square_h <= '0';
reg_h_ce <= '0';
sel_reg_h <= '0';
reg_syndrome_ce <= '0';
reg_syndrome_rst <= '1';
reg_codeword_ce <= '0';
reg_first_syndrome_ce <= '0';
reg_first_syndrome_rst <= '1';
ctr_syndrome_ce <= '0';
ctr_syndrome_rst <= '1';
ctr_codeword_ce <= '0';
ctr_codeword_rst <= '1';
end case;
end process;
NewState: process (actual_state, limit_ctr_codeword_q, limit_ctr_syndrome_q, reg_first_syndrome_q, reg_codeword_q)
begin
case (actual_state) is
when reset =>
next_state <= load_counters;
when load_counters =>
next_state <= prepare_values;
when prepare_values =>
next_state <= load_values;
when load_values =>
next_state <= jump_codeword;
when jump_codeword =>
if(reg_codeword_q(0) = '1') then
next_state <= prepare_synd;
elsif(limit_ctr_codeword_q = '1') then
next_state <= final;
else
next_state <= prepare_values;
end if;
when prepare_synd =>
next_state <= load_synd;
when load_synd =>
next_state <= store_synd;
when store_synd =>
if(limit_ctr_syndrome_q = '1') then
if(limit_ctr_codeword_q = '1') then
next_state <= final;
else
next_state <= prepare_values;
end if;
else
next_state <= prepare_synd;
end if;
when final =>
next_state <= final;
when others =>
next_state <= reset;
end case;
end process;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MUX_RF_DWR is
Port (
data_dm : in STD_LOGIC_VECTOR (31 downto 0);
alurs : in STD_LOGIC_VECTOR (31 downto 0);
pc : in STD_LOGIC_VECTOR (31 downto 0);
rf_src : in STD_LOGIC_VECTOR (1 downto 0);
rf_data : out STD_LOGIC_VECTOR (31 downto 0)
);
end MUX_RF_DWR;
architecture Behavioral of MUX_RF_DWR is
begin
process(data_dm,alurs,pc,rf_src)
begin
case rf_src is
when "00" =>
rf_data <= data_dm;
when "01" =>
rf_data <= alurs;
when "10" =>
rf_data <= pc;
when others =>
rf_data <= (others =>'0');
end case;
end process;
end Behavioral; |
-------------------------------------------------------------------------------
-- axi_datamover_wrdata_cntl.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_wrdata_cntl.vhd
--
-- Description:
-- This file implements the DataMover Master Write Data Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_9;
use axi_datamover_v5_1_9.axi_datamover_fifo;
use axi_datamover_v5_1_9.axi_datamover_strb_gen2;
-------------------------------------------------------------------------------
entity axi_datamover_wrdata_cntl is
generic (
C_REALIGNER_INCLUDED : Integer range 0 to 1 := 0;
-- Indicates the Data Realignment function is included (external
-- to this module)
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Indicates the INDET BTT function is included (external
-- to this module)
C_SF_BYTES_RCVD_WIDTH : Integer range 1 to 23 := 1;
-- Sets the width of the data2wsc_bytes_rcvd port used for
-- relaying the actual number of bytes received when Idet BTT is
-- enabled (C_ENABLE_INDET_BTT = 1)
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS bits of the transfer address that
-- are being used to Demux write data to a wider AXI4 Write
-- Data Bus
C_DATA_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 4;
-- Sets the depth of the internal command fifo used for the
-- command queue
C_MMAP_DWIDTH : Integer range 32 to 1024 := 32;
-- Indicates the native data width of the Read Data port
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Stream output data port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Indicates the width of the Tag field of the input command
C_FAMILY : String := "virtex7"
-- Indicates the device family of the target FPGA
);
port (
-- Clock and Reset inputs ----------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
------------------------------------------------------------------------
-- Soft Shutdown internal interface ------------------------------------
--
rst2data_stop_request : in std_logic; --
-- Active high soft stop request to modules --
--
data2addr_stop_req : Out std_logic; --
-- Active high signal requesting the Address Controller --
-- to stop posting commands to the AXI Read Address Channel --
--
data2rst_stop_cmplt : Out std_logic; --
-- Active high indication that the Data Controller has completed --
-- any pending transfers committed by the Address Controller --
-- after a stop has been requested by the Reset module. --
------------------------------------------------------------------------
-- Store and Forward support signals for external User logic ------------
--
wr_xfer_cmplt : Out std_logic; --
-- Active high indication that the Data Controller has completed --
-- a single write data transfer on the AXI4 Write Data Channel. --
-- This signal is escentially echos the assertion of wlast sent --
-- to the AXI4. --
--
s2mm_ld_nxt_len : out std_logic; --
-- Active high pulse indicating a new xfer length has been queued --
-- to the WDC Cmd FIFO --
--
s2mm_wr_len : out std_logic_vector(7 downto 0); --
-- Bus indicating the AXI LEN value associated with the xfer command --
-- loaded into the WDC Command FIFO. --
-------------------------------------------------------------------------
-- AXI Write Data Channel Skid buffer I/O ---------------------------------------
--
data2skid_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- Write DATA output to skid buffer --
--
data2skid_wdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- Write DATA output to skid buffer --
--
data2skid_wstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- Write DATA output to skid buffer --
--
data2skid_wlast : Out std_logic; --
-- Write LAST output to skid buffer --
--
data2skid_wvalid : Out std_logic; --
-- Write VALID output to skid buffer --
--
skid2data_wready : In std_logic; --
-- Write READY input from skid buffer --
----------------------------------------------------------------------------------
-- AXI Slave Stream In -----------------------------------------------------------
--
s2mm_strm_wvalid : In std_logic; --
-- AXI Stream VALID input --
--
s2mm_strm_wready : Out Std_logic; --
-- AXI Stream READY Output --
--
s2mm_strm_wdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data input --
--
s2mm_strm_wstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB input --
--
s2mm_strm_wlast : In std_logic; --
-- AXI Stream LAST input --
----------------------------------------------------------------------------------
-- Stream input sideband signal from Indeterminate BTT and/or DRE ----------------
--
s2mm_strm_eop : In std_logic; --
-- Stream End of Packet marker input. This is only used when Indeterminate --
-- BTT mode is enable. Otherwise it is ignored --
--
--
s2mm_stbs_asserted : in std_logic_vector(7 downto 0); --
-- Indicates the number of asserted WSTRB bits for the --
-- associated input stream data beat --
--
--
-- Realigner Underrun/overrun error flag used in non Indeterminate BTT --
-- Mode --
realign2wdc_eop_error : In std_logic ; --
-- Asserted active high and will only clear with reset. It is only used --
-- when Indeterminate BTT is not enabled and the Realigner Module is --
-- instantiated upstream from the WDC. The Realigner will detect overrun --
-- underrun conditions and will will relay these conditions via this signal. --
----------------------------------------------------------------------------------
-- Command Calculator Interface --------------------------------------------------
--
mstr2data_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the write strb --
-- demux (only used if Stream data width is less than the MMap Dwidth). --
--
mstr2data_len : In std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the first stream data beat --
--
mstr2data_last_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the last stream --
-- data beat --
--
mstr2data_drr : In std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : In std_logic; --
-- The endiing tranfer of a sequence of transfers --
--
mstr2data_sequential : In std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : In std_logic; --
-- The final child tranfer of a parent command fetched from --
-- the Command FIFO (not necessarily an EOF command) --
--
mstr2data_cmd_valid : In std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : Out std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
----------------------------------------------------------------------------------
-- Address Controller Interface --------------------------------------------------
--
addr2data_addr_posted : In std_logic ; --
-- Indication from the Address Channel Controller to the --
-- Data Controller that an address has been posted to the --
-- AXI Address Channel --
--
--
data2addr_data_rdy : out std_logic; --
-- Indication that the Data Channel is ready to send the first --
-- databeat of the next command on the write data channel. --
-- This is used for the "wait for data" feature which keeps the --
-- address controller from issuing a transfer request until the --
-- corresponding data valid is asserted on the stream input. The --
-- WDC will continue to assert the output until an assertion on --
-- the addr2data_addr_posted is received. --
---------------------------------------------------------------------------------
-- Premature TLAST assertion error flag ------------------------------------------
--
data2all_tlast_error : Out std_logic; --
-- When asserted, this indicates the data controller detected --
-- a premature TLAST assertion on the incoming data stream. --
---------------------------------------------------------------------------------
-- Data Controller Halted Status -------------------------------------------------
--
data2all_dcntlr_halted : Out std_logic; --
-- When asserted, this indicates the data controller has satisfied --
-- all pending transfers queued by the Address Controller and is halted. --
----------------------------------------------------------------------------------
-- Input Stream Skid Buffer Halt control -----------------------------------------
--
data2skid_halt : Out std_logic; --
-- The data controller asserts this output for 1 primary clock period --
-- The pulse commands the MM2S Stream skid buffer to tun off outputs --
-- at the next tlast transmission. --
----------------------------------------------------------------------------------
-- Write Status Controller Interface ---------------------------------------------
--
data2wsc_tag : Out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The command tag --
--
data2wsc_calc_err : Out std_logic ; --
-- Indication that the current command out from the Cntl FIFO --
-- has a calculation error --
--
data2wsc_last_err : Out std_logic ; --
-- Indication that the current write transfer encountered a premature --
-- TLAST assertion on the incoming Stream Channel --
--
data2wsc_cmd_cmplt : Out std_logic ; --
-- Indication by the Data Channel Controller that the --
-- corresponding status is the last status for a command --
-- pulled from the command FIFO --
--
wsc2data_ready : in std_logic; --
-- Input from the Write Status Module indicating that the --
-- Status Reg/FIFO is ready to accept data --
--
data2wsc_valid : Out std_logic; --
-- Output to the Command/Status Module indicating that the --
-- Data Controller has valid tag and err indicators to write --
-- to the Status module --
--
data2wsc_eop : Out std_logic; --
-- Output to the Write Status Controller indicating that the --
-- associated command status also corresponds to a End of Packet --
-- marker for the input Stream. This is only used when Inderminate --
-- BTT is enabled in the S2MM. --
--
data2wsc_bytes_rcvd : Out std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0); --
-- Output to the Write Status Controller indicating the actual --
-- number of bytes received from the Stream input for the --
-- corresponding command status. This is only used when Inderminate --
-- BTT is enabled in the S2MM. --
--
wsc2mstr_halt_pipe : In std_logic --
-- Indication to Halt the Data and Address Command pipeline due --
-- to the Status FIFO going full or an internal error being logged --
----------------------------------------------------------------------------------
);
end entity axi_datamover_wrdata_cntl;
architecture implementation of axi_datamover_wrdata_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declaration ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_dbeat_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_dbeat_residue_width (bytes_per_beat : integer) return integer is
Variable temp_dbeat_residue_width : Integer := 0; -- 8-bit stream
begin
case bytes_per_beat is
when 128 => -- 1024 bits -- Added per Per CR616409
temp_dbeat_residue_width := 7; -- Added per Per CR616409
when 64 => -- 512 bits -- Added per Per CR616409
temp_dbeat_residue_width := 6; -- Added per Per CR616409
when 32 => -- 256 bits
temp_dbeat_residue_width := 5;
when 16 => -- 128 bits
temp_dbeat_residue_width := 4;
when 8 => -- 64 bits
temp_dbeat_residue_width := 3;
when 4 => -- 32 bits
temp_dbeat_residue_width := 2;
when 2 => -- 16 bits
temp_dbeat_residue_width := 1;
when others => -- assume 1-byte transfers
temp_dbeat_residue_width := 0;
end case;
Return (temp_dbeat_residue_width);
end function funct_get_dbeat_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_cnt_width
--
-- Function Description:
-- Sets a count width based on a fifo depth. A depth of 4 or less
-- is a special case which requires a minimum count width of 3 bits.
--
-------------------------------------------------------------------
function funct_set_cnt_width (fifo_depth : integer) return integer is
Variable temp_cnt_width : Integer := 4;
begin
if (fifo_depth <= 4) then
temp_cnt_width := 3;
elsif (fifo_depth <= 8) then
temp_cnt_width := 4;
elsif (fifo_depth <= 16) then
temp_cnt_width := 5;
elsif (fifo_depth <= 32) then
temp_cnt_width := 6;
else -- fifo depth <= 64
temp_cnt_width := 7;
end if;
Return (temp_cnt_width);
end function funct_set_cnt_width;
-- Constant Declarations --------------------------------------------
Constant STRM_STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant LEN_OF_ZERO : std_logic_vector(7 downto 0) := (others => '0');
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant SADDR_LSB_WIDTH : integer := C_SEL_ADDR_WIDTH;
Constant LEN_WIDTH : integer := 8;
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant DRR_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant CMD_CMPLT_WIDTH : integer := 1;
Constant SEQUENTIAL_WIDTH : integer := 1;
Constant DCTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
SADDR_LSB_WIDTH + -- LS Address field width
LEN_WIDTH + -- LEN field
STRB_WIDTH + -- Starting Strobe field
STRB_WIDTH + -- Ending Strobe field
DRR_WIDTH + -- DRE Re-alignment Request Flag Field
EOF_WIDTH + -- EOF flag field
SEQUENTIAL_WIDTH + -- Sequential command flag
CMD_CMPLT_WIDTH + -- Command Complete Flag
CALC_ERR_WIDTH; -- Calc error flag
Constant TAG_STRT_INDEX : integer := 0;
Constant SADDR_LSB_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant LEN_STRT_INDEX : integer := SADDR_LSB_STRT_INDEX + SADDR_LSB_WIDTH;
Constant STRT_STRB_STRT_INDEX : integer := LEN_STRT_INDEX + LEN_WIDTH;
Constant LAST_STRB_STRT_INDEX : integer := STRT_STRB_STRT_INDEX + STRB_WIDTH;
Constant DRR_STRT_INDEX : integer := LAST_STRB_STRT_INDEX + STRB_WIDTH;
Constant EOF_STRT_INDEX : integer := DRR_STRT_INDEX + DRR_WIDTH;
Constant SEQUENTIAL_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant CMD_CMPLT_STRT_INDEX : integer := SEQUENTIAL_STRT_INDEX+SEQUENTIAL_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := CMD_CMPLT_STRT_INDEX+CMD_CMPLT_WIDTH;
Constant ADDR_INCR_VALUE : integer := C_STREAM_DWIDTH/8;
Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_DATA_CNTL_FIFO_DEPTH);
Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '0');
Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH);
Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '1');
-- Signal Declarations --------------------------------------------
signal sig_get_next_dqual : std_logic := '0';
signal sig_last_mmap_dbeat : std_logic := '0';
signal sig_last_mmap_dbeat_reg : std_logic := '0';
signal sig_mmap2data_ready : std_logic := '0';
signal sig_data2mmap_valid : std_logic := '0';
signal sig_data2mmap_last : std_logic := '0';
signal sig_data2mmap_data : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_ld_new_cmd : std_logic := '0';
signal sig_ld_new_cmd_reg : std_logic := '0';
signal sig_cmd_cmplt_reg : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_lsb_reg : std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted : std_logic := '0';
signal sig_dqual_rdy : std_logic := '0';
signal sig_good_mmap_dbeat : std_logic := '0';
signal sig_first_dbeat : std_logic := '0';
signal sig_last_dbeat : std_logic := '0';
signal sig_single_dbeat : std_logic := '0';
signal sig_new_len_eq_0 : std_logic := '0';
signal sig_dbeat_cntr : unsigned(7 downto 0) := (others => '0');
Signal sig_dbeat_cntr_int : Integer range 0 to 255 := 0;
signal sig_dbeat_cntr_eq_0 : std_logic := '0';
signal sig_dbeat_cntr_eq_1 : std_logic := '0';
signal sig_wsc_ready : std_logic := '0';
signal sig_push_to_wsc : std_logic := '0';
signal sig_push_to_wsc_cmplt : std_logic := '0';
signal sig_set_push2wsc : std_logic := '0';
signal sig_data2wsc_tag : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2wsc_calc_err : std_logic := '0';
signal sig_data2wsc_last_err : std_logic := '0';
signal sig_data2wsc_cmd_cmplt : std_logic := '0';
signal sig_tlast_error : std_logic := '0';
signal sig_tlast_error_strbs : std_logic := '0';
signal sig_end_stbs_match_err : std_logic := '0';
signal sig_tlast_error_reg : std_logic := '0';
signal sig_cmd_is_eof : std_logic := '0';
signal sig_push_err2wsc : std_logic := '0';
signal sig_tlast_error_ovrrun : std_logic := '0';
signal sig_tlast_error_undrrun : std_logic := '0';
signal sig_next_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_eof_reg : std_logic := '0';
signal sig_next_sequential_reg : std_logic := '0';
signal sig_next_cmd_cmplt_reg : std_logic := '0';
signal sig_next_calc_error_reg : std_logic := '0';
signal sig_pop_dqual_reg : std_logic := '0';
signal sig_push_dqual_reg : std_logic := '0';
signal sig_dqual_reg_empty : std_logic := '0';
signal sig_dqual_reg_full : std_logic := '0';
signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted_cntr_eq_0 : std_logic := '0';
signal sig_addr_posted_cntr_max : std_logic := '0';
signal sig_decr_addr_posted_cntr : std_logic := '0';
signal sig_incr_addr_posted_cntr : std_logic := '0';
signal sig_addr_posted_cntr_eq_1 : std_logic := '0';
signal sig_apc_going2zero : std_logic := '0';
signal sig_aposted_cntr_ready : std_logic := '0';
signal sig_addr_chan_rdy : std_logic := '0';
Signal sig_no_posted_cmds : std_logic := '0';
signal sig_ls_addr_cntr : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_ls_addr_cntr : std_logic := '0';
signal sig_addr_incr_unsgnd : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
Signal sig_cmd_fifo_data_in : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0) := (others => '0');
Signal sig_cmd_fifo_data_out : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_tag : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_sadddr_lsb : std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_fifo_next_strt_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_last_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_drr : std_logic := '0';
signal sig_fifo_next_eof : std_logic := '0';
signal sig_fifo_next_cmd_cmplt : std_logic := '0';
signal sig_fifo_next_sequential : std_logic := '0';
signal sig_fifo_next_calc_error : std_logic := '0';
signal sig_cmd_fifo_empty : std_logic := '0';
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_sequential_push : std_logic := '0';
signal sig_clr_dqual_reg : std_logic := '0';
signal sig_tlast_err_stop : std_logic := '0';
signal sig_halt_reg : std_logic := '0';
signal sig_halt_reg_dly1 : std_logic := '0';
signal sig_halt_reg_dly2 : std_logic := '0';
signal sig_halt_reg_dly3 : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_stop_wvalid : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_s2mm_strm_wready : std_logic := '0';
signal sig_good_strm_dbeat : std_logic := '0';
signal sig_halt_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_sfhalt_next_strt_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_wfd_simult_clr_set : std_logic := '0';
signal sig_wr_xfer_cmplt : std_logic := '0';
signal sig_s2mm_ld_nxt_len : std_logic := '0';
signal sig_s2mm_wr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_spcl_push_err2wsc : std_logic := '0';
begin --(architecture implementation)
-- Command calculator handshake
data2mstr_cmd_ready <= sig_data2mstr_cmd_ready;
-- Write Data Channel Skid Buffer Port assignments
sig_mmap2data_ready <= skid2data_wready ;
data2skid_wvalid <= sig_data2mmap_valid ;
data2skid_wlast <= sig_data2mmap_last ;
data2skid_wdata <= sig_data2mmap_data ;
data2skid_saddr_lsb <= sig_addr_lsb_reg ;
-- AXI MM2S Stream Channel Port assignments
sig_data2mmap_data <= s2mm_strm_wdata ;
-- Premature TLAST assertion indication
data2all_tlast_error <= sig_tlast_error_reg ;
-- Stream Input Ready Handshake
s2mm_strm_wready <= sig_s2mm_strm_wready ;
sig_good_strm_dbeat <= s2mm_strm_wvalid and
sig_s2mm_strm_wready;
sig_data2mmap_last <= sig_dbeat_cntr_eq_0 and
sig_dqual_rdy;
-- Write Status Block interface signals
data2wsc_valid <= sig_push_to_wsc and
not(sig_tlast_err_stop) ; -- only allow 1 status write on TLAST errror
sig_wsc_ready <= wsc2data_ready ;
data2wsc_tag <= sig_data2wsc_tag ;
data2wsc_calc_err <= sig_data2wsc_calc_err ;
data2wsc_last_err <= sig_data2wsc_last_err ;
data2wsc_cmd_cmplt <= sig_data2wsc_cmd_cmplt ;
-- Address Channel Controller synchro pulse input
sig_addr_posted <= addr2data_addr_posted;
-- Request to halt the Address Channel Controller
data2addr_stop_req <= sig_halt_reg or
sig_tlast_error_reg;
-- Halted flag to the reset module
data2rst_stop_cmplt <= sig_data2rst_stop_cmplt;
-- Indicate the Write Data Controller is always ready
data2addr_data_rdy <= '1';
-- Write Transfer Completed Status output
wr_xfer_cmplt <= sig_wr_xfer_cmplt ;
-- New LEN value is being loaded
s2mm_ld_nxt_len <= sig_s2mm_ld_nxt_len;
-- The new LEN value
s2mm_wr_len <= sig_s2mm_wr_len;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_WR_CMPLT_FLAG
--
-- Process Description:
-- Implements the status flag indicating that a write data
-- transfer has completed. This is an echo of a wlast assertion
-- and a qualified data beat on the AXI4 Write Data Channel.
--
-------------------------------------------------------------
IMP_WR_CMPLT_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_wr_xfer_cmplt <= '0';
else
sig_wr_xfer_cmplt <= sig_data2mmap_last and
sig_good_strm_dbeat;
end if;
end if;
end process IMP_WR_CMPLT_FLAG;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Omits any Indeterminate BTT Support logic and includes
-- any error detection needed in Non Indeterminate BTT mode.
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
begin
sig_sfhalt_next_strt_strb <= sig_fifo_next_strt_strb;
-- Just housekeep the output port signals
data2wsc_eop <= '0';
data2wsc_bytes_rcvd <= (others => '0');
-- WRSTRB logic ------------------------------
-- Generate the Write Strobes for the MMap Write Data Channel
-- for the non Indeterminate BTT Case
data2skid_wstrb <= sig_strt_strb_reg
When (sig_first_dbeat = '1')
Else sig_last_strb_reg
When (sig_last_dbeat = '1')
Else (others => '1');
-- Generate the Stream Ready for the Stream input side
sig_s2mm_strm_wready <= sig_halt_reg or -- force tready if a halt requested
(sig_mmap2data_ready and
sig_addr_chan_rdy and -- This puts combinational logic in the stream WREADY path
sig_dqual_rdy and
not(sig_calc_error_reg) and
not(sig_tlast_error_reg)); -- Stop the stream channel at a overrun/underrun detection
-- MMap Write Data Channel Valid Handshaking
sig_data2mmap_valid <= (s2mm_strm_wvalid or
sig_tlast_error_reg or -- force valid if TLAST error
sig_halt_reg ) and -- force valid if halt requested
sig_addr_chan_rdy and -- xfers are commited on the address channel and
sig_dqual_rdy and -- there are commands in the command fifo
not(sig_calc_error_reg) and
not(sig_stop_wvalid); -- gate off wvalid immediately after a wlast for 1 clk
-- or when the soft shutdown has completed
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LOCAL_ERR_DETECT
--
-- If Generate Description:
-- Implements the local overrun and underrun detection when
-- the S2MM Realigner is not included.
--
--
------------------------------------------------------------
GEN_LOCAL_ERR_DETECT : if (C_REALIGNER_INCLUDED = 0) generate
begin
------- Input Stream TLAST assertion error -------------------------------
sig_tlast_error_ovrrun <= sig_cmd_is_eof and
sig_dbeat_cntr_eq_0 and
sig_good_mmap_dbeat and
not(s2mm_strm_wlast);
sig_tlast_error_undrrun <= s2mm_strm_wlast and
sig_good_mmap_dbeat and
(not(sig_dbeat_cntr_eq_0) or
not(sig_cmd_is_eof));
sig_end_stbs_match_err <= '1' -- Set flag if the calculated end strobe value
When ((s2mm_strm_wstrb /= sig_next_last_strb_reg) and -- does not match the received strobe value
(s2mm_strm_wlast = '1') and -- at TLAST assertion
(sig_good_mmap_dbeat = '1')) -- Qualified databeat
Else '0';
sig_tlast_error <= (sig_tlast_error_ovrrun or
sig_tlast_error_undrrun or
sig_end_stbs_match_err) and
not(sig_halt_reg); -- Suppress TLAST error when in soft shutdown
-- Just housekeep this when local TLAST error detection is used
sig_spcl_push_err2wsc <= '0';
end generate GEN_LOCAL_ERR_DETECT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_EXTERN_ERR_DETECT
--
-- If Generate Description:
-- Omits the local overrun and underrun detection and relies
-- on the S2MM Realigner for the detection.
--
------------------------------------------------------------
GEN_EXTERN_ERR_DETECT : if (C_REALIGNER_INCLUDED = 1) generate
begin
sig_tlast_error_undrrun <= '0'; -- not used here
sig_tlast_error_ovrrun <= '0'; -- not used here
sig_end_stbs_match_err <= '0'; -- not used here
sig_tlast_error <= realign2wdc_eop_error and -- External error detection asserted
not(sig_halt_reg); -- Suppress TLAST error when in soft shutdown
-- Special case for pushing error status when timing is such that no
-- addresses have been posted to AXI and a TLAST error has been detected
-- by the Realigner module and propagated in from the Stream input side.
sig_spcl_push_err2wsc <= sig_tlast_error_reg and
not(sig_tlast_err_stop) and
not(sig_addr_chan_rdy );
end generate GEN_EXTERN_ERR_DETECT;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERR_REG
--
-- Process Description:
-- Implements a sample and hold flop for the flag indicating
-- that the input Stream TLAST assertion was not at the expected
-- data beat relative to the commanded number of databeats
-- from the associated command from the SCC or PCC.
-------------------------------------------------------------
IMP_TLAST_ERR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_tlast_error_reg <= '0';
elsif (sig_tlast_error = '1') then
sig_tlast_error_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_TLAST_ERR_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERROR_STOP
--
-- Process Description:
-- Implements the flop to generate a stop flag once the TLAST
-- error condition has been relayed to the Write Status
-- Controller. This stop flag is used to prevent any more
-- pushes to the Write Status Controller.
--
-------------------------------------------------------------
IMP_TLAST_ERROR_STOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_tlast_err_stop <= '0';
elsif (sig_tlast_error_reg = '1' and
sig_push_to_wsc_cmplt = '1') then
sig_tlast_err_stop <= '1';
else
null; -- Hold State
end if;
end if;
end process IMP_TLAST_ERROR_STOP;
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INDET_BTT
--
-- If Generate Description:
-- Includes any Indeterminate BTT Support logic. Primarily
-- this is a counter for the input stream bytes received. The
-- received byte count is relayed to the Write Status Controller
-- for each parent command completed.
-- When a packet completion is indicated via the EOP marker
-- assertion, the status to the Write Status Controller also
-- indicates the EOP condition.
-- Note that underrun and overrun detection/error flagging
-- is disabled in Indeterminate BTT Mode.
--
------------------------------------------------------------
GEN_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
-- local constants
Constant BYTE_CNTR_WIDTH : integer := C_SF_BYTES_RCVD_WIDTH;
Constant NUM_ZEROS_WIDTH : integer := 8;
Constant BYTES_PER_DBEAT : integer := C_STREAM_DWIDTH/8;
Constant STRBGEN_ADDR_SLICE_WIDTH : integer :=
funct_get_dbeat_residue_width(BYTES_PER_DBEAT);
Constant STRBGEN_ADDR_0 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
-- local signals
signal lsig_byte_cntr : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_byte_cntr_incr_value : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_ld_byte_cntr : std_logic := '0';
signal lsig_incr_byte_cntr : std_logic := '0';
signal lsig_clr_byte_cntr : std_logic := '0';
signal lsig_end_of_cmd_reg : std_logic := '0';
signal lsig_eop_s_h_reg : std_logic := '0';
signal lsig_eop_reg : std_logic := '0';
signal sig_strbgen_addr : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_strbgen_bytes : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH downto 0) := (others => '0');
begin
-- Assign the outputs to the Write Status Controller
data2wsc_eop <= lsig_eop_reg and
not(sig_next_calc_error_reg);
data2wsc_bytes_rcvd <= STD_LOGIC_VECTOR(lsig_byte_cntr);
-- WRSTRB logic ------------------------------
--sig_strbgen_bytes <= (others => '1'); -- set to the max value
-- set the length to the max number of bytes per databeat
sig_strbgen_bytes <= STD_LOGIC_VECTOR(TO_UNSIGNED(BYTES_PER_DBEAT, STRBGEN_ADDR_SLICE_WIDTH+1));
sig_strbgen_addr <= STD_LOGIC_VECTOR(RESIZE(UNSIGNED(sig_fifo_next_sadddr_lsb),
STRBGEN_ADDR_SLICE_WIDTH)) ;
------------------------------------------------------------
-- Instance: I_STRT_STRB_GEN
--
-- Description:
-- Strobe generator used to generate the starting databeat
-- strobe value for soft shutdown case where the S2MM has to
-- flush out all of the transfers that have been committed
-- to the AXI Write address channel. Starting Strobes must
-- match the committed address offest for each transfer.
--
------------------------------------------------------------
I_STRT_STRB_GEN : entity axi_datamover_v5_1_9.axi_datamover_strb_gen2
generic map (
C_OP_MODE => 0 , -- 0 = Offset/Length mode
C_STRB_WIDTH => BYTES_PER_DBEAT ,
C_OFFSET_WIDTH => STRBGEN_ADDR_SLICE_WIDTH ,
C_NUM_BYTES_WIDTH => STRBGEN_ADDR_SLICE_WIDTH+1
)
port map (
start_addr_offset => sig_strbgen_addr ,
end_addr_offset => STRBGEN_ADDR_0 , -- not used in op mode 0
num_valid_bytes => sig_strbgen_bytes ,
strb_out => sig_sfhalt_next_strt_strb
);
-- Generate the WSTRB to use during soft shutdown
sig_halt_strb <= sig_strt_strb_reg
When (sig_first_dbeat = '1' or
sig_single_dbeat = '1')
Else (others => '1');
-- Generate the Write Strobes for the MMap Write Data Channel
-- for the Indeterminate BTT case. Strobes come from the Stream
-- input from the Indeterminate BTT module during normal operation.
-- However, during soft shutdown, those strobes become unpredictable
-- so generated strobes have to be used.
data2skid_wstrb <= sig_halt_strb
When (sig_halt_reg = '1')
Else s2mm_strm_wstrb;
-- Generate the Stream Ready for the Stream input side
sig_s2mm_strm_wready <= sig_halt_reg or -- force tready if a halt requested
(sig_mmap2data_ready and -- MMap is accepting the xfers
sig_addr_chan_rdy and -- xfers are commited on the address channel and
sig_dqual_rdy and -- there are commands in the command fifo
not(sig_calc_error_reg) and -- No internal error
not(sig_stop_wvalid)); -- Gate off stream ready immediately after a wlast for 1 clk
-- or when the soft shutdown has completed
-- MMap Write Data Channel Valid Handshaking
sig_data2mmap_valid <= (s2mm_strm_wvalid or -- Normal Stream input valid
sig_halt_reg ) and -- force valid if halt requested
sig_addr_chan_rdy and -- xfers are commited on the address channel and
sig_dqual_rdy and -- there are commands in the command fifo
not(sig_calc_error_reg) and -- No internal error
not(sig_stop_wvalid); -- Gate off wvalid immediately after a wlast for 1 clk
-- or when the soft shutdown has completed
-- TLAST Error housekeeping for Indeterminate BTT Mode
-- There is no Underrun/overrun in Stroe and Forward mode
sig_tlast_error_ovrrun <= '0'; -- Not used with Indeterminate BTT
sig_tlast_error_undrrun <= '0'; -- Not used with Indeterminate BTT
sig_end_stbs_match_err <= '0'; -- Not used with Indeterminate BTT
sig_tlast_error <= '0'; -- Not used with Indeterminate BTT
sig_tlast_error_reg <= '0'; -- Not used with Indeterminate BTT
sig_tlast_err_stop <= '0'; -- Not used with Indeterminate BTT
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOP_REG_FLOP
--
-- Process Description:
-- Register the End of Packet marker.
--
-------------------------------------------------------------
IMP_EOP_REG_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_end_of_cmd_reg <= '0';
lsig_eop_reg <= '0';
Elsif (sig_good_strm_dbeat = '1') Then
lsig_end_of_cmd_reg <= sig_next_cmd_cmplt_reg and
s2mm_strm_wlast;
lsig_eop_reg <= s2mm_strm_eop;
else
null; -- hold current state
end if;
end if;
end process IMP_EOP_REG_FLOP;
----- Byte Counter Logic -----------------------------------------------
-- The Byte counter reflects the actual byte count received on the
-- Stream input for each parent command loaded into the S2MM command
-- FIFO. Thus it counts input bytes until the command complete qualifier
-- is set and the TLAST input from the Stream input.
lsig_clr_byte_cntr <= lsig_end_of_cmd_reg and -- Clear if a new stream packet does not start
not(sig_good_strm_dbeat); -- immediately after the previous one finished.
lsig_ld_byte_cntr <= lsig_end_of_cmd_reg and -- Only load if a new stream packet starts
sig_good_strm_dbeat; -- immediately after the previous one finished.
lsig_incr_byte_cntr <= sig_good_strm_dbeat;
lsig_byte_cntr_incr_value <= RESIZE(UNSIGNED(s2mm_stbs_asserted),
BYTE_CNTR_WIDTH);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BYTE_CMTR
--
-- Process Description:
-- Keeps a running byte count per burst packet loaded into the
-- xfer FIFO. It is based on the strobes set on the incoming
-- Stream dbeat.
--
-------------------------------------------------------------
IMP_BYTE_CMTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
lsig_clr_byte_cntr = '1') then
lsig_byte_cntr <= (others => '0');
elsif (lsig_ld_byte_cntr = '1') then
lsig_byte_cntr <= lsig_byte_cntr_incr_value;
elsif (lsig_incr_byte_cntr = '1') then
lsig_byte_cntr <= lsig_byte_cntr + lsig_byte_cntr_incr_value;
else
null; -- hold current value
end if;
end if;
end process IMP_BYTE_CMTR;
end generate GEN_INDET_BTT;
-- Internal logic ------------------------------
sig_good_mmap_dbeat <= sig_mmap2data_ready and
sig_data2mmap_valid;
sig_last_mmap_dbeat <= sig_good_mmap_dbeat and
sig_data2mmap_last;
sig_get_next_dqual <= sig_last_mmap_dbeat;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_LAST_DBEAT
--
-- Process Description:
-- This implements a FLOP that creates a pulse
-- indicating the LAST signal for an outgoing write data channel
-- has been sent. Note that it is possible to have back to
-- back LAST databeats.
--
-------------------------------------------------------------
REG_LAST_DBEAT : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_last_mmap_dbeat_reg <= '0';
else
sig_last_mmap_dbeat_reg <= sig_last_mmap_dbeat;
end if;
end if;
end process REG_LAST_DBEAT;
----- Write Status Interface Stuff --------------------------
sig_push_to_wsc_cmplt <= sig_push_to_wsc and sig_wsc_ready;
sig_set_push2wsc <= (sig_good_mmap_dbeat and
sig_dbeat_cntr_eq_0) or
sig_push_err2wsc or
sig_spcl_push_err2wsc; -- Special case from CR616212
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_INTERR_PUSH_FLOP
--
-- Process Description:
-- Generate a 1 clock wide pulse when a calc error has propagated
-- from the Command Calculator. This pulse is used to force a
-- push of the error status to the Write Status Controller
-- without a AXI transfer completion.
--
-------------------------------------------------------------
IMP_INTERR_PUSH_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_push_err2wsc = '1') then
sig_push_err2wsc <= '0';
elsif (sig_ld_new_cmd_reg = '1' and
sig_calc_error_reg = '1') then
sig_push_err2wsc <= '1';
else
null; -- hold state
end if;
end if;
end process IMP_INTERR_PUSH_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PUSH2WSC_FLOP
--
-- Process Description:
-- Implements a Sample and hold register for the outbound status
-- signals to the Write Status Controller (WSC). This register
-- has to support back to back transfer completions.
--
-------------------------------------------------------------
IMP_PUSH2WSC_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(sig_push_to_wsc_cmplt = '1' and
sig_set_push2wsc = '0')) then
sig_push_to_wsc <= '0';
sig_data2wsc_tag <= (others => '0');
sig_data2wsc_calc_err <= '0';
sig_data2wsc_last_err <= '0';
sig_data2wsc_cmd_cmplt <= '0';
elsif (sig_set_push2wsc = '1' and
sig_tlast_err_stop = '0') then
sig_push_to_wsc <= '1';
sig_data2wsc_tag <= sig_tag_reg ;
sig_data2wsc_calc_err <= sig_calc_error_reg ;
sig_data2wsc_last_err <= sig_tlast_error_reg or
sig_tlast_error ;
sig_data2wsc_cmd_cmplt <= sig_cmd_cmplt_reg or
sig_tlast_error_reg or
sig_tlast_error ;
else
null; -- hold current state
end if;
end if;
end process IMP_PUSH2WSC_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_LD_NEW_CMD_REG
--
-- Process Description:
-- Registers the flag indicating a new command has been
-- loaded. Needs to be a 1 clk wide pulse.
--
-------------------------------------------------------------
IMP_LD_NEW_CMD_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_ld_new_cmd_reg = '1') then
sig_ld_new_cmd_reg <= '0';
else
sig_ld_new_cmd_reg <= sig_ld_new_cmd;
end if;
end if;
end process IMP_LD_NEW_CMD_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_NXT_LEN_REG
--
-- Process Description:
-- Registers the load control and length value for a command
-- passed to the WDC input command interface. The registered
-- signals are used for the external Indeterminate BTT support
-- ports.
--
-------------------------------------------------------------
IMP_NXT_LEN_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_s2mm_ld_nxt_len <= '0';
sig_s2mm_wr_len <= (others => '0');
else
sig_s2mm_ld_nxt_len <= mstr2data_cmd_valid and
sig_data2mstr_cmd_ready;
sig_s2mm_wr_len <= mstr2data_len;
end if;
end if;
end process IMP_NXT_LEN_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_DATA_CNTL_FIFO
--
-- If Generate Description:
-- Omits the input data control FIFO if the requested FIFO
-- depth is 1. The Data Qualifier Register serves as a
-- 1 deep FIFO by itself.
--
------------------------------------------------------------
GEN_NO_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH = 1) generate
begin
-- Command Calculator Handshake output
sig_data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_rd_cmd_valid <= mstr2data_cmd_valid ;
-- pre 13.1 sig_fifo_wr_cmd_ready <= sig_dqual_reg_empty and
-- pre 13.1 sig_aposted_cntr_ready and
-- pre 13.1 not(wsc2mstr_halt_pipe) and -- The Wr Status Controller is not stalling
-- pre 13.1 not(sig_calc_error_reg); -- the command execution pipe and there is
-- pre 13.1 -- no calculation error being propagated
sig_fifo_wr_cmd_ready <= sig_push_dqual_reg;
sig_fifo_next_tag <= mstr2data_tag ;
sig_fifo_next_sadddr_lsb <= mstr2data_saddr_lsb ;
sig_fifo_next_len <= mstr2data_len ;
sig_fifo_next_strt_strb <= mstr2data_strt_strb ;
sig_fifo_next_last_strb <= mstr2data_last_strb ;
sig_fifo_next_drr <= mstr2data_drr ;
sig_fifo_next_eof <= mstr2data_eof ;
sig_fifo_next_sequential <= mstr2data_sequential ;
sig_fifo_next_cmd_cmplt <= mstr2data_cmd_cmplt ;
sig_fifo_next_calc_error <= mstr2data_calc_error ;
end generate GEN_NO_DATA_CNTL_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_DATA_CNTL_FIFO
--
-- If Generate Description:
-- Includes the input data control FIFO if the requested
-- FIFO depth is more than 1.
--
------------------------------------------------------------
GEN_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH > 1) generate
begin
-- Command Calculator Handshake output
sig_data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_wr_cmd_valid <= mstr2data_cmd_valid ;
-- pop the fifo when dqual reg is pushed
sig_fifo_rd_cmd_ready <= sig_push_dqual_reg;
-- Format the input fifo data word
sig_cmd_fifo_data_in <= mstr2data_calc_error &
mstr2data_cmd_cmplt &
mstr2data_sequential &
mstr2data_eof &
mstr2data_drr &
mstr2data_last_strb &
mstr2data_strt_strb &
mstr2data_len &
mstr2data_saddr_lsb &
mstr2data_tag ;
-- Rip the output fifo data word
sig_fifo_next_tag <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto
TAG_STRT_INDEX);
sig_fifo_next_sadddr_lsb <= sig_cmd_fifo_data_out((SADDR_LSB_STRT_INDEX+SADDR_LSB_WIDTH)-1 downto
SADDR_LSB_STRT_INDEX);
sig_fifo_next_len <= sig_cmd_fifo_data_out((LEN_STRT_INDEX+LEN_WIDTH)-1 downto
LEN_STRT_INDEX);
sig_fifo_next_strt_strb <= sig_cmd_fifo_data_out((STRT_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
STRT_STRB_STRT_INDEX);
sig_fifo_next_last_strb <= sig_cmd_fifo_data_out((LAST_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
LAST_STRB_STRT_INDEX);
sig_fifo_next_drr <= sig_cmd_fifo_data_out(DRR_STRT_INDEX);
sig_fifo_next_eof <= sig_cmd_fifo_data_out(EOF_STRT_INDEX);
sig_fifo_next_sequential <= sig_cmd_fifo_data_out(SEQUENTIAL_STRT_INDEX);
sig_fifo_next_cmd_cmplt <= sig_cmd_fifo_data_out(CMD_CMPLT_STRT_INDEX);
sig_fifo_next_calc_error <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX);
------------------------------------------------------------
-- Instance: I_DATA_CNTL_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO
--
------------------------------------------------------------
I_DATA_CNTL_FIFO : entity axi_datamover_v5_1_9.axi_datamover_fifo
generic map (
C_DWIDTH => DCTL_FIFO_WIDTH ,
C_DEPTH => C_DATA_CNTL_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
fifo_wr_tready => sig_fifo_wr_cmd_ready ,
fifo_wr_tdata => sig_cmd_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
fifo_rd_tready => sig_fifo_rd_cmd_ready ,
fifo_rd_tdata => sig_cmd_fifo_data_out ,
fifo_rd_empty => sig_cmd_fifo_empty
);
end generate GEN_DATA_CNTL_FIFO;
-- Data Qualifier Register ------------------------------------
sig_ld_new_cmd <= sig_push_dqual_reg ;
sig_dqual_rdy <= sig_dqual_reg_full ;
sig_strt_strb_reg <= sig_next_strt_strb_reg ;
sig_last_strb_reg <= sig_next_last_strb_reg ;
sig_tag_reg <= sig_next_tag_reg ;
sig_cmd_cmplt_reg <= sig_next_cmd_cmplt_reg ;
sig_calc_error_reg <= sig_next_calc_error_reg ;
sig_cmd_is_eof <= sig_next_eof_reg ;
-- new for no bubbles between child requests
sig_sequential_push <= sig_good_mmap_dbeat and -- MMap handshake qualified
sig_last_dbeat and -- last data beat of transfer
sig_next_sequential_reg;-- next queued command is sequential
-- to the current command
-- pre 13.1 sig_push_dqual_reg <= (sig_sequential_push or
-- pre 13.1 sig_dqual_reg_empty) and
-- pre 13.1 sig_fifo_rd_cmd_valid and
-- pre 13.1 sig_aposted_cntr_ready and
-- pre 13.1 not(wsc2mstr_halt_pipe); -- The Wr Status Controller is not
-- pre 13.1 -- stalling the command execution pipe
sig_push_dqual_reg <= (sig_sequential_push or
sig_dqual_reg_empty) and
sig_fifo_rd_cmd_valid and
sig_aposted_cntr_ready and
not(sig_calc_error_reg) and -- 13.1 addition => An error has not been propagated
not(wsc2mstr_halt_pipe); -- The Wr Status Controller is not
-- stalling the command execution pipe
sig_pop_dqual_reg <= not(sig_next_calc_error_reg) and
sig_get_next_dqual and
sig_dqual_reg_full ;
-- new for no bubbles between child requests
sig_clr_dqual_reg <= mmap_reset or
(sig_pop_dqual_reg and
not(sig_push_dqual_reg));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DQUAL_REG
--
-- Process Description:
-- This process implements a register for the Data
-- Control and qualifiers. It operates like a 1 deep Sync FIFO.
--
-------------------------------------------------------------
IMP_DQUAL_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_clr_dqual_reg = '1') then
sig_next_tag_reg <= (others => '0');
sig_next_strt_strb_reg <= (others => '0');
sig_next_last_strb_reg <= (others => '0');
sig_next_eof_reg <= '0' ;
sig_next_sequential_reg <= '0' ;
sig_next_cmd_cmplt_reg <= '0' ;
sig_next_calc_error_reg <= '0' ;
sig_dqual_reg_empty <= '1' ;
sig_dqual_reg_full <= '0' ;
elsif (sig_push_dqual_reg = '1') then
sig_next_tag_reg <= sig_fifo_next_tag ;
sig_next_strt_strb_reg <= sig_sfhalt_next_strt_strb ;
sig_next_last_strb_reg <= sig_fifo_next_last_strb ;
sig_next_eof_reg <= sig_fifo_next_eof ;
sig_next_sequential_reg <= sig_fifo_next_sequential ;
sig_next_cmd_cmplt_reg <= sig_fifo_next_cmd_cmplt ;
sig_next_calc_error_reg <= sig_fifo_next_calc_error ;
sig_dqual_reg_empty <= '0';
sig_dqual_reg_full <= '1';
else
null; -- don't change state
end if;
end if;
end process IMP_DQUAL_REG;
-- Address LS Cntr logic --------------------------
sig_addr_lsb_reg <= STD_LOGIC_VECTOR(sig_ls_addr_cntr);
sig_addr_incr_unsgnd <= TO_UNSIGNED(ADDR_INCR_VALUE, C_SEL_ADDR_WIDTH);
sig_incr_ls_addr_cntr <= sig_good_mmap_dbeat;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_ADDR_LSB_CNTR
--
-- Process Description:
-- Implements the LS Address Counter used for controlling
-- the Write STRB DeMux during Burst transfers
--
-------------------------------------------------------------
DO_ADDR_LSB_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(sig_pop_dqual_reg = '1'and
sig_push_dqual_reg = '0')) then -- Clear the Counter
sig_ls_addr_cntr <= (others => '0');
elsif (sig_push_dqual_reg = '1') then -- Load the Counter
sig_ls_addr_cntr <= unsigned(sig_fifo_next_sadddr_lsb);
elsif (sig_incr_ls_addr_cntr = '1') then -- Increment the Counter
sig_ls_addr_cntr <= sig_ls_addr_cntr + sig_addr_incr_unsgnd;
else
null; -- Hold Current value
end if;
end if;
end process DO_ADDR_LSB_CNTR;
-- Address Posted Counter Logic --------------------------------------
sig_addr_chan_rdy <= not(sig_addr_posted_cntr_eq_0 or
sig_apc_going2zero) ; -- Gates data channel xfer handshake
sig_aposted_cntr_ready <= not(sig_addr_posted_cntr_max) ; -- Gates new command fetching
sig_no_posted_cmds <= sig_addr_posted_cntr_eq_0 ; -- Used for flushing cmds that are posted
sig_incr_addr_posted_cntr <= sig_addr_posted ;
sig_decr_addr_posted_cntr <= sig_last_mmap_dbeat_reg ;
sig_addr_posted_cntr_eq_0 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ZERO)
Else '0';
sig_addr_posted_cntr_max <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_MAX)
Else '0';
sig_addr_posted_cntr_eq_1 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ONE)
Else '0';
sig_apc_going2zero <= sig_addr_posted_cntr_eq_1 and
sig_decr_addr_posted_cntr and
not(sig_incr_addr_posted_cntr);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_POSTED_FIFO_CNTR
--
-- Process Description:
-- This process implements a counter for the tracking
-- if an Address has been posted on the AXI address channel.
-- The Data Controller must wait for an address to be posted
-- before proceeding with the corresponding data transfer on
-- the Data Channel. The counter is also used to track flushing
-- operations where all transfers commited on the AXI Address
-- Channel have to be completed before a halt can occur.
-------------------------------------------------------------
IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_addr_posted_cntr <= ADDR_POSTED_ZERO;
elsif (sig_incr_addr_posted_cntr = '1' and
sig_decr_addr_posted_cntr = '0' and
sig_addr_posted_cntr_max = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ;
elsif (sig_incr_addr_posted_cntr = '0' and
sig_decr_addr_posted_cntr = '1' and
sig_addr_posted_cntr_eq_0 = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_POSTED_FIFO_CNTR;
------- First/Middle/Last Dbeat detimination -------------------
sig_new_len_eq_0 <= '1'
When (sig_fifo_next_len = LEN_OF_ZERO)
else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_FIRST_MID_LAST
--
-- Process Description:
-- Implements the detection of the First/Mid/Last databeat of
-- a transfer.
--
-------------------------------------------------------------
DO_FIRST_MID_LAST : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_first_dbeat <= '0';
sig_last_dbeat <= '0';
sig_single_dbeat <= '0';
elsif (sig_ld_new_cmd = '1') then
sig_first_dbeat <= not(sig_new_len_eq_0);
sig_last_dbeat <= sig_new_len_eq_0;
sig_single_dbeat <= sig_new_len_eq_0;
Elsif (sig_dbeat_cntr_eq_1 = '1' and
sig_good_mmap_dbeat = '1') Then
sig_first_dbeat <= '0';
sig_last_dbeat <= '1';
sig_single_dbeat <= '0';
Elsif (sig_dbeat_cntr_eq_0 = '0' and
sig_dbeat_cntr_eq_1 = '0' and
sig_good_mmap_dbeat = '1') Then
sig_first_dbeat <= '0';
sig_last_dbeat <= '0';
sig_single_dbeat <= '0';
else
null; -- hold current state
end if;
end if;
end process DO_FIRST_MID_LAST;
------- Data Controller Halted Indication -------------------------------
data2all_dcntlr_halted <= sig_no_posted_cmds or
sig_calc_error_reg;
------- Data Beat counter logic -------------------------------
sig_dbeat_cntr_int <= TO_INTEGER(sig_dbeat_cntr);
sig_dbeat_cntr_eq_0 <= '1'
when (sig_dbeat_cntr_int = 0)
Else '0';
sig_dbeat_cntr_eq_1 <= '1'
when (sig_dbeat_cntr_int = 1)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_DBEAT_CNTR
--
-- Process Description:
-- Implements the transfer data beat counter used to track
-- progress of the transfer.
--
-------------------------------------------------------------
DO_DBEAT_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_dbeat_cntr <= (others => '0');
elsif (sig_ld_new_cmd = '1') then
sig_dbeat_cntr <= unsigned(sig_fifo_next_len);
Elsif (sig_good_mmap_dbeat = '1' and
sig_dbeat_cntr_eq_0 = '0') Then
sig_dbeat_cntr <= sig_dbeat_cntr-1;
else
null; -- Hold current state
end if;
end if;
end process DO_DBEAT_CNTR;
------- Soft Shutdown Logic -------------------------------
-- Formulate the soft shutdown complete flag
sig_data2rst_stop_cmplt <= (sig_halt_reg_dly3 and -- Normal Mode shutdown
sig_no_posted_cmds and
not(sig_calc_error_reg)) or
(sig_halt_reg_dly3 and -- Shutdown after error trap
sig_calc_error_reg);
-- Generate a gate signal to deassert the WVALID output
-- for 1 clock cycle after a WLAST is issued. This only
-- occurs when in soft shutdown mode.
sig_stop_wvalid <= (sig_last_mmap_dbeat_reg and
sig_halt_reg) or
sig_data2rst_stop_cmplt;
-- Assign the output port skid buf control for the
-- input Stream skid buffer
data2skid_halt <= sig_data2skid_halt;
-- Create a 1 clock wide pulse to tell the input
-- stream skid buffer to shut down.
sig_data2skid_halt <= sig_halt_reg_dly2 and
not(sig_halt_reg_dly3);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG
--
-- Process Description:
-- Implements the flop for capturing the Halt request from
-- the Reset module.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg <= '0';
elsif (rst2data_stop_request = '1') then
sig_halt_reg <= '1';
else
null; -- Hold current State
end if;
end if;
end process IMP_HALT_REQ_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG_DLY
--
-- Process Description:
-- Implements the flops for delaying the halt request by 3
-- clocks to allow the Address Controller to halt before the
-- Data Contoller can safely indicate it has exhausted all
-- transfers committed to the AXI Address Channel by the Address
-- Controller.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG_DLY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg_dly1 <= '0';
sig_halt_reg_dly2 <= '0';
sig_halt_reg_dly3 <= '0';
else
sig_halt_reg_dly1 <= sig_halt_reg;
sig_halt_reg_dly2 <= sig_halt_reg_dly1;
sig_halt_reg_dly3 <= sig_halt_reg_dly2;
end if;
end if;
end process IMP_HALT_REQ_REG_DLY;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_wrdata_cntl.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_wrdata_cntl.vhd
--
-- Description:
-- This file implements the DataMover Master Write Data Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_9;
use axi_datamover_v5_1_9.axi_datamover_fifo;
use axi_datamover_v5_1_9.axi_datamover_strb_gen2;
-------------------------------------------------------------------------------
entity axi_datamover_wrdata_cntl is
generic (
C_REALIGNER_INCLUDED : Integer range 0 to 1 := 0;
-- Indicates the Data Realignment function is included (external
-- to this module)
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Indicates the INDET BTT function is included (external
-- to this module)
C_SF_BYTES_RCVD_WIDTH : Integer range 1 to 23 := 1;
-- Sets the width of the data2wsc_bytes_rcvd port used for
-- relaying the actual number of bytes received when Idet BTT is
-- enabled (C_ENABLE_INDET_BTT = 1)
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS bits of the transfer address that
-- are being used to Demux write data to a wider AXI4 Write
-- Data Bus
C_DATA_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 4;
-- Sets the depth of the internal command fifo used for the
-- command queue
C_MMAP_DWIDTH : Integer range 32 to 1024 := 32;
-- Indicates the native data width of the Read Data port
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Stream output data port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Indicates the width of the Tag field of the input command
C_FAMILY : String := "virtex7"
-- Indicates the device family of the target FPGA
);
port (
-- Clock and Reset inputs ----------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
------------------------------------------------------------------------
-- Soft Shutdown internal interface ------------------------------------
--
rst2data_stop_request : in std_logic; --
-- Active high soft stop request to modules --
--
data2addr_stop_req : Out std_logic; --
-- Active high signal requesting the Address Controller --
-- to stop posting commands to the AXI Read Address Channel --
--
data2rst_stop_cmplt : Out std_logic; --
-- Active high indication that the Data Controller has completed --
-- any pending transfers committed by the Address Controller --
-- after a stop has been requested by the Reset module. --
------------------------------------------------------------------------
-- Store and Forward support signals for external User logic ------------
--
wr_xfer_cmplt : Out std_logic; --
-- Active high indication that the Data Controller has completed --
-- a single write data transfer on the AXI4 Write Data Channel. --
-- This signal is escentially echos the assertion of wlast sent --
-- to the AXI4. --
--
s2mm_ld_nxt_len : out std_logic; --
-- Active high pulse indicating a new xfer length has been queued --
-- to the WDC Cmd FIFO --
--
s2mm_wr_len : out std_logic_vector(7 downto 0); --
-- Bus indicating the AXI LEN value associated with the xfer command --
-- loaded into the WDC Command FIFO. --
-------------------------------------------------------------------------
-- AXI Write Data Channel Skid buffer I/O ---------------------------------------
--
data2skid_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- Write DATA output to skid buffer --
--
data2skid_wdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- Write DATA output to skid buffer --
--
data2skid_wstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- Write DATA output to skid buffer --
--
data2skid_wlast : Out std_logic; --
-- Write LAST output to skid buffer --
--
data2skid_wvalid : Out std_logic; --
-- Write VALID output to skid buffer --
--
skid2data_wready : In std_logic; --
-- Write READY input from skid buffer --
----------------------------------------------------------------------------------
-- AXI Slave Stream In -----------------------------------------------------------
--
s2mm_strm_wvalid : In std_logic; --
-- AXI Stream VALID input --
--
s2mm_strm_wready : Out Std_logic; --
-- AXI Stream READY Output --
--
s2mm_strm_wdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data input --
--
s2mm_strm_wstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB input --
--
s2mm_strm_wlast : In std_logic; --
-- AXI Stream LAST input --
----------------------------------------------------------------------------------
-- Stream input sideband signal from Indeterminate BTT and/or DRE ----------------
--
s2mm_strm_eop : In std_logic; --
-- Stream End of Packet marker input. This is only used when Indeterminate --
-- BTT mode is enable. Otherwise it is ignored --
--
--
s2mm_stbs_asserted : in std_logic_vector(7 downto 0); --
-- Indicates the number of asserted WSTRB bits for the --
-- associated input stream data beat --
--
--
-- Realigner Underrun/overrun error flag used in non Indeterminate BTT --
-- Mode --
realign2wdc_eop_error : In std_logic ; --
-- Asserted active high and will only clear with reset. It is only used --
-- when Indeterminate BTT is not enabled and the Realigner Module is --
-- instantiated upstream from the WDC. The Realigner will detect overrun --
-- underrun conditions and will will relay these conditions via this signal. --
----------------------------------------------------------------------------------
-- Command Calculator Interface --------------------------------------------------
--
mstr2data_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the write strb --
-- demux (only used if Stream data width is less than the MMap Dwidth). --
--
mstr2data_len : In std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the first stream data beat --
--
mstr2data_last_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the last stream --
-- data beat --
--
mstr2data_drr : In std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : In std_logic; --
-- The endiing tranfer of a sequence of transfers --
--
mstr2data_sequential : In std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : In std_logic; --
-- The final child tranfer of a parent command fetched from --
-- the Command FIFO (not necessarily an EOF command) --
--
mstr2data_cmd_valid : In std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : Out std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
----------------------------------------------------------------------------------
-- Address Controller Interface --------------------------------------------------
--
addr2data_addr_posted : In std_logic ; --
-- Indication from the Address Channel Controller to the --
-- Data Controller that an address has been posted to the --
-- AXI Address Channel --
--
--
data2addr_data_rdy : out std_logic; --
-- Indication that the Data Channel is ready to send the first --
-- databeat of the next command on the write data channel. --
-- This is used for the "wait for data" feature which keeps the --
-- address controller from issuing a transfer request until the --
-- corresponding data valid is asserted on the stream input. The --
-- WDC will continue to assert the output until an assertion on --
-- the addr2data_addr_posted is received. --
---------------------------------------------------------------------------------
-- Premature TLAST assertion error flag ------------------------------------------
--
data2all_tlast_error : Out std_logic; --
-- When asserted, this indicates the data controller detected --
-- a premature TLAST assertion on the incoming data stream. --
---------------------------------------------------------------------------------
-- Data Controller Halted Status -------------------------------------------------
--
data2all_dcntlr_halted : Out std_logic; --
-- When asserted, this indicates the data controller has satisfied --
-- all pending transfers queued by the Address Controller and is halted. --
----------------------------------------------------------------------------------
-- Input Stream Skid Buffer Halt control -----------------------------------------
--
data2skid_halt : Out std_logic; --
-- The data controller asserts this output for 1 primary clock period --
-- The pulse commands the MM2S Stream skid buffer to tun off outputs --
-- at the next tlast transmission. --
----------------------------------------------------------------------------------
-- Write Status Controller Interface ---------------------------------------------
--
data2wsc_tag : Out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The command tag --
--
data2wsc_calc_err : Out std_logic ; --
-- Indication that the current command out from the Cntl FIFO --
-- has a calculation error --
--
data2wsc_last_err : Out std_logic ; --
-- Indication that the current write transfer encountered a premature --
-- TLAST assertion on the incoming Stream Channel --
--
data2wsc_cmd_cmplt : Out std_logic ; --
-- Indication by the Data Channel Controller that the --
-- corresponding status is the last status for a command --
-- pulled from the command FIFO --
--
wsc2data_ready : in std_logic; --
-- Input from the Write Status Module indicating that the --
-- Status Reg/FIFO is ready to accept data --
--
data2wsc_valid : Out std_logic; --
-- Output to the Command/Status Module indicating that the --
-- Data Controller has valid tag and err indicators to write --
-- to the Status module --
--
data2wsc_eop : Out std_logic; --
-- Output to the Write Status Controller indicating that the --
-- associated command status also corresponds to a End of Packet --
-- marker for the input Stream. This is only used when Inderminate --
-- BTT is enabled in the S2MM. --
--
data2wsc_bytes_rcvd : Out std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0); --
-- Output to the Write Status Controller indicating the actual --
-- number of bytes received from the Stream input for the --
-- corresponding command status. This is only used when Inderminate --
-- BTT is enabled in the S2MM. --
--
wsc2mstr_halt_pipe : In std_logic --
-- Indication to Halt the Data and Address Command pipeline due --
-- to the Status FIFO going full or an internal error being logged --
----------------------------------------------------------------------------------
);
end entity axi_datamover_wrdata_cntl;
architecture implementation of axi_datamover_wrdata_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declaration ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_dbeat_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_dbeat_residue_width (bytes_per_beat : integer) return integer is
Variable temp_dbeat_residue_width : Integer := 0; -- 8-bit stream
begin
case bytes_per_beat is
when 128 => -- 1024 bits -- Added per Per CR616409
temp_dbeat_residue_width := 7; -- Added per Per CR616409
when 64 => -- 512 bits -- Added per Per CR616409
temp_dbeat_residue_width := 6; -- Added per Per CR616409
when 32 => -- 256 bits
temp_dbeat_residue_width := 5;
when 16 => -- 128 bits
temp_dbeat_residue_width := 4;
when 8 => -- 64 bits
temp_dbeat_residue_width := 3;
when 4 => -- 32 bits
temp_dbeat_residue_width := 2;
when 2 => -- 16 bits
temp_dbeat_residue_width := 1;
when others => -- assume 1-byte transfers
temp_dbeat_residue_width := 0;
end case;
Return (temp_dbeat_residue_width);
end function funct_get_dbeat_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_cnt_width
--
-- Function Description:
-- Sets a count width based on a fifo depth. A depth of 4 or less
-- is a special case which requires a minimum count width of 3 bits.
--
-------------------------------------------------------------------
function funct_set_cnt_width (fifo_depth : integer) return integer is
Variable temp_cnt_width : Integer := 4;
begin
if (fifo_depth <= 4) then
temp_cnt_width := 3;
elsif (fifo_depth <= 8) then
temp_cnt_width := 4;
elsif (fifo_depth <= 16) then
temp_cnt_width := 5;
elsif (fifo_depth <= 32) then
temp_cnt_width := 6;
else -- fifo depth <= 64
temp_cnt_width := 7;
end if;
Return (temp_cnt_width);
end function funct_set_cnt_width;
-- Constant Declarations --------------------------------------------
Constant STRM_STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant LEN_OF_ZERO : std_logic_vector(7 downto 0) := (others => '0');
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant SADDR_LSB_WIDTH : integer := C_SEL_ADDR_WIDTH;
Constant LEN_WIDTH : integer := 8;
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant DRR_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant CMD_CMPLT_WIDTH : integer := 1;
Constant SEQUENTIAL_WIDTH : integer := 1;
Constant DCTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
SADDR_LSB_WIDTH + -- LS Address field width
LEN_WIDTH + -- LEN field
STRB_WIDTH + -- Starting Strobe field
STRB_WIDTH + -- Ending Strobe field
DRR_WIDTH + -- DRE Re-alignment Request Flag Field
EOF_WIDTH + -- EOF flag field
SEQUENTIAL_WIDTH + -- Sequential command flag
CMD_CMPLT_WIDTH + -- Command Complete Flag
CALC_ERR_WIDTH; -- Calc error flag
Constant TAG_STRT_INDEX : integer := 0;
Constant SADDR_LSB_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant LEN_STRT_INDEX : integer := SADDR_LSB_STRT_INDEX + SADDR_LSB_WIDTH;
Constant STRT_STRB_STRT_INDEX : integer := LEN_STRT_INDEX + LEN_WIDTH;
Constant LAST_STRB_STRT_INDEX : integer := STRT_STRB_STRT_INDEX + STRB_WIDTH;
Constant DRR_STRT_INDEX : integer := LAST_STRB_STRT_INDEX + STRB_WIDTH;
Constant EOF_STRT_INDEX : integer := DRR_STRT_INDEX + DRR_WIDTH;
Constant SEQUENTIAL_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant CMD_CMPLT_STRT_INDEX : integer := SEQUENTIAL_STRT_INDEX+SEQUENTIAL_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := CMD_CMPLT_STRT_INDEX+CMD_CMPLT_WIDTH;
Constant ADDR_INCR_VALUE : integer := C_STREAM_DWIDTH/8;
Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_DATA_CNTL_FIFO_DEPTH);
Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '0');
Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH);
Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '1');
-- Signal Declarations --------------------------------------------
signal sig_get_next_dqual : std_logic := '0';
signal sig_last_mmap_dbeat : std_logic := '0';
signal sig_last_mmap_dbeat_reg : std_logic := '0';
signal sig_mmap2data_ready : std_logic := '0';
signal sig_data2mmap_valid : std_logic := '0';
signal sig_data2mmap_last : std_logic := '0';
signal sig_data2mmap_data : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_ld_new_cmd : std_logic := '0';
signal sig_ld_new_cmd_reg : std_logic := '0';
signal sig_cmd_cmplt_reg : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_lsb_reg : std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted : std_logic := '0';
signal sig_dqual_rdy : std_logic := '0';
signal sig_good_mmap_dbeat : std_logic := '0';
signal sig_first_dbeat : std_logic := '0';
signal sig_last_dbeat : std_logic := '0';
signal sig_single_dbeat : std_logic := '0';
signal sig_new_len_eq_0 : std_logic := '0';
signal sig_dbeat_cntr : unsigned(7 downto 0) := (others => '0');
Signal sig_dbeat_cntr_int : Integer range 0 to 255 := 0;
signal sig_dbeat_cntr_eq_0 : std_logic := '0';
signal sig_dbeat_cntr_eq_1 : std_logic := '0';
signal sig_wsc_ready : std_logic := '0';
signal sig_push_to_wsc : std_logic := '0';
signal sig_push_to_wsc_cmplt : std_logic := '0';
signal sig_set_push2wsc : std_logic := '0';
signal sig_data2wsc_tag : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2wsc_calc_err : std_logic := '0';
signal sig_data2wsc_last_err : std_logic := '0';
signal sig_data2wsc_cmd_cmplt : std_logic := '0';
signal sig_tlast_error : std_logic := '0';
signal sig_tlast_error_strbs : std_logic := '0';
signal sig_end_stbs_match_err : std_logic := '0';
signal sig_tlast_error_reg : std_logic := '0';
signal sig_cmd_is_eof : std_logic := '0';
signal sig_push_err2wsc : std_logic := '0';
signal sig_tlast_error_ovrrun : std_logic := '0';
signal sig_tlast_error_undrrun : std_logic := '0';
signal sig_next_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_eof_reg : std_logic := '0';
signal sig_next_sequential_reg : std_logic := '0';
signal sig_next_cmd_cmplt_reg : std_logic := '0';
signal sig_next_calc_error_reg : std_logic := '0';
signal sig_pop_dqual_reg : std_logic := '0';
signal sig_push_dqual_reg : std_logic := '0';
signal sig_dqual_reg_empty : std_logic := '0';
signal sig_dqual_reg_full : std_logic := '0';
signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted_cntr_eq_0 : std_logic := '0';
signal sig_addr_posted_cntr_max : std_logic := '0';
signal sig_decr_addr_posted_cntr : std_logic := '0';
signal sig_incr_addr_posted_cntr : std_logic := '0';
signal sig_addr_posted_cntr_eq_1 : std_logic := '0';
signal sig_apc_going2zero : std_logic := '0';
signal sig_aposted_cntr_ready : std_logic := '0';
signal sig_addr_chan_rdy : std_logic := '0';
Signal sig_no_posted_cmds : std_logic := '0';
signal sig_ls_addr_cntr : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_ls_addr_cntr : std_logic := '0';
signal sig_addr_incr_unsgnd : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
Signal sig_cmd_fifo_data_in : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0) := (others => '0');
Signal sig_cmd_fifo_data_out : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_tag : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_sadddr_lsb : std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_fifo_next_strt_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_last_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_drr : std_logic := '0';
signal sig_fifo_next_eof : std_logic := '0';
signal sig_fifo_next_cmd_cmplt : std_logic := '0';
signal sig_fifo_next_sequential : std_logic := '0';
signal sig_fifo_next_calc_error : std_logic := '0';
signal sig_cmd_fifo_empty : std_logic := '0';
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_sequential_push : std_logic := '0';
signal sig_clr_dqual_reg : std_logic := '0';
signal sig_tlast_err_stop : std_logic := '0';
signal sig_halt_reg : std_logic := '0';
signal sig_halt_reg_dly1 : std_logic := '0';
signal sig_halt_reg_dly2 : std_logic := '0';
signal sig_halt_reg_dly3 : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_stop_wvalid : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_s2mm_strm_wready : std_logic := '0';
signal sig_good_strm_dbeat : std_logic := '0';
signal sig_halt_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_sfhalt_next_strt_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_wfd_simult_clr_set : std_logic := '0';
signal sig_wr_xfer_cmplt : std_logic := '0';
signal sig_s2mm_ld_nxt_len : std_logic := '0';
signal sig_s2mm_wr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_spcl_push_err2wsc : std_logic := '0';
begin --(architecture implementation)
-- Command calculator handshake
data2mstr_cmd_ready <= sig_data2mstr_cmd_ready;
-- Write Data Channel Skid Buffer Port assignments
sig_mmap2data_ready <= skid2data_wready ;
data2skid_wvalid <= sig_data2mmap_valid ;
data2skid_wlast <= sig_data2mmap_last ;
data2skid_wdata <= sig_data2mmap_data ;
data2skid_saddr_lsb <= sig_addr_lsb_reg ;
-- AXI MM2S Stream Channel Port assignments
sig_data2mmap_data <= s2mm_strm_wdata ;
-- Premature TLAST assertion indication
data2all_tlast_error <= sig_tlast_error_reg ;
-- Stream Input Ready Handshake
s2mm_strm_wready <= sig_s2mm_strm_wready ;
sig_good_strm_dbeat <= s2mm_strm_wvalid and
sig_s2mm_strm_wready;
sig_data2mmap_last <= sig_dbeat_cntr_eq_0 and
sig_dqual_rdy;
-- Write Status Block interface signals
data2wsc_valid <= sig_push_to_wsc and
not(sig_tlast_err_stop) ; -- only allow 1 status write on TLAST errror
sig_wsc_ready <= wsc2data_ready ;
data2wsc_tag <= sig_data2wsc_tag ;
data2wsc_calc_err <= sig_data2wsc_calc_err ;
data2wsc_last_err <= sig_data2wsc_last_err ;
data2wsc_cmd_cmplt <= sig_data2wsc_cmd_cmplt ;
-- Address Channel Controller synchro pulse input
sig_addr_posted <= addr2data_addr_posted;
-- Request to halt the Address Channel Controller
data2addr_stop_req <= sig_halt_reg or
sig_tlast_error_reg;
-- Halted flag to the reset module
data2rst_stop_cmplt <= sig_data2rst_stop_cmplt;
-- Indicate the Write Data Controller is always ready
data2addr_data_rdy <= '1';
-- Write Transfer Completed Status output
wr_xfer_cmplt <= sig_wr_xfer_cmplt ;
-- New LEN value is being loaded
s2mm_ld_nxt_len <= sig_s2mm_ld_nxt_len;
-- The new LEN value
s2mm_wr_len <= sig_s2mm_wr_len;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_WR_CMPLT_FLAG
--
-- Process Description:
-- Implements the status flag indicating that a write data
-- transfer has completed. This is an echo of a wlast assertion
-- and a qualified data beat on the AXI4 Write Data Channel.
--
-------------------------------------------------------------
IMP_WR_CMPLT_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_wr_xfer_cmplt <= '0';
else
sig_wr_xfer_cmplt <= sig_data2mmap_last and
sig_good_strm_dbeat;
end if;
end if;
end process IMP_WR_CMPLT_FLAG;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Omits any Indeterminate BTT Support logic and includes
-- any error detection needed in Non Indeterminate BTT mode.
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
begin
sig_sfhalt_next_strt_strb <= sig_fifo_next_strt_strb;
-- Just housekeep the output port signals
data2wsc_eop <= '0';
data2wsc_bytes_rcvd <= (others => '0');
-- WRSTRB logic ------------------------------
-- Generate the Write Strobes for the MMap Write Data Channel
-- for the non Indeterminate BTT Case
data2skid_wstrb <= sig_strt_strb_reg
When (sig_first_dbeat = '1')
Else sig_last_strb_reg
When (sig_last_dbeat = '1')
Else (others => '1');
-- Generate the Stream Ready for the Stream input side
sig_s2mm_strm_wready <= sig_halt_reg or -- force tready if a halt requested
(sig_mmap2data_ready and
sig_addr_chan_rdy and -- This puts combinational logic in the stream WREADY path
sig_dqual_rdy and
not(sig_calc_error_reg) and
not(sig_tlast_error_reg)); -- Stop the stream channel at a overrun/underrun detection
-- MMap Write Data Channel Valid Handshaking
sig_data2mmap_valid <= (s2mm_strm_wvalid or
sig_tlast_error_reg or -- force valid if TLAST error
sig_halt_reg ) and -- force valid if halt requested
sig_addr_chan_rdy and -- xfers are commited on the address channel and
sig_dqual_rdy and -- there are commands in the command fifo
not(sig_calc_error_reg) and
not(sig_stop_wvalid); -- gate off wvalid immediately after a wlast for 1 clk
-- or when the soft shutdown has completed
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LOCAL_ERR_DETECT
--
-- If Generate Description:
-- Implements the local overrun and underrun detection when
-- the S2MM Realigner is not included.
--
--
------------------------------------------------------------
GEN_LOCAL_ERR_DETECT : if (C_REALIGNER_INCLUDED = 0) generate
begin
------- Input Stream TLAST assertion error -------------------------------
sig_tlast_error_ovrrun <= sig_cmd_is_eof and
sig_dbeat_cntr_eq_0 and
sig_good_mmap_dbeat and
not(s2mm_strm_wlast);
sig_tlast_error_undrrun <= s2mm_strm_wlast and
sig_good_mmap_dbeat and
(not(sig_dbeat_cntr_eq_0) or
not(sig_cmd_is_eof));
sig_end_stbs_match_err <= '1' -- Set flag if the calculated end strobe value
When ((s2mm_strm_wstrb /= sig_next_last_strb_reg) and -- does not match the received strobe value
(s2mm_strm_wlast = '1') and -- at TLAST assertion
(sig_good_mmap_dbeat = '1')) -- Qualified databeat
Else '0';
sig_tlast_error <= (sig_tlast_error_ovrrun or
sig_tlast_error_undrrun or
sig_end_stbs_match_err) and
not(sig_halt_reg); -- Suppress TLAST error when in soft shutdown
-- Just housekeep this when local TLAST error detection is used
sig_spcl_push_err2wsc <= '0';
end generate GEN_LOCAL_ERR_DETECT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_EXTERN_ERR_DETECT
--
-- If Generate Description:
-- Omits the local overrun and underrun detection and relies
-- on the S2MM Realigner for the detection.
--
------------------------------------------------------------
GEN_EXTERN_ERR_DETECT : if (C_REALIGNER_INCLUDED = 1) generate
begin
sig_tlast_error_undrrun <= '0'; -- not used here
sig_tlast_error_ovrrun <= '0'; -- not used here
sig_end_stbs_match_err <= '0'; -- not used here
sig_tlast_error <= realign2wdc_eop_error and -- External error detection asserted
not(sig_halt_reg); -- Suppress TLAST error when in soft shutdown
-- Special case for pushing error status when timing is such that no
-- addresses have been posted to AXI and a TLAST error has been detected
-- by the Realigner module and propagated in from the Stream input side.
sig_spcl_push_err2wsc <= sig_tlast_error_reg and
not(sig_tlast_err_stop) and
not(sig_addr_chan_rdy );
end generate GEN_EXTERN_ERR_DETECT;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERR_REG
--
-- Process Description:
-- Implements a sample and hold flop for the flag indicating
-- that the input Stream TLAST assertion was not at the expected
-- data beat relative to the commanded number of databeats
-- from the associated command from the SCC or PCC.
-------------------------------------------------------------
IMP_TLAST_ERR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_tlast_error_reg <= '0';
elsif (sig_tlast_error = '1') then
sig_tlast_error_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_TLAST_ERR_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERROR_STOP
--
-- Process Description:
-- Implements the flop to generate a stop flag once the TLAST
-- error condition has been relayed to the Write Status
-- Controller. This stop flag is used to prevent any more
-- pushes to the Write Status Controller.
--
-------------------------------------------------------------
IMP_TLAST_ERROR_STOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_tlast_err_stop <= '0';
elsif (sig_tlast_error_reg = '1' and
sig_push_to_wsc_cmplt = '1') then
sig_tlast_err_stop <= '1';
else
null; -- Hold State
end if;
end if;
end process IMP_TLAST_ERROR_STOP;
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INDET_BTT
--
-- If Generate Description:
-- Includes any Indeterminate BTT Support logic. Primarily
-- this is a counter for the input stream bytes received. The
-- received byte count is relayed to the Write Status Controller
-- for each parent command completed.
-- When a packet completion is indicated via the EOP marker
-- assertion, the status to the Write Status Controller also
-- indicates the EOP condition.
-- Note that underrun and overrun detection/error flagging
-- is disabled in Indeterminate BTT Mode.
--
------------------------------------------------------------
GEN_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
-- local constants
Constant BYTE_CNTR_WIDTH : integer := C_SF_BYTES_RCVD_WIDTH;
Constant NUM_ZEROS_WIDTH : integer := 8;
Constant BYTES_PER_DBEAT : integer := C_STREAM_DWIDTH/8;
Constant STRBGEN_ADDR_SLICE_WIDTH : integer :=
funct_get_dbeat_residue_width(BYTES_PER_DBEAT);
Constant STRBGEN_ADDR_0 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
-- local signals
signal lsig_byte_cntr : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_byte_cntr_incr_value : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_ld_byte_cntr : std_logic := '0';
signal lsig_incr_byte_cntr : std_logic := '0';
signal lsig_clr_byte_cntr : std_logic := '0';
signal lsig_end_of_cmd_reg : std_logic := '0';
signal lsig_eop_s_h_reg : std_logic := '0';
signal lsig_eop_reg : std_logic := '0';
signal sig_strbgen_addr : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_strbgen_bytes : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH downto 0) := (others => '0');
begin
-- Assign the outputs to the Write Status Controller
data2wsc_eop <= lsig_eop_reg and
not(sig_next_calc_error_reg);
data2wsc_bytes_rcvd <= STD_LOGIC_VECTOR(lsig_byte_cntr);
-- WRSTRB logic ------------------------------
--sig_strbgen_bytes <= (others => '1'); -- set to the max value
-- set the length to the max number of bytes per databeat
sig_strbgen_bytes <= STD_LOGIC_VECTOR(TO_UNSIGNED(BYTES_PER_DBEAT, STRBGEN_ADDR_SLICE_WIDTH+1));
sig_strbgen_addr <= STD_LOGIC_VECTOR(RESIZE(UNSIGNED(sig_fifo_next_sadddr_lsb),
STRBGEN_ADDR_SLICE_WIDTH)) ;
------------------------------------------------------------
-- Instance: I_STRT_STRB_GEN
--
-- Description:
-- Strobe generator used to generate the starting databeat
-- strobe value for soft shutdown case where the S2MM has to
-- flush out all of the transfers that have been committed
-- to the AXI Write address channel. Starting Strobes must
-- match the committed address offest for each transfer.
--
------------------------------------------------------------
I_STRT_STRB_GEN : entity axi_datamover_v5_1_9.axi_datamover_strb_gen2
generic map (
C_OP_MODE => 0 , -- 0 = Offset/Length mode
C_STRB_WIDTH => BYTES_PER_DBEAT ,
C_OFFSET_WIDTH => STRBGEN_ADDR_SLICE_WIDTH ,
C_NUM_BYTES_WIDTH => STRBGEN_ADDR_SLICE_WIDTH+1
)
port map (
start_addr_offset => sig_strbgen_addr ,
end_addr_offset => STRBGEN_ADDR_0 , -- not used in op mode 0
num_valid_bytes => sig_strbgen_bytes ,
strb_out => sig_sfhalt_next_strt_strb
);
-- Generate the WSTRB to use during soft shutdown
sig_halt_strb <= sig_strt_strb_reg
When (sig_first_dbeat = '1' or
sig_single_dbeat = '1')
Else (others => '1');
-- Generate the Write Strobes for the MMap Write Data Channel
-- for the Indeterminate BTT case. Strobes come from the Stream
-- input from the Indeterminate BTT module during normal operation.
-- However, during soft shutdown, those strobes become unpredictable
-- so generated strobes have to be used.
data2skid_wstrb <= sig_halt_strb
When (sig_halt_reg = '1')
Else s2mm_strm_wstrb;
-- Generate the Stream Ready for the Stream input side
sig_s2mm_strm_wready <= sig_halt_reg or -- force tready if a halt requested
(sig_mmap2data_ready and -- MMap is accepting the xfers
sig_addr_chan_rdy and -- xfers are commited on the address channel and
sig_dqual_rdy and -- there are commands in the command fifo
not(sig_calc_error_reg) and -- No internal error
not(sig_stop_wvalid)); -- Gate off stream ready immediately after a wlast for 1 clk
-- or when the soft shutdown has completed
-- MMap Write Data Channel Valid Handshaking
sig_data2mmap_valid <= (s2mm_strm_wvalid or -- Normal Stream input valid
sig_halt_reg ) and -- force valid if halt requested
sig_addr_chan_rdy and -- xfers are commited on the address channel and
sig_dqual_rdy and -- there are commands in the command fifo
not(sig_calc_error_reg) and -- No internal error
not(sig_stop_wvalid); -- Gate off wvalid immediately after a wlast for 1 clk
-- or when the soft shutdown has completed
-- TLAST Error housekeeping for Indeterminate BTT Mode
-- There is no Underrun/overrun in Stroe and Forward mode
sig_tlast_error_ovrrun <= '0'; -- Not used with Indeterminate BTT
sig_tlast_error_undrrun <= '0'; -- Not used with Indeterminate BTT
sig_end_stbs_match_err <= '0'; -- Not used with Indeterminate BTT
sig_tlast_error <= '0'; -- Not used with Indeterminate BTT
sig_tlast_error_reg <= '0'; -- Not used with Indeterminate BTT
sig_tlast_err_stop <= '0'; -- Not used with Indeterminate BTT
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOP_REG_FLOP
--
-- Process Description:
-- Register the End of Packet marker.
--
-------------------------------------------------------------
IMP_EOP_REG_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_end_of_cmd_reg <= '0';
lsig_eop_reg <= '0';
Elsif (sig_good_strm_dbeat = '1') Then
lsig_end_of_cmd_reg <= sig_next_cmd_cmplt_reg and
s2mm_strm_wlast;
lsig_eop_reg <= s2mm_strm_eop;
else
null; -- hold current state
end if;
end if;
end process IMP_EOP_REG_FLOP;
----- Byte Counter Logic -----------------------------------------------
-- The Byte counter reflects the actual byte count received on the
-- Stream input for each parent command loaded into the S2MM command
-- FIFO. Thus it counts input bytes until the command complete qualifier
-- is set and the TLAST input from the Stream input.
lsig_clr_byte_cntr <= lsig_end_of_cmd_reg and -- Clear if a new stream packet does not start
not(sig_good_strm_dbeat); -- immediately after the previous one finished.
lsig_ld_byte_cntr <= lsig_end_of_cmd_reg and -- Only load if a new stream packet starts
sig_good_strm_dbeat; -- immediately after the previous one finished.
lsig_incr_byte_cntr <= sig_good_strm_dbeat;
lsig_byte_cntr_incr_value <= RESIZE(UNSIGNED(s2mm_stbs_asserted),
BYTE_CNTR_WIDTH);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BYTE_CMTR
--
-- Process Description:
-- Keeps a running byte count per burst packet loaded into the
-- xfer FIFO. It is based on the strobes set on the incoming
-- Stream dbeat.
--
-------------------------------------------------------------
IMP_BYTE_CMTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
lsig_clr_byte_cntr = '1') then
lsig_byte_cntr <= (others => '0');
elsif (lsig_ld_byte_cntr = '1') then
lsig_byte_cntr <= lsig_byte_cntr_incr_value;
elsif (lsig_incr_byte_cntr = '1') then
lsig_byte_cntr <= lsig_byte_cntr + lsig_byte_cntr_incr_value;
else
null; -- hold current value
end if;
end if;
end process IMP_BYTE_CMTR;
end generate GEN_INDET_BTT;
-- Internal logic ------------------------------
sig_good_mmap_dbeat <= sig_mmap2data_ready and
sig_data2mmap_valid;
sig_last_mmap_dbeat <= sig_good_mmap_dbeat and
sig_data2mmap_last;
sig_get_next_dqual <= sig_last_mmap_dbeat;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_LAST_DBEAT
--
-- Process Description:
-- This implements a FLOP that creates a pulse
-- indicating the LAST signal for an outgoing write data channel
-- has been sent. Note that it is possible to have back to
-- back LAST databeats.
--
-------------------------------------------------------------
REG_LAST_DBEAT : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_last_mmap_dbeat_reg <= '0';
else
sig_last_mmap_dbeat_reg <= sig_last_mmap_dbeat;
end if;
end if;
end process REG_LAST_DBEAT;
----- Write Status Interface Stuff --------------------------
sig_push_to_wsc_cmplt <= sig_push_to_wsc and sig_wsc_ready;
sig_set_push2wsc <= (sig_good_mmap_dbeat and
sig_dbeat_cntr_eq_0) or
sig_push_err2wsc or
sig_spcl_push_err2wsc; -- Special case from CR616212
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_INTERR_PUSH_FLOP
--
-- Process Description:
-- Generate a 1 clock wide pulse when a calc error has propagated
-- from the Command Calculator. This pulse is used to force a
-- push of the error status to the Write Status Controller
-- without a AXI transfer completion.
--
-------------------------------------------------------------
IMP_INTERR_PUSH_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_push_err2wsc = '1') then
sig_push_err2wsc <= '0';
elsif (sig_ld_new_cmd_reg = '1' and
sig_calc_error_reg = '1') then
sig_push_err2wsc <= '1';
else
null; -- hold state
end if;
end if;
end process IMP_INTERR_PUSH_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PUSH2WSC_FLOP
--
-- Process Description:
-- Implements a Sample and hold register for the outbound status
-- signals to the Write Status Controller (WSC). This register
-- has to support back to back transfer completions.
--
-------------------------------------------------------------
IMP_PUSH2WSC_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(sig_push_to_wsc_cmplt = '1' and
sig_set_push2wsc = '0')) then
sig_push_to_wsc <= '0';
sig_data2wsc_tag <= (others => '0');
sig_data2wsc_calc_err <= '0';
sig_data2wsc_last_err <= '0';
sig_data2wsc_cmd_cmplt <= '0';
elsif (sig_set_push2wsc = '1' and
sig_tlast_err_stop = '0') then
sig_push_to_wsc <= '1';
sig_data2wsc_tag <= sig_tag_reg ;
sig_data2wsc_calc_err <= sig_calc_error_reg ;
sig_data2wsc_last_err <= sig_tlast_error_reg or
sig_tlast_error ;
sig_data2wsc_cmd_cmplt <= sig_cmd_cmplt_reg or
sig_tlast_error_reg or
sig_tlast_error ;
else
null; -- hold current state
end if;
end if;
end process IMP_PUSH2WSC_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_LD_NEW_CMD_REG
--
-- Process Description:
-- Registers the flag indicating a new command has been
-- loaded. Needs to be a 1 clk wide pulse.
--
-------------------------------------------------------------
IMP_LD_NEW_CMD_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_ld_new_cmd_reg = '1') then
sig_ld_new_cmd_reg <= '0';
else
sig_ld_new_cmd_reg <= sig_ld_new_cmd;
end if;
end if;
end process IMP_LD_NEW_CMD_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_NXT_LEN_REG
--
-- Process Description:
-- Registers the load control and length value for a command
-- passed to the WDC input command interface. The registered
-- signals are used for the external Indeterminate BTT support
-- ports.
--
-------------------------------------------------------------
IMP_NXT_LEN_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_s2mm_ld_nxt_len <= '0';
sig_s2mm_wr_len <= (others => '0');
else
sig_s2mm_ld_nxt_len <= mstr2data_cmd_valid and
sig_data2mstr_cmd_ready;
sig_s2mm_wr_len <= mstr2data_len;
end if;
end if;
end process IMP_NXT_LEN_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_DATA_CNTL_FIFO
--
-- If Generate Description:
-- Omits the input data control FIFO if the requested FIFO
-- depth is 1. The Data Qualifier Register serves as a
-- 1 deep FIFO by itself.
--
------------------------------------------------------------
GEN_NO_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH = 1) generate
begin
-- Command Calculator Handshake output
sig_data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_rd_cmd_valid <= mstr2data_cmd_valid ;
-- pre 13.1 sig_fifo_wr_cmd_ready <= sig_dqual_reg_empty and
-- pre 13.1 sig_aposted_cntr_ready and
-- pre 13.1 not(wsc2mstr_halt_pipe) and -- The Wr Status Controller is not stalling
-- pre 13.1 not(sig_calc_error_reg); -- the command execution pipe and there is
-- pre 13.1 -- no calculation error being propagated
sig_fifo_wr_cmd_ready <= sig_push_dqual_reg;
sig_fifo_next_tag <= mstr2data_tag ;
sig_fifo_next_sadddr_lsb <= mstr2data_saddr_lsb ;
sig_fifo_next_len <= mstr2data_len ;
sig_fifo_next_strt_strb <= mstr2data_strt_strb ;
sig_fifo_next_last_strb <= mstr2data_last_strb ;
sig_fifo_next_drr <= mstr2data_drr ;
sig_fifo_next_eof <= mstr2data_eof ;
sig_fifo_next_sequential <= mstr2data_sequential ;
sig_fifo_next_cmd_cmplt <= mstr2data_cmd_cmplt ;
sig_fifo_next_calc_error <= mstr2data_calc_error ;
end generate GEN_NO_DATA_CNTL_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_DATA_CNTL_FIFO
--
-- If Generate Description:
-- Includes the input data control FIFO if the requested
-- FIFO depth is more than 1.
--
------------------------------------------------------------
GEN_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH > 1) generate
begin
-- Command Calculator Handshake output
sig_data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_wr_cmd_valid <= mstr2data_cmd_valid ;
-- pop the fifo when dqual reg is pushed
sig_fifo_rd_cmd_ready <= sig_push_dqual_reg;
-- Format the input fifo data word
sig_cmd_fifo_data_in <= mstr2data_calc_error &
mstr2data_cmd_cmplt &
mstr2data_sequential &
mstr2data_eof &
mstr2data_drr &
mstr2data_last_strb &
mstr2data_strt_strb &
mstr2data_len &
mstr2data_saddr_lsb &
mstr2data_tag ;
-- Rip the output fifo data word
sig_fifo_next_tag <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto
TAG_STRT_INDEX);
sig_fifo_next_sadddr_lsb <= sig_cmd_fifo_data_out((SADDR_LSB_STRT_INDEX+SADDR_LSB_WIDTH)-1 downto
SADDR_LSB_STRT_INDEX);
sig_fifo_next_len <= sig_cmd_fifo_data_out((LEN_STRT_INDEX+LEN_WIDTH)-1 downto
LEN_STRT_INDEX);
sig_fifo_next_strt_strb <= sig_cmd_fifo_data_out((STRT_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
STRT_STRB_STRT_INDEX);
sig_fifo_next_last_strb <= sig_cmd_fifo_data_out((LAST_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
LAST_STRB_STRT_INDEX);
sig_fifo_next_drr <= sig_cmd_fifo_data_out(DRR_STRT_INDEX);
sig_fifo_next_eof <= sig_cmd_fifo_data_out(EOF_STRT_INDEX);
sig_fifo_next_sequential <= sig_cmd_fifo_data_out(SEQUENTIAL_STRT_INDEX);
sig_fifo_next_cmd_cmplt <= sig_cmd_fifo_data_out(CMD_CMPLT_STRT_INDEX);
sig_fifo_next_calc_error <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX);
------------------------------------------------------------
-- Instance: I_DATA_CNTL_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO
--
------------------------------------------------------------
I_DATA_CNTL_FIFO : entity axi_datamover_v5_1_9.axi_datamover_fifo
generic map (
C_DWIDTH => DCTL_FIFO_WIDTH ,
C_DEPTH => C_DATA_CNTL_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
fifo_wr_tready => sig_fifo_wr_cmd_ready ,
fifo_wr_tdata => sig_cmd_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
fifo_rd_tready => sig_fifo_rd_cmd_ready ,
fifo_rd_tdata => sig_cmd_fifo_data_out ,
fifo_rd_empty => sig_cmd_fifo_empty
);
end generate GEN_DATA_CNTL_FIFO;
-- Data Qualifier Register ------------------------------------
sig_ld_new_cmd <= sig_push_dqual_reg ;
sig_dqual_rdy <= sig_dqual_reg_full ;
sig_strt_strb_reg <= sig_next_strt_strb_reg ;
sig_last_strb_reg <= sig_next_last_strb_reg ;
sig_tag_reg <= sig_next_tag_reg ;
sig_cmd_cmplt_reg <= sig_next_cmd_cmplt_reg ;
sig_calc_error_reg <= sig_next_calc_error_reg ;
sig_cmd_is_eof <= sig_next_eof_reg ;
-- new for no bubbles between child requests
sig_sequential_push <= sig_good_mmap_dbeat and -- MMap handshake qualified
sig_last_dbeat and -- last data beat of transfer
sig_next_sequential_reg;-- next queued command is sequential
-- to the current command
-- pre 13.1 sig_push_dqual_reg <= (sig_sequential_push or
-- pre 13.1 sig_dqual_reg_empty) and
-- pre 13.1 sig_fifo_rd_cmd_valid and
-- pre 13.1 sig_aposted_cntr_ready and
-- pre 13.1 not(wsc2mstr_halt_pipe); -- The Wr Status Controller is not
-- pre 13.1 -- stalling the command execution pipe
sig_push_dqual_reg <= (sig_sequential_push or
sig_dqual_reg_empty) and
sig_fifo_rd_cmd_valid and
sig_aposted_cntr_ready and
not(sig_calc_error_reg) and -- 13.1 addition => An error has not been propagated
not(wsc2mstr_halt_pipe); -- The Wr Status Controller is not
-- stalling the command execution pipe
sig_pop_dqual_reg <= not(sig_next_calc_error_reg) and
sig_get_next_dqual and
sig_dqual_reg_full ;
-- new for no bubbles between child requests
sig_clr_dqual_reg <= mmap_reset or
(sig_pop_dqual_reg and
not(sig_push_dqual_reg));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DQUAL_REG
--
-- Process Description:
-- This process implements a register for the Data
-- Control and qualifiers. It operates like a 1 deep Sync FIFO.
--
-------------------------------------------------------------
IMP_DQUAL_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_clr_dqual_reg = '1') then
sig_next_tag_reg <= (others => '0');
sig_next_strt_strb_reg <= (others => '0');
sig_next_last_strb_reg <= (others => '0');
sig_next_eof_reg <= '0' ;
sig_next_sequential_reg <= '0' ;
sig_next_cmd_cmplt_reg <= '0' ;
sig_next_calc_error_reg <= '0' ;
sig_dqual_reg_empty <= '1' ;
sig_dqual_reg_full <= '0' ;
elsif (sig_push_dqual_reg = '1') then
sig_next_tag_reg <= sig_fifo_next_tag ;
sig_next_strt_strb_reg <= sig_sfhalt_next_strt_strb ;
sig_next_last_strb_reg <= sig_fifo_next_last_strb ;
sig_next_eof_reg <= sig_fifo_next_eof ;
sig_next_sequential_reg <= sig_fifo_next_sequential ;
sig_next_cmd_cmplt_reg <= sig_fifo_next_cmd_cmplt ;
sig_next_calc_error_reg <= sig_fifo_next_calc_error ;
sig_dqual_reg_empty <= '0';
sig_dqual_reg_full <= '1';
else
null; -- don't change state
end if;
end if;
end process IMP_DQUAL_REG;
-- Address LS Cntr logic --------------------------
sig_addr_lsb_reg <= STD_LOGIC_VECTOR(sig_ls_addr_cntr);
sig_addr_incr_unsgnd <= TO_UNSIGNED(ADDR_INCR_VALUE, C_SEL_ADDR_WIDTH);
sig_incr_ls_addr_cntr <= sig_good_mmap_dbeat;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_ADDR_LSB_CNTR
--
-- Process Description:
-- Implements the LS Address Counter used for controlling
-- the Write STRB DeMux during Burst transfers
--
-------------------------------------------------------------
DO_ADDR_LSB_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(sig_pop_dqual_reg = '1'and
sig_push_dqual_reg = '0')) then -- Clear the Counter
sig_ls_addr_cntr <= (others => '0');
elsif (sig_push_dqual_reg = '1') then -- Load the Counter
sig_ls_addr_cntr <= unsigned(sig_fifo_next_sadddr_lsb);
elsif (sig_incr_ls_addr_cntr = '1') then -- Increment the Counter
sig_ls_addr_cntr <= sig_ls_addr_cntr + sig_addr_incr_unsgnd;
else
null; -- Hold Current value
end if;
end if;
end process DO_ADDR_LSB_CNTR;
-- Address Posted Counter Logic --------------------------------------
sig_addr_chan_rdy <= not(sig_addr_posted_cntr_eq_0 or
sig_apc_going2zero) ; -- Gates data channel xfer handshake
sig_aposted_cntr_ready <= not(sig_addr_posted_cntr_max) ; -- Gates new command fetching
sig_no_posted_cmds <= sig_addr_posted_cntr_eq_0 ; -- Used for flushing cmds that are posted
sig_incr_addr_posted_cntr <= sig_addr_posted ;
sig_decr_addr_posted_cntr <= sig_last_mmap_dbeat_reg ;
sig_addr_posted_cntr_eq_0 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ZERO)
Else '0';
sig_addr_posted_cntr_max <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_MAX)
Else '0';
sig_addr_posted_cntr_eq_1 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ONE)
Else '0';
sig_apc_going2zero <= sig_addr_posted_cntr_eq_1 and
sig_decr_addr_posted_cntr and
not(sig_incr_addr_posted_cntr);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_POSTED_FIFO_CNTR
--
-- Process Description:
-- This process implements a counter for the tracking
-- if an Address has been posted on the AXI address channel.
-- The Data Controller must wait for an address to be posted
-- before proceeding with the corresponding data transfer on
-- the Data Channel. The counter is also used to track flushing
-- operations where all transfers commited on the AXI Address
-- Channel have to be completed before a halt can occur.
-------------------------------------------------------------
IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_addr_posted_cntr <= ADDR_POSTED_ZERO;
elsif (sig_incr_addr_posted_cntr = '1' and
sig_decr_addr_posted_cntr = '0' and
sig_addr_posted_cntr_max = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ;
elsif (sig_incr_addr_posted_cntr = '0' and
sig_decr_addr_posted_cntr = '1' and
sig_addr_posted_cntr_eq_0 = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_POSTED_FIFO_CNTR;
------- First/Middle/Last Dbeat detimination -------------------
sig_new_len_eq_0 <= '1'
When (sig_fifo_next_len = LEN_OF_ZERO)
else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_FIRST_MID_LAST
--
-- Process Description:
-- Implements the detection of the First/Mid/Last databeat of
-- a transfer.
--
-------------------------------------------------------------
DO_FIRST_MID_LAST : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_first_dbeat <= '0';
sig_last_dbeat <= '0';
sig_single_dbeat <= '0';
elsif (sig_ld_new_cmd = '1') then
sig_first_dbeat <= not(sig_new_len_eq_0);
sig_last_dbeat <= sig_new_len_eq_0;
sig_single_dbeat <= sig_new_len_eq_0;
Elsif (sig_dbeat_cntr_eq_1 = '1' and
sig_good_mmap_dbeat = '1') Then
sig_first_dbeat <= '0';
sig_last_dbeat <= '1';
sig_single_dbeat <= '0';
Elsif (sig_dbeat_cntr_eq_0 = '0' and
sig_dbeat_cntr_eq_1 = '0' and
sig_good_mmap_dbeat = '1') Then
sig_first_dbeat <= '0';
sig_last_dbeat <= '0';
sig_single_dbeat <= '0';
else
null; -- hold current state
end if;
end if;
end process DO_FIRST_MID_LAST;
------- Data Controller Halted Indication -------------------------------
data2all_dcntlr_halted <= sig_no_posted_cmds or
sig_calc_error_reg;
------- Data Beat counter logic -------------------------------
sig_dbeat_cntr_int <= TO_INTEGER(sig_dbeat_cntr);
sig_dbeat_cntr_eq_0 <= '1'
when (sig_dbeat_cntr_int = 0)
Else '0';
sig_dbeat_cntr_eq_1 <= '1'
when (sig_dbeat_cntr_int = 1)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_DBEAT_CNTR
--
-- Process Description:
-- Implements the transfer data beat counter used to track
-- progress of the transfer.
--
-------------------------------------------------------------
DO_DBEAT_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_dbeat_cntr <= (others => '0');
elsif (sig_ld_new_cmd = '1') then
sig_dbeat_cntr <= unsigned(sig_fifo_next_len);
Elsif (sig_good_mmap_dbeat = '1' and
sig_dbeat_cntr_eq_0 = '0') Then
sig_dbeat_cntr <= sig_dbeat_cntr-1;
else
null; -- Hold current state
end if;
end if;
end process DO_DBEAT_CNTR;
------- Soft Shutdown Logic -------------------------------
-- Formulate the soft shutdown complete flag
sig_data2rst_stop_cmplt <= (sig_halt_reg_dly3 and -- Normal Mode shutdown
sig_no_posted_cmds and
not(sig_calc_error_reg)) or
(sig_halt_reg_dly3 and -- Shutdown after error trap
sig_calc_error_reg);
-- Generate a gate signal to deassert the WVALID output
-- for 1 clock cycle after a WLAST is issued. This only
-- occurs when in soft shutdown mode.
sig_stop_wvalid <= (sig_last_mmap_dbeat_reg and
sig_halt_reg) or
sig_data2rst_stop_cmplt;
-- Assign the output port skid buf control for the
-- input Stream skid buffer
data2skid_halt <= sig_data2skid_halt;
-- Create a 1 clock wide pulse to tell the input
-- stream skid buffer to shut down.
sig_data2skid_halt <= sig_halt_reg_dly2 and
not(sig_halt_reg_dly3);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG
--
-- Process Description:
-- Implements the flop for capturing the Halt request from
-- the Reset module.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg <= '0';
elsif (rst2data_stop_request = '1') then
sig_halt_reg <= '1';
else
null; -- Hold current State
end if;
end if;
end process IMP_HALT_REQ_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG_DLY
--
-- Process Description:
-- Implements the flops for delaying the halt request by 3
-- clocks to allow the Address Controller to halt before the
-- Data Contoller can safely indicate it has exhausted all
-- transfers committed to the AXI Address Channel by the Address
-- Controller.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG_DLY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg_dly1 <= '0';
sig_halt_reg_dly2 <= '0';
sig_halt_reg_dly3 <= '0';
else
sig_halt_reg_dly1 <= sig_halt_reg;
sig_halt_reg_dly2 <= sig_halt_reg_dly1;
sig_halt_reg_dly3 <= sig_halt_reg_dly2;
end if;
end if;
end process IMP_HALT_REQ_REG_DLY;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_wrdata_cntl.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_wrdata_cntl.vhd
--
-- Description:
-- This file implements the DataMover Master Write Data Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_9;
use axi_datamover_v5_1_9.axi_datamover_fifo;
use axi_datamover_v5_1_9.axi_datamover_strb_gen2;
-------------------------------------------------------------------------------
entity axi_datamover_wrdata_cntl is
generic (
C_REALIGNER_INCLUDED : Integer range 0 to 1 := 0;
-- Indicates the Data Realignment function is included (external
-- to this module)
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Indicates the INDET BTT function is included (external
-- to this module)
C_SF_BYTES_RCVD_WIDTH : Integer range 1 to 23 := 1;
-- Sets the width of the data2wsc_bytes_rcvd port used for
-- relaying the actual number of bytes received when Idet BTT is
-- enabled (C_ENABLE_INDET_BTT = 1)
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS bits of the transfer address that
-- are being used to Demux write data to a wider AXI4 Write
-- Data Bus
C_DATA_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 4;
-- Sets the depth of the internal command fifo used for the
-- command queue
C_MMAP_DWIDTH : Integer range 32 to 1024 := 32;
-- Indicates the native data width of the Read Data port
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Stream output data port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Indicates the width of the Tag field of the input command
C_FAMILY : String := "virtex7"
-- Indicates the device family of the target FPGA
);
port (
-- Clock and Reset inputs ----------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
------------------------------------------------------------------------
-- Soft Shutdown internal interface ------------------------------------
--
rst2data_stop_request : in std_logic; --
-- Active high soft stop request to modules --
--
data2addr_stop_req : Out std_logic; --
-- Active high signal requesting the Address Controller --
-- to stop posting commands to the AXI Read Address Channel --
--
data2rst_stop_cmplt : Out std_logic; --
-- Active high indication that the Data Controller has completed --
-- any pending transfers committed by the Address Controller --
-- after a stop has been requested by the Reset module. --
------------------------------------------------------------------------
-- Store and Forward support signals for external User logic ------------
--
wr_xfer_cmplt : Out std_logic; --
-- Active high indication that the Data Controller has completed --
-- a single write data transfer on the AXI4 Write Data Channel. --
-- This signal is escentially echos the assertion of wlast sent --
-- to the AXI4. --
--
s2mm_ld_nxt_len : out std_logic; --
-- Active high pulse indicating a new xfer length has been queued --
-- to the WDC Cmd FIFO --
--
s2mm_wr_len : out std_logic_vector(7 downto 0); --
-- Bus indicating the AXI LEN value associated with the xfer command --
-- loaded into the WDC Command FIFO. --
-------------------------------------------------------------------------
-- AXI Write Data Channel Skid buffer I/O ---------------------------------------
--
data2skid_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- Write DATA output to skid buffer --
--
data2skid_wdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- Write DATA output to skid buffer --
--
data2skid_wstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- Write DATA output to skid buffer --
--
data2skid_wlast : Out std_logic; --
-- Write LAST output to skid buffer --
--
data2skid_wvalid : Out std_logic; --
-- Write VALID output to skid buffer --
--
skid2data_wready : In std_logic; --
-- Write READY input from skid buffer --
----------------------------------------------------------------------------------
-- AXI Slave Stream In -----------------------------------------------------------
--
s2mm_strm_wvalid : In std_logic; --
-- AXI Stream VALID input --
--
s2mm_strm_wready : Out Std_logic; --
-- AXI Stream READY Output --
--
s2mm_strm_wdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data input --
--
s2mm_strm_wstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB input --
--
s2mm_strm_wlast : In std_logic; --
-- AXI Stream LAST input --
----------------------------------------------------------------------------------
-- Stream input sideband signal from Indeterminate BTT and/or DRE ----------------
--
s2mm_strm_eop : In std_logic; --
-- Stream End of Packet marker input. This is only used when Indeterminate --
-- BTT mode is enable. Otherwise it is ignored --
--
--
s2mm_stbs_asserted : in std_logic_vector(7 downto 0); --
-- Indicates the number of asserted WSTRB bits for the --
-- associated input stream data beat --
--
--
-- Realigner Underrun/overrun error flag used in non Indeterminate BTT --
-- Mode --
realign2wdc_eop_error : In std_logic ; --
-- Asserted active high and will only clear with reset. It is only used --
-- when Indeterminate BTT is not enabled and the Realigner Module is --
-- instantiated upstream from the WDC. The Realigner will detect overrun --
-- underrun conditions and will will relay these conditions via this signal. --
----------------------------------------------------------------------------------
-- Command Calculator Interface --------------------------------------------------
--
mstr2data_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the write strb --
-- demux (only used if Stream data width is less than the MMap Dwidth). --
--
mstr2data_len : In std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the first stream data beat --
--
mstr2data_last_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the last stream --
-- data beat --
--
mstr2data_drr : In std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : In std_logic; --
-- The endiing tranfer of a sequence of transfers --
--
mstr2data_sequential : In std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : In std_logic; --
-- The final child tranfer of a parent command fetched from --
-- the Command FIFO (not necessarily an EOF command) --
--
mstr2data_cmd_valid : In std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : Out std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
----------------------------------------------------------------------------------
-- Address Controller Interface --------------------------------------------------
--
addr2data_addr_posted : In std_logic ; --
-- Indication from the Address Channel Controller to the --
-- Data Controller that an address has been posted to the --
-- AXI Address Channel --
--
--
data2addr_data_rdy : out std_logic; --
-- Indication that the Data Channel is ready to send the first --
-- databeat of the next command on the write data channel. --
-- This is used for the "wait for data" feature which keeps the --
-- address controller from issuing a transfer request until the --
-- corresponding data valid is asserted on the stream input. The --
-- WDC will continue to assert the output until an assertion on --
-- the addr2data_addr_posted is received. --
---------------------------------------------------------------------------------
-- Premature TLAST assertion error flag ------------------------------------------
--
data2all_tlast_error : Out std_logic; --
-- When asserted, this indicates the data controller detected --
-- a premature TLAST assertion on the incoming data stream. --
---------------------------------------------------------------------------------
-- Data Controller Halted Status -------------------------------------------------
--
data2all_dcntlr_halted : Out std_logic; --
-- When asserted, this indicates the data controller has satisfied --
-- all pending transfers queued by the Address Controller and is halted. --
----------------------------------------------------------------------------------
-- Input Stream Skid Buffer Halt control -----------------------------------------
--
data2skid_halt : Out std_logic; --
-- The data controller asserts this output for 1 primary clock period --
-- The pulse commands the MM2S Stream skid buffer to tun off outputs --
-- at the next tlast transmission. --
----------------------------------------------------------------------------------
-- Write Status Controller Interface ---------------------------------------------
--
data2wsc_tag : Out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The command tag --
--
data2wsc_calc_err : Out std_logic ; --
-- Indication that the current command out from the Cntl FIFO --
-- has a calculation error --
--
data2wsc_last_err : Out std_logic ; --
-- Indication that the current write transfer encountered a premature --
-- TLAST assertion on the incoming Stream Channel --
--
data2wsc_cmd_cmplt : Out std_logic ; --
-- Indication by the Data Channel Controller that the --
-- corresponding status is the last status for a command --
-- pulled from the command FIFO --
--
wsc2data_ready : in std_logic; --
-- Input from the Write Status Module indicating that the --
-- Status Reg/FIFO is ready to accept data --
--
data2wsc_valid : Out std_logic; --
-- Output to the Command/Status Module indicating that the --
-- Data Controller has valid tag and err indicators to write --
-- to the Status module --
--
data2wsc_eop : Out std_logic; --
-- Output to the Write Status Controller indicating that the --
-- associated command status also corresponds to a End of Packet --
-- marker for the input Stream. This is only used when Inderminate --
-- BTT is enabled in the S2MM. --
--
data2wsc_bytes_rcvd : Out std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0); --
-- Output to the Write Status Controller indicating the actual --
-- number of bytes received from the Stream input for the --
-- corresponding command status. This is only used when Inderminate --
-- BTT is enabled in the S2MM. --
--
wsc2mstr_halt_pipe : In std_logic --
-- Indication to Halt the Data and Address Command pipeline due --
-- to the Status FIFO going full or an internal error being logged --
----------------------------------------------------------------------------------
);
end entity axi_datamover_wrdata_cntl;
architecture implementation of axi_datamover_wrdata_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declaration ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_dbeat_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_dbeat_residue_width (bytes_per_beat : integer) return integer is
Variable temp_dbeat_residue_width : Integer := 0; -- 8-bit stream
begin
case bytes_per_beat is
when 128 => -- 1024 bits -- Added per Per CR616409
temp_dbeat_residue_width := 7; -- Added per Per CR616409
when 64 => -- 512 bits -- Added per Per CR616409
temp_dbeat_residue_width := 6; -- Added per Per CR616409
when 32 => -- 256 bits
temp_dbeat_residue_width := 5;
when 16 => -- 128 bits
temp_dbeat_residue_width := 4;
when 8 => -- 64 bits
temp_dbeat_residue_width := 3;
when 4 => -- 32 bits
temp_dbeat_residue_width := 2;
when 2 => -- 16 bits
temp_dbeat_residue_width := 1;
when others => -- assume 1-byte transfers
temp_dbeat_residue_width := 0;
end case;
Return (temp_dbeat_residue_width);
end function funct_get_dbeat_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_cnt_width
--
-- Function Description:
-- Sets a count width based on a fifo depth. A depth of 4 or less
-- is a special case which requires a minimum count width of 3 bits.
--
-------------------------------------------------------------------
function funct_set_cnt_width (fifo_depth : integer) return integer is
Variable temp_cnt_width : Integer := 4;
begin
if (fifo_depth <= 4) then
temp_cnt_width := 3;
elsif (fifo_depth <= 8) then
temp_cnt_width := 4;
elsif (fifo_depth <= 16) then
temp_cnt_width := 5;
elsif (fifo_depth <= 32) then
temp_cnt_width := 6;
else -- fifo depth <= 64
temp_cnt_width := 7;
end if;
Return (temp_cnt_width);
end function funct_set_cnt_width;
-- Constant Declarations --------------------------------------------
Constant STRM_STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant LEN_OF_ZERO : std_logic_vector(7 downto 0) := (others => '0');
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant SADDR_LSB_WIDTH : integer := C_SEL_ADDR_WIDTH;
Constant LEN_WIDTH : integer := 8;
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant DRR_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant CMD_CMPLT_WIDTH : integer := 1;
Constant SEQUENTIAL_WIDTH : integer := 1;
Constant DCTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
SADDR_LSB_WIDTH + -- LS Address field width
LEN_WIDTH + -- LEN field
STRB_WIDTH + -- Starting Strobe field
STRB_WIDTH + -- Ending Strobe field
DRR_WIDTH + -- DRE Re-alignment Request Flag Field
EOF_WIDTH + -- EOF flag field
SEQUENTIAL_WIDTH + -- Sequential command flag
CMD_CMPLT_WIDTH + -- Command Complete Flag
CALC_ERR_WIDTH; -- Calc error flag
Constant TAG_STRT_INDEX : integer := 0;
Constant SADDR_LSB_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant LEN_STRT_INDEX : integer := SADDR_LSB_STRT_INDEX + SADDR_LSB_WIDTH;
Constant STRT_STRB_STRT_INDEX : integer := LEN_STRT_INDEX + LEN_WIDTH;
Constant LAST_STRB_STRT_INDEX : integer := STRT_STRB_STRT_INDEX + STRB_WIDTH;
Constant DRR_STRT_INDEX : integer := LAST_STRB_STRT_INDEX + STRB_WIDTH;
Constant EOF_STRT_INDEX : integer := DRR_STRT_INDEX + DRR_WIDTH;
Constant SEQUENTIAL_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant CMD_CMPLT_STRT_INDEX : integer := SEQUENTIAL_STRT_INDEX+SEQUENTIAL_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := CMD_CMPLT_STRT_INDEX+CMD_CMPLT_WIDTH;
Constant ADDR_INCR_VALUE : integer := C_STREAM_DWIDTH/8;
Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_DATA_CNTL_FIFO_DEPTH);
Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '0');
Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH);
Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '1');
-- Signal Declarations --------------------------------------------
signal sig_get_next_dqual : std_logic := '0';
signal sig_last_mmap_dbeat : std_logic := '0';
signal sig_last_mmap_dbeat_reg : std_logic := '0';
signal sig_mmap2data_ready : std_logic := '0';
signal sig_data2mmap_valid : std_logic := '0';
signal sig_data2mmap_last : std_logic := '0';
signal sig_data2mmap_data : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_ld_new_cmd : std_logic := '0';
signal sig_ld_new_cmd_reg : std_logic := '0';
signal sig_cmd_cmplt_reg : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_lsb_reg : std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted : std_logic := '0';
signal sig_dqual_rdy : std_logic := '0';
signal sig_good_mmap_dbeat : std_logic := '0';
signal sig_first_dbeat : std_logic := '0';
signal sig_last_dbeat : std_logic := '0';
signal sig_single_dbeat : std_logic := '0';
signal sig_new_len_eq_0 : std_logic := '0';
signal sig_dbeat_cntr : unsigned(7 downto 0) := (others => '0');
Signal sig_dbeat_cntr_int : Integer range 0 to 255 := 0;
signal sig_dbeat_cntr_eq_0 : std_logic := '0';
signal sig_dbeat_cntr_eq_1 : std_logic := '0';
signal sig_wsc_ready : std_logic := '0';
signal sig_push_to_wsc : std_logic := '0';
signal sig_push_to_wsc_cmplt : std_logic := '0';
signal sig_set_push2wsc : std_logic := '0';
signal sig_data2wsc_tag : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2wsc_calc_err : std_logic := '0';
signal sig_data2wsc_last_err : std_logic := '0';
signal sig_data2wsc_cmd_cmplt : std_logic := '0';
signal sig_tlast_error : std_logic := '0';
signal sig_tlast_error_strbs : std_logic := '0';
signal sig_end_stbs_match_err : std_logic := '0';
signal sig_tlast_error_reg : std_logic := '0';
signal sig_cmd_is_eof : std_logic := '0';
signal sig_push_err2wsc : std_logic := '0';
signal sig_tlast_error_ovrrun : std_logic := '0';
signal sig_tlast_error_undrrun : std_logic := '0';
signal sig_next_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_eof_reg : std_logic := '0';
signal sig_next_sequential_reg : std_logic := '0';
signal sig_next_cmd_cmplt_reg : std_logic := '0';
signal sig_next_calc_error_reg : std_logic := '0';
signal sig_pop_dqual_reg : std_logic := '0';
signal sig_push_dqual_reg : std_logic := '0';
signal sig_dqual_reg_empty : std_logic := '0';
signal sig_dqual_reg_full : std_logic := '0';
signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted_cntr_eq_0 : std_logic := '0';
signal sig_addr_posted_cntr_max : std_logic := '0';
signal sig_decr_addr_posted_cntr : std_logic := '0';
signal sig_incr_addr_posted_cntr : std_logic := '0';
signal sig_addr_posted_cntr_eq_1 : std_logic := '0';
signal sig_apc_going2zero : std_logic := '0';
signal sig_aposted_cntr_ready : std_logic := '0';
signal sig_addr_chan_rdy : std_logic := '0';
Signal sig_no_posted_cmds : std_logic := '0';
signal sig_ls_addr_cntr : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_ls_addr_cntr : std_logic := '0';
signal sig_addr_incr_unsgnd : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
Signal sig_cmd_fifo_data_in : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0) := (others => '0');
Signal sig_cmd_fifo_data_out : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_tag : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_sadddr_lsb : std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_fifo_next_strt_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_last_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_drr : std_logic := '0';
signal sig_fifo_next_eof : std_logic := '0';
signal sig_fifo_next_cmd_cmplt : std_logic := '0';
signal sig_fifo_next_sequential : std_logic := '0';
signal sig_fifo_next_calc_error : std_logic := '0';
signal sig_cmd_fifo_empty : std_logic := '0';
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_sequential_push : std_logic := '0';
signal sig_clr_dqual_reg : std_logic := '0';
signal sig_tlast_err_stop : std_logic := '0';
signal sig_halt_reg : std_logic := '0';
signal sig_halt_reg_dly1 : std_logic := '0';
signal sig_halt_reg_dly2 : std_logic := '0';
signal sig_halt_reg_dly3 : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_stop_wvalid : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_s2mm_strm_wready : std_logic := '0';
signal sig_good_strm_dbeat : std_logic := '0';
signal sig_halt_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_sfhalt_next_strt_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_wfd_simult_clr_set : std_logic := '0';
signal sig_wr_xfer_cmplt : std_logic := '0';
signal sig_s2mm_ld_nxt_len : std_logic := '0';
signal sig_s2mm_wr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_spcl_push_err2wsc : std_logic := '0';
begin --(architecture implementation)
-- Command calculator handshake
data2mstr_cmd_ready <= sig_data2mstr_cmd_ready;
-- Write Data Channel Skid Buffer Port assignments
sig_mmap2data_ready <= skid2data_wready ;
data2skid_wvalid <= sig_data2mmap_valid ;
data2skid_wlast <= sig_data2mmap_last ;
data2skid_wdata <= sig_data2mmap_data ;
data2skid_saddr_lsb <= sig_addr_lsb_reg ;
-- AXI MM2S Stream Channel Port assignments
sig_data2mmap_data <= s2mm_strm_wdata ;
-- Premature TLAST assertion indication
data2all_tlast_error <= sig_tlast_error_reg ;
-- Stream Input Ready Handshake
s2mm_strm_wready <= sig_s2mm_strm_wready ;
sig_good_strm_dbeat <= s2mm_strm_wvalid and
sig_s2mm_strm_wready;
sig_data2mmap_last <= sig_dbeat_cntr_eq_0 and
sig_dqual_rdy;
-- Write Status Block interface signals
data2wsc_valid <= sig_push_to_wsc and
not(sig_tlast_err_stop) ; -- only allow 1 status write on TLAST errror
sig_wsc_ready <= wsc2data_ready ;
data2wsc_tag <= sig_data2wsc_tag ;
data2wsc_calc_err <= sig_data2wsc_calc_err ;
data2wsc_last_err <= sig_data2wsc_last_err ;
data2wsc_cmd_cmplt <= sig_data2wsc_cmd_cmplt ;
-- Address Channel Controller synchro pulse input
sig_addr_posted <= addr2data_addr_posted;
-- Request to halt the Address Channel Controller
data2addr_stop_req <= sig_halt_reg or
sig_tlast_error_reg;
-- Halted flag to the reset module
data2rst_stop_cmplt <= sig_data2rst_stop_cmplt;
-- Indicate the Write Data Controller is always ready
data2addr_data_rdy <= '1';
-- Write Transfer Completed Status output
wr_xfer_cmplt <= sig_wr_xfer_cmplt ;
-- New LEN value is being loaded
s2mm_ld_nxt_len <= sig_s2mm_ld_nxt_len;
-- The new LEN value
s2mm_wr_len <= sig_s2mm_wr_len;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_WR_CMPLT_FLAG
--
-- Process Description:
-- Implements the status flag indicating that a write data
-- transfer has completed. This is an echo of a wlast assertion
-- and a qualified data beat on the AXI4 Write Data Channel.
--
-------------------------------------------------------------
IMP_WR_CMPLT_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_wr_xfer_cmplt <= '0';
else
sig_wr_xfer_cmplt <= sig_data2mmap_last and
sig_good_strm_dbeat;
end if;
end if;
end process IMP_WR_CMPLT_FLAG;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Omits any Indeterminate BTT Support logic and includes
-- any error detection needed in Non Indeterminate BTT mode.
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
begin
sig_sfhalt_next_strt_strb <= sig_fifo_next_strt_strb;
-- Just housekeep the output port signals
data2wsc_eop <= '0';
data2wsc_bytes_rcvd <= (others => '0');
-- WRSTRB logic ------------------------------
-- Generate the Write Strobes for the MMap Write Data Channel
-- for the non Indeterminate BTT Case
data2skid_wstrb <= sig_strt_strb_reg
When (sig_first_dbeat = '1')
Else sig_last_strb_reg
When (sig_last_dbeat = '1')
Else (others => '1');
-- Generate the Stream Ready for the Stream input side
sig_s2mm_strm_wready <= sig_halt_reg or -- force tready if a halt requested
(sig_mmap2data_ready and
sig_addr_chan_rdy and -- This puts combinational logic in the stream WREADY path
sig_dqual_rdy and
not(sig_calc_error_reg) and
not(sig_tlast_error_reg)); -- Stop the stream channel at a overrun/underrun detection
-- MMap Write Data Channel Valid Handshaking
sig_data2mmap_valid <= (s2mm_strm_wvalid or
sig_tlast_error_reg or -- force valid if TLAST error
sig_halt_reg ) and -- force valid if halt requested
sig_addr_chan_rdy and -- xfers are commited on the address channel and
sig_dqual_rdy and -- there are commands in the command fifo
not(sig_calc_error_reg) and
not(sig_stop_wvalid); -- gate off wvalid immediately after a wlast for 1 clk
-- or when the soft shutdown has completed
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LOCAL_ERR_DETECT
--
-- If Generate Description:
-- Implements the local overrun and underrun detection when
-- the S2MM Realigner is not included.
--
--
------------------------------------------------------------
GEN_LOCAL_ERR_DETECT : if (C_REALIGNER_INCLUDED = 0) generate
begin
------- Input Stream TLAST assertion error -------------------------------
sig_tlast_error_ovrrun <= sig_cmd_is_eof and
sig_dbeat_cntr_eq_0 and
sig_good_mmap_dbeat and
not(s2mm_strm_wlast);
sig_tlast_error_undrrun <= s2mm_strm_wlast and
sig_good_mmap_dbeat and
(not(sig_dbeat_cntr_eq_0) or
not(sig_cmd_is_eof));
sig_end_stbs_match_err <= '1' -- Set flag if the calculated end strobe value
When ((s2mm_strm_wstrb /= sig_next_last_strb_reg) and -- does not match the received strobe value
(s2mm_strm_wlast = '1') and -- at TLAST assertion
(sig_good_mmap_dbeat = '1')) -- Qualified databeat
Else '0';
sig_tlast_error <= (sig_tlast_error_ovrrun or
sig_tlast_error_undrrun or
sig_end_stbs_match_err) and
not(sig_halt_reg); -- Suppress TLAST error when in soft shutdown
-- Just housekeep this when local TLAST error detection is used
sig_spcl_push_err2wsc <= '0';
end generate GEN_LOCAL_ERR_DETECT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_EXTERN_ERR_DETECT
--
-- If Generate Description:
-- Omits the local overrun and underrun detection and relies
-- on the S2MM Realigner for the detection.
--
------------------------------------------------------------
GEN_EXTERN_ERR_DETECT : if (C_REALIGNER_INCLUDED = 1) generate
begin
sig_tlast_error_undrrun <= '0'; -- not used here
sig_tlast_error_ovrrun <= '0'; -- not used here
sig_end_stbs_match_err <= '0'; -- not used here
sig_tlast_error <= realign2wdc_eop_error and -- External error detection asserted
not(sig_halt_reg); -- Suppress TLAST error when in soft shutdown
-- Special case for pushing error status when timing is such that no
-- addresses have been posted to AXI and a TLAST error has been detected
-- by the Realigner module and propagated in from the Stream input side.
sig_spcl_push_err2wsc <= sig_tlast_error_reg and
not(sig_tlast_err_stop) and
not(sig_addr_chan_rdy );
end generate GEN_EXTERN_ERR_DETECT;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERR_REG
--
-- Process Description:
-- Implements a sample and hold flop for the flag indicating
-- that the input Stream TLAST assertion was not at the expected
-- data beat relative to the commanded number of databeats
-- from the associated command from the SCC or PCC.
-------------------------------------------------------------
IMP_TLAST_ERR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_tlast_error_reg <= '0';
elsif (sig_tlast_error = '1') then
sig_tlast_error_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_TLAST_ERR_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERROR_STOP
--
-- Process Description:
-- Implements the flop to generate a stop flag once the TLAST
-- error condition has been relayed to the Write Status
-- Controller. This stop flag is used to prevent any more
-- pushes to the Write Status Controller.
--
-------------------------------------------------------------
IMP_TLAST_ERROR_STOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_tlast_err_stop <= '0';
elsif (sig_tlast_error_reg = '1' and
sig_push_to_wsc_cmplt = '1') then
sig_tlast_err_stop <= '1';
else
null; -- Hold State
end if;
end if;
end process IMP_TLAST_ERROR_STOP;
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INDET_BTT
--
-- If Generate Description:
-- Includes any Indeterminate BTT Support logic. Primarily
-- this is a counter for the input stream bytes received. The
-- received byte count is relayed to the Write Status Controller
-- for each parent command completed.
-- When a packet completion is indicated via the EOP marker
-- assertion, the status to the Write Status Controller also
-- indicates the EOP condition.
-- Note that underrun and overrun detection/error flagging
-- is disabled in Indeterminate BTT Mode.
--
------------------------------------------------------------
GEN_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
-- local constants
Constant BYTE_CNTR_WIDTH : integer := C_SF_BYTES_RCVD_WIDTH;
Constant NUM_ZEROS_WIDTH : integer := 8;
Constant BYTES_PER_DBEAT : integer := C_STREAM_DWIDTH/8;
Constant STRBGEN_ADDR_SLICE_WIDTH : integer :=
funct_get_dbeat_residue_width(BYTES_PER_DBEAT);
Constant STRBGEN_ADDR_0 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
-- local signals
signal lsig_byte_cntr : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_byte_cntr_incr_value : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_ld_byte_cntr : std_logic := '0';
signal lsig_incr_byte_cntr : std_logic := '0';
signal lsig_clr_byte_cntr : std_logic := '0';
signal lsig_end_of_cmd_reg : std_logic := '0';
signal lsig_eop_s_h_reg : std_logic := '0';
signal lsig_eop_reg : std_logic := '0';
signal sig_strbgen_addr : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_strbgen_bytes : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH downto 0) := (others => '0');
begin
-- Assign the outputs to the Write Status Controller
data2wsc_eop <= lsig_eop_reg and
not(sig_next_calc_error_reg);
data2wsc_bytes_rcvd <= STD_LOGIC_VECTOR(lsig_byte_cntr);
-- WRSTRB logic ------------------------------
--sig_strbgen_bytes <= (others => '1'); -- set to the max value
-- set the length to the max number of bytes per databeat
sig_strbgen_bytes <= STD_LOGIC_VECTOR(TO_UNSIGNED(BYTES_PER_DBEAT, STRBGEN_ADDR_SLICE_WIDTH+1));
sig_strbgen_addr <= STD_LOGIC_VECTOR(RESIZE(UNSIGNED(sig_fifo_next_sadddr_lsb),
STRBGEN_ADDR_SLICE_WIDTH)) ;
------------------------------------------------------------
-- Instance: I_STRT_STRB_GEN
--
-- Description:
-- Strobe generator used to generate the starting databeat
-- strobe value for soft shutdown case where the S2MM has to
-- flush out all of the transfers that have been committed
-- to the AXI Write address channel. Starting Strobes must
-- match the committed address offest for each transfer.
--
------------------------------------------------------------
I_STRT_STRB_GEN : entity axi_datamover_v5_1_9.axi_datamover_strb_gen2
generic map (
C_OP_MODE => 0 , -- 0 = Offset/Length mode
C_STRB_WIDTH => BYTES_PER_DBEAT ,
C_OFFSET_WIDTH => STRBGEN_ADDR_SLICE_WIDTH ,
C_NUM_BYTES_WIDTH => STRBGEN_ADDR_SLICE_WIDTH+1
)
port map (
start_addr_offset => sig_strbgen_addr ,
end_addr_offset => STRBGEN_ADDR_0 , -- not used in op mode 0
num_valid_bytes => sig_strbgen_bytes ,
strb_out => sig_sfhalt_next_strt_strb
);
-- Generate the WSTRB to use during soft shutdown
sig_halt_strb <= sig_strt_strb_reg
When (sig_first_dbeat = '1' or
sig_single_dbeat = '1')
Else (others => '1');
-- Generate the Write Strobes for the MMap Write Data Channel
-- for the Indeterminate BTT case. Strobes come from the Stream
-- input from the Indeterminate BTT module during normal operation.
-- However, during soft shutdown, those strobes become unpredictable
-- so generated strobes have to be used.
data2skid_wstrb <= sig_halt_strb
When (sig_halt_reg = '1')
Else s2mm_strm_wstrb;
-- Generate the Stream Ready for the Stream input side
sig_s2mm_strm_wready <= sig_halt_reg or -- force tready if a halt requested
(sig_mmap2data_ready and -- MMap is accepting the xfers
sig_addr_chan_rdy and -- xfers are commited on the address channel and
sig_dqual_rdy and -- there are commands in the command fifo
not(sig_calc_error_reg) and -- No internal error
not(sig_stop_wvalid)); -- Gate off stream ready immediately after a wlast for 1 clk
-- or when the soft shutdown has completed
-- MMap Write Data Channel Valid Handshaking
sig_data2mmap_valid <= (s2mm_strm_wvalid or -- Normal Stream input valid
sig_halt_reg ) and -- force valid if halt requested
sig_addr_chan_rdy and -- xfers are commited on the address channel and
sig_dqual_rdy and -- there are commands in the command fifo
not(sig_calc_error_reg) and -- No internal error
not(sig_stop_wvalid); -- Gate off wvalid immediately after a wlast for 1 clk
-- or when the soft shutdown has completed
-- TLAST Error housekeeping for Indeterminate BTT Mode
-- There is no Underrun/overrun in Stroe and Forward mode
sig_tlast_error_ovrrun <= '0'; -- Not used with Indeterminate BTT
sig_tlast_error_undrrun <= '0'; -- Not used with Indeterminate BTT
sig_end_stbs_match_err <= '0'; -- Not used with Indeterminate BTT
sig_tlast_error <= '0'; -- Not used with Indeterminate BTT
sig_tlast_error_reg <= '0'; -- Not used with Indeterminate BTT
sig_tlast_err_stop <= '0'; -- Not used with Indeterminate BTT
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOP_REG_FLOP
--
-- Process Description:
-- Register the End of Packet marker.
--
-------------------------------------------------------------
IMP_EOP_REG_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_end_of_cmd_reg <= '0';
lsig_eop_reg <= '0';
Elsif (sig_good_strm_dbeat = '1') Then
lsig_end_of_cmd_reg <= sig_next_cmd_cmplt_reg and
s2mm_strm_wlast;
lsig_eop_reg <= s2mm_strm_eop;
else
null; -- hold current state
end if;
end if;
end process IMP_EOP_REG_FLOP;
----- Byte Counter Logic -----------------------------------------------
-- The Byte counter reflects the actual byte count received on the
-- Stream input for each parent command loaded into the S2MM command
-- FIFO. Thus it counts input bytes until the command complete qualifier
-- is set and the TLAST input from the Stream input.
lsig_clr_byte_cntr <= lsig_end_of_cmd_reg and -- Clear if a new stream packet does not start
not(sig_good_strm_dbeat); -- immediately after the previous one finished.
lsig_ld_byte_cntr <= lsig_end_of_cmd_reg and -- Only load if a new stream packet starts
sig_good_strm_dbeat; -- immediately after the previous one finished.
lsig_incr_byte_cntr <= sig_good_strm_dbeat;
lsig_byte_cntr_incr_value <= RESIZE(UNSIGNED(s2mm_stbs_asserted),
BYTE_CNTR_WIDTH);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BYTE_CMTR
--
-- Process Description:
-- Keeps a running byte count per burst packet loaded into the
-- xfer FIFO. It is based on the strobes set on the incoming
-- Stream dbeat.
--
-------------------------------------------------------------
IMP_BYTE_CMTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
lsig_clr_byte_cntr = '1') then
lsig_byte_cntr <= (others => '0');
elsif (lsig_ld_byte_cntr = '1') then
lsig_byte_cntr <= lsig_byte_cntr_incr_value;
elsif (lsig_incr_byte_cntr = '1') then
lsig_byte_cntr <= lsig_byte_cntr + lsig_byte_cntr_incr_value;
else
null; -- hold current value
end if;
end if;
end process IMP_BYTE_CMTR;
end generate GEN_INDET_BTT;
-- Internal logic ------------------------------
sig_good_mmap_dbeat <= sig_mmap2data_ready and
sig_data2mmap_valid;
sig_last_mmap_dbeat <= sig_good_mmap_dbeat and
sig_data2mmap_last;
sig_get_next_dqual <= sig_last_mmap_dbeat;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_LAST_DBEAT
--
-- Process Description:
-- This implements a FLOP that creates a pulse
-- indicating the LAST signal for an outgoing write data channel
-- has been sent. Note that it is possible to have back to
-- back LAST databeats.
--
-------------------------------------------------------------
REG_LAST_DBEAT : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_last_mmap_dbeat_reg <= '0';
else
sig_last_mmap_dbeat_reg <= sig_last_mmap_dbeat;
end if;
end if;
end process REG_LAST_DBEAT;
----- Write Status Interface Stuff --------------------------
sig_push_to_wsc_cmplt <= sig_push_to_wsc and sig_wsc_ready;
sig_set_push2wsc <= (sig_good_mmap_dbeat and
sig_dbeat_cntr_eq_0) or
sig_push_err2wsc or
sig_spcl_push_err2wsc; -- Special case from CR616212
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_INTERR_PUSH_FLOP
--
-- Process Description:
-- Generate a 1 clock wide pulse when a calc error has propagated
-- from the Command Calculator. This pulse is used to force a
-- push of the error status to the Write Status Controller
-- without a AXI transfer completion.
--
-------------------------------------------------------------
IMP_INTERR_PUSH_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_push_err2wsc = '1') then
sig_push_err2wsc <= '0';
elsif (sig_ld_new_cmd_reg = '1' and
sig_calc_error_reg = '1') then
sig_push_err2wsc <= '1';
else
null; -- hold state
end if;
end if;
end process IMP_INTERR_PUSH_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PUSH2WSC_FLOP
--
-- Process Description:
-- Implements a Sample and hold register for the outbound status
-- signals to the Write Status Controller (WSC). This register
-- has to support back to back transfer completions.
--
-------------------------------------------------------------
IMP_PUSH2WSC_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(sig_push_to_wsc_cmplt = '1' and
sig_set_push2wsc = '0')) then
sig_push_to_wsc <= '0';
sig_data2wsc_tag <= (others => '0');
sig_data2wsc_calc_err <= '0';
sig_data2wsc_last_err <= '0';
sig_data2wsc_cmd_cmplt <= '0';
elsif (sig_set_push2wsc = '1' and
sig_tlast_err_stop = '0') then
sig_push_to_wsc <= '1';
sig_data2wsc_tag <= sig_tag_reg ;
sig_data2wsc_calc_err <= sig_calc_error_reg ;
sig_data2wsc_last_err <= sig_tlast_error_reg or
sig_tlast_error ;
sig_data2wsc_cmd_cmplt <= sig_cmd_cmplt_reg or
sig_tlast_error_reg or
sig_tlast_error ;
else
null; -- hold current state
end if;
end if;
end process IMP_PUSH2WSC_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_LD_NEW_CMD_REG
--
-- Process Description:
-- Registers the flag indicating a new command has been
-- loaded. Needs to be a 1 clk wide pulse.
--
-------------------------------------------------------------
IMP_LD_NEW_CMD_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_ld_new_cmd_reg = '1') then
sig_ld_new_cmd_reg <= '0';
else
sig_ld_new_cmd_reg <= sig_ld_new_cmd;
end if;
end if;
end process IMP_LD_NEW_CMD_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_NXT_LEN_REG
--
-- Process Description:
-- Registers the load control and length value for a command
-- passed to the WDC input command interface. The registered
-- signals are used for the external Indeterminate BTT support
-- ports.
--
-------------------------------------------------------------
IMP_NXT_LEN_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_s2mm_ld_nxt_len <= '0';
sig_s2mm_wr_len <= (others => '0');
else
sig_s2mm_ld_nxt_len <= mstr2data_cmd_valid and
sig_data2mstr_cmd_ready;
sig_s2mm_wr_len <= mstr2data_len;
end if;
end if;
end process IMP_NXT_LEN_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_DATA_CNTL_FIFO
--
-- If Generate Description:
-- Omits the input data control FIFO if the requested FIFO
-- depth is 1. The Data Qualifier Register serves as a
-- 1 deep FIFO by itself.
--
------------------------------------------------------------
GEN_NO_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH = 1) generate
begin
-- Command Calculator Handshake output
sig_data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_rd_cmd_valid <= mstr2data_cmd_valid ;
-- pre 13.1 sig_fifo_wr_cmd_ready <= sig_dqual_reg_empty and
-- pre 13.1 sig_aposted_cntr_ready and
-- pre 13.1 not(wsc2mstr_halt_pipe) and -- The Wr Status Controller is not stalling
-- pre 13.1 not(sig_calc_error_reg); -- the command execution pipe and there is
-- pre 13.1 -- no calculation error being propagated
sig_fifo_wr_cmd_ready <= sig_push_dqual_reg;
sig_fifo_next_tag <= mstr2data_tag ;
sig_fifo_next_sadddr_lsb <= mstr2data_saddr_lsb ;
sig_fifo_next_len <= mstr2data_len ;
sig_fifo_next_strt_strb <= mstr2data_strt_strb ;
sig_fifo_next_last_strb <= mstr2data_last_strb ;
sig_fifo_next_drr <= mstr2data_drr ;
sig_fifo_next_eof <= mstr2data_eof ;
sig_fifo_next_sequential <= mstr2data_sequential ;
sig_fifo_next_cmd_cmplt <= mstr2data_cmd_cmplt ;
sig_fifo_next_calc_error <= mstr2data_calc_error ;
end generate GEN_NO_DATA_CNTL_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_DATA_CNTL_FIFO
--
-- If Generate Description:
-- Includes the input data control FIFO if the requested
-- FIFO depth is more than 1.
--
------------------------------------------------------------
GEN_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH > 1) generate
begin
-- Command Calculator Handshake output
sig_data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_wr_cmd_valid <= mstr2data_cmd_valid ;
-- pop the fifo when dqual reg is pushed
sig_fifo_rd_cmd_ready <= sig_push_dqual_reg;
-- Format the input fifo data word
sig_cmd_fifo_data_in <= mstr2data_calc_error &
mstr2data_cmd_cmplt &
mstr2data_sequential &
mstr2data_eof &
mstr2data_drr &
mstr2data_last_strb &
mstr2data_strt_strb &
mstr2data_len &
mstr2data_saddr_lsb &
mstr2data_tag ;
-- Rip the output fifo data word
sig_fifo_next_tag <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto
TAG_STRT_INDEX);
sig_fifo_next_sadddr_lsb <= sig_cmd_fifo_data_out((SADDR_LSB_STRT_INDEX+SADDR_LSB_WIDTH)-1 downto
SADDR_LSB_STRT_INDEX);
sig_fifo_next_len <= sig_cmd_fifo_data_out((LEN_STRT_INDEX+LEN_WIDTH)-1 downto
LEN_STRT_INDEX);
sig_fifo_next_strt_strb <= sig_cmd_fifo_data_out((STRT_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
STRT_STRB_STRT_INDEX);
sig_fifo_next_last_strb <= sig_cmd_fifo_data_out((LAST_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
LAST_STRB_STRT_INDEX);
sig_fifo_next_drr <= sig_cmd_fifo_data_out(DRR_STRT_INDEX);
sig_fifo_next_eof <= sig_cmd_fifo_data_out(EOF_STRT_INDEX);
sig_fifo_next_sequential <= sig_cmd_fifo_data_out(SEQUENTIAL_STRT_INDEX);
sig_fifo_next_cmd_cmplt <= sig_cmd_fifo_data_out(CMD_CMPLT_STRT_INDEX);
sig_fifo_next_calc_error <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX);
------------------------------------------------------------
-- Instance: I_DATA_CNTL_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO
--
------------------------------------------------------------
I_DATA_CNTL_FIFO : entity axi_datamover_v5_1_9.axi_datamover_fifo
generic map (
C_DWIDTH => DCTL_FIFO_WIDTH ,
C_DEPTH => C_DATA_CNTL_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
fifo_wr_tready => sig_fifo_wr_cmd_ready ,
fifo_wr_tdata => sig_cmd_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
fifo_rd_tready => sig_fifo_rd_cmd_ready ,
fifo_rd_tdata => sig_cmd_fifo_data_out ,
fifo_rd_empty => sig_cmd_fifo_empty
);
end generate GEN_DATA_CNTL_FIFO;
-- Data Qualifier Register ------------------------------------
sig_ld_new_cmd <= sig_push_dqual_reg ;
sig_dqual_rdy <= sig_dqual_reg_full ;
sig_strt_strb_reg <= sig_next_strt_strb_reg ;
sig_last_strb_reg <= sig_next_last_strb_reg ;
sig_tag_reg <= sig_next_tag_reg ;
sig_cmd_cmplt_reg <= sig_next_cmd_cmplt_reg ;
sig_calc_error_reg <= sig_next_calc_error_reg ;
sig_cmd_is_eof <= sig_next_eof_reg ;
-- new for no bubbles between child requests
sig_sequential_push <= sig_good_mmap_dbeat and -- MMap handshake qualified
sig_last_dbeat and -- last data beat of transfer
sig_next_sequential_reg;-- next queued command is sequential
-- to the current command
-- pre 13.1 sig_push_dqual_reg <= (sig_sequential_push or
-- pre 13.1 sig_dqual_reg_empty) and
-- pre 13.1 sig_fifo_rd_cmd_valid and
-- pre 13.1 sig_aposted_cntr_ready and
-- pre 13.1 not(wsc2mstr_halt_pipe); -- The Wr Status Controller is not
-- pre 13.1 -- stalling the command execution pipe
sig_push_dqual_reg <= (sig_sequential_push or
sig_dqual_reg_empty) and
sig_fifo_rd_cmd_valid and
sig_aposted_cntr_ready and
not(sig_calc_error_reg) and -- 13.1 addition => An error has not been propagated
not(wsc2mstr_halt_pipe); -- The Wr Status Controller is not
-- stalling the command execution pipe
sig_pop_dqual_reg <= not(sig_next_calc_error_reg) and
sig_get_next_dqual and
sig_dqual_reg_full ;
-- new for no bubbles between child requests
sig_clr_dqual_reg <= mmap_reset or
(sig_pop_dqual_reg and
not(sig_push_dqual_reg));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DQUAL_REG
--
-- Process Description:
-- This process implements a register for the Data
-- Control and qualifiers. It operates like a 1 deep Sync FIFO.
--
-------------------------------------------------------------
IMP_DQUAL_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_clr_dqual_reg = '1') then
sig_next_tag_reg <= (others => '0');
sig_next_strt_strb_reg <= (others => '0');
sig_next_last_strb_reg <= (others => '0');
sig_next_eof_reg <= '0' ;
sig_next_sequential_reg <= '0' ;
sig_next_cmd_cmplt_reg <= '0' ;
sig_next_calc_error_reg <= '0' ;
sig_dqual_reg_empty <= '1' ;
sig_dqual_reg_full <= '0' ;
elsif (sig_push_dqual_reg = '1') then
sig_next_tag_reg <= sig_fifo_next_tag ;
sig_next_strt_strb_reg <= sig_sfhalt_next_strt_strb ;
sig_next_last_strb_reg <= sig_fifo_next_last_strb ;
sig_next_eof_reg <= sig_fifo_next_eof ;
sig_next_sequential_reg <= sig_fifo_next_sequential ;
sig_next_cmd_cmplt_reg <= sig_fifo_next_cmd_cmplt ;
sig_next_calc_error_reg <= sig_fifo_next_calc_error ;
sig_dqual_reg_empty <= '0';
sig_dqual_reg_full <= '1';
else
null; -- don't change state
end if;
end if;
end process IMP_DQUAL_REG;
-- Address LS Cntr logic --------------------------
sig_addr_lsb_reg <= STD_LOGIC_VECTOR(sig_ls_addr_cntr);
sig_addr_incr_unsgnd <= TO_UNSIGNED(ADDR_INCR_VALUE, C_SEL_ADDR_WIDTH);
sig_incr_ls_addr_cntr <= sig_good_mmap_dbeat;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_ADDR_LSB_CNTR
--
-- Process Description:
-- Implements the LS Address Counter used for controlling
-- the Write STRB DeMux during Burst transfers
--
-------------------------------------------------------------
DO_ADDR_LSB_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(sig_pop_dqual_reg = '1'and
sig_push_dqual_reg = '0')) then -- Clear the Counter
sig_ls_addr_cntr <= (others => '0');
elsif (sig_push_dqual_reg = '1') then -- Load the Counter
sig_ls_addr_cntr <= unsigned(sig_fifo_next_sadddr_lsb);
elsif (sig_incr_ls_addr_cntr = '1') then -- Increment the Counter
sig_ls_addr_cntr <= sig_ls_addr_cntr + sig_addr_incr_unsgnd;
else
null; -- Hold Current value
end if;
end if;
end process DO_ADDR_LSB_CNTR;
-- Address Posted Counter Logic --------------------------------------
sig_addr_chan_rdy <= not(sig_addr_posted_cntr_eq_0 or
sig_apc_going2zero) ; -- Gates data channel xfer handshake
sig_aposted_cntr_ready <= not(sig_addr_posted_cntr_max) ; -- Gates new command fetching
sig_no_posted_cmds <= sig_addr_posted_cntr_eq_0 ; -- Used for flushing cmds that are posted
sig_incr_addr_posted_cntr <= sig_addr_posted ;
sig_decr_addr_posted_cntr <= sig_last_mmap_dbeat_reg ;
sig_addr_posted_cntr_eq_0 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ZERO)
Else '0';
sig_addr_posted_cntr_max <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_MAX)
Else '0';
sig_addr_posted_cntr_eq_1 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ONE)
Else '0';
sig_apc_going2zero <= sig_addr_posted_cntr_eq_1 and
sig_decr_addr_posted_cntr and
not(sig_incr_addr_posted_cntr);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_POSTED_FIFO_CNTR
--
-- Process Description:
-- This process implements a counter for the tracking
-- if an Address has been posted on the AXI address channel.
-- The Data Controller must wait for an address to be posted
-- before proceeding with the corresponding data transfer on
-- the Data Channel. The counter is also used to track flushing
-- operations where all transfers commited on the AXI Address
-- Channel have to be completed before a halt can occur.
-------------------------------------------------------------
IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_addr_posted_cntr <= ADDR_POSTED_ZERO;
elsif (sig_incr_addr_posted_cntr = '1' and
sig_decr_addr_posted_cntr = '0' and
sig_addr_posted_cntr_max = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ;
elsif (sig_incr_addr_posted_cntr = '0' and
sig_decr_addr_posted_cntr = '1' and
sig_addr_posted_cntr_eq_0 = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_POSTED_FIFO_CNTR;
------- First/Middle/Last Dbeat detimination -------------------
sig_new_len_eq_0 <= '1'
When (sig_fifo_next_len = LEN_OF_ZERO)
else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_FIRST_MID_LAST
--
-- Process Description:
-- Implements the detection of the First/Mid/Last databeat of
-- a transfer.
--
-------------------------------------------------------------
DO_FIRST_MID_LAST : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_first_dbeat <= '0';
sig_last_dbeat <= '0';
sig_single_dbeat <= '0';
elsif (sig_ld_new_cmd = '1') then
sig_first_dbeat <= not(sig_new_len_eq_0);
sig_last_dbeat <= sig_new_len_eq_0;
sig_single_dbeat <= sig_new_len_eq_0;
Elsif (sig_dbeat_cntr_eq_1 = '1' and
sig_good_mmap_dbeat = '1') Then
sig_first_dbeat <= '0';
sig_last_dbeat <= '1';
sig_single_dbeat <= '0';
Elsif (sig_dbeat_cntr_eq_0 = '0' and
sig_dbeat_cntr_eq_1 = '0' and
sig_good_mmap_dbeat = '1') Then
sig_first_dbeat <= '0';
sig_last_dbeat <= '0';
sig_single_dbeat <= '0';
else
null; -- hold current state
end if;
end if;
end process DO_FIRST_MID_LAST;
------- Data Controller Halted Indication -------------------------------
data2all_dcntlr_halted <= sig_no_posted_cmds or
sig_calc_error_reg;
------- Data Beat counter logic -------------------------------
sig_dbeat_cntr_int <= TO_INTEGER(sig_dbeat_cntr);
sig_dbeat_cntr_eq_0 <= '1'
when (sig_dbeat_cntr_int = 0)
Else '0';
sig_dbeat_cntr_eq_1 <= '1'
when (sig_dbeat_cntr_int = 1)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_DBEAT_CNTR
--
-- Process Description:
-- Implements the transfer data beat counter used to track
-- progress of the transfer.
--
-------------------------------------------------------------
DO_DBEAT_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_dbeat_cntr <= (others => '0');
elsif (sig_ld_new_cmd = '1') then
sig_dbeat_cntr <= unsigned(sig_fifo_next_len);
Elsif (sig_good_mmap_dbeat = '1' and
sig_dbeat_cntr_eq_0 = '0') Then
sig_dbeat_cntr <= sig_dbeat_cntr-1;
else
null; -- Hold current state
end if;
end if;
end process DO_DBEAT_CNTR;
------- Soft Shutdown Logic -------------------------------
-- Formulate the soft shutdown complete flag
sig_data2rst_stop_cmplt <= (sig_halt_reg_dly3 and -- Normal Mode shutdown
sig_no_posted_cmds and
not(sig_calc_error_reg)) or
(sig_halt_reg_dly3 and -- Shutdown after error trap
sig_calc_error_reg);
-- Generate a gate signal to deassert the WVALID output
-- for 1 clock cycle after a WLAST is issued. This only
-- occurs when in soft shutdown mode.
sig_stop_wvalid <= (sig_last_mmap_dbeat_reg and
sig_halt_reg) or
sig_data2rst_stop_cmplt;
-- Assign the output port skid buf control for the
-- input Stream skid buffer
data2skid_halt <= sig_data2skid_halt;
-- Create a 1 clock wide pulse to tell the input
-- stream skid buffer to shut down.
sig_data2skid_halt <= sig_halt_reg_dly2 and
not(sig_halt_reg_dly3);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG
--
-- Process Description:
-- Implements the flop for capturing the Halt request from
-- the Reset module.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg <= '0';
elsif (rst2data_stop_request = '1') then
sig_halt_reg <= '1';
else
null; -- Hold current State
end if;
end if;
end process IMP_HALT_REQ_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG_DLY
--
-- Process Description:
-- Implements the flops for delaying the halt request by 3
-- clocks to allow the Address Controller to halt before the
-- Data Contoller can safely indicate it has exhausted all
-- transfers committed to the AXI Address Channel by the Address
-- Controller.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG_DLY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg_dly1 <= '0';
sig_halt_reg_dly2 <= '0';
sig_halt_reg_dly3 <= '0';
else
sig_halt_reg_dly1 <= sig_halt_reg;
sig_halt_reg_dly2 <= sig_halt_reg_dly1;
sig_halt_reg_dly3 <= sig_halt_reg_dly2;
end if;
end if;
end process IMP_HALT_REQ_REG_DLY;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_wrdata_cntl.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_wrdata_cntl.vhd
--
-- Description:
-- This file implements the DataMover Master Write Data Controller.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_9;
use axi_datamover_v5_1_9.axi_datamover_fifo;
use axi_datamover_v5_1_9.axi_datamover_strb_gen2;
-------------------------------------------------------------------------------
entity axi_datamover_wrdata_cntl is
generic (
C_REALIGNER_INCLUDED : Integer range 0 to 1 := 0;
-- Indicates the Data Realignment function is included (external
-- to this module)
C_ENABLE_INDET_BTT : Integer range 0 to 1 := 0;
-- Indicates the INDET BTT function is included (external
-- to this module)
C_SF_BYTES_RCVD_WIDTH : Integer range 1 to 23 := 1;
-- Sets the width of the data2wsc_bytes_rcvd port used for
-- relaying the actual number of bytes received when Idet BTT is
-- enabled (C_ENABLE_INDET_BTT = 1)
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
-- Sets the width of the LS bits of the transfer address that
-- are being used to Demux write data to a wider AXI4 Write
-- Data Bus
C_DATA_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 4;
-- Sets the depth of the internal command fifo used for the
-- command queue
C_MMAP_DWIDTH : Integer range 32 to 1024 := 32;
-- Indicates the native data width of the Read Data port
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Sets the width of the Stream output data port
C_TAG_WIDTH : Integer range 1 to 8 := 4;
-- Indicates the width of the Tag field of the input command
C_FAMILY : String := "virtex7"
-- Indicates the device family of the target FPGA
);
port (
-- Clock and Reset inputs ----------------------------------------------
--
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
------------------------------------------------------------------------
-- Soft Shutdown internal interface ------------------------------------
--
rst2data_stop_request : in std_logic; --
-- Active high soft stop request to modules --
--
data2addr_stop_req : Out std_logic; --
-- Active high signal requesting the Address Controller --
-- to stop posting commands to the AXI Read Address Channel --
--
data2rst_stop_cmplt : Out std_logic; --
-- Active high indication that the Data Controller has completed --
-- any pending transfers committed by the Address Controller --
-- after a stop has been requested by the Reset module. --
------------------------------------------------------------------------
-- Store and Forward support signals for external User logic ------------
--
wr_xfer_cmplt : Out std_logic; --
-- Active high indication that the Data Controller has completed --
-- a single write data transfer on the AXI4 Write Data Channel. --
-- This signal is escentially echos the assertion of wlast sent --
-- to the AXI4. --
--
s2mm_ld_nxt_len : out std_logic; --
-- Active high pulse indicating a new xfer length has been queued --
-- to the WDC Cmd FIFO --
--
s2mm_wr_len : out std_logic_vector(7 downto 0); --
-- Bus indicating the AXI LEN value associated with the xfer command --
-- loaded into the WDC Command FIFO. --
-------------------------------------------------------------------------
-- AXI Write Data Channel Skid buffer I/O ---------------------------------------
--
data2skid_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- Write DATA output to skid buffer --
--
data2skid_wdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- Write DATA output to skid buffer --
--
data2skid_wstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- Write DATA output to skid buffer --
--
data2skid_wlast : Out std_logic; --
-- Write LAST output to skid buffer --
--
data2skid_wvalid : Out std_logic; --
-- Write VALID output to skid buffer --
--
skid2data_wready : In std_logic; --
-- Write READY input from skid buffer --
----------------------------------------------------------------------------------
-- AXI Slave Stream In -----------------------------------------------------------
--
s2mm_strm_wvalid : In std_logic; --
-- AXI Stream VALID input --
--
s2mm_strm_wready : Out Std_logic; --
-- AXI Stream READY Output --
--
s2mm_strm_wdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- AXI Stream data input --
--
s2mm_strm_wstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- AXI Stream STRB input --
--
s2mm_strm_wlast : In std_logic; --
-- AXI Stream LAST input --
----------------------------------------------------------------------------------
-- Stream input sideband signal from Indeterminate BTT and/or DRE ----------------
--
s2mm_strm_eop : In std_logic; --
-- Stream End of Packet marker input. This is only used when Indeterminate --
-- BTT mode is enable. Otherwise it is ignored --
--
--
s2mm_stbs_asserted : in std_logic_vector(7 downto 0); --
-- Indicates the number of asserted WSTRB bits for the --
-- associated input stream data beat --
--
--
-- Realigner Underrun/overrun error flag used in non Indeterminate BTT --
-- Mode --
realign2wdc_eop_error : In std_logic ; --
-- Asserted active high and will only clear with reset. It is only used --
-- when Indeterminate BTT is not enabled and the Realigner Module is --
-- instantiated upstream from the WDC. The Realigner will detect overrun --
-- underrun conditions and will will relay these conditions via this signal. --
----------------------------------------------------------------------------------
-- Command Calculator Interface --------------------------------------------------
--
mstr2data_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The next command tag --
--
mstr2data_saddr_lsb : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0); --
-- The next command start address LSbs to use for the write strb --
-- demux (only used if Stream data width is less than the MMap Dwidth). --
--
mstr2data_len : In std_logic_vector(7 downto 0); --
-- The LEN value output to the Address Channel --
--
mstr2data_strt_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The starting strobe value to use for the first stream data beat --
--
mstr2data_last_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- The endiing (LAST) strobe value to use for the last stream --
-- data beat --
--
mstr2data_drr : In std_logic; --
-- The starting tranfer of a sequence of transfers --
--
mstr2data_eof : In std_logic; --
-- The endiing tranfer of a sequence of transfers --
--
mstr2data_sequential : In std_logic; --
-- The next sequential tranfer of a sequence of transfers --
-- spawned from a single parent command --
--
mstr2data_calc_error : In std_logic; --
-- Indication if the next command in the calculation pipe --
-- has a calculation error --
--
mstr2data_cmd_cmplt : In std_logic; --
-- The final child tranfer of a parent command fetched from --
-- the Command FIFO (not necessarily an EOF command) --
--
mstr2data_cmd_valid : In std_logic; --
-- The next command valid indication to the Data Channel --
-- Controller for the AXI MMap --
--
data2mstr_cmd_ready : Out std_logic ; --
-- Indication from the Data Channel Controller that the --
-- command is being accepted on the AXI Address --
-- Channel --
----------------------------------------------------------------------------------
-- Address Controller Interface --------------------------------------------------
--
addr2data_addr_posted : In std_logic ; --
-- Indication from the Address Channel Controller to the --
-- Data Controller that an address has been posted to the --
-- AXI Address Channel --
--
--
data2addr_data_rdy : out std_logic; --
-- Indication that the Data Channel is ready to send the first --
-- databeat of the next command on the write data channel. --
-- This is used for the "wait for data" feature which keeps the --
-- address controller from issuing a transfer request until the --
-- corresponding data valid is asserted on the stream input. The --
-- WDC will continue to assert the output until an assertion on --
-- the addr2data_addr_posted is received. --
---------------------------------------------------------------------------------
-- Premature TLAST assertion error flag ------------------------------------------
--
data2all_tlast_error : Out std_logic; --
-- When asserted, this indicates the data controller detected --
-- a premature TLAST assertion on the incoming data stream. --
---------------------------------------------------------------------------------
-- Data Controller Halted Status -------------------------------------------------
--
data2all_dcntlr_halted : Out std_logic; --
-- When asserted, this indicates the data controller has satisfied --
-- all pending transfers queued by the Address Controller and is halted. --
----------------------------------------------------------------------------------
-- Input Stream Skid Buffer Halt control -----------------------------------------
--
data2skid_halt : Out std_logic; --
-- The data controller asserts this output for 1 primary clock period --
-- The pulse commands the MM2S Stream skid buffer to tun off outputs --
-- at the next tlast transmission. --
----------------------------------------------------------------------------------
-- Write Status Controller Interface ---------------------------------------------
--
data2wsc_tag : Out std_logic_vector(C_TAG_WIDTH-1 downto 0); --
-- The command tag --
--
data2wsc_calc_err : Out std_logic ; --
-- Indication that the current command out from the Cntl FIFO --
-- has a calculation error --
--
data2wsc_last_err : Out std_logic ; --
-- Indication that the current write transfer encountered a premature --
-- TLAST assertion on the incoming Stream Channel --
--
data2wsc_cmd_cmplt : Out std_logic ; --
-- Indication by the Data Channel Controller that the --
-- corresponding status is the last status for a command --
-- pulled from the command FIFO --
--
wsc2data_ready : in std_logic; --
-- Input from the Write Status Module indicating that the --
-- Status Reg/FIFO is ready to accept data --
--
data2wsc_valid : Out std_logic; --
-- Output to the Command/Status Module indicating that the --
-- Data Controller has valid tag and err indicators to write --
-- to the Status module --
--
data2wsc_eop : Out std_logic; --
-- Output to the Write Status Controller indicating that the --
-- associated command status also corresponds to a End of Packet --
-- marker for the input Stream. This is only used when Inderminate --
-- BTT is enabled in the S2MM. --
--
data2wsc_bytes_rcvd : Out std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0); --
-- Output to the Write Status Controller indicating the actual --
-- number of bytes received from the Stream input for the --
-- corresponding command status. This is only used when Inderminate --
-- BTT is enabled in the S2MM. --
--
wsc2mstr_halt_pipe : In std_logic --
-- Indication to Halt the Data and Address Command pipeline due --
-- to the Status FIFO going full or an internal error being logged --
----------------------------------------------------------------------------------
);
end entity axi_datamover_wrdata_cntl;
architecture implementation of axi_datamover_wrdata_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declaration ----------------------------------------
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_dbeat_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_dbeat_residue_width (bytes_per_beat : integer) return integer is
Variable temp_dbeat_residue_width : Integer := 0; -- 8-bit stream
begin
case bytes_per_beat is
when 128 => -- 1024 bits -- Added per Per CR616409
temp_dbeat_residue_width := 7; -- Added per Per CR616409
when 64 => -- 512 bits -- Added per Per CR616409
temp_dbeat_residue_width := 6; -- Added per Per CR616409
when 32 => -- 256 bits
temp_dbeat_residue_width := 5;
when 16 => -- 128 bits
temp_dbeat_residue_width := 4;
when 8 => -- 64 bits
temp_dbeat_residue_width := 3;
when 4 => -- 32 bits
temp_dbeat_residue_width := 2;
when 2 => -- 16 bits
temp_dbeat_residue_width := 1;
when others => -- assume 1-byte transfers
temp_dbeat_residue_width := 0;
end case;
Return (temp_dbeat_residue_width);
end function funct_get_dbeat_residue_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_cnt_width
--
-- Function Description:
-- Sets a count width based on a fifo depth. A depth of 4 or less
-- is a special case which requires a minimum count width of 3 bits.
--
-------------------------------------------------------------------
function funct_set_cnt_width (fifo_depth : integer) return integer is
Variable temp_cnt_width : Integer := 4;
begin
if (fifo_depth <= 4) then
temp_cnt_width := 3;
elsif (fifo_depth <= 8) then
temp_cnt_width := 4;
elsif (fifo_depth <= 16) then
temp_cnt_width := 5;
elsif (fifo_depth <= 32) then
temp_cnt_width := 6;
else -- fifo depth <= 64
temp_cnt_width := 7;
end if;
Return (temp_cnt_width);
end function funct_set_cnt_width;
-- Constant Declarations --------------------------------------------
Constant STRM_STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant LEN_OF_ZERO : std_logic_vector(7 downto 0) := (others => '0');
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant SADDR_LSB_WIDTH : integer := C_SEL_ADDR_WIDTH;
Constant LEN_WIDTH : integer := 8;
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant DRR_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant CMD_CMPLT_WIDTH : integer := 1;
Constant SEQUENTIAL_WIDTH : integer := 1;
Constant DCTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
SADDR_LSB_WIDTH + -- LS Address field width
LEN_WIDTH + -- LEN field
STRB_WIDTH + -- Starting Strobe field
STRB_WIDTH + -- Ending Strobe field
DRR_WIDTH + -- DRE Re-alignment Request Flag Field
EOF_WIDTH + -- EOF flag field
SEQUENTIAL_WIDTH + -- Sequential command flag
CMD_CMPLT_WIDTH + -- Command Complete Flag
CALC_ERR_WIDTH; -- Calc error flag
Constant TAG_STRT_INDEX : integer := 0;
Constant SADDR_LSB_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant LEN_STRT_INDEX : integer := SADDR_LSB_STRT_INDEX + SADDR_LSB_WIDTH;
Constant STRT_STRB_STRT_INDEX : integer := LEN_STRT_INDEX + LEN_WIDTH;
Constant LAST_STRB_STRT_INDEX : integer := STRT_STRB_STRT_INDEX + STRB_WIDTH;
Constant DRR_STRT_INDEX : integer := LAST_STRB_STRT_INDEX + STRB_WIDTH;
Constant EOF_STRT_INDEX : integer := DRR_STRT_INDEX + DRR_WIDTH;
Constant SEQUENTIAL_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant CMD_CMPLT_STRT_INDEX : integer := SEQUENTIAL_STRT_INDEX+SEQUENTIAL_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := CMD_CMPLT_STRT_INDEX+CMD_CMPLT_WIDTH;
Constant ADDR_INCR_VALUE : integer := C_STREAM_DWIDTH/8;
Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_DATA_CNTL_FIFO_DEPTH);
Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '0');
Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH);
Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '1');
-- Signal Declarations --------------------------------------------
signal sig_get_next_dqual : std_logic := '0';
signal sig_last_mmap_dbeat : std_logic := '0';
signal sig_last_mmap_dbeat_reg : std_logic := '0';
signal sig_mmap2data_ready : std_logic := '0';
signal sig_data2mmap_valid : std_logic := '0';
signal sig_data2mmap_last : std_logic := '0';
signal sig_data2mmap_data : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_ld_new_cmd : std_logic := '0';
signal sig_ld_new_cmd_reg : std_logic := '0';
signal sig_cmd_cmplt_reg : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_lsb_reg : std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted : std_logic := '0';
signal sig_dqual_rdy : std_logic := '0';
signal sig_good_mmap_dbeat : std_logic := '0';
signal sig_first_dbeat : std_logic := '0';
signal sig_last_dbeat : std_logic := '0';
signal sig_single_dbeat : std_logic := '0';
signal sig_new_len_eq_0 : std_logic := '0';
signal sig_dbeat_cntr : unsigned(7 downto 0) := (others => '0');
Signal sig_dbeat_cntr_int : Integer range 0 to 255 := 0;
signal sig_dbeat_cntr_eq_0 : std_logic := '0';
signal sig_dbeat_cntr_eq_1 : std_logic := '0';
signal sig_wsc_ready : std_logic := '0';
signal sig_push_to_wsc : std_logic := '0';
signal sig_push_to_wsc_cmplt : std_logic := '0';
signal sig_set_push2wsc : std_logic := '0';
signal sig_data2wsc_tag : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2wsc_calc_err : std_logic := '0';
signal sig_data2wsc_last_err : std_logic := '0';
signal sig_data2wsc_cmd_cmplt : std_logic := '0';
signal sig_tlast_error : std_logic := '0';
signal sig_tlast_error_strbs : std_logic := '0';
signal sig_end_stbs_match_err : std_logic := '0';
signal sig_tlast_error_reg : std_logic := '0';
signal sig_cmd_is_eof : std_logic := '0';
signal sig_push_err2wsc : std_logic := '0';
signal sig_tlast_error_ovrrun : std_logic := '0';
signal sig_tlast_error_undrrun : std_logic := '0';
signal sig_next_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_eof_reg : std_logic := '0';
signal sig_next_sequential_reg : std_logic := '0';
signal sig_next_cmd_cmplt_reg : std_logic := '0';
signal sig_next_calc_error_reg : std_logic := '0';
signal sig_pop_dqual_reg : std_logic := '0';
signal sig_push_dqual_reg : std_logic := '0';
signal sig_dqual_reg_empty : std_logic := '0';
signal sig_dqual_reg_full : std_logic := '0';
signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted_cntr_eq_0 : std_logic := '0';
signal sig_addr_posted_cntr_max : std_logic := '0';
signal sig_decr_addr_posted_cntr : std_logic := '0';
signal sig_incr_addr_posted_cntr : std_logic := '0';
signal sig_addr_posted_cntr_eq_1 : std_logic := '0';
signal sig_apc_going2zero : std_logic := '0';
signal sig_aposted_cntr_ready : std_logic := '0';
signal sig_addr_chan_rdy : std_logic := '0';
Signal sig_no_posted_cmds : std_logic := '0';
signal sig_ls_addr_cntr : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_ls_addr_cntr : std_logic := '0';
signal sig_addr_incr_unsgnd : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
Signal sig_cmd_fifo_data_in : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0) := (others => '0');
Signal sig_cmd_fifo_data_out : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_tag : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_sadddr_lsb : std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_fifo_next_strt_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_last_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_drr : std_logic := '0';
signal sig_fifo_next_eof : std_logic := '0';
signal sig_fifo_next_cmd_cmplt : std_logic := '0';
signal sig_fifo_next_sequential : std_logic := '0';
signal sig_fifo_next_calc_error : std_logic := '0';
signal sig_cmd_fifo_empty : std_logic := '0';
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_sequential_push : std_logic := '0';
signal sig_clr_dqual_reg : std_logic := '0';
signal sig_tlast_err_stop : std_logic := '0';
signal sig_halt_reg : std_logic := '0';
signal sig_halt_reg_dly1 : std_logic := '0';
signal sig_halt_reg_dly2 : std_logic := '0';
signal sig_halt_reg_dly3 : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_stop_wvalid : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_s2mm_strm_wready : std_logic := '0';
signal sig_good_strm_dbeat : std_logic := '0';
signal sig_halt_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_sfhalt_next_strt_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_wfd_simult_clr_set : std_logic := '0';
signal sig_wr_xfer_cmplt : std_logic := '0';
signal sig_s2mm_ld_nxt_len : std_logic := '0';
signal sig_s2mm_wr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_data2mstr_cmd_ready : std_logic := '0';
signal sig_spcl_push_err2wsc : std_logic := '0';
begin --(architecture implementation)
-- Command calculator handshake
data2mstr_cmd_ready <= sig_data2mstr_cmd_ready;
-- Write Data Channel Skid Buffer Port assignments
sig_mmap2data_ready <= skid2data_wready ;
data2skid_wvalid <= sig_data2mmap_valid ;
data2skid_wlast <= sig_data2mmap_last ;
data2skid_wdata <= sig_data2mmap_data ;
data2skid_saddr_lsb <= sig_addr_lsb_reg ;
-- AXI MM2S Stream Channel Port assignments
sig_data2mmap_data <= s2mm_strm_wdata ;
-- Premature TLAST assertion indication
data2all_tlast_error <= sig_tlast_error_reg ;
-- Stream Input Ready Handshake
s2mm_strm_wready <= sig_s2mm_strm_wready ;
sig_good_strm_dbeat <= s2mm_strm_wvalid and
sig_s2mm_strm_wready;
sig_data2mmap_last <= sig_dbeat_cntr_eq_0 and
sig_dqual_rdy;
-- Write Status Block interface signals
data2wsc_valid <= sig_push_to_wsc and
not(sig_tlast_err_stop) ; -- only allow 1 status write on TLAST errror
sig_wsc_ready <= wsc2data_ready ;
data2wsc_tag <= sig_data2wsc_tag ;
data2wsc_calc_err <= sig_data2wsc_calc_err ;
data2wsc_last_err <= sig_data2wsc_last_err ;
data2wsc_cmd_cmplt <= sig_data2wsc_cmd_cmplt ;
-- Address Channel Controller synchro pulse input
sig_addr_posted <= addr2data_addr_posted;
-- Request to halt the Address Channel Controller
data2addr_stop_req <= sig_halt_reg or
sig_tlast_error_reg;
-- Halted flag to the reset module
data2rst_stop_cmplt <= sig_data2rst_stop_cmplt;
-- Indicate the Write Data Controller is always ready
data2addr_data_rdy <= '1';
-- Write Transfer Completed Status output
wr_xfer_cmplt <= sig_wr_xfer_cmplt ;
-- New LEN value is being loaded
s2mm_ld_nxt_len <= sig_s2mm_ld_nxt_len;
-- The new LEN value
s2mm_wr_len <= sig_s2mm_wr_len;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_WR_CMPLT_FLAG
--
-- Process Description:
-- Implements the status flag indicating that a write data
-- transfer has completed. This is an echo of a wlast assertion
-- and a qualified data beat on the AXI4 Write Data Channel.
--
-------------------------------------------------------------
IMP_WR_CMPLT_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_wr_xfer_cmplt <= '0';
else
sig_wr_xfer_cmplt <= sig_data2mmap_last and
sig_good_strm_dbeat;
end if;
end if;
end process IMP_WR_CMPLT_FLAG;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_INDET_BTT
--
-- If Generate Description:
-- Omits any Indeterminate BTT Support logic and includes
-- any error detection needed in Non Indeterminate BTT mode.
--
------------------------------------------------------------
GEN_OMIT_INDET_BTT : if (C_ENABLE_INDET_BTT = 0) generate
begin
sig_sfhalt_next_strt_strb <= sig_fifo_next_strt_strb;
-- Just housekeep the output port signals
data2wsc_eop <= '0';
data2wsc_bytes_rcvd <= (others => '0');
-- WRSTRB logic ------------------------------
-- Generate the Write Strobes for the MMap Write Data Channel
-- for the non Indeterminate BTT Case
data2skid_wstrb <= sig_strt_strb_reg
When (sig_first_dbeat = '1')
Else sig_last_strb_reg
When (sig_last_dbeat = '1')
Else (others => '1');
-- Generate the Stream Ready for the Stream input side
sig_s2mm_strm_wready <= sig_halt_reg or -- force tready if a halt requested
(sig_mmap2data_ready and
sig_addr_chan_rdy and -- This puts combinational logic in the stream WREADY path
sig_dqual_rdy and
not(sig_calc_error_reg) and
not(sig_tlast_error_reg)); -- Stop the stream channel at a overrun/underrun detection
-- MMap Write Data Channel Valid Handshaking
sig_data2mmap_valid <= (s2mm_strm_wvalid or
sig_tlast_error_reg or -- force valid if TLAST error
sig_halt_reg ) and -- force valid if halt requested
sig_addr_chan_rdy and -- xfers are commited on the address channel and
sig_dqual_rdy and -- there are commands in the command fifo
not(sig_calc_error_reg) and
not(sig_stop_wvalid); -- gate off wvalid immediately after a wlast for 1 clk
-- or when the soft shutdown has completed
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LOCAL_ERR_DETECT
--
-- If Generate Description:
-- Implements the local overrun and underrun detection when
-- the S2MM Realigner is not included.
--
--
------------------------------------------------------------
GEN_LOCAL_ERR_DETECT : if (C_REALIGNER_INCLUDED = 0) generate
begin
------- Input Stream TLAST assertion error -------------------------------
sig_tlast_error_ovrrun <= sig_cmd_is_eof and
sig_dbeat_cntr_eq_0 and
sig_good_mmap_dbeat and
not(s2mm_strm_wlast);
sig_tlast_error_undrrun <= s2mm_strm_wlast and
sig_good_mmap_dbeat and
(not(sig_dbeat_cntr_eq_0) or
not(sig_cmd_is_eof));
sig_end_stbs_match_err <= '1' -- Set flag if the calculated end strobe value
When ((s2mm_strm_wstrb /= sig_next_last_strb_reg) and -- does not match the received strobe value
(s2mm_strm_wlast = '1') and -- at TLAST assertion
(sig_good_mmap_dbeat = '1')) -- Qualified databeat
Else '0';
sig_tlast_error <= (sig_tlast_error_ovrrun or
sig_tlast_error_undrrun or
sig_end_stbs_match_err) and
not(sig_halt_reg); -- Suppress TLAST error when in soft shutdown
-- Just housekeep this when local TLAST error detection is used
sig_spcl_push_err2wsc <= '0';
end generate GEN_LOCAL_ERR_DETECT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_EXTERN_ERR_DETECT
--
-- If Generate Description:
-- Omits the local overrun and underrun detection and relies
-- on the S2MM Realigner for the detection.
--
------------------------------------------------------------
GEN_EXTERN_ERR_DETECT : if (C_REALIGNER_INCLUDED = 1) generate
begin
sig_tlast_error_undrrun <= '0'; -- not used here
sig_tlast_error_ovrrun <= '0'; -- not used here
sig_end_stbs_match_err <= '0'; -- not used here
sig_tlast_error <= realign2wdc_eop_error and -- External error detection asserted
not(sig_halt_reg); -- Suppress TLAST error when in soft shutdown
-- Special case for pushing error status when timing is such that no
-- addresses have been posted to AXI and a TLAST error has been detected
-- by the Realigner module and propagated in from the Stream input side.
sig_spcl_push_err2wsc <= sig_tlast_error_reg and
not(sig_tlast_err_stop) and
not(sig_addr_chan_rdy );
end generate GEN_EXTERN_ERR_DETECT;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERR_REG
--
-- Process Description:
-- Implements a sample and hold flop for the flag indicating
-- that the input Stream TLAST assertion was not at the expected
-- data beat relative to the commanded number of databeats
-- from the associated command from the SCC or PCC.
-------------------------------------------------------------
IMP_TLAST_ERR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_tlast_error_reg <= '0';
elsif (sig_tlast_error = '1') then
sig_tlast_error_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_TLAST_ERR_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERROR_STOP
--
-- Process Description:
-- Implements the flop to generate a stop flag once the TLAST
-- error condition has been relayed to the Write Status
-- Controller. This stop flag is used to prevent any more
-- pushes to the Write Status Controller.
--
-------------------------------------------------------------
IMP_TLAST_ERROR_STOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_tlast_err_stop <= '0';
elsif (sig_tlast_error_reg = '1' and
sig_push_to_wsc_cmplt = '1') then
sig_tlast_err_stop <= '1';
else
null; -- Hold State
end if;
end if;
end process IMP_TLAST_ERROR_STOP;
end generate GEN_OMIT_INDET_BTT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_INDET_BTT
--
-- If Generate Description:
-- Includes any Indeterminate BTT Support logic. Primarily
-- this is a counter for the input stream bytes received. The
-- received byte count is relayed to the Write Status Controller
-- for each parent command completed.
-- When a packet completion is indicated via the EOP marker
-- assertion, the status to the Write Status Controller also
-- indicates the EOP condition.
-- Note that underrun and overrun detection/error flagging
-- is disabled in Indeterminate BTT Mode.
--
------------------------------------------------------------
GEN_INDET_BTT : if (C_ENABLE_INDET_BTT = 1) generate
-- local constants
Constant BYTE_CNTR_WIDTH : integer := C_SF_BYTES_RCVD_WIDTH;
Constant NUM_ZEROS_WIDTH : integer := 8;
Constant BYTES_PER_DBEAT : integer := C_STREAM_DWIDTH/8;
Constant STRBGEN_ADDR_SLICE_WIDTH : integer :=
funct_get_dbeat_residue_width(BYTES_PER_DBEAT);
Constant STRBGEN_ADDR_0 : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
-- local signals
signal lsig_byte_cntr : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_byte_cntr_incr_value : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_ld_byte_cntr : std_logic := '0';
signal lsig_incr_byte_cntr : std_logic := '0';
signal lsig_clr_byte_cntr : std_logic := '0';
signal lsig_end_of_cmd_reg : std_logic := '0';
signal lsig_eop_s_h_reg : std_logic := '0';
signal lsig_eop_reg : std_logic := '0';
signal sig_strbgen_addr : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_strbgen_bytes : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH downto 0) := (others => '0');
begin
-- Assign the outputs to the Write Status Controller
data2wsc_eop <= lsig_eop_reg and
not(sig_next_calc_error_reg);
data2wsc_bytes_rcvd <= STD_LOGIC_VECTOR(lsig_byte_cntr);
-- WRSTRB logic ------------------------------
--sig_strbgen_bytes <= (others => '1'); -- set to the max value
-- set the length to the max number of bytes per databeat
sig_strbgen_bytes <= STD_LOGIC_VECTOR(TO_UNSIGNED(BYTES_PER_DBEAT, STRBGEN_ADDR_SLICE_WIDTH+1));
sig_strbgen_addr <= STD_LOGIC_VECTOR(RESIZE(UNSIGNED(sig_fifo_next_sadddr_lsb),
STRBGEN_ADDR_SLICE_WIDTH)) ;
------------------------------------------------------------
-- Instance: I_STRT_STRB_GEN
--
-- Description:
-- Strobe generator used to generate the starting databeat
-- strobe value for soft shutdown case where the S2MM has to
-- flush out all of the transfers that have been committed
-- to the AXI Write address channel. Starting Strobes must
-- match the committed address offest for each transfer.
--
------------------------------------------------------------
I_STRT_STRB_GEN : entity axi_datamover_v5_1_9.axi_datamover_strb_gen2
generic map (
C_OP_MODE => 0 , -- 0 = Offset/Length mode
C_STRB_WIDTH => BYTES_PER_DBEAT ,
C_OFFSET_WIDTH => STRBGEN_ADDR_SLICE_WIDTH ,
C_NUM_BYTES_WIDTH => STRBGEN_ADDR_SLICE_WIDTH+1
)
port map (
start_addr_offset => sig_strbgen_addr ,
end_addr_offset => STRBGEN_ADDR_0 , -- not used in op mode 0
num_valid_bytes => sig_strbgen_bytes ,
strb_out => sig_sfhalt_next_strt_strb
);
-- Generate the WSTRB to use during soft shutdown
sig_halt_strb <= sig_strt_strb_reg
When (sig_first_dbeat = '1' or
sig_single_dbeat = '1')
Else (others => '1');
-- Generate the Write Strobes for the MMap Write Data Channel
-- for the Indeterminate BTT case. Strobes come from the Stream
-- input from the Indeterminate BTT module during normal operation.
-- However, during soft shutdown, those strobes become unpredictable
-- so generated strobes have to be used.
data2skid_wstrb <= sig_halt_strb
When (sig_halt_reg = '1')
Else s2mm_strm_wstrb;
-- Generate the Stream Ready for the Stream input side
sig_s2mm_strm_wready <= sig_halt_reg or -- force tready if a halt requested
(sig_mmap2data_ready and -- MMap is accepting the xfers
sig_addr_chan_rdy and -- xfers are commited on the address channel and
sig_dqual_rdy and -- there are commands in the command fifo
not(sig_calc_error_reg) and -- No internal error
not(sig_stop_wvalid)); -- Gate off stream ready immediately after a wlast for 1 clk
-- or when the soft shutdown has completed
-- MMap Write Data Channel Valid Handshaking
sig_data2mmap_valid <= (s2mm_strm_wvalid or -- Normal Stream input valid
sig_halt_reg ) and -- force valid if halt requested
sig_addr_chan_rdy and -- xfers are commited on the address channel and
sig_dqual_rdy and -- there are commands in the command fifo
not(sig_calc_error_reg) and -- No internal error
not(sig_stop_wvalid); -- Gate off wvalid immediately after a wlast for 1 clk
-- or when the soft shutdown has completed
-- TLAST Error housekeeping for Indeterminate BTT Mode
-- There is no Underrun/overrun in Stroe and Forward mode
sig_tlast_error_ovrrun <= '0'; -- Not used with Indeterminate BTT
sig_tlast_error_undrrun <= '0'; -- Not used with Indeterminate BTT
sig_end_stbs_match_err <= '0'; -- Not used with Indeterminate BTT
sig_tlast_error <= '0'; -- Not used with Indeterminate BTT
sig_tlast_error_reg <= '0'; -- Not used with Indeterminate BTT
sig_tlast_err_stop <= '0'; -- Not used with Indeterminate BTT
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOP_REG_FLOP
--
-- Process Description:
-- Register the End of Packet marker.
--
-------------------------------------------------------------
IMP_EOP_REG_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_end_of_cmd_reg <= '0';
lsig_eop_reg <= '0';
Elsif (sig_good_strm_dbeat = '1') Then
lsig_end_of_cmd_reg <= sig_next_cmd_cmplt_reg and
s2mm_strm_wlast;
lsig_eop_reg <= s2mm_strm_eop;
else
null; -- hold current state
end if;
end if;
end process IMP_EOP_REG_FLOP;
----- Byte Counter Logic -----------------------------------------------
-- The Byte counter reflects the actual byte count received on the
-- Stream input for each parent command loaded into the S2MM command
-- FIFO. Thus it counts input bytes until the command complete qualifier
-- is set and the TLAST input from the Stream input.
lsig_clr_byte_cntr <= lsig_end_of_cmd_reg and -- Clear if a new stream packet does not start
not(sig_good_strm_dbeat); -- immediately after the previous one finished.
lsig_ld_byte_cntr <= lsig_end_of_cmd_reg and -- Only load if a new stream packet starts
sig_good_strm_dbeat; -- immediately after the previous one finished.
lsig_incr_byte_cntr <= sig_good_strm_dbeat;
lsig_byte_cntr_incr_value <= RESIZE(UNSIGNED(s2mm_stbs_asserted),
BYTE_CNTR_WIDTH);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BYTE_CMTR
--
-- Process Description:
-- Keeps a running byte count per burst packet loaded into the
-- xfer FIFO. It is based on the strobes set on the incoming
-- Stream dbeat.
--
-------------------------------------------------------------
IMP_BYTE_CMTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
lsig_clr_byte_cntr = '1') then
lsig_byte_cntr <= (others => '0');
elsif (lsig_ld_byte_cntr = '1') then
lsig_byte_cntr <= lsig_byte_cntr_incr_value;
elsif (lsig_incr_byte_cntr = '1') then
lsig_byte_cntr <= lsig_byte_cntr + lsig_byte_cntr_incr_value;
else
null; -- hold current value
end if;
end if;
end process IMP_BYTE_CMTR;
end generate GEN_INDET_BTT;
-- Internal logic ------------------------------
sig_good_mmap_dbeat <= sig_mmap2data_ready and
sig_data2mmap_valid;
sig_last_mmap_dbeat <= sig_good_mmap_dbeat and
sig_data2mmap_last;
sig_get_next_dqual <= sig_last_mmap_dbeat;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_LAST_DBEAT
--
-- Process Description:
-- This implements a FLOP that creates a pulse
-- indicating the LAST signal for an outgoing write data channel
-- has been sent. Note that it is possible to have back to
-- back LAST databeats.
--
-------------------------------------------------------------
REG_LAST_DBEAT : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_last_mmap_dbeat_reg <= '0';
else
sig_last_mmap_dbeat_reg <= sig_last_mmap_dbeat;
end if;
end if;
end process REG_LAST_DBEAT;
----- Write Status Interface Stuff --------------------------
sig_push_to_wsc_cmplt <= sig_push_to_wsc and sig_wsc_ready;
sig_set_push2wsc <= (sig_good_mmap_dbeat and
sig_dbeat_cntr_eq_0) or
sig_push_err2wsc or
sig_spcl_push_err2wsc; -- Special case from CR616212
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_INTERR_PUSH_FLOP
--
-- Process Description:
-- Generate a 1 clock wide pulse when a calc error has propagated
-- from the Command Calculator. This pulse is used to force a
-- push of the error status to the Write Status Controller
-- without a AXI transfer completion.
--
-------------------------------------------------------------
IMP_INTERR_PUSH_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_push_err2wsc = '1') then
sig_push_err2wsc <= '0';
elsif (sig_ld_new_cmd_reg = '1' and
sig_calc_error_reg = '1') then
sig_push_err2wsc <= '1';
else
null; -- hold state
end if;
end if;
end process IMP_INTERR_PUSH_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PUSH2WSC_FLOP
--
-- Process Description:
-- Implements a Sample and hold register for the outbound status
-- signals to the Write Status Controller (WSC). This register
-- has to support back to back transfer completions.
--
-------------------------------------------------------------
IMP_PUSH2WSC_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(sig_push_to_wsc_cmplt = '1' and
sig_set_push2wsc = '0')) then
sig_push_to_wsc <= '0';
sig_data2wsc_tag <= (others => '0');
sig_data2wsc_calc_err <= '0';
sig_data2wsc_last_err <= '0';
sig_data2wsc_cmd_cmplt <= '0';
elsif (sig_set_push2wsc = '1' and
sig_tlast_err_stop = '0') then
sig_push_to_wsc <= '1';
sig_data2wsc_tag <= sig_tag_reg ;
sig_data2wsc_calc_err <= sig_calc_error_reg ;
sig_data2wsc_last_err <= sig_tlast_error_reg or
sig_tlast_error ;
sig_data2wsc_cmd_cmplt <= sig_cmd_cmplt_reg or
sig_tlast_error_reg or
sig_tlast_error ;
else
null; -- hold current state
end if;
end if;
end process IMP_PUSH2WSC_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_LD_NEW_CMD_REG
--
-- Process Description:
-- Registers the flag indicating a new command has been
-- loaded. Needs to be a 1 clk wide pulse.
--
-------------------------------------------------------------
IMP_LD_NEW_CMD_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_ld_new_cmd_reg = '1') then
sig_ld_new_cmd_reg <= '0';
else
sig_ld_new_cmd_reg <= sig_ld_new_cmd;
end if;
end if;
end process IMP_LD_NEW_CMD_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_NXT_LEN_REG
--
-- Process Description:
-- Registers the load control and length value for a command
-- passed to the WDC input command interface. The registered
-- signals are used for the external Indeterminate BTT support
-- ports.
--
-------------------------------------------------------------
IMP_NXT_LEN_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_s2mm_ld_nxt_len <= '0';
sig_s2mm_wr_len <= (others => '0');
else
sig_s2mm_ld_nxt_len <= mstr2data_cmd_valid and
sig_data2mstr_cmd_ready;
sig_s2mm_wr_len <= mstr2data_len;
end if;
end if;
end process IMP_NXT_LEN_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_DATA_CNTL_FIFO
--
-- If Generate Description:
-- Omits the input data control FIFO if the requested FIFO
-- depth is 1. The Data Qualifier Register serves as a
-- 1 deep FIFO by itself.
--
------------------------------------------------------------
GEN_NO_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH = 1) generate
begin
-- Command Calculator Handshake output
sig_data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_rd_cmd_valid <= mstr2data_cmd_valid ;
-- pre 13.1 sig_fifo_wr_cmd_ready <= sig_dqual_reg_empty and
-- pre 13.1 sig_aposted_cntr_ready and
-- pre 13.1 not(wsc2mstr_halt_pipe) and -- The Wr Status Controller is not stalling
-- pre 13.1 not(sig_calc_error_reg); -- the command execution pipe and there is
-- pre 13.1 -- no calculation error being propagated
sig_fifo_wr_cmd_ready <= sig_push_dqual_reg;
sig_fifo_next_tag <= mstr2data_tag ;
sig_fifo_next_sadddr_lsb <= mstr2data_saddr_lsb ;
sig_fifo_next_len <= mstr2data_len ;
sig_fifo_next_strt_strb <= mstr2data_strt_strb ;
sig_fifo_next_last_strb <= mstr2data_last_strb ;
sig_fifo_next_drr <= mstr2data_drr ;
sig_fifo_next_eof <= mstr2data_eof ;
sig_fifo_next_sequential <= mstr2data_sequential ;
sig_fifo_next_cmd_cmplt <= mstr2data_cmd_cmplt ;
sig_fifo_next_calc_error <= mstr2data_calc_error ;
end generate GEN_NO_DATA_CNTL_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_DATA_CNTL_FIFO
--
-- If Generate Description:
-- Includes the input data control FIFO if the requested
-- FIFO depth is more than 1.
--
------------------------------------------------------------
GEN_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH > 1) generate
begin
-- Command Calculator Handshake output
sig_data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_wr_cmd_valid <= mstr2data_cmd_valid ;
-- pop the fifo when dqual reg is pushed
sig_fifo_rd_cmd_ready <= sig_push_dqual_reg;
-- Format the input fifo data word
sig_cmd_fifo_data_in <= mstr2data_calc_error &
mstr2data_cmd_cmplt &
mstr2data_sequential &
mstr2data_eof &
mstr2data_drr &
mstr2data_last_strb &
mstr2data_strt_strb &
mstr2data_len &
mstr2data_saddr_lsb &
mstr2data_tag ;
-- Rip the output fifo data word
sig_fifo_next_tag <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto
TAG_STRT_INDEX);
sig_fifo_next_sadddr_lsb <= sig_cmd_fifo_data_out((SADDR_LSB_STRT_INDEX+SADDR_LSB_WIDTH)-1 downto
SADDR_LSB_STRT_INDEX);
sig_fifo_next_len <= sig_cmd_fifo_data_out((LEN_STRT_INDEX+LEN_WIDTH)-1 downto
LEN_STRT_INDEX);
sig_fifo_next_strt_strb <= sig_cmd_fifo_data_out((STRT_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
STRT_STRB_STRT_INDEX);
sig_fifo_next_last_strb <= sig_cmd_fifo_data_out((LAST_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
LAST_STRB_STRT_INDEX);
sig_fifo_next_drr <= sig_cmd_fifo_data_out(DRR_STRT_INDEX);
sig_fifo_next_eof <= sig_cmd_fifo_data_out(EOF_STRT_INDEX);
sig_fifo_next_sequential <= sig_cmd_fifo_data_out(SEQUENTIAL_STRT_INDEX);
sig_fifo_next_cmd_cmplt <= sig_cmd_fifo_data_out(CMD_CMPLT_STRT_INDEX);
sig_fifo_next_calc_error <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX);
------------------------------------------------------------
-- Instance: I_DATA_CNTL_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO
--
------------------------------------------------------------
I_DATA_CNTL_FIFO : entity axi_datamover_v5_1_9.axi_datamover_fifo
generic map (
C_DWIDTH => DCTL_FIFO_WIDTH ,
C_DEPTH => C_DATA_CNTL_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
fifo_wr_tready => sig_fifo_wr_cmd_ready ,
fifo_wr_tdata => sig_cmd_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
fifo_rd_tready => sig_fifo_rd_cmd_ready ,
fifo_rd_tdata => sig_cmd_fifo_data_out ,
fifo_rd_empty => sig_cmd_fifo_empty
);
end generate GEN_DATA_CNTL_FIFO;
-- Data Qualifier Register ------------------------------------
sig_ld_new_cmd <= sig_push_dqual_reg ;
sig_dqual_rdy <= sig_dqual_reg_full ;
sig_strt_strb_reg <= sig_next_strt_strb_reg ;
sig_last_strb_reg <= sig_next_last_strb_reg ;
sig_tag_reg <= sig_next_tag_reg ;
sig_cmd_cmplt_reg <= sig_next_cmd_cmplt_reg ;
sig_calc_error_reg <= sig_next_calc_error_reg ;
sig_cmd_is_eof <= sig_next_eof_reg ;
-- new for no bubbles between child requests
sig_sequential_push <= sig_good_mmap_dbeat and -- MMap handshake qualified
sig_last_dbeat and -- last data beat of transfer
sig_next_sequential_reg;-- next queued command is sequential
-- to the current command
-- pre 13.1 sig_push_dqual_reg <= (sig_sequential_push or
-- pre 13.1 sig_dqual_reg_empty) and
-- pre 13.1 sig_fifo_rd_cmd_valid and
-- pre 13.1 sig_aposted_cntr_ready and
-- pre 13.1 not(wsc2mstr_halt_pipe); -- The Wr Status Controller is not
-- pre 13.1 -- stalling the command execution pipe
sig_push_dqual_reg <= (sig_sequential_push or
sig_dqual_reg_empty) and
sig_fifo_rd_cmd_valid and
sig_aposted_cntr_ready and
not(sig_calc_error_reg) and -- 13.1 addition => An error has not been propagated
not(wsc2mstr_halt_pipe); -- The Wr Status Controller is not
-- stalling the command execution pipe
sig_pop_dqual_reg <= not(sig_next_calc_error_reg) and
sig_get_next_dqual and
sig_dqual_reg_full ;
-- new for no bubbles between child requests
sig_clr_dqual_reg <= mmap_reset or
(sig_pop_dqual_reg and
not(sig_push_dqual_reg));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DQUAL_REG
--
-- Process Description:
-- This process implements a register for the Data
-- Control and qualifiers. It operates like a 1 deep Sync FIFO.
--
-------------------------------------------------------------
IMP_DQUAL_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_clr_dqual_reg = '1') then
sig_next_tag_reg <= (others => '0');
sig_next_strt_strb_reg <= (others => '0');
sig_next_last_strb_reg <= (others => '0');
sig_next_eof_reg <= '0' ;
sig_next_sequential_reg <= '0' ;
sig_next_cmd_cmplt_reg <= '0' ;
sig_next_calc_error_reg <= '0' ;
sig_dqual_reg_empty <= '1' ;
sig_dqual_reg_full <= '0' ;
elsif (sig_push_dqual_reg = '1') then
sig_next_tag_reg <= sig_fifo_next_tag ;
sig_next_strt_strb_reg <= sig_sfhalt_next_strt_strb ;
sig_next_last_strb_reg <= sig_fifo_next_last_strb ;
sig_next_eof_reg <= sig_fifo_next_eof ;
sig_next_sequential_reg <= sig_fifo_next_sequential ;
sig_next_cmd_cmplt_reg <= sig_fifo_next_cmd_cmplt ;
sig_next_calc_error_reg <= sig_fifo_next_calc_error ;
sig_dqual_reg_empty <= '0';
sig_dqual_reg_full <= '1';
else
null; -- don't change state
end if;
end if;
end process IMP_DQUAL_REG;
-- Address LS Cntr logic --------------------------
sig_addr_lsb_reg <= STD_LOGIC_VECTOR(sig_ls_addr_cntr);
sig_addr_incr_unsgnd <= TO_UNSIGNED(ADDR_INCR_VALUE, C_SEL_ADDR_WIDTH);
sig_incr_ls_addr_cntr <= sig_good_mmap_dbeat;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_ADDR_LSB_CNTR
--
-- Process Description:
-- Implements the LS Address Counter used for controlling
-- the Write STRB DeMux during Burst transfers
--
-------------------------------------------------------------
DO_ADDR_LSB_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(sig_pop_dqual_reg = '1'and
sig_push_dqual_reg = '0')) then -- Clear the Counter
sig_ls_addr_cntr <= (others => '0');
elsif (sig_push_dqual_reg = '1') then -- Load the Counter
sig_ls_addr_cntr <= unsigned(sig_fifo_next_sadddr_lsb);
elsif (sig_incr_ls_addr_cntr = '1') then -- Increment the Counter
sig_ls_addr_cntr <= sig_ls_addr_cntr + sig_addr_incr_unsgnd;
else
null; -- Hold Current value
end if;
end if;
end process DO_ADDR_LSB_CNTR;
-- Address Posted Counter Logic --------------------------------------
sig_addr_chan_rdy <= not(sig_addr_posted_cntr_eq_0 or
sig_apc_going2zero) ; -- Gates data channel xfer handshake
sig_aposted_cntr_ready <= not(sig_addr_posted_cntr_max) ; -- Gates new command fetching
sig_no_posted_cmds <= sig_addr_posted_cntr_eq_0 ; -- Used for flushing cmds that are posted
sig_incr_addr_posted_cntr <= sig_addr_posted ;
sig_decr_addr_posted_cntr <= sig_last_mmap_dbeat_reg ;
sig_addr_posted_cntr_eq_0 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ZERO)
Else '0';
sig_addr_posted_cntr_max <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_MAX)
Else '0';
sig_addr_posted_cntr_eq_1 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ONE)
Else '0';
sig_apc_going2zero <= sig_addr_posted_cntr_eq_1 and
sig_decr_addr_posted_cntr and
not(sig_incr_addr_posted_cntr);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_POSTED_FIFO_CNTR
--
-- Process Description:
-- This process implements a counter for the tracking
-- if an Address has been posted on the AXI address channel.
-- The Data Controller must wait for an address to be posted
-- before proceeding with the corresponding data transfer on
-- the Data Channel. The counter is also used to track flushing
-- operations where all transfers commited on the AXI Address
-- Channel have to be completed before a halt can occur.
-------------------------------------------------------------
IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_addr_posted_cntr <= ADDR_POSTED_ZERO;
elsif (sig_incr_addr_posted_cntr = '1' and
sig_decr_addr_posted_cntr = '0' and
sig_addr_posted_cntr_max = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ;
elsif (sig_incr_addr_posted_cntr = '0' and
sig_decr_addr_posted_cntr = '1' and
sig_addr_posted_cntr_eq_0 = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_POSTED_FIFO_CNTR;
------- First/Middle/Last Dbeat detimination -------------------
sig_new_len_eq_0 <= '1'
When (sig_fifo_next_len = LEN_OF_ZERO)
else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_FIRST_MID_LAST
--
-- Process Description:
-- Implements the detection of the First/Mid/Last databeat of
-- a transfer.
--
-------------------------------------------------------------
DO_FIRST_MID_LAST : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_first_dbeat <= '0';
sig_last_dbeat <= '0';
sig_single_dbeat <= '0';
elsif (sig_ld_new_cmd = '1') then
sig_first_dbeat <= not(sig_new_len_eq_0);
sig_last_dbeat <= sig_new_len_eq_0;
sig_single_dbeat <= sig_new_len_eq_0;
Elsif (sig_dbeat_cntr_eq_1 = '1' and
sig_good_mmap_dbeat = '1') Then
sig_first_dbeat <= '0';
sig_last_dbeat <= '1';
sig_single_dbeat <= '0';
Elsif (sig_dbeat_cntr_eq_0 = '0' and
sig_dbeat_cntr_eq_1 = '0' and
sig_good_mmap_dbeat = '1') Then
sig_first_dbeat <= '0';
sig_last_dbeat <= '0';
sig_single_dbeat <= '0';
else
null; -- hold current state
end if;
end if;
end process DO_FIRST_MID_LAST;
------- Data Controller Halted Indication -------------------------------
data2all_dcntlr_halted <= sig_no_posted_cmds or
sig_calc_error_reg;
------- Data Beat counter logic -------------------------------
sig_dbeat_cntr_int <= TO_INTEGER(sig_dbeat_cntr);
sig_dbeat_cntr_eq_0 <= '1'
when (sig_dbeat_cntr_int = 0)
Else '0';
sig_dbeat_cntr_eq_1 <= '1'
when (sig_dbeat_cntr_int = 1)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_DBEAT_CNTR
--
-- Process Description:
-- Implements the transfer data beat counter used to track
-- progress of the transfer.
--
-------------------------------------------------------------
DO_DBEAT_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_dbeat_cntr <= (others => '0');
elsif (sig_ld_new_cmd = '1') then
sig_dbeat_cntr <= unsigned(sig_fifo_next_len);
Elsif (sig_good_mmap_dbeat = '1' and
sig_dbeat_cntr_eq_0 = '0') Then
sig_dbeat_cntr <= sig_dbeat_cntr-1;
else
null; -- Hold current state
end if;
end if;
end process DO_DBEAT_CNTR;
------- Soft Shutdown Logic -------------------------------
-- Formulate the soft shutdown complete flag
sig_data2rst_stop_cmplt <= (sig_halt_reg_dly3 and -- Normal Mode shutdown
sig_no_posted_cmds and
not(sig_calc_error_reg)) or
(sig_halt_reg_dly3 and -- Shutdown after error trap
sig_calc_error_reg);
-- Generate a gate signal to deassert the WVALID output
-- for 1 clock cycle after a WLAST is issued. This only
-- occurs when in soft shutdown mode.
sig_stop_wvalid <= (sig_last_mmap_dbeat_reg and
sig_halt_reg) or
sig_data2rst_stop_cmplt;
-- Assign the output port skid buf control for the
-- input Stream skid buffer
data2skid_halt <= sig_data2skid_halt;
-- Create a 1 clock wide pulse to tell the input
-- stream skid buffer to shut down.
sig_data2skid_halt <= sig_halt_reg_dly2 and
not(sig_halt_reg_dly3);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG
--
-- Process Description:
-- Implements the flop for capturing the Halt request from
-- the Reset module.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg <= '0';
elsif (rst2data_stop_request = '1') then
sig_halt_reg <= '1';
else
null; -- Hold current State
end if;
end if;
end process IMP_HALT_REQ_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG_DLY
--
-- Process Description:
-- Implements the flops for delaying the halt request by 3
-- clocks to allow the Address Controller to halt before the
-- Data Contoller can safely indicate it has exhausted all
-- transfers committed to the AXI Address Channel by the Address
-- Controller.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG_DLY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg_dly1 <= '0';
sig_halt_reg_dly2 <= '0';
sig_halt_reg_dly3 <= '0';
else
sig_halt_reg_dly1 <= sig_halt_reg;
sig_halt_reg_dly2 <= sig_halt_reg_dly1;
sig_halt_reg_dly3 <= sig_halt_reg_dly2;
end if;
end if;
end process IMP_HALT_REQ_REG_DLY;
end implementation;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 01.03.2014 13:25:44
-- Design Name:
-- Module Name: Eth_GMII_RXTest - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments: Modulo ue analiza la recepción de
-- paquetes ethernet y analiza sus estadìsticas.
-- Las señales que utiliza son las recibidas de una interfaz GMII.
-- No valdia preambulo, delimitador de inicio de trama ni checksum.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.ALL;
use IEEE.numeric_std.all;
library UNISIM;
use UNISIM.VComponents.all;
entity EthFrameAnalizer is
Port (
gmii_rx_clk : in STD_LOGIC;
gmii_rx_data : in STD_LOGIC_VECTOR (7 downto 0);
gmii_rx_dataValid : in STD_LOGIC;
gmii_rx_col : in STD_LOGIC;
gmii_rx_err : in STD_LOGIC;
--Caracteristicas extraidas
--Se actualizan de forma simultanea al momento que se termina la recepcion del paquete
--Solo son validos durante un cicl ode reloj, cuando packet_evaluationFinished es '1'
packet_evaluationFinished : out std_logic;
packet_actualByte : out std_logic_vector(15 downto 0);
packet_MACDstAddrBroadcast : out std_logic;
packet_PHYSignaledError : out std_logic;
packet_Valid : out std_logic;-- Si el paquete es valida, comprueba, PHYSignaledError y Len
packet_EthTypeOrLen : out std_logic;
packet_EtherType_Len : out std_logic_vector(15 downto 0);
packet_IPV4 : out std_logic;
packet_IPV6 : out std_logic;
packet_ARP : out std_logic
);
end EthFrameAnalizer;
architecture Behavioral of EthFrameAnalizer is
signal packet_MACDstAddrBroadcast_newValue : std_logic;
signal packet_IPV4_newValue : std_logic;
signal packet_IPV6_newValue : std_logic;
signal packet_ARP_newValue : std_logic;
signal eth_rx_frameEnded : boolean;-- Señal que indica que se ha terminado la captura de un frame ethernet
--Con esta señal las caracterísitcas del frame recibido deben guardarse y reniciarse para
--estar listas para el sgte
signal eth_rx_MACDstAddrBroadcast : boolean := false;
signal eth_rx_PHYErr : boolean := false; --Cuando el chip PHY ha indicado error durante la recepción del frame
signal eth_rx_Type_Len_Byte1 : std_logic_vector(7 downto 0); --Cuando el chip PHY ha indicado error durante la recepción del frame
signal eth_rx_Type_Len_Byte2 : std_logic_vector(7 downto 0); --Cuando el chip PHY ha indicado error durante la recepción del frame
signal eth_rx_TypeIPV4 : boolean := false; --Cuando el chip PHY ha indicado error durante la recepción del frame
signal eth_rx_TypeIPV6 : boolean := false; --Cuando el chip PHY ha indicado error durante la recepción del frame
signal eth_rx_isARP : boolean := false; --Cuando el chip PHY ha indicado error durante la recepción del frame
signal eth_rx_payloadLen : std_logic_vector(15 downto 0) := x"002E"; --Cuando el chip PHY ha indicado error durante la recepciòn del frame
signal eth_rx_lenOK : boolean := false;
signal eth_rx_EthTypeOrLen : boolean := false; --EtherType='1', Len= '0'
signal thisLenOK : boolean := true;
signal eth_rx_payloadLen_newValue : std_logic_vector(15 downto 0);
signal oldDataValid : std_logic;
signal bytesCounter : std_logic_vector(15 downto 0) := x"0000";
signal MACDst_Byte_IsFF : std_logic_vector(5 downto 0) := "000000";
signal MACDst_Byte_IsFF_Registered : std_logic_vector(5 downto 0) := "000000";
signal MACDst_IsFF : std_logic := '0';
signal evaluateMACBcst : boolean;
signal EtherTypeByte1IsIPV4 : boolean := false;
signal EtherTypeByte1IsIPV6 : boolean := false;
signal EtherTypeByte1IsARP : boolean := false;
signal EtherTypeByte2IsIPV4 : boolean := false;
signal EtherTypeByte2IsIPV6 : boolean := false;
signal EtherTypeByte2IsARP : boolean := false;
begin
--tratar eth_rx_frameEnd
eth_rx_frameEnded <= (gmii_rx_dataValid='0') and (oldDataValid='1');
packet_evaluationFinished<= '1' when eth_rx_frameEnded else '0';
detectEndOfFrame: process(gmii_rx_clk, gmii_rx_dataValid, oldDataValid)
begin
if ( rising_edge(gmii_rx_clk) ) then
oldDataValid<=gmii_rx_dataValid;
end if;
end process detectEndOfFrame;
bytesCounterUdpate: process (gmii_rx_clk, gmii_rx_dataValid, eth_rx_frameEnded)
begin
if( rising_edge(gmii_rx_clk) ) then
if ( eth_rx_frameEnded ) then
bytesCounter <= ( others => '0');
else
if ( gmii_rx_dataValid = '1') then
bytesCounter <= (bytesCounter+1);
end if;
end if;
end if;
end process bytesCounterUdpate;
--detectar MAC es broadcast
evaluateMACBcst <= ((gmii_rx_data = x"FF") and (gmii_rx_dataValid='1') );
evaluateDstMACIsBroadcast : for macOffset in 0 to 5 generate
MACDst_Byte_IsFF(macOffset) <= '1' when ( (bytesCounter = (x"0008"+macOffset)) and evaluateMACBcst ) else '0';
end generate evaluateDstMACIsBroadcast;
detectMACIsBroadcast: process(gmii_rx_clk, gmii_rx_dataValid, oldDataValid, gmii_rx_data, eth_rx_frameEnded, bytesCounter, MACDst_Byte_IsFF)
begin
if( rising_edge(gmii_rx_clk) ) then
if (eth_rx_frameEnded) then
MACDst_Byte_IsFF_Registered <= "000000";
else
registerActualByteMACIsBroadcast : for macOffset in 0 to 5 loop
if (bytesCounter = (x"0008"+macOffset)) then
MACDst_Byte_IsFF_Registered(macOffset) <= MACDst_Byte_IsFF(macOffset);
end if;
end loop;
end if;
end if;
end process detectMACIsBroadcast;
eth_rx_MACDstAddrBroadcast <= true when ( MACDst_Byte_IsFF_Registered = (MACDst_Byte_IsFF_Registered'range => '1') ) else false;--haciendo un AND de todos los valores del vector
-- detect PHY error
detectPHYError: process (gmii_rx_clk, gmii_rx_col, gmii_rx_err, eth_rx_frameEnded, eth_rx_PHYErr )
begin
if( rising_edge(gmii_rx_clk) ) then
if(eth_rx_frameEnded)then
eth_rx_PHYErr <= false;
else
if( (gmii_rx_err='1') or (gmii_rx_col='1') ) then
eth_rx_PHYErr <= true;
end if;
end if;
end if;
end process;
--detectar paquetes TypeIPV4, TypeIPV6 ó ARP
thisLenOK <= ((eth_rx_Type_Len_Byte1 & gmii_rx_data)>x"002E");
eth_rx_payloadLen_newValue <= (eth_rx_Type_Len_Byte1 & gmii_rx_data) when thisLenOK else x"002E";
detectTypeOrLen: process (gmii_rx_clk , eth_rx_frameEnded, eth_rx_PHYErr, bytesCounter, gmii_rx_data, gmii_rx_dataValid )
begin
if( rising_edge(gmii_rx_clk) ) then
if( (bytesCounter=20) and (gmii_rx_dataValid='1') ) then
eth_rx_Type_Len_Byte1 <= gmii_rx_data;
end if;
if( (bytesCounter=21) and (gmii_rx_dataValid='1') ) then
eth_rx_Type_Len_Byte2 <= gmii_rx_data;
eth_rx_EthTypeOrLen <= ((eth_rx_Type_Len_Byte1 & gmii_rx_data)>x"05DC");
eth_rx_lenOK <= thisLenOK;
eth_rx_payloadLen <= eth_rx_payloadLen_newValue;
end if;
end if;
end process;
eth_rx_TypeIPV4 <= (eth_rx_Type_Len_Byte1 = x"08") and (eth_rx_Type_Len_Byte2 = x"00");
eth_rx_TypeIPV6 <= (eth_rx_Type_Len_Byte1 = x"86") and (eth_rx_Type_Len_Byte2 = x"DD");
eth_rx_isARP <= (eth_rx_Type_Len_Byte1 = x"08") and (eth_rx_Type_Len_Byte2 = x"06") and eth_rx_MACDstAddrBroadcast;
--eth_rx_EthTypeOrLen <= eth_rx_payloadLen>
--Registrar las señales a la salida
packet_evaluationFinished <= '1' when (eth_rx_frameEnded) else '0';
packet_actualByte <= bytesCounter;
packet_PHYSignaledError <= '1' when eth_rx_PHYErr else '0';
packet_Valid <= '1' when (not(eth_rx_PHYErr) and eth_rx_lenOK) else '0';
packet_EthTypeOrLen <= '1' when eth_rx_EthTypeOrLen else '0';
packet_EtherType_Len <= eth_rx_payloadLen;
packet_MACDstAddrBroadcast_newValue <= '1' when eth_rx_MACDstAddrBroadcast else '0';
packet_IPV4_newValue <= '1' when eth_rx_TypeIPV4 else '0';
packet_IPV6_newValue <= '1' when eth_rx_TypeIPV6 else '0';
packet_ARP_newValue <= '1' when eth_rx_isARP else '0';
registerResults: process (gmii_rx_clk, eth_rx_frameEnded, eth_rx_PHYErr, bytesCounter, gmii_rx_data, gmii_rx_dataValid )
begin
if( rising_edge(gmii_rx_clk) ) then
packet_MACDstAddrBroadcast <= packet_MACDstAddrBroadcast_newValue;
packet_IPV4 <= packet_IPV4_newValue;
packet_IPV6 <= packet_IPV6_newValue;
packet_ARP <= packet_ARP_newValue;
end if;
end process registerResults;
end Behavioral ;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL reset_ex1 : STD_LOGIC := '0';
SIGNAL reset_ex2 : STD_LOGIC := '0';
SIGNAL reset_ex3 : STD_LOGIC := '0';
SIGNAL ae_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL af_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL sim_done_d1 : STD_LOGIC := '0';
SIGNAL sim_done_wr1 : STD_LOGIC := '0';
SIGNAL sim_done_wr2 : STD_LOGIC := '0';
SIGNAL empty_d1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom1 : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL state_rd_dom1 : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
SIGNAL rd_en_wr1 : STD_LOGIC := '0';
SIGNAL wr_en_d1 : STD_LOGIC := '0';
SIGNAL wr_en_rd1 : STD_LOGIC := '0';
SIGNAL full_chk_d1 : STD_LOGIC := '0';
SIGNAL full_chk_rd1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom3 : STD_LOGIC := '0';
SIGNAL rd_en_wr2 : STD_LOGIC := '0';
SIGNAL wr_en_rd2 : STD_LOGIC := '0';
SIGNAL full_chk_rd2 : STD_LOGIC := '0';
SIGNAL reset_en_d1 : STD_LOGIC := '0';
SIGNAL reset_en_rd1 : STD_LOGIC := '0';
SIGNAL reset_en_rd2 : STD_LOGIC := '0';
SIGNAL data_chk_wr_d1 : STD_LOGIC := '0';
SIGNAL data_chk_rd1 : STD_LOGIC := '0';
SIGNAL data_chk_rd2 : STD_LOGIC := '0';
SIGNAL full_d1 : STD_LOGIC := '0';
SIGNAL full_rd_dom1 : STD_LOGIC := '0';
SIGNAL full_rd_dom2 : STD_LOGIC := '0';
SIGNAL af_chk_d1 : STD_LOGIC := '0';
SIGNAL af_chk_rd1 : STD_LOGIC := '0';
SIGNAL af_chk_rd2 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_rd2 & empty_chk_i & af_chk_rd2 & ae_chk_i;
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_wr2 = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
-- Reset pulse extension require for FULL flags checks
-- FULL flag may stay high for 3 clocks after reset is removed.
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
reset_ex1 <= '1';
reset_ex2 <= '1';
reset_ex3 <= '1';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
reset_ex1 <= '0';
reset_ex2 <= reset_ex1;
reset_ex3 <= reset_ex2;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rdw_gt_wrw <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(wr_en_rd2 = '1' AND rd_en_i= '0' AND EMPTY = '1') THEN
rdw_gt_wrw <= rdw_gt_wrw + '1';
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 24 ns;
PRC_RD_EN <= prc_re_i AFTER 12 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-- Almost full flag checks
PROCESS(WR_CLK,reset_ex3)
BEGIN
IF(reset_ex3 = '1') THEN
af_chk_i <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
IF((FULL = '1' AND ALMOST_FULL = '0') OR (empty_wr_dom2 = '1' AND ALMOST_FULL = '1' AND C_WR_PNTR_WIDTH > 4)) THEN
af_chk_i <= '1';
ELSE
af_chk_i <= '0';
END IF;
END IF;
END PROCESS;
-- Almost empty flag checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
ae_chk_i <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF((EMPTY = '1' AND ALMOST_EMPTY = '0') OR
(state = '1' AND full_rd_dom2 = '1' AND ALMOST_EMPTY = '1')) THEN
ae_chk_i <= '1';
ELSE
ae_chk_i <= '0';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- SYNCHRONIZERS B/W WRITE AND READ DOMAINS
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
empty_wr_dom1 <= '1';
empty_wr_dom2 <= '1';
state_d1 <= '0';
wr_en_d1 <= '0';
rd_en_wr1 <= '0';
rd_en_wr2 <= '0';
full_chk_d1 <= '0';
af_chk_d1 <= '0';
full_d1 <= '0';
reset_en_d1 <= '0';
sim_done_wr1 <= '0';
sim_done_wr2 <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
sim_done_wr1 <= sim_done_d1;
sim_done_wr2 <= sim_done_wr1;
reset_en_d1 <= reset_en_i;
full_d1 <= FULL;
state_d1 <= state;
empty_wr_dom1 <= empty_d1;
empty_wr_dom2 <= empty_wr_dom1;
wr_en_d1 <= wr_en_i;
rd_en_wr1 <= rd_en_d1;
rd_en_wr2 <= rd_en_wr1;
full_chk_d1 <= full_chk_i;
af_chk_d1 <= af_chk_i;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_d1 <= '1';
state_rd_dom1 <= '0';
state_rd_dom2 <= '0';
state_rd_dom3 <= '0';
wr_en_rd1 <= '0';
wr_en_rd2 <= '0';
rd_en_d1 <= '0';
full_chk_rd1 <= '0';
full_chk_rd2 <= '0';
af_chk_rd1 <= '0';
af_chk_rd2 <= '0';
full_rd_dom1 <= '0';
full_rd_dom2 <= '0';
reset_en_rd1 <= '0';
reset_en_rd2 <= '0';
sim_done_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
sim_done_d1 <= sim_done_i;
reset_en_rd1 <= reset_en_d1;
reset_en_rd2 <= reset_en_rd1;
empty_d1 <= EMPTY;
rd_en_d1 <= rd_en_i;
state_rd_dom1 <= state_d1;
state_rd_dom2 <= state_rd_dom1;
state_rd_dom3 <= state_rd_dom2;
wr_en_rd1 <= wr_en_d1;
wr_en_rd2 <= wr_en_rd1;
full_chk_rd1 <= full_chk_d1;
full_chk_rd2 <= full_chk_rd1;
af_chk_rd1 <= af_chk_d1;
af_chk_rd2 <= af_chk_rd1;
full_rd_dom1 <= full_d1;
full_rd_dom2 <= full_rd_dom1;
END IF;
END PROCESS;
RESET_EN <= reset_en_rd2;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_wr2 = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_rd2 = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND empty_wr_dom2 = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(empty_wr_dom2 = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL reset_ex1 : STD_LOGIC := '0';
SIGNAL reset_ex2 : STD_LOGIC := '0';
SIGNAL reset_ex3 : STD_LOGIC := '0';
SIGNAL ae_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL af_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL sim_done_d1 : STD_LOGIC := '0';
SIGNAL sim_done_wr1 : STD_LOGIC := '0';
SIGNAL sim_done_wr2 : STD_LOGIC := '0';
SIGNAL empty_d1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom1 : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL state_rd_dom1 : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
SIGNAL rd_en_wr1 : STD_LOGIC := '0';
SIGNAL wr_en_d1 : STD_LOGIC := '0';
SIGNAL wr_en_rd1 : STD_LOGIC := '0';
SIGNAL full_chk_d1 : STD_LOGIC := '0';
SIGNAL full_chk_rd1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom3 : STD_LOGIC := '0';
SIGNAL rd_en_wr2 : STD_LOGIC := '0';
SIGNAL wr_en_rd2 : STD_LOGIC := '0';
SIGNAL full_chk_rd2 : STD_LOGIC := '0';
SIGNAL reset_en_d1 : STD_LOGIC := '0';
SIGNAL reset_en_rd1 : STD_LOGIC := '0';
SIGNAL reset_en_rd2 : STD_LOGIC := '0';
SIGNAL data_chk_wr_d1 : STD_LOGIC := '0';
SIGNAL data_chk_rd1 : STD_LOGIC := '0';
SIGNAL data_chk_rd2 : STD_LOGIC := '0';
SIGNAL full_d1 : STD_LOGIC := '0';
SIGNAL full_rd_dom1 : STD_LOGIC := '0';
SIGNAL full_rd_dom2 : STD_LOGIC := '0';
SIGNAL af_chk_d1 : STD_LOGIC := '0';
SIGNAL af_chk_rd1 : STD_LOGIC := '0';
SIGNAL af_chk_rd2 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_rd2 & empty_chk_i & af_chk_rd2 & ae_chk_i;
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_wr2 = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
wrw_gt_rdw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
-- Reset pulse extension require for FULL flags checks
-- FULL flag may stay high for 3 clocks after reset is removed.
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
reset_ex1 <= '1';
reset_ex2 <= '1';
reset_ex3 <= '1';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
reset_ex1 <= '0';
reset_ex2 <= reset_ex1;
reset_ex3 <= reset_ex2;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rdw_gt_wrw <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(wr_en_rd2 = '1' AND rd_en_i= '0' AND EMPTY = '1') THEN
rdw_gt_wrw <= rdw_gt_wrw + '1';
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 24 ns;
PRC_RD_EN <= prc_re_i AFTER 12 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-- Almost full flag checks
PROCESS(WR_CLK,reset_ex3)
BEGIN
IF(reset_ex3 = '1') THEN
af_chk_i <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
IF((FULL = '1' AND ALMOST_FULL = '0') OR (empty_wr_dom2 = '1' AND ALMOST_FULL = '1' AND C_WR_PNTR_WIDTH > 4)) THEN
af_chk_i <= '1';
ELSE
af_chk_i <= '0';
END IF;
END IF;
END PROCESS;
-- Almost empty flag checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
ae_chk_i <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF((EMPTY = '1' AND ALMOST_EMPTY = '0') OR
(state = '1' AND full_rd_dom2 = '1' AND ALMOST_EMPTY = '1')) THEN
ae_chk_i <= '1';
ELSE
ae_chk_i <= '0';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- SYNCHRONIZERS B/W WRITE AND READ DOMAINS
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
empty_wr_dom1 <= '1';
empty_wr_dom2 <= '1';
state_d1 <= '0';
wr_en_d1 <= '0';
rd_en_wr1 <= '0';
rd_en_wr2 <= '0';
full_chk_d1 <= '0';
af_chk_d1 <= '0';
full_d1 <= '0';
reset_en_d1 <= '0';
sim_done_wr1 <= '0';
sim_done_wr2 <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
sim_done_wr1 <= sim_done_d1;
sim_done_wr2 <= sim_done_wr1;
reset_en_d1 <= reset_en_i;
full_d1 <= FULL;
state_d1 <= state;
empty_wr_dom1 <= empty_d1;
empty_wr_dom2 <= empty_wr_dom1;
wr_en_d1 <= wr_en_i;
rd_en_wr1 <= rd_en_d1;
rd_en_wr2 <= rd_en_wr1;
full_chk_d1 <= full_chk_i;
af_chk_d1 <= af_chk_i;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_d1 <= '1';
state_rd_dom1 <= '0';
state_rd_dom2 <= '0';
state_rd_dom3 <= '0';
wr_en_rd1 <= '0';
wr_en_rd2 <= '0';
rd_en_d1 <= '0';
full_chk_rd1 <= '0';
full_chk_rd2 <= '0';
af_chk_rd1 <= '0';
af_chk_rd2 <= '0';
full_rd_dom1 <= '0';
full_rd_dom2 <= '0';
reset_en_rd1 <= '0';
reset_en_rd2 <= '0';
sim_done_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
sim_done_d1 <= sim_done_i;
reset_en_rd1 <= reset_en_d1;
reset_en_rd2 <= reset_en_rd1;
empty_d1 <= EMPTY;
rd_en_d1 <= rd_en_i;
state_rd_dom1 <= state_d1;
state_rd_dom2 <= state_rd_dom1;
state_rd_dom3 <= state_rd_dom2;
wr_en_rd1 <= wr_en_d1;
wr_en_rd2 <= wr_en_rd1;
full_chk_rd1 <= full_chk_d1;
full_chk_rd2 <= full_chk_rd1;
af_chk_rd1 <= af_chk_d1;
af_chk_rd2 <= af_chk_rd1;
full_rd_dom1 <= full_d1;
full_rd_dom2 <= full_rd_dom1;
END IF;
END PROCESS;
RESET_EN <= reset_en_rd2;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_wr2 = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_rd2 = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND empty_wr_dom2 = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(empty_wr_dom2 = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
---------------------------------------------------------------------------------------------------
-- divider_f2m.vhd ---
----------------------------------------------------------------------------------------------------
-- Author : Miguel Morales-Sandoval ---
-- Project : "Hardware Arquitecture for ECC and Lossless Data Compression ---
-- Organization : INAOE, Computer Science Department ---
-- Date : July, 2004. ---
----------------------------------------------------------------------------------------------------
-- Inverter for F_2^m
----------------------------------------------------------------------------------------------------
-- Coments: This is an implementation of the division algorithm. Dirent to the other implemented inverter
-- in this, the division is performed directly.
----------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;
----------------------------------------------------------------------------------------------------
entity f2m_divider_233 is
generic(
NUM_BITS : positive := 233
);
port(
x : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
y : in STD_LOGIC_VECTOR(NUM_BITS-1 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
done : out STD_LOGIC;
Ux : out STD_LOGIC_VECTOR(NUM_BITS-1 downto 0) -- U = x/y mod Fx,
);
end;
----------------------------------------------------------------------------------------------------
architecture behave of f2m_divider_233 is
----------------------------------------------------------------------------------------------------
-- Signal for up-date regsiters A and B
signal A,B : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
signal U, V : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
----------------------------------------------------------------------------------------------------
-- m = 163, the irreductible polynomial
--constant F : std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011001001";
-- m = 233 x233 + x74 + 1
constant F: std_logic_vector(NUM_BITS downto 0) := "100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000001";
-- m = 277 x277 + x74 + 1
--constant F: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000001001001"; --277 bits
-- m = 283 x283 + x12 + x7 + x5 + 1
--constant F: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000010100001";
-- m = 409 x409 + x87 + 1
--constant F: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000001";
-- m = 571 x571 + x10 + x5 + x2 + 1
--constant F: std_logic_vector(NUM_BITS downto 0) := "10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000100101";
----------------------------------------------------------------------------------------------------
-- control signals
signal a_greater_b, a_eq_b, A_par, B_par, U_par, V_par, u_mas_v_par: std_logic;
signal A_div_t, B_div_t, U_div_t, V_div_t : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
signal u_mas_M, v_mas_M, u_mas_v, u_mas_v_mas_M, a_mas_b : STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
signal u_mas_M_div_t, v_mas_M_div_t, u_mas_v_div_t, u_mas_v_mas_M_div_t, a_mas_b_div_t: STD_LOGIC_VECTOR(NUM_BITS downto 0); -- Internal registers
----------------------------------------------------------------------------------------------------------------------------------------------------------
type CurrentState_type is (END_STATE, INIT, CYCLE);
signal currentState: CurrentState_type;
----------------------------------------------------------------------------------------------------
begin
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
-- Control signals
A_par <= '1' when A(0) = '0' else
'0';
B_par <= '1' when B(0) = '0' else
'0';
U_par <= '1' when U(0) = '0' else
'0';
V_par <= '1' when V(0) = '0' else
'0';
a_greater_b <= '1' when A > B else
'0';
a_eq_b <= '1' when A = B else
'0';
----------------------------------------------------------------------------------------------------
-- Mux definitions
----------------------------------------------------------------------------------------------------
u_mas_M <= U xor F;
v_mas_M <= V xor F;
u_mas_v <= U xor V;
u_mas_v_mas_M <= u_mas_v xor F;
a_mas_b <= A xor B;
-- Muxes for A and B
a_div_t <= '0'& A(NUM_BITS downto 1);
b_div_t <= '0'& B(NUM_BITS downto 1);
u_div_t <= '0'& U(NUM_BITS downto 1);
v_div_t <= '0'& V(NUM_BITS downto 1);
u_mas_M_div_t <= '0' & u_mas_M(NUM_BITS downto 1);
v_mas_M_div_t <= '0' & v_mas_M(NUM_BITS downto 1);
u_mas_v_div_t <= '0' & u_mas_v(NUM_BITS downto 1);
u_mas_v_mas_M_div_t <= '0' & u_mas_v_mas_M(NUM_BITS downto 1);
a_mas_b_div_t <= '0' & a_mas_b(NUM_BITS downto 1);
----------------------------------------------------------------------------------------------------
-- Finite state machine
----------------------------------------------------------------------------------------------------
EEAL: process (clk)
begin -- syncronous reset
if CLK'event and CLK = '1' then
if (rst = '1')then
A <= '0' & y;
B <= F;
U <= '0' & x;
v <= (others => '0');
Ux <= (others => '0');
done <= '0';
currentState <= CYCLE;
else
case currentState is
-----------------------------------------------------------------------------------
when CYCLE =>
if A_eq_B = '1' then
currentState <= END_STATE;
Done <= '1';
Ux <= U(NUM_BITS-1 downto 0);
elsif A_par = '1' then
A <= A_div_t;
if U_par = '1' then
U <= U_div_t;
else
U <= u_mas_M_div_t;
end if;
elsif B_par = '1' then
B <= B_div_t;
if V_par = '1' then
V <= V_div_t;
else
V <= V_mas_M_div_t;
end if;
elsif a_greater_b = '1' then
A <= a_mas_b_div_t;
if u_mas_v(0) = '0' then
U <= u_mas_v_div_t;
else
U <= u_mas_v_mas_M_div_t;
end if;
else
B <= a_mas_b_div_t;
if u_mas_v(0) = '0' then
V <= u_mas_v_div_t;
else
V <= u_mas_v_mas_M_div_t;
end if;
end if;
-----------------------------------------------------------------------------------
when END_STATE => -- Do nothing
currentState <= END_STATE;
done <= '0'; -- para generar el pulso, quitarlo entity caso contrario
-----------------------------------------------------------------------------------
when others =>
null;
end case;
end if;
end if;
end process;
end behave; |
entity e is
end entity;
architecture a of e is
signal x : integer := -3 * 4 + 2;
type t is range -5 to 11 - 3;
constant c : integer := +4 + 1;
signal y : t;
type int_array is array (integer range <>) of integer;
constant a1 : int_array(1 to 5) := (1, 2, 3, 4, 5);
constant a2 : int_array(1 to 7) := (2 to 3 => 6, others => 5);
constant a3 : int_array(1 to 9) := (8 => 24, others => 0);
constant a4 : int_array(5 downto 1) := (1, 2, 3, 4, 5);
constant a5 : int_array(5 downto 1) := (5 downto 3 => -1, others => 1);
begin
process is
variable b : boolean;
begin
x <= c / 2;
y <= t'high;
y <= t'left;
b := t'right = 8;
b := (t'right - t'left) = 2;
b := t'high /= 2;
b := true and true;
b := true and false;
b := true or false;
b := true xor true;
b := not true;
b := not false;
b := true xnor false;
b := false nand false;
b := false nor true;
b := 7 > 5 and 6 < 2;
x <= a1(2);
x <= a2(1);
x <= a2(3);
x <= a3(8);
x <= a1'length;
x <= a4(2);
x <= a5(4);
x <= 2 ** 4;
end process;
process is
begin
if true then
x <= 1;
end if;
if false then
x <= 5;
end if;
if false then
null;
else
x <= 5;
end if;
while false loop
null;
end loop;
if true then
x <= 1;
x <= 5;
null;
end if;
end process;
process is
variable r : real;
variable b : boolean;
begin
r := 1.0 + 0.0;
r := 1.5 * 4.0;
r := 2.0 / 2.0;
b := 4.6 > 1.2;
end process;
process
variable k : time;
begin
end process;
process
type int2_vec is array (66 to 67) of integer;
begin
assert a1'length = 5;
assert a1'low(1) = 1;
assert a1'high(1) = 5;
assert a1'left = 1;
assert a1'right = 5;
assert int2_vec'length = 2;
assert int2_vec'low = 66;
end process;
process is
begin
case 1 is
when 1 => null;
when others => report "bang";
end case;
end process;
process is
variable r : real;
begin
r := 1.5 * 2;
r := 3 * 0.2;
r := 5.0 / 2;
end process;
process is
constant one : bit := '1';
variable b : boolean;
begin
b := one = '1';
b := '0' /= one;
end process;
end architecture;
|
entity e is
end entity;
architecture a of e is
signal x : integer := -3 * 4 + 2;
type t is range -5 to 11 - 3;
constant c : integer := +4 + 1;
signal y : t;
type int_array is array (integer range <>) of integer;
constant a1 : int_array(1 to 5) := (1, 2, 3, 4, 5);
constant a2 : int_array(1 to 7) := (2 to 3 => 6, others => 5);
constant a3 : int_array(1 to 9) := (8 => 24, others => 0);
constant a4 : int_array(5 downto 1) := (1, 2, 3, 4, 5);
constant a5 : int_array(5 downto 1) := (5 downto 3 => -1, others => 1);
begin
process is
variable b : boolean;
begin
x <= c / 2;
y <= t'high;
y <= t'left;
b := t'right = 8;
b := (t'right - t'left) = 2;
b := t'high /= 2;
b := true and true;
b := true and false;
b := true or false;
b := true xor true;
b := not true;
b := not false;
b := true xnor false;
b := false nand false;
b := false nor true;
b := 7 > 5 and 6 < 2;
x <= a1(2);
x <= a2(1);
x <= a2(3);
x <= a3(8);
x <= a1'length;
x <= a4(2);
x <= a5(4);
x <= 2 ** 4;
end process;
process is
begin
if true then
x <= 1;
end if;
if false then
x <= 5;
end if;
if false then
null;
else
x <= 5;
end if;
while false loop
null;
end loop;
if true then
x <= 1;
x <= 5;
null;
end if;
end process;
process is
variable r : real;
variable b : boolean;
begin
r := 1.0 + 0.0;
r := 1.5 * 4.0;
r := 2.0 / 2.0;
b := 4.6 > 1.2;
end process;
process
variable k : time;
begin
end process;
process
type int2_vec is array (66 to 67) of integer;
begin
assert a1'length = 5;
assert a1'low(1) = 1;
assert a1'high(1) = 5;
assert a1'left = 1;
assert a1'right = 5;
assert int2_vec'length = 2;
assert int2_vec'low = 66;
end process;
process is
begin
case 1 is
when 1 => null;
when others => report "bang";
end case;
end process;
process is
variable r : real;
begin
r := 1.5 * 2;
r := 3 * 0.2;
r := 5.0 / 2;
end process;
process is
constant one : bit := '1';
variable b : boolean;
begin
b := one = '1';
b := '0' /= one;
end process;
end architecture;
|
entity e is
end entity;
architecture a of e is
signal x : integer := -3 * 4 + 2;
type t is range -5 to 11 - 3;
constant c : integer := +4 + 1;
signal y : t;
type int_array is array (integer range <>) of integer;
constant a1 : int_array(1 to 5) := (1, 2, 3, 4, 5);
constant a2 : int_array(1 to 7) := (2 to 3 => 6, others => 5);
constant a3 : int_array(1 to 9) := (8 => 24, others => 0);
constant a4 : int_array(5 downto 1) := (1, 2, 3, 4, 5);
constant a5 : int_array(5 downto 1) := (5 downto 3 => -1, others => 1);
begin
process is
variable b : boolean;
begin
x <= c / 2;
y <= t'high;
y <= t'left;
b := t'right = 8;
b := (t'right - t'left) = 2;
b := t'high /= 2;
b := true and true;
b := true and false;
b := true or false;
b := true xor true;
b := not true;
b := not false;
b := true xnor false;
b := false nand false;
b := false nor true;
b := 7 > 5 and 6 < 2;
x <= a1(2);
x <= a2(1);
x <= a2(3);
x <= a3(8);
x <= a1'length;
x <= a4(2);
x <= a5(4);
x <= 2 ** 4;
end process;
process is
begin
if true then
x <= 1;
end if;
if false then
x <= 5;
end if;
if false then
null;
else
x <= 5;
end if;
while false loop
null;
end loop;
if true then
x <= 1;
x <= 5;
null;
end if;
end process;
process is
variable r : real;
variable b : boolean;
begin
r := 1.0 + 0.0;
r := 1.5 * 4.0;
r := 2.0 / 2.0;
b := 4.6 > 1.2;
end process;
process
variable k : time;
begin
end process;
process
type int2_vec is array (66 to 67) of integer;
begin
assert a1'length = 5;
assert a1'low(1) = 1;
assert a1'high(1) = 5;
assert a1'left = 1;
assert a1'right = 5;
assert int2_vec'length = 2;
assert int2_vec'low = 66;
end process;
process is
begin
case 1 is
when 1 => null;
when others => report "bang";
end case;
end process;
process is
variable r : real;
begin
r := 1.5 * 2;
r := 3 * 0.2;
r := 5.0 / 2;
end process;
process is
constant one : bit := '1';
variable b : boolean;
begin
b := one = '1';
b := '0' /= one;
end process;
end architecture;
|
-- -------------------------------------------------------------
--
-- File Name: hdl_prj/hdlsrc/OFDM_transmitter/RADIX22FFT_SDNF1_3_block5.vhd
-- Created: 2017-03-27 15:50:06
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF1_3_block5
-- Source Path: OFDM_transmitter/IFFT HDL Optimized/RADIX22FFT_SDNF1_3
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY RADIX22FFT_SDNF1_3_block5 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb_1_16_0 : IN std_logic;
twdlXdin_13_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_13_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_15_re : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_15_im : IN std_logic_vector(15 DOWNTO 0); -- sfix16_En13
twdlXdin_1_vld : IN std_logic;
softReset : IN std_logic;
dout_13_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_13_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_14_re : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_14_im : OUT std_logic_vector(15 DOWNTO 0); -- sfix16_En13
dout_13_vld : OUT std_logic
);
END RADIX22FFT_SDNF1_3_block5;
ARCHITECTURE rtl OF RADIX22FFT_SDNF1_3_block5 IS
-- Signals
SIGNAL twdlXdin_13_re_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL twdlXdin_13_im_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL twdlXdin_15_re_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL twdlXdin_15_im_signed : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 : std_logic;
SIGNAL Radix22ButterflyG1_NF_btf1_re_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG1_NF_btf1_im_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG1_NF_btf2_re_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG1_NF_btf2_im_reg_next : signed(16 DOWNTO 0); -- sfix17_En13
SIGNAL Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next : std_logic;
SIGNAL dout_13_re_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_13_im_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_14_re_tmp : signed(15 DOWNTO 0); -- sfix16_En13
SIGNAL dout_14_im_tmp : signed(15 DOWNTO 0); -- sfix16_En13
BEGIN
twdlXdin_13_re_signed <= signed(twdlXdin_13_re);
twdlXdin_13_im_signed <= signed(twdlXdin_13_im);
twdlXdin_15_re_signed <= signed(twdlXdin_15_re);
twdlXdin_15_im_signed <= signed(twdlXdin_15_im);
-- Radix22ButterflyG1_NF
Radix22ButterflyG1_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG1_NF_btf1_im_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG1_NF_btf2_re_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG1_NF_btf2_im_reg <= to_signed(16#00000#, 17);
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb_1_16_0 = '1' THEN
Radix22ButterflyG1_NF_btf1_re_reg <= Radix22ButterflyG1_NF_btf1_re_reg_next;
Radix22ButterflyG1_NF_btf1_im_reg <= Radix22ButterflyG1_NF_btf1_im_reg_next;
Radix22ButterflyG1_NF_btf2_re_reg <= Radix22ButterflyG1_NF_btf2_re_reg_next;
Radix22ButterflyG1_NF_btf2_im_reg <= Radix22ButterflyG1_NF_btf2_im_reg_next;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1 <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG1_NF_process;
Radix22ButterflyG1_NF_output : PROCESS (Radix22ButterflyG1_NF_btf1_re_reg, Radix22ButterflyG1_NF_btf1_im_reg,
Radix22ButterflyG1_NF_btf2_re_reg, Radix22ButterflyG1_NF_btf2_im_reg,
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1, twdlXdin_13_re_signed,
twdlXdin_13_im_signed, twdlXdin_15_re_signed, twdlXdin_15_im_signed,
twdlXdin_1_vld)
VARIABLE add_cast : signed(16 DOWNTO 0);
VARIABLE add_cast_0 : signed(16 DOWNTO 0);
VARIABLE sra_temp : signed(16 DOWNTO 0);
VARIABLE sub_cast : signed(16 DOWNTO 0);
VARIABLE sub_cast_0 : signed(16 DOWNTO 0);
VARIABLE sra_temp_0 : signed(16 DOWNTO 0);
VARIABLE add_cast_1 : signed(16 DOWNTO 0);
VARIABLE add_cast_2 : signed(16 DOWNTO 0);
VARIABLE sra_temp_1 : signed(16 DOWNTO 0);
VARIABLE sub_cast_1 : signed(16 DOWNTO 0);
VARIABLE sub_cast_2 : signed(16 DOWNTO 0);
VARIABLE sra_temp_2 : signed(16 DOWNTO 0);
BEGIN
Radix22ButterflyG1_NF_btf1_re_reg_next <= Radix22ButterflyG1_NF_btf1_re_reg;
Radix22ButterflyG1_NF_btf1_im_reg_next <= Radix22ButterflyG1_NF_btf1_im_reg;
Radix22ButterflyG1_NF_btf2_re_reg_next <= Radix22ButterflyG1_NF_btf2_re_reg;
Radix22ButterflyG1_NF_btf2_im_reg_next <= Radix22ButterflyG1_NF_btf2_im_reg;
Radix22ButterflyG1_NF_dinXtwdl_vld_dly1_next <= twdlXdin_1_vld;
IF twdlXdin_1_vld = '1' THEN
add_cast := resize(twdlXdin_13_re_signed, 17);
add_cast_0 := resize(twdlXdin_15_re_signed, 17);
Radix22ButterflyG1_NF_btf1_re_reg_next <= add_cast + add_cast_0;
sub_cast := resize(twdlXdin_13_re_signed, 17);
sub_cast_0 := resize(twdlXdin_15_re_signed, 17);
Radix22ButterflyG1_NF_btf2_re_reg_next <= sub_cast - sub_cast_0;
add_cast_1 := resize(twdlXdin_13_im_signed, 17);
add_cast_2 := resize(twdlXdin_15_im_signed, 17);
Radix22ButterflyG1_NF_btf1_im_reg_next <= add_cast_1 + add_cast_2;
sub_cast_1 := resize(twdlXdin_13_im_signed, 17);
sub_cast_2 := resize(twdlXdin_15_im_signed, 17);
Radix22ButterflyG1_NF_btf2_im_reg_next <= sub_cast_1 - sub_cast_2;
END IF;
sra_temp := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf1_re_reg, 1);
dout_13_re_tmp <= sra_temp(15 DOWNTO 0);
sra_temp_0 := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf1_im_reg, 1);
dout_13_im_tmp <= sra_temp_0(15 DOWNTO 0);
sra_temp_1 := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf2_re_reg, 1);
dout_14_re_tmp <= sra_temp_1(15 DOWNTO 0);
sra_temp_2 := SHIFT_RIGHT(Radix22ButterflyG1_NF_btf2_im_reg, 1);
dout_14_im_tmp <= sra_temp_2(15 DOWNTO 0);
dout_13_vld <= Radix22ButterflyG1_NF_dinXtwdl_vld_dly1;
END PROCESS Radix22ButterflyG1_NF_output;
dout_13_re <= std_logic_vector(dout_13_re_tmp);
dout_13_im <= std_logic_vector(dout_13_im_tmp);
dout_14_re <= std_logic_vector(dout_14_re_tmp);
dout_14_im <= std_logic_vector(dout_14_im_tmp);
END rtl;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
entity buffered_spi is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
avalon_read : in STD_LOGIC;
avalon_write : in STD_LOGIC;
avalon_address : in STD_LOGIC_VECTOR (13 downto 0);
avalon_waitrequest : out std_logic := '0';
avalon_writedata : in STD_LOGIC_VECTOR (15 downto 0);
avalon_readdata : out STD_LOGIC_VECTOR (15 downto 0);
avalon_readdatavalid : out std_logic := '0';
spi_mosi : out STD_LOGIC := '0';
spi_clk : out STD_LOGIC := '0';
spi_miso : in STD_LOGIC;
spi_cs : out STD_LOGIC := '1');
end buffered_spi;
architecture Behavioral of buffered_spi is
signal transaction_active : std_logic := '0';
signal transaction_active_p1 : std_logic := '0';
signal transaction_active_readreg : std_logic := '0';
signal writebuffer_write1 : std_logic := '0';
signal writebuffer_write2 : std_logic := '0';
signal readbuffer_write1 : std_logic := '0';
signal readbuffer_write2 : std_logic := '0';
signal readbuffer_transaction_write1 : std_logic := '0';
signal readbuffer_transaction_write2 : std_logic := '0';
signal transaction_prestart_1 : std_logic := '0';
signal transaction_prestart_2 : std_logic := '0';
signal transaction_start : std_logic := '0';
signal transaction_bit_counter : unsigned (15 downto 0) := (others => '1');
signal transaction_bit_counter_p1 : unsigned (15 downto 0) := (others => '1');
signal transaction_byte_counter : unsigned (11 downto 0) := (others => '1');
signal transaction_byte_counter_p1 : unsigned (11 downto 0) := (others => '1');
signal transaction_data_read : std_logic_vector (15 downto 0) := (others => '0');
signal transaction_data_write1 : std_logic_vector (15 downto 0) := (others => '0');
signal transaction_data_write2 : std_logic_vector (15 downto 0) := (others => '0');
signal transaction_buf_write1 : std_logic := '0';
signal transaction_buf_write2 : std_logic := '0';
signal transaction_clkdiv_counter : std_logic_vector (3 downto 0) := (others => '0');
signal spi_cs_constant : std_logic := '1';
signal spi_cs_gappy : std_logic := '1';
signal length_register : std_logic_vector(10 downto 0) := (others => '0');
signal cs_mode_register : std_logic := '0';
signal delay_register : std_logic_vector(15 downto 0) := (others => '0');
signal buffer_select_register : std_logic := '0';
signal avalon_readdata_readbuf1 : std_logic_vector (15 downto 0);
signal avalon_readdata_writebuf1 : std_logic_vector (15 downto 0);
signal avalon_readdata_readbuf2 : std_logic_vector (15 downto 0);
signal avalon_readdata_writebuf2 : std_logic_vector (15 downto 0);
--signal avalon_address_f1 : std_logic_vector (13 downto 0);
signal avalon_readdata_p1 : std_logic_vector (15 downto 0);
signal avalon_read_f1 : STD_LOGIC;
signal avalon_read_f2 : STD_LOGIC;
signal avalon_address_latched : std_logic_vector (13 downto 0);
signal avalon_readdatavalid_p1 : STD_LOGIC;
--inferred ram, quartus fails to recognize'em like bram
--type spi_buf_type is array(0 to 511) of std_logic_vector(15 downto 0);
--signal write_buffer1 : spi_buf_type;
--signal read_buffer1 : spi_buf_type;
--signal write_buffer2 : spi_buf_type;
--signal read_buffer2 : spi_buf_type;
--using core-generated bram instead
component buff_spi_ram IS
PORT
(
address_a : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
end component;
begin
avalon_address_latched <= avalon_address when rising_edge(clock) and (avalon_read = '1' or avalon_write = '1');
avalon_read_f1 <= avalon_read when rising_edge(clock);
avalon_read_f2 <= avalon_read_f1 when rising_edge(clock);
--Avalon regs read interface
process (clock)
begin
if rising_edge(clock) then
avalon_readdatavalid_p1 <= '0';
if avalon_read_f2 = '1' then
avalon_readdatavalid_p1 <= '1';
case avalon_address_latched(13 downto 11) is
when "000" =>
avalon_readdata_p1 <= avalon_readdata_writebuf1;
when "001" =>
avalon_readdata_p1 <= avalon_readdata_writebuf2;
when "010" =>
avalon_readdata_p1 <= avalon_readdata_readbuf1;
when "011" =>
avalon_readdata_p1 <= avalon_readdata_readbuf2;
when "100" =>
case avalon_address_latched(2 downto 0) is
when "000" =>
avalon_readdata_p1 <= X"000"&"000"&transaction_active_readreg;
when "001" =>
avalon_readdata_p1 <= X"0"&"0"&length_register;
when "010" =>
avalon_readdata_p1 <= X"0"&std_logic_vector(transaction_byte_counter);
when "011" =>
avalon_readdata_p1 <= X"000"&"000"&cs_mode_register;
when "100" =>
avalon_readdata_p1 <= delay_register;
when "101" =>
avalon_readdata_p1 <= X"000"&"000"&buffer_select_register;
when "110" =>
avalon_readdata_p1 <= X"DEAF";
when "111" =>
avalon_readdata_p1 <= X"FACE";
when others =>
avalon_readdata_p1 <= X"ABBA";
end case;
when others =>
null;
end case;
end if;
end if;
end process;
avalon_readdata <= avalon_readdata_p1 when rising_edge(clock);
avalon_readdatavalid <= avalon_readdatavalid_p1 when rising_edge(clock);
--Avalon regs write interface
process (clock)
begin
if rising_edge(clock) then
transaction_prestart_1 <= '0';
writebuffer_write1 <= '0';
writebuffer_write2 <= '0';
readbuffer_write1 <= '0';
readbuffer_write2 <= '0';
if avalon_write= '1' then
case avalon_address(13 downto 11) is
when "000" =>
writebuffer_write1 <= '1';
when "001" =>
writebuffer_write2 <= '1';
when "010" =>
readbuffer_write1 <= '1';
when "011" =>
readbuffer_write2 <= '1';
when "100" =>
case avalon_address(2 downto 0) is
when "000" =>
transaction_prestart_1 <= avalon_writedata(0);
when "001" =>
length_register <= avalon_writedata(10 downto 0);
when "010" =>
null;
when "011" =>
cs_mode_register <= avalon_writedata(0);
when "100" =>
delay_register <= avalon_writedata;
when "101" =>
buffer_select_register <= avalon_writedata(0);
when others =>
null;
end case;
when others =>
null;
end case;
end if;
end if;
end process;
--async avalon write decoders
--writebuffer_write1 <= avalon_write when avalon_address(13 downto 11) = "000" else '0';
--writebuffer_write2 <= avalon_write when avalon_address(13 downto 11) = "001" else '0';
--readbuffer_write1 <= avalon_write when avalon_address(13 downto 11) = "010" else '0';
--readbuffer_write2 <= avalon_write when avalon_address(13 downto 11) = "011" else '0';
--delaying transaction_start cor a clock cycle to wait for cs
process (clock)
begin
if rising_edge(clock) then
if transaction_prestart_1 = '1' then
transaction_prestart_2 <= '1';
elsif transaction_clkdiv_counter = "1011" then
transaction_prestart_2 <= '0';
end if;
end if;
end process;
process (clock)
begin
if rising_edge(clock) then
if transaction_clkdiv_counter = "1011" then
transaction_start<= transaction_prestart_2;
end if;
end if;
end process;
transaction_byte_counter_p1 <= transaction_byte_counter when rising_edge(clock);
-- --read buffer1, should be inferred as 1.5-port block ram
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- if (readbuffer_write1 = '1') then
-- read_buffer1(to_integer(unsigned(avalon_address(8 downto 0)))) <= avalon_writedata;
-- end if;
-- avalon_readdata_readbuf1 <= read_buffer1(to_integer(unsigned(avalon_address(8 downto 0))));
-- if (readbuffer_transaction_write1 = '1') then
-- read_buffer1(to_integer(unsigned(transaction_byte_counter_p1(8 downto 0)))) <= transaction_data_read;
-- end if;
-- end if;
-- end process;
-- --read buffer2
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- if (readbuffer_write2 = '1') then
-- read_buffer2(to_integer(unsigned(avalon_address(8 downto 0)))) <= avalon_writedata;
-- end if;
-- avalon_readdata_readbuf2 <= read_buffer2(to_integer(unsigned(avalon_address(8 downto 0))));
-- if (readbuffer_transaction_write2 = '1') then
-- read_buffer2(to_integer(unsigned(transaction_byte_counter_p1(8 downto 0)))) <= transaction_data_read;
-- end if;
-- end if;
-- end process;
-- --write buffer1
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- if (writebuffer_write1 = '1') then
-- write_buffer1(to_integer(unsigned(avalon_address(8 downto 0)))) <= avalon_writedata;
-- end if;
-- transaction_data_write1 <= write_buffer1(to_integer(unsigned(transaction_byte_counter(8 downto 0))));
-- avalon_readdata_writebuf1 <= write_buffer1(to_integer(unsigned(avalon_address(8 downto 0))));
-- end if;
-- end process;
-- --write buffer2
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- if (writebuffer_write2 = '1') then
-- write_buffer2(to_integer(unsigned(avalon_address(8 downto 0)))) <= avalon_writedata;
-- end if;
-- transaction_data_write2 <= write_buffer2(to_integer(unsigned(transaction_byte_counter(8 downto 0))));
-- avalon_readdata_writebuf2 <= write_buffer2(to_integer(unsigned(avalon_address(8 downto 0))));
-- end if;
-- end process;
--using bram cores instead
read1_buf: buff_spi_ram
port map
(
address_a => avalon_address_latched(8 downto 0),
address_b => std_logic_vector(transaction_byte_counter_p1(8 downto 0)),
clock => clock,
data_a => avalon_writedata,
data_b => transaction_data_read,
wren_a => readbuffer_write1,
wren_b => readbuffer_transaction_write1,
q_a => avalon_readdata_readbuf1,
q_b => open --write-only port
);
read2_buf: buff_spi_ram
port map
(
address_a => avalon_address_latched(8 downto 0),
address_b => std_logic_vector(transaction_byte_counter_p1(8 downto 0)),
clock => clock,
data_a => avalon_writedata,
data_b => transaction_data_read,
wren_a => readbuffer_write2,
wren_b => readbuffer_transaction_write2,
q_a => avalon_readdata_readbuf2,
q_b => open --write-only port
);
write1_buf: buff_spi_ram
port map
(
address_a => avalon_address_latched(8 downto 0),
address_b => std_logic_vector(transaction_byte_counter(8 downto 0)),
clock => clock,
data_a => avalon_writedata,
data_b => X"0000",
wren_a => writebuffer_write1,
wren_b => '0', --read-only port
q_a => avalon_readdata_writebuf1,
q_b => transaction_data_write1
);
write2_buf: buff_spi_ram
port map
(
address_a => avalon_address_latched(8 downto 0),
address_b => std_logic_vector(transaction_byte_counter(8 downto 0)),
clock => clock,
data_a => avalon_writedata,
data_b => X"0000",
wren_a => writebuffer_write2,
wren_b => '0', --read-only port
q_a => avalon_readdata_writebuf2,
q_b => transaction_data_write2
);
--Avalon interface is only regs, so always ready to write.
avalon_waitrequest <= '0';
--transaction bit counter
process (clock)
begin
if rising_edge(clock) then
if (transaction_start = '1') then
transaction_bit_counter <= to_unsigned(0,16);
elsif (transaction_clkdiv_counter = "1000") and transaction_active = '1' then
if transaction_bit_counter < 16 + unsigned(delay_register) then
transaction_bit_counter <= transaction_bit_counter + 1;
else
transaction_bit_counter <= to_unsigned(0,16);
end if;
end if;
end if;
end process;
--transaction byte counter
process (clock)
begin
if rising_edge(clock) then
if (transaction_start = '1') then
transaction_byte_counter <= to_unsigned(0,12);
elsif transaction_clkdiv_counter = "1001" and transaction_active = '1' then
if transaction_byte_counter <= unsigned(length_register) then
if transaction_bit_counter = to_unsigned(16,16) then --16 bits per frame
transaction_byte_counter <= transaction_byte_counter + 1;
end if;
end if;
end if;
end if;
end process;
--transaction active flag
process (clock)
begin
if rising_edge(clock) then
if (transaction_start = '1') then
transaction_active <= '1';
elsif transaction_byte_counter = unsigned(length_register) then
transaction_active <= '0';
end if;
end if;
end process;
--transaction active flag for nios to read
process (clock)
begin
if rising_edge(clock) then
if (transaction_prestart_1 = '1') then
transaction_active_readreg <= '1';
elsif transaction_byte_counter = unsigned(length_register) then
transaction_active_readreg <= '0';
end if;
end if;
end process;
--transaction clock divider (test clockspeed is 1/16, 7.25 Mhz for 116Mhz base clock)
process (clock)
begin
if rising_edge(clock) then
if (transaction_prestart_1 = '1') then
transaction_clkdiv_counter <= "1100";
else
transaction_clkdiv_counter <= std_logic_vector(unsigned(transaction_clkdiv_counter) + 1);
end if;
end if;
end process;
-- SPI CLK output
process (clock)
begin
if rising_edge(clock) then
if (transaction_active = '1') and transaction_bit_counter <= to_unsigned(15,16) then
if (transaction_clkdiv_counter = "0001") and (transaction_start = '0') then
spi_clk <= '1';
elsif (transaction_clkdiv_counter = "1001") then
spi_clk <= '0';
end if;
else
spi_clk <= '0';
end if;
end if;
end process;
-- SPI MOSI output
process (clock)
begin
if rising_edge(clock) then
if (transaction_active = '0') then
spi_mosi <= '0';
elsif (buffer_select_register = '0') then
spi_mosi <= transaction_data_write1(15-to_integer(transaction_bit_counter(3 downto 0)));
else
spi_mosi <= transaction_data_write2(15-to_integer(transaction_bit_counter(3 downto 0)));
end if;
end if;
end process;
-- SPI CS output
transaction_active_p1 <= transaction_active when rising_edge(clock);
process (clock)
begin
if rising_edge(clock) then
if transaction_prestart_1 = '1' then
spi_cs_gappy <= '0';
elsif (transaction_bit_counter = to_unsigned(16,16)) then
spi_cs_gappy <= '1';
elsif (transaction_bit_counter = to_unsigned(0,16)) then
spi_cs_gappy <= '0';
elsif transaction_active = '0' and transaction_active_p1 = '1' then
spi_cs_gappy <= '1';
end if;
end if;
end process;
process (clock)
begin
if rising_edge(clock) then
if transaction_prestart_1 = '1' then
spi_cs_constant <= '0';
elsif transaction_active = '0' and transaction_active_p1 = '1' then
spi_cs_constant <= '1';
end if;
end if;
end process;
spi_cs <= spi_cs_gappy when cs_mode_register = '1' else
spi_cs_constant;
-- SPI MISO input
process (clock)
begin
if rising_edge(clock) then
if (transaction_active = '1') and transaction_bit_counter <= to_unsigned(15,16) then
transaction_data_read(15-to_integer(transaction_bit_counter(3 downto 0))) <= spi_miso;
end if;
end if;
end process;
transaction_bit_counter_p1 <= transaction_bit_counter when rising_edge(clock);
process (clock)
begin
if rising_edge(clock) then
readbuffer_transaction_write1 <= '0';
readbuffer_transaction_write2 <= '0';
if (transaction_active = '1') and transaction_bit_counter = to_unsigned(16,16) and transaction_bit_counter_p1 = to_unsigned(15,16) then
if (buffer_select_register = '0') then
readbuffer_transaction_write1 <= '1';
else
readbuffer_transaction_write2 <= '1';
end if;
end if;
end if;
end process;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
entity buffered_spi is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
avalon_read : in STD_LOGIC;
avalon_write : in STD_LOGIC;
avalon_address : in STD_LOGIC_VECTOR (13 downto 0);
avalon_waitrequest : out std_logic := '0';
avalon_writedata : in STD_LOGIC_VECTOR (15 downto 0);
avalon_readdata : out STD_LOGIC_VECTOR (15 downto 0);
avalon_readdatavalid : out std_logic := '0';
spi_mosi : out STD_LOGIC := '0';
spi_clk : out STD_LOGIC := '0';
spi_miso : in STD_LOGIC;
spi_cs : out STD_LOGIC := '1');
end buffered_spi;
architecture Behavioral of buffered_spi is
signal transaction_active : std_logic := '0';
signal transaction_active_p1 : std_logic := '0';
signal transaction_active_readreg : std_logic := '0';
signal writebuffer_write1 : std_logic := '0';
signal writebuffer_write2 : std_logic := '0';
signal readbuffer_write1 : std_logic := '0';
signal readbuffer_write2 : std_logic := '0';
signal readbuffer_transaction_write1 : std_logic := '0';
signal readbuffer_transaction_write2 : std_logic := '0';
signal transaction_prestart_1 : std_logic := '0';
signal transaction_prestart_2 : std_logic := '0';
signal transaction_start : std_logic := '0';
signal transaction_bit_counter : unsigned (15 downto 0) := (others => '1');
signal transaction_bit_counter_p1 : unsigned (15 downto 0) := (others => '1');
signal transaction_byte_counter : unsigned (11 downto 0) := (others => '1');
signal transaction_byte_counter_p1 : unsigned (11 downto 0) := (others => '1');
signal transaction_data_read : std_logic_vector (15 downto 0) := (others => '0');
signal transaction_data_write1 : std_logic_vector (15 downto 0) := (others => '0');
signal transaction_data_write2 : std_logic_vector (15 downto 0) := (others => '0');
signal transaction_buf_write1 : std_logic := '0';
signal transaction_buf_write2 : std_logic := '0';
signal transaction_clkdiv_counter : std_logic_vector (3 downto 0) := (others => '0');
signal spi_cs_constant : std_logic := '1';
signal spi_cs_gappy : std_logic := '1';
signal length_register : std_logic_vector(10 downto 0) := (others => '0');
signal cs_mode_register : std_logic := '0';
signal delay_register : std_logic_vector(15 downto 0) := (others => '0');
signal buffer_select_register : std_logic := '0';
signal avalon_readdata_readbuf1 : std_logic_vector (15 downto 0);
signal avalon_readdata_writebuf1 : std_logic_vector (15 downto 0);
signal avalon_readdata_readbuf2 : std_logic_vector (15 downto 0);
signal avalon_readdata_writebuf2 : std_logic_vector (15 downto 0);
--signal avalon_address_f1 : std_logic_vector (13 downto 0);
signal avalon_readdata_p1 : std_logic_vector (15 downto 0);
signal avalon_read_f1 : STD_LOGIC;
signal avalon_read_f2 : STD_LOGIC;
signal avalon_address_latched : std_logic_vector (13 downto 0);
signal avalon_readdatavalid_p1 : STD_LOGIC;
--inferred ram, quartus fails to recognize'em like bram
--type spi_buf_type is array(0 to 511) of std_logic_vector(15 downto 0);
--signal write_buffer1 : spi_buf_type;
--signal read_buffer1 : spi_buf_type;
--signal write_buffer2 : spi_buf_type;
--signal read_buffer2 : spi_buf_type;
--using core-generated bram instead
component buff_spi_ram IS
PORT
(
address_a : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
end component;
begin
avalon_address_latched <= avalon_address when rising_edge(clock) and (avalon_read = '1' or avalon_write = '1');
avalon_read_f1 <= avalon_read when rising_edge(clock);
avalon_read_f2 <= avalon_read_f1 when rising_edge(clock);
--Avalon regs read interface
process (clock)
begin
if rising_edge(clock) then
avalon_readdatavalid_p1 <= '0';
if avalon_read_f2 = '1' then
avalon_readdatavalid_p1 <= '1';
case avalon_address_latched(13 downto 11) is
when "000" =>
avalon_readdata_p1 <= avalon_readdata_writebuf1;
when "001" =>
avalon_readdata_p1 <= avalon_readdata_writebuf2;
when "010" =>
avalon_readdata_p1 <= avalon_readdata_readbuf1;
when "011" =>
avalon_readdata_p1 <= avalon_readdata_readbuf2;
when "100" =>
case avalon_address_latched(2 downto 0) is
when "000" =>
avalon_readdata_p1 <= X"000"&"000"&transaction_active_readreg;
when "001" =>
avalon_readdata_p1 <= X"0"&"0"&length_register;
when "010" =>
avalon_readdata_p1 <= X"0"&std_logic_vector(transaction_byte_counter);
when "011" =>
avalon_readdata_p1 <= X"000"&"000"&cs_mode_register;
when "100" =>
avalon_readdata_p1 <= delay_register;
when "101" =>
avalon_readdata_p1 <= X"000"&"000"&buffer_select_register;
when "110" =>
avalon_readdata_p1 <= X"DEAF";
when "111" =>
avalon_readdata_p1 <= X"FACE";
when others =>
avalon_readdata_p1 <= X"ABBA";
end case;
when others =>
null;
end case;
end if;
end if;
end process;
avalon_readdata <= avalon_readdata_p1 when rising_edge(clock);
avalon_readdatavalid <= avalon_readdatavalid_p1 when rising_edge(clock);
--Avalon regs write interface
process (clock)
begin
if rising_edge(clock) then
transaction_prestart_1 <= '0';
writebuffer_write1 <= '0';
writebuffer_write2 <= '0';
readbuffer_write1 <= '0';
readbuffer_write2 <= '0';
if avalon_write= '1' then
case avalon_address(13 downto 11) is
when "000" =>
writebuffer_write1 <= '1';
when "001" =>
writebuffer_write2 <= '1';
when "010" =>
readbuffer_write1 <= '1';
when "011" =>
readbuffer_write2 <= '1';
when "100" =>
case avalon_address(2 downto 0) is
when "000" =>
transaction_prestart_1 <= avalon_writedata(0);
when "001" =>
length_register <= avalon_writedata(10 downto 0);
when "010" =>
null;
when "011" =>
cs_mode_register <= avalon_writedata(0);
when "100" =>
delay_register <= avalon_writedata;
when "101" =>
buffer_select_register <= avalon_writedata(0);
when others =>
null;
end case;
when others =>
null;
end case;
end if;
end if;
end process;
--async avalon write decoders
--writebuffer_write1 <= avalon_write when avalon_address(13 downto 11) = "000" else '0';
--writebuffer_write2 <= avalon_write when avalon_address(13 downto 11) = "001" else '0';
--readbuffer_write1 <= avalon_write when avalon_address(13 downto 11) = "010" else '0';
--readbuffer_write2 <= avalon_write when avalon_address(13 downto 11) = "011" else '0';
--delaying transaction_start cor a clock cycle to wait for cs
process (clock)
begin
if rising_edge(clock) then
if transaction_prestart_1 = '1' then
transaction_prestart_2 <= '1';
elsif transaction_clkdiv_counter = "1011" then
transaction_prestart_2 <= '0';
end if;
end if;
end process;
process (clock)
begin
if rising_edge(clock) then
if transaction_clkdiv_counter = "1011" then
transaction_start<= transaction_prestart_2;
end if;
end if;
end process;
transaction_byte_counter_p1 <= transaction_byte_counter when rising_edge(clock);
-- --read buffer1, should be inferred as 1.5-port block ram
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- if (readbuffer_write1 = '1') then
-- read_buffer1(to_integer(unsigned(avalon_address(8 downto 0)))) <= avalon_writedata;
-- end if;
-- avalon_readdata_readbuf1 <= read_buffer1(to_integer(unsigned(avalon_address(8 downto 0))));
-- if (readbuffer_transaction_write1 = '1') then
-- read_buffer1(to_integer(unsigned(transaction_byte_counter_p1(8 downto 0)))) <= transaction_data_read;
-- end if;
-- end if;
-- end process;
-- --read buffer2
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- if (readbuffer_write2 = '1') then
-- read_buffer2(to_integer(unsigned(avalon_address(8 downto 0)))) <= avalon_writedata;
-- end if;
-- avalon_readdata_readbuf2 <= read_buffer2(to_integer(unsigned(avalon_address(8 downto 0))));
-- if (readbuffer_transaction_write2 = '1') then
-- read_buffer2(to_integer(unsigned(transaction_byte_counter_p1(8 downto 0)))) <= transaction_data_read;
-- end if;
-- end if;
-- end process;
-- --write buffer1
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- if (writebuffer_write1 = '1') then
-- write_buffer1(to_integer(unsigned(avalon_address(8 downto 0)))) <= avalon_writedata;
-- end if;
-- transaction_data_write1 <= write_buffer1(to_integer(unsigned(transaction_byte_counter(8 downto 0))));
-- avalon_readdata_writebuf1 <= write_buffer1(to_integer(unsigned(avalon_address(8 downto 0))));
-- end if;
-- end process;
-- --write buffer2
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- if (writebuffer_write2 = '1') then
-- write_buffer2(to_integer(unsigned(avalon_address(8 downto 0)))) <= avalon_writedata;
-- end if;
-- transaction_data_write2 <= write_buffer2(to_integer(unsigned(transaction_byte_counter(8 downto 0))));
-- avalon_readdata_writebuf2 <= write_buffer2(to_integer(unsigned(avalon_address(8 downto 0))));
-- end if;
-- end process;
--using bram cores instead
read1_buf: buff_spi_ram
port map
(
address_a => avalon_address_latched(8 downto 0),
address_b => std_logic_vector(transaction_byte_counter_p1(8 downto 0)),
clock => clock,
data_a => avalon_writedata,
data_b => transaction_data_read,
wren_a => readbuffer_write1,
wren_b => readbuffer_transaction_write1,
q_a => avalon_readdata_readbuf1,
q_b => open --write-only port
);
read2_buf: buff_spi_ram
port map
(
address_a => avalon_address_latched(8 downto 0),
address_b => std_logic_vector(transaction_byte_counter_p1(8 downto 0)),
clock => clock,
data_a => avalon_writedata,
data_b => transaction_data_read,
wren_a => readbuffer_write2,
wren_b => readbuffer_transaction_write2,
q_a => avalon_readdata_readbuf2,
q_b => open --write-only port
);
write1_buf: buff_spi_ram
port map
(
address_a => avalon_address_latched(8 downto 0),
address_b => std_logic_vector(transaction_byte_counter(8 downto 0)),
clock => clock,
data_a => avalon_writedata,
data_b => X"0000",
wren_a => writebuffer_write1,
wren_b => '0', --read-only port
q_a => avalon_readdata_writebuf1,
q_b => transaction_data_write1
);
write2_buf: buff_spi_ram
port map
(
address_a => avalon_address_latched(8 downto 0),
address_b => std_logic_vector(transaction_byte_counter(8 downto 0)),
clock => clock,
data_a => avalon_writedata,
data_b => X"0000",
wren_a => writebuffer_write2,
wren_b => '0', --read-only port
q_a => avalon_readdata_writebuf2,
q_b => transaction_data_write2
);
--Avalon interface is only regs, so always ready to write.
avalon_waitrequest <= '0';
--transaction bit counter
process (clock)
begin
if rising_edge(clock) then
if (transaction_start = '1') then
transaction_bit_counter <= to_unsigned(0,16);
elsif (transaction_clkdiv_counter = "1000") and transaction_active = '1' then
if transaction_bit_counter < 16 + unsigned(delay_register) then
transaction_bit_counter <= transaction_bit_counter + 1;
else
transaction_bit_counter <= to_unsigned(0,16);
end if;
end if;
end if;
end process;
--transaction byte counter
process (clock)
begin
if rising_edge(clock) then
if (transaction_start = '1') then
transaction_byte_counter <= to_unsigned(0,12);
elsif transaction_clkdiv_counter = "1001" and transaction_active = '1' then
if transaction_byte_counter <= unsigned(length_register) then
if transaction_bit_counter = to_unsigned(16,16) then --16 bits per frame
transaction_byte_counter <= transaction_byte_counter + 1;
end if;
end if;
end if;
end if;
end process;
--transaction active flag
process (clock)
begin
if rising_edge(clock) then
if (transaction_start = '1') then
transaction_active <= '1';
elsif transaction_byte_counter = unsigned(length_register) then
transaction_active <= '0';
end if;
end if;
end process;
--transaction active flag for nios to read
process (clock)
begin
if rising_edge(clock) then
if (transaction_prestart_1 = '1') then
transaction_active_readreg <= '1';
elsif transaction_byte_counter = unsigned(length_register) then
transaction_active_readreg <= '0';
end if;
end if;
end process;
--transaction clock divider (test clockspeed is 1/16, 7.25 Mhz for 116Mhz base clock)
process (clock)
begin
if rising_edge(clock) then
if (transaction_prestart_1 = '1') then
transaction_clkdiv_counter <= "1100";
else
transaction_clkdiv_counter <= std_logic_vector(unsigned(transaction_clkdiv_counter) + 1);
end if;
end if;
end process;
-- SPI CLK output
process (clock)
begin
if rising_edge(clock) then
if (transaction_active = '1') and transaction_bit_counter <= to_unsigned(15,16) then
if (transaction_clkdiv_counter = "0001") and (transaction_start = '0') then
spi_clk <= '1';
elsif (transaction_clkdiv_counter = "1001") then
spi_clk <= '0';
end if;
else
spi_clk <= '0';
end if;
end if;
end process;
-- SPI MOSI output
process (clock)
begin
if rising_edge(clock) then
if (transaction_active = '0') then
spi_mosi <= '0';
elsif (buffer_select_register = '0') then
spi_mosi <= transaction_data_write1(15-to_integer(transaction_bit_counter(3 downto 0)));
else
spi_mosi <= transaction_data_write2(15-to_integer(transaction_bit_counter(3 downto 0)));
end if;
end if;
end process;
-- SPI CS output
transaction_active_p1 <= transaction_active when rising_edge(clock);
process (clock)
begin
if rising_edge(clock) then
if transaction_prestart_1 = '1' then
spi_cs_gappy <= '0';
elsif (transaction_bit_counter = to_unsigned(16,16)) then
spi_cs_gappy <= '1';
elsif (transaction_bit_counter = to_unsigned(0,16)) then
spi_cs_gappy <= '0';
elsif transaction_active = '0' and transaction_active_p1 = '1' then
spi_cs_gappy <= '1';
end if;
end if;
end process;
process (clock)
begin
if rising_edge(clock) then
if transaction_prestart_1 = '1' then
spi_cs_constant <= '0';
elsif transaction_active = '0' and transaction_active_p1 = '1' then
spi_cs_constant <= '1';
end if;
end if;
end process;
spi_cs <= spi_cs_gappy when cs_mode_register = '1' else
spi_cs_constant;
-- SPI MISO input
process (clock)
begin
if rising_edge(clock) then
if (transaction_active = '1') and transaction_bit_counter <= to_unsigned(15,16) then
transaction_data_read(15-to_integer(transaction_bit_counter(3 downto 0))) <= spi_miso;
end if;
end if;
end process;
transaction_bit_counter_p1 <= transaction_bit_counter when rising_edge(clock);
process (clock)
begin
if rising_edge(clock) then
readbuffer_transaction_write1 <= '0';
readbuffer_transaction_write2 <= '0';
if (transaction_active = '1') and transaction_bit_counter = to_unsigned(16,16) and transaction_bit_counter_p1 = to_unsigned(15,16) then
if (buffer_select_register = '0') then
readbuffer_transaction_write1 <= '1';
else
readbuffer_transaction_write2 <= '1';
end if;
end if;
end if;
end process;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
entity buffered_spi is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
avalon_read : in STD_LOGIC;
avalon_write : in STD_LOGIC;
avalon_address : in STD_LOGIC_VECTOR (13 downto 0);
avalon_waitrequest : out std_logic := '0';
avalon_writedata : in STD_LOGIC_VECTOR (15 downto 0);
avalon_readdata : out STD_LOGIC_VECTOR (15 downto 0);
avalon_readdatavalid : out std_logic := '0';
spi_mosi : out STD_LOGIC := '0';
spi_clk : out STD_LOGIC := '0';
spi_miso : in STD_LOGIC;
spi_cs : out STD_LOGIC := '1');
end buffered_spi;
architecture Behavioral of buffered_spi is
signal transaction_active : std_logic := '0';
signal transaction_active_p1 : std_logic := '0';
signal transaction_active_readreg : std_logic := '0';
signal writebuffer_write1 : std_logic := '0';
signal writebuffer_write2 : std_logic := '0';
signal readbuffer_write1 : std_logic := '0';
signal readbuffer_write2 : std_logic := '0';
signal readbuffer_transaction_write1 : std_logic := '0';
signal readbuffer_transaction_write2 : std_logic := '0';
signal transaction_prestart_1 : std_logic := '0';
signal transaction_prestart_2 : std_logic := '0';
signal transaction_start : std_logic := '0';
signal transaction_bit_counter : unsigned (15 downto 0) := (others => '1');
signal transaction_bit_counter_p1 : unsigned (15 downto 0) := (others => '1');
signal transaction_byte_counter : unsigned (11 downto 0) := (others => '1');
signal transaction_byte_counter_p1 : unsigned (11 downto 0) := (others => '1');
signal transaction_data_read : std_logic_vector (15 downto 0) := (others => '0');
signal transaction_data_write1 : std_logic_vector (15 downto 0) := (others => '0');
signal transaction_data_write2 : std_logic_vector (15 downto 0) := (others => '0');
signal transaction_buf_write1 : std_logic := '0';
signal transaction_buf_write2 : std_logic := '0';
signal transaction_clkdiv_counter : std_logic_vector (3 downto 0) := (others => '0');
signal spi_cs_constant : std_logic := '1';
signal spi_cs_gappy : std_logic := '1';
signal length_register : std_logic_vector(10 downto 0) := (others => '0');
signal cs_mode_register : std_logic := '0';
signal delay_register : std_logic_vector(15 downto 0) := (others => '0');
signal buffer_select_register : std_logic := '0';
signal avalon_readdata_readbuf1 : std_logic_vector (15 downto 0);
signal avalon_readdata_writebuf1 : std_logic_vector (15 downto 0);
signal avalon_readdata_readbuf2 : std_logic_vector (15 downto 0);
signal avalon_readdata_writebuf2 : std_logic_vector (15 downto 0);
--signal avalon_address_f1 : std_logic_vector (13 downto 0);
signal avalon_readdata_p1 : std_logic_vector (15 downto 0);
signal avalon_read_f1 : STD_LOGIC;
signal avalon_read_f2 : STD_LOGIC;
signal avalon_address_latched : std_logic_vector (13 downto 0);
signal avalon_readdatavalid_p1 : STD_LOGIC;
--inferred ram, quartus fails to recognize'em like bram
--type spi_buf_type is array(0 to 511) of std_logic_vector(15 downto 0);
--signal write_buffer1 : spi_buf_type;
--signal read_buffer1 : spi_buf_type;
--signal write_buffer2 : spi_buf_type;
--signal read_buffer2 : spi_buf_type;
--using core-generated bram instead
component buff_spi_ram IS
PORT
(
address_a : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
end component;
begin
avalon_address_latched <= avalon_address when rising_edge(clock) and (avalon_read = '1' or avalon_write = '1');
avalon_read_f1 <= avalon_read when rising_edge(clock);
avalon_read_f2 <= avalon_read_f1 when rising_edge(clock);
--Avalon regs read interface
process (clock)
begin
if rising_edge(clock) then
avalon_readdatavalid_p1 <= '0';
if avalon_read_f2 = '1' then
avalon_readdatavalid_p1 <= '1';
case avalon_address_latched(13 downto 11) is
when "000" =>
avalon_readdata_p1 <= avalon_readdata_writebuf1;
when "001" =>
avalon_readdata_p1 <= avalon_readdata_writebuf2;
when "010" =>
avalon_readdata_p1 <= avalon_readdata_readbuf1;
when "011" =>
avalon_readdata_p1 <= avalon_readdata_readbuf2;
when "100" =>
case avalon_address_latched(2 downto 0) is
when "000" =>
avalon_readdata_p1 <= X"000"&"000"&transaction_active_readreg;
when "001" =>
avalon_readdata_p1 <= X"0"&"0"&length_register;
when "010" =>
avalon_readdata_p1 <= X"0"&std_logic_vector(transaction_byte_counter);
when "011" =>
avalon_readdata_p1 <= X"000"&"000"&cs_mode_register;
when "100" =>
avalon_readdata_p1 <= delay_register;
when "101" =>
avalon_readdata_p1 <= X"000"&"000"&buffer_select_register;
when "110" =>
avalon_readdata_p1 <= X"DEAF";
when "111" =>
avalon_readdata_p1 <= X"FACE";
when others =>
avalon_readdata_p1 <= X"ABBA";
end case;
when others =>
null;
end case;
end if;
end if;
end process;
avalon_readdata <= avalon_readdata_p1 when rising_edge(clock);
avalon_readdatavalid <= avalon_readdatavalid_p1 when rising_edge(clock);
--Avalon regs write interface
process (clock)
begin
if rising_edge(clock) then
transaction_prestart_1 <= '0';
writebuffer_write1 <= '0';
writebuffer_write2 <= '0';
readbuffer_write1 <= '0';
readbuffer_write2 <= '0';
if avalon_write= '1' then
case avalon_address(13 downto 11) is
when "000" =>
writebuffer_write1 <= '1';
when "001" =>
writebuffer_write2 <= '1';
when "010" =>
readbuffer_write1 <= '1';
when "011" =>
readbuffer_write2 <= '1';
when "100" =>
case avalon_address(2 downto 0) is
when "000" =>
transaction_prestart_1 <= avalon_writedata(0);
when "001" =>
length_register <= avalon_writedata(10 downto 0);
when "010" =>
null;
when "011" =>
cs_mode_register <= avalon_writedata(0);
when "100" =>
delay_register <= avalon_writedata;
when "101" =>
buffer_select_register <= avalon_writedata(0);
when others =>
null;
end case;
when others =>
null;
end case;
end if;
end if;
end process;
--async avalon write decoders
--writebuffer_write1 <= avalon_write when avalon_address(13 downto 11) = "000" else '0';
--writebuffer_write2 <= avalon_write when avalon_address(13 downto 11) = "001" else '0';
--readbuffer_write1 <= avalon_write when avalon_address(13 downto 11) = "010" else '0';
--readbuffer_write2 <= avalon_write when avalon_address(13 downto 11) = "011" else '0';
--delaying transaction_start cor a clock cycle to wait for cs
process (clock)
begin
if rising_edge(clock) then
if transaction_prestart_1 = '1' then
transaction_prestart_2 <= '1';
elsif transaction_clkdiv_counter = "1011" then
transaction_prestart_2 <= '0';
end if;
end if;
end process;
process (clock)
begin
if rising_edge(clock) then
if transaction_clkdiv_counter = "1011" then
transaction_start<= transaction_prestart_2;
end if;
end if;
end process;
transaction_byte_counter_p1 <= transaction_byte_counter when rising_edge(clock);
-- --read buffer1, should be inferred as 1.5-port block ram
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- if (readbuffer_write1 = '1') then
-- read_buffer1(to_integer(unsigned(avalon_address(8 downto 0)))) <= avalon_writedata;
-- end if;
-- avalon_readdata_readbuf1 <= read_buffer1(to_integer(unsigned(avalon_address(8 downto 0))));
-- if (readbuffer_transaction_write1 = '1') then
-- read_buffer1(to_integer(unsigned(transaction_byte_counter_p1(8 downto 0)))) <= transaction_data_read;
-- end if;
-- end if;
-- end process;
-- --read buffer2
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- if (readbuffer_write2 = '1') then
-- read_buffer2(to_integer(unsigned(avalon_address(8 downto 0)))) <= avalon_writedata;
-- end if;
-- avalon_readdata_readbuf2 <= read_buffer2(to_integer(unsigned(avalon_address(8 downto 0))));
-- if (readbuffer_transaction_write2 = '1') then
-- read_buffer2(to_integer(unsigned(transaction_byte_counter_p1(8 downto 0)))) <= transaction_data_read;
-- end if;
-- end if;
-- end process;
-- --write buffer1
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- if (writebuffer_write1 = '1') then
-- write_buffer1(to_integer(unsigned(avalon_address(8 downto 0)))) <= avalon_writedata;
-- end if;
-- transaction_data_write1 <= write_buffer1(to_integer(unsigned(transaction_byte_counter(8 downto 0))));
-- avalon_readdata_writebuf1 <= write_buffer1(to_integer(unsigned(avalon_address(8 downto 0))));
-- end if;
-- end process;
-- --write buffer2
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- if (writebuffer_write2 = '1') then
-- write_buffer2(to_integer(unsigned(avalon_address(8 downto 0)))) <= avalon_writedata;
-- end if;
-- transaction_data_write2 <= write_buffer2(to_integer(unsigned(transaction_byte_counter(8 downto 0))));
-- avalon_readdata_writebuf2 <= write_buffer2(to_integer(unsigned(avalon_address(8 downto 0))));
-- end if;
-- end process;
--using bram cores instead
read1_buf: buff_spi_ram
port map
(
address_a => avalon_address_latched(8 downto 0),
address_b => std_logic_vector(transaction_byte_counter_p1(8 downto 0)),
clock => clock,
data_a => avalon_writedata,
data_b => transaction_data_read,
wren_a => readbuffer_write1,
wren_b => readbuffer_transaction_write1,
q_a => avalon_readdata_readbuf1,
q_b => open --write-only port
);
read2_buf: buff_spi_ram
port map
(
address_a => avalon_address_latched(8 downto 0),
address_b => std_logic_vector(transaction_byte_counter_p1(8 downto 0)),
clock => clock,
data_a => avalon_writedata,
data_b => transaction_data_read,
wren_a => readbuffer_write2,
wren_b => readbuffer_transaction_write2,
q_a => avalon_readdata_readbuf2,
q_b => open --write-only port
);
write1_buf: buff_spi_ram
port map
(
address_a => avalon_address_latched(8 downto 0),
address_b => std_logic_vector(transaction_byte_counter(8 downto 0)),
clock => clock,
data_a => avalon_writedata,
data_b => X"0000",
wren_a => writebuffer_write1,
wren_b => '0', --read-only port
q_a => avalon_readdata_writebuf1,
q_b => transaction_data_write1
);
write2_buf: buff_spi_ram
port map
(
address_a => avalon_address_latched(8 downto 0),
address_b => std_logic_vector(transaction_byte_counter(8 downto 0)),
clock => clock,
data_a => avalon_writedata,
data_b => X"0000",
wren_a => writebuffer_write2,
wren_b => '0', --read-only port
q_a => avalon_readdata_writebuf2,
q_b => transaction_data_write2
);
--Avalon interface is only regs, so always ready to write.
avalon_waitrequest <= '0';
--transaction bit counter
process (clock)
begin
if rising_edge(clock) then
if (transaction_start = '1') then
transaction_bit_counter <= to_unsigned(0,16);
elsif (transaction_clkdiv_counter = "1000") and transaction_active = '1' then
if transaction_bit_counter < 16 + unsigned(delay_register) then
transaction_bit_counter <= transaction_bit_counter + 1;
else
transaction_bit_counter <= to_unsigned(0,16);
end if;
end if;
end if;
end process;
--transaction byte counter
process (clock)
begin
if rising_edge(clock) then
if (transaction_start = '1') then
transaction_byte_counter <= to_unsigned(0,12);
elsif transaction_clkdiv_counter = "1001" and transaction_active = '1' then
if transaction_byte_counter <= unsigned(length_register) then
if transaction_bit_counter = to_unsigned(16,16) then --16 bits per frame
transaction_byte_counter <= transaction_byte_counter + 1;
end if;
end if;
end if;
end if;
end process;
--transaction active flag
process (clock)
begin
if rising_edge(clock) then
if (transaction_start = '1') then
transaction_active <= '1';
elsif transaction_byte_counter = unsigned(length_register) then
transaction_active <= '0';
end if;
end if;
end process;
--transaction active flag for nios to read
process (clock)
begin
if rising_edge(clock) then
if (transaction_prestart_1 = '1') then
transaction_active_readreg <= '1';
elsif transaction_byte_counter = unsigned(length_register) then
transaction_active_readreg <= '0';
end if;
end if;
end process;
--transaction clock divider (test clockspeed is 1/16, 7.25 Mhz for 116Mhz base clock)
process (clock)
begin
if rising_edge(clock) then
if (transaction_prestart_1 = '1') then
transaction_clkdiv_counter <= "1100";
else
transaction_clkdiv_counter <= std_logic_vector(unsigned(transaction_clkdiv_counter) + 1);
end if;
end if;
end process;
-- SPI CLK output
process (clock)
begin
if rising_edge(clock) then
if (transaction_active = '1') and transaction_bit_counter <= to_unsigned(15,16) then
if (transaction_clkdiv_counter = "0001") and (transaction_start = '0') then
spi_clk <= '1';
elsif (transaction_clkdiv_counter = "1001") then
spi_clk <= '0';
end if;
else
spi_clk <= '0';
end if;
end if;
end process;
-- SPI MOSI output
process (clock)
begin
if rising_edge(clock) then
if (transaction_active = '0') then
spi_mosi <= '0';
elsif (buffer_select_register = '0') then
spi_mosi <= transaction_data_write1(15-to_integer(transaction_bit_counter(3 downto 0)));
else
spi_mosi <= transaction_data_write2(15-to_integer(transaction_bit_counter(3 downto 0)));
end if;
end if;
end process;
-- SPI CS output
transaction_active_p1 <= transaction_active when rising_edge(clock);
process (clock)
begin
if rising_edge(clock) then
if transaction_prestart_1 = '1' then
spi_cs_gappy <= '0';
elsif (transaction_bit_counter = to_unsigned(16,16)) then
spi_cs_gappy <= '1';
elsif (transaction_bit_counter = to_unsigned(0,16)) then
spi_cs_gappy <= '0';
elsif transaction_active = '0' and transaction_active_p1 = '1' then
spi_cs_gappy <= '1';
end if;
end if;
end process;
process (clock)
begin
if rising_edge(clock) then
if transaction_prestart_1 = '1' then
spi_cs_constant <= '0';
elsif transaction_active = '0' and transaction_active_p1 = '1' then
spi_cs_constant <= '1';
end if;
end if;
end process;
spi_cs <= spi_cs_gappy when cs_mode_register = '1' else
spi_cs_constant;
-- SPI MISO input
process (clock)
begin
if rising_edge(clock) then
if (transaction_active = '1') and transaction_bit_counter <= to_unsigned(15,16) then
transaction_data_read(15-to_integer(transaction_bit_counter(3 downto 0))) <= spi_miso;
end if;
end if;
end process;
transaction_bit_counter_p1 <= transaction_bit_counter when rising_edge(clock);
process (clock)
begin
if rising_edge(clock) then
readbuffer_transaction_write1 <= '0';
readbuffer_transaction_write2 <= '0';
if (transaction_active = '1') and transaction_bit_counter = to_unsigned(16,16) and transaction_bit_counter_p1 = to_unsigned(15,16) then
if (buffer_select_register = '0') then
readbuffer_transaction_write1 <= '1';
else
readbuffer_transaction_write2 <= '1';
end if;
end if;
end if;
end process;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
entity buffered_spi is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
avalon_read : in STD_LOGIC;
avalon_write : in STD_LOGIC;
avalon_address : in STD_LOGIC_VECTOR (13 downto 0);
avalon_waitrequest : out std_logic := '0';
avalon_writedata : in STD_LOGIC_VECTOR (15 downto 0);
avalon_readdata : out STD_LOGIC_VECTOR (15 downto 0);
avalon_readdatavalid : out std_logic := '0';
spi_mosi : out STD_LOGIC := '0';
spi_clk : out STD_LOGIC := '0';
spi_miso : in STD_LOGIC;
spi_cs : out STD_LOGIC := '1');
end buffered_spi;
architecture Behavioral of buffered_spi is
signal transaction_active : std_logic := '0';
signal transaction_active_p1 : std_logic := '0';
signal transaction_active_readreg : std_logic := '0';
signal writebuffer_write1 : std_logic := '0';
signal writebuffer_write2 : std_logic := '0';
signal readbuffer_write1 : std_logic := '0';
signal readbuffer_write2 : std_logic := '0';
signal readbuffer_transaction_write1 : std_logic := '0';
signal readbuffer_transaction_write2 : std_logic := '0';
signal transaction_prestart_1 : std_logic := '0';
signal transaction_prestart_2 : std_logic := '0';
signal transaction_start : std_logic := '0';
signal transaction_bit_counter : unsigned (15 downto 0) := (others => '1');
signal transaction_bit_counter_p1 : unsigned (15 downto 0) := (others => '1');
signal transaction_byte_counter : unsigned (11 downto 0) := (others => '1');
signal transaction_byte_counter_p1 : unsigned (11 downto 0) := (others => '1');
signal transaction_data_read : std_logic_vector (15 downto 0) := (others => '0');
signal transaction_data_write1 : std_logic_vector (15 downto 0) := (others => '0');
signal transaction_data_write2 : std_logic_vector (15 downto 0) := (others => '0');
signal transaction_buf_write1 : std_logic := '0';
signal transaction_buf_write2 : std_logic := '0';
signal transaction_clkdiv_counter : std_logic_vector (3 downto 0) := (others => '0');
signal spi_cs_constant : std_logic := '1';
signal spi_cs_gappy : std_logic := '1';
signal length_register : std_logic_vector(10 downto 0) := (others => '0');
signal cs_mode_register : std_logic := '0';
signal delay_register : std_logic_vector(15 downto 0) := (others => '0');
signal buffer_select_register : std_logic := '0';
signal avalon_readdata_readbuf1 : std_logic_vector (15 downto 0);
signal avalon_readdata_writebuf1 : std_logic_vector (15 downto 0);
signal avalon_readdata_readbuf2 : std_logic_vector (15 downto 0);
signal avalon_readdata_writebuf2 : std_logic_vector (15 downto 0);
--signal avalon_address_f1 : std_logic_vector (13 downto 0);
signal avalon_readdata_p1 : std_logic_vector (15 downto 0);
signal avalon_read_f1 : STD_LOGIC;
signal avalon_read_f2 : STD_LOGIC;
signal avalon_address_latched : std_logic_vector (13 downto 0);
signal avalon_readdatavalid_p1 : STD_LOGIC;
--inferred ram, quartus fails to recognize'em like bram
--type spi_buf_type is array(0 to 511) of std_logic_vector(15 downto 0);
--signal write_buffer1 : spi_buf_type;
--signal read_buffer1 : spi_buf_type;
--signal write_buffer2 : spi_buf_type;
--signal read_buffer2 : spi_buf_type;
--using core-generated bram instead
component buff_spi_ram IS
PORT
(
address_a : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
end component;
begin
avalon_address_latched <= avalon_address when rising_edge(clock) and (avalon_read = '1' or avalon_write = '1');
avalon_read_f1 <= avalon_read when rising_edge(clock);
avalon_read_f2 <= avalon_read_f1 when rising_edge(clock);
--Avalon regs read interface
process (clock)
begin
if rising_edge(clock) then
avalon_readdatavalid_p1 <= '0';
if avalon_read_f2 = '1' then
avalon_readdatavalid_p1 <= '1';
case avalon_address_latched(13 downto 11) is
when "000" =>
avalon_readdata_p1 <= avalon_readdata_writebuf1;
when "001" =>
avalon_readdata_p1 <= avalon_readdata_writebuf2;
when "010" =>
avalon_readdata_p1 <= avalon_readdata_readbuf1;
when "011" =>
avalon_readdata_p1 <= avalon_readdata_readbuf2;
when "100" =>
case avalon_address_latched(2 downto 0) is
when "000" =>
avalon_readdata_p1 <= X"000"&"000"&transaction_active_readreg;
when "001" =>
avalon_readdata_p1 <= X"0"&"0"&length_register;
when "010" =>
avalon_readdata_p1 <= X"0"&std_logic_vector(transaction_byte_counter);
when "011" =>
avalon_readdata_p1 <= X"000"&"000"&cs_mode_register;
when "100" =>
avalon_readdata_p1 <= delay_register;
when "101" =>
avalon_readdata_p1 <= X"000"&"000"&buffer_select_register;
when "110" =>
avalon_readdata_p1 <= X"DEAF";
when "111" =>
avalon_readdata_p1 <= X"FACE";
when others =>
avalon_readdata_p1 <= X"ABBA";
end case;
when others =>
null;
end case;
end if;
end if;
end process;
avalon_readdata <= avalon_readdata_p1 when rising_edge(clock);
avalon_readdatavalid <= avalon_readdatavalid_p1 when rising_edge(clock);
--Avalon regs write interface
process (clock)
begin
if rising_edge(clock) then
transaction_prestart_1 <= '0';
writebuffer_write1 <= '0';
writebuffer_write2 <= '0';
readbuffer_write1 <= '0';
readbuffer_write2 <= '0';
if avalon_write= '1' then
case avalon_address(13 downto 11) is
when "000" =>
writebuffer_write1 <= '1';
when "001" =>
writebuffer_write2 <= '1';
when "010" =>
readbuffer_write1 <= '1';
when "011" =>
readbuffer_write2 <= '1';
when "100" =>
case avalon_address(2 downto 0) is
when "000" =>
transaction_prestart_1 <= avalon_writedata(0);
when "001" =>
length_register <= avalon_writedata(10 downto 0);
when "010" =>
null;
when "011" =>
cs_mode_register <= avalon_writedata(0);
when "100" =>
delay_register <= avalon_writedata;
when "101" =>
buffer_select_register <= avalon_writedata(0);
when others =>
null;
end case;
when others =>
null;
end case;
end if;
end if;
end process;
--async avalon write decoders
--writebuffer_write1 <= avalon_write when avalon_address(13 downto 11) = "000" else '0';
--writebuffer_write2 <= avalon_write when avalon_address(13 downto 11) = "001" else '0';
--readbuffer_write1 <= avalon_write when avalon_address(13 downto 11) = "010" else '0';
--readbuffer_write2 <= avalon_write when avalon_address(13 downto 11) = "011" else '0';
--delaying transaction_start cor a clock cycle to wait for cs
process (clock)
begin
if rising_edge(clock) then
if transaction_prestart_1 = '1' then
transaction_prestart_2 <= '1';
elsif transaction_clkdiv_counter = "1011" then
transaction_prestart_2 <= '0';
end if;
end if;
end process;
process (clock)
begin
if rising_edge(clock) then
if transaction_clkdiv_counter = "1011" then
transaction_start<= transaction_prestart_2;
end if;
end if;
end process;
transaction_byte_counter_p1 <= transaction_byte_counter when rising_edge(clock);
-- --read buffer1, should be inferred as 1.5-port block ram
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- if (readbuffer_write1 = '1') then
-- read_buffer1(to_integer(unsigned(avalon_address(8 downto 0)))) <= avalon_writedata;
-- end if;
-- avalon_readdata_readbuf1 <= read_buffer1(to_integer(unsigned(avalon_address(8 downto 0))));
-- if (readbuffer_transaction_write1 = '1') then
-- read_buffer1(to_integer(unsigned(transaction_byte_counter_p1(8 downto 0)))) <= transaction_data_read;
-- end if;
-- end if;
-- end process;
-- --read buffer2
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- if (readbuffer_write2 = '1') then
-- read_buffer2(to_integer(unsigned(avalon_address(8 downto 0)))) <= avalon_writedata;
-- end if;
-- avalon_readdata_readbuf2 <= read_buffer2(to_integer(unsigned(avalon_address(8 downto 0))));
-- if (readbuffer_transaction_write2 = '1') then
-- read_buffer2(to_integer(unsigned(transaction_byte_counter_p1(8 downto 0)))) <= transaction_data_read;
-- end if;
-- end if;
-- end process;
-- --write buffer1
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- if (writebuffer_write1 = '1') then
-- write_buffer1(to_integer(unsigned(avalon_address(8 downto 0)))) <= avalon_writedata;
-- end if;
-- transaction_data_write1 <= write_buffer1(to_integer(unsigned(transaction_byte_counter(8 downto 0))));
-- avalon_readdata_writebuf1 <= write_buffer1(to_integer(unsigned(avalon_address(8 downto 0))));
-- end if;
-- end process;
-- --write buffer2
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- if (writebuffer_write2 = '1') then
-- write_buffer2(to_integer(unsigned(avalon_address(8 downto 0)))) <= avalon_writedata;
-- end if;
-- transaction_data_write2 <= write_buffer2(to_integer(unsigned(transaction_byte_counter(8 downto 0))));
-- avalon_readdata_writebuf2 <= write_buffer2(to_integer(unsigned(avalon_address(8 downto 0))));
-- end if;
-- end process;
--using bram cores instead
read1_buf: buff_spi_ram
port map
(
address_a => avalon_address_latched(8 downto 0),
address_b => std_logic_vector(transaction_byte_counter_p1(8 downto 0)),
clock => clock,
data_a => avalon_writedata,
data_b => transaction_data_read,
wren_a => readbuffer_write1,
wren_b => readbuffer_transaction_write1,
q_a => avalon_readdata_readbuf1,
q_b => open --write-only port
);
read2_buf: buff_spi_ram
port map
(
address_a => avalon_address_latched(8 downto 0),
address_b => std_logic_vector(transaction_byte_counter_p1(8 downto 0)),
clock => clock,
data_a => avalon_writedata,
data_b => transaction_data_read,
wren_a => readbuffer_write2,
wren_b => readbuffer_transaction_write2,
q_a => avalon_readdata_readbuf2,
q_b => open --write-only port
);
write1_buf: buff_spi_ram
port map
(
address_a => avalon_address_latched(8 downto 0),
address_b => std_logic_vector(transaction_byte_counter(8 downto 0)),
clock => clock,
data_a => avalon_writedata,
data_b => X"0000",
wren_a => writebuffer_write1,
wren_b => '0', --read-only port
q_a => avalon_readdata_writebuf1,
q_b => transaction_data_write1
);
write2_buf: buff_spi_ram
port map
(
address_a => avalon_address_latched(8 downto 0),
address_b => std_logic_vector(transaction_byte_counter(8 downto 0)),
clock => clock,
data_a => avalon_writedata,
data_b => X"0000",
wren_a => writebuffer_write2,
wren_b => '0', --read-only port
q_a => avalon_readdata_writebuf2,
q_b => transaction_data_write2
);
--Avalon interface is only regs, so always ready to write.
avalon_waitrequest <= '0';
--transaction bit counter
process (clock)
begin
if rising_edge(clock) then
if (transaction_start = '1') then
transaction_bit_counter <= to_unsigned(0,16);
elsif (transaction_clkdiv_counter = "1000") and transaction_active = '1' then
if transaction_bit_counter < 16 + unsigned(delay_register) then
transaction_bit_counter <= transaction_bit_counter + 1;
else
transaction_bit_counter <= to_unsigned(0,16);
end if;
end if;
end if;
end process;
--transaction byte counter
process (clock)
begin
if rising_edge(clock) then
if (transaction_start = '1') then
transaction_byte_counter <= to_unsigned(0,12);
elsif transaction_clkdiv_counter = "1001" and transaction_active = '1' then
if transaction_byte_counter <= unsigned(length_register) then
if transaction_bit_counter = to_unsigned(16,16) then --16 bits per frame
transaction_byte_counter <= transaction_byte_counter + 1;
end if;
end if;
end if;
end if;
end process;
--transaction active flag
process (clock)
begin
if rising_edge(clock) then
if (transaction_start = '1') then
transaction_active <= '1';
elsif transaction_byte_counter = unsigned(length_register) then
transaction_active <= '0';
end if;
end if;
end process;
--transaction active flag for nios to read
process (clock)
begin
if rising_edge(clock) then
if (transaction_prestart_1 = '1') then
transaction_active_readreg <= '1';
elsif transaction_byte_counter = unsigned(length_register) then
transaction_active_readreg <= '0';
end if;
end if;
end process;
--transaction clock divider (test clockspeed is 1/16, 7.25 Mhz for 116Mhz base clock)
process (clock)
begin
if rising_edge(clock) then
if (transaction_prestart_1 = '1') then
transaction_clkdiv_counter <= "1100";
else
transaction_clkdiv_counter <= std_logic_vector(unsigned(transaction_clkdiv_counter) + 1);
end if;
end if;
end process;
-- SPI CLK output
process (clock)
begin
if rising_edge(clock) then
if (transaction_active = '1') and transaction_bit_counter <= to_unsigned(15,16) then
if (transaction_clkdiv_counter = "0001") and (transaction_start = '0') then
spi_clk <= '1';
elsif (transaction_clkdiv_counter = "1001") then
spi_clk <= '0';
end if;
else
spi_clk <= '0';
end if;
end if;
end process;
-- SPI MOSI output
process (clock)
begin
if rising_edge(clock) then
if (transaction_active = '0') then
spi_mosi <= '0';
elsif (buffer_select_register = '0') then
spi_mosi <= transaction_data_write1(15-to_integer(transaction_bit_counter(3 downto 0)));
else
spi_mosi <= transaction_data_write2(15-to_integer(transaction_bit_counter(3 downto 0)));
end if;
end if;
end process;
-- SPI CS output
transaction_active_p1 <= transaction_active when rising_edge(clock);
process (clock)
begin
if rising_edge(clock) then
if transaction_prestart_1 = '1' then
spi_cs_gappy <= '0';
elsif (transaction_bit_counter = to_unsigned(16,16)) then
spi_cs_gappy <= '1';
elsif (transaction_bit_counter = to_unsigned(0,16)) then
spi_cs_gappy <= '0';
elsif transaction_active = '0' and transaction_active_p1 = '1' then
spi_cs_gappy <= '1';
end if;
end if;
end process;
process (clock)
begin
if rising_edge(clock) then
if transaction_prestart_1 = '1' then
spi_cs_constant <= '0';
elsif transaction_active = '0' and transaction_active_p1 = '1' then
spi_cs_constant <= '1';
end if;
end if;
end process;
spi_cs <= spi_cs_gappy when cs_mode_register = '1' else
spi_cs_constant;
-- SPI MISO input
process (clock)
begin
if rising_edge(clock) then
if (transaction_active = '1') and transaction_bit_counter <= to_unsigned(15,16) then
transaction_data_read(15-to_integer(transaction_bit_counter(3 downto 0))) <= spi_miso;
end if;
end if;
end process;
transaction_bit_counter_p1 <= transaction_bit_counter when rising_edge(clock);
process (clock)
begin
if rising_edge(clock) then
readbuffer_transaction_write1 <= '0';
readbuffer_transaction_write2 <= '0';
if (transaction_active = '1') and transaction_bit_counter = to_unsigned(16,16) and transaction_bit_counter_p1 = to_unsigned(15,16) then
if (buffer_select_register = '0') then
readbuffer_transaction_write1 <= '1';
else
readbuffer_transaction_write2 <= '1';
end if;
end if;
end if;
end process;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
entity buffered_spi is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
avalon_read : in STD_LOGIC;
avalon_write : in STD_LOGIC;
avalon_address : in STD_LOGIC_VECTOR (13 downto 0);
avalon_waitrequest : out std_logic := '0';
avalon_writedata : in STD_LOGIC_VECTOR (15 downto 0);
avalon_readdata : out STD_LOGIC_VECTOR (15 downto 0);
avalon_readdatavalid : out std_logic := '0';
spi_mosi : out STD_LOGIC := '0';
spi_clk : out STD_LOGIC := '0';
spi_miso : in STD_LOGIC;
spi_cs : out STD_LOGIC := '1');
end buffered_spi;
architecture Behavioral of buffered_spi is
signal transaction_active : std_logic := '0';
signal transaction_active_p1 : std_logic := '0';
signal transaction_active_readreg : std_logic := '0';
signal writebuffer_write1 : std_logic := '0';
signal writebuffer_write2 : std_logic := '0';
signal readbuffer_write1 : std_logic := '0';
signal readbuffer_write2 : std_logic := '0';
signal readbuffer_transaction_write1 : std_logic := '0';
signal readbuffer_transaction_write2 : std_logic := '0';
signal transaction_prestart_1 : std_logic := '0';
signal transaction_prestart_2 : std_logic := '0';
signal transaction_start : std_logic := '0';
signal transaction_bit_counter : unsigned (15 downto 0) := (others => '1');
signal transaction_bit_counter_p1 : unsigned (15 downto 0) := (others => '1');
signal transaction_byte_counter : unsigned (11 downto 0) := (others => '1');
signal transaction_byte_counter_p1 : unsigned (11 downto 0) := (others => '1');
signal transaction_data_read : std_logic_vector (15 downto 0) := (others => '0');
signal transaction_data_write1 : std_logic_vector (15 downto 0) := (others => '0');
signal transaction_data_write2 : std_logic_vector (15 downto 0) := (others => '0');
signal transaction_buf_write1 : std_logic := '0';
signal transaction_buf_write2 : std_logic := '0';
signal transaction_clkdiv_counter : std_logic_vector (3 downto 0) := (others => '0');
signal spi_cs_constant : std_logic := '1';
signal spi_cs_gappy : std_logic := '1';
signal length_register : std_logic_vector(10 downto 0) := (others => '0');
signal cs_mode_register : std_logic := '0';
signal delay_register : std_logic_vector(15 downto 0) := (others => '0');
signal buffer_select_register : std_logic := '0';
signal avalon_readdata_readbuf1 : std_logic_vector (15 downto 0);
signal avalon_readdata_writebuf1 : std_logic_vector (15 downto 0);
signal avalon_readdata_readbuf2 : std_logic_vector (15 downto 0);
signal avalon_readdata_writebuf2 : std_logic_vector (15 downto 0);
--signal avalon_address_f1 : std_logic_vector (13 downto 0);
signal avalon_readdata_p1 : std_logic_vector (15 downto 0);
signal avalon_read_f1 : STD_LOGIC;
signal avalon_read_f2 : STD_LOGIC;
signal avalon_address_latched : std_logic_vector (13 downto 0);
signal avalon_readdatavalid_p1 : STD_LOGIC;
--inferred ram, quartus fails to recognize'em like bram
--type spi_buf_type is array(0 to 511) of std_logic_vector(15 downto 0);
--signal write_buffer1 : spi_buf_type;
--signal read_buffer1 : spi_buf_type;
--signal write_buffer2 : spi_buf_type;
--signal read_buffer2 : spi_buf_type;
--using core-generated bram instead
component buff_spi_ram IS
PORT
(
address_a : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
end component;
begin
avalon_address_latched <= avalon_address when rising_edge(clock) and (avalon_read = '1' or avalon_write = '1');
avalon_read_f1 <= avalon_read when rising_edge(clock);
avalon_read_f2 <= avalon_read_f1 when rising_edge(clock);
--Avalon regs read interface
process (clock)
begin
if rising_edge(clock) then
avalon_readdatavalid_p1 <= '0';
if avalon_read_f2 = '1' then
avalon_readdatavalid_p1 <= '1';
case avalon_address_latched(13 downto 11) is
when "000" =>
avalon_readdata_p1 <= avalon_readdata_writebuf1;
when "001" =>
avalon_readdata_p1 <= avalon_readdata_writebuf2;
when "010" =>
avalon_readdata_p1 <= avalon_readdata_readbuf1;
when "011" =>
avalon_readdata_p1 <= avalon_readdata_readbuf2;
when "100" =>
case avalon_address_latched(2 downto 0) is
when "000" =>
avalon_readdata_p1 <= X"000"&"000"&transaction_active_readreg;
when "001" =>
avalon_readdata_p1 <= X"0"&"0"&length_register;
when "010" =>
avalon_readdata_p1 <= X"0"&std_logic_vector(transaction_byte_counter);
when "011" =>
avalon_readdata_p1 <= X"000"&"000"&cs_mode_register;
when "100" =>
avalon_readdata_p1 <= delay_register;
when "101" =>
avalon_readdata_p1 <= X"000"&"000"&buffer_select_register;
when "110" =>
avalon_readdata_p1 <= X"DEAF";
when "111" =>
avalon_readdata_p1 <= X"FACE";
when others =>
avalon_readdata_p1 <= X"ABBA";
end case;
when others =>
null;
end case;
end if;
end if;
end process;
avalon_readdata <= avalon_readdata_p1 when rising_edge(clock);
avalon_readdatavalid <= avalon_readdatavalid_p1 when rising_edge(clock);
--Avalon regs write interface
process (clock)
begin
if rising_edge(clock) then
transaction_prestart_1 <= '0';
writebuffer_write1 <= '0';
writebuffer_write2 <= '0';
readbuffer_write1 <= '0';
readbuffer_write2 <= '0';
if avalon_write= '1' then
case avalon_address(13 downto 11) is
when "000" =>
writebuffer_write1 <= '1';
when "001" =>
writebuffer_write2 <= '1';
when "010" =>
readbuffer_write1 <= '1';
when "011" =>
readbuffer_write2 <= '1';
when "100" =>
case avalon_address(2 downto 0) is
when "000" =>
transaction_prestart_1 <= avalon_writedata(0);
when "001" =>
length_register <= avalon_writedata(10 downto 0);
when "010" =>
null;
when "011" =>
cs_mode_register <= avalon_writedata(0);
when "100" =>
delay_register <= avalon_writedata;
when "101" =>
buffer_select_register <= avalon_writedata(0);
when others =>
null;
end case;
when others =>
null;
end case;
end if;
end if;
end process;
--async avalon write decoders
--writebuffer_write1 <= avalon_write when avalon_address(13 downto 11) = "000" else '0';
--writebuffer_write2 <= avalon_write when avalon_address(13 downto 11) = "001" else '0';
--readbuffer_write1 <= avalon_write when avalon_address(13 downto 11) = "010" else '0';
--readbuffer_write2 <= avalon_write when avalon_address(13 downto 11) = "011" else '0';
--delaying transaction_start cor a clock cycle to wait for cs
process (clock)
begin
if rising_edge(clock) then
if transaction_prestart_1 = '1' then
transaction_prestart_2 <= '1';
elsif transaction_clkdiv_counter = "1011" then
transaction_prestart_2 <= '0';
end if;
end if;
end process;
process (clock)
begin
if rising_edge(clock) then
if transaction_clkdiv_counter = "1011" then
transaction_start<= transaction_prestart_2;
end if;
end if;
end process;
transaction_byte_counter_p1 <= transaction_byte_counter when rising_edge(clock);
-- --read buffer1, should be inferred as 1.5-port block ram
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- if (readbuffer_write1 = '1') then
-- read_buffer1(to_integer(unsigned(avalon_address(8 downto 0)))) <= avalon_writedata;
-- end if;
-- avalon_readdata_readbuf1 <= read_buffer1(to_integer(unsigned(avalon_address(8 downto 0))));
-- if (readbuffer_transaction_write1 = '1') then
-- read_buffer1(to_integer(unsigned(transaction_byte_counter_p1(8 downto 0)))) <= transaction_data_read;
-- end if;
-- end if;
-- end process;
-- --read buffer2
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- if (readbuffer_write2 = '1') then
-- read_buffer2(to_integer(unsigned(avalon_address(8 downto 0)))) <= avalon_writedata;
-- end if;
-- avalon_readdata_readbuf2 <= read_buffer2(to_integer(unsigned(avalon_address(8 downto 0))));
-- if (readbuffer_transaction_write2 = '1') then
-- read_buffer2(to_integer(unsigned(transaction_byte_counter_p1(8 downto 0)))) <= transaction_data_read;
-- end if;
-- end if;
-- end process;
-- --write buffer1
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- if (writebuffer_write1 = '1') then
-- write_buffer1(to_integer(unsigned(avalon_address(8 downto 0)))) <= avalon_writedata;
-- end if;
-- transaction_data_write1 <= write_buffer1(to_integer(unsigned(transaction_byte_counter(8 downto 0))));
-- avalon_readdata_writebuf1 <= write_buffer1(to_integer(unsigned(avalon_address(8 downto 0))));
-- end if;
-- end process;
-- --write buffer2
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- if (writebuffer_write2 = '1') then
-- write_buffer2(to_integer(unsigned(avalon_address(8 downto 0)))) <= avalon_writedata;
-- end if;
-- transaction_data_write2 <= write_buffer2(to_integer(unsigned(transaction_byte_counter(8 downto 0))));
-- avalon_readdata_writebuf2 <= write_buffer2(to_integer(unsigned(avalon_address(8 downto 0))));
-- end if;
-- end process;
--using bram cores instead
read1_buf: buff_spi_ram
port map
(
address_a => avalon_address_latched(8 downto 0),
address_b => std_logic_vector(transaction_byte_counter_p1(8 downto 0)),
clock => clock,
data_a => avalon_writedata,
data_b => transaction_data_read,
wren_a => readbuffer_write1,
wren_b => readbuffer_transaction_write1,
q_a => avalon_readdata_readbuf1,
q_b => open --write-only port
);
read2_buf: buff_spi_ram
port map
(
address_a => avalon_address_latched(8 downto 0),
address_b => std_logic_vector(transaction_byte_counter_p1(8 downto 0)),
clock => clock,
data_a => avalon_writedata,
data_b => transaction_data_read,
wren_a => readbuffer_write2,
wren_b => readbuffer_transaction_write2,
q_a => avalon_readdata_readbuf2,
q_b => open --write-only port
);
write1_buf: buff_spi_ram
port map
(
address_a => avalon_address_latched(8 downto 0),
address_b => std_logic_vector(transaction_byte_counter(8 downto 0)),
clock => clock,
data_a => avalon_writedata,
data_b => X"0000",
wren_a => writebuffer_write1,
wren_b => '0', --read-only port
q_a => avalon_readdata_writebuf1,
q_b => transaction_data_write1
);
write2_buf: buff_spi_ram
port map
(
address_a => avalon_address_latched(8 downto 0),
address_b => std_logic_vector(transaction_byte_counter(8 downto 0)),
clock => clock,
data_a => avalon_writedata,
data_b => X"0000",
wren_a => writebuffer_write2,
wren_b => '0', --read-only port
q_a => avalon_readdata_writebuf2,
q_b => transaction_data_write2
);
--Avalon interface is only regs, so always ready to write.
avalon_waitrequest <= '0';
--transaction bit counter
process (clock)
begin
if rising_edge(clock) then
if (transaction_start = '1') then
transaction_bit_counter <= to_unsigned(0,16);
elsif (transaction_clkdiv_counter = "1000") and transaction_active = '1' then
if transaction_bit_counter < 16 + unsigned(delay_register) then
transaction_bit_counter <= transaction_bit_counter + 1;
else
transaction_bit_counter <= to_unsigned(0,16);
end if;
end if;
end if;
end process;
--transaction byte counter
process (clock)
begin
if rising_edge(clock) then
if (transaction_start = '1') then
transaction_byte_counter <= to_unsigned(0,12);
elsif transaction_clkdiv_counter = "1001" and transaction_active = '1' then
if transaction_byte_counter <= unsigned(length_register) then
if transaction_bit_counter = to_unsigned(16,16) then --16 bits per frame
transaction_byte_counter <= transaction_byte_counter + 1;
end if;
end if;
end if;
end if;
end process;
--transaction active flag
process (clock)
begin
if rising_edge(clock) then
if (transaction_start = '1') then
transaction_active <= '1';
elsif transaction_byte_counter = unsigned(length_register) then
transaction_active <= '0';
end if;
end if;
end process;
--transaction active flag for nios to read
process (clock)
begin
if rising_edge(clock) then
if (transaction_prestart_1 = '1') then
transaction_active_readreg <= '1';
elsif transaction_byte_counter = unsigned(length_register) then
transaction_active_readreg <= '0';
end if;
end if;
end process;
--transaction clock divider (test clockspeed is 1/16, 7.25 Mhz for 116Mhz base clock)
process (clock)
begin
if rising_edge(clock) then
if (transaction_prestart_1 = '1') then
transaction_clkdiv_counter <= "1100";
else
transaction_clkdiv_counter <= std_logic_vector(unsigned(transaction_clkdiv_counter) + 1);
end if;
end if;
end process;
-- SPI CLK output
process (clock)
begin
if rising_edge(clock) then
if (transaction_active = '1') and transaction_bit_counter <= to_unsigned(15,16) then
if (transaction_clkdiv_counter = "0001") and (transaction_start = '0') then
spi_clk <= '1';
elsif (transaction_clkdiv_counter = "1001") then
spi_clk <= '0';
end if;
else
spi_clk <= '0';
end if;
end if;
end process;
-- SPI MOSI output
process (clock)
begin
if rising_edge(clock) then
if (transaction_active = '0') then
spi_mosi <= '0';
elsif (buffer_select_register = '0') then
spi_mosi <= transaction_data_write1(15-to_integer(transaction_bit_counter(3 downto 0)));
else
spi_mosi <= transaction_data_write2(15-to_integer(transaction_bit_counter(3 downto 0)));
end if;
end if;
end process;
-- SPI CS output
transaction_active_p1 <= transaction_active when rising_edge(clock);
process (clock)
begin
if rising_edge(clock) then
if transaction_prestart_1 = '1' then
spi_cs_gappy <= '0';
elsif (transaction_bit_counter = to_unsigned(16,16)) then
spi_cs_gappy <= '1';
elsif (transaction_bit_counter = to_unsigned(0,16)) then
spi_cs_gappy <= '0';
elsif transaction_active = '0' and transaction_active_p1 = '1' then
spi_cs_gappy <= '1';
end if;
end if;
end process;
process (clock)
begin
if rising_edge(clock) then
if transaction_prestart_1 = '1' then
spi_cs_constant <= '0';
elsif transaction_active = '0' and transaction_active_p1 = '1' then
spi_cs_constant <= '1';
end if;
end if;
end process;
spi_cs <= spi_cs_gappy when cs_mode_register = '1' else
spi_cs_constant;
-- SPI MISO input
process (clock)
begin
if rising_edge(clock) then
if (transaction_active = '1') and transaction_bit_counter <= to_unsigned(15,16) then
transaction_data_read(15-to_integer(transaction_bit_counter(3 downto 0))) <= spi_miso;
end if;
end if;
end process;
transaction_bit_counter_p1 <= transaction_bit_counter when rising_edge(clock);
process (clock)
begin
if rising_edge(clock) then
readbuffer_transaction_write1 <= '0';
readbuffer_transaction_write2 <= '0';
if (transaction_active = '1') and transaction_bit_counter = to_unsigned(16,16) and transaction_bit_counter_p1 = to_unsigned(15,16) then
if (buffer_select_register = '0') then
readbuffer_transaction_write1 <= '1';
else
readbuffer_transaction_write2 <= '1';
end if;
end if;
end if;
end process;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
entity buffered_spi is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
avalon_read : in STD_LOGIC;
avalon_write : in STD_LOGIC;
avalon_address : in STD_LOGIC_VECTOR (13 downto 0);
avalon_waitrequest : out std_logic := '0';
avalon_writedata : in STD_LOGIC_VECTOR (15 downto 0);
avalon_readdata : out STD_LOGIC_VECTOR (15 downto 0);
avalon_readdatavalid : out std_logic := '0';
spi_mosi : out STD_LOGIC := '0';
spi_clk : out STD_LOGIC := '0';
spi_miso : in STD_LOGIC;
spi_cs : out STD_LOGIC := '1');
end buffered_spi;
architecture Behavioral of buffered_spi is
signal transaction_active : std_logic := '0';
signal transaction_active_p1 : std_logic := '0';
signal transaction_active_readreg : std_logic := '0';
signal writebuffer_write1 : std_logic := '0';
signal writebuffer_write2 : std_logic := '0';
signal readbuffer_write1 : std_logic := '0';
signal readbuffer_write2 : std_logic := '0';
signal readbuffer_transaction_write1 : std_logic := '0';
signal readbuffer_transaction_write2 : std_logic := '0';
signal transaction_prestart_1 : std_logic := '0';
signal transaction_prestart_2 : std_logic := '0';
signal transaction_start : std_logic := '0';
signal transaction_bit_counter : unsigned (15 downto 0) := (others => '1');
signal transaction_bit_counter_p1 : unsigned (15 downto 0) := (others => '1');
signal transaction_byte_counter : unsigned (11 downto 0) := (others => '1');
signal transaction_byte_counter_p1 : unsigned (11 downto 0) := (others => '1');
signal transaction_data_read : std_logic_vector (15 downto 0) := (others => '0');
signal transaction_data_write1 : std_logic_vector (15 downto 0) := (others => '0');
signal transaction_data_write2 : std_logic_vector (15 downto 0) := (others => '0');
signal transaction_buf_write1 : std_logic := '0';
signal transaction_buf_write2 : std_logic := '0';
signal transaction_clkdiv_counter : std_logic_vector (3 downto 0) := (others => '0');
signal spi_cs_constant : std_logic := '1';
signal spi_cs_gappy : std_logic := '1';
signal length_register : std_logic_vector(10 downto 0) := (others => '0');
signal cs_mode_register : std_logic := '0';
signal delay_register : std_logic_vector(15 downto 0) := (others => '0');
signal buffer_select_register : std_logic := '0';
signal avalon_readdata_readbuf1 : std_logic_vector (15 downto 0);
signal avalon_readdata_writebuf1 : std_logic_vector (15 downto 0);
signal avalon_readdata_readbuf2 : std_logic_vector (15 downto 0);
signal avalon_readdata_writebuf2 : std_logic_vector (15 downto 0);
--signal avalon_address_f1 : std_logic_vector (13 downto 0);
signal avalon_readdata_p1 : std_logic_vector (15 downto 0);
signal avalon_read_f1 : STD_LOGIC;
signal avalon_read_f2 : STD_LOGIC;
signal avalon_address_latched : std_logic_vector (13 downto 0);
signal avalon_readdatavalid_p1 : STD_LOGIC;
--inferred ram, quartus fails to recognize'em like bram
--type spi_buf_type is array(0 to 511) of std_logic_vector(15 downto 0);
--signal write_buffer1 : spi_buf_type;
--signal read_buffer1 : spi_buf_type;
--signal write_buffer2 : spi_buf_type;
--signal read_buffer2 : spi_buf_type;
--using core-generated bram instead
component buff_spi_ram IS
PORT
(
address_a : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
address_b : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
clock : IN STD_LOGIC := '1';
data_a : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
data_b : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
wren_a : IN STD_LOGIC := '0';
wren_b : IN STD_LOGIC := '0';
q_a : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
q_b : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
);
end component;
begin
avalon_address_latched <= avalon_address when rising_edge(clock) and (avalon_read = '1' or avalon_write = '1');
avalon_read_f1 <= avalon_read when rising_edge(clock);
avalon_read_f2 <= avalon_read_f1 when rising_edge(clock);
--Avalon regs read interface
process (clock)
begin
if rising_edge(clock) then
avalon_readdatavalid_p1 <= '0';
if avalon_read_f2 = '1' then
avalon_readdatavalid_p1 <= '1';
case avalon_address_latched(13 downto 11) is
when "000" =>
avalon_readdata_p1 <= avalon_readdata_writebuf1;
when "001" =>
avalon_readdata_p1 <= avalon_readdata_writebuf2;
when "010" =>
avalon_readdata_p1 <= avalon_readdata_readbuf1;
when "011" =>
avalon_readdata_p1 <= avalon_readdata_readbuf2;
when "100" =>
case avalon_address_latched(2 downto 0) is
when "000" =>
avalon_readdata_p1 <= X"000"&"000"&transaction_active_readreg;
when "001" =>
avalon_readdata_p1 <= X"0"&"0"&length_register;
when "010" =>
avalon_readdata_p1 <= X"0"&std_logic_vector(transaction_byte_counter);
when "011" =>
avalon_readdata_p1 <= X"000"&"000"&cs_mode_register;
when "100" =>
avalon_readdata_p1 <= delay_register;
when "101" =>
avalon_readdata_p1 <= X"000"&"000"&buffer_select_register;
when "110" =>
avalon_readdata_p1 <= X"DEAF";
when "111" =>
avalon_readdata_p1 <= X"FACE";
when others =>
avalon_readdata_p1 <= X"ABBA";
end case;
when others =>
null;
end case;
end if;
end if;
end process;
avalon_readdata <= avalon_readdata_p1 when rising_edge(clock);
avalon_readdatavalid <= avalon_readdatavalid_p1 when rising_edge(clock);
--Avalon regs write interface
process (clock)
begin
if rising_edge(clock) then
transaction_prestart_1 <= '0';
writebuffer_write1 <= '0';
writebuffer_write2 <= '0';
readbuffer_write1 <= '0';
readbuffer_write2 <= '0';
if avalon_write= '1' then
case avalon_address(13 downto 11) is
when "000" =>
writebuffer_write1 <= '1';
when "001" =>
writebuffer_write2 <= '1';
when "010" =>
readbuffer_write1 <= '1';
when "011" =>
readbuffer_write2 <= '1';
when "100" =>
case avalon_address(2 downto 0) is
when "000" =>
transaction_prestart_1 <= avalon_writedata(0);
when "001" =>
length_register <= avalon_writedata(10 downto 0);
when "010" =>
null;
when "011" =>
cs_mode_register <= avalon_writedata(0);
when "100" =>
delay_register <= avalon_writedata;
when "101" =>
buffer_select_register <= avalon_writedata(0);
when others =>
null;
end case;
when others =>
null;
end case;
end if;
end if;
end process;
--async avalon write decoders
--writebuffer_write1 <= avalon_write when avalon_address(13 downto 11) = "000" else '0';
--writebuffer_write2 <= avalon_write when avalon_address(13 downto 11) = "001" else '0';
--readbuffer_write1 <= avalon_write when avalon_address(13 downto 11) = "010" else '0';
--readbuffer_write2 <= avalon_write when avalon_address(13 downto 11) = "011" else '0';
--delaying transaction_start cor a clock cycle to wait for cs
process (clock)
begin
if rising_edge(clock) then
if transaction_prestart_1 = '1' then
transaction_prestart_2 <= '1';
elsif transaction_clkdiv_counter = "1011" then
transaction_prestart_2 <= '0';
end if;
end if;
end process;
process (clock)
begin
if rising_edge(clock) then
if transaction_clkdiv_counter = "1011" then
transaction_start<= transaction_prestart_2;
end if;
end if;
end process;
transaction_byte_counter_p1 <= transaction_byte_counter when rising_edge(clock);
-- --read buffer1, should be inferred as 1.5-port block ram
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- if (readbuffer_write1 = '1') then
-- read_buffer1(to_integer(unsigned(avalon_address(8 downto 0)))) <= avalon_writedata;
-- end if;
-- avalon_readdata_readbuf1 <= read_buffer1(to_integer(unsigned(avalon_address(8 downto 0))));
-- if (readbuffer_transaction_write1 = '1') then
-- read_buffer1(to_integer(unsigned(transaction_byte_counter_p1(8 downto 0)))) <= transaction_data_read;
-- end if;
-- end if;
-- end process;
-- --read buffer2
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- if (readbuffer_write2 = '1') then
-- read_buffer2(to_integer(unsigned(avalon_address(8 downto 0)))) <= avalon_writedata;
-- end if;
-- avalon_readdata_readbuf2 <= read_buffer2(to_integer(unsigned(avalon_address(8 downto 0))));
-- if (readbuffer_transaction_write2 = '1') then
-- read_buffer2(to_integer(unsigned(transaction_byte_counter_p1(8 downto 0)))) <= transaction_data_read;
-- end if;
-- end if;
-- end process;
-- --write buffer1
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- if (writebuffer_write1 = '1') then
-- write_buffer1(to_integer(unsigned(avalon_address(8 downto 0)))) <= avalon_writedata;
-- end if;
-- transaction_data_write1 <= write_buffer1(to_integer(unsigned(transaction_byte_counter(8 downto 0))));
-- avalon_readdata_writebuf1 <= write_buffer1(to_integer(unsigned(avalon_address(8 downto 0))));
-- end if;
-- end process;
-- --write buffer2
-- process (clock)
-- begin
-- if rising_edge(clock) then
-- if (writebuffer_write2 = '1') then
-- write_buffer2(to_integer(unsigned(avalon_address(8 downto 0)))) <= avalon_writedata;
-- end if;
-- transaction_data_write2 <= write_buffer2(to_integer(unsigned(transaction_byte_counter(8 downto 0))));
-- avalon_readdata_writebuf2 <= write_buffer2(to_integer(unsigned(avalon_address(8 downto 0))));
-- end if;
-- end process;
--using bram cores instead
read1_buf: buff_spi_ram
port map
(
address_a => avalon_address_latched(8 downto 0),
address_b => std_logic_vector(transaction_byte_counter_p1(8 downto 0)),
clock => clock,
data_a => avalon_writedata,
data_b => transaction_data_read,
wren_a => readbuffer_write1,
wren_b => readbuffer_transaction_write1,
q_a => avalon_readdata_readbuf1,
q_b => open --write-only port
);
read2_buf: buff_spi_ram
port map
(
address_a => avalon_address_latched(8 downto 0),
address_b => std_logic_vector(transaction_byte_counter_p1(8 downto 0)),
clock => clock,
data_a => avalon_writedata,
data_b => transaction_data_read,
wren_a => readbuffer_write2,
wren_b => readbuffer_transaction_write2,
q_a => avalon_readdata_readbuf2,
q_b => open --write-only port
);
write1_buf: buff_spi_ram
port map
(
address_a => avalon_address_latched(8 downto 0),
address_b => std_logic_vector(transaction_byte_counter(8 downto 0)),
clock => clock,
data_a => avalon_writedata,
data_b => X"0000",
wren_a => writebuffer_write1,
wren_b => '0', --read-only port
q_a => avalon_readdata_writebuf1,
q_b => transaction_data_write1
);
write2_buf: buff_spi_ram
port map
(
address_a => avalon_address_latched(8 downto 0),
address_b => std_logic_vector(transaction_byte_counter(8 downto 0)),
clock => clock,
data_a => avalon_writedata,
data_b => X"0000",
wren_a => writebuffer_write2,
wren_b => '0', --read-only port
q_a => avalon_readdata_writebuf2,
q_b => transaction_data_write2
);
--Avalon interface is only regs, so always ready to write.
avalon_waitrequest <= '0';
--transaction bit counter
process (clock)
begin
if rising_edge(clock) then
if (transaction_start = '1') then
transaction_bit_counter <= to_unsigned(0,16);
elsif (transaction_clkdiv_counter = "1000") and transaction_active = '1' then
if transaction_bit_counter < 16 + unsigned(delay_register) then
transaction_bit_counter <= transaction_bit_counter + 1;
else
transaction_bit_counter <= to_unsigned(0,16);
end if;
end if;
end if;
end process;
--transaction byte counter
process (clock)
begin
if rising_edge(clock) then
if (transaction_start = '1') then
transaction_byte_counter <= to_unsigned(0,12);
elsif transaction_clkdiv_counter = "1001" and transaction_active = '1' then
if transaction_byte_counter <= unsigned(length_register) then
if transaction_bit_counter = to_unsigned(16,16) then --16 bits per frame
transaction_byte_counter <= transaction_byte_counter + 1;
end if;
end if;
end if;
end if;
end process;
--transaction active flag
process (clock)
begin
if rising_edge(clock) then
if (transaction_start = '1') then
transaction_active <= '1';
elsif transaction_byte_counter = unsigned(length_register) then
transaction_active <= '0';
end if;
end if;
end process;
--transaction active flag for nios to read
process (clock)
begin
if rising_edge(clock) then
if (transaction_prestart_1 = '1') then
transaction_active_readreg <= '1';
elsif transaction_byte_counter = unsigned(length_register) then
transaction_active_readreg <= '0';
end if;
end if;
end process;
--transaction clock divider (test clockspeed is 1/16, 7.25 Mhz for 116Mhz base clock)
process (clock)
begin
if rising_edge(clock) then
if (transaction_prestart_1 = '1') then
transaction_clkdiv_counter <= "1100";
else
transaction_clkdiv_counter <= std_logic_vector(unsigned(transaction_clkdiv_counter) + 1);
end if;
end if;
end process;
-- SPI CLK output
process (clock)
begin
if rising_edge(clock) then
if (transaction_active = '1') and transaction_bit_counter <= to_unsigned(15,16) then
if (transaction_clkdiv_counter = "0001") and (transaction_start = '0') then
spi_clk <= '1';
elsif (transaction_clkdiv_counter = "1001") then
spi_clk <= '0';
end if;
else
spi_clk <= '0';
end if;
end if;
end process;
-- SPI MOSI output
process (clock)
begin
if rising_edge(clock) then
if (transaction_active = '0') then
spi_mosi <= '0';
elsif (buffer_select_register = '0') then
spi_mosi <= transaction_data_write1(15-to_integer(transaction_bit_counter(3 downto 0)));
else
spi_mosi <= transaction_data_write2(15-to_integer(transaction_bit_counter(3 downto 0)));
end if;
end if;
end process;
-- SPI CS output
transaction_active_p1 <= transaction_active when rising_edge(clock);
process (clock)
begin
if rising_edge(clock) then
if transaction_prestart_1 = '1' then
spi_cs_gappy <= '0';
elsif (transaction_bit_counter = to_unsigned(16,16)) then
spi_cs_gappy <= '1';
elsif (transaction_bit_counter = to_unsigned(0,16)) then
spi_cs_gappy <= '0';
elsif transaction_active = '0' and transaction_active_p1 = '1' then
spi_cs_gappy <= '1';
end if;
end if;
end process;
process (clock)
begin
if rising_edge(clock) then
if transaction_prestart_1 = '1' then
spi_cs_constant <= '0';
elsif transaction_active = '0' and transaction_active_p1 = '1' then
spi_cs_constant <= '1';
end if;
end if;
end process;
spi_cs <= spi_cs_gappy when cs_mode_register = '1' else
spi_cs_constant;
-- SPI MISO input
process (clock)
begin
if rising_edge(clock) then
if (transaction_active = '1') and transaction_bit_counter <= to_unsigned(15,16) then
transaction_data_read(15-to_integer(transaction_bit_counter(3 downto 0))) <= spi_miso;
end if;
end if;
end process;
transaction_bit_counter_p1 <= transaction_bit_counter when rising_edge(clock);
process (clock)
begin
if rising_edge(clock) then
readbuffer_transaction_write1 <= '0';
readbuffer_transaction_write2 <= '0';
if (transaction_active = '1') and transaction_bit_counter = to_unsigned(16,16) and transaction_bit_counter_p1 = to_unsigned(15,16) then
if (buffer_select_register = '0') then
readbuffer_transaction_write1 <= '1';
else
readbuffer_transaction_write2 <= '1';
end if;
end if;
end if;
end process;
end Behavioral;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2013 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file vram.vhd when simulating
-- the core, vram. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY vram IS
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END vram;
ARCHITECTURE vram_a OF vram IS
-- synthesis translate_off
COMPONENT wrapped_vram
PORT (
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_vram USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral)
GENERIC MAP (
c_addra_width => 13,
c_addrb_width => 13,
c_algorithm => 1,
c_axi_id_width => 4,
c_axi_slave_type => 0,
c_axi_type => 1,
c_byte_size => 9,
c_common_clk => 0,
c_default_data => "00",
c_disable_warn_bhv_coll => 0,
c_disable_warn_bhv_range => 0,
c_enable_32bit_address => 0,
c_family => "spartan6",
c_has_axi_id => 0,
c_has_ena => 0,
c_has_enb => 0,
c_has_injecterr => 0,
c_has_mem_output_regs_a => 0,
c_has_mem_output_regs_b => 0,
c_has_mux_output_regs_a => 0,
c_has_mux_output_regs_b => 0,
c_has_regcea => 0,
c_has_regceb => 0,
c_has_rsta => 0,
c_has_rstb => 0,
c_has_softecc_input_regs_a => 0,
c_has_softecc_output_regs_b => 0,
c_init_file => "BlankString",
c_init_file_name => "no_coe_file_loaded",
c_inita_val => "0",
c_initb_val => "0",
c_interface_type => 0,
c_load_init_file => 0,
c_mem_type => 2,
c_mux_pipeline_stages => 0,
c_prim_type => 1,
c_read_depth_a => 7168,
c_read_depth_b => 7168,
c_read_width_a => 8,
c_read_width_b => 8,
c_rst_priority_a => "CE",
c_rst_priority_b => "CE",
c_rst_type => "SYNC",
c_rstram_a => 0,
c_rstram_b => 0,
c_sim_collision_check => "ALL",
c_use_bram_block => 0,
c_use_byte_wea => 0,
c_use_byte_web => 0,
c_use_default_data => 1,
c_use_ecc => 0,
c_use_softecc => 0,
c_wea_width => 1,
c_web_width => 1,
c_write_depth_a => 7168,
c_write_depth_b => 7168,
c_write_mode_a => "WRITE_FIRST",
c_write_mode_b => "WRITE_FIRST",
c_write_width_a => 8,
c_write_width_b => 8,
c_xdevicefamily => "spartan6"
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_vram
PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb
);
-- synthesis translate_on
END vram_a;
|
library verilog;
use verilog.vl_types.all;
entity pll_iobuf is
port(
i : in vl_logic;
oe : in vl_logic;
io : inout vl_logic;
o : out vl_logic
);
end pll_iobuf;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_10_bvat-b.vhd,v 1.3 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library bv_utilities;
use std.textio.all, bv_utilities.bv_arithmetic.all;
architecture bench of bv_test is
begin
process is
variable L : line;
variable byte : bit_vector(0 to 7);
variable word : bit_vector(1 to 32);
variable half_byte : bit_vector(1 to 4);
variable overflow, div_by_zero, result : boolean;
begin
wait for 1 ns;
----------------------------------------------------------------
----------------------------------------------------------------
-- test bit_vector to numeric conversions
----------------------------------------------------------------
----------------------------------------------------------------
write(L, string'("Testing bv_to_natural:"));
writeline(output, L);
write(L, string'(" bv_to_natural(X""02"") = "));
write(L, bv_to_natural(X"02"));
writeline(output, L);
assert bv_to_natural(X"02") = 2;
write(L, string'(" bv_to_natural(X""FE"") = "));
write(L, bv_to_natural(X"FE"));
writeline(output, L);
assert bv_to_natural(X"FE") = 254;
----------------------------------------------------------------
write(L, string'("Testing natural_to_bv:"));
writeline(output, L);
write(L, string'(" natural_to_bv(2) = "));
write(L, natural_to_bv(2, 8));
writeline(output, L);
assert natural_to_bv(2, 8) = X"02";
write(L, string'(" natural_to_bv(254) = "));
write(L, natural_to_bv(254, 8));
writeline(output, L);
assert natural_to_bv(254, 8) = X"FE";
----------------------------------------------------------------
write(L, string'("Testing bv_to_integer:"));
writeline(output, L);
write(L, string'(" bv_to_integer(X""02"") = "));
write(L, bv_to_integer(X"02"));
writeline(output, L);
assert bv_to_integer(X"02") = 2;
write(L, string'(" bv_to_integer(X""FE"") = "));
write(L, bv_to_integer(X"FE"));
writeline(output, L);
assert bv_to_integer(X"FE") = -2;
----------------------------------------------------------------
write(L, string'("Testing integer_to_bv:"));
writeline(output, L);
write(L, string'(" integer_to_bv(2) = "));
write(L, integer_to_bv(2, 8));
writeline(output, L);
assert integer_to_bv(2, 8) = X"02";
write(L, string'(" integer_to_bv(-2) = "));
write(L, integer_to_bv(-2, 8));
writeline(output, L);
assert integer_to_bv(-2, 8) = X"FE";
----------------------------------------------------------------
----------------------------------------------------------------
-- Arithmetic operations
----------------------------------------------------------------
----------------------------------------------------------------
----------------------------------------------------------------
-- bv_add: Signed addition with overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_add with overflow:"));
writeline(output, L);
write(L, string'(" 2+2 = "));
bv_add(X"02", X"02", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"04" and not overflow;
write(L, string'(" 2+(-3) = "));
bv_add(X"02", X"FD", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"FF" and not overflow;
write(L, string'(" 64+64 = "));
bv_add(X"40", X"40", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and overflow;
write(L, string'(" -64+(-64) = "));
bv_add(X"C0", X"C0", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and not overflow;
----------------------------------------------------------------
-- "+": Signed addition without overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing ""+"" without overflow:"));
writeline(output, L);
write(L, string'(" 2+2 = "));
byte := X"02" + X"02";
write(L, byte);
writeline(output, L);
assert byte = X"04";
write(L, string'(" 2+(-3) = "));
byte := X"02" + X"FD";
write(L, byte);
writeline(output, L);
assert byte = X"FF";
write(L, string'(" 64+64 = "));
byte := X"40" + X"40";
write(L, byte);
writeline(output, L);
assert byte = X"80";
write(L, string'(" -64+(-64) = "));
byte := X"C0" + X"C0";
write(L, byte);
writeline(output, L);
assert byte = X"80";
----------------------------------------------------------------
-- bv_sub: Signed subtraction with overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_sub with overflow:"));
writeline(output, L);
write(L, string'(" 2-2 = "));
bv_sub(X"02", X"02", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"00" and not overflow;
write(L, string'(" 2-(-3) = "));
bv_sub(X"02", X"FD", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"05" and not overflow;
write(L, string'(" 64-(-64) = "));
bv_sub(X"40", X"C0", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and overflow;
write(L, string'(" -64-64 = "));
bv_sub(X"C0", X"40", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and not overflow;
----------------------------------------------------------------
-- "-": Signed subtraction without overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing ""-"" without overflow:"));
writeline(output, L);
write(L, string'(" 2-2 = "));
byte := X"02" - X"02";
write(L, byte);
writeline(output, L);
assert byte = X"00";
write(L, string'(" 2-(-3) = "));
byte := X"02" - X"FD";
write(L, byte);
writeline(output, L);
assert byte = X"05";
write(L, string'(" 64-(-64) = "));
byte := X"40" - X"C0";
write(L, byte);
writeline(output, L);
assert byte = X"80";
write(L, string'(" -64-64 = "));
byte := X"C0" - X"40";
write(L, byte);
writeline(output, L);
assert byte = X"80";
----------------------------------------------------------------
-- bv_addu: Unsigned addition with overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_addu with overflow:"));
writeline(output, L);
write(L, string'(" 2+2 = "));
bv_addu(X"02", X"02", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"04" and not overflow;
write(L, string'(" 64+64 = "));
bv_addu(X"40", X"40", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and not overflow;
write(L, string'(" 128+128 = "));
bv_addu(X"80", X"80", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"00" and overflow;
----------------------------------------------------------------
-- bv_addu: Unsigned addition without overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_addu without overflow:"));
writeline(output, L);
write(L, string'(" 2+2 = "));
byte := bv_addu(X"02", X"02");
write(L, byte);
writeline(output, L);
assert byte = X"04";
write(L, string'(" 64+64 = "));
byte := bv_addu(X"40", X"40");
write(L, byte);
writeline(output, L);
assert byte = X"80";
write(L, string'(" 128+128 = "));
byte := bv_addu(X"80", X"80");
write(L, byte);
writeline(output, L);
assert byte = X"00";
----------------------------------------------------------------
-- bv_subu: Unsigned subtraction with overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_subu with overflow:"));
writeline(output, L);
write(L, string'(" 3-2 = "));
bv_subu(X"03", X"02", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"01" and not overflow;
write(L, string'(" 64-64 = "));
bv_subu(X"40", X"40", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"00" and not overflow;
write(L, string'(" 64-128 = "));
bv_subu(X"40", X"80", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"C0" and overflow;
----------------------------------------------------------------
-- bv_subu: Unsigned subtraction without overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_subu without overflow:"));
writeline(output, L);
write(L, string'(" 3-2 = "));
byte := bv_subu(X"03", X"02");
write(L, byte);
writeline(output, L);
assert byte = X"01";
write(L, string'(" 64-64 = "));
byte := bv_subu(X"40", X"40");
write(L, byte);
writeline(output, L);
assert byte = X"00";
write(L, string'(" 64-128 = "));
byte := bv_subu(X"40", X"80");
write(L, byte);
writeline(output, L);
assert byte = X"C0";
----------------------------------------------------------------
-- bv_neg: Signed negation with overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_neg with overflow:"));
writeline(output, L);
write(L, string'(" -(3) = "));
bv_neg(X"03", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"FD" and not overflow;
write(L, string'(" -(-3) = "));
bv_neg(X"FD", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"03" and not overflow;
write(L, string'(" -(127) = "));
bv_neg(X"7F", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"81" and not overflow;
write(L, string'(" -(-128) = "));
bv_neg(X"80", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and overflow;
----------------------------------------------------------------
-- "-": Signed negation without overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing ""-"" without overflow:"));
writeline(output, L);
write(L, string'(" -(3) = "));
byte := - X"03";
write(L, byte);
writeline(output, L);
assert byte = X"FD";
write(L, string'(" -(-3) = "));
byte := - X"FD";
write(L, byte);
writeline(output, L);
assert byte = X"03";
write(L, string'(" -(127) = "));
byte := - X"7F";
write(L, byte);
writeline(output, L);
assert byte = X"81";
write(L, string'(" -(-128) = "));
byte := - X"80";
write(L, byte);
writeline(output, L);
assert byte = X"80";
----------------------------------------------------------------
-- bv_mult: Signed multiplication with overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_mult with overflow:"));
writeline(output, L);
write(L, string'(" 5*(-3) = "));
bv_mult(X"05", X"FD", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"F1" and not overflow;
write(L, string'(" (-5)*(-3) = "));
bv_mult(X"FB", X"FD", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"0F" and not overflow;
write(L, string'(" 16*8 = "));
bv_mult(X"10", X"08", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and overflow;
write(L, string'(" 16*16 = "));
bv_mult(X"10", X"10", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"00" and overflow;
write(L, string'(" 16*(-8) = "));
bv_mult(X"10", X"F8", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and not overflow;
write(L, string'(" 16*(-16) = "));
bv_mult(X"10", X"F0", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"00" and overflow;
----------------------------------------------------------------
-- "*": Signed multiplication without overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing ""*"" without overflow:"));
writeline(output, L);
write(L, string'(" 5*(-3) = "));
byte := X"05" * X"FD";
write(L, byte);
writeline(output, L);
assert byte = X"F1";
write(L, string'(" (-5)*(-3) = "));
byte := X"FB" * X"FD";
write(L, byte);
writeline(output, L);
assert byte = X"0F";
write(L, string'(" 16*8 = "));
byte := X"10" * X"08";
write(L, byte);
writeline(output, L);
assert byte = X"80";
write(L, string'(" 16*16 = "));
byte := X"10" * X"10";
write(L, byte);
writeline(output, L);
assert byte = X"00";
write(L, string'(" 16*(-8) = "));
byte := X"10" * X"F8";
write(L, byte);
writeline(output, L);
assert byte = X"80";
write(L, string'(" 16*(-16) = "));
byte := X"10" * X"F0";
write(L, byte);
writeline(output, L);
assert byte = X"00";
----------------------------------------------------------------
-- bv_multu: Unsigned multiplication with overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_multu with overflow:"));
writeline(output, L);
write(L, string'(" 5*7 = "));
bv_multu(X"05", X"07", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"23" and not overflow;
write(L, string'(" 16*8 = "));
bv_multu(X"10", X"08", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and not overflow;
write(L, string'(" 16*16 = "));
bv_multu(X"10", X"10", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"00" and overflow;
----------------------------------------------------------------
-- bv_multu: Unsigned multiplication without overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_multu without overflow:"));
writeline(output, L);
write(L, string'(" 5*7 = "));
byte := bv_multu(X"05", X"07");
write(L, byte);
writeline(output, L);
assert byte = X"23";
write(L, string'(" 16*8 = "));
byte := bv_multu(X"10", X"08");
write(L, byte);
writeline(output, L);
assert byte = X"80";
write(L, string'(" 16*16 = "));
byte := bv_multu(X"10", X"10");
write(L, byte);
writeline(output, L);
assert byte = X"00";
----------------------------------------------------------------
-- bv_div: Signed division with divide by zero and overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_div with flags:"));
writeline(output, L);
write(L, string'(" 7/2 = "));
bv_div(X"07", X"02", byte, div_by_zero, overflow);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"03" and not div_by_zero and not overflow;
write(L, string'(" -7/2 = "));
bv_div(X"F9", X"02", byte, div_by_zero, overflow);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"FD" and not div_by_zero and not overflow;
write(L, string'(" 7/-2 = "));
bv_div(X"07", X"FE", byte, div_by_zero, overflow);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"FD" and not div_by_zero and not overflow;
write(L, string'(" -7/-2 = "));
bv_div(X"F9", X"FE", byte, div_by_zero, overflow);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"03" and not div_by_zero and not overflow;
write(L, string'(" -128/1 = "));
bv_div(X"80", X"01", byte, div_by_zero, overflow);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and not div_by_zero and not overflow;
write(L, string'(" -128/-1 = "));
bv_div(X"80", X"FF", byte, div_by_zero, overflow);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and not div_by_zero and overflow;
write(L, string'(" -16/0 = "));
bv_div(X"F0", X"00", byte, div_by_zero, overflow);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"00" and div_by_zero and not overflow;
----------------------------------------------------------------
-- "/": Signed division without divide by zero and overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing ""/"" without flags:"));
writeline(output, L);
write(L, string'(" 7/2 = "));
byte := X"07" / X"02";
write(L, byte);
writeline(output, L);
assert byte = X"03";
write(L, string'(" -7/2 = "));
byte := X"F9" / X"02";
write(L, byte);
writeline(output, L);
assert byte = X"FD";
write(L, string'(" 7/-2 = "));
byte := X"07" / X"FE";
write(L, byte);
writeline(output, L);
assert byte = X"FD";
write(L, string'(" -7/-2 = "));
byte := X"F9" / X"FE";
write(L, byte);
writeline(output, L);
assert byte = X"03";
write(L, string'(" -128/1 = "));
byte := X"80" / X"01";
write(L, byte);
writeline(output, L);
assert byte = X"80";
write(L, string'(" -128/-1 = "));
byte := X"80" / X"FF";
write(L, byte);
writeline(output, L);
assert byte = X"80";
write(L, string'(" -16/0 = "));
byte := X"F0" / X"00";
write(L, byte);
writeline(output, L);
assert byte = X"00";
----------------------------------------------------------------
-- bv_divu: Unsigned division with divide by zero detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_divu with flag:"));
writeline(output, L);
write(L, string'(" 7/2 = "));
bv_divu(X"07", X"02", byte, div_by_zero);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
writeline(output, L);
assert byte = X"03" and not div_by_zero;
write(L, string'(" 14/7 = "));
bv_divu(X"0E", X"07", byte, div_by_zero);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
writeline(output, L);
assert byte = X"02" and not div_by_zero;
write(L, string'(" 16/1 = "));
bv_divu(X"10", X"01", byte, div_by_zero);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
writeline(output, L);
assert byte = X"10" and not div_by_zero;
write(L, string'(" 16/0 = "));
bv_divu(X"10", X"00", byte, div_by_zero);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
writeline(output, L);
assert byte = X"10" and div_by_zero;
write(L, string'(" 16/16 = "));
bv_divu(X"10", X"10", byte, div_by_zero);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
writeline(output, L);
assert byte = X"01" and not div_by_zero;
write(L, string'(" 1/16 = "));
bv_divu(X"01", X"10", byte, div_by_zero);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
writeline(output, L);
assert byte = X"00" and not div_by_zero;
write(L, string'(" 255/1 = "));
bv_divu(X"FF", X"01", byte, div_by_zero);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
writeline(output, L);
assert byte = X"FF" and not div_by_zero;
----------------------------------------------------------------
-- bv_divu: Unsigned division without divide by zero detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_divu without flag:"));
writeline(output, L);
write(L, string'(" 7/2 = "));
byte := bv_divu(X"07", X"02");
write(L, byte);
writeline(output, L);
assert byte = X"03";
write(L, string'(" 14/7 = "));
byte := bv_divu(X"0E", X"07");
write(L, byte);
writeline(output, L);
assert byte = X"02";
write(L, string'(" 16/1 = "));
byte := bv_divu(X"10", X"01");
write(L, byte);
writeline(output, L);
assert byte = X"10";
write(L, string'(" 16/0 = "));
byte := bv_divu(X"10", X"00");
write(L, byte);
writeline(output, L);
assert byte = X"00";
write(L, string'(" 16/16 = "));
byte := bv_divu(X"10", X"10");
write(L, byte);
writeline(output, L);
assert byte = X"01";
write(L, string'(" 1/16 = "));
byte := bv_divu(X"01", X"10");
write(L, byte);
writeline(output, L);
assert byte = X"00";
write(L, string'(" 255/1 = "));
byte := bv_divu(X"FF", X"01");
write(L, byte);
writeline(output, L);
assert byte = X"FF";
----------------------------------------------------------------
----------------------------------------------------------------
-- Arithmetic comparison operators.
----------------------------------------------------------------
----------------------------------------------------------------
----------------------------------------------------------------
-- bv_lt: Signed less than comparison
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_lt:"));
writeline(output, L);
write(L, string'(" 2 < 2 = "));
result := bv_lt(X"02", X"02");
write(L, result);
writeline(output, L);
assert NOT result;
write(L, string'(" 2 < 3 = "));
result := bv_lt(X"02", X"03");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" -2 < 2 = "));
result := bv_lt(X"FE", X"02");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" 2 < -3 = "));
result := bv_lt(X"02", X"FD");
write(L, result);
writeline(output, L);
assert NOT result;
----------------------------------------------------------------
-- bv_le: Signed less than or equal comparison
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_le:"));
writeline(output, L);
write(L, string'(" 2 <= 2 = "));
result := bv_le(X"02", X"02");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" 2 <= 3 = "));
result := bv_le(X"02", X"03");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" -2 <= 2 = "));
result := bv_le(X"FE", X"02");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" 2 <= -3 = "));
result := bv_le(X"02", X"FD");
write(L, result);
writeline(output, L);
assert NOT result;
----------------------------------------------------------------
-- bv_gt: Signed greater than comparison
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_gt:"));
writeline(output, L);
write(L, string'(" 2 > 2 = "));
result := bv_gt(X"02", X"02");
write(L, result);
writeline(output, L);
assert NOT result;
write(L, string'(" 3 > 2 = "));
result := bv_gt(X"03", X"02");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" 2 > -2 = "));
result := bv_gt(X"02", X"FE");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" -3 > 2 = "));
result := bv_gt(X"FD", X"02");
write(L, result);
writeline(output, L);
assert NOT result;
----------------------------------------------------------------
-- bv_ge: Signed greater than or equal comparison
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_ge:"));
writeline(output, L);
write(L, string'(" 2 >= 2 = "));
result := bv_ge(X"02", X"02");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" 3 >= 2 = "));
result := bv_ge(X"03", X"02");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" 2 >= -2 = "));
result := bv_ge(X"02", X"FE");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" -3 >= 2 = "));
result := bv_ge(X"FD", X"02");
write(L, result);
writeline(output, L);
assert NOT result;
----------------------------------------------------------------
----------------------------------------------------------------
-- Extension operators - convert a bit vector to a longer one
----------------------------------------------------------------
----------------------------------------------------------------
----------------------------------------------------------------
-- bv_sext: Sign extension
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_sext:"));
writeline(output, L);
write(L, string'(" sext(X""02"", 32) = "));
word := bv_sext(X"02", 32);
write(L, word);
writeline(output, L);
assert word = X"00000002";
write(L, string'(" sext(X""FE"", 32) = "));
word := bv_sext(X"FE", 32);
write(L, word);
writeline(output, L);
assert word = X"FFFFFFFE";
write(L, string'(" sext(X""02"", 8) = "));
byte := bv_sext(X"02", 8);
write(L, byte);
writeline(output, L);
assert byte = X"02";
write(L, string'(" sext(X""FE"", 8) = "));
byte := bv_sext(X"FE", 8);
write(L, byte);
writeline(output, L);
assert byte = X"FE";
write(L, string'(" sext(X""02"", 4) = "));
half_byte := bv_sext(X"02", 4);
write(L, half_byte);
writeline(output, L);
assert half_byte = X"2";
write(L, string'(" sext(X""FE"", 4) = "));
half_byte := bv_sext(X"FE", 4);
write(L, half_byte);
writeline(output, L);
assert half_byte = X"E";
----------------------------------------------------------------
-- bv_zext" Zero extension
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_zext:"));
writeline(output, L);
write(L, string'(" zext(X""02"", 32) = "));
word := bv_zext(X"02", 32);
write(L, word);
writeline(output, L);
assert word = X"00000002";
write(L, string'(" zext(X""FE"", 32) = "));
word := bv_zext(X"FE", 32);
write(L, word);
writeline(output, L);
assert word = X"000000FE";
write(L, string'(" zext(X""02"", 8) = "));
byte := bv_zext(X"02", 8);
write(L, byte);
writeline(output, L);
assert byte = X"02";
write(L, string'(" zext(X""FE"", 8) = "));
byte := bv_zext(X"FE", 8);
write(L, byte);
writeline(output, L);
assert byte = X"FE";
write(L, string'(" zext(X""02"", 4) = "));
half_byte := bv_zext(X"02", 4);
write(L, half_byte);
writeline(output, L);
assert half_byte = X"2";
write(L, string'(" zext(X""FE"", 4) = "));
half_byte := bv_zext(X"FE", 4);
write(L, half_byte);
writeline(output, L);
assert half_byte = X"E";
wait;
end process;
end architecture bench;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_10_bvat-b.vhd,v 1.3 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library bv_utilities;
use std.textio.all, bv_utilities.bv_arithmetic.all;
architecture bench of bv_test is
begin
process is
variable L : line;
variable byte : bit_vector(0 to 7);
variable word : bit_vector(1 to 32);
variable half_byte : bit_vector(1 to 4);
variable overflow, div_by_zero, result : boolean;
begin
wait for 1 ns;
----------------------------------------------------------------
----------------------------------------------------------------
-- test bit_vector to numeric conversions
----------------------------------------------------------------
----------------------------------------------------------------
write(L, string'("Testing bv_to_natural:"));
writeline(output, L);
write(L, string'(" bv_to_natural(X""02"") = "));
write(L, bv_to_natural(X"02"));
writeline(output, L);
assert bv_to_natural(X"02") = 2;
write(L, string'(" bv_to_natural(X""FE"") = "));
write(L, bv_to_natural(X"FE"));
writeline(output, L);
assert bv_to_natural(X"FE") = 254;
----------------------------------------------------------------
write(L, string'("Testing natural_to_bv:"));
writeline(output, L);
write(L, string'(" natural_to_bv(2) = "));
write(L, natural_to_bv(2, 8));
writeline(output, L);
assert natural_to_bv(2, 8) = X"02";
write(L, string'(" natural_to_bv(254) = "));
write(L, natural_to_bv(254, 8));
writeline(output, L);
assert natural_to_bv(254, 8) = X"FE";
----------------------------------------------------------------
write(L, string'("Testing bv_to_integer:"));
writeline(output, L);
write(L, string'(" bv_to_integer(X""02"") = "));
write(L, bv_to_integer(X"02"));
writeline(output, L);
assert bv_to_integer(X"02") = 2;
write(L, string'(" bv_to_integer(X""FE"") = "));
write(L, bv_to_integer(X"FE"));
writeline(output, L);
assert bv_to_integer(X"FE") = -2;
----------------------------------------------------------------
write(L, string'("Testing integer_to_bv:"));
writeline(output, L);
write(L, string'(" integer_to_bv(2) = "));
write(L, integer_to_bv(2, 8));
writeline(output, L);
assert integer_to_bv(2, 8) = X"02";
write(L, string'(" integer_to_bv(-2) = "));
write(L, integer_to_bv(-2, 8));
writeline(output, L);
assert integer_to_bv(-2, 8) = X"FE";
----------------------------------------------------------------
----------------------------------------------------------------
-- Arithmetic operations
----------------------------------------------------------------
----------------------------------------------------------------
----------------------------------------------------------------
-- bv_add: Signed addition with overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_add with overflow:"));
writeline(output, L);
write(L, string'(" 2+2 = "));
bv_add(X"02", X"02", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"04" and not overflow;
write(L, string'(" 2+(-3) = "));
bv_add(X"02", X"FD", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"FF" and not overflow;
write(L, string'(" 64+64 = "));
bv_add(X"40", X"40", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and overflow;
write(L, string'(" -64+(-64) = "));
bv_add(X"C0", X"C0", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and not overflow;
----------------------------------------------------------------
-- "+": Signed addition without overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing ""+"" without overflow:"));
writeline(output, L);
write(L, string'(" 2+2 = "));
byte := X"02" + X"02";
write(L, byte);
writeline(output, L);
assert byte = X"04";
write(L, string'(" 2+(-3) = "));
byte := X"02" + X"FD";
write(L, byte);
writeline(output, L);
assert byte = X"FF";
write(L, string'(" 64+64 = "));
byte := X"40" + X"40";
write(L, byte);
writeline(output, L);
assert byte = X"80";
write(L, string'(" -64+(-64) = "));
byte := X"C0" + X"C0";
write(L, byte);
writeline(output, L);
assert byte = X"80";
----------------------------------------------------------------
-- bv_sub: Signed subtraction with overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_sub with overflow:"));
writeline(output, L);
write(L, string'(" 2-2 = "));
bv_sub(X"02", X"02", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"00" and not overflow;
write(L, string'(" 2-(-3) = "));
bv_sub(X"02", X"FD", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"05" and not overflow;
write(L, string'(" 64-(-64) = "));
bv_sub(X"40", X"C0", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and overflow;
write(L, string'(" -64-64 = "));
bv_sub(X"C0", X"40", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and not overflow;
----------------------------------------------------------------
-- "-": Signed subtraction without overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing ""-"" without overflow:"));
writeline(output, L);
write(L, string'(" 2-2 = "));
byte := X"02" - X"02";
write(L, byte);
writeline(output, L);
assert byte = X"00";
write(L, string'(" 2-(-3) = "));
byte := X"02" - X"FD";
write(L, byte);
writeline(output, L);
assert byte = X"05";
write(L, string'(" 64-(-64) = "));
byte := X"40" - X"C0";
write(L, byte);
writeline(output, L);
assert byte = X"80";
write(L, string'(" -64-64 = "));
byte := X"C0" - X"40";
write(L, byte);
writeline(output, L);
assert byte = X"80";
----------------------------------------------------------------
-- bv_addu: Unsigned addition with overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_addu with overflow:"));
writeline(output, L);
write(L, string'(" 2+2 = "));
bv_addu(X"02", X"02", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"04" and not overflow;
write(L, string'(" 64+64 = "));
bv_addu(X"40", X"40", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and not overflow;
write(L, string'(" 128+128 = "));
bv_addu(X"80", X"80", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"00" and overflow;
----------------------------------------------------------------
-- bv_addu: Unsigned addition without overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_addu without overflow:"));
writeline(output, L);
write(L, string'(" 2+2 = "));
byte := bv_addu(X"02", X"02");
write(L, byte);
writeline(output, L);
assert byte = X"04";
write(L, string'(" 64+64 = "));
byte := bv_addu(X"40", X"40");
write(L, byte);
writeline(output, L);
assert byte = X"80";
write(L, string'(" 128+128 = "));
byte := bv_addu(X"80", X"80");
write(L, byte);
writeline(output, L);
assert byte = X"00";
----------------------------------------------------------------
-- bv_subu: Unsigned subtraction with overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_subu with overflow:"));
writeline(output, L);
write(L, string'(" 3-2 = "));
bv_subu(X"03", X"02", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"01" and not overflow;
write(L, string'(" 64-64 = "));
bv_subu(X"40", X"40", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"00" and not overflow;
write(L, string'(" 64-128 = "));
bv_subu(X"40", X"80", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"C0" and overflow;
----------------------------------------------------------------
-- bv_subu: Unsigned subtraction without overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_subu without overflow:"));
writeline(output, L);
write(L, string'(" 3-2 = "));
byte := bv_subu(X"03", X"02");
write(L, byte);
writeline(output, L);
assert byte = X"01";
write(L, string'(" 64-64 = "));
byte := bv_subu(X"40", X"40");
write(L, byte);
writeline(output, L);
assert byte = X"00";
write(L, string'(" 64-128 = "));
byte := bv_subu(X"40", X"80");
write(L, byte);
writeline(output, L);
assert byte = X"C0";
----------------------------------------------------------------
-- bv_neg: Signed negation with overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_neg with overflow:"));
writeline(output, L);
write(L, string'(" -(3) = "));
bv_neg(X"03", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"FD" and not overflow;
write(L, string'(" -(-3) = "));
bv_neg(X"FD", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"03" and not overflow;
write(L, string'(" -(127) = "));
bv_neg(X"7F", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"81" and not overflow;
write(L, string'(" -(-128) = "));
bv_neg(X"80", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and overflow;
----------------------------------------------------------------
-- "-": Signed negation without overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing ""-"" without overflow:"));
writeline(output, L);
write(L, string'(" -(3) = "));
byte := - X"03";
write(L, byte);
writeline(output, L);
assert byte = X"FD";
write(L, string'(" -(-3) = "));
byte := - X"FD";
write(L, byte);
writeline(output, L);
assert byte = X"03";
write(L, string'(" -(127) = "));
byte := - X"7F";
write(L, byte);
writeline(output, L);
assert byte = X"81";
write(L, string'(" -(-128) = "));
byte := - X"80";
write(L, byte);
writeline(output, L);
assert byte = X"80";
----------------------------------------------------------------
-- bv_mult: Signed multiplication with overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_mult with overflow:"));
writeline(output, L);
write(L, string'(" 5*(-3) = "));
bv_mult(X"05", X"FD", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"F1" and not overflow;
write(L, string'(" (-5)*(-3) = "));
bv_mult(X"FB", X"FD", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"0F" and not overflow;
write(L, string'(" 16*8 = "));
bv_mult(X"10", X"08", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and overflow;
write(L, string'(" 16*16 = "));
bv_mult(X"10", X"10", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"00" and overflow;
write(L, string'(" 16*(-8) = "));
bv_mult(X"10", X"F8", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and not overflow;
write(L, string'(" 16*(-16) = "));
bv_mult(X"10", X"F0", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"00" and overflow;
----------------------------------------------------------------
-- "*": Signed multiplication without overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing ""*"" without overflow:"));
writeline(output, L);
write(L, string'(" 5*(-3) = "));
byte := X"05" * X"FD";
write(L, byte);
writeline(output, L);
assert byte = X"F1";
write(L, string'(" (-5)*(-3) = "));
byte := X"FB" * X"FD";
write(L, byte);
writeline(output, L);
assert byte = X"0F";
write(L, string'(" 16*8 = "));
byte := X"10" * X"08";
write(L, byte);
writeline(output, L);
assert byte = X"80";
write(L, string'(" 16*16 = "));
byte := X"10" * X"10";
write(L, byte);
writeline(output, L);
assert byte = X"00";
write(L, string'(" 16*(-8) = "));
byte := X"10" * X"F8";
write(L, byte);
writeline(output, L);
assert byte = X"80";
write(L, string'(" 16*(-16) = "));
byte := X"10" * X"F0";
write(L, byte);
writeline(output, L);
assert byte = X"00";
----------------------------------------------------------------
-- bv_multu: Unsigned multiplication with overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_multu with overflow:"));
writeline(output, L);
write(L, string'(" 5*7 = "));
bv_multu(X"05", X"07", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"23" and not overflow;
write(L, string'(" 16*8 = "));
bv_multu(X"10", X"08", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and not overflow;
write(L, string'(" 16*16 = "));
bv_multu(X"10", X"10", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"00" and overflow;
----------------------------------------------------------------
-- bv_multu: Unsigned multiplication without overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_multu without overflow:"));
writeline(output, L);
write(L, string'(" 5*7 = "));
byte := bv_multu(X"05", X"07");
write(L, byte);
writeline(output, L);
assert byte = X"23";
write(L, string'(" 16*8 = "));
byte := bv_multu(X"10", X"08");
write(L, byte);
writeline(output, L);
assert byte = X"80";
write(L, string'(" 16*16 = "));
byte := bv_multu(X"10", X"10");
write(L, byte);
writeline(output, L);
assert byte = X"00";
----------------------------------------------------------------
-- bv_div: Signed division with divide by zero and overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_div with flags:"));
writeline(output, L);
write(L, string'(" 7/2 = "));
bv_div(X"07", X"02", byte, div_by_zero, overflow);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"03" and not div_by_zero and not overflow;
write(L, string'(" -7/2 = "));
bv_div(X"F9", X"02", byte, div_by_zero, overflow);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"FD" and not div_by_zero and not overflow;
write(L, string'(" 7/-2 = "));
bv_div(X"07", X"FE", byte, div_by_zero, overflow);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"FD" and not div_by_zero and not overflow;
write(L, string'(" -7/-2 = "));
bv_div(X"F9", X"FE", byte, div_by_zero, overflow);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"03" and not div_by_zero and not overflow;
write(L, string'(" -128/1 = "));
bv_div(X"80", X"01", byte, div_by_zero, overflow);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and not div_by_zero and not overflow;
write(L, string'(" -128/-1 = "));
bv_div(X"80", X"FF", byte, div_by_zero, overflow);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and not div_by_zero and overflow;
write(L, string'(" -16/0 = "));
bv_div(X"F0", X"00", byte, div_by_zero, overflow);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"00" and div_by_zero and not overflow;
----------------------------------------------------------------
-- "/": Signed division without divide by zero and overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing ""/"" without flags:"));
writeline(output, L);
write(L, string'(" 7/2 = "));
byte := X"07" / X"02";
write(L, byte);
writeline(output, L);
assert byte = X"03";
write(L, string'(" -7/2 = "));
byte := X"F9" / X"02";
write(L, byte);
writeline(output, L);
assert byte = X"FD";
write(L, string'(" 7/-2 = "));
byte := X"07" / X"FE";
write(L, byte);
writeline(output, L);
assert byte = X"FD";
write(L, string'(" -7/-2 = "));
byte := X"F9" / X"FE";
write(L, byte);
writeline(output, L);
assert byte = X"03";
write(L, string'(" -128/1 = "));
byte := X"80" / X"01";
write(L, byte);
writeline(output, L);
assert byte = X"80";
write(L, string'(" -128/-1 = "));
byte := X"80" / X"FF";
write(L, byte);
writeline(output, L);
assert byte = X"80";
write(L, string'(" -16/0 = "));
byte := X"F0" / X"00";
write(L, byte);
writeline(output, L);
assert byte = X"00";
----------------------------------------------------------------
-- bv_divu: Unsigned division with divide by zero detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_divu with flag:"));
writeline(output, L);
write(L, string'(" 7/2 = "));
bv_divu(X"07", X"02", byte, div_by_zero);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
writeline(output, L);
assert byte = X"03" and not div_by_zero;
write(L, string'(" 14/7 = "));
bv_divu(X"0E", X"07", byte, div_by_zero);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
writeline(output, L);
assert byte = X"02" and not div_by_zero;
write(L, string'(" 16/1 = "));
bv_divu(X"10", X"01", byte, div_by_zero);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
writeline(output, L);
assert byte = X"10" and not div_by_zero;
write(L, string'(" 16/0 = "));
bv_divu(X"10", X"00", byte, div_by_zero);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
writeline(output, L);
assert byte = X"10" and div_by_zero;
write(L, string'(" 16/16 = "));
bv_divu(X"10", X"10", byte, div_by_zero);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
writeline(output, L);
assert byte = X"01" and not div_by_zero;
write(L, string'(" 1/16 = "));
bv_divu(X"01", X"10", byte, div_by_zero);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
writeline(output, L);
assert byte = X"00" and not div_by_zero;
write(L, string'(" 255/1 = "));
bv_divu(X"FF", X"01", byte, div_by_zero);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
writeline(output, L);
assert byte = X"FF" and not div_by_zero;
----------------------------------------------------------------
-- bv_divu: Unsigned division without divide by zero detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_divu without flag:"));
writeline(output, L);
write(L, string'(" 7/2 = "));
byte := bv_divu(X"07", X"02");
write(L, byte);
writeline(output, L);
assert byte = X"03";
write(L, string'(" 14/7 = "));
byte := bv_divu(X"0E", X"07");
write(L, byte);
writeline(output, L);
assert byte = X"02";
write(L, string'(" 16/1 = "));
byte := bv_divu(X"10", X"01");
write(L, byte);
writeline(output, L);
assert byte = X"10";
write(L, string'(" 16/0 = "));
byte := bv_divu(X"10", X"00");
write(L, byte);
writeline(output, L);
assert byte = X"00";
write(L, string'(" 16/16 = "));
byte := bv_divu(X"10", X"10");
write(L, byte);
writeline(output, L);
assert byte = X"01";
write(L, string'(" 1/16 = "));
byte := bv_divu(X"01", X"10");
write(L, byte);
writeline(output, L);
assert byte = X"00";
write(L, string'(" 255/1 = "));
byte := bv_divu(X"FF", X"01");
write(L, byte);
writeline(output, L);
assert byte = X"FF";
----------------------------------------------------------------
----------------------------------------------------------------
-- Arithmetic comparison operators.
----------------------------------------------------------------
----------------------------------------------------------------
----------------------------------------------------------------
-- bv_lt: Signed less than comparison
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_lt:"));
writeline(output, L);
write(L, string'(" 2 < 2 = "));
result := bv_lt(X"02", X"02");
write(L, result);
writeline(output, L);
assert NOT result;
write(L, string'(" 2 < 3 = "));
result := bv_lt(X"02", X"03");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" -2 < 2 = "));
result := bv_lt(X"FE", X"02");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" 2 < -3 = "));
result := bv_lt(X"02", X"FD");
write(L, result);
writeline(output, L);
assert NOT result;
----------------------------------------------------------------
-- bv_le: Signed less than or equal comparison
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_le:"));
writeline(output, L);
write(L, string'(" 2 <= 2 = "));
result := bv_le(X"02", X"02");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" 2 <= 3 = "));
result := bv_le(X"02", X"03");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" -2 <= 2 = "));
result := bv_le(X"FE", X"02");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" 2 <= -3 = "));
result := bv_le(X"02", X"FD");
write(L, result);
writeline(output, L);
assert NOT result;
----------------------------------------------------------------
-- bv_gt: Signed greater than comparison
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_gt:"));
writeline(output, L);
write(L, string'(" 2 > 2 = "));
result := bv_gt(X"02", X"02");
write(L, result);
writeline(output, L);
assert NOT result;
write(L, string'(" 3 > 2 = "));
result := bv_gt(X"03", X"02");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" 2 > -2 = "));
result := bv_gt(X"02", X"FE");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" -3 > 2 = "));
result := bv_gt(X"FD", X"02");
write(L, result);
writeline(output, L);
assert NOT result;
----------------------------------------------------------------
-- bv_ge: Signed greater than or equal comparison
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_ge:"));
writeline(output, L);
write(L, string'(" 2 >= 2 = "));
result := bv_ge(X"02", X"02");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" 3 >= 2 = "));
result := bv_ge(X"03", X"02");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" 2 >= -2 = "));
result := bv_ge(X"02", X"FE");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" -3 >= 2 = "));
result := bv_ge(X"FD", X"02");
write(L, result);
writeline(output, L);
assert NOT result;
----------------------------------------------------------------
----------------------------------------------------------------
-- Extension operators - convert a bit vector to a longer one
----------------------------------------------------------------
----------------------------------------------------------------
----------------------------------------------------------------
-- bv_sext: Sign extension
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_sext:"));
writeline(output, L);
write(L, string'(" sext(X""02"", 32) = "));
word := bv_sext(X"02", 32);
write(L, word);
writeline(output, L);
assert word = X"00000002";
write(L, string'(" sext(X""FE"", 32) = "));
word := bv_sext(X"FE", 32);
write(L, word);
writeline(output, L);
assert word = X"FFFFFFFE";
write(L, string'(" sext(X""02"", 8) = "));
byte := bv_sext(X"02", 8);
write(L, byte);
writeline(output, L);
assert byte = X"02";
write(L, string'(" sext(X""FE"", 8) = "));
byte := bv_sext(X"FE", 8);
write(L, byte);
writeline(output, L);
assert byte = X"FE";
write(L, string'(" sext(X""02"", 4) = "));
half_byte := bv_sext(X"02", 4);
write(L, half_byte);
writeline(output, L);
assert half_byte = X"2";
write(L, string'(" sext(X""FE"", 4) = "));
half_byte := bv_sext(X"FE", 4);
write(L, half_byte);
writeline(output, L);
assert half_byte = X"E";
----------------------------------------------------------------
-- bv_zext" Zero extension
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_zext:"));
writeline(output, L);
write(L, string'(" zext(X""02"", 32) = "));
word := bv_zext(X"02", 32);
write(L, word);
writeline(output, L);
assert word = X"00000002";
write(L, string'(" zext(X""FE"", 32) = "));
word := bv_zext(X"FE", 32);
write(L, word);
writeline(output, L);
assert word = X"000000FE";
write(L, string'(" zext(X""02"", 8) = "));
byte := bv_zext(X"02", 8);
write(L, byte);
writeline(output, L);
assert byte = X"02";
write(L, string'(" zext(X""FE"", 8) = "));
byte := bv_zext(X"FE", 8);
write(L, byte);
writeline(output, L);
assert byte = X"FE";
write(L, string'(" zext(X""02"", 4) = "));
half_byte := bv_zext(X"02", 4);
write(L, half_byte);
writeline(output, L);
assert half_byte = X"2";
write(L, string'(" zext(X""FE"", 4) = "));
half_byte := bv_zext(X"FE", 4);
write(L, half_byte);
writeline(output, L);
assert half_byte = X"E";
wait;
end process;
end architecture bench;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_10_bvat-b.vhd,v 1.3 2001-10-26 16:29:35 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library bv_utilities;
use std.textio.all, bv_utilities.bv_arithmetic.all;
architecture bench of bv_test is
begin
process is
variable L : line;
variable byte : bit_vector(0 to 7);
variable word : bit_vector(1 to 32);
variable half_byte : bit_vector(1 to 4);
variable overflow, div_by_zero, result : boolean;
begin
wait for 1 ns;
----------------------------------------------------------------
----------------------------------------------------------------
-- test bit_vector to numeric conversions
----------------------------------------------------------------
----------------------------------------------------------------
write(L, string'("Testing bv_to_natural:"));
writeline(output, L);
write(L, string'(" bv_to_natural(X""02"") = "));
write(L, bv_to_natural(X"02"));
writeline(output, L);
assert bv_to_natural(X"02") = 2;
write(L, string'(" bv_to_natural(X""FE"") = "));
write(L, bv_to_natural(X"FE"));
writeline(output, L);
assert bv_to_natural(X"FE") = 254;
----------------------------------------------------------------
write(L, string'("Testing natural_to_bv:"));
writeline(output, L);
write(L, string'(" natural_to_bv(2) = "));
write(L, natural_to_bv(2, 8));
writeline(output, L);
assert natural_to_bv(2, 8) = X"02";
write(L, string'(" natural_to_bv(254) = "));
write(L, natural_to_bv(254, 8));
writeline(output, L);
assert natural_to_bv(254, 8) = X"FE";
----------------------------------------------------------------
write(L, string'("Testing bv_to_integer:"));
writeline(output, L);
write(L, string'(" bv_to_integer(X""02"") = "));
write(L, bv_to_integer(X"02"));
writeline(output, L);
assert bv_to_integer(X"02") = 2;
write(L, string'(" bv_to_integer(X""FE"") = "));
write(L, bv_to_integer(X"FE"));
writeline(output, L);
assert bv_to_integer(X"FE") = -2;
----------------------------------------------------------------
write(L, string'("Testing integer_to_bv:"));
writeline(output, L);
write(L, string'(" integer_to_bv(2) = "));
write(L, integer_to_bv(2, 8));
writeline(output, L);
assert integer_to_bv(2, 8) = X"02";
write(L, string'(" integer_to_bv(-2) = "));
write(L, integer_to_bv(-2, 8));
writeline(output, L);
assert integer_to_bv(-2, 8) = X"FE";
----------------------------------------------------------------
----------------------------------------------------------------
-- Arithmetic operations
----------------------------------------------------------------
----------------------------------------------------------------
----------------------------------------------------------------
-- bv_add: Signed addition with overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_add with overflow:"));
writeline(output, L);
write(L, string'(" 2+2 = "));
bv_add(X"02", X"02", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"04" and not overflow;
write(L, string'(" 2+(-3) = "));
bv_add(X"02", X"FD", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"FF" and not overflow;
write(L, string'(" 64+64 = "));
bv_add(X"40", X"40", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and overflow;
write(L, string'(" -64+(-64) = "));
bv_add(X"C0", X"C0", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and not overflow;
----------------------------------------------------------------
-- "+": Signed addition without overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing ""+"" without overflow:"));
writeline(output, L);
write(L, string'(" 2+2 = "));
byte := X"02" + X"02";
write(L, byte);
writeline(output, L);
assert byte = X"04";
write(L, string'(" 2+(-3) = "));
byte := X"02" + X"FD";
write(L, byte);
writeline(output, L);
assert byte = X"FF";
write(L, string'(" 64+64 = "));
byte := X"40" + X"40";
write(L, byte);
writeline(output, L);
assert byte = X"80";
write(L, string'(" -64+(-64) = "));
byte := X"C0" + X"C0";
write(L, byte);
writeline(output, L);
assert byte = X"80";
----------------------------------------------------------------
-- bv_sub: Signed subtraction with overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_sub with overflow:"));
writeline(output, L);
write(L, string'(" 2-2 = "));
bv_sub(X"02", X"02", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"00" and not overflow;
write(L, string'(" 2-(-3) = "));
bv_sub(X"02", X"FD", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"05" and not overflow;
write(L, string'(" 64-(-64) = "));
bv_sub(X"40", X"C0", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and overflow;
write(L, string'(" -64-64 = "));
bv_sub(X"C0", X"40", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and not overflow;
----------------------------------------------------------------
-- "-": Signed subtraction without overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing ""-"" without overflow:"));
writeline(output, L);
write(L, string'(" 2-2 = "));
byte := X"02" - X"02";
write(L, byte);
writeline(output, L);
assert byte = X"00";
write(L, string'(" 2-(-3) = "));
byte := X"02" - X"FD";
write(L, byte);
writeline(output, L);
assert byte = X"05";
write(L, string'(" 64-(-64) = "));
byte := X"40" - X"C0";
write(L, byte);
writeline(output, L);
assert byte = X"80";
write(L, string'(" -64-64 = "));
byte := X"C0" - X"40";
write(L, byte);
writeline(output, L);
assert byte = X"80";
----------------------------------------------------------------
-- bv_addu: Unsigned addition with overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_addu with overflow:"));
writeline(output, L);
write(L, string'(" 2+2 = "));
bv_addu(X"02", X"02", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"04" and not overflow;
write(L, string'(" 64+64 = "));
bv_addu(X"40", X"40", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and not overflow;
write(L, string'(" 128+128 = "));
bv_addu(X"80", X"80", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"00" and overflow;
----------------------------------------------------------------
-- bv_addu: Unsigned addition without overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_addu without overflow:"));
writeline(output, L);
write(L, string'(" 2+2 = "));
byte := bv_addu(X"02", X"02");
write(L, byte);
writeline(output, L);
assert byte = X"04";
write(L, string'(" 64+64 = "));
byte := bv_addu(X"40", X"40");
write(L, byte);
writeline(output, L);
assert byte = X"80";
write(L, string'(" 128+128 = "));
byte := bv_addu(X"80", X"80");
write(L, byte);
writeline(output, L);
assert byte = X"00";
----------------------------------------------------------------
-- bv_subu: Unsigned subtraction with overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_subu with overflow:"));
writeline(output, L);
write(L, string'(" 3-2 = "));
bv_subu(X"03", X"02", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"01" and not overflow;
write(L, string'(" 64-64 = "));
bv_subu(X"40", X"40", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"00" and not overflow;
write(L, string'(" 64-128 = "));
bv_subu(X"40", X"80", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"C0" and overflow;
----------------------------------------------------------------
-- bv_subu: Unsigned subtraction without overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_subu without overflow:"));
writeline(output, L);
write(L, string'(" 3-2 = "));
byte := bv_subu(X"03", X"02");
write(L, byte);
writeline(output, L);
assert byte = X"01";
write(L, string'(" 64-64 = "));
byte := bv_subu(X"40", X"40");
write(L, byte);
writeline(output, L);
assert byte = X"00";
write(L, string'(" 64-128 = "));
byte := bv_subu(X"40", X"80");
write(L, byte);
writeline(output, L);
assert byte = X"C0";
----------------------------------------------------------------
-- bv_neg: Signed negation with overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_neg with overflow:"));
writeline(output, L);
write(L, string'(" -(3) = "));
bv_neg(X"03", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"FD" and not overflow;
write(L, string'(" -(-3) = "));
bv_neg(X"FD", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"03" and not overflow;
write(L, string'(" -(127) = "));
bv_neg(X"7F", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"81" and not overflow;
write(L, string'(" -(-128) = "));
bv_neg(X"80", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and overflow;
----------------------------------------------------------------
-- "-": Signed negation without overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing ""-"" without overflow:"));
writeline(output, L);
write(L, string'(" -(3) = "));
byte := - X"03";
write(L, byte);
writeline(output, L);
assert byte = X"FD";
write(L, string'(" -(-3) = "));
byte := - X"FD";
write(L, byte);
writeline(output, L);
assert byte = X"03";
write(L, string'(" -(127) = "));
byte := - X"7F";
write(L, byte);
writeline(output, L);
assert byte = X"81";
write(L, string'(" -(-128) = "));
byte := - X"80";
write(L, byte);
writeline(output, L);
assert byte = X"80";
----------------------------------------------------------------
-- bv_mult: Signed multiplication with overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_mult with overflow:"));
writeline(output, L);
write(L, string'(" 5*(-3) = "));
bv_mult(X"05", X"FD", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"F1" and not overflow;
write(L, string'(" (-5)*(-3) = "));
bv_mult(X"FB", X"FD", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"0F" and not overflow;
write(L, string'(" 16*8 = "));
bv_mult(X"10", X"08", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and overflow;
write(L, string'(" 16*16 = "));
bv_mult(X"10", X"10", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"00" and overflow;
write(L, string'(" 16*(-8) = "));
bv_mult(X"10", X"F8", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and not overflow;
write(L, string'(" 16*(-16) = "));
bv_mult(X"10", X"F0", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"00" and overflow;
----------------------------------------------------------------
-- "*": Signed multiplication without overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing ""*"" without overflow:"));
writeline(output, L);
write(L, string'(" 5*(-3) = "));
byte := X"05" * X"FD";
write(L, byte);
writeline(output, L);
assert byte = X"F1";
write(L, string'(" (-5)*(-3) = "));
byte := X"FB" * X"FD";
write(L, byte);
writeline(output, L);
assert byte = X"0F";
write(L, string'(" 16*8 = "));
byte := X"10" * X"08";
write(L, byte);
writeline(output, L);
assert byte = X"80";
write(L, string'(" 16*16 = "));
byte := X"10" * X"10";
write(L, byte);
writeline(output, L);
assert byte = X"00";
write(L, string'(" 16*(-8) = "));
byte := X"10" * X"F8";
write(L, byte);
writeline(output, L);
assert byte = X"80";
write(L, string'(" 16*(-16) = "));
byte := X"10" * X"F0";
write(L, byte);
writeline(output, L);
assert byte = X"00";
----------------------------------------------------------------
-- bv_multu: Unsigned multiplication with overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_multu with overflow:"));
writeline(output, L);
write(L, string'(" 5*7 = "));
bv_multu(X"05", X"07", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"23" and not overflow;
write(L, string'(" 16*8 = "));
bv_multu(X"10", X"08", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and not overflow;
write(L, string'(" 16*16 = "));
bv_multu(X"10", X"10", byte, overflow);
write(L, byte);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"00" and overflow;
----------------------------------------------------------------
-- bv_multu: Unsigned multiplication without overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_multu without overflow:"));
writeline(output, L);
write(L, string'(" 5*7 = "));
byte := bv_multu(X"05", X"07");
write(L, byte);
writeline(output, L);
assert byte = X"23";
write(L, string'(" 16*8 = "));
byte := bv_multu(X"10", X"08");
write(L, byte);
writeline(output, L);
assert byte = X"80";
write(L, string'(" 16*16 = "));
byte := bv_multu(X"10", X"10");
write(L, byte);
writeline(output, L);
assert byte = X"00";
----------------------------------------------------------------
-- bv_div: Signed division with divide by zero and overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_div with flags:"));
writeline(output, L);
write(L, string'(" 7/2 = "));
bv_div(X"07", X"02", byte, div_by_zero, overflow);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"03" and not div_by_zero and not overflow;
write(L, string'(" -7/2 = "));
bv_div(X"F9", X"02", byte, div_by_zero, overflow);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"FD" and not div_by_zero and not overflow;
write(L, string'(" 7/-2 = "));
bv_div(X"07", X"FE", byte, div_by_zero, overflow);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"FD" and not div_by_zero and not overflow;
write(L, string'(" -7/-2 = "));
bv_div(X"F9", X"FE", byte, div_by_zero, overflow);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"03" and not div_by_zero and not overflow;
write(L, string'(" -128/1 = "));
bv_div(X"80", X"01", byte, div_by_zero, overflow);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and not div_by_zero and not overflow;
write(L, string'(" -128/-1 = "));
bv_div(X"80", X"FF", byte, div_by_zero, overflow);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"80" and not div_by_zero and overflow;
write(L, string'(" -16/0 = "));
bv_div(X"F0", X"00", byte, div_by_zero, overflow);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
write(L, string'(", overflow = ")); write(L, overflow);
writeline(output, L);
assert byte = X"00" and div_by_zero and not overflow;
----------------------------------------------------------------
-- "/": Signed division without divide by zero and overflow detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing ""/"" without flags:"));
writeline(output, L);
write(L, string'(" 7/2 = "));
byte := X"07" / X"02";
write(L, byte);
writeline(output, L);
assert byte = X"03";
write(L, string'(" -7/2 = "));
byte := X"F9" / X"02";
write(L, byte);
writeline(output, L);
assert byte = X"FD";
write(L, string'(" 7/-2 = "));
byte := X"07" / X"FE";
write(L, byte);
writeline(output, L);
assert byte = X"FD";
write(L, string'(" -7/-2 = "));
byte := X"F9" / X"FE";
write(L, byte);
writeline(output, L);
assert byte = X"03";
write(L, string'(" -128/1 = "));
byte := X"80" / X"01";
write(L, byte);
writeline(output, L);
assert byte = X"80";
write(L, string'(" -128/-1 = "));
byte := X"80" / X"FF";
write(L, byte);
writeline(output, L);
assert byte = X"80";
write(L, string'(" -16/0 = "));
byte := X"F0" / X"00";
write(L, byte);
writeline(output, L);
assert byte = X"00";
----------------------------------------------------------------
-- bv_divu: Unsigned division with divide by zero detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_divu with flag:"));
writeline(output, L);
write(L, string'(" 7/2 = "));
bv_divu(X"07", X"02", byte, div_by_zero);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
writeline(output, L);
assert byte = X"03" and not div_by_zero;
write(L, string'(" 14/7 = "));
bv_divu(X"0E", X"07", byte, div_by_zero);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
writeline(output, L);
assert byte = X"02" and not div_by_zero;
write(L, string'(" 16/1 = "));
bv_divu(X"10", X"01", byte, div_by_zero);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
writeline(output, L);
assert byte = X"10" and not div_by_zero;
write(L, string'(" 16/0 = "));
bv_divu(X"10", X"00", byte, div_by_zero);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
writeline(output, L);
assert byte = X"10" and div_by_zero;
write(L, string'(" 16/16 = "));
bv_divu(X"10", X"10", byte, div_by_zero);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
writeline(output, L);
assert byte = X"01" and not div_by_zero;
write(L, string'(" 1/16 = "));
bv_divu(X"01", X"10", byte, div_by_zero);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
writeline(output, L);
assert byte = X"00" and not div_by_zero;
write(L, string'(" 255/1 = "));
bv_divu(X"FF", X"01", byte, div_by_zero);
write(L, byte);
write(L, string'(", div_by_zero = ")); write(L, div_by_zero);
writeline(output, L);
assert byte = X"FF" and not div_by_zero;
----------------------------------------------------------------
-- bv_divu: Unsigned division without divide by zero detection
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_divu without flag:"));
writeline(output, L);
write(L, string'(" 7/2 = "));
byte := bv_divu(X"07", X"02");
write(L, byte);
writeline(output, L);
assert byte = X"03";
write(L, string'(" 14/7 = "));
byte := bv_divu(X"0E", X"07");
write(L, byte);
writeline(output, L);
assert byte = X"02";
write(L, string'(" 16/1 = "));
byte := bv_divu(X"10", X"01");
write(L, byte);
writeline(output, L);
assert byte = X"10";
write(L, string'(" 16/0 = "));
byte := bv_divu(X"10", X"00");
write(L, byte);
writeline(output, L);
assert byte = X"00";
write(L, string'(" 16/16 = "));
byte := bv_divu(X"10", X"10");
write(L, byte);
writeline(output, L);
assert byte = X"01";
write(L, string'(" 1/16 = "));
byte := bv_divu(X"01", X"10");
write(L, byte);
writeline(output, L);
assert byte = X"00";
write(L, string'(" 255/1 = "));
byte := bv_divu(X"FF", X"01");
write(L, byte);
writeline(output, L);
assert byte = X"FF";
----------------------------------------------------------------
----------------------------------------------------------------
-- Arithmetic comparison operators.
----------------------------------------------------------------
----------------------------------------------------------------
----------------------------------------------------------------
-- bv_lt: Signed less than comparison
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_lt:"));
writeline(output, L);
write(L, string'(" 2 < 2 = "));
result := bv_lt(X"02", X"02");
write(L, result);
writeline(output, L);
assert NOT result;
write(L, string'(" 2 < 3 = "));
result := bv_lt(X"02", X"03");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" -2 < 2 = "));
result := bv_lt(X"FE", X"02");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" 2 < -3 = "));
result := bv_lt(X"02", X"FD");
write(L, result);
writeline(output, L);
assert NOT result;
----------------------------------------------------------------
-- bv_le: Signed less than or equal comparison
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_le:"));
writeline(output, L);
write(L, string'(" 2 <= 2 = "));
result := bv_le(X"02", X"02");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" 2 <= 3 = "));
result := bv_le(X"02", X"03");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" -2 <= 2 = "));
result := bv_le(X"FE", X"02");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" 2 <= -3 = "));
result := bv_le(X"02", X"FD");
write(L, result);
writeline(output, L);
assert NOT result;
----------------------------------------------------------------
-- bv_gt: Signed greater than comparison
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_gt:"));
writeline(output, L);
write(L, string'(" 2 > 2 = "));
result := bv_gt(X"02", X"02");
write(L, result);
writeline(output, L);
assert NOT result;
write(L, string'(" 3 > 2 = "));
result := bv_gt(X"03", X"02");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" 2 > -2 = "));
result := bv_gt(X"02", X"FE");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" -3 > 2 = "));
result := bv_gt(X"FD", X"02");
write(L, result);
writeline(output, L);
assert NOT result;
----------------------------------------------------------------
-- bv_ge: Signed greater than or equal comparison
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_ge:"));
writeline(output, L);
write(L, string'(" 2 >= 2 = "));
result := bv_ge(X"02", X"02");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" 3 >= 2 = "));
result := bv_ge(X"03", X"02");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" 2 >= -2 = "));
result := bv_ge(X"02", X"FE");
write(L, result);
writeline(output, L);
assert result;
write(L, string'(" -3 >= 2 = "));
result := bv_ge(X"FD", X"02");
write(L, result);
writeline(output, L);
assert NOT result;
----------------------------------------------------------------
----------------------------------------------------------------
-- Extension operators - convert a bit vector to a longer one
----------------------------------------------------------------
----------------------------------------------------------------
----------------------------------------------------------------
-- bv_sext: Sign extension
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_sext:"));
writeline(output, L);
write(L, string'(" sext(X""02"", 32) = "));
word := bv_sext(X"02", 32);
write(L, word);
writeline(output, L);
assert word = X"00000002";
write(L, string'(" sext(X""FE"", 32) = "));
word := bv_sext(X"FE", 32);
write(L, word);
writeline(output, L);
assert word = X"FFFFFFFE";
write(L, string'(" sext(X""02"", 8) = "));
byte := bv_sext(X"02", 8);
write(L, byte);
writeline(output, L);
assert byte = X"02";
write(L, string'(" sext(X""FE"", 8) = "));
byte := bv_sext(X"FE", 8);
write(L, byte);
writeline(output, L);
assert byte = X"FE";
write(L, string'(" sext(X""02"", 4) = "));
half_byte := bv_sext(X"02", 4);
write(L, half_byte);
writeline(output, L);
assert half_byte = X"2";
write(L, string'(" sext(X""FE"", 4) = "));
half_byte := bv_sext(X"FE", 4);
write(L, half_byte);
writeline(output, L);
assert half_byte = X"E";
----------------------------------------------------------------
-- bv_zext" Zero extension
----------------------------------------------------------------
writeline(output, L);
write(L, string'("Testing bv_zext:"));
writeline(output, L);
write(L, string'(" zext(X""02"", 32) = "));
word := bv_zext(X"02", 32);
write(L, word);
writeline(output, L);
assert word = X"00000002";
write(L, string'(" zext(X""FE"", 32) = "));
word := bv_zext(X"FE", 32);
write(L, word);
writeline(output, L);
assert word = X"000000FE";
write(L, string'(" zext(X""02"", 8) = "));
byte := bv_zext(X"02", 8);
write(L, byte);
writeline(output, L);
assert byte = X"02";
write(L, string'(" zext(X""FE"", 8) = "));
byte := bv_zext(X"FE", 8);
write(L, byte);
writeline(output, L);
assert byte = X"FE";
write(L, string'(" zext(X""02"", 4) = "));
half_byte := bv_zext(X"02", 4);
write(L, half_byte);
writeline(output, L);
assert half_byte = X"2";
write(L, string'(" zext(X""FE"", 4) = "));
half_byte := bv_zext(X"FE", 4);
write(L, half_byte);
writeline(output, L);
assert half_byte = X"E";
wait;
end process;
end architecture bench;
|
package predef is
end package;
package body predef is
function add1(x : integer) return integer is
begin
return x + 1;
end function;
-- Calls to predefined functions should always be folded
constant c1 : integer := 1 + 2;
constant c2 : boolean := true xor false;
-- This should not be folded in analysis phase
constant c3 : integer := add1(2);
end package body;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_DIV_LUT0.VHD ***
--*** ***
--*** Function: Look Up Table - Inverse ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_div_lut0 IS
PORT (
add : IN STD_LOGIC_VECTOR (9 DOWNTO 1);
data : OUT STD_LOGIC_VECTOR (20 DOWNTO 1)
);
END fp_div_lut0;
ARCHITECTURE rtl OF fp_div_lut0 IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "000000000" => data <= conv_std_logic_vector(1048575,20);
WHEN "000000001" => data <= conv_std_logic_vector(1046531,20);
WHEN "000000010" => data <= conv_std_logic_vector(1044495,20);
WHEN "000000011" => data <= conv_std_logic_vector(1042467,20);
WHEN "000000100" => data <= conv_std_logic_vector(1040447,20);
WHEN "000000101" => data <= conv_std_logic_vector(1038434,20);
WHEN "000000110" => data <= conv_std_logic_vector(1036429,20);
WHEN "000000111" => data <= conv_std_logic_vector(1034432,20);
WHEN "000001000" => data <= conv_std_logic_vector(1032443,20);
WHEN "000001001" => data <= conv_std_logic_vector(1030461,20);
WHEN "000001010" => data <= conv_std_logic_vector(1028487,20);
WHEN "000001011" => data <= conv_std_logic_vector(1026521,20);
WHEN "000001100" => data <= conv_std_logic_vector(1024562,20);
WHEN "000001101" => data <= conv_std_logic_vector(1022610,20);
WHEN "000001110" => data <= conv_std_logic_vector(1020666,20);
WHEN "000001111" => data <= conv_std_logic_vector(1018729,20);
WHEN "000010000" => data <= conv_std_logic_vector(1016800,20);
WHEN "000010001" => data <= conv_std_logic_vector(1014878,20);
WHEN "000010010" => data <= conv_std_logic_vector(1012963,20);
WHEN "000010011" => data <= conv_std_logic_vector(1011055,20);
WHEN "000010100" => data <= conv_std_logic_vector(1009155,20);
WHEN "000010101" => data <= conv_std_logic_vector(1007262,20);
WHEN "000010110" => data <= conv_std_logic_vector(1005375,20);
WHEN "000010111" => data <= conv_std_logic_vector(1003496,20);
WHEN "000011000" => data <= conv_std_logic_vector(1001624,20);
WHEN "000011001" => data <= conv_std_logic_vector(999759,20);
WHEN "000011010" => data <= conv_std_logic_vector(997900,20);
WHEN "000011011" => data <= conv_std_logic_vector(996049,20);
WHEN "000011100" => data <= conv_std_logic_vector(994205,20);
WHEN "000011101" => data <= conv_std_logic_vector(992367,20);
WHEN "000011110" => data <= conv_std_logic_vector(990536,20);
WHEN "000011111" => data <= conv_std_logic_vector(988712,20);
WHEN "000100000" => data <= conv_std_logic_vector(986894,20);
WHEN "000100001" => data <= conv_std_logic_vector(985083,20);
WHEN "000100010" => data <= conv_std_logic_vector(983279,20);
WHEN "000100011" => data <= conv_std_logic_vector(981482,20);
WHEN "000100100" => data <= conv_std_logic_vector(979691,20);
WHEN "000100101" => data <= conv_std_logic_vector(977906,20);
WHEN "000100110" => data <= conv_std_logic_vector(976128,20);
WHEN "000100111" => data <= conv_std_logic_vector(974357,20);
WHEN "000101000" => data <= conv_std_logic_vector(972591,20);
WHEN "000101001" => data <= conv_std_logic_vector(970833,20);
WHEN "000101010" => data <= conv_std_logic_vector(969080,20);
WHEN "000101011" => data <= conv_std_logic_vector(967334,20);
WHEN "000101100" => data <= conv_std_logic_vector(965594,20);
WHEN "000101101" => data <= conv_std_logic_vector(963861,20);
WHEN "000101110" => data <= conv_std_logic_vector(962133,20);
WHEN "000101111" => data <= conv_std_logic_vector(960412,20);
WHEN "000110000" => data <= conv_std_logic_vector(958697,20);
WHEN "000110001" => data <= conv_std_logic_vector(956988,20);
WHEN "000110010" => data <= conv_std_logic_vector(955286,20);
WHEN "000110011" => data <= conv_std_logic_vector(953589,20);
WHEN "000110100" => data <= conv_std_logic_vector(951898,20);
WHEN "000110101" => data <= conv_std_logic_vector(950213,20);
WHEN "000110110" => data <= conv_std_logic_vector(948534,20);
WHEN "000110111" => data <= conv_std_logic_vector(946862,20);
WHEN "000111000" => data <= conv_std_logic_vector(945195,20);
WHEN "000111001" => data <= conv_std_logic_vector(943533,20);
WHEN "000111010" => data <= conv_std_logic_vector(941878,20);
WHEN "000111011" => data <= conv_std_logic_vector(940229,20);
WHEN "000111100" => data <= conv_std_logic_vector(938585,20);
WHEN "000111101" => data <= conv_std_logic_vector(936947,20);
WHEN "000111110" => data <= conv_std_logic_vector(935314,20);
WHEN "000111111" => data <= conv_std_logic_vector(933688,20);
WHEN "001000000" => data <= conv_std_logic_vector(932067,20);
WHEN "001000001" => data <= conv_std_logic_vector(930451,20);
WHEN "001000010" => data <= conv_std_logic_vector(928842,20);
WHEN "001000011" => data <= conv_std_logic_vector(927237,20);
WHEN "001000100" => data <= conv_std_logic_vector(925639,20);
WHEN "001000101" => data <= conv_std_logic_vector(924046,20);
WHEN "001000110" => data <= conv_std_logic_vector(922458,20);
WHEN "001000111" => data <= conv_std_logic_vector(920876,20);
WHEN "001001000" => data <= conv_std_logic_vector(919299,20);
WHEN "001001001" => data <= conv_std_logic_vector(917727,20);
WHEN "001001010" => data <= conv_std_logic_vector(916161,20);
WHEN "001001011" => data <= conv_std_logic_vector(914601,20);
WHEN "001001100" => data <= conv_std_logic_vector(913045,20);
WHEN "001001101" => data <= conv_std_logic_vector(911495,20);
WHEN "001001110" => data <= conv_std_logic_vector(909950,20);
WHEN "001001111" => data <= conv_std_logic_vector(908410,20);
WHEN "001010000" => data <= conv_std_logic_vector(906876,20);
WHEN "001010001" => data <= conv_std_logic_vector(905347,20);
WHEN "001010010" => data <= conv_std_logic_vector(903822,20);
WHEN "001010011" => data <= conv_std_logic_vector(902303,20);
WHEN "001010100" => data <= conv_std_logic_vector(900789,20);
WHEN "001010101" => data <= conv_std_logic_vector(899281,20);
WHEN "001010110" => data <= conv_std_logic_vector(897777,20);
WHEN "001010111" => data <= conv_std_logic_vector(896278,20);
WHEN "001011000" => data <= conv_std_logic_vector(894784,20);
WHEN "001011001" => data <= conv_std_logic_vector(893295,20);
WHEN "001011010" => data <= conv_std_logic_vector(891812,20);
WHEN "001011011" => data <= conv_std_logic_vector(890333,20);
WHEN "001011100" => data <= conv_std_logic_vector(888859,20);
WHEN "001011101" => data <= conv_std_logic_vector(887389,20);
WHEN "001011110" => data <= conv_std_logic_vector(885925,20);
WHEN "001011111" => data <= conv_std_logic_vector(884465,20);
WHEN "001100000" => data <= conv_std_logic_vector(883011,20);
WHEN "001100001" => data <= conv_std_logic_vector(881561,20);
WHEN "001100010" => data <= conv_std_logic_vector(880116,20);
WHEN "001100011" => data <= conv_std_logic_vector(878675,20);
WHEN "001100100" => data <= conv_std_logic_vector(877239,20);
WHEN "001100101" => data <= conv_std_logic_vector(875808,20);
WHEN "001100110" => data <= conv_std_logic_vector(874382,20);
WHEN "001100111" => data <= conv_std_logic_vector(872960,20);
WHEN "001101000" => data <= conv_std_logic_vector(871543,20);
WHEN "001101001" => data <= conv_std_logic_vector(870131,20);
WHEN "001101010" => data <= conv_std_logic_vector(868723,20);
WHEN "001101011" => data <= conv_std_logic_vector(867319,20);
WHEN "001101100" => data <= conv_std_logic_vector(865920,20);
WHEN "001101101" => data <= conv_std_logic_vector(864526,20);
WHEN "001101110" => data <= conv_std_logic_vector(863136,20);
WHEN "001101111" => data <= conv_std_logic_vector(861751,20);
WHEN "001110000" => data <= conv_std_logic_vector(860369,20);
WHEN "001110001" => data <= conv_std_logic_vector(858993,20);
WHEN "001110010" => data <= conv_std_logic_vector(857621,20);
WHEN "001110011" => data <= conv_std_logic_vector(856253,20);
WHEN "001110100" => data <= conv_std_logic_vector(854889,20);
WHEN "001110101" => data <= conv_std_logic_vector(853530,20);
WHEN "001110110" => data <= conv_std_logic_vector(852176,20);
WHEN "001110111" => data <= conv_std_logic_vector(850825,20);
WHEN "001111000" => data <= conv_std_logic_vector(849479,20);
WHEN "001111001" => data <= conv_std_logic_vector(848137,20);
WHEN "001111010" => data <= conv_std_logic_vector(846799,20);
WHEN "001111011" => data <= conv_std_logic_vector(845465,20);
WHEN "001111100" => data <= conv_std_logic_vector(844136,20);
WHEN "001111101" => data <= conv_std_logic_vector(842811,20);
WHEN "001111110" => data <= conv_std_logic_vector(841490,20);
WHEN "001111111" => data <= conv_std_logic_vector(840173,20);
WHEN "010000000" => data <= conv_std_logic_vector(838860,20);
WHEN "010000001" => data <= conv_std_logic_vector(837552,20);
WHEN "010000010" => data <= conv_std_logic_vector(836247,20);
WHEN "010000011" => data <= conv_std_logic_vector(834946,20);
WHEN "010000100" => data <= conv_std_logic_vector(833650,20);
WHEN "010000101" => data <= conv_std_logic_vector(832358,20);
WHEN "010000110" => data <= conv_std_logic_vector(831069,20);
WHEN "010000111" => data <= conv_std_logic_vector(829785,20);
WHEN "010001000" => data <= conv_std_logic_vector(828504,20);
WHEN "010001001" => data <= conv_std_logic_vector(827227,20);
WHEN "010001010" => data <= conv_std_logic_vector(825955,20);
WHEN "010001011" => data <= conv_std_logic_vector(824686,20);
WHEN "010001100" => data <= conv_std_logic_vector(823421,20);
WHEN "010001101" => data <= conv_std_logic_vector(822160,20);
WHEN "010001110" => data <= conv_std_logic_vector(820903,20);
WHEN "010001111" => data <= conv_std_logic_vector(819650,20);
WHEN "010010000" => data <= conv_std_logic_vector(818400,20);
WHEN "010010001" => data <= conv_std_logic_vector(817155,20);
WHEN "010010010" => data <= conv_std_logic_vector(815913,20);
WHEN "010010011" => data <= conv_std_logic_vector(814675,20);
WHEN "010010100" => data <= conv_std_logic_vector(813440,20);
WHEN "010010101" => data <= conv_std_logic_vector(812210,20);
WHEN "010010110" => data <= conv_std_logic_vector(810983,20);
WHEN "010010111" => data <= conv_std_logic_vector(809760,20);
WHEN "010011000" => data <= conv_std_logic_vector(808540,20);
WHEN "010011001" => data <= conv_std_logic_vector(807324,20);
WHEN "010011010" => data <= conv_std_logic_vector(806112,20);
WHEN "010011011" => data <= conv_std_logic_vector(804903,20);
WHEN "010011100" => data <= conv_std_logic_vector(803699,20);
WHEN "010011101" => data <= conv_std_logic_vector(802497,20);
WHEN "010011110" => data <= conv_std_logic_vector(801299,20);
WHEN "010011111" => data <= conv_std_logic_vector(800105,20);
WHEN "010100000" => data <= conv_std_logic_vector(798915,20);
WHEN "010100001" => data <= conv_std_logic_vector(797728,20);
WHEN "010100010" => data <= conv_std_logic_vector(796544,20);
WHEN "010100011" => data <= conv_std_logic_vector(795364,20);
WHEN "010100100" => data <= conv_std_logic_vector(794187,20);
WHEN "010100101" => data <= conv_std_logic_vector(793014,20);
WHEN "010100110" => data <= conv_std_logic_vector(791845,20);
WHEN "010100111" => data <= conv_std_logic_vector(790678,20);
WHEN "010101000" => data <= conv_std_logic_vector(789516,20);
WHEN "010101001" => data <= conv_std_logic_vector(788356,20);
WHEN "010101010" => data <= conv_std_logic_vector(787200,20);
WHEN "010101011" => data <= conv_std_logic_vector(786048,20);
WHEN "010101100" => data <= conv_std_logic_vector(784899,20);
WHEN "010101101" => data <= conv_std_logic_vector(783753,20);
WHEN "010101110" => data <= conv_std_logic_vector(782610,20);
WHEN "010101111" => data <= conv_std_logic_vector(781471,20);
WHEN "010110000" => data <= conv_std_logic_vector(780335,20);
WHEN "010110001" => data <= conv_std_logic_vector(779203,20);
WHEN "010110010" => data <= conv_std_logic_vector(778073,20);
WHEN "010110011" => data <= conv_std_logic_vector(776947,20);
WHEN "010110100" => data <= conv_std_logic_vector(775825,20);
WHEN "010110101" => data <= conv_std_logic_vector(774705,20);
WHEN "010110110" => data <= conv_std_logic_vector(773589,20);
WHEN "010110111" => data <= conv_std_logic_vector(772476,20);
WHEN "010111000" => data <= conv_std_logic_vector(771366,20);
WHEN "010111001" => data <= conv_std_logic_vector(770259,20);
WHEN "010111010" => data <= conv_std_logic_vector(769156,20);
WHEN "010111011" => data <= conv_std_logic_vector(768055,20);
WHEN "010111100" => data <= conv_std_logic_vector(766958,20);
WHEN "010111101" => data <= conv_std_logic_vector(765864,20);
WHEN "010111110" => data <= conv_std_logic_vector(764773,20);
WHEN "010111111" => data <= conv_std_logic_vector(763685,20);
WHEN "011000000" => data <= conv_std_logic_vector(762600,20);
WHEN "011000001" => data <= conv_std_logic_vector(761519,20);
WHEN "011000010" => data <= conv_std_logic_vector(760440,20);
WHEN "011000011" => data <= conv_std_logic_vector(759364,20);
WHEN "011000100" => data <= conv_std_logic_vector(758292,20);
WHEN "011000101" => data <= conv_std_logic_vector(757222,20);
WHEN "011000110" => data <= conv_std_logic_vector(756156,20);
WHEN "011000111" => data <= conv_std_logic_vector(755092,20);
WHEN "011001000" => data <= conv_std_logic_vector(754032,20);
WHEN "011001001" => data <= conv_std_logic_vector(752974,20);
WHEN "011001010" => data <= conv_std_logic_vector(751920,20);
WHEN "011001011" => data <= conv_std_logic_vector(750868,20);
WHEN "011001100" => data <= conv_std_logic_vector(749819,20);
WHEN "011001101" => data <= conv_std_logic_vector(748774,20);
WHEN "011001110" => data <= conv_std_logic_vector(747731,20);
WHEN "011001111" => data <= conv_std_logic_vector(746691,20);
WHEN "011010000" => data <= conv_std_logic_vector(745654,20);
WHEN "011010001" => data <= conv_std_logic_vector(744619,20);
WHEN "011010010" => data <= conv_std_logic_vector(743588,20);
WHEN "011010011" => data <= conv_std_logic_vector(742560,20);
WHEN "011010100" => data <= conv_std_logic_vector(741534,20);
WHEN "011010101" => data <= conv_std_logic_vector(740511,20);
WHEN "011010110" => data <= conv_std_logic_vector(739491,20);
WHEN "011010111" => data <= conv_std_logic_vector(738474,20);
WHEN "011011000" => data <= conv_std_logic_vector(737460,20);
WHEN "011011001" => data <= conv_std_logic_vector(736448,20);
WHEN "011011010" => data <= conv_std_logic_vector(735439,20);
WHEN "011011011" => data <= conv_std_logic_vector(734433,20);
WHEN "011011100" => data <= conv_std_logic_vector(733430,20);
WHEN "011011101" => data <= conv_std_logic_vector(732429,20);
WHEN "011011110" => data <= conv_std_logic_vector(731431,20);
WHEN "011011111" => data <= conv_std_logic_vector(730436,20);
WHEN "011100000" => data <= conv_std_logic_vector(729444,20);
WHEN "011100001" => data <= conv_std_logic_vector(728454,20);
WHEN "011100010" => data <= conv_std_logic_vector(727467,20);
WHEN "011100011" => data <= conv_std_logic_vector(726483,20);
WHEN "011100100" => data <= conv_std_logic_vector(725501,20);
WHEN "011100101" => data <= conv_std_logic_vector(724522,20);
WHEN "011100110" => data <= conv_std_logic_vector(723545,20);
WHEN "011100111" => data <= conv_std_logic_vector(722572,20);
WHEN "011101000" => data <= conv_std_logic_vector(721600,20);
WHEN "011101001" => data <= conv_std_logic_vector(720632,20);
WHEN "011101010" => data <= conv_std_logic_vector(719666,20);
WHEN "011101011" => data <= conv_std_logic_vector(718702,20);
WHEN "011101100" => data <= conv_std_logic_vector(717742,20);
WHEN "011101101" => data <= conv_std_logic_vector(716783,20);
WHEN "011101110" => data <= conv_std_logic_vector(715828,20);
WHEN "011101111" => data <= conv_std_logic_vector(714874,20);
WHEN "011110000" => data <= conv_std_logic_vector(713924,20);
WHEN "011110001" => data <= conv_std_logic_vector(712976,20);
WHEN "011110010" => data <= conv_std_logic_vector(712030,20);
WHEN "011110011" => data <= conv_std_logic_vector(711087,20);
WHEN "011110100" => data <= conv_std_logic_vector(710146,20);
WHEN "011110101" => data <= conv_std_logic_vector(709208,20);
WHEN "011110110" => data <= conv_std_logic_vector(708273,20);
WHEN "011110111" => data <= conv_std_logic_vector(707339,20);
WHEN "011111000" => data <= conv_std_logic_vector(706409,20);
WHEN "011111001" => data <= conv_std_logic_vector(705481,20);
WHEN "011111010" => data <= conv_std_logic_vector(704555,20);
WHEN "011111011" => data <= conv_std_logic_vector(703631,20);
WHEN "011111100" => data <= conv_std_logic_vector(702710,20);
WHEN "011111101" => data <= conv_std_logic_vector(701792,20);
WHEN "011111110" => data <= conv_std_logic_vector(700876,20);
WHEN "011111111" => data <= conv_std_logic_vector(699962,20);
WHEN "100000000" => data <= conv_std_logic_vector(699050,20);
WHEN "100000001" => data <= conv_std_logic_vector(698141,20);
WHEN "100000010" => data <= conv_std_logic_vector(697235,20);
WHEN "100000011" => data <= conv_std_logic_vector(696330,20);
WHEN "100000100" => data <= conv_std_logic_vector(695428,20);
WHEN "100000101" => data <= conv_std_logic_vector(694529,20);
WHEN "100000110" => data <= conv_std_logic_vector(693631,20);
WHEN "100000111" => data <= conv_std_logic_vector(692736,20);
WHEN "100001000" => data <= conv_std_logic_vector(691844,20);
WHEN "100001001" => data <= conv_std_logic_vector(690953,20);
WHEN "100001010" => data <= conv_std_logic_vector(690065,20);
WHEN "100001011" => data <= conv_std_logic_vector(689179,20);
WHEN "100001100" => data <= conv_std_logic_vector(688296,20);
WHEN "100001101" => data <= conv_std_logic_vector(687414,20);
WHEN "100001110" => data <= conv_std_logic_vector(686535,20);
WHEN "100001111" => data <= conv_std_logic_vector(685659,20);
WHEN "100010000" => data <= conv_std_logic_vector(684784,20);
WHEN "100010001" => data <= conv_std_logic_vector(683912,20);
WHEN "100010010" => data <= conv_std_logic_vector(683042,20);
WHEN "100010011" => data <= conv_std_logic_vector(682174,20);
WHEN "100010100" => data <= conv_std_logic_vector(681308,20);
WHEN "100010101" => data <= conv_std_logic_vector(680444,20);
WHEN "100010110" => data <= conv_std_logic_vector(679583,20);
WHEN "100010111" => data <= conv_std_logic_vector(678724,20);
WHEN "100011000" => data <= conv_std_logic_vector(677867,20);
WHEN "100011001" => data <= conv_std_logic_vector(677012,20);
WHEN "100011010" => data <= conv_std_logic_vector(676160,20);
WHEN "100011011" => data <= conv_std_logic_vector(675309,20);
WHEN "100011100" => data <= conv_std_logic_vector(674461,20);
WHEN "100011101" => data <= conv_std_logic_vector(673614,20);
WHEN "100011110" => data <= conv_std_logic_vector(672770,20);
WHEN "100011111" => data <= conv_std_logic_vector(671928,20);
WHEN "100100000" => data <= conv_std_logic_vector(671088,20);
WHEN "100100001" => data <= conv_std_logic_vector(670251,20);
WHEN "100100010" => data <= conv_std_logic_vector(669415,20);
WHEN "100100011" => data <= conv_std_logic_vector(668581,20);
WHEN "100100100" => data <= conv_std_logic_vector(667750,20);
WHEN "100100101" => data <= conv_std_logic_vector(666920,20);
WHEN "100100110" => data <= conv_std_logic_vector(666093,20);
WHEN "100100111" => data <= conv_std_logic_vector(665267,20);
WHEN "100101000" => data <= conv_std_logic_vector(664444,20);
WHEN "100101001" => data <= conv_std_logic_vector(663623,20);
WHEN "100101010" => data <= conv_std_logic_vector(662803,20);
WHEN "100101011" => data <= conv_std_logic_vector(661986,20);
WHEN "100101100" => data <= conv_std_logic_vector(661171,20);
WHEN "100101101" => data <= conv_std_logic_vector(660358,20);
WHEN "100101110" => data <= conv_std_logic_vector(659546,20);
WHEN "100101111" => data <= conv_std_logic_vector(658737,20);
WHEN "100110000" => data <= conv_std_logic_vector(657930,20);
WHEN "100110001" => data <= conv_std_logic_vector(657124,20);
WHEN "100110010" => data <= conv_std_logic_vector(656321,20);
WHEN "100110011" => data <= conv_std_logic_vector(655520,20);
WHEN "100110100" => data <= conv_std_logic_vector(654720,20);
WHEN "100110101" => data <= conv_std_logic_vector(653923,20);
WHEN "100110110" => data <= conv_std_logic_vector(653127,20);
WHEN "100110111" => data <= conv_std_logic_vector(652334,20);
WHEN "100111000" => data <= conv_std_logic_vector(651542,20);
WHEN "100111001" => data <= conv_std_logic_vector(650752,20);
WHEN "100111010" => data <= conv_std_logic_vector(649965,20);
WHEN "100111011" => data <= conv_std_logic_vector(649179,20);
WHEN "100111100" => data <= conv_std_logic_vector(648395,20);
WHEN "100111101" => data <= conv_std_logic_vector(647612,20);
WHEN "100111110" => data <= conv_std_logic_vector(646832,20);
WHEN "100111111" => data <= conv_std_logic_vector(646054,20);
WHEN "101000000" => data <= conv_std_logic_vector(645277,20);
WHEN "101000001" => data <= conv_std_logic_vector(644503,20);
WHEN "101000010" => data <= conv_std_logic_vector(643730,20);
WHEN "101000011" => data <= conv_std_logic_vector(642959,20);
WHEN "101000100" => data <= conv_std_logic_vector(642190,20);
WHEN "101000101" => data <= conv_std_logic_vector(641423,20);
WHEN "101000110" => data <= conv_std_logic_vector(640657,20);
WHEN "101000111" => data <= conv_std_logic_vector(639894,20);
WHEN "101001000" => data <= conv_std_logic_vector(639132,20);
WHEN "101001001" => data <= conv_std_logic_vector(638372,20);
WHEN "101001010" => data <= conv_std_logic_vector(637614,20);
WHEN "101001011" => data <= conv_std_logic_vector(636857,20);
WHEN "101001100" => data <= conv_std_logic_vector(636103,20);
WHEN "101001101" => data <= conv_std_logic_vector(635350,20);
WHEN "101001110" => data <= conv_std_logic_vector(634599,20);
WHEN "101001111" => data <= conv_std_logic_vector(633850,20);
WHEN "101010000" => data <= conv_std_logic_vector(633102,20);
WHEN "101010001" => data <= conv_std_logic_vector(632357,20);
WHEN "101010010" => data <= conv_std_logic_vector(631613,20);
WHEN "101010011" => data <= conv_std_logic_vector(630870,20);
WHEN "101010100" => data <= conv_std_logic_vector(630130,20);
WHEN "101010101" => data <= conv_std_logic_vector(629391,20);
WHEN "101010110" => data <= conv_std_logic_vector(628654,20);
WHEN "101010111" => data <= conv_std_logic_vector(627919,20);
WHEN "101011000" => data <= conv_std_logic_vector(627185,20);
WHEN "101011001" => data <= conv_std_logic_vector(626454,20);
WHEN "101011010" => data <= conv_std_logic_vector(625723,20);
WHEN "101011011" => data <= conv_std_logic_vector(624995,20);
WHEN "101011100" => data <= conv_std_logic_vector(624268,20);
WHEN "101011101" => data <= conv_std_logic_vector(623543,20);
WHEN "101011110" => data <= conv_std_logic_vector(622820,20);
WHEN "101011111" => data <= conv_std_logic_vector(622098,20);
WHEN "101100000" => data <= conv_std_logic_vector(621378,20);
WHEN "101100001" => data <= conv_std_logic_vector(620660,20);
WHEN "101100010" => data <= conv_std_logic_vector(619943,20);
WHEN "101100011" => data <= conv_std_logic_vector(619228,20);
WHEN "101100100" => data <= conv_std_logic_vector(618515,20);
WHEN "101100101" => data <= conv_std_logic_vector(617803,20);
WHEN "101100110" => data <= conv_std_logic_vector(617093,20);
WHEN "101100111" => data <= conv_std_logic_vector(616384,20);
WHEN "101101000" => data <= conv_std_logic_vector(615677,20);
WHEN "101101001" => data <= conv_std_logic_vector(614972,20);
WHEN "101101010" => data <= conv_std_logic_vector(614269,20);
WHEN "101101011" => data <= conv_std_logic_vector(613567,20);
WHEN "101101100" => data <= conv_std_logic_vector(612866,20);
WHEN "101101101" => data <= conv_std_logic_vector(612167,20);
WHEN "101101110" => data <= conv_std_logic_vector(611470,20);
WHEN "101101111" => data <= conv_std_logic_vector(610774,20);
WHEN "101110000" => data <= conv_std_logic_vector(610080,20);
WHEN "101110001" => data <= conv_std_logic_vector(609388,20);
WHEN "101110010" => data <= conv_std_logic_vector(608697,20);
WHEN "101110011" => data <= conv_std_logic_vector(608008,20);
WHEN "101110100" => data <= conv_std_logic_vector(607320,20);
WHEN "101110101" => data <= conv_std_logic_vector(606634,20);
WHEN "101110110" => data <= conv_std_logic_vector(605949,20);
WHEN "101110111" => data <= conv_std_logic_vector(605266,20);
WHEN "101111000" => data <= conv_std_logic_vector(604584,20);
WHEN "101111001" => data <= conv_std_logic_vector(603904,20);
WHEN "101111010" => data <= conv_std_logic_vector(603226,20);
WHEN "101111011" => data <= conv_std_logic_vector(602549,20);
WHEN "101111100" => data <= conv_std_logic_vector(601873,20);
WHEN "101111101" => data <= conv_std_logic_vector(601199,20);
WHEN "101111110" => data <= conv_std_logic_vector(600527,20);
WHEN "101111111" => data <= conv_std_logic_vector(599856,20);
WHEN "110000000" => data <= conv_std_logic_vector(599186,20);
WHEN "110000001" => data <= conv_std_logic_vector(598518,20);
WHEN "110000010" => data <= conv_std_logic_vector(597852,20);
WHEN "110000011" => data <= conv_std_logic_vector(597187,20);
WHEN "110000100" => data <= conv_std_logic_vector(596523,20);
WHEN "110000101" => data <= conv_std_logic_vector(595861,20);
WHEN "110000110" => data <= conv_std_logic_vector(595200,20);
WHEN "110000111" => data <= conv_std_logic_vector(594541,20);
WHEN "110001000" => data <= conv_std_logic_vector(593884,20);
WHEN "110001001" => data <= conv_std_logic_vector(593227,20);
WHEN "110001010" => data <= conv_std_logic_vector(592573,20);
WHEN "110001011" => data <= conv_std_logic_vector(591919,20);
WHEN "110001100" => data <= conv_std_logic_vector(591267,20);
WHEN "110001101" => data <= conv_std_logic_vector(590617,20);
WHEN "110001110" => data <= conv_std_logic_vector(589968,20);
WHEN "110001111" => data <= conv_std_logic_vector(589320,20);
WHEN "110010000" => data <= conv_std_logic_vector(588674,20);
WHEN "110010001" => data <= conv_std_logic_vector(588029,20);
WHEN "110010010" => data <= conv_std_logic_vector(587386,20);
WHEN "110010011" => data <= conv_std_logic_vector(586744,20);
WHEN "110010100" => data <= conv_std_logic_vector(586103,20);
WHEN "110010101" => data <= conv_std_logic_vector(585464,20);
WHEN "110010110" => data <= conv_std_logic_vector(584827,20);
WHEN "110010111" => data <= conv_std_logic_vector(584190,20);
WHEN "110011000" => data <= conv_std_logic_vector(583555,20);
WHEN "110011001" => data <= conv_std_logic_vector(582922,20);
WHEN "110011010" => data <= conv_std_logic_vector(582289,20);
WHEN "110011011" => data <= conv_std_logic_vector(581658,20);
WHEN "110011100" => data <= conv_std_logic_vector(581029,20);
WHEN "110011101" => data <= conv_std_logic_vector(580401,20);
WHEN "110011110" => data <= conv_std_logic_vector(579774,20);
WHEN "110011111" => data <= conv_std_logic_vector(579149,20);
WHEN "110100000" => data <= conv_std_logic_vector(578525,20);
WHEN "110100001" => data <= conv_std_logic_vector(577902,20);
WHEN "110100010" => data <= conv_std_logic_vector(577280,20);
WHEN "110100011" => data <= conv_std_logic_vector(576660,20);
WHEN "110100100" => data <= conv_std_logic_vector(576042,20);
WHEN "110100101" => data <= conv_std_logic_vector(575424,20);
WHEN "110100110" => data <= conv_std_logic_vector(574808,20);
WHEN "110100111" => data <= conv_std_logic_vector(574193,20);
WHEN "110101000" => data <= conv_std_logic_vector(573580,20);
WHEN "110101001" => data <= conv_std_logic_vector(572968,20);
WHEN "110101010" => data <= conv_std_logic_vector(572357,20);
WHEN "110101011" => data <= conv_std_logic_vector(571747,20);
WHEN "110101100" => data <= conv_std_logic_vector(571139,20);
WHEN "110101101" => data <= conv_std_logic_vector(570532,20);
WHEN "110101110" => data <= conv_std_logic_vector(569926,20);
WHEN "110101111" => data <= conv_std_logic_vector(569322,20);
WHEN "110110000" => data <= conv_std_logic_vector(568719,20);
WHEN "110110001" => data <= conv_std_logic_vector(568117,20);
WHEN "110110010" => data <= conv_std_logic_vector(567517,20);
WHEN "110110011" => data <= conv_std_logic_vector(566917,20);
WHEN "110110100" => data <= conv_std_logic_vector(566319,20);
WHEN "110110101" => data <= conv_std_logic_vector(565723,20);
WHEN "110110110" => data <= conv_std_logic_vector(565127,20);
WHEN "110110111" => data <= conv_std_logic_vector(564533,20);
WHEN "110111000" => data <= conv_std_logic_vector(563940,20);
WHEN "110111001" => data <= conv_std_logic_vector(563348,20);
WHEN "110111010" => data <= conv_std_logic_vector(562758,20);
WHEN "110111011" => data <= conv_std_logic_vector(562168,20);
WHEN "110111100" => data <= conv_std_logic_vector(561580,20);
WHEN "110111101" => data <= conv_std_logic_vector(560993,20);
WHEN "110111110" => data <= conv_std_logic_vector(560408,20);
WHEN "110111111" => data <= conv_std_logic_vector(559824,20);
WHEN "111000000" => data <= conv_std_logic_vector(559240,20);
WHEN "111000001" => data <= conv_std_logic_vector(558658,20);
WHEN "111000010" => data <= conv_std_logic_vector(558078,20);
WHEN "111000011" => data <= conv_std_logic_vector(557498,20);
WHEN "111000100" => data <= conv_std_logic_vector(556920,20);
WHEN "111000101" => data <= conv_std_logic_vector(556343,20);
WHEN "111000110" => data <= conv_std_logic_vector(555767,20);
WHEN "111000111" => data <= conv_std_logic_vector(555192,20);
WHEN "111001000" => data <= conv_std_logic_vector(554619,20);
WHEN "111001001" => data <= conv_std_logic_vector(554046,20);
WHEN "111001010" => data <= conv_std_logic_vector(553475,20);
WHEN "111001011" => data <= conv_std_logic_vector(552905,20);
WHEN "111001100" => data <= conv_std_logic_vector(552336,20);
WHEN "111001101" => data <= conv_std_logic_vector(551769,20);
WHEN "111001110" => data <= conv_std_logic_vector(551202,20);
WHEN "111001111" => data <= conv_std_logic_vector(550637,20);
WHEN "111010000" => data <= conv_std_logic_vector(550073,20);
WHEN "111010001" => data <= conv_std_logic_vector(549509,20);
WHEN "111010010" => data <= conv_std_logic_vector(548948,20);
WHEN "111010011" => data <= conv_std_logic_vector(548387,20);
WHEN "111010100" => data <= conv_std_logic_vector(547827,20);
WHEN "111010101" => data <= conv_std_logic_vector(547269,20);
WHEN "111010110" => data <= conv_std_logic_vector(546712,20);
WHEN "111010111" => data <= conv_std_logic_vector(546155,20);
WHEN "111011000" => data <= conv_std_logic_vector(545600,20);
WHEN "111011001" => data <= conv_std_logic_vector(545046,20);
WHEN "111011010" => data <= conv_std_logic_vector(544494,20);
WHEN "111011011" => data <= conv_std_logic_vector(543942,20);
WHEN "111011100" => data <= conv_std_logic_vector(543391,20);
WHEN "111011101" => data <= conv_std_logic_vector(542842,20);
WHEN "111011110" => data <= conv_std_logic_vector(542294,20);
WHEN "111011111" => data <= conv_std_logic_vector(541746,20);
WHEN "111100000" => data <= conv_std_logic_vector(541200,20);
WHEN "111100001" => data <= conv_std_logic_vector(540655,20);
WHEN "111100010" => data <= conv_std_logic_vector(540111,20);
WHEN "111100011" => data <= conv_std_logic_vector(539569,20);
WHEN "111100100" => data <= conv_std_logic_vector(539027,20);
WHEN "111100101" => data <= conv_std_logic_vector(538486,20);
WHEN "111100110" => data <= conv_std_logic_vector(537947,20);
WHEN "111100111" => data <= conv_std_logic_vector(537408,20);
WHEN "111101000" => data <= conv_std_logic_vector(536871,20);
WHEN "111101001" => data <= conv_std_logic_vector(536334,20);
WHEN "111101010" => data <= conv_std_logic_vector(535799,20);
WHEN "111101011" => data <= conv_std_logic_vector(535265,20);
WHEN "111101100" => data <= conv_std_logic_vector(534732,20);
WHEN "111101101" => data <= conv_std_logic_vector(534200,20);
WHEN "111101110" => data <= conv_std_logic_vector(533669,20);
WHEN "111101111" => data <= conv_std_logic_vector(533139,20);
WHEN "111110000" => data <= conv_std_logic_vector(532610,20);
WHEN "111110001" => data <= conv_std_logic_vector(532082,20);
WHEN "111110010" => data <= conv_std_logic_vector(531555,20);
WHEN "111110011" => data <= conv_std_logic_vector(531029,20);
WHEN "111110100" => data <= conv_std_logic_vector(530505,20);
WHEN "111110101" => data <= conv_std_logic_vector(529981,20);
WHEN "111110110" => data <= conv_std_logic_vector(529458,20);
WHEN "111110111" => data <= conv_std_logic_vector(528937,20);
WHEN "111111000" => data <= conv_std_logic_vector(528416,20);
WHEN "111111001" => data <= conv_std_logic_vector(527897,20);
WHEN "111111010" => data <= conv_std_logic_vector(527378,20);
WHEN "111111011" => data <= conv_std_logic_vector(526860,20);
WHEN "111111100" => data <= conv_std_logic_vector(526344,20);
WHEN "111111101" => data <= conv_std_logic_vector(525828,20);
WHEN "111111110" => data <= conv_std_logic_vector(525314,20);
WHEN "111111111" => data <= conv_std_logic_vector(524800,20);
WHEN others => data <= conv_std_logic_vector(0,20);
END CASE;
END PROCESS;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_DIV_LUT0.VHD ***
--*** ***
--*** Function: Look Up Table - Inverse ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_div_lut0 IS
PORT (
add : IN STD_LOGIC_VECTOR (9 DOWNTO 1);
data : OUT STD_LOGIC_VECTOR (20 DOWNTO 1)
);
END fp_div_lut0;
ARCHITECTURE rtl OF fp_div_lut0 IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "000000000" => data <= conv_std_logic_vector(1048575,20);
WHEN "000000001" => data <= conv_std_logic_vector(1046531,20);
WHEN "000000010" => data <= conv_std_logic_vector(1044495,20);
WHEN "000000011" => data <= conv_std_logic_vector(1042467,20);
WHEN "000000100" => data <= conv_std_logic_vector(1040447,20);
WHEN "000000101" => data <= conv_std_logic_vector(1038434,20);
WHEN "000000110" => data <= conv_std_logic_vector(1036429,20);
WHEN "000000111" => data <= conv_std_logic_vector(1034432,20);
WHEN "000001000" => data <= conv_std_logic_vector(1032443,20);
WHEN "000001001" => data <= conv_std_logic_vector(1030461,20);
WHEN "000001010" => data <= conv_std_logic_vector(1028487,20);
WHEN "000001011" => data <= conv_std_logic_vector(1026521,20);
WHEN "000001100" => data <= conv_std_logic_vector(1024562,20);
WHEN "000001101" => data <= conv_std_logic_vector(1022610,20);
WHEN "000001110" => data <= conv_std_logic_vector(1020666,20);
WHEN "000001111" => data <= conv_std_logic_vector(1018729,20);
WHEN "000010000" => data <= conv_std_logic_vector(1016800,20);
WHEN "000010001" => data <= conv_std_logic_vector(1014878,20);
WHEN "000010010" => data <= conv_std_logic_vector(1012963,20);
WHEN "000010011" => data <= conv_std_logic_vector(1011055,20);
WHEN "000010100" => data <= conv_std_logic_vector(1009155,20);
WHEN "000010101" => data <= conv_std_logic_vector(1007262,20);
WHEN "000010110" => data <= conv_std_logic_vector(1005375,20);
WHEN "000010111" => data <= conv_std_logic_vector(1003496,20);
WHEN "000011000" => data <= conv_std_logic_vector(1001624,20);
WHEN "000011001" => data <= conv_std_logic_vector(999759,20);
WHEN "000011010" => data <= conv_std_logic_vector(997900,20);
WHEN "000011011" => data <= conv_std_logic_vector(996049,20);
WHEN "000011100" => data <= conv_std_logic_vector(994205,20);
WHEN "000011101" => data <= conv_std_logic_vector(992367,20);
WHEN "000011110" => data <= conv_std_logic_vector(990536,20);
WHEN "000011111" => data <= conv_std_logic_vector(988712,20);
WHEN "000100000" => data <= conv_std_logic_vector(986894,20);
WHEN "000100001" => data <= conv_std_logic_vector(985083,20);
WHEN "000100010" => data <= conv_std_logic_vector(983279,20);
WHEN "000100011" => data <= conv_std_logic_vector(981482,20);
WHEN "000100100" => data <= conv_std_logic_vector(979691,20);
WHEN "000100101" => data <= conv_std_logic_vector(977906,20);
WHEN "000100110" => data <= conv_std_logic_vector(976128,20);
WHEN "000100111" => data <= conv_std_logic_vector(974357,20);
WHEN "000101000" => data <= conv_std_logic_vector(972591,20);
WHEN "000101001" => data <= conv_std_logic_vector(970833,20);
WHEN "000101010" => data <= conv_std_logic_vector(969080,20);
WHEN "000101011" => data <= conv_std_logic_vector(967334,20);
WHEN "000101100" => data <= conv_std_logic_vector(965594,20);
WHEN "000101101" => data <= conv_std_logic_vector(963861,20);
WHEN "000101110" => data <= conv_std_logic_vector(962133,20);
WHEN "000101111" => data <= conv_std_logic_vector(960412,20);
WHEN "000110000" => data <= conv_std_logic_vector(958697,20);
WHEN "000110001" => data <= conv_std_logic_vector(956988,20);
WHEN "000110010" => data <= conv_std_logic_vector(955286,20);
WHEN "000110011" => data <= conv_std_logic_vector(953589,20);
WHEN "000110100" => data <= conv_std_logic_vector(951898,20);
WHEN "000110101" => data <= conv_std_logic_vector(950213,20);
WHEN "000110110" => data <= conv_std_logic_vector(948534,20);
WHEN "000110111" => data <= conv_std_logic_vector(946862,20);
WHEN "000111000" => data <= conv_std_logic_vector(945195,20);
WHEN "000111001" => data <= conv_std_logic_vector(943533,20);
WHEN "000111010" => data <= conv_std_logic_vector(941878,20);
WHEN "000111011" => data <= conv_std_logic_vector(940229,20);
WHEN "000111100" => data <= conv_std_logic_vector(938585,20);
WHEN "000111101" => data <= conv_std_logic_vector(936947,20);
WHEN "000111110" => data <= conv_std_logic_vector(935314,20);
WHEN "000111111" => data <= conv_std_logic_vector(933688,20);
WHEN "001000000" => data <= conv_std_logic_vector(932067,20);
WHEN "001000001" => data <= conv_std_logic_vector(930451,20);
WHEN "001000010" => data <= conv_std_logic_vector(928842,20);
WHEN "001000011" => data <= conv_std_logic_vector(927237,20);
WHEN "001000100" => data <= conv_std_logic_vector(925639,20);
WHEN "001000101" => data <= conv_std_logic_vector(924046,20);
WHEN "001000110" => data <= conv_std_logic_vector(922458,20);
WHEN "001000111" => data <= conv_std_logic_vector(920876,20);
WHEN "001001000" => data <= conv_std_logic_vector(919299,20);
WHEN "001001001" => data <= conv_std_logic_vector(917727,20);
WHEN "001001010" => data <= conv_std_logic_vector(916161,20);
WHEN "001001011" => data <= conv_std_logic_vector(914601,20);
WHEN "001001100" => data <= conv_std_logic_vector(913045,20);
WHEN "001001101" => data <= conv_std_logic_vector(911495,20);
WHEN "001001110" => data <= conv_std_logic_vector(909950,20);
WHEN "001001111" => data <= conv_std_logic_vector(908410,20);
WHEN "001010000" => data <= conv_std_logic_vector(906876,20);
WHEN "001010001" => data <= conv_std_logic_vector(905347,20);
WHEN "001010010" => data <= conv_std_logic_vector(903822,20);
WHEN "001010011" => data <= conv_std_logic_vector(902303,20);
WHEN "001010100" => data <= conv_std_logic_vector(900789,20);
WHEN "001010101" => data <= conv_std_logic_vector(899281,20);
WHEN "001010110" => data <= conv_std_logic_vector(897777,20);
WHEN "001010111" => data <= conv_std_logic_vector(896278,20);
WHEN "001011000" => data <= conv_std_logic_vector(894784,20);
WHEN "001011001" => data <= conv_std_logic_vector(893295,20);
WHEN "001011010" => data <= conv_std_logic_vector(891812,20);
WHEN "001011011" => data <= conv_std_logic_vector(890333,20);
WHEN "001011100" => data <= conv_std_logic_vector(888859,20);
WHEN "001011101" => data <= conv_std_logic_vector(887389,20);
WHEN "001011110" => data <= conv_std_logic_vector(885925,20);
WHEN "001011111" => data <= conv_std_logic_vector(884465,20);
WHEN "001100000" => data <= conv_std_logic_vector(883011,20);
WHEN "001100001" => data <= conv_std_logic_vector(881561,20);
WHEN "001100010" => data <= conv_std_logic_vector(880116,20);
WHEN "001100011" => data <= conv_std_logic_vector(878675,20);
WHEN "001100100" => data <= conv_std_logic_vector(877239,20);
WHEN "001100101" => data <= conv_std_logic_vector(875808,20);
WHEN "001100110" => data <= conv_std_logic_vector(874382,20);
WHEN "001100111" => data <= conv_std_logic_vector(872960,20);
WHEN "001101000" => data <= conv_std_logic_vector(871543,20);
WHEN "001101001" => data <= conv_std_logic_vector(870131,20);
WHEN "001101010" => data <= conv_std_logic_vector(868723,20);
WHEN "001101011" => data <= conv_std_logic_vector(867319,20);
WHEN "001101100" => data <= conv_std_logic_vector(865920,20);
WHEN "001101101" => data <= conv_std_logic_vector(864526,20);
WHEN "001101110" => data <= conv_std_logic_vector(863136,20);
WHEN "001101111" => data <= conv_std_logic_vector(861751,20);
WHEN "001110000" => data <= conv_std_logic_vector(860369,20);
WHEN "001110001" => data <= conv_std_logic_vector(858993,20);
WHEN "001110010" => data <= conv_std_logic_vector(857621,20);
WHEN "001110011" => data <= conv_std_logic_vector(856253,20);
WHEN "001110100" => data <= conv_std_logic_vector(854889,20);
WHEN "001110101" => data <= conv_std_logic_vector(853530,20);
WHEN "001110110" => data <= conv_std_logic_vector(852176,20);
WHEN "001110111" => data <= conv_std_logic_vector(850825,20);
WHEN "001111000" => data <= conv_std_logic_vector(849479,20);
WHEN "001111001" => data <= conv_std_logic_vector(848137,20);
WHEN "001111010" => data <= conv_std_logic_vector(846799,20);
WHEN "001111011" => data <= conv_std_logic_vector(845465,20);
WHEN "001111100" => data <= conv_std_logic_vector(844136,20);
WHEN "001111101" => data <= conv_std_logic_vector(842811,20);
WHEN "001111110" => data <= conv_std_logic_vector(841490,20);
WHEN "001111111" => data <= conv_std_logic_vector(840173,20);
WHEN "010000000" => data <= conv_std_logic_vector(838860,20);
WHEN "010000001" => data <= conv_std_logic_vector(837552,20);
WHEN "010000010" => data <= conv_std_logic_vector(836247,20);
WHEN "010000011" => data <= conv_std_logic_vector(834946,20);
WHEN "010000100" => data <= conv_std_logic_vector(833650,20);
WHEN "010000101" => data <= conv_std_logic_vector(832358,20);
WHEN "010000110" => data <= conv_std_logic_vector(831069,20);
WHEN "010000111" => data <= conv_std_logic_vector(829785,20);
WHEN "010001000" => data <= conv_std_logic_vector(828504,20);
WHEN "010001001" => data <= conv_std_logic_vector(827227,20);
WHEN "010001010" => data <= conv_std_logic_vector(825955,20);
WHEN "010001011" => data <= conv_std_logic_vector(824686,20);
WHEN "010001100" => data <= conv_std_logic_vector(823421,20);
WHEN "010001101" => data <= conv_std_logic_vector(822160,20);
WHEN "010001110" => data <= conv_std_logic_vector(820903,20);
WHEN "010001111" => data <= conv_std_logic_vector(819650,20);
WHEN "010010000" => data <= conv_std_logic_vector(818400,20);
WHEN "010010001" => data <= conv_std_logic_vector(817155,20);
WHEN "010010010" => data <= conv_std_logic_vector(815913,20);
WHEN "010010011" => data <= conv_std_logic_vector(814675,20);
WHEN "010010100" => data <= conv_std_logic_vector(813440,20);
WHEN "010010101" => data <= conv_std_logic_vector(812210,20);
WHEN "010010110" => data <= conv_std_logic_vector(810983,20);
WHEN "010010111" => data <= conv_std_logic_vector(809760,20);
WHEN "010011000" => data <= conv_std_logic_vector(808540,20);
WHEN "010011001" => data <= conv_std_logic_vector(807324,20);
WHEN "010011010" => data <= conv_std_logic_vector(806112,20);
WHEN "010011011" => data <= conv_std_logic_vector(804903,20);
WHEN "010011100" => data <= conv_std_logic_vector(803699,20);
WHEN "010011101" => data <= conv_std_logic_vector(802497,20);
WHEN "010011110" => data <= conv_std_logic_vector(801299,20);
WHEN "010011111" => data <= conv_std_logic_vector(800105,20);
WHEN "010100000" => data <= conv_std_logic_vector(798915,20);
WHEN "010100001" => data <= conv_std_logic_vector(797728,20);
WHEN "010100010" => data <= conv_std_logic_vector(796544,20);
WHEN "010100011" => data <= conv_std_logic_vector(795364,20);
WHEN "010100100" => data <= conv_std_logic_vector(794187,20);
WHEN "010100101" => data <= conv_std_logic_vector(793014,20);
WHEN "010100110" => data <= conv_std_logic_vector(791845,20);
WHEN "010100111" => data <= conv_std_logic_vector(790678,20);
WHEN "010101000" => data <= conv_std_logic_vector(789516,20);
WHEN "010101001" => data <= conv_std_logic_vector(788356,20);
WHEN "010101010" => data <= conv_std_logic_vector(787200,20);
WHEN "010101011" => data <= conv_std_logic_vector(786048,20);
WHEN "010101100" => data <= conv_std_logic_vector(784899,20);
WHEN "010101101" => data <= conv_std_logic_vector(783753,20);
WHEN "010101110" => data <= conv_std_logic_vector(782610,20);
WHEN "010101111" => data <= conv_std_logic_vector(781471,20);
WHEN "010110000" => data <= conv_std_logic_vector(780335,20);
WHEN "010110001" => data <= conv_std_logic_vector(779203,20);
WHEN "010110010" => data <= conv_std_logic_vector(778073,20);
WHEN "010110011" => data <= conv_std_logic_vector(776947,20);
WHEN "010110100" => data <= conv_std_logic_vector(775825,20);
WHEN "010110101" => data <= conv_std_logic_vector(774705,20);
WHEN "010110110" => data <= conv_std_logic_vector(773589,20);
WHEN "010110111" => data <= conv_std_logic_vector(772476,20);
WHEN "010111000" => data <= conv_std_logic_vector(771366,20);
WHEN "010111001" => data <= conv_std_logic_vector(770259,20);
WHEN "010111010" => data <= conv_std_logic_vector(769156,20);
WHEN "010111011" => data <= conv_std_logic_vector(768055,20);
WHEN "010111100" => data <= conv_std_logic_vector(766958,20);
WHEN "010111101" => data <= conv_std_logic_vector(765864,20);
WHEN "010111110" => data <= conv_std_logic_vector(764773,20);
WHEN "010111111" => data <= conv_std_logic_vector(763685,20);
WHEN "011000000" => data <= conv_std_logic_vector(762600,20);
WHEN "011000001" => data <= conv_std_logic_vector(761519,20);
WHEN "011000010" => data <= conv_std_logic_vector(760440,20);
WHEN "011000011" => data <= conv_std_logic_vector(759364,20);
WHEN "011000100" => data <= conv_std_logic_vector(758292,20);
WHEN "011000101" => data <= conv_std_logic_vector(757222,20);
WHEN "011000110" => data <= conv_std_logic_vector(756156,20);
WHEN "011000111" => data <= conv_std_logic_vector(755092,20);
WHEN "011001000" => data <= conv_std_logic_vector(754032,20);
WHEN "011001001" => data <= conv_std_logic_vector(752974,20);
WHEN "011001010" => data <= conv_std_logic_vector(751920,20);
WHEN "011001011" => data <= conv_std_logic_vector(750868,20);
WHEN "011001100" => data <= conv_std_logic_vector(749819,20);
WHEN "011001101" => data <= conv_std_logic_vector(748774,20);
WHEN "011001110" => data <= conv_std_logic_vector(747731,20);
WHEN "011001111" => data <= conv_std_logic_vector(746691,20);
WHEN "011010000" => data <= conv_std_logic_vector(745654,20);
WHEN "011010001" => data <= conv_std_logic_vector(744619,20);
WHEN "011010010" => data <= conv_std_logic_vector(743588,20);
WHEN "011010011" => data <= conv_std_logic_vector(742560,20);
WHEN "011010100" => data <= conv_std_logic_vector(741534,20);
WHEN "011010101" => data <= conv_std_logic_vector(740511,20);
WHEN "011010110" => data <= conv_std_logic_vector(739491,20);
WHEN "011010111" => data <= conv_std_logic_vector(738474,20);
WHEN "011011000" => data <= conv_std_logic_vector(737460,20);
WHEN "011011001" => data <= conv_std_logic_vector(736448,20);
WHEN "011011010" => data <= conv_std_logic_vector(735439,20);
WHEN "011011011" => data <= conv_std_logic_vector(734433,20);
WHEN "011011100" => data <= conv_std_logic_vector(733430,20);
WHEN "011011101" => data <= conv_std_logic_vector(732429,20);
WHEN "011011110" => data <= conv_std_logic_vector(731431,20);
WHEN "011011111" => data <= conv_std_logic_vector(730436,20);
WHEN "011100000" => data <= conv_std_logic_vector(729444,20);
WHEN "011100001" => data <= conv_std_logic_vector(728454,20);
WHEN "011100010" => data <= conv_std_logic_vector(727467,20);
WHEN "011100011" => data <= conv_std_logic_vector(726483,20);
WHEN "011100100" => data <= conv_std_logic_vector(725501,20);
WHEN "011100101" => data <= conv_std_logic_vector(724522,20);
WHEN "011100110" => data <= conv_std_logic_vector(723545,20);
WHEN "011100111" => data <= conv_std_logic_vector(722572,20);
WHEN "011101000" => data <= conv_std_logic_vector(721600,20);
WHEN "011101001" => data <= conv_std_logic_vector(720632,20);
WHEN "011101010" => data <= conv_std_logic_vector(719666,20);
WHEN "011101011" => data <= conv_std_logic_vector(718702,20);
WHEN "011101100" => data <= conv_std_logic_vector(717742,20);
WHEN "011101101" => data <= conv_std_logic_vector(716783,20);
WHEN "011101110" => data <= conv_std_logic_vector(715828,20);
WHEN "011101111" => data <= conv_std_logic_vector(714874,20);
WHEN "011110000" => data <= conv_std_logic_vector(713924,20);
WHEN "011110001" => data <= conv_std_logic_vector(712976,20);
WHEN "011110010" => data <= conv_std_logic_vector(712030,20);
WHEN "011110011" => data <= conv_std_logic_vector(711087,20);
WHEN "011110100" => data <= conv_std_logic_vector(710146,20);
WHEN "011110101" => data <= conv_std_logic_vector(709208,20);
WHEN "011110110" => data <= conv_std_logic_vector(708273,20);
WHEN "011110111" => data <= conv_std_logic_vector(707339,20);
WHEN "011111000" => data <= conv_std_logic_vector(706409,20);
WHEN "011111001" => data <= conv_std_logic_vector(705481,20);
WHEN "011111010" => data <= conv_std_logic_vector(704555,20);
WHEN "011111011" => data <= conv_std_logic_vector(703631,20);
WHEN "011111100" => data <= conv_std_logic_vector(702710,20);
WHEN "011111101" => data <= conv_std_logic_vector(701792,20);
WHEN "011111110" => data <= conv_std_logic_vector(700876,20);
WHEN "011111111" => data <= conv_std_logic_vector(699962,20);
WHEN "100000000" => data <= conv_std_logic_vector(699050,20);
WHEN "100000001" => data <= conv_std_logic_vector(698141,20);
WHEN "100000010" => data <= conv_std_logic_vector(697235,20);
WHEN "100000011" => data <= conv_std_logic_vector(696330,20);
WHEN "100000100" => data <= conv_std_logic_vector(695428,20);
WHEN "100000101" => data <= conv_std_logic_vector(694529,20);
WHEN "100000110" => data <= conv_std_logic_vector(693631,20);
WHEN "100000111" => data <= conv_std_logic_vector(692736,20);
WHEN "100001000" => data <= conv_std_logic_vector(691844,20);
WHEN "100001001" => data <= conv_std_logic_vector(690953,20);
WHEN "100001010" => data <= conv_std_logic_vector(690065,20);
WHEN "100001011" => data <= conv_std_logic_vector(689179,20);
WHEN "100001100" => data <= conv_std_logic_vector(688296,20);
WHEN "100001101" => data <= conv_std_logic_vector(687414,20);
WHEN "100001110" => data <= conv_std_logic_vector(686535,20);
WHEN "100001111" => data <= conv_std_logic_vector(685659,20);
WHEN "100010000" => data <= conv_std_logic_vector(684784,20);
WHEN "100010001" => data <= conv_std_logic_vector(683912,20);
WHEN "100010010" => data <= conv_std_logic_vector(683042,20);
WHEN "100010011" => data <= conv_std_logic_vector(682174,20);
WHEN "100010100" => data <= conv_std_logic_vector(681308,20);
WHEN "100010101" => data <= conv_std_logic_vector(680444,20);
WHEN "100010110" => data <= conv_std_logic_vector(679583,20);
WHEN "100010111" => data <= conv_std_logic_vector(678724,20);
WHEN "100011000" => data <= conv_std_logic_vector(677867,20);
WHEN "100011001" => data <= conv_std_logic_vector(677012,20);
WHEN "100011010" => data <= conv_std_logic_vector(676160,20);
WHEN "100011011" => data <= conv_std_logic_vector(675309,20);
WHEN "100011100" => data <= conv_std_logic_vector(674461,20);
WHEN "100011101" => data <= conv_std_logic_vector(673614,20);
WHEN "100011110" => data <= conv_std_logic_vector(672770,20);
WHEN "100011111" => data <= conv_std_logic_vector(671928,20);
WHEN "100100000" => data <= conv_std_logic_vector(671088,20);
WHEN "100100001" => data <= conv_std_logic_vector(670251,20);
WHEN "100100010" => data <= conv_std_logic_vector(669415,20);
WHEN "100100011" => data <= conv_std_logic_vector(668581,20);
WHEN "100100100" => data <= conv_std_logic_vector(667750,20);
WHEN "100100101" => data <= conv_std_logic_vector(666920,20);
WHEN "100100110" => data <= conv_std_logic_vector(666093,20);
WHEN "100100111" => data <= conv_std_logic_vector(665267,20);
WHEN "100101000" => data <= conv_std_logic_vector(664444,20);
WHEN "100101001" => data <= conv_std_logic_vector(663623,20);
WHEN "100101010" => data <= conv_std_logic_vector(662803,20);
WHEN "100101011" => data <= conv_std_logic_vector(661986,20);
WHEN "100101100" => data <= conv_std_logic_vector(661171,20);
WHEN "100101101" => data <= conv_std_logic_vector(660358,20);
WHEN "100101110" => data <= conv_std_logic_vector(659546,20);
WHEN "100101111" => data <= conv_std_logic_vector(658737,20);
WHEN "100110000" => data <= conv_std_logic_vector(657930,20);
WHEN "100110001" => data <= conv_std_logic_vector(657124,20);
WHEN "100110010" => data <= conv_std_logic_vector(656321,20);
WHEN "100110011" => data <= conv_std_logic_vector(655520,20);
WHEN "100110100" => data <= conv_std_logic_vector(654720,20);
WHEN "100110101" => data <= conv_std_logic_vector(653923,20);
WHEN "100110110" => data <= conv_std_logic_vector(653127,20);
WHEN "100110111" => data <= conv_std_logic_vector(652334,20);
WHEN "100111000" => data <= conv_std_logic_vector(651542,20);
WHEN "100111001" => data <= conv_std_logic_vector(650752,20);
WHEN "100111010" => data <= conv_std_logic_vector(649965,20);
WHEN "100111011" => data <= conv_std_logic_vector(649179,20);
WHEN "100111100" => data <= conv_std_logic_vector(648395,20);
WHEN "100111101" => data <= conv_std_logic_vector(647612,20);
WHEN "100111110" => data <= conv_std_logic_vector(646832,20);
WHEN "100111111" => data <= conv_std_logic_vector(646054,20);
WHEN "101000000" => data <= conv_std_logic_vector(645277,20);
WHEN "101000001" => data <= conv_std_logic_vector(644503,20);
WHEN "101000010" => data <= conv_std_logic_vector(643730,20);
WHEN "101000011" => data <= conv_std_logic_vector(642959,20);
WHEN "101000100" => data <= conv_std_logic_vector(642190,20);
WHEN "101000101" => data <= conv_std_logic_vector(641423,20);
WHEN "101000110" => data <= conv_std_logic_vector(640657,20);
WHEN "101000111" => data <= conv_std_logic_vector(639894,20);
WHEN "101001000" => data <= conv_std_logic_vector(639132,20);
WHEN "101001001" => data <= conv_std_logic_vector(638372,20);
WHEN "101001010" => data <= conv_std_logic_vector(637614,20);
WHEN "101001011" => data <= conv_std_logic_vector(636857,20);
WHEN "101001100" => data <= conv_std_logic_vector(636103,20);
WHEN "101001101" => data <= conv_std_logic_vector(635350,20);
WHEN "101001110" => data <= conv_std_logic_vector(634599,20);
WHEN "101001111" => data <= conv_std_logic_vector(633850,20);
WHEN "101010000" => data <= conv_std_logic_vector(633102,20);
WHEN "101010001" => data <= conv_std_logic_vector(632357,20);
WHEN "101010010" => data <= conv_std_logic_vector(631613,20);
WHEN "101010011" => data <= conv_std_logic_vector(630870,20);
WHEN "101010100" => data <= conv_std_logic_vector(630130,20);
WHEN "101010101" => data <= conv_std_logic_vector(629391,20);
WHEN "101010110" => data <= conv_std_logic_vector(628654,20);
WHEN "101010111" => data <= conv_std_logic_vector(627919,20);
WHEN "101011000" => data <= conv_std_logic_vector(627185,20);
WHEN "101011001" => data <= conv_std_logic_vector(626454,20);
WHEN "101011010" => data <= conv_std_logic_vector(625723,20);
WHEN "101011011" => data <= conv_std_logic_vector(624995,20);
WHEN "101011100" => data <= conv_std_logic_vector(624268,20);
WHEN "101011101" => data <= conv_std_logic_vector(623543,20);
WHEN "101011110" => data <= conv_std_logic_vector(622820,20);
WHEN "101011111" => data <= conv_std_logic_vector(622098,20);
WHEN "101100000" => data <= conv_std_logic_vector(621378,20);
WHEN "101100001" => data <= conv_std_logic_vector(620660,20);
WHEN "101100010" => data <= conv_std_logic_vector(619943,20);
WHEN "101100011" => data <= conv_std_logic_vector(619228,20);
WHEN "101100100" => data <= conv_std_logic_vector(618515,20);
WHEN "101100101" => data <= conv_std_logic_vector(617803,20);
WHEN "101100110" => data <= conv_std_logic_vector(617093,20);
WHEN "101100111" => data <= conv_std_logic_vector(616384,20);
WHEN "101101000" => data <= conv_std_logic_vector(615677,20);
WHEN "101101001" => data <= conv_std_logic_vector(614972,20);
WHEN "101101010" => data <= conv_std_logic_vector(614269,20);
WHEN "101101011" => data <= conv_std_logic_vector(613567,20);
WHEN "101101100" => data <= conv_std_logic_vector(612866,20);
WHEN "101101101" => data <= conv_std_logic_vector(612167,20);
WHEN "101101110" => data <= conv_std_logic_vector(611470,20);
WHEN "101101111" => data <= conv_std_logic_vector(610774,20);
WHEN "101110000" => data <= conv_std_logic_vector(610080,20);
WHEN "101110001" => data <= conv_std_logic_vector(609388,20);
WHEN "101110010" => data <= conv_std_logic_vector(608697,20);
WHEN "101110011" => data <= conv_std_logic_vector(608008,20);
WHEN "101110100" => data <= conv_std_logic_vector(607320,20);
WHEN "101110101" => data <= conv_std_logic_vector(606634,20);
WHEN "101110110" => data <= conv_std_logic_vector(605949,20);
WHEN "101110111" => data <= conv_std_logic_vector(605266,20);
WHEN "101111000" => data <= conv_std_logic_vector(604584,20);
WHEN "101111001" => data <= conv_std_logic_vector(603904,20);
WHEN "101111010" => data <= conv_std_logic_vector(603226,20);
WHEN "101111011" => data <= conv_std_logic_vector(602549,20);
WHEN "101111100" => data <= conv_std_logic_vector(601873,20);
WHEN "101111101" => data <= conv_std_logic_vector(601199,20);
WHEN "101111110" => data <= conv_std_logic_vector(600527,20);
WHEN "101111111" => data <= conv_std_logic_vector(599856,20);
WHEN "110000000" => data <= conv_std_logic_vector(599186,20);
WHEN "110000001" => data <= conv_std_logic_vector(598518,20);
WHEN "110000010" => data <= conv_std_logic_vector(597852,20);
WHEN "110000011" => data <= conv_std_logic_vector(597187,20);
WHEN "110000100" => data <= conv_std_logic_vector(596523,20);
WHEN "110000101" => data <= conv_std_logic_vector(595861,20);
WHEN "110000110" => data <= conv_std_logic_vector(595200,20);
WHEN "110000111" => data <= conv_std_logic_vector(594541,20);
WHEN "110001000" => data <= conv_std_logic_vector(593884,20);
WHEN "110001001" => data <= conv_std_logic_vector(593227,20);
WHEN "110001010" => data <= conv_std_logic_vector(592573,20);
WHEN "110001011" => data <= conv_std_logic_vector(591919,20);
WHEN "110001100" => data <= conv_std_logic_vector(591267,20);
WHEN "110001101" => data <= conv_std_logic_vector(590617,20);
WHEN "110001110" => data <= conv_std_logic_vector(589968,20);
WHEN "110001111" => data <= conv_std_logic_vector(589320,20);
WHEN "110010000" => data <= conv_std_logic_vector(588674,20);
WHEN "110010001" => data <= conv_std_logic_vector(588029,20);
WHEN "110010010" => data <= conv_std_logic_vector(587386,20);
WHEN "110010011" => data <= conv_std_logic_vector(586744,20);
WHEN "110010100" => data <= conv_std_logic_vector(586103,20);
WHEN "110010101" => data <= conv_std_logic_vector(585464,20);
WHEN "110010110" => data <= conv_std_logic_vector(584827,20);
WHEN "110010111" => data <= conv_std_logic_vector(584190,20);
WHEN "110011000" => data <= conv_std_logic_vector(583555,20);
WHEN "110011001" => data <= conv_std_logic_vector(582922,20);
WHEN "110011010" => data <= conv_std_logic_vector(582289,20);
WHEN "110011011" => data <= conv_std_logic_vector(581658,20);
WHEN "110011100" => data <= conv_std_logic_vector(581029,20);
WHEN "110011101" => data <= conv_std_logic_vector(580401,20);
WHEN "110011110" => data <= conv_std_logic_vector(579774,20);
WHEN "110011111" => data <= conv_std_logic_vector(579149,20);
WHEN "110100000" => data <= conv_std_logic_vector(578525,20);
WHEN "110100001" => data <= conv_std_logic_vector(577902,20);
WHEN "110100010" => data <= conv_std_logic_vector(577280,20);
WHEN "110100011" => data <= conv_std_logic_vector(576660,20);
WHEN "110100100" => data <= conv_std_logic_vector(576042,20);
WHEN "110100101" => data <= conv_std_logic_vector(575424,20);
WHEN "110100110" => data <= conv_std_logic_vector(574808,20);
WHEN "110100111" => data <= conv_std_logic_vector(574193,20);
WHEN "110101000" => data <= conv_std_logic_vector(573580,20);
WHEN "110101001" => data <= conv_std_logic_vector(572968,20);
WHEN "110101010" => data <= conv_std_logic_vector(572357,20);
WHEN "110101011" => data <= conv_std_logic_vector(571747,20);
WHEN "110101100" => data <= conv_std_logic_vector(571139,20);
WHEN "110101101" => data <= conv_std_logic_vector(570532,20);
WHEN "110101110" => data <= conv_std_logic_vector(569926,20);
WHEN "110101111" => data <= conv_std_logic_vector(569322,20);
WHEN "110110000" => data <= conv_std_logic_vector(568719,20);
WHEN "110110001" => data <= conv_std_logic_vector(568117,20);
WHEN "110110010" => data <= conv_std_logic_vector(567517,20);
WHEN "110110011" => data <= conv_std_logic_vector(566917,20);
WHEN "110110100" => data <= conv_std_logic_vector(566319,20);
WHEN "110110101" => data <= conv_std_logic_vector(565723,20);
WHEN "110110110" => data <= conv_std_logic_vector(565127,20);
WHEN "110110111" => data <= conv_std_logic_vector(564533,20);
WHEN "110111000" => data <= conv_std_logic_vector(563940,20);
WHEN "110111001" => data <= conv_std_logic_vector(563348,20);
WHEN "110111010" => data <= conv_std_logic_vector(562758,20);
WHEN "110111011" => data <= conv_std_logic_vector(562168,20);
WHEN "110111100" => data <= conv_std_logic_vector(561580,20);
WHEN "110111101" => data <= conv_std_logic_vector(560993,20);
WHEN "110111110" => data <= conv_std_logic_vector(560408,20);
WHEN "110111111" => data <= conv_std_logic_vector(559824,20);
WHEN "111000000" => data <= conv_std_logic_vector(559240,20);
WHEN "111000001" => data <= conv_std_logic_vector(558658,20);
WHEN "111000010" => data <= conv_std_logic_vector(558078,20);
WHEN "111000011" => data <= conv_std_logic_vector(557498,20);
WHEN "111000100" => data <= conv_std_logic_vector(556920,20);
WHEN "111000101" => data <= conv_std_logic_vector(556343,20);
WHEN "111000110" => data <= conv_std_logic_vector(555767,20);
WHEN "111000111" => data <= conv_std_logic_vector(555192,20);
WHEN "111001000" => data <= conv_std_logic_vector(554619,20);
WHEN "111001001" => data <= conv_std_logic_vector(554046,20);
WHEN "111001010" => data <= conv_std_logic_vector(553475,20);
WHEN "111001011" => data <= conv_std_logic_vector(552905,20);
WHEN "111001100" => data <= conv_std_logic_vector(552336,20);
WHEN "111001101" => data <= conv_std_logic_vector(551769,20);
WHEN "111001110" => data <= conv_std_logic_vector(551202,20);
WHEN "111001111" => data <= conv_std_logic_vector(550637,20);
WHEN "111010000" => data <= conv_std_logic_vector(550073,20);
WHEN "111010001" => data <= conv_std_logic_vector(549509,20);
WHEN "111010010" => data <= conv_std_logic_vector(548948,20);
WHEN "111010011" => data <= conv_std_logic_vector(548387,20);
WHEN "111010100" => data <= conv_std_logic_vector(547827,20);
WHEN "111010101" => data <= conv_std_logic_vector(547269,20);
WHEN "111010110" => data <= conv_std_logic_vector(546712,20);
WHEN "111010111" => data <= conv_std_logic_vector(546155,20);
WHEN "111011000" => data <= conv_std_logic_vector(545600,20);
WHEN "111011001" => data <= conv_std_logic_vector(545046,20);
WHEN "111011010" => data <= conv_std_logic_vector(544494,20);
WHEN "111011011" => data <= conv_std_logic_vector(543942,20);
WHEN "111011100" => data <= conv_std_logic_vector(543391,20);
WHEN "111011101" => data <= conv_std_logic_vector(542842,20);
WHEN "111011110" => data <= conv_std_logic_vector(542294,20);
WHEN "111011111" => data <= conv_std_logic_vector(541746,20);
WHEN "111100000" => data <= conv_std_logic_vector(541200,20);
WHEN "111100001" => data <= conv_std_logic_vector(540655,20);
WHEN "111100010" => data <= conv_std_logic_vector(540111,20);
WHEN "111100011" => data <= conv_std_logic_vector(539569,20);
WHEN "111100100" => data <= conv_std_logic_vector(539027,20);
WHEN "111100101" => data <= conv_std_logic_vector(538486,20);
WHEN "111100110" => data <= conv_std_logic_vector(537947,20);
WHEN "111100111" => data <= conv_std_logic_vector(537408,20);
WHEN "111101000" => data <= conv_std_logic_vector(536871,20);
WHEN "111101001" => data <= conv_std_logic_vector(536334,20);
WHEN "111101010" => data <= conv_std_logic_vector(535799,20);
WHEN "111101011" => data <= conv_std_logic_vector(535265,20);
WHEN "111101100" => data <= conv_std_logic_vector(534732,20);
WHEN "111101101" => data <= conv_std_logic_vector(534200,20);
WHEN "111101110" => data <= conv_std_logic_vector(533669,20);
WHEN "111101111" => data <= conv_std_logic_vector(533139,20);
WHEN "111110000" => data <= conv_std_logic_vector(532610,20);
WHEN "111110001" => data <= conv_std_logic_vector(532082,20);
WHEN "111110010" => data <= conv_std_logic_vector(531555,20);
WHEN "111110011" => data <= conv_std_logic_vector(531029,20);
WHEN "111110100" => data <= conv_std_logic_vector(530505,20);
WHEN "111110101" => data <= conv_std_logic_vector(529981,20);
WHEN "111110110" => data <= conv_std_logic_vector(529458,20);
WHEN "111110111" => data <= conv_std_logic_vector(528937,20);
WHEN "111111000" => data <= conv_std_logic_vector(528416,20);
WHEN "111111001" => data <= conv_std_logic_vector(527897,20);
WHEN "111111010" => data <= conv_std_logic_vector(527378,20);
WHEN "111111011" => data <= conv_std_logic_vector(526860,20);
WHEN "111111100" => data <= conv_std_logic_vector(526344,20);
WHEN "111111101" => data <= conv_std_logic_vector(525828,20);
WHEN "111111110" => data <= conv_std_logic_vector(525314,20);
WHEN "111111111" => data <= conv_std_logic_vector(524800,20);
WHEN others => data <= conv_std_logic_vector(0,20);
END CASE;
END PROCESS;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_DIV_LUT0.VHD ***
--*** ***
--*** Function: Look Up Table - Inverse ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_div_lut0 IS
PORT (
add : IN STD_LOGIC_VECTOR (9 DOWNTO 1);
data : OUT STD_LOGIC_VECTOR (20 DOWNTO 1)
);
END fp_div_lut0;
ARCHITECTURE rtl OF fp_div_lut0 IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "000000000" => data <= conv_std_logic_vector(1048575,20);
WHEN "000000001" => data <= conv_std_logic_vector(1046531,20);
WHEN "000000010" => data <= conv_std_logic_vector(1044495,20);
WHEN "000000011" => data <= conv_std_logic_vector(1042467,20);
WHEN "000000100" => data <= conv_std_logic_vector(1040447,20);
WHEN "000000101" => data <= conv_std_logic_vector(1038434,20);
WHEN "000000110" => data <= conv_std_logic_vector(1036429,20);
WHEN "000000111" => data <= conv_std_logic_vector(1034432,20);
WHEN "000001000" => data <= conv_std_logic_vector(1032443,20);
WHEN "000001001" => data <= conv_std_logic_vector(1030461,20);
WHEN "000001010" => data <= conv_std_logic_vector(1028487,20);
WHEN "000001011" => data <= conv_std_logic_vector(1026521,20);
WHEN "000001100" => data <= conv_std_logic_vector(1024562,20);
WHEN "000001101" => data <= conv_std_logic_vector(1022610,20);
WHEN "000001110" => data <= conv_std_logic_vector(1020666,20);
WHEN "000001111" => data <= conv_std_logic_vector(1018729,20);
WHEN "000010000" => data <= conv_std_logic_vector(1016800,20);
WHEN "000010001" => data <= conv_std_logic_vector(1014878,20);
WHEN "000010010" => data <= conv_std_logic_vector(1012963,20);
WHEN "000010011" => data <= conv_std_logic_vector(1011055,20);
WHEN "000010100" => data <= conv_std_logic_vector(1009155,20);
WHEN "000010101" => data <= conv_std_logic_vector(1007262,20);
WHEN "000010110" => data <= conv_std_logic_vector(1005375,20);
WHEN "000010111" => data <= conv_std_logic_vector(1003496,20);
WHEN "000011000" => data <= conv_std_logic_vector(1001624,20);
WHEN "000011001" => data <= conv_std_logic_vector(999759,20);
WHEN "000011010" => data <= conv_std_logic_vector(997900,20);
WHEN "000011011" => data <= conv_std_logic_vector(996049,20);
WHEN "000011100" => data <= conv_std_logic_vector(994205,20);
WHEN "000011101" => data <= conv_std_logic_vector(992367,20);
WHEN "000011110" => data <= conv_std_logic_vector(990536,20);
WHEN "000011111" => data <= conv_std_logic_vector(988712,20);
WHEN "000100000" => data <= conv_std_logic_vector(986894,20);
WHEN "000100001" => data <= conv_std_logic_vector(985083,20);
WHEN "000100010" => data <= conv_std_logic_vector(983279,20);
WHEN "000100011" => data <= conv_std_logic_vector(981482,20);
WHEN "000100100" => data <= conv_std_logic_vector(979691,20);
WHEN "000100101" => data <= conv_std_logic_vector(977906,20);
WHEN "000100110" => data <= conv_std_logic_vector(976128,20);
WHEN "000100111" => data <= conv_std_logic_vector(974357,20);
WHEN "000101000" => data <= conv_std_logic_vector(972591,20);
WHEN "000101001" => data <= conv_std_logic_vector(970833,20);
WHEN "000101010" => data <= conv_std_logic_vector(969080,20);
WHEN "000101011" => data <= conv_std_logic_vector(967334,20);
WHEN "000101100" => data <= conv_std_logic_vector(965594,20);
WHEN "000101101" => data <= conv_std_logic_vector(963861,20);
WHEN "000101110" => data <= conv_std_logic_vector(962133,20);
WHEN "000101111" => data <= conv_std_logic_vector(960412,20);
WHEN "000110000" => data <= conv_std_logic_vector(958697,20);
WHEN "000110001" => data <= conv_std_logic_vector(956988,20);
WHEN "000110010" => data <= conv_std_logic_vector(955286,20);
WHEN "000110011" => data <= conv_std_logic_vector(953589,20);
WHEN "000110100" => data <= conv_std_logic_vector(951898,20);
WHEN "000110101" => data <= conv_std_logic_vector(950213,20);
WHEN "000110110" => data <= conv_std_logic_vector(948534,20);
WHEN "000110111" => data <= conv_std_logic_vector(946862,20);
WHEN "000111000" => data <= conv_std_logic_vector(945195,20);
WHEN "000111001" => data <= conv_std_logic_vector(943533,20);
WHEN "000111010" => data <= conv_std_logic_vector(941878,20);
WHEN "000111011" => data <= conv_std_logic_vector(940229,20);
WHEN "000111100" => data <= conv_std_logic_vector(938585,20);
WHEN "000111101" => data <= conv_std_logic_vector(936947,20);
WHEN "000111110" => data <= conv_std_logic_vector(935314,20);
WHEN "000111111" => data <= conv_std_logic_vector(933688,20);
WHEN "001000000" => data <= conv_std_logic_vector(932067,20);
WHEN "001000001" => data <= conv_std_logic_vector(930451,20);
WHEN "001000010" => data <= conv_std_logic_vector(928842,20);
WHEN "001000011" => data <= conv_std_logic_vector(927237,20);
WHEN "001000100" => data <= conv_std_logic_vector(925639,20);
WHEN "001000101" => data <= conv_std_logic_vector(924046,20);
WHEN "001000110" => data <= conv_std_logic_vector(922458,20);
WHEN "001000111" => data <= conv_std_logic_vector(920876,20);
WHEN "001001000" => data <= conv_std_logic_vector(919299,20);
WHEN "001001001" => data <= conv_std_logic_vector(917727,20);
WHEN "001001010" => data <= conv_std_logic_vector(916161,20);
WHEN "001001011" => data <= conv_std_logic_vector(914601,20);
WHEN "001001100" => data <= conv_std_logic_vector(913045,20);
WHEN "001001101" => data <= conv_std_logic_vector(911495,20);
WHEN "001001110" => data <= conv_std_logic_vector(909950,20);
WHEN "001001111" => data <= conv_std_logic_vector(908410,20);
WHEN "001010000" => data <= conv_std_logic_vector(906876,20);
WHEN "001010001" => data <= conv_std_logic_vector(905347,20);
WHEN "001010010" => data <= conv_std_logic_vector(903822,20);
WHEN "001010011" => data <= conv_std_logic_vector(902303,20);
WHEN "001010100" => data <= conv_std_logic_vector(900789,20);
WHEN "001010101" => data <= conv_std_logic_vector(899281,20);
WHEN "001010110" => data <= conv_std_logic_vector(897777,20);
WHEN "001010111" => data <= conv_std_logic_vector(896278,20);
WHEN "001011000" => data <= conv_std_logic_vector(894784,20);
WHEN "001011001" => data <= conv_std_logic_vector(893295,20);
WHEN "001011010" => data <= conv_std_logic_vector(891812,20);
WHEN "001011011" => data <= conv_std_logic_vector(890333,20);
WHEN "001011100" => data <= conv_std_logic_vector(888859,20);
WHEN "001011101" => data <= conv_std_logic_vector(887389,20);
WHEN "001011110" => data <= conv_std_logic_vector(885925,20);
WHEN "001011111" => data <= conv_std_logic_vector(884465,20);
WHEN "001100000" => data <= conv_std_logic_vector(883011,20);
WHEN "001100001" => data <= conv_std_logic_vector(881561,20);
WHEN "001100010" => data <= conv_std_logic_vector(880116,20);
WHEN "001100011" => data <= conv_std_logic_vector(878675,20);
WHEN "001100100" => data <= conv_std_logic_vector(877239,20);
WHEN "001100101" => data <= conv_std_logic_vector(875808,20);
WHEN "001100110" => data <= conv_std_logic_vector(874382,20);
WHEN "001100111" => data <= conv_std_logic_vector(872960,20);
WHEN "001101000" => data <= conv_std_logic_vector(871543,20);
WHEN "001101001" => data <= conv_std_logic_vector(870131,20);
WHEN "001101010" => data <= conv_std_logic_vector(868723,20);
WHEN "001101011" => data <= conv_std_logic_vector(867319,20);
WHEN "001101100" => data <= conv_std_logic_vector(865920,20);
WHEN "001101101" => data <= conv_std_logic_vector(864526,20);
WHEN "001101110" => data <= conv_std_logic_vector(863136,20);
WHEN "001101111" => data <= conv_std_logic_vector(861751,20);
WHEN "001110000" => data <= conv_std_logic_vector(860369,20);
WHEN "001110001" => data <= conv_std_logic_vector(858993,20);
WHEN "001110010" => data <= conv_std_logic_vector(857621,20);
WHEN "001110011" => data <= conv_std_logic_vector(856253,20);
WHEN "001110100" => data <= conv_std_logic_vector(854889,20);
WHEN "001110101" => data <= conv_std_logic_vector(853530,20);
WHEN "001110110" => data <= conv_std_logic_vector(852176,20);
WHEN "001110111" => data <= conv_std_logic_vector(850825,20);
WHEN "001111000" => data <= conv_std_logic_vector(849479,20);
WHEN "001111001" => data <= conv_std_logic_vector(848137,20);
WHEN "001111010" => data <= conv_std_logic_vector(846799,20);
WHEN "001111011" => data <= conv_std_logic_vector(845465,20);
WHEN "001111100" => data <= conv_std_logic_vector(844136,20);
WHEN "001111101" => data <= conv_std_logic_vector(842811,20);
WHEN "001111110" => data <= conv_std_logic_vector(841490,20);
WHEN "001111111" => data <= conv_std_logic_vector(840173,20);
WHEN "010000000" => data <= conv_std_logic_vector(838860,20);
WHEN "010000001" => data <= conv_std_logic_vector(837552,20);
WHEN "010000010" => data <= conv_std_logic_vector(836247,20);
WHEN "010000011" => data <= conv_std_logic_vector(834946,20);
WHEN "010000100" => data <= conv_std_logic_vector(833650,20);
WHEN "010000101" => data <= conv_std_logic_vector(832358,20);
WHEN "010000110" => data <= conv_std_logic_vector(831069,20);
WHEN "010000111" => data <= conv_std_logic_vector(829785,20);
WHEN "010001000" => data <= conv_std_logic_vector(828504,20);
WHEN "010001001" => data <= conv_std_logic_vector(827227,20);
WHEN "010001010" => data <= conv_std_logic_vector(825955,20);
WHEN "010001011" => data <= conv_std_logic_vector(824686,20);
WHEN "010001100" => data <= conv_std_logic_vector(823421,20);
WHEN "010001101" => data <= conv_std_logic_vector(822160,20);
WHEN "010001110" => data <= conv_std_logic_vector(820903,20);
WHEN "010001111" => data <= conv_std_logic_vector(819650,20);
WHEN "010010000" => data <= conv_std_logic_vector(818400,20);
WHEN "010010001" => data <= conv_std_logic_vector(817155,20);
WHEN "010010010" => data <= conv_std_logic_vector(815913,20);
WHEN "010010011" => data <= conv_std_logic_vector(814675,20);
WHEN "010010100" => data <= conv_std_logic_vector(813440,20);
WHEN "010010101" => data <= conv_std_logic_vector(812210,20);
WHEN "010010110" => data <= conv_std_logic_vector(810983,20);
WHEN "010010111" => data <= conv_std_logic_vector(809760,20);
WHEN "010011000" => data <= conv_std_logic_vector(808540,20);
WHEN "010011001" => data <= conv_std_logic_vector(807324,20);
WHEN "010011010" => data <= conv_std_logic_vector(806112,20);
WHEN "010011011" => data <= conv_std_logic_vector(804903,20);
WHEN "010011100" => data <= conv_std_logic_vector(803699,20);
WHEN "010011101" => data <= conv_std_logic_vector(802497,20);
WHEN "010011110" => data <= conv_std_logic_vector(801299,20);
WHEN "010011111" => data <= conv_std_logic_vector(800105,20);
WHEN "010100000" => data <= conv_std_logic_vector(798915,20);
WHEN "010100001" => data <= conv_std_logic_vector(797728,20);
WHEN "010100010" => data <= conv_std_logic_vector(796544,20);
WHEN "010100011" => data <= conv_std_logic_vector(795364,20);
WHEN "010100100" => data <= conv_std_logic_vector(794187,20);
WHEN "010100101" => data <= conv_std_logic_vector(793014,20);
WHEN "010100110" => data <= conv_std_logic_vector(791845,20);
WHEN "010100111" => data <= conv_std_logic_vector(790678,20);
WHEN "010101000" => data <= conv_std_logic_vector(789516,20);
WHEN "010101001" => data <= conv_std_logic_vector(788356,20);
WHEN "010101010" => data <= conv_std_logic_vector(787200,20);
WHEN "010101011" => data <= conv_std_logic_vector(786048,20);
WHEN "010101100" => data <= conv_std_logic_vector(784899,20);
WHEN "010101101" => data <= conv_std_logic_vector(783753,20);
WHEN "010101110" => data <= conv_std_logic_vector(782610,20);
WHEN "010101111" => data <= conv_std_logic_vector(781471,20);
WHEN "010110000" => data <= conv_std_logic_vector(780335,20);
WHEN "010110001" => data <= conv_std_logic_vector(779203,20);
WHEN "010110010" => data <= conv_std_logic_vector(778073,20);
WHEN "010110011" => data <= conv_std_logic_vector(776947,20);
WHEN "010110100" => data <= conv_std_logic_vector(775825,20);
WHEN "010110101" => data <= conv_std_logic_vector(774705,20);
WHEN "010110110" => data <= conv_std_logic_vector(773589,20);
WHEN "010110111" => data <= conv_std_logic_vector(772476,20);
WHEN "010111000" => data <= conv_std_logic_vector(771366,20);
WHEN "010111001" => data <= conv_std_logic_vector(770259,20);
WHEN "010111010" => data <= conv_std_logic_vector(769156,20);
WHEN "010111011" => data <= conv_std_logic_vector(768055,20);
WHEN "010111100" => data <= conv_std_logic_vector(766958,20);
WHEN "010111101" => data <= conv_std_logic_vector(765864,20);
WHEN "010111110" => data <= conv_std_logic_vector(764773,20);
WHEN "010111111" => data <= conv_std_logic_vector(763685,20);
WHEN "011000000" => data <= conv_std_logic_vector(762600,20);
WHEN "011000001" => data <= conv_std_logic_vector(761519,20);
WHEN "011000010" => data <= conv_std_logic_vector(760440,20);
WHEN "011000011" => data <= conv_std_logic_vector(759364,20);
WHEN "011000100" => data <= conv_std_logic_vector(758292,20);
WHEN "011000101" => data <= conv_std_logic_vector(757222,20);
WHEN "011000110" => data <= conv_std_logic_vector(756156,20);
WHEN "011000111" => data <= conv_std_logic_vector(755092,20);
WHEN "011001000" => data <= conv_std_logic_vector(754032,20);
WHEN "011001001" => data <= conv_std_logic_vector(752974,20);
WHEN "011001010" => data <= conv_std_logic_vector(751920,20);
WHEN "011001011" => data <= conv_std_logic_vector(750868,20);
WHEN "011001100" => data <= conv_std_logic_vector(749819,20);
WHEN "011001101" => data <= conv_std_logic_vector(748774,20);
WHEN "011001110" => data <= conv_std_logic_vector(747731,20);
WHEN "011001111" => data <= conv_std_logic_vector(746691,20);
WHEN "011010000" => data <= conv_std_logic_vector(745654,20);
WHEN "011010001" => data <= conv_std_logic_vector(744619,20);
WHEN "011010010" => data <= conv_std_logic_vector(743588,20);
WHEN "011010011" => data <= conv_std_logic_vector(742560,20);
WHEN "011010100" => data <= conv_std_logic_vector(741534,20);
WHEN "011010101" => data <= conv_std_logic_vector(740511,20);
WHEN "011010110" => data <= conv_std_logic_vector(739491,20);
WHEN "011010111" => data <= conv_std_logic_vector(738474,20);
WHEN "011011000" => data <= conv_std_logic_vector(737460,20);
WHEN "011011001" => data <= conv_std_logic_vector(736448,20);
WHEN "011011010" => data <= conv_std_logic_vector(735439,20);
WHEN "011011011" => data <= conv_std_logic_vector(734433,20);
WHEN "011011100" => data <= conv_std_logic_vector(733430,20);
WHEN "011011101" => data <= conv_std_logic_vector(732429,20);
WHEN "011011110" => data <= conv_std_logic_vector(731431,20);
WHEN "011011111" => data <= conv_std_logic_vector(730436,20);
WHEN "011100000" => data <= conv_std_logic_vector(729444,20);
WHEN "011100001" => data <= conv_std_logic_vector(728454,20);
WHEN "011100010" => data <= conv_std_logic_vector(727467,20);
WHEN "011100011" => data <= conv_std_logic_vector(726483,20);
WHEN "011100100" => data <= conv_std_logic_vector(725501,20);
WHEN "011100101" => data <= conv_std_logic_vector(724522,20);
WHEN "011100110" => data <= conv_std_logic_vector(723545,20);
WHEN "011100111" => data <= conv_std_logic_vector(722572,20);
WHEN "011101000" => data <= conv_std_logic_vector(721600,20);
WHEN "011101001" => data <= conv_std_logic_vector(720632,20);
WHEN "011101010" => data <= conv_std_logic_vector(719666,20);
WHEN "011101011" => data <= conv_std_logic_vector(718702,20);
WHEN "011101100" => data <= conv_std_logic_vector(717742,20);
WHEN "011101101" => data <= conv_std_logic_vector(716783,20);
WHEN "011101110" => data <= conv_std_logic_vector(715828,20);
WHEN "011101111" => data <= conv_std_logic_vector(714874,20);
WHEN "011110000" => data <= conv_std_logic_vector(713924,20);
WHEN "011110001" => data <= conv_std_logic_vector(712976,20);
WHEN "011110010" => data <= conv_std_logic_vector(712030,20);
WHEN "011110011" => data <= conv_std_logic_vector(711087,20);
WHEN "011110100" => data <= conv_std_logic_vector(710146,20);
WHEN "011110101" => data <= conv_std_logic_vector(709208,20);
WHEN "011110110" => data <= conv_std_logic_vector(708273,20);
WHEN "011110111" => data <= conv_std_logic_vector(707339,20);
WHEN "011111000" => data <= conv_std_logic_vector(706409,20);
WHEN "011111001" => data <= conv_std_logic_vector(705481,20);
WHEN "011111010" => data <= conv_std_logic_vector(704555,20);
WHEN "011111011" => data <= conv_std_logic_vector(703631,20);
WHEN "011111100" => data <= conv_std_logic_vector(702710,20);
WHEN "011111101" => data <= conv_std_logic_vector(701792,20);
WHEN "011111110" => data <= conv_std_logic_vector(700876,20);
WHEN "011111111" => data <= conv_std_logic_vector(699962,20);
WHEN "100000000" => data <= conv_std_logic_vector(699050,20);
WHEN "100000001" => data <= conv_std_logic_vector(698141,20);
WHEN "100000010" => data <= conv_std_logic_vector(697235,20);
WHEN "100000011" => data <= conv_std_logic_vector(696330,20);
WHEN "100000100" => data <= conv_std_logic_vector(695428,20);
WHEN "100000101" => data <= conv_std_logic_vector(694529,20);
WHEN "100000110" => data <= conv_std_logic_vector(693631,20);
WHEN "100000111" => data <= conv_std_logic_vector(692736,20);
WHEN "100001000" => data <= conv_std_logic_vector(691844,20);
WHEN "100001001" => data <= conv_std_logic_vector(690953,20);
WHEN "100001010" => data <= conv_std_logic_vector(690065,20);
WHEN "100001011" => data <= conv_std_logic_vector(689179,20);
WHEN "100001100" => data <= conv_std_logic_vector(688296,20);
WHEN "100001101" => data <= conv_std_logic_vector(687414,20);
WHEN "100001110" => data <= conv_std_logic_vector(686535,20);
WHEN "100001111" => data <= conv_std_logic_vector(685659,20);
WHEN "100010000" => data <= conv_std_logic_vector(684784,20);
WHEN "100010001" => data <= conv_std_logic_vector(683912,20);
WHEN "100010010" => data <= conv_std_logic_vector(683042,20);
WHEN "100010011" => data <= conv_std_logic_vector(682174,20);
WHEN "100010100" => data <= conv_std_logic_vector(681308,20);
WHEN "100010101" => data <= conv_std_logic_vector(680444,20);
WHEN "100010110" => data <= conv_std_logic_vector(679583,20);
WHEN "100010111" => data <= conv_std_logic_vector(678724,20);
WHEN "100011000" => data <= conv_std_logic_vector(677867,20);
WHEN "100011001" => data <= conv_std_logic_vector(677012,20);
WHEN "100011010" => data <= conv_std_logic_vector(676160,20);
WHEN "100011011" => data <= conv_std_logic_vector(675309,20);
WHEN "100011100" => data <= conv_std_logic_vector(674461,20);
WHEN "100011101" => data <= conv_std_logic_vector(673614,20);
WHEN "100011110" => data <= conv_std_logic_vector(672770,20);
WHEN "100011111" => data <= conv_std_logic_vector(671928,20);
WHEN "100100000" => data <= conv_std_logic_vector(671088,20);
WHEN "100100001" => data <= conv_std_logic_vector(670251,20);
WHEN "100100010" => data <= conv_std_logic_vector(669415,20);
WHEN "100100011" => data <= conv_std_logic_vector(668581,20);
WHEN "100100100" => data <= conv_std_logic_vector(667750,20);
WHEN "100100101" => data <= conv_std_logic_vector(666920,20);
WHEN "100100110" => data <= conv_std_logic_vector(666093,20);
WHEN "100100111" => data <= conv_std_logic_vector(665267,20);
WHEN "100101000" => data <= conv_std_logic_vector(664444,20);
WHEN "100101001" => data <= conv_std_logic_vector(663623,20);
WHEN "100101010" => data <= conv_std_logic_vector(662803,20);
WHEN "100101011" => data <= conv_std_logic_vector(661986,20);
WHEN "100101100" => data <= conv_std_logic_vector(661171,20);
WHEN "100101101" => data <= conv_std_logic_vector(660358,20);
WHEN "100101110" => data <= conv_std_logic_vector(659546,20);
WHEN "100101111" => data <= conv_std_logic_vector(658737,20);
WHEN "100110000" => data <= conv_std_logic_vector(657930,20);
WHEN "100110001" => data <= conv_std_logic_vector(657124,20);
WHEN "100110010" => data <= conv_std_logic_vector(656321,20);
WHEN "100110011" => data <= conv_std_logic_vector(655520,20);
WHEN "100110100" => data <= conv_std_logic_vector(654720,20);
WHEN "100110101" => data <= conv_std_logic_vector(653923,20);
WHEN "100110110" => data <= conv_std_logic_vector(653127,20);
WHEN "100110111" => data <= conv_std_logic_vector(652334,20);
WHEN "100111000" => data <= conv_std_logic_vector(651542,20);
WHEN "100111001" => data <= conv_std_logic_vector(650752,20);
WHEN "100111010" => data <= conv_std_logic_vector(649965,20);
WHEN "100111011" => data <= conv_std_logic_vector(649179,20);
WHEN "100111100" => data <= conv_std_logic_vector(648395,20);
WHEN "100111101" => data <= conv_std_logic_vector(647612,20);
WHEN "100111110" => data <= conv_std_logic_vector(646832,20);
WHEN "100111111" => data <= conv_std_logic_vector(646054,20);
WHEN "101000000" => data <= conv_std_logic_vector(645277,20);
WHEN "101000001" => data <= conv_std_logic_vector(644503,20);
WHEN "101000010" => data <= conv_std_logic_vector(643730,20);
WHEN "101000011" => data <= conv_std_logic_vector(642959,20);
WHEN "101000100" => data <= conv_std_logic_vector(642190,20);
WHEN "101000101" => data <= conv_std_logic_vector(641423,20);
WHEN "101000110" => data <= conv_std_logic_vector(640657,20);
WHEN "101000111" => data <= conv_std_logic_vector(639894,20);
WHEN "101001000" => data <= conv_std_logic_vector(639132,20);
WHEN "101001001" => data <= conv_std_logic_vector(638372,20);
WHEN "101001010" => data <= conv_std_logic_vector(637614,20);
WHEN "101001011" => data <= conv_std_logic_vector(636857,20);
WHEN "101001100" => data <= conv_std_logic_vector(636103,20);
WHEN "101001101" => data <= conv_std_logic_vector(635350,20);
WHEN "101001110" => data <= conv_std_logic_vector(634599,20);
WHEN "101001111" => data <= conv_std_logic_vector(633850,20);
WHEN "101010000" => data <= conv_std_logic_vector(633102,20);
WHEN "101010001" => data <= conv_std_logic_vector(632357,20);
WHEN "101010010" => data <= conv_std_logic_vector(631613,20);
WHEN "101010011" => data <= conv_std_logic_vector(630870,20);
WHEN "101010100" => data <= conv_std_logic_vector(630130,20);
WHEN "101010101" => data <= conv_std_logic_vector(629391,20);
WHEN "101010110" => data <= conv_std_logic_vector(628654,20);
WHEN "101010111" => data <= conv_std_logic_vector(627919,20);
WHEN "101011000" => data <= conv_std_logic_vector(627185,20);
WHEN "101011001" => data <= conv_std_logic_vector(626454,20);
WHEN "101011010" => data <= conv_std_logic_vector(625723,20);
WHEN "101011011" => data <= conv_std_logic_vector(624995,20);
WHEN "101011100" => data <= conv_std_logic_vector(624268,20);
WHEN "101011101" => data <= conv_std_logic_vector(623543,20);
WHEN "101011110" => data <= conv_std_logic_vector(622820,20);
WHEN "101011111" => data <= conv_std_logic_vector(622098,20);
WHEN "101100000" => data <= conv_std_logic_vector(621378,20);
WHEN "101100001" => data <= conv_std_logic_vector(620660,20);
WHEN "101100010" => data <= conv_std_logic_vector(619943,20);
WHEN "101100011" => data <= conv_std_logic_vector(619228,20);
WHEN "101100100" => data <= conv_std_logic_vector(618515,20);
WHEN "101100101" => data <= conv_std_logic_vector(617803,20);
WHEN "101100110" => data <= conv_std_logic_vector(617093,20);
WHEN "101100111" => data <= conv_std_logic_vector(616384,20);
WHEN "101101000" => data <= conv_std_logic_vector(615677,20);
WHEN "101101001" => data <= conv_std_logic_vector(614972,20);
WHEN "101101010" => data <= conv_std_logic_vector(614269,20);
WHEN "101101011" => data <= conv_std_logic_vector(613567,20);
WHEN "101101100" => data <= conv_std_logic_vector(612866,20);
WHEN "101101101" => data <= conv_std_logic_vector(612167,20);
WHEN "101101110" => data <= conv_std_logic_vector(611470,20);
WHEN "101101111" => data <= conv_std_logic_vector(610774,20);
WHEN "101110000" => data <= conv_std_logic_vector(610080,20);
WHEN "101110001" => data <= conv_std_logic_vector(609388,20);
WHEN "101110010" => data <= conv_std_logic_vector(608697,20);
WHEN "101110011" => data <= conv_std_logic_vector(608008,20);
WHEN "101110100" => data <= conv_std_logic_vector(607320,20);
WHEN "101110101" => data <= conv_std_logic_vector(606634,20);
WHEN "101110110" => data <= conv_std_logic_vector(605949,20);
WHEN "101110111" => data <= conv_std_logic_vector(605266,20);
WHEN "101111000" => data <= conv_std_logic_vector(604584,20);
WHEN "101111001" => data <= conv_std_logic_vector(603904,20);
WHEN "101111010" => data <= conv_std_logic_vector(603226,20);
WHEN "101111011" => data <= conv_std_logic_vector(602549,20);
WHEN "101111100" => data <= conv_std_logic_vector(601873,20);
WHEN "101111101" => data <= conv_std_logic_vector(601199,20);
WHEN "101111110" => data <= conv_std_logic_vector(600527,20);
WHEN "101111111" => data <= conv_std_logic_vector(599856,20);
WHEN "110000000" => data <= conv_std_logic_vector(599186,20);
WHEN "110000001" => data <= conv_std_logic_vector(598518,20);
WHEN "110000010" => data <= conv_std_logic_vector(597852,20);
WHEN "110000011" => data <= conv_std_logic_vector(597187,20);
WHEN "110000100" => data <= conv_std_logic_vector(596523,20);
WHEN "110000101" => data <= conv_std_logic_vector(595861,20);
WHEN "110000110" => data <= conv_std_logic_vector(595200,20);
WHEN "110000111" => data <= conv_std_logic_vector(594541,20);
WHEN "110001000" => data <= conv_std_logic_vector(593884,20);
WHEN "110001001" => data <= conv_std_logic_vector(593227,20);
WHEN "110001010" => data <= conv_std_logic_vector(592573,20);
WHEN "110001011" => data <= conv_std_logic_vector(591919,20);
WHEN "110001100" => data <= conv_std_logic_vector(591267,20);
WHEN "110001101" => data <= conv_std_logic_vector(590617,20);
WHEN "110001110" => data <= conv_std_logic_vector(589968,20);
WHEN "110001111" => data <= conv_std_logic_vector(589320,20);
WHEN "110010000" => data <= conv_std_logic_vector(588674,20);
WHEN "110010001" => data <= conv_std_logic_vector(588029,20);
WHEN "110010010" => data <= conv_std_logic_vector(587386,20);
WHEN "110010011" => data <= conv_std_logic_vector(586744,20);
WHEN "110010100" => data <= conv_std_logic_vector(586103,20);
WHEN "110010101" => data <= conv_std_logic_vector(585464,20);
WHEN "110010110" => data <= conv_std_logic_vector(584827,20);
WHEN "110010111" => data <= conv_std_logic_vector(584190,20);
WHEN "110011000" => data <= conv_std_logic_vector(583555,20);
WHEN "110011001" => data <= conv_std_logic_vector(582922,20);
WHEN "110011010" => data <= conv_std_logic_vector(582289,20);
WHEN "110011011" => data <= conv_std_logic_vector(581658,20);
WHEN "110011100" => data <= conv_std_logic_vector(581029,20);
WHEN "110011101" => data <= conv_std_logic_vector(580401,20);
WHEN "110011110" => data <= conv_std_logic_vector(579774,20);
WHEN "110011111" => data <= conv_std_logic_vector(579149,20);
WHEN "110100000" => data <= conv_std_logic_vector(578525,20);
WHEN "110100001" => data <= conv_std_logic_vector(577902,20);
WHEN "110100010" => data <= conv_std_logic_vector(577280,20);
WHEN "110100011" => data <= conv_std_logic_vector(576660,20);
WHEN "110100100" => data <= conv_std_logic_vector(576042,20);
WHEN "110100101" => data <= conv_std_logic_vector(575424,20);
WHEN "110100110" => data <= conv_std_logic_vector(574808,20);
WHEN "110100111" => data <= conv_std_logic_vector(574193,20);
WHEN "110101000" => data <= conv_std_logic_vector(573580,20);
WHEN "110101001" => data <= conv_std_logic_vector(572968,20);
WHEN "110101010" => data <= conv_std_logic_vector(572357,20);
WHEN "110101011" => data <= conv_std_logic_vector(571747,20);
WHEN "110101100" => data <= conv_std_logic_vector(571139,20);
WHEN "110101101" => data <= conv_std_logic_vector(570532,20);
WHEN "110101110" => data <= conv_std_logic_vector(569926,20);
WHEN "110101111" => data <= conv_std_logic_vector(569322,20);
WHEN "110110000" => data <= conv_std_logic_vector(568719,20);
WHEN "110110001" => data <= conv_std_logic_vector(568117,20);
WHEN "110110010" => data <= conv_std_logic_vector(567517,20);
WHEN "110110011" => data <= conv_std_logic_vector(566917,20);
WHEN "110110100" => data <= conv_std_logic_vector(566319,20);
WHEN "110110101" => data <= conv_std_logic_vector(565723,20);
WHEN "110110110" => data <= conv_std_logic_vector(565127,20);
WHEN "110110111" => data <= conv_std_logic_vector(564533,20);
WHEN "110111000" => data <= conv_std_logic_vector(563940,20);
WHEN "110111001" => data <= conv_std_logic_vector(563348,20);
WHEN "110111010" => data <= conv_std_logic_vector(562758,20);
WHEN "110111011" => data <= conv_std_logic_vector(562168,20);
WHEN "110111100" => data <= conv_std_logic_vector(561580,20);
WHEN "110111101" => data <= conv_std_logic_vector(560993,20);
WHEN "110111110" => data <= conv_std_logic_vector(560408,20);
WHEN "110111111" => data <= conv_std_logic_vector(559824,20);
WHEN "111000000" => data <= conv_std_logic_vector(559240,20);
WHEN "111000001" => data <= conv_std_logic_vector(558658,20);
WHEN "111000010" => data <= conv_std_logic_vector(558078,20);
WHEN "111000011" => data <= conv_std_logic_vector(557498,20);
WHEN "111000100" => data <= conv_std_logic_vector(556920,20);
WHEN "111000101" => data <= conv_std_logic_vector(556343,20);
WHEN "111000110" => data <= conv_std_logic_vector(555767,20);
WHEN "111000111" => data <= conv_std_logic_vector(555192,20);
WHEN "111001000" => data <= conv_std_logic_vector(554619,20);
WHEN "111001001" => data <= conv_std_logic_vector(554046,20);
WHEN "111001010" => data <= conv_std_logic_vector(553475,20);
WHEN "111001011" => data <= conv_std_logic_vector(552905,20);
WHEN "111001100" => data <= conv_std_logic_vector(552336,20);
WHEN "111001101" => data <= conv_std_logic_vector(551769,20);
WHEN "111001110" => data <= conv_std_logic_vector(551202,20);
WHEN "111001111" => data <= conv_std_logic_vector(550637,20);
WHEN "111010000" => data <= conv_std_logic_vector(550073,20);
WHEN "111010001" => data <= conv_std_logic_vector(549509,20);
WHEN "111010010" => data <= conv_std_logic_vector(548948,20);
WHEN "111010011" => data <= conv_std_logic_vector(548387,20);
WHEN "111010100" => data <= conv_std_logic_vector(547827,20);
WHEN "111010101" => data <= conv_std_logic_vector(547269,20);
WHEN "111010110" => data <= conv_std_logic_vector(546712,20);
WHEN "111010111" => data <= conv_std_logic_vector(546155,20);
WHEN "111011000" => data <= conv_std_logic_vector(545600,20);
WHEN "111011001" => data <= conv_std_logic_vector(545046,20);
WHEN "111011010" => data <= conv_std_logic_vector(544494,20);
WHEN "111011011" => data <= conv_std_logic_vector(543942,20);
WHEN "111011100" => data <= conv_std_logic_vector(543391,20);
WHEN "111011101" => data <= conv_std_logic_vector(542842,20);
WHEN "111011110" => data <= conv_std_logic_vector(542294,20);
WHEN "111011111" => data <= conv_std_logic_vector(541746,20);
WHEN "111100000" => data <= conv_std_logic_vector(541200,20);
WHEN "111100001" => data <= conv_std_logic_vector(540655,20);
WHEN "111100010" => data <= conv_std_logic_vector(540111,20);
WHEN "111100011" => data <= conv_std_logic_vector(539569,20);
WHEN "111100100" => data <= conv_std_logic_vector(539027,20);
WHEN "111100101" => data <= conv_std_logic_vector(538486,20);
WHEN "111100110" => data <= conv_std_logic_vector(537947,20);
WHEN "111100111" => data <= conv_std_logic_vector(537408,20);
WHEN "111101000" => data <= conv_std_logic_vector(536871,20);
WHEN "111101001" => data <= conv_std_logic_vector(536334,20);
WHEN "111101010" => data <= conv_std_logic_vector(535799,20);
WHEN "111101011" => data <= conv_std_logic_vector(535265,20);
WHEN "111101100" => data <= conv_std_logic_vector(534732,20);
WHEN "111101101" => data <= conv_std_logic_vector(534200,20);
WHEN "111101110" => data <= conv_std_logic_vector(533669,20);
WHEN "111101111" => data <= conv_std_logic_vector(533139,20);
WHEN "111110000" => data <= conv_std_logic_vector(532610,20);
WHEN "111110001" => data <= conv_std_logic_vector(532082,20);
WHEN "111110010" => data <= conv_std_logic_vector(531555,20);
WHEN "111110011" => data <= conv_std_logic_vector(531029,20);
WHEN "111110100" => data <= conv_std_logic_vector(530505,20);
WHEN "111110101" => data <= conv_std_logic_vector(529981,20);
WHEN "111110110" => data <= conv_std_logic_vector(529458,20);
WHEN "111110111" => data <= conv_std_logic_vector(528937,20);
WHEN "111111000" => data <= conv_std_logic_vector(528416,20);
WHEN "111111001" => data <= conv_std_logic_vector(527897,20);
WHEN "111111010" => data <= conv_std_logic_vector(527378,20);
WHEN "111111011" => data <= conv_std_logic_vector(526860,20);
WHEN "111111100" => data <= conv_std_logic_vector(526344,20);
WHEN "111111101" => data <= conv_std_logic_vector(525828,20);
WHEN "111111110" => data <= conv_std_logic_vector(525314,20);
WHEN "111111111" => data <= conv_std_logic_vector(524800,20);
WHEN others => data <= conv_std_logic_vector(0,20);
END CASE;
END PROCESS;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_DIV_LUT0.VHD ***
--*** ***
--*** Function: Look Up Table - Inverse ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_div_lut0 IS
PORT (
add : IN STD_LOGIC_VECTOR (9 DOWNTO 1);
data : OUT STD_LOGIC_VECTOR (20 DOWNTO 1)
);
END fp_div_lut0;
ARCHITECTURE rtl OF fp_div_lut0 IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "000000000" => data <= conv_std_logic_vector(1048575,20);
WHEN "000000001" => data <= conv_std_logic_vector(1046531,20);
WHEN "000000010" => data <= conv_std_logic_vector(1044495,20);
WHEN "000000011" => data <= conv_std_logic_vector(1042467,20);
WHEN "000000100" => data <= conv_std_logic_vector(1040447,20);
WHEN "000000101" => data <= conv_std_logic_vector(1038434,20);
WHEN "000000110" => data <= conv_std_logic_vector(1036429,20);
WHEN "000000111" => data <= conv_std_logic_vector(1034432,20);
WHEN "000001000" => data <= conv_std_logic_vector(1032443,20);
WHEN "000001001" => data <= conv_std_logic_vector(1030461,20);
WHEN "000001010" => data <= conv_std_logic_vector(1028487,20);
WHEN "000001011" => data <= conv_std_logic_vector(1026521,20);
WHEN "000001100" => data <= conv_std_logic_vector(1024562,20);
WHEN "000001101" => data <= conv_std_logic_vector(1022610,20);
WHEN "000001110" => data <= conv_std_logic_vector(1020666,20);
WHEN "000001111" => data <= conv_std_logic_vector(1018729,20);
WHEN "000010000" => data <= conv_std_logic_vector(1016800,20);
WHEN "000010001" => data <= conv_std_logic_vector(1014878,20);
WHEN "000010010" => data <= conv_std_logic_vector(1012963,20);
WHEN "000010011" => data <= conv_std_logic_vector(1011055,20);
WHEN "000010100" => data <= conv_std_logic_vector(1009155,20);
WHEN "000010101" => data <= conv_std_logic_vector(1007262,20);
WHEN "000010110" => data <= conv_std_logic_vector(1005375,20);
WHEN "000010111" => data <= conv_std_logic_vector(1003496,20);
WHEN "000011000" => data <= conv_std_logic_vector(1001624,20);
WHEN "000011001" => data <= conv_std_logic_vector(999759,20);
WHEN "000011010" => data <= conv_std_logic_vector(997900,20);
WHEN "000011011" => data <= conv_std_logic_vector(996049,20);
WHEN "000011100" => data <= conv_std_logic_vector(994205,20);
WHEN "000011101" => data <= conv_std_logic_vector(992367,20);
WHEN "000011110" => data <= conv_std_logic_vector(990536,20);
WHEN "000011111" => data <= conv_std_logic_vector(988712,20);
WHEN "000100000" => data <= conv_std_logic_vector(986894,20);
WHEN "000100001" => data <= conv_std_logic_vector(985083,20);
WHEN "000100010" => data <= conv_std_logic_vector(983279,20);
WHEN "000100011" => data <= conv_std_logic_vector(981482,20);
WHEN "000100100" => data <= conv_std_logic_vector(979691,20);
WHEN "000100101" => data <= conv_std_logic_vector(977906,20);
WHEN "000100110" => data <= conv_std_logic_vector(976128,20);
WHEN "000100111" => data <= conv_std_logic_vector(974357,20);
WHEN "000101000" => data <= conv_std_logic_vector(972591,20);
WHEN "000101001" => data <= conv_std_logic_vector(970833,20);
WHEN "000101010" => data <= conv_std_logic_vector(969080,20);
WHEN "000101011" => data <= conv_std_logic_vector(967334,20);
WHEN "000101100" => data <= conv_std_logic_vector(965594,20);
WHEN "000101101" => data <= conv_std_logic_vector(963861,20);
WHEN "000101110" => data <= conv_std_logic_vector(962133,20);
WHEN "000101111" => data <= conv_std_logic_vector(960412,20);
WHEN "000110000" => data <= conv_std_logic_vector(958697,20);
WHEN "000110001" => data <= conv_std_logic_vector(956988,20);
WHEN "000110010" => data <= conv_std_logic_vector(955286,20);
WHEN "000110011" => data <= conv_std_logic_vector(953589,20);
WHEN "000110100" => data <= conv_std_logic_vector(951898,20);
WHEN "000110101" => data <= conv_std_logic_vector(950213,20);
WHEN "000110110" => data <= conv_std_logic_vector(948534,20);
WHEN "000110111" => data <= conv_std_logic_vector(946862,20);
WHEN "000111000" => data <= conv_std_logic_vector(945195,20);
WHEN "000111001" => data <= conv_std_logic_vector(943533,20);
WHEN "000111010" => data <= conv_std_logic_vector(941878,20);
WHEN "000111011" => data <= conv_std_logic_vector(940229,20);
WHEN "000111100" => data <= conv_std_logic_vector(938585,20);
WHEN "000111101" => data <= conv_std_logic_vector(936947,20);
WHEN "000111110" => data <= conv_std_logic_vector(935314,20);
WHEN "000111111" => data <= conv_std_logic_vector(933688,20);
WHEN "001000000" => data <= conv_std_logic_vector(932067,20);
WHEN "001000001" => data <= conv_std_logic_vector(930451,20);
WHEN "001000010" => data <= conv_std_logic_vector(928842,20);
WHEN "001000011" => data <= conv_std_logic_vector(927237,20);
WHEN "001000100" => data <= conv_std_logic_vector(925639,20);
WHEN "001000101" => data <= conv_std_logic_vector(924046,20);
WHEN "001000110" => data <= conv_std_logic_vector(922458,20);
WHEN "001000111" => data <= conv_std_logic_vector(920876,20);
WHEN "001001000" => data <= conv_std_logic_vector(919299,20);
WHEN "001001001" => data <= conv_std_logic_vector(917727,20);
WHEN "001001010" => data <= conv_std_logic_vector(916161,20);
WHEN "001001011" => data <= conv_std_logic_vector(914601,20);
WHEN "001001100" => data <= conv_std_logic_vector(913045,20);
WHEN "001001101" => data <= conv_std_logic_vector(911495,20);
WHEN "001001110" => data <= conv_std_logic_vector(909950,20);
WHEN "001001111" => data <= conv_std_logic_vector(908410,20);
WHEN "001010000" => data <= conv_std_logic_vector(906876,20);
WHEN "001010001" => data <= conv_std_logic_vector(905347,20);
WHEN "001010010" => data <= conv_std_logic_vector(903822,20);
WHEN "001010011" => data <= conv_std_logic_vector(902303,20);
WHEN "001010100" => data <= conv_std_logic_vector(900789,20);
WHEN "001010101" => data <= conv_std_logic_vector(899281,20);
WHEN "001010110" => data <= conv_std_logic_vector(897777,20);
WHEN "001010111" => data <= conv_std_logic_vector(896278,20);
WHEN "001011000" => data <= conv_std_logic_vector(894784,20);
WHEN "001011001" => data <= conv_std_logic_vector(893295,20);
WHEN "001011010" => data <= conv_std_logic_vector(891812,20);
WHEN "001011011" => data <= conv_std_logic_vector(890333,20);
WHEN "001011100" => data <= conv_std_logic_vector(888859,20);
WHEN "001011101" => data <= conv_std_logic_vector(887389,20);
WHEN "001011110" => data <= conv_std_logic_vector(885925,20);
WHEN "001011111" => data <= conv_std_logic_vector(884465,20);
WHEN "001100000" => data <= conv_std_logic_vector(883011,20);
WHEN "001100001" => data <= conv_std_logic_vector(881561,20);
WHEN "001100010" => data <= conv_std_logic_vector(880116,20);
WHEN "001100011" => data <= conv_std_logic_vector(878675,20);
WHEN "001100100" => data <= conv_std_logic_vector(877239,20);
WHEN "001100101" => data <= conv_std_logic_vector(875808,20);
WHEN "001100110" => data <= conv_std_logic_vector(874382,20);
WHEN "001100111" => data <= conv_std_logic_vector(872960,20);
WHEN "001101000" => data <= conv_std_logic_vector(871543,20);
WHEN "001101001" => data <= conv_std_logic_vector(870131,20);
WHEN "001101010" => data <= conv_std_logic_vector(868723,20);
WHEN "001101011" => data <= conv_std_logic_vector(867319,20);
WHEN "001101100" => data <= conv_std_logic_vector(865920,20);
WHEN "001101101" => data <= conv_std_logic_vector(864526,20);
WHEN "001101110" => data <= conv_std_logic_vector(863136,20);
WHEN "001101111" => data <= conv_std_logic_vector(861751,20);
WHEN "001110000" => data <= conv_std_logic_vector(860369,20);
WHEN "001110001" => data <= conv_std_logic_vector(858993,20);
WHEN "001110010" => data <= conv_std_logic_vector(857621,20);
WHEN "001110011" => data <= conv_std_logic_vector(856253,20);
WHEN "001110100" => data <= conv_std_logic_vector(854889,20);
WHEN "001110101" => data <= conv_std_logic_vector(853530,20);
WHEN "001110110" => data <= conv_std_logic_vector(852176,20);
WHEN "001110111" => data <= conv_std_logic_vector(850825,20);
WHEN "001111000" => data <= conv_std_logic_vector(849479,20);
WHEN "001111001" => data <= conv_std_logic_vector(848137,20);
WHEN "001111010" => data <= conv_std_logic_vector(846799,20);
WHEN "001111011" => data <= conv_std_logic_vector(845465,20);
WHEN "001111100" => data <= conv_std_logic_vector(844136,20);
WHEN "001111101" => data <= conv_std_logic_vector(842811,20);
WHEN "001111110" => data <= conv_std_logic_vector(841490,20);
WHEN "001111111" => data <= conv_std_logic_vector(840173,20);
WHEN "010000000" => data <= conv_std_logic_vector(838860,20);
WHEN "010000001" => data <= conv_std_logic_vector(837552,20);
WHEN "010000010" => data <= conv_std_logic_vector(836247,20);
WHEN "010000011" => data <= conv_std_logic_vector(834946,20);
WHEN "010000100" => data <= conv_std_logic_vector(833650,20);
WHEN "010000101" => data <= conv_std_logic_vector(832358,20);
WHEN "010000110" => data <= conv_std_logic_vector(831069,20);
WHEN "010000111" => data <= conv_std_logic_vector(829785,20);
WHEN "010001000" => data <= conv_std_logic_vector(828504,20);
WHEN "010001001" => data <= conv_std_logic_vector(827227,20);
WHEN "010001010" => data <= conv_std_logic_vector(825955,20);
WHEN "010001011" => data <= conv_std_logic_vector(824686,20);
WHEN "010001100" => data <= conv_std_logic_vector(823421,20);
WHEN "010001101" => data <= conv_std_logic_vector(822160,20);
WHEN "010001110" => data <= conv_std_logic_vector(820903,20);
WHEN "010001111" => data <= conv_std_logic_vector(819650,20);
WHEN "010010000" => data <= conv_std_logic_vector(818400,20);
WHEN "010010001" => data <= conv_std_logic_vector(817155,20);
WHEN "010010010" => data <= conv_std_logic_vector(815913,20);
WHEN "010010011" => data <= conv_std_logic_vector(814675,20);
WHEN "010010100" => data <= conv_std_logic_vector(813440,20);
WHEN "010010101" => data <= conv_std_logic_vector(812210,20);
WHEN "010010110" => data <= conv_std_logic_vector(810983,20);
WHEN "010010111" => data <= conv_std_logic_vector(809760,20);
WHEN "010011000" => data <= conv_std_logic_vector(808540,20);
WHEN "010011001" => data <= conv_std_logic_vector(807324,20);
WHEN "010011010" => data <= conv_std_logic_vector(806112,20);
WHEN "010011011" => data <= conv_std_logic_vector(804903,20);
WHEN "010011100" => data <= conv_std_logic_vector(803699,20);
WHEN "010011101" => data <= conv_std_logic_vector(802497,20);
WHEN "010011110" => data <= conv_std_logic_vector(801299,20);
WHEN "010011111" => data <= conv_std_logic_vector(800105,20);
WHEN "010100000" => data <= conv_std_logic_vector(798915,20);
WHEN "010100001" => data <= conv_std_logic_vector(797728,20);
WHEN "010100010" => data <= conv_std_logic_vector(796544,20);
WHEN "010100011" => data <= conv_std_logic_vector(795364,20);
WHEN "010100100" => data <= conv_std_logic_vector(794187,20);
WHEN "010100101" => data <= conv_std_logic_vector(793014,20);
WHEN "010100110" => data <= conv_std_logic_vector(791845,20);
WHEN "010100111" => data <= conv_std_logic_vector(790678,20);
WHEN "010101000" => data <= conv_std_logic_vector(789516,20);
WHEN "010101001" => data <= conv_std_logic_vector(788356,20);
WHEN "010101010" => data <= conv_std_logic_vector(787200,20);
WHEN "010101011" => data <= conv_std_logic_vector(786048,20);
WHEN "010101100" => data <= conv_std_logic_vector(784899,20);
WHEN "010101101" => data <= conv_std_logic_vector(783753,20);
WHEN "010101110" => data <= conv_std_logic_vector(782610,20);
WHEN "010101111" => data <= conv_std_logic_vector(781471,20);
WHEN "010110000" => data <= conv_std_logic_vector(780335,20);
WHEN "010110001" => data <= conv_std_logic_vector(779203,20);
WHEN "010110010" => data <= conv_std_logic_vector(778073,20);
WHEN "010110011" => data <= conv_std_logic_vector(776947,20);
WHEN "010110100" => data <= conv_std_logic_vector(775825,20);
WHEN "010110101" => data <= conv_std_logic_vector(774705,20);
WHEN "010110110" => data <= conv_std_logic_vector(773589,20);
WHEN "010110111" => data <= conv_std_logic_vector(772476,20);
WHEN "010111000" => data <= conv_std_logic_vector(771366,20);
WHEN "010111001" => data <= conv_std_logic_vector(770259,20);
WHEN "010111010" => data <= conv_std_logic_vector(769156,20);
WHEN "010111011" => data <= conv_std_logic_vector(768055,20);
WHEN "010111100" => data <= conv_std_logic_vector(766958,20);
WHEN "010111101" => data <= conv_std_logic_vector(765864,20);
WHEN "010111110" => data <= conv_std_logic_vector(764773,20);
WHEN "010111111" => data <= conv_std_logic_vector(763685,20);
WHEN "011000000" => data <= conv_std_logic_vector(762600,20);
WHEN "011000001" => data <= conv_std_logic_vector(761519,20);
WHEN "011000010" => data <= conv_std_logic_vector(760440,20);
WHEN "011000011" => data <= conv_std_logic_vector(759364,20);
WHEN "011000100" => data <= conv_std_logic_vector(758292,20);
WHEN "011000101" => data <= conv_std_logic_vector(757222,20);
WHEN "011000110" => data <= conv_std_logic_vector(756156,20);
WHEN "011000111" => data <= conv_std_logic_vector(755092,20);
WHEN "011001000" => data <= conv_std_logic_vector(754032,20);
WHEN "011001001" => data <= conv_std_logic_vector(752974,20);
WHEN "011001010" => data <= conv_std_logic_vector(751920,20);
WHEN "011001011" => data <= conv_std_logic_vector(750868,20);
WHEN "011001100" => data <= conv_std_logic_vector(749819,20);
WHEN "011001101" => data <= conv_std_logic_vector(748774,20);
WHEN "011001110" => data <= conv_std_logic_vector(747731,20);
WHEN "011001111" => data <= conv_std_logic_vector(746691,20);
WHEN "011010000" => data <= conv_std_logic_vector(745654,20);
WHEN "011010001" => data <= conv_std_logic_vector(744619,20);
WHEN "011010010" => data <= conv_std_logic_vector(743588,20);
WHEN "011010011" => data <= conv_std_logic_vector(742560,20);
WHEN "011010100" => data <= conv_std_logic_vector(741534,20);
WHEN "011010101" => data <= conv_std_logic_vector(740511,20);
WHEN "011010110" => data <= conv_std_logic_vector(739491,20);
WHEN "011010111" => data <= conv_std_logic_vector(738474,20);
WHEN "011011000" => data <= conv_std_logic_vector(737460,20);
WHEN "011011001" => data <= conv_std_logic_vector(736448,20);
WHEN "011011010" => data <= conv_std_logic_vector(735439,20);
WHEN "011011011" => data <= conv_std_logic_vector(734433,20);
WHEN "011011100" => data <= conv_std_logic_vector(733430,20);
WHEN "011011101" => data <= conv_std_logic_vector(732429,20);
WHEN "011011110" => data <= conv_std_logic_vector(731431,20);
WHEN "011011111" => data <= conv_std_logic_vector(730436,20);
WHEN "011100000" => data <= conv_std_logic_vector(729444,20);
WHEN "011100001" => data <= conv_std_logic_vector(728454,20);
WHEN "011100010" => data <= conv_std_logic_vector(727467,20);
WHEN "011100011" => data <= conv_std_logic_vector(726483,20);
WHEN "011100100" => data <= conv_std_logic_vector(725501,20);
WHEN "011100101" => data <= conv_std_logic_vector(724522,20);
WHEN "011100110" => data <= conv_std_logic_vector(723545,20);
WHEN "011100111" => data <= conv_std_logic_vector(722572,20);
WHEN "011101000" => data <= conv_std_logic_vector(721600,20);
WHEN "011101001" => data <= conv_std_logic_vector(720632,20);
WHEN "011101010" => data <= conv_std_logic_vector(719666,20);
WHEN "011101011" => data <= conv_std_logic_vector(718702,20);
WHEN "011101100" => data <= conv_std_logic_vector(717742,20);
WHEN "011101101" => data <= conv_std_logic_vector(716783,20);
WHEN "011101110" => data <= conv_std_logic_vector(715828,20);
WHEN "011101111" => data <= conv_std_logic_vector(714874,20);
WHEN "011110000" => data <= conv_std_logic_vector(713924,20);
WHEN "011110001" => data <= conv_std_logic_vector(712976,20);
WHEN "011110010" => data <= conv_std_logic_vector(712030,20);
WHEN "011110011" => data <= conv_std_logic_vector(711087,20);
WHEN "011110100" => data <= conv_std_logic_vector(710146,20);
WHEN "011110101" => data <= conv_std_logic_vector(709208,20);
WHEN "011110110" => data <= conv_std_logic_vector(708273,20);
WHEN "011110111" => data <= conv_std_logic_vector(707339,20);
WHEN "011111000" => data <= conv_std_logic_vector(706409,20);
WHEN "011111001" => data <= conv_std_logic_vector(705481,20);
WHEN "011111010" => data <= conv_std_logic_vector(704555,20);
WHEN "011111011" => data <= conv_std_logic_vector(703631,20);
WHEN "011111100" => data <= conv_std_logic_vector(702710,20);
WHEN "011111101" => data <= conv_std_logic_vector(701792,20);
WHEN "011111110" => data <= conv_std_logic_vector(700876,20);
WHEN "011111111" => data <= conv_std_logic_vector(699962,20);
WHEN "100000000" => data <= conv_std_logic_vector(699050,20);
WHEN "100000001" => data <= conv_std_logic_vector(698141,20);
WHEN "100000010" => data <= conv_std_logic_vector(697235,20);
WHEN "100000011" => data <= conv_std_logic_vector(696330,20);
WHEN "100000100" => data <= conv_std_logic_vector(695428,20);
WHEN "100000101" => data <= conv_std_logic_vector(694529,20);
WHEN "100000110" => data <= conv_std_logic_vector(693631,20);
WHEN "100000111" => data <= conv_std_logic_vector(692736,20);
WHEN "100001000" => data <= conv_std_logic_vector(691844,20);
WHEN "100001001" => data <= conv_std_logic_vector(690953,20);
WHEN "100001010" => data <= conv_std_logic_vector(690065,20);
WHEN "100001011" => data <= conv_std_logic_vector(689179,20);
WHEN "100001100" => data <= conv_std_logic_vector(688296,20);
WHEN "100001101" => data <= conv_std_logic_vector(687414,20);
WHEN "100001110" => data <= conv_std_logic_vector(686535,20);
WHEN "100001111" => data <= conv_std_logic_vector(685659,20);
WHEN "100010000" => data <= conv_std_logic_vector(684784,20);
WHEN "100010001" => data <= conv_std_logic_vector(683912,20);
WHEN "100010010" => data <= conv_std_logic_vector(683042,20);
WHEN "100010011" => data <= conv_std_logic_vector(682174,20);
WHEN "100010100" => data <= conv_std_logic_vector(681308,20);
WHEN "100010101" => data <= conv_std_logic_vector(680444,20);
WHEN "100010110" => data <= conv_std_logic_vector(679583,20);
WHEN "100010111" => data <= conv_std_logic_vector(678724,20);
WHEN "100011000" => data <= conv_std_logic_vector(677867,20);
WHEN "100011001" => data <= conv_std_logic_vector(677012,20);
WHEN "100011010" => data <= conv_std_logic_vector(676160,20);
WHEN "100011011" => data <= conv_std_logic_vector(675309,20);
WHEN "100011100" => data <= conv_std_logic_vector(674461,20);
WHEN "100011101" => data <= conv_std_logic_vector(673614,20);
WHEN "100011110" => data <= conv_std_logic_vector(672770,20);
WHEN "100011111" => data <= conv_std_logic_vector(671928,20);
WHEN "100100000" => data <= conv_std_logic_vector(671088,20);
WHEN "100100001" => data <= conv_std_logic_vector(670251,20);
WHEN "100100010" => data <= conv_std_logic_vector(669415,20);
WHEN "100100011" => data <= conv_std_logic_vector(668581,20);
WHEN "100100100" => data <= conv_std_logic_vector(667750,20);
WHEN "100100101" => data <= conv_std_logic_vector(666920,20);
WHEN "100100110" => data <= conv_std_logic_vector(666093,20);
WHEN "100100111" => data <= conv_std_logic_vector(665267,20);
WHEN "100101000" => data <= conv_std_logic_vector(664444,20);
WHEN "100101001" => data <= conv_std_logic_vector(663623,20);
WHEN "100101010" => data <= conv_std_logic_vector(662803,20);
WHEN "100101011" => data <= conv_std_logic_vector(661986,20);
WHEN "100101100" => data <= conv_std_logic_vector(661171,20);
WHEN "100101101" => data <= conv_std_logic_vector(660358,20);
WHEN "100101110" => data <= conv_std_logic_vector(659546,20);
WHEN "100101111" => data <= conv_std_logic_vector(658737,20);
WHEN "100110000" => data <= conv_std_logic_vector(657930,20);
WHEN "100110001" => data <= conv_std_logic_vector(657124,20);
WHEN "100110010" => data <= conv_std_logic_vector(656321,20);
WHEN "100110011" => data <= conv_std_logic_vector(655520,20);
WHEN "100110100" => data <= conv_std_logic_vector(654720,20);
WHEN "100110101" => data <= conv_std_logic_vector(653923,20);
WHEN "100110110" => data <= conv_std_logic_vector(653127,20);
WHEN "100110111" => data <= conv_std_logic_vector(652334,20);
WHEN "100111000" => data <= conv_std_logic_vector(651542,20);
WHEN "100111001" => data <= conv_std_logic_vector(650752,20);
WHEN "100111010" => data <= conv_std_logic_vector(649965,20);
WHEN "100111011" => data <= conv_std_logic_vector(649179,20);
WHEN "100111100" => data <= conv_std_logic_vector(648395,20);
WHEN "100111101" => data <= conv_std_logic_vector(647612,20);
WHEN "100111110" => data <= conv_std_logic_vector(646832,20);
WHEN "100111111" => data <= conv_std_logic_vector(646054,20);
WHEN "101000000" => data <= conv_std_logic_vector(645277,20);
WHEN "101000001" => data <= conv_std_logic_vector(644503,20);
WHEN "101000010" => data <= conv_std_logic_vector(643730,20);
WHEN "101000011" => data <= conv_std_logic_vector(642959,20);
WHEN "101000100" => data <= conv_std_logic_vector(642190,20);
WHEN "101000101" => data <= conv_std_logic_vector(641423,20);
WHEN "101000110" => data <= conv_std_logic_vector(640657,20);
WHEN "101000111" => data <= conv_std_logic_vector(639894,20);
WHEN "101001000" => data <= conv_std_logic_vector(639132,20);
WHEN "101001001" => data <= conv_std_logic_vector(638372,20);
WHEN "101001010" => data <= conv_std_logic_vector(637614,20);
WHEN "101001011" => data <= conv_std_logic_vector(636857,20);
WHEN "101001100" => data <= conv_std_logic_vector(636103,20);
WHEN "101001101" => data <= conv_std_logic_vector(635350,20);
WHEN "101001110" => data <= conv_std_logic_vector(634599,20);
WHEN "101001111" => data <= conv_std_logic_vector(633850,20);
WHEN "101010000" => data <= conv_std_logic_vector(633102,20);
WHEN "101010001" => data <= conv_std_logic_vector(632357,20);
WHEN "101010010" => data <= conv_std_logic_vector(631613,20);
WHEN "101010011" => data <= conv_std_logic_vector(630870,20);
WHEN "101010100" => data <= conv_std_logic_vector(630130,20);
WHEN "101010101" => data <= conv_std_logic_vector(629391,20);
WHEN "101010110" => data <= conv_std_logic_vector(628654,20);
WHEN "101010111" => data <= conv_std_logic_vector(627919,20);
WHEN "101011000" => data <= conv_std_logic_vector(627185,20);
WHEN "101011001" => data <= conv_std_logic_vector(626454,20);
WHEN "101011010" => data <= conv_std_logic_vector(625723,20);
WHEN "101011011" => data <= conv_std_logic_vector(624995,20);
WHEN "101011100" => data <= conv_std_logic_vector(624268,20);
WHEN "101011101" => data <= conv_std_logic_vector(623543,20);
WHEN "101011110" => data <= conv_std_logic_vector(622820,20);
WHEN "101011111" => data <= conv_std_logic_vector(622098,20);
WHEN "101100000" => data <= conv_std_logic_vector(621378,20);
WHEN "101100001" => data <= conv_std_logic_vector(620660,20);
WHEN "101100010" => data <= conv_std_logic_vector(619943,20);
WHEN "101100011" => data <= conv_std_logic_vector(619228,20);
WHEN "101100100" => data <= conv_std_logic_vector(618515,20);
WHEN "101100101" => data <= conv_std_logic_vector(617803,20);
WHEN "101100110" => data <= conv_std_logic_vector(617093,20);
WHEN "101100111" => data <= conv_std_logic_vector(616384,20);
WHEN "101101000" => data <= conv_std_logic_vector(615677,20);
WHEN "101101001" => data <= conv_std_logic_vector(614972,20);
WHEN "101101010" => data <= conv_std_logic_vector(614269,20);
WHEN "101101011" => data <= conv_std_logic_vector(613567,20);
WHEN "101101100" => data <= conv_std_logic_vector(612866,20);
WHEN "101101101" => data <= conv_std_logic_vector(612167,20);
WHEN "101101110" => data <= conv_std_logic_vector(611470,20);
WHEN "101101111" => data <= conv_std_logic_vector(610774,20);
WHEN "101110000" => data <= conv_std_logic_vector(610080,20);
WHEN "101110001" => data <= conv_std_logic_vector(609388,20);
WHEN "101110010" => data <= conv_std_logic_vector(608697,20);
WHEN "101110011" => data <= conv_std_logic_vector(608008,20);
WHEN "101110100" => data <= conv_std_logic_vector(607320,20);
WHEN "101110101" => data <= conv_std_logic_vector(606634,20);
WHEN "101110110" => data <= conv_std_logic_vector(605949,20);
WHEN "101110111" => data <= conv_std_logic_vector(605266,20);
WHEN "101111000" => data <= conv_std_logic_vector(604584,20);
WHEN "101111001" => data <= conv_std_logic_vector(603904,20);
WHEN "101111010" => data <= conv_std_logic_vector(603226,20);
WHEN "101111011" => data <= conv_std_logic_vector(602549,20);
WHEN "101111100" => data <= conv_std_logic_vector(601873,20);
WHEN "101111101" => data <= conv_std_logic_vector(601199,20);
WHEN "101111110" => data <= conv_std_logic_vector(600527,20);
WHEN "101111111" => data <= conv_std_logic_vector(599856,20);
WHEN "110000000" => data <= conv_std_logic_vector(599186,20);
WHEN "110000001" => data <= conv_std_logic_vector(598518,20);
WHEN "110000010" => data <= conv_std_logic_vector(597852,20);
WHEN "110000011" => data <= conv_std_logic_vector(597187,20);
WHEN "110000100" => data <= conv_std_logic_vector(596523,20);
WHEN "110000101" => data <= conv_std_logic_vector(595861,20);
WHEN "110000110" => data <= conv_std_logic_vector(595200,20);
WHEN "110000111" => data <= conv_std_logic_vector(594541,20);
WHEN "110001000" => data <= conv_std_logic_vector(593884,20);
WHEN "110001001" => data <= conv_std_logic_vector(593227,20);
WHEN "110001010" => data <= conv_std_logic_vector(592573,20);
WHEN "110001011" => data <= conv_std_logic_vector(591919,20);
WHEN "110001100" => data <= conv_std_logic_vector(591267,20);
WHEN "110001101" => data <= conv_std_logic_vector(590617,20);
WHEN "110001110" => data <= conv_std_logic_vector(589968,20);
WHEN "110001111" => data <= conv_std_logic_vector(589320,20);
WHEN "110010000" => data <= conv_std_logic_vector(588674,20);
WHEN "110010001" => data <= conv_std_logic_vector(588029,20);
WHEN "110010010" => data <= conv_std_logic_vector(587386,20);
WHEN "110010011" => data <= conv_std_logic_vector(586744,20);
WHEN "110010100" => data <= conv_std_logic_vector(586103,20);
WHEN "110010101" => data <= conv_std_logic_vector(585464,20);
WHEN "110010110" => data <= conv_std_logic_vector(584827,20);
WHEN "110010111" => data <= conv_std_logic_vector(584190,20);
WHEN "110011000" => data <= conv_std_logic_vector(583555,20);
WHEN "110011001" => data <= conv_std_logic_vector(582922,20);
WHEN "110011010" => data <= conv_std_logic_vector(582289,20);
WHEN "110011011" => data <= conv_std_logic_vector(581658,20);
WHEN "110011100" => data <= conv_std_logic_vector(581029,20);
WHEN "110011101" => data <= conv_std_logic_vector(580401,20);
WHEN "110011110" => data <= conv_std_logic_vector(579774,20);
WHEN "110011111" => data <= conv_std_logic_vector(579149,20);
WHEN "110100000" => data <= conv_std_logic_vector(578525,20);
WHEN "110100001" => data <= conv_std_logic_vector(577902,20);
WHEN "110100010" => data <= conv_std_logic_vector(577280,20);
WHEN "110100011" => data <= conv_std_logic_vector(576660,20);
WHEN "110100100" => data <= conv_std_logic_vector(576042,20);
WHEN "110100101" => data <= conv_std_logic_vector(575424,20);
WHEN "110100110" => data <= conv_std_logic_vector(574808,20);
WHEN "110100111" => data <= conv_std_logic_vector(574193,20);
WHEN "110101000" => data <= conv_std_logic_vector(573580,20);
WHEN "110101001" => data <= conv_std_logic_vector(572968,20);
WHEN "110101010" => data <= conv_std_logic_vector(572357,20);
WHEN "110101011" => data <= conv_std_logic_vector(571747,20);
WHEN "110101100" => data <= conv_std_logic_vector(571139,20);
WHEN "110101101" => data <= conv_std_logic_vector(570532,20);
WHEN "110101110" => data <= conv_std_logic_vector(569926,20);
WHEN "110101111" => data <= conv_std_logic_vector(569322,20);
WHEN "110110000" => data <= conv_std_logic_vector(568719,20);
WHEN "110110001" => data <= conv_std_logic_vector(568117,20);
WHEN "110110010" => data <= conv_std_logic_vector(567517,20);
WHEN "110110011" => data <= conv_std_logic_vector(566917,20);
WHEN "110110100" => data <= conv_std_logic_vector(566319,20);
WHEN "110110101" => data <= conv_std_logic_vector(565723,20);
WHEN "110110110" => data <= conv_std_logic_vector(565127,20);
WHEN "110110111" => data <= conv_std_logic_vector(564533,20);
WHEN "110111000" => data <= conv_std_logic_vector(563940,20);
WHEN "110111001" => data <= conv_std_logic_vector(563348,20);
WHEN "110111010" => data <= conv_std_logic_vector(562758,20);
WHEN "110111011" => data <= conv_std_logic_vector(562168,20);
WHEN "110111100" => data <= conv_std_logic_vector(561580,20);
WHEN "110111101" => data <= conv_std_logic_vector(560993,20);
WHEN "110111110" => data <= conv_std_logic_vector(560408,20);
WHEN "110111111" => data <= conv_std_logic_vector(559824,20);
WHEN "111000000" => data <= conv_std_logic_vector(559240,20);
WHEN "111000001" => data <= conv_std_logic_vector(558658,20);
WHEN "111000010" => data <= conv_std_logic_vector(558078,20);
WHEN "111000011" => data <= conv_std_logic_vector(557498,20);
WHEN "111000100" => data <= conv_std_logic_vector(556920,20);
WHEN "111000101" => data <= conv_std_logic_vector(556343,20);
WHEN "111000110" => data <= conv_std_logic_vector(555767,20);
WHEN "111000111" => data <= conv_std_logic_vector(555192,20);
WHEN "111001000" => data <= conv_std_logic_vector(554619,20);
WHEN "111001001" => data <= conv_std_logic_vector(554046,20);
WHEN "111001010" => data <= conv_std_logic_vector(553475,20);
WHEN "111001011" => data <= conv_std_logic_vector(552905,20);
WHEN "111001100" => data <= conv_std_logic_vector(552336,20);
WHEN "111001101" => data <= conv_std_logic_vector(551769,20);
WHEN "111001110" => data <= conv_std_logic_vector(551202,20);
WHEN "111001111" => data <= conv_std_logic_vector(550637,20);
WHEN "111010000" => data <= conv_std_logic_vector(550073,20);
WHEN "111010001" => data <= conv_std_logic_vector(549509,20);
WHEN "111010010" => data <= conv_std_logic_vector(548948,20);
WHEN "111010011" => data <= conv_std_logic_vector(548387,20);
WHEN "111010100" => data <= conv_std_logic_vector(547827,20);
WHEN "111010101" => data <= conv_std_logic_vector(547269,20);
WHEN "111010110" => data <= conv_std_logic_vector(546712,20);
WHEN "111010111" => data <= conv_std_logic_vector(546155,20);
WHEN "111011000" => data <= conv_std_logic_vector(545600,20);
WHEN "111011001" => data <= conv_std_logic_vector(545046,20);
WHEN "111011010" => data <= conv_std_logic_vector(544494,20);
WHEN "111011011" => data <= conv_std_logic_vector(543942,20);
WHEN "111011100" => data <= conv_std_logic_vector(543391,20);
WHEN "111011101" => data <= conv_std_logic_vector(542842,20);
WHEN "111011110" => data <= conv_std_logic_vector(542294,20);
WHEN "111011111" => data <= conv_std_logic_vector(541746,20);
WHEN "111100000" => data <= conv_std_logic_vector(541200,20);
WHEN "111100001" => data <= conv_std_logic_vector(540655,20);
WHEN "111100010" => data <= conv_std_logic_vector(540111,20);
WHEN "111100011" => data <= conv_std_logic_vector(539569,20);
WHEN "111100100" => data <= conv_std_logic_vector(539027,20);
WHEN "111100101" => data <= conv_std_logic_vector(538486,20);
WHEN "111100110" => data <= conv_std_logic_vector(537947,20);
WHEN "111100111" => data <= conv_std_logic_vector(537408,20);
WHEN "111101000" => data <= conv_std_logic_vector(536871,20);
WHEN "111101001" => data <= conv_std_logic_vector(536334,20);
WHEN "111101010" => data <= conv_std_logic_vector(535799,20);
WHEN "111101011" => data <= conv_std_logic_vector(535265,20);
WHEN "111101100" => data <= conv_std_logic_vector(534732,20);
WHEN "111101101" => data <= conv_std_logic_vector(534200,20);
WHEN "111101110" => data <= conv_std_logic_vector(533669,20);
WHEN "111101111" => data <= conv_std_logic_vector(533139,20);
WHEN "111110000" => data <= conv_std_logic_vector(532610,20);
WHEN "111110001" => data <= conv_std_logic_vector(532082,20);
WHEN "111110010" => data <= conv_std_logic_vector(531555,20);
WHEN "111110011" => data <= conv_std_logic_vector(531029,20);
WHEN "111110100" => data <= conv_std_logic_vector(530505,20);
WHEN "111110101" => data <= conv_std_logic_vector(529981,20);
WHEN "111110110" => data <= conv_std_logic_vector(529458,20);
WHEN "111110111" => data <= conv_std_logic_vector(528937,20);
WHEN "111111000" => data <= conv_std_logic_vector(528416,20);
WHEN "111111001" => data <= conv_std_logic_vector(527897,20);
WHEN "111111010" => data <= conv_std_logic_vector(527378,20);
WHEN "111111011" => data <= conv_std_logic_vector(526860,20);
WHEN "111111100" => data <= conv_std_logic_vector(526344,20);
WHEN "111111101" => data <= conv_std_logic_vector(525828,20);
WHEN "111111110" => data <= conv_std_logic_vector(525314,20);
WHEN "111111111" => data <= conv_std_logic_vector(524800,20);
WHEN others => data <= conv_std_logic_vector(0,20);
END CASE;
END PROCESS;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_DIV_LUT0.VHD ***
--*** ***
--*** Function: Look Up Table - Inverse ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_div_lut0 IS
PORT (
add : IN STD_LOGIC_VECTOR (9 DOWNTO 1);
data : OUT STD_LOGIC_VECTOR (20 DOWNTO 1)
);
END fp_div_lut0;
ARCHITECTURE rtl OF fp_div_lut0 IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "000000000" => data <= conv_std_logic_vector(1048575,20);
WHEN "000000001" => data <= conv_std_logic_vector(1046531,20);
WHEN "000000010" => data <= conv_std_logic_vector(1044495,20);
WHEN "000000011" => data <= conv_std_logic_vector(1042467,20);
WHEN "000000100" => data <= conv_std_logic_vector(1040447,20);
WHEN "000000101" => data <= conv_std_logic_vector(1038434,20);
WHEN "000000110" => data <= conv_std_logic_vector(1036429,20);
WHEN "000000111" => data <= conv_std_logic_vector(1034432,20);
WHEN "000001000" => data <= conv_std_logic_vector(1032443,20);
WHEN "000001001" => data <= conv_std_logic_vector(1030461,20);
WHEN "000001010" => data <= conv_std_logic_vector(1028487,20);
WHEN "000001011" => data <= conv_std_logic_vector(1026521,20);
WHEN "000001100" => data <= conv_std_logic_vector(1024562,20);
WHEN "000001101" => data <= conv_std_logic_vector(1022610,20);
WHEN "000001110" => data <= conv_std_logic_vector(1020666,20);
WHEN "000001111" => data <= conv_std_logic_vector(1018729,20);
WHEN "000010000" => data <= conv_std_logic_vector(1016800,20);
WHEN "000010001" => data <= conv_std_logic_vector(1014878,20);
WHEN "000010010" => data <= conv_std_logic_vector(1012963,20);
WHEN "000010011" => data <= conv_std_logic_vector(1011055,20);
WHEN "000010100" => data <= conv_std_logic_vector(1009155,20);
WHEN "000010101" => data <= conv_std_logic_vector(1007262,20);
WHEN "000010110" => data <= conv_std_logic_vector(1005375,20);
WHEN "000010111" => data <= conv_std_logic_vector(1003496,20);
WHEN "000011000" => data <= conv_std_logic_vector(1001624,20);
WHEN "000011001" => data <= conv_std_logic_vector(999759,20);
WHEN "000011010" => data <= conv_std_logic_vector(997900,20);
WHEN "000011011" => data <= conv_std_logic_vector(996049,20);
WHEN "000011100" => data <= conv_std_logic_vector(994205,20);
WHEN "000011101" => data <= conv_std_logic_vector(992367,20);
WHEN "000011110" => data <= conv_std_logic_vector(990536,20);
WHEN "000011111" => data <= conv_std_logic_vector(988712,20);
WHEN "000100000" => data <= conv_std_logic_vector(986894,20);
WHEN "000100001" => data <= conv_std_logic_vector(985083,20);
WHEN "000100010" => data <= conv_std_logic_vector(983279,20);
WHEN "000100011" => data <= conv_std_logic_vector(981482,20);
WHEN "000100100" => data <= conv_std_logic_vector(979691,20);
WHEN "000100101" => data <= conv_std_logic_vector(977906,20);
WHEN "000100110" => data <= conv_std_logic_vector(976128,20);
WHEN "000100111" => data <= conv_std_logic_vector(974357,20);
WHEN "000101000" => data <= conv_std_logic_vector(972591,20);
WHEN "000101001" => data <= conv_std_logic_vector(970833,20);
WHEN "000101010" => data <= conv_std_logic_vector(969080,20);
WHEN "000101011" => data <= conv_std_logic_vector(967334,20);
WHEN "000101100" => data <= conv_std_logic_vector(965594,20);
WHEN "000101101" => data <= conv_std_logic_vector(963861,20);
WHEN "000101110" => data <= conv_std_logic_vector(962133,20);
WHEN "000101111" => data <= conv_std_logic_vector(960412,20);
WHEN "000110000" => data <= conv_std_logic_vector(958697,20);
WHEN "000110001" => data <= conv_std_logic_vector(956988,20);
WHEN "000110010" => data <= conv_std_logic_vector(955286,20);
WHEN "000110011" => data <= conv_std_logic_vector(953589,20);
WHEN "000110100" => data <= conv_std_logic_vector(951898,20);
WHEN "000110101" => data <= conv_std_logic_vector(950213,20);
WHEN "000110110" => data <= conv_std_logic_vector(948534,20);
WHEN "000110111" => data <= conv_std_logic_vector(946862,20);
WHEN "000111000" => data <= conv_std_logic_vector(945195,20);
WHEN "000111001" => data <= conv_std_logic_vector(943533,20);
WHEN "000111010" => data <= conv_std_logic_vector(941878,20);
WHEN "000111011" => data <= conv_std_logic_vector(940229,20);
WHEN "000111100" => data <= conv_std_logic_vector(938585,20);
WHEN "000111101" => data <= conv_std_logic_vector(936947,20);
WHEN "000111110" => data <= conv_std_logic_vector(935314,20);
WHEN "000111111" => data <= conv_std_logic_vector(933688,20);
WHEN "001000000" => data <= conv_std_logic_vector(932067,20);
WHEN "001000001" => data <= conv_std_logic_vector(930451,20);
WHEN "001000010" => data <= conv_std_logic_vector(928842,20);
WHEN "001000011" => data <= conv_std_logic_vector(927237,20);
WHEN "001000100" => data <= conv_std_logic_vector(925639,20);
WHEN "001000101" => data <= conv_std_logic_vector(924046,20);
WHEN "001000110" => data <= conv_std_logic_vector(922458,20);
WHEN "001000111" => data <= conv_std_logic_vector(920876,20);
WHEN "001001000" => data <= conv_std_logic_vector(919299,20);
WHEN "001001001" => data <= conv_std_logic_vector(917727,20);
WHEN "001001010" => data <= conv_std_logic_vector(916161,20);
WHEN "001001011" => data <= conv_std_logic_vector(914601,20);
WHEN "001001100" => data <= conv_std_logic_vector(913045,20);
WHEN "001001101" => data <= conv_std_logic_vector(911495,20);
WHEN "001001110" => data <= conv_std_logic_vector(909950,20);
WHEN "001001111" => data <= conv_std_logic_vector(908410,20);
WHEN "001010000" => data <= conv_std_logic_vector(906876,20);
WHEN "001010001" => data <= conv_std_logic_vector(905347,20);
WHEN "001010010" => data <= conv_std_logic_vector(903822,20);
WHEN "001010011" => data <= conv_std_logic_vector(902303,20);
WHEN "001010100" => data <= conv_std_logic_vector(900789,20);
WHEN "001010101" => data <= conv_std_logic_vector(899281,20);
WHEN "001010110" => data <= conv_std_logic_vector(897777,20);
WHEN "001010111" => data <= conv_std_logic_vector(896278,20);
WHEN "001011000" => data <= conv_std_logic_vector(894784,20);
WHEN "001011001" => data <= conv_std_logic_vector(893295,20);
WHEN "001011010" => data <= conv_std_logic_vector(891812,20);
WHEN "001011011" => data <= conv_std_logic_vector(890333,20);
WHEN "001011100" => data <= conv_std_logic_vector(888859,20);
WHEN "001011101" => data <= conv_std_logic_vector(887389,20);
WHEN "001011110" => data <= conv_std_logic_vector(885925,20);
WHEN "001011111" => data <= conv_std_logic_vector(884465,20);
WHEN "001100000" => data <= conv_std_logic_vector(883011,20);
WHEN "001100001" => data <= conv_std_logic_vector(881561,20);
WHEN "001100010" => data <= conv_std_logic_vector(880116,20);
WHEN "001100011" => data <= conv_std_logic_vector(878675,20);
WHEN "001100100" => data <= conv_std_logic_vector(877239,20);
WHEN "001100101" => data <= conv_std_logic_vector(875808,20);
WHEN "001100110" => data <= conv_std_logic_vector(874382,20);
WHEN "001100111" => data <= conv_std_logic_vector(872960,20);
WHEN "001101000" => data <= conv_std_logic_vector(871543,20);
WHEN "001101001" => data <= conv_std_logic_vector(870131,20);
WHEN "001101010" => data <= conv_std_logic_vector(868723,20);
WHEN "001101011" => data <= conv_std_logic_vector(867319,20);
WHEN "001101100" => data <= conv_std_logic_vector(865920,20);
WHEN "001101101" => data <= conv_std_logic_vector(864526,20);
WHEN "001101110" => data <= conv_std_logic_vector(863136,20);
WHEN "001101111" => data <= conv_std_logic_vector(861751,20);
WHEN "001110000" => data <= conv_std_logic_vector(860369,20);
WHEN "001110001" => data <= conv_std_logic_vector(858993,20);
WHEN "001110010" => data <= conv_std_logic_vector(857621,20);
WHEN "001110011" => data <= conv_std_logic_vector(856253,20);
WHEN "001110100" => data <= conv_std_logic_vector(854889,20);
WHEN "001110101" => data <= conv_std_logic_vector(853530,20);
WHEN "001110110" => data <= conv_std_logic_vector(852176,20);
WHEN "001110111" => data <= conv_std_logic_vector(850825,20);
WHEN "001111000" => data <= conv_std_logic_vector(849479,20);
WHEN "001111001" => data <= conv_std_logic_vector(848137,20);
WHEN "001111010" => data <= conv_std_logic_vector(846799,20);
WHEN "001111011" => data <= conv_std_logic_vector(845465,20);
WHEN "001111100" => data <= conv_std_logic_vector(844136,20);
WHEN "001111101" => data <= conv_std_logic_vector(842811,20);
WHEN "001111110" => data <= conv_std_logic_vector(841490,20);
WHEN "001111111" => data <= conv_std_logic_vector(840173,20);
WHEN "010000000" => data <= conv_std_logic_vector(838860,20);
WHEN "010000001" => data <= conv_std_logic_vector(837552,20);
WHEN "010000010" => data <= conv_std_logic_vector(836247,20);
WHEN "010000011" => data <= conv_std_logic_vector(834946,20);
WHEN "010000100" => data <= conv_std_logic_vector(833650,20);
WHEN "010000101" => data <= conv_std_logic_vector(832358,20);
WHEN "010000110" => data <= conv_std_logic_vector(831069,20);
WHEN "010000111" => data <= conv_std_logic_vector(829785,20);
WHEN "010001000" => data <= conv_std_logic_vector(828504,20);
WHEN "010001001" => data <= conv_std_logic_vector(827227,20);
WHEN "010001010" => data <= conv_std_logic_vector(825955,20);
WHEN "010001011" => data <= conv_std_logic_vector(824686,20);
WHEN "010001100" => data <= conv_std_logic_vector(823421,20);
WHEN "010001101" => data <= conv_std_logic_vector(822160,20);
WHEN "010001110" => data <= conv_std_logic_vector(820903,20);
WHEN "010001111" => data <= conv_std_logic_vector(819650,20);
WHEN "010010000" => data <= conv_std_logic_vector(818400,20);
WHEN "010010001" => data <= conv_std_logic_vector(817155,20);
WHEN "010010010" => data <= conv_std_logic_vector(815913,20);
WHEN "010010011" => data <= conv_std_logic_vector(814675,20);
WHEN "010010100" => data <= conv_std_logic_vector(813440,20);
WHEN "010010101" => data <= conv_std_logic_vector(812210,20);
WHEN "010010110" => data <= conv_std_logic_vector(810983,20);
WHEN "010010111" => data <= conv_std_logic_vector(809760,20);
WHEN "010011000" => data <= conv_std_logic_vector(808540,20);
WHEN "010011001" => data <= conv_std_logic_vector(807324,20);
WHEN "010011010" => data <= conv_std_logic_vector(806112,20);
WHEN "010011011" => data <= conv_std_logic_vector(804903,20);
WHEN "010011100" => data <= conv_std_logic_vector(803699,20);
WHEN "010011101" => data <= conv_std_logic_vector(802497,20);
WHEN "010011110" => data <= conv_std_logic_vector(801299,20);
WHEN "010011111" => data <= conv_std_logic_vector(800105,20);
WHEN "010100000" => data <= conv_std_logic_vector(798915,20);
WHEN "010100001" => data <= conv_std_logic_vector(797728,20);
WHEN "010100010" => data <= conv_std_logic_vector(796544,20);
WHEN "010100011" => data <= conv_std_logic_vector(795364,20);
WHEN "010100100" => data <= conv_std_logic_vector(794187,20);
WHEN "010100101" => data <= conv_std_logic_vector(793014,20);
WHEN "010100110" => data <= conv_std_logic_vector(791845,20);
WHEN "010100111" => data <= conv_std_logic_vector(790678,20);
WHEN "010101000" => data <= conv_std_logic_vector(789516,20);
WHEN "010101001" => data <= conv_std_logic_vector(788356,20);
WHEN "010101010" => data <= conv_std_logic_vector(787200,20);
WHEN "010101011" => data <= conv_std_logic_vector(786048,20);
WHEN "010101100" => data <= conv_std_logic_vector(784899,20);
WHEN "010101101" => data <= conv_std_logic_vector(783753,20);
WHEN "010101110" => data <= conv_std_logic_vector(782610,20);
WHEN "010101111" => data <= conv_std_logic_vector(781471,20);
WHEN "010110000" => data <= conv_std_logic_vector(780335,20);
WHEN "010110001" => data <= conv_std_logic_vector(779203,20);
WHEN "010110010" => data <= conv_std_logic_vector(778073,20);
WHEN "010110011" => data <= conv_std_logic_vector(776947,20);
WHEN "010110100" => data <= conv_std_logic_vector(775825,20);
WHEN "010110101" => data <= conv_std_logic_vector(774705,20);
WHEN "010110110" => data <= conv_std_logic_vector(773589,20);
WHEN "010110111" => data <= conv_std_logic_vector(772476,20);
WHEN "010111000" => data <= conv_std_logic_vector(771366,20);
WHEN "010111001" => data <= conv_std_logic_vector(770259,20);
WHEN "010111010" => data <= conv_std_logic_vector(769156,20);
WHEN "010111011" => data <= conv_std_logic_vector(768055,20);
WHEN "010111100" => data <= conv_std_logic_vector(766958,20);
WHEN "010111101" => data <= conv_std_logic_vector(765864,20);
WHEN "010111110" => data <= conv_std_logic_vector(764773,20);
WHEN "010111111" => data <= conv_std_logic_vector(763685,20);
WHEN "011000000" => data <= conv_std_logic_vector(762600,20);
WHEN "011000001" => data <= conv_std_logic_vector(761519,20);
WHEN "011000010" => data <= conv_std_logic_vector(760440,20);
WHEN "011000011" => data <= conv_std_logic_vector(759364,20);
WHEN "011000100" => data <= conv_std_logic_vector(758292,20);
WHEN "011000101" => data <= conv_std_logic_vector(757222,20);
WHEN "011000110" => data <= conv_std_logic_vector(756156,20);
WHEN "011000111" => data <= conv_std_logic_vector(755092,20);
WHEN "011001000" => data <= conv_std_logic_vector(754032,20);
WHEN "011001001" => data <= conv_std_logic_vector(752974,20);
WHEN "011001010" => data <= conv_std_logic_vector(751920,20);
WHEN "011001011" => data <= conv_std_logic_vector(750868,20);
WHEN "011001100" => data <= conv_std_logic_vector(749819,20);
WHEN "011001101" => data <= conv_std_logic_vector(748774,20);
WHEN "011001110" => data <= conv_std_logic_vector(747731,20);
WHEN "011001111" => data <= conv_std_logic_vector(746691,20);
WHEN "011010000" => data <= conv_std_logic_vector(745654,20);
WHEN "011010001" => data <= conv_std_logic_vector(744619,20);
WHEN "011010010" => data <= conv_std_logic_vector(743588,20);
WHEN "011010011" => data <= conv_std_logic_vector(742560,20);
WHEN "011010100" => data <= conv_std_logic_vector(741534,20);
WHEN "011010101" => data <= conv_std_logic_vector(740511,20);
WHEN "011010110" => data <= conv_std_logic_vector(739491,20);
WHEN "011010111" => data <= conv_std_logic_vector(738474,20);
WHEN "011011000" => data <= conv_std_logic_vector(737460,20);
WHEN "011011001" => data <= conv_std_logic_vector(736448,20);
WHEN "011011010" => data <= conv_std_logic_vector(735439,20);
WHEN "011011011" => data <= conv_std_logic_vector(734433,20);
WHEN "011011100" => data <= conv_std_logic_vector(733430,20);
WHEN "011011101" => data <= conv_std_logic_vector(732429,20);
WHEN "011011110" => data <= conv_std_logic_vector(731431,20);
WHEN "011011111" => data <= conv_std_logic_vector(730436,20);
WHEN "011100000" => data <= conv_std_logic_vector(729444,20);
WHEN "011100001" => data <= conv_std_logic_vector(728454,20);
WHEN "011100010" => data <= conv_std_logic_vector(727467,20);
WHEN "011100011" => data <= conv_std_logic_vector(726483,20);
WHEN "011100100" => data <= conv_std_logic_vector(725501,20);
WHEN "011100101" => data <= conv_std_logic_vector(724522,20);
WHEN "011100110" => data <= conv_std_logic_vector(723545,20);
WHEN "011100111" => data <= conv_std_logic_vector(722572,20);
WHEN "011101000" => data <= conv_std_logic_vector(721600,20);
WHEN "011101001" => data <= conv_std_logic_vector(720632,20);
WHEN "011101010" => data <= conv_std_logic_vector(719666,20);
WHEN "011101011" => data <= conv_std_logic_vector(718702,20);
WHEN "011101100" => data <= conv_std_logic_vector(717742,20);
WHEN "011101101" => data <= conv_std_logic_vector(716783,20);
WHEN "011101110" => data <= conv_std_logic_vector(715828,20);
WHEN "011101111" => data <= conv_std_logic_vector(714874,20);
WHEN "011110000" => data <= conv_std_logic_vector(713924,20);
WHEN "011110001" => data <= conv_std_logic_vector(712976,20);
WHEN "011110010" => data <= conv_std_logic_vector(712030,20);
WHEN "011110011" => data <= conv_std_logic_vector(711087,20);
WHEN "011110100" => data <= conv_std_logic_vector(710146,20);
WHEN "011110101" => data <= conv_std_logic_vector(709208,20);
WHEN "011110110" => data <= conv_std_logic_vector(708273,20);
WHEN "011110111" => data <= conv_std_logic_vector(707339,20);
WHEN "011111000" => data <= conv_std_logic_vector(706409,20);
WHEN "011111001" => data <= conv_std_logic_vector(705481,20);
WHEN "011111010" => data <= conv_std_logic_vector(704555,20);
WHEN "011111011" => data <= conv_std_logic_vector(703631,20);
WHEN "011111100" => data <= conv_std_logic_vector(702710,20);
WHEN "011111101" => data <= conv_std_logic_vector(701792,20);
WHEN "011111110" => data <= conv_std_logic_vector(700876,20);
WHEN "011111111" => data <= conv_std_logic_vector(699962,20);
WHEN "100000000" => data <= conv_std_logic_vector(699050,20);
WHEN "100000001" => data <= conv_std_logic_vector(698141,20);
WHEN "100000010" => data <= conv_std_logic_vector(697235,20);
WHEN "100000011" => data <= conv_std_logic_vector(696330,20);
WHEN "100000100" => data <= conv_std_logic_vector(695428,20);
WHEN "100000101" => data <= conv_std_logic_vector(694529,20);
WHEN "100000110" => data <= conv_std_logic_vector(693631,20);
WHEN "100000111" => data <= conv_std_logic_vector(692736,20);
WHEN "100001000" => data <= conv_std_logic_vector(691844,20);
WHEN "100001001" => data <= conv_std_logic_vector(690953,20);
WHEN "100001010" => data <= conv_std_logic_vector(690065,20);
WHEN "100001011" => data <= conv_std_logic_vector(689179,20);
WHEN "100001100" => data <= conv_std_logic_vector(688296,20);
WHEN "100001101" => data <= conv_std_logic_vector(687414,20);
WHEN "100001110" => data <= conv_std_logic_vector(686535,20);
WHEN "100001111" => data <= conv_std_logic_vector(685659,20);
WHEN "100010000" => data <= conv_std_logic_vector(684784,20);
WHEN "100010001" => data <= conv_std_logic_vector(683912,20);
WHEN "100010010" => data <= conv_std_logic_vector(683042,20);
WHEN "100010011" => data <= conv_std_logic_vector(682174,20);
WHEN "100010100" => data <= conv_std_logic_vector(681308,20);
WHEN "100010101" => data <= conv_std_logic_vector(680444,20);
WHEN "100010110" => data <= conv_std_logic_vector(679583,20);
WHEN "100010111" => data <= conv_std_logic_vector(678724,20);
WHEN "100011000" => data <= conv_std_logic_vector(677867,20);
WHEN "100011001" => data <= conv_std_logic_vector(677012,20);
WHEN "100011010" => data <= conv_std_logic_vector(676160,20);
WHEN "100011011" => data <= conv_std_logic_vector(675309,20);
WHEN "100011100" => data <= conv_std_logic_vector(674461,20);
WHEN "100011101" => data <= conv_std_logic_vector(673614,20);
WHEN "100011110" => data <= conv_std_logic_vector(672770,20);
WHEN "100011111" => data <= conv_std_logic_vector(671928,20);
WHEN "100100000" => data <= conv_std_logic_vector(671088,20);
WHEN "100100001" => data <= conv_std_logic_vector(670251,20);
WHEN "100100010" => data <= conv_std_logic_vector(669415,20);
WHEN "100100011" => data <= conv_std_logic_vector(668581,20);
WHEN "100100100" => data <= conv_std_logic_vector(667750,20);
WHEN "100100101" => data <= conv_std_logic_vector(666920,20);
WHEN "100100110" => data <= conv_std_logic_vector(666093,20);
WHEN "100100111" => data <= conv_std_logic_vector(665267,20);
WHEN "100101000" => data <= conv_std_logic_vector(664444,20);
WHEN "100101001" => data <= conv_std_logic_vector(663623,20);
WHEN "100101010" => data <= conv_std_logic_vector(662803,20);
WHEN "100101011" => data <= conv_std_logic_vector(661986,20);
WHEN "100101100" => data <= conv_std_logic_vector(661171,20);
WHEN "100101101" => data <= conv_std_logic_vector(660358,20);
WHEN "100101110" => data <= conv_std_logic_vector(659546,20);
WHEN "100101111" => data <= conv_std_logic_vector(658737,20);
WHEN "100110000" => data <= conv_std_logic_vector(657930,20);
WHEN "100110001" => data <= conv_std_logic_vector(657124,20);
WHEN "100110010" => data <= conv_std_logic_vector(656321,20);
WHEN "100110011" => data <= conv_std_logic_vector(655520,20);
WHEN "100110100" => data <= conv_std_logic_vector(654720,20);
WHEN "100110101" => data <= conv_std_logic_vector(653923,20);
WHEN "100110110" => data <= conv_std_logic_vector(653127,20);
WHEN "100110111" => data <= conv_std_logic_vector(652334,20);
WHEN "100111000" => data <= conv_std_logic_vector(651542,20);
WHEN "100111001" => data <= conv_std_logic_vector(650752,20);
WHEN "100111010" => data <= conv_std_logic_vector(649965,20);
WHEN "100111011" => data <= conv_std_logic_vector(649179,20);
WHEN "100111100" => data <= conv_std_logic_vector(648395,20);
WHEN "100111101" => data <= conv_std_logic_vector(647612,20);
WHEN "100111110" => data <= conv_std_logic_vector(646832,20);
WHEN "100111111" => data <= conv_std_logic_vector(646054,20);
WHEN "101000000" => data <= conv_std_logic_vector(645277,20);
WHEN "101000001" => data <= conv_std_logic_vector(644503,20);
WHEN "101000010" => data <= conv_std_logic_vector(643730,20);
WHEN "101000011" => data <= conv_std_logic_vector(642959,20);
WHEN "101000100" => data <= conv_std_logic_vector(642190,20);
WHEN "101000101" => data <= conv_std_logic_vector(641423,20);
WHEN "101000110" => data <= conv_std_logic_vector(640657,20);
WHEN "101000111" => data <= conv_std_logic_vector(639894,20);
WHEN "101001000" => data <= conv_std_logic_vector(639132,20);
WHEN "101001001" => data <= conv_std_logic_vector(638372,20);
WHEN "101001010" => data <= conv_std_logic_vector(637614,20);
WHEN "101001011" => data <= conv_std_logic_vector(636857,20);
WHEN "101001100" => data <= conv_std_logic_vector(636103,20);
WHEN "101001101" => data <= conv_std_logic_vector(635350,20);
WHEN "101001110" => data <= conv_std_logic_vector(634599,20);
WHEN "101001111" => data <= conv_std_logic_vector(633850,20);
WHEN "101010000" => data <= conv_std_logic_vector(633102,20);
WHEN "101010001" => data <= conv_std_logic_vector(632357,20);
WHEN "101010010" => data <= conv_std_logic_vector(631613,20);
WHEN "101010011" => data <= conv_std_logic_vector(630870,20);
WHEN "101010100" => data <= conv_std_logic_vector(630130,20);
WHEN "101010101" => data <= conv_std_logic_vector(629391,20);
WHEN "101010110" => data <= conv_std_logic_vector(628654,20);
WHEN "101010111" => data <= conv_std_logic_vector(627919,20);
WHEN "101011000" => data <= conv_std_logic_vector(627185,20);
WHEN "101011001" => data <= conv_std_logic_vector(626454,20);
WHEN "101011010" => data <= conv_std_logic_vector(625723,20);
WHEN "101011011" => data <= conv_std_logic_vector(624995,20);
WHEN "101011100" => data <= conv_std_logic_vector(624268,20);
WHEN "101011101" => data <= conv_std_logic_vector(623543,20);
WHEN "101011110" => data <= conv_std_logic_vector(622820,20);
WHEN "101011111" => data <= conv_std_logic_vector(622098,20);
WHEN "101100000" => data <= conv_std_logic_vector(621378,20);
WHEN "101100001" => data <= conv_std_logic_vector(620660,20);
WHEN "101100010" => data <= conv_std_logic_vector(619943,20);
WHEN "101100011" => data <= conv_std_logic_vector(619228,20);
WHEN "101100100" => data <= conv_std_logic_vector(618515,20);
WHEN "101100101" => data <= conv_std_logic_vector(617803,20);
WHEN "101100110" => data <= conv_std_logic_vector(617093,20);
WHEN "101100111" => data <= conv_std_logic_vector(616384,20);
WHEN "101101000" => data <= conv_std_logic_vector(615677,20);
WHEN "101101001" => data <= conv_std_logic_vector(614972,20);
WHEN "101101010" => data <= conv_std_logic_vector(614269,20);
WHEN "101101011" => data <= conv_std_logic_vector(613567,20);
WHEN "101101100" => data <= conv_std_logic_vector(612866,20);
WHEN "101101101" => data <= conv_std_logic_vector(612167,20);
WHEN "101101110" => data <= conv_std_logic_vector(611470,20);
WHEN "101101111" => data <= conv_std_logic_vector(610774,20);
WHEN "101110000" => data <= conv_std_logic_vector(610080,20);
WHEN "101110001" => data <= conv_std_logic_vector(609388,20);
WHEN "101110010" => data <= conv_std_logic_vector(608697,20);
WHEN "101110011" => data <= conv_std_logic_vector(608008,20);
WHEN "101110100" => data <= conv_std_logic_vector(607320,20);
WHEN "101110101" => data <= conv_std_logic_vector(606634,20);
WHEN "101110110" => data <= conv_std_logic_vector(605949,20);
WHEN "101110111" => data <= conv_std_logic_vector(605266,20);
WHEN "101111000" => data <= conv_std_logic_vector(604584,20);
WHEN "101111001" => data <= conv_std_logic_vector(603904,20);
WHEN "101111010" => data <= conv_std_logic_vector(603226,20);
WHEN "101111011" => data <= conv_std_logic_vector(602549,20);
WHEN "101111100" => data <= conv_std_logic_vector(601873,20);
WHEN "101111101" => data <= conv_std_logic_vector(601199,20);
WHEN "101111110" => data <= conv_std_logic_vector(600527,20);
WHEN "101111111" => data <= conv_std_logic_vector(599856,20);
WHEN "110000000" => data <= conv_std_logic_vector(599186,20);
WHEN "110000001" => data <= conv_std_logic_vector(598518,20);
WHEN "110000010" => data <= conv_std_logic_vector(597852,20);
WHEN "110000011" => data <= conv_std_logic_vector(597187,20);
WHEN "110000100" => data <= conv_std_logic_vector(596523,20);
WHEN "110000101" => data <= conv_std_logic_vector(595861,20);
WHEN "110000110" => data <= conv_std_logic_vector(595200,20);
WHEN "110000111" => data <= conv_std_logic_vector(594541,20);
WHEN "110001000" => data <= conv_std_logic_vector(593884,20);
WHEN "110001001" => data <= conv_std_logic_vector(593227,20);
WHEN "110001010" => data <= conv_std_logic_vector(592573,20);
WHEN "110001011" => data <= conv_std_logic_vector(591919,20);
WHEN "110001100" => data <= conv_std_logic_vector(591267,20);
WHEN "110001101" => data <= conv_std_logic_vector(590617,20);
WHEN "110001110" => data <= conv_std_logic_vector(589968,20);
WHEN "110001111" => data <= conv_std_logic_vector(589320,20);
WHEN "110010000" => data <= conv_std_logic_vector(588674,20);
WHEN "110010001" => data <= conv_std_logic_vector(588029,20);
WHEN "110010010" => data <= conv_std_logic_vector(587386,20);
WHEN "110010011" => data <= conv_std_logic_vector(586744,20);
WHEN "110010100" => data <= conv_std_logic_vector(586103,20);
WHEN "110010101" => data <= conv_std_logic_vector(585464,20);
WHEN "110010110" => data <= conv_std_logic_vector(584827,20);
WHEN "110010111" => data <= conv_std_logic_vector(584190,20);
WHEN "110011000" => data <= conv_std_logic_vector(583555,20);
WHEN "110011001" => data <= conv_std_logic_vector(582922,20);
WHEN "110011010" => data <= conv_std_logic_vector(582289,20);
WHEN "110011011" => data <= conv_std_logic_vector(581658,20);
WHEN "110011100" => data <= conv_std_logic_vector(581029,20);
WHEN "110011101" => data <= conv_std_logic_vector(580401,20);
WHEN "110011110" => data <= conv_std_logic_vector(579774,20);
WHEN "110011111" => data <= conv_std_logic_vector(579149,20);
WHEN "110100000" => data <= conv_std_logic_vector(578525,20);
WHEN "110100001" => data <= conv_std_logic_vector(577902,20);
WHEN "110100010" => data <= conv_std_logic_vector(577280,20);
WHEN "110100011" => data <= conv_std_logic_vector(576660,20);
WHEN "110100100" => data <= conv_std_logic_vector(576042,20);
WHEN "110100101" => data <= conv_std_logic_vector(575424,20);
WHEN "110100110" => data <= conv_std_logic_vector(574808,20);
WHEN "110100111" => data <= conv_std_logic_vector(574193,20);
WHEN "110101000" => data <= conv_std_logic_vector(573580,20);
WHEN "110101001" => data <= conv_std_logic_vector(572968,20);
WHEN "110101010" => data <= conv_std_logic_vector(572357,20);
WHEN "110101011" => data <= conv_std_logic_vector(571747,20);
WHEN "110101100" => data <= conv_std_logic_vector(571139,20);
WHEN "110101101" => data <= conv_std_logic_vector(570532,20);
WHEN "110101110" => data <= conv_std_logic_vector(569926,20);
WHEN "110101111" => data <= conv_std_logic_vector(569322,20);
WHEN "110110000" => data <= conv_std_logic_vector(568719,20);
WHEN "110110001" => data <= conv_std_logic_vector(568117,20);
WHEN "110110010" => data <= conv_std_logic_vector(567517,20);
WHEN "110110011" => data <= conv_std_logic_vector(566917,20);
WHEN "110110100" => data <= conv_std_logic_vector(566319,20);
WHEN "110110101" => data <= conv_std_logic_vector(565723,20);
WHEN "110110110" => data <= conv_std_logic_vector(565127,20);
WHEN "110110111" => data <= conv_std_logic_vector(564533,20);
WHEN "110111000" => data <= conv_std_logic_vector(563940,20);
WHEN "110111001" => data <= conv_std_logic_vector(563348,20);
WHEN "110111010" => data <= conv_std_logic_vector(562758,20);
WHEN "110111011" => data <= conv_std_logic_vector(562168,20);
WHEN "110111100" => data <= conv_std_logic_vector(561580,20);
WHEN "110111101" => data <= conv_std_logic_vector(560993,20);
WHEN "110111110" => data <= conv_std_logic_vector(560408,20);
WHEN "110111111" => data <= conv_std_logic_vector(559824,20);
WHEN "111000000" => data <= conv_std_logic_vector(559240,20);
WHEN "111000001" => data <= conv_std_logic_vector(558658,20);
WHEN "111000010" => data <= conv_std_logic_vector(558078,20);
WHEN "111000011" => data <= conv_std_logic_vector(557498,20);
WHEN "111000100" => data <= conv_std_logic_vector(556920,20);
WHEN "111000101" => data <= conv_std_logic_vector(556343,20);
WHEN "111000110" => data <= conv_std_logic_vector(555767,20);
WHEN "111000111" => data <= conv_std_logic_vector(555192,20);
WHEN "111001000" => data <= conv_std_logic_vector(554619,20);
WHEN "111001001" => data <= conv_std_logic_vector(554046,20);
WHEN "111001010" => data <= conv_std_logic_vector(553475,20);
WHEN "111001011" => data <= conv_std_logic_vector(552905,20);
WHEN "111001100" => data <= conv_std_logic_vector(552336,20);
WHEN "111001101" => data <= conv_std_logic_vector(551769,20);
WHEN "111001110" => data <= conv_std_logic_vector(551202,20);
WHEN "111001111" => data <= conv_std_logic_vector(550637,20);
WHEN "111010000" => data <= conv_std_logic_vector(550073,20);
WHEN "111010001" => data <= conv_std_logic_vector(549509,20);
WHEN "111010010" => data <= conv_std_logic_vector(548948,20);
WHEN "111010011" => data <= conv_std_logic_vector(548387,20);
WHEN "111010100" => data <= conv_std_logic_vector(547827,20);
WHEN "111010101" => data <= conv_std_logic_vector(547269,20);
WHEN "111010110" => data <= conv_std_logic_vector(546712,20);
WHEN "111010111" => data <= conv_std_logic_vector(546155,20);
WHEN "111011000" => data <= conv_std_logic_vector(545600,20);
WHEN "111011001" => data <= conv_std_logic_vector(545046,20);
WHEN "111011010" => data <= conv_std_logic_vector(544494,20);
WHEN "111011011" => data <= conv_std_logic_vector(543942,20);
WHEN "111011100" => data <= conv_std_logic_vector(543391,20);
WHEN "111011101" => data <= conv_std_logic_vector(542842,20);
WHEN "111011110" => data <= conv_std_logic_vector(542294,20);
WHEN "111011111" => data <= conv_std_logic_vector(541746,20);
WHEN "111100000" => data <= conv_std_logic_vector(541200,20);
WHEN "111100001" => data <= conv_std_logic_vector(540655,20);
WHEN "111100010" => data <= conv_std_logic_vector(540111,20);
WHEN "111100011" => data <= conv_std_logic_vector(539569,20);
WHEN "111100100" => data <= conv_std_logic_vector(539027,20);
WHEN "111100101" => data <= conv_std_logic_vector(538486,20);
WHEN "111100110" => data <= conv_std_logic_vector(537947,20);
WHEN "111100111" => data <= conv_std_logic_vector(537408,20);
WHEN "111101000" => data <= conv_std_logic_vector(536871,20);
WHEN "111101001" => data <= conv_std_logic_vector(536334,20);
WHEN "111101010" => data <= conv_std_logic_vector(535799,20);
WHEN "111101011" => data <= conv_std_logic_vector(535265,20);
WHEN "111101100" => data <= conv_std_logic_vector(534732,20);
WHEN "111101101" => data <= conv_std_logic_vector(534200,20);
WHEN "111101110" => data <= conv_std_logic_vector(533669,20);
WHEN "111101111" => data <= conv_std_logic_vector(533139,20);
WHEN "111110000" => data <= conv_std_logic_vector(532610,20);
WHEN "111110001" => data <= conv_std_logic_vector(532082,20);
WHEN "111110010" => data <= conv_std_logic_vector(531555,20);
WHEN "111110011" => data <= conv_std_logic_vector(531029,20);
WHEN "111110100" => data <= conv_std_logic_vector(530505,20);
WHEN "111110101" => data <= conv_std_logic_vector(529981,20);
WHEN "111110110" => data <= conv_std_logic_vector(529458,20);
WHEN "111110111" => data <= conv_std_logic_vector(528937,20);
WHEN "111111000" => data <= conv_std_logic_vector(528416,20);
WHEN "111111001" => data <= conv_std_logic_vector(527897,20);
WHEN "111111010" => data <= conv_std_logic_vector(527378,20);
WHEN "111111011" => data <= conv_std_logic_vector(526860,20);
WHEN "111111100" => data <= conv_std_logic_vector(526344,20);
WHEN "111111101" => data <= conv_std_logic_vector(525828,20);
WHEN "111111110" => data <= conv_std_logic_vector(525314,20);
WHEN "111111111" => data <= conv_std_logic_vector(524800,20);
WHEN others => data <= conv_std_logic_vector(0,20);
END CASE;
END PROCESS;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_DIV_LUT0.VHD ***
--*** ***
--*** Function: Look Up Table - Inverse ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_div_lut0 IS
PORT (
add : IN STD_LOGIC_VECTOR (9 DOWNTO 1);
data : OUT STD_LOGIC_VECTOR (20 DOWNTO 1)
);
END fp_div_lut0;
ARCHITECTURE rtl OF fp_div_lut0 IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "000000000" => data <= conv_std_logic_vector(1048575,20);
WHEN "000000001" => data <= conv_std_logic_vector(1046531,20);
WHEN "000000010" => data <= conv_std_logic_vector(1044495,20);
WHEN "000000011" => data <= conv_std_logic_vector(1042467,20);
WHEN "000000100" => data <= conv_std_logic_vector(1040447,20);
WHEN "000000101" => data <= conv_std_logic_vector(1038434,20);
WHEN "000000110" => data <= conv_std_logic_vector(1036429,20);
WHEN "000000111" => data <= conv_std_logic_vector(1034432,20);
WHEN "000001000" => data <= conv_std_logic_vector(1032443,20);
WHEN "000001001" => data <= conv_std_logic_vector(1030461,20);
WHEN "000001010" => data <= conv_std_logic_vector(1028487,20);
WHEN "000001011" => data <= conv_std_logic_vector(1026521,20);
WHEN "000001100" => data <= conv_std_logic_vector(1024562,20);
WHEN "000001101" => data <= conv_std_logic_vector(1022610,20);
WHEN "000001110" => data <= conv_std_logic_vector(1020666,20);
WHEN "000001111" => data <= conv_std_logic_vector(1018729,20);
WHEN "000010000" => data <= conv_std_logic_vector(1016800,20);
WHEN "000010001" => data <= conv_std_logic_vector(1014878,20);
WHEN "000010010" => data <= conv_std_logic_vector(1012963,20);
WHEN "000010011" => data <= conv_std_logic_vector(1011055,20);
WHEN "000010100" => data <= conv_std_logic_vector(1009155,20);
WHEN "000010101" => data <= conv_std_logic_vector(1007262,20);
WHEN "000010110" => data <= conv_std_logic_vector(1005375,20);
WHEN "000010111" => data <= conv_std_logic_vector(1003496,20);
WHEN "000011000" => data <= conv_std_logic_vector(1001624,20);
WHEN "000011001" => data <= conv_std_logic_vector(999759,20);
WHEN "000011010" => data <= conv_std_logic_vector(997900,20);
WHEN "000011011" => data <= conv_std_logic_vector(996049,20);
WHEN "000011100" => data <= conv_std_logic_vector(994205,20);
WHEN "000011101" => data <= conv_std_logic_vector(992367,20);
WHEN "000011110" => data <= conv_std_logic_vector(990536,20);
WHEN "000011111" => data <= conv_std_logic_vector(988712,20);
WHEN "000100000" => data <= conv_std_logic_vector(986894,20);
WHEN "000100001" => data <= conv_std_logic_vector(985083,20);
WHEN "000100010" => data <= conv_std_logic_vector(983279,20);
WHEN "000100011" => data <= conv_std_logic_vector(981482,20);
WHEN "000100100" => data <= conv_std_logic_vector(979691,20);
WHEN "000100101" => data <= conv_std_logic_vector(977906,20);
WHEN "000100110" => data <= conv_std_logic_vector(976128,20);
WHEN "000100111" => data <= conv_std_logic_vector(974357,20);
WHEN "000101000" => data <= conv_std_logic_vector(972591,20);
WHEN "000101001" => data <= conv_std_logic_vector(970833,20);
WHEN "000101010" => data <= conv_std_logic_vector(969080,20);
WHEN "000101011" => data <= conv_std_logic_vector(967334,20);
WHEN "000101100" => data <= conv_std_logic_vector(965594,20);
WHEN "000101101" => data <= conv_std_logic_vector(963861,20);
WHEN "000101110" => data <= conv_std_logic_vector(962133,20);
WHEN "000101111" => data <= conv_std_logic_vector(960412,20);
WHEN "000110000" => data <= conv_std_logic_vector(958697,20);
WHEN "000110001" => data <= conv_std_logic_vector(956988,20);
WHEN "000110010" => data <= conv_std_logic_vector(955286,20);
WHEN "000110011" => data <= conv_std_logic_vector(953589,20);
WHEN "000110100" => data <= conv_std_logic_vector(951898,20);
WHEN "000110101" => data <= conv_std_logic_vector(950213,20);
WHEN "000110110" => data <= conv_std_logic_vector(948534,20);
WHEN "000110111" => data <= conv_std_logic_vector(946862,20);
WHEN "000111000" => data <= conv_std_logic_vector(945195,20);
WHEN "000111001" => data <= conv_std_logic_vector(943533,20);
WHEN "000111010" => data <= conv_std_logic_vector(941878,20);
WHEN "000111011" => data <= conv_std_logic_vector(940229,20);
WHEN "000111100" => data <= conv_std_logic_vector(938585,20);
WHEN "000111101" => data <= conv_std_logic_vector(936947,20);
WHEN "000111110" => data <= conv_std_logic_vector(935314,20);
WHEN "000111111" => data <= conv_std_logic_vector(933688,20);
WHEN "001000000" => data <= conv_std_logic_vector(932067,20);
WHEN "001000001" => data <= conv_std_logic_vector(930451,20);
WHEN "001000010" => data <= conv_std_logic_vector(928842,20);
WHEN "001000011" => data <= conv_std_logic_vector(927237,20);
WHEN "001000100" => data <= conv_std_logic_vector(925639,20);
WHEN "001000101" => data <= conv_std_logic_vector(924046,20);
WHEN "001000110" => data <= conv_std_logic_vector(922458,20);
WHEN "001000111" => data <= conv_std_logic_vector(920876,20);
WHEN "001001000" => data <= conv_std_logic_vector(919299,20);
WHEN "001001001" => data <= conv_std_logic_vector(917727,20);
WHEN "001001010" => data <= conv_std_logic_vector(916161,20);
WHEN "001001011" => data <= conv_std_logic_vector(914601,20);
WHEN "001001100" => data <= conv_std_logic_vector(913045,20);
WHEN "001001101" => data <= conv_std_logic_vector(911495,20);
WHEN "001001110" => data <= conv_std_logic_vector(909950,20);
WHEN "001001111" => data <= conv_std_logic_vector(908410,20);
WHEN "001010000" => data <= conv_std_logic_vector(906876,20);
WHEN "001010001" => data <= conv_std_logic_vector(905347,20);
WHEN "001010010" => data <= conv_std_logic_vector(903822,20);
WHEN "001010011" => data <= conv_std_logic_vector(902303,20);
WHEN "001010100" => data <= conv_std_logic_vector(900789,20);
WHEN "001010101" => data <= conv_std_logic_vector(899281,20);
WHEN "001010110" => data <= conv_std_logic_vector(897777,20);
WHEN "001010111" => data <= conv_std_logic_vector(896278,20);
WHEN "001011000" => data <= conv_std_logic_vector(894784,20);
WHEN "001011001" => data <= conv_std_logic_vector(893295,20);
WHEN "001011010" => data <= conv_std_logic_vector(891812,20);
WHEN "001011011" => data <= conv_std_logic_vector(890333,20);
WHEN "001011100" => data <= conv_std_logic_vector(888859,20);
WHEN "001011101" => data <= conv_std_logic_vector(887389,20);
WHEN "001011110" => data <= conv_std_logic_vector(885925,20);
WHEN "001011111" => data <= conv_std_logic_vector(884465,20);
WHEN "001100000" => data <= conv_std_logic_vector(883011,20);
WHEN "001100001" => data <= conv_std_logic_vector(881561,20);
WHEN "001100010" => data <= conv_std_logic_vector(880116,20);
WHEN "001100011" => data <= conv_std_logic_vector(878675,20);
WHEN "001100100" => data <= conv_std_logic_vector(877239,20);
WHEN "001100101" => data <= conv_std_logic_vector(875808,20);
WHEN "001100110" => data <= conv_std_logic_vector(874382,20);
WHEN "001100111" => data <= conv_std_logic_vector(872960,20);
WHEN "001101000" => data <= conv_std_logic_vector(871543,20);
WHEN "001101001" => data <= conv_std_logic_vector(870131,20);
WHEN "001101010" => data <= conv_std_logic_vector(868723,20);
WHEN "001101011" => data <= conv_std_logic_vector(867319,20);
WHEN "001101100" => data <= conv_std_logic_vector(865920,20);
WHEN "001101101" => data <= conv_std_logic_vector(864526,20);
WHEN "001101110" => data <= conv_std_logic_vector(863136,20);
WHEN "001101111" => data <= conv_std_logic_vector(861751,20);
WHEN "001110000" => data <= conv_std_logic_vector(860369,20);
WHEN "001110001" => data <= conv_std_logic_vector(858993,20);
WHEN "001110010" => data <= conv_std_logic_vector(857621,20);
WHEN "001110011" => data <= conv_std_logic_vector(856253,20);
WHEN "001110100" => data <= conv_std_logic_vector(854889,20);
WHEN "001110101" => data <= conv_std_logic_vector(853530,20);
WHEN "001110110" => data <= conv_std_logic_vector(852176,20);
WHEN "001110111" => data <= conv_std_logic_vector(850825,20);
WHEN "001111000" => data <= conv_std_logic_vector(849479,20);
WHEN "001111001" => data <= conv_std_logic_vector(848137,20);
WHEN "001111010" => data <= conv_std_logic_vector(846799,20);
WHEN "001111011" => data <= conv_std_logic_vector(845465,20);
WHEN "001111100" => data <= conv_std_logic_vector(844136,20);
WHEN "001111101" => data <= conv_std_logic_vector(842811,20);
WHEN "001111110" => data <= conv_std_logic_vector(841490,20);
WHEN "001111111" => data <= conv_std_logic_vector(840173,20);
WHEN "010000000" => data <= conv_std_logic_vector(838860,20);
WHEN "010000001" => data <= conv_std_logic_vector(837552,20);
WHEN "010000010" => data <= conv_std_logic_vector(836247,20);
WHEN "010000011" => data <= conv_std_logic_vector(834946,20);
WHEN "010000100" => data <= conv_std_logic_vector(833650,20);
WHEN "010000101" => data <= conv_std_logic_vector(832358,20);
WHEN "010000110" => data <= conv_std_logic_vector(831069,20);
WHEN "010000111" => data <= conv_std_logic_vector(829785,20);
WHEN "010001000" => data <= conv_std_logic_vector(828504,20);
WHEN "010001001" => data <= conv_std_logic_vector(827227,20);
WHEN "010001010" => data <= conv_std_logic_vector(825955,20);
WHEN "010001011" => data <= conv_std_logic_vector(824686,20);
WHEN "010001100" => data <= conv_std_logic_vector(823421,20);
WHEN "010001101" => data <= conv_std_logic_vector(822160,20);
WHEN "010001110" => data <= conv_std_logic_vector(820903,20);
WHEN "010001111" => data <= conv_std_logic_vector(819650,20);
WHEN "010010000" => data <= conv_std_logic_vector(818400,20);
WHEN "010010001" => data <= conv_std_logic_vector(817155,20);
WHEN "010010010" => data <= conv_std_logic_vector(815913,20);
WHEN "010010011" => data <= conv_std_logic_vector(814675,20);
WHEN "010010100" => data <= conv_std_logic_vector(813440,20);
WHEN "010010101" => data <= conv_std_logic_vector(812210,20);
WHEN "010010110" => data <= conv_std_logic_vector(810983,20);
WHEN "010010111" => data <= conv_std_logic_vector(809760,20);
WHEN "010011000" => data <= conv_std_logic_vector(808540,20);
WHEN "010011001" => data <= conv_std_logic_vector(807324,20);
WHEN "010011010" => data <= conv_std_logic_vector(806112,20);
WHEN "010011011" => data <= conv_std_logic_vector(804903,20);
WHEN "010011100" => data <= conv_std_logic_vector(803699,20);
WHEN "010011101" => data <= conv_std_logic_vector(802497,20);
WHEN "010011110" => data <= conv_std_logic_vector(801299,20);
WHEN "010011111" => data <= conv_std_logic_vector(800105,20);
WHEN "010100000" => data <= conv_std_logic_vector(798915,20);
WHEN "010100001" => data <= conv_std_logic_vector(797728,20);
WHEN "010100010" => data <= conv_std_logic_vector(796544,20);
WHEN "010100011" => data <= conv_std_logic_vector(795364,20);
WHEN "010100100" => data <= conv_std_logic_vector(794187,20);
WHEN "010100101" => data <= conv_std_logic_vector(793014,20);
WHEN "010100110" => data <= conv_std_logic_vector(791845,20);
WHEN "010100111" => data <= conv_std_logic_vector(790678,20);
WHEN "010101000" => data <= conv_std_logic_vector(789516,20);
WHEN "010101001" => data <= conv_std_logic_vector(788356,20);
WHEN "010101010" => data <= conv_std_logic_vector(787200,20);
WHEN "010101011" => data <= conv_std_logic_vector(786048,20);
WHEN "010101100" => data <= conv_std_logic_vector(784899,20);
WHEN "010101101" => data <= conv_std_logic_vector(783753,20);
WHEN "010101110" => data <= conv_std_logic_vector(782610,20);
WHEN "010101111" => data <= conv_std_logic_vector(781471,20);
WHEN "010110000" => data <= conv_std_logic_vector(780335,20);
WHEN "010110001" => data <= conv_std_logic_vector(779203,20);
WHEN "010110010" => data <= conv_std_logic_vector(778073,20);
WHEN "010110011" => data <= conv_std_logic_vector(776947,20);
WHEN "010110100" => data <= conv_std_logic_vector(775825,20);
WHEN "010110101" => data <= conv_std_logic_vector(774705,20);
WHEN "010110110" => data <= conv_std_logic_vector(773589,20);
WHEN "010110111" => data <= conv_std_logic_vector(772476,20);
WHEN "010111000" => data <= conv_std_logic_vector(771366,20);
WHEN "010111001" => data <= conv_std_logic_vector(770259,20);
WHEN "010111010" => data <= conv_std_logic_vector(769156,20);
WHEN "010111011" => data <= conv_std_logic_vector(768055,20);
WHEN "010111100" => data <= conv_std_logic_vector(766958,20);
WHEN "010111101" => data <= conv_std_logic_vector(765864,20);
WHEN "010111110" => data <= conv_std_logic_vector(764773,20);
WHEN "010111111" => data <= conv_std_logic_vector(763685,20);
WHEN "011000000" => data <= conv_std_logic_vector(762600,20);
WHEN "011000001" => data <= conv_std_logic_vector(761519,20);
WHEN "011000010" => data <= conv_std_logic_vector(760440,20);
WHEN "011000011" => data <= conv_std_logic_vector(759364,20);
WHEN "011000100" => data <= conv_std_logic_vector(758292,20);
WHEN "011000101" => data <= conv_std_logic_vector(757222,20);
WHEN "011000110" => data <= conv_std_logic_vector(756156,20);
WHEN "011000111" => data <= conv_std_logic_vector(755092,20);
WHEN "011001000" => data <= conv_std_logic_vector(754032,20);
WHEN "011001001" => data <= conv_std_logic_vector(752974,20);
WHEN "011001010" => data <= conv_std_logic_vector(751920,20);
WHEN "011001011" => data <= conv_std_logic_vector(750868,20);
WHEN "011001100" => data <= conv_std_logic_vector(749819,20);
WHEN "011001101" => data <= conv_std_logic_vector(748774,20);
WHEN "011001110" => data <= conv_std_logic_vector(747731,20);
WHEN "011001111" => data <= conv_std_logic_vector(746691,20);
WHEN "011010000" => data <= conv_std_logic_vector(745654,20);
WHEN "011010001" => data <= conv_std_logic_vector(744619,20);
WHEN "011010010" => data <= conv_std_logic_vector(743588,20);
WHEN "011010011" => data <= conv_std_logic_vector(742560,20);
WHEN "011010100" => data <= conv_std_logic_vector(741534,20);
WHEN "011010101" => data <= conv_std_logic_vector(740511,20);
WHEN "011010110" => data <= conv_std_logic_vector(739491,20);
WHEN "011010111" => data <= conv_std_logic_vector(738474,20);
WHEN "011011000" => data <= conv_std_logic_vector(737460,20);
WHEN "011011001" => data <= conv_std_logic_vector(736448,20);
WHEN "011011010" => data <= conv_std_logic_vector(735439,20);
WHEN "011011011" => data <= conv_std_logic_vector(734433,20);
WHEN "011011100" => data <= conv_std_logic_vector(733430,20);
WHEN "011011101" => data <= conv_std_logic_vector(732429,20);
WHEN "011011110" => data <= conv_std_logic_vector(731431,20);
WHEN "011011111" => data <= conv_std_logic_vector(730436,20);
WHEN "011100000" => data <= conv_std_logic_vector(729444,20);
WHEN "011100001" => data <= conv_std_logic_vector(728454,20);
WHEN "011100010" => data <= conv_std_logic_vector(727467,20);
WHEN "011100011" => data <= conv_std_logic_vector(726483,20);
WHEN "011100100" => data <= conv_std_logic_vector(725501,20);
WHEN "011100101" => data <= conv_std_logic_vector(724522,20);
WHEN "011100110" => data <= conv_std_logic_vector(723545,20);
WHEN "011100111" => data <= conv_std_logic_vector(722572,20);
WHEN "011101000" => data <= conv_std_logic_vector(721600,20);
WHEN "011101001" => data <= conv_std_logic_vector(720632,20);
WHEN "011101010" => data <= conv_std_logic_vector(719666,20);
WHEN "011101011" => data <= conv_std_logic_vector(718702,20);
WHEN "011101100" => data <= conv_std_logic_vector(717742,20);
WHEN "011101101" => data <= conv_std_logic_vector(716783,20);
WHEN "011101110" => data <= conv_std_logic_vector(715828,20);
WHEN "011101111" => data <= conv_std_logic_vector(714874,20);
WHEN "011110000" => data <= conv_std_logic_vector(713924,20);
WHEN "011110001" => data <= conv_std_logic_vector(712976,20);
WHEN "011110010" => data <= conv_std_logic_vector(712030,20);
WHEN "011110011" => data <= conv_std_logic_vector(711087,20);
WHEN "011110100" => data <= conv_std_logic_vector(710146,20);
WHEN "011110101" => data <= conv_std_logic_vector(709208,20);
WHEN "011110110" => data <= conv_std_logic_vector(708273,20);
WHEN "011110111" => data <= conv_std_logic_vector(707339,20);
WHEN "011111000" => data <= conv_std_logic_vector(706409,20);
WHEN "011111001" => data <= conv_std_logic_vector(705481,20);
WHEN "011111010" => data <= conv_std_logic_vector(704555,20);
WHEN "011111011" => data <= conv_std_logic_vector(703631,20);
WHEN "011111100" => data <= conv_std_logic_vector(702710,20);
WHEN "011111101" => data <= conv_std_logic_vector(701792,20);
WHEN "011111110" => data <= conv_std_logic_vector(700876,20);
WHEN "011111111" => data <= conv_std_logic_vector(699962,20);
WHEN "100000000" => data <= conv_std_logic_vector(699050,20);
WHEN "100000001" => data <= conv_std_logic_vector(698141,20);
WHEN "100000010" => data <= conv_std_logic_vector(697235,20);
WHEN "100000011" => data <= conv_std_logic_vector(696330,20);
WHEN "100000100" => data <= conv_std_logic_vector(695428,20);
WHEN "100000101" => data <= conv_std_logic_vector(694529,20);
WHEN "100000110" => data <= conv_std_logic_vector(693631,20);
WHEN "100000111" => data <= conv_std_logic_vector(692736,20);
WHEN "100001000" => data <= conv_std_logic_vector(691844,20);
WHEN "100001001" => data <= conv_std_logic_vector(690953,20);
WHEN "100001010" => data <= conv_std_logic_vector(690065,20);
WHEN "100001011" => data <= conv_std_logic_vector(689179,20);
WHEN "100001100" => data <= conv_std_logic_vector(688296,20);
WHEN "100001101" => data <= conv_std_logic_vector(687414,20);
WHEN "100001110" => data <= conv_std_logic_vector(686535,20);
WHEN "100001111" => data <= conv_std_logic_vector(685659,20);
WHEN "100010000" => data <= conv_std_logic_vector(684784,20);
WHEN "100010001" => data <= conv_std_logic_vector(683912,20);
WHEN "100010010" => data <= conv_std_logic_vector(683042,20);
WHEN "100010011" => data <= conv_std_logic_vector(682174,20);
WHEN "100010100" => data <= conv_std_logic_vector(681308,20);
WHEN "100010101" => data <= conv_std_logic_vector(680444,20);
WHEN "100010110" => data <= conv_std_logic_vector(679583,20);
WHEN "100010111" => data <= conv_std_logic_vector(678724,20);
WHEN "100011000" => data <= conv_std_logic_vector(677867,20);
WHEN "100011001" => data <= conv_std_logic_vector(677012,20);
WHEN "100011010" => data <= conv_std_logic_vector(676160,20);
WHEN "100011011" => data <= conv_std_logic_vector(675309,20);
WHEN "100011100" => data <= conv_std_logic_vector(674461,20);
WHEN "100011101" => data <= conv_std_logic_vector(673614,20);
WHEN "100011110" => data <= conv_std_logic_vector(672770,20);
WHEN "100011111" => data <= conv_std_logic_vector(671928,20);
WHEN "100100000" => data <= conv_std_logic_vector(671088,20);
WHEN "100100001" => data <= conv_std_logic_vector(670251,20);
WHEN "100100010" => data <= conv_std_logic_vector(669415,20);
WHEN "100100011" => data <= conv_std_logic_vector(668581,20);
WHEN "100100100" => data <= conv_std_logic_vector(667750,20);
WHEN "100100101" => data <= conv_std_logic_vector(666920,20);
WHEN "100100110" => data <= conv_std_logic_vector(666093,20);
WHEN "100100111" => data <= conv_std_logic_vector(665267,20);
WHEN "100101000" => data <= conv_std_logic_vector(664444,20);
WHEN "100101001" => data <= conv_std_logic_vector(663623,20);
WHEN "100101010" => data <= conv_std_logic_vector(662803,20);
WHEN "100101011" => data <= conv_std_logic_vector(661986,20);
WHEN "100101100" => data <= conv_std_logic_vector(661171,20);
WHEN "100101101" => data <= conv_std_logic_vector(660358,20);
WHEN "100101110" => data <= conv_std_logic_vector(659546,20);
WHEN "100101111" => data <= conv_std_logic_vector(658737,20);
WHEN "100110000" => data <= conv_std_logic_vector(657930,20);
WHEN "100110001" => data <= conv_std_logic_vector(657124,20);
WHEN "100110010" => data <= conv_std_logic_vector(656321,20);
WHEN "100110011" => data <= conv_std_logic_vector(655520,20);
WHEN "100110100" => data <= conv_std_logic_vector(654720,20);
WHEN "100110101" => data <= conv_std_logic_vector(653923,20);
WHEN "100110110" => data <= conv_std_logic_vector(653127,20);
WHEN "100110111" => data <= conv_std_logic_vector(652334,20);
WHEN "100111000" => data <= conv_std_logic_vector(651542,20);
WHEN "100111001" => data <= conv_std_logic_vector(650752,20);
WHEN "100111010" => data <= conv_std_logic_vector(649965,20);
WHEN "100111011" => data <= conv_std_logic_vector(649179,20);
WHEN "100111100" => data <= conv_std_logic_vector(648395,20);
WHEN "100111101" => data <= conv_std_logic_vector(647612,20);
WHEN "100111110" => data <= conv_std_logic_vector(646832,20);
WHEN "100111111" => data <= conv_std_logic_vector(646054,20);
WHEN "101000000" => data <= conv_std_logic_vector(645277,20);
WHEN "101000001" => data <= conv_std_logic_vector(644503,20);
WHEN "101000010" => data <= conv_std_logic_vector(643730,20);
WHEN "101000011" => data <= conv_std_logic_vector(642959,20);
WHEN "101000100" => data <= conv_std_logic_vector(642190,20);
WHEN "101000101" => data <= conv_std_logic_vector(641423,20);
WHEN "101000110" => data <= conv_std_logic_vector(640657,20);
WHEN "101000111" => data <= conv_std_logic_vector(639894,20);
WHEN "101001000" => data <= conv_std_logic_vector(639132,20);
WHEN "101001001" => data <= conv_std_logic_vector(638372,20);
WHEN "101001010" => data <= conv_std_logic_vector(637614,20);
WHEN "101001011" => data <= conv_std_logic_vector(636857,20);
WHEN "101001100" => data <= conv_std_logic_vector(636103,20);
WHEN "101001101" => data <= conv_std_logic_vector(635350,20);
WHEN "101001110" => data <= conv_std_logic_vector(634599,20);
WHEN "101001111" => data <= conv_std_logic_vector(633850,20);
WHEN "101010000" => data <= conv_std_logic_vector(633102,20);
WHEN "101010001" => data <= conv_std_logic_vector(632357,20);
WHEN "101010010" => data <= conv_std_logic_vector(631613,20);
WHEN "101010011" => data <= conv_std_logic_vector(630870,20);
WHEN "101010100" => data <= conv_std_logic_vector(630130,20);
WHEN "101010101" => data <= conv_std_logic_vector(629391,20);
WHEN "101010110" => data <= conv_std_logic_vector(628654,20);
WHEN "101010111" => data <= conv_std_logic_vector(627919,20);
WHEN "101011000" => data <= conv_std_logic_vector(627185,20);
WHEN "101011001" => data <= conv_std_logic_vector(626454,20);
WHEN "101011010" => data <= conv_std_logic_vector(625723,20);
WHEN "101011011" => data <= conv_std_logic_vector(624995,20);
WHEN "101011100" => data <= conv_std_logic_vector(624268,20);
WHEN "101011101" => data <= conv_std_logic_vector(623543,20);
WHEN "101011110" => data <= conv_std_logic_vector(622820,20);
WHEN "101011111" => data <= conv_std_logic_vector(622098,20);
WHEN "101100000" => data <= conv_std_logic_vector(621378,20);
WHEN "101100001" => data <= conv_std_logic_vector(620660,20);
WHEN "101100010" => data <= conv_std_logic_vector(619943,20);
WHEN "101100011" => data <= conv_std_logic_vector(619228,20);
WHEN "101100100" => data <= conv_std_logic_vector(618515,20);
WHEN "101100101" => data <= conv_std_logic_vector(617803,20);
WHEN "101100110" => data <= conv_std_logic_vector(617093,20);
WHEN "101100111" => data <= conv_std_logic_vector(616384,20);
WHEN "101101000" => data <= conv_std_logic_vector(615677,20);
WHEN "101101001" => data <= conv_std_logic_vector(614972,20);
WHEN "101101010" => data <= conv_std_logic_vector(614269,20);
WHEN "101101011" => data <= conv_std_logic_vector(613567,20);
WHEN "101101100" => data <= conv_std_logic_vector(612866,20);
WHEN "101101101" => data <= conv_std_logic_vector(612167,20);
WHEN "101101110" => data <= conv_std_logic_vector(611470,20);
WHEN "101101111" => data <= conv_std_logic_vector(610774,20);
WHEN "101110000" => data <= conv_std_logic_vector(610080,20);
WHEN "101110001" => data <= conv_std_logic_vector(609388,20);
WHEN "101110010" => data <= conv_std_logic_vector(608697,20);
WHEN "101110011" => data <= conv_std_logic_vector(608008,20);
WHEN "101110100" => data <= conv_std_logic_vector(607320,20);
WHEN "101110101" => data <= conv_std_logic_vector(606634,20);
WHEN "101110110" => data <= conv_std_logic_vector(605949,20);
WHEN "101110111" => data <= conv_std_logic_vector(605266,20);
WHEN "101111000" => data <= conv_std_logic_vector(604584,20);
WHEN "101111001" => data <= conv_std_logic_vector(603904,20);
WHEN "101111010" => data <= conv_std_logic_vector(603226,20);
WHEN "101111011" => data <= conv_std_logic_vector(602549,20);
WHEN "101111100" => data <= conv_std_logic_vector(601873,20);
WHEN "101111101" => data <= conv_std_logic_vector(601199,20);
WHEN "101111110" => data <= conv_std_logic_vector(600527,20);
WHEN "101111111" => data <= conv_std_logic_vector(599856,20);
WHEN "110000000" => data <= conv_std_logic_vector(599186,20);
WHEN "110000001" => data <= conv_std_logic_vector(598518,20);
WHEN "110000010" => data <= conv_std_logic_vector(597852,20);
WHEN "110000011" => data <= conv_std_logic_vector(597187,20);
WHEN "110000100" => data <= conv_std_logic_vector(596523,20);
WHEN "110000101" => data <= conv_std_logic_vector(595861,20);
WHEN "110000110" => data <= conv_std_logic_vector(595200,20);
WHEN "110000111" => data <= conv_std_logic_vector(594541,20);
WHEN "110001000" => data <= conv_std_logic_vector(593884,20);
WHEN "110001001" => data <= conv_std_logic_vector(593227,20);
WHEN "110001010" => data <= conv_std_logic_vector(592573,20);
WHEN "110001011" => data <= conv_std_logic_vector(591919,20);
WHEN "110001100" => data <= conv_std_logic_vector(591267,20);
WHEN "110001101" => data <= conv_std_logic_vector(590617,20);
WHEN "110001110" => data <= conv_std_logic_vector(589968,20);
WHEN "110001111" => data <= conv_std_logic_vector(589320,20);
WHEN "110010000" => data <= conv_std_logic_vector(588674,20);
WHEN "110010001" => data <= conv_std_logic_vector(588029,20);
WHEN "110010010" => data <= conv_std_logic_vector(587386,20);
WHEN "110010011" => data <= conv_std_logic_vector(586744,20);
WHEN "110010100" => data <= conv_std_logic_vector(586103,20);
WHEN "110010101" => data <= conv_std_logic_vector(585464,20);
WHEN "110010110" => data <= conv_std_logic_vector(584827,20);
WHEN "110010111" => data <= conv_std_logic_vector(584190,20);
WHEN "110011000" => data <= conv_std_logic_vector(583555,20);
WHEN "110011001" => data <= conv_std_logic_vector(582922,20);
WHEN "110011010" => data <= conv_std_logic_vector(582289,20);
WHEN "110011011" => data <= conv_std_logic_vector(581658,20);
WHEN "110011100" => data <= conv_std_logic_vector(581029,20);
WHEN "110011101" => data <= conv_std_logic_vector(580401,20);
WHEN "110011110" => data <= conv_std_logic_vector(579774,20);
WHEN "110011111" => data <= conv_std_logic_vector(579149,20);
WHEN "110100000" => data <= conv_std_logic_vector(578525,20);
WHEN "110100001" => data <= conv_std_logic_vector(577902,20);
WHEN "110100010" => data <= conv_std_logic_vector(577280,20);
WHEN "110100011" => data <= conv_std_logic_vector(576660,20);
WHEN "110100100" => data <= conv_std_logic_vector(576042,20);
WHEN "110100101" => data <= conv_std_logic_vector(575424,20);
WHEN "110100110" => data <= conv_std_logic_vector(574808,20);
WHEN "110100111" => data <= conv_std_logic_vector(574193,20);
WHEN "110101000" => data <= conv_std_logic_vector(573580,20);
WHEN "110101001" => data <= conv_std_logic_vector(572968,20);
WHEN "110101010" => data <= conv_std_logic_vector(572357,20);
WHEN "110101011" => data <= conv_std_logic_vector(571747,20);
WHEN "110101100" => data <= conv_std_logic_vector(571139,20);
WHEN "110101101" => data <= conv_std_logic_vector(570532,20);
WHEN "110101110" => data <= conv_std_logic_vector(569926,20);
WHEN "110101111" => data <= conv_std_logic_vector(569322,20);
WHEN "110110000" => data <= conv_std_logic_vector(568719,20);
WHEN "110110001" => data <= conv_std_logic_vector(568117,20);
WHEN "110110010" => data <= conv_std_logic_vector(567517,20);
WHEN "110110011" => data <= conv_std_logic_vector(566917,20);
WHEN "110110100" => data <= conv_std_logic_vector(566319,20);
WHEN "110110101" => data <= conv_std_logic_vector(565723,20);
WHEN "110110110" => data <= conv_std_logic_vector(565127,20);
WHEN "110110111" => data <= conv_std_logic_vector(564533,20);
WHEN "110111000" => data <= conv_std_logic_vector(563940,20);
WHEN "110111001" => data <= conv_std_logic_vector(563348,20);
WHEN "110111010" => data <= conv_std_logic_vector(562758,20);
WHEN "110111011" => data <= conv_std_logic_vector(562168,20);
WHEN "110111100" => data <= conv_std_logic_vector(561580,20);
WHEN "110111101" => data <= conv_std_logic_vector(560993,20);
WHEN "110111110" => data <= conv_std_logic_vector(560408,20);
WHEN "110111111" => data <= conv_std_logic_vector(559824,20);
WHEN "111000000" => data <= conv_std_logic_vector(559240,20);
WHEN "111000001" => data <= conv_std_logic_vector(558658,20);
WHEN "111000010" => data <= conv_std_logic_vector(558078,20);
WHEN "111000011" => data <= conv_std_logic_vector(557498,20);
WHEN "111000100" => data <= conv_std_logic_vector(556920,20);
WHEN "111000101" => data <= conv_std_logic_vector(556343,20);
WHEN "111000110" => data <= conv_std_logic_vector(555767,20);
WHEN "111000111" => data <= conv_std_logic_vector(555192,20);
WHEN "111001000" => data <= conv_std_logic_vector(554619,20);
WHEN "111001001" => data <= conv_std_logic_vector(554046,20);
WHEN "111001010" => data <= conv_std_logic_vector(553475,20);
WHEN "111001011" => data <= conv_std_logic_vector(552905,20);
WHEN "111001100" => data <= conv_std_logic_vector(552336,20);
WHEN "111001101" => data <= conv_std_logic_vector(551769,20);
WHEN "111001110" => data <= conv_std_logic_vector(551202,20);
WHEN "111001111" => data <= conv_std_logic_vector(550637,20);
WHEN "111010000" => data <= conv_std_logic_vector(550073,20);
WHEN "111010001" => data <= conv_std_logic_vector(549509,20);
WHEN "111010010" => data <= conv_std_logic_vector(548948,20);
WHEN "111010011" => data <= conv_std_logic_vector(548387,20);
WHEN "111010100" => data <= conv_std_logic_vector(547827,20);
WHEN "111010101" => data <= conv_std_logic_vector(547269,20);
WHEN "111010110" => data <= conv_std_logic_vector(546712,20);
WHEN "111010111" => data <= conv_std_logic_vector(546155,20);
WHEN "111011000" => data <= conv_std_logic_vector(545600,20);
WHEN "111011001" => data <= conv_std_logic_vector(545046,20);
WHEN "111011010" => data <= conv_std_logic_vector(544494,20);
WHEN "111011011" => data <= conv_std_logic_vector(543942,20);
WHEN "111011100" => data <= conv_std_logic_vector(543391,20);
WHEN "111011101" => data <= conv_std_logic_vector(542842,20);
WHEN "111011110" => data <= conv_std_logic_vector(542294,20);
WHEN "111011111" => data <= conv_std_logic_vector(541746,20);
WHEN "111100000" => data <= conv_std_logic_vector(541200,20);
WHEN "111100001" => data <= conv_std_logic_vector(540655,20);
WHEN "111100010" => data <= conv_std_logic_vector(540111,20);
WHEN "111100011" => data <= conv_std_logic_vector(539569,20);
WHEN "111100100" => data <= conv_std_logic_vector(539027,20);
WHEN "111100101" => data <= conv_std_logic_vector(538486,20);
WHEN "111100110" => data <= conv_std_logic_vector(537947,20);
WHEN "111100111" => data <= conv_std_logic_vector(537408,20);
WHEN "111101000" => data <= conv_std_logic_vector(536871,20);
WHEN "111101001" => data <= conv_std_logic_vector(536334,20);
WHEN "111101010" => data <= conv_std_logic_vector(535799,20);
WHEN "111101011" => data <= conv_std_logic_vector(535265,20);
WHEN "111101100" => data <= conv_std_logic_vector(534732,20);
WHEN "111101101" => data <= conv_std_logic_vector(534200,20);
WHEN "111101110" => data <= conv_std_logic_vector(533669,20);
WHEN "111101111" => data <= conv_std_logic_vector(533139,20);
WHEN "111110000" => data <= conv_std_logic_vector(532610,20);
WHEN "111110001" => data <= conv_std_logic_vector(532082,20);
WHEN "111110010" => data <= conv_std_logic_vector(531555,20);
WHEN "111110011" => data <= conv_std_logic_vector(531029,20);
WHEN "111110100" => data <= conv_std_logic_vector(530505,20);
WHEN "111110101" => data <= conv_std_logic_vector(529981,20);
WHEN "111110110" => data <= conv_std_logic_vector(529458,20);
WHEN "111110111" => data <= conv_std_logic_vector(528937,20);
WHEN "111111000" => data <= conv_std_logic_vector(528416,20);
WHEN "111111001" => data <= conv_std_logic_vector(527897,20);
WHEN "111111010" => data <= conv_std_logic_vector(527378,20);
WHEN "111111011" => data <= conv_std_logic_vector(526860,20);
WHEN "111111100" => data <= conv_std_logic_vector(526344,20);
WHEN "111111101" => data <= conv_std_logic_vector(525828,20);
WHEN "111111110" => data <= conv_std_logic_vector(525314,20);
WHEN "111111111" => data <= conv_std_logic_vector(524800,20);
WHEN others => data <= conv_std_logic_vector(0,20);
END CASE;
END PROCESS;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_DIV_LUT0.VHD ***
--*** ***
--*** Function: Look Up Table - Inverse ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_div_lut0 IS
PORT (
add : IN STD_LOGIC_VECTOR (9 DOWNTO 1);
data : OUT STD_LOGIC_VECTOR (20 DOWNTO 1)
);
END fp_div_lut0;
ARCHITECTURE rtl OF fp_div_lut0 IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "000000000" => data <= conv_std_logic_vector(1048575,20);
WHEN "000000001" => data <= conv_std_logic_vector(1046531,20);
WHEN "000000010" => data <= conv_std_logic_vector(1044495,20);
WHEN "000000011" => data <= conv_std_logic_vector(1042467,20);
WHEN "000000100" => data <= conv_std_logic_vector(1040447,20);
WHEN "000000101" => data <= conv_std_logic_vector(1038434,20);
WHEN "000000110" => data <= conv_std_logic_vector(1036429,20);
WHEN "000000111" => data <= conv_std_logic_vector(1034432,20);
WHEN "000001000" => data <= conv_std_logic_vector(1032443,20);
WHEN "000001001" => data <= conv_std_logic_vector(1030461,20);
WHEN "000001010" => data <= conv_std_logic_vector(1028487,20);
WHEN "000001011" => data <= conv_std_logic_vector(1026521,20);
WHEN "000001100" => data <= conv_std_logic_vector(1024562,20);
WHEN "000001101" => data <= conv_std_logic_vector(1022610,20);
WHEN "000001110" => data <= conv_std_logic_vector(1020666,20);
WHEN "000001111" => data <= conv_std_logic_vector(1018729,20);
WHEN "000010000" => data <= conv_std_logic_vector(1016800,20);
WHEN "000010001" => data <= conv_std_logic_vector(1014878,20);
WHEN "000010010" => data <= conv_std_logic_vector(1012963,20);
WHEN "000010011" => data <= conv_std_logic_vector(1011055,20);
WHEN "000010100" => data <= conv_std_logic_vector(1009155,20);
WHEN "000010101" => data <= conv_std_logic_vector(1007262,20);
WHEN "000010110" => data <= conv_std_logic_vector(1005375,20);
WHEN "000010111" => data <= conv_std_logic_vector(1003496,20);
WHEN "000011000" => data <= conv_std_logic_vector(1001624,20);
WHEN "000011001" => data <= conv_std_logic_vector(999759,20);
WHEN "000011010" => data <= conv_std_logic_vector(997900,20);
WHEN "000011011" => data <= conv_std_logic_vector(996049,20);
WHEN "000011100" => data <= conv_std_logic_vector(994205,20);
WHEN "000011101" => data <= conv_std_logic_vector(992367,20);
WHEN "000011110" => data <= conv_std_logic_vector(990536,20);
WHEN "000011111" => data <= conv_std_logic_vector(988712,20);
WHEN "000100000" => data <= conv_std_logic_vector(986894,20);
WHEN "000100001" => data <= conv_std_logic_vector(985083,20);
WHEN "000100010" => data <= conv_std_logic_vector(983279,20);
WHEN "000100011" => data <= conv_std_logic_vector(981482,20);
WHEN "000100100" => data <= conv_std_logic_vector(979691,20);
WHEN "000100101" => data <= conv_std_logic_vector(977906,20);
WHEN "000100110" => data <= conv_std_logic_vector(976128,20);
WHEN "000100111" => data <= conv_std_logic_vector(974357,20);
WHEN "000101000" => data <= conv_std_logic_vector(972591,20);
WHEN "000101001" => data <= conv_std_logic_vector(970833,20);
WHEN "000101010" => data <= conv_std_logic_vector(969080,20);
WHEN "000101011" => data <= conv_std_logic_vector(967334,20);
WHEN "000101100" => data <= conv_std_logic_vector(965594,20);
WHEN "000101101" => data <= conv_std_logic_vector(963861,20);
WHEN "000101110" => data <= conv_std_logic_vector(962133,20);
WHEN "000101111" => data <= conv_std_logic_vector(960412,20);
WHEN "000110000" => data <= conv_std_logic_vector(958697,20);
WHEN "000110001" => data <= conv_std_logic_vector(956988,20);
WHEN "000110010" => data <= conv_std_logic_vector(955286,20);
WHEN "000110011" => data <= conv_std_logic_vector(953589,20);
WHEN "000110100" => data <= conv_std_logic_vector(951898,20);
WHEN "000110101" => data <= conv_std_logic_vector(950213,20);
WHEN "000110110" => data <= conv_std_logic_vector(948534,20);
WHEN "000110111" => data <= conv_std_logic_vector(946862,20);
WHEN "000111000" => data <= conv_std_logic_vector(945195,20);
WHEN "000111001" => data <= conv_std_logic_vector(943533,20);
WHEN "000111010" => data <= conv_std_logic_vector(941878,20);
WHEN "000111011" => data <= conv_std_logic_vector(940229,20);
WHEN "000111100" => data <= conv_std_logic_vector(938585,20);
WHEN "000111101" => data <= conv_std_logic_vector(936947,20);
WHEN "000111110" => data <= conv_std_logic_vector(935314,20);
WHEN "000111111" => data <= conv_std_logic_vector(933688,20);
WHEN "001000000" => data <= conv_std_logic_vector(932067,20);
WHEN "001000001" => data <= conv_std_logic_vector(930451,20);
WHEN "001000010" => data <= conv_std_logic_vector(928842,20);
WHEN "001000011" => data <= conv_std_logic_vector(927237,20);
WHEN "001000100" => data <= conv_std_logic_vector(925639,20);
WHEN "001000101" => data <= conv_std_logic_vector(924046,20);
WHEN "001000110" => data <= conv_std_logic_vector(922458,20);
WHEN "001000111" => data <= conv_std_logic_vector(920876,20);
WHEN "001001000" => data <= conv_std_logic_vector(919299,20);
WHEN "001001001" => data <= conv_std_logic_vector(917727,20);
WHEN "001001010" => data <= conv_std_logic_vector(916161,20);
WHEN "001001011" => data <= conv_std_logic_vector(914601,20);
WHEN "001001100" => data <= conv_std_logic_vector(913045,20);
WHEN "001001101" => data <= conv_std_logic_vector(911495,20);
WHEN "001001110" => data <= conv_std_logic_vector(909950,20);
WHEN "001001111" => data <= conv_std_logic_vector(908410,20);
WHEN "001010000" => data <= conv_std_logic_vector(906876,20);
WHEN "001010001" => data <= conv_std_logic_vector(905347,20);
WHEN "001010010" => data <= conv_std_logic_vector(903822,20);
WHEN "001010011" => data <= conv_std_logic_vector(902303,20);
WHEN "001010100" => data <= conv_std_logic_vector(900789,20);
WHEN "001010101" => data <= conv_std_logic_vector(899281,20);
WHEN "001010110" => data <= conv_std_logic_vector(897777,20);
WHEN "001010111" => data <= conv_std_logic_vector(896278,20);
WHEN "001011000" => data <= conv_std_logic_vector(894784,20);
WHEN "001011001" => data <= conv_std_logic_vector(893295,20);
WHEN "001011010" => data <= conv_std_logic_vector(891812,20);
WHEN "001011011" => data <= conv_std_logic_vector(890333,20);
WHEN "001011100" => data <= conv_std_logic_vector(888859,20);
WHEN "001011101" => data <= conv_std_logic_vector(887389,20);
WHEN "001011110" => data <= conv_std_logic_vector(885925,20);
WHEN "001011111" => data <= conv_std_logic_vector(884465,20);
WHEN "001100000" => data <= conv_std_logic_vector(883011,20);
WHEN "001100001" => data <= conv_std_logic_vector(881561,20);
WHEN "001100010" => data <= conv_std_logic_vector(880116,20);
WHEN "001100011" => data <= conv_std_logic_vector(878675,20);
WHEN "001100100" => data <= conv_std_logic_vector(877239,20);
WHEN "001100101" => data <= conv_std_logic_vector(875808,20);
WHEN "001100110" => data <= conv_std_logic_vector(874382,20);
WHEN "001100111" => data <= conv_std_logic_vector(872960,20);
WHEN "001101000" => data <= conv_std_logic_vector(871543,20);
WHEN "001101001" => data <= conv_std_logic_vector(870131,20);
WHEN "001101010" => data <= conv_std_logic_vector(868723,20);
WHEN "001101011" => data <= conv_std_logic_vector(867319,20);
WHEN "001101100" => data <= conv_std_logic_vector(865920,20);
WHEN "001101101" => data <= conv_std_logic_vector(864526,20);
WHEN "001101110" => data <= conv_std_logic_vector(863136,20);
WHEN "001101111" => data <= conv_std_logic_vector(861751,20);
WHEN "001110000" => data <= conv_std_logic_vector(860369,20);
WHEN "001110001" => data <= conv_std_logic_vector(858993,20);
WHEN "001110010" => data <= conv_std_logic_vector(857621,20);
WHEN "001110011" => data <= conv_std_logic_vector(856253,20);
WHEN "001110100" => data <= conv_std_logic_vector(854889,20);
WHEN "001110101" => data <= conv_std_logic_vector(853530,20);
WHEN "001110110" => data <= conv_std_logic_vector(852176,20);
WHEN "001110111" => data <= conv_std_logic_vector(850825,20);
WHEN "001111000" => data <= conv_std_logic_vector(849479,20);
WHEN "001111001" => data <= conv_std_logic_vector(848137,20);
WHEN "001111010" => data <= conv_std_logic_vector(846799,20);
WHEN "001111011" => data <= conv_std_logic_vector(845465,20);
WHEN "001111100" => data <= conv_std_logic_vector(844136,20);
WHEN "001111101" => data <= conv_std_logic_vector(842811,20);
WHEN "001111110" => data <= conv_std_logic_vector(841490,20);
WHEN "001111111" => data <= conv_std_logic_vector(840173,20);
WHEN "010000000" => data <= conv_std_logic_vector(838860,20);
WHEN "010000001" => data <= conv_std_logic_vector(837552,20);
WHEN "010000010" => data <= conv_std_logic_vector(836247,20);
WHEN "010000011" => data <= conv_std_logic_vector(834946,20);
WHEN "010000100" => data <= conv_std_logic_vector(833650,20);
WHEN "010000101" => data <= conv_std_logic_vector(832358,20);
WHEN "010000110" => data <= conv_std_logic_vector(831069,20);
WHEN "010000111" => data <= conv_std_logic_vector(829785,20);
WHEN "010001000" => data <= conv_std_logic_vector(828504,20);
WHEN "010001001" => data <= conv_std_logic_vector(827227,20);
WHEN "010001010" => data <= conv_std_logic_vector(825955,20);
WHEN "010001011" => data <= conv_std_logic_vector(824686,20);
WHEN "010001100" => data <= conv_std_logic_vector(823421,20);
WHEN "010001101" => data <= conv_std_logic_vector(822160,20);
WHEN "010001110" => data <= conv_std_logic_vector(820903,20);
WHEN "010001111" => data <= conv_std_logic_vector(819650,20);
WHEN "010010000" => data <= conv_std_logic_vector(818400,20);
WHEN "010010001" => data <= conv_std_logic_vector(817155,20);
WHEN "010010010" => data <= conv_std_logic_vector(815913,20);
WHEN "010010011" => data <= conv_std_logic_vector(814675,20);
WHEN "010010100" => data <= conv_std_logic_vector(813440,20);
WHEN "010010101" => data <= conv_std_logic_vector(812210,20);
WHEN "010010110" => data <= conv_std_logic_vector(810983,20);
WHEN "010010111" => data <= conv_std_logic_vector(809760,20);
WHEN "010011000" => data <= conv_std_logic_vector(808540,20);
WHEN "010011001" => data <= conv_std_logic_vector(807324,20);
WHEN "010011010" => data <= conv_std_logic_vector(806112,20);
WHEN "010011011" => data <= conv_std_logic_vector(804903,20);
WHEN "010011100" => data <= conv_std_logic_vector(803699,20);
WHEN "010011101" => data <= conv_std_logic_vector(802497,20);
WHEN "010011110" => data <= conv_std_logic_vector(801299,20);
WHEN "010011111" => data <= conv_std_logic_vector(800105,20);
WHEN "010100000" => data <= conv_std_logic_vector(798915,20);
WHEN "010100001" => data <= conv_std_logic_vector(797728,20);
WHEN "010100010" => data <= conv_std_logic_vector(796544,20);
WHEN "010100011" => data <= conv_std_logic_vector(795364,20);
WHEN "010100100" => data <= conv_std_logic_vector(794187,20);
WHEN "010100101" => data <= conv_std_logic_vector(793014,20);
WHEN "010100110" => data <= conv_std_logic_vector(791845,20);
WHEN "010100111" => data <= conv_std_logic_vector(790678,20);
WHEN "010101000" => data <= conv_std_logic_vector(789516,20);
WHEN "010101001" => data <= conv_std_logic_vector(788356,20);
WHEN "010101010" => data <= conv_std_logic_vector(787200,20);
WHEN "010101011" => data <= conv_std_logic_vector(786048,20);
WHEN "010101100" => data <= conv_std_logic_vector(784899,20);
WHEN "010101101" => data <= conv_std_logic_vector(783753,20);
WHEN "010101110" => data <= conv_std_logic_vector(782610,20);
WHEN "010101111" => data <= conv_std_logic_vector(781471,20);
WHEN "010110000" => data <= conv_std_logic_vector(780335,20);
WHEN "010110001" => data <= conv_std_logic_vector(779203,20);
WHEN "010110010" => data <= conv_std_logic_vector(778073,20);
WHEN "010110011" => data <= conv_std_logic_vector(776947,20);
WHEN "010110100" => data <= conv_std_logic_vector(775825,20);
WHEN "010110101" => data <= conv_std_logic_vector(774705,20);
WHEN "010110110" => data <= conv_std_logic_vector(773589,20);
WHEN "010110111" => data <= conv_std_logic_vector(772476,20);
WHEN "010111000" => data <= conv_std_logic_vector(771366,20);
WHEN "010111001" => data <= conv_std_logic_vector(770259,20);
WHEN "010111010" => data <= conv_std_logic_vector(769156,20);
WHEN "010111011" => data <= conv_std_logic_vector(768055,20);
WHEN "010111100" => data <= conv_std_logic_vector(766958,20);
WHEN "010111101" => data <= conv_std_logic_vector(765864,20);
WHEN "010111110" => data <= conv_std_logic_vector(764773,20);
WHEN "010111111" => data <= conv_std_logic_vector(763685,20);
WHEN "011000000" => data <= conv_std_logic_vector(762600,20);
WHEN "011000001" => data <= conv_std_logic_vector(761519,20);
WHEN "011000010" => data <= conv_std_logic_vector(760440,20);
WHEN "011000011" => data <= conv_std_logic_vector(759364,20);
WHEN "011000100" => data <= conv_std_logic_vector(758292,20);
WHEN "011000101" => data <= conv_std_logic_vector(757222,20);
WHEN "011000110" => data <= conv_std_logic_vector(756156,20);
WHEN "011000111" => data <= conv_std_logic_vector(755092,20);
WHEN "011001000" => data <= conv_std_logic_vector(754032,20);
WHEN "011001001" => data <= conv_std_logic_vector(752974,20);
WHEN "011001010" => data <= conv_std_logic_vector(751920,20);
WHEN "011001011" => data <= conv_std_logic_vector(750868,20);
WHEN "011001100" => data <= conv_std_logic_vector(749819,20);
WHEN "011001101" => data <= conv_std_logic_vector(748774,20);
WHEN "011001110" => data <= conv_std_logic_vector(747731,20);
WHEN "011001111" => data <= conv_std_logic_vector(746691,20);
WHEN "011010000" => data <= conv_std_logic_vector(745654,20);
WHEN "011010001" => data <= conv_std_logic_vector(744619,20);
WHEN "011010010" => data <= conv_std_logic_vector(743588,20);
WHEN "011010011" => data <= conv_std_logic_vector(742560,20);
WHEN "011010100" => data <= conv_std_logic_vector(741534,20);
WHEN "011010101" => data <= conv_std_logic_vector(740511,20);
WHEN "011010110" => data <= conv_std_logic_vector(739491,20);
WHEN "011010111" => data <= conv_std_logic_vector(738474,20);
WHEN "011011000" => data <= conv_std_logic_vector(737460,20);
WHEN "011011001" => data <= conv_std_logic_vector(736448,20);
WHEN "011011010" => data <= conv_std_logic_vector(735439,20);
WHEN "011011011" => data <= conv_std_logic_vector(734433,20);
WHEN "011011100" => data <= conv_std_logic_vector(733430,20);
WHEN "011011101" => data <= conv_std_logic_vector(732429,20);
WHEN "011011110" => data <= conv_std_logic_vector(731431,20);
WHEN "011011111" => data <= conv_std_logic_vector(730436,20);
WHEN "011100000" => data <= conv_std_logic_vector(729444,20);
WHEN "011100001" => data <= conv_std_logic_vector(728454,20);
WHEN "011100010" => data <= conv_std_logic_vector(727467,20);
WHEN "011100011" => data <= conv_std_logic_vector(726483,20);
WHEN "011100100" => data <= conv_std_logic_vector(725501,20);
WHEN "011100101" => data <= conv_std_logic_vector(724522,20);
WHEN "011100110" => data <= conv_std_logic_vector(723545,20);
WHEN "011100111" => data <= conv_std_logic_vector(722572,20);
WHEN "011101000" => data <= conv_std_logic_vector(721600,20);
WHEN "011101001" => data <= conv_std_logic_vector(720632,20);
WHEN "011101010" => data <= conv_std_logic_vector(719666,20);
WHEN "011101011" => data <= conv_std_logic_vector(718702,20);
WHEN "011101100" => data <= conv_std_logic_vector(717742,20);
WHEN "011101101" => data <= conv_std_logic_vector(716783,20);
WHEN "011101110" => data <= conv_std_logic_vector(715828,20);
WHEN "011101111" => data <= conv_std_logic_vector(714874,20);
WHEN "011110000" => data <= conv_std_logic_vector(713924,20);
WHEN "011110001" => data <= conv_std_logic_vector(712976,20);
WHEN "011110010" => data <= conv_std_logic_vector(712030,20);
WHEN "011110011" => data <= conv_std_logic_vector(711087,20);
WHEN "011110100" => data <= conv_std_logic_vector(710146,20);
WHEN "011110101" => data <= conv_std_logic_vector(709208,20);
WHEN "011110110" => data <= conv_std_logic_vector(708273,20);
WHEN "011110111" => data <= conv_std_logic_vector(707339,20);
WHEN "011111000" => data <= conv_std_logic_vector(706409,20);
WHEN "011111001" => data <= conv_std_logic_vector(705481,20);
WHEN "011111010" => data <= conv_std_logic_vector(704555,20);
WHEN "011111011" => data <= conv_std_logic_vector(703631,20);
WHEN "011111100" => data <= conv_std_logic_vector(702710,20);
WHEN "011111101" => data <= conv_std_logic_vector(701792,20);
WHEN "011111110" => data <= conv_std_logic_vector(700876,20);
WHEN "011111111" => data <= conv_std_logic_vector(699962,20);
WHEN "100000000" => data <= conv_std_logic_vector(699050,20);
WHEN "100000001" => data <= conv_std_logic_vector(698141,20);
WHEN "100000010" => data <= conv_std_logic_vector(697235,20);
WHEN "100000011" => data <= conv_std_logic_vector(696330,20);
WHEN "100000100" => data <= conv_std_logic_vector(695428,20);
WHEN "100000101" => data <= conv_std_logic_vector(694529,20);
WHEN "100000110" => data <= conv_std_logic_vector(693631,20);
WHEN "100000111" => data <= conv_std_logic_vector(692736,20);
WHEN "100001000" => data <= conv_std_logic_vector(691844,20);
WHEN "100001001" => data <= conv_std_logic_vector(690953,20);
WHEN "100001010" => data <= conv_std_logic_vector(690065,20);
WHEN "100001011" => data <= conv_std_logic_vector(689179,20);
WHEN "100001100" => data <= conv_std_logic_vector(688296,20);
WHEN "100001101" => data <= conv_std_logic_vector(687414,20);
WHEN "100001110" => data <= conv_std_logic_vector(686535,20);
WHEN "100001111" => data <= conv_std_logic_vector(685659,20);
WHEN "100010000" => data <= conv_std_logic_vector(684784,20);
WHEN "100010001" => data <= conv_std_logic_vector(683912,20);
WHEN "100010010" => data <= conv_std_logic_vector(683042,20);
WHEN "100010011" => data <= conv_std_logic_vector(682174,20);
WHEN "100010100" => data <= conv_std_logic_vector(681308,20);
WHEN "100010101" => data <= conv_std_logic_vector(680444,20);
WHEN "100010110" => data <= conv_std_logic_vector(679583,20);
WHEN "100010111" => data <= conv_std_logic_vector(678724,20);
WHEN "100011000" => data <= conv_std_logic_vector(677867,20);
WHEN "100011001" => data <= conv_std_logic_vector(677012,20);
WHEN "100011010" => data <= conv_std_logic_vector(676160,20);
WHEN "100011011" => data <= conv_std_logic_vector(675309,20);
WHEN "100011100" => data <= conv_std_logic_vector(674461,20);
WHEN "100011101" => data <= conv_std_logic_vector(673614,20);
WHEN "100011110" => data <= conv_std_logic_vector(672770,20);
WHEN "100011111" => data <= conv_std_logic_vector(671928,20);
WHEN "100100000" => data <= conv_std_logic_vector(671088,20);
WHEN "100100001" => data <= conv_std_logic_vector(670251,20);
WHEN "100100010" => data <= conv_std_logic_vector(669415,20);
WHEN "100100011" => data <= conv_std_logic_vector(668581,20);
WHEN "100100100" => data <= conv_std_logic_vector(667750,20);
WHEN "100100101" => data <= conv_std_logic_vector(666920,20);
WHEN "100100110" => data <= conv_std_logic_vector(666093,20);
WHEN "100100111" => data <= conv_std_logic_vector(665267,20);
WHEN "100101000" => data <= conv_std_logic_vector(664444,20);
WHEN "100101001" => data <= conv_std_logic_vector(663623,20);
WHEN "100101010" => data <= conv_std_logic_vector(662803,20);
WHEN "100101011" => data <= conv_std_logic_vector(661986,20);
WHEN "100101100" => data <= conv_std_logic_vector(661171,20);
WHEN "100101101" => data <= conv_std_logic_vector(660358,20);
WHEN "100101110" => data <= conv_std_logic_vector(659546,20);
WHEN "100101111" => data <= conv_std_logic_vector(658737,20);
WHEN "100110000" => data <= conv_std_logic_vector(657930,20);
WHEN "100110001" => data <= conv_std_logic_vector(657124,20);
WHEN "100110010" => data <= conv_std_logic_vector(656321,20);
WHEN "100110011" => data <= conv_std_logic_vector(655520,20);
WHEN "100110100" => data <= conv_std_logic_vector(654720,20);
WHEN "100110101" => data <= conv_std_logic_vector(653923,20);
WHEN "100110110" => data <= conv_std_logic_vector(653127,20);
WHEN "100110111" => data <= conv_std_logic_vector(652334,20);
WHEN "100111000" => data <= conv_std_logic_vector(651542,20);
WHEN "100111001" => data <= conv_std_logic_vector(650752,20);
WHEN "100111010" => data <= conv_std_logic_vector(649965,20);
WHEN "100111011" => data <= conv_std_logic_vector(649179,20);
WHEN "100111100" => data <= conv_std_logic_vector(648395,20);
WHEN "100111101" => data <= conv_std_logic_vector(647612,20);
WHEN "100111110" => data <= conv_std_logic_vector(646832,20);
WHEN "100111111" => data <= conv_std_logic_vector(646054,20);
WHEN "101000000" => data <= conv_std_logic_vector(645277,20);
WHEN "101000001" => data <= conv_std_logic_vector(644503,20);
WHEN "101000010" => data <= conv_std_logic_vector(643730,20);
WHEN "101000011" => data <= conv_std_logic_vector(642959,20);
WHEN "101000100" => data <= conv_std_logic_vector(642190,20);
WHEN "101000101" => data <= conv_std_logic_vector(641423,20);
WHEN "101000110" => data <= conv_std_logic_vector(640657,20);
WHEN "101000111" => data <= conv_std_logic_vector(639894,20);
WHEN "101001000" => data <= conv_std_logic_vector(639132,20);
WHEN "101001001" => data <= conv_std_logic_vector(638372,20);
WHEN "101001010" => data <= conv_std_logic_vector(637614,20);
WHEN "101001011" => data <= conv_std_logic_vector(636857,20);
WHEN "101001100" => data <= conv_std_logic_vector(636103,20);
WHEN "101001101" => data <= conv_std_logic_vector(635350,20);
WHEN "101001110" => data <= conv_std_logic_vector(634599,20);
WHEN "101001111" => data <= conv_std_logic_vector(633850,20);
WHEN "101010000" => data <= conv_std_logic_vector(633102,20);
WHEN "101010001" => data <= conv_std_logic_vector(632357,20);
WHEN "101010010" => data <= conv_std_logic_vector(631613,20);
WHEN "101010011" => data <= conv_std_logic_vector(630870,20);
WHEN "101010100" => data <= conv_std_logic_vector(630130,20);
WHEN "101010101" => data <= conv_std_logic_vector(629391,20);
WHEN "101010110" => data <= conv_std_logic_vector(628654,20);
WHEN "101010111" => data <= conv_std_logic_vector(627919,20);
WHEN "101011000" => data <= conv_std_logic_vector(627185,20);
WHEN "101011001" => data <= conv_std_logic_vector(626454,20);
WHEN "101011010" => data <= conv_std_logic_vector(625723,20);
WHEN "101011011" => data <= conv_std_logic_vector(624995,20);
WHEN "101011100" => data <= conv_std_logic_vector(624268,20);
WHEN "101011101" => data <= conv_std_logic_vector(623543,20);
WHEN "101011110" => data <= conv_std_logic_vector(622820,20);
WHEN "101011111" => data <= conv_std_logic_vector(622098,20);
WHEN "101100000" => data <= conv_std_logic_vector(621378,20);
WHEN "101100001" => data <= conv_std_logic_vector(620660,20);
WHEN "101100010" => data <= conv_std_logic_vector(619943,20);
WHEN "101100011" => data <= conv_std_logic_vector(619228,20);
WHEN "101100100" => data <= conv_std_logic_vector(618515,20);
WHEN "101100101" => data <= conv_std_logic_vector(617803,20);
WHEN "101100110" => data <= conv_std_logic_vector(617093,20);
WHEN "101100111" => data <= conv_std_logic_vector(616384,20);
WHEN "101101000" => data <= conv_std_logic_vector(615677,20);
WHEN "101101001" => data <= conv_std_logic_vector(614972,20);
WHEN "101101010" => data <= conv_std_logic_vector(614269,20);
WHEN "101101011" => data <= conv_std_logic_vector(613567,20);
WHEN "101101100" => data <= conv_std_logic_vector(612866,20);
WHEN "101101101" => data <= conv_std_logic_vector(612167,20);
WHEN "101101110" => data <= conv_std_logic_vector(611470,20);
WHEN "101101111" => data <= conv_std_logic_vector(610774,20);
WHEN "101110000" => data <= conv_std_logic_vector(610080,20);
WHEN "101110001" => data <= conv_std_logic_vector(609388,20);
WHEN "101110010" => data <= conv_std_logic_vector(608697,20);
WHEN "101110011" => data <= conv_std_logic_vector(608008,20);
WHEN "101110100" => data <= conv_std_logic_vector(607320,20);
WHEN "101110101" => data <= conv_std_logic_vector(606634,20);
WHEN "101110110" => data <= conv_std_logic_vector(605949,20);
WHEN "101110111" => data <= conv_std_logic_vector(605266,20);
WHEN "101111000" => data <= conv_std_logic_vector(604584,20);
WHEN "101111001" => data <= conv_std_logic_vector(603904,20);
WHEN "101111010" => data <= conv_std_logic_vector(603226,20);
WHEN "101111011" => data <= conv_std_logic_vector(602549,20);
WHEN "101111100" => data <= conv_std_logic_vector(601873,20);
WHEN "101111101" => data <= conv_std_logic_vector(601199,20);
WHEN "101111110" => data <= conv_std_logic_vector(600527,20);
WHEN "101111111" => data <= conv_std_logic_vector(599856,20);
WHEN "110000000" => data <= conv_std_logic_vector(599186,20);
WHEN "110000001" => data <= conv_std_logic_vector(598518,20);
WHEN "110000010" => data <= conv_std_logic_vector(597852,20);
WHEN "110000011" => data <= conv_std_logic_vector(597187,20);
WHEN "110000100" => data <= conv_std_logic_vector(596523,20);
WHEN "110000101" => data <= conv_std_logic_vector(595861,20);
WHEN "110000110" => data <= conv_std_logic_vector(595200,20);
WHEN "110000111" => data <= conv_std_logic_vector(594541,20);
WHEN "110001000" => data <= conv_std_logic_vector(593884,20);
WHEN "110001001" => data <= conv_std_logic_vector(593227,20);
WHEN "110001010" => data <= conv_std_logic_vector(592573,20);
WHEN "110001011" => data <= conv_std_logic_vector(591919,20);
WHEN "110001100" => data <= conv_std_logic_vector(591267,20);
WHEN "110001101" => data <= conv_std_logic_vector(590617,20);
WHEN "110001110" => data <= conv_std_logic_vector(589968,20);
WHEN "110001111" => data <= conv_std_logic_vector(589320,20);
WHEN "110010000" => data <= conv_std_logic_vector(588674,20);
WHEN "110010001" => data <= conv_std_logic_vector(588029,20);
WHEN "110010010" => data <= conv_std_logic_vector(587386,20);
WHEN "110010011" => data <= conv_std_logic_vector(586744,20);
WHEN "110010100" => data <= conv_std_logic_vector(586103,20);
WHEN "110010101" => data <= conv_std_logic_vector(585464,20);
WHEN "110010110" => data <= conv_std_logic_vector(584827,20);
WHEN "110010111" => data <= conv_std_logic_vector(584190,20);
WHEN "110011000" => data <= conv_std_logic_vector(583555,20);
WHEN "110011001" => data <= conv_std_logic_vector(582922,20);
WHEN "110011010" => data <= conv_std_logic_vector(582289,20);
WHEN "110011011" => data <= conv_std_logic_vector(581658,20);
WHEN "110011100" => data <= conv_std_logic_vector(581029,20);
WHEN "110011101" => data <= conv_std_logic_vector(580401,20);
WHEN "110011110" => data <= conv_std_logic_vector(579774,20);
WHEN "110011111" => data <= conv_std_logic_vector(579149,20);
WHEN "110100000" => data <= conv_std_logic_vector(578525,20);
WHEN "110100001" => data <= conv_std_logic_vector(577902,20);
WHEN "110100010" => data <= conv_std_logic_vector(577280,20);
WHEN "110100011" => data <= conv_std_logic_vector(576660,20);
WHEN "110100100" => data <= conv_std_logic_vector(576042,20);
WHEN "110100101" => data <= conv_std_logic_vector(575424,20);
WHEN "110100110" => data <= conv_std_logic_vector(574808,20);
WHEN "110100111" => data <= conv_std_logic_vector(574193,20);
WHEN "110101000" => data <= conv_std_logic_vector(573580,20);
WHEN "110101001" => data <= conv_std_logic_vector(572968,20);
WHEN "110101010" => data <= conv_std_logic_vector(572357,20);
WHEN "110101011" => data <= conv_std_logic_vector(571747,20);
WHEN "110101100" => data <= conv_std_logic_vector(571139,20);
WHEN "110101101" => data <= conv_std_logic_vector(570532,20);
WHEN "110101110" => data <= conv_std_logic_vector(569926,20);
WHEN "110101111" => data <= conv_std_logic_vector(569322,20);
WHEN "110110000" => data <= conv_std_logic_vector(568719,20);
WHEN "110110001" => data <= conv_std_logic_vector(568117,20);
WHEN "110110010" => data <= conv_std_logic_vector(567517,20);
WHEN "110110011" => data <= conv_std_logic_vector(566917,20);
WHEN "110110100" => data <= conv_std_logic_vector(566319,20);
WHEN "110110101" => data <= conv_std_logic_vector(565723,20);
WHEN "110110110" => data <= conv_std_logic_vector(565127,20);
WHEN "110110111" => data <= conv_std_logic_vector(564533,20);
WHEN "110111000" => data <= conv_std_logic_vector(563940,20);
WHEN "110111001" => data <= conv_std_logic_vector(563348,20);
WHEN "110111010" => data <= conv_std_logic_vector(562758,20);
WHEN "110111011" => data <= conv_std_logic_vector(562168,20);
WHEN "110111100" => data <= conv_std_logic_vector(561580,20);
WHEN "110111101" => data <= conv_std_logic_vector(560993,20);
WHEN "110111110" => data <= conv_std_logic_vector(560408,20);
WHEN "110111111" => data <= conv_std_logic_vector(559824,20);
WHEN "111000000" => data <= conv_std_logic_vector(559240,20);
WHEN "111000001" => data <= conv_std_logic_vector(558658,20);
WHEN "111000010" => data <= conv_std_logic_vector(558078,20);
WHEN "111000011" => data <= conv_std_logic_vector(557498,20);
WHEN "111000100" => data <= conv_std_logic_vector(556920,20);
WHEN "111000101" => data <= conv_std_logic_vector(556343,20);
WHEN "111000110" => data <= conv_std_logic_vector(555767,20);
WHEN "111000111" => data <= conv_std_logic_vector(555192,20);
WHEN "111001000" => data <= conv_std_logic_vector(554619,20);
WHEN "111001001" => data <= conv_std_logic_vector(554046,20);
WHEN "111001010" => data <= conv_std_logic_vector(553475,20);
WHEN "111001011" => data <= conv_std_logic_vector(552905,20);
WHEN "111001100" => data <= conv_std_logic_vector(552336,20);
WHEN "111001101" => data <= conv_std_logic_vector(551769,20);
WHEN "111001110" => data <= conv_std_logic_vector(551202,20);
WHEN "111001111" => data <= conv_std_logic_vector(550637,20);
WHEN "111010000" => data <= conv_std_logic_vector(550073,20);
WHEN "111010001" => data <= conv_std_logic_vector(549509,20);
WHEN "111010010" => data <= conv_std_logic_vector(548948,20);
WHEN "111010011" => data <= conv_std_logic_vector(548387,20);
WHEN "111010100" => data <= conv_std_logic_vector(547827,20);
WHEN "111010101" => data <= conv_std_logic_vector(547269,20);
WHEN "111010110" => data <= conv_std_logic_vector(546712,20);
WHEN "111010111" => data <= conv_std_logic_vector(546155,20);
WHEN "111011000" => data <= conv_std_logic_vector(545600,20);
WHEN "111011001" => data <= conv_std_logic_vector(545046,20);
WHEN "111011010" => data <= conv_std_logic_vector(544494,20);
WHEN "111011011" => data <= conv_std_logic_vector(543942,20);
WHEN "111011100" => data <= conv_std_logic_vector(543391,20);
WHEN "111011101" => data <= conv_std_logic_vector(542842,20);
WHEN "111011110" => data <= conv_std_logic_vector(542294,20);
WHEN "111011111" => data <= conv_std_logic_vector(541746,20);
WHEN "111100000" => data <= conv_std_logic_vector(541200,20);
WHEN "111100001" => data <= conv_std_logic_vector(540655,20);
WHEN "111100010" => data <= conv_std_logic_vector(540111,20);
WHEN "111100011" => data <= conv_std_logic_vector(539569,20);
WHEN "111100100" => data <= conv_std_logic_vector(539027,20);
WHEN "111100101" => data <= conv_std_logic_vector(538486,20);
WHEN "111100110" => data <= conv_std_logic_vector(537947,20);
WHEN "111100111" => data <= conv_std_logic_vector(537408,20);
WHEN "111101000" => data <= conv_std_logic_vector(536871,20);
WHEN "111101001" => data <= conv_std_logic_vector(536334,20);
WHEN "111101010" => data <= conv_std_logic_vector(535799,20);
WHEN "111101011" => data <= conv_std_logic_vector(535265,20);
WHEN "111101100" => data <= conv_std_logic_vector(534732,20);
WHEN "111101101" => data <= conv_std_logic_vector(534200,20);
WHEN "111101110" => data <= conv_std_logic_vector(533669,20);
WHEN "111101111" => data <= conv_std_logic_vector(533139,20);
WHEN "111110000" => data <= conv_std_logic_vector(532610,20);
WHEN "111110001" => data <= conv_std_logic_vector(532082,20);
WHEN "111110010" => data <= conv_std_logic_vector(531555,20);
WHEN "111110011" => data <= conv_std_logic_vector(531029,20);
WHEN "111110100" => data <= conv_std_logic_vector(530505,20);
WHEN "111110101" => data <= conv_std_logic_vector(529981,20);
WHEN "111110110" => data <= conv_std_logic_vector(529458,20);
WHEN "111110111" => data <= conv_std_logic_vector(528937,20);
WHEN "111111000" => data <= conv_std_logic_vector(528416,20);
WHEN "111111001" => data <= conv_std_logic_vector(527897,20);
WHEN "111111010" => data <= conv_std_logic_vector(527378,20);
WHEN "111111011" => data <= conv_std_logic_vector(526860,20);
WHEN "111111100" => data <= conv_std_logic_vector(526344,20);
WHEN "111111101" => data <= conv_std_logic_vector(525828,20);
WHEN "111111110" => data <= conv_std_logic_vector(525314,20);
WHEN "111111111" => data <= conv_std_logic_vector(524800,20);
WHEN others => data <= conv_std_logic_vector(0,20);
END CASE;
END PROCESS;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_DIV_LUT0.VHD ***
--*** ***
--*** Function: Look Up Table - Inverse ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_div_lut0 IS
PORT (
add : IN STD_LOGIC_VECTOR (9 DOWNTO 1);
data : OUT STD_LOGIC_VECTOR (20 DOWNTO 1)
);
END fp_div_lut0;
ARCHITECTURE rtl OF fp_div_lut0 IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "000000000" => data <= conv_std_logic_vector(1048575,20);
WHEN "000000001" => data <= conv_std_logic_vector(1046531,20);
WHEN "000000010" => data <= conv_std_logic_vector(1044495,20);
WHEN "000000011" => data <= conv_std_logic_vector(1042467,20);
WHEN "000000100" => data <= conv_std_logic_vector(1040447,20);
WHEN "000000101" => data <= conv_std_logic_vector(1038434,20);
WHEN "000000110" => data <= conv_std_logic_vector(1036429,20);
WHEN "000000111" => data <= conv_std_logic_vector(1034432,20);
WHEN "000001000" => data <= conv_std_logic_vector(1032443,20);
WHEN "000001001" => data <= conv_std_logic_vector(1030461,20);
WHEN "000001010" => data <= conv_std_logic_vector(1028487,20);
WHEN "000001011" => data <= conv_std_logic_vector(1026521,20);
WHEN "000001100" => data <= conv_std_logic_vector(1024562,20);
WHEN "000001101" => data <= conv_std_logic_vector(1022610,20);
WHEN "000001110" => data <= conv_std_logic_vector(1020666,20);
WHEN "000001111" => data <= conv_std_logic_vector(1018729,20);
WHEN "000010000" => data <= conv_std_logic_vector(1016800,20);
WHEN "000010001" => data <= conv_std_logic_vector(1014878,20);
WHEN "000010010" => data <= conv_std_logic_vector(1012963,20);
WHEN "000010011" => data <= conv_std_logic_vector(1011055,20);
WHEN "000010100" => data <= conv_std_logic_vector(1009155,20);
WHEN "000010101" => data <= conv_std_logic_vector(1007262,20);
WHEN "000010110" => data <= conv_std_logic_vector(1005375,20);
WHEN "000010111" => data <= conv_std_logic_vector(1003496,20);
WHEN "000011000" => data <= conv_std_logic_vector(1001624,20);
WHEN "000011001" => data <= conv_std_logic_vector(999759,20);
WHEN "000011010" => data <= conv_std_logic_vector(997900,20);
WHEN "000011011" => data <= conv_std_logic_vector(996049,20);
WHEN "000011100" => data <= conv_std_logic_vector(994205,20);
WHEN "000011101" => data <= conv_std_logic_vector(992367,20);
WHEN "000011110" => data <= conv_std_logic_vector(990536,20);
WHEN "000011111" => data <= conv_std_logic_vector(988712,20);
WHEN "000100000" => data <= conv_std_logic_vector(986894,20);
WHEN "000100001" => data <= conv_std_logic_vector(985083,20);
WHEN "000100010" => data <= conv_std_logic_vector(983279,20);
WHEN "000100011" => data <= conv_std_logic_vector(981482,20);
WHEN "000100100" => data <= conv_std_logic_vector(979691,20);
WHEN "000100101" => data <= conv_std_logic_vector(977906,20);
WHEN "000100110" => data <= conv_std_logic_vector(976128,20);
WHEN "000100111" => data <= conv_std_logic_vector(974357,20);
WHEN "000101000" => data <= conv_std_logic_vector(972591,20);
WHEN "000101001" => data <= conv_std_logic_vector(970833,20);
WHEN "000101010" => data <= conv_std_logic_vector(969080,20);
WHEN "000101011" => data <= conv_std_logic_vector(967334,20);
WHEN "000101100" => data <= conv_std_logic_vector(965594,20);
WHEN "000101101" => data <= conv_std_logic_vector(963861,20);
WHEN "000101110" => data <= conv_std_logic_vector(962133,20);
WHEN "000101111" => data <= conv_std_logic_vector(960412,20);
WHEN "000110000" => data <= conv_std_logic_vector(958697,20);
WHEN "000110001" => data <= conv_std_logic_vector(956988,20);
WHEN "000110010" => data <= conv_std_logic_vector(955286,20);
WHEN "000110011" => data <= conv_std_logic_vector(953589,20);
WHEN "000110100" => data <= conv_std_logic_vector(951898,20);
WHEN "000110101" => data <= conv_std_logic_vector(950213,20);
WHEN "000110110" => data <= conv_std_logic_vector(948534,20);
WHEN "000110111" => data <= conv_std_logic_vector(946862,20);
WHEN "000111000" => data <= conv_std_logic_vector(945195,20);
WHEN "000111001" => data <= conv_std_logic_vector(943533,20);
WHEN "000111010" => data <= conv_std_logic_vector(941878,20);
WHEN "000111011" => data <= conv_std_logic_vector(940229,20);
WHEN "000111100" => data <= conv_std_logic_vector(938585,20);
WHEN "000111101" => data <= conv_std_logic_vector(936947,20);
WHEN "000111110" => data <= conv_std_logic_vector(935314,20);
WHEN "000111111" => data <= conv_std_logic_vector(933688,20);
WHEN "001000000" => data <= conv_std_logic_vector(932067,20);
WHEN "001000001" => data <= conv_std_logic_vector(930451,20);
WHEN "001000010" => data <= conv_std_logic_vector(928842,20);
WHEN "001000011" => data <= conv_std_logic_vector(927237,20);
WHEN "001000100" => data <= conv_std_logic_vector(925639,20);
WHEN "001000101" => data <= conv_std_logic_vector(924046,20);
WHEN "001000110" => data <= conv_std_logic_vector(922458,20);
WHEN "001000111" => data <= conv_std_logic_vector(920876,20);
WHEN "001001000" => data <= conv_std_logic_vector(919299,20);
WHEN "001001001" => data <= conv_std_logic_vector(917727,20);
WHEN "001001010" => data <= conv_std_logic_vector(916161,20);
WHEN "001001011" => data <= conv_std_logic_vector(914601,20);
WHEN "001001100" => data <= conv_std_logic_vector(913045,20);
WHEN "001001101" => data <= conv_std_logic_vector(911495,20);
WHEN "001001110" => data <= conv_std_logic_vector(909950,20);
WHEN "001001111" => data <= conv_std_logic_vector(908410,20);
WHEN "001010000" => data <= conv_std_logic_vector(906876,20);
WHEN "001010001" => data <= conv_std_logic_vector(905347,20);
WHEN "001010010" => data <= conv_std_logic_vector(903822,20);
WHEN "001010011" => data <= conv_std_logic_vector(902303,20);
WHEN "001010100" => data <= conv_std_logic_vector(900789,20);
WHEN "001010101" => data <= conv_std_logic_vector(899281,20);
WHEN "001010110" => data <= conv_std_logic_vector(897777,20);
WHEN "001010111" => data <= conv_std_logic_vector(896278,20);
WHEN "001011000" => data <= conv_std_logic_vector(894784,20);
WHEN "001011001" => data <= conv_std_logic_vector(893295,20);
WHEN "001011010" => data <= conv_std_logic_vector(891812,20);
WHEN "001011011" => data <= conv_std_logic_vector(890333,20);
WHEN "001011100" => data <= conv_std_logic_vector(888859,20);
WHEN "001011101" => data <= conv_std_logic_vector(887389,20);
WHEN "001011110" => data <= conv_std_logic_vector(885925,20);
WHEN "001011111" => data <= conv_std_logic_vector(884465,20);
WHEN "001100000" => data <= conv_std_logic_vector(883011,20);
WHEN "001100001" => data <= conv_std_logic_vector(881561,20);
WHEN "001100010" => data <= conv_std_logic_vector(880116,20);
WHEN "001100011" => data <= conv_std_logic_vector(878675,20);
WHEN "001100100" => data <= conv_std_logic_vector(877239,20);
WHEN "001100101" => data <= conv_std_logic_vector(875808,20);
WHEN "001100110" => data <= conv_std_logic_vector(874382,20);
WHEN "001100111" => data <= conv_std_logic_vector(872960,20);
WHEN "001101000" => data <= conv_std_logic_vector(871543,20);
WHEN "001101001" => data <= conv_std_logic_vector(870131,20);
WHEN "001101010" => data <= conv_std_logic_vector(868723,20);
WHEN "001101011" => data <= conv_std_logic_vector(867319,20);
WHEN "001101100" => data <= conv_std_logic_vector(865920,20);
WHEN "001101101" => data <= conv_std_logic_vector(864526,20);
WHEN "001101110" => data <= conv_std_logic_vector(863136,20);
WHEN "001101111" => data <= conv_std_logic_vector(861751,20);
WHEN "001110000" => data <= conv_std_logic_vector(860369,20);
WHEN "001110001" => data <= conv_std_logic_vector(858993,20);
WHEN "001110010" => data <= conv_std_logic_vector(857621,20);
WHEN "001110011" => data <= conv_std_logic_vector(856253,20);
WHEN "001110100" => data <= conv_std_logic_vector(854889,20);
WHEN "001110101" => data <= conv_std_logic_vector(853530,20);
WHEN "001110110" => data <= conv_std_logic_vector(852176,20);
WHEN "001110111" => data <= conv_std_logic_vector(850825,20);
WHEN "001111000" => data <= conv_std_logic_vector(849479,20);
WHEN "001111001" => data <= conv_std_logic_vector(848137,20);
WHEN "001111010" => data <= conv_std_logic_vector(846799,20);
WHEN "001111011" => data <= conv_std_logic_vector(845465,20);
WHEN "001111100" => data <= conv_std_logic_vector(844136,20);
WHEN "001111101" => data <= conv_std_logic_vector(842811,20);
WHEN "001111110" => data <= conv_std_logic_vector(841490,20);
WHEN "001111111" => data <= conv_std_logic_vector(840173,20);
WHEN "010000000" => data <= conv_std_logic_vector(838860,20);
WHEN "010000001" => data <= conv_std_logic_vector(837552,20);
WHEN "010000010" => data <= conv_std_logic_vector(836247,20);
WHEN "010000011" => data <= conv_std_logic_vector(834946,20);
WHEN "010000100" => data <= conv_std_logic_vector(833650,20);
WHEN "010000101" => data <= conv_std_logic_vector(832358,20);
WHEN "010000110" => data <= conv_std_logic_vector(831069,20);
WHEN "010000111" => data <= conv_std_logic_vector(829785,20);
WHEN "010001000" => data <= conv_std_logic_vector(828504,20);
WHEN "010001001" => data <= conv_std_logic_vector(827227,20);
WHEN "010001010" => data <= conv_std_logic_vector(825955,20);
WHEN "010001011" => data <= conv_std_logic_vector(824686,20);
WHEN "010001100" => data <= conv_std_logic_vector(823421,20);
WHEN "010001101" => data <= conv_std_logic_vector(822160,20);
WHEN "010001110" => data <= conv_std_logic_vector(820903,20);
WHEN "010001111" => data <= conv_std_logic_vector(819650,20);
WHEN "010010000" => data <= conv_std_logic_vector(818400,20);
WHEN "010010001" => data <= conv_std_logic_vector(817155,20);
WHEN "010010010" => data <= conv_std_logic_vector(815913,20);
WHEN "010010011" => data <= conv_std_logic_vector(814675,20);
WHEN "010010100" => data <= conv_std_logic_vector(813440,20);
WHEN "010010101" => data <= conv_std_logic_vector(812210,20);
WHEN "010010110" => data <= conv_std_logic_vector(810983,20);
WHEN "010010111" => data <= conv_std_logic_vector(809760,20);
WHEN "010011000" => data <= conv_std_logic_vector(808540,20);
WHEN "010011001" => data <= conv_std_logic_vector(807324,20);
WHEN "010011010" => data <= conv_std_logic_vector(806112,20);
WHEN "010011011" => data <= conv_std_logic_vector(804903,20);
WHEN "010011100" => data <= conv_std_logic_vector(803699,20);
WHEN "010011101" => data <= conv_std_logic_vector(802497,20);
WHEN "010011110" => data <= conv_std_logic_vector(801299,20);
WHEN "010011111" => data <= conv_std_logic_vector(800105,20);
WHEN "010100000" => data <= conv_std_logic_vector(798915,20);
WHEN "010100001" => data <= conv_std_logic_vector(797728,20);
WHEN "010100010" => data <= conv_std_logic_vector(796544,20);
WHEN "010100011" => data <= conv_std_logic_vector(795364,20);
WHEN "010100100" => data <= conv_std_logic_vector(794187,20);
WHEN "010100101" => data <= conv_std_logic_vector(793014,20);
WHEN "010100110" => data <= conv_std_logic_vector(791845,20);
WHEN "010100111" => data <= conv_std_logic_vector(790678,20);
WHEN "010101000" => data <= conv_std_logic_vector(789516,20);
WHEN "010101001" => data <= conv_std_logic_vector(788356,20);
WHEN "010101010" => data <= conv_std_logic_vector(787200,20);
WHEN "010101011" => data <= conv_std_logic_vector(786048,20);
WHEN "010101100" => data <= conv_std_logic_vector(784899,20);
WHEN "010101101" => data <= conv_std_logic_vector(783753,20);
WHEN "010101110" => data <= conv_std_logic_vector(782610,20);
WHEN "010101111" => data <= conv_std_logic_vector(781471,20);
WHEN "010110000" => data <= conv_std_logic_vector(780335,20);
WHEN "010110001" => data <= conv_std_logic_vector(779203,20);
WHEN "010110010" => data <= conv_std_logic_vector(778073,20);
WHEN "010110011" => data <= conv_std_logic_vector(776947,20);
WHEN "010110100" => data <= conv_std_logic_vector(775825,20);
WHEN "010110101" => data <= conv_std_logic_vector(774705,20);
WHEN "010110110" => data <= conv_std_logic_vector(773589,20);
WHEN "010110111" => data <= conv_std_logic_vector(772476,20);
WHEN "010111000" => data <= conv_std_logic_vector(771366,20);
WHEN "010111001" => data <= conv_std_logic_vector(770259,20);
WHEN "010111010" => data <= conv_std_logic_vector(769156,20);
WHEN "010111011" => data <= conv_std_logic_vector(768055,20);
WHEN "010111100" => data <= conv_std_logic_vector(766958,20);
WHEN "010111101" => data <= conv_std_logic_vector(765864,20);
WHEN "010111110" => data <= conv_std_logic_vector(764773,20);
WHEN "010111111" => data <= conv_std_logic_vector(763685,20);
WHEN "011000000" => data <= conv_std_logic_vector(762600,20);
WHEN "011000001" => data <= conv_std_logic_vector(761519,20);
WHEN "011000010" => data <= conv_std_logic_vector(760440,20);
WHEN "011000011" => data <= conv_std_logic_vector(759364,20);
WHEN "011000100" => data <= conv_std_logic_vector(758292,20);
WHEN "011000101" => data <= conv_std_logic_vector(757222,20);
WHEN "011000110" => data <= conv_std_logic_vector(756156,20);
WHEN "011000111" => data <= conv_std_logic_vector(755092,20);
WHEN "011001000" => data <= conv_std_logic_vector(754032,20);
WHEN "011001001" => data <= conv_std_logic_vector(752974,20);
WHEN "011001010" => data <= conv_std_logic_vector(751920,20);
WHEN "011001011" => data <= conv_std_logic_vector(750868,20);
WHEN "011001100" => data <= conv_std_logic_vector(749819,20);
WHEN "011001101" => data <= conv_std_logic_vector(748774,20);
WHEN "011001110" => data <= conv_std_logic_vector(747731,20);
WHEN "011001111" => data <= conv_std_logic_vector(746691,20);
WHEN "011010000" => data <= conv_std_logic_vector(745654,20);
WHEN "011010001" => data <= conv_std_logic_vector(744619,20);
WHEN "011010010" => data <= conv_std_logic_vector(743588,20);
WHEN "011010011" => data <= conv_std_logic_vector(742560,20);
WHEN "011010100" => data <= conv_std_logic_vector(741534,20);
WHEN "011010101" => data <= conv_std_logic_vector(740511,20);
WHEN "011010110" => data <= conv_std_logic_vector(739491,20);
WHEN "011010111" => data <= conv_std_logic_vector(738474,20);
WHEN "011011000" => data <= conv_std_logic_vector(737460,20);
WHEN "011011001" => data <= conv_std_logic_vector(736448,20);
WHEN "011011010" => data <= conv_std_logic_vector(735439,20);
WHEN "011011011" => data <= conv_std_logic_vector(734433,20);
WHEN "011011100" => data <= conv_std_logic_vector(733430,20);
WHEN "011011101" => data <= conv_std_logic_vector(732429,20);
WHEN "011011110" => data <= conv_std_logic_vector(731431,20);
WHEN "011011111" => data <= conv_std_logic_vector(730436,20);
WHEN "011100000" => data <= conv_std_logic_vector(729444,20);
WHEN "011100001" => data <= conv_std_logic_vector(728454,20);
WHEN "011100010" => data <= conv_std_logic_vector(727467,20);
WHEN "011100011" => data <= conv_std_logic_vector(726483,20);
WHEN "011100100" => data <= conv_std_logic_vector(725501,20);
WHEN "011100101" => data <= conv_std_logic_vector(724522,20);
WHEN "011100110" => data <= conv_std_logic_vector(723545,20);
WHEN "011100111" => data <= conv_std_logic_vector(722572,20);
WHEN "011101000" => data <= conv_std_logic_vector(721600,20);
WHEN "011101001" => data <= conv_std_logic_vector(720632,20);
WHEN "011101010" => data <= conv_std_logic_vector(719666,20);
WHEN "011101011" => data <= conv_std_logic_vector(718702,20);
WHEN "011101100" => data <= conv_std_logic_vector(717742,20);
WHEN "011101101" => data <= conv_std_logic_vector(716783,20);
WHEN "011101110" => data <= conv_std_logic_vector(715828,20);
WHEN "011101111" => data <= conv_std_logic_vector(714874,20);
WHEN "011110000" => data <= conv_std_logic_vector(713924,20);
WHEN "011110001" => data <= conv_std_logic_vector(712976,20);
WHEN "011110010" => data <= conv_std_logic_vector(712030,20);
WHEN "011110011" => data <= conv_std_logic_vector(711087,20);
WHEN "011110100" => data <= conv_std_logic_vector(710146,20);
WHEN "011110101" => data <= conv_std_logic_vector(709208,20);
WHEN "011110110" => data <= conv_std_logic_vector(708273,20);
WHEN "011110111" => data <= conv_std_logic_vector(707339,20);
WHEN "011111000" => data <= conv_std_logic_vector(706409,20);
WHEN "011111001" => data <= conv_std_logic_vector(705481,20);
WHEN "011111010" => data <= conv_std_logic_vector(704555,20);
WHEN "011111011" => data <= conv_std_logic_vector(703631,20);
WHEN "011111100" => data <= conv_std_logic_vector(702710,20);
WHEN "011111101" => data <= conv_std_logic_vector(701792,20);
WHEN "011111110" => data <= conv_std_logic_vector(700876,20);
WHEN "011111111" => data <= conv_std_logic_vector(699962,20);
WHEN "100000000" => data <= conv_std_logic_vector(699050,20);
WHEN "100000001" => data <= conv_std_logic_vector(698141,20);
WHEN "100000010" => data <= conv_std_logic_vector(697235,20);
WHEN "100000011" => data <= conv_std_logic_vector(696330,20);
WHEN "100000100" => data <= conv_std_logic_vector(695428,20);
WHEN "100000101" => data <= conv_std_logic_vector(694529,20);
WHEN "100000110" => data <= conv_std_logic_vector(693631,20);
WHEN "100000111" => data <= conv_std_logic_vector(692736,20);
WHEN "100001000" => data <= conv_std_logic_vector(691844,20);
WHEN "100001001" => data <= conv_std_logic_vector(690953,20);
WHEN "100001010" => data <= conv_std_logic_vector(690065,20);
WHEN "100001011" => data <= conv_std_logic_vector(689179,20);
WHEN "100001100" => data <= conv_std_logic_vector(688296,20);
WHEN "100001101" => data <= conv_std_logic_vector(687414,20);
WHEN "100001110" => data <= conv_std_logic_vector(686535,20);
WHEN "100001111" => data <= conv_std_logic_vector(685659,20);
WHEN "100010000" => data <= conv_std_logic_vector(684784,20);
WHEN "100010001" => data <= conv_std_logic_vector(683912,20);
WHEN "100010010" => data <= conv_std_logic_vector(683042,20);
WHEN "100010011" => data <= conv_std_logic_vector(682174,20);
WHEN "100010100" => data <= conv_std_logic_vector(681308,20);
WHEN "100010101" => data <= conv_std_logic_vector(680444,20);
WHEN "100010110" => data <= conv_std_logic_vector(679583,20);
WHEN "100010111" => data <= conv_std_logic_vector(678724,20);
WHEN "100011000" => data <= conv_std_logic_vector(677867,20);
WHEN "100011001" => data <= conv_std_logic_vector(677012,20);
WHEN "100011010" => data <= conv_std_logic_vector(676160,20);
WHEN "100011011" => data <= conv_std_logic_vector(675309,20);
WHEN "100011100" => data <= conv_std_logic_vector(674461,20);
WHEN "100011101" => data <= conv_std_logic_vector(673614,20);
WHEN "100011110" => data <= conv_std_logic_vector(672770,20);
WHEN "100011111" => data <= conv_std_logic_vector(671928,20);
WHEN "100100000" => data <= conv_std_logic_vector(671088,20);
WHEN "100100001" => data <= conv_std_logic_vector(670251,20);
WHEN "100100010" => data <= conv_std_logic_vector(669415,20);
WHEN "100100011" => data <= conv_std_logic_vector(668581,20);
WHEN "100100100" => data <= conv_std_logic_vector(667750,20);
WHEN "100100101" => data <= conv_std_logic_vector(666920,20);
WHEN "100100110" => data <= conv_std_logic_vector(666093,20);
WHEN "100100111" => data <= conv_std_logic_vector(665267,20);
WHEN "100101000" => data <= conv_std_logic_vector(664444,20);
WHEN "100101001" => data <= conv_std_logic_vector(663623,20);
WHEN "100101010" => data <= conv_std_logic_vector(662803,20);
WHEN "100101011" => data <= conv_std_logic_vector(661986,20);
WHEN "100101100" => data <= conv_std_logic_vector(661171,20);
WHEN "100101101" => data <= conv_std_logic_vector(660358,20);
WHEN "100101110" => data <= conv_std_logic_vector(659546,20);
WHEN "100101111" => data <= conv_std_logic_vector(658737,20);
WHEN "100110000" => data <= conv_std_logic_vector(657930,20);
WHEN "100110001" => data <= conv_std_logic_vector(657124,20);
WHEN "100110010" => data <= conv_std_logic_vector(656321,20);
WHEN "100110011" => data <= conv_std_logic_vector(655520,20);
WHEN "100110100" => data <= conv_std_logic_vector(654720,20);
WHEN "100110101" => data <= conv_std_logic_vector(653923,20);
WHEN "100110110" => data <= conv_std_logic_vector(653127,20);
WHEN "100110111" => data <= conv_std_logic_vector(652334,20);
WHEN "100111000" => data <= conv_std_logic_vector(651542,20);
WHEN "100111001" => data <= conv_std_logic_vector(650752,20);
WHEN "100111010" => data <= conv_std_logic_vector(649965,20);
WHEN "100111011" => data <= conv_std_logic_vector(649179,20);
WHEN "100111100" => data <= conv_std_logic_vector(648395,20);
WHEN "100111101" => data <= conv_std_logic_vector(647612,20);
WHEN "100111110" => data <= conv_std_logic_vector(646832,20);
WHEN "100111111" => data <= conv_std_logic_vector(646054,20);
WHEN "101000000" => data <= conv_std_logic_vector(645277,20);
WHEN "101000001" => data <= conv_std_logic_vector(644503,20);
WHEN "101000010" => data <= conv_std_logic_vector(643730,20);
WHEN "101000011" => data <= conv_std_logic_vector(642959,20);
WHEN "101000100" => data <= conv_std_logic_vector(642190,20);
WHEN "101000101" => data <= conv_std_logic_vector(641423,20);
WHEN "101000110" => data <= conv_std_logic_vector(640657,20);
WHEN "101000111" => data <= conv_std_logic_vector(639894,20);
WHEN "101001000" => data <= conv_std_logic_vector(639132,20);
WHEN "101001001" => data <= conv_std_logic_vector(638372,20);
WHEN "101001010" => data <= conv_std_logic_vector(637614,20);
WHEN "101001011" => data <= conv_std_logic_vector(636857,20);
WHEN "101001100" => data <= conv_std_logic_vector(636103,20);
WHEN "101001101" => data <= conv_std_logic_vector(635350,20);
WHEN "101001110" => data <= conv_std_logic_vector(634599,20);
WHEN "101001111" => data <= conv_std_logic_vector(633850,20);
WHEN "101010000" => data <= conv_std_logic_vector(633102,20);
WHEN "101010001" => data <= conv_std_logic_vector(632357,20);
WHEN "101010010" => data <= conv_std_logic_vector(631613,20);
WHEN "101010011" => data <= conv_std_logic_vector(630870,20);
WHEN "101010100" => data <= conv_std_logic_vector(630130,20);
WHEN "101010101" => data <= conv_std_logic_vector(629391,20);
WHEN "101010110" => data <= conv_std_logic_vector(628654,20);
WHEN "101010111" => data <= conv_std_logic_vector(627919,20);
WHEN "101011000" => data <= conv_std_logic_vector(627185,20);
WHEN "101011001" => data <= conv_std_logic_vector(626454,20);
WHEN "101011010" => data <= conv_std_logic_vector(625723,20);
WHEN "101011011" => data <= conv_std_logic_vector(624995,20);
WHEN "101011100" => data <= conv_std_logic_vector(624268,20);
WHEN "101011101" => data <= conv_std_logic_vector(623543,20);
WHEN "101011110" => data <= conv_std_logic_vector(622820,20);
WHEN "101011111" => data <= conv_std_logic_vector(622098,20);
WHEN "101100000" => data <= conv_std_logic_vector(621378,20);
WHEN "101100001" => data <= conv_std_logic_vector(620660,20);
WHEN "101100010" => data <= conv_std_logic_vector(619943,20);
WHEN "101100011" => data <= conv_std_logic_vector(619228,20);
WHEN "101100100" => data <= conv_std_logic_vector(618515,20);
WHEN "101100101" => data <= conv_std_logic_vector(617803,20);
WHEN "101100110" => data <= conv_std_logic_vector(617093,20);
WHEN "101100111" => data <= conv_std_logic_vector(616384,20);
WHEN "101101000" => data <= conv_std_logic_vector(615677,20);
WHEN "101101001" => data <= conv_std_logic_vector(614972,20);
WHEN "101101010" => data <= conv_std_logic_vector(614269,20);
WHEN "101101011" => data <= conv_std_logic_vector(613567,20);
WHEN "101101100" => data <= conv_std_logic_vector(612866,20);
WHEN "101101101" => data <= conv_std_logic_vector(612167,20);
WHEN "101101110" => data <= conv_std_logic_vector(611470,20);
WHEN "101101111" => data <= conv_std_logic_vector(610774,20);
WHEN "101110000" => data <= conv_std_logic_vector(610080,20);
WHEN "101110001" => data <= conv_std_logic_vector(609388,20);
WHEN "101110010" => data <= conv_std_logic_vector(608697,20);
WHEN "101110011" => data <= conv_std_logic_vector(608008,20);
WHEN "101110100" => data <= conv_std_logic_vector(607320,20);
WHEN "101110101" => data <= conv_std_logic_vector(606634,20);
WHEN "101110110" => data <= conv_std_logic_vector(605949,20);
WHEN "101110111" => data <= conv_std_logic_vector(605266,20);
WHEN "101111000" => data <= conv_std_logic_vector(604584,20);
WHEN "101111001" => data <= conv_std_logic_vector(603904,20);
WHEN "101111010" => data <= conv_std_logic_vector(603226,20);
WHEN "101111011" => data <= conv_std_logic_vector(602549,20);
WHEN "101111100" => data <= conv_std_logic_vector(601873,20);
WHEN "101111101" => data <= conv_std_logic_vector(601199,20);
WHEN "101111110" => data <= conv_std_logic_vector(600527,20);
WHEN "101111111" => data <= conv_std_logic_vector(599856,20);
WHEN "110000000" => data <= conv_std_logic_vector(599186,20);
WHEN "110000001" => data <= conv_std_logic_vector(598518,20);
WHEN "110000010" => data <= conv_std_logic_vector(597852,20);
WHEN "110000011" => data <= conv_std_logic_vector(597187,20);
WHEN "110000100" => data <= conv_std_logic_vector(596523,20);
WHEN "110000101" => data <= conv_std_logic_vector(595861,20);
WHEN "110000110" => data <= conv_std_logic_vector(595200,20);
WHEN "110000111" => data <= conv_std_logic_vector(594541,20);
WHEN "110001000" => data <= conv_std_logic_vector(593884,20);
WHEN "110001001" => data <= conv_std_logic_vector(593227,20);
WHEN "110001010" => data <= conv_std_logic_vector(592573,20);
WHEN "110001011" => data <= conv_std_logic_vector(591919,20);
WHEN "110001100" => data <= conv_std_logic_vector(591267,20);
WHEN "110001101" => data <= conv_std_logic_vector(590617,20);
WHEN "110001110" => data <= conv_std_logic_vector(589968,20);
WHEN "110001111" => data <= conv_std_logic_vector(589320,20);
WHEN "110010000" => data <= conv_std_logic_vector(588674,20);
WHEN "110010001" => data <= conv_std_logic_vector(588029,20);
WHEN "110010010" => data <= conv_std_logic_vector(587386,20);
WHEN "110010011" => data <= conv_std_logic_vector(586744,20);
WHEN "110010100" => data <= conv_std_logic_vector(586103,20);
WHEN "110010101" => data <= conv_std_logic_vector(585464,20);
WHEN "110010110" => data <= conv_std_logic_vector(584827,20);
WHEN "110010111" => data <= conv_std_logic_vector(584190,20);
WHEN "110011000" => data <= conv_std_logic_vector(583555,20);
WHEN "110011001" => data <= conv_std_logic_vector(582922,20);
WHEN "110011010" => data <= conv_std_logic_vector(582289,20);
WHEN "110011011" => data <= conv_std_logic_vector(581658,20);
WHEN "110011100" => data <= conv_std_logic_vector(581029,20);
WHEN "110011101" => data <= conv_std_logic_vector(580401,20);
WHEN "110011110" => data <= conv_std_logic_vector(579774,20);
WHEN "110011111" => data <= conv_std_logic_vector(579149,20);
WHEN "110100000" => data <= conv_std_logic_vector(578525,20);
WHEN "110100001" => data <= conv_std_logic_vector(577902,20);
WHEN "110100010" => data <= conv_std_logic_vector(577280,20);
WHEN "110100011" => data <= conv_std_logic_vector(576660,20);
WHEN "110100100" => data <= conv_std_logic_vector(576042,20);
WHEN "110100101" => data <= conv_std_logic_vector(575424,20);
WHEN "110100110" => data <= conv_std_logic_vector(574808,20);
WHEN "110100111" => data <= conv_std_logic_vector(574193,20);
WHEN "110101000" => data <= conv_std_logic_vector(573580,20);
WHEN "110101001" => data <= conv_std_logic_vector(572968,20);
WHEN "110101010" => data <= conv_std_logic_vector(572357,20);
WHEN "110101011" => data <= conv_std_logic_vector(571747,20);
WHEN "110101100" => data <= conv_std_logic_vector(571139,20);
WHEN "110101101" => data <= conv_std_logic_vector(570532,20);
WHEN "110101110" => data <= conv_std_logic_vector(569926,20);
WHEN "110101111" => data <= conv_std_logic_vector(569322,20);
WHEN "110110000" => data <= conv_std_logic_vector(568719,20);
WHEN "110110001" => data <= conv_std_logic_vector(568117,20);
WHEN "110110010" => data <= conv_std_logic_vector(567517,20);
WHEN "110110011" => data <= conv_std_logic_vector(566917,20);
WHEN "110110100" => data <= conv_std_logic_vector(566319,20);
WHEN "110110101" => data <= conv_std_logic_vector(565723,20);
WHEN "110110110" => data <= conv_std_logic_vector(565127,20);
WHEN "110110111" => data <= conv_std_logic_vector(564533,20);
WHEN "110111000" => data <= conv_std_logic_vector(563940,20);
WHEN "110111001" => data <= conv_std_logic_vector(563348,20);
WHEN "110111010" => data <= conv_std_logic_vector(562758,20);
WHEN "110111011" => data <= conv_std_logic_vector(562168,20);
WHEN "110111100" => data <= conv_std_logic_vector(561580,20);
WHEN "110111101" => data <= conv_std_logic_vector(560993,20);
WHEN "110111110" => data <= conv_std_logic_vector(560408,20);
WHEN "110111111" => data <= conv_std_logic_vector(559824,20);
WHEN "111000000" => data <= conv_std_logic_vector(559240,20);
WHEN "111000001" => data <= conv_std_logic_vector(558658,20);
WHEN "111000010" => data <= conv_std_logic_vector(558078,20);
WHEN "111000011" => data <= conv_std_logic_vector(557498,20);
WHEN "111000100" => data <= conv_std_logic_vector(556920,20);
WHEN "111000101" => data <= conv_std_logic_vector(556343,20);
WHEN "111000110" => data <= conv_std_logic_vector(555767,20);
WHEN "111000111" => data <= conv_std_logic_vector(555192,20);
WHEN "111001000" => data <= conv_std_logic_vector(554619,20);
WHEN "111001001" => data <= conv_std_logic_vector(554046,20);
WHEN "111001010" => data <= conv_std_logic_vector(553475,20);
WHEN "111001011" => data <= conv_std_logic_vector(552905,20);
WHEN "111001100" => data <= conv_std_logic_vector(552336,20);
WHEN "111001101" => data <= conv_std_logic_vector(551769,20);
WHEN "111001110" => data <= conv_std_logic_vector(551202,20);
WHEN "111001111" => data <= conv_std_logic_vector(550637,20);
WHEN "111010000" => data <= conv_std_logic_vector(550073,20);
WHEN "111010001" => data <= conv_std_logic_vector(549509,20);
WHEN "111010010" => data <= conv_std_logic_vector(548948,20);
WHEN "111010011" => data <= conv_std_logic_vector(548387,20);
WHEN "111010100" => data <= conv_std_logic_vector(547827,20);
WHEN "111010101" => data <= conv_std_logic_vector(547269,20);
WHEN "111010110" => data <= conv_std_logic_vector(546712,20);
WHEN "111010111" => data <= conv_std_logic_vector(546155,20);
WHEN "111011000" => data <= conv_std_logic_vector(545600,20);
WHEN "111011001" => data <= conv_std_logic_vector(545046,20);
WHEN "111011010" => data <= conv_std_logic_vector(544494,20);
WHEN "111011011" => data <= conv_std_logic_vector(543942,20);
WHEN "111011100" => data <= conv_std_logic_vector(543391,20);
WHEN "111011101" => data <= conv_std_logic_vector(542842,20);
WHEN "111011110" => data <= conv_std_logic_vector(542294,20);
WHEN "111011111" => data <= conv_std_logic_vector(541746,20);
WHEN "111100000" => data <= conv_std_logic_vector(541200,20);
WHEN "111100001" => data <= conv_std_logic_vector(540655,20);
WHEN "111100010" => data <= conv_std_logic_vector(540111,20);
WHEN "111100011" => data <= conv_std_logic_vector(539569,20);
WHEN "111100100" => data <= conv_std_logic_vector(539027,20);
WHEN "111100101" => data <= conv_std_logic_vector(538486,20);
WHEN "111100110" => data <= conv_std_logic_vector(537947,20);
WHEN "111100111" => data <= conv_std_logic_vector(537408,20);
WHEN "111101000" => data <= conv_std_logic_vector(536871,20);
WHEN "111101001" => data <= conv_std_logic_vector(536334,20);
WHEN "111101010" => data <= conv_std_logic_vector(535799,20);
WHEN "111101011" => data <= conv_std_logic_vector(535265,20);
WHEN "111101100" => data <= conv_std_logic_vector(534732,20);
WHEN "111101101" => data <= conv_std_logic_vector(534200,20);
WHEN "111101110" => data <= conv_std_logic_vector(533669,20);
WHEN "111101111" => data <= conv_std_logic_vector(533139,20);
WHEN "111110000" => data <= conv_std_logic_vector(532610,20);
WHEN "111110001" => data <= conv_std_logic_vector(532082,20);
WHEN "111110010" => data <= conv_std_logic_vector(531555,20);
WHEN "111110011" => data <= conv_std_logic_vector(531029,20);
WHEN "111110100" => data <= conv_std_logic_vector(530505,20);
WHEN "111110101" => data <= conv_std_logic_vector(529981,20);
WHEN "111110110" => data <= conv_std_logic_vector(529458,20);
WHEN "111110111" => data <= conv_std_logic_vector(528937,20);
WHEN "111111000" => data <= conv_std_logic_vector(528416,20);
WHEN "111111001" => data <= conv_std_logic_vector(527897,20);
WHEN "111111010" => data <= conv_std_logic_vector(527378,20);
WHEN "111111011" => data <= conv_std_logic_vector(526860,20);
WHEN "111111100" => data <= conv_std_logic_vector(526344,20);
WHEN "111111101" => data <= conv_std_logic_vector(525828,20);
WHEN "111111110" => data <= conv_std_logic_vector(525314,20);
WHEN "111111111" => data <= conv_std_logic_vector(524800,20);
WHEN others => data <= conv_std_logic_vector(0,20);
END CASE;
END PROCESS;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_DIV_LUT0.VHD ***
--*** ***
--*** Function: Look Up Table - Inverse ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_div_lut0 IS
PORT (
add : IN STD_LOGIC_VECTOR (9 DOWNTO 1);
data : OUT STD_LOGIC_VECTOR (20 DOWNTO 1)
);
END fp_div_lut0;
ARCHITECTURE rtl OF fp_div_lut0 IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "000000000" => data <= conv_std_logic_vector(1048575,20);
WHEN "000000001" => data <= conv_std_logic_vector(1046531,20);
WHEN "000000010" => data <= conv_std_logic_vector(1044495,20);
WHEN "000000011" => data <= conv_std_logic_vector(1042467,20);
WHEN "000000100" => data <= conv_std_logic_vector(1040447,20);
WHEN "000000101" => data <= conv_std_logic_vector(1038434,20);
WHEN "000000110" => data <= conv_std_logic_vector(1036429,20);
WHEN "000000111" => data <= conv_std_logic_vector(1034432,20);
WHEN "000001000" => data <= conv_std_logic_vector(1032443,20);
WHEN "000001001" => data <= conv_std_logic_vector(1030461,20);
WHEN "000001010" => data <= conv_std_logic_vector(1028487,20);
WHEN "000001011" => data <= conv_std_logic_vector(1026521,20);
WHEN "000001100" => data <= conv_std_logic_vector(1024562,20);
WHEN "000001101" => data <= conv_std_logic_vector(1022610,20);
WHEN "000001110" => data <= conv_std_logic_vector(1020666,20);
WHEN "000001111" => data <= conv_std_logic_vector(1018729,20);
WHEN "000010000" => data <= conv_std_logic_vector(1016800,20);
WHEN "000010001" => data <= conv_std_logic_vector(1014878,20);
WHEN "000010010" => data <= conv_std_logic_vector(1012963,20);
WHEN "000010011" => data <= conv_std_logic_vector(1011055,20);
WHEN "000010100" => data <= conv_std_logic_vector(1009155,20);
WHEN "000010101" => data <= conv_std_logic_vector(1007262,20);
WHEN "000010110" => data <= conv_std_logic_vector(1005375,20);
WHEN "000010111" => data <= conv_std_logic_vector(1003496,20);
WHEN "000011000" => data <= conv_std_logic_vector(1001624,20);
WHEN "000011001" => data <= conv_std_logic_vector(999759,20);
WHEN "000011010" => data <= conv_std_logic_vector(997900,20);
WHEN "000011011" => data <= conv_std_logic_vector(996049,20);
WHEN "000011100" => data <= conv_std_logic_vector(994205,20);
WHEN "000011101" => data <= conv_std_logic_vector(992367,20);
WHEN "000011110" => data <= conv_std_logic_vector(990536,20);
WHEN "000011111" => data <= conv_std_logic_vector(988712,20);
WHEN "000100000" => data <= conv_std_logic_vector(986894,20);
WHEN "000100001" => data <= conv_std_logic_vector(985083,20);
WHEN "000100010" => data <= conv_std_logic_vector(983279,20);
WHEN "000100011" => data <= conv_std_logic_vector(981482,20);
WHEN "000100100" => data <= conv_std_logic_vector(979691,20);
WHEN "000100101" => data <= conv_std_logic_vector(977906,20);
WHEN "000100110" => data <= conv_std_logic_vector(976128,20);
WHEN "000100111" => data <= conv_std_logic_vector(974357,20);
WHEN "000101000" => data <= conv_std_logic_vector(972591,20);
WHEN "000101001" => data <= conv_std_logic_vector(970833,20);
WHEN "000101010" => data <= conv_std_logic_vector(969080,20);
WHEN "000101011" => data <= conv_std_logic_vector(967334,20);
WHEN "000101100" => data <= conv_std_logic_vector(965594,20);
WHEN "000101101" => data <= conv_std_logic_vector(963861,20);
WHEN "000101110" => data <= conv_std_logic_vector(962133,20);
WHEN "000101111" => data <= conv_std_logic_vector(960412,20);
WHEN "000110000" => data <= conv_std_logic_vector(958697,20);
WHEN "000110001" => data <= conv_std_logic_vector(956988,20);
WHEN "000110010" => data <= conv_std_logic_vector(955286,20);
WHEN "000110011" => data <= conv_std_logic_vector(953589,20);
WHEN "000110100" => data <= conv_std_logic_vector(951898,20);
WHEN "000110101" => data <= conv_std_logic_vector(950213,20);
WHEN "000110110" => data <= conv_std_logic_vector(948534,20);
WHEN "000110111" => data <= conv_std_logic_vector(946862,20);
WHEN "000111000" => data <= conv_std_logic_vector(945195,20);
WHEN "000111001" => data <= conv_std_logic_vector(943533,20);
WHEN "000111010" => data <= conv_std_logic_vector(941878,20);
WHEN "000111011" => data <= conv_std_logic_vector(940229,20);
WHEN "000111100" => data <= conv_std_logic_vector(938585,20);
WHEN "000111101" => data <= conv_std_logic_vector(936947,20);
WHEN "000111110" => data <= conv_std_logic_vector(935314,20);
WHEN "000111111" => data <= conv_std_logic_vector(933688,20);
WHEN "001000000" => data <= conv_std_logic_vector(932067,20);
WHEN "001000001" => data <= conv_std_logic_vector(930451,20);
WHEN "001000010" => data <= conv_std_logic_vector(928842,20);
WHEN "001000011" => data <= conv_std_logic_vector(927237,20);
WHEN "001000100" => data <= conv_std_logic_vector(925639,20);
WHEN "001000101" => data <= conv_std_logic_vector(924046,20);
WHEN "001000110" => data <= conv_std_logic_vector(922458,20);
WHEN "001000111" => data <= conv_std_logic_vector(920876,20);
WHEN "001001000" => data <= conv_std_logic_vector(919299,20);
WHEN "001001001" => data <= conv_std_logic_vector(917727,20);
WHEN "001001010" => data <= conv_std_logic_vector(916161,20);
WHEN "001001011" => data <= conv_std_logic_vector(914601,20);
WHEN "001001100" => data <= conv_std_logic_vector(913045,20);
WHEN "001001101" => data <= conv_std_logic_vector(911495,20);
WHEN "001001110" => data <= conv_std_logic_vector(909950,20);
WHEN "001001111" => data <= conv_std_logic_vector(908410,20);
WHEN "001010000" => data <= conv_std_logic_vector(906876,20);
WHEN "001010001" => data <= conv_std_logic_vector(905347,20);
WHEN "001010010" => data <= conv_std_logic_vector(903822,20);
WHEN "001010011" => data <= conv_std_logic_vector(902303,20);
WHEN "001010100" => data <= conv_std_logic_vector(900789,20);
WHEN "001010101" => data <= conv_std_logic_vector(899281,20);
WHEN "001010110" => data <= conv_std_logic_vector(897777,20);
WHEN "001010111" => data <= conv_std_logic_vector(896278,20);
WHEN "001011000" => data <= conv_std_logic_vector(894784,20);
WHEN "001011001" => data <= conv_std_logic_vector(893295,20);
WHEN "001011010" => data <= conv_std_logic_vector(891812,20);
WHEN "001011011" => data <= conv_std_logic_vector(890333,20);
WHEN "001011100" => data <= conv_std_logic_vector(888859,20);
WHEN "001011101" => data <= conv_std_logic_vector(887389,20);
WHEN "001011110" => data <= conv_std_logic_vector(885925,20);
WHEN "001011111" => data <= conv_std_logic_vector(884465,20);
WHEN "001100000" => data <= conv_std_logic_vector(883011,20);
WHEN "001100001" => data <= conv_std_logic_vector(881561,20);
WHEN "001100010" => data <= conv_std_logic_vector(880116,20);
WHEN "001100011" => data <= conv_std_logic_vector(878675,20);
WHEN "001100100" => data <= conv_std_logic_vector(877239,20);
WHEN "001100101" => data <= conv_std_logic_vector(875808,20);
WHEN "001100110" => data <= conv_std_logic_vector(874382,20);
WHEN "001100111" => data <= conv_std_logic_vector(872960,20);
WHEN "001101000" => data <= conv_std_logic_vector(871543,20);
WHEN "001101001" => data <= conv_std_logic_vector(870131,20);
WHEN "001101010" => data <= conv_std_logic_vector(868723,20);
WHEN "001101011" => data <= conv_std_logic_vector(867319,20);
WHEN "001101100" => data <= conv_std_logic_vector(865920,20);
WHEN "001101101" => data <= conv_std_logic_vector(864526,20);
WHEN "001101110" => data <= conv_std_logic_vector(863136,20);
WHEN "001101111" => data <= conv_std_logic_vector(861751,20);
WHEN "001110000" => data <= conv_std_logic_vector(860369,20);
WHEN "001110001" => data <= conv_std_logic_vector(858993,20);
WHEN "001110010" => data <= conv_std_logic_vector(857621,20);
WHEN "001110011" => data <= conv_std_logic_vector(856253,20);
WHEN "001110100" => data <= conv_std_logic_vector(854889,20);
WHEN "001110101" => data <= conv_std_logic_vector(853530,20);
WHEN "001110110" => data <= conv_std_logic_vector(852176,20);
WHEN "001110111" => data <= conv_std_logic_vector(850825,20);
WHEN "001111000" => data <= conv_std_logic_vector(849479,20);
WHEN "001111001" => data <= conv_std_logic_vector(848137,20);
WHEN "001111010" => data <= conv_std_logic_vector(846799,20);
WHEN "001111011" => data <= conv_std_logic_vector(845465,20);
WHEN "001111100" => data <= conv_std_logic_vector(844136,20);
WHEN "001111101" => data <= conv_std_logic_vector(842811,20);
WHEN "001111110" => data <= conv_std_logic_vector(841490,20);
WHEN "001111111" => data <= conv_std_logic_vector(840173,20);
WHEN "010000000" => data <= conv_std_logic_vector(838860,20);
WHEN "010000001" => data <= conv_std_logic_vector(837552,20);
WHEN "010000010" => data <= conv_std_logic_vector(836247,20);
WHEN "010000011" => data <= conv_std_logic_vector(834946,20);
WHEN "010000100" => data <= conv_std_logic_vector(833650,20);
WHEN "010000101" => data <= conv_std_logic_vector(832358,20);
WHEN "010000110" => data <= conv_std_logic_vector(831069,20);
WHEN "010000111" => data <= conv_std_logic_vector(829785,20);
WHEN "010001000" => data <= conv_std_logic_vector(828504,20);
WHEN "010001001" => data <= conv_std_logic_vector(827227,20);
WHEN "010001010" => data <= conv_std_logic_vector(825955,20);
WHEN "010001011" => data <= conv_std_logic_vector(824686,20);
WHEN "010001100" => data <= conv_std_logic_vector(823421,20);
WHEN "010001101" => data <= conv_std_logic_vector(822160,20);
WHEN "010001110" => data <= conv_std_logic_vector(820903,20);
WHEN "010001111" => data <= conv_std_logic_vector(819650,20);
WHEN "010010000" => data <= conv_std_logic_vector(818400,20);
WHEN "010010001" => data <= conv_std_logic_vector(817155,20);
WHEN "010010010" => data <= conv_std_logic_vector(815913,20);
WHEN "010010011" => data <= conv_std_logic_vector(814675,20);
WHEN "010010100" => data <= conv_std_logic_vector(813440,20);
WHEN "010010101" => data <= conv_std_logic_vector(812210,20);
WHEN "010010110" => data <= conv_std_logic_vector(810983,20);
WHEN "010010111" => data <= conv_std_logic_vector(809760,20);
WHEN "010011000" => data <= conv_std_logic_vector(808540,20);
WHEN "010011001" => data <= conv_std_logic_vector(807324,20);
WHEN "010011010" => data <= conv_std_logic_vector(806112,20);
WHEN "010011011" => data <= conv_std_logic_vector(804903,20);
WHEN "010011100" => data <= conv_std_logic_vector(803699,20);
WHEN "010011101" => data <= conv_std_logic_vector(802497,20);
WHEN "010011110" => data <= conv_std_logic_vector(801299,20);
WHEN "010011111" => data <= conv_std_logic_vector(800105,20);
WHEN "010100000" => data <= conv_std_logic_vector(798915,20);
WHEN "010100001" => data <= conv_std_logic_vector(797728,20);
WHEN "010100010" => data <= conv_std_logic_vector(796544,20);
WHEN "010100011" => data <= conv_std_logic_vector(795364,20);
WHEN "010100100" => data <= conv_std_logic_vector(794187,20);
WHEN "010100101" => data <= conv_std_logic_vector(793014,20);
WHEN "010100110" => data <= conv_std_logic_vector(791845,20);
WHEN "010100111" => data <= conv_std_logic_vector(790678,20);
WHEN "010101000" => data <= conv_std_logic_vector(789516,20);
WHEN "010101001" => data <= conv_std_logic_vector(788356,20);
WHEN "010101010" => data <= conv_std_logic_vector(787200,20);
WHEN "010101011" => data <= conv_std_logic_vector(786048,20);
WHEN "010101100" => data <= conv_std_logic_vector(784899,20);
WHEN "010101101" => data <= conv_std_logic_vector(783753,20);
WHEN "010101110" => data <= conv_std_logic_vector(782610,20);
WHEN "010101111" => data <= conv_std_logic_vector(781471,20);
WHEN "010110000" => data <= conv_std_logic_vector(780335,20);
WHEN "010110001" => data <= conv_std_logic_vector(779203,20);
WHEN "010110010" => data <= conv_std_logic_vector(778073,20);
WHEN "010110011" => data <= conv_std_logic_vector(776947,20);
WHEN "010110100" => data <= conv_std_logic_vector(775825,20);
WHEN "010110101" => data <= conv_std_logic_vector(774705,20);
WHEN "010110110" => data <= conv_std_logic_vector(773589,20);
WHEN "010110111" => data <= conv_std_logic_vector(772476,20);
WHEN "010111000" => data <= conv_std_logic_vector(771366,20);
WHEN "010111001" => data <= conv_std_logic_vector(770259,20);
WHEN "010111010" => data <= conv_std_logic_vector(769156,20);
WHEN "010111011" => data <= conv_std_logic_vector(768055,20);
WHEN "010111100" => data <= conv_std_logic_vector(766958,20);
WHEN "010111101" => data <= conv_std_logic_vector(765864,20);
WHEN "010111110" => data <= conv_std_logic_vector(764773,20);
WHEN "010111111" => data <= conv_std_logic_vector(763685,20);
WHEN "011000000" => data <= conv_std_logic_vector(762600,20);
WHEN "011000001" => data <= conv_std_logic_vector(761519,20);
WHEN "011000010" => data <= conv_std_logic_vector(760440,20);
WHEN "011000011" => data <= conv_std_logic_vector(759364,20);
WHEN "011000100" => data <= conv_std_logic_vector(758292,20);
WHEN "011000101" => data <= conv_std_logic_vector(757222,20);
WHEN "011000110" => data <= conv_std_logic_vector(756156,20);
WHEN "011000111" => data <= conv_std_logic_vector(755092,20);
WHEN "011001000" => data <= conv_std_logic_vector(754032,20);
WHEN "011001001" => data <= conv_std_logic_vector(752974,20);
WHEN "011001010" => data <= conv_std_logic_vector(751920,20);
WHEN "011001011" => data <= conv_std_logic_vector(750868,20);
WHEN "011001100" => data <= conv_std_logic_vector(749819,20);
WHEN "011001101" => data <= conv_std_logic_vector(748774,20);
WHEN "011001110" => data <= conv_std_logic_vector(747731,20);
WHEN "011001111" => data <= conv_std_logic_vector(746691,20);
WHEN "011010000" => data <= conv_std_logic_vector(745654,20);
WHEN "011010001" => data <= conv_std_logic_vector(744619,20);
WHEN "011010010" => data <= conv_std_logic_vector(743588,20);
WHEN "011010011" => data <= conv_std_logic_vector(742560,20);
WHEN "011010100" => data <= conv_std_logic_vector(741534,20);
WHEN "011010101" => data <= conv_std_logic_vector(740511,20);
WHEN "011010110" => data <= conv_std_logic_vector(739491,20);
WHEN "011010111" => data <= conv_std_logic_vector(738474,20);
WHEN "011011000" => data <= conv_std_logic_vector(737460,20);
WHEN "011011001" => data <= conv_std_logic_vector(736448,20);
WHEN "011011010" => data <= conv_std_logic_vector(735439,20);
WHEN "011011011" => data <= conv_std_logic_vector(734433,20);
WHEN "011011100" => data <= conv_std_logic_vector(733430,20);
WHEN "011011101" => data <= conv_std_logic_vector(732429,20);
WHEN "011011110" => data <= conv_std_logic_vector(731431,20);
WHEN "011011111" => data <= conv_std_logic_vector(730436,20);
WHEN "011100000" => data <= conv_std_logic_vector(729444,20);
WHEN "011100001" => data <= conv_std_logic_vector(728454,20);
WHEN "011100010" => data <= conv_std_logic_vector(727467,20);
WHEN "011100011" => data <= conv_std_logic_vector(726483,20);
WHEN "011100100" => data <= conv_std_logic_vector(725501,20);
WHEN "011100101" => data <= conv_std_logic_vector(724522,20);
WHEN "011100110" => data <= conv_std_logic_vector(723545,20);
WHEN "011100111" => data <= conv_std_logic_vector(722572,20);
WHEN "011101000" => data <= conv_std_logic_vector(721600,20);
WHEN "011101001" => data <= conv_std_logic_vector(720632,20);
WHEN "011101010" => data <= conv_std_logic_vector(719666,20);
WHEN "011101011" => data <= conv_std_logic_vector(718702,20);
WHEN "011101100" => data <= conv_std_logic_vector(717742,20);
WHEN "011101101" => data <= conv_std_logic_vector(716783,20);
WHEN "011101110" => data <= conv_std_logic_vector(715828,20);
WHEN "011101111" => data <= conv_std_logic_vector(714874,20);
WHEN "011110000" => data <= conv_std_logic_vector(713924,20);
WHEN "011110001" => data <= conv_std_logic_vector(712976,20);
WHEN "011110010" => data <= conv_std_logic_vector(712030,20);
WHEN "011110011" => data <= conv_std_logic_vector(711087,20);
WHEN "011110100" => data <= conv_std_logic_vector(710146,20);
WHEN "011110101" => data <= conv_std_logic_vector(709208,20);
WHEN "011110110" => data <= conv_std_logic_vector(708273,20);
WHEN "011110111" => data <= conv_std_logic_vector(707339,20);
WHEN "011111000" => data <= conv_std_logic_vector(706409,20);
WHEN "011111001" => data <= conv_std_logic_vector(705481,20);
WHEN "011111010" => data <= conv_std_logic_vector(704555,20);
WHEN "011111011" => data <= conv_std_logic_vector(703631,20);
WHEN "011111100" => data <= conv_std_logic_vector(702710,20);
WHEN "011111101" => data <= conv_std_logic_vector(701792,20);
WHEN "011111110" => data <= conv_std_logic_vector(700876,20);
WHEN "011111111" => data <= conv_std_logic_vector(699962,20);
WHEN "100000000" => data <= conv_std_logic_vector(699050,20);
WHEN "100000001" => data <= conv_std_logic_vector(698141,20);
WHEN "100000010" => data <= conv_std_logic_vector(697235,20);
WHEN "100000011" => data <= conv_std_logic_vector(696330,20);
WHEN "100000100" => data <= conv_std_logic_vector(695428,20);
WHEN "100000101" => data <= conv_std_logic_vector(694529,20);
WHEN "100000110" => data <= conv_std_logic_vector(693631,20);
WHEN "100000111" => data <= conv_std_logic_vector(692736,20);
WHEN "100001000" => data <= conv_std_logic_vector(691844,20);
WHEN "100001001" => data <= conv_std_logic_vector(690953,20);
WHEN "100001010" => data <= conv_std_logic_vector(690065,20);
WHEN "100001011" => data <= conv_std_logic_vector(689179,20);
WHEN "100001100" => data <= conv_std_logic_vector(688296,20);
WHEN "100001101" => data <= conv_std_logic_vector(687414,20);
WHEN "100001110" => data <= conv_std_logic_vector(686535,20);
WHEN "100001111" => data <= conv_std_logic_vector(685659,20);
WHEN "100010000" => data <= conv_std_logic_vector(684784,20);
WHEN "100010001" => data <= conv_std_logic_vector(683912,20);
WHEN "100010010" => data <= conv_std_logic_vector(683042,20);
WHEN "100010011" => data <= conv_std_logic_vector(682174,20);
WHEN "100010100" => data <= conv_std_logic_vector(681308,20);
WHEN "100010101" => data <= conv_std_logic_vector(680444,20);
WHEN "100010110" => data <= conv_std_logic_vector(679583,20);
WHEN "100010111" => data <= conv_std_logic_vector(678724,20);
WHEN "100011000" => data <= conv_std_logic_vector(677867,20);
WHEN "100011001" => data <= conv_std_logic_vector(677012,20);
WHEN "100011010" => data <= conv_std_logic_vector(676160,20);
WHEN "100011011" => data <= conv_std_logic_vector(675309,20);
WHEN "100011100" => data <= conv_std_logic_vector(674461,20);
WHEN "100011101" => data <= conv_std_logic_vector(673614,20);
WHEN "100011110" => data <= conv_std_logic_vector(672770,20);
WHEN "100011111" => data <= conv_std_logic_vector(671928,20);
WHEN "100100000" => data <= conv_std_logic_vector(671088,20);
WHEN "100100001" => data <= conv_std_logic_vector(670251,20);
WHEN "100100010" => data <= conv_std_logic_vector(669415,20);
WHEN "100100011" => data <= conv_std_logic_vector(668581,20);
WHEN "100100100" => data <= conv_std_logic_vector(667750,20);
WHEN "100100101" => data <= conv_std_logic_vector(666920,20);
WHEN "100100110" => data <= conv_std_logic_vector(666093,20);
WHEN "100100111" => data <= conv_std_logic_vector(665267,20);
WHEN "100101000" => data <= conv_std_logic_vector(664444,20);
WHEN "100101001" => data <= conv_std_logic_vector(663623,20);
WHEN "100101010" => data <= conv_std_logic_vector(662803,20);
WHEN "100101011" => data <= conv_std_logic_vector(661986,20);
WHEN "100101100" => data <= conv_std_logic_vector(661171,20);
WHEN "100101101" => data <= conv_std_logic_vector(660358,20);
WHEN "100101110" => data <= conv_std_logic_vector(659546,20);
WHEN "100101111" => data <= conv_std_logic_vector(658737,20);
WHEN "100110000" => data <= conv_std_logic_vector(657930,20);
WHEN "100110001" => data <= conv_std_logic_vector(657124,20);
WHEN "100110010" => data <= conv_std_logic_vector(656321,20);
WHEN "100110011" => data <= conv_std_logic_vector(655520,20);
WHEN "100110100" => data <= conv_std_logic_vector(654720,20);
WHEN "100110101" => data <= conv_std_logic_vector(653923,20);
WHEN "100110110" => data <= conv_std_logic_vector(653127,20);
WHEN "100110111" => data <= conv_std_logic_vector(652334,20);
WHEN "100111000" => data <= conv_std_logic_vector(651542,20);
WHEN "100111001" => data <= conv_std_logic_vector(650752,20);
WHEN "100111010" => data <= conv_std_logic_vector(649965,20);
WHEN "100111011" => data <= conv_std_logic_vector(649179,20);
WHEN "100111100" => data <= conv_std_logic_vector(648395,20);
WHEN "100111101" => data <= conv_std_logic_vector(647612,20);
WHEN "100111110" => data <= conv_std_logic_vector(646832,20);
WHEN "100111111" => data <= conv_std_logic_vector(646054,20);
WHEN "101000000" => data <= conv_std_logic_vector(645277,20);
WHEN "101000001" => data <= conv_std_logic_vector(644503,20);
WHEN "101000010" => data <= conv_std_logic_vector(643730,20);
WHEN "101000011" => data <= conv_std_logic_vector(642959,20);
WHEN "101000100" => data <= conv_std_logic_vector(642190,20);
WHEN "101000101" => data <= conv_std_logic_vector(641423,20);
WHEN "101000110" => data <= conv_std_logic_vector(640657,20);
WHEN "101000111" => data <= conv_std_logic_vector(639894,20);
WHEN "101001000" => data <= conv_std_logic_vector(639132,20);
WHEN "101001001" => data <= conv_std_logic_vector(638372,20);
WHEN "101001010" => data <= conv_std_logic_vector(637614,20);
WHEN "101001011" => data <= conv_std_logic_vector(636857,20);
WHEN "101001100" => data <= conv_std_logic_vector(636103,20);
WHEN "101001101" => data <= conv_std_logic_vector(635350,20);
WHEN "101001110" => data <= conv_std_logic_vector(634599,20);
WHEN "101001111" => data <= conv_std_logic_vector(633850,20);
WHEN "101010000" => data <= conv_std_logic_vector(633102,20);
WHEN "101010001" => data <= conv_std_logic_vector(632357,20);
WHEN "101010010" => data <= conv_std_logic_vector(631613,20);
WHEN "101010011" => data <= conv_std_logic_vector(630870,20);
WHEN "101010100" => data <= conv_std_logic_vector(630130,20);
WHEN "101010101" => data <= conv_std_logic_vector(629391,20);
WHEN "101010110" => data <= conv_std_logic_vector(628654,20);
WHEN "101010111" => data <= conv_std_logic_vector(627919,20);
WHEN "101011000" => data <= conv_std_logic_vector(627185,20);
WHEN "101011001" => data <= conv_std_logic_vector(626454,20);
WHEN "101011010" => data <= conv_std_logic_vector(625723,20);
WHEN "101011011" => data <= conv_std_logic_vector(624995,20);
WHEN "101011100" => data <= conv_std_logic_vector(624268,20);
WHEN "101011101" => data <= conv_std_logic_vector(623543,20);
WHEN "101011110" => data <= conv_std_logic_vector(622820,20);
WHEN "101011111" => data <= conv_std_logic_vector(622098,20);
WHEN "101100000" => data <= conv_std_logic_vector(621378,20);
WHEN "101100001" => data <= conv_std_logic_vector(620660,20);
WHEN "101100010" => data <= conv_std_logic_vector(619943,20);
WHEN "101100011" => data <= conv_std_logic_vector(619228,20);
WHEN "101100100" => data <= conv_std_logic_vector(618515,20);
WHEN "101100101" => data <= conv_std_logic_vector(617803,20);
WHEN "101100110" => data <= conv_std_logic_vector(617093,20);
WHEN "101100111" => data <= conv_std_logic_vector(616384,20);
WHEN "101101000" => data <= conv_std_logic_vector(615677,20);
WHEN "101101001" => data <= conv_std_logic_vector(614972,20);
WHEN "101101010" => data <= conv_std_logic_vector(614269,20);
WHEN "101101011" => data <= conv_std_logic_vector(613567,20);
WHEN "101101100" => data <= conv_std_logic_vector(612866,20);
WHEN "101101101" => data <= conv_std_logic_vector(612167,20);
WHEN "101101110" => data <= conv_std_logic_vector(611470,20);
WHEN "101101111" => data <= conv_std_logic_vector(610774,20);
WHEN "101110000" => data <= conv_std_logic_vector(610080,20);
WHEN "101110001" => data <= conv_std_logic_vector(609388,20);
WHEN "101110010" => data <= conv_std_logic_vector(608697,20);
WHEN "101110011" => data <= conv_std_logic_vector(608008,20);
WHEN "101110100" => data <= conv_std_logic_vector(607320,20);
WHEN "101110101" => data <= conv_std_logic_vector(606634,20);
WHEN "101110110" => data <= conv_std_logic_vector(605949,20);
WHEN "101110111" => data <= conv_std_logic_vector(605266,20);
WHEN "101111000" => data <= conv_std_logic_vector(604584,20);
WHEN "101111001" => data <= conv_std_logic_vector(603904,20);
WHEN "101111010" => data <= conv_std_logic_vector(603226,20);
WHEN "101111011" => data <= conv_std_logic_vector(602549,20);
WHEN "101111100" => data <= conv_std_logic_vector(601873,20);
WHEN "101111101" => data <= conv_std_logic_vector(601199,20);
WHEN "101111110" => data <= conv_std_logic_vector(600527,20);
WHEN "101111111" => data <= conv_std_logic_vector(599856,20);
WHEN "110000000" => data <= conv_std_logic_vector(599186,20);
WHEN "110000001" => data <= conv_std_logic_vector(598518,20);
WHEN "110000010" => data <= conv_std_logic_vector(597852,20);
WHEN "110000011" => data <= conv_std_logic_vector(597187,20);
WHEN "110000100" => data <= conv_std_logic_vector(596523,20);
WHEN "110000101" => data <= conv_std_logic_vector(595861,20);
WHEN "110000110" => data <= conv_std_logic_vector(595200,20);
WHEN "110000111" => data <= conv_std_logic_vector(594541,20);
WHEN "110001000" => data <= conv_std_logic_vector(593884,20);
WHEN "110001001" => data <= conv_std_logic_vector(593227,20);
WHEN "110001010" => data <= conv_std_logic_vector(592573,20);
WHEN "110001011" => data <= conv_std_logic_vector(591919,20);
WHEN "110001100" => data <= conv_std_logic_vector(591267,20);
WHEN "110001101" => data <= conv_std_logic_vector(590617,20);
WHEN "110001110" => data <= conv_std_logic_vector(589968,20);
WHEN "110001111" => data <= conv_std_logic_vector(589320,20);
WHEN "110010000" => data <= conv_std_logic_vector(588674,20);
WHEN "110010001" => data <= conv_std_logic_vector(588029,20);
WHEN "110010010" => data <= conv_std_logic_vector(587386,20);
WHEN "110010011" => data <= conv_std_logic_vector(586744,20);
WHEN "110010100" => data <= conv_std_logic_vector(586103,20);
WHEN "110010101" => data <= conv_std_logic_vector(585464,20);
WHEN "110010110" => data <= conv_std_logic_vector(584827,20);
WHEN "110010111" => data <= conv_std_logic_vector(584190,20);
WHEN "110011000" => data <= conv_std_logic_vector(583555,20);
WHEN "110011001" => data <= conv_std_logic_vector(582922,20);
WHEN "110011010" => data <= conv_std_logic_vector(582289,20);
WHEN "110011011" => data <= conv_std_logic_vector(581658,20);
WHEN "110011100" => data <= conv_std_logic_vector(581029,20);
WHEN "110011101" => data <= conv_std_logic_vector(580401,20);
WHEN "110011110" => data <= conv_std_logic_vector(579774,20);
WHEN "110011111" => data <= conv_std_logic_vector(579149,20);
WHEN "110100000" => data <= conv_std_logic_vector(578525,20);
WHEN "110100001" => data <= conv_std_logic_vector(577902,20);
WHEN "110100010" => data <= conv_std_logic_vector(577280,20);
WHEN "110100011" => data <= conv_std_logic_vector(576660,20);
WHEN "110100100" => data <= conv_std_logic_vector(576042,20);
WHEN "110100101" => data <= conv_std_logic_vector(575424,20);
WHEN "110100110" => data <= conv_std_logic_vector(574808,20);
WHEN "110100111" => data <= conv_std_logic_vector(574193,20);
WHEN "110101000" => data <= conv_std_logic_vector(573580,20);
WHEN "110101001" => data <= conv_std_logic_vector(572968,20);
WHEN "110101010" => data <= conv_std_logic_vector(572357,20);
WHEN "110101011" => data <= conv_std_logic_vector(571747,20);
WHEN "110101100" => data <= conv_std_logic_vector(571139,20);
WHEN "110101101" => data <= conv_std_logic_vector(570532,20);
WHEN "110101110" => data <= conv_std_logic_vector(569926,20);
WHEN "110101111" => data <= conv_std_logic_vector(569322,20);
WHEN "110110000" => data <= conv_std_logic_vector(568719,20);
WHEN "110110001" => data <= conv_std_logic_vector(568117,20);
WHEN "110110010" => data <= conv_std_logic_vector(567517,20);
WHEN "110110011" => data <= conv_std_logic_vector(566917,20);
WHEN "110110100" => data <= conv_std_logic_vector(566319,20);
WHEN "110110101" => data <= conv_std_logic_vector(565723,20);
WHEN "110110110" => data <= conv_std_logic_vector(565127,20);
WHEN "110110111" => data <= conv_std_logic_vector(564533,20);
WHEN "110111000" => data <= conv_std_logic_vector(563940,20);
WHEN "110111001" => data <= conv_std_logic_vector(563348,20);
WHEN "110111010" => data <= conv_std_logic_vector(562758,20);
WHEN "110111011" => data <= conv_std_logic_vector(562168,20);
WHEN "110111100" => data <= conv_std_logic_vector(561580,20);
WHEN "110111101" => data <= conv_std_logic_vector(560993,20);
WHEN "110111110" => data <= conv_std_logic_vector(560408,20);
WHEN "110111111" => data <= conv_std_logic_vector(559824,20);
WHEN "111000000" => data <= conv_std_logic_vector(559240,20);
WHEN "111000001" => data <= conv_std_logic_vector(558658,20);
WHEN "111000010" => data <= conv_std_logic_vector(558078,20);
WHEN "111000011" => data <= conv_std_logic_vector(557498,20);
WHEN "111000100" => data <= conv_std_logic_vector(556920,20);
WHEN "111000101" => data <= conv_std_logic_vector(556343,20);
WHEN "111000110" => data <= conv_std_logic_vector(555767,20);
WHEN "111000111" => data <= conv_std_logic_vector(555192,20);
WHEN "111001000" => data <= conv_std_logic_vector(554619,20);
WHEN "111001001" => data <= conv_std_logic_vector(554046,20);
WHEN "111001010" => data <= conv_std_logic_vector(553475,20);
WHEN "111001011" => data <= conv_std_logic_vector(552905,20);
WHEN "111001100" => data <= conv_std_logic_vector(552336,20);
WHEN "111001101" => data <= conv_std_logic_vector(551769,20);
WHEN "111001110" => data <= conv_std_logic_vector(551202,20);
WHEN "111001111" => data <= conv_std_logic_vector(550637,20);
WHEN "111010000" => data <= conv_std_logic_vector(550073,20);
WHEN "111010001" => data <= conv_std_logic_vector(549509,20);
WHEN "111010010" => data <= conv_std_logic_vector(548948,20);
WHEN "111010011" => data <= conv_std_logic_vector(548387,20);
WHEN "111010100" => data <= conv_std_logic_vector(547827,20);
WHEN "111010101" => data <= conv_std_logic_vector(547269,20);
WHEN "111010110" => data <= conv_std_logic_vector(546712,20);
WHEN "111010111" => data <= conv_std_logic_vector(546155,20);
WHEN "111011000" => data <= conv_std_logic_vector(545600,20);
WHEN "111011001" => data <= conv_std_logic_vector(545046,20);
WHEN "111011010" => data <= conv_std_logic_vector(544494,20);
WHEN "111011011" => data <= conv_std_logic_vector(543942,20);
WHEN "111011100" => data <= conv_std_logic_vector(543391,20);
WHEN "111011101" => data <= conv_std_logic_vector(542842,20);
WHEN "111011110" => data <= conv_std_logic_vector(542294,20);
WHEN "111011111" => data <= conv_std_logic_vector(541746,20);
WHEN "111100000" => data <= conv_std_logic_vector(541200,20);
WHEN "111100001" => data <= conv_std_logic_vector(540655,20);
WHEN "111100010" => data <= conv_std_logic_vector(540111,20);
WHEN "111100011" => data <= conv_std_logic_vector(539569,20);
WHEN "111100100" => data <= conv_std_logic_vector(539027,20);
WHEN "111100101" => data <= conv_std_logic_vector(538486,20);
WHEN "111100110" => data <= conv_std_logic_vector(537947,20);
WHEN "111100111" => data <= conv_std_logic_vector(537408,20);
WHEN "111101000" => data <= conv_std_logic_vector(536871,20);
WHEN "111101001" => data <= conv_std_logic_vector(536334,20);
WHEN "111101010" => data <= conv_std_logic_vector(535799,20);
WHEN "111101011" => data <= conv_std_logic_vector(535265,20);
WHEN "111101100" => data <= conv_std_logic_vector(534732,20);
WHEN "111101101" => data <= conv_std_logic_vector(534200,20);
WHEN "111101110" => data <= conv_std_logic_vector(533669,20);
WHEN "111101111" => data <= conv_std_logic_vector(533139,20);
WHEN "111110000" => data <= conv_std_logic_vector(532610,20);
WHEN "111110001" => data <= conv_std_logic_vector(532082,20);
WHEN "111110010" => data <= conv_std_logic_vector(531555,20);
WHEN "111110011" => data <= conv_std_logic_vector(531029,20);
WHEN "111110100" => data <= conv_std_logic_vector(530505,20);
WHEN "111110101" => data <= conv_std_logic_vector(529981,20);
WHEN "111110110" => data <= conv_std_logic_vector(529458,20);
WHEN "111110111" => data <= conv_std_logic_vector(528937,20);
WHEN "111111000" => data <= conv_std_logic_vector(528416,20);
WHEN "111111001" => data <= conv_std_logic_vector(527897,20);
WHEN "111111010" => data <= conv_std_logic_vector(527378,20);
WHEN "111111011" => data <= conv_std_logic_vector(526860,20);
WHEN "111111100" => data <= conv_std_logic_vector(526344,20);
WHEN "111111101" => data <= conv_std_logic_vector(525828,20);
WHEN "111111110" => data <= conv_std_logic_vector(525314,20);
WHEN "111111111" => data <= conv_std_logic_vector(524800,20);
WHEN others => data <= conv_std_logic_vector(0,20);
END CASE;
END PROCESS;
END rtl;
|
-- (C) 1992-2014 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_DIV_LUT0.VHD ***
--*** ***
--*** Function: Look Up Table - Inverse ***
--*** ***
--*** Generated by MATLAB Utility ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY fp_div_lut0 IS
PORT (
add : IN STD_LOGIC_VECTOR (9 DOWNTO 1);
data : OUT STD_LOGIC_VECTOR (20 DOWNTO 1)
);
END fp_div_lut0;
ARCHITECTURE rtl OF fp_div_lut0 IS
BEGIN
pca: PROCESS (add)
BEGIN
CASE add IS
WHEN "000000000" => data <= conv_std_logic_vector(1048575,20);
WHEN "000000001" => data <= conv_std_logic_vector(1046531,20);
WHEN "000000010" => data <= conv_std_logic_vector(1044495,20);
WHEN "000000011" => data <= conv_std_logic_vector(1042467,20);
WHEN "000000100" => data <= conv_std_logic_vector(1040447,20);
WHEN "000000101" => data <= conv_std_logic_vector(1038434,20);
WHEN "000000110" => data <= conv_std_logic_vector(1036429,20);
WHEN "000000111" => data <= conv_std_logic_vector(1034432,20);
WHEN "000001000" => data <= conv_std_logic_vector(1032443,20);
WHEN "000001001" => data <= conv_std_logic_vector(1030461,20);
WHEN "000001010" => data <= conv_std_logic_vector(1028487,20);
WHEN "000001011" => data <= conv_std_logic_vector(1026521,20);
WHEN "000001100" => data <= conv_std_logic_vector(1024562,20);
WHEN "000001101" => data <= conv_std_logic_vector(1022610,20);
WHEN "000001110" => data <= conv_std_logic_vector(1020666,20);
WHEN "000001111" => data <= conv_std_logic_vector(1018729,20);
WHEN "000010000" => data <= conv_std_logic_vector(1016800,20);
WHEN "000010001" => data <= conv_std_logic_vector(1014878,20);
WHEN "000010010" => data <= conv_std_logic_vector(1012963,20);
WHEN "000010011" => data <= conv_std_logic_vector(1011055,20);
WHEN "000010100" => data <= conv_std_logic_vector(1009155,20);
WHEN "000010101" => data <= conv_std_logic_vector(1007262,20);
WHEN "000010110" => data <= conv_std_logic_vector(1005375,20);
WHEN "000010111" => data <= conv_std_logic_vector(1003496,20);
WHEN "000011000" => data <= conv_std_logic_vector(1001624,20);
WHEN "000011001" => data <= conv_std_logic_vector(999759,20);
WHEN "000011010" => data <= conv_std_logic_vector(997900,20);
WHEN "000011011" => data <= conv_std_logic_vector(996049,20);
WHEN "000011100" => data <= conv_std_logic_vector(994205,20);
WHEN "000011101" => data <= conv_std_logic_vector(992367,20);
WHEN "000011110" => data <= conv_std_logic_vector(990536,20);
WHEN "000011111" => data <= conv_std_logic_vector(988712,20);
WHEN "000100000" => data <= conv_std_logic_vector(986894,20);
WHEN "000100001" => data <= conv_std_logic_vector(985083,20);
WHEN "000100010" => data <= conv_std_logic_vector(983279,20);
WHEN "000100011" => data <= conv_std_logic_vector(981482,20);
WHEN "000100100" => data <= conv_std_logic_vector(979691,20);
WHEN "000100101" => data <= conv_std_logic_vector(977906,20);
WHEN "000100110" => data <= conv_std_logic_vector(976128,20);
WHEN "000100111" => data <= conv_std_logic_vector(974357,20);
WHEN "000101000" => data <= conv_std_logic_vector(972591,20);
WHEN "000101001" => data <= conv_std_logic_vector(970833,20);
WHEN "000101010" => data <= conv_std_logic_vector(969080,20);
WHEN "000101011" => data <= conv_std_logic_vector(967334,20);
WHEN "000101100" => data <= conv_std_logic_vector(965594,20);
WHEN "000101101" => data <= conv_std_logic_vector(963861,20);
WHEN "000101110" => data <= conv_std_logic_vector(962133,20);
WHEN "000101111" => data <= conv_std_logic_vector(960412,20);
WHEN "000110000" => data <= conv_std_logic_vector(958697,20);
WHEN "000110001" => data <= conv_std_logic_vector(956988,20);
WHEN "000110010" => data <= conv_std_logic_vector(955286,20);
WHEN "000110011" => data <= conv_std_logic_vector(953589,20);
WHEN "000110100" => data <= conv_std_logic_vector(951898,20);
WHEN "000110101" => data <= conv_std_logic_vector(950213,20);
WHEN "000110110" => data <= conv_std_logic_vector(948534,20);
WHEN "000110111" => data <= conv_std_logic_vector(946862,20);
WHEN "000111000" => data <= conv_std_logic_vector(945195,20);
WHEN "000111001" => data <= conv_std_logic_vector(943533,20);
WHEN "000111010" => data <= conv_std_logic_vector(941878,20);
WHEN "000111011" => data <= conv_std_logic_vector(940229,20);
WHEN "000111100" => data <= conv_std_logic_vector(938585,20);
WHEN "000111101" => data <= conv_std_logic_vector(936947,20);
WHEN "000111110" => data <= conv_std_logic_vector(935314,20);
WHEN "000111111" => data <= conv_std_logic_vector(933688,20);
WHEN "001000000" => data <= conv_std_logic_vector(932067,20);
WHEN "001000001" => data <= conv_std_logic_vector(930451,20);
WHEN "001000010" => data <= conv_std_logic_vector(928842,20);
WHEN "001000011" => data <= conv_std_logic_vector(927237,20);
WHEN "001000100" => data <= conv_std_logic_vector(925639,20);
WHEN "001000101" => data <= conv_std_logic_vector(924046,20);
WHEN "001000110" => data <= conv_std_logic_vector(922458,20);
WHEN "001000111" => data <= conv_std_logic_vector(920876,20);
WHEN "001001000" => data <= conv_std_logic_vector(919299,20);
WHEN "001001001" => data <= conv_std_logic_vector(917727,20);
WHEN "001001010" => data <= conv_std_logic_vector(916161,20);
WHEN "001001011" => data <= conv_std_logic_vector(914601,20);
WHEN "001001100" => data <= conv_std_logic_vector(913045,20);
WHEN "001001101" => data <= conv_std_logic_vector(911495,20);
WHEN "001001110" => data <= conv_std_logic_vector(909950,20);
WHEN "001001111" => data <= conv_std_logic_vector(908410,20);
WHEN "001010000" => data <= conv_std_logic_vector(906876,20);
WHEN "001010001" => data <= conv_std_logic_vector(905347,20);
WHEN "001010010" => data <= conv_std_logic_vector(903822,20);
WHEN "001010011" => data <= conv_std_logic_vector(902303,20);
WHEN "001010100" => data <= conv_std_logic_vector(900789,20);
WHEN "001010101" => data <= conv_std_logic_vector(899281,20);
WHEN "001010110" => data <= conv_std_logic_vector(897777,20);
WHEN "001010111" => data <= conv_std_logic_vector(896278,20);
WHEN "001011000" => data <= conv_std_logic_vector(894784,20);
WHEN "001011001" => data <= conv_std_logic_vector(893295,20);
WHEN "001011010" => data <= conv_std_logic_vector(891812,20);
WHEN "001011011" => data <= conv_std_logic_vector(890333,20);
WHEN "001011100" => data <= conv_std_logic_vector(888859,20);
WHEN "001011101" => data <= conv_std_logic_vector(887389,20);
WHEN "001011110" => data <= conv_std_logic_vector(885925,20);
WHEN "001011111" => data <= conv_std_logic_vector(884465,20);
WHEN "001100000" => data <= conv_std_logic_vector(883011,20);
WHEN "001100001" => data <= conv_std_logic_vector(881561,20);
WHEN "001100010" => data <= conv_std_logic_vector(880116,20);
WHEN "001100011" => data <= conv_std_logic_vector(878675,20);
WHEN "001100100" => data <= conv_std_logic_vector(877239,20);
WHEN "001100101" => data <= conv_std_logic_vector(875808,20);
WHEN "001100110" => data <= conv_std_logic_vector(874382,20);
WHEN "001100111" => data <= conv_std_logic_vector(872960,20);
WHEN "001101000" => data <= conv_std_logic_vector(871543,20);
WHEN "001101001" => data <= conv_std_logic_vector(870131,20);
WHEN "001101010" => data <= conv_std_logic_vector(868723,20);
WHEN "001101011" => data <= conv_std_logic_vector(867319,20);
WHEN "001101100" => data <= conv_std_logic_vector(865920,20);
WHEN "001101101" => data <= conv_std_logic_vector(864526,20);
WHEN "001101110" => data <= conv_std_logic_vector(863136,20);
WHEN "001101111" => data <= conv_std_logic_vector(861751,20);
WHEN "001110000" => data <= conv_std_logic_vector(860369,20);
WHEN "001110001" => data <= conv_std_logic_vector(858993,20);
WHEN "001110010" => data <= conv_std_logic_vector(857621,20);
WHEN "001110011" => data <= conv_std_logic_vector(856253,20);
WHEN "001110100" => data <= conv_std_logic_vector(854889,20);
WHEN "001110101" => data <= conv_std_logic_vector(853530,20);
WHEN "001110110" => data <= conv_std_logic_vector(852176,20);
WHEN "001110111" => data <= conv_std_logic_vector(850825,20);
WHEN "001111000" => data <= conv_std_logic_vector(849479,20);
WHEN "001111001" => data <= conv_std_logic_vector(848137,20);
WHEN "001111010" => data <= conv_std_logic_vector(846799,20);
WHEN "001111011" => data <= conv_std_logic_vector(845465,20);
WHEN "001111100" => data <= conv_std_logic_vector(844136,20);
WHEN "001111101" => data <= conv_std_logic_vector(842811,20);
WHEN "001111110" => data <= conv_std_logic_vector(841490,20);
WHEN "001111111" => data <= conv_std_logic_vector(840173,20);
WHEN "010000000" => data <= conv_std_logic_vector(838860,20);
WHEN "010000001" => data <= conv_std_logic_vector(837552,20);
WHEN "010000010" => data <= conv_std_logic_vector(836247,20);
WHEN "010000011" => data <= conv_std_logic_vector(834946,20);
WHEN "010000100" => data <= conv_std_logic_vector(833650,20);
WHEN "010000101" => data <= conv_std_logic_vector(832358,20);
WHEN "010000110" => data <= conv_std_logic_vector(831069,20);
WHEN "010000111" => data <= conv_std_logic_vector(829785,20);
WHEN "010001000" => data <= conv_std_logic_vector(828504,20);
WHEN "010001001" => data <= conv_std_logic_vector(827227,20);
WHEN "010001010" => data <= conv_std_logic_vector(825955,20);
WHEN "010001011" => data <= conv_std_logic_vector(824686,20);
WHEN "010001100" => data <= conv_std_logic_vector(823421,20);
WHEN "010001101" => data <= conv_std_logic_vector(822160,20);
WHEN "010001110" => data <= conv_std_logic_vector(820903,20);
WHEN "010001111" => data <= conv_std_logic_vector(819650,20);
WHEN "010010000" => data <= conv_std_logic_vector(818400,20);
WHEN "010010001" => data <= conv_std_logic_vector(817155,20);
WHEN "010010010" => data <= conv_std_logic_vector(815913,20);
WHEN "010010011" => data <= conv_std_logic_vector(814675,20);
WHEN "010010100" => data <= conv_std_logic_vector(813440,20);
WHEN "010010101" => data <= conv_std_logic_vector(812210,20);
WHEN "010010110" => data <= conv_std_logic_vector(810983,20);
WHEN "010010111" => data <= conv_std_logic_vector(809760,20);
WHEN "010011000" => data <= conv_std_logic_vector(808540,20);
WHEN "010011001" => data <= conv_std_logic_vector(807324,20);
WHEN "010011010" => data <= conv_std_logic_vector(806112,20);
WHEN "010011011" => data <= conv_std_logic_vector(804903,20);
WHEN "010011100" => data <= conv_std_logic_vector(803699,20);
WHEN "010011101" => data <= conv_std_logic_vector(802497,20);
WHEN "010011110" => data <= conv_std_logic_vector(801299,20);
WHEN "010011111" => data <= conv_std_logic_vector(800105,20);
WHEN "010100000" => data <= conv_std_logic_vector(798915,20);
WHEN "010100001" => data <= conv_std_logic_vector(797728,20);
WHEN "010100010" => data <= conv_std_logic_vector(796544,20);
WHEN "010100011" => data <= conv_std_logic_vector(795364,20);
WHEN "010100100" => data <= conv_std_logic_vector(794187,20);
WHEN "010100101" => data <= conv_std_logic_vector(793014,20);
WHEN "010100110" => data <= conv_std_logic_vector(791845,20);
WHEN "010100111" => data <= conv_std_logic_vector(790678,20);
WHEN "010101000" => data <= conv_std_logic_vector(789516,20);
WHEN "010101001" => data <= conv_std_logic_vector(788356,20);
WHEN "010101010" => data <= conv_std_logic_vector(787200,20);
WHEN "010101011" => data <= conv_std_logic_vector(786048,20);
WHEN "010101100" => data <= conv_std_logic_vector(784899,20);
WHEN "010101101" => data <= conv_std_logic_vector(783753,20);
WHEN "010101110" => data <= conv_std_logic_vector(782610,20);
WHEN "010101111" => data <= conv_std_logic_vector(781471,20);
WHEN "010110000" => data <= conv_std_logic_vector(780335,20);
WHEN "010110001" => data <= conv_std_logic_vector(779203,20);
WHEN "010110010" => data <= conv_std_logic_vector(778073,20);
WHEN "010110011" => data <= conv_std_logic_vector(776947,20);
WHEN "010110100" => data <= conv_std_logic_vector(775825,20);
WHEN "010110101" => data <= conv_std_logic_vector(774705,20);
WHEN "010110110" => data <= conv_std_logic_vector(773589,20);
WHEN "010110111" => data <= conv_std_logic_vector(772476,20);
WHEN "010111000" => data <= conv_std_logic_vector(771366,20);
WHEN "010111001" => data <= conv_std_logic_vector(770259,20);
WHEN "010111010" => data <= conv_std_logic_vector(769156,20);
WHEN "010111011" => data <= conv_std_logic_vector(768055,20);
WHEN "010111100" => data <= conv_std_logic_vector(766958,20);
WHEN "010111101" => data <= conv_std_logic_vector(765864,20);
WHEN "010111110" => data <= conv_std_logic_vector(764773,20);
WHEN "010111111" => data <= conv_std_logic_vector(763685,20);
WHEN "011000000" => data <= conv_std_logic_vector(762600,20);
WHEN "011000001" => data <= conv_std_logic_vector(761519,20);
WHEN "011000010" => data <= conv_std_logic_vector(760440,20);
WHEN "011000011" => data <= conv_std_logic_vector(759364,20);
WHEN "011000100" => data <= conv_std_logic_vector(758292,20);
WHEN "011000101" => data <= conv_std_logic_vector(757222,20);
WHEN "011000110" => data <= conv_std_logic_vector(756156,20);
WHEN "011000111" => data <= conv_std_logic_vector(755092,20);
WHEN "011001000" => data <= conv_std_logic_vector(754032,20);
WHEN "011001001" => data <= conv_std_logic_vector(752974,20);
WHEN "011001010" => data <= conv_std_logic_vector(751920,20);
WHEN "011001011" => data <= conv_std_logic_vector(750868,20);
WHEN "011001100" => data <= conv_std_logic_vector(749819,20);
WHEN "011001101" => data <= conv_std_logic_vector(748774,20);
WHEN "011001110" => data <= conv_std_logic_vector(747731,20);
WHEN "011001111" => data <= conv_std_logic_vector(746691,20);
WHEN "011010000" => data <= conv_std_logic_vector(745654,20);
WHEN "011010001" => data <= conv_std_logic_vector(744619,20);
WHEN "011010010" => data <= conv_std_logic_vector(743588,20);
WHEN "011010011" => data <= conv_std_logic_vector(742560,20);
WHEN "011010100" => data <= conv_std_logic_vector(741534,20);
WHEN "011010101" => data <= conv_std_logic_vector(740511,20);
WHEN "011010110" => data <= conv_std_logic_vector(739491,20);
WHEN "011010111" => data <= conv_std_logic_vector(738474,20);
WHEN "011011000" => data <= conv_std_logic_vector(737460,20);
WHEN "011011001" => data <= conv_std_logic_vector(736448,20);
WHEN "011011010" => data <= conv_std_logic_vector(735439,20);
WHEN "011011011" => data <= conv_std_logic_vector(734433,20);
WHEN "011011100" => data <= conv_std_logic_vector(733430,20);
WHEN "011011101" => data <= conv_std_logic_vector(732429,20);
WHEN "011011110" => data <= conv_std_logic_vector(731431,20);
WHEN "011011111" => data <= conv_std_logic_vector(730436,20);
WHEN "011100000" => data <= conv_std_logic_vector(729444,20);
WHEN "011100001" => data <= conv_std_logic_vector(728454,20);
WHEN "011100010" => data <= conv_std_logic_vector(727467,20);
WHEN "011100011" => data <= conv_std_logic_vector(726483,20);
WHEN "011100100" => data <= conv_std_logic_vector(725501,20);
WHEN "011100101" => data <= conv_std_logic_vector(724522,20);
WHEN "011100110" => data <= conv_std_logic_vector(723545,20);
WHEN "011100111" => data <= conv_std_logic_vector(722572,20);
WHEN "011101000" => data <= conv_std_logic_vector(721600,20);
WHEN "011101001" => data <= conv_std_logic_vector(720632,20);
WHEN "011101010" => data <= conv_std_logic_vector(719666,20);
WHEN "011101011" => data <= conv_std_logic_vector(718702,20);
WHEN "011101100" => data <= conv_std_logic_vector(717742,20);
WHEN "011101101" => data <= conv_std_logic_vector(716783,20);
WHEN "011101110" => data <= conv_std_logic_vector(715828,20);
WHEN "011101111" => data <= conv_std_logic_vector(714874,20);
WHEN "011110000" => data <= conv_std_logic_vector(713924,20);
WHEN "011110001" => data <= conv_std_logic_vector(712976,20);
WHEN "011110010" => data <= conv_std_logic_vector(712030,20);
WHEN "011110011" => data <= conv_std_logic_vector(711087,20);
WHEN "011110100" => data <= conv_std_logic_vector(710146,20);
WHEN "011110101" => data <= conv_std_logic_vector(709208,20);
WHEN "011110110" => data <= conv_std_logic_vector(708273,20);
WHEN "011110111" => data <= conv_std_logic_vector(707339,20);
WHEN "011111000" => data <= conv_std_logic_vector(706409,20);
WHEN "011111001" => data <= conv_std_logic_vector(705481,20);
WHEN "011111010" => data <= conv_std_logic_vector(704555,20);
WHEN "011111011" => data <= conv_std_logic_vector(703631,20);
WHEN "011111100" => data <= conv_std_logic_vector(702710,20);
WHEN "011111101" => data <= conv_std_logic_vector(701792,20);
WHEN "011111110" => data <= conv_std_logic_vector(700876,20);
WHEN "011111111" => data <= conv_std_logic_vector(699962,20);
WHEN "100000000" => data <= conv_std_logic_vector(699050,20);
WHEN "100000001" => data <= conv_std_logic_vector(698141,20);
WHEN "100000010" => data <= conv_std_logic_vector(697235,20);
WHEN "100000011" => data <= conv_std_logic_vector(696330,20);
WHEN "100000100" => data <= conv_std_logic_vector(695428,20);
WHEN "100000101" => data <= conv_std_logic_vector(694529,20);
WHEN "100000110" => data <= conv_std_logic_vector(693631,20);
WHEN "100000111" => data <= conv_std_logic_vector(692736,20);
WHEN "100001000" => data <= conv_std_logic_vector(691844,20);
WHEN "100001001" => data <= conv_std_logic_vector(690953,20);
WHEN "100001010" => data <= conv_std_logic_vector(690065,20);
WHEN "100001011" => data <= conv_std_logic_vector(689179,20);
WHEN "100001100" => data <= conv_std_logic_vector(688296,20);
WHEN "100001101" => data <= conv_std_logic_vector(687414,20);
WHEN "100001110" => data <= conv_std_logic_vector(686535,20);
WHEN "100001111" => data <= conv_std_logic_vector(685659,20);
WHEN "100010000" => data <= conv_std_logic_vector(684784,20);
WHEN "100010001" => data <= conv_std_logic_vector(683912,20);
WHEN "100010010" => data <= conv_std_logic_vector(683042,20);
WHEN "100010011" => data <= conv_std_logic_vector(682174,20);
WHEN "100010100" => data <= conv_std_logic_vector(681308,20);
WHEN "100010101" => data <= conv_std_logic_vector(680444,20);
WHEN "100010110" => data <= conv_std_logic_vector(679583,20);
WHEN "100010111" => data <= conv_std_logic_vector(678724,20);
WHEN "100011000" => data <= conv_std_logic_vector(677867,20);
WHEN "100011001" => data <= conv_std_logic_vector(677012,20);
WHEN "100011010" => data <= conv_std_logic_vector(676160,20);
WHEN "100011011" => data <= conv_std_logic_vector(675309,20);
WHEN "100011100" => data <= conv_std_logic_vector(674461,20);
WHEN "100011101" => data <= conv_std_logic_vector(673614,20);
WHEN "100011110" => data <= conv_std_logic_vector(672770,20);
WHEN "100011111" => data <= conv_std_logic_vector(671928,20);
WHEN "100100000" => data <= conv_std_logic_vector(671088,20);
WHEN "100100001" => data <= conv_std_logic_vector(670251,20);
WHEN "100100010" => data <= conv_std_logic_vector(669415,20);
WHEN "100100011" => data <= conv_std_logic_vector(668581,20);
WHEN "100100100" => data <= conv_std_logic_vector(667750,20);
WHEN "100100101" => data <= conv_std_logic_vector(666920,20);
WHEN "100100110" => data <= conv_std_logic_vector(666093,20);
WHEN "100100111" => data <= conv_std_logic_vector(665267,20);
WHEN "100101000" => data <= conv_std_logic_vector(664444,20);
WHEN "100101001" => data <= conv_std_logic_vector(663623,20);
WHEN "100101010" => data <= conv_std_logic_vector(662803,20);
WHEN "100101011" => data <= conv_std_logic_vector(661986,20);
WHEN "100101100" => data <= conv_std_logic_vector(661171,20);
WHEN "100101101" => data <= conv_std_logic_vector(660358,20);
WHEN "100101110" => data <= conv_std_logic_vector(659546,20);
WHEN "100101111" => data <= conv_std_logic_vector(658737,20);
WHEN "100110000" => data <= conv_std_logic_vector(657930,20);
WHEN "100110001" => data <= conv_std_logic_vector(657124,20);
WHEN "100110010" => data <= conv_std_logic_vector(656321,20);
WHEN "100110011" => data <= conv_std_logic_vector(655520,20);
WHEN "100110100" => data <= conv_std_logic_vector(654720,20);
WHEN "100110101" => data <= conv_std_logic_vector(653923,20);
WHEN "100110110" => data <= conv_std_logic_vector(653127,20);
WHEN "100110111" => data <= conv_std_logic_vector(652334,20);
WHEN "100111000" => data <= conv_std_logic_vector(651542,20);
WHEN "100111001" => data <= conv_std_logic_vector(650752,20);
WHEN "100111010" => data <= conv_std_logic_vector(649965,20);
WHEN "100111011" => data <= conv_std_logic_vector(649179,20);
WHEN "100111100" => data <= conv_std_logic_vector(648395,20);
WHEN "100111101" => data <= conv_std_logic_vector(647612,20);
WHEN "100111110" => data <= conv_std_logic_vector(646832,20);
WHEN "100111111" => data <= conv_std_logic_vector(646054,20);
WHEN "101000000" => data <= conv_std_logic_vector(645277,20);
WHEN "101000001" => data <= conv_std_logic_vector(644503,20);
WHEN "101000010" => data <= conv_std_logic_vector(643730,20);
WHEN "101000011" => data <= conv_std_logic_vector(642959,20);
WHEN "101000100" => data <= conv_std_logic_vector(642190,20);
WHEN "101000101" => data <= conv_std_logic_vector(641423,20);
WHEN "101000110" => data <= conv_std_logic_vector(640657,20);
WHEN "101000111" => data <= conv_std_logic_vector(639894,20);
WHEN "101001000" => data <= conv_std_logic_vector(639132,20);
WHEN "101001001" => data <= conv_std_logic_vector(638372,20);
WHEN "101001010" => data <= conv_std_logic_vector(637614,20);
WHEN "101001011" => data <= conv_std_logic_vector(636857,20);
WHEN "101001100" => data <= conv_std_logic_vector(636103,20);
WHEN "101001101" => data <= conv_std_logic_vector(635350,20);
WHEN "101001110" => data <= conv_std_logic_vector(634599,20);
WHEN "101001111" => data <= conv_std_logic_vector(633850,20);
WHEN "101010000" => data <= conv_std_logic_vector(633102,20);
WHEN "101010001" => data <= conv_std_logic_vector(632357,20);
WHEN "101010010" => data <= conv_std_logic_vector(631613,20);
WHEN "101010011" => data <= conv_std_logic_vector(630870,20);
WHEN "101010100" => data <= conv_std_logic_vector(630130,20);
WHEN "101010101" => data <= conv_std_logic_vector(629391,20);
WHEN "101010110" => data <= conv_std_logic_vector(628654,20);
WHEN "101010111" => data <= conv_std_logic_vector(627919,20);
WHEN "101011000" => data <= conv_std_logic_vector(627185,20);
WHEN "101011001" => data <= conv_std_logic_vector(626454,20);
WHEN "101011010" => data <= conv_std_logic_vector(625723,20);
WHEN "101011011" => data <= conv_std_logic_vector(624995,20);
WHEN "101011100" => data <= conv_std_logic_vector(624268,20);
WHEN "101011101" => data <= conv_std_logic_vector(623543,20);
WHEN "101011110" => data <= conv_std_logic_vector(622820,20);
WHEN "101011111" => data <= conv_std_logic_vector(622098,20);
WHEN "101100000" => data <= conv_std_logic_vector(621378,20);
WHEN "101100001" => data <= conv_std_logic_vector(620660,20);
WHEN "101100010" => data <= conv_std_logic_vector(619943,20);
WHEN "101100011" => data <= conv_std_logic_vector(619228,20);
WHEN "101100100" => data <= conv_std_logic_vector(618515,20);
WHEN "101100101" => data <= conv_std_logic_vector(617803,20);
WHEN "101100110" => data <= conv_std_logic_vector(617093,20);
WHEN "101100111" => data <= conv_std_logic_vector(616384,20);
WHEN "101101000" => data <= conv_std_logic_vector(615677,20);
WHEN "101101001" => data <= conv_std_logic_vector(614972,20);
WHEN "101101010" => data <= conv_std_logic_vector(614269,20);
WHEN "101101011" => data <= conv_std_logic_vector(613567,20);
WHEN "101101100" => data <= conv_std_logic_vector(612866,20);
WHEN "101101101" => data <= conv_std_logic_vector(612167,20);
WHEN "101101110" => data <= conv_std_logic_vector(611470,20);
WHEN "101101111" => data <= conv_std_logic_vector(610774,20);
WHEN "101110000" => data <= conv_std_logic_vector(610080,20);
WHEN "101110001" => data <= conv_std_logic_vector(609388,20);
WHEN "101110010" => data <= conv_std_logic_vector(608697,20);
WHEN "101110011" => data <= conv_std_logic_vector(608008,20);
WHEN "101110100" => data <= conv_std_logic_vector(607320,20);
WHEN "101110101" => data <= conv_std_logic_vector(606634,20);
WHEN "101110110" => data <= conv_std_logic_vector(605949,20);
WHEN "101110111" => data <= conv_std_logic_vector(605266,20);
WHEN "101111000" => data <= conv_std_logic_vector(604584,20);
WHEN "101111001" => data <= conv_std_logic_vector(603904,20);
WHEN "101111010" => data <= conv_std_logic_vector(603226,20);
WHEN "101111011" => data <= conv_std_logic_vector(602549,20);
WHEN "101111100" => data <= conv_std_logic_vector(601873,20);
WHEN "101111101" => data <= conv_std_logic_vector(601199,20);
WHEN "101111110" => data <= conv_std_logic_vector(600527,20);
WHEN "101111111" => data <= conv_std_logic_vector(599856,20);
WHEN "110000000" => data <= conv_std_logic_vector(599186,20);
WHEN "110000001" => data <= conv_std_logic_vector(598518,20);
WHEN "110000010" => data <= conv_std_logic_vector(597852,20);
WHEN "110000011" => data <= conv_std_logic_vector(597187,20);
WHEN "110000100" => data <= conv_std_logic_vector(596523,20);
WHEN "110000101" => data <= conv_std_logic_vector(595861,20);
WHEN "110000110" => data <= conv_std_logic_vector(595200,20);
WHEN "110000111" => data <= conv_std_logic_vector(594541,20);
WHEN "110001000" => data <= conv_std_logic_vector(593884,20);
WHEN "110001001" => data <= conv_std_logic_vector(593227,20);
WHEN "110001010" => data <= conv_std_logic_vector(592573,20);
WHEN "110001011" => data <= conv_std_logic_vector(591919,20);
WHEN "110001100" => data <= conv_std_logic_vector(591267,20);
WHEN "110001101" => data <= conv_std_logic_vector(590617,20);
WHEN "110001110" => data <= conv_std_logic_vector(589968,20);
WHEN "110001111" => data <= conv_std_logic_vector(589320,20);
WHEN "110010000" => data <= conv_std_logic_vector(588674,20);
WHEN "110010001" => data <= conv_std_logic_vector(588029,20);
WHEN "110010010" => data <= conv_std_logic_vector(587386,20);
WHEN "110010011" => data <= conv_std_logic_vector(586744,20);
WHEN "110010100" => data <= conv_std_logic_vector(586103,20);
WHEN "110010101" => data <= conv_std_logic_vector(585464,20);
WHEN "110010110" => data <= conv_std_logic_vector(584827,20);
WHEN "110010111" => data <= conv_std_logic_vector(584190,20);
WHEN "110011000" => data <= conv_std_logic_vector(583555,20);
WHEN "110011001" => data <= conv_std_logic_vector(582922,20);
WHEN "110011010" => data <= conv_std_logic_vector(582289,20);
WHEN "110011011" => data <= conv_std_logic_vector(581658,20);
WHEN "110011100" => data <= conv_std_logic_vector(581029,20);
WHEN "110011101" => data <= conv_std_logic_vector(580401,20);
WHEN "110011110" => data <= conv_std_logic_vector(579774,20);
WHEN "110011111" => data <= conv_std_logic_vector(579149,20);
WHEN "110100000" => data <= conv_std_logic_vector(578525,20);
WHEN "110100001" => data <= conv_std_logic_vector(577902,20);
WHEN "110100010" => data <= conv_std_logic_vector(577280,20);
WHEN "110100011" => data <= conv_std_logic_vector(576660,20);
WHEN "110100100" => data <= conv_std_logic_vector(576042,20);
WHEN "110100101" => data <= conv_std_logic_vector(575424,20);
WHEN "110100110" => data <= conv_std_logic_vector(574808,20);
WHEN "110100111" => data <= conv_std_logic_vector(574193,20);
WHEN "110101000" => data <= conv_std_logic_vector(573580,20);
WHEN "110101001" => data <= conv_std_logic_vector(572968,20);
WHEN "110101010" => data <= conv_std_logic_vector(572357,20);
WHEN "110101011" => data <= conv_std_logic_vector(571747,20);
WHEN "110101100" => data <= conv_std_logic_vector(571139,20);
WHEN "110101101" => data <= conv_std_logic_vector(570532,20);
WHEN "110101110" => data <= conv_std_logic_vector(569926,20);
WHEN "110101111" => data <= conv_std_logic_vector(569322,20);
WHEN "110110000" => data <= conv_std_logic_vector(568719,20);
WHEN "110110001" => data <= conv_std_logic_vector(568117,20);
WHEN "110110010" => data <= conv_std_logic_vector(567517,20);
WHEN "110110011" => data <= conv_std_logic_vector(566917,20);
WHEN "110110100" => data <= conv_std_logic_vector(566319,20);
WHEN "110110101" => data <= conv_std_logic_vector(565723,20);
WHEN "110110110" => data <= conv_std_logic_vector(565127,20);
WHEN "110110111" => data <= conv_std_logic_vector(564533,20);
WHEN "110111000" => data <= conv_std_logic_vector(563940,20);
WHEN "110111001" => data <= conv_std_logic_vector(563348,20);
WHEN "110111010" => data <= conv_std_logic_vector(562758,20);
WHEN "110111011" => data <= conv_std_logic_vector(562168,20);
WHEN "110111100" => data <= conv_std_logic_vector(561580,20);
WHEN "110111101" => data <= conv_std_logic_vector(560993,20);
WHEN "110111110" => data <= conv_std_logic_vector(560408,20);
WHEN "110111111" => data <= conv_std_logic_vector(559824,20);
WHEN "111000000" => data <= conv_std_logic_vector(559240,20);
WHEN "111000001" => data <= conv_std_logic_vector(558658,20);
WHEN "111000010" => data <= conv_std_logic_vector(558078,20);
WHEN "111000011" => data <= conv_std_logic_vector(557498,20);
WHEN "111000100" => data <= conv_std_logic_vector(556920,20);
WHEN "111000101" => data <= conv_std_logic_vector(556343,20);
WHEN "111000110" => data <= conv_std_logic_vector(555767,20);
WHEN "111000111" => data <= conv_std_logic_vector(555192,20);
WHEN "111001000" => data <= conv_std_logic_vector(554619,20);
WHEN "111001001" => data <= conv_std_logic_vector(554046,20);
WHEN "111001010" => data <= conv_std_logic_vector(553475,20);
WHEN "111001011" => data <= conv_std_logic_vector(552905,20);
WHEN "111001100" => data <= conv_std_logic_vector(552336,20);
WHEN "111001101" => data <= conv_std_logic_vector(551769,20);
WHEN "111001110" => data <= conv_std_logic_vector(551202,20);
WHEN "111001111" => data <= conv_std_logic_vector(550637,20);
WHEN "111010000" => data <= conv_std_logic_vector(550073,20);
WHEN "111010001" => data <= conv_std_logic_vector(549509,20);
WHEN "111010010" => data <= conv_std_logic_vector(548948,20);
WHEN "111010011" => data <= conv_std_logic_vector(548387,20);
WHEN "111010100" => data <= conv_std_logic_vector(547827,20);
WHEN "111010101" => data <= conv_std_logic_vector(547269,20);
WHEN "111010110" => data <= conv_std_logic_vector(546712,20);
WHEN "111010111" => data <= conv_std_logic_vector(546155,20);
WHEN "111011000" => data <= conv_std_logic_vector(545600,20);
WHEN "111011001" => data <= conv_std_logic_vector(545046,20);
WHEN "111011010" => data <= conv_std_logic_vector(544494,20);
WHEN "111011011" => data <= conv_std_logic_vector(543942,20);
WHEN "111011100" => data <= conv_std_logic_vector(543391,20);
WHEN "111011101" => data <= conv_std_logic_vector(542842,20);
WHEN "111011110" => data <= conv_std_logic_vector(542294,20);
WHEN "111011111" => data <= conv_std_logic_vector(541746,20);
WHEN "111100000" => data <= conv_std_logic_vector(541200,20);
WHEN "111100001" => data <= conv_std_logic_vector(540655,20);
WHEN "111100010" => data <= conv_std_logic_vector(540111,20);
WHEN "111100011" => data <= conv_std_logic_vector(539569,20);
WHEN "111100100" => data <= conv_std_logic_vector(539027,20);
WHEN "111100101" => data <= conv_std_logic_vector(538486,20);
WHEN "111100110" => data <= conv_std_logic_vector(537947,20);
WHEN "111100111" => data <= conv_std_logic_vector(537408,20);
WHEN "111101000" => data <= conv_std_logic_vector(536871,20);
WHEN "111101001" => data <= conv_std_logic_vector(536334,20);
WHEN "111101010" => data <= conv_std_logic_vector(535799,20);
WHEN "111101011" => data <= conv_std_logic_vector(535265,20);
WHEN "111101100" => data <= conv_std_logic_vector(534732,20);
WHEN "111101101" => data <= conv_std_logic_vector(534200,20);
WHEN "111101110" => data <= conv_std_logic_vector(533669,20);
WHEN "111101111" => data <= conv_std_logic_vector(533139,20);
WHEN "111110000" => data <= conv_std_logic_vector(532610,20);
WHEN "111110001" => data <= conv_std_logic_vector(532082,20);
WHEN "111110010" => data <= conv_std_logic_vector(531555,20);
WHEN "111110011" => data <= conv_std_logic_vector(531029,20);
WHEN "111110100" => data <= conv_std_logic_vector(530505,20);
WHEN "111110101" => data <= conv_std_logic_vector(529981,20);
WHEN "111110110" => data <= conv_std_logic_vector(529458,20);
WHEN "111110111" => data <= conv_std_logic_vector(528937,20);
WHEN "111111000" => data <= conv_std_logic_vector(528416,20);
WHEN "111111001" => data <= conv_std_logic_vector(527897,20);
WHEN "111111010" => data <= conv_std_logic_vector(527378,20);
WHEN "111111011" => data <= conv_std_logic_vector(526860,20);
WHEN "111111100" => data <= conv_std_logic_vector(526344,20);
WHEN "111111101" => data <= conv_std_logic_vector(525828,20);
WHEN "111111110" => data <= conv_std_logic_vector(525314,20);
WHEN "111111111" => data <= conv_std_logic_vector(524800,20);
WHEN others => data <= conv_std_logic_vector(0,20);
END CASE;
END PROCESS;
END rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.math_real.all;
entity test is
generic (
BITS : positive := 2
);
end entity test;
architecture rtl of test is
constant count : positive := 2 ** BITS - 1;
subtype node_t is integer range 0 to count;
begin
end;
|
--
---- SPI Module - entity/architecture pair
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
---- Filename: qspi_mode_0_module.vhd
---- Version: v3.0
---- Description: Serial Peripheral Interface (SPI) Module for interfacing
---- with a 32-bit AXI4 Bus.
----
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg;
use lib_pkg_v1_0_2.lib_pkg.log2;
library axi_lite_ipif_v3_0_4;
use axi_lite_ipif_v3_0_4.axi_lite_ipif;
use axi_lite_ipif_v3_0_4.ipif_pkg.all;
library lib_cdc_v1_0_2;
use lib_cdc_v1_0_2.cdc_sync;
library unisim;
use unisim.vcomponents.FD;
use unisim.vcomponents.FDRE;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------:
-- C_SCK_RATIO -- 2, 4, 16, 32, , , , 1024, 2048 SPI
-- clock ratio (16*N), where N=1,2,3...
-- C_SPI_NUM_BITS_REG -- Width of SPI Control register
-- in this module
-- C_NUM_SS_BITS -- Total number of SS-bits
-- C_NUM_TRANSFER_BITS -- SPI Serial transfer width.
-- Can be 8, 16 or 32 bit wide
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- SYSTEM
-- Bus2IP_Clk -- Bus to IP clock
-- Soft_Reset_op -- Soft_Reset_op Signal
-- OTHER INTERFACE
-- Slave_MODF_strobe -- Slave mode fault strobe
-- MODF_strobe -- Mode fault strobe
-- SR_3_MODF -- Mode fault error flag
-- SR_5_Tx_Empty -- Transmit Empty
-- Control_Reg -- Control Register
-- Slave_Select_Reg -- Slave Select Register
-- Transmit_Data -- Data Transmit Register Interface
-- Receive_Data -- Data Receive Register Interface
-- SPIXfer_done -- SPI transfer done flag
-- DTR_underrun -- DTR underrun generation signal
-- SPI INTERFACE
-- SCK_I -- SPI Bus Clock Input
-- SCK_O_reg -- SPI Bus Clock Output
-- SCK_T -- SPI Bus Clock 3-state Enable
-- (3-state when high)
-- MISO_I -- Master out,Slave in Input
-- MISO_O -- Master out,Slave in Output
-- MISO_T -- Master out,Slave in 3-state Enable
-- MOSI_I -- Master in,Slave out Input
-- MOSI_O -- Master in,Slave out Output
-- MOSI_T -- Master in,Slave out 3-state Enable
-- SPISEL -- Local SPI slave select active low input
-- has to be initialzed to VCC
-- SS_I -- Input of slave select vector
-- of length N input where there are
-- N SPI devices,but not connected
-- SS_O -- One-hot encoded,active low slave select
-- vector of length N ouput
-- SS_T -- Single 3-state control signal for
-- slave select vector of length N
-- (3-state when high)
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity qspi_mode_0_module is
generic
(
--C_SPI_MODE : integer;
C_SCK_RATIO : integer;
C_NUM_SS_BITS : integer;
C_NUM_TRANSFER_BITS : integer;
C_USE_STARTUP : integer;
C_SPICR_REG_WIDTH : integer;
C_SUB_FAMILY : string;
C_FIFO_EXIST : integer
);
port
(
Bus2IP_Clk : in std_logic;
Soft_Reset_op : in std_logic;
----------------------
-- Control Reg is 10-bit wide
SPICR_0_LOOP : in std_logic;
SPICR_1_SPE : in std_logic;
SPICR_2_MASTER_N_SLV : in std_logic;
SPICR_3_CPOL : in std_logic;
SPICR_4_CPHA : in std_logic;
SPICR_5_TXFIFO_RST : in std_logic;
SPICR_6_RXFIFO_RST : in std_logic;
SPICR_7_SS : in std_logic;
SPICR_8_TR_INHIBIT : in std_logic;
SPICR_9_LSB : in std_logic;
----------------------
Rx_FIFO_Empty_i_no_fifo : in std_logic;
SR_3_MODF : in std_logic;
SR_5_Tx_Empty : in std_logic;
Slave_MODF_strobe : out std_logic;
MODF_strobe : out std_logic;
SPIXfer_done_rd_tx_en: out std_logic;
Slave_Select_Reg : in std_logic_vector(0 to (C_NUM_SS_BITS-1));
Transmit_Data : in std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
Receive_Data : out std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
SPIXfer_done : out std_logic;
DTR_underrun : out std_logic;
SPISEL_pulse_op : out std_logic;
SPISEL_d1_reg : out std_logic;
--SPI Interface
SCK_I : in std_logic;
SCK_O_reg : out std_logic;
SCK_T : out std_logic;
MISO_I : in std_logic;
MISO_O : out std_logic;
MISO_T : out std_logic;
MOSI_I : in std_logic;
MOSI_O : out std_logic;
MOSI_T : out std_logic;
SPISEL : in std_logic;
SS_I : in std_logic_vector((C_NUM_SS_BITS-1) downto 0);
SS_O : out std_logic_vector((C_NUM_SS_BITS-1) downto 0);
SS_T : out std_logic;
control_bit_7_8 : in std_logic_vector(0 to 1);
Mst_N_Slv_mode : out std_logic;
Rx_FIFO_Full : in std_logic;
reset_RcFIFO_ptr_to_spi : in std_logic;
DRR_Overrun_reg : out std_logic;
tx_cntr_xfer_done : out std_logic
);
end qspi_mode_0_module;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of qspi_mode_0_module is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Function Declarations
---------------------------------------------------------------------
------------------------
-- spcl_log2 : Performs log2(x) function for value of C_SCK_RATIO > 2
------------------------
function spcl_log2(x : natural) return integer is
variable j : integer := 0;
variable k : integer := 0;
begin
if(C_SCK_RATIO /= 2) then
for i in 0 to 11 loop
if(2**i >= x) then
if(k = 0) then
j := i;
end if;
k := 1;
end if;
end loop;
return j;
else
-- coverage off
return 2;
-- coverage on
end if;
end spcl_log2;
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
-------------------------------------------------------------------------------
-- Constant Declarations
------------------------------------------------------------------
constant RESET_ACTIVE : std_logic := '1';
constant COUNT_WIDTH : INTEGER := log2(C_NUM_TRANSFER_BITS)+1;
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal Ratio_Count : std_logic_vector
(0 to (spcl_log2(C_SCK_RATIO))-2);
signal Count : std_logic_vector
(COUNT_WIDTH downto 0)
:= (others => '0');
signal LSB_first : std_logic;
signal Mst_Trans_inhibit : std_logic;
signal Manual_SS_mode : std_logic;
signal CPHA : std_logic;
signal CPOL : std_logic;
signal Mst_N_Slv : std_logic;
signal SPI_En : std_logic;
signal Loop_mode : std_logic;
signal transfer_start : std_logic;
signal transfer_start_d1 : std_logic;
signal transfer_start_pulse : std_logic;
signal SPIXfer_done_int : std_logic;
signal SPIXfer_done_int_d1 : std_logic;
signal SPIXfer_done_int_pulse : std_logic;
signal SPIXfer_done_int_pulse_d1 : std_logic;
signal sck_o_int : std_logic;
signal sck_o_in : std_logic;
signal Count_trigger : std_logic;
signal Count_trigger_d1 : std_logic;
signal Count_trigger_pulse : std_logic;
signal Sync_Set : std_logic;
signal Sync_Reset : std_logic;
signal Serial_Dout : std_logic;
signal Serial_Din : std_logic;
signal Shift_Reg : std_logic_vector
(0 to C_NUM_TRANSFER_BITS-1);
signal SS_Asserted : std_logic;
signal SS_Asserted_1dly : std_logic;
signal Allow_Slave_MODF_Strobe : std_logic;
signal Allow_MODF_Strobe : std_logic;
signal Loading_SR_Reg_int : std_logic;
signal sck_i_d1 : std_logic;
signal spisel_d1 : std_logic;
signal spisel_pulse : std_logic;
signal rising_edge_sck_i : std_logic;
signal falling_edge_sck_i : std_logic;
signal edge_sck_i : std_logic;
signal MODF_strobe_int : std_logic;
signal master_tri_state_en_control: std_logic;
signal slave_tri_state_en_control: std_logic;
-- following signals are added for use in variouos clock ratio modes.
signal sck_d1 : std_logic;
signal sck_d2 : std_logic;
signal sck_rising_edge : std_logic;
signal rx_shft_reg : std_logic_vector(0 to C_NUM_TRANSFER_BITS-1);
signal SPIXfer_done_int_pulse_d2 : std_logic;
signal SPIXfer_done_int_pulse_d3 : std_logic;
-- added synchronization signals for SPISEL and SCK_I
signal SPISEL_sync : std_logic;
signal SCK_I_sync : std_logic;
-- following register are declared for making data path clear in different modes
signal rx_shft_reg_s : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1))
:=(others => '0');
signal rx_shft_reg_mode_0011 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1))
:=(others => '0');
signal rx_shft_reg_mode_0110 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1))
:=(others => '0');
signal sck_fe1 : std_logic;
signal sck_d21 : std_logic:='0';
signal sck_d11 : std_logic:='0';
signal SCK_O_1 : std_logic:='0';
signal receive_Data_int : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1))
:=(others => '0');
signal mosi_i_sync : std_logic;
signal miso_i_sync : std_logic;
signal serial_dout_int : std_logic;
--
signal Mst_Trans_inhibit_d1, Mst_Trans_inhibit_pulse : std_logic;
signal no_slave_selected : std_logic;
type STATE_TYPE is
(IDLE, -- decode command can be combined here later
TRANSFER_OKAY,
TEMP_TRANSFER_OKAY
);
signal spi_cntrl_ps: STATE_TYPE;
signal spi_cntrl_ns: STATE_TYPE;
signal stop_clock_reg : std_logic;
signal stop_clock : std_logic;
signal Rx_FIFO_Full_reg, DRR_Overrun_reg_int : std_logic;
signal transfer_start_d2 : std_logic;
signal transfer_start_d3 : std_logic;
signal SR_5_Tx_Empty_d1 : std_logic;
signal SR_5_Tx_Empty_pulse: std_logic;
signal SR_5_Tx_comeplete_Empty : std_logic;
signal falling_edge_sck_i_d1, rising_edge_sck_i_d1 : std_logic;
signal spisel_d2 : std_logic;
signal xfer_done_fifo_0 : std_logic;
signal rst_xfer_done_fifo_0 : std_logic;
signal Rx_FIFO_Empty_i_no_fifo_sync : std_logic;
signal SPIXfer_done_drr : std_logic;
-------------------------------------------------------------------------------
-- Architecture Starts
-------------------------------------------------------------------------------
begin
SPIXfer_done <= SPIXfer_done_drr;
--------------------------------------------------
LOCAL_TX_EMPTY_RX_FULL_FIFO_0_GEN: if C_FIFO_EXIST = 0 generate
-----
begin
rx_empty_no_fifo_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => 2
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => Rx_FIFO_Empty_i_no_fifo,
scndry_aclk => Bus2IP_Clk,
prmry_vect_in => (others => '0' ),
scndry_resetn => '0',
scndry_out => Rx_FIFO_Empty_i_no_fifo_sync
);
-----------------------------------------
-----------------------------------------
TX_EMPTY_MODE_0_P: process (Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) or
(transfer_start_pulse = '1') or
(rst_xfer_done_fifo_0 = '1')then
xfer_done_fifo_0 <= '0';
elsif(SPIXfer_done_int_pulse = '1')then
xfer_done_fifo_0 <= '1';
end if;
end if;
end process TX_EMPTY_MODE_0_P;
------------------------------
------------------------------
--RX_FULL_CHECK_PROCESS: process(Bus2IP_Clk) is
--begin
-- if(Bus2IP_Clk'event and Bus2IP_Clk='1') then
-- if (Soft_Reset_op = RESET_ACTIVE)or(reset_RcFIFO_ptr_to_spi = '1') then
-- Rx_FIFO_Full_reg <= '0';
-- elsif(SPIXfer_done_int_pulse = '1')then
-- Rx_FIFO_Full_reg <= '1';
-- end if;
-- end if;
--end process RX_FULL_CHECK_PROCESS;
RX_FULL_CHECK_PROCESS: process(Bus2IP_Clk) is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
Rx_FIFO_Full_reg <= '0';
elsif(DRR_Overrun_reg_int = '1') then
Rx_FIFO_Full_reg <= '0';
elsif((SPIXfer_done_int_pulse = '1') and (Rx_FIFO_Empty_i_no_fifo_sync = '0'))then
Rx_FIFO_Full_reg <= '1';
end if;
end if;
end process RX_FULL_CHECK_PROCESS;
DRR_OVERRUN_REG_PROCESS:process(Bus2IP_Clk) is
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
DRR_Overrun_reg_int <= '0';
else
DRR_Overrun_reg_int <= not(DRR_Overrun_reg_int or Soft_Reset_op) and
Rx_FIFO_Full_reg and
SPIXfer_done_int_pulse_d1; --_d2;
--SPIXfer_done_int_pulse_d1; --_d2;
end if;
end if;
end process DRR_OVERRUN_REG_PROCESS;
--RX_FULL_CHECK_PROCESS: process(Bus2IP_Clk) is
--begin
-- if(Bus2IP_Clk'event and Bus2IP_Clk='1') then
-- if (Soft_Reset_op = RESET_ACTIVE)or(reset_RcFIFO_ptr_to_spi = '1') then
-- --if ((Soft_Reset_op = RESET_ACTIVE)or(reset_RcFIFO_ptr_to_spi = '1') or (Rx_FIFO_Full_reg = '1' and SPIXfer_done_int_pulse = '0')) then
-- --if ((Soft_Reset_op = RESET_ACTIVE)or(reset_RcFIFO_ptr_to_spi = '1') or (Rx_FIFO_Empty_i_no_fifo = '1'))then
-- Rx_FIFO_Full_reg <= '0';
-- elsif(SPIXfer_done_int_pulse = '1')then
-- Rx_FIFO_Full_reg <= '1';
-- elsif(Rx_FIFO_Empty_i_no_fifo = '1')then --Clear only if no simultaneous SPIXfer_done_int_pulse
-- Rx_FIFO_Full_reg <= '0';
-- end if;
-- end if;
--end process RX_FULL_CHECK_PROCESS;
-----------------------------------
PS_TO_NS_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
spi_cntrl_ps <= IDLE;
stop_clock_reg <= '0';
else
spi_cntrl_ps <= spi_cntrl_ns;
stop_clock_reg <= stop_clock;
end if;
end if;
end process PS_TO_NS_PROCESS;
-----------------------------
SPI_STATE_MACHINE_P: process(
Mst_N_Slv,
stop_clock_reg,
spi_cntrl_ps,
no_slave_selected,
SR_5_Tx_Empty,
SPIXfer_done_int_pulse,
transfer_start_pulse,
xfer_done_fifo_0
)
begin
stop_clock <= '0';
rst_xfer_done_fifo_0 <= '0';
--------------------------
case spi_cntrl_ps is
--------------------------
when IDLE => if(SR_5_Tx_Empty = '0' and transfer_start_pulse = '1' and Mst_N_Slv = '1') then
stop_clock <= '0';
spi_cntrl_ns <= TRANSFER_OKAY;
else
stop_clock <= SR_5_Tx_Empty;
spi_cntrl_ns <= IDLE;
end if;
-------------------------------------
when TRANSFER_OKAY => if(SR_5_Tx_Empty = '1') then
if(no_slave_selected = '1')then
stop_clock <= '1';
spi_cntrl_ns <= IDLE;
else
spi_cntrl_ns <= TEMP_TRANSFER_OKAY;
end if;
else
spi_cntrl_ns <= TRANSFER_OKAY;
end if;
-------------------------------------
when TEMP_TRANSFER_OKAY => stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
stop_clock <= xfer_done_fifo_0;
if (no_slave_selected = '1')then
spi_cntrl_ns <= IDLE;
--code coverage -- elsif(SPIXfer_done_int_pulse='1')then
--code coverage -- stop_clock <= SR_5_Tx_Empty;
--code coverage -- spi_cntrl_ns <= TEMP_TRANSFER_OKAY;
else
spi_cntrl_ns <= TEMP_TRANSFER_OKAY;
end if;
else
stop_clock <= '0';
rst_xfer_done_fifo_0 <= '1';
spi_cntrl_ns <= TRANSFER_OKAY;
end if;
-------------------------------------
-- coverage off
when others => spi_cntrl_ns <= IDLE;
-- coverage on
-------------------------------------
end case;
--------------------------
end process SPI_STATE_MACHINE_P;
-----------------------------------------------
end generate LOCAL_TX_EMPTY_RX_FULL_FIFO_0_GEN;
-------------------------------------------------------------------------------
LOCAL_TX_EMPTY_FIFO_12_GEN: if C_FIFO_EXIST /= 0 generate
-----
begin
-----
xfer_done_fifo_0 <= '0';
--RX_FULL_CHECK_PROCESS: process(Bus2IP_Clk) is
------------------------
--begin
-------
-- if(Bus2IP_Clk'event and Bus2IP_Clk='1') then
-- if (Soft_Reset_op = RESET_ACTIVE) then
-- Rx_FIFO_Full_reg <= '0';
-- elsif(reset_RcFIFO_ptr_to_spi = '1') or (DRR_Overrun_reg_int = '1') then
-- Rx_FIFO_Full_reg <= '0';
-- elsif(SPIXfer_done_int_pulse = '1')and (Rx_FIFO_Full = '1') then
-- Rx_FIFO_Full_reg <= '1';
-- end if;
-- end if;
--end process RX_FULL_CHECK_PROCESS;
------------------------------------
--DRR_OVERRUN_REG_PROCESS:process(Bus2IP_Clk) is
-------
--begin
-------
-- if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
-- if (Soft_Reset_op = RESET_ACTIVE) then
-- DRR_Overrun_reg_int <= '0';
-- else
-- DRR_Overrun_reg_int <= not(DRR_Overrun_reg_int or Soft_Reset_op) and
-- Rx_FIFO_Full_reg and
-- SPIXfer_done_int_pulse_d1; --_d2;
-- --SPIXfer_done_int_pulse_d1; --_d2;
-- end if;
-- end if;
--end process DRR_OVERRUN_REG_PROCESS;
DRR_OVERRUN_REG_PROCESS:process(Bus2IP_Clk) is
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
DRR_Overrun_reg_int <= '0';
else
DRR_Overrun_reg_int <= not(DRR_Overrun_reg_int or Soft_Reset_op) and
Rx_FIFO_Full and
SPIXfer_done_drr; --_d2;
end if;
end if;
end process DRR_OVERRUN_REG_PROCESS;
PS_TO_NS_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
spi_cntrl_ps <= IDLE;
stop_clock_reg <= '0';
else
spi_cntrl_ps <= spi_cntrl_ns;
stop_clock_reg <= stop_clock;
end if;
end if;
end process PS_TO_NS_PROCESS;
-----------------------------
SPI_STATE_MACHINE_P: process(
Mst_N_Slv ,
stop_clock_reg ,
spi_cntrl_ps ,
no_slave_selected ,
SR_5_Tx_Empty ,
SPIXfer_done_int_pulse ,
transfer_start_pulse ,
SPIXfer_done_int_pulse_d2,
SR_5_Tx_comeplete_Empty,
Loop_mode
)is
-----
begin
-----
stop_clock <= '0';
--rst_xfer_done_fifo_0 <= '0';
--------------------------
case spi_cntrl_ps is
--------------------------
when IDLE => if(SR_5_Tx_Empty = '0' and transfer_start_pulse = '1' and Mst_N_Slv = '1') then
spi_cntrl_ns <= TRANSFER_OKAY;
stop_clock <= '0';
else
stop_clock <= SR_5_Tx_Empty;
spi_cntrl_ns <= IDLE;
end if;
-------------------------------------
when TRANSFER_OKAY => if(SR_5_Tx_Empty = '1') then
--if(no_slave_selected = '1')then
if(SR_5_Tx_comeplete_Empty = '1' and
SPIXfer_done_int_pulse_d2 = '1') then
stop_clock <= '1';
spi_cntrl_ns <= IDLE;
else
spi_cntrl_ns <= TEMP_TRANSFER_OKAY;
end if;
else
spi_cntrl_ns <= TRANSFER_OKAY;
end if;
-------------------------------------
when TEMP_TRANSFER_OKAY => stop_clock <= stop_clock_reg;
--if(SR_5_Tx_Empty='1')then
if(SR_5_Tx_comeplete_Empty='1')then
-- stop_clock <= xfer_done_fifo_0;
if (Loop_mode = '1' and
SPIXfer_done_int_pulse_d2 = '1')then
stop_clock <= '1';
spi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
stop_clock <= SR_5_Tx_Empty;
spi_cntrl_ns <= TEMP_TRANSFER_OKAY;
elsif(no_slave_selected = '1') then
stop_clock <= '1';
spi_cntrl_ns <= IDLE;
else
spi_cntrl_ns <= TEMP_TRANSFER_OKAY;
end if;
else
--stop_clock <= '0';
--rst_xfer_done_fifo_0 <= '1';
spi_cntrl_ns <= TRANSFER_OKAY;
end if;
-------------------------------------
-- coverage off
when others => spi_cntrl_ns <= IDLE;
-- coverage on
-------------------------------------
end case;
--------------------------
end process SPI_STATE_MACHINE_P;
----------------------------------------
----------------------------------------
end generate LOCAL_TX_EMPTY_FIFO_12_GEN;
-----------------------------------------
SR_5_TX_EMPTY_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
SR_5_Tx_Empty_d1 <= '0';
else
SR_5_Tx_Empty_d1 <= SR_5_Tx_Empty;
end if;
end if;
end process SR_5_TX_EMPTY_PROCESS;
----------------------------------
SR_5_Tx_Empty_pulse <= SR_5_Tx_Empty_d1 and not (SR_5_Tx_Empty);
----------------------------------
-------------------------------------------------------------------------------
-- Combinatorial operations
-------------------------------------------------------------------------------
-----------------------------------------------------------
LSB_first <= SPICR_9_LSB; -- Control_Reg(0);
Mst_Trans_inhibit <= SPICR_8_TR_INHIBIT; -- Control_Reg(1);
Manual_SS_mode <= SPICR_7_SS; -- Control_Reg(2);
CPHA <= SPICR_4_CPHA; -- Control_Reg(5);
CPOL <= SPICR_3_CPOL; -- Control_Reg(6);
Mst_N_Slv <= SPICR_2_MASTER_N_SLV; -- Control_Reg(7);
SPI_En <= SPICR_1_SPE; -- Control_Reg(8);
Loop_mode <= SPICR_0_LOOP; -- Control_Reg(9);
Mst_N_Slv_mode <= SPICR_2_MASTER_N_SLV; -- Control_Reg(7);
-----------------------------------------------------------
MOSI_O <= Serial_Dout;
MISO_O <= Serial_Dout;
Receive_Data <= receive_Data_int;
DRR_Overrun_reg <= DRR_Overrun_reg_int;
MST_TRANS_INHIBIT_D1_I: component FD
generic map
(
INIT => '1'
)
port map
(
Q => Mst_Trans_inhibit_d1,
C => Bus2IP_Clk,
D => Mst_Trans_inhibit
);
Mst_Trans_inhibit_pulse <= Mst_Trans_inhibit and (not Mst_Trans_inhibit_d1);
-------------------------------------------------------------------------------
--* -------------------------------------------------------------------------------
--* -- MASTER_TRIST_EN_PROCESS : If not master make tristate enabled
--* ----------------------------
master_tri_state_en_control <=
'0' when
(
(control_bit_7_8(0)='1') and -- decides master/slave mode
(control_bit_7_8(1)='1') and -- decide the spi_en
((MODF_strobe_int or SR_3_MODF)='0') and --no mode fault
(Loop_mode = '0')
) else
'1';
--SPI_TRISTATE_CONTROL_II : Tri-state register for SCK_T, ideal state-deactive
SPI_TRISTATE_CONTROL_II: component FD
generic map
(
INIT => '1'
)
port map
(
Q => SCK_T,
C => Bus2IP_Clk,
D => master_tri_state_en_control
);
--SPI_TRISTATE_CONTROL_III: tri-state register for MOSI, ideal state-deactive
SPI_TRISTATE_CONTROL_III: component FD
generic map
(
INIT => '1'
)
port map
(
Q => MOSI_T,
C => Bus2IP_Clk,
D => master_tri_state_en_control
);
--SPI_TRISTATE_CONTROL_IV: tri-state register for SS,ideal state-deactive
SPI_TRISTATE_CONTROL_IV: component FD
generic map
(
INIT => '1'
)
port map
(
Q => SS_T,
C => Bus2IP_Clk,
D => master_tri_state_en_control
);
--* -------------------------------------------------------------------------------
--* -- SLAVE_TRIST_EN_PROCESS : If slave mode, then make tristate enabled
--* ---------------------------
slave_tri_state_en_control <=
'0' when
(
(control_bit_7_8(0)='0') and -- decides master/slave
(control_bit_7_8(1)='1') and -- decide the spi_en
(SPISEL_sync = '0') and
(Loop_mode = '0')
) else
'1';
--SPI_TRISTATE_CONTROL_V: tri-state register for MISO, ideal state-deactive
SPI_TRISTATE_CONTROL_V: component FD
generic map
(
INIT => '1'
)
port map
(
Q => MISO_T,
C => Bus2IP_Clk,
D => slave_tri_state_en_control
);
-------------------------------------------------------------------------------
DTR_COMPLETE_EMPTY_P:process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1')then
if(SR_5_Tx_Empty = '1' and SPIXfer_done_int_pulse = '1')then
SR_5_Tx_comeplete_Empty <= '1';
elsif(SR_5_Tx_Empty = '0')then
SR_5_Tx_comeplete_Empty <= '0';
end if;
end if;
end process DTR_COMPLETE_EMPTY_P;
---------------------------------
DTR_UNDERRUN_FIFO_0_GEN: if C_FIFO_EXIST = 0 generate
begin
-- DTR_UNDERRUN_PROCESS_P : For Generating DTR underrun error
-------------------------
DTR_UNDERRUN_PROCESS_P: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or
(SPISEL_sync = '1') or
(Mst_N_Slv = '1')--master mode
) then
DTR_underrun <= '0';
elsif((Mst_N_Slv = '0') and (SPI_En = '1')) then-- slave mode
if (SR_5_Tx_comeplete_Empty = '1') then
--if(SPIXfer_done_int_pulse_d2 = '1') then
DTR_underrun <= '1';
--end if;
else
DTR_underrun <= '0';
end if;
end if;
end if;
end process DTR_UNDERRUN_PROCESS_P;
-------------------------------------
end generate DTR_UNDERRUN_FIFO_0_GEN;
DTR_UNDERRUN_FIFO_EXIST_GEN: if C_FIFO_EXIST /= 0 generate
begin
-- DTR_UNDERRUN_PROCESS_P : For Generating DTR underrun error
-------------------------
DTR_UNDERRUN_PROCESS_P: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or
(SPISEL_sync = '1') or
(Mst_N_Slv = '1')--master mode
) then
DTR_underrun <= '0';
elsif((Mst_N_Slv = '0') and (SPI_En = '1')) then-- slave mode
if (SR_5_Tx_comeplete_Empty = '1') then
if(SPIXfer_done_int_pulse = '1') then
DTR_underrun <= '1';
end if;
else
DTR_underrun <= '0';
end if;
end if;
end if;
end process DTR_UNDERRUN_PROCESS_P;
-------------------------------------
end generate DTR_UNDERRUN_FIFO_EXIST_GEN;
-------------------------------------------------------------------------------
-- SPISEL_SYNC: first synchronize the incoming signal, this is required is slave
--------------- mode of the core.
SPISEL_REG: component FD
generic map
(
INIT => '1' -- default '1' to make the device in default master mode
)
port map
(
Q => SPISEL_sync,
C => Bus2IP_Clk,
D => SPISEL
);
---- SPISEL_DELAY_1CLK_PROCESS_P : Detect active SCK edge in slave mode
-------------------------------
SPISEL_DELAY_1CLK_PROCESS_P: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
spisel_d1 <= '1';
spisel_d2 <= '1';
else
spisel_d1 <= SPISEL_sync;
spisel_d2 <= spisel_d1;
end if;
end if;
end process SPISEL_DELAY_1CLK_PROCESS_P;
--SPISEL_DELAY_1CLK: component FD
-- generic map
-- (
-- INIT => '1' -- default '1' to make the device in default master mode
-- )
-- port map
-- (
-- Q => spisel_d1,
-- C => Bus2IP_Clk,
-- D => SPISEL_sync
-- );
--SPISEL_DELAY_2CLK: component FD
-- generic map
-- (
-- INIT => '1' -- default '1' to make the device in default master mode
-- )
-- port map
-- (
-- Q => spisel_d2,
-- C => Bus2IP_Clk,
-- D => spisel_d1
-- );
---- spisel pulse generating logic
---- this one clock cycle pulse will be available for data loading into
---- shift register
--spisel_pulse <= (not SPISEL_sync) and spisel_d1;
------------------------------------------------
-- spisel pulse generating logic
-- this one clock cycle pulse will be available for data loading into
-- shift register
spisel_pulse <= (not spisel_d1) and spisel_d2;
-- --------|__________ -- SPISEL
-- ----------|________ -- SPISEL_sync
-- -------------|_____ -- spisel_d1
-- ----------------|___-- spisel_d2
-- _____________|--|__ -- SPISEL_pulse_op
SPISEL_pulse_op <= spisel_pulse;
SPISEL_d1_reg <= spisel_d2;
-------------------------------------------------------------------------------
--SCK_I_SYNC: first synchronize incomming signal
-------------
SCK_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => SCK_I_sync,
C => Bus2IP_Clk,
D => SCK_I
);
------------------------------------------------------------------
-- SCK_I_DELAY_1CLK_PROCESS : Detect active SCK edge in slave mode on +ve edge
SCK_I_DELAY_1CLK_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
sck_i_d1 <= '0';
else
sck_i_d1 <= SCK_I_sync;
end if;
end if;
end process SCK_I_DELAY_1CLK_PROCESS;
-------------------------------------------------------------------------------
-- RISING_EDGE_CLK_RATIO_4_GEN: to synchronise the incoming clock signal in
-- slave mode in SCK ratio = 4
RISING_EDGE_CLK_RATIO_4_GEN : if C_SCK_RATIO = 4 generate
begin
-- generate a SCK control pulse for rising edge as well as falling edge
rising_edge_sck_i <= SCK_I and (not(SCK_I_sync)) and (not(SPISEL_sync));
falling_edge_sck_i <= (not(SCK_I) and SCK_I_sync) and (not(SPISEL_sync));
end generate RISING_EDGE_CLK_RATIO_4_GEN;
-------------------------------------------------------------------------------
-- RISING_EDGE_CLK_RATIO_OTHERS_GEN: Due to timing crunch, in SCK> 4 mode,
-- the incoming clock signal cant be synchro
-- -nized with internal AXI clock.
-- slave mode operation on SCK_RATIO=2 isn't
-- supported in the core.
RISING_EDGE_CLK_RATIO_OTHERS_GEN: if ((C_SCK_RATIO /= 2) and (C_SCK_RATIO /= 4))
generate
begin
-- generate a SCK control pulse for rising edge as well as falling edge
rising_edge_sck_i <= SCK_I_sync and (not(sck_i_d1)) and (not(SPISEL_sync));
falling_edge_sck_i <= (not(SCK_I_sync) and sck_i_d1) and (not(SPISEL_sync));
end generate RISING_EDGE_CLK_RATIO_OTHERS_GEN;
-------------------------------------------------------------------------------
-- combine rising edge as well as falling edge as a single signal
edge_sck_i <= rising_edge_sck_i or falling_edge_sck_i;
no_slave_selected <= and_reduce(Slave_Select_Reg(0 to (C_NUM_SS_BITS-1)));
-------------------------------------------------------------------------------
-- TRANSFER_START_PROCESS : Generate transfer start signal. When the transfer
-- gets completed, SPI Transfer done strobe pulls
-- transfer_start back to zero.
---------------------------
TRANSFER_START_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE or
(
Mst_N_Slv = '1' and -- If Master Mode
(
SPI_En = '0' or -- enable not asserted or
(SPIXfer_done_int = '1' and SR_5_Tx_Empty = '1') or -- no data in Tx reg/FIFO or
-------------------- To remove glitch----------------((SPIXfer_done_int = '1' or SPIXfer_done_int_pulse_d1 = '1' ) and SR_5_Tx_Empty = '1') or -- no data in Tx reg/FIFO or
SR_3_MODF = '1' or -- mode fault error
Mst_Trans_inhibit = '1' or -- Do not start if Mst xfer inhibited
stop_clock = '1'
)
) or
(
Mst_N_Slv = '0' and -- If Slave Mode
(
SPI_En = '0' -- enable not asserted or
)
)
)then
transfer_start <= '0';
else
-- Delayed SPIXfer_done_int_pulse to work for synchronous design and to remove
-- asserting of loading_sr_reg in master mode after SR_5_Tx_Empty goes to 1
--if((SPIXfer_done_int_pulse = '1') or
-- (SPIXfer_done_int_pulse_d1 = '1') or
-- (SPIXfer_done_int_pulse_d2='1')) then-- this is added to remove
-- -- glitch at the end of
-- -- transfer in AUTO mode
-- transfer_start <= '0'; -- Set to 0 for at least 1 period
-- else
transfer_start <= '1'; -- Proceed with SPI Transfer
-- end if;
end if;
end if;
end process TRANSFER_START_PROCESS;
-------------------------------------------------------------------------------
-- TRANSFER_START_1CLK_PROCESS : Delay transfer start by 1 clock cycle
--------------------------------
TRANSFER_START_1CLK_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
transfer_start_d1 <= '0';
transfer_start_d2 <= '0';
transfer_start_d3 <= '0';
else
transfer_start_d1 <= transfer_start;
transfer_start_d2 <= transfer_start_d1;
transfer_start_d3 <= transfer_start_d2;
end if;
end if;
end process TRANSFER_START_1CLK_PROCESS;
-- transfer start pulse generating logic
transfer_start_pulse <= transfer_start and (not(transfer_start_d1));
---------------------------------------------------------------------------------
---- TRANSFER_DONE_PROCESS : Generate SPI transfer done signal
----------------------------
--TRANSFER_DONE_PROCESS: process(Bus2IP_Clk)
--begin
-- if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
-- if(Soft_Reset_op = RESET_ACTIVE or transfer_start_pulse = '1' or (and_reduce(Count(COUNT_WIDTH-1 downto (COUNT_WIDTH-COUNT_WIDTH)))='1')) then
-- SPIXfer_done_int <= '0';
-- --elsif (transfer_start_pulse = '1') then
-- -- SPIXfer_done_int <= '0';
-- elsif(and_reduce(Count((COUNT_WIDTH-1) downto (COUNT_WIDTH-COUNT_WIDTH+1))) = '1') then --(Count(COUNT_WIDTH) = '1') then
-- SPIXfer_done_int <= '1';
-- end if;
-- end if;
--end process TRANSFER_DONE_PROCESS;
-------------------------------------------------------------------------------
-- TRANSFER_DONE_1CLK_PROCESS : Delay SPI transfer done signal by 1 clock cycle
-------------------------------
TRANSFER_DONE_1CLK_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
SPIXfer_done_int_d1 <= '0';
else
SPIXfer_done_int_d1 <= SPIXfer_done_int;
end if;
end if;
end process TRANSFER_DONE_1CLK_PROCESS;
--
-- transfer done pulse generating logic
SPIXfer_done_int_pulse <= SPIXfer_done_int and (not(SPIXfer_done_int_d1));
-------------------------------------------------------------------------------
-- TRANSFER_DONE_PULSE_DLY_PROCESS : Delay SPI transfer done pulse by 1 and 2
-- clock cycles
------------------------------------
-- Delay the Done pulse by a further cycle. This is used as the output Rx
-- data strobe when C_SCK_RATIO = 2
TRANSFER_DONE_PULSE_DLY_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
SPIXfer_done_int_pulse_d1 <= '0';
SPIXfer_done_int_pulse_d2 <= '0';
SPIXfer_done_int_pulse_d3 <= '0';
else
SPIXfer_done_int_pulse_d1 <= SPIXfer_done_int_pulse;
SPIXfer_done_int_pulse_d2 <= SPIXfer_done_int_pulse_d1;
SPIXfer_done_int_pulse_d3 <= SPIXfer_done_int_pulse_d2;
end if;
end if;
end process TRANSFER_DONE_PULSE_DLY_PROCESS;
-------------------------------------------------------------------------------
-- RX_DATA_GEN1: Only for C_SCK_RATIO = 2 mode.
----------------
RX_DATA_SCK_RATIO_2_GEN1 : if C_SCK_RATIO = 2 generate
begin
-----
TRANSFER_DONE_8: if C_NUM_TRANSFER_BITS = 8 generate
TRANSFER_DONE_PROCESS_8: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE or transfer_start_pulse = '1' or SPIXfer_done_int = '1') then -- or (and_reduce(Count(COUNT_WIDTH-1 downto (COUNT_WIDTH-COUNT_WIDTH)))='1')) then
SPIXfer_done_int <= '0';
elsif (Count(COUNT_WIDTH-1) = '1' and
Count(COUNT_WIDTH-2) = '1' and
Count(COUNT_WIDTH-3) = '1' and
Count(COUNT_WIDTH-4) = '0') then
SPIXfer_done_int <= '1';
end if;
end if;
end process TRANSFER_DONE_PROCESS_8;
end generate TRANSFER_DONE_8;
TRANSFER_DONE_16: if C_NUM_TRANSFER_BITS = 16 generate
TRANSFER_DONE_PROCESS_16: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE or transfer_start_pulse = '1' or SPIXfer_done_int = '1') then -- or (and_reduce(Count(COUNT_WIDTH-1 downto (COUNT_WIDTH-COUNT_WIDTH)))='1')) then
SPIXfer_done_int <= '0';
elsif (Count(COUNT_WIDTH-1) = '1' and
Count(COUNT_WIDTH-2) = '1' and
Count(COUNT_WIDTH-3) = '1' and
Count(COUNT_WIDTH-4) = '1' and
Count(COUNT_WIDTH-5) = '0') then
SPIXfer_done_int <= '1';
end if;
end if;
end process TRANSFER_DONE_PROCESS_16;
end generate TRANSFER_DONE_16;
TRANSFER_DONE_32: if C_NUM_TRANSFER_BITS = 32 generate
TRANSFER_DONE_PROCESS_32: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE or transfer_start_pulse = '1' or SPIXfer_done_int = '1') then -- or (and_reduce(Count(COUNT_WIDTH-1 downto (COUNT_WIDTH-COUNT_WIDTH)))='1')) then
SPIXfer_done_int <= '0';
elsif (Count(COUNT_WIDTH-1) = '1' and
Count(COUNT_WIDTH-2) = '1' and
Count(COUNT_WIDTH-3) = '1' and
Count(COUNT_WIDTH-4) = '1' and
Count(COUNT_WIDTH-5) = '1' and
Count(COUNT_WIDTH-6) = '0') then
SPIXfer_done_int <= '1';
end if;
end if;
end process TRANSFER_DONE_PROCESS_32;
end generate TRANSFER_DONE_32;
-- This is mux to choose the data register for SPI mode 00,11 and 01,10.
rx_shft_reg <= rx_shft_reg_mode_0011
when ((CPOL = '0' and CPHA = '0') or (CPOL = '1' and CPHA = '1'))
else rx_shft_reg_mode_0110
when ((CPOL = '0' and CPHA = '1') or (CPOL = '1' and CPHA = '0'))
else
(others=>'0');
-- RECEIVE_DATA_STROBE_PROCESS : Strobe data from shift register to receive
-- data register
--------------------------------
-- For a SCK ratio of 2 the Done needs to be delayed by an extra cycle
-- due to the serial input being captured on the falling edge of the PLB
-- clock. this is purely required for dealing with the real SPI slave memories.
RECEIVE_DATA_STROBE_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Loop_mode = '1') then
if(SPIXfer_done_int_pulse_d1 = '1') then
if (LSB_first = '1') then
for i in 0 to C_NUM_TRANSFER_BITS-1 loop
receive_Data_int(i) <= Shift_Reg(C_NUM_TRANSFER_BITS-1-i);
end loop;
else
receive_Data_int <= Shift_Reg;
end if;
end if;
else
if(SPIXfer_done_int_pulse_d2 = '1') then
if (LSB_first = '1') then
for i in 0 to C_NUM_TRANSFER_BITS-1 loop
receive_Data_int(i) <= rx_shft_reg(C_NUM_TRANSFER_BITS-1-i);
end loop;
else
receive_Data_int <= rx_shft_reg;
end if;
end if;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
-- Done strobe delayed to match receive data
SPIXfer_done_drr <= SPIXfer_done_int_pulse_d3;
SPIXfer_done_rd_tx_en <= transfer_start_pulse or SPIXfer_done_int_pulse_d3; -- SPIXfer_done_int_pulse_d1;
tx_cntr_xfer_done <= transfer_start_pulse or SPIXfer_done_int_pulse_d3;
--RatioSlave_2_GEN : if (Mst_N_Slv = '0') generate
--begin
---ratio count for spi = 2
-------------------------------------------------------------------------------
-- RATIO_COUNT_PROCESS : Counter which counts from (C_SCK_RATIO/2)-1 down to 0
-- Used for counting the time to control SCK_O_reg generation
-- depending on C_SCK_RATIO
------------------------
RATIO_COUNT_PROCESS_SPI2: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (transfer_start = '0')) then
Ratio_Count <= "1";
else if(Ratio_Count = "1" and Mst_N_Slv = '0') then
Ratio_Count <= "0"; --not (Ratio_Count);-- - 1;
else
Ratio_Count <= "1";--not (Ratio_Count);-- - 1;
end if;
end if;
end if;
end process RATIO_COUNT_PROCESS_SPI2;
-------------------------------------------------------------------------------
-- COUNT_TRIGGER_GEN_PROCESS : Generate a trigger whenever Ratio_Count reaches
-- zero
------------------------------
COUNT_TRIGGER_GEN_SCK2_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (transfer_start = '0')) then
Count_trigger <= '0';
elsif(Ratio_Count = 0 and Mst_N_Slv = '0') then
Count_trigger <= not Count_trigger;
end if;
end if;
end process COUNT_TRIGGER_GEN_SCK2_PROCESS;
-------------------------------------------------------------------------------
-- COUNT_TRIGGER_1CLK_PROCESS : Delay cnt_trigger signal by 1 clock cycle
-------------------------------
COUNT_TRIGGER_1CLK_SCK2_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (transfer_start = '0')) then
Count_trigger_d1 <= '0';
else
Count_trigger_d1 <= Count_trigger;
end if;
end if;
end process COUNT_TRIGGER_1CLK_SCK2_PROCESS;
-- generate a trigger pulse for rising edge as well as falling edge
Count_trigger_pulse <= (Count_trigger and (not(Count_trigger_d1))) or
((not(Count_trigger)) and Count_trigger_d1);
--end generate RatioSlave_2_GEN;
-------------------------------------------------
end generate RX_DATA_SCK_RATIO_2_GEN1;
-------------------------------------------------------------------------------
-- RX_DATA_GEN_OTHER_RATIOS: This logic is for other SCK ratios than
---------------------------- C_SCK_RATIO =2
RX_DATA_GEN_OTHER_SCK_RATIOS : if C_SCK_RATIO /= 2 generate
begin
FIFO_PRESENT_GEN: if C_FIFO_EXIST = 1 generate
-----
begin
-----
-------------------------------------------------------------------------------
-- TRANSFER_DONE_PROCESS : Generate SPI transfer done signal
--------------------------
TRANSFER_DONE_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE or
transfer_start_pulse = '1' or
SPIXfer_done_int = '1') then -- or (and_reduce(Count(COUNT_WIDTH-1 downto (COUNT_WIDTH-COUNT_WIDTH)))='1')) then
SPIXfer_done_int <= '0';
elsif(Mst_N_Slv = '1') and ((CPOL xor CPHA) = '1') and
--and_reduce(Count((COUNT_WIDTH-1) downto (COUNT_WIDTH-COUNT_WIDTH))) ='1'
((and_reduce(Count((COUNT_WIDTH-1) downto 0)) = '1') and (or_reduce(ratio_count) = '0'))
then
SPIXfer_done_int <= '1';
elsif(Mst_N_Slv = '1') and ((CPOL xor CPHA) = '0') and
--and_reduce(Count((COUNT_WIDTH-1) downto (COUNT_WIDTH-COUNT_WIDTH))) ='1'
((and_reduce(Count((COUNT_WIDTH-1) downto 0)) = '1') and (or_reduce(ratio_count) = '0'))
-- ((Count(COUNT_WIDTH) ='1') and (or_reduce(Count((COUNT_WIDTH-1) downto 0)) = '0'))
and
Count_trigger = '1'
then
SPIXfer_done_int <= '1';
elsif--(Mst_N_Slv = '0') and
and_reduce(Count((COUNT_WIDTH-1) downto (COUNT_WIDTH-COUNT_WIDTH+1))) ='1' then
if((CPOL xor CPHA) = '0') and rising_edge_sck_i = '1' then
SPIXfer_done_int <= '1';
elsif((CPOL xor CPHA) = '1') and falling_edge_sck_i = '1' then
SPIXfer_done_int <= '1';
end if;
end if;
end if;
end process TRANSFER_DONE_PROCESS;
-- TRANSFER_DONE_PROCESS: process(Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
-- if(Soft_Reset_op = RESET_ACTIVE or
-- transfer_start_pulse = '1' or
-- SPIXfer_done_int = '1') then -- or (and_reduce(Count(COUNT_WIDTH-1 downto (COUNT_WIDTH-COUNT_WIDTH)))='1')) then
-- SPIXfer_done_int <= '0';
-- elsif(Mst_N_Slv = '1') and
-- --and_reduce(Count((COUNT_WIDTH-1) downto (COUNT_WIDTH-COUNT_WIDTH))) ='1'
-- ((Count(COUNT_WIDTH) ='1') and (or_reduce(Count((COUNT_WIDTH-1) downto 0)) = '0'))
-- and
-- Count_trigger = '1'
-- then
-- SPIXfer_done_int <= '1';
-- elsif--(Mst_N_Slv = '0') and
-- and_reduce(Count((COUNT_WIDTH-1) downto (COUNT_WIDTH-COUNT_WIDTH+1))) ='1' then
-- if((CPOL xor CPHA) = '0') and rising_edge_sck_i = '1' then
-- SPIXfer_done_int <= '1';
-- elsif((CPOL xor CPHA) = '1') and falling_edge_sck_i = '1' then
-- SPIXfer_done_int <= '1';
-- end if;
-- end if;
-- end if;
-- end process TRANSFER_DONE_PROCESS;
end generate FIFO_PRESENT_GEN;
--------------------------------------------------------------
FIFO_ABSENT_GEN: if C_FIFO_EXIST = 0 generate
-----
begin
-----
-------------------------------------------------------------------------------
-- TRANSFER_DONE_PROCESS : Generate SPI transfer done signal
--------------------------
TRANSFER_DONE_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE or
transfer_start_pulse = '1' or
SPIXfer_done_int = '1') then
SPIXfer_done_int <= '0';
elsif(Mst_N_Slv = '1') and
((Count(COUNT_WIDTH) ='1') and (or_reduce(Count((COUNT_WIDTH-1) downto 0)) = '0'))
and
Count_trigger = '1'
then
SPIXfer_done_int <= '1';
elsif--(Mst_N_Slv = '0') and
and_reduce(Count((COUNT_WIDTH-1) downto (COUNT_WIDTH-COUNT_WIDTH+1))) ='1' then
if((CPOL xor CPHA) = '0') and rising_edge_sck_i = '1' then
SPIXfer_done_int <= '1';
elsif((CPOL xor CPHA) = '1') and falling_edge_sck_i = '1' then
SPIXfer_done_int <= '1';
end if;
end if;
end if;
end process TRANSFER_DONE_PROCESS;
end generate FIFO_ABSENT_GEN;
-- This is mux to choose the data register for SPI mode 00,11 and 01,10.
-- the below mux is applicable only for Master mode of SPI.
rx_shft_reg <=
rx_shft_reg_mode_0011
when ((CPOL = '0' and CPHA = '0') or (CPOL = '1' and CPHA = '1'))
else
rx_shft_reg_mode_0110
when ((CPOL = '0' and CPHA = '1') or (CPOL = '1' and CPHA = '0'))
else
(others=>'0');
-- RECEIVE_DATA_STROBE_PROCESS_OTHER_RATIO: the below process if for other
-------------------------------------------- SPI ratios of C_SCK_RATIO >2
-- -- It multiplexes the data stored
-- -- in internal registers in LSB and
-- -- non-LSB modes, in master as well as
-- -- in slave mode.
RECEIVE_DATA_STROBE_PROCESS_OTHER_RATIO: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(SPIXfer_done_int_pulse_d1 = '1') then
if (Mst_N_Slv = '1') then -- in master mode
if (LSB_first = '1') then
for i in 0 to (C_NUM_TRANSFER_BITS-1) loop
receive_Data_int(i) <= rx_shft_reg(C_NUM_TRANSFER_BITS-1-i);
end loop;
else
receive_Data_int <= rx_shft_reg;
end if;
elsif(Mst_N_Slv = '0') then -- in slave mode
if (LSB_first = '1') then
for i in 0 to (C_NUM_TRANSFER_BITS-1) loop
receive_Data_int(i) <= rx_shft_reg_s
(C_NUM_TRANSFER_BITS-1-i);
end loop;
else
receive_Data_int <= rx_shft_reg_s;
end if;
end if;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS_OTHER_RATIO;
SPIXfer_done_drr <= SPIXfer_done_int_pulse_d2;
SPIXfer_done_rd_tx_en <= transfer_start_pulse or
SPIXfer_done_int_pulse_d2 or
spisel_pulse;
tx_cntr_xfer_done <= transfer_start_pulse or SPIXfer_done_int_pulse_d2;
--------------------------------------------
end generate RX_DATA_GEN_OTHER_SCK_RATIOS;
-------------------------------------------------------------------------------
-- OTHER_RATIO_GENERATE : Logic to be used when C_SCK_RATIO is not equal to 2
-------------------------
OTHER_RATIO_GENERATE: if(C_SCK_RATIO /= 2) generate
begin
miso_i_sync <= MISO_I;
mosi_i_sync <= MOSI_I;
------------------------------
LOOP_BACK_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Loop_mode = '0' or Soft_Reset_op = RESET_ACTIVE) then
serial_dout_int <= '0';
elsif(Loop_mode = '1') then
serial_dout_int <= Serial_Dout;
end if;
end if;
end process LOOP_BACK_PROCESS;
------------------------------
-- EXTERNAL_INPUT_OR_LOOP_PROCESS: The logic below provides MUXed input to
-- serial_din input.
EXTERNAL_INPUT_OR_LOOP_PROCESS: process(Loop_mode,
Mst_N_Slv,
mosi_i_sync,
miso_i_sync,
serial_dout_int
)is
-----
begin
-----
if(Mst_N_Slv = '1' )then
if(Loop_mode = '1')then
Serial_Din <= serial_dout_int;
else
Serial_Din <= miso_i_sync;
end if;
else
Serial_Din <= mosi_i_sync;
end if;
end process EXTERNAL_INPUT_OR_LOOP_PROCESS;
-------------------------------------------------------------------------------
-- RATIO_COUNT_PROCESS : Counter which counts from (C_SCK_RATIO/2)-1 down to 0
-- Used for counting the time to control SCK_O_reg generation
-- depending on C_SCK_RATIO
------------------------
RATIO_COUNT_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (transfer_start = '0')) then
Ratio_Count <= CONV_STD_LOGIC_VECTOR(
((C_SCK_RATIO/2)-1),(spcl_log2(C_SCK_RATIO)-1));
else
Ratio_Count <= Ratio_Count - 1;
if (Ratio_Count = 0) then
Ratio_Count <= CONV_STD_LOGIC_VECTOR(
((C_SCK_RATIO/2)-1),(spcl_log2(C_SCK_RATIO)-1));
end if;
end if;
end if;
end process RATIO_COUNT_PROCESS;
-------------------------------------------------------------------------------
-- COUNT_TRIGGER_GEN_PROCESS : Generate a trigger whenever Ratio_Count reaches
-- zero
------------------------------
COUNT_TRIGGER_GEN_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (transfer_start = '0')) then
Count_trigger <= '0';
elsif(Ratio_Count = 0) then
Count_trigger <= not Count_trigger;
end if;
end if;
end process COUNT_TRIGGER_GEN_PROCESS;
-------------------------------------------------------------------------------
-- COUNT_TRIGGER_1CLK_PROCESS : Delay cnt_trigger signal by 1 clock cycle
-------------------------------
COUNT_TRIGGER_1CLK_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (transfer_start = '0')) then
Count_trigger_d1 <= '0';
else
Count_trigger_d1 <= Count_trigger;
end if;
end if;
end process COUNT_TRIGGER_1CLK_PROCESS;
-- generate a trigger pulse for rising edge as well as falling edge
Count_trigger_pulse <= (Count_trigger and (not(Count_trigger_d1))) or
((not(Count_trigger)) and Count_trigger_d1);
-------------------------------------------------------------------------------
-- SCK_CYCLE_COUNT_PROCESS : Counts number of trigger pulses provided. Used for
-- controlling the number of bits to be transfered
-- based on generic C_NUM_TRANSFER_BITS
----------------------------
SCK_CYCLE_COUNT_PROCESS: process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
Count <= (others => '0');
elsif (Mst_N_Slv = '1') then
if (SPIXfer_done_int = '1')or
(transfer_start = '0') or
(xfer_done_fifo_0 = '1') then
Count <= (others => '0');
elsif((Count_trigger_pulse = '1') and (Count(COUNT_WIDTH) = '0')) then
Count <= Count + 1;
-- coverage off
if (Count(COUNT_WIDTH) = '1') then
Count <= (others => '0');
end if;
-- coverage on
end if;
elsif (Mst_N_Slv = '0') then
if ((transfer_start = '0') or (SPISEL_sync = '1')or
(spixfer_done_int = '1')) then
Count <= (others => '0');
elsif (edge_sck_i = '1') then
Count <= Count + 1;
-- coverage off
if (Count(COUNT_WIDTH) = '1') then
Count <= (others => '0');
end if;
-- coverage on
end if;
end if;
end if;
end process SCK_CYCLE_COUNT_PROCESS;
-------------------------------------------------------------------------------
-- SCK_SET_RESET_PROCESS : Sync set/reset toggle flip flop controlled by
-- transfer_start signal
--------------------------
SCK_SET_RESET_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or
(Sync_Reset = '1') or
(Mst_N_Slv='0')
)then
sck_o_int <= '0';
elsif(Sync_Set = '1') then
sck_o_int <= '1';
elsif (transfer_start = '1') then
sck_o_int <= sck_o_int xor Count_trigger_pulse;
end if;
end if;
end process SCK_SET_RESET_PROCESS;
------------------------------------
-- DELAY_CLK: Delay the internal clock for a cycle to generate internal enable
-- -- signal for data register.
-------------
DELAY_CLK: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Soft_Reset_op = RESET_ACTIVE)then
sck_d1 <= '0';
sck_d2 <= '0';
else
sck_d1 <= sck_o_int;
sck_d2 <= sck_d1;
end if;
end if;
end process DELAY_CLK;
------------------------------------
-- Rising egde pulse for CPHA-CPOL = 00/11 mode
sck_rising_edge <= not(sck_d2) and sck_d1;
-- CAPT_RX_FE_MODE_00_11: The below logic is the date registery process for
------------------------- SPI CPHA-CPOL modes of 00 and 11.
CAPT_RX_FE_MODE_00_11 : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Soft_Reset_op = RESET_ACTIVE)then
rx_shft_reg_mode_0011 <= (others => '0');
elsif((sck_rising_edge = '1') and (transfer_start='1')) then
rx_shft_reg_mode_0011<= rx_shft_reg_mode_0011
(1 to (C_NUM_TRANSFER_BITS-1)) & Serial_Din;
end if;
end if;
end process CAPT_RX_FE_MODE_00_11;
--
sck_fe1 <= (not sck_d1) and sck_d2;
-- CAPT_RX_FE_MODE_01_10 : The below logic is the date registery process for
------------------------- SPI CPHA-CPOL modes of 01 and 10.
CAPT_RX_FE_MODE_01_10 : process(Bus2IP_Clk)
begin
--if rising_edge(Bus2IP_Clk) then
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Soft_Reset_op = RESET_ACTIVE)then
rx_shft_reg_mode_0110 <= (others => '0');
elsif ((sck_fe1 = '1') and (transfer_start = '1')) then
rx_shft_reg_mode_0110 <= rx_shft_reg_mode_0110
(1 to (C_NUM_TRANSFER_BITS-1)) & Serial_Din;
end if;
end if;
end process CAPT_RX_FE_MODE_01_10;
-------------------------------------------------------------------------------
-- CAPTURE_AND_SHIFT_PROCESS : This logic essentially controls the entire
-- capture and shift operation for serial data
------------------------------
CAPTURE_AND_SHIFT_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
Shift_Reg(0) <= '0';
Shift_Reg(1) <= '1';
Shift_Reg(2 to C_NUM_TRANSFER_BITS -1) <= (others => '0');
Serial_Dout <= '1';
elsif((Mst_N_Slv = '1')) then -- and (not(Count(COUNT_WIDTH) = '1'))) then
--if(Loading_SR_Reg_int = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1')then
if(LSB_first = '1') then
for i in 0 to C_NUM_TRANSFER_BITS-1 loop
Shift_Reg(i) <= Transmit_Data
(C_NUM_TRANSFER_BITS-1-i);
end loop;
Serial_Dout <= Transmit_Data(C_NUM_TRANSFER_BITS-1);
else
Shift_Reg <= Transmit_Data;
Serial_Dout <= Transmit_Data(0);
end if;
-- Capture Data on even Count
elsif(--(transfer_start = '1') and
(Count(0) = '0') ) then
Serial_Dout <= Shift_Reg(0);
-- Shift Data on odd Count
elsif(--(transfer_start = '1') and
(Count(0) = '1') and
(Count_trigger_pulse = '1')) then
Shift_Reg <= Shift_Reg
(1 to C_NUM_TRANSFER_BITS -1) & Serial_Din;
end if;
-- below mode is slave mode logic for SPI
elsif(Mst_N_Slv = '0') then
--if((Loading_SR_Reg_int = '1') or (spisel_pulse = '1')) then
--if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1')then
if(SR_5_Tx_Empty_pulse = '1' or SPIXfer_done_int = '1')then
if(LSB_first = '1') then
for i in 0 to C_NUM_TRANSFER_BITS-1 loop
Shift_Reg(i) <= Transmit_Data
(C_NUM_TRANSFER_BITS-1-i);
end loop;
Serial_Dout <= Transmit_Data(C_NUM_TRANSFER_BITS-1);
else
Shift_Reg <= Transmit_Data;
Serial_Dout <= Transmit_Data(0);
end if;
elsif (transfer_start = '1') then
if((CPOL = '0' and CPHA = '0') or
(CPOL = '1' and CPHA = '1')) then
if(rising_edge_sck_i = '1') then
rx_shft_reg_s <= rx_shft_reg_s(1 to
C_NUM_TRANSFER_BITS -1) & Serial_Din;
Shift_Reg <= Shift_Reg(1 to
C_NUM_TRANSFER_BITS -1) & Serial_Din;
--elsif(falling_edge_sck_i = '1') then
--elsif(rising_edge_sck_i_d1 = '1')then
-- Serial_Dout <= Shift_Reg(0);
end if;
Serial_Dout <= Shift_Reg(0);
elsif((CPOL = '0' and CPHA = '1') or
(CPOL = '1' and CPHA = '0')) then
--Serial_Dout <= Shift_Reg(0);
if(falling_edge_sck_i = '1') then
rx_shft_reg_s <= rx_shft_reg_s(1 to
C_NUM_TRANSFER_BITS -1) & Serial_Din;
Shift_Reg <= Shift_Reg(1 to
C_NUM_TRANSFER_BITS -1) & Serial_Din;
--elsif(rising_edge_sck_i = '1') then
--elsif(falling_edge_sck_i_d1 = '1')then
-- Serial_Dout <= Shift_Reg(0);
end if;
Serial_Dout <= Shift_Reg(0);
end if;
end if;
end if;
end if;
end process CAPTURE_AND_SHIFT_PROCESS;
-----
end generate OTHER_RATIO_GENERATE;
-------------------------------------------------------------------------------
-- RATIO_OF_2_GENERATE : Logic to be used when C_SCK_RATIO is equal to 2
------------------------
RATIO_OF_2_GENERATE: if(C_SCK_RATIO = 2) generate
--------------------
begin
-----
-------------------------------------------------------------------------------
-- SCK_CYCLE_COUNT_PROCESS : Counts number of trigger pulses provided. Used for
-- controlling the number of bits to be transfered
-- based on generic C_NUM_TRANSFER_BITS
----------------------------
SCK_CYCLE_COUNT_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or
(transfer_start = '0') or
(SPIXfer_done_int = '1') or
(Mst_N_Slv = '0')) then
Count <= (others => '0');
--elsif (Count(COUNT_WIDTH) = '0') then
-- Count <= Count + 1;
elsif(Count(COUNT_WIDTH) = '0')then
if(CPHA = '0')then
if(CPOL = '0' and transfer_start_d1 = '1')then -- cpol = cpha = 00
Count <= Count + 1;
elsif(transfer_start_d1 = '1') then -- cpol = cpha = 10
Count <= Count + 1;
end if;
else
if(CPOL = '1' and transfer_start_d1 = '1')then -- cpol = cpha = 11
Count <= Count + 1;
elsif(transfer_start_d1 = '1') then-- cpol = cpha = 10
Count <= Count + 1;
end if;
end if;
end if;
end if;
end process SCK_CYCLE_COUNT_PROCESS;
-------------------------------------------------------------------------------
-- SCK_SET_RESET_PROCESS : Sync set/reset toggle flip flop controlled by
-- transfer_start signal
--------------------------
SCK_SET_RESET_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (Sync_Reset = '1')) then
sck_o_int <= '0';
elsif(Sync_Set = '1') then
sck_o_int <= '1';
elsif (transfer_start = '1') then
sck_o_int <= (not sck_o_int);-- xor Count(COUNT_WIDTH);
end if;
end if;
end process SCK_SET_RESET_PROCESS;
-- CAPT_RX_FE_MODE_00_11: The below logic is to capture data for SPI mode of
--------------------------- 00 and 11.
-- Generate a falling edge pulse from the serial clock. Use this to
-- capture the incoming serial data into a shift register.
-- CAPT_RX_FE_MODE_00_11 : process(Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'event and Bus2IP_Clk = '0') then
-- sck_d1 <= sck_o_int;
-- sck_d2 <= sck_d1;
-- -- if (sck_rising_edge = '1') then
-- if (sck_d1 = '1') then
-- rx_shft_reg_mode_0011 <= rx_shft_reg_mode_0011
-- (1 to (C_NUM_TRANSFER_BITS-1)) & MISO_I;
-- end if;
-- end if;
-- end process CAPT_RX_FE_MODE_00_11;
CAPT_RX_FE_MODE_00_11 : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
sck_d1 <= sck_o_int;
sck_d2 <= sck_d1;
-- sck_d3 <= sck_d2;
-- if (sck_rising_edge = '1') then
if (sck_d2 = '0') then
rx_shft_reg_mode_0011 <= rx_shft_reg_mode_0011
(1 to (C_NUM_TRANSFER_BITS-1)) & MISO_I;
end if;
end if;
end process CAPT_RX_FE_MODE_00_11;
-- Falling egde pulse
sck_rising_edge <= sck_d2 and not sck_d1;
--
-- CAPT_RX_FE_MODE_01_10: the below logic captures data in SPI 01 or 10 mode.
---------------------------
CAPT_RX_FE_MODE_01_10: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
sck_d11 <= sck_o_in;
sck_d21 <= sck_d11;
if(CPOL = '1' and CPHA = '0') then
-------------------if ((sck_d1 = '1') and (transfer_start = '1')) then
if (sck_d2 = '1') then
rx_shft_reg_mode_0110 <= rx_shft_reg_mode_0110
(1 to (C_NUM_TRANSFER_BITS-1)) & MISO_I;
end if;
elsif((CPOL = '0') and (CPHA = '1')) then
-------------------if ((sck_fe1 = '0') and (transfer_start = '1')) then
if (sck_fe1 = '1') then
rx_shft_reg_mode_0110 <= rx_shft_reg_mode_0110
(1 to (C_NUM_TRANSFER_BITS-1)) & MISO_I;
end if;
end if;
end if;
end process CAPT_RX_FE_MODE_01_10;
sck_fe1 <= (not sck_d11) and sck_d21;
-------------------------------------------------------------------------------
-- CAPTURE_AND_SHIFT_PROCESS : This logic essentially controls the entire
-- capture and shift operation for serial data in
------------------------------ master SPI mode only
CAPTURE_AND_SHIFT_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
Shift_Reg(0) <= '0';
Shift_Reg(1) <= '1';
Shift_Reg(2 to C_NUM_TRANSFER_BITS -1) <= (others => '0');
Serial_Dout <= '1';
elsif(Mst_N_Slv = '1') then
--if(Loading_SR_Reg_int = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1') then
if(LSB_first = '1') then
for i in 0 to C_NUM_TRANSFER_BITS-1 loop
Shift_Reg(i) <= Transmit_Data
(C_NUM_TRANSFER_BITS-1-i);
end loop;
Serial_Dout <= Transmit_Data(C_NUM_TRANSFER_BITS-1);
else
Shift_Reg <= Transmit_Data;
Serial_Dout <= Transmit_Data(0);
end if;
elsif(--(transfer_start = '1') and
(Count(0) = '0') -- and
--(Count(COUNT_WIDTH) = '0')
) then -- Shift Data on even
Serial_Dout <= Shift_Reg(0);
elsif(--(transfer_start = '1') and
(Count(0) = '1')-- and
--(Count(COUNT_WIDTH) = '0')
) then -- Capture Data on odd
if(Loop_mode = '1') then -- Loop mode
Shift_Reg <= Shift_Reg(1 to
C_NUM_TRANSFER_BITS -1) & Serial_Dout;
else
Shift_Reg <= Shift_Reg(1 to
C_NUM_TRANSFER_BITS -1) & MISO_I;
end if;
end if;
elsif(Mst_N_Slv = '0') then
-- Added to have consistent default value after reset
--if((Loading_SR_Reg_int = '1') or (spisel_pulse = '1')) then
if(spisel_pulse = '1' or SPIXfer_done_int_d1 = '1') then
Shift_Reg <= (others => '0');
Serial_Dout <= '0';
end if;
end if;
end if;
end process CAPTURE_AND_SHIFT_PROCESS;
-----
end generate RATIO_OF_2_GENERATE;
-------------------------------------------------------------------------------
-- SCK_SET_GEN_PROCESS : Generate SET control for SCK_O_reg
------------------------
SCK_SET_GEN_PROCESS: process(CPOL,CPHA,transfer_start_pulse,
SPIXfer_done_int,
Mst_Trans_inhibit_pulse
)
begin
-- if(transfer_start_pulse = '1') then
--if(Mst_Trans_inhibit_pulse = '1' or SPIXfer_done_int = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int = '1') then
Sync_Set <= (CPOL xor CPHA);
else
Sync_Set <= '0';
end if;
end process SCK_SET_GEN_PROCESS;
-------------------------------------------------------------------------------
-- SCK_RESET_GEN_PROCESS : Generate SET control for SCK_O_reg
--------------------------
SCK_RESET_GEN_PROCESS: process(CPOL,
CPHA,
transfer_start_pulse,
SPIXfer_done_int,
Mst_Trans_inhibit_pulse)
begin
--if(transfer_start_pulse = '1') then
--if(Mst_Trans_inhibit_pulse = '1' or SPIXfer_done_int = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int = '1') then
Sync_Reset <= not(CPOL xor CPHA);
else
Sync_Reset <= '0';
end if;
end process SCK_RESET_GEN_PROCESS;
-------------------------------------------------------------------------------
-- RATIO_NOT_EQUAL_4_GENERATE : Logic to be used when C_SCK_RATIO is not equal
-- to 4
-------------------------------
RATIO_NOT_EQUAL_4_GENERATE: if(C_SCK_RATIO /= 4) generate
begin
-----
-------------------------------------------------------------------------------
-- SCK_O_SELECT_PROCESS : Select the idle state (CPOL bit) when not transfering
-- data else select the clock for slave device
-------------------------
SCK_O_NQ_4_SELECT_PROCESS: process(sck_o_int,
CPOL,
transfer_start,
transfer_start_d1,
Count(COUNT_WIDTH),
xfer_done_fifo_0
)is
begin
if((transfer_start = '1') and
(transfer_start_d1 = '1') and
(Count(COUNT_WIDTH) = '0')and
(xfer_done_fifo_0 = '0')
) then
sck_o_in <= sck_o_int;
else
sck_o_in <= CPOL;
end if;
end process SCK_O_NQ_4_SELECT_PROCESS;
---------------------------------
SCK_O_NQ_4_NO_STARTUP_USED: if (C_USE_STARTUP = 0) generate
----------------
attribute IOB : string;
attribute IOB of SCK_O_NE_4_FDRE_INST : label is "true";
signal slave_mode : std_logic;
----------------
begin
-----
slave_mode <= not (Mst_N_Slv);
-- FDRE: Single Data Rate D Flip-Flop with Synchronous Reset and
-- Clock Enable (posedge clk).
SCK_O_NE_4_FDRE_INST : component FDRE
generic map (
INIT => '0'
) -- Initial value of register (0 or 1)
port map
(
Q => SCK_O_reg, -- Data output
C => Bus2IP_Clk, -- Clock input
CE => '1', -- Clock enable input
R => slave_mode, -- Synchronous reset input
D => sck_o_in -- Data input
);
end generate SCK_O_NQ_4_NO_STARTUP_USED;
-----------------------------
SCK_O_NQ_4_STARTUP_USED: if (C_USE_STARTUP = 1) generate
-------------
begin
-----
---------------------------------------------------------------------------
-- SCK_O_FINAL_PROCESS : Register the final SCK_O_reg
------------------------
SCK_O_NQ_4_FINAL_PROCESS: process(Bus2IP_Clk)
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
--If Soft_Reset_op or slave Mode.Prevents SCK_O_reg to be generated in slave
if((Soft_Reset_op = RESET_ACTIVE) or
(Mst_N_Slv = '0')
) then
SCK_O_reg <= '0';
else
SCK_O_reg <= sck_o_in;
end if;
end if;
end process SCK_O_NQ_4_FINAL_PROCESS;
-------------------------------------
end generate SCK_O_NQ_4_STARTUP_USED;
-------------------------------------
end generate RATIO_NOT_EQUAL_4_GENERATE;
-------------------------------------------------------------------------------
-- RATIO_OF_4_GENERATE : Logic to be used when C_SCK_RATIO is equal to 4
------------------------
RATIO_OF_4_GENERATE: if(C_SCK_RATIO = 4) generate
begin
-----
-------------------------------------------------------------------------------
-- SCK_O_FINAL_PROCESS : Select the idle state (CPOL bit) when not transfering
-- data else select the clock for slave device
------------------------
-- A work around to reduce one clock cycle for sck_o generation. This would
-- allow for proper shifting of data bits into the slave device.
-- Removing the final stage F/F. Disadvantage of not registering final output
-------------------------------------------------------------------------------
SCK_O_EQ_4_FINAL_PROCESS: process(Mst_N_Slv,
sck_o_int,
CPOL,
transfer_start,
transfer_start_d1,
Count(COUNT_WIDTH),
xfer_done_fifo_0
)is
-----
begin
-----
if((Mst_N_Slv = '1') and
(transfer_start = '1') and
(transfer_start_d1 = '1') and
(Count(COUNT_WIDTH) = '0')and
(xfer_done_fifo_0 = '0')
) then
SCK_O_1 <= sck_o_int;
else
SCK_O_1 <= CPOL and Mst_N_Slv;
end if;
end process SCK_O_EQ_4_FINAL_PROCESS;
-------------------------------------
SCK_O_EQ_4_NO_STARTUP_USED: if (C_USE_STARTUP = 0) generate
----------------
attribute IOB : string;
attribute IOB of SCK_O_EQ_4_FDRE_INST : label is "true";
signal slave_mode : std_logic;
----------------
begin
-----
slave_mode <= not (Mst_N_Slv);
-- FDRE: Single Data Rate D Flip-Flop with Synchronous Reset and
-- Clock Enable (posedge clk).
SCK_O_EQ_4_FDRE_INST : component FDRE
generic map (
INIT => '0'
) -- Initial value of register (0 or 1)
port map
(
Q => SCK_O_reg, -- Data output
C => Bus2IP_Clk, -- Clock input
CE => '1', -- Clock enable input
R => slave_mode, -- Synchronous reset input
D => SCK_O_1 -- Data input
);
end generate SCK_O_EQ_4_NO_STARTUP_USED;
-----------------------------
SCK_O_EQ_4_STARTUP_USED: if (C_USE_STARTUP = 1) generate
-------------
begin
-----
----------------------------------------------------------------------------
-- SCK_RATIO_4_REG_PROCESS : The SCK is registered in SCK RATIO = 4 mode
----------------------------------------------------------------------------
SCK_O_EQ_4_REG_PROCESS: process(Bus2IP_Clk)
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
-- If Soft_Reset_op or slave Mode. Prevents SCK_O_reg to be generated in slave
if((Soft_Reset_op = RESET_ACTIVE) or
(Mst_N_Slv = '0')
) then
SCK_O_reg <= '0';
else
SCK_O_reg <= SCK_O_1;
end if;
end if;
end process SCK_O_EQ_4_REG_PROCESS;
-----------------------------------
end generate SCK_O_EQ_4_STARTUP_USED;
-------------------------------------
end generate RATIO_OF_4_GENERATE;
-------------------------------------------------------------------------------
-- LOADING_FIRST_ELEMENT_PROCESS : Combinatorial process to generate flag
-- when loading first data element in shift
-- register from transmit register/fifo
----------------------------------
LOADING_FIRST_ELEMENT_PROCESS: process(Soft_Reset_op,
SPI_En,Mst_N_Slv,
SS_Asserted,
SS_Asserted_1dly,
SR_3_MODF,
transfer_start_pulse)is
begin
if(Soft_Reset_op = RESET_ACTIVE) then
Loading_SR_Reg_int <= '0'; --Clear flag
elsif(SPI_En = '1' and --Enabled
(
((Mst_N_Slv = '1') and --Master configuration
(SS_Asserted = '1') and
(SS_Asserted_1dly = '0') and
(SR_3_MODF = '0')
) or
((Mst_N_Slv = '0') and --Slave configuration
((transfer_start_pulse = '1'))
)
)
)then
Loading_SR_Reg_int <= '1'; --Set flag
else
Loading_SR_Reg_int <= '0'; --Clear flag
end if;
end process LOADING_FIRST_ELEMENT_PROCESS;
-------------------------------------------------------------------------------
-- SELECT_OUT_PROCESS : This process sets SS active-low, one-hot encoded select
-- bit. Changing SS is premitted during a transfer by
-- hardware, but is to be prevented by software. In Auto
-- mode SS_O reflects value of Slave_Select_Reg only
-- when transfer is in progress, otherwise is SS_O is held
-- high
-----------------------
SELECT_OUT_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
SS_O <= (others => '1');
SS_Asserted <= '0';
SS_Asserted_1dly <= '0';
elsif(transfer_start = '0') or (xfer_done_fifo_0 = '1') then -- Tranfer not in progress
if(Manual_SS_mode = '0') then -- Auto SS assert
SS_O <= (others => '1');
else
for i in C_NUM_SS_BITS-1 downto 0 loop
SS_O(i) <= Slave_Select_Reg(C_NUM_SS_BITS-1-i);
end loop;
end if;
SS_Asserted <= '0';
SS_Asserted_1dly <= '0';
else
for i in C_NUM_SS_BITS-1 downto 0 loop
SS_O(i) <= Slave_Select_Reg(C_NUM_SS_BITS-1-i);
end loop;
SS_Asserted <= '1';
SS_Asserted_1dly <= SS_Asserted;
end if;
end if;
end process SELECT_OUT_PROCESS;
-------------------------------------------------------------------------------
-- MODF_STROBE_PROCESS : Strobe MODF signal when master is addressed as slave
------------------------
MODF_STROBE_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (SPISEL_sync = '1')) then
MODF_strobe <= '0';
MODF_strobe_int <= '0';
Allow_MODF_Strobe <= '1';
elsif((Mst_N_Slv = '1') and --In Master mode
(SPISEL_sync = '0') and (Allow_MODF_Strobe = '1')) then
MODF_strobe <= '1';
MODF_strobe_int <= '1';
Allow_MODF_Strobe <= '0';
else
MODF_strobe <= '0';
MODF_strobe_int <= '0';
end if;
end if;
end process MODF_STROBE_PROCESS;
-------------------------------------------------------------------------------
-- SLAVE_MODF_STROBE_PROCESS : Strobe MODF signal when slave is addressed
-- but not enabled.
------------------------------
SLAVE_MODF_STROBE_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (SPISEL_sync = '1')) then
Slave_MODF_strobe <= '0';
Allow_Slave_MODF_Strobe<= '1';
elsif((Mst_N_Slv = '0') and --In Slave mode
(SPI_En = '0') and --but not enabled
(SPISEL_sync = '0') and
(Allow_Slave_MODF_Strobe = '1')
) then
Slave_MODF_strobe <= '1';
Allow_Slave_MODF_Strobe <= '0';
else
Slave_MODF_strobe <= '0';
end if;
end if;
end process SLAVE_MODF_STROBE_PROCESS;
---------------------xxx------------------------------------------------------
end imp;
|
--
---- SPI Module - entity/architecture pair
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
---- Filename: qspi_mode_0_module.vhd
---- Version: v3.0
---- Description: Serial Peripheral Interface (SPI) Module for interfacing
---- with a 32-bit AXI4 Bus.
----
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library lib_pkg_v1_0_2;
use lib_pkg_v1_0_2.lib_pkg;
use lib_pkg_v1_0_2.lib_pkg.log2;
library axi_lite_ipif_v3_0_4;
use axi_lite_ipif_v3_0_4.axi_lite_ipif;
use axi_lite_ipif_v3_0_4.ipif_pkg.all;
library lib_cdc_v1_0_2;
use lib_cdc_v1_0_2.cdc_sync;
library unisim;
use unisim.vcomponents.FD;
use unisim.vcomponents.FDRE;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------:
-- C_SCK_RATIO -- 2, 4, 16, 32, , , , 1024, 2048 SPI
-- clock ratio (16*N), where N=1,2,3...
-- C_SPI_NUM_BITS_REG -- Width of SPI Control register
-- in this module
-- C_NUM_SS_BITS -- Total number of SS-bits
-- C_NUM_TRANSFER_BITS -- SPI Serial transfer width.
-- Can be 8, 16 or 32 bit wide
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- SYSTEM
-- Bus2IP_Clk -- Bus to IP clock
-- Soft_Reset_op -- Soft_Reset_op Signal
-- OTHER INTERFACE
-- Slave_MODF_strobe -- Slave mode fault strobe
-- MODF_strobe -- Mode fault strobe
-- SR_3_MODF -- Mode fault error flag
-- SR_5_Tx_Empty -- Transmit Empty
-- Control_Reg -- Control Register
-- Slave_Select_Reg -- Slave Select Register
-- Transmit_Data -- Data Transmit Register Interface
-- Receive_Data -- Data Receive Register Interface
-- SPIXfer_done -- SPI transfer done flag
-- DTR_underrun -- DTR underrun generation signal
-- SPI INTERFACE
-- SCK_I -- SPI Bus Clock Input
-- SCK_O_reg -- SPI Bus Clock Output
-- SCK_T -- SPI Bus Clock 3-state Enable
-- (3-state when high)
-- MISO_I -- Master out,Slave in Input
-- MISO_O -- Master out,Slave in Output
-- MISO_T -- Master out,Slave in 3-state Enable
-- MOSI_I -- Master in,Slave out Input
-- MOSI_O -- Master in,Slave out Output
-- MOSI_T -- Master in,Slave out 3-state Enable
-- SPISEL -- Local SPI slave select active low input
-- has to be initialzed to VCC
-- SS_I -- Input of slave select vector
-- of length N input where there are
-- N SPI devices,but not connected
-- SS_O -- One-hot encoded,active low slave select
-- vector of length N ouput
-- SS_T -- Single 3-state control signal for
-- slave select vector of length N
-- (3-state when high)
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity qspi_mode_0_module is
generic
(
--C_SPI_MODE : integer;
C_SCK_RATIO : integer;
C_NUM_SS_BITS : integer;
C_NUM_TRANSFER_BITS : integer;
C_USE_STARTUP : integer;
C_SPICR_REG_WIDTH : integer;
C_SUB_FAMILY : string;
C_FIFO_EXIST : integer
);
port
(
Bus2IP_Clk : in std_logic;
Soft_Reset_op : in std_logic;
----------------------
-- Control Reg is 10-bit wide
SPICR_0_LOOP : in std_logic;
SPICR_1_SPE : in std_logic;
SPICR_2_MASTER_N_SLV : in std_logic;
SPICR_3_CPOL : in std_logic;
SPICR_4_CPHA : in std_logic;
SPICR_5_TXFIFO_RST : in std_logic;
SPICR_6_RXFIFO_RST : in std_logic;
SPICR_7_SS : in std_logic;
SPICR_8_TR_INHIBIT : in std_logic;
SPICR_9_LSB : in std_logic;
----------------------
Rx_FIFO_Empty_i_no_fifo : in std_logic;
SR_3_MODF : in std_logic;
SR_5_Tx_Empty : in std_logic;
Slave_MODF_strobe : out std_logic;
MODF_strobe : out std_logic;
SPIXfer_done_rd_tx_en: out std_logic;
Slave_Select_Reg : in std_logic_vector(0 to (C_NUM_SS_BITS-1));
Transmit_Data : in std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
Receive_Data : out std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
SPIXfer_done : out std_logic;
DTR_underrun : out std_logic;
SPISEL_pulse_op : out std_logic;
SPISEL_d1_reg : out std_logic;
--SPI Interface
SCK_I : in std_logic;
SCK_O_reg : out std_logic;
SCK_T : out std_logic;
MISO_I : in std_logic;
MISO_O : out std_logic;
MISO_T : out std_logic;
MOSI_I : in std_logic;
MOSI_O : out std_logic;
MOSI_T : out std_logic;
SPISEL : in std_logic;
SS_I : in std_logic_vector((C_NUM_SS_BITS-1) downto 0);
SS_O : out std_logic_vector((C_NUM_SS_BITS-1) downto 0);
SS_T : out std_logic;
control_bit_7_8 : in std_logic_vector(0 to 1);
Mst_N_Slv_mode : out std_logic;
Rx_FIFO_Full : in std_logic;
reset_RcFIFO_ptr_to_spi : in std_logic;
DRR_Overrun_reg : out std_logic;
tx_cntr_xfer_done : out std_logic
);
end qspi_mode_0_module;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of qspi_mode_0_module is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Function Declarations
---------------------------------------------------------------------
------------------------
-- spcl_log2 : Performs log2(x) function for value of C_SCK_RATIO > 2
------------------------
function spcl_log2(x : natural) return integer is
variable j : integer := 0;
variable k : integer := 0;
begin
if(C_SCK_RATIO /= 2) then
for i in 0 to 11 loop
if(2**i >= x) then
if(k = 0) then
j := i;
end if;
k := 1;
end if;
end loop;
return j;
else
-- coverage off
return 2;
-- coverage on
end if;
end spcl_log2;
function log2(x : natural) return integer is
variable i : integer := 0;
variable val: integer := 1;
begin
if x = 0 then return 0;
else
for j in 0 to 29 loop -- for loop for XST
if val >= x then null;
else
i := i+1;
val := val*2;
end if;
end loop;
assert val >= x
report "Function log2 received argument larger" &
" than its capability of 2^30. "
severity failure;
-- synthesis translate_on
return i;
end if;
end function log2;
-------------------------------------------------------------------------------
-- Constant Declarations
------------------------------------------------------------------
constant RESET_ACTIVE : std_logic := '1';
constant COUNT_WIDTH : INTEGER := log2(C_NUM_TRANSFER_BITS)+1;
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal Ratio_Count : std_logic_vector
(0 to (spcl_log2(C_SCK_RATIO))-2);
signal Count : std_logic_vector
(COUNT_WIDTH downto 0)
:= (others => '0');
signal LSB_first : std_logic;
signal Mst_Trans_inhibit : std_logic;
signal Manual_SS_mode : std_logic;
signal CPHA : std_logic;
signal CPOL : std_logic;
signal Mst_N_Slv : std_logic;
signal SPI_En : std_logic;
signal Loop_mode : std_logic;
signal transfer_start : std_logic;
signal transfer_start_d1 : std_logic;
signal transfer_start_pulse : std_logic;
signal SPIXfer_done_int : std_logic;
signal SPIXfer_done_int_d1 : std_logic;
signal SPIXfer_done_int_pulse : std_logic;
signal SPIXfer_done_int_pulse_d1 : std_logic;
signal sck_o_int : std_logic;
signal sck_o_in : std_logic;
signal Count_trigger : std_logic;
signal Count_trigger_d1 : std_logic;
signal Count_trigger_pulse : std_logic;
signal Sync_Set : std_logic;
signal Sync_Reset : std_logic;
signal Serial_Dout : std_logic;
signal Serial_Din : std_logic;
signal Shift_Reg : std_logic_vector
(0 to C_NUM_TRANSFER_BITS-1);
signal SS_Asserted : std_logic;
signal SS_Asserted_1dly : std_logic;
signal Allow_Slave_MODF_Strobe : std_logic;
signal Allow_MODF_Strobe : std_logic;
signal Loading_SR_Reg_int : std_logic;
signal sck_i_d1 : std_logic;
signal spisel_d1 : std_logic;
signal spisel_pulse : std_logic;
signal rising_edge_sck_i : std_logic;
signal falling_edge_sck_i : std_logic;
signal edge_sck_i : std_logic;
signal MODF_strobe_int : std_logic;
signal master_tri_state_en_control: std_logic;
signal slave_tri_state_en_control: std_logic;
-- following signals are added for use in variouos clock ratio modes.
signal sck_d1 : std_logic;
signal sck_d2 : std_logic;
signal sck_rising_edge : std_logic;
signal rx_shft_reg : std_logic_vector(0 to C_NUM_TRANSFER_BITS-1);
signal SPIXfer_done_int_pulse_d2 : std_logic;
signal SPIXfer_done_int_pulse_d3 : std_logic;
-- added synchronization signals for SPISEL and SCK_I
signal SPISEL_sync : std_logic;
signal SCK_I_sync : std_logic;
-- following register are declared for making data path clear in different modes
signal rx_shft_reg_s : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1))
:=(others => '0');
signal rx_shft_reg_mode_0011 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1))
:=(others => '0');
signal rx_shft_reg_mode_0110 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1))
:=(others => '0');
signal sck_fe1 : std_logic;
signal sck_d21 : std_logic:='0';
signal sck_d11 : std_logic:='0';
signal SCK_O_1 : std_logic:='0';
signal receive_Data_int : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1))
:=(others => '0');
signal mosi_i_sync : std_logic;
signal miso_i_sync : std_logic;
signal serial_dout_int : std_logic;
--
signal Mst_Trans_inhibit_d1, Mst_Trans_inhibit_pulse : std_logic;
signal no_slave_selected : std_logic;
type STATE_TYPE is
(IDLE, -- decode command can be combined here later
TRANSFER_OKAY,
TEMP_TRANSFER_OKAY
);
signal spi_cntrl_ps: STATE_TYPE;
signal spi_cntrl_ns: STATE_TYPE;
signal stop_clock_reg : std_logic;
signal stop_clock : std_logic;
signal Rx_FIFO_Full_reg, DRR_Overrun_reg_int : std_logic;
signal transfer_start_d2 : std_logic;
signal transfer_start_d3 : std_logic;
signal SR_5_Tx_Empty_d1 : std_logic;
signal SR_5_Tx_Empty_pulse: std_logic;
signal SR_5_Tx_comeplete_Empty : std_logic;
signal falling_edge_sck_i_d1, rising_edge_sck_i_d1 : std_logic;
signal spisel_d2 : std_logic;
signal xfer_done_fifo_0 : std_logic;
signal rst_xfer_done_fifo_0 : std_logic;
signal Rx_FIFO_Empty_i_no_fifo_sync : std_logic;
signal SPIXfer_done_drr : std_logic;
-------------------------------------------------------------------------------
-- Architecture Starts
-------------------------------------------------------------------------------
begin
SPIXfer_done <= SPIXfer_done_drr;
--------------------------------------------------
LOCAL_TX_EMPTY_RX_FULL_FIFO_0_GEN: if C_FIFO_EXIST = 0 generate
-----
begin
rx_empty_no_fifo_CDC: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 1 ,
C_MTBF_STAGES => 2
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => Rx_FIFO_Empty_i_no_fifo,
scndry_aclk => Bus2IP_Clk,
prmry_vect_in => (others => '0' ),
scndry_resetn => '0',
scndry_out => Rx_FIFO_Empty_i_no_fifo_sync
);
-----------------------------------------
-----------------------------------------
TX_EMPTY_MODE_0_P: process (Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) or
(transfer_start_pulse = '1') or
(rst_xfer_done_fifo_0 = '1')then
xfer_done_fifo_0 <= '0';
elsif(SPIXfer_done_int_pulse = '1')then
xfer_done_fifo_0 <= '1';
end if;
end if;
end process TX_EMPTY_MODE_0_P;
------------------------------
------------------------------
--RX_FULL_CHECK_PROCESS: process(Bus2IP_Clk) is
--begin
-- if(Bus2IP_Clk'event and Bus2IP_Clk='1') then
-- if (Soft_Reset_op = RESET_ACTIVE)or(reset_RcFIFO_ptr_to_spi = '1') then
-- Rx_FIFO_Full_reg <= '0';
-- elsif(SPIXfer_done_int_pulse = '1')then
-- Rx_FIFO_Full_reg <= '1';
-- end if;
-- end if;
--end process RX_FULL_CHECK_PROCESS;
RX_FULL_CHECK_PROCESS: process(Bus2IP_Clk) is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
Rx_FIFO_Full_reg <= '0';
elsif(DRR_Overrun_reg_int = '1') then
Rx_FIFO_Full_reg <= '0';
elsif((SPIXfer_done_int_pulse = '1') and (Rx_FIFO_Empty_i_no_fifo_sync = '0'))then
Rx_FIFO_Full_reg <= '1';
end if;
end if;
end process RX_FULL_CHECK_PROCESS;
DRR_OVERRUN_REG_PROCESS:process(Bus2IP_Clk) is
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
DRR_Overrun_reg_int <= '0';
else
DRR_Overrun_reg_int <= not(DRR_Overrun_reg_int or Soft_Reset_op) and
Rx_FIFO_Full_reg and
SPIXfer_done_int_pulse_d1; --_d2;
--SPIXfer_done_int_pulse_d1; --_d2;
end if;
end if;
end process DRR_OVERRUN_REG_PROCESS;
--RX_FULL_CHECK_PROCESS: process(Bus2IP_Clk) is
--begin
-- if(Bus2IP_Clk'event and Bus2IP_Clk='1') then
-- if (Soft_Reset_op = RESET_ACTIVE)or(reset_RcFIFO_ptr_to_spi = '1') then
-- --if ((Soft_Reset_op = RESET_ACTIVE)or(reset_RcFIFO_ptr_to_spi = '1') or (Rx_FIFO_Full_reg = '1' and SPIXfer_done_int_pulse = '0')) then
-- --if ((Soft_Reset_op = RESET_ACTIVE)or(reset_RcFIFO_ptr_to_spi = '1') or (Rx_FIFO_Empty_i_no_fifo = '1'))then
-- Rx_FIFO_Full_reg <= '0';
-- elsif(SPIXfer_done_int_pulse = '1')then
-- Rx_FIFO_Full_reg <= '1';
-- elsif(Rx_FIFO_Empty_i_no_fifo = '1')then --Clear only if no simultaneous SPIXfer_done_int_pulse
-- Rx_FIFO_Full_reg <= '0';
-- end if;
-- end if;
--end process RX_FULL_CHECK_PROCESS;
-----------------------------------
PS_TO_NS_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
spi_cntrl_ps <= IDLE;
stop_clock_reg <= '0';
else
spi_cntrl_ps <= spi_cntrl_ns;
stop_clock_reg <= stop_clock;
end if;
end if;
end process PS_TO_NS_PROCESS;
-----------------------------
SPI_STATE_MACHINE_P: process(
Mst_N_Slv,
stop_clock_reg,
spi_cntrl_ps,
no_slave_selected,
SR_5_Tx_Empty,
SPIXfer_done_int_pulse,
transfer_start_pulse,
xfer_done_fifo_0
)
begin
stop_clock <= '0';
rst_xfer_done_fifo_0 <= '0';
--------------------------
case spi_cntrl_ps is
--------------------------
when IDLE => if(SR_5_Tx_Empty = '0' and transfer_start_pulse = '1' and Mst_N_Slv = '1') then
stop_clock <= '0';
spi_cntrl_ns <= TRANSFER_OKAY;
else
stop_clock <= SR_5_Tx_Empty;
spi_cntrl_ns <= IDLE;
end if;
-------------------------------------
when TRANSFER_OKAY => if(SR_5_Tx_Empty = '1') then
if(no_slave_selected = '1')then
stop_clock <= '1';
spi_cntrl_ns <= IDLE;
else
spi_cntrl_ns <= TEMP_TRANSFER_OKAY;
end if;
else
spi_cntrl_ns <= TRANSFER_OKAY;
end if;
-------------------------------------
when TEMP_TRANSFER_OKAY => stop_clock <= stop_clock_reg;
if(SR_5_Tx_Empty='1')then
stop_clock <= xfer_done_fifo_0;
if (no_slave_selected = '1')then
spi_cntrl_ns <= IDLE;
--code coverage -- elsif(SPIXfer_done_int_pulse='1')then
--code coverage -- stop_clock <= SR_5_Tx_Empty;
--code coverage -- spi_cntrl_ns <= TEMP_TRANSFER_OKAY;
else
spi_cntrl_ns <= TEMP_TRANSFER_OKAY;
end if;
else
stop_clock <= '0';
rst_xfer_done_fifo_0 <= '1';
spi_cntrl_ns <= TRANSFER_OKAY;
end if;
-------------------------------------
-- coverage off
when others => spi_cntrl_ns <= IDLE;
-- coverage on
-------------------------------------
end case;
--------------------------
end process SPI_STATE_MACHINE_P;
-----------------------------------------------
end generate LOCAL_TX_EMPTY_RX_FULL_FIFO_0_GEN;
-------------------------------------------------------------------------------
LOCAL_TX_EMPTY_FIFO_12_GEN: if C_FIFO_EXIST /= 0 generate
-----
begin
-----
xfer_done_fifo_0 <= '0';
--RX_FULL_CHECK_PROCESS: process(Bus2IP_Clk) is
------------------------
--begin
-------
-- if(Bus2IP_Clk'event and Bus2IP_Clk='1') then
-- if (Soft_Reset_op = RESET_ACTIVE) then
-- Rx_FIFO_Full_reg <= '0';
-- elsif(reset_RcFIFO_ptr_to_spi = '1') or (DRR_Overrun_reg_int = '1') then
-- Rx_FIFO_Full_reg <= '0';
-- elsif(SPIXfer_done_int_pulse = '1')and (Rx_FIFO_Full = '1') then
-- Rx_FIFO_Full_reg <= '1';
-- end if;
-- end if;
--end process RX_FULL_CHECK_PROCESS;
------------------------------------
--DRR_OVERRUN_REG_PROCESS:process(Bus2IP_Clk) is
-------
--begin
-------
-- if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
-- if (Soft_Reset_op = RESET_ACTIVE) then
-- DRR_Overrun_reg_int <= '0';
-- else
-- DRR_Overrun_reg_int <= not(DRR_Overrun_reg_int or Soft_Reset_op) and
-- Rx_FIFO_Full_reg and
-- SPIXfer_done_int_pulse_d1; --_d2;
-- --SPIXfer_done_int_pulse_d1; --_d2;
-- end if;
-- end if;
--end process DRR_OVERRUN_REG_PROCESS;
DRR_OVERRUN_REG_PROCESS:process(Bus2IP_Clk) is
-----
begin
-----
if (Bus2IP_Clk'event and Bus2IP_Clk='1') then
if (Soft_Reset_op = RESET_ACTIVE) then
DRR_Overrun_reg_int <= '0';
else
DRR_Overrun_reg_int <= not(DRR_Overrun_reg_int or Soft_Reset_op) and
Rx_FIFO_Full and
SPIXfer_done_drr; --_d2;
end if;
end if;
end process DRR_OVERRUN_REG_PROCESS;
PS_TO_NS_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
spi_cntrl_ps <= IDLE;
stop_clock_reg <= '0';
else
spi_cntrl_ps <= spi_cntrl_ns;
stop_clock_reg <= stop_clock;
end if;
end if;
end process PS_TO_NS_PROCESS;
-----------------------------
SPI_STATE_MACHINE_P: process(
Mst_N_Slv ,
stop_clock_reg ,
spi_cntrl_ps ,
no_slave_selected ,
SR_5_Tx_Empty ,
SPIXfer_done_int_pulse ,
transfer_start_pulse ,
SPIXfer_done_int_pulse_d2,
SR_5_Tx_comeplete_Empty,
Loop_mode
)is
-----
begin
-----
stop_clock <= '0';
--rst_xfer_done_fifo_0 <= '0';
--------------------------
case spi_cntrl_ps is
--------------------------
when IDLE => if(SR_5_Tx_Empty = '0' and transfer_start_pulse = '1' and Mst_N_Slv = '1') then
spi_cntrl_ns <= TRANSFER_OKAY;
stop_clock <= '0';
else
stop_clock <= SR_5_Tx_Empty;
spi_cntrl_ns <= IDLE;
end if;
-------------------------------------
when TRANSFER_OKAY => if(SR_5_Tx_Empty = '1') then
--if(no_slave_selected = '1')then
if(SR_5_Tx_comeplete_Empty = '1' and
SPIXfer_done_int_pulse_d2 = '1') then
stop_clock <= '1';
spi_cntrl_ns <= IDLE;
else
spi_cntrl_ns <= TEMP_TRANSFER_OKAY;
end if;
else
spi_cntrl_ns <= TRANSFER_OKAY;
end if;
-------------------------------------
when TEMP_TRANSFER_OKAY => stop_clock <= stop_clock_reg;
--if(SR_5_Tx_Empty='1')then
if(SR_5_Tx_comeplete_Empty='1')then
-- stop_clock <= xfer_done_fifo_0;
if (Loop_mode = '1' and
SPIXfer_done_int_pulse_d2 = '1')then
stop_clock <= '1';
spi_cntrl_ns <= IDLE;
elsif(SPIXfer_done_int_pulse_d2 = '1')then
stop_clock <= SR_5_Tx_Empty;
spi_cntrl_ns <= TEMP_TRANSFER_OKAY;
elsif(no_slave_selected = '1') then
stop_clock <= '1';
spi_cntrl_ns <= IDLE;
else
spi_cntrl_ns <= TEMP_TRANSFER_OKAY;
end if;
else
--stop_clock <= '0';
--rst_xfer_done_fifo_0 <= '1';
spi_cntrl_ns <= TRANSFER_OKAY;
end if;
-------------------------------------
-- coverage off
when others => spi_cntrl_ns <= IDLE;
-- coverage on
-------------------------------------
end case;
--------------------------
end process SPI_STATE_MACHINE_P;
----------------------------------------
----------------------------------------
end generate LOCAL_TX_EMPTY_FIFO_12_GEN;
-----------------------------------------
SR_5_TX_EMPTY_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
SR_5_Tx_Empty_d1 <= '0';
else
SR_5_Tx_Empty_d1 <= SR_5_Tx_Empty;
end if;
end if;
end process SR_5_TX_EMPTY_PROCESS;
----------------------------------
SR_5_Tx_Empty_pulse <= SR_5_Tx_Empty_d1 and not (SR_5_Tx_Empty);
----------------------------------
-------------------------------------------------------------------------------
-- Combinatorial operations
-------------------------------------------------------------------------------
-----------------------------------------------------------
LSB_first <= SPICR_9_LSB; -- Control_Reg(0);
Mst_Trans_inhibit <= SPICR_8_TR_INHIBIT; -- Control_Reg(1);
Manual_SS_mode <= SPICR_7_SS; -- Control_Reg(2);
CPHA <= SPICR_4_CPHA; -- Control_Reg(5);
CPOL <= SPICR_3_CPOL; -- Control_Reg(6);
Mst_N_Slv <= SPICR_2_MASTER_N_SLV; -- Control_Reg(7);
SPI_En <= SPICR_1_SPE; -- Control_Reg(8);
Loop_mode <= SPICR_0_LOOP; -- Control_Reg(9);
Mst_N_Slv_mode <= SPICR_2_MASTER_N_SLV; -- Control_Reg(7);
-----------------------------------------------------------
MOSI_O <= Serial_Dout;
MISO_O <= Serial_Dout;
Receive_Data <= receive_Data_int;
DRR_Overrun_reg <= DRR_Overrun_reg_int;
MST_TRANS_INHIBIT_D1_I: component FD
generic map
(
INIT => '1'
)
port map
(
Q => Mst_Trans_inhibit_d1,
C => Bus2IP_Clk,
D => Mst_Trans_inhibit
);
Mst_Trans_inhibit_pulse <= Mst_Trans_inhibit and (not Mst_Trans_inhibit_d1);
-------------------------------------------------------------------------------
--* -------------------------------------------------------------------------------
--* -- MASTER_TRIST_EN_PROCESS : If not master make tristate enabled
--* ----------------------------
master_tri_state_en_control <=
'0' when
(
(control_bit_7_8(0)='1') and -- decides master/slave mode
(control_bit_7_8(1)='1') and -- decide the spi_en
((MODF_strobe_int or SR_3_MODF)='0') and --no mode fault
(Loop_mode = '0')
) else
'1';
--SPI_TRISTATE_CONTROL_II : Tri-state register for SCK_T, ideal state-deactive
SPI_TRISTATE_CONTROL_II: component FD
generic map
(
INIT => '1'
)
port map
(
Q => SCK_T,
C => Bus2IP_Clk,
D => master_tri_state_en_control
);
--SPI_TRISTATE_CONTROL_III: tri-state register for MOSI, ideal state-deactive
SPI_TRISTATE_CONTROL_III: component FD
generic map
(
INIT => '1'
)
port map
(
Q => MOSI_T,
C => Bus2IP_Clk,
D => master_tri_state_en_control
);
--SPI_TRISTATE_CONTROL_IV: tri-state register for SS,ideal state-deactive
SPI_TRISTATE_CONTROL_IV: component FD
generic map
(
INIT => '1'
)
port map
(
Q => SS_T,
C => Bus2IP_Clk,
D => master_tri_state_en_control
);
--* -------------------------------------------------------------------------------
--* -- SLAVE_TRIST_EN_PROCESS : If slave mode, then make tristate enabled
--* ---------------------------
slave_tri_state_en_control <=
'0' when
(
(control_bit_7_8(0)='0') and -- decides master/slave
(control_bit_7_8(1)='1') and -- decide the spi_en
(SPISEL_sync = '0') and
(Loop_mode = '0')
) else
'1';
--SPI_TRISTATE_CONTROL_V: tri-state register for MISO, ideal state-deactive
SPI_TRISTATE_CONTROL_V: component FD
generic map
(
INIT => '1'
)
port map
(
Q => MISO_T,
C => Bus2IP_Clk,
D => slave_tri_state_en_control
);
-------------------------------------------------------------------------------
DTR_COMPLETE_EMPTY_P:process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1')then
if(SR_5_Tx_Empty = '1' and SPIXfer_done_int_pulse = '1')then
SR_5_Tx_comeplete_Empty <= '1';
elsif(SR_5_Tx_Empty = '0')then
SR_5_Tx_comeplete_Empty <= '0';
end if;
end if;
end process DTR_COMPLETE_EMPTY_P;
---------------------------------
DTR_UNDERRUN_FIFO_0_GEN: if C_FIFO_EXIST = 0 generate
begin
-- DTR_UNDERRUN_PROCESS_P : For Generating DTR underrun error
-------------------------
DTR_UNDERRUN_PROCESS_P: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or
(SPISEL_sync = '1') or
(Mst_N_Slv = '1')--master mode
) then
DTR_underrun <= '0';
elsif((Mst_N_Slv = '0') and (SPI_En = '1')) then-- slave mode
if (SR_5_Tx_comeplete_Empty = '1') then
--if(SPIXfer_done_int_pulse_d2 = '1') then
DTR_underrun <= '1';
--end if;
else
DTR_underrun <= '0';
end if;
end if;
end if;
end process DTR_UNDERRUN_PROCESS_P;
-------------------------------------
end generate DTR_UNDERRUN_FIFO_0_GEN;
DTR_UNDERRUN_FIFO_EXIST_GEN: if C_FIFO_EXIST /= 0 generate
begin
-- DTR_UNDERRUN_PROCESS_P : For Generating DTR underrun error
-------------------------
DTR_UNDERRUN_PROCESS_P: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or
(SPISEL_sync = '1') or
(Mst_N_Slv = '1')--master mode
) then
DTR_underrun <= '0';
elsif((Mst_N_Slv = '0') and (SPI_En = '1')) then-- slave mode
if (SR_5_Tx_comeplete_Empty = '1') then
if(SPIXfer_done_int_pulse = '1') then
DTR_underrun <= '1';
end if;
else
DTR_underrun <= '0';
end if;
end if;
end if;
end process DTR_UNDERRUN_PROCESS_P;
-------------------------------------
end generate DTR_UNDERRUN_FIFO_EXIST_GEN;
-------------------------------------------------------------------------------
-- SPISEL_SYNC: first synchronize the incoming signal, this is required is slave
--------------- mode of the core.
SPISEL_REG: component FD
generic map
(
INIT => '1' -- default '1' to make the device in default master mode
)
port map
(
Q => SPISEL_sync,
C => Bus2IP_Clk,
D => SPISEL
);
---- SPISEL_DELAY_1CLK_PROCESS_P : Detect active SCK edge in slave mode
-------------------------------
SPISEL_DELAY_1CLK_PROCESS_P: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
spisel_d1 <= '1';
spisel_d2 <= '1';
else
spisel_d1 <= SPISEL_sync;
spisel_d2 <= spisel_d1;
end if;
end if;
end process SPISEL_DELAY_1CLK_PROCESS_P;
--SPISEL_DELAY_1CLK: component FD
-- generic map
-- (
-- INIT => '1' -- default '1' to make the device in default master mode
-- )
-- port map
-- (
-- Q => spisel_d1,
-- C => Bus2IP_Clk,
-- D => SPISEL_sync
-- );
--SPISEL_DELAY_2CLK: component FD
-- generic map
-- (
-- INIT => '1' -- default '1' to make the device in default master mode
-- )
-- port map
-- (
-- Q => spisel_d2,
-- C => Bus2IP_Clk,
-- D => spisel_d1
-- );
---- spisel pulse generating logic
---- this one clock cycle pulse will be available for data loading into
---- shift register
--spisel_pulse <= (not SPISEL_sync) and spisel_d1;
------------------------------------------------
-- spisel pulse generating logic
-- this one clock cycle pulse will be available for data loading into
-- shift register
spisel_pulse <= (not spisel_d1) and spisel_d2;
-- --------|__________ -- SPISEL
-- ----------|________ -- SPISEL_sync
-- -------------|_____ -- spisel_d1
-- ----------------|___-- spisel_d2
-- _____________|--|__ -- SPISEL_pulse_op
SPISEL_pulse_op <= spisel_pulse;
SPISEL_d1_reg <= spisel_d2;
-------------------------------------------------------------------------------
--SCK_I_SYNC: first synchronize incomming signal
-------------
SCK_I_REG: component FD
generic map
(
INIT => '0'
)
port map
(
Q => SCK_I_sync,
C => Bus2IP_Clk,
D => SCK_I
);
------------------------------------------------------------------
-- SCK_I_DELAY_1CLK_PROCESS : Detect active SCK edge in slave mode on +ve edge
SCK_I_DELAY_1CLK_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
sck_i_d1 <= '0';
else
sck_i_d1 <= SCK_I_sync;
end if;
end if;
end process SCK_I_DELAY_1CLK_PROCESS;
-------------------------------------------------------------------------------
-- RISING_EDGE_CLK_RATIO_4_GEN: to synchronise the incoming clock signal in
-- slave mode in SCK ratio = 4
RISING_EDGE_CLK_RATIO_4_GEN : if C_SCK_RATIO = 4 generate
begin
-- generate a SCK control pulse for rising edge as well as falling edge
rising_edge_sck_i <= SCK_I and (not(SCK_I_sync)) and (not(SPISEL_sync));
falling_edge_sck_i <= (not(SCK_I) and SCK_I_sync) and (not(SPISEL_sync));
end generate RISING_EDGE_CLK_RATIO_4_GEN;
-------------------------------------------------------------------------------
-- RISING_EDGE_CLK_RATIO_OTHERS_GEN: Due to timing crunch, in SCK> 4 mode,
-- the incoming clock signal cant be synchro
-- -nized with internal AXI clock.
-- slave mode operation on SCK_RATIO=2 isn't
-- supported in the core.
RISING_EDGE_CLK_RATIO_OTHERS_GEN: if ((C_SCK_RATIO /= 2) and (C_SCK_RATIO /= 4))
generate
begin
-- generate a SCK control pulse for rising edge as well as falling edge
rising_edge_sck_i <= SCK_I_sync and (not(sck_i_d1)) and (not(SPISEL_sync));
falling_edge_sck_i <= (not(SCK_I_sync) and sck_i_d1) and (not(SPISEL_sync));
end generate RISING_EDGE_CLK_RATIO_OTHERS_GEN;
-------------------------------------------------------------------------------
-- combine rising edge as well as falling edge as a single signal
edge_sck_i <= rising_edge_sck_i or falling_edge_sck_i;
no_slave_selected <= and_reduce(Slave_Select_Reg(0 to (C_NUM_SS_BITS-1)));
-------------------------------------------------------------------------------
-- TRANSFER_START_PROCESS : Generate transfer start signal. When the transfer
-- gets completed, SPI Transfer done strobe pulls
-- transfer_start back to zero.
---------------------------
TRANSFER_START_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE or
(
Mst_N_Slv = '1' and -- If Master Mode
(
SPI_En = '0' or -- enable not asserted or
(SPIXfer_done_int = '1' and SR_5_Tx_Empty = '1') or -- no data in Tx reg/FIFO or
-------------------- To remove glitch----------------((SPIXfer_done_int = '1' or SPIXfer_done_int_pulse_d1 = '1' ) and SR_5_Tx_Empty = '1') or -- no data in Tx reg/FIFO or
SR_3_MODF = '1' or -- mode fault error
Mst_Trans_inhibit = '1' or -- Do not start if Mst xfer inhibited
stop_clock = '1'
)
) or
(
Mst_N_Slv = '0' and -- If Slave Mode
(
SPI_En = '0' -- enable not asserted or
)
)
)then
transfer_start <= '0';
else
-- Delayed SPIXfer_done_int_pulse to work for synchronous design and to remove
-- asserting of loading_sr_reg in master mode after SR_5_Tx_Empty goes to 1
--if((SPIXfer_done_int_pulse = '1') or
-- (SPIXfer_done_int_pulse_d1 = '1') or
-- (SPIXfer_done_int_pulse_d2='1')) then-- this is added to remove
-- -- glitch at the end of
-- -- transfer in AUTO mode
-- transfer_start <= '0'; -- Set to 0 for at least 1 period
-- else
transfer_start <= '1'; -- Proceed with SPI Transfer
-- end if;
end if;
end if;
end process TRANSFER_START_PROCESS;
-------------------------------------------------------------------------------
-- TRANSFER_START_1CLK_PROCESS : Delay transfer start by 1 clock cycle
--------------------------------
TRANSFER_START_1CLK_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
transfer_start_d1 <= '0';
transfer_start_d2 <= '0';
transfer_start_d3 <= '0';
else
transfer_start_d1 <= transfer_start;
transfer_start_d2 <= transfer_start_d1;
transfer_start_d3 <= transfer_start_d2;
end if;
end if;
end process TRANSFER_START_1CLK_PROCESS;
-- transfer start pulse generating logic
transfer_start_pulse <= transfer_start and (not(transfer_start_d1));
---------------------------------------------------------------------------------
---- TRANSFER_DONE_PROCESS : Generate SPI transfer done signal
----------------------------
--TRANSFER_DONE_PROCESS: process(Bus2IP_Clk)
--begin
-- if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
-- if(Soft_Reset_op = RESET_ACTIVE or transfer_start_pulse = '1' or (and_reduce(Count(COUNT_WIDTH-1 downto (COUNT_WIDTH-COUNT_WIDTH)))='1')) then
-- SPIXfer_done_int <= '0';
-- --elsif (transfer_start_pulse = '1') then
-- -- SPIXfer_done_int <= '0';
-- elsif(and_reduce(Count((COUNT_WIDTH-1) downto (COUNT_WIDTH-COUNT_WIDTH+1))) = '1') then --(Count(COUNT_WIDTH) = '1') then
-- SPIXfer_done_int <= '1';
-- end if;
-- end if;
--end process TRANSFER_DONE_PROCESS;
-------------------------------------------------------------------------------
-- TRANSFER_DONE_1CLK_PROCESS : Delay SPI transfer done signal by 1 clock cycle
-------------------------------
TRANSFER_DONE_1CLK_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
SPIXfer_done_int_d1 <= '0';
else
SPIXfer_done_int_d1 <= SPIXfer_done_int;
end if;
end if;
end process TRANSFER_DONE_1CLK_PROCESS;
--
-- transfer done pulse generating logic
SPIXfer_done_int_pulse <= SPIXfer_done_int and (not(SPIXfer_done_int_d1));
-------------------------------------------------------------------------------
-- TRANSFER_DONE_PULSE_DLY_PROCESS : Delay SPI transfer done pulse by 1 and 2
-- clock cycles
------------------------------------
-- Delay the Done pulse by a further cycle. This is used as the output Rx
-- data strobe when C_SCK_RATIO = 2
TRANSFER_DONE_PULSE_DLY_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
SPIXfer_done_int_pulse_d1 <= '0';
SPIXfer_done_int_pulse_d2 <= '0';
SPIXfer_done_int_pulse_d3 <= '0';
else
SPIXfer_done_int_pulse_d1 <= SPIXfer_done_int_pulse;
SPIXfer_done_int_pulse_d2 <= SPIXfer_done_int_pulse_d1;
SPIXfer_done_int_pulse_d3 <= SPIXfer_done_int_pulse_d2;
end if;
end if;
end process TRANSFER_DONE_PULSE_DLY_PROCESS;
-------------------------------------------------------------------------------
-- RX_DATA_GEN1: Only for C_SCK_RATIO = 2 mode.
----------------
RX_DATA_SCK_RATIO_2_GEN1 : if C_SCK_RATIO = 2 generate
begin
-----
TRANSFER_DONE_8: if C_NUM_TRANSFER_BITS = 8 generate
TRANSFER_DONE_PROCESS_8: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE or transfer_start_pulse = '1' or SPIXfer_done_int = '1') then -- or (and_reduce(Count(COUNT_WIDTH-1 downto (COUNT_WIDTH-COUNT_WIDTH)))='1')) then
SPIXfer_done_int <= '0';
elsif (Count(COUNT_WIDTH-1) = '1' and
Count(COUNT_WIDTH-2) = '1' and
Count(COUNT_WIDTH-3) = '1' and
Count(COUNT_WIDTH-4) = '0') then
SPIXfer_done_int <= '1';
end if;
end if;
end process TRANSFER_DONE_PROCESS_8;
end generate TRANSFER_DONE_8;
TRANSFER_DONE_16: if C_NUM_TRANSFER_BITS = 16 generate
TRANSFER_DONE_PROCESS_16: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE or transfer_start_pulse = '1' or SPIXfer_done_int = '1') then -- or (and_reduce(Count(COUNT_WIDTH-1 downto (COUNT_WIDTH-COUNT_WIDTH)))='1')) then
SPIXfer_done_int <= '0';
elsif (Count(COUNT_WIDTH-1) = '1' and
Count(COUNT_WIDTH-2) = '1' and
Count(COUNT_WIDTH-3) = '1' and
Count(COUNT_WIDTH-4) = '1' and
Count(COUNT_WIDTH-5) = '0') then
SPIXfer_done_int <= '1';
end if;
end if;
end process TRANSFER_DONE_PROCESS_16;
end generate TRANSFER_DONE_16;
TRANSFER_DONE_32: if C_NUM_TRANSFER_BITS = 32 generate
TRANSFER_DONE_PROCESS_32: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE or transfer_start_pulse = '1' or SPIXfer_done_int = '1') then -- or (and_reduce(Count(COUNT_WIDTH-1 downto (COUNT_WIDTH-COUNT_WIDTH)))='1')) then
SPIXfer_done_int <= '0';
elsif (Count(COUNT_WIDTH-1) = '1' and
Count(COUNT_WIDTH-2) = '1' and
Count(COUNT_WIDTH-3) = '1' and
Count(COUNT_WIDTH-4) = '1' and
Count(COUNT_WIDTH-5) = '1' and
Count(COUNT_WIDTH-6) = '0') then
SPIXfer_done_int <= '1';
end if;
end if;
end process TRANSFER_DONE_PROCESS_32;
end generate TRANSFER_DONE_32;
-- This is mux to choose the data register for SPI mode 00,11 and 01,10.
rx_shft_reg <= rx_shft_reg_mode_0011
when ((CPOL = '0' and CPHA = '0') or (CPOL = '1' and CPHA = '1'))
else rx_shft_reg_mode_0110
when ((CPOL = '0' and CPHA = '1') or (CPOL = '1' and CPHA = '0'))
else
(others=>'0');
-- RECEIVE_DATA_STROBE_PROCESS : Strobe data from shift register to receive
-- data register
--------------------------------
-- For a SCK ratio of 2 the Done needs to be delayed by an extra cycle
-- due to the serial input being captured on the falling edge of the PLB
-- clock. this is purely required for dealing with the real SPI slave memories.
RECEIVE_DATA_STROBE_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Loop_mode = '1') then
if(SPIXfer_done_int_pulse_d1 = '1') then
if (LSB_first = '1') then
for i in 0 to C_NUM_TRANSFER_BITS-1 loop
receive_Data_int(i) <= Shift_Reg(C_NUM_TRANSFER_BITS-1-i);
end loop;
else
receive_Data_int <= Shift_Reg;
end if;
end if;
else
if(SPIXfer_done_int_pulse_d2 = '1') then
if (LSB_first = '1') then
for i in 0 to C_NUM_TRANSFER_BITS-1 loop
receive_Data_int(i) <= rx_shft_reg(C_NUM_TRANSFER_BITS-1-i);
end loop;
else
receive_Data_int <= rx_shft_reg;
end if;
end if;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS;
-- Done strobe delayed to match receive data
SPIXfer_done_drr <= SPIXfer_done_int_pulse_d3;
SPIXfer_done_rd_tx_en <= transfer_start_pulse or SPIXfer_done_int_pulse_d3; -- SPIXfer_done_int_pulse_d1;
tx_cntr_xfer_done <= transfer_start_pulse or SPIXfer_done_int_pulse_d3;
--RatioSlave_2_GEN : if (Mst_N_Slv = '0') generate
--begin
---ratio count for spi = 2
-------------------------------------------------------------------------------
-- RATIO_COUNT_PROCESS : Counter which counts from (C_SCK_RATIO/2)-1 down to 0
-- Used for counting the time to control SCK_O_reg generation
-- depending on C_SCK_RATIO
------------------------
RATIO_COUNT_PROCESS_SPI2: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (transfer_start = '0')) then
Ratio_Count <= "1";
else if(Ratio_Count = "1" and Mst_N_Slv = '0') then
Ratio_Count <= "0"; --not (Ratio_Count);-- - 1;
else
Ratio_Count <= "1";--not (Ratio_Count);-- - 1;
end if;
end if;
end if;
end process RATIO_COUNT_PROCESS_SPI2;
-------------------------------------------------------------------------------
-- COUNT_TRIGGER_GEN_PROCESS : Generate a trigger whenever Ratio_Count reaches
-- zero
------------------------------
COUNT_TRIGGER_GEN_SCK2_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (transfer_start = '0')) then
Count_trigger <= '0';
elsif(Ratio_Count = 0 and Mst_N_Slv = '0') then
Count_trigger <= not Count_trigger;
end if;
end if;
end process COUNT_TRIGGER_GEN_SCK2_PROCESS;
-------------------------------------------------------------------------------
-- COUNT_TRIGGER_1CLK_PROCESS : Delay cnt_trigger signal by 1 clock cycle
-------------------------------
COUNT_TRIGGER_1CLK_SCK2_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (transfer_start = '0')) then
Count_trigger_d1 <= '0';
else
Count_trigger_d1 <= Count_trigger;
end if;
end if;
end process COUNT_TRIGGER_1CLK_SCK2_PROCESS;
-- generate a trigger pulse for rising edge as well as falling edge
Count_trigger_pulse <= (Count_trigger and (not(Count_trigger_d1))) or
((not(Count_trigger)) and Count_trigger_d1);
--end generate RatioSlave_2_GEN;
-------------------------------------------------
end generate RX_DATA_SCK_RATIO_2_GEN1;
-------------------------------------------------------------------------------
-- RX_DATA_GEN_OTHER_RATIOS: This logic is for other SCK ratios than
---------------------------- C_SCK_RATIO =2
RX_DATA_GEN_OTHER_SCK_RATIOS : if C_SCK_RATIO /= 2 generate
begin
FIFO_PRESENT_GEN: if C_FIFO_EXIST = 1 generate
-----
begin
-----
-------------------------------------------------------------------------------
-- TRANSFER_DONE_PROCESS : Generate SPI transfer done signal
--------------------------
TRANSFER_DONE_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE or
transfer_start_pulse = '1' or
SPIXfer_done_int = '1') then -- or (and_reduce(Count(COUNT_WIDTH-1 downto (COUNT_WIDTH-COUNT_WIDTH)))='1')) then
SPIXfer_done_int <= '0';
elsif(Mst_N_Slv = '1') and ((CPOL xor CPHA) = '1') and
--and_reduce(Count((COUNT_WIDTH-1) downto (COUNT_WIDTH-COUNT_WIDTH))) ='1'
((and_reduce(Count((COUNT_WIDTH-1) downto 0)) = '1') and (or_reduce(ratio_count) = '0'))
then
SPIXfer_done_int <= '1';
elsif(Mst_N_Slv = '1') and ((CPOL xor CPHA) = '0') and
--and_reduce(Count((COUNT_WIDTH-1) downto (COUNT_WIDTH-COUNT_WIDTH))) ='1'
((and_reduce(Count((COUNT_WIDTH-1) downto 0)) = '1') and (or_reduce(ratio_count) = '0'))
-- ((Count(COUNT_WIDTH) ='1') and (or_reduce(Count((COUNT_WIDTH-1) downto 0)) = '0'))
and
Count_trigger = '1'
then
SPIXfer_done_int <= '1';
elsif--(Mst_N_Slv = '0') and
and_reduce(Count((COUNT_WIDTH-1) downto (COUNT_WIDTH-COUNT_WIDTH+1))) ='1' then
if((CPOL xor CPHA) = '0') and rising_edge_sck_i = '1' then
SPIXfer_done_int <= '1';
elsif((CPOL xor CPHA) = '1') and falling_edge_sck_i = '1' then
SPIXfer_done_int <= '1';
end if;
end if;
end if;
end process TRANSFER_DONE_PROCESS;
-- TRANSFER_DONE_PROCESS: process(Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
-- if(Soft_Reset_op = RESET_ACTIVE or
-- transfer_start_pulse = '1' or
-- SPIXfer_done_int = '1') then -- or (and_reduce(Count(COUNT_WIDTH-1 downto (COUNT_WIDTH-COUNT_WIDTH)))='1')) then
-- SPIXfer_done_int <= '0';
-- elsif(Mst_N_Slv = '1') and
-- --and_reduce(Count((COUNT_WIDTH-1) downto (COUNT_WIDTH-COUNT_WIDTH))) ='1'
-- ((Count(COUNT_WIDTH) ='1') and (or_reduce(Count((COUNT_WIDTH-1) downto 0)) = '0'))
-- and
-- Count_trigger = '1'
-- then
-- SPIXfer_done_int <= '1';
-- elsif--(Mst_N_Slv = '0') and
-- and_reduce(Count((COUNT_WIDTH-1) downto (COUNT_WIDTH-COUNT_WIDTH+1))) ='1' then
-- if((CPOL xor CPHA) = '0') and rising_edge_sck_i = '1' then
-- SPIXfer_done_int <= '1';
-- elsif((CPOL xor CPHA) = '1') and falling_edge_sck_i = '1' then
-- SPIXfer_done_int <= '1';
-- end if;
-- end if;
-- end if;
-- end process TRANSFER_DONE_PROCESS;
end generate FIFO_PRESENT_GEN;
--------------------------------------------------------------
FIFO_ABSENT_GEN: if C_FIFO_EXIST = 0 generate
-----
begin
-----
-------------------------------------------------------------------------------
-- TRANSFER_DONE_PROCESS : Generate SPI transfer done signal
--------------------------
TRANSFER_DONE_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE or
transfer_start_pulse = '1' or
SPIXfer_done_int = '1') then
SPIXfer_done_int <= '0';
elsif(Mst_N_Slv = '1') and
((Count(COUNT_WIDTH) ='1') and (or_reduce(Count((COUNT_WIDTH-1) downto 0)) = '0'))
and
Count_trigger = '1'
then
SPIXfer_done_int <= '1';
elsif--(Mst_N_Slv = '0') and
and_reduce(Count((COUNT_WIDTH-1) downto (COUNT_WIDTH-COUNT_WIDTH+1))) ='1' then
if((CPOL xor CPHA) = '0') and rising_edge_sck_i = '1' then
SPIXfer_done_int <= '1';
elsif((CPOL xor CPHA) = '1') and falling_edge_sck_i = '1' then
SPIXfer_done_int <= '1';
end if;
end if;
end if;
end process TRANSFER_DONE_PROCESS;
end generate FIFO_ABSENT_GEN;
-- This is mux to choose the data register for SPI mode 00,11 and 01,10.
-- the below mux is applicable only for Master mode of SPI.
rx_shft_reg <=
rx_shft_reg_mode_0011
when ((CPOL = '0' and CPHA = '0') or (CPOL = '1' and CPHA = '1'))
else
rx_shft_reg_mode_0110
when ((CPOL = '0' and CPHA = '1') or (CPOL = '1' and CPHA = '0'))
else
(others=>'0');
-- RECEIVE_DATA_STROBE_PROCESS_OTHER_RATIO: the below process if for other
-------------------------------------------- SPI ratios of C_SCK_RATIO >2
-- -- It multiplexes the data stored
-- -- in internal registers in LSB and
-- -- non-LSB modes, in master as well as
-- -- in slave mode.
RECEIVE_DATA_STROBE_PROCESS_OTHER_RATIO: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(SPIXfer_done_int_pulse_d1 = '1') then
if (Mst_N_Slv = '1') then -- in master mode
if (LSB_first = '1') then
for i in 0 to (C_NUM_TRANSFER_BITS-1) loop
receive_Data_int(i) <= rx_shft_reg(C_NUM_TRANSFER_BITS-1-i);
end loop;
else
receive_Data_int <= rx_shft_reg;
end if;
elsif(Mst_N_Slv = '0') then -- in slave mode
if (LSB_first = '1') then
for i in 0 to (C_NUM_TRANSFER_BITS-1) loop
receive_Data_int(i) <= rx_shft_reg_s
(C_NUM_TRANSFER_BITS-1-i);
end loop;
else
receive_Data_int <= rx_shft_reg_s;
end if;
end if;
end if;
end if;
end process RECEIVE_DATA_STROBE_PROCESS_OTHER_RATIO;
SPIXfer_done_drr <= SPIXfer_done_int_pulse_d2;
SPIXfer_done_rd_tx_en <= transfer_start_pulse or
SPIXfer_done_int_pulse_d2 or
spisel_pulse;
tx_cntr_xfer_done <= transfer_start_pulse or SPIXfer_done_int_pulse_d2;
--------------------------------------------
end generate RX_DATA_GEN_OTHER_SCK_RATIOS;
-------------------------------------------------------------------------------
-- OTHER_RATIO_GENERATE : Logic to be used when C_SCK_RATIO is not equal to 2
-------------------------
OTHER_RATIO_GENERATE: if(C_SCK_RATIO /= 2) generate
begin
miso_i_sync <= MISO_I;
mosi_i_sync <= MOSI_I;
------------------------------
LOOP_BACK_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Loop_mode = '0' or Soft_Reset_op = RESET_ACTIVE) then
serial_dout_int <= '0';
elsif(Loop_mode = '1') then
serial_dout_int <= Serial_Dout;
end if;
end if;
end process LOOP_BACK_PROCESS;
------------------------------
-- EXTERNAL_INPUT_OR_LOOP_PROCESS: The logic below provides MUXed input to
-- serial_din input.
EXTERNAL_INPUT_OR_LOOP_PROCESS: process(Loop_mode,
Mst_N_Slv,
mosi_i_sync,
miso_i_sync,
serial_dout_int
)is
-----
begin
-----
if(Mst_N_Slv = '1' )then
if(Loop_mode = '1')then
Serial_Din <= serial_dout_int;
else
Serial_Din <= miso_i_sync;
end if;
else
Serial_Din <= mosi_i_sync;
end if;
end process EXTERNAL_INPUT_OR_LOOP_PROCESS;
-------------------------------------------------------------------------------
-- RATIO_COUNT_PROCESS : Counter which counts from (C_SCK_RATIO/2)-1 down to 0
-- Used for counting the time to control SCK_O_reg generation
-- depending on C_SCK_RATIO
------------------------
RATIO_COUNT_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (transfer_start = '0')) then
Ratio_Count <= CONV_STD_LOGIC_VECTOR(
((C_SCK_RATIO/2)-1),(spcl_log2(C_SCK_RATIO)-1));
else
Ratio_Count <= Ratio_Count - 1;
if (Ratio_Count = 0) then
Ratio_Count <= CONV_STD_LOGIC_VECTOR(
((C_SCK_RATIO/2)-1),(spcl_log2(C_SCK_RATIO)-1));
end if;
end if;
end if;
end process RATIO_COUNT_PROCESS;
-------------------------------------------------------------------------------
-- COUNT_TRIGGER_GEN_PROCESS : Generate a trigger whenever Ratio_Count reaches
-- zero
------------------------------
COUNT_TRIGGER_GEN_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (transfer_start = '0')) then
Count_trigger <= '0';
elsif(Ratio_Count = 0) then
Count_trigger <= not Count_trigger;
end if;
end if;
end process COUNT_TRIGGER_GEN_PROCESS;
-------------------------------------------------------------------------------
-- COUNT_TRIGGER_1CLK_PROCESS : Delay cnt_trigger signal by 1 clock cycle
-------------------------------
COUNT_TRIGGER_1CLK_PROCESS: process(Bus2IP_Clk)is
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (transfer_start = '0')) then
Count_trigger_d1 <= '0';
else
Count_trigger_d1 <= Count_trigger;
end if;
end if;
end process COUNT_TRIGGER_1CLK_PROCESS;
-- generate a trigger pulse for rising edge as well as falling edge
Count_trigger_pulse <= (Count_trigger and (not(Count_trigger_d1))) or
((not(Count_trigger)) and Count_trigger_d1);
-------------------------------------------------------------------------------
-- SCK_CYCLE_COUNT_PROCESS : Counts number of trigger pulses provided. Used for
-- controlling the number of bits to be transfered
-- based on generic C_NUM_TRANSFER_BITS
----------------------------
SCK_CYCLE_COUNT_PROCESS: process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
Count <= (others => '0');
elsif (Mst_N_Slv = '1') then
if (SPIXfer_done_int = '1')or
(transfer_start = '0') or
(xfer_done_fifo_0 = '1') then
Count <= (others => '0');
elsif((Count_trigger_pulse = '1') and (Count(COUNT_WIDTH) = '0')) then
Count <= Count + 1;
-- coverage off
if (Count(COUNT_WIDTH) = '1') then
Count <= (others => '0');
end if;
-- coverage on
end if;
elsif (Mst_N_Slv = '0') then
if ((transfer_start = '0') or (SPISEL_sync = '1')or
(spixfer_done_int = '1')) then
Count <= (others => '0');
elsif (edge_sck_i = '1') then
Count <= Count + 1;
-- coverage off
if (Count(COUNT_WIDTH) = '1') then
Count <= (others => '0');
end if;
-- coverage on
end if;
end if;
end if;
end process SCK_CYCLE_COUNT_PROCESS;
-------------------------------------------------------------------------------
-- SCK_SET_RESET_PROCESS : Sync set/reset toggle flip flop controlled by
-- transfer_start signal
--------------------------
SCK_SET_RESET_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or
(Sync_Reset = '1') or
(Mst_N_Slv='0')
)then
sck_o_int <= '0';
elsif(Sync_Set = '1') then
sck_o_int <= '1';
elsif (transfer_start = '1') then
sck_o_int <= sck_o_int xor Count_trigger_pulse;
end if;
end if;
end process SCK_SET_RESET_PROCESS;
------------------------------------
-- DELAY_CLK: Delay the internal clock for a cycle to generate internal enable
-- -- signal for data register.
-------------
DELAY_CLK: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Soft_Reset_op = RESET_ACTIVE)then
sck_d1 <= '0';
sck_d2 <= '0';
else
sck_d1 <= sck_o_int;
sck_d2 <= sck_d1;
end if;
end if;
end process DELAY_CLK;
------------------------------------
-- Rising egde pulse for CPHA-CPOL = 00/11 mode
sck_rising_edge <= not(sck_d2) and sck_d1;
-- CAPT_RX_FE_MODE_00_11: The below logic is the date registery process for
------------------------- SPI CPHA-CPOL modes of 00 and 11.
CAPT_RX_FE_MODE_00_11 : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Soft_Reset_op = RESET_ACTIVE)then
rx_shft_reg_mode_0011 <= (others => '0');
elsif((sck_rising_edge = '1') and (transfer_start='1')) then
rx_shft_reg_mode_0011<= rx_shft_reg_mode_0011
(1 to (C_NUM_TRANSFER_BITS-1)) & Serial_Din;
end if;
end if;
end process CAPT_RX_FE_MODE_00_11;
--
sck_fe1 <= (not sck_d1) and sck_d2;
-- CAPT_RX_FE_MODE_01_10 : The below logic is the date registery process for
------------------------- SPI CPHA-CPOL modes of 01 and 10.
CAPT_RX_FE_MODE_01_10 : process(Bus2IP_Clk)
begin
--if rising_edge(Bus2IP_Clk) then
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if (Soft_Reset_op = RESET_ACTIVE)then
rx_shft_reg_mode_0110 <= (others => '0');
elsif ((sck_fe1 = '1') and (transfer_start = '1')) then
rx_shft_reg_mode_0110 <= rx_shft_reg_mode_0110
(1 to (C_NUM_TRANSFER_BITS-1)) & Serial_Din;
end if;
end if;
end process CAPT_RX_FE_MODE_01_10;
-------------------------------------------------------------------------------
-- CAPTURE_AND_SHIFT_PROCESS : This logic essentially controls the entire
-- capture and shift operation for serial data
------------------------------
CAPTURE_AND_SHIFT_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
Shift_Reg(0) <= '0';
Shift_Reg(1) <= '1';
Shift_Reg(2 to C_NUM_TRANSFER_BITS -1) <= (others => '0');
Serial_Dout <= '1';
elsif((Mst_N_Slv = '1')) then -- and (not(Count(COUNT_WIDTH) = '1'))) then
--if(Loading_SR_Reg_int = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1')then
if(LSB_first = '1') then
for i in 0 to C_NUM_TRANSFER_BITS-1 loop
Shift_Reg(i) <= Transmit_Data
(C_NUM_TRANSFER_BITS-1-i);
end loop;
Serial_Dout <= Transmit_Data(C_NUM_TRANSFER_BITS-1);
else
Shift_Reg <= Transmit_Data;
Serial_Dout <= Transmit_Data(0);
end if;
-- Capture Data on even Count
elsif(--(transfer_start = '1') and
(Count(0) = '0') ) then
Serial_Dout <= Shift_Reg(0);
-- Shift Data on odd Count
elsif(--(transfer_start = '1') and
(Count(0) = '1') and
(Count_trigger_pulse = '1')) then
Shift_Reg <= Shift_Reg
(1 to C_NUM_TRANSFER_BITS -1) & Serial_Din;
end if;
-- below mode is slave mode logic for SPI
elsif(Mst_N_Slv = '0') then
--if((Loading_SR_Reg_int = '1') or (spisel_pulse = '1')) then
--if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1')then
if(SR_5_Tx_Empty_pulse = '1' or SPIXfer_done_int = '1')then
if(LSB_first = '1') then
for i in 0 to C_NUM_TRANSFER_BITS-1 loop
Shift_Reg(i) <= Transmit_Data
(C_NUM_TRANSFER_BITS-1-i);
end loop;
Serial_Dout <= Transmit_Data(C_NUM_TRANSFER_BITS-1);
else
Shift_Reg <= Transmit_Data;
Serial_Dout <= Transmit_Data(0);
end if;
elsif (transfer_start = '1') then
if((CPOL = '0' and CPHA = '0') or
(CPOL = '1' and CPHA = '1')) then
if(rising_edge_sck_i = '1') then
rx_shft_reg_s <= rx_shft_reg_s(1 to
C_NUM_TRANSFER_BITS -1) & Serial_Din;
Shift_Reg <= Shift_Reg(1 to
C_NUM_TRANSFER_BITS -1) & Serial_Din;
--elsif(falling_edge_sck_i = '1') then
--elsif(rising_edge_sck_i_d1 = '1')then
-- Serial_Dout <= Shift_Reg(0);
end if;
Serial_Dout <= Shift_Reg(0);
elsif((CPOL = '0' and CPHA = '1') or
(CPOL = '1' and CPHA = '0')) then
--Serial_Dout <= Shift_Reg(0);
if(falling_edge_sck_i = '1') then
rx_shft_reg_s <= rx_shft_reg_s(1 to
C_NUM_TRANSFER_BITS -1) & Serial_Din;
Shift_Reg <= Shift_Reg(1 to
C_NUM_TRANSFER_BITS -1) & Serial_Din;
--elsif(rising_edge_sck_i = '1') then
--elsif(falling_edge_sck_i_d1 = '1')then
-- Serial_Dout <= Shift_Reg(0);
end if;
Serial_Dout <= Shift_Reg(0);
end if;
end if;
end if;
end if;
end process CAPTURE_AND_SHIFT_PROCESS;
-----
end generate OTHER_RATIO_GENERATE;
-------------------------------------------------------------------------------
-- RATIO_OF_2_GENERATE : Logic to be used when C_SCK_RATIO is equal to 2
------------------------
RATIO_OF_2_GENERATE: if(C_SCK_RATIO = 2) generate
--------------------
begin
-----
-------------------------------------------------------------------------------
-- SCK_CYCLE_COUNT_PROCESS : Counts number of trigger pulses provided. Used for
-- controlling the number of bits to be transfered
-- based on generic C_NUM_TRANSFER_BITS
----------------------------
SCK_CYCLE_COUNT_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or
(transfer_start = '0') or
(SPIXfer_done_int = '1') or
(Mst_N_Slv = '0')) then
Count <= (others => '0');
--elsif (Count(COUNT_WIDTH) = '0') then
-- Count <= Count + 1;
elsif(Count(COUNT_WIDTH) = '0')then
if(CPHA = '0')then
if(CPOL = '0' and transfer_start_d1 = '1')then -- cpol = cpha = 00
Count <= Count + 1;
elsif(transfer_start_d1 = '1') then -- cpol = cpha = 10
Count <= Count + 1;
end if;
else
if(CPOL = '1' and transfer_start_d1 = '1')then -- cpol = cpha = 11
Count <= Count + 1;
elsif(transfer_start_d1 = '1') then-- cpol = cpha = 10
Count <= Count + 1;
end if;
end if;
end if;
end if;
end process SCK_CYCLE_COUNT_PROCESS;
-------------------------------------------------------------------------------
-- SCK_SET_RESET_PROCESS : Sync set/reset toggle flip flop controlled by
-- transfer_start signal
--------------------------
SCK_SET_RESET_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (Sync_Reset = '1')) then
sck_o_int <= '0';
elsif(Sync_Set = '1') then
sck_o_int <= '1';
elsif (transfer_start = '1') then
sck_o_int <= (not sck_o_int);-- xor Count(COUNT_WIDTH);
end if;
end if;
end process SCK_SET_RESET_PROCESS;
-- CAPT_RX_FE_MODE_00_11: The below logic is to capture data for SPI mode of
--------------------------- 00 and 11.
-- Generate a falling edge pulse from the serial clock. Use this to
-- capture the incoming serial data into a shift register.
-- CAPT_RX_FE_MODE_00_11 : process(Bus2IP_Clk)
-- begin
-- if(Bus2IP_Clk'event and Bus2IP_Clk = '0') then
-- sck_d1 <= sck_o_int;
-- sck_d2 <= sck_d1;
-- -- if (sck_rising_edge = '1') then
-- if (sck_d1 = '1') then
-- rx_shft_reg_mode_0011 <= rx_shft_reg_mode_0011
-- (1 to (C_NUM_TRANSFER_BITS-1)) & MISO_I;
-- end if;
-- end if;
-- end process CAPT_RX_FE_MODE_00_11;
CAPT_RX_FE_MODE_00_11 : process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
sck_d1 <= sck_o_int;
sck_d2 <= sck_d1;
-- sck_d3 <= sck_d2;
-- if (sck_rising_edge = '1') then
if (sck_d2 = '0') then
rx_shft_reg_mode_0011 <= rx_shft_reg_mode_0011
(1 to (C_NUM_TRANSFER_BITS-1)) & MISO_I;
end if;
end if;
end process CAPT_RX_FE_MODE_00_11;
-- Falling egde pulse
sck_rising_edge <= sck_d2 and not sck_d1;
--
-- CAPT_RX_FE_MODE_01_10: the below logic captures data in SPI 01 or 10 mode.
---------------------------
CAPT_RX_FE_MODE_01_10: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
sck_d11 <= sck_o_in;
sck_d21 <= sck_d11;
if(CPOL = '1' and CPHA = '0') then
-------------------if ((sck_d1 = '1') and (transfer_start = '1')) then
if (sck_d2 = '1') then
rx_shft_reg_mode_0110 <= rx_shft_reg_mode_0110
(1 to (C_NUM_TRANSFER_BITS-1)) & MISO_I;
end if;
elsif((CPOL = '0') and (CPHA = '1')) then
-------------------if ((sck_fe1 = '0') and (transfer_start = '1')) then
if (sck_fe1 = '1') then
rx_shft_reg_mode_0110 <= rx_shft_reg_mode_0110
(1 to (C_NUM_TRANSFER_BITS-1)) & MISO_I;
end if;
end if;
end if;
end process CAPT_RX_FE_MODE_01_10;
sck_fe1 <= (not sck_d11) and sck_d21;
-------------------------------------------------------------------------------
-- CAPTURE_AND_SHIFT_PROCESS : This logic essentially controls the entire
-- capture and shift operation for serial data in
------------------------------ master SPI mode only
CAPTURE_AND_SHIFT_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
Shift_Reg(0) <= '0';
Shift_Reg(1) <= '1';
Shift_Reg(2 to C_NUM_TRANSFER_BITS -1) <= (others => '0');
Serial_Dout <= '1';
elsif(Mst_N_Slv = '1') then
--if(Loading_SR_Reg_int = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int_d1 = '1') then
if(LSB_first = '1') then
for i in 0 to C_NUM_TRANSFER_BITS-1 loop
Shift_Reg(i) <= Transmit_Data
(C_NUM_TRANSFER_BITS-1-i);
end loop;
Serial_Dout <= Transmit_Data(C_NUM_TRANSFER_BITS-1);
else
Shift_Reg <= Transmit_Data;
Serial_Dout <= Transmit_Data(0);
end if;
elsif(--(transfer_start = '1') and
(Count(0) = '0') -- and
--(Count(COUNT_WIDTH) = '0')
) then -- Shift Data on even
Serial_Dout <= Shift_Reg(0);
elsif(--(transfer_start = '1') and
(Count(0) = '1')-- and
--(Count(COUNT_WIDTH) = '0')
) then -- Capture Data on odd
if(Loop_mode = '1') then -- Loop mode
Shift_Reg <= Shift_Reg(1 to
C_NUM_TRANSFER_BITS -1) & Serial_Dout;
else
Shift_Reg <= Shift_Reg(1 to
C_NUM_TRANSFER_BITS -1) & MISO_I;
end if;
end if;
elsif(Mst_N_Slv = '0') then
-- Added to have consistent default value after reset
--if((Loading_SR_Reg_int = '1') or (spisel_pulse = '1')) then
if(spisel_pulse = '1' or SPIXfer_done_int_d1 = '1') then
Shift_Reg <= (others => '0');
Serial_Dout <= '0';
end if;
end if;
end if;
end process CAPTURE_AND_SHIFT_PROCESS;
-----
end generate RATIO_OF_2_GENERATE;
-------------------------------------------------------------------------------
-- SCK_SET_GEN_PROCESS : Generate SET control for SCK_O_reg
------------------------
SCK_SET_GEN_PROCESS: process(CPOL,CPHA,transfer_start_pulse,
SPIXfer_done_int,
Mst_Trans_inhibit_pulse
)
begin
-- if(transfer_start_pulse = '1') then
--if(Mst_Trans_inhibit_pulse = '1' or SPIXfer_done_int = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int = '1') then
Sync_Set <= (CPOL xor CPHA);
else
Sync_Set <= '0';
end if;
end process SCK_SET_GEN_PROCESS;
-------------------------------------------------------------------------------
-- SCK_RESET_GEN_PROCESS : Generate SET control for SCK_O_reg
--------------------------
SCK_RESET_GEN_PROCESS: process(CPOL,
CPHA,
transfer_start_pulse,
SPIXfer_done_int,
Mst_Trans_inhibit_pulse)
begin
--if(transfer_start_pulse = '1') then
--if(Mst_Trans_inhibit_pulse = '1' or SPIXfer_done_int = '1') then
if(transfer_start_pulse = '1' or SPIXfer_done_int = '1') then
Sync_Reset <= not(CPOL xor CPHA);
else
Sync_Reset <= '0';
end if;
end process SCK_RESET_GEN_PROCESS;
-------------------------------------------------------------------------------
-- RATIO_NOT_EQUAL_4_GENERATE : Logic to be used when C_SCK_RATIO is not equal
-- to 4
-------------------------------
RATIO_NOT_EQUAL_4_GENERATE: if(C_SCK_RATIO /= 4) generate
begin
-----
-------------------------------------------------------------------------------
-- SCK_O_SELECT_PROCESS : Select the idle state (CPOL bit) when not transfering
-- data else select the clock for slave device
-------------------------
SCK_O_NQ_4_SELECT_PROCESS: process(sck_o_int,
CPOL,
transfer_start,
transfer_start_d1,
Count(COUNT_WIDTH),
xfer_done_fifo_0
)is
begin
if((transfer_start = '1') and
(transfer_start_d1 = '1') and
(Count(COUNT_WIDTH) = '0')and
(xfer_done_fifo_0 = '0')
) then
sck_o_in <= sck_o_int;
else
sck_o_in <= CPOL;
end if;
end process SCK_O_NQ_4_SELECT_PROCESS;
---------------------------------
SCK_O_NQ_4_NO_STARTUP_USED: if (C_USE_STARTUP = 0) generate
----------------
attribute IOB : string;
attribute IOB of SCK_O_NE_4_FDRE_INST : label is "true";
signal slave_mode : std_logic;
----------------
begin
-----
slave_mode <= not (Mst_N_Slv);
-- FDRE: Single Data Rate D Flip-Flop with Synchronous Reset and
-- Clock Enable (posedge clk).
SCK_O_NE_4_FDRE_INST : component FDRE
generic map (
INIT => '0'
) -- Initial value of register (0 or 1)
port map
(
Q => SCK_O_reg, -- Data output
C => Bus2IP_Clk, -- Clock input
CE => '1', -- Clock enable input
R => slave_mode, -- Synchronous reset input
D => sck_o_in -- Data input
);
end generate SCK_O_NQ_4_NO_STARTUP_USED;
-----------------------------
SCK_O_NQ_4_STARTUP_USED: if (C_USE_STARTUP = 1) generate
-------------
begin
-----
---------------------------------------------------------------------------
-- SCK_O_FINAL_PROCESS : Register the final SCK_O_reg
------------------------
SCK_O_NQ_4_FINAL_PROCESS: process(Bus2IP_Clk)
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
--If Soft_Reset_op or slave Mode.Prevents SCK_O_reg to be generated in slave
if((Soft_Reset_op = RESET_ACTIVE) or
(Mst_N_Slv = '0')
) then
SCK_O_reg <= '0';
else
SCK_O_reg <= sck_o_in;
end if;
end if;
end process SCK_O_NQ_4_FINAL_PROCESS;
-------------------------------------
end generate SCK_O_NQ_4_STARTUP_USED;
-------------------------------------
end generate RATIO_NOT_EQUAL_4_GENERATE;
-------------------------------------------------------------------------------
-- RATIO_OF_4_GENERATE : Logic to be used when C_SCK_RATIO is equal to 4
------------------------
RATIO_OF_4_GENERATE: if(C_SCK_RATIO = 4) generate
begin
-----
-------------------------------------------------------------------------------
-- SCK_O_FINAL_PROCESS : Select the idle state (CPOL bit) when not transfering
-- data else select the clock for slave device
------------------------
-- A work around to reduce one clock cycle for sck_o generation. This would
-- allow for proper shifting of data bits into the slave device.
-- Removing the final stage F/F. Disadvantage of not registering final output
-------------------------------------------------------------------------------
SCK_O_EQ_4_FINAL_PROCESS: process(Mst_N_Slv,
sck_o_int,
CPOL,
transfer_start,
transfer_start_d1,
Count(COUNT_WIDTH),
xfer_done_fifo_0
)is
-----
begin
-----
if((Mst_N_Slv = '1') and
(transfer_start = '1') and
(transfer_start_d1 = '1') and
(Count(COUNT_WIDTH) = '0')and
(xfer_done_fifo_0 = '0')
) then
SCK_O_1 <= sck_o_int;
else
SCK_O_1 <= CPOL and Mst_N_Slv;
end if;
end process SCK_O_EQ_4_FINAL_PROCESS;
-------------------------------------
SCK_O_EQ_4_NO_STARTUP_USED: if (C_USE_STARTUP = 0) generate
----------------
attribute IOB : string;
attribute IOB of SCK_O_EQ_4_FDRE_INST : label is "true";
signal slave_mode : std_logic;
----------------
begin
-----
slave_mode <= not (Mst_N_Slv);
-- FDRE: Single Data Rate D Flip-Flop with Synchronous Reset and
-- Clock Enable (posedge clk).
SCK_O_EQ_4_FDRE_INST : component FDRE
generic map (
INIT => '0'
) -- Initial value of register (0 or 1)
port map
(
Q => SCK_O_reg, -- Data output
C => Bus2IP_Clk, -- Clock input
CE => '1', -- Clock enable input
R => slave_mode, -- Synchronous reset input
D => SCK_O_1 -- Data input
);
end generate SCK_O_EQ_4_NO_STARTUP_USED;
-----------------------------
SCK_O_EQ_4_STARTUP_USED: if (C_USE_STARTUP = 1) generate
-------------
begin
-----
----------------------------------------------------------------------------
-- SCK_RATIO_4_REG_PROCESS : The SCK is registered in SCK RATIO = 4 mode
----------------------------------------------------------------------------
SCK_O_EQ_4_REG_PROCESS: process(Bus2IP_Clk)
-----
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
-- If Soft_Reset_op or slave Mode. Prevents SCK_O_reg to be generated in slave
if((Soft_Reset_op = RESET_ACTIVE) or
(Mst_N_Slv = '0')
) then
SCK_O_reg <= '0';
else
SCK_O_reg <= SCK_O_1;
end if;
end if;
end process SCK_O_EQ_4_REG_PROCESS;
-----------------------------------
end generate SCK_O_EQ_4_STARTUP_USED;
-------------------------------------
end generate RATIO_OF_4_GENERATE;
-------------------------------------------------------------------------------
-- LOADING_FIRST_ELEMENT_PROCESS : Combinatorial process to generate flag
-- when loading first data element in shift
-- register from transmit register/fifo
----------------------------------
LOADING_FIRST_ELEMENT_PROCESS: process(Soft_Reset_op,
SPI_En,Mst_N_Slv,
SS_Asserted,
SS_Asserted_1dly,
SR_3_MODF,
transfer_start_pulse)is
begin
if(Soft_Reset_op = RESET_ACTIVE) then
Loading_SR_Reg_int <= '0'; --Clear flag
elsif(SPI_En = '1' and --Enabled
(
((Mst_N_Slv = '1') and --Master configuration
(SS_Asserted = '1') and
(SS_Asserted_1dly = '0') and
(SR_3_MODF = '0')
) or
((Mst_N_Slv = '0') and --Slave configuration
((transfer_start_pulse = '1'))
)
)
)then
Loading_SR_Reg_int <= '1'; --Set flag
else
Loading_SR_Reg_int <= '0'; --Clear flag
end if;
end process LOADING_FIRST_ELEMENT_PROCESS;
-------------------------------------------------------------------------------
-- SELECT_OUT_PROCESS : This process sets SS active-low, one-hot encoded select
-- bit. Changing SS is premitted during a transfer by
-- hardware, but is to be prevented by software. In Auto
-- mode SS_O reflects value of Slave_Select_Reg only
-- when transfer is in progress, otherwise is SS_O is held
-- high
-----------------------
SELECT_OUT_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = RESET_ACTIVE) then
SS_O <= (others => '1');
SS_Asserted <= '0';
SS_Asserted_1dly <= '0';
elsif(transfer_start = '0') or (xfer_done_fifo_0 = '1') then -- Tranfer not in progress
if(Manual_SS_mode = '0') then -- Auto SS assert
SS_O <= (others => '1');
else
for i in C_NUM_SS_BITS-1 downto 0 loop
SS_O(i) <= Slave_Select_Reg(C_NUM_SS_BITS-1-i);
end loop;
end if;
SS_Asserted <= '0';
SS_Asserted_1dly <= '0';
else
for i in C_NUM_SS_BITS-1 downto 0 loop
SS_O(i) <= Slave_Select_Reg(C_NUM_SS_BITS-1-i);
end loop;
SS_Asserted <= '1';
SS_Asserted_1dly <= SS_Asserted;
end if;
end if;
end process SELECT_OUT_PROCESS;
-------------------------------------------------------------------------------
-- MODF_STROBE_PROCESS : Strobe MODF signal when master is addressed as slave
------------------------
MODF_STROBE_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (SPISEL_sync = '1')) then
MODF_strobe <= '0';
MODF_strobe_int <= '0';
Allow_MODF_Strobe <= '1';
elsif((Mst_N_Slv = '1') and --In Master mode
(SPISEL_sync = '0') and (Allow_MODF_Strobe = '1')) then
MODF_strobe <= '1';
MODF_strobe_int <= '1';
Allow_MODF_Strobe <= '0';
else
MODF_strobe <= '0';
MODF_strobe_int <= '0';
end if;
end if;
end process MODF_STROBE_PROCESS;
-------------------------------------------------------------------------------
-- SLAVE_MODF_STROBE_PROCESS : Strobe MODF signal when slave is addressed
-- but not enabled.
------------------------------
SLAVE_MODF_STROBE_PROCESS: process(Bus2IP_Clk)
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if((Soft_Reset_op = RESET_ACTIVE) or (SPISEL_sync = '1')) then
Slave_MODF_strobe <= '0';
Allow_Slave_MODF_Strobe<= '1';
elsif((Mst_N_Slv = '0') and --In Slave mode
(SPI_En = '0') and --but not enabled
(SPISEL_sync = '0') and
(Allow_Slave_MODF_Strobe = '1')
) then
Slave_MODF_strobe <= '1';
Allow_Slave_MODF_Strobe <= '0';
else
Slave_MODF_strobe <= '0';
end if;
end if;
end process SLAVE_MODF_STROBE_PROCESS;
---------------------xxx------------------------------------------------------
end imp;
|
--------------------------------------------------------------------------------
-- Author: Ahmad Anvari
--------------------------------------------------------------------------------
-- Create Date: 06-04-2017
-- Package Name: alu_component
-- Module Name: NOT_COMPONENT
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity NOT_COMPONENT is
port(
INPUT : in std_logic_vector(16 - 1 downto 0);
OUTPUT : out std_logic_vector(16 - 1 downto 0)
);
end entity;
architecture NOT_COMPONENT_ARCH of NOT_COMPONENT is
begin
OUTPUT(0) <= not INPUT(0);
OUTPUT(1) <= not INPUT(1);
OUTPUT(2) <= not INPUT(2);
OUTPUT(3) <= not INPUT(3);
OUTPUT(4) <= not INPUT(4);
OUTPUT(5) <= not INPUT(5);
OUTPUT(6) <= not INPUT(6);
OUTPUT(7) <= not INPUT(7);
OUTPUT(8) <= not INPUT(8);
OUTPUT(9) <= not INPUT(9);
OUTPUT(10) <= not INPUT(10);
OUTPUT(11) <= not INPUT(11);
OUTPUT(12) <= not INPUT(12);
OUTPUT(13) <= not INPUT(13);
OUTPUT(14) <= not INPUT(14);
OUTPUT(15) <= not INPUT(15);
end architecture;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_cmdsts_if.vhd
-- Description: This entity is the descriptor fetch command and status inteface
-- for the Scatter Gather Engine AXI DataMover.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_9;
use axi_dma_v7_1_9.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_cmdsts_if is
generic (
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 64 := 32;
C_ENABLE_QUEUE : integer range 0 to 1 := 1;
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Command write interface from mm2s sm --
mm2s_cmnd_wr : in std_logic ; --
mm2s_cmnd_data : in std_logic_vector --
((C_M_AXI_MM2S_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0); --
mm2s_cmnd_pending : out std_logic ; --
mm2s_sts_received_clr : in std_logic ; --
mm2s_sts_received : out std_logic ; --
mm2s_tailpntr_enble : in std_logic ; --
mm2s_desc_cmplt : in std_logic ; --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_mm2s_cmd_tvalid : out std_logic ; --
s_axis_mm2s_cmd_tready : in std_logic ; --
s_axis_mm2s_cmd_tdata : out std_logic_vector --
((C_M_AXI_MM2S_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0); --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_mm2s_sts_tvalid : in std_logic ; --
m_axis_mm2s_sts_tready : out std_logic ; --
m_axis_mm2s_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_mm2s_sts_tkeep : in std_logic_vector(0 downto 0) ; --
--
-- Scatter Gather Fetch Status --
mm2s_err : in std_logic ; --
mm2s_done : out std_logic ; --
mm2s_error : out std_logic ; --
mm2s_interr : out std_logic ; --
mm2s_slverr : out std_logic ; --
mm2s_decerr : out std_logic ; --
mm2s_tag : out std_logic_vector(3 downto 0) --
);
end axi_dma_mm2s_cmdsts_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_cmdsts_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal sts_tready : std_logic := '0';
signal sts_received_i : std_logic := '0';
signal stale_desc : std_logic := '0';
signal log_status : std_logic := '0';
signal mm2s_slverr_i : std_logic := '0';
signal mm2s_decerr_i : std_logic := '0';
signal mm2s_interr_i : std_logic := '0';
signal mm2s_error_or : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
mm2s_slverr <= mm2s_slverr_i;
mm2s_decerr <= mm2s_decerr_i;
mm2s_interr <= mm2s_interr_i;
-- Stale descriptor if complete bit already set and in tail pointer mode.
stale_desc <= '1' when mm2s_desc_cmplt = '1' and mm2s_tailpntr_enble = '1'
else '0';
-------------------------------------------------------------------------------
-- DataMover Command Interface
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- When command by fetch sm, drive descriptor fetch command to data mover.
-- Hold until data mover indicates ready.
-------------------------------------------------------------------------------
GEN_NO_HOLD_DATA : if C_ENABLE_QUEUE = 1 generate
begin
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_axis_mm2s_cmd_tvalid <= '0';
-- s_axis_mm2s_cmd_tdata <= (others => '0');
mm2s_cmnd_pending <= '0';
-- New command write and not flagged as stale descriptor
elsif(mm2s_cmnd_wr = '1' and stale_desc = '0')then
s_axis_mm2s_cmd_tvalid <= '1';
-- s_axis_mm2s_cmd_tdata <= mm2s_cmnd_data;
mm2s_cmnd_pending <= '1';
-- Clear flags when command excepted by datamover
elsif(s_axis_mm2s_cmd_tready = '1')then
s_axis_mm2s_cmd_tvalid <= '0';
-- s_axis_mm2s_cmd_tdata <= (others => '0');
mm2s_cmnd_pending <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
s_axis_mm2s_cmd_tdata <= mm2s_cmnd_data;
end generate GEN_NO_HOLD_DATA;
GEN_HOLD_DATA : if C_ENABLE_QUEUE = 0 generate
begin
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_axis_mm2s_cmd_tvalid <= '0';
s_axis_mm2s_cmd_tdata <= (others => '0');
mm2s_cmnd_pending <= '0';
-- New command write and not flagged as stale descriptor
elsif(mm2s_cmnd_wr = '1' and stale_desc = '0')then
s_axis_mm2s_cmd_tvalid <= '1';
s_axis_mm2s_cmd_tdata <= mm2s_cmnd_data;
mm2s_cmnd_pending <= '1';
-- Clear flags when command excepted by datamover
elsif(s_axis_mm2s_cmd_tready = '1')then
s_axis_mm2s_cmd_tvalid <= '0';
s_axis_mm2s_cmd_tdata <= (others => '0');
mm2s_cmnd_pending <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
-- s_axis_mm2s_cmd_tdata <= mm2s_cmnd_data;
end generate GEN_HOLD_DATA;
-------------------------------------------------------------------------------
-- DataMover Status Interface
-------------------------------------------------------------------------------
-- Drive ready low during reset to indicate not ready
REG_STS_READY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sts_tready <= '0';
-- De-assert tready on acceptance of status to prevent
-- over writing current status
elsif(sts_tready = '1' and m_axis_mm2s_sts_tvalid = '1')then
sts_tready <= '0';
-- If not status received assert ready to datamover
elsif(sts_received_i = '0') then
sts_tready <= '1';
end if;
end if;
end process REG_STS_READY;
-- Pass to DataMover
m_axis_mm2s_sts_tready <= sts_tready;
-------------------------------------------------------------------------------
-- Log status bits out of data mover.
-------------------------------------------------------------------------------
log_status <= '1' when m_axis_mm2s_sts_tvalid = '1' and sts_received_i = '0'
else '0';
DATAMOVER_STS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_done <= '0';
mm2s_slverr_i <= '0';
mm2s_decerr_i <= '0';
mm2s_interr_i <= '0';
mm2s_tag <= (others => '0');
-- Status valid, therefore capture status
elsif(log_status = '1')then
mm2s_done <= m_axis_mm2s_sts_tdata(DATAMOVER_STS_CMDDONE_BIT);
mm2s_slverr_i <= m_axis_mm2s_sts_tdata(DATAMOVER_STS_SLVERR_BIT);
mm2s_decerr_i <= m_axis_mm2s_sts_tdata(DATAMOVER_STS_DECERR_BIT);
mm2s_interr_i <= m_axis_mm2s_sts_tdata(DATAMOVER_STS_INTERR_BIT);
mm2s_tag <= m_axis_mm2s_sts_tdata(DATAMOVER_STS_TAGMSB_BIT downto DATAMOVER_STS_TAGLSB_BIT);
-- Only assert when valid
else
mm2s_done <= '0';
mm2s_slverr_i <= '0';
mm2s_decerr_i <= '0';
mm2s_interr_i <= '0';
mm2s_tag <= (others => '0');
end if;
end if;
end process DATAMOVER_STS;
-- Flag when status is received. Used to hold status until sg if
-- can use status. This only has meaning when SG Engine Queues are turned
-- on
STS_RCVD_FLAG : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- Clear flag on reset or sg_if status clear
if(m_axi_sg_aresetn = '0' or mm2s_sts_received_clr = '1')then
sts_received_i <= '0';
-- Status valid, therefore capture status
elsif(m_axis_mm2s_sts_tvalid = '1' and sts_received_i = '0')then
sts_received_i <= '1';
end if;
end if;
end process STS_RCVD_FLAG;
mm2s_sts_received <= sts_received_i;
-------------------------------------------------------------------------------
-- Register global error from data mover.
-------------------------------------------------------------------------------
mm2s_error_or <= mm2s_slverr_i or mm2s_decerr_i or mm2s_interr_i;
-- Log errors into a global error output
MM2S_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_error <= '0';
-- If Datamover issues error on the transfer or if a stale descriptor is
-- detected when in tailpointer mode then issue an error
elsif((mm2s_error_or = '1')
or (stale_desc = '1' and mm2s_cmnd_wr='1'))then
mm2s_error <= '1';
end if;
end if;
end process MM2S_ERROR_PROCESS;
end implementation;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_cmdsts_if.vhd
-- Description: This entity is the descriptor fetch command and status inteface
-- for the Scatter Gather Engine AXI DataMover.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_9;
use axi_dma_v7_1_9.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_cmdsts_if is
generic (
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 64 := 32;
C_ENABLE_QUEUE : integer range 0 to 1 := 1;
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Command write interface from mm2s sm --
mm2s_cmnd_wr : in std_logic ; --
mm2s_cmnd_data : in std_logic_vector --
((C_M_AXI_MM2S_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0); --
mm2s_cmnd_pending : out std_logic ; --
mm2s_sts_received_clr : in std_logic ; --
mm2s_sts_received : out std_logic ; --
mm2s_tailpntr_enble : in std_logic ; --
mm2s_desc_cmplt : in std_logic ; --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_mm2s_cmd_tvalid : out std_logic ; --
s_axis_mm2s_cmd_tready : in std_logic ; --
s_axis_mm2s_cmd_tdata : out std_logic_vector --
((C_M_AXI_MM2S_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0); --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_mm2s_sts_tvalid : in std_logic ; --
m_axis_mm2s_sts_tready : out std_logic ; --
m_axis_mm2s_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_mm2s_sts_tkeep : in std_logic_vector(0 downto 0) ; --
--
-- Scatter Gather Fetch Status --
mm2s_err : in std_logic ; --
mm2s_done : out std_logic ; --
mm2s_error : out std_logic ; --
mm2s_interr : out std_logic ; --
mm2s_slverr : out std_logic ; --
mm2s_decerr : out std_logic ; --
mm2s_tag : out std_logic_vector(3 downto 0) --
);
end axi_dma_mm2s_cmdsts_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_cmdsts_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal sts_tready : std_logic := '0';
signal sts_received_i : std_logic := '0';
signal stale_desc : std_logic := '0';
signal log_status : std_logic := '0';
signal mm2s_slverr_i : std_logic := '0';
signal mm2s_decerr_i : std_logic := '0';
signal mm2s_interr_i : std_logic := '0';
signal mm2s_error_or : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
mm2s_slverr <= mm2s_slverr_i;
mm2s_decerr <= mm2s_decerr_i;
mm2s_interr <= mm2s_interr_i;
-- Stale descriptor if complete bit already set and in tail pointer mode.
stale_desc <= '1' when mm2s_desc_cmplt = '1' and mm2s_tailpntr_enble = '1'
else '0';
-------------------------------------------------------------------------------
-- DataMover Command Interface
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- When command by fetch sm, drive descriptor fetch command to data mover.
-- Hold until data mover indicates ready.
-------------------------------------------------------------------------------
GEN_NO_HOLD_DATA : if C_ENABLE_QUEUE = 1 generate
begin
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_axis_mm2s_cmd_tvalid <= '0';
-- s_axis_mm2s_cmd_tdata <= (others => '0');
mm2s_cmnd_pending <= '0';
-- New command write and not flagged as stale descriptor
elsif(mm2s_cmnd_wr = '1' and stale_desc = '0')then
s_axis_mm2s_cmd_tvalid <= '1';
-- s_axis_mm2s_cmd_tdata <= mm2s_cmnd_data;
mm2s_cmnd_pending <= '1';
-- Clear flags when command excepted by datamover
elsif(s_axis_mm2s_cmd_tready = '1')then
s_axis_mm2s_cmd_tvalid <= '0';
-- s_axis_mm2s_cmd_tdata <= (others => '0');
mm2s_cmnd_pending <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
s_axis_mm2s_cmd_tdata <= mm2s_cmnd_data;
end generate GEN_NO_HOLD_DATA;
GEN_HOLD_DATA : if C_ENABLE_QUEUE = 0 generate
begin
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_axis_mm2s_cmd_tvalid <= '0';
s_axis_mm2s_cmd_tdata <= (others => '0');
mm2s_cmnd_pending <= '0';
-- New command write and not flagged as stale descriptor
elsif(mm2s_cmnd_wr = '1' and stale_desc = '0')then
s_axis_mm2s_cmd_tvalid <= '1';
s_axis_mm2s_cmd_tdata <= mm2s_cmnd_data;
mm2s_cmnd_pending <= '1';
-- Clear flags when command excepted by datamover
elsif(s_axis_mm2s_cmd_tready = '1')then
s_axis_mm2s_cmd_tvalid <= '0';
s_axis_mm2s_cmd_tdata <= (others => '0');
mm2s_cmnd_pending <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
-- s_axis_mm2s_cmd_tdata <= mm2s_cmnd_data;
end generate GEN_HOLD_DATA;
-------------------------------------------------------------------------------
-- DataMover Status Interface
-------------------------------------------------------------------------------
-- Drive ready low during reset to indicate not ready
REG_STS_READY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sts_tready <= '0';
-- De-assert tready on acceptance of status to prevent
-- over writing current status
elsif(sts_tready = '1' and m_axis_mm2s_sts_tvalid = '1')then
sts_tready <= '0';
-- If not status received assert ready to datamover
elsif(sts_received_i = '0') then
sts_tready <= '1';
end if;
end if;
end process REG_STS_READY;
-- Pass to DataMover
m_axis_mm2s_sts_tready <= sts_tready;
-------------------------------------------------------------------------------
-- Log status bits out of data mover.
-------------------------------------------------------------------------------
log_status <= '1' when m_axis_mm2s_sts_tvalid = '1' and sts_received_i = '0'
else '0';
DATAMOVER_STS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_done <= '0';
mm2s_slverr_i <= '0';
mm2s_decerr_i <= '0';
mm2s_interr_i <= '0';
mm2s_tag <= (others => '0');
-- Status valid, therefore capture status
elsif(log_status = '1')then
mm2s_done <= m_axis_mm2s_sts_tdata(DATAMOVER_STS_CMDDONE_BIT);
mm2s_slverr_i <= m_axis_mm2s_sts_tdata(DATAMOVER_STS_SLVERR_BIT);
mm2s_decerr_i <= m_axis_mm2s_sts_tdata(DATAMOVER_STS_DECERR_BIT);
mm2s_interr_i <= m_axis_mm2s_sts_tdata(DATAMOVER_STS_INTERR_BIT);
mm2s_tag <= m_axis_mm2s_sts_tdata(DATAMOVER_STS_TAGMSB_BIT downto DATAMOVER_STS_TAGLSB_BIT);
-- Only assert when valid
else
mm2s_done <= '0';
mm2s_slverr_i <= '0';
mm2s_decerr_i <= '0';
mm2s_interr_i <= '0';
mm2s_tag <= (others => '0');
end if;
end if;
end process DATAMOVER_STS;
-- Flag when status is received. Used to hold status until sg if
-- can use status. This only has meaning when SG Engine Queues are turned
-- on
STS_RCVD_FLAG : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- Clear flag on reset or sg_if status clear
if(m_axi_sg_aresetn = '0' or mm2s_sts_received_clr = '1')then
sts_received_i <= '0';
-- Status valid, therefore capture status
elsif(m_axis_mm2s_sts_tvalid = '1' and sts_received_i = '0')then
sts_received_i <= '1';
end if;
end if;
end process STS_RCVD_FLAG;
mm2s_sts_received <= sts_received_i;
-------------------------------------------------------------------------------
-- Register global error from data mover.
-------------------------------------------------------------------------------
mm2s_error_or <= mm2s_slverr_i or mm2s_decerr_i or mm2s_interr_i;
-- Log errors into a global error output
MM2S_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_error <= '0';
-- If Datamover issues error on the transfer or if a stale descriptor is
-- detected when in tailpointer mode then issue an error
elsif((mm2s_error_or = '1')
or (stale_desc = '1' and mm2s_cmnd_wr='1'))then
mm2s_error <= '1';
end if;
end if;
end process MM2S_ERROR_PROCESS;
end implementation;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_cmdsts_if.vhd
-- Description: This entity is the descriptor fetch command and status inteface
-- for the Scatter Gather Engine AXI DataMover.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1_9;
use axi_dma_v7_1_9.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_cmdsts_if is
generic (
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 64 := 32;
C_ENABLE_QUEUE : integer range 0 to 1 := 1;
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Command write interface from mm2s sm --
mm2s_cmnd_wr : in std_logic ; --
mm2s_cmnd_data : in std_logic_vector --
((C_M_AXI_MM2S_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0); --
mm2s_cmnd_pending : out std_logic ; --
mm2s_sts_received_clr : in std_logic ; --
mm2s_sts_received : out std_logic ; --
mm2s_tailpntr_enble : in std_logic ; --
mm2s_desc_cmplt : in std_logic ; --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_mm2s_cmd_tvalid : out std_logic ; --
s_axis_mm2s_cmd_tready : in std_logic ; --
s_axis_mm2s_cmd_tdata : out std_logic_vector --
((C_M_AXI_MM2S_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0); --
--
-- User Status Interface Ports (AXI Stream) --
m_axis_mm2s_sts_tvalid : in std_logic ; --
m_axis_mm2s_sts_tready : out std_logic ; --
m_axis_mm2s_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_mm2s_sts_tkeep : in std_logic_vector(0 downto 0) ; --
--
-- Scatter Gather Fetch Status --
mm2s_err : in std_logic ; --
mm2s_done : out std_logic ; --
mm2s_error : out std_logic ; --
mm2s_interr : out std_logic ; --
mm2s_slverr : out std_logic ; --
mm2s_decerr : out std_logic ; --
mm2s_tag : out std_logic_vector(3 downto 0) --
);
end axi_dma_mm2s_cmdsts_if;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_cmdsts_if is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal sts_tready : std_logic := '0';
signal sts_received_i : std_logic := '0';
signal stale_desc : std_logic := '0';
signal log_status : std_logic := '0';
signal mm2s_slverr_i : std_logic := '0';
signal mm2s_decerr_i : std_logic := '0';
signal mm2s_interr_i : std_logic := '0';
signal mm2s_error_or : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
mm2s_slverr <= mm2s_slverr_i;
mm2s_decerr <= mm2s_decerr_i;
mm2s_interr <= mm2s_interr_i;
-- Stale descriptor if complete bit already set and in tail pointer mode.
stale_desc <= '1' when mm2s_desc_cmplt = '1' and mm2s_tailpntr_enble = '1'
else '0';
-------------------------------------------------------------------------------
-- DataMover Command Interface
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- When command by fetch sm, drive descriptor fetch command to data mover.
-- Hold until data mover indicates ready.
-------------------------------------------------------------------------------
GEN_NO_HOLD_DATA : if C_ENABLE_QUEUE = 1 generate
begin
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_axis_mm2s_cmd_tvalid <= '0';
-- s_axis_mm2s_cmd_tdata <= (others => '0');
mm2s_cmnd_pending <= '0';
-- New command write and not flagged as stale descriptor
elsif(mm2s_cmnd_wr = '1' and stale_desc = '0')then
s_axis_mm2s_cmd_tvalid <= '1';
-- s_axis_mm2s_cmd_tdata <= mm2s_cmnd_data;
mm2s_cmnd_pending <= '1';
-- Clear flags when command excepted by datamover
elsif(s_axis_mm2s_cmd_tready = '1')then
s_axis_mm2s_cmd_tvalid <= '0';
-- s_axis_mm2s_cmd_tdata <= (others => '0');
mm2s_cmnd_pending <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
s_axis_mm2s_cmd_tdata <= mm2s_cmnd_data;
end generate GEN_NO_HOLD_DATA;
GEN_HOLD_DATA : if C_ENABLE_QUEUE = 0 generate
begin
GEN_DATAMOVER_CMND : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
s_axis_mm2s_cmd_tvalid <= '0';
s_axis_mm2s_cmd_tdata <= (others => '0');
mm2s_cmnd_pending <= '0';
-- New command write and not flagged as stale descriptor
elsif(mm2s_cmnd_wr = '1' and stale_desc = '0')then
s_axis_mm2s_cmd_tvalid <= '1';
s_axis_mm2s_cmd_tdata <= mm2s_cmnd_data;
mm2s_cmnd_pending <= '1';
-- Clear flags when command excepted by datamover
elsif(s_axis_mm2s_cmd_tready = '1')then
s_axis_mm2s_cmd_tvalid <= '0';
s_axis_mm2s_cmd_tdata <= (others => '0');
mm2s_cmnd_pending <= '0';
end if;
end if;
end process GEN_DATAMOVER_CMND;
-- s_axis_mm2s_cmd_tdata <= mm2s_cmnd_data;
end generate GEN_HOLD_DATA;
-------------------------------------------------------------------------------
-- DataMover Status Interface
-------------------------------------------------------------------------------
-- Drive ready low during reset to indicate not ready
REG_STS_READY : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
sts_tready <= '0';
-- De-assert tready on acceptance of status to prevent
-- over writing current status
elsif(sts_tready = '1' and m_axis_mm2s_sts_tvalid = '1')then
sts_tready <= '0';
-- If not status received assert ready to datamover
elsif(sts_received_i = '0') then
sts_tready <= '1';
end if;
end if;
end process REG_STS_READY;
-- Pass to DataMover
m_axis_mm2s_sts_tready <= sts_tready;
-------------------------------------------------------------------------------
-- Log status bits out of data mover.
-------------------------------------------------------------------------------
log_status <= '1' when m_axis_mm2s_sts_tvalid = '1' and sts_received_i = '0'
else '0';
DATAMOVER_STS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_done <= '0';
mm2s_slverr_i <= '0';
mm2s_decerr_i <= '0';
mm2s_interr_i <= '0';
mm2s_tag <= (others => '0');
-- Status valid, therefore capture status
elsif(log_status = '1')then
mm2s_done <= m_axis_mm2s_sts_tdata(DATAMOVER_STS_CMDDONE_BIT);
mm2s_slverr_i <= m_axis_mm2s_sts_tdata(DATAMOVER_STS_SLVERR_BIT);
mm2s_decerr_i <= m_axis_mm2s_sts_tdata(DATAMOVER_STS_DECERR_BIT);
mm2s_interr_i <= m_axis_mm2s_sts_tdata(DATAMOVER_STS_INTERR_BIT);
mm2s_tag <= m_axis_mm2s_sts_tdata(DATAMOVER_STS_TAGMSB_BIT downto DATAMOVER_STS_TAGLSB_BIT);
-- Only assert when valid
else
mm2s_done <= '0';
mm2s_slverr_i <= '0';
mm2s_decerr_i <= '0';
mm2s_interr_i <= '0';
mm2s_tag <= (others => '0');
end if;
end if;
end process DATAMOVER_STS;
-- Flag when status is received. Used to hold status until sg if
-- can use status. This only has meaning when SG Engine Queues are turned
-- on
STS_RCVD_FLAG : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- Clear flag on reset or sg_if status clear
if(m_axi_sg_aresetn = '0' or mm2s_sts_received_clr = '1')then
sts_received_i <= '0';
-- Status valid, therefore capture status
elsif(m_axis_mm2s_sts_tvalid = '1' and sts_received_i = '0')then
sts_received_i <= '1';
end if;
end if;
end process STS_RCVD_FLAG;
mm2s_sts_received <= sts_received_i;
-------------------------------------------------------------------------------
-- Register global error from data mover.
-------------------------------------------------------------------------------
mm2s_error_or <= mm2s_slverr_i or mm2s_decerr_i or mm2s_interr_i;
-- Log errors into a global error output
MM2S_ERROR_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_error <= '0';
-- If Datamover issues error on the transfer or if a stale descriptor is
-- detected when in tailpointer mode then issue an error
elsif((mm2s_error_or = '1')
or (stale_desc = '1' and mm2s_cmnd_wr='1'))then
mm2s_error <= '1';
end if;
end if;
end process MM2S_ERROR_PROCESS;
end implementation;
|
-------------------------------------------------------------------------------
-- _________ _____ _____ ____ _____ ___ ____ --
-- |_ ___ | |_ _| |_ _| |_ \|_ _| |_ ||_ _| --
-- | |_ \_| | | | | | \ | | | |_/ / --
-- | _| | | _ | | | |\ \| | | __'. --
-- _| |_ _| |__/ | _| |_ _| |_\ |_ _| | \ \_ --
-- |_____| |________| |_____| |_____|\____| |____||____| --
-- --
-------------------------------------------------------------------------------
-- --
-- Test bench to "Avalon MM interface for GPIO" --
-- --
-------------------------------------------------------------------------------
-- Copyright 2014 NTB University of Applied Sciences in Technology --
-- --
-- Licensed under the Apache License, Version 2.0 (the "License"); --
-- you may not use this file except in compliance with the License. --
-- You may obtain a copy of the License at --
-- --
-- http://www.apache.org/licenses/LICENSE-2.0 --
-- --
-- Unless required by applicable law or agreed to in writing, software --
-- distributed under the License is distributed on an "AS IS" BASIS, --
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. --
-- See the License for the specific language governing permissions and --
-- limitations under the License. --
-------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE IEEE.math_real.ALL;
USE work.fLink_definitions.ALL;
USE work.avalon_gpio_interface_pkg.ALL;
ENTITY avalon_gpio_interface_tb IS
END ENTITY avalon_gpio_interface_tb;
ARCHITECTURE sim OF avalon_gpio_interface_tb IS
CONSTANT main_period : TIME := 8 ns; -- 50Mhz
CONSTANT number_of_gpios : INTEGER := 33;
CONSTANT unice_id: STD_LOGIC_VECTOR (c_fLink_avs_data_width-1 DOWNTO 0) := x"6770696f";
SIGNAL sl_clk : STD_LOGIC := '0';
SIGNAL sl_reset_n : STD_LOGIC := '0';
SIGNAL slv_avs_address : STD_LOGIC_VECTOR (c_gpio_interface_address_with-1 DOWNTO 0):= (OTHERS =>'0');
SIGNAL slv_avs_byteenable : STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS =>'1');
SIGNAL sl_avs_read : STD_LOGIC:= '0';
SIGNAL sl_avs_write : STD_LOGIC:= '0';
SIGNAL slv_avs_write_data : STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0):= (OTHERS =>'0');
SIGNAL slv_avs_read_data : STD_LOGIC_VECTOR(c_fLink_avs_data_width-1 DOWNTO 0):= (OTHERS =>'0');
SIGNAL slv_gpios : STD_LOGIC_VECTOR(number_of_gpios-1 DOWNTO 0):= (OTHERS =>'0');
CONSTANT c_usig_number_of_regs: INTEGER := (number_of_gpios-1)/c_fLink_avs_data_width+1;
BEGIN
--create component
my_unit_under_test : avalon_gpio_interface
GENERIC MAP(
number_of_gpios =>number_of_gpios,
unice_id => unice_id
)
PORT MAP(
isl_clk => sl_clk,
isl_reset_n => sl_reset_n,
islv_avs_address => slv_avs_address,
islv_avs_byteenable => slv_avs_byteenable,
isl_avs_read => sl_avs_read,
isl_avs_write => sl_avs_write,
islv_avs_write_data => slv_avs_write_data,
oslv_avs_read_data => slv_avs_read_data,
oslv_gpios => slv_gpios
);
sl_clk <= NOT sl_clk after main_period/2;
tb_main_proc : PROCESS
BEGIN
sl_reset_n <= '0';
WAIT FOR 2*main_period;
sl_reset_n <= '1';
WAIT FOR main_period/2;
--test id register:
WAIT FOR 10*main_period;
sl_avs_read <= '1';
slv_avs_address <= STD_LOGIC_VECTOR(to_unsigned(c_fLink_typdef_address,c_gpio_interface_address_with));
WAIT FOR main_period;
sl_avs_read <= '0';
slv_avs_address <= (OTHERS =>'0');
ASSERT slv_avs_read_data(c_fLink_interface_version_length-1 DOWNTO 0) = STD_LOGIC_VECTOR(to_unsigned(c_gpio_interface_version,c_fLink_interface_version_length))
REPORT "Interface Version Missmatch" SEVERITY FAILURE;
ASSERT slv_avs_read_data(c_fLink_interface_version_length+c_fLink_subtype_length-1 DOWNTO c_fLink_interface_version_length) = STD_LOGIC_VECTOR(to_unsigned(c_gpio_subtype_id,c_fLink_subtype_length))
REPORT "Subtype ID Missmatch" SEVERITY FAILURE;
ASSERT slv_avs_read_data(c_fLink_avs_data_width-1 DOWNTO c_fLink_interface_version_length+c_fLink_interface_version_length) = STD_LOGIC_VECTOR(to_unsigned(c_fLink_digital_io_id,c_fLink_id_length))
REPORT "Type ID Missmatch" SEVERITY FAILURE;
--test mem size register:
WAIT FOR 10*main_period;
sl_avs_read <= '1';
slv_avs_address <= STD_LOGIC_VECTOR(to_unsigned(c_fLink_mem_size_address,c_gpio_interface_address_with));
WAIT FOR main_period;
sl_avs_read <= '0';
slv_avs_address <= (OTHERS =>'0');
ASSERT to_integer(UNSIGNED(slv_avs_read_data)) = 4*INTEGER(2**c_gpio_interface_address_with)
REPORT "Memory Size Error: "&INTEGER'IMAGE(4*INTEGER(2**(number_of_gpios/c_fLink_avs_data_width)))&"/"&INTEGER'IMAGE(to_integer(UNSIGNED(slv_avs_read_data))) SEVERITY FAILURE;
--test unic id register:
WAIT FOR 10*main_period;
sl_avs_read <= '1';
slv_avs_address <= STD_LOGIC_VECTOR(to_unsigned(c_fLink_unice_id_address,c_gpio_interface_address_with));
WAIT FOR main_period;
sl_avs_read <= '0';
slv_avs_address <= (OTHERS =>'0');
ASSERT slv_avs_read_data = unice_id
REPORT "Unic Id Error" SEVERITY FAILURE;
--test number of chanels register:
WAIT FOR 10*main_period;
sl_avs_read <= '1';
slv_avs_address <= STD_LOGIC_VECTOR(to_unsigned(c_fLink_number_of_chanels_address,c_gpio_interface_address_with));
WAIT FOR main_period;
sl_avs_read <= '0';
slv_avs_address <= (OTHERS =>'0');
ASSERT slv_avs_read_data(c_fLink_interface_version_length-1 DOWNTO 0) = STD_LOGIC_VECTOR(to_unsigned(number_of_gpios,c_fLink_interface_version_length))
REPORT "Number of Channels Error" SEVERITY FAILURE;
FOR i IN 0 TO c_usig_number_of_regs-1 LOOP
--test dir register:
WAIT FOR 1000*main_period;
sl_avs_write <= '1';
slv_avs_address <= STD_LOGIC_VECTOR(to_unsigned(c_fLink_number_of_std_registers+i,c_gpio_interface_address_with));
slv_avs_write_data <= x"FFFFFFFF";
WAIT FOR main_period;
sl_avs_write <= '0';
slv_avs_address <= (OTHERS =>'0');
slv_avs_write_data <= (OTHERS =>'0');
WAIT FOR main_period;
sl_avs_read <= '1';
slv_avs_address <= STD_LOGIC_VECTOR(to_unsigned(c_fLink_number_of_std_registers+i,c_gpio_interface_address_with));
WAIT FOR main_period;
sl_avs_read <= '0';
slv_avs_address <= (OTHERS =>'0');
IF i /= c_usig_number_of_regs -1 THEN
ASSERT slv_avs_read_data = x"FFFFFFFF"
REPORT "Wrong dir was given back" SEVERITY FAILURE;
ELSE
FOR u IN 0 TO (number_of_gpios mod c_fLink_avs_data_width)-1 LOOP
ASSERT slv_avs_read_data(u) = '1'
REPORT "Wrong dir was given back" SEVERITY FAILURE;
END LOOP;
END IF;
--test value register:
WAIT FOR 1000*main_period;
sl_avs_write <= '1';
slv_avs_address <= STD_LOGIC_VECTOR(to_unsigned(c_fLink_number_of_std_registers+(number_of_gpios-1)/c_fLink_avs_data_width+i+1,c_gpio_interface_address_with));
slv_avs_write_data <= x"FFFFFFFF";
WAIT FOR main_period;
sl_avs_write <= '0';
slv_avs_address <= (OTHERS =>'0');
slv_avs_write_data <= (OTHERS =>'0');
WAIT FOR main_period;
sl_avs_read <= '1';
slv_avs_address <= STD_LOGIC_VECTOR(to_unsigned(c_fLink_number_of_std_registers+(number_of_gpios-1)/c_fLink_avs_data_width+i+1,c_gpio_interface_address_with));
WAIT FOR main_period;
sl_avs_read <= '0';
slv_avs_address <= (OTHERS =>'0');
IF i /= c_usig_number_of_regs-1 THEN
ASSERT slv_avs_read_data = x"FFFFFFFF"
REPORT "Wrong value was given back" SEVERITY FAILURE;
ASSERT slv_gpios((i+1)*c_fLink_avs_data_width-1 DOWNTO i*c_fLink_avs_data_width) = x"FFFFFFFF"
REPORT "Output not set" SEVERITY FAILURE;
ELSE
FOR u IN 0 TO (number_of_gpios mod c_fLink_avs_data_width)-1 LOOP
ASSERT slv_avs_read_data(u) = '1'
REPORT "Wrong value was given back" SEVERITY FAILURE;
ASSERT slv_gpios(u+i*c_fLink_avs_data_width) = '1'
REPORT "Output not set" SEVERITY FAILURE;
END LOOP;
END IF;
END LOOP;
WAIT FOR 1000*main_period;
ASSERT false REPORT "End of simulation" SEVERITY FAILURE;
END PROCESS tb_main_proc;
END ARCHITECTURE sim;
|
-------------------------------------------------------------------------------
-- axi_master_lite.vhd
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_master_lite.vhd
--
-- Description:
--
-- This VHDL file is the top level design file for the (Lite) AXI Master
-- design that only supports single data beat transfers. This succeeds
-- the plbv46_master_single design.
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_master_lite.vhd
--
-------------------------------------------------------------------------------
-- Author: DET
-- Revision: $Revision: 1.1.2.3 $
-- Date: $12/01/2010$
--
-- History:
-- DET 12/01/2010 Initial Version
--
-- DET 12/14/2010 Initial
-- ~~~~~~
-- -- Per CR587090
-- - Removed the input port m_axi_rlast. It is not part of the AXI4-Lite
-- signal set.
-- ^^^^^^
--
-- DET 12/17/2010 Initial
-- ~~~~~~
-- -- Per CR587285
-- - Add _lite to AXI4 port names per DDS.
-- ^^^^^^
--
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_master_lite_v1_00_a;
Use axi_master_lite_v1_00_a.axi_master_lite_reset;
Use axi_master_lite_v1_00_a.axi_master_lite_cntlr;
-------------------------------------------------------------------------------
entity axi_master_lite is
generic (
-- AXI4-Lite Parameters
C_M_AXI_LITE_ADDR_WIDTH : INTEGER range 32 to 32 := 32;
-- width of AXI4 Address Bus (in bits)
C_M_AXI_LITE_DATA_WIDTH : INTEGER range 32 to 32 := 32;
-- Width of the AXI4 Data Bus (in bits)
-- FPGA Family Parameter
C_FAMILY : String := "virtex6"
-- Select the target architecture type
-- see the family.vhd package in the proc_common
-- library
);
port (
-----------------------------------------------------------------------
-- Clock Input
-----------------------------------------------------------------------
m_axi_lite_aclk : in std_logic ;-- AXI4
-----------------------------------------------------------------------
-- Reset Input (active low)
-----------------------------------------------------------------------
m_axi_lite_aresetn : in std_logic ;-- AXI4
-----------------------------------------------------------------------
-- Master Detected Error output
-----------------------------------------------------------------------
md_error : out std_logic ;-- Discrete Out
----------------------------------------------------------------------------
-- AXI4 Read Channels
----------------------------------------------------------------------------
-- AXI4 Read Address Channel -- AXI4
m_axi_lite_arready : in std_logic ; -- AXI4
m_axi_lite_arvalid : out std_logic ; -- AXI4
m_axi_lite_araddr : out std_logic_vector -- AXI4
(C_M_AXI_LITE_ADDR_WIDTH-1 downto 0); -- AXI4
m_axi_lite_arprot : out std_logic_vector(2 downto 0) ; -- AXI4
-- AXI4
-- AXI4 Read Data Channel -- AXI4
m_axi_lite_rready : out std_logic ; -- AXI4
m_axi_lite_rvalid : in std_logic ; -- AXI4
m_axi_lite_rdata : in std_logic_vector -- AXI4
(C_M_AXI_LITE_DATA_WIDTH-1 downto 0) ; -- AXI4
m_axi_lite_rresp : in std_logic_vector(1 downto 0) ; -- AXI4
-----------------------------------------------------------------------------
-- AXI4 Write Channels
-----------------------------------------------------------------------------
-- AXI4 Write Address Channel
m_axi_lite_awready : in std_logic ; -- AXI4
m_axi_lite_awvalid : out std_logic ; -- AXI4
m_axi_lite_awaddr : out std_logic_vector -- AXI4
(C_M_AXI_LITE_ADDR_WIDTH-1 downto 0); -- AXI4
m_axi_lite_awprot : out std_logic_vector(2 downto 0) ; -- AXI4
-- AXI4
-- AXI4 Write Data Channel -- AXI4
m_axi_lite_wready : in std_logic ; -- AXI4
m_axi_lite_wvalid : out std_logic ; -- AXI4
m_axi_lite_wdata : out std_logic_vector -- AXI4
(C_M_AXI_LITE_DATA_WIDTH-1 downto 0); -- AXI4
m_axi_lite_wstrb : out std_logic_vector -- AXI4
((C_M_AXI_LITE_DATA_WIDTH/8)-1 downto 0);-- AXI4
-- AXI4
-- AXI4 Write Response Channel -- AXI4
m_axi_lite_bready : out std_logic ; -- AXI4
m_axi_lite_bvalid : in std_logic ; -- AXI4
m_axi_lite_bresp : in std_logic_vector(1 downto 0) ; -- AXI4
-----------------------------------------------------------------------------
-- IP Master Request/Qualifers
-----------------------------------------------------------------------------
ip2bus_mstrd_req : In std_logic; -- IPIC
ip2bus_mstwr_req : In std_logic; -- IPIC
ip2bus_mst_addr : in std_logic_vector(0 to C_M_AXI_LITE_ADDR_WIDTH-1); -- IPIC
ip2bus_mst_be : in std_logic_vector(0 to (C_M_AXI_LITE_DATA_WIDTH/8)-1);-- IPIC
ip2bus_mst_lock : In std_logic; -- IPIC
ip2bus_mst_reset : In std_logic; -- IPIC
-- IPIC
-----------------------------------------------------------------------------
-- IP Request Status Reply
-----------------------------------------------------------------------------
bus2ip_mst_cmdack : Out std_logic; -- IPIC
bus2ip_mst_cmplt : Out std_logic; -- IPIC
bus2ip_mst_error : Out std_logic; -- IPIC
bus2ip_mst_rearbitrate : Out std_logic; -- IPIC
bus2ip_mst_cmd_timeout : out std_logic; -- IPIC
-- IPIC
-- IPIC
-----------------------------------------------------------------------------
-- IPIC Read data
-----------------------------------------------------------------------------
bus2ip_mstrd_d : out std_logic_vector(0 to C_M_AXI_LITE_DATA_WIDTH-1); -- IPIC
bus2ip_mstrd_src_rdy_n : Out std_logic; -- IPIC
-- IPIC
-----------------------------------------------------------------------------
-- IPIC Write data
-----------------------------------------------------------------------------
ip2bus_mstwr_d : In std_logic_vector(0 to C_M_AXI_LITE_DATA_WIDTH-1); -- IPIC
bus2ip_mstwr_dst_rdy_n : Out std_logic -- IPIC
);
end entity axi_master_lite;
architecture implementation of axi_master_lite is
-- Signals
signal sig_master_reset : std_logic := '0';
begin --(architecture implementation)
------------------------------------------------------------
-- Instance: I_RESET_MODULE
--
-- Description:
-- Instance for the Reset Module
--
------------------------------------------------------------
I_RESET_MODULE : entity axi_master_lite_v1_00_a.axi_master_lite_reset
port map (
-- Clock Input
axi_aclk => m_axi_lite_aclk ,
-- Reset Input (active low)
axi_aresetn => m_axi_lite_aresetn ,
-- IPIC Reset Input
ip2bus_mst_reset => ip2bus_mst_reset ,
-- Combined Reset Output
rst2ip_reset_out => sig_master_reset
);
------------------------------------------------------------
-- Instance: I_RD_WR_CNTLR
--
-- Description:
-- Instance for the Read/Write Controller Module
--
------------------------------------------------------------
I_RD_WR_CNTLR : entity axi_master_lite_v1_00_a.axi_master_lite_cntlr
generic map (
C_M_AXI_LITE_ADDR_WIDTH => C_M_AXI_LITE_ADDR_WIDTH,
C_M_AXI_LITE_DATA_WIDTH => C_M_AXI_LITE_DATA_WIDTH,
C_FAMILY => C_FAMILY
)
port map (
-----------------------------------
-- Clock Input
-----------------------------------
axi_aclk => m_axi_lite_aclk ,
-----------------------------------
-- Reset Input (active high)
-----------------------------------
axi_reset => sig_master_reset,
-----------------------------------
-- Master Detected Error output
-----------------------------------
md_error => md_error ,
-----------------------------------
-- AXI4 Read Channels
-----------------------------------
-- AXI4 Read Address Channel
m_axi_arready => m_axi_lite_arready ,
m_axi_arvalid => m_axi_lite_arvalid ,
m_axi_araddr => m_axi_lite_araddr ,
m_axi_arprot => m_axi_lite_arprot ,
-- AXI4 Read Data Channel
m_axi_rready => m_axi_lite_rready ,
m_axi_rvalid => m_axi_lite_rvalid ,
m_axi_rdata => m_axi_lite_rdata ,
m_axi_rresp => m_axi_lite_rresp ,
-----------------------------------
-- AXI4 Write Channels
-----------------------------------
-- AXI4 Write Address Channel
m_axi_awready => m_axi_lite_awready ,
m_axi_awvalid => m_axi_lite_awvalid ,
m_axi_awaddr => m_axi_lite_awaddr ,
m_axi_awprot => m_axi_lite_awprot ,
-- AXI4 Write Data Channel
m_axi_wready => m_axi_lite_wready ,
m_axi_wvalid => m_axi_lite_wvalid ,
m_axi_wdata => m_axi_lite_wdata ,
m_axi_wstrb => m_axi_lite_wstrb ,
-- AXI4 Write Response Channel
m_axi_bready => m_axi_lite_bready ,
m_axi_bvalid => m_axi_lite_bvalid ,
m_axi_bresp => m_axi_lite_bresp ,
-----------------------------------
-- IP Master Request/Qualifers
-----------------------------------
ip2bus_mstrd_req => ip2bus_mstrd_req ,
ip2bus_mstwr_req => ip2bus_mstwr_req ,
ip2bus_mst_addr => ip2bus_mst_addr ,
ip2bus_mst_be => ip2bus_mst_be ,
ip2bus_mst_lock => ip2bus_mst_lock ,
-----------------------------------
-- IP Request Status Reply
-----------------------------------
bus2ip_mst_cmdack => bus2ip_mst_cmdack ,
bus2ip_mst_cmplt => bus2ip_mst_cmplt ,
bus2ip_mst_error => bus2ip_mst_error ,
bus2ip_mst_rearbitrate => bus2ip_mst_rearbitrate ,
bus2ip_mst_cmd_timeout => bus2ip_mst_cmd_timeout ,
-----------------------------------
-- IPIC Read data
-----------------------------------
bus2ip_mstrd_d => bus2ip_mstrd_d ,
bus2ip_mstrd_src_rdy_n => bus2ip_mstrd_src_rdy_n ,
----------------------------------
-- IPIC Write data
----------------------------------
ip2bus_mstwr_d => ip2bus_mstwr_d ,
bus2ip_mstwr_dst_rdy_n => bus2ip_mstwr_dst_rdy_n
);
end implementation;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library gpr;
use gpr.OneHotGPR.all;
entity MRAM is
port(
-- 0 - write; 1 - read
RW: in std_logic;
CLK: in std_logic;
-- address for the first operand
ADDR1: in mem_addr;
-- address for the second operand
ADDR2: in mem_addr;
-- address to write
ADDRW: in mem_addr;
-- first operand
D1OUT: out operand;
-- second operand
D2OUT: out operand;
-- data to write
DWIN: in operand
);
end MRAM;
architecture Beh_GPR of MRAM is
type tRAM is array (0 to 31) of operand;
signal RAM: tRAM:= (
-- | VALUE BIN | ADR BIN | CONST NAME |
"0000000000000000", -- | 00000 | STUB, ADDR_DATA_START |
"0000000000000000", -- | 00001 | |
"0000000000000000", -- | 00010 | |
"0000000000000000", -- | 00011 | |
"0000000000000000", -- | 00100 | |
"0000000000000000", -- | 00101 | |
"0000000000000000", -- | 00110 | |
"0000000000000000", -- | 00111 | |
"0000000000000000", -- | 01000 | |
"0000000000000000", -- | 01001 | |
"0000000000000000", -- | 01010 | |
"0000000000000000", -- | 01011 | |
"0000000000000000", -- | 01100 | |
"0000000000000000", -- | 01101 | |
"0000000000000000", -- | 01110 | |
"0000000000000000", -- | 01111 | |
"0000000000001000", -- | 10000 | ADDR_LENGTH |
"0000000000000000", -- | 10001 | ADDR_COUNTER |
"0000000000000000", -- | 10010 | ADDR_CURRENT_VALUE |
"0000000000000001", -- | 10011 | ADDR_INIT_VALUE |
"0000000000000000", -- | 10100 | ADDR_ZERO |
"0000000000000001", -- | 10101 | ADDR_ONE |
"0000000000000000", -- | 10110 | EMPTY_SPACE |
others => "0000000000000000"
);
signal data_win: operand;
signal data_1out: operand;
signal data_2out: operand;
Begin
data_win <= DWIN;
WRITE: process(CLK)
begin
if (rising_edge(CLK)) then
if (RW = '0') then
RAM(conv_integer(ADDRW)) <= data_win;
end if;
end if;
end process;
data_1out <= RAM (conv_integer(ADDR1));
data_2out <= RAM (conv_integer(ADDR2));
READ: process(CLK)
begin
if (rising_edge(CLK)) then
if (RW = '1') then
D1OUT <= data_1out;
D2OUT <= data_2out;
else
D1OUT <= (others => 'Z');
D2OUT <= (others => 'Z');
end if;
end if;
end process;
End Beh_GPR;
|
-------------------------------------------------------------------------------
-- Author: Aragonés Orellana, Silvia
-- García Garcia, Ruy
-- Project Name: PIC
-- Design Name: dma.vhd
-- Module Name: dma_bus_controller.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- La funcionalidad del Controlador de Bus es enmascarar las señales de entrada
-- y salida de los subsistemas Transmisor y Receptor del DMA, con el fin de
-- mantener tanto los Buses de Datos y Direcciones como las señales de control
-- conectadas entre la fuente y el destino correspondiente en función de las
-- señales de handshake entre uP/DMA y DMA/RS232.
-- A su vez, se encarga de mantener excitados los buses y las señales de
-- control (a una combinación de valores que no modifiquen el estado de la
-- memoria) durante las transiciones entre Receptor/Transmisor y el uP.
entity dma_bus_controller is
Port ( -- Señales procedentes del bus del uP.
Clk : in STD_LOGIC;
Reset : in STD_LOGIC;
Databus : inout STD_LOGIC_VECTOR (7 downto 0);
Address : out STD_LOGIC_VECTOR (7 downto 0);
ChipSelect : out STD_LOGIC;
WriteEnable : out STD_LOGIC;
OutputEnable : out STD_LOGIC;
-- Señales de handshake entre uP y DMA.
Send : in STD_LOGIC;
Ready : out STD_LOGIC;
-- Señales de handshake entre RS232 y DMA.
DMA_RQ : out STD_LOGIC;
DMA_ACK : in STD_LOGIC;
RX_empty : in STD_LOGIC;
-- pragma synthesis off
BC_state_ns : out integer;
-- pragma synthesis on
-- Señales procedentes del Receptor para el control de los buses de
-- datos y direcciones, y las señales de control.
RX_Databus : in STD_LOGIC_VECTOR (7 downto 0);
RX_Address : in STD_LOGIC_VECTOR (7 downto 0);
RX_ChipSelect : in STD_LOGIC;
RX_WriteEnable : in STD_LOGIC;
-- Señales de control utilizadas por la máquina de estados del
-- Controlador de Bus para comunicarse con el Receptor.
RX_OutputEnable : in STD_LOGIC;
RX_start : out STD_LOGIC;
RX_end : in STD_LOGIC;
-- Señales procedentes del Transmisor.
TX_Databus : out STD_LOGIC_VECTOR (7 downto 0);
TX_Address : in STD_LOGIC_VECTOR (7 downto 0);
TX_ChipSelect : in STD_LOGIC;
TX_WriteEnable : in STD_LOGIC;
TX_OutputEnable : in STD_LOGIC;
-- Señales de control utilizadas por la máquina de estados del
-- Controlador de Bus para comunicarse con el Transmisor.
TX_start : out STD_LOGIC;
TX_ready : in STD_LOGIC;
TX_end : in STD_LOGIC
);
end dma_bus_controller;
architecture Behavioral of dma_bus_controller is
-- Definición de los posibles estados de la FSM del Controlador de Bus:
-- + Idle: Los buses de datos y direcciones, y las señales de control están
-- bajo el control del uP.
-- Las salidas del DMA se mantienen a alta impedancia.
-- + RX_wait_bus: Los buses de datos y direcciones, y las señales de control
-- están bajo el control del uP. El DMA avisa al uP de que hay datos a la
-- espera de ser recibidos.
-- Las salidas del DMA se mantienen a alta impedancia.
-- + RX_use_bus: El Controlador de Bus da el control de los buses de datos y
-- direcciones, y las señales de control, al Receptor.
-- Las salidas del DMA se correponden con las del Receptor.
-- + RX_free_bus: El Receptor ha terminado de utilizar los buses de datos y
-- direcciones, y las señales de control. El Controlador de Bus mantiene
-- excitadas dichas señales a la espera de que el uP vuelva a tomar su
-- control.
-- + TX_use_bus: El Controlador de Bus da el control de los buses de datos y
-- direcciones, y las señales de control, al Transmisor.
-- Las salidas del DMA se correponden con las del Transmisor.
-- + RX_free_bus: El Transmisor ha terminado de utilizar los buses de datos
-- y direcciones, y las señales de control. El Controlador de Bus
-- mantiene excitadas dichas señales a la espera de que el uP vuelva a
-- tomar su control.
type BusController_ST is (idle, RX_wait_bus, RX_use_bus , RX_free_bus,
TX_use_bus, TX_free_bus);
signal BC_now, BC_next : BusController_ST;
begin
-- Proceso secuencial de la máquina de estados del Controlador de Bus.
-- Dispone de una señal de Reset asíncrono activa a nivel bajo. Mientras que
-- esta señal se mantenga activa, la FSM se mantiene en el estado de 'Idle'.
process(Clk, Reset)
begin
if (Reset = '0') then
BC_now <= idle;
elsif Clk'event and Clk = '1' then
BC_now <= BC_next;
end if;
end process;
-- Proceso combinacional de la máquina de estados.
process(BC_now,
RX_empty, Send,
DMA_ACK, RX_end, TX_ready, TX_end, RX_Databus,
RX_Address, RX_ChipSelect, RX_WriteEnable, RX_OutputEnable,
TX_Address, TX_ChipSelect, TX_WriteEnable, TX_OutputEnable)
begin
-- Valores preasignados por defecto.
Databus <= (others => 'Z');
Address <= (others => 'Z');
ChipSelect <= 'Z';
WriteEnable <= 'Z';
OutputEnable <= 'Z';
DMA_RQ <= '0';
Ready <= '0';
RX_start <= '0';
TX_start <= '0';
case BC_now is
when idle =>
Ready <= '1';
-- Cuando el uP ordene envíar datos y el Transmisor del DMA este
-- listo:
if (Send = '1' and TX_ready = '1') then
Ready <= '0';
TX_start <= '1';
BC_next <= TX_use_bus;
-- Si no, si el DMA recibe la señal de que hay datos preparados
-- para leer desde el RS232...
elsif (RX_empty = '0') then
DMA_RQ <= '1';
BC_next <= RX_wait_bus;
else
BC_next <= idle;
end if;
when TX_use_bus =>
Address <= TX_Address;
ChipSelect <= TX_ChipSelect;
WriteEnable <= TX_WriteEnable;
OutputEnable <= TX_OutputEnable;
-- Si el Transmisor ha terminado de utilizar el bus...
if TX_end = '1' then
BC_next <= TX_free_bus;
else
BC_next <= TX_use_bus;
end if;
when TX_free_bus =>
Databus <= (others => '0');
Address <= (others => '0');
ChipSelect <= '0';
WriteEnable <= '0';
OutputEnable <= '0';
Ready <= '1';
-- Si el uP vuelve a tomar el control del bus en el siguiente
-- ciclo de reloj...
if Send = '0' then
BC_next <= idle;
else
BC_next <= TX_free_bus;
end if;
when RX_wait_bus =>
DMA_RQ <= '1';
Ready <= '1';
-- Si el uP cede el bus a partir del siguiente ciclo de reloj...
if DMA_ACK = '1' then
RX_start <= '1';
BC_next <= RX_use_bus;
-- Si no, y el uP ordene envíar datos y el Transmisor del DMA este
-- listo:
elsif (Send = '1' and TX_ready = '1') then
Ready <= '0';
TX_start <= '1';
BC_next <= TX_use_bus;
else
BC_next <= RX_wait_bus;
end if;
when RX_use_bus =>
Databus <= RX_Databus;
Address <= RX_Address;
ChipSelect <= RX_ChipSelect;
WriteEnable <= RX_WriteEnable;
OutputEnable <= RX_OutputEnable;
DMA_RQ <= '1';
-- Si el Receptor ha terminado de utilizar el bus...
if RX_end = '1' then
BC_next <= RX_free_bus;
else
BC_next <= RX_use_bus;
end if;
when RX_free_bus =>
Databus <= (others => '0');
Address <= (others => '0');
ChipSelect <= '0';
WriteEnable <= '0';
OutputEnable <= '0';
-- Si el uP vuelve a tomar el control del bus en el siguiente
-- ciclo de reloj...
if DMA_ACK = '0' then
BC_next <= idle;
else
BC_next <= RX_free_bus;
end if;
end case;
end process;
-- El bus de datos siempre estará conectado a la entrada del bus de datos
-- del subsistema receptor.
TX_Databus <= Databus;
-- pragma synthesis off
process(BC_now)
begin
case BC_now is
when idle => BC_state_ns <= 0;
when TX_use_bus => BC_state_ns <= 1;
when TX_free_bus => BC_state_ns <= 2;
when RX_wait_bus => BC_state_ns <= 3;
when RX_use_bus => BC_state_ns <= 4;
when RX_free_bus => BC_state_ns <= 5;
end case;
end process;
-- pragma synthesis on
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- The T8243 asynchronous toplevel without tri-state signals
--
-- $Id: t8243_async_notri.vhd,v 1.1 2006-07-13 22:53:56 arniml Exp $
-- $Name: not supported by cvs2svn $
--
-- Copyright (c) 2006, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t48/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity t8243_async_notri is
port (
-- System Interface -------------------------------------------------------
reset_n_i : in std_logic;
-- Control Interface ------------------------------------------------------
cs_n_i : in std_logic;
prog_n_i : in std_logic;
-- Port 2 Interface -------------------------------------------------------
p2_i : in std_logic_vector(3 downto 0);
p2_o : out std_logic_vector(3 downto 0);
p2_en_o : out std_logic;
-- Port 4 Interface -------------------------------------------------------
p4_i : in std_logic_vector(3 downto 0);
p4_o : out std_logic_vector(3 downto 0);
p4_en_o : out std_logic;
-- Port 5 Interface -------------------------------------------------------
p5_i : in std_logic_vector(3 downto 0);
p5_o : out std_logic_vector(3 downto 0);
p5_en_o : out std_logic;
-- Port 6 Interface -------------------------------------------------------
p6_i : in std_logic_vector(3 downto 0);
p6_o : out std_logic_vector(3 downto 0);
p6_en_o : out std_logic;
-- Port 7 Interface -------------------------------------------------------
p7_i : in std_logic_vector(3 downto 0);
p7_o : out std_logic_vector(3 downto 0);
p7_en_o : out std_logic
);
end t8243_async_notri;
use work.t8243_comp_pack.t8243_core;
architecture struct of t8243_async_notri is
signal vdd_s : std_logic;
begin
vdd_s <= '1';
-----------------------------------------------------------------------------
-- The T8243 Core
-----------------------------------------------------------------------------
t8243_core_b : t8243_core
generic map (
clk_fall_level_g => 0
)
port map (
clk_i => prog_n_i,
clk_rise_en_i => vdd_s,
clk_fall_en_i => vdd_s,
reset_n_i => reset_n_i,
cs_n_i => cs_n_i,
prog_n_i => prog_n_i,
p2_i => p2_i,
p2_o => p2_o,
p2_en_o => p2_en_o,
p4_i => p4_i,
p4_o => p4_o,
p4_en_o => p4_en_o,
p5_i => p5_i,
p5_o => p5_o,
p5_en_o => p5_en_o,
p6_i => p6_i,
p6_o => p6_o,
p6_en_o => p6_en_o,
p7_i => p7_i,
p7_o => p7_o,
p7_en_o => p7_en_o
);
end struct;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-------------------------------------------------------------------------------
|
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32
);
port (
I_PORT1 : in std_logic;
I_PORT2 : out std_logic
);
end entity FIFO;
-- Violation below
entity FIFO is
generic(G_SIZE : integer := 10;
G_WIDTH : integer := 256;
G_DEPTH : integer := 32
);
port (
I_PORT1 :in std_logic;
I_PORT2 :out std_logic
);
end entity FIFO;
|
entity test is begin end;
entity test is begin end;
|
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:29:27 MST 2014
-- Date : Tue Jun 30 15:23:02 2015
-- Host : Vangelis-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/Users/Vfor/Documents/GitHub/Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/ip/Clock8346/Clock8346_stub.vhdl
-- Design : Clock8346
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a100tcsg324-3
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Clock8346 is
Port (
clk_in1 : in STD_LOGIC;
clk_out1 : out STD_LOGIC;
locked : out STD_LOGIC
);
end Clock8346;
architecture stub of Clock8346 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk_in1,clk_out1,locked";
begin
end;
|
entity repro1 is
end repro1;
architecture arch of repro1 is
type wf_el is record
t : time;
v : bit;
end record;
type wf_arr is array (natural range <>) of wf_el;
function get_wf (bv : bit_vector; p : time) return wf_arr is
variable res : wf_arr (bv'range);
variable t : time;
begin
t := 0 ns;
for i in bv'range loop
res (i) := (t => t, v => bv (i));
t := t + p;
end loop;
return res;
end get_wf;
procedure play_wf (signal s : out bit; wf : wf_arr; init : bit) is
begin
s <= init;
for i in wf'range loop
wait for wf (i).t;
s <= wf (i).v;
end loop;
wait;
end play_wf;
function get_str (l : natural; c : character) return string is
begin
return string'(1 to l => c);
end get_str;
signal o : bit;
begin
play_wf (o, get_wf (b"0110100", 2 ns), '1');
process
begin
for i in 1 to 8 loop
report get_str (32 + 4 * i, character'val (64 + i));
wait for 2 ns;
end loop;
wait;
end process;
end arch;
|
entity repro1 is
end repro1;
architecture arch of repro1 is
type wf_el is record
t : time;
v : bit;
end record;
type wf_arr is array (natural range <>) of wf_el;
function get_wf (bv : bit_vector; p : time) return wf_arr is
variable res : wf_arr (bv'range);
variable t : time;
begin
t := 0 ns;
for i in bv'range loop
res (i) := (t => t, v => bv (i));
t := t + p;
end loop;
return res;
end get_wf;
procedure play_wf (signal s : out bit; wf : wf_arr; init : bit) is
begin
s <= init;
for i in wf'range loop
wait for wf (i).t;
s <= wf (i).v;
end loop;
wait;
end play_wf;
function get_str (l : natural; c : character) return string is
begin
return string'(1 to l => c);
end get_str;
signal o : bit;
begin
play_wf (o, get_wf (b"0110100", 2 ns), '1');
process
begin
for i in 1 to 8 loop
report get_str (32 + 4 * i, character'val (64 + i));
wait for 2 ns;
end loop;
wait;
end process;
end arch;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
-- Date : Tue Oct 31 12:11:23 2017
-- Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ dbg_ila_stub.vhdl
-- Design : dbg_ila
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7k325tffg676-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
clk : in STD_LOGIC;
probe0 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe1 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe2 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe3 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe4 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe5 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe6 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe7 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe8 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe9 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe10 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe11 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe12 : in STD_LOGIC_VECTOR ( 63 downto 0 );
probe13 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe14 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe15 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe16 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe17 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe18 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe19 : in STD_LOGIC_VECTOR ( 8 downto 0 );
probe20 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe21 : in STD_LOGIC_VECTOR ( 2 downto 0 );
probe22 : in STD_LOGIC_VECTOR ( 2 downto 0 );
probe23 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe24 : in STD_LOGIC_VECTOR ( 0 to 0 );
probe25 : in STD_LOGIC_VECTOR ( 7 downto 0 );
probe26 : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,probe0[63:0],probe1[63:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[63:0],probe8[0:0],probe9[0:0],probe10[0:0],probe11[0:0],probe12[63:0],probe13[0:0],probe14[0:0],probe15[0:0],probe16[0:0],probe17[0:0],probe18[0:0],probe19[8:0],probe20[7:0],probe21[2:0],probe22[2:0],probe23[0:0],probe24[0:0],probe25[7:0],probe26[3:0]";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "ila,Vivado 2016.3";
begin
end;
|
-- file: my_dcm_exdes.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard example design
------------------------------------------------------------------------------
-- This example design instantiates the created clocking network, where each
-- output clock drives a counter. The high bit of each counter is ported.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity my_dcm_exdes is
generic (
TCQ : in time := 100 ps);
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(1 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic
);
end my_dcm_exdes;
architecture xilinx of my_dcm_exdes is
-- Parameters for the counters
---------------------------------
-- Counter width
constant C_W : integer := 16;
-- Reset for counters when lock status changes
signal reset_int : std_logic := '0';
-- Declare the clocks and counter
signal clk : std_logic;
signal clk_int : std_logic;
signal clk_n : std_logic;
signal counter : std_logic_vector(C_W-1 downto 0) := (others => '0');
signal rst_sync : std_logic;
signal rst_sync_int : std_logic;
signal rst_sync_int1 : std_logic;
signal rst_sync_int2 : std_logic;
component my_dcm is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic
);
end component;
begin
-- Create reset for the counters
reset_int <= COUNTER_RESET;
process (clk, reset_int) begin
if (reset_int = '1') then
rst_sync <= '1';
rst_sync_int <= '1';
rst_sync_int1 <= '1';
rst_sync_int2 <= '1';
elsif (clk 'event and clk='1') then
rst_sync <= '0';
rst_sync_int <= rst_sync;
rst_sync_int1 <= rst_sync_int;
rst_sync_int2 <= rst_sync_int1;
end if;
end process;
-- Instantiation of the clocking network
----------------------------------------
clknetwork : my_dcm
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Clock out ports
CLK_OUT1 => clk_int);
clk_n <= not clk;
clkout_oddr : ODDR2
port map
(Q => CLK_OUT(1),
C0 => clk,
C1 => clk_n,
CE => '1',
D0 => '1',
D1 => '0',
R => '0',
S => '0');
-- Connect the output clocks to the design
-------------------------------------------
clk <= clk_int;
-- Output clock sampling
-------------------------------------
process (clk, rst_sync_int2) begin
if (rst_sync_int2 = '1') then
counter <= (others => '0') after TCQ;
elsif (rising_edge(clk)) then
counter <= counter + 1 after TCQ;
end if;
end process;
-- alias the high bit to the output
COUNT <= counter(C_W-1);
end xilinx;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library work;
use work.zpu_config.all;
use work.zpuino_config.all;
use work.zpuinopkg.all;
use work.zpupkg.all;
use work.wishbonepkg.all;
library unisim;
use unisim.vcomponents.all;
entity sdram_ctrl is
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb_dat_o: out std_logic_vector(31 downto 0);
wb_dat_i: in std_logic_vector(31 downto 0);
wb_adr_i: in std_logic_vector(maxIOBit downto minIOBit);
wb_we_i: in std_logic;
wb_cyc_i: in std_logic;
wb_stb_i: in std_logic;
wb_sel_i: in std_logic_vector(3 downto 0);
wb_ack_o: out std_logic;
wb_stall_o: out std_logic;
-- extra clocking
clk_off_3ns: in std_logic;
-- SDRAM signals
DRAM_ADDR : OUT STD_LOGIC_VECTOR (11 downto 0);
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC
);
end entity sdram_ctrl;
architecture behave of sdram_ctrl is
component sdram_controller is
generic (
HIGH_BIT: integer := 24
);
PORT (
clock_100: in std_logic;
clock_100_delayed_3ns: in std_logic;
rst: in std_logic;
-- Signals to/from the SDRAM chip
DRAM_ADDR : OUT STD_LOGIC_VECTOR (11 downto 0);
DRAM_BA : OUT STD_LOGIC_VECTOR (1 downto 0);
DRAM_CAS_N : OUT STD_LOGIC;
DRAM_CKE : OUT STD_LOGIC;
DRAM_CLK : OUT STD_LOGIC;
DRAM_CS_N : OUT STD_LOGIC;
DRAM_DQ : INOUT STD_LOGIC_VECTOR(15 downto 0);
DRAM_DQM : OUT STD_LOGIC_VECTOR(1 downto 0);
DRAM_RAS_N : OUT STD_LOGIC;
DRAM_WE_N : OUT STD_LOGIC;
pending: out std_logic;
--- Inputs from rest of the system
address : IN STD_LOGIC_VECTOR (HIGH_BIT downto 2);
req_read : IN STD_LOGIC;
req_write : IN STD_LOGIC;
data_out : OUT STD_LOGIC_VECTOR (31 downto 0);
data_out_valid : OUT STD_LOGIC;
data_in : IN STD_LOGIC_VECTOR (31 downto 0);
data_mask : in std_logic_vector(3 downto 0)
);
end component;
signal sdr_address: STD_LOGIC_VECTOR (maxAddrBitBRAM downto 2);
signal sdr_req_read : STD_LOGIC;
signal sdr_req_write : STD_LOGIC;
signal sdr_data_out : STD_LOGIC_VECTOR (31 downto 0);
signal sdr_data_out_valid : STD_LOGIC;
signal sdr_data_in : STD_LOGIC_VECTOR (31 downto 0);
signal sdr_data_mask: std_logic_vector(3 downto 0);
signal pending: std_logic;
begin
ctrl: sdram_controller
generic map (
HIGH_BIT => maxAddrBitBRAM
)
port map (
clock_100 => wb_clk_i,
clock_100_delayed_3ns => clk_off_3ns,
rst => wb_rst_i,
DRAM_ADDR => DRAM_ADDR,
DRAM_BA => DRAM_BA,
DRAM_CAS_N => DRAM_CAS_N,
DRAM_CKE => DRAM_CKE,
DRAM_CLK => DRAM_CLK,
DRAM_CS_N => DRAM_CS_N,
DRAM_DQ => DRAM_DQ,
DRAM_DQM => DRAM_DQM,
DRAM_RAS_N => DRAM_RAS_N,
DRAM_WE_N => DRAM_WE_N,
pending => pending,
address => sdr_address,
req_read => sdr_req_read,
req_write => sdr_req_write,
data_out => sdr_data_out,
data_out_valid => sdr_data_out_valid,
data_in => sdr_data_in,
data_mask => sdr_data_mask
);
sdr_address(maxAddrBitBRAM downto 2) <= wb_adr_i(maxAddrBitBRAM downto 2);
sdr_req_read<='1' when wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='0' else '0';
sdr_req_write<='1' when wb_cyc_i='1' and wb_stb_i='1' and wb_we_i='1' else '0';
sdr_data_in <= wb_dat_i;
sdr_data_mask <= wb_sel_i;
wb_stall_o <= '1' when pending='1' else '0';
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
wb_ack_o <= sdr_data_out_valid;
wb_dat_o <= sdr_data_out;
end if;
end process;
end behave;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: libfpu
-- File: libfpu.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: LEON3 FPU interface types and components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.leon3.all;
library techmap;
use techmap.gencomp.all;
package libfpu is
type fp_rf_in_type is record
rd1addr : std_logic_vector(3 downto 0); -- read address 1
rd2addr : std_logic_vector(3 downto 0); -- read address 2
wraddr : std_logic_vector(3 downto 0); -- write address
wrdata : std_logic_vector(31 downto 0); -- write data
ren1 : std_ulogic; -- read 1 enable
ren2 : std_ulogic; -- read 2 enable
wren : std_ulogic; -- write enable
end record;
type fp_rf_out_type is record
data1 : std_logic_vector(31 downto 0); -- read data 1
data2 : std_logic_vector(31 downto 0); -- read data 2
end record;
type fpc_pipeline_control_type is record
pc : std_logic_vector(31 downto 0);
inst : std_logic_vector(31 downto 0);
cnt : std_logic_vector(1 downto 0);
trap : std_ulogic;
annul : std_ulogic;
pv : std_ulogic;
end record;
type fpc_debug_in_type is record
enable : std_ulogic;
write : std_ulogic;
fsr : std_ulogic; -- FSR access
addr : std_logic_vector(4 downto 0);
data : std_logic_vector(31 downto 0);
end record;
type fpc_debug_out_type is record
data : std_logic_vector(31 downto 0);
end record;
constant fpc_debug_none : fpc_debug_out_type := (data => X"00000000"
);
type fpc_in_type is record
flush : std_ulogic; -- pipeline flush
exack : std_ulogic; -- FP exception acknowledge
a_rs1 : std_logic_vector(4 downto 0);
d : fpc_pipeline_control_type;
a : fpc_pipeline_control_type;
e : fpc_pipeline_control_type;
m : fpc_pipeline_control_type;
x : fpc_pipeline_control_type;
lddata : std_logic_vector(31 downto 0); -- load data
dbg : fpc_debug_in_type; -- debug signals
end record;
type fpc_out_type is record
data : std_logic_vector(31 downto 0); -- store data
exc : std_logic; -- FP exception
cc : std_logic_vector(1 downto 0); -- FP condition codes
ccv : std_ulogic; -- FP condition codes valid
ldlock : std_logic; -- FP pipeline hold
holdn : std_ulogic;
dbg : fpc_debug_out_type; -- FP debug signals
end record;
constant fpc_out_none : fpc_out_type := (X"00000000", '0', "00", '1', '0', '1',
fpc_debug_none);
component grfpwxsh
generic (
tech : integer range 0 to NTECH := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
id : integer range 0 to 7 := 0
);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi : in fpc_in_type;
cpo : out fpc_out_type;
fpui : out grfpu_in_type;
fpuo : in grfpu_out_type
);
end component;
end;
|
entity e is end entity;
architecture a of e is
constant s1 :string := foreign'path;
constant s2 :string := foreign'foreign;
begin
end architecture;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_AROUND is
generic (
widthin : natural :=8;
widthout : natural :=4
);
port (
xin : in std_logic_vector(widthin-1 downto 0);
yout : out std_logic_vector(widthout-1 downto 0)
);
end alt_dspbuilder_AROUND;
architecture AROUND_SYNTH of alt_dspbuilder_AROUND is
signal ADDOFIVE : std_logic_vector(widthin downto 0) ;
signal XINEXT : std_logic_vector(widthin downto 0) ;
signal YOUTEXT : std_logic_vector(widthin downto 0);
signal notsigned : std_logic :='0';
begin
ev:if widthin=widthout generate
yout <= xin;
end generate ev;
nev:if (widthin>widthout) generate
ad5:if (widthin-widthout>1) generate
lo:for i in 0 to widthin-widthout-2 generate
ADDOFIVE(i) <= '1';
end generate lo;
hi:for i in widthin-widthout-1 to widthin generate
ADDOFIVE(i) <= '0';
end generate hi;
end generate ad5;
adn:if (widthin-widthout=1) generate
hi:for i in 0 to widthin generate
ADDOFIVE(i) <= '0';
end generate hi;
end generate adn;
XINEXT(widthin-1 downto 0) <= xin(widthin-1 downto 0);
XINEXT(widthin) <= xin(widthin-1);
notsigned <= not(XINEXT(widthin-1));
YOUTEXT <= XINEXT + ADDOFIVE + notsigned;
gy:for i in 0 to widthout-1 generate
yout(i) <= YOUTEXT(i+widthin-widthout) ;
end generate gy;
end generate ;
end AROUND_SYNTH;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_AROUND is
generic (
widthin : natural :=8;
widthout : natural :=4
);
port (
xin : in std_logic_vector(widthin-1 downto 0);
yout : out std_logic_vector(widthout-1 downto 0)
);
end alt_dspbuilder_AROUND;
architecture AROUND_SYNTH of alt_dspbuilder_AROUND is
signal ADDOFIVE : std_logic_vector(widthin downto 0) ;
signal XINEXT : std_logic_vector(widthin downto 0) ;
signal YOUTEXT : std_logic_vector(widthin downto 0);
signal notsigned : std_logic :='0';
begin
ev:if widthin=widthout generate
yout <= xin;
end generate ev;
nev:if (widthin>widthout) generate
ad5:if (widthin-widthout>1) generate
lo:for i in 0 to widthin-widthout-2 generate
ADDOFIVE(i) <= '1';
end generate lo;
hi:for i in widthin-widthout-1 to widthin generate
ADDOFIVE(i) <= '0';
end generate hi;
end generate ad5;
adn:if (widthin-widthout=1) generate
hi:for i in 0 to widthin generate
ADDOFIVE(i) <= '0';
end generate hi;
end generate adn;
XINEXT(widthin-1 downto 0) <= xin(widthin-1 downto 0);
XINEXT(widthin) <= xin(widthin-1);
notsigned <= not(XINEXT(widthin-1));
YOUTEXT <= XINEXT + ADDOFIVE + notsigned;
gy:for i in 0 to widthout-1 generate
yout(i) <= YOUTEXT(i+widthin-widthout) ;
end generate gy;
end generate ;
end AROUND_SYNTH;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_AROUND is
generic (
widthin : natural :=8;
widthout : natural :=4
);
port (
xin : in std_logic_vector(widthin-1 downto 0);
yout : out std_logic_vector(widthout-1 downto 0)
);
end alt_dspbuilder_AROUND;
architecture AROUND_SYNTH of alt_dspbuilder_AROUND is
signal ADDOFIVE : std_logic_vector(widthin downto 0) ;
signal XINEXT : std_logic_vector(widthin downto 0) ;
signal YOUTEXT : std_logic_vector(widthin downto 0);
signal notsigned : std_logic :='0';
begin
ev:if widthin=widthout generate
yout <= xin;
end generate ev;
nev:if (widthin>widthout) generate
ad5:if (widthin-widthout>1) generate
lo:for i in 0 to widthin-widthout-2 generate
ADDOFIVE(i) <= '1';
end generate lo;
hi:for i in widthin-widthout-1 to widthin generate
ADDOFIVE(i) <= '0';
end generate hi;
end generate ad5;
adn:if (widthin-widthout=1) generate
hi:for i in 0 to widthin generate
ADDOFIVE(i) <= '0';
end generate hi;
end generate adn;
XINEXT(widthin-1 downto 0) <= xin(widthin-1 downto 0);
XINEXT(widthin) <= xin(widthin-1);
notsigned <= not(XINEXT(widthin-1));
YOUTEXT <= XINEXT + ADDOFIVE + notsigned;
gy:for i in 0 to widthout-1 generate
yout(i) <= YOUTEXT(i+widthin-widthout) ;
end generate gy;
end generate ;
end AROUND_SYNTH;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_AROUND is
generic (
widthin : natural :=8;
widthout : natural :=4
);
port (
xin : in std_logic_vector(widthin-1 downto 0);
yout : out std_logic_vector(widthout-1 downto 0)
);
end alt_dspbuilder_AROUND;
architecture AROUND_SYNTH of alt_dspbuilder_AROUND is
signal ADDOFIVE : std_logic_vector(widthin downto 0) ;
signal XINEXT : std_logic_vector(widthin downto 0) ;
signal YOUTEXT : std_logic_vector(widthin downto 0);
signal notsigned : std_logic :='0';
begin
ev:if widthin=widthout generate
yout <= xin;
end generate ev;
nev:if (widthin>widthout) generate
ad5:if (widthin-widthout>1) generate
lo:for i in 0 to widthin-widthout-2 generate
ADDOFIVE(i) <= '1';
end generate lo;
hi:for i in widthin-widthout-1 to widthin generate
ADDOFIVE(i) <= '0';
end generate hi;
end generate ad5;
adn:if (widthin-widthout=1) generate
hi:for i in 0 to widthin generate
ADDOFIVE(i) <= '0';
end generate hi;
end generate adn;
XINEXT(widthin-1 downto 0) <= xin(widthin-1 downto 0);
XINEXT(widthin) <= xin(widthin-1);
notsigned <= not(XINEXT(widthin-1));
YOUTEXT <= XINEXT + ADDOFIVE + notsigned;
gy:for i in 0 to widthout-1 generate
yout(i) <= YOUTEXT(i+widthin-widthout) ;
end generate gy;
end generate ;
end AROUND_SYNTH;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_AROUND is
generic (
widthin : natural :=8;
widthout : natural :=4
);
port (
xin : in std_logic_vector(widthin-1 downto 0);
yout : out std_logic_vector(widthout-1 downto 0)
);
end alt_dspbuilder_AROUND;
architecture AROUND_SYNTH of alt_dspbuilder_AROUND is
signal ADDOFIVE : std_logic_vector(widthin downto 0) ;
signal XINEXT : std_logic_vector(widthin downto 0) ;
signal YOUTEXT : std_logic_vector(widthin downto 0);
signal notsigned : std_logic :='0';
begin
ev:if widthin=widthout generate
yout <= xin;
end generate ev;
nev:if (widthin>widthout) generate
ad5:if (widthin-widthout>1) generate
lo:for i in 0 to widthin-widthout-2 generate
ADDOFIVE(i) <= '1';
end generate lo;
hi:for i in widthin-widthout-1 to widthin generate
ADDOFIVE(i) <= '0';
end generate hi;
end generate ad5;
adn:if (widthin-widthout=1) generate
hi:for i in 0 to widthin generate
ADDOFIVE(i) <= '0';
end generate hi;
end generate adn;
XINEXT(widthin-1 downto 0) <= xin(widthin-1 downto 0);
XINEXT(widthin) <= xin(widthin-1);
notsigned <= not(XINEXT(widthin-1));
YOUTEXT <= XINEXT + ADDOFIVE + notsigned;
gy:for i in 0 to widthout-1 generate
yout(i) <= YOUTEXT(i+widthin-widthout) ;
end generate gy;
end generate ;
end AROUND_SYNTH;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_AROUND is
generic (
widthin : natural :=8;
widthout : natural :=4
);
port (
xin : in std_logic_vector(widthin-1 downto 0);
yout : out std_logic_vector(widthout-1 downto 0)
);
end alt_dspbuilder_AROUND;
architecture AROUND_SYNTH of alt_dspbuilder_AROUND is
signal ADDOFIVE : std_logic_vector(widthin downto 0) ;
signal XINEXT : std_logic_vector(widthin downto 0) ;
signal YOUTEXT : std_logic_vector(widthin downto 0);
signal notsigned : std_logic :='0';
begin
ev:if widthin=widthout generate
yout <= xin;
end generate ev;
nev:if (widthin>widthout) generate
ad5:if (widthin-widthout>1) generate
lo:for i in 0 to widthin-widthout-2 generate
ADDOFIVE(i) <= '1';
end generate lo;
hi:for i in widthin-widthout-1 to widthin generate
ADDOFIVE(i) <= '0';
end generate hi;
end generate ad5;
adn:if (widthin-widthout=1) generate
hi:for i in 0 to widthin generate
ADDOFIVE(i) <= '0';
end generate hi;
end generate adn;
XINEXT(widthin-1 downto 0) <= xin(widthin-1 downto 0);
XINEXT(widthin) <= xin(widthin-1);
notsigned <= not(XINEXT(widthin-1));
YOUTEXT <= XINEXT + ADDOFIVE + notsigned;
gy:for i in 0 to widthout-1 generate
yout(i) <= YOUTEXT(i+widthin-widthout) ;
end generate gy;
end generate ;
end AROUND_SYNTH;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_AROUND is
generic (
widthin : natural :=8;
widthout : natural :=4
);
port (
xin : in std_logic_vector(widthin-1 downto 0);
yout : out std_logic_vector(widthout-1 downto 0)
);
end alt_dspbuilder_AROUND;
architecture AROUND_SYNTH of alt_dspbuilder_AROUND is
signal ADDOFIVE : std_logic_vector(widthin downto 0) ;
signal XINEXT : std_logic_vector(widthin downto 0) ;
signal YOUTEXT : std_logic_vector(widthin downto 0);
signal notsigned : std_logic :='0';
begin
ev:if widthin=widthout generate
yout <= xin;
end generate ev;
nev:if (widthin>widthout) generate
ad5:if (widthin-widthout>1) generate
lo:for i in 0 to widthin-widthout-2 generate
ADDOFIVE(i) <= '1';
end generate lo;
hi:for i in widthin-widthout-1 to widthin generate
ADDOFIVE(i) <= '0';
end generate hi;
end generate ad5;
adn:if (widthin-widthout=1) generate
hi:for i in 0 to widthin generate
ADDOFIVE(i) <= '0';
end generate hi;
end generate adn;
XINEXT(widthin-1 downto 0) <= xin(widthin-1 downto 0);
XINEXT(widthin) <= xin(widthin-1);
notsigned <= not(XINEXT(widthin-1));
YOUTEXT <= XINEXT + ADDOFIVE + notsigned;
gy:for i in 0 to widthout-1 generate
yout(i) <= YOUTEXT(i+widthin-widthout) ;
end generate gy;
end generate ;
end AROUND_SYNTH;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_AROUND is
generic (
widthin : natural :=8;
widthout : natural :=4
);
port (
xin : in std_logic_vector(widthin-1 downto 0);
yout : out std_logic_vector(widthout-1 downto 0)
);
end alt_dspbuilder_AROUND;
architecture AROUND_SYNTH of alt_dspbuilder_AROUND is
signal ADDOFIVE : std_logic_vector(widthin downto 0) ;
signal XINEXT : std_logic_vector(widthin downto 0) ;
signal YOUTEXT : std_logic_vector(widthin downto 0);
signal notsigned : std_logic :='0';
begin
ev:if widthin=widthout generate
yout <= xin;
end generate ev;
nev:if (widthin>widthout) generate
ad5:if (widthin-widthout>1) generate
lo:for i in 0 to widthin-widthout-2 generate
ADDOFIVE(i) <= '1';
end generate lo;
hi:for i in widthin-widthout-1 to widthin generate
ADDOFIVE(i) <= '0';
end generate hi;
end generate ad5;
adn:if (widthin-widthout=1) generate
hi:for i in 0 to widthin generate
ADDOFIVE(i) <= '0';
end generate hi;
end generate adn;
XINEXT(widthin-1 downto 0) <= xin(widthin-1 downto 0);
XINEXT(widthin) <= xin(widthin-1);
notsigned <= not(XINEXT(widthin-1));
YOUTEXT <= XINEXT + ADDOFIVE + notsigned;
gy:for i in 0 to widthout-1 generate
yout(i) <= YOUTEXT(i+widthin-widthout) ;
end generate gy;
end generate ;
end AROUND_SYNTH;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_AROUND is
generic (
widthin : natural :=8;
widthout : natural :=4
);
port (
xin : in std_logic_vector(widthin-1 downto 0);
yout : out std_logic_vector(widthout-1 downto 0)
);
end alt_dspbuilder_AROUND;
architecture AROUND_SYNTH of alt_dspbuilder_AROUND is
signal ADDOFIVE : std_logic_vector(widthin downto 0) ;
signal XINEXT : std_logic_vector(widthin downto 0) ;
signal YOUTEXT : std_logic_vector(widthin downto 0);
signal notsigned : std_logic :='0';
begin
ev:if widthin=widthout generate
yout <= xin;
end generate ev;
nev:if (widthin>widthout) generate
ad5:if (widthin-widthout>1) generate
lo:for i in 0 to widthin-widthout-2 generate
ADDOFIVE(i) <= '1';
end generate lo;
hi:for i in widthin-widthout-1 to widthin generate
ADDOFIVE(i) <= '0';
end generate hi;
end generate ad5;
adn:if (widthin-widthout=1) generate
hi:for i in 0 to widthin generate
ADDOFIVE(i) <= '0';
end generate hi;
end generate adn;
XINEXT(widthin-1 downto 0) <= xin(widthin-1 downto 0);
XINEXT(widthin) <= xin(widthin-1);
notsigned <= not(XINEXT(widthin-1));
YOUTEXT <= XINEXT + ADDOFIVE + notsigned;
gy:for i in 0 to widthout-1 generate
yout(i) <= YOUTEXT(i+widthin-widthout) ;
end generate gy;
end generate ;
end AROUND_SYNTH;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_AROUND is
generic (
widthin : natural :=8;
widthout : natural :=4
);
port (
xin : in std_logic_vector(widthin-1 downto 0);
yout : out std_logic_vector(widthout-1 downto 0)
);
end alt_dspbuilder_AROUND;
architecture AROUND_SYNTH of alt_dspbuilder_AROUND is
signal ADDOFIVE : std_logic_vector(widthin downto 0) ;
signal XINEXT : std_logic_vector(widthin downto 0) ;
signal YOUTEXT : std_logic_vector(widthin downto 0);
signal notsigned : std_logic :='0';
begin
ev:if widthin=widthout generate
yout <= xin;
end generate ev;
nev:if (widthin>widthout) generate
ad5:if (widthin-widthout>1) generate
lo:for i in 0 to widthin-widthout-2 generate
ADDOFIVE(i) <= '1';
end generate lo;
hi:for i in widthin-widthout-1 to widthin generate
ADDOFIVE(i) <= '0';
end generate hi;
end generate ad5;
adn:if (widthin-widthout=1) generate
hi:for i in 0 to widthin generate
ADDOFIVE(i) <= '0';
end generate hi;
end generate adn;
XINEXT(widthin-1 downto 0) <= xin(widthin-1 downto 0);
XINEXT(widthin) <= xin(widthin-1);
notsigned <= not(XINEXT(widthin-1));
YOUTEXT <= XINEXT + ADDOFIVE + notsigned;
gy:for i in 0 to widthout-1 generate
yout(i) <= YOUTEXT(i+widthin-widthout) ;
end generate gy;
end generate ;
end AROUND_SYNTH;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_AROUND is
generic (
widthin : natural :=8;
widthout : natural :=4
);
port (
xin : in std_logic_vector(widthin-1 downto 0);
yout : out std_logic_vector(widthout-1 downto 0)
);
end alt_dspbuilder_AROUND;
architecture AROUND_SYNTH of alt_dspbuilder_AROUND is
signal ADDOFIVE : std_logic_vector(widthin downto 0) ;
signal XINEXT : std_logic_vector(widthin downto 0) ;
signal YOUTEXT : std_logic_vector(widthin downto 0);
signal notsigned : std_logic :='0';
begin
ev:if widthin=widthout generate
yout <= xin;
end generate ev;
nev:if (widthin>widthout) generate
ad5:if (widthin-widthout>1) generate
lo:for i in 0 to widthin-widthout-2 generate
ADDOFIVE(i) <= '1';
end generate lo;
hi:for i in widthin-widthout-1 to widthin generate
ADDOFIVE(i) <= '0';
end generate hi;
end generate ad5;
adn:if (widthin-widthout=1) generate
hi:for i in 0 to widthin generate
ADDOFIVE(i) <= '0';
end generate hi;
end generate adn;
XINEXT(widthin-1 downto 0) <= xin(widthin-1 downto 0);
XINEXT(widthin) <= xin(widthin-1);
notsigned <= not(XINEXT(widthin-1));
YOUTEXT <= XINEXT + ADDOFIVE + notsigned;
gy:for i in 0 to widthout-1 generate
yout(i) <= YOUTEXT(i+widthin-widthout) ;
end generate gy;
end generate ;
end AROUND_SYNTH;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_AROUND is
generic (
widthin : natural :=8;
widthout : natural :=4
);
port (
xin : in std_logic_vector(widthin-1 downto 0);
yout : out std_logic_vector(widthout-1 downto 0)
);
end alt_dspbuilder_AROUND;
architecture AROUND_SYNTH of alt_dspbuilder_AROUND is
signal ADDOFIVE : std_logic_vector(widthin downto 0) ;
signal XINEXT : std_logic_vector(widthin downto 0) ;
signal YOUTEXT : std_logic_vector(widthin downto 0);
signal notsigned : std_logic :='0';
begin
ev:if widthin=widthout generate
yout <= xin;
end generate ev;
nev:if (widthin>widthout) generate
ad5:if (widthin-widthout>1) generate
lo:for i in 0 to widthin-widthout-2 generate
ADDOFIVE(i) <= '1';
end generate lo;
hi:for i in widthin-widthout-1 to widthin generate
ADDOFIVE(i) <= '0';
end generate hi;
end generate ad5;
adn:if (widthin-widthout=1) generate
hi:for i in 0 to widthin generate
ADDOFIVE(i) <= '0';
end generate hi;
end generate adn;
XINEXT(widthin-1 downto 0) <= xin(widthin-1 downto 0);
XINEXT(widthin) <= xin(widthin-1);
notsigned <= not(XINEXT(widthin-1));
YOUTEXT <= XINEXT + ADDOFIVE + notsigned;
gy:for i in 0 to widthout-1 generate
yout(i) <= YOUTEXT(i+widthin-widthout) ;
end generate gy;
end generate ;
end AROUND_SYNTH;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_AROUND is
generic (
widthin : natural :=8;
widthout : natural :=4
);
port (
xin : in std_logic_vector(widthin-1 downto 0);
yout : out std_logic_vector(widthout-1 downto 0)
);
end alt_dspbuilder_AROUND;
architecture AROUND_SYNTH of alt_dspbuilder_AROUND is
signal ADDOFIVE : std_logic_vector(widthin downto 0) ;
signal XINEXT : std_logic_vector(widthin downto 0) ;
signal YOUTEXT : std_logic_vector(widthin downto 0);
signal notsigned : std_logic :='0';
begin
ev:if widthin=widthout generate
yout <= xin;
end generate ev;
nev:if (widthin>widthout) generate
ad5:if (widthin-widthout>1) generate
lo:for i in 0 to widthin-widthout-2 generate
ADDOFIVE(i) <= '1';
end generate lo;
hi:for i in widthin-widthout-1 to widthin generate
ADDOFIVE(i) <= '0';
end generate hi;
end generate ad5;
adn:if (widthin-widthout=1) generate
hi:for i in 0 to widthin generate
ADDOFIVE(i) <= '0';
end generate hi;
end generate adn;
XINEXT(widthin-1 downto 0) <= xin(widthin-1 downto 0);
XINEXT(widthin) <= xin(widthin-1);
notsigned <= not(XINEXT(widthin-1));
YOUTEXT <= XINEXT + ADDOFIVE + notsigned;
gy:for i in 0 to widthout-1 generate
yout(i) <= YOUTEXT(i+widthin-widthout) ;
end generate gy;
end generate ;
end AROUND_SYNTH;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_AROUND is
generic (
widthin : natural :=8;
widthout : natural :=4
);
port (
xin : in std_logic_vector(widthin-1 downto 0);
yout : out std_logic_vector(widthout-1 downto 0)
);
end alt_dspbuilder_AROUND;
architecture AROUND_SYNTH of alt_dspbuilder_AROUND is
signal ADDOFIVE : std_logic_vector(widthin downto 0) ;
signal XINEXT : std_logic_vector(widthin downto 0) ;
signal YOUTEXT : std_logic_vector(widthin downto 0);
signal notsigned : std_logic :='0';
begin
ev:if widthin=widthout generate
yout <= xin;
end generate ev;
nev:if (widthin>widthout) generate
ad5:if (widthin-widthout>1) generate
lo:for i in 0 to widthin-widthout-2 generate
ADDOFIVE(i) <= '1';
end generate lo;
hi:for i in widthin-widthout-1 to widthin generate
ADDOFIVE(i) <= '0';
end generate hi;
end generate ad5;
adn:if (widthin-widthout=1) generate
hi:for i in 0 to widthin generate
ADDOFIVE(i) <= '0';
end generate hi;
end generate adn;
XINEXT(widthin-1 downto 0) <= xin(widthin-1 downto 0);
XINEXT(widthin) <= xin(widthin-1);
notsigned <= not(XINEXT(widthin-1));
YOUTEXT <= XINEXT + ADDOFIVE + notsigned;
gy:for i in 0 to widthout-1 generate
yout(i) <= YOUTEXT(i+widthin-widthout) ;
end generate gy;
end generate ;
end AROUND_SYNTH;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_AROUND is
generic (
widthin : natural :=8;
widthout : natural :=4
);
port (
xin : in std_logic_vector(widthin-1 downto 0);
yout : out std_logic_vector(widthout-1 downto 0)
);
end alt_dspbuilder_AROUND;
architecture AROUND_SYNTH of alt_dspbuilder_AROUND is
signal ADDOFIVE : std_logic_vector(widthin downto 0) ;
signal XINEXT : std_logic_vector(widthin downto 0) ;
signal YOUTEXT : std_logic_vector(widthin downto 0);
signal notsigned : std_logic :='0';
begin
ev:if widthin=widthout generate
yout <= xin;
end generate ev;
nev:if (widthin>widthout) generate
ad5:if (widthin-widthout>1) generate
lo:for i in 0 to widthin-widthout-2 generate
ADDOFIVE(i) <= '1';
end generate lo;
hi:for i in widthin-widthout-1 to widthin generate
ADDOFIVE(i) <= '0';
end generate hi;
end generate ad5;
adn:if (widthin-widthout=1) generate
hi:for i in 0 to widthin generate
ADDOFIVE(i) <= '0';
end generate hi;
end generate adn;
XINEXT(widthin-1 downto 0) <= xin(widthin-1 downto 0);
XINEXT(widthin) <= xin(widthin-1);
notsigned <= not(XINEXT(widthin-1));
YOUTEXT <= XINEXT + ADDOFIVE + notsigned;
gy:for i in 0 to widthout-1 generate
yout(i) <= YOUTEXT(i+widthin-widthout) ;
end generate gy;
end generate ;
end AROUND_SYNTH;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_AROUND is
generic (
widthin : natural :=8;
widthout : natural :=4
);
port (
xin : in std_logic_vector(widthin-1 downto 0);
yout : out std_logic_vector(widthout-1 downto 0)
);
end alt_dspbuilder_AROUND;
architecture AROUND_SYNTH of alt_dspbuilder_AROUND is
signal ADDOFIVE : std_logic_vector(widthin downto 0) ;
signal XINEXT : std_logic_vector(widthin downto 0) ;
signal YOUTEXT : std_logic_vector(widthin downto 0);
signal notsigned : std_logic :='0';
begin
ev:if widthin=widthout generate
yout <= xin;
end generate ev;
nev:if (widthin>widthout) generate
ad5:if (widthin-widthout>1) generate
lo:for i in 0 to widthin-widthout-2 generate
ADDOFIVE(i) <= '1';
end generate lo;
hi:for i in widthin-widthout-1 to widthin generate
ADDOFIVE(i) <= '0';
end generate hi;
end generate ad5;
adn:if (widthin-widthout=1) generate
hi:for i in 0 to widthin generate
ADDOFIVE(i) <= '0';
end generate hi;
end generate adn;
XINEXT(widthin-1 downto 0) <= xin(widthin-1 downto 0);
XINEXT(widthin) <= xin(widthin-1);
notsigned <= not(XINEXT(widthin-1));
YOUTEXT <= XINEXT + ADDOFIVE + notsigned;
gy:for i in 0 to widthout-1 generate
yout(i) <= YOUTEXT(i+widthin-widthout) ;
end generate gy;
end generate ;
end AROUND_SYNTH;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_AROUND is
generic (
widthin : natural :=8;
widthout : natural :=4
);
port (
xin : in std_logic_vector(widthin-1 downto 0);
yout : out std_logic_vector(widthout-1 downto 0)
);
end alt_dspbuilder_AROUND;
architecture AROUND_SYNTH of alt_dspbuilder_AROUND is
signal ADDOFIVE : std_logic_vector(widthin downto 0) ;
signal XINEXT : std_logic_vector(widthin downto 0) ;
signal YOUTEXT : std_logic_vector(widthin downto 0);
signal notsigned : std_logic :='0';
begin
ev:if widthin=widthout generate
yout <= xin;
end generate ev;
nev:if (widthin>widthout) generate
ad5:if (widthin-widthout>1) generate
lo:for i in 0 to widthin-widthout-2 generate
ADDOFIVE(i) <= '1';
end generate lo;
hi:for i in widthin-widthout-1 to widthin generate
ADDOFIVE(i) <= '0';
end generate hi;
end generate ad5;
adn:if (widthin-widthout=1) generate
hi:for i in 0 to widthin generate
ADDOFIVE(i) <= '0';
end generate hi;
end generate adn;
XINEXT(widthin-1 downto 0) <= xin(widthin-1 downto 0);
XINEXT(widthin) <= xin(widthin-1);
notsigned <= not(XINEXT(widthin-1));
YOUTEXT <= XINEXT + ADDOFIVE + notsigned;
gy:for i in 0 to widthout-1 generate
yout(i) <= YOUTEXT(i+widthin-widthout) ;
end generate gy;
end generate ;
end AROUND_SYNTH;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_AROUND is
generic (
widthin : natural :=8;
widthout : natural :=4
);
port (
xin : in std_logic_vector(widthin-1 downto 0);
yout : out std_logic_vector(widthout-1 downto 0)
);
end alt_dspbuilder_AROUND;
architecture AROUND_SYNTH of alt_dspbuilder_AROUND is
signal ADDOFIVE : std_logic_vector(widthin downto 0) ;
signal XINEXT : std_logic_vector(widthin downto 0) ;
signal YOUTEXT : std_logic_vector(widthin downto 0);
signal notsigned : std_logic :='0';
begin
ev:if widthin=widthout generate
yout <= xin;
end generate ev;
nev:if (widthin>widthout) generate
ad5:if (widthin-widthout>1) generate
lo:for i in 0 to widthin-widthout-2 generate
ADDOFIVE(i) <= '1';
end generate lo;
hi:for i in widthin-widthout-1 to widthin generate
ADDOFIVE(i) <= '0';
end generate hi;
end generate ad5;
adn:if (widthin-widthout=1) generate
hi:for i in 0 to widthin generate
ADDOFIVE(i) <= '0';
end generate hi;
end generate adn;
XINEXT(widthin-1 downto 0) <= xin(widthin-1 downto 0);
XINEXT(widthin) <= xin(widthin-1);
notsigned <= not(XINEXT(widthin-1));
YOUTEXT <= XINEXT + ADDOFIVE + notsigned;
gy:for i in 0 to widthout-1 generate
yout(i) <= YOUTEXT(i+widthin-widthout) ;
end generate gy;
end generate ;
end AROUND_SYNTH;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_AROUND is
generic (
widthin : natural :=8;
widthout : natural :=4
);
port (
xin : in std_logic_vector(widthin-1 downto 0);
yout : out std_logic_vector(widthout-1 downto 0)
);
end alt_dspbuilder_AROUND;
architecture AROUND_SYNTH of alt_dspbuilder_AROUND is
signal ADDOFIVE : std_logic_vector(widthin downto 0) ;
signal XINEXT : std_logic_vector(widthin downto 0) ;
signal YOUTEXT : std_logic_vector(widthin downto 0);
signal notsigned : std_logic :='0';
begin
ev:if widthin=widthout generate
yout <= xin;
end generate ev;
nev:if (widthin>widthout) generate
ad5:if (widthin-widthout>1) generate
lo:for i in 0 to widthin-widthout-2 generate
ADDOFIVE(i) <= '1';
end generate lo;
hi:for i in widthin-widthout-1 to widthin generate
ADDOFIVE(i) <= '0';
end generate hi;
end generate ad5;
adn:if (widthin-widthout=1) generate
hi:for i in 0 to widthin generate
ADDOFIVE(i) <= '0';
end generate hi;
end generate adn;
XINEXT(widthin-1 downto 0) <= xin(widthin-1 downto 0);
XINEXT(widthin) <= xin(widthin-1);
notsigned <= not(XINEXT(widthin-1));
YOUTEXT <= XINEXT + ADDOFIVE + notsigned;
gy:for i in 0 to widthout-1 generate
yout(i) <= YOUTEXT(i+widthin-widthout) ;
end generate gy;
end generate ;
end AROUND_SYNTH;
|
--------------------------------------------------------------------------------------------
-- DSP Builder (Version 9.1)
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera
-- Corporation's design tools, logic functions and other software and tools, and its
-- AMPP partner logic functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any associated
-- documentation or information are expressly subject to the terms and conditions
-- of the Altera Program License Subscription Agreement, Altera MegaCore Function
-- License Agreement, or other applicable license agreement, including, without
-- limitation, that your use is for the sole purpose of programming logic devices
-- manufactured by Altera and sold by Altera or its authorized distributors.
-- Please refer to the applicable agreement for further details.
--------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
library altera;
use altera.alt_dspbuilder_package.all;
entity alt_dspbuilder_AROUND is
generic (
widthin : natural :=8;
widthout : natural :=4
);
port (
xin : in std_logic_vector(widthin-1 downto 0);
yout : out std_logic_vector(widthout-1 downto 0)
);
end alt_dspbuilder_AROUND;
architecture AROUND_SYNTH of alt_dspbuilder_AROUND is
signal ADDOFIVE : std_logic_vector(widthin downto 0) ;
signal XINEXT : std_logic_vector(widthin downto 0) ;
signal YOUTEXT : std_logic_vector(widthin downto 0);
signal notsigned : std_logic :='0';
begin
ev:if widthin=widthout generate
yout <= xin;
end generate ev;
nev:if (widthin>widthout) generate
ad5:if (widthin-widthout>1) generate
lo:for i in 0 to widthin-widthout-2 generate
ADDOFIVE(i) <= '1';
end generate lo;
hi:for i in widthin-widthout-1 to widthin generate
ADDOFIVE(i) <= '0';
end generate hi;
end generate ad5;
adn:if (widthin-widthout=1) generate
hi:for i in 0 to widthin generate
ADDOFIVE(i) <= '0';
end generate hi;
end generate adn;
XINEXT(widthin-1 downto 0) <= xin(widthin-1 downto 0);
XINEXT(widthin) <= xin(widthin-1);
notsigned <= not(XINEXT(widthin-1));
YOUTEXT <= XINEXT + ADDOFIVE + notsigned;
gy:for i in 0 to widthout-1 generate
yout(i) <= YOUTEXT(i+widthin-widthout) ;
end generate gy;
end generate ;
end AROUND_SYNTH;
|
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|
`protect begin_protected
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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|
`protect begin_protected
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5184)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_block
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`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5184)
`protect data_block
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E6riudccfkrAQsWlNSfg95qEVD6KrnQN/7eHoxbWoz0bChoSCoFrmYKiE2K2cRdkpVxNVC6R
`protect end_protected
|
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
-- Date : Tue Sep 17 19:44:45 2019
-- Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ gcd_zynq_snick_processing_system7_0_0_stub.vhdl
-- Design : gcd_zynq_snick_processing_system7_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg400-3
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
GPIO_I : in STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_O : out STD_LOGIC_VECTOR ( 63 downto 0 );
GPIO_T : out STD_LOGIC_VECTOR ( 63 downto 0 );
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_CLK1 : out STD_LOGIC;
FCLK_CLK2 : out STD_LOGIC;
FCLK_CLK3 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
FCLK_RESET1_N : out STD_LOGIC;
FCLK_RESET2_N : out STD_LOGIC;
FCLK_RESET3_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "GPIO_I[63:0],GPIO_O[63:0],GPIO_T[63:0],M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],IRQ_F2P[0:0],FCLK_CLK0,FCLK_CLK1,FCLK_CLK2,FCLK_CLK3,FCLK_RESET0_N,FCLK_RESET1_N,FCLK_RESET2_N,FCLK_RESET3_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "processing_system7_v5_5_processing_system7,Vivado 2018.2";
begin
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1143.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p05n02i01143ent IS
END c06s05b00x00p05n02i01143ent;
ARCHITECTURE c06s05b00x00p05n02i01143arch OF c06s05b00x00p05n02i01143ent IS
BEGIN
TESTING: PROCESS
type B is array ( INTEGER range <> ) of BOOLEAN;
subtype B1 is B(1 to 6) ;
subtype B2 is B(6 downto 1) ;
variable V3: B1 ;
variable V4: B2 ;
BEGIN
V3(2 to 4) := V3(4 downto 2);
--ERROR: discrete range descending when the prefix
--type was declared with a ascending range results in a null
--slice, which is incompatible with non-null slice
assert FALSE
report "***FAILED TEST: c06s05b00x00p05n02i01143 - Null slice is not compatible with non-null slice."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p05n02i01143arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1143.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p05n02i01143ent IS
END c06s05b00x00p05n02i01143ent;
ARCHITECTURE c06s05b00x00p05n02i01143arch OF c06s05b00x00p05n02i01143ent IS
BEGIN
TESTING: PROCESS
type B is array ( INTEGER range <> ) of BOOLEAN;
subtype B1 is B(1 to 6) ;
subtype B2 is B(6 downto 1) ;
variable V3: B1 ;
variable V4: B2 ;
BEGIN
V3(2 to 4) := V3(4 downto 2);
--ERROR: discrete range descending when the prefix
--type was declared with a ascending range results in a null
--slice, which is incompatible with non-null slice
assert FALSE
report "***FAILED TEST: c06s05b00x00p05n02i01143 - Null slice is not compatible with non-null slice."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p05n02i01143arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1143.vhd,v 1.2 2001-10-26 16:30:06 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p05n02i01143ent IS
END c06s05b00x00p05n02i01143ent;
ARCHITECTURE c06s05b00x00p05n02i01143arch OF c06s05b00x00p05n02i01143ent IS
BEGIN
TESTING: PROCESS
type B is array ( INTEGER range <> ) of BOOLEAN;
subtype B1 is B(1 to 6) ;
subtype B2 is B(6 downto 1) ;
variable V3: B1 ;
variable V4: B2 ;
BEGIN
V3(2 to 4) := V3(4 downto 2);
--ERROR: discrete range descending when the prefix
--type was declared with a ascending range results in a null
--slice, which is incompatible with non-null slice
assert FALSE
report "***FAILED TEST: c06s05b00x00p05n02i01143 - Null slice is not compatible with non-null slice."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p05n02i01143arch;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_gpio:2.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_gpio_v2_0;
USE axi_gpio_v2_0.axi_gpio;
ENTITY design_1_axi_gpio_0_0 IS
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END design_1_axi_gpio_0_0;
ARCHITECTURE design_1_axi_gpio_0_0_arch OF design_1_axi_gpio_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_axi_gpio_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_gpio IS
GENERIC (
C_FAMILY : STRING;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_GPIO_WIDTH : INTEGER;
C_GPIO2_WIDTH : INTEGER;
C_ALL_INPUTS : INTEGER;
C_ALL_INPUTS_2 : INTEGER;
C_ALL_OUTPUTS : INTEGER;
C_ALL_OUTPUTS_2 : INTEGER;
C_INTERRUPT_PRESENT : INTEGER;
C_DOUT_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_IS_DUAL : INTEGER;
C_DOUT_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
C_TRI_DEFAULT_2 : STD_LOGIC_VECTOR(31 DOWNTO 0)
);
PORT (
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC;
gpio_io_i : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio_io_o : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio_io_t : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
gpio2_io_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_o : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
gpio2_io_t : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT axi_gpio;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 S_AXI_ARESETN RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 S_AXI RREADY";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_i: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_I";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_o: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_O";
ATTRIBUTE X_INTERFACE_INFO OF gpio_io_t: SIGNAL IS "xilinx.com:interface:gpio:1.0 GPIO TRI_T";
BEGIN
U0 : axi_gpio
GENERIC MAP (
C_FAMILY => "zynq",
C_S_AXI_ADDR_WIDTH => 9,
C_S_AXI_DATA_WIDTH => 32,
C_GPIO_WIDTH => 8,
C_GPIO2_WIDTH => 32,
C_ALL_INPUTS => 0,
C_ALL_INPUTS_2 => 0,
C_ALL_OUTPUTS => 0,
C_ALL_OUTPUTS_2 => 0,
C_INTERRUPT_PRESENT => 0,
C_DOUT_DEFAULT => X"00000000",
C_TRI_DEFAULT => X"FFFFFFFF",
C_IS_DUAL => 0,
C_DOUT_DEFAULT_2 => X"00000000",
C_TRI_DEFAULT_2 => X"FFFFFFFF"
)
PORT MAP (
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
gpio_io_i => gpio_io_i,
gpio_io_o => gpio_io_o,
gpio_io_t => gpio_io_t,
gpio2_io_i => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32))
);
END design_1_axi_gpio_0_0_arch;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: dsu
-- File: dsu.vhd
-- Author: Jiri Gaisler, Edvin Catovic - Aeroflex Gaisler AB
-- Description: Combined LEON3 debug support with AHB trace unit
-- connected on separate bus.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.leon3.all;
library techmap;
use techmap.gencomp.all;
entity dsu3_mb is
generic (
hindex : integer := 0;
haddr : integer := 16#900#;
hmask : integer := 16#f00#;
ncpu : integer := 1;
tbits : integer := 30; -- timer bits (instruction trace time tag)
tech : integer := DEFMEMTECH;
irq : integer := 0;
kbytes : integer := 0;
testen : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
tahbsi : in ahb_slv_in_type;
dbgi : in l3_debug_out_vector(0 to NCPU-1);
dbgo : out l3_debug_in_vector(0 to NCPU-1);
dsui : in dsu_in_type;
dsuo : out dsu_out_type
);
end;
architecture rtl of dsu3_mb is
signal gnd, vcc : std_ulogic;
begin
gnd <= '0'; vcc <= '1';
x0 : dsu3x generic map (hindex, haddr, hmask, ncpu, tbits, tech, irq, kbytes, 0, testen)
port map (rst, gnd, clk, ahbmi, ahbsi, ahbso, tahbsi, dbgi, dbgo, dsui, dsuo, vcc);
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1820.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01820ent IS
type small_int is range 0 to 7;
type byte is range 0 to 3;
END c07s01b00x00p08n01i01820ent;
ARCHITECTURE c07s01b00x00p08n01i01820arch OF c07s01b00x00p08n01i01820ent IS
function test return small_int is
variable tmp : small_int := 0;
begin
case small_int is -- type name illegal here
when 0 => tmp := 0;
when others => tmp := 1;
end case;
return tmp;
end test;
signal s_int : small_int := 0;
BEGIN
TESTING : PROCESS
BEGIN
s_int <= test after 5 ns;
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01820 - Type names are not permitted as primaries in a case expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01820arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1820.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01820ent IS
type small_int is range 0 to 7;
type byte is range 0 to 3;
END c07s01b00x00p08n01i01820ent;
ARCHITECTURE c07s01b00x00p08n01i01820arch OF c07s01b00x00p08n01i01820ent IS
function test return small_int is
variable tmp : small_int := 0;
begin
case small_int is -- type name illegal here
when 0 => tmp := 0;
when others => tmp := 1;
end case;
return tmp;
end test;
signal s_int : small_int := 0;
BEGIN
TESTING : PROCESS
BEGIN
s_int <= test after 5 ns;
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01820 - Type names are not permitted as primaries in a case expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01820arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1820.vhd,v 1.2 2001-10-26 16:30:13 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01820ent IS
type small_int is range 0 to 7;
type byte is range 0 to 3;
END c07s01b00x00p08n01i01820ent;
ARCHITECTURE c07s01b00x00p08n01i01820arch OF c07s01b00x00p08n01i01820ent IS
function test return small_int is
variable tmp : small_int := 0;
begin
case small_int is -- type name illegal here
when 0 => tmp := 0;
when others => tmp := 1;
end case;
return tmp;
end test;
signal s_int : small_int := 0;
BEGIN
TESTING : PROCESS
BEGIN
s_int <= test after 5 ns;
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01820 - Type names are not permitted as primaries in a case expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01820arch;
|
-- Test generic clause
package PACK1 is
generic (
-- Test constants
constant con1, con2 : in std_logic := 0;
constant con1, con2 : std_logic := 0;
constant con1, con2 : in std_logic;
constant con1, con2 : std_logic;
-- Test signals
signal sig1, sig2 : in std_logic bus := 0;
signal sig1, sig2 : out std_logic bus := 0;
signal sig1, sig2 : inout std_logic bus := 0;
signal sig1, sig2 : buffer std_logic bus := 0;
signal sig1, sig2 : linkage std_logic bus := 0;
signal sig1, sig2 : in std_logic bus;
signal sig1, sig2 : out std_logic bus;
signal sig1, sig2 : inout std_logic bus;
signal sig1, sig2 : buffer std_logic bus;
signal sig1, sig2 : linkage std_logic bus;
signal sig1, sig2 : std_logic bus := 0;
signal sig1, sig2 : std_logic bus := 0;
signal sig1, sig2 : std_logic bus := 0;
signal sig1, sig2 : std_logic bus := 0;
signal sig1, sig2 : std_logic bus := 0;
signal sig1, sig2 : std_logic := 0;
signal sig1, sig2 : std_logic := 0;
signal sig1, sig2 : std_logic := 0;
signal sig1, sig2 : std_logic := 0;
signal sig1, sig2 : std_logic := 0;
signal sig1, sig2 : std_logic;
signal sig1, sig2 : std_logic;
signal sig1, sig2 : std_logic;
signal sig1, sig2 : std_logic;
signal sig1, sig2 : std_logic;
-- Test signals
variable sig1, sig2 : in std_logic := 0;
variable sig1, sig2 : out std_logic := 0;
variable sig1, sig2 : inout std_logic := 0;
variable sig1, sig2 : buffer std_logic := 0;
variable sig1, sig2 : linkage std_logic := 0;
variable sig1, sig2 : in std_logic ;
variable sig1, sig2 : out std_logic ;
variable sig1, sig2 : inout std_logic ;
variable sig1, sig2 : buffer std_logic ;
variable sig1, sig2 : linkage std_logic ;
variable sig1, sig2 : std_logic := 0;
variable sig1, sig2 : std_logic := 0;
variable sig1, sig2 : std_logic := 0;
variable sig1, sig2 : std_logic := 0;
variable sig1, sig2 : std_logic := 0;
variable sig1, sig2 : std_logic;
variable sig1, sig2 : std_logic;
variable sig1, sig2 : std_logic;
variable sig1, sig2 : std_logic;
variable sig1, sig2 : std_logic;
-- Test unknown
sig1, sig2 : in std_logic bus := 0;
sig1, sig2 : out std_logic bus := 0;
sig1, sig2 : inout std_logic bus := 0;
sig1, sig2 : buffer std_logic bus := 0;
sig1, sig2 : linkage std_logic bus := 0;
sig1, sig2 : in std_logic bus;
sig1, sig2 : out std_logic bus;
sig1, sig2 : inout std_logic bus;
sig1, sig2 : buffer std_logic bus;
sig1, sig2 : linkage std_logic bus;
sig1, sig2 : std_logic bus := 0;
sig1, sig2 : std_logic bus := 0;
sig1, sig2 : std_logic bus := 0;
sig1, sig2 : std_logic bus := 0;
sig1, sig2 : std_logic bus := 0;
sig1, sig2 : std_logic := 0;
sig1, sig2 : std_logic := 0;
sig1, sig2 : std_logic := 0;
sig1, sig2 : std_logic := 0;
sig1, sig2 : std_logic := 0;
sig1, sig2 : std_logic;
sig1, sig2 : std_logic;
sig1, sig2 : std_logic;
sig1, sig2 : std_logic;
sig1, sig2 : std_logic;
-- Test files
file fil1, fil2 : std_logic;
file fil1, fil2 : std_logic;
-- Test Types
type typ1;
type typ1;
-- Test Procedures
procedure proc1 parameter (
signal sig1, sig2 : in std_logic bus := 0;
constant con1, con2 : in std_logic := 0;
variable sig1, sig2 : in std_logic := 0;
sig1, sig2 : in std_logic bus := 0;
file fil1, fil2 : std_logic;
type typ1) is proc_name;
procedure proc1 parameter (
signal sig1, sig2 : in std_logic bus := 0;
constant con1, con2 : in std_logic := 0;
variable sig1, sig2 : in std_logic := 0;
sig1, sig2 : in std_logic bus := 0;
file fil1, fil2 : std_logic;
type typ1) is <>;
procedure proc1 (
signal sig1, sig2 : in std_logic bus := 0;
constant con1, con2 : in std_logic := 0;
variable sig1, sig2 : in std_logic := 0;
sig1, sig2 : in std_logic bus := 0;
file fil1, fil2 : std_logic;
type typ1) is proc_name;
procedure proc1 (
signal sig1, sig2 : in std_logic bus := 0;
constant con1, con2 : in std_logic := 0;
variable sig1, sig2 : in std_logic := 0;
sig1, sig2 : in std_logic bus := 0;
file fil1, fil2 : std_logic;
type typ1) is <>;
procedure proc1 is proc_name;
procedure proc1 is <>;
procedure proc1;
-- Test functions
pure function funct1 parameter (
signal sig1, sig2 : in std_logic bus := 0;
constant con1, con2 : in std_logic := 0;
variable sig1, sig2 : in std_logic := 0;
sig1, sig2 : in std_logic bus := 0;
file fil1, fil2 : std_logic;
type typ1) return boolean is <>;
pure function funct1 parameter (
signal sig1, sig2 : in std_logic bus := 0;
constant con1, con2 : in std_logic := 0;
variable sig1, sig2 : in std_logic := 0;
sig1, sig2 : in std_logic bus := 0;
file fil1, fil2 : std_logic;
type typ1) return boolean is func1;
impure function funct1 parameter (
signal sig1, sig2 : in std_logic bus := 0;
constant con1, con2 : in std_logic := 0;
variable sig1, sig2 : in std_logic := 0;
sig1, sig2 : in std_logic bus := 0;
file fil1, fil2 : std_logic;
type typ1) return boolean is <>;
impure function funct1 parameter (
signal sig1, sig2 : in std_logic bus := 0;
constant con1, con2 : in std_logic := 0;
variable sig1, sig2 : in std_logic := 0;
sig1, sig2 : in std_logic bus := 0;
file fil1, fil2 : std_logic;
type typ1) return boolean is func1;
-- Remove Parameter
pure function funct1 (
signal sig1, sig2 : in std_logic bus := 0;
constant con1, con2 : in std_logic := 0;
variable sig1, sig2 : in std_logic := 0;
sig1, sig2 : in std_logic bus := 0;
file fil1, fil2 : std_logic;
type typ1) return boolean is <>;
pure function funct1 (
signal sig1, sig2 : in std_logic bus := 0;
constant con1, con2 : in std_logic := 0;
variable sig1, sig2 : in std_logic := 0;
sig1, sig2 : in std_logic bus := 0;
file fil1, fil2 : std_logic;
type typ1) return boolean is func1;
impure function funct1 (
signal sig1, sig2 : in std_logic bus := 0;
constant con1, con2 : in std_logic := 0;
variable sig1, sig2 : in std_logic := 0;
sig1, sig2 : in std_logic bus := 0;
file fil1, fil2 : std_logic;
type typ1) return boolean is <>;
impure function funct1 (
signal sig1, sig2 : in std_logic bus := 0;
constant con1, con2 : in std_logic := 0;
variable sig1, sig2 : in std_logic := 0;
sig1, sig2 : in std_logic bus := 0;
file fil1, fil2 : std_logic;
type typ1) return boolean is func1;
-- Remove formal_parameter_list
pure function funct1 return boolean is <>;
pure function funct1 return boolean is func1;
impure function funct1 return boolean is <>;
impure function funct1 return boolean is func1;
-- Remove interface_subprogram_default
pure function funct1 return boolean;
pure function funct1 return boolean;
impure function funct1 return boolean;
impure function funct1 return boolean
);
generic map (
A => B,
C => D,
E, F
);
end package PACK1;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Syma_Ctrl_core_v1_1_S_AXI_INTR is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 5;
-- Number of Interrupts
C_NUM_OF_INTR : integer := 1;
-- Each bit corresponds to Sensitivity of interrupt : 0 - EDGE, 1 - LEVEL
C_INTR_SENSITIVITY : std_logic_vector := x"FFFFFFFF";
-- Each bit corresponds to Sub-type of INTR: [0 - FALLING_EDGE, 1 - RISING_EDGE : if C_INTR_SENSITIVITY is EDGE(0)] and [ 0 - LEVEL_LOW, 1 - LEVEL_LOW : if C_INTR_SENSITIVITY is LEVEL(1) ]
C_INTR_ACTIVE_STATE : std_logic_vector := x"FFFFFFFF";
-- Sensitivity of IRQ: 0 - EDGE, 1 - LEVEL
C_IRQ_SENSITIVITY : integer := 1;
-- Sub-type of IRQ: [0 - FALLING_EDGE, 1 - RISING_EDGE : if C_IRQ_SENSITIVITY is EDGE(0)] and [ 0 - LEVEL_LOW, 1 - LEVEL_LOW : if C_IRQ_SENSITIVITY is LEVEL(1) ]
C_IRQ_ACTIVE_STATE : integer := 1
);
port (
-- Users to add ports here
-- User ports ends
-- Do not modify the ports beyond this line
-- Global Clock Signal
S_AXI_ACLK : in std_logic;
-- Global Reset Signal. This Signal is Active LOW
S_AXI_ARESETN : in std_logic;
-- Write address (issued by master, acceped by Slave)
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Write channel Protection type. This signal indicates the
-- privilege and security level of the transaction, and whether
-- the transaction is a data access or an instruction access.
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
-- Write address valid. This signal indicates that the master signaling
-- valid write address and control information.
S_AXI_AWVALID : in std_logic;
-- Write address ready. This signal indicates that the slave is ready
-- to accept an address and associated control signals.
S_AXI_AWREADY : out std_logic;
-- Write data (issued by master, acceped by Slave)
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Write strobes. This signal indicates which byte lanes hold
-- valid data. There is one write strobe bit for each eight
-- bits of the write data bus.
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
-- Write valid. This signal indicates that valid write
-- data and strobes are available.
S_AXI_WVALID : in std_logic;
-- Write ready. This signal indicates that the slave
-- can accept the write data.
S_AXI_WREADY : out std_logic;
-- Write response. This signal indicates the status
-- of the write transaction.
S_AXI_BRESP : out std_logic_vector(1 downto 0);
-- Write response valid. This signal indicates that the channel
-- is signaling a valid write response.
S_AXI_BVALID : out std_logic;
-- Response ready. This signal indicates that the master
-- can accept a write response.
S_AXI_BREADY : in std_logic;
-- Read address (issued by master, acceped by Slave)
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
-- Protection type. This signal indicates the privilege
-- and security level of the transaction, and whether the
-- transaction is a data access or an instruction access.
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
-- Read address valid. This signal indicates that the channel
-- is signaling valid read address and control information.
S_AXI_ARVALID : in std_logic;
-- Read address ready. This signal indicates that the slave is
-- ready to accept an address and associated control signals.
S_AXI_ARREADY : out std_logic;
-- Read data (issued by slave)
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
-- Read response. This signal indicates the status of the
-- read transfer.
S_AXI_RRESP : out std_logic_vector(1 downto 0);
-- Read valid. This signal indicates that the channel is
-- signaling the required read data.
S_AXI_RVALID : out std_logic;
-- Read ready. This signal indicates that the master can
-- accept the read data and response information.
S_AXI_RREADY : in std_logic;
-- interrupt out port
irq : out std_logic
);
end Syma_Ctrl_core_v1_1_S_AXI_INTR;
architecture arch_imp of Syma_Ctrl_core_v1_1_S_AXI_INTR is
-- AXI4LITE signals
signal axi_awaddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_awready : std_logic;
signal axi_wready : std_logic;
signal axi_bresp : std_logic_vector(1 downto 0);
signal axi_bvalid : std_logic;
signal axi_araddr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal axi_arready : std_logic;
signal axi_rdata : std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal axi_rresp : std_logic_vector(1 downto 0);
signal axi_rvalid : std_logic;
--------------------------------------------------
---- Signals for Interrupt register space
--------------------------------------------------
---- Number of Slave Registers 5
signal reg_global_intr_en :std_logic_vector(0 downto 0);
signal reg_intr_en :std_logic_vector(C_NUM_OF_INTR-1 downto 0);
signal reg_intr_sts :std_logic_vector(C_NUM_OF_INTR-1 downto 0);
signal reg_intr_ack :std_logic_vector(C_NUM_OF_INTR-1 downto 0);
signal reg_intr_pending :std_logic_vector(C_NUM_OF_INTR-1 downto 0);
signal intr_reg_rden :std_logic;
signal intr_reg_wren :std_logic;
signal reg_data_out :std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
signal intr : std_logic;
signal s_irq : std_logic;
signal intr_all_ff : std_logic;
signal s_irq_lvl_ff:std_logic;
begin
-- I/O Connections assignments
S_AXI_AWREADY <= axi_awready;
S_AXI_WREADY <= axi_wready;
S_AXI_BRESP <= axi_bresp;
S_AXI_BVALID <= axi_bvalid;
S_AXI_ARREADY <= axi_arready;
S_AXI_RDATA <= axi_rdata;
S_AXI_RRESP <= axi_rresp;
S_AXI_RVALID <= axi_rvalid;
-- Implement axi_awready generation
-- axi_awready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awready <= '0';
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- slave is ready to accept write address when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_awready <= '1';
else
axi_awready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_awaddr latching
-- This process is used to latch the address when both
-- S_AXI_AWVALID and S_AXI_WVALID are valid.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_awaddr <= (others => '0');
else
if (axi_awready = '0' and S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
-- Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end if;
end if;
end if;
end process;
-- Implement axi_wready generation
-- axi_wready is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
-- de-asserted when reset is low.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_wready <= '0';
else
if (axi_wready = '0' and S_AXI_WVALID = '1' and S_AXI_AWVALID = '1') then
-- slave is ready to accept write data when
-- there is a valid write address and write data
-- on the write address and data bus. This design
-- expects no outstanding transactions.
axi_wready <= '1';
else
axi_wready <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and write logic generation
-- The write data is accepted and written to memory mapped registers when
-- axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
-- select byte enables of slave registers while writing.
-- These registers are cleared when reset (active low) is applied.
-- Slave register write enable is asserted when valid address and data are available
-- and the slave is ready to accept the write address and write data.
intr_reg_wren <= axi_wready and S_AXI_WVALID and axi_awready and S_AXI_AWVAintrLID ;
gen_intr_reg : for i in 0 to (C_NUM_OF_INTR - 1) generate
begin
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
reg_global_intr_en <= (others => '0');
else
if (intr_reg_wren = '1' and axi_awaddr(4 downto 2) = "000") then
reg_global_intr_en(0) <= S_AXI_WDATA(0);
end if;
end if;
end if;
end process;
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
reg_intr_en(i) <= '0';
else
if (intr_reg_wren = '1' and axi_awaddr(4 downto 2) = "001") then
reg_intr_en(i) <= S_AXI_WDATA(i);
end if;
end if;
end if;
end process;
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if (S_AXI_ARESETN = '0' or reg_intr_ack(i) = '1') then
reg_intr_sts(i) <= '0';
else
reg_intr_sts(i) <= det_intr(i);
end if;
end if;
end process;
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if (S_AXI_ARESETN = '0' or reg_intr_ack(i) = '1') then
reg_intr_ack(i) <= '0';
else
if (intr_reg_wren = '1' and axi_awaddr(4 downto 2) = "011") then
reg_intr_ack(i) <= S_AXI_WDATA(i);
end if;
end if;
end if;
end process;
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if (S_AXI_ARESETN = '0' or reg_intr_ack(i) = '1') then
reg_intr_pending(i) <= '0';
else
reg_intr_pending(i) <= reg_intr_sts(i) and reg_intr_en(i);
end if;
end if;
end process;
end generate gen_intr_reg;
-- Implement write response logic generation
-- The write response and response valid signals are asserted by the slave
-- when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
-- This marks the acceptance of address and indicates the status of
-- write transaction.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_bvalid <= '0';
axi_bresp <= "00"; --need to work more on the responses
else
if (axi_awready = '1' and S_AXI_AWVALID = '1' and axi_wready = '1' and S_AXI_WVALID = '1' and axi_bvalid = '0' ) then
axi_bvalid <= '1';
axi_bresp <= "00";
elsif (S_AXI_BREADY = '1' and axi_bvalid = '1') then --check if bready is asserted while bvalid is high)
axi_bvalid <= '0'; -- (there is a possibility that bready is always asserted high)
end if;
end if;
end if;
end process;
-- Implement axi_arready generation
-- axi_arready is asserted for one S_AXI_ACLK clock cycle when
-- S_AXI_ARVALID is asserted. axi_awready is
-- de-asserted when reset (active low) is asserted.
-- The read address is also latched when S_AXI_ARVALID is
-- asserted. axi_araddr is reset to zero on reset assertion.
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_arready <= '0';
axi_araddr <= (others => '1');
else
if (axi_arready = '0' and S_AXI_ARVALID = '1') then
-- indicates that the slave has acceped the valid read address
axi_arready <= '1';
-- Read Address latching
axi_araddr <= S_AXI_ARADDR;
else
axi_arready <= '0';
end if;
end if;
end if;
end process;
-- Implement axi_arvalid generation
-- axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
-- S_AXI_ARVALID and axi_arready are asserted. The slave registers
-- data are available on the axi_rdata bus at this instance. The
-- assertion of axi_rvalid marks the validity of read data on the
-- bus and axi_rresp indicates the status of read transaction.axi_rvalid
-- is deasserted on reset (active low). axi_rresp and axi_rdata are
-- cleared to zero on reset (active low).
process (S_AXI_ACLK)
begin
if rising_edge(S_AXI_ACLK) then
if S_AXI_ARESETN = '0' then
axi_rvalid <= '0';
axi_rresp <= "00";
else
if (axi_arready = '1' and S_AXI_ARVALID = '1' and axi_rvalid = '0') then
-- Valid read data is available at the read data bus
axi_rvalid <= '1';
axi_rresp <= "00"; -- 'OKAY' response
elsif (axi_rvalid = '1' and S_AXI_RREADY = '1') then
-- Read data is accepted by the master
axi_rvalid <= '0';
end if;
end if;
end if;
end process;
-- Implement memory mapped register select and read logic generation
-- Slave register read enable is asserted when valid address is available
-- and the slave is ready to accept the read address.
intr_reg_rden <= axi_arready and S_AXI_ARVALID and (not axi_rvalid) ;
RDATA_INTR_NUM_32: if (C_NUM_OF_INTR=32) generate
begin
process (reg_global_intr_en, reg_intr_en, reg_intr_sts, reg_intr_ack, reg_intr_pending, axi_araddr, S_AXI_ARESETN, intr_reg_rden)
variable loc_addr :std_logic_vector(2 downto 0);
begin
if S_AXI_ARESETN = '0' then
reg_data_out <= (others => '0');
else
-- Address decoding for reading registers
loc_addr := axi_araddr(4 downto 2);
case loc_addr is
when "000" =>
reg_data_out <= x"0000000" & "000" & reg_global_intr_en(0);
when "001" =>
reg_data_out <= reg_intr_en;
when "010" =>
reg_data_out <= reg_intr_sts;
when "011" =>
reg_data_out <= reg_intr_ack;
when "100" =>
reg_data_out <= reg_intr_pending;
when others =>
reg_data_out <= (others => '0');
end case;
end if;
end process;
end generate RDATA_INTR_NUM_32;
RDATA_INTR_NUM_LESS_32: if (C_NUM_OF_INTR/=32) generate
begin
process (reg_global_intr_en, reg_intr_en, reg_intr_sts, reg_intr_ack, reg_intr_pending, axi_araddr, S_AXI_ARESETN, intr_reg_rden)
variable loc_addr :std_logic_vector(2 downto 0);
variable zero : std_logic_vector (C_S_AXI_DATA_WIDTH-C_NUM_OF_INTR-1 downto 0);
begin
if S_AXI_ARESETN = '0' then
reg_data_out <= (others => '0');
zero := (others=>'0');
else
zero := (others=>'0');
-- Address decoding for reading registers
loc_addr := axi_araddr(4 downto 2);
case loc_addr is
when "000" =>
reg_data_out <= x"0000000" & "000" & reg_global_intr_en(0);
when "001" =>
reg_data_out <= zero & reg_intr_en;
when "010" =>
reg_data_out <= zero & reg_intr_sts;
when "011" =>
reg_data_out <= zero & reg_intr_ack;
when "100" =>
reg_data_out <= zero & reg_intr_pending;
when others =>
reg_data_out <= (others => '0');
end case;
end if;
end process;
end generate RDATA_INTR_NUM_LESS_32;
-- Output register or memory read data
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0' ) then
axi_rdata <= (others => '0');
else
if (intr_reg_rden = '1') then
-- When there is a valid read address (S_AXI_ARVALID) with
-- acceptance of read address by the slave (axi_arready),
-- output the read dada
-- Read address mux
axi_rdata <= reg_data_out; -- register read data
end if;
end if;
end if;
end process;
------------------------------------------------------
--Example code to generate user logic interrupts
--Note: The example code presented here is to show you one way of generating
-- interrupts from the user logic. This code snippet generates a level
-- triggered interrupt when the intr_counter_reg counts down to zero.
-- while intr_control_reg[0] is asserted. Deasserting the intr_control_reg[0]
-- disables the counter and clears the interrupt signal.
------------------------------------------------------
process( S_AXI_ACLK ) is
begin
if (rising_edge (S_AXI_ACLK)) then
if ( S_AXI_ARESETN = '0') then
s_irq_lvl <= '0';
s_irq_lvl_ff <= '0';
elsif (intr = '1' and reg_global_intr_en(0) = '1') then
s_irq_lvl <= '1';
s_irq_lvl_ff <= s_irq_lvl;
end if;
end if;
end process;
s_irq <= s_irq_lvl and (not s_irq_lvl_ff);
irq <= s_irq;
-- Add user logic here
-- User logic ends
end arch_imp;
|
--------------------------------------------------------------------------
-- Autor original: Antony Nelson.
-- Modificaciones de esta versión: Jorge Márquez
--
-- Esta rutina contiene las modificaciones indicadas en la sección de
-- Anexos del informe de trabajo de grado PROCESAMIENTO DE IMÁGENES DE
-- ANGIOGRAFÍA BIPLANA USANDO UNA TARJETA DE DESARROLLO SPARTAN-3E
--
-- UNIVERSIDAD DE LOS ANDES
-- FACULTAD DE INGENIERÍA
-- ESCUELA DE INGENIERÍA ELÉCTRICA
--
-- Mérida, Septiembre, 2008
--
-- Datos para la simulación:
--
-- t_valid = time when output data first becomes valid
-- t_delay = t_valid - 5 ns
-- t_sim_stop = 163835 ns + t_delay + 10 ns --ojo:para 512x512 son 5253510 ns
-- this is 165305ns for this entity --ojo:para 512x512 son 5253510 ns
--
--
---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use std.textio.all;
entity ro_filt_3x3_tb is
generic(
vwidth : INTEGER := 8;
order : INTEGER := 5;
num_cols : INTEGER := 512;
num_rows : INTEGER := 512 );
end ro_filt_3x3_tb;
architecture TB_ARCHITECTURE of ro_filt_3x3_tb is
component ro_filt_3x3
generic(
vwidth : INTEGER := 8;
order : INTEGER := 5;
num_cols : INTEGER := 512;
num_rows : INTEGER := 512 );
port(
Clk : in std_logic;
RSTn : in std_logic;
D : in std_logic_vector((vwidth -1) downto 0);
Dout : out std_logic_vector((vwidth -1) downto 0);
DV : out std_logic );
end component;
signal Clk : std_logic;
signal RSTn : std_logic;
signal D : std_logic_vector((vwidth-1) downto 0);
signal Dout : std_logic_vector((vwidth-1) downto 0);
signal DV : std_logic;
begin
UUT : ro_filt_3x3
port map --portmap
(Clk => Clk, --portmap
RSTn => RSTn, --portmap
D => D, --portmap
Dout => Dout, --portmap
DV => DV ); --portmap
read_from_file: process(Clk) --read_from_file
variable indata_line: line; --read_from_file
variable indata: integer; --read_from_file
file input_data_file: text open read_mode is "D:\JORGETESIS\lena512_syp.txt"; --read_from_file
begin --read_from_file
if rising_edge(Clk) then --read_from_file
readline(input_data_file,indata_line); --read_from_file
read(indata_line,indata); --read_from_file
D <= conv_std_logic_vector(indata,8); --read_from_file
if endfile(input_data_file) then --read_from_file
report "end of file -- looping back to start of file"; --read_from_file
file_close(input_data_file); --read_from_file
file_open(input_data_file,"D:\JORGETESIS\lena512_syp.txt"); --read_from_file
end if; --read_from_file
end if; --read_from_file
end process; --read_from_file
write_to_file: process(Clk) --write_to_file
variable outdata_line: line; --write_to_file
variable outdata: integer:=0; --write_to_file
file output_data_file: text open write_mode is "D:\JORGETESIS\lena512_syp.bin"; --write_to_file
begin --write_to_file
if rising_edge(Clk) then --write_to_file
outdata := CONV_INTEGER(unsigned(Dout)); --write_to_file
if DV = '1' then --write_to_file
write(outdata_line,outdata); --write_to_file
writeline(output_data_file,outdata_line); --write_to_file
end if; --write_to_file
end if; --write_to_file
end process; --write_to_file
clock_gen: process
begin
Clk <= '0';
wait for 10 ns;
Clk <= '1';
wait for 10 ns;
end process;
reset_gen: process
begin
RSTn <= '0';
wait for 20 ns;
RSTn <= '1';
wait;
end process;
end TB_ARCHITECTURE;
configuration TESTBENCH_FOR_ro_filt_3x3 of ro_filt_3x3_tb is
for TB_ARCHITECTURE
for UUT : ro_filt_3x3
use entity work.ro_filt_3x3(ro_filt_3x3);
end for;
end for;
end TESTBENCH_FOR_ro_filt_3x3;
|
--------------------------------------------------------------------------
-- Autor original: Antony Nelson.
-- Modificaciones de esta versión: Jorge Márquez
--
-- Esta rutina contiene las modificaciones indicadas en la sección de
-- Anexos del informe de trabajo de grado PROCESAMIENTO DE IMÁGENES DE
-- ANGIOGRAFÍA BIPLANA USANDO UNA TARJETA DE DESARROLLO SPARTAN-3E
--
-- UNIVERSIDAD DE LOS ANDES
-- FACULTAD DE INGENIERÍA
-- ESCUELA DE INGENIERÍA ELÉCTRICA
--
-- Mérida, Septiembre, 2008
--
-- Datos para la simulación:
--
-- t_valid = time when output data first becomes valid
-- t_delay = t_valid - 5 ns
-- t_sim_stop = 163835 ns + t_delay + 10 ns --ojo:para 512x512 son 5253510 ns
-- this is 165305ns for this entity --ojo:para 512x512 son 5253510 ns
--
--
---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use std.textio.all;
entity ro_filt_3x3_tb is
generic(
vwidth : INTEGER := 8;
order : INTEGER := 5;
num_cols : INTEGER := 512;
num_rows : INTEGER := 512 );
end ro_filt_3x3_tb;
architecture TB_ARCHITECTURE of ro_filt_3x3_tb is
component ro_filt_3x3
generic(
vwidth : INTEGER := 8;
order : INTEGER := 5;
num_cols : INTEGER := 512;
num_rows : INTEGER := 512 );
port(
Clk : in std_logic;
RSTn : in std_logic;
D : in std_logic_vector((vwidth -1) downto 0);
Dout : out std_logic_vector((vwidth -1) downto 0);
DV : out std_logic );
end component;
signal Clk : std_logic;
signal RSTn : std_logic;
signal D : std_logic_vector((vwidth-1) downto 0);
signal Dout : std_logic_vector((vwidth-1) downto 0);
signal DV : std_logic;
begin
UUT : ro_filt_3x3
port map --portmap
(Clk => Clk, --portmap
RSTn => RSTn, --portmap
D => D, --portmap
Dout => Dout, --portmap
DV => DV ); --portmap
read_from_file: process(Clk) --read_from_file
variable indata_line: line; --read_from_file
variable indata: integer; --read_from_file
file input_data_file: text open read_mode is "D:\JORGETESIS\lena512_syp.txt"; --read_from_file
begin --read_from_file
if rising_edge(Clk) then --read_from_file
readline(input_data_file,indata_line); --read_from_file
read(indata_line,indata); --read_from_file
D <= conv_std_logic_vector(indata,8); --read_from_file
if endfile(input_data_file) then --read_from_file
report "end of file -- looping back to start of file"; --read_from_file
file_close(input_data_file); --read_from_file
file_open(input_data_file,"D:\JORGETESIS\lena512_syp.txt"); --read_from_file
end if; --read_from_file
end if; --read_from_file
end process; --read_from_file
write_to_file: process(Clk) --write_to_file
variable outdata_line: line; --write_to_file
variable outdata: integer:=0; --write_to_file
file output_data_file: text open write_mode is "D:\JORGETESIS\lena512_syp.bin"; --write_to_file
begin --write_to_file
if rising_edge(Clk) then --write_to_file
outdata := CONV_INTEGER(unsigned(Dout)); --write_to_file
if DV = '1' then --write_to_file
write(outdata_line,outdata); --write_to_file
writeline(output_data_file,outdata_line); --write_to_file
end if; --write_to_file
end if; --write_to_file
end process; --write_to_file
clock_gen: process
begin
Clk <= '0';
wait for 10 ns;
Clk <= '1';
wait for 10 ns;
end process;
reset_gen: process
begin
RSTn <= '0';
wait for 20 ns;
RSTn <= '1';
wait;
end process;
end TB_ARCHITECTURE;
configuration TESTBENCH_FOR_ro_filt_3x3 of ro_filt_3x3_tb is
for TB_ARCHITECTURE
for UUT : ro_filt_3x3
use entity work.ro_filt_3x3(ro_filt_3x3);
end for;
end for;
end TESTBENCH_FOR_ro_filt_3x3;
|
--------------------------------------------------------------------------
-- Autor original: Antony Nelson.
-- Modificaciones de esta versión: Jorge Márquez
--
-- Esta rutina contiene las modificaciones indicadas en la sección de
-- Anexos del informe de trabajo de grado PROCESAMIENTO DE IMÁGENES DE
-- ANGIOGRAFÍA BIPLANA USANDO UNA TARJETA DE DESARROLLO SPARTAN-3E
--
-- UNIVERSIDAD DE LOS ANDES
-- FACULTAD DE INGENIERÍA
-- ESCUELA DE INGENIERÍA ELÉCTRICA
--
-- Mérida, Septiembre, 2008
--
-- Datos para la simulación:
--
-- t_valid = time when output data first becomes valid
-- t_delay = t_valid - 5 ns
-- t_sim_stop = 163835 ns + t_delay + 10 ns --ojo:para 512x512 son 5253510 ns
-- this is 165305ns for this entity --ojo:para 512x512 son 5253510 ns
--
--
---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use std.textio.all;
entity ro_filt_3x3_tb is
generic(
vwidth : INTEGER := 8;
order : INTEGER := 5;
num_cols : INTEGER := 512;
num_rows : INTEGER := 512 );
end ro_filt_3x3_tb;
architecture TB_ARCHITECTURE of ro_filt_3x3_tb is
component ro_filt_3x3
generic(
vwidth : INTEGER := 8;
order : INTEGER := 5;
num_cols : INTEGER := 512;
num_rows : INTEGER := 512 );
port(
Clk : in std_logic;
RSTn : in std_logic;
D : in std_logic_vector((vwidth -1) downto 0);
Dout : out std_logic_vector((vwidth -1) downto 0);
DV : out std_logic );
end component;
signal Clk : std_logic;
signal RSTn : std_logic;
signal D : std_logic_vector((vwidth-1) downto 0);
signal Dout : std_logic_vector((vwidth-1) downto 0);
signal DV : std_logic;
begin
UUT : ro_filt_3x3
port map --portmap
(Clk => Clk, --portmap
RSTn => RSTn, --portmap
D => D, --portmap
Dout => Dout, --portmap
DV => DV ); --portmap
read_from_file: process(Clk) --read_from_file
variable indata_line: line; --read_from_file
variable indata: integer; --read_from_file
file input_data_file: text open read_mode is "D:\JORGETESIS\lena512_syp.txt"; --read_from_file
begin --read_from_file
if rising_edge(Clk) then --read_from_file
readline(input_data_file,indata_line); --read_from_file
read(indata_line,indata); --read_from_file
D <= conv_std_logic_vector(indata,8); --read_from_file
if endfile(input_data_file) then --read_from_file
report "end of file -- looping back to start of file"; --read_from_file
file_close(input_data_file); --read_from_file
file_open(input_data_file,"D:\JORGETESIS\lena512_syp.txt"); --read_from_file
end if; --read_from_file
end if; --read_from_file
end process; --read_from_file
write_to_file: process(Clk) --write_to_file
variable outdata_line: line; --write_to_file
variable outdata: integer:=0; --write_to_file
file output_data_file: text open write_mode is "D:\JORGETESIS\lena512_syp.bin"; --write_to_file
begin --write_to_file
if rising_edge(Clk) then --write_to_file
outdata := CONV_INTEGER(unsigned(Dout)); --write_to_file
if DV = '1' then --write_to_file
write(outdata_line,outdata); --write_to_file
writeline(output_data_file,outdata_line); --write_to_file
end if; --write_to_file
end if; --write_to_file
end process; --write_to_file
clock_gen: process
begin
Clk <= '0';
wait for 10 ns;
Clk <= '1';
wait for 10 ns;
end process;
reset_gen: process
begin
RSTn <= '0';
wait for 20 ns;
RSTn <= '1';
wait;
end process;
end TB_ARCHITECTURE;
configuration TESTBENCH_FOR_ro_filt_3x3 of ro_filt_3x3_tb is
for TB_ARCHITECTURE
for UUT : ro_filt_3x3
use entity work.ro_filt_3x3(ro_filt_3x3);
end for;
end for;
end TESTBENCH_FOR_ro_filt_3x3;
|
-- file: clock.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- "Output Output Phase Duty Pk-to-Pk Phase"
-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
------------------------------------------------------------------------------
-- CLK_OUT1____56.000______0.000______50.0______557.143____150.000
-- CLK_OUT2____25.000______0.000______50.0______300.000____150.000
--
------------------------------------------------------------------------------
-- "Input Clock Freq (MHz) Input Jitter (UI)"
------------------------------------------------------------------------------
-- __primary______________50____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clock is
port
(-- Clock in ports
CLK50 : in std_logic;
-- Clock out ports
CLK : out std_logic;
VGA_CLK : out std_logic;
-- Status and control signals
LOCKED : out std_logic
);
end clock;
architecture xilinx of clock is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clock,clk_wiz_v3_3,{component_name=clock,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=2,clkin1_period=20.0,clkin2_period=20.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering
signal clkfb : std_logic;
signal clk0 : std_logic;
signal clkfx : std_logic;
signal clkdv : std_logic;
signal clkfbout : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(7 downto 0);
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK50);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_sp_inst: DCM_SP
generic map
(CLKDV_DIVIDE => 2.000,
CLKFX_DIVIDE => 25,
CLKFX_MULTIPLY => 28,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 20.0,
CLKOUT_PHASE_SHIFT => "NONE",
CLK_FEEDBACK => "1X",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map
-- Input clock
(CLKIN => clkin1,
CLKFB => clkfb,
-- Output clocks
CLK0 => clk0,
CLK90 => open,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKFX => clkfx,
CLKFX180 => open,
CLKDV => clkdv,
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_internal,
STATUS => status_internal,
RST => '0',
-- Unused pin, tie low
DSSEN => '0');
LOCKED <= locked_internal;
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfb,
I => clk0);
clkout1_buf : BUFG
port map
(O => CLK,
I => clkfx);
clkout2_buf : BUFG
port map
(O => VGA_CLK,
I => clkdv);
end xilinx;
|
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